From 2b5fa44f60165d66d74131778df0b64b706887e2 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 25 Apr 2022 18:56:52 +0100 Subject: [PATCH 01/75] dnsmasq: add logfacility file to jail mounts If logfacility is a path to a file it needs to be r/w mounted in the sandbox as well for dnsmasq to work. Reported-by: @iointerrupt Signed-off-by: Daniel Golle --- package/network/services/dnsmasq/files/dnsmasq.init | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/package/network/services/dnsmasq/files/dnsmasq.init b/package/network/services/dnsmasq/files/dnsmasq.init index d95502c0da..040ceaea2f 100755 --- a/package/network/services/dnsmasq/files/dnsmasq.init +++ b/package/network/services/dnsmasq/files/dnsmasq.init @@ -820,7 +820,7 @@ dnsmasq_ipset_add() { dnsmasq_start() { local cfg="$1" - local disabled user_dhcpscript + local disabled user_dhcpscript logfacility local resolvfile resolvdir localuse=0 config_get_bool disabled "$cfg" disabled 0 @@ -933,7 +933,7 @@ dnsmasq_start() append_bool "$cfg" scriptarp "--script-arp" append_parm "$cfg" logfacility "--log-facility" - + config_get logfacility "$cfg" "logfacility" append_parm "$cfg" cachesize "--cache-size" append_parm "$cfg" dnsforwardmax "--dns-forward-max" append_parm "$cfg" port "--port" @@ -1167,6 +1167,10 @@ dnsmasq_start() procd_add_jail_mount $dnsmasqconffile $dnsmasqconfdir $resolvdir $user_dhcpscript procd_add_jail_mount /etc/passwd /etc/group /etc/TZ /etc/hosts /etc/ethers procd_add_jail_mount_rw /var/run/dnsmasq/ $leasefile + case "$logfacility" in */*) + [ ! -e "$logfacility" ] && touch "$logfacility" + procd_add_jail_mount_rw "$logfacility" + esac procd_close_instance } From 8b3c313515c1ae37be9d61a4e92c4bf4b43f605f Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sun, 24 Apr 2022 23:48:42 +0200 Subject: [PATCH 02/75] mpc85xx: define reset-delay for WS-AP3825i eth PHY The WS-AP3825i uses Atheros PHYs which according to the datasheet require the reset to be asserted for at least 1 ms. This fixes broken eth1 upon soft-reboot. eth0 is no affected, as the ifup / ifdown cycle in preinit prevents this issue from happening when the system is ready. Reported-by: Tom Herbers Signed-off-by: David Bauer --- .../linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts index 43c044b4fc..26f742b222 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts @@ -149,12 +149,16 @@ interrupts = <3 1 0 0>; reg = <0x5>; reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; }; phy2: ethernet-phy@2 { interrupts = <1 1 0 0>; reg = <0x6>; reset-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; }; }; From c6d52515e009d96e0afbe77310bf172f113d0eef Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 25 Apr 2022 01:00:49 +0200 Subject: [PATCH 03/75] mpc85xx: set WS-AP3825i mac-address in preinit The bootloader does seem to not correctly patch in the MAC address for eth0 / eth1 in some cases. While the root cause is not known, manually applying the MAC-Address in preinit does not hurt. Reported-by: Tom Herbers Signed-off-by: David Bauer --- .../mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh diff --git a/target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh new file mode 100644 index 0000000000..d94eba688c --- /dev/null +++ b/target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh @@ -0,0 +1,12 @@ +. /lib/functions.sh + +preinit_set_mac_address() { + case $(board_name) in + extreme-networks,ws-ap3825i) + ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr) + ip link set dev eth1 address $(mtd_get_mac_ascii cfg1 eth1addr) + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address From fb7ff6b027d1c69e97e6d39e688a969c164065c8 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 25 Apr 2022 00:04:09 +0200 Subject: [PATCH 04/75] uboot-envtools: add WS-AP3825i config Add configuration to use uboot-envtools with the Extreme Networks WS-AP3825i. Signed-off-by: David Bauer --- package/boot/uboot-envtools/files/mpc85xx | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/package/boot/uboot-envtools/files/mpc85xx b/package/boot/uboot-envtools/files/mpc85xx index df6e5f670b..36d9f753a1 100644 --- a/package/boot/uboot-envtools/files/mpc85xx +++ b/package/boot/uboot-envtools/files/mpc85xx @@ -8,6 +8,10 @@ touch /etc/config/ubootenv board=$(board_name) case "$board" in +extreme-networks,ws-ap3825i) + ubootenv_add_uci_config "$(find_mtd_part 'cfg1')" "0x0" "0x10000" "0x20000" + ubootenv_add_uci_config "$(find_mtd_part 'cfg2')" "0x0" "0x10000" "0x20000" + ;; ocedo,panda) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000" ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x20000" "0x20000" From 432a25db72efe36b051fbe36cf6c8e5bc4fafd91 Mon Sep 17 00:00:00 2001 From: Hans Dedecker Date: Tue, 26 Apr 2022 22:39:02 +0200 Subject: [PATCH 05/75] nat46: update to git HEAD 95ca1c3 nat46-core: ignore IPv4 options when translating packets 39778c2 add a module argument to ignore TOS translate for IPv4 9a36ee1 add a module argument to ignore TOS translate for IPv4 79190a8 add a module argument to ignore TOS translate for IPv4 Signed-off-by: Hans Dedecker --- package/kernel/nat46/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/kernel/nat46/Makefile b/package/kernel/nat46/Makefile index c365026f08..2b131a9a70 100644 --- a/package/kernel/nat46/Makefile +++ b/package/kernel/nat46/Makefile @@ -3,11 +3,11 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=nat46 -PKG_MIRROR_HASH:=1476da31996e26ef76e2ba9623d978d33002abf357a59323d9b539812b0a4b76 +PKG_MIRROR_HASH:=c26b8c60aa991a087011b8b6492e43a6749f0a5d9dc79ffcfd352da5fa20b78d PKG_SOURCE_URL:=https://github.com/ayourtch/nat46.git -PKG_SOURCE_DATE:=2021-11-24 +PKG_SOURCE_DATE:=2022-03-30 PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=d9bc161faa4c18ad1d327a96baa2dc4460b71ccd +PKG_SOURCE_VERSION:=95ca1c3b99376da2d0306919f2df4a8d3c9bb78b PKG_MAINTAINER:=Hans Dedecker PKG_LICENSE:=GPL-2.0 From f757a8a09885e3c8bb76371e037b8c0731111980 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Wed, 27 Apr 2022 00:53:11 +0200 Subject: [PATCH 06/75] iwinfo: update to latest HEAD dc6847e iwinfo: nl80211: omit A-hwmode on non-5GHz hardware Signed-off-by: David Bauer --- package/network/utils/iwinfo/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/utils/iwinfo/Makefile b/package/network/utils/iwinfo/Makefile index b01a1a3b9d..25cc210acb 100644 --- a/package/network/utils/iwinfo/Makefile +++ b/package/network/utils/iwinfo/Makefile @@ -11,9 +11,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/iwinfo.git -PKG_SOURCE_DATE:=2022-04-24 -PKG_SOURCE_VERSION:=a479b9b08aeac82fd45cc7a306937c9447157f5e -PKG_MIRROR_HASH:=ed3e8d0b665f2ee95117fe86fc5619d90f9e4849d518111c2f62ebd58ea99f35 +PKG_SOURCE_DATE:=2022-04-26 +PKG_SOURCE_VERSION:=dc6847eb5ec8747867bc20f1024723c6397c1df7 +PKG_MIRROR_HASH:=3f243cf75f4cec02e9e8ecc2087577146845346c0172808f64dea066f84f88d4 PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=GPL-2.0 From 0f207ade12fdfffae3554c6a7214aa670a8d6854 Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Wed, 27 Apr 2022 17:27:28 +0200 Subject: [PATCH 07/75] firmware-utils: bump to git HEAD Includes image support for new TP-Link devices: ddc3e00e314d tplink-safeloader: add TP-Link EAP265 HD support ceea1a7fe56e tplink-safeloader: add TP-Link Deco M4R v1 and v2 support Signed-off-by: Sander Vanheule --- tools/firmware-utils/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/firmware-utils/Makefile b/tools/firmware-utils/Makefile index 5cca587a8b..2534cec543 100644 --- a/tools/firmware-utils/Makefile +++ b/tools/firmware-utils/Makefile @@ -11,9 +11,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware-utils.git -PKG_SOURCE_DATE:=2022-04-23 -PKG_SOURCE_VERSION:=05fd7007b0c842cb560b83f07b50282733ccf2ca -PKG_MIRROR_HASH:=58a0578cd1a8bf934dc683fc3cced6208b17f528fe2f0329f169ea50eb83bc76 +PKG_SOURCE_DATE:=2022-04-25 +PKG_SOURCE_VERSION:=ddc3e00e314d3fbc3f9faab2d07395722ce9b01a +PKG_MIRROR_HASH:=246fc1d72d3a8cdb4072d81e033c92abaf614acd6f35a10fffd029d5c7f9303b include $(INCLUDE_DIR)/host-build.mk include $(INCLUDE_DIR)/cmake.mk From 8fa4361f55c48c7f1e103782fee6f739b873cbee Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Wed, 27 Apr 2022 17:27:28 +0200 Subject: [PATCH 08/75] ath79: add support for TP-Link EAP265 HD The EAP265 HD is a rebadged EAP245v3, so images are compatible with both devices. Link: https://fccid.io/TE7EAP265HD/Letter/6-Request-for-FCC-Change-ID-4823578.pdf Signed-off-by: Sander Vanheule --- target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts | 2 +- target/linux/ath79/image/generic-tp-link.mk | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts b/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts index ee9f5ff5c7..5d789d7869 100644 --- a/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts +++ b/target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts @@ -7,7 +7,7 @@ / { compatible = "tplink,eap245-v3", "qca,qca9563"; - model = "TP-Link EAP245 v3"; + model = "TP-Link EAP245 v3 / EAP265 HD v1"; aliases { led-boot = &led_status_green; diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index 6479f6e26a..ce0f81be6e 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -451,6 +451,9 @@ define Device/tplink_eap245-v3 IMAGE_SIZE := 14592k DEVICE_MODEL := EAP245 DEVICE_VARIANT := v3 + DEVICE_ALT0_VENDOR := $$(DEVICE_VENDOR) + DEVICE_ALT0_MODEL := EAP265 HD + DEVICE_ALT0_VARIANT := v1 DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca99x0-ct TPLINK_BOARD_ID := EAP245-V3 endef From 573ce80ca612b0f642b7cbd5d9d33d89b7e96670 Mon Sep 17 00:00:00 2001 From: Jo-Philipp Wich Date: Thu, 28 Apr 2022 10:28:20 +0200 Subject: [PATCH 09/75] ucode: reorder BuildPackage calls Ensure that the libucode recipe is processed before the ucode one in order to reliably encode the ABI version into ucode's libucode dependency. Fixes: #9788 Ref: https://forum.openwrt.org/t/fw4-wont-start-after-upgrade/126308 Signed-off-by: Jo-Philipp Wich --- package/utils/ucode/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/utils/ucode/Makefile b/package/utils/ucode/Makefile index bd31c6f521..64edf198ce 100644 --- a/package/utils/ucode/Makefile +++ b/package/utils/ucode/Makefile @@ -201,8 +201,8 @@ define Package/ucode-mod-uci/install endef -$(eval $(call BuildPackage,ucode)) $(eval $(call BuildPackage,libucode)) +$(eval $(call BuildPackage,ucode)) $(eval $(call BuildPackage,ucode-mod-fs)) $(eval $(call BuildPackage,ucode-mod-math)) $(eval $(call BuildPackage,ucode-mod-nl80211)) From 3e5925225ec27519f1eccc1605fe9a76303d539b Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Thu, 7 Apr 2022 10:03:50 +0800 Subject: [PATCH 10/75] mediatek: drop spi-nand driver from mtk Signed-off-by: Chuanhong Guo --- .../files/drivers/mtd/mtk-snand/Kconfig | 13 - .../files/drivers/mtd/mtk-snand/Makefile | 10 - .../drivers/mtd/mtk-snand/mtk-snand-def.h | 268 --- .../drivers/mtd/mtk-snand/mtk-snand-ecc.c | 379 ---- .../drivers/mtd/mtk-snand/mtk-snand-ids.c | 515 ----- .../drivers/mtd/mtk-snand/mtk-snand-mtd.c | 681 ------ .../drivers/mtd/mtk-snand/mtk-snand-os.c | 48 - .../drivers/mtd/mtk-snand/mtk-snand-os.h | 127 -- .../files/drivers/mtd/mtk-snand/mtk-snand.c | 1862 ----------------- .../files/drivers/mtd/mtk-snand/mtk-snand.h | 76 - .../330-mtk-snand-bmt-support.patch | 36 - .../360-mtd-add-mtk-snand-driver.patch | 21 - 12 files changed, 4036 deletions(-) delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h delete mode 100644 target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch delete mode 100644 target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig b/target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig deleted file mode 100644 index 58aa563832..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 MediaTek Inc. All rights reserved. -# Author: Weijie Gao -# - -config MTK_SPI_NAND - tristate "MediaTek SPI NAND flash controller driver" - depends on MTD - default n - help - This option enables access to SPI-NAND flashes through the - MTD interface of MediaTek SPI NAND Flash Controller diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile b/target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile deleted file mode 100644 index e6b3710046..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 MediaTek Inc. All rights reserved. -# Author: Weijie Gao -# - -obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o \ - mtk-snand-mtd.o - -ccflags-y += -DPRIVATE_MTK_SNAND_HEADER diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h deleted file mode 100644 index 1a93d93dcd..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h +++ /dev/null @@ -1,268 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#ifndef _MTK_SNAND_DEF_H_ -#define _MTK_SNAND_DEF_H_ - -#include "mtk-snand-os.h" - -#ifdef PRIVATE_MTK_SNAND_HEADER -#include "mtk-snand.h" -#else -#include -#endif - -struct mtk_snand_plat_dev; - -enum snand_flash_io { - SNAND_IO_1_1_1, - SNAND_IO_1_1_2, - SNAND_IO_1_2_2, - SNAND_IO_1_1_4, - SNAND_IO_1_4_4, - - __SNAND_IO_MAX -}; - -#define SPI_IO_1_1_1 BIT(SNAND_IO_1_1_1) -#define SPI_IO_1_1_2 BIT(SNAND_IO_1_1_2) -#define SPI_IO_1_2_2 BIT(SNAND_IO_1_2_2) -#define SPI_IO_1_1_4 BIT(SNAND_IO_1_1_4) -#define SPI_IO_1_4_4 BIT(SNAND_IO_1_4_4) - -struct snand_opcode { - uint8_t opcode; - uint8_t dummy; -}; - -struct snand_io_cap { - uint8_t caps; - struct snand_opcode opcodes[__SNAND_IO_MAX]; -}; - -#define SNAND_OP(_io, _opcode, _dummy) [_io] = { .opcode = (_opcode), \ - .dummy = (_dummy) } - -#define SNAND_IO_CAP(_name, _caps, ...) \ - struct snand_io_cap _name = { .caps = (_caps), \ - .opcodes = { __VA_ARGS__ } } - -#define SNAND_MAX_ID_LEN 4 - -enum snand_id_type { - SNAND_ID_DYMMY, - SNAND_ID_ADDR = SNAND_ID_DYMMY, - SNAND_ID_DIRECT, - - __SNAND_ID_TYPE_MAX -}; - -struct snand_id { - uint8_t type; /* enum snand_id_type */ - uint8_t len; - uint8_t id[SNAND_MAX_ID_LEN]; -}; - -#define SNAND_ID(_type, ...) \ - { .type = (_type), .id = { __VA_ARGS__ }, \ - .len = sizeof((uint8_t[]) { __VA_ARGS__ }) } - -struct snand_mem_org { - uint16_t pagesize; - uint16_t sparesize; - uint16_t pages_per_block; - uint16_t blocks_per_die; - uint16_t planes_per_die; - uint16_t ndies; -}; - -#define SNAND_MEMORG(_ps, _ss, _ppb, _bpd, _ppd, _nd) \ - { .pagesize = (_ps), .sparesize = (_ss), .pages_per_block = (_ppb), \ - .blocks_per_die = (_bpd), .planes_per_die = (_ppd), .ndies = (_nd) } - -typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx); - -struct snand_flash_info { - const char *model; - struct snand_id id; - const struct snand_mem_org memorg; - const struct snand_io_cap *cap_rd; - const struct snand_io_cap *cap_pl; - snand_select_die_t select_die; -}; - -#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \ - { .model = (_model), .id = _id, .memorg = _memorg, \ - .cap_rd = (_cap_rd), .cap_pl = (_cap_pl), __VA_ARGS__ } - -const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type, - const uint8_t *id); - -struct mtk_snand_soc_data { - uint16_t sector_size; - uint16_t max_sectors; - uint16_t fdm_size; - uint16_t fdm_ecc_size; - uint16_t fifo_size; - - bool bbm_swap; - bool empty_page_check; - uint32_t mastersta_mask; - - const uint8_t *spare_sizes; - uint32_t num_spare_size; -}; - -enum mtk_ecc_regs { - ECC_DECDONE, -}; - -struct mtk_ecc_soc_data { - const uint8_t *ecc_caps; - uint32_t num_ecc_cap; - const uint32_t *regs; - uint16_t mode_shift; - uint8_t errnum_bits; - uint8_t errnum_shift; -}; - -struct mtk_snand { - struct mtk_snand_plat_dev *pdev; - - void __iomem *nfi_base; - void __iomem *ecc_base; - - enum mtk_snand_soc soc; - const struct mtk_snand_soc_data *nfi_soc; - const struct mtk_ecc_soc_data *ecc_soc; - bool snfi_quad_spi; - bool quad_spi_op; - - const char *model; - uint64_t size; - uint64_t die_size; - uint32_t erasesize; - uint32_t writesize; - uint32_t oobsize; - - uint32_t num_dies; - snand_select_die_t select_die; - - uint8_t opcode_rfc; - uint8_t opcode_pl; - uint8_t dummy_rfc; - uint8_t mode_rfc; - uint8_t mode_pl; - - uint32_t writesize_mask; - uint32_t writesize_shift; - uint32_t erasesize_mask; - uint32_t erasesize_shift; - uint64_t die_mask; - uint32_t die_shift; - - uint32_t spare_per_sector; - uint32_t raw_sector_size; - uint32_t ecc_strength; - uint32_t ecc_steps; - uint32_t ecc_bytes; - uint32_t ecc_parity_bits; - - uint8_t *page_cache; /* Used by read/write page */ - uint8_t *buf_cache; /* Used by block bad/markbad & auto_oob */ - int *sect_bf; /* Used by ECC correction */ -}; - -enum mtk_snand_log_category { - SNAND_LOG_NFI, - SNAND_LOG_SNFI, - SNAND_LOG_ECC, - SNAND_LOG_CHIP, - - __SNAND_LOG_CAT_MAX -}; - -int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes, - uint32_t msg_size); -int mtk_snand_ecc_encoder_start(struct mtk_snand *snf); -void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf); -int mtk_snand_ecc_decoder_start(struct mtk_snand *snf); -void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf); -int mtk_ecc_wait_decoder_done(struct mtk_snand *snf); -int mtk_ecc_check_decode_error(struct mtk_snand *snf); -int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect); - -int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen, - uint8_t *in, uint32_t inlen); -int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val); - -int mtk_snand_log(struct mtk_snand_plat_dev *pdev, - enum mtk_snand_log_category cat, const char *fmt, ...); - -#define snand_log_nfi(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_NFI, fmt, ##__VA_ARGS__) - -#define snand_log_snfi(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_SNFI, fmt, ##__VA_ARGS__) - -#define snand_log_ecc(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_ECC, fmt, ##__VA_ARGS__) - -#define snand_log_chip(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_CHIP, fmt, ##__VA_ARGS__) - -/* ffs64 */ -static inline int mtk_snand_ffs64(uint64_t x) -{ - if (!x) - return 0; - - if (!(x & 0xffffffff)) - return ffs((uint32_t)(x >> 32)) + 32; - - return ffs((uint32_t)(x & 0xffffffff)); -} - -/* NFI dummy commands */ -#define NFI_CMD_DUMMY_READ 0x00 -#define NFI_CMD_DUMMY_WRITE 0x80 - -/* SPI-NAND opcodes */ -#define SNAND_CMD_RESET 0xff -#define SNAND_CMD_BLOCK_ERASE 0xd8 -#define SNAND_CMD_READ_FROM_CACHE_QUAD 0xeb -#define SNAND_CMD_WINBOND_SELECT_DIE 0xc2 -#define SNAND_CMD_READ_FROM_CACHE_DUAL 0xbb -#define SNAND_CMD_READID 0x9f -#define SNAND_CMD_READ_FROM_CACHE_X4 0x6b -#define SNAND_CMD_READ_FROM_CACHE_X2 0x3b -#define SNAND_CMD_PROGRAM_LOAD_X4 0x32 -#define SNAND_CMD_SET_FEATURE 0x1f -#define SNAND_CMD_READ_TO_CACHE 0x13 -#define SNAND_CMD_PROGRAM_EXECUTE 0x10 -#define SNAND_CMD_GET_FEATURE 0x0f -#define SNAND_CMD_READ_FROM_CACHE 0x0b -#define SNAND_CMD_WRITE_ENABLE 0x06 -#define SNAND_CMD_PROGRAM_LOAD 0x02 - -/* SPI-NAND feature addresses */ -#define SNAND_FEATURE_MICRON_DIE_ADDR 0xd0 -#define SNAND_MICRON_DIE_SEL_1 BIT(6) - -#define SNAND_FEATURE_STATUS_ADDR 0xc0 -#define SNAND_STATUS_OIP BIT(0) -#define SNAND_STATUS_WEL BIT(1) -#define SNAND_STATUS_ERASE_FAIL BIT(2) -#define SNAND_STATUS_PROGRAM_FAIL BIT(3) - -#define SNAND_FEATURE_CONFIG_ADDR 0xb0 -#define SNAND_FEATURE_QUAD_ENABLE BIT(0) -#define SNAND_FEATURE_ECC_EN BIT(4) - -#define SNAND_FEATURE_PROTECT_ADDR 0xa0 - -#endif /* _MTK_SNAND_DEF_H_ */ diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c deleted file mode 100644 index 6dd0f346c8..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c +++ /dev/null @@ -1,379 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -/* ECC registers */ -#define ECC_ENCCON 0x000 -#define ENC_EN BIT(0) - -#define ECC_ENCCNFG 0x004 -#define ENC_MS_S 16 -#define ENC_BURST_EN BIT(8) -#define ENC_TNUM_S 0 - -#define ECC_ENCIDLE 0x00c -#define ENC_IDLE BIT(0) - -#define ECC_DECCON 0x100 -#define DEC_EN BIT(0) - -#define ECC_DECCNFG 0x104 -#define DEC_EMPTY_EN BIT(31) -#define DEC_CS_S 16 -#define DEC_CON_S 12 -#define DEC_CON_CORRECT 3 -#define DEC_BURST_EN BIT(8) -#define DEC_TNUM_S 0 - -#define ECC_DECIDLE 0x10c -#define DEC_IDLE BIT(0) - -#define ECC_DECENUM0 0x114 -#define ECC_DECENUM(n) (ECC_DECENUM0 + (n) * 4) - -/* ECC_ENCIDLE & ECC_DECIDLE */ -#define ECC_IDLE BIT(0) - -/* ENC_MODE & DEC_MODE */ -#define ECC_MODE_NFI 1 - -#define ECC_TIMEOUT 500000 - -static const uint8_t mt7622_ecc_caps[] = { 4, 6, 8, 10, 12 }; - -static const uint32_t mt7622_ecc_regs[] = { - [ECC_DECDONE] = 0x11c, -}; - -static const struct mtk_ecc_soc_data mtk_ecc_socs[__SNAND_SOC_MAX] = { - [SNAND_SOC_MT7622] = { - .ecc_caps = mt7622_ecc_caps, - .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps), - .regs = mt7622_ecc_regs, - .mode_shift = 4, - .errnum_bits = 5, - .errnum_shift = 5, - }, - [SNAND_SOC_MT7629] = { - .ecc_caps = mt7622_ecc_caps, - .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps), - .regs = mt7622_ecc_regs, - .mode_shift = 4, - .errnum_bits = 5, - .errnum_shift = 5, - }, -}; - -static inline uint32_t ecc_read32(struct mtk_snand *snf, uint32_t reg) -{ - return readl(snf->ecc_base + reg); -} - -static inline void ecc_write32(struct mtk_snand *snf, uint32_t reg, - uint32_t val) -{ - writel(val, snf->ecc_base + reg); -} - -static inline void ecc_write16(struct mtk_snand *snf, uint32_t reg, - uint16_t val) -{ - writew(val, snf->ecc_base + reg); -} - -static int mtk_ecc_poll(struct mtk_snand *snf, uint32_t reg, uint32_t bits) -{ - uint32_t val; - - return read16_poll_timeout(snf->ecc_base + reg, val, (val & bits), 0, - ECC_TIMEOUT); -} - -static int mtk_ecc_wait_idle(struct mtk_snand *snf, uint32_t reg) -{ - int ret; - - ret = mtk_ecc_poll(snf, reg, ECC_IDLE); - if (ret) { - snand_log_ecc(snf->pdev, "ECC engine is busy\n"); - return -EBUSY; - } - - return 0; -} - -int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes, - uint32_t msg_size) -{ - uint32_t i, val, ecc_msg_bits, ecc_strength; - int ret; - - snf->ecc_soc = &mtk_ecc_socs[snf->soc]; - - snf->ecc_parity_bits = fls(1 + 8 * msg_size); - ecc_strength = max_ecc_bytes * 8 / snf->ecc_parity_bits; - - for (i = snf->ecc_soc->num_ecc_cap - 1; i >= 0; i--) { - if (snf->ecc_soc->ecc_caps[i] <= ecc_strength) - break; - } - - if (unlikely(i < 0)) { - snand_log_ecc(snf->pdev, "Page size %u+%u is not supported\n", - snf->writesize, snf->oobsize); - return -ENOTSUPP; - } - - snf->ecc_strength = snf->ecc_soc->ecc_caps[i]; - snf->ecc_bytes = DIV_ROUND_UP(snf->ecc_strength * snf->ecc_parity_bits, - 8); - - /* Encoder config */ - ecc_write16(snf, ECC_ENCCON, 0); - ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - if (ret) - return ret; - - ecc_msg_bits = msg_size * 8; - val = (ecc_msg_bits << ENC_MS_S) | - (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i; - ecc_write32(snf, ECC_ENCCNFG, val); - - /* Decoder config */ - ecc_write16(snf, ECC_DECCON, 0); - ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE); - if (ret) - return ret; - - ecc_msg_bits += snf->ecc_strength * snf->ecc_parity_bits; - val = DEC_EMPTY_EN | (ecc_msg_bits << DEC_CS_S) | - (DEC_CON_CORRECT << DEC_CON_S) | - (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i; - ecc_write32(snf, ECC_DECCNFG, val); - - return 0; -} - -int mtk_snand_ecc_encoder_start(struct mtk_snand *snf) -{ - int ret; - - ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - if (ret) { - ecc_write16(snf, ECC_ENCCON, 0); - mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - } - - ecc_write16(snf, ECC_ENCCON, ENC_EN); - - return 0; -} - -void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf) -{ - mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - ecc_write16(snf, ECC_ENCCON, 0); -} - -int mtk_snand_ecc_decoder_start(struct mtk_snand *snf) -{ - int ret; - - ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE); - if (ret) { - ecc_write16(snf, ECC_DECCON, 0); - mtk_ecc_wait_idle(snf, ECC_DECIDLE); - } - - ecc_write16(snf, ECC_DECCON, DEC_EN); - - return 0; -} - -void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf) -{ - mtk_ecc_wait_idle(snf, ECC_DECIDLE); - ecc_write16(snf, ECC_DECCON, 0); -} - -int mtk_ecc_wait_decoder_done(struct mtk_snand *snf) -{ - uint16_t val, step_mask = (1 << snf->ecc_steps) - 1; - uint32_t reg = snf->ecc_soc->regs[ECC_DECDONE]; - int ret; - - ret = read16_poll_timeout(snf->ecc_base + reg, val, - (val & step_mask) == step_mask, 0, - ECC_TIMEOUT); - if (ret) - snand_log_ecc(snf->pdev, "ECC decoder is busy\n"); - - return ret; -} - -int mtk_ecc_check_decode_error(struct mtk_snand *snf) -{ - uint32_t i, regi, fi, errnum; - uint32_t errnum_shift = snf->ecc_soc->errnum_shift; - uint32_t errnum_mask = (1 << snf->ecc_soc->errnum_bits) - 1; - int ret = 0; - - for (i = 0; i < snf->ecc_steps; i++) { - regi = i / 4; - fi = i % 4; - - errnum = ecc_read32(snf, ECC_DECENUM(regi)); - errnum = (errnum >> (fi * errnum_shift)) & errnum_mask; - - if (errnum <= snf->ecc_strength) { - snf->sect_bf[i] = errnum; - } else { - snf->sect_bf[i] = -1; - ret = -EBADMSG; - } - } - - return ret; -} - -static int mtk_ecc_check_buf_bitflips(struct mtk_snand *snf, const void *buf, - size_t len, uint32_t bitflips) -{ - const uint8_t *buf8 = buf; - const uint32_t *buf32; - uint32_t d, weight; - - while (len && ((uintptr_t)buf8) % sizeof(uint32_t)) { - weight = hweight8(*buf8); - bitflips += BITS_PER_BYTE - weight; - buf8++; - len--; - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - } - - buf32 = (const uint32_t *)buf8; - while (len >= sizeof(uint32_t)) { - d = *buf32; - - if (d != ~0) { - weight = hweight32(d); - bitflips += sizeof(uint32_t) * BITS_PER_BYTE - weight; - } - - buf32++; - len -= sizeof(uint32_t); - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - } - - buf8 = (const uint8_t *)buf32; - while (len) { - weight = hweight8(*buf8); - bitflips += BITS_PER_BYTE - weight; - buf8++; - len--; - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - } - - return bitflips; -} - -static int mtk_ecc_check_parity_bitflips(struct mtk_snand *snf, const void *buf, - uint32_t bits, uint32_t bitflips) -{ - uint32_t len, i; - uint8_t b; - int rc; - - len = bits >> 3; - bits &= 7; - - rc = mtk_ecc_check_buf_bitflips(snf, buf, len, bitflips); - if (!bits || rc < 0) - return rc; - - bitflips = rc; - - /* We want a precise count of bits */ - b = ((const uint8_t *)buf)[len]; - for (i = 0; i < bits; i++) { - if (!(b & BIT(i))) - bitflips++; - } - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - - return bitflips; -} - -static void mtk_ecc_reset_parity(void *buf, uint32_t bits) -{ - uint32_t len; - - len = bits >> 3; - bits &= 7; - - memset(buf, 0xff, len); - - /* Only reset bits protected by ECC to 1 */ - if (bits) - ((uint8_t *)buf)[len] |= GENMASK(bits - 1, 0); -} - -int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect) -{ - uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - uint8_t *oob = snf->page_cache + snf->writesize; - uint8_t *data_ptr, *fdm_ptr, *ecc_ptr; - int bitflips = 0, ecc_bits, parity_bits; - - parity_bits = fls(snf->nfi_soc->sector_size * 8); - ecc_bits = snf->ecc_strength * parity_bits; - - data_ptr = snf->page_cache + sect * snf->nfi_soc->sector_size; - fdm_ptr = oob + sect * snf->nfi_soc->fdm_size; - ecc_ptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size + - sect * ecc_bytes; - - /* - * Check whether DATA + FDM + ECC of a sector contains correctable - * bitflips - */ - bitflips = mtk_ecc_check_buf_bitflips(snf, data_ptr, - snf->nfi_soc->sector_size, - bitflips); - if (bitflips < 0) - return -EBADMSG; - - bitflips = mtk_ecc_check_buf_bitflips(snf, fdm_ptr, - snf->nfi_soc->fdm_ecc_size, - bitflips); - if (bitflips < 0) - return -EBADMSG; - - bitflips = mtk_ecc_check_parity_bitflips(snf, ecc_ptr, ecc_bits, - bitflips); - if (bitflips < 0) - return -EBADMSG; - - if (!bitflips) - return 0; - - /* Reset the data of this sector to 0xff */ - memset(data_ptr, 0xff, snf->nfi_soc->sector_size); - memset(fdm_ptr, 0xff, snf->nfi_soc->fdm_ecc_size); - mtk_ecc_reset_parity(ecc_ptr, ecc_bits); - - return bitflips; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c deleted file mode 100644 index 89c72c10a5..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c +++ /dev/null @@ -1,515 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx); -static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx); - -#define SNAND_MEMORG_512M_2K_64 SNAND_MEMORG(2048, 64, 64, 512, 1, 1) -#define SNAND_MEMORG_1G_2K_64 SNAND_MEMORG(2048, 64, 64, 1024, 1, 1) -#define SNAND_MEMORG_2G_2K_64 SNAND_MEMORG(2048, 64, 64, 2048, 1, 1) -#define SNAND_MEMORG_2G_2K_120 SNAND_MEMORG(2048, 120, 64, 2048, 1, 1) -#define SNAND_MEMORG_4G_2K_64 SNAND_MEMORG(2048, 64, 64, 4096, 1, 1) -#define SNAND_MEMORG_1G_2K_120 SNAND_MEMORG(2048, 120, 64, 1024, 1, 1) -#define SNAND_MEMORG_1G_2K_128 SNAND_MEMORG(2048, 128, 64, 1024, 1, 1) -#define SNAND_MEMORG_2G_2K_128 SNAND_MEMORG(2048, 128, 64, 2048, 1, 1) -#define SNAND_MEMORG_4G_2K_128 SNAND_MEMORG(2048, 128, 64, 4096, 1, 1) -#define SNAND_MEMORG_4G_4K_240 SNAND_MEMORG(4096, 240, 64, 2048, 1, 1) -#define SNAND_MEMORG_4G_4K_256 SNAND_MEMORG(4096, 256, 64, 2048, 1, 1) -#define SNAND_MEMORG_8G_4K_256 SNAND_MEMORG(4096, 256, 64, 4096, 1, 1) -#define SNAND_MEMORG_2G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 2048, 2, 1) -#define SNAND_MEMORG_2G_2K_64_2D SNAND_MEMORG(2048, 64, 64, 1024, 1, 2) -#define SNAND_MEMORG_2G_2K_128_2P SNAND_MEMORG(2048, 128, 64, 2048, 2, 1) -#define SNAND_MEMORG_4G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 4096, 2, 1) -#define SNAND_MEMORG_4G_2K_128_2P_2D SNAND_MEMORG(2048, 128, 64, 2048, 2, 2) -#define SNAND_MEMORG_8G_4K_256_2D SNAND_MEMORG(4096, 256, 64, 2048, 1, 2) - -static const SNAND_IO_CAP(snand_cap_read_from_cache_quad, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 | - SPI_IO_1_4_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8), - SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 4)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_q2d, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 | - SPI_IO_1_4_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8), - SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 2)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_a8d, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 | - SPI_IO_1_4_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 8), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8), - SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 8)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_x4, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_1_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_x4_only, - SPI_IO_1_1_1 | SPI_IO_1_1_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8)); - -static const SNAND_IO_CAP(snand_cap_program_load_x1, - SPI_IO_1_1_1, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0)); - -static const SNAND_IO_CAP(snand_cap_program_load_x4, - SPI_IO_1_1_1 | SPI_IO_1_1_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_PROGRAM_LOAD_X4, 0)); - -static const struct snand_flash_info snand_flash_ids[] = { - SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20), - SNAND_MEMORG_512M_2K_64, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21), - SNAND_MEMORG_2G_2K_64_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_winbond_select_die), - SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - - SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_a8d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4), - SNAND_MEMORG_4G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ5xExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x51), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF1G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x14), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MX31LF1GE4BC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x1e), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x22), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x24), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x26), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2G14AC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x20), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF4G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x35), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF4GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x37), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("MT29F1G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x12), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("MT29F1G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x14), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MT29F2G01AAAED", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x9f), - SNAND_MEMORG_2G_2K_64_2P, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("MT29F2G01ABAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x24), - SNAND_MEMORG_2G_2K_128_2P, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MT29F4G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x32), - SNAND_MEMORG_4G_2K_64_2P, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("MT29F4G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x34), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MT29F4G01ADAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x36), - SNAND_MEMORG_4G_2K_128_2P_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_micron_select_die), - SNAND_INFO("MT29F8G01ADAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x46), - SNAND_MEMORG_8G_4K_256_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_micron_select_die), - - SNAND_INFO("TC58CVG0S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xc2), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("TC58CVG1S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcb), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("TC58CVG2S0HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcd), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("TC58CVG0S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe2), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("TC58CVG1S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xeb), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("TC58CVG2S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xed), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("TH58CVG3S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe4), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("F50L512M41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x20), - SNAND_MEMORG_512M_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("F50L1G41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("F50L1G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x01), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("F50L2G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x0a), - SNAND_MEMORG_2G_2K_64_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_winbond_select_die), - - SNAND_INFO("CS11G0T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x00), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G0G0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x10), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G0S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x20), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G1T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x01), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G1S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x21), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G2T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x02), - SNAND_MEMORG_4G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G2S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x22), - SNAND_MEMORG_4G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("EM73B044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x01), - SNAND_MEMORG_512M_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x11), - SNAND_MEMORG_1G_2K_120, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x09), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x18), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x19), - SNAND_MEMORG(2048, 64, 128, 512, 1, 1), - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1c), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1e), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x22), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x25), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x31), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0a), - SNAND_MEMORG_2G_2K_120, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x12), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x10), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x13), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x14), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x17), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCH", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1b), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCG", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1f), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCE", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x20), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCL", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2e), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x32), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x03), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0b), - SNAND_MEMORG_4G_4K_240, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x23), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2c), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044VCB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2f), - SNAND_MEMORG_4G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73F044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x24), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73F044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2d), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SNE", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0e), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNG", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0c), - SNAND_MEMORG_1G_2K_120, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCN", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0f), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("PN26G02A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe2), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("IS37SML01G1", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("ATO25D1GA", SNAND_ID(SNAND_ID_DYMMY, 0x9b, 0x12), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4_only, - &snand_cap_program_load_x4), - - SNAND_INFO("HYF1GQ4U", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x51), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("HYF2GQ4U", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x52), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), -}; - -static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx) -{ - uint8_t op[2]; - - if (dieidx > 1) { - snand_log_chip(snf->pdev, "Invalid die index %u\n", dieidx); - return -EINVAL; - } - - op[0] = SNAND_CMD_WINBOND_SELECT_DIE; - op[1] = (uint8_t)dieidx; - - return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0); -} - -static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx) -{ - int ret; - - if (dieidx > 1) { - snand_log_chip(snf->pdev, "Invalid die index %u\n", dieidx); - return -EINVAL; - } - - ret = mtk_snand_set_feature(snf, SNAND_FEATURE_MICRON_DIE_ADDR, - SNAND_MICRON_DIE_SEL_1); - if (ret) { - snand_log_chip(snf->pdev, - "Failed to set die selection feature\n"); - return ret; - } - - return 0; -} - -const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type, - const uint8_t *id) -{ - const struct snand_id *fid; - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(snand_flash_ids); i++) { - if (snand_flash_ids[i].id.type != type) - continue; - - fid = &snand_flash_ids[i].id; - if (memcmp(fid->id, id, fid->len)) - continue; - - return &snand_flash_ids[i]; - } - - return NULL; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c deleted file mode 100644 index 7e5baf0369..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c +++ /dev/null @@ -1,681 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mtk-snand.h" -#include "mtk-snand-os.h" - -struct mtk_snand_of_id { - enum mtk_snand_soc soc; -}; - -struct mtk_snand_mtd { - struct mtk_snand_plat_dev pdev; - - struct clk *nfi_clk; - struct clk *pad_clk; - struct clk *ecc_clk; - - void __iomem *nfi_regs; - void __iomem *ecc_regs; - - int irq; - - bool quad_spi; - enum mtk_snand_soc soc; - - struct mtd_info mtd; - struct mtk_snand *snf; - struct mtk_snand_chip_info cinfo; - uint8_t *page_cache; - struct mutex lock; -}; - -#define mtd_to_msm(mtd) container_of(mtd, struct mtk_snand_mtd, mtd) - -static int mtk_snand_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - u64 start_addr, end_addr; - int ret; - - /* Do not allow write past end of device */ - if ((instr->addr + instr->len) > msm->cinfo.chipsize) { - dev_err(msm->pdev.dev, - "attempt to erase beyond end of device\n"); - return -EINVAL; - } - - start_addr = instr->addr & (~mtd->erasesize_mask); - end_addr = instr->addr + instr->len; - if (end_addr & mtd->erasesize_mask) { - end_addr = (end_addr + mtd->erasesize_mask) & - (~mtd->erasesize_mask); - } - - mutex_lock(&msm->lock); - - while (start_addr < end_addr) { - if (mtk_snand_block_isbad(msm->snf, start_addr)) { - instr->fail_addr = start_addr; - ret = -EIO; - break; - } - - ret = mtk_snand_erase_block(msm->snf, start_addr); - if (ret) { - instr->fail_addr = start_addr; - break; - } - - start_addr += mtd->erasesize; - } - - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_read_data(struct mtk_snand_mtd *msm, uint64_t addr, - struct mtd_oob_ops *ops) -{ - struct mtd_info *mtd = &msm->mtd; - size_t len, ooblen, maxooblen, chklen; - uint32_t col, ooboffs; - uint8_t *datcache, *oobcache; - bool ecc_failed = false, raw = ops->mode == MTD_OPS_RAW ? true : false; - int ret, max_bitflips = 0; - - col = addr & mtd->writesize_mask; - addr &= ~mtd->writesize_mask; - maxooblen = mtd_oobavail(mtd, ops); - ooboffs = ops->ooboffs; - ooblen = ops->ooblen; - len = ops->len; - - datcache = len ? msm->page_cache : NULL; - oobcache = ooblen ? msm->page_cache + mtd->writesize : NULL; - - ops->oobretlen = 0; - ops->retlen = 0; - - while (len || ooblen) { - if (ops->mode == MTD_OPS_AUTO_OOB) - ret = mtk_snand_read_page_auto_oob(msm->snf, addr, - datcache, oobcache, maxooblen, NULL, raw); - else - ret = mtk_snand_read_page(msm->snf, addr, datcache, - oobcache, raw); - - if (ret < 0 && ret != -EBADMSG) - return ret; - - if (ret == -EBADMSG) { - mtd->ecc_stats.failed++; - ecc_failed = true; - } else { - mtd->ecc_stats.corrected += ret; - max_bitflips = max_t(int, ret, max_bitflips); - } - - if (len) { - /* Move data */ - chklen = mtd->writesize - col; - if (chklen > len) - chklen = len; - - memcpy(ops->datbuf + ops->retlen, datcache + col, - chklen); - len -= chklen; - col = 0; /* (col + chklen) % */ - ops->retlen += chklen; - } - - if (ooblen) { - /* Move oob */ - chklen = maxooblen - ooboffs; - if (chklen > ooblen) - chklen = ooblen; - - memcpy(ops->oobbuf + ops->oobretlen, oobcache + ooboffs, - chklen); - ooblen -= chklen; - ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */ - ops->oobretlen += chklen; - } - - addr += mtd->writesize; - } - - return ecc_failed ? -EBADMSG : max_bitflips; -} - -static int mtk_snand_mtd_read_oob(struct mtd_info *mtd, loff_t from, - struct mtd_oob_ops *ops) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - uint32_t maxooblen; - int ret; - - if (!ops->oobbuf && !ops->datbuf) { - if (ops->ooblen || ops->len) - return -EINVAL; - - return 0; - } - - switch (ops->mode) { - case MTD_OPS_PLACE_OOB: - case MTD_OPS_AUTO_OOB: - case MTD_OPS_RAW: - break; - default: - dev_err(msm->pdev.dev, "unsupported oob mode: %u\n", ops->mode); - return -EINVAL; - } - - maxooblen = mtd_oobavail(mtd, ops); - - /* Do not allow read past end of device */ - if (ops->datbuf && (from + ops->len) > msm->cinfo.chipsize) { - dev_err(msm->pdev.dev, - "attempt to read beyond end of device\n"); - return -EINVAL; - } - - if (unlikely(ops->ooboffs >= maxooblen)) { - dev_err(msm->pdev.dev, "attempt to start read outside oob\n"); - return -EINVAL; - } - - if (unlikely(from >= msm->cinfo.chipsize || - ops->ooboffs + ops->ooblen > - ((msm->cinfo.chipsize >> mtd->writesize_shift) - - (from >> mtd->writesize_shift)) * - maxooblen)) { - dev_err(msm->pdev.dev, - "attempt to read beyond end of device\n"); - return -EINVAL; - } - - mutex_lock(&msm->lock); - ret = mtk_snand_mtd_read_data(msm, from, ops); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_write_data(struct mtk_snand_mtd *msm, uint64_t addr, - struct mtd_oob_ops *ops) -{ - struct mtd_info *mtd = &msm->mtd; - size_t len, ooblen, maxooblen, chklen, oobwrlen; - uint32_t col, ooboffs; - uint8_t *datcache, *oobcache; - bool raw = ops->mode == MTD_OPS_RAW ? true : false; - int ret; - - col = addr & mtd->writesize_mask; - addr &= ~mtd->writesize_mask; - maxooblen = mtd_oobavail(mtd, ops); - ooboffs = ops->ooboffs; - ooblen = ops->ooblen; - len = ops->len; - - datcache = len ? msm->page_cache : NULL; - oobcache = ooblen ? msm->page_cache + mtd->writesize : NULL; - - ops->oobretlen = 0; - ops->retlen = 0; - - while (len || ooblen) { - if (len) { - /* Move data */ - chklen = mtd->writesize - col; - if (chklen > len) - chklen = len; - - memset(datcache, 0xff, col); - memcpy(datcache + col, ops->datbuf + ops->retlen, - chklen); - memset(datcache + col + chklen, 0xff, - mtd->writesize - col - chklen); - len -= chklen; - col = 0; /* (col + chklen) % */ - ops->retlen += chklen; - } - - oobwrlen = 0; - if (ooblen) { - /* Move oob */ - chklen = maxooblen - ooboffs; - if (chklen > ooblen) - chklen = ooblen; - - memset(oobcache, 0xff, ooboffs); - memcpy(oobcache + ooboffs, - ops->oobbuf + ops->oobretlen, chklen); - memset(oobcache + ooboffs + chklen, 0xff, - mtd->oobsize - ooboffs - chklen); - oobwrlen = chklen + ooboffs; - ooblen -= chklen; - ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */ - ops->oobretlen += chklen; - } - - if (ops->mode == MTD_OPS_AUTO_OOB) - ret = mtk_snand_write_page_auto_oob(msm->snf, addr, - datcache, oobcache, oobwrlen, NULL, raw); - else - ret = mtk_snand_write_page(msm->snf, addr, datcache, - oobcache, raw); - - if (ret) - return ret; - - addr += mtd->writesize; - } - - return 0; -} - -static int mtk_snand_mtd_write_oob(struct mtd_info *mtd, loff_t to, - struct mtd_oob_ops *ops) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - uint32_t maxooblen; - int ret; - - if (!ops->oobbuf && !ops->datbuf) { - if (ops->ooblen || ops->len) - return -EINVAL; - - return 0; - } - - switch (ops->mode) { - case MTD_OPS_PLACE_OOB: - case MTD_OPS_AUTO_OOB: - case MTD_OPS_RAW: - break; - default: - dev_err(msm->pdev.dev, "unsupported oob mode: %u\n", ops->mode); - return -EINVAL; - } - - maxooblen = mtd_oobavail(mtd, ops); - - /* Do not allow write past end of device */ - if (ops->datbuf && (to + ops->len) > msm->cinfo.chipsize) { - dev_err(msm->pdev.dev, - "attempt to write beyond end of device\n"); - return -EINVAL; - } - - if (unlikely(ops->ooboffs >= maxooblen)) { - dev_err(msm->pdev.dev, - "attempt to start write outside oob\n"); - return -EINVAL; - } - - if (unlikely(to >= msm->cinfo.chipsize || - ops->ooboffs + ops->ooblen > - ((msm->cinfo.chipsize >> mtd->writesize_shift) - - (to >> mtd->writesize_shift)) * - maxooblen)) { - dev_err(msm->pdev.dev, - "attempt to write beyond end of device\n"); - return -EINVAL; - } - - mutex_lock(&msm->lock); - ret = mtk_snand_mtd_write_data(msm, to, ops); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - int ret; - - mutex_lock(&msm->lock); - ret = mtk_snand_block_isbad(msm->snf, offs); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - int ret; - - mutex_lock(&msm->lock); - ret = mtk_snand_block_markbad(msm->snf, offs); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobecc) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - - if (section) - return -ERANGE; - - oobecc->offset = msm->cinfo.fdm_size * msm->cinfo.num_sectors; - oobecc->length = mtd->oobsize - oobecc->offset; - - return 0; -} - -static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobfree) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - - if (section >= msm->cinfo.num_sectors) - return -ERANGE; - - oobfree->length = msm->cinfo.fdm_size - 1; - oobfree->offset = section * msm->cinfo.fdm_size + 1; - - return 0; -} - -static irqreturn_t mtk_snand_irq(int irq, void *id) -{ - struct mtk_snand_mtd *msm = id; - int ret; - - ret = mtk_snand_irq_process(msm->snf); - if (ret > 0) - return IRQ_HANDLED; - - return IRQ_NONE; -} - -static int mtk_snand_enable_clk(struct mtk_snand_mtd *msm) -{ - int ret; - - ret = clk_prepare_enable(msm->nfi_clk); - if (ret) { - dev_err(msm->pdev.dev, "unable to enable nfi clk\n"); - return ret; - } - - ret = clk_prepare_enable(msm->pad_clk); - if (ret) { - dev_err(msm->pdev.dev, "unable to enable pad clk\n"); - clk_disable_unprepare(msm->nfi_clk); - return ret; - } - - ret = clk_prepare_enable(msm->ecc_clk); - if (ret) { - dev_err(msm->pdev.dev, "unable to enable ecc clk\n"); - clk_disable_unprepare(msm->nfi_clk); - clk_disable_unprepare(msm->pad_clk); - return ret; - } - - return 0; -} - -static void mtk_snand_disable_clk(struct mtk_snand_mtd *msm) -{ - clk_disable_unprepare(msm->nfi_clk); - clk_disable_unprepare(msm->pad_clk); - clk_disable_unprepare(msm->ecc_clk); -} - -static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { - .ecc = mtk_snand_ooblayout_ecc, - .free = mtk_snand_ooblayout_free, -}; - -static struct mtk_snand_of_id mt7622_soc_id = { .soc = SNAND_SOC_MT7622 }; -static struct mtk_snand_of_id mt7629_soc_id = { .soc = SNAND_SOC_MT7629 }; - -static const struct of_device_id mtk_snand_ids[] = { - { .compatible = "mediatek,mt7622-snand", .data = &mt7622_soc_id }, - { .compatible = "mediatek,mt7629-snand", .data = &mt7629_soc_id }, - { }, -}; - -MODULE_DEVICE_TABLE(of, mtk_snand_ids); - -static int mtk_snand_probe(struct platform_device *pdev) -{ - struct mtk_snand_platdata mtk_snand_pdata = {}; - struct device_node *np = pdev->dev.of_node; - const struct of_device_id *of_soc_id; - const struct mtk_snand_of_id *soc_id; - struct mtk_snand_mtd *msm; - struct mtd_info *mtd; - struct resource *r; - uint32_t size; - int ret; - - of_soc_id = of_match_node(mtk_snand_ids, np); - if (!of_soc_id) - return -EINVAL; - - soc_id = of_soc_id->data; - - msm = devm_kzalloc(&pdev->dev, sizeof(*msm), GFP_KERNEL); - if (!msm) - return -ENOMEM; - - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nfi"); - msm->nfi_regs = devm_ioremap_resource(&pdev->dev, r); - if (IS_ERR(msm->nfi_regs)) { - ret = PTR_ERR(msm->nfi_regs); - goto errout1; - } - - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecc"); - msm->ecc_regs = devm_ioremap_resource(&pdev->dev, r); - if (IS_ERR(msm->ecc_regs)) { - ret = PTR_ERR(msm->ecc_regs); - goto errout1; - } - - msm->pdev.dev = &pdev->dev; - msm->quad_spi = of_property_read_bool(np, "mediatek,quad-spi"); - msm->soc = soc_id->soc; - - msm->nfi_clk = devm_clk_get(msm->pdev.dev, "nfi_clk"); - if (IS_ERR(msm->nfi_clk)) { - ret = PTR_ERR(msm->nfi_clk); - dev_err(msm->pdev.dev, "unable to get nfi_clk, err = %d\n", - ret); - goto errout1; - } - - msm->ecc_clk = devm_clk_get(msm->pdev.dev, "ecc_clk"); - if (IS_ERR(msm->ecc_clk)) { - ret = PTR_ERR(msm->ecc_clk); - dev_err(msm->pdev.dev, "unable to get ecc_clk, err = %d\n", - ret); - goto errout1; - } - - msm->pad_clk = devm_clk_get(msm->pdev.dev, "pad_clk"); - if (IS_ERR(msm->pad_clk)) { - ret = PTR_ERR(msm->pad_clk); - dev_err(msm->pdev.dev, "unable to get pad_clk, err = %d\n", - ret); - goto errout1; - } - - ret = mtk_snand_enable_clk(msm); - if (ret) - goto errout1; - - /* Probe SPI-NAND Flash */ - mtk_snand_pdata.soc = msm->soc; - mtk_snand_pdata.quad_spi = msm->quad_spi; - mtk_snand_pdata.nfi_base = msm->nfi_regs; - mtk_snand_pdata.ecc_base = msm->ecc_regs; - - ret = mtk_snand_init(&msm->pdev, &mtk_snand_pdata, &msm->snf); - if (ret) - goto errout1; - - msm->irq = platform_get_irq(pdev, 0); - if (msm->irq >= 0) { - ret = devm_request_irq(msm->pdev.dev, msm->irq, mtk_snand_irq, - 0x0, "mtk-snand", msm); - if (ret) { - dev_err(msm->pdev.dev, "failed to request snfi irq\n"); - goto errout2; - } - - ret = dma_set_mask(msm->pdev.dev, DMA_BIT_MASK(32)); - if (ret) { - dev_err(msm->pdev.dev, "failed to set dma mask\n"); - goto errout3; - } - } - - mtk_snand_get_chip_info(msm->snf, &msm->cinfo); - - size = msm->cinfo.pagesize + msm->cinfo.sparesize; - msm->page_cache = devm_kmalloc(msm->pdev.dev, size, GFP_KERNEL); - if (!msm->page_cache) { - dev_err(msm->pdev.dev, "failed to allocate page cache\n"); - ret = -ENOMEM; - goto errout3; - } - - mutex_init(&msm->lock); - - dev_info(msm->pdev.dev, - "chip is %s, size %lluMB, page size %u, oob size %u\n", - msm->cinfo.model, msm->cinfo.chipsize >> 20, - msm->cinfo.pagesize, msm->cinfo.sparesize); - - /* Initialize mtd for SPI-NAND */ - mtd = &msm->mtd; - - mtd->owner = THIS_MODULE; - mtd->dev.parent = &pdev->dev; - mtd->type = MTD_NANDFLASH; - mtd->flags = MTD_CAP_NANDFLASH; - - mtd_set_of_node(mtd, np); - - mtd->size = msm->cinfo.chipsize; - mtd->erasesize = msm->cinfo.blocksize; - mtd->writesize = msm->cinfo.pagesize; - mtd->writebufsize = mtd->writesize; - mtd->oobsize = msm->cinfo.sparesize; - mtd->oobavail = msm->cinfo.num_sectors * (msm->cinfo.fdm_size - 1); - - mtd->erasesize_shift = ffs(mtd->erasesize) - 1; - mtd->writesize_shift = ffs(mtd->writesize) - 1; - mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1; - mtd->writesize_mask = (1 << mtd->writesize_shift) - 1; - - mtd->ooblayout = &mtk_snand_ooblayout; - - mtd->ecc_strength = msm->cinfo.ecc_strength; - mtd->bitflip_threshold = (mtd->ecc_strength * 3) / 4; - mtd->ecc_step_size = msm->cinfo.sector_size; - - mtd->_erase = mtk_snand_mtd_erase; - mtd->_read_oob = mtk_snand_mtd_read_oob; - mtd->_write_oob = mtk_snand_mtd_write_oob; - mtd->_block_isbad = mtk_snand_mtd_block_isbad; - mtd->_block_markbad = mtk_snand_mtd_block_markbad; - - ret = mtd_device_register(mtd, NULL, 0); - if (ret) { - dev_err(msm->pdev.dev, "failed to register mtd partition\n"); - goto errout4; - } - - platform_set_drvdata(pdev, msm); - - return 0; - -errout4: - devm_kfree(msm->pdev.dev, msm->page_cache); - -errout3: - if (msm->irq >= 0) - devm_free_irq(msm->pdev.dev, msm->irq, msm); - -errout2: - mtk_snand_cleanup(msm->snf); - -errout1: - devm_kfree(msm->pdev.dev, msm); - - platform_set_drvdata(pdev, NULL); - - return ret; -} - -static int mtk_snand_remove(struct platform_device *pdev) -{ - struct mtk_snand_mtd *msm = platform_get_drvdata(pdev); - struct mtd_info *mtd = &msm->mtd; - int ret; - - ret = mtd_device_unregister(mtd); - if (ret) - return ret; - - mtk_snand_cleanup(msm->snf); - - if (msm->irq >= 0) - devm_free_irq(msm->pdev.dev, msm->irq, msm); - - mtk_snand_disable_clk(msm); - - devm_kfree(msm->pdev.dev, msm->page_cache); - devm_kfree(msm->pdev.dev, msm); - - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static struct platform_driver mtk_snand_driver = { - .probe = mtk_snand_probe, - .remove = mtk_snand_remove, - .driver = { - .name = "mtk-snand", - .of_match_table = mtk_snand_ids, - }, -}; - -module_platform_driver(mtk_snand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Weijie Gao "); -MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c deleted file mode 100644 index 0c3ffec8b4..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -int mtk_snand_log(struct mtk_snand_plat_dev *pdev, - enum mtk_snand_log_category cat, const char *fmt, ...) -{ - const char *catname = ""; - va_list ap; - char *msg; - - switch (cat) { - case SNAND_LOG_NFI: - catname = "NFI"; - break; - case SNAND_LOG_SNFI: - catname = "SNFI"; - break; - case SNAND_LOG_ECC: - catname = "ECC"; - break; - default: - break; - } - - va_start(ap, fmt); - msg = kvasprintf(GFP_KERNEL, fmt, ap); - va_end(ap); - - if (!msg) { - dev_warn(pdev->dev, "unable to print log\n"); - return -1; - } - - if (*catname) - dev_warn(pdev->dev, "%s: %s", catname, msg); - else - dev_warn(pdev->dev, "%s", msg); - - kfree(msg); - - return 0; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h deleted file mode 100644 index eeeb83b53d..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#ifndef _MTK_SNAND_OS_H_ -#define _MTK_SNAND_OS_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct mtk_snand_plat_dev { - struct device *dev; - struct completion done; -}; - -/* Polling helpers */ -#define read16_poll_timeout(addr, val, cond, sleep_us, timeout_us) \ - readw_poll_timeout((addr), (val), (cond), (sleep_us), (timeout_us)) - -#define read32_poll_timeout(addr, val, cond, sleep_us, timeout_us) \ - readl_poll_timeout((addr), (val), (cond), (sleep_us), (timeout_us)) - -/* Timer helpers */ -#define mtk_snand_time_t ktime_t - -static inline mtk_snand_time_t timer_get_ticks(void) -{ - return ktime_get(); -} - -static inline mtk_snand_time_t timer_time_to_tick(uint32_t timeout_us) -{ - return ktime_add_us(ktime_set(0, 0), timeout_us); -} - -static inline bool timer_is_timeout(mtk_snand_time_t start_tick, - mtk_snand_time_t timeout_tick) -{ - ktime_t tmo = ktime_add(start_tick, timeout_tick); - - return ktime_compare(ktime_get(), tmo) > 0; -} - -/* Memory helpers */ -static inline void *generic_mem_alloc(struct mtk_snand_plat_dev *pdev, - size_t size) -{ - return devm_kzalloc(pdev->dev, size, GFP_KERNEL); -} -static inline void generic_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr) -{ - devm_kfree(pdev->dev, ptr); -} - -static inline void *dma_mem_alloc(struct mtk_snand_plat_dev *pdev, size_t size) -{ - return kzalloc(size, GFP_KERNEL); -} -static inline void dma_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr) -{ - kfree(ptr); -} - -static inline int dma_mem_map(struct mtk_snand_plat_dev *pdev, void *vaddr, - uintptr_t *dma_addr, size_t size, bool to_device) -{ - dma_addr_t addr; - int ret; - - addr = dma_map_single(pdev->dev, vaddr, size, - to_device ? DMA_TO_DEVICE : DMA_FROM_DEVICE); - ret = dma_mapping_error(pdev->dev, addr); - if (ret) - return ret; - - *dma_addr = (uintptr_t)addr; - - return 0; -} - -static inline void dma_mem_unmap(struct mtk_snand_plat_dev *pdev, - uintptr_t dma_addr, size_t size, - bool to_device) -{ - dma_unmap_single(pdev->dev, dma_addr, size, - to_device ? DMA_TO_DEVICE : DMA_FROM_DEVICE); -} - -/* Interrupt helpers */ -static inline void irq_completion_done(struct mtk_snand_plat_dev *pdev) -{ - complete(&pdev->done); -} - -static inline void irq_completion_init(struct mtk_snand_plat_dev *pdev) -{ - init_completion(&pdev->done); -} - -static inline int irq_completion_wait(struct mtk_snand_plat_dev *pdev, - void __iomem *reg, uint32_t bit, - uint32_t timeout_us) -{ - int ret; - - ret = wait_for_completion_timeout(&pdev->done, - usecs_to_jiffies(timeout_us)); - if (!ret) - return -ETIMEDOUT; - - return 0; -} - -#endif /* _MTK_SNAND_OS_H_ */ diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c deleted file mode 100644 index 729fd82d39..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c +++ /dev/null @@ -1,1862 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -/* NFI registers */ -#define NFI_CNFG 0x000 -#define CNFG_OP_MODE_S 12 -#define CNFG_OP_MODE_CUST 6 -#define CNFG_OP_MODE_PROGRAM 3 -#define CNFG_AUTO_FMT_EN BIT(9) -#define CNFG_HW_ECC_EN BIT(8) -#define CNFG_DMA_BURST_EN BIT(2) -#define CNFG_READ_MODE BIT(1) -#define CNFG_DMA_MODE BIT(0) - -#define NFI_PAGEFMT 0x0004 -#define NFI_SPARE_SIZE_LS_S 16 -#define NFI_FDM_ECC_NUM_S 12 -#define NFI_FDM_NUM_S 8 -#define NFI_SPARE_SIZE_S 4 -#define NFI_SEC_SEL_512 BIT(2) -#define NFI_PAGE_SIZE_S 0 -#define NFI_PAGE_SIZE_512_2K 0 -#define NFI_PAGE_SIZE_2K_4K 1 -#define NFI_PAGE_SIZE_4K_8K 2 -#define NFI_PAGE_SIZE_8K_16K 3 - -#define NFI_CON 0x008 -#define CON_SEC_NUM_S 12 -#define CON_BWR BIT(9) -#define CON_BRD BIT(8) -#define CON_NFI_RST BIT(1) -#define CON_FIFO_FLUSH BIT(0) - -#define NFI_INTR_EN 0x010 -#define NFI_INTR_STA 0x014 -#define NFI_IRQ_INTR_EN BIT(31) -#define NFI_IRQ_CUS_READ BIT(8) -#define NFI_IRQ_CUS_PG BIT(7) - -#define NFI_CMD 0x020 - -#define NFI_STRDATA 0x040 -#define STR_DATA BIT(0) - -#define NFI_STA 0x060 -#define NFI_NAND_FSM GENMASK(28, 24) -#define NFI_FSM GENMASK(19, 16) -#define READ_EMPTY BIT(12) - -#define NFI_FIFOSTA 0x064 -#define FIFO_WR_REMAIN_S 8 -#define FIFO_RD_REMAIN_S 0 - -#define NFI_ADDRCNTR 0x070 -#define SEC_CNTR GENMASK(16, 12) -#define SEC_CNTR_S 12 -#define NFI_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S) - -#define NFI_STRADDR 0x080 - -#define NFI_BYTELEN 0x084 -#define BUS_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S) - -#define NFI_FDM0L 0x0a0 -#define NFI_FDM0M 0x0a4 -#define NFI_FDML(n) (NFI_FDM0L + (n) * 8) -#define NFI_FDMM(n) (NFI_FDM0M + (n) * 8) - -#define NFI_DEBUG_CON1 0x220 -#define WBUF_EN BIT(2) - -#define NFI_MASTERSTA 0x224 -#define MAS_ADDR GENMASK(11, 9) -#define MAS_RD GENMASK(8, 6) -#define MAS_WR GENMASK(5, 3) -#define MAS_RDDLY GENMASK(2, 0) -#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) - -/* SNFI registers */ -#define SNF_MAC_CTL 0x500 -#define MAC_XIO_SEL BIT(4) -#define SF_MAC_EN BIT(3) -#define SF_TRIG BIT(2) -#define WIP_READY BIT(1) -#define WIP BIT(0) - -#define SNF_MAC_OUTL 0x504 -#define SNF_MAC_INL 0x508 - -#define SNF_RD_CTL2 0x510 -#define DATA_READ_DUMMY_S 8 -#define DATA_READ_CMD_S 0 - -#define SNF_RD_CTL3 0x514 - -#define SNF_PG_CTL1 0x524 -#define PG_LOAD_CMD_S 8 - -#define SNF_PG_CTL2 0x528 - -#define SNF_MISC_CTL 0x538 -#define SW_RST BIT(28) -#define FIFO_RD_LTC_S 25 -#define PG_LOAD_X4_EN BIT(20) -#define DATA_READ_MODE_S 16 -#define DATA_READ_MODE GENMASK(18, 16) -#define DATA_READ_MODE_X1 0 -#define DATA_READ_MODE_X2 1 -#define DATA_READ_MODE_X4 2 -#define DATA_READ_MODE_DUAL 5 -#define DATA_READ_MODE_QUAD 6 -#define PG_LOAD_CUSTOM_EN BIT(7) -#define DATARD_CUSTOM_EN BIT(6) -#define CS_DESELECT_CYC_S 0 - -#define SNF_MISC_CTL2 0x53c -#define PROGRAM_LOAD_BYTE_NUM_S 16 -#define READ_DATA_BYTE_NUM_S 11 - -#define SNF_DLY_CTL3 0x548 -#define SFCK_SAM_DLY_S 0 - -#define SNF_STA_CTL1 0x550 -#define CUS_PG_DONE BIT(28) -#define CUS_READ_DONE BIT(27) -#define SPI_STATE_S 0 -#define SPI_STATE GENMASK(3, 0) - -#define SNF_CFG 0x55c -#define SPI_MODE BIT(0) - -#define SNF_GPRAM 0x800 -#define SNF_GPRAM_SIZE 0xa0 - -#define SNFI_POLL_INTERVAL 1000000 - -static const uint8_t mt7622_spare_sizes[] = { 16, 26, 27, 28 }; - -static const struct mtk_snand_soc_data mtk_snand_socs[__SNAND_SOC_MAX] = { - [SNAND_SOC_MT7622] = { - .sector_size = 512, - .max_sectors = 8, - .fdm_size = 8, - .fdm_ecc_size = 1, - .fifo_size = 32, - .bbm_swap = false, - .empty_page_check = false, - .mastersta_mask = NFI_MASTERSTA_MASK_7622, - .spare_sizes = mt7622_spare_sizes, - .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) - }, - [SNAND_SOC_MT7629] = { - .sector_size = 512, - .max_sectors = 8, - .fdm_size = 8, - .fdm_ecc_size = 1, - .fifo_size = 32, - .bbm_swap = true, - .empty_page_check = false, - .mastersta_mask = NFI_MASTERSTA_MASK_7622, - .spare_sizes = mt7622_spare_sizes, - .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) - }, -}; - -static inline uint32_t nfi_read32(struct mtk_snand *snf, uint32_t reg) -{ - return readl(snf->nfi_base + reg); -} - -static inline void nfi_write32(struct mtk_snand *snf, uint32_t reg, - uint32_t val) -{ - writel(val, snf->nfi_base + reg); -} - -static inline void nfi_write16(struct mtk_snand *snf, uint32_t reg, - uint16_t val) -{ - writew(val, snf->nfi_base + reg); -} - -static inline void nfi_rmw32(struct mtk_snand *snf, uint32_t reg, uint32_t clr, - uint32_t set) -{ - uint32_t val; - - val = readl(snf->nfi_base + reg); - val &= ~clr; - val |= set; - writel(val, snf->nfi_base + reg); -} - -static void nfi_write_data(struct mtk_snand *snf, uint32_t reg, - const uint8_t *data, uint32_t len) -{ - uint32_t i, val = 0, es = sizeof(uint32_t); - - for (i = reg; i < reg + len; i++) { - val |= ((uint32_t)*data++) << (8 * (i % es)); - - if (i % es == es - 1 || i == reg + len - 1) { - nfi_write32(snf, i & ~(es - 1), val); - val = 0; - } - } -} - -static void nfi_read_data(struct mtk_snand *snf, uint32_t reg, uint8_t *data, - uint32_t len) -{ - uint32_t i, val = 0, es = sizeof(uint32_t); - - for (i = reg; i < reg + len; i++) { - if (i == reg || i % es == 0) - val = nfi_read32(snf, i & ~(es - 1)); - - *data++ = (uint8_t)(val >> (8 * (i % es))); - } -} - -static inline void do_bm_swap(uint8_t *bm1, uint8_t *bm2) -{ - uint8_t tmp = *bm1; - *bm1 = *bm2; - *bm2 = tmp; -} - -static void mtk_snand_bm_swap_raw(struct mtk_snand *snf) -{ - uint32_t fdm_bbm_pos; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - fdm_bbm_pos = (snf->ecc_steps - 1) * snf->raw_sector_size + - snf->nfi_soc->sector_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos], - &snf->page_cache[snf->writesize]); -} - -static void mtk_snand_bm_swap(struct mtk_snand *snf) -{ - uint32_t buf_bbm_pos, fdm_bbm_pos; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - buf_bbm_pos = snf->writesize - - (snf->ecc_steps - 1) * snf->spare_per_sector; - fdm_bbm_pos = snf->writesize + - (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos], - &snf->page_cache[buf_bbm_pos]); -} - -static void mtk_snand_fdm_bm_swap_raw(struct mtk_snand *snf) -{ - uint32_t fdm_bbm_pos1, fdm_bbm_pos2; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - fdm_bbm_pos1 = snf->nfi_soc->sector_size; - fdm_bbm_pos2 = (snf->ecc_steps - 1) * snf->raw_sector_size + - snf->nfi_soc->sector_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos1], - &snf->page_cache[fdm_bbm_pos2]); -} - -static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) -{ - uint32_t fdm_bbm_pos1, fdm_bbm_pos2; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - fdm_bbm_pos1 = snf->writesize; - fdm_bbm_pos2 = snf->writesize + - (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos1], - &snf->page_cache[fdm_bbm_pos2]); -} - -static int mtk_nfi_reset(struct mtk_snand *snf) -{ - uint32_t val, fifo_mask; - int ret; - - nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); - - ret = read16_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, - !(val & snf->nfi_soc->mastersta_mask), 0, - SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "NFI master is still busy after reset\n"); - return ret; - } - - ret = read32_poll_timeout(snf->nfi_base + NFI_STA, val, - !(val & (NFI_FSM | NFI_NAND_FSM)), 0, - SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, "Failed to reset NFI\n"); - return ret; - } - - fifo_mask = ((snf->nfi_soc->fifo_size - 1) << FIFO_RD_REMAIN_S) | - ((snf->nfi_soc->fifo_size - 1) << FIFO_WR_REMAIN_S); - ret = read16_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, - !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, "NFI FIFOs are not empty\n"); - return ret; - } - - return 0; -} - -static int mtk_snand_mac_reset(struct mtk_snand *snf) -{ - int ret; - uint32_t val; - - nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); - - ret = read32_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, - !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); - if (ret) - snand_log_snfi(snf->pdev, "Failed to reset SNFI MAC\n"); - - nfi_write32(snf, SNF_MISC_CTL, (2 << FIFO_RD_LTC_S) | - (10 << CS_DESELECT_CYC_S)); - - return ret; -} - -static int mtk_snand_mac_trigger(struct mtk_snand *snf, uint32_t outlen, - uint32_t inlen) -{ - int ret; - uint32_t val; - - nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); - nfi_write32(snf, SNF_MAC_OUTL, outlen); - nfi_write32(snf, SNF_MAC_INL, inlen); - - nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); - - ret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, - val & WIP_READY, 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_snfi(snf->pdev, "Timed out waiting for WIP_READY\n"); - goto cleanup; - } - - ret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, - !(val & WIP), 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_snfi(snf->pdev, - "Timed out waiting for WIP cleared\n"); - } - -cleanup: - nfi_write32(snf, SNF_MAC_CTL, 0); - - return ret; -} - -int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen, - uint8_t *in, uint32_t inlen) -{ - int ret; - - if (outlen + inlen > SNF_GPRAM_SIZE) - return -EINVAL; - - mtk_snand_mac_reset(snf); - - nfi_write_data(snf, SNF_GPRAM, out, outlen); - - ret = mtk_snand_mac_trigger(snf, outlen, inlen); - if (ret) - return ret; - - if (!inlen) - return 0; - - nfi_read_data(snf, SNF_GPRAM + outlen, in, inlen); - - return 0; -} - -static int mtk_snand_get_feature(struct mtk_snand *snf, uint32_t addr) -{ - uint8_t op[2], val; - int ret; - - op[0] = SNAND_CMD_GET_FEATURE; - op[1] = (uint8_t)addr; - - ret = mtk_snand_mac_io(snf, op, sizeof(op), &val, 1); - if (ret) - return ret; - - return val; -} - -int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val) -{ - uint8_t op[3]; - - op[0] = SNAND_CMD_SET_FEATURE; - op[1] = (uint8_t)addr; - op[2] = (uint8_t)val; - - return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0); -} - -static int mtk_snand_poll_status(struct mtk_snand *snf, uint32_t wait_us) -{ - int val; - mtk_snand_time_t time_start, tmo; - - time_start = timer_get_ticks(); - tmo = timer_time_to_tick(wait_us); - - do { - val = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR); - if (!(val & SNAND_STATUS_OIP)) - return val & (SNAND_STATUS_ERASE_FAIL | - SNAND_STATUS_PROGRAM_FAIL); - } while (!timer_is_timeout(time_start, tmo)); - - return -ETIMEDOUT; -} - -int mtk_snand_chip_reset(struct mtk_snand *snf) -{ - uint8_t op = SNAND_CMD_RESET; - int ret; - - ret = mtk_snand_mac_io(snf, &op, 1, NULL, 0); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) - return ret; - - return 0; -} - -static int mtk_snand_config_feature(struct mtk_snand *snf, uint8_t clr, - uint8_t set) -{ - int val, newval; - int ret; - - val = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR); - if (val < 0) { - snand_log_chip(snf->pdev, - "Failed to get configuration feature\n"); - return val; - } - - newval = (val & (~clr)) | set; - - if (newval == val) - return 0; - - ret = mtk_snand_set_feature(snf, SNAND_FEATURE_CONFIG_ADDR, - (uint8_t)newval); - if (val < 0) { - snand_log_chip(snf->pdev, - "Failed to set configuration feature\n"); - return ret; - } - - val = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR); - if (val < 0) { - snand_log_chip(snf->pdev, - "Failed to get configuration feature\n"); - return val; - } - - if (newval != val) - return -ENOTSUPP; - - return 0; -} - -static int mtk_snand_ondie_ecc_control(struct mtk_snand *snf, bool enable) -{ - int ret; - - if (enable) - ret = mtk_snand_config_feature(snf, 0, SNAND_FEATURE_ECC_EN); - else - ret = mtk_snand_config_feature(snf, SNAND_FEATURE_ECC_EN, 0); - - if (ret) { - snand_log_chip(snf->pdev, "Failed to %s On-Die ECC engine\n", - enable ? "enable" : "disable"); - } - - return ret; -} - -static int mtk_snand_qspi_control(struct mtk_snand *snf, bool enable) -{ - int ret; - - if (enable) { - ret = mtk_snand_config_feature(snf, 0, - SNAND_FEATURE_QUAD_ENABLE); - } else { - ret = mtk_snand_config_feature(snf, - SNAND_FEATURE_QUAD_ENABLE, 0); - } - - if (ret) { - snand_log_chip(snf->pdev, "Failed to %s quad spi\n", - enable ? "enable" : "disable"); - } - - return ret; -} - -static int mtk_snand_unlock(struct mtk_snand *snf) -{ - int ret; - - ret = mtk_snand_set_feature(snf, SNAND_FEATURE_PROTECT_ADDR, 0); - if (ret) { - snand_log_chip(snf->pdev, "Failed to set protection feature\n"); - return ret; - } - - return 0; -} - -static int mtk_snand_write_enable(struct mtk_snand *snf) -{ - uint8_t op = SNAND_CMD_WRITE_ENABLE; - int ret, val; - - ret = mtk_snand_mac_io(snf, &op, 1, NULL, 0); - if (ret) - return ret; - - val = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR); - if (val < 0) - return ret; - - if (val & SNAND_STATUS_WEL) - return 0; - - snand_log_chip(snf->pdev, "Failed to send write-enable command\n"); - - return -ENOTSUPP; -} - -static int mtk_snand_select_die(struct mtk_snand *snf, uint32_t dieidx) -{ - if (!snf->select_die) - return 0; - - return snf->select_die(snf, dieidx); -} - -static uint64_t mtk_snand_select_die_address(struct mtk_snand *snf, - uint64_t addr) -{ - uint32_t dieidx; - - if (!snf->select_die) - return addr; - - dieidx = addr >> snf->die_shift; - - mtk_snand_select_die(snf, dieidx); - - return addr & snf->die_mask; -} - -static uint32_t mtk_snand_get_plane_address(struct mtk_snand *snf, - uint32_t page) -{ - uint32_t pages_per_block; - - pages_per_block = 1 << (snf->erasesize_shift - snf->writesize_shift); - - if (page & pages_per_block) - return 1 << (snf->writesize_shift + 1); - - return 0; -} - -static int mtk_snand_page_op(struct mtk_snand *snf, uint32_t page, uint8_t cmd) -{ - uint8_t op[4]; - - op[0] = cmd; - op[1] = (page >> 16) & 0xff; - op[2] = (page >> 8) & 0xff; - op[3] = page & 0xff; - - return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0); -} - -static void mtk_snand_read_fdm(struct mtk_snand *snf, uint8_t *buf) -{ - uint32_t vall, valm; - uint8_t *oobptr = buf; - int i, j; - - for (i = 0; i < snf->ecc_steps; i++) { - vall = nfi_read32(snf, NFI_FDML(i)); - valm = nfi_read32(snf, NFI_FDMM(i)); - - for (j = 0; j < snf->nfi_soc->fdm_size; j++) - oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); - - oobptr += snf->nfi_soc->fdm_size; - } -} - -static int mtk_snand_read_ecc_parity(struct mtk_snand *snf, uint32_t page, - uint32_t sect, uint8_t *oob) -{ - uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - uint32_t coladdr, raw_offs, offs; - uint8_t op[4]; - - if (sizeof(op) + ecc_bytes > SNF_GPRAM_SIZE) { - snand_log_snfi(snf->pdev, - "ECC parity size does not fit the GPRAM\n"); - return -ENOTSUPP; - } - - raw_offs = sect * snf->raw_sector_size + snf->nfi_soc->sector_size + - snf->nfi_soc->fdm_size; - offs = snf->ecc_steps * snf->nfi_soc->fdm_size + sect * ecc_bytes; - - /* Column address with plane bit */ - coladdr = raw_offs | mtk_snand_get_plane_address(snf, page); - - op[0] = SNAND_CMD_READ_FROM_CACHE; - op[1] = (coladdr >> 8) & 0xff; - op[2] = coladdr & 0xff; - op[3] = 0; - - return mtk_snand_mac_io(snf, op, sizeof(op), oob + offs, ecc_bytes); -} - -static int mtk_snand_check_ecc_result(struct mtk_snand *snf, uint32_t page) -{ - uint8_t *oob = snf->page_cache + snf->writesize; - int i, rc, ret = 0, max_bitflips = 0; - - for (i = 0; i < snf->ecc_steps; i++) { - if (snf->sect_bf[i] >= 0) { - if (snf->sect_bf[i] > max_bitflips) - max_bitflips = snf->sect_bf[i]; - continue; - } - - rc = mtk_snand_read_ecc_parity(snf, page, i, oob); - if (rc) - return rc; - - rc = mtk_ecc_fixup_empty_sector(snf, i); - if (rc < 0) { - ret = -EBADMSG; - - snand_log_ecc(snf->pdev, - "Uncorrectable bitflips in page %u sect %u\n", - page, i); - } else if (rc) { - snf->sect_bf[i] = rc; - - if (snf->sect_bf[i] > max_bitflips) - max_bitflips = snf->sect_bf[i]; - - snand_log_ecc(snf->pdev, - "%u bitflip%s corrected in page %u sect %u\n", - rc, rc > 1 ? "s" : "", page, i); - } else { - snf->sect_bf[i] = 0; - } - } - - return ret ? ret : max_bitflips; -} - -static int mtk_snand_read_cache(struct mtk_snand *snf, uint32_t page, bool raw) -{ - uint32_t coladdr, rwbytes, mode, len, val; - uintptr_t dma_addr; - int ret; - - /* Column address with plane bit */ - coladdr = mtk_snand_get_plane_address(snf, page); - - mtk_snand_mac_reset(snf); - mtk_nfi_reset(snf); - - /* Command and dummy cycles */ - nfi_write32(snf, SNF_RD_CTL2, - ((uint32_t)snf->dummy_rfc << DATA_READ_DUMMY_S) | - (snf->opcode_rfc << DATA_READ_CMD_S)); - - /* Column address */ - nfi_write32(snf, SNF_RD_CTL3, coladdr); - - /* Set read mode */ - mode = (uint32_t)snf->mode_rfc << DATA_READ_MODE_S; - nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, mode | DATARD_CUSTOM_EN); - - /* Set bytes to read */ - rwbytes = snf->ecc_steps * snf->raw_sector_size; - nfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) | - rwbytes); - - /* NFI read prepare */ - mode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN; - nfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | - CNFG_DMA_BURST_EN | CNFG_READ_MODE | CNFG_DMA_MODE | mode); - - nfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S)); - - /* Prepare for DMA read */ - len = snf->writesize + snf->oobsize; - ret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, false); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA map from device failed with %d\n", ret); - return ret; - } - - nfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr); - - if (!raw) - mtk_snand_ecc_decoder_start(snf); - - /* Prepare for custom read interrupt */ - nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); - irq_completion_init(snf->pdev); - - /* Trigger NFI into custom mode */ - nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); - - /* Start DMA read */ - nfi_rmw32(snf, NFI_CON, 0, CON_BRD); - nfi_write16(snf, NFI_STRDATA, STR_DATA); - - /* Wait for operation finished */ - ret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1, - CUS_READ_DONE, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA timed out for reading from cache\n"); - goto cleanup; - } - - /* Wait for BUS_SEC_CNTR returning expected value */ - ret = read32_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, - BUS_SEC_CNTR(val) >= snf->ecc_steps, - 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "Timed out waiting for BUS_SEC_CNTR\n"); - goto cleanup; - } - - /* Wait for bus becoming idle */ - ret = read32_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, - !(val & snf->nfi_soc->mastersta_mask), - 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "Timed out waiting for bus becoming idle\n"); - goto cleanup; - } - - if (!raw) { - ret = mtk_ecc_wait_decoder_done(snf); - if (ret) - goto cleanup; - - mtk_snand_read_fdm(snf, snf->page_cache + snf->writesize); - - mtk_ecc_check_decode_error(snf); - mtk_snand_ecc_decoder_stop(snf); - - ret = mtk_snand_check_ecc_result(snf, page); - } - -cleanup: - /* DMA cleanup */ - dma_mem_unmap(snf->pdev, dma_addr, len, false); - - /* Stop read */ - nfi_write32(snf, NFI_CON, 0); - nfi_write16(snf, NFI_CNFG, 0); - - /* Clear SNF done flag */ - nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); - nfi_write32(snf, SNF_STA_CTL1, 0); - - /* Disable interrupt */ - nfi_read32(snf, NFI_INTR_STA); - nfi_write32(snf, NFI_INTR_EN, 0); - - nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); - - return ret; -} - -static void mtk_snand_from_raw_page(struct mtk_snand *snf, void *buf, void *oob) -{ - uint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - uint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size; - uint8_t *bufptr = buf, *oobptr = oob, *raw_sector; - - for (i = 0; i < snf->ecc_steps; i++) { - raw_sector = snf->page_cache + i * snf->raw_sector_size; - - if (buf) { - memcpy(bufptr, raw_sector, snf->nfi_soc->sector_size); - bufptr += snf->nfi_soc->sector_size; - } - - raw_sector += snf->nfi_soc->sector_size; - - if (oob) { - memcpy(oobptr, raw_sector, snf->nfi_soc->fdm_size); - oobptr += snf->nfi_soc->fdm_size; - raw_sector += snf->nfi_soc->fdm_size; - - memcpy(eccptr, raw_sector, ecc_bytes); - eccptr += ecc_bytes; - } - } -} - -static int mtk_snand_do_read_page(struct mtk_snand *snf, uint64_t addr, - void *buf, void *oob, bool raw, bool format) -{ - uint64_t die_addr; - uint32_t page; - int ret; - - die_addr = mtk_snand_select_die_address(snf, addr); - page = die_addr >> snf->writesize_shift; - - ret = mtk_snand_page_op(snf, page, SNAND_CMD_READ_TO_CACHE); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) { - snand_log_chip(snf->pdev, "Read to cache command timed out\n"); - return ret; - } - - ret = mtk_snand_read_cache(snf, page, raw); - if (ret < 0 && ret != -EBADMSG) - return ret; - - if (raw) { - if (format) { - mtk_snand_bm_swap_raw(snf); - mtk_snand_fdm_bm_swap_raw(snf); - mtk_snand_from_raw_page(snf, buf, oob); - } else { - if (buf) - memcpy(buf, snf->page_cache, snf->writesize); - - if (oob) { - memset(oob, 0xff, snf->oobsize); - memcpy(oob, snf->page_cache + snf->writesize, - snf->ecc_steps * snf->spare_per_sector); - } - } - } else { - mtk_snand_bm_swap(snf); - mtk_snand_fdm_bm_swap(snf); - - if (buf) - memcpy(buf, snf->page_cache, snf->writesize); - - if (oob) { - memset(oob, 0xff, snf->oobsize); - memcpy(oob, snf->page_cache + snf->writesize, - snf->ecc_steps * snf->nfi_soc->fdm_size); - } - } - - return ret; -} - -int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf, - void *oob, bool raw) -{ - if (!snf || (!buf && !oob)) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - return mtk_snand_do_read_page(snf, addr, buf, oob, raw, true); -} - -static void mtk_snand_write_fdm(struct mtk_snand *snf, const uint8_t *buf) -{ - uint32_t vall, valm, fdm_size = snf->nfi_soc->fdm_size; - const uint8_t *oobptr = buf; - int i, j; - - for (i = 0; i < snf->ecc_steps; i++) { - vall = 0; - valm = 0; - - for (j = 0; j < 8; j++) { - if (j < 4) - vall |= (j < fdm_size ? oobptr[j] : 0xff) - << (j * 8); - else - valm |= (j < fdm_size ? oobptr[j] : 0xff) - << ((j - 4) * 8); - } - - nfi_write32(snf, NFI_FDML(i), vall); - nfi_write32(snf, NFI_FDMM(i), valm); - - oobptr += fdm_size; - } -} - -static int mtk_snand_program_load(struct mtk_snand *snf, uint32_t page, - bool raw) -{ - uint32_t coladdr, rwbytes, mode, len, val; - uintptr_t dma_addr; - int ret; - - /* Column address with plane bit */ - coladdr = mtk_snand_get_plane_address(snf, page); - - mtk_snand_mac_reset(snf); - mtk_nfi_reset(snf); - - /* Write FDM registers if necessary */ - if (!raw) - mtk_snand_write_fdm(snf, snf->page_cache + snf->writesize); - - /* Command */ - nfi_write32(snf, SNF_PG_CTL1, (snf->opcode_pl << PG_LOAD_CMD_S)); - - /* Column address */ - nfi_write32(snf, SNF_PG_CTL2, coladdr); - - /* Set write mode */ - mode = snf->mode_pl ? PG_LOAD_X4_EN : 0; - nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, mode | PG_LOAD_CUSTOM_EN); - - /* Set bytes to write */ - rwbytes = snf->ecc_steps * snf->raw_sector_size; - nfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) | - rwbytes); - - /* NFI write prepare */ - mode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN; - nfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | - CNFG_DMA_BURST_EN | CNFG_DMA_MODE | mode); - - nfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S)); - - /* Prepare for DMA write */ - len = snf->writesize + snf->oobsize; - ret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, true); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA map to device failed with %d\n", ret); - return ret; - } - - nfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr); - - if (!raw) - mtk_snand_ecc_encoder_start(snf); - - /* Prepare for custom write interrupt */ - nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); - irq_completion_init(snf->pdev); - - /* Trigger NFI into custom mode */ - nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); - - /* Start DMA write */ - nfi_rmw32(snf, NFI_CON, 0, CON_BWR); - nfi_write16(snf, NFI_STRDATA, STR_DATA); - - /* Wait for operation finished */ - ret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1, - CUS_PG_DONE, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA timed out for program load\n"); - goto cleanup; - } - - /* Wait for NFI_SEC_CNTR returning expected value */ - ret = read32_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, - NFI_SEC_CNTR(val) >= snf->ecc_steps, - 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "Timed out waiting for NFI_SEC_CNTR\n"); - goto cleanup; - } - - if (!raw) - mtk_snand_ecc_encoder_stop(snf); - -cleanup: - /* DMA cleanup */ - dma_mem_unmap(snf->pdev, dma_addr, len, true); - - /* Stop write */ - nfi_write32(snf, NFI_CON, 0); - nfi_write16(snf, NFI_CNFG, 0); - - /* Clear SNF done flag */ - nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); - nfi_write32(snf, SNF_STA_CTL1, 0); - - /* Disable interrupt */ - nfi_read32(snf, NFI_INTR_STA); - nfi_write32(snf, NFI_INTR_EN, 0); - - nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0); - - return ret; -} - -static void mtk_snand_to_raw_page(struct mtk_snand *snf, - const void *buf, const void *oob, - bool empty_ecc) -{ - uint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - const uint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size; - const uint8_t *bufptr = buf, *oobptr = oob; - uint8_t *raw_sector; - - memset(snf->page_cache, 0xff, snf->writesize + snf->oobsize); - for (i = 0; i < snf->ecc_steps; i++) { - raw_sector = snf->page_cache + i * snf->raw_sector_size; - - if (buf) { - memcpy(raw_sector, bufptr, snf->nfi_soc->sector_size); - bufptr += snf->nfi_soc->sector_size; - } - - raw_sector += snf->nfi_soc->sector_size; - - if (oob) { - memcpy(raw_sector, oobptr, snf->nfi_soc->fdm_size); - oobptr += snf->nfi_soc->fdm_size; - raw_sector += snf->nfi_soc->fdm_size; - - if (empty_ecc) - memset(raw_sector, 0xff, ecc_bytes); - else - memcpy(raw_sector, eccptr, ecc_bytes); - eccptr += ecc_bytes; - } - } -} - -static bool mtk_snand_is_empty_page(struct mtk_snand *snf, const void *buf, - const void *oob) -{ - const uint8_t *p = buf; - uint32_t i, j; - - if (buf) { - for (i = 0; i < snf->writesize; i++) { - if (p[i] != 0xff) - return false; - } - } - - if (oob) { - for (j = 0; j < snf->ecc_steps; j++) { - p = oob + j * snf->nfi_soc->fdm_size; - - for (i = 0; i < snf->nfi_soc->fdm_ecc_size; i++) { - if (p[i] != 0xff) - return false; - } - } - } - - return true; -} - -static int mtk_snand_do_write_page(struct mtk_snand *snf, uint64_t addr, - const void *buf, const void *oob, - bool raw, bool format) -{ - uint64_t die_addr; - bool empty_ecc = false; - uint32_t page; - int ret; - - die_addr = mtk_snand_select_die_address(snf, addr); - page = die_addr >> snf->writesize_shift; - - if (!raw && mtk_snand_is_empty_page(snf, buf, oob)) { - /* - * If the data in the page to be ecc-ed is full 0xff, - * change to raw write mode - */ - raw = true; - format = true; - - /* fill ecc parity code region with 0xff */ - empty_ecc = true; - } - - if (raw) { - if (format) { - mtk_snand_to_raw_page(snf, buf, oob, empty_ecc); - mtk_snand_fdm_bm_swap_raw(snf); - mtk_snand_bm_swap_raw(snf); - } else { - memset(snf->page_cache, 0xff, - snf->writesize + snf->oobsize); - - if (buf) - memcpy(snf->page_cache, buf, snf->writesize); - - if (oob) { - memcpy(snf->page_cache + snf->writesize, oob, - snf->ecc_steps * snf->spare_per_sector); - } - } - } else { - memset(snf->page_cache, 0xff, snf->writesize + snf->oobsize); - if (buf) - memcpy(snf->page_cache, buf, snf->writesize); - - if (oob) { - memcpy(snf->page_cache + snf->writesize, oob, - snf->ecc_steps * snf->nfi_soc->fdm_size); - } - - mtk_snand_fdm_bm_swap(snf); - mtk_snand_bm_swap(snf); - } - - ret = mtk_snand_write_enable(snf); - if (ret) - return ret; - - ret = mtk_snand_program_load(snf, page, raw); - if (ret) - return ret; - - ret = mtk_snand_page_op(snf, page, SNAND_CMD_PROGRAM_EXECUTE); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) { - snand_log_chip(snf->pdev, - "Page program command timed out on page %u\n", - page); - return ret; - } - - if (ret & SNAND_STATUS_PROGRAM_FAIL) { - snand_log_chip(snf->pdev, - "Page program failed on page %u\n", page); - return -EIO; - } - - return 0; -} - -int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf, - const void *oob, bool raw) -{ - if (!snf || (!buf && !oob)) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - return mtk_snand_do_write_page(snf, addr, buf, oob, raw, true); -} - -int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr) -{ - uint64_t die_addr; - uint32_t page, block; - int ret; - - if (!snf) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - die_addr = mtk_snand_select_die_address(snf, addr); - block = die_addr >> snf->erasesize_shift; - page = block << (snf->erasesize_shift - snf->writesize_shift); - - ret = mtk_snand_write_enable(snf); - if (ret) - return ret; - - ret = mtk_snand_page_op(snf, page, SNAND_CMD_BLOCK_ERASE); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) { - snand_log_chip(snf->pdev, - "Block erase command timed out on block %u\n", - block); - return ret; - } - - if (ret & SNAND_STATUS_ERASE_FAIL) { - snand_log_chip(snf->pdev, - "Block erase failed on block %u\n", block); - return -EIO; - } - - return 0; -} - -static int mtk_snand_block_isbad_std(struct mtk_snand *snf, uint64_t addr) -{ - int ret; - - ret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true, - false); - if (ret && ret != -EBADMSG) - return ret; - - return snf->buf_cache[0] != 0xff; -} - -static int mtk_snand_block_isbad_mtk(struct mtk_snand *snf, uint64_t addr) -{ - int ret; - - ret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true, - true); - if (ret && ret != -EBADMSG) - return ret; - - return snf->buf_cache[0] != 0xff; -} - -int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr) -{ - if (!snf) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - addr &= ~snf->erasesize_mask; - - if (snf->nfi_soc->bbm_swap) - return mtk_snand_block_isbad_std(snf, addr); - - return mtk_snand_block_isbad_mtk(snf, addr); -} - -static int mtk_snand_block_markbad_std(struct mtk_snand *snf, uint64_t addr) -{ - /* Standard BBM position */ - memset(snf->buf_cache, 0xff, snf->oobsize); - snf->buf_cache[0] = 0; - - return mtk_snand_do_write_page(snf, addr, NULL, snf->buf_cache, true, - false); -} - -static int mtk_snand_block_markbad_mtk(struct mtk_snand *snf, uint64_t addr) -{ - /* Write the whole page with zeros */ - memset(snf->buf_cache, 0, snf->writesize + snf->oobsize); - - return mtk_snand_do_write_page(snf, addr, snf->buf_cache, - snf->buf_cache + snf->writesize, true, - true); -} - -int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr) -{ - if (!snf) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - addr &= ~snf->erasesize_mask; - - if (snf->nfi_soc->bbm_swap) - return mtk_snand_block_markbad_std(snf, addr); - - return mtk_snand_block_markbad_mtk(snf, addr); -} - -int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw, - const uint8_t *oobbuf, size_t ooblen) -{ - size_t len = ooblen, sect_fdm_len; - const uint8_t *oob = oobbuf; - uint32_t step = 0; - - if (!snf || !oobraw || !oob) - return -EINVAL; - - while (len && step < snf->ecc_steps) { - sect_fdm_len = snf->nfi_soc->fdm_size - 1; - if (sect_fdm_len > len) - sect_fdm_len = len; - - memcpy(oobraw + step * snf->nfi_soc->fdm_size + 1, oob, - sect_fdm_len); - - len -= sect_fdm_len; - oob += sect_fdm_len; - step++; - } - - return len; -} - -int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf, - size_t ooblen, const uint8_t *oobraw) -{ - size_t len = ooblen, sect_fdm_len; - uint8_t *oob = oobbuf; - uint32_t step = 0; - - if (!snf || !oobraw || !oob) - return -EINVAL; - - while (len && step < snf->ecc_steps) { - sect_fdm_len = snf->nfi_soc->fdm_size - 1; - if (sect_fdm_len > len) - sect_fdm_len = len; - - memcpy(oob, oobraw + step * snf->nfi_soc->fdm_size + 1, - sect_fdm_len); - - len -= sect_fdm_len; - oob += sect_fdm_len; - step++; - } - - return len; -} - -int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - void *buf, void *oob, size_t ooblen, - size_t *actualooblen, bool raw) -{ - int ret, oobremain; - - if (!snf) - return -EINVAL; - - if (!oob) - return mtk_snand_read_page(snf, addr, buf, NULL, raw); - - ret = mtk_snand_read_page(snf, addr, buf, snf->buf_cache, raw); - if (ret && ret != -EBADMSG) { - if (actualooblen) - *actualooblen = 0; - return ret; - } - - oobremain = mtk_snand_transfer_oob(snf, oob, ooblen, snf->buf_cache); - if (actualooblen) - *actualooblen = ooblen - oobremain; - - return ret; -} - -int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - const void *buf, const void *oob, - size_t ooblen, size_t *actualooblen, bool raw) -{ - int oobremain; - - if (!snf) - return -EINVAL; - - if (!oob) - return mtk_snand_write_page(snf, addr, buf, NULL, raw); - - memset(snf->buf_cache, 0xff, snf->oobsize); - oobremain = mtk_snand_fill_oob(snf, snf->buf_cache, oob, ooblen); - if (actualooblen) - *actualooblen = ooblen - oobremain; - - return mtk_snand_write_page(snf, addr, buf, snf->buf_cache, raw); -} - -int mtk_snand_get_chip_info(struct mtk_snand *snf, - struct mtk_snand_chip_info *info) -{ - if (!snf || !info) - return -EINVAL; - - info->model = snf->model; - info->chipsize = snf->size; - info->blocksize = snf->erasesize; - info->pagesize = snf->writesize; - info->sparesize = snf->oobsize; - info->spare_per_sector = snf->spare_per_sector; - info->fdm_size = snf->nfi_soc->fdm_size; - info->fdm_ecc_size = snf->nfi_soc->fdm_ecc_size; - info->num_sectors = snf->ecc_steps; - info->sector_size = snf->nfi_soc->sector_size; - info->ecc_strength = snf->ecc_strength; - info->ecc_bytes = snf->ecc_bytes; - - return 0; -} - -int mtk_snand_irq_process(struct mtk_snand *snf) -{ - uint32_t sta, ien; - - if (!snf) - return -EINVAL; - - sta = nfi_read32(snf, NFI_INTR_STA); - ien = nfi_read32(snf, NFI_INTR_EN); - - if (!(sta & ien)) - return 0; - - nfi_write32(snf, NFI_INTR_EN, 0); - irq_completion_done(snf->pdev); - - return 1; -} - -static int mtk_snand_select_spare_per_sector(struct mtk_snand *snf) -{ - uint32_t spare_per_step = snf->oobsize / snf->ecc_steps; - int i, mul = 1; - - /* - * If we're using the 1KB sector size, HW will automatically - * double the spare size. So we should only use half of the value. - */ - if (snf->nfi_soc->sector_size == 1024) - mul = 2; - - spare_per_step /= mul; - - for (i = snf->nfi_soc->num_spare_size - 1; i >= 0; i--) { - if (snf->nfi_soc->spare_sizes[i] <= spare_per_step) { - snf->spare_per_sector = snf->nfi_soc->spare_sizes[i]; - snf->spare_per_sector *= mul; - return i; - } - } - - snand_log_nfi(snf->pdev, - "Page size %u+%u is not supported\n", snf->writesize, - snf->oobsize); - - return -1; -} - -static int mtk_snand_pagefmt_setup(struct mtk_snand *snf) -{ - uint32_t spare_size_idx, spare_size_shift, pagesize_idx; - uint32_t sector_size_512; - - if (snf->nfi_soc->sector_size == 512) { - sector_size_512 = NFI_SEC_SEL_512; - spare_size_shift = NFI_SPARE_SIZE_S; - } else { - sector_size_512 = 0; - spare_size_shift = NFI_SPARE_SIZE_LS_S; - } - - switch (snf->writesize) { - case SZ_512: - pagesize_idx = NFI_PAGE_SIZE_512_2K; - break; - case SZ_2K: - if (snf->nfi_soc->sector_size == 512) - pagesize_idx = NFI_PAGE_SIZE_2K_4K; - else - pagesize_idx = NFI_PAGE_SIZE_512_2K; - break; - case SZ_4K: - if (snf->nfi_soc->sector_size == 512) - pagesize_idx = NFI_PAGE_SIZE_4K_8K; - else - pagesize_idx = NFI_PAGE_SIZE_2K_4K; - break; - case SZ_8K: - if (snf->nfi_soc->sector_size == 512) - pagesize_idx = NFI_PAGE_SIZE_8K_16K; - else - pagesize_idx = NFI_PAGE_SIZE_4K_8K; - break; - case SZ_16K: - pagesize_idx = NFI_PAGE_SIZE_8K_16K; - break; - default: - snand_log_nfi(snf->pdev, "Page size %u is not supported\n", - snf->writesize); - return -ENOTSUPP; - } - - spare_size_idx = mtk_snand_select_spare_per_sector(snf); - if (unlikely(spare_size_idx < 0)) - return -ENOTSUPP; - - snf->raw_sector_size = snf->nfi_soc->sector_size + - snf->spare_per_sector; - - /* Setup page format */ - nfi_write32(snf, NFI_PAGEFMT, - (snf->nfi_soc->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | - (snf->nfi_soc->fdm_size << NFI_FDM_NUM_S) | - (spare_size_idx << spare_size_shift) | - (pagesize_idx << NFI_PAGE_SIZE_S) | - sector_size_512); - - return 0; -} - -static enum snand_flash_io mtk_snand_select_opcode(struct mtk_snand *snf, - uint32_t snfi_caps, uint8_t *opcode, - uint8_t *dummy, - const struct snand_io_cap *op_cap) -{ - uint32_t i, caps; - - caps = snfi_caps & op_cap->caps; - - i = fls(caps); - if (i > 0) { - *opcode = op_cap->opcodes[i - 1].opcode; - if (dummy) - *dummy = op_cap->opcodes[i - 1].dummy; - return i - 1; - } - - return __SNAND_IO_MAX; -} - -static int mtk_snand_select_opcode_rfc(struct mtk_snand *snf, - uint32_t snfi_caps, - const struct snand_io_cap *op_cap) -{ - enum snand_flash_io idx; - - static const uint8_t rfc_modes[__SNAND_IO_MAX] = { - [SNAND_IO_1_1_1] = DATA_READ_MODE_X1, - [SNAND_IO_1_1_2] = DATA_READ_MODE_X2, - [SNAND_IO_1_2_2] = DATA_READ_MODE_DUAL, - [SNAND_IO_1_1_4] = DATA_READ_MODE_X4, - [SNAND_IO_1_4_4] = DATA_READ_MODE_QUAD, - }; - - idx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_rfc, - &snf->dummy_rfc, op_cap); - if (idx >= __SNAND_IO_MAX) { - snand_log_snfi(snf->pdev, - "No capable opcode for read from cache\n"); - return -ENOTSUPP; - } - - snf->mode_rfc = rfc_modes[idx]; - - if (idx == SNAND_IO_1_1_4 || idx == SNAND_IO_1_4_4) - snf->quad_spi_op = true; - - return 0; -} - -static int mtk_snand_select_opcode_pl(struct mtk_snand *snf, uint32_t snfi_caps, - const struct snand_io_cap *op_cap) -{ - enum snand_flash_io idx; - - static const uint8_t pl_modes[__SNAND_IO_MAX] = { - [SNAND_IO_1_1_1] = 0, - [SNAND_IO_1_1_4] = 1, - }; - - idx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_pl, - NULL, op_cap); - if (idx >= __SNAND_IO_MAX) { - snand_log_snfi(snf->pdev, - "No capable opcode for program load\n"); - return -ENOTSUPP; - } - - snf->mode_pl = pl_modes[idx]; - - if (idx == SNAND_IO_1_1_4) - snf->quad_spi_op = true; - - return 0; -} - -static int mtk_snand_setup(struct mtk_snand *snf, - const struct snand_flash_info *snand_info) -{ - const struct snand_mem_org *memorg = &snand_info->memorg; - uint32_t i, msg_size, snfi_caps; - int ret; - - /* Calculate flash memory organization */ - snf->model = snand_info->model; - snf->writesize = memorg->pagesize; - snf->oobsize = memorg->sparesize; - snf->erasesize = snf->writesize * memorg->pages_per_block; - snf->die_size = (uint64_t)snf->erasesize * memorg->blocks_per_die; - snf->size = snf->die_size * memorg->ndies; - snf->num_dies = memorg->ndies; - - snf->writesize_mask = snf->writesize - 1; - snf->erasesize_mask = snf->erasesize - 1; - snf->die_mask = snf->die_size - 1; - - snf->writesize_shift = ffs(snf->writesize) - 1; - snf->erasesize_shift = ffs(snf->erasesize) - 1; - snf->die_shift = mtk_snand_ffs64(snf->die_size) - 1; - - snf->select_die = snand_info->select_die; - - /* Determine opcodes for read from cache/program load */ - snfi_caps = SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2; - if (snf->snfi_quad_spi) - snfi_caps |= SPI_IO_1_1_4 | SPI_IO_1_4_4; - - ret = mtk_snand_select_opcode_rfc(snf, snfi_caps, snand_info->cap_rd); - if (ret) - return ret; - - ret = mtk_snand_select_opcode_pl(snf, snfi_caps, snand_info->cap_pl); - if (ret) - return ret; - - /* ECC and page format */ - snf->ecc_steps = snf->writesize / snf->nfi_soc->sector_size; - if (snf->ecc_steps > snf->nfi_soc->max_sectors) { - snand_log_nfi(snf->pdev, "Page size %u is not supported\n", - snf->writesize); - return -ENOTSUPP; - } - - ret = mtk_snand_pagefmt_setup(snf); - if (ret) - return ret; - - msg_size = snf->nfi_soc->sector_size + snf->nfi_soc->fdm_ecc_size; - ret = mtk_ecc_setup(snf, snf->nfi_base + NFI_FDM0L, - snf->spare_per_sector - snf->nfi_soc->fdm_size, - msg_size); - if (ret) - return ret; - - nfi_write16(snf, NFI_CNFG, 0); - - /* Tuning options */ - nfi_write16(snf, NFI_DEBUG_CON1, WBUF_EN); - nfi_write32(snf, SNF_DLY_CTL3, (40 << SFCK_SAM_DLY_S)); - - /* Interrupts */ - nfi_read32(snf, NFI_INTR_STA); - nfi_write32(snf, NFI_INTR_EN, 0); - - /* Clear SNF done flag */ - nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE | CUS_PG_DONE); - nfi_write32(snf, SNF_STA_CTL1, 0); - - /* Initialization on all dies */ - for (i = 0; i < snf->num_dies; i++) { - mtk_snand_select_die(snf, i); - - /* Disable On-Die ECC engine */ - ret = mtk_snand_ondie_ecc_control(snf, false); - if (ret) - return ret; - - /* Disable block protection */ - mtk_snand_unlock(snf); - - /* Enable/disable quad-spi */ - mtk_snand_qspi_control(snf, snf->quad_spi_op); - } - - mtk_snand_select_die(snf, 0); - - return 0; -} - -static int mtk_snand_id_probe(struct mtk_snand *snf, - const struct snand_flash_info **snand_info) -{ - uint8_t id[4], op[2]; - int ret; - - /* Read SPI-NAND JEDEC ID, OP + dummy/addr + ID */ - op[0] = SNAND_CMD_READID; - op[1] = 0; - ret = mtk_snand_mac_io(snf, op, 2, id, sizeof(id)); - if (ret) - return ret; - - *snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id); - if (*snand_info) - return 0; - - /* Read SPI-NAND JEDEC ID, OP + ID */ - op[0] = SNAND_CMD_READID; - ret = mtk_snand_mac_io(snf, op, 1, id, sizeof(id)); - if (ret) - return ret; - - *snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id); - if (*snand_info) - return 0; - - snand_log_chip(snf->pdev, - "Unrecognized SPI-NAND ID: %02x %02x %02x %02x\n", - id[0], id[1], id[2], id[3]); - - return -EINVAL; -} - -int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata, - struct mtk_snand **psnf) -{ - const struct snand_flash_info *snand_info; - uint32_t rawpage_size, sect_bf_size; - struct mtk_snand tmpsnf, *snf; - int ret; - - if (!pdata || !psnf) - return -EINVAL; - - if (pdata->soc >= __SNAND_SOC_MAX) { - snand_log_chip(dev, "Invalid SOC %u for MTK-SNAND\n", - pdata->soc); - return -EINVAL; - } - - /* Dummy instance only for initial reset and id probe */ - tmpsnf.nfi_base = pdata->nfi_base; - tmpsnf.ecc_base = pdata->ecc_base; - tmpsnf.soc = pdata->soc; - tmpsnf.nfi_soc = &mtk_snand_socs[pdata->soc]; - tmpsnf.pdev = dev; - - /* Switch to SNFI mode */ - writel(SPI_MODE, tmpsnf.nfi_base + SNF_CFG); - - /* Reset SNFI & NFI */ - mtk_snand_mac_reset(&tmpsnf); - mtk_nfi_reset(&tmpsnf); - - /* Reset SPI-NAND chip */ - ret = mtk_snand_chip_reset(&tmpsnf); - if (ret) { - snand_log_chip(dev, "Failed to reset SPI-NAND chip\n"); - return ret; - } - - /* Probe SPI-NAND flash by JEDEC ID */ - ret = mtk_snand_id_probe(&tmpsnf, &snand_info); - if (ret) - return ret; - - rawpage_size = snand_info->memorg.pagesize + - snand_info->memorg.sparesize; - - sect_bf_size = mtk_snand_socs[pdata->soc].max_sectors * - sizeof(*snf->sect_bf); - - /* Allocate memory for instance and cache */ - snf = generic_mem_alloc(dev, - sizeof(*snf) + rawpage_size + sect_bf_size); - if (!snf) { - snand_log_chip(dev, "Failed to allocate memory for instance\n"); - return -ENOMEM; - } - - snf->sect_bf = (int *)((uintptr_t)snf + sizeof(*snf)); - snf->buf_cache = (uint8_t *)((uintptr_t)snf->sect_bf + sect_bf_size); - - /* Allocate memory for DMA buffer */ - snf->page_cache = dma_mem_alloc(dev, rawpage_size); - if (!snf->page_cache) { - generic_mem_free(dev, snf); - snand_log_chip(dev, - "Failed to allocate memory for DMA buffer\n"); - return -ENOMEM; - } - - /* Fill up instance */ - snf->pdev = dev; - snf->nfi_base = pdata->nfi_base; - snf->ecc_base = pdata->ecc_base; - snf->soc = pdata->soc; - snf->nfi_soc = &mtk_snand_socs[pdata->soc]; - snf->snfi_quad_spi = pdata->quad_spi; - - /* Initialize SNFI & ECC engine */ - ret = mtk_snand_setup(snf, snand_info); - if (ret) { - dma_mem_free(dev, snf->page_cache); - generic_mem_free(dev, snf); - return ret; - } - - *psnf = snf; - - return 0; -} - -int mtk_snand_cleanup(struct mtk_snand *snf) -{ - if (!snf) - return 0; - - dma_mem_free(snf->pdev, snf->page_cache); - generic_mem_free(snf->pdev, snf); - - return 0; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h deleted file mode 100644 index 73c5cc60c9..0000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#ifndef _MTK_SNAND_H_ -#define _MTK_SNAND_H_ - -#ifndef PRIVATE_MTK_SNAND_HEADER -#include -#include -#include -#endif - -enum mtk_snand_soc { - SNAND_SOC_MT7622, - SNAND_SOC_MT7629, - - __SNAND_SOC_MAX -}; - -struct mtk_snand_platdata { - void *nfi_base; - void *ecc_base; - enum mtk_snand_soc soc; - bool quad_spi; -}; - -struct mtk_snand_chip_info { - const char *model; - uint64_t chipsize; - uint32_t blocksize; - uint32_t pagesize; - uint32_t sparesize; - uint32_t spare_per_sector; - uint32_t fdm_size; - uint32_t fdm_ecc_size; - uint32_t num_sectors; - uint32_t sector_size; - uint32_t ecc_strength; - uint32_t ecc_bytes; -}; - -struct mtk_snand; -struct snand_flash_info; - -int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata, - struct mtk_snand **psnf); -int mtk_snand_cleanup(struct mtk_snand *snf); - -int mtk_snand_chip_reset(struct mtk_snand *snf); -int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf, - void *oob, bool raw); -int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf, - const void *oob, bool raw); -int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr); -int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr); -int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr); -int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw, - const uint8_t *oobbuf, size_t ooblen); -int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf, - size_t ooblen, const uint8_t *oobraw); -int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - void *buf, void *oob, size_t ooblen, - size_t *actualooblen, bool raw); -int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - const void *buf, const void *oob, - size_t ooblen, size_t *actualooblen, - bool raw); -int mtk_snand_get_chip_info(struct mtk_snand *snf, - struct mtk_snand_chip_info *info); -int mtk_snand_irq_process(struct mtk_snand *snf); - -#endif /* _MTK_SNAND_H_ */ diff --git a/target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch deleted file mode 100644 index 318c8b2873..0000000000 --- a/target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- a/drivers/mtd/mtk-snand/mtk-snand-mtd.c -+++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -612,6 +613,8 @@ static int mtk_snand_probe(struct platfo - mtd->_block_isbad = mtk_snand_mtd_block_isbad; - mtd->_block_markbad = mtk_snand_mtd_block_markbad; - -+ mtk_bmt_attach(mtd); -+ - ret = mtd_device_register(mtd, NULL, 0); - if (ret) { - dev_err(msm->pdev.dev, "failed to register mtd partition\n"); -@@ -623,6 +626,7 @@ static int mtk_snand_probe(struct platfo - return 0; - - errout4: -+ mtk_bmt_detach(mtd); - devm_kfree(msm->pdev.dev, msm->page_cache); - - errout3: -@@ -650,6 +654,8 @@ static int mtk_snand_remove(struct platf - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); -+ - mtk_snand_cleanup(msm->snf); - - if (msm->irq >= 0) diff --git a/target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch b/target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch deleted file mode 100644 index 149215c113..0000000000 --- a/target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -241,6 +241,8 @@ source "drivers/mtd/ubi/Kconfig" - - source "drivers/mtd/hyperbus/Kconfig" - -+source "drivers/mtd/mtk-snand/Kconfig" -+ - source "drivers/mtd/composite/Kconfig" - - endif # MTD ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -34,5 +34,7 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ - obj-$(CONFIG_MTD_UBI) += ubi/ - obj-$(CONFIG_MTD_HYPERBUS) += hyperbus/ - -+obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/ -+ - # Composite drivers must be loaded last - obj-y += composite/ From 861efe158ac56da2e00637aed704a77994bec54c Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Thu, 7 Apr 2022 10:05:25 +0800 Subject: [PATCH 11/75] mediatek: v5.15: backport spi-mem ecc support Signed-off-by: Chuanhong Guo --- ...-infrastructure-to-support-hardware-.patch | 224 ++++++++++++++++++ ...ew-helper-to-retrieve-the-ECC-contex.patch | 36 +++ ...vide-a-helper-to-retrieve-a-pileline.patch | 80 +++++++ ...mem-Introduce-a-capability-structure.patch | 78 ++++++ ...ck-the-controller-extra-capabilities.patch | 56 +++++ ...l-the-spi_mem_dtr_supports_op-helper.patch | 122 ++++++++++ ...an-ecc-parameter-to-the-spi_mem_op-s.patch | 79 ++++++ ...lay-a-little-bit-the-dirmap-creation.patch | 55 +++++ ...te-direct-mapping-descriptors-for-EC.patch | 105 ++++++++ ...d-nand-fix-ecc-parameters-for-mt7622.patch | 93 ++++++++ 10 files changed, 928 insertions(+) create mode 100644 target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch create mode 100644 target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch create mode 100644 target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch create mode 100644 target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch create mode 100644 target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch create mode 100644 target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch create mode 100644 target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch create mode 100644 target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch create mode 100644 target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch create mode 100644 target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch diff --git a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch new file mode 100644 index 0000000000..b6b069d234 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch @@ -0,0 +1,224 @@ +From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:38 +0100 +Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware + engines + +Add the necessary helpers to register/unregister hardware ECC engines +that will be called from ECC engine drivers. + +Also add helpers to get the right engine from the user +perspective. Keep a reference of the in use ECC engine in order to +prevent modules to be unloaded. Put the reference when the engine gets +retired. + +A static list of hardware (only) ECC engines is setup to keep track of +the registered engines. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com +(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152) +--- + drivers/mtd/nand/core.c | 10 +++-- + drivers/mtd/nand/ecc.c | 88 ++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/nand.h | 28 +++++++++++++ + 3 files changed, 123 insertions(+), 3 deletions(-) + +diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c +index 5e13a03d2b32..b228b4d13b7a 100644 +--- a/drivers/mtd/nand/core.c ++++ b/drivers/mtd/nand/core.c +@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct nand_device *nand) + nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand); + break; + case NAND_ECC_ENGINE_TYPE_ON_HOST: +- pr_err("On-host hardware ECC engines not supported yet\n"); ++ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand); ++ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; + break; + default: + pr_err("Missing ECC engine type\n"); +@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct nand_device *nand) + { + switch (nand->ecc.ctx.conf.engine_type) { + case NAND_ECC_ENGINE_TYPE_ON_HOST: +- pr_err("On-host hardware ECC engines not supported yet\n"); ++ nand_ecc_put_on_host_hw_engine(nand); + break; + case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_SOFT: +@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_device *nand) + /* Look for the ECC engine to use */ + ret = nanddev_get_ecc_engine(nand); + if (ret) { +- pr_err("No ECC engine found\n"); ++ if (ret != -EPROBE_DEFER) ++ pr_err("No ECC engine found\n"); ++ + return ret; + } + +diff --git a/drivers/mtd/nand/ecc.c b/drivers/mtd/nand/ecc.c +index 6c43dfda01d4..078f5ec38de3 100644 +--- a/drivers/mtd/nand/ecc.c ++++ b/drivers/mtd/nand/ecc.c +@@ -96,6 +96,12 @@ + #include + #include + #include ++#include ++#include ++#include ++ ++static LIST_HEAD(on_host_hw_engines); ++static DEFINE_MUTEX(on_host_hw_engines_mutex); + + /** + * nand_ecc_init_ctx - Init the ECC engine context +@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand) + } + EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine); + ++int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine) ++{ ++ struct nand_ecc_engine *item; ++ ++ if (!engine) ++ return -EINVAL; ++ ++ /* Prevent multiple registrations of one engine */ ++ list_for_each_entry(item, &on_host_hw_engines, node) ++ if (item == engine) ++ return 0; ++ ++ mutex_lock(&on_host_hw_engines_mutex); ++ list_add_tail(&engine->node, &on_host_hw_engines); ++ mutex_unlock(&on_host_hw_engines_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine); ++ ++int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine) ++{ ++ if (!engine) ++ return -EINVAL; ++ ++ mutex_lock(&on_host_hw_engines_mutex); ++ list_del(&engine->node); ++ mutex_unlock(&on_host_hw_engines_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine); ++ ++static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev) ++{ ++ struct nand_ecc_engine *item; ++ ++ list_for_each_entry(item, &on_host_hw_engines, node) ++ if (item->dev == dev) ++ return item; ++ ++ return NULL; ++} ++ ++struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand) ++{ ++ struct nand_ecc_engine *engine = NULL; ++ struct device *dev = &nand->mtd.dev; ++ struct platform_device *pdev; ++ struct device_node *np; ++ ++ if (list_empty(&on_host_hw_engines)) ++ return NULL; ++ ++ /* Check for an explicit nand-ecc-engine property */ ++ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0); ++ if (np) { ++ pdev = of_find_device_by_node(np); ++ if (!pdev) ++ return ERR_PTR(-EPROBE_DEFER); ++ ++ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev); ++ platform_device_put(pdev); ++ of_node_put(np); ++ ++ if (!engine) ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ if (engine) ++ get_device(engine->dev); ++ ++ return engine; ++} ++EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine); ++ ++void nand_ecc_put_on_host_hw_engine(struct nand_device *nand) ++{ ++ put_device(nand->ecc.engine->dev); ++} ++EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); ++ + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Miquel Raynal "); + MODULE_DESCRIPTION("Generic ECC engine"); +diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h +index 32fc7edf65b3..4ddd20fe9c9e 100644 +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -263,12 +263,36 @@ struct nand_ecc_engine_ops { + struct nand_page_io_req *req); + }; + ++/** ++ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated ++ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value ++ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly ++ * correction, does not need to copy ++ * data around ++ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the ++ * data into its own area before use ++ */ ++enum nand_ecc_engine_integration { ++ NAND_ECC_ENGINE_INTEGRATION_INVALID, ++ NAND_ECC_ENGINE_INTEGRATION_PIPELINED, ++ NAND_ECC_ENGINE_INTEGRATION_EXTERNAL, ++}; ++ + /** + * struct nand_ecc_engine - ECC engine abstraction for NAND devices ++ * @dev: Host device ++ * @node: Private field for registration time + * @ops: ECC engine operations ++ * @integration: How the engine is integrated with the host ++ * (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines) ++ * @priv: Private data + */ + struct nand_ecc_engine { ++ struct device *dev; ++ struct list_head node; + struct nand_ecc_engine_ops *ops; ++ enum nand_ecc_engine_integration integration; ++ void *priv; + }; + + void of_get_nand_ecc_user_config(struct nand_device *nand); +@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_device *nand, + int nand_ecc_finish_io_req(struct nand_device *nand, + struct nand_page_io_req *req); + bool nand_ecc_is_strong_enough(struct nand_device *nand); ++int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine); ++int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine); + struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand); + struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); ++struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); ++void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); + + #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) + struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch new file mode 100644 index 0000000000..6522507786 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch @@ -0,0 +1,36 @@ +From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:39 +0100 +Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context + +Introduce nand_to_ecc_ctx() which will allow to easily jump to the +private pointer of an ECC context given a NAND device. This is very +handy, from the prepare or finish ECC hook, to get the internal context +out of the NAND device object. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com +(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4) +--- + include/linux/mtd/nand.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h +index 4ddd20fe9c9e..b617efa0a881 100644 +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos); + int nanddev_ecc_engine_init(struct nand_device *nand); + void nanddev_ecc_engine_cleanup(struct nand_device *nand); + ++static inline void *nand_to_ecc_ctx(struct nand_device *nand) ++{ ++ return nand->ecc.ctx.priv; ++} ++ + /* BBT related functions */ + enum nand_bbt_block_status { + NAND_BBT_BLOCK_STATUS_UNKNOWN, +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch new file mode 100644 index 0000000000..ce353a9226 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch @@ -0,0 +1,80 @@ +From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:41 +0100 +Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a + pilelined engine device + +In a pipelined engine situation, we might either have the host which +internally has support for error correction, or have it using an +external hardware block for this purpose. In the former case, the host +is also the ECC engine. In the latter case, it is not. In order to get +the right pointers on the right devices (for example: in order to devm_* +allocate variables), let's introduce this helper which can safely be +called by pipelined ECC engines in order to retrieve the right device +structure. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com +(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309) +--- + drivers/mtd/nand/ecc.c | 31 +++++++++++++++++++++++++++++++ + include/linux/mtd/nand.h | 1 + + 2 files changed, 32 insertions(+) + +diff --git a/drivers/mtd/nand/ecc.c b/drivers/mtd/nand/ecc.c +index 078f5ec38de3..5250764cedee 100644 +--- a/drivers/mtd/nand/ecc.c ++++ b/drivers/mtd/nand/ecc.c +@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(struct nand_device *nand) + } + EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); + ++/* ++ * In the case of a pipelined engine, the device registering the ECC ++ * engine is not necessarily the ECC engine itself but may be a host controller. ++ * It is then useful to provide a helper to retrieve the right device object ++ * which actually represents the ECC engine. ++ */ ++struct device *nand_ecc_get_engine_dev(struct device *host) ++{ ++ struct platform_device *ecc_pdev; ++ struct device_node *np; ++ ++ /* ++ * If the device node contains this property, it means we need to follow ++ * it in order to get the right ECC engine device we are looking for. ++ */ ++ np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0); ++ if (!np) ++ return host; ++ ++ ecc_pdev = of_find_device_by_node(np); ++ if (!ecc_pdev) { ++ of_node_put(np); ++ return NULL; ++ } ++ ++ platform_device_put(ecc_pdev); ++ of_node_put(np); ++ ++ return &ecc_pdev->dev; ++} ++ + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Miquel Raynal "); + MODULE_DESCRIPTION("Generic ECC engine"); +diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h +index b617efa0a881..615b3e3a3920 100644 +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand); + struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); + struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); + void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); ++struct device *nand_ecc_get_engine_dev(struct device *host); + + #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) + struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch new file mode 100644 index 0000000000..bcd2ee8004 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch @@ -0,0 +1,78 @@ +From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:17:56 +0100 +Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure + +Create a spi_controller_mem_caps structure and put it within the +spi_controller structure close to the spi_controller_mem_ops +strucure. So far the only field in this structure is the support for dtr +operations, but soon we will add another parameter. + +Also create a helper to parse the capabilities and check if the +requested capability has been set or not. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Reviewed-by: Mark Brown +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com +(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20) +--- + include/linux/spi/spi-mem.h | 11 +++++++++++ + include/linux/spi/spi.h | 3 +++ + 2 files changed, 14 insertions(+) + +diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h +index 85e2ff7b840d..38e5d45c9842 100644 +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -285,6 +285,17 @@ struct spi_controller_mem_ops { + unsigned long timeout_ms); + }; + ++/** ++ * struct spi_controller_mem_caps - SPI memory controller capabilities ++ * @dtr: Supports DTR operations ++ */ ++struct spi_controller_mem_caps { ++ bool dtr; ++}; ++ ++#define spi_mem_controller_is_capable(ctlr, cap) \ ++ ((ctlr)->mem_caps && (ctlr)->mem_caps->cap) ++ + /** + * struct spi_mem_driver - SPI memory driver + * @spidrv: inherit from a SPI driver +diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h +index 6b0b686f6f90..8ac58b1a2a9f 100644 +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -23,6 +23,7 @@ struct software_node; + struct spi_controller; + struct spi_transfer; + struct spi_controller_mem_ops; ++struct spi_controller_mem_caps; + + /* + * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, +@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch + * @mem_ops: optimized/dedicated operations for interactions with SPI memory. + * This field is optional and should only be implemented if the + * controller has native support for memory like operations. ++ * @mem_caps: controller capabilities for the handling of memory operations. + * @unprepare_message: undo any work done by prepare_message(). + * @slave_abort: abort the ongoing transfer request on an SPI slave controller + * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per +@@ -643,6 +645,7 @@ struct spi_controller { + + /* Optimized handlers for SPI memory-like operations. */ + const struct spi_controller_mem_ops *mem_ops; ++ const struct spi_controller_mem_caps *mem_caps; + + /* gpio chip select */ + int *cs_gpios; +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch new file mode 100644 index 0000000000..20e7bac651 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch @@ -0,0 +1,56 @@ +From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:17:57 +0100 +Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities + +Controllers can now provide a spi-mem capabilities structure. Let's make +use of it in spi_mem_controller_default_supports_op(). As we want to +check for DTR operations as well as normal operations in a single +helper, let's pull the necessary checks from spi_mem_dtr_supports_op() +for now. + +However, because no controller provide these extra capabilities, this +change has no effect so far. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com +(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37) +--- + drivers/spi/spi-mem.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c +index 37f4443ce9a0..86e6597bc3dc 100644 +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) +- return false; ++ struct spi_controller *ctlr = mem->spi->controller; ++ bool op_is_dtr = ++ op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr; + +- if (op->cmd.nbytes != 1) +- return false; ++ if (op_is_dtr) { ++ if (!spi_mem_controller_is_capable(ctlr, dtr)) ++ return false; ++ ++ if (op->cmd.nbytes != 2) ++ return false; ++ } else { ++ if (op->cmd.nbytes != 1) ++ return false; ++ } + + return spi_mem_check_buswidth(mem, op); + } +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch new file mode 100644 index 0000000000..efc0ed526c --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch @@ -0,0 +1,122 @@ +From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:00 +0100 +Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper + +Now that spi_mem_default_supports_op() has access to the static +controller capabilities (relating to memory operations), and now that +these capabilities have been filled by the relevant controllers, there +is no need for a specific helper checking only DTR operations, so let's +just kill spi_mem_dtr_supports_op() and simply use +spi_mem_default_supports_op() instead. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com +(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20) +--- + drivers/spi/spi-cadence-quadspi.c | 5 +---- + drivers/spi/spi-mem.c | 10 ---------- + drivers/spi/spi-mxic.c | 10 +--------- + include/linux/spi/spi-mem.h | 11 ----------- + 4 files changed, 2 insertions(+), 34 deletions(-) + +diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c +index 101cc71bffa7..2c98d6a9a2aa 100644 +--- a/drivers/spi/spi-cadence-quadspi.c ++++ b/drivers/spi/spi-cadence-quadspi.c +@@ -1252,10 +1252,7 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, + if (!(all_true || all_false)) + return false; + +- if (all_true) +- return spi_mem_dtr_supports_op(mem, op); +- else +- return spi_mem_default_supports_op(mem, op); ++ return spi_mem_default_supports_op(mem, op); + } + + static int cqspi_of_get_flash_pdata(struct platform_device *pdev, +diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c +index 86e6597bc3dc..ed966d8129eb 100644 +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem, + return true; + } + +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op) +-{ +- if (op->cmd.nbytes != 2) +- return false; +- +- return spi_mem_check_buswidth(mem, op); +-} +-EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); +- + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c +index 45889947afed..e895df09896a 100644 +--- a/drivers/spi/spi-mxic.c ++++ b/drivers/spi/spi-mxic.c +@@ -335,8 +335,6 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, + static bool mxic_spi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +- bool all_false; +- + if (op->data.buswidth > 8 || op->addr.buswidth > 8 || + op->dummy.buswidth > 8 || op->cmd.buswidth > 8) + return false; +@@ -348,13 +346,7 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem, + if (op->addr.nbytes > 7) + return false; + +- all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && +- !op->data.dtr; +- +- if (all_false) +- return spi_mem_default_supports_op(mem, op); +- else +- return spi_mem_dtr_supports_op(mem, op); ++ return spi_mem_default_supports_op(mem, op); + } + + static int mxic_spi_mem_exec_op(struct spi_mem *mem, +diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h +index 38e5d45c9842..4a1bfe689872 100644 +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, + + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op); +- +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op); +- + #else + static inline int + spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, +@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, + { + return false; + } +- +-static inline +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op) +-{ +- return false; +-} + #endif /* CONFIG_SPI_MEM */ + + int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch new file mode 100644 index 0000000000..fd9e9e2c48 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch @@ -0,0 +1,79 @@ +From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:01 +0100 +Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op + structure + +Soon the SPI-NAND core will need a way to request a SPI controller to +enable ECC support for a given operation. This is because of the +pipelined integration of certain ECC engines, which are directly managed +by the SPI controller itself. + +Introduce a spi_mem_op additional field for this purpose: ecc. + +So far this field is left unset and checked to be false by all +the SPI controller drivers in their ->supports_op() hook, as they all +call spi_mem_default_supports_op(). + +Signed-off-by: Miquel Raynal +Acked-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com +(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7) +--- + drivers/spi/spi-mem.c | 5 +++++ + include/linux/spi/spi-mem.h | 4 ++++ + 2 files changed, 9 insertions(+) + +diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c +index ed966d8129eb..f38ac31961c9 100644 +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, + return false; + } + ++ if (op->data.ecc) { ++ if (!spi_mem_controller_is_capable(ctlr, ecc)) ++ return false; ++ } ++ + return spi_mem_check_buswidth(mem, op); + } + EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); +diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h +index 4a1bfe689872..2ba044d0d5e5 100644 +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -89,6 +89,7 @@ enum spi_mem_data_dir { + * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not + * @data.buswidth: number of IO lanes used to send/receive the data + * @data.dtr: whether the data should be sent in DTR mode or not ++ * @data.ecc: whether error correction is required or not + * @data.dir: direction of the transfer + * @data.nbytes: number of data bytes to send/receive. Can be zero if the + * operation does not involve transferring data +@@ -119,6 +120,7 @@ struct spi_mem_op { + struct { + u8 buswidth; + u8 dtr : 1; ++ u8 ecc : 1; + enum spi_mem_data_dir dir; + unsigned int nbytes; + union { +@@ -288,9 +290,11 @@ struct spi_controller_mem_ops { + /** + * struct spi_controller_mem_caps - SPI memory controller capabilities + * @dtr: Supports DTR operations ++ * @ecc: Supports operations with error correction + */ + struct spi_controller_mem_caps { + bool dtr; ++ bool ecc; + }; + + #define spi_mem_controller_is_capable(ctlr, cap) \ +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch new file mode 100644 index 0000000000..d8c0e1bcd8 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch @@ -0,0 +1,55 @@ +From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:02 +0100 +Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation + +As we will soon tweak the dirmap creation to act a little bit +differently depending on the picked ECC engine, we need to initialize +dirmaps after ECC engines. This should not have any effect as dirmaps +are not yet used at this point. + +Signed-off-by: Miquel Raynal +Reviewed-by: Boris Brezillon +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com +(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949) +--- + drivers/mtd/nand/spi/core.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c +index 2c8685f1f2fa..bb6b026b558b 100644 +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1208,14 +1208,6 @@ static int spinand_init(struct spinand_device *spinand) + if (ret) + goto err_free_bufs; + +- ret = spinand_create_dirmaps(spinand); +- if (ret) { +- dev_err(dev, +- "Failed to create direct mappings for read/write operations (err = %d)\n", +- ret); +- goto err_manuf_cleanup; +- } +- + ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); + if (ret) + goto err_manuf_cleanup; +@@ -1250,6 +1242,14 @@ static int spinand_init(struct spinand_device *spinand) + mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; + mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; + ++ ret = spinand_create_dirmaps(spinand); ++ if (ret) { ++ dev_err(dev, ++ "Failed to create direct mappings for read/write operations (err = %d)\n", ++ ret); ++ goto err_cleanup_ecc_engine; ++ } ++ + return 0; + + err_cleanup_ecc_engine: +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch new file mode 100644 index 0000000000..ee3a6d384f --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch @@ -0,0 +1,105 @@ +From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:03 +0100 +Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC + operations + +In order for pipelined ECC engines to be able to enable/disable the ECC +engine only when needed and avoid races when future parallel-operations +will be supported, we need to provide the information about the use of +the ECC engine in the direct mapping hooks. As direct mapping +configurations are meant to be static, it is best to create two new +mappings: one for regular 'raw' accesses and one for accesses involving +correction. It is up to the driver to use or not the new ECC enable +boolean contained in the spi-mem operation. + +As dirmaps are not free (they consume a few pages of MMIO address space) +and because these extra entries are only meant to be used by pipelined +engines, let's limit their use to this specific type of engine and save +a bit of memory with all the other setups. + +Signed-off-by: Miquel Raynal +Reviewed-by: Boris Brezillon +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com +(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2) +--- + drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++-- + include/linux/mtd/spinand.h | 2 ++ + 2 files changed, 35 insertions(+), 2 deletions(-) + +diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c +index bb6b026b558b..ff8336870bc0 100644 +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand, + } + } + +- rdesc = spinand->dirmaps[req->pos.plane].rdesc; ++ if (req->mode == MTD_OPS_RAW) ++ rdesc = spinand->dirmaps[req->pos.plane].rdesc; ++ else ++ rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; + + while (nbytes) { + ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); +@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand, + req->ooblen); + } + +- wdesc = spinand->dirmaps[req->pos.plane].wdesc; ++ if (req->mode == MTD_OPS_RAW) ++ wdesc = spinand->dirmaps[req->pos.plane].wdesc; ++ else ++ wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; + + while (nbytes) { + ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); +@@ -865,6 +871,31 @@ static int spinand_create_dirmap(struct spinand_device *spinand, + + spinand->dirmaps[plane].rdesc = desc; + ++ if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) { ++ spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc; ++ spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc; ++ ++ return 0; ++ } ++ ++ info.op_tmpl = *spinand->op_templates.update_cache; ++ info.op_tmpl.data.ecc = true; ++ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, ++ spinand->spimem, &info); ++ if (IS_ERR(desc)) ++ return PTR_ERR(desc); ++ ++ spinand->dirmaps[plane].wdesc_ecc = desc; ++ ++ info.op_tmpl = *spinand->op_templates.read_cache; ++ info.op_tmpl.data.ecc = true; ++ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, ++ spinand->spimem, &info); ++ if (IS_ERR(desc)) ++ return PTR_ERR(desc); ++ ++ spinand->dirmaps[plane].rdesc_ecc = desc; ++ + return 0; + } + +diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h +index 6988956b8492..3aa28240a77f 100644 +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -389,6 +389,8 @@ struct spinand_info { + struct spinand_dirmap { + struct spi_mem_dirmap_desc *wdesc; + struct spi_mem_dirmap_desc *rdesc; ++ struct spi_mem_dirmap_desc *wdesc_ecc; ++ struct spi_mem_dirmap_desc *rdesc_ecc; + }; + + /** +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch new file mode 100644 index 0000000000..7dbcf2fcda --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch @@ -0,0 +1,93 @@ +From 41825166744c6e5664281611f5e6d9a2e9333c2b Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Sat, 2 Apr 2022 22:31:20 +0800 +Subject: [PATCH 10/15] mtd: nand: fix ecc parameters for mt7622 + +According to the datasheet, mt7622 only has 5 ECC capabilities instead +of 7, and the decoding error register is arranged as follows: ++------+---------+---------+---------+---------+ +| Bits | 19:15 | 14:10 | 9:5 | 4:0 | ++------+---------+---------+---------+---------+ +| Name | ERRNUM3 | ERRNUM2 | ERRNUM1 | ERRNUM0 | ++------+---------+---------+---------+---------+ +This means err_mask should be 0x1f instead of 0x3f and the number of +bits shifted in mtk_ecc_get_stats should be 5 instead of 8. + +This commit introduces err_shift for the difference in this register +and fix other existing parameters. + +Public MT7622 reference manual can be found on [0] and the info this +commit is based on is from page 656 and page 660. + +[0]: https://wiki.banana-pi.org/Banana_Pi_BPI-R64#Documents + +Fixes: 98dea8d71931 ("mtd: nand: mtk: Support MT7622 NAND flash controller.") +Signed-off-by: Chuanhong Guo +(cherry picked from commit 088b769abd1bd21753002b17b696ae1778b16e8c) +--- + drivers/mtd/nand/raw/mtk_ecc.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/mtd/nand/raw/mtk_ecc.c b/drivers/mtd/nand/raw/mtk_ecc.c +index c437d97debb8..ec9d1fb07006 100644 +--- a/drivers/mtd/nand/raw/mtk_ecc.c ++++ b/drivers/mtd/nand/raw/mtk_ecc.c +@@ -43,6 +43,7 @@ + + struct mtk_ecc_caps { + u32 err_mask; ++ u32 err_shift; + const u8 *ecc_strength; + const u32 *ecc_regs; + u8 num_ecc_strength; +@@ -76,7 +77,7 @@ static const u8 ecc_strength_mt2712[] = { + }; + + static const u8 ecc_strength_mt7622[] = { +- 4, 6, 8, 10, 12, 14, 16 ++ 4, 6, 8, 10, 12 + }; + + enum mtk_ecc_regs { +@@ -221,7 +222,7 @@ void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, + for (i = 0; i < sectors; i++) { + offset = (i >> 2) << 2; + err = readl(ecc->regs + ECC_DECENUM0 + offset); +- err = err >> ((i % 4) * 8); ++ err = err >> ((i % 4) * ecc->caps->err_shift); + err &= ecc->caps->err_mask; + if (err == ecc->caps->err_mask) { + /* uncorrectable errors */ +@@ -449,6 +450,7 @@ EXPORT_SYMBOL(mtk_ecc_get_parity_bits); + + static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { + .err_mask = 0x3f, ++ .err_shift = 8, + .ecc_strength = ecc_strength_mt2701, + .ecc_regs = mt2701_ecc_regs, + .num_ecc_strength = 20, +@@ -459,6 +461,7 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { + + static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { + .err_mask = 0x7f, ++ .err_shift = 8, + .ecc_strength = ecc_strength_mt2712, + .ecc_regs = mt2712_ecc_regs, + .num_ecc_strength = 23, +@@ -468,10 +471,11 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { + }; + + static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { +- .err_mask = 0x3f, ++ .err_mask = 0x1f, ++ .err_shift = 5, + .ecc_strength = ecc_strength_mt7622, + .ecc_regs = mt7622_ecc_regs, +- .num_ecc_strength = 7, ++ .num_ecc_strength = 5, + .ecc_mode_shift = 4, + .parity_bits = 13, + .pg_irq_sel = 0, +-- +2.35.1 + From 2138956bdc3145fac26d2ba8ac966f31d33cd290 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Thu, 7 Apr 2022 10:05:56 +0800 Subject: [PATCH 12/75] mediatek: spi-nand: check for 1 byte BBM only the OOB layout in MTK SNFI uses the 2nd byte, and anything using OOB will make the block a bad-block in spi-nand driver. Hack it for now. We need a proper solution upstream. Signed-off-by: Chuanhong Guo --- .../121-hack-spi-nand-1b-bbm.patch | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch diff --git a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch new file mode 100644 index 0000000000..eccd363395 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch @@ -0,0 +1,20 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -715,7 +715,7 @@ static int spinand_mtd_write(struct mtd_ + static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) + { + struct spinand_device *spinand = nand_to_spinand(nand); +- u8 marker[2] = { }; ++ u8 marker[1] = { }; + struct nand_page_io_req req = { + .pos = *pos, + .ooblen = sizeof(marker), +@@ -726,7 +726,7 @@ static bool spinand_isbad(struct nand_de + + spinand_select_target(spinand, pos->target); + spinand_read_page(spinand, &req); +- if (marker[0] != 0xff || marker[1] != 0xff) ++ if (marker[0] != 0xff) + return true; + + return false; From 68d5efaa10cf0689521fe05e386e3a1e11d8cb29 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Thu, 7 Apr 2022 10:16:47 +0800 Subject: [PATCH 13/75] mediatek: add an upstreamed spi-nand driver This patch implements the spi-nand controller driver as an ECC-capable spi-mem controller to use the upstream SPI-NAND driver. Signed-off-by: Chuanhong Guo --- .../dts/mt7622-elecom-wrc-2533gent.dts | 86 +- .../mediatek/dts/mt7622-linksys-e8450.dtsi | 15 +- target/linux/mediatek/dts/mt7622-rfb1-ubi.dts | 88 +- .../mediatek/dts/mt7622-totolink-a8000ru.dts | 98 +- .../dts/mt7622-xiaomi-redmi-router-ax6s.dts | 157 +- target/linux/mediatek/mt7622/config-5.15 | 4 +- .../115-dts-bpi64-add-snand-support.patch | 61 +- ...nd-make-mtk_ecc.c-a-separated-module.patch | 1383 +++++++++++++++ ...ver-for-MTK-SPI-NAND-Flash-Interface.patch | 1547 +++++++++++++++++ ...-also-parse-nand-ecc-engine-if-avail.patch | 35 + ...dts-mediatek-add-mtk-snfi-for-mt7622.patch | 40 + .../130-dts-mt7629-add-snand-support.patch | 83 +- .../131-dts-mt7622-add-snand-support.patch | 103 +- ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 18 +- .../330-snand-mtk-bmt-support.patch | 34 + .../331-mt7622-rfb1-enable-bmt.patch | 15 +- 16 files changed, 3431 insertions(+), 336 deletions(-) create mode 100644 target/linux/mediatek/patches-5.15/120-11-mtd-nand-make-mtk_ecc.c-a-separated-module.patch create mode 100644 target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch create mode 100644 target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch create mode 100644 target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch create mode 100644 target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch diff --git a/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts b/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts index 867982b061..3e061ef945 100644 --- a/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts +++ b/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts @@ -497,55 +497,65 @@ status = "okay"; }; -&snand { - mediatek,quad-spi; +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "Preloader"; - reg = <0x00000 0x0080000>; - read-only; - }; + partition@0 { + label = "Preloader"; + reg = <0x00000 0x0080000>; + read-only; + }; - partition@80000 { - label = "ATF"; - reg = <0x80000 0x0040000>; - read-only; - }; + partition@80000 { + label = "ATF"; + reg = <0x80000 0x0040000>; + read-only; + }; - partition@c0000 { - label = "uboot"; - reg = <0xc0000 0x0080000>; - read-only; - }; + partition@c0000 { + label = "uboot"; + reg = <0xc0000 0x0080000>; + read-only; + }; - partition@140000 { - label = "uboot-env"; - reg = <0x140000 0x0080000>; - read-only; - }; + partition@140000 { + label = "uboot-env"; + reg = <0x140000 0x0080000>; + read-only; + }; - factory: partition@1c0000 { - label = "factory"; - reg = <0x1c0000 0x0040000>; - read-only; - }; + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x0040000>; + read-only; + }; - partition@200000 { - label = "firmware"; - reg = <0x200000 0x2000000>; - }; + partition@200000 { + label = "firmware"; + reg = <0x200000 0x2000000>; + }; - partition@2200000 { - label = "reserved"; - reg = <0x2200000 0x4000000>; + partition@2200000 { + label = "reserved"; + reg = <0x2200000 0x4000000>; + }; }; }; }; diff --git a/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi b/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi index 047a4a59ef..9f0dabdb4e 100644 --- a/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi +++ b/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi @@ -342,11 +342,22 @@ }; }; -&snand { - mediatek,quad-spi; +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; + + snand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + }; }; &spi0 { diff --git a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts index 1a94446c7a..0f6d9bbc50 100644 --- a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts +++ b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts @@ -6,51 +6,53 @@ compatible = "mediatek,mt7622-rfb1-ubi"; }; -&snand { - mediatek,bmt-v2; - mediatek,bmt-remap-range = <0x0 0x6c0000>; +&snfi { + flash@0 { + mediatek,bmt-v2; + mediatek,bmt-remap-range = <0x0 0x6c0000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "Preloader"; - reg = <0x00000 0x0080000>; - read-only; + partition@0 { + label = "Preloader"; + reg = <0x00000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x80000 0x0040000>; + }; + + partition@c0000 { + label = "Bootloader"; + reg = <0xc0000 0x0080000>; + }; + + partition@140000 { + label = "Config"; + reg = <0x140000 0x0080000>; + }; + + factory: partition@1c0000 { + label = "Factory"; + reg = <0x1c0000 0x0100000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x2c0000 0x400000>; + }; + + partition@6c0000 { + label = "ubi"; + reg = <0x6c0000 0x6f00000>; + }; + + /delete-node/ partition@2200000; }; - - partition@80000 { - label = "ATF"; - reg = <0x80000 0x0040000>; - }; - - partition@c0000 { - label = "Bootloader"; - reg = <0xc0000 0x0080000>; - }; - - partition@140000 { - label = "Config"; - reg = <0x140000 0x0080000>; - }; - - factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x2c0000 0x400000>; - }; - - partition@6c0000 { - label = "ubi"; - reg = <0x6c0000 0x6f00000>; - }; - - /delete-node/ partition@2200000; }; }; diff --git a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts index 0386865cc2..d67fb4efbf 100644 --- a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts +++ b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts @@ -226,62 +226,72 @@ status = "okay"; }; -&snand { - mediatek,quad-spi; +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; - mediatek,bmt-v2; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + mediatek,bmt-v2; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "Preloader"; - reg = <0x0 0x80000>; - read-only; - }; + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; + }; - partition@80000 { - label = "ATF"; - reg = <0x80000 0x40000>; - read-only; - }; + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; - partition@c0000 { - label = "u-boot"; - reg = <0xc0000 0x80000>; - read-only; - }; + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; - partition@140000 { - label = "u-boot-env"; - reg = <0x140000 0x80000>; - read-only; - }; + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x80000>; + read-only; + }; - factory: partition@1c0000 { - label = "factory"; - reg = <0x1c0000 0x40000>; - read-only; - }; + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x40000>; + read-only; + }; - partition@200000 { - label = "ubi"; - reg = <0x200000 0x6400000>; - }; + partition@200000 { + label = "ubi"; + reg = <0x200000 0x6400000>; + }; - partition@6600000 { - label = "User_data"; - reg = <0x6600000 0x100000>; - }; + partition@6600000 { + label = "User_data"; + reg = <0x6600000 0x100000>; + }; - /* size of this partition varies due to BMT & bad blocks. */ - partition@6700000 { - label = "reserved"; - reg = <0x6700000 0>; + /* size of this partition varies due to BMT & bad blocks. */ + partition@6700000 { + label = "reserved"; + reg = <0x6700000 0>; + }; }; }; }; diff --git a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts index 933d2c9275..6c1208d4a8 100644 --- a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts +++ b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts @@ -211,94 +211,105 @@ }; }; -&snand { +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; - mediatek,bmt-v2; - mediatek,bmt-table-size = <0x1000>; - mediatek,bmt-remap-range = <0x0 0x6c0000>; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + mediatek,bmt-v2; + mediatek,bmt-table-size = <0x1000>; + mediatek,bmt-remap-range = <0x0 0x6c0000>; - partition@0 { - label = "Preloader"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "ATF"; - reg = <0x80000 0x40000>; - read-only; - }; - - partition@c0000 { - label = "u-boot"; - reg = <0xc0000 0x80000>; - read-only; - }; - - partition@140000 { - label = "u-boot-env"; - reg = <0x140000 0x40000>; - }; - - partition@180000 { - label = "bdata"; - reg = <0x180000 0x40000>; - }; - - factory: partition@1c0000 { - label = "factory"; - reg = <0x1c0000 0x80000>; - read-only; - - compatible = "nvmem-cells"; + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; }; - }; - partition@240000 { - label = "crash"; - reg = <0x240000 0x40000>; - read-only; - }; + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; - partition@280000 { - label = "crash_log"; - reg = <0x280000 0x40000>; - read-only; - }; + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; - /* Shrunk and renamed from "firmware" - * as to not break luci size checks - */ - partition@2c0000 { - label = "kernel"; - compatible = "denx,fit"; - reg = <0x2c0000 0x400000>; - }; + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x40000>; + }; + partition@180000 { + label = "bdata"; + reg = <0x180000 0x40000>; + }; - /* ubi partition is the result of squashing - * consecutive stock partitions: - * - firmware (partially) - * - firmware1 - * - overlay - * - obr - */ - partition@6c0000 { - label = "ubi"; - reg = <0x6C0000 0x6f00000>; + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x80000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + }; + + partition@240000 { + label = "crash"; + reg = <0x240000 0x40000>; + read-only; + }; + + partition@280000 { + label = "crash_log"; + reg = <0x280000 0x40000>; + read-only; + }; + + /* Shrunk and renamed from "firmware" + * as to not break luci size checks + */ + partition@2c0000 { + label = "kernel"; + compatible = "denx,fit"; + reg = <0x2c0000 0x400000>; + }; + + /* ubi partition is the result of squashing + * consecutive stock partitions: + * - firmware (partially) + * - firmware1 + * - overlay + * - obr + */ + partition@6c0000 { + label = "ubi"; + reg = <0x6C0000 0x6f00000>; + }; }; }; }; diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index 0ed8a854d3..c613fd0dcb 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -247,6 +247,7 @@ CONFIG_MODULES_TREE_LOOKUP=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MTD_NAND_CORE=y CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_MTK=y CONFIG_MTD_NAND_MTK_BMT=y @@ -268,7 +269,6 @@ CONFIG_MTK_INFRACFG=y CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SPI_NAND=y CONFIG_MTK_THERMAL=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set @@ -349,7 +349,6 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y CONFIG_PRINTK_TIME=y CONFIG_PSTORE=y -# CONFIG_PSTORE_BLK is not set CONFIG_PSTORE_COMPRESS=y CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y @@ -411,6 +410,7 @@ CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_MT65XX=y CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y CONFIG_SRCU=y CONFIG_SWCONFIG=y CONFIG_SWIOTLB=y diff --git a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch index 39d81bd5d5..34539a5d10 100644 --- a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch +++ b/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch @@ -1,40 +1,49 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -259,14 +259,32 @@ +@@ -259,14 +259,42 @@ status = "disabled"; }; -&nor_flash { -+&snand { - pinctrl-names = "default"; +- pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; -+ pinctrl-0 = <&serial_nand_pins>; -+ mediatek,quad-spi; ++&bch { + status = "okay"; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; ++}; -- flash@0 { ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; + flash@0 { - compatible = "jedec,spi-nor"; -- reg = <0>; -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; ++ compatible = "spi-nand"; + reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "fip"; ++ reg = <0x80000 0x200000>; ++ read-only; ++ }; ++ ++ partition@280000 { ++ label = "ubi"; ++ reg = <0x280000 0x7d80000>; ++ }; + }; }; }; diff --git a/target/linux/mediatek/patches-5.15/120-11-mtd-nand-make-mtk_ecc.c-a-separated-module.patch b/target/linux/mediatek/patches-5.15/120-11-mtd-nand-make-mtk_ecc.c-a-separated-module.patch new file mode 100644 index 0000000000..fd9098eae9 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-11-mtd-nand-make-mtk_ecc.c-a-separated-module.patch @@ -0,0 +1,1383 @@ +From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 22 Mar 2022 18:44:21 +0800 +Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module + +this code will be used in mediatek snfi spi-mem controller with +pipelined ECC engine. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d) +--- + drivers/mtd/nand/Kconfig | 7 +++++++ + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} | 3 +-- + drivers/mtd/nand/raw/Kconfig | 1 + + drivers/mtd/nand/raw/Makefile | 2 +- + drivers/mtd/nand/raw/mtk_nand.c | 2 +- + .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0 + 7 files changed, 12 insertions(+), 4 deletions(-) + rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%) + rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%) + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT + bool "Support MediaTek NAND Bad-block Management Table" + default n + ++config MTD_NAND_ECC_MEDIATEK ++ tristate "Mediatek hardware ECC engine" ++ depends on HAS_IOMEM ++ select MTD_NAND_ECC ++ help ++ This enables support for the hardware ECC engine from Mediatek. ++ + endmenu + + endmenu +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -3,6 +3,7 @@ + nandcore-objs := core.o bbt.o + obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o + obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o ++obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o + + obj-y += onenand/ + obj-y += raw/ +--- a/drivers/mtd/nand/raw/mtk_ecc.c ++++ /dev/null +@@ -1,599 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * MTK ECC controller driver. +- * Copyright (C) 2016 MediaTek Inc. +- * Authors: Xiaolei Li +- * Jorge Ramirez-Ortiz +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "mtk_ecc.h" +- +-#define ECC_IDLE_MASK BIT(0) +-#define ECC_IRQ_EN BIT(0) +-#define ECC_PG_IRQ_SEL BIT(1) +-#define ECC_OP_ENABLE (1) +-#define ECC_OP_DISABLE (0) +- +-#define ECC_ENCCON (0x00) +-#define ECC_ENCCNFG (0x04) +-#define ECC_MS_SHIFT (16) +-#define ECC_ENCDIADDR (0x08) +-#define ECC_ENCIDLE (0x0C) +-#define ECC_DECCON (0x100) +-#define ECC_DECCNFG (0x104) +-#define DEC_EMPTY_EN BIT(31) +-#define DEC_CNFG_CORRECT (0x3 << 12) +-#define ECC_DECIDLE (0x10C) +-#define ECC_DECENUM0 (0x114) +- +-#define ECC_TIMEOUT (500000) +- +-#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) +-#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) +- +-struct mtk_ecc_caps { +- u32 err_mask; +- u32 err_shift; +- const u8 *ecc_strength; +- const u32 *ecc_regs; +- u8 num_ecc_strength; +- u8 ecc_mode_shift; +- u32 parity_bits; +- int pg_irq_sel; +-}; +- +-struct mtk_ecc { +- struct device *dev; +- const struct mtk_ecc_caps *caps; +- void __iomem *regs; +- struct clk *clk; +- +- struct completion done; +- struct mutex lock; +- u32 sectors; +- +- u8 *eccdata; +-}; +- +-/* ecc strength that each IP supports */ +-static const u8 ecc_strength_mt2701[] = { +- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, +- 40, 44, 48, 52, 56, 60 +-}; +- +-static const u8 ecc_strength_mt2712[] = { +- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, +- 40, 44, 48, 52, 56, 60, 68, 72, 80 +-}; +- +-static const u8 ecc_strength_mt7622[] = { +- 4, 6, 8, 10, 12 +-}; +- +-enum mtk_ecc_regs { +- ECC_ENCPAR00, +- ECC_ENCIRQ_EN, +- ECC_ENCIRQ_STA, +- ECC_DECDONE, +- ECC_DECIRQ_EN, +- ECC_DECIRQ_STA, +-}; +- +-static int mt2701_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x10, +- [ECC_ENCIRQ_EN] = 0x80, +- [ECC_ENCIRQ_STA] = 0x84, +- [ECC_DECDONE] = 0x124, +- [ECC_DECIRQ_EN] = 0x200, +- [ECC_DECIRQ_STA] = 0x204, +-}; +- +-static int mt2712_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x300, +- [ECC_ENCIRQ_EN] = 0x80, +- [ECC_ENCIRQ_STA] = 0x84, +- [ECC_DECDONE] = 0x124, +- [ECC_DECIRQ_EN] = 0x200, +- [ECC_DECIRQ_STA] = 0x204, +-}; +- +-static int mt7622_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x10, +- [ECC_ENCIRQ_EN] = 0x30, +- [ECC_ENCIRQ_STA] = 0x34, +- [ECC_DECDONE] = 0x11c, +- [ECC_DECIRQ_EN] = 0x140, +- [ECC_DECIRQ_STA] = 0x144, +-}; +- +-static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, +- enum mtk_ecc_operation op) +-{ +- struct device *dev = ecc->dev; +- u32 val; +- int ret; +- +- ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, +- val & ECC_IDLE_MASK, +- 10, ECC_TIMEOUT); +- if (ret) +- dev_warn(dev, "%s NOT idle\n", +- op == ECC_ENCODE ? "encoder" : "decoder"); +-} +- +-static irqreturn_t mtk_ecc_irq(int irq, void *id) +-{ +- struct mtk_ecc *ecc = id; +- u32 dec, enc; +- +- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) +- & ECC_IRQ_EN; +- if (dec) { +- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); +- if (dec & ecc->sectors) { +- /* +- * Clear decode IRQ status once again to ensure that +- * there will be no extra IRQ. +- */ +- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); +- ecc->sectors = 0; +- complete(&ecc->done); +- } else { +- return IRQ_HANDLED; +- } +- } else { +- enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) +- & ECC_IRQ_EN; +- if (enc) +- complete(&ecc->done); +- else +- return IRQ_NONE; +- } +- +- return IRQ_HANDLED; +-} +- +-static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) +-{ +- u32 ecc_bit, dec_sz, enc_sz; +- u32 reg, i; +- +- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { +- if (ecc->caps->ecc_strength[i] == config->strength) +- break; +- } +- +- if (i == ecc->caps->num_ecc_strength) { +- dev_err(ecc->dev, "invalid ecc strength %d\n", +- config->strength); +- return -EINVAL; +- } +- +- ecc_bit = i; +- +- if (config->op == ECC_ENCODE) { +- /* configure ECC encoder (in bits) */ +- enc_sz = config->len << 3; +- +- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); +- reg |= (enc_sz << ECC_MS_SHIFT); +- writel(reg, ecc->regs + ECC_ENCCNFG); +- +- if (config->mode != ECC_NFI_MODE) +- writel(lower_32_bits(config->addr), +- ecc->regs + ECC_ENCDIADDR); +- +- } else { +- /* configure ECC decoder (in bits) */ +- dec_sz = (config->len << 3) + +- config->strength * ecc->caps->parity_bits; +- +- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); +- reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; +- reg |= DEC_EMPTY_EN; +- writel(reg, ecc->regs + ECC_DECCNFG); +- +- if (config->sectors) +- ecc->sectors = 1 << (config->sectors - 1); +- } +- +- return 0; +-} +- +-void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, +- int sectors) +-{ +- u32 offset, i, err; +- u32 bitflips = 0; +- +- stats->corrected = 0; +- stats->failed = 0; +- +- for (i = 0; i < sectors; i++) { +- offset = (i >> 2) << 2; +- err = readl(ecc->regs + ECC_DECENUM0 + offset); +- err = err >> ((i % 4) * ecc->caps->err_shift); +- err &= ecc->caps->err_mask; +- if (err == ecc->caps->err_mask) { +- /* uncorrectable errors */ +- stats->failed++; +- continue; +- } +- +- stats->corrected += err; +- bitflips = max_t(u32, bitflips, err); +- } +- +- stats->bitflips = bitflips; +-} +-EXPORT_SYMBOL(mtk_ecc_get_stats); +- +-void mtk_ecc_release(struct mtk_ecc *ecc) +-{ +- clk_disable_unprepare(ecc->clk); +- put_device(ecc->dev); +-} +-EXPORT_SYMBOL(mtk_ecc_release); +- +-static void mtk_ecc_hw_init(struct mtk_ecc *ecc) +-{ +- mtk_ecc_wait_idle(ecc, ECC_ENCODE); +- writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); +- +- mtk_ecc_wait_idle(ecc, ECC_DECODE); +- writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); +-} +- +-static struct mtk_ecc *mtk_ecc_get(struct device_node *np) +-{ +- struct platform_device *pdev; +- struct mtk_ecc *ecc; +- +- pdev = of_find_device_by_node(np); +- if (!pdev) +- return ERR_PTR(-EPROBE_DEFER); +- +- ecc = platform_get_drvdata(pdev); +- if (!ecc) { +- put_device(&pdev->dev); +- return ERR_PTR(-EPROBE_DEFER); +- } +- +- clk_prepare_enable(ecc->clk); +- mtk_ecc_hw_init(ecc); +- +- return ecc; +-} +- +-struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) +-{ +- struct mtk_ecc *ecc = NULL; +- struct device_node *np; +- +- np = of_parse_phandle(of_node, "ecc-engine", 0); +- if (np) { +- ecc = mtk_ecc_get(np); +- of_node_put(np); +- } +- +- return ecc; +-} +-EXPORT_SYMBOL(of_mtk_ecc_get); +- +-int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) +-{ +- enum mtk_ecc_operation op = config->op; +- u16 reg_val; +- int ret; +- +- ret = mutex_lock_interruptible(&ecc->lock); +- if (ret) { +- dev_err(ecc->dev, "interrupted when attempting to lock\n"); +- return ret; +- } +- +- mtk_ecc_wait_idle(ecc, op); +- +- ret = mtk_ecc_config(ecc, config); +- if (ret) { +- mutex_unlock(&ecc->lock); +- return ret; +- } +- +- if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { +- init_completion(&ecc->done); +- reg_val = ECC_IRQ_EN; +- /* +- * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it +- * means this chip can only generate one ecc irq during page +- * read / write. If is 0, generate one ecc irq each ecc step. +- */ +- if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) +- reg_val |= ECC_PG_IRQ_SEL; +- if (op == ECC_ENCODE) +- writew(reg_val, ecc->regs + +- ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); +- else +- writew(reg_val, ecc->regs + +- ecc->caps->ecc_regs[ECC_DECIRQ_EN]); +- } +- +- writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); +- +- return 0; +-} +-EXPORT_SYMBOL(mtk_ecc_enable); +- +-void mtk_ecc_disable(struct mtk_ecc *ecc) +-{ +- enum mtk_ecc_operation op = ECC_ENCODE; +- +- /* find out the running operation */ +- if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) +- op = ECC_DECODE; +- +- /* disable it */ +- mtk_ecc_wait_idle(ecc, op); +- if (op == ECC_DECODE) { +- /* +- * Clear decode IRQ status in case there is a timeout to wait +- * decode IRQ. +- */ +- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); +- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); +- } else { +- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); +- } +- +- writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); +- +- mutex_unlock(&ecc->lock); +-} +-EXPORT_SYMBOL(mtk_ecc_disable); +- +-int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) +-{ +- int ret; +- +- ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); +- if (!ret) { +- dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", +- (op == ECC_ENCODE) ? "encoder" : "decoder"); +- return -ETIMEDOUT; +- } +- +- return 0; +-} +-EXPORT_SYMBOL(mtk_ecc_wait_done); +- +-int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, +- u8 *data, u32 bytes) +-{ +- dma_addr_t addr; +- u32 len; +- int ret; +- +- addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); +- ret = dma_mapping_error(ecc->dev, addr); +- if (ret) { +- dev_err(ecc->dev, "dma mapping error\n"); +- return -EINVAL; +- } +- +- config->op = ECC_ENCODE; +- config->addr = addr; +- ret = mtk_ecc_enable(ecc, config); +- if (ret) { +- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); +- return ret; +- } +- +- ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); +- if (ret) +- goto timeout; +- +- mtk_ecc_wait_idle(ecc, ECC_ENCODE); +- +- /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ +- len = (config->strength * ecc->caps->parity_bits + 7) >> 3; +- +- /* write the parity bytes generated by the ECC back to temp buffer */ +- __ioread32_copy(ecc->eccdata, +- ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], +- round_up(len, 4)); +- +- /* copy into possibly unaligned OOB region with actual length */ +- memcpy(data + bytes, ecc->eccdata, len); +-timeout: +- +- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); +- mtk_ecc_disable(ecc); +- +- return ret; +-} +-EXPORT_SYMBOL(mtk_ecc_encode); +- +-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) +-{ +- const u8 *ecc_strength = ecc->caps->ecc_strength; +- int i; +- +- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { +- if (*p <= ecc_strength[i]) { +- if (!i) +- *p = ecc_strength[i]; +- else if (*p != ecc_strength[i]) +- *p = ecc_strength[i - 1]; +- return; +- } +- } +- +- *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; +-} +-EXPORT_SYMBOL(mtk_ecc_adjust_strength); +- +-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) +-{ +- return ecc->caps->parity_bits; +-} +-EXPORT_SYMBOL(mtk_ecc_get_parity_bits); +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { +- .err_mask = 0x3f, +- .err_shift = 8, +- .ecc_strength = ecc_strength_mt2701, +- .ecc_regs = mt2701_ecc_regs, +- .num_ecc_strength = 20, +- .ecc_mode_shift = 5, +- .parity_bits = 14, +- .pg_irq_sel = 0, +-}; +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { +- .err_mask = 0x7f, +- .err_shift = 8, +- .ecc_strength = ecc_strength_mt2712, +- .ecc_regs = mt2712_ecc_regs, +- .num_ecc_strength = 23, +- .ecc_mode_shift = 5, +- .parity_bits = 14, +- .pg_irq_sel = 1, +-}; +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { +- .err_mask = 0x1f, +- .err_shift = 5, +- .ecc_strength = ecc_strength_mt7622, +- .ecc_regs = mt7622_ecc_regs, +- .num_ecc_strength = 5, +- .ecc_mode_shift = 4, +- .parity_bits = 13, +- .pg_irq_sel = 0, +-}; +- +-static const struct of_device_id mtk_ecc_dt_match[] = { +- { +- .compatible = "mediatek,mt2701-ecc", +- .data = &mtk_ecc_caps_mt2701, +- }, { +- .compatible = "mediatek,mt2712-ecc", +- .data = &mtk_ecc_caps_mt2712, +- }, { +- .compatible = "mediatek,mt7622-ecc", +- .data = &mtk_ecc_caps_mt7622, +- }, +- {}, +-}; +- +-static int mtk_ecc_probe(struct platform_device *pdev) +-{ +- struct device *dev = &pdev->dev; +- struct mtk_ecc *ecc; +- struct resource *res; +- u32 max_eccdata_size; +- int irq, ret; +- +- ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); +- if (!ecc) +- return -ENOMEM; +- +- ecc->caps = of_device_get_match_data(dev); +- +- max_eccdata_size = ecc->caps->num_ecc_strength - 1; +- max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; +- max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; +- max_eccdata_size = round_up(max_eccdata_size, 4); +- ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); +- if (!ecc->eccdata) +- return -ENOMEM; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- ecc->regs = devm_ioremap_resource(dev, res); +- if (IS_ERR(ecc->regs)) +- return PTR_ERR(ecc->regs); +- +- ecc->clk = devm_clk_get(dev, NULL); +- if (IS_ERR(ecc->clk)) { +- dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); +- return PTR_ERR(ecc->clk); +- } +- +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) +- return irq; +- +- ret = dma_set_mask(dev, DMA_BIT_MASK(32)); +- if (ret) { +- dev_err(dev, "failed to set DMA mask\n"); +- return ret; +- } +- +- ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); +- if (ret) { +- dev_err(dev, "failed to request irq\n"); +- return -EINVAL; +- } +- +- ecc->dev = dev; +- mutex_init(&ecc->lock); +- platform_set_drvdata(pdev, ecc); +- dev_info(dev, "probed\n"); +- +- return 0; +-} +- +-#ifdef CONFIG_PM_SLEEP +-static int mtk_ecc_suspend(struct device *dev) +-{ +- struct mtk_ecc *ecc = dev_get_drvdata(dev); +- +- clk_disable_unprepare(ecc->clk); +- +- return 0; +-} +- +-static int mtk_ecc_resume(struct device *dev) +-{ +- struct mtk_ecc *ecc = dev_get_drvdata(dev); +- int ret; +- +- ret = clk_prepare_enable(ecc->clk); +- if (ret) { +- dev_err(dev, "failed to enable clk\n"); +- return ret; +- } +- +- return 0; +-} +- +-static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); +-#endif +- +-MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); +- +-static struct platform_driver mtk_ecc_driver = { +- .probe = mtk_ecc_probe, +- .driver = { +- .name = "mtk-ecc", +- .of_match_table = of_match_ptr(mtk_ecc_dt_match), +-#ifdef CONFIG_PM_SLEEP +- .pm = &mtk_ecc_pm_ops, +-#endif +- }, +-}; +- +-module_platform_driver(mtk_ecc_driver); +- +-MODULE_AUTHOR("Xiaolei Li "); +-MODULE_DESCRIPTION("MTK Nand ECC Driver"); +-MODULE_LICENSE("Dual MIT/GPL"); +--- /dev/null ++++ b/drivers/mtd/nand/ecc-mtk.c +@@ -0,0 +1,598 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * MTK ECC controller driver. ++ * Copyright (C) 2016 MediaTek Inc. ++ * Authors: Xiaolei Li ++ * Jorge Ramirez-Ortiz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define ECC_IDLE_MASK BIT(0) ++#define ECC_IRQ_EN BIT(0) ++#define ECC_PG_IRQ_SEL BIT(1) ++#define ECC_OP_ENABLE (1) ++#define ECC_OP_DISABLE (0) ++ ++#define ECC_ENCCON (0x00) ++#define ECC_ENCCNFG (0x04) ++#define ECC_MS_SHIFT (16) ++#define ECC_ENCDIADDR (0x08) ++#define ECC_ENCIDLE (0x0C) ++#define ECC_DECCON (0x100) ++#define ECC_DECCNFG (0x104) ++#define DEC_EMPTY_EN BIT(31) ++#define DEC_CNFG_CORRECT (0x3 << 12) ++#define ECC_DECIDLE (0x10C) ++#define ECC_DECENUM0 (0x114) ++ ++#define ECC_TIMEOUT (500000) ++ ++#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) ++#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) ++ ++struct mtk_ecc_caps { ++ u32 err_mask; ++ u32 err_shift; ++ const u8 *ecc_strength; ++ const u32 *ecc_regs; ++ u8 num_ecc_strength; ++ u8 ecc_mode_shift; ++ u32 parity_bits; ++ int pg_irq_sel; ++}; ++ ++struct mtk_ecc { ++ struct device *dev; ++ const struct mtk_ecc_caps *caps; ++ void __iomem *regs; ++ struct clk *clk; ++ ++ struct completion done; ++ struct mutex lock; ++ u32 sectors; ++ ++ u8 *eccdata; ++}; ++ ++/* ecc strength that each IP supports */ ++static const u8 ecc_strength_mt2701[] = { ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, ++ 40, 44, 48, 52, 56, 60 ++}; ++ ++static const u8 ecc_strength_mt2712[] = { ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, ++ 40, 44, 48, 52, 56, 60, 68, 72, 80 ++}; ++ ++static const u8 ecc_strength_mt7622[] = { ++ 4, 6, 8, 10, 12 ++}; ++ ++enum mtk_ecc_regs { ++ ECC_ENCPAR00, ++ ECC_ENCIRQ_EN, ++ ECC_ENCIRQ_STA, ++ ECC_DECDONE, ++ ECC_DECIRQ_EN, ++ ECC_DECIRQ_STA, ++}; ++ ++static int mt2701_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ ++static int mt2712_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x300, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ ++static int mt7622_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x30, ++ [ECC_ENCIRQ_STA] = 0x34, ++ [ECC_DECDONE] = 0x11c, ++ [ECC_DECIRQ_EN] = 0x140, ++ [ECC_DECIRQ_STA] = 0x144, ++}; ++ ++static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, ++ enum mtk_ecc_operation op) ++{ ++ struct device *dev = ecc->dev; ++ u32 val; ++ int ret; ++ ++ ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, ++ val & ECC_IDLE_MASK, ++ 10, ECC_TIMEOUT); ++ if (ret) ++ dev_warn(dev, "%s NOT idle\n", ++ op == ECC_ENCODE ? "encoder" : "decoder"); ++} ++ ++static irqreturn_t mtk_ecc_irq(int irq, void *id) ++{ ++ struct mtk_ecc *ecc = id; ++ u32 dec, enc; ++ ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) ++ & ECC_IRQ_EN; ++ if (dec) { ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); ++ if (dec & ecc->sectors) { ++ /* ++ * Clear decode IRQ status once again to ensure that ++ * there will be no extra IRQ. ++ */ ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); ++ ecc->sectors = 0; ++ complete(&ecc->done); ++ } else { ++ return IRQ_HANDLED; ++ } ++ } else { ++ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) ++ & ECC_IRQ_EN; ++ if (enc) ++ complete(&ecc->done); ++ else ++ return IRQ_NONE; ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) ++{ ++ u32 ecc_bit, dec_sz, enc_sz; ++ u32 reg, i; ++ ++ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { ++ if (ecc->caps->ecc_strength[i] == config->strength) ++ break; ++ } ++ ++ if (i == ecc->caps->num_ecc_strength) { ++ dev_err(ecc->dev, "invalid ecc strength %d\n", ++ config->strength); ++ return -EINVAL; ++ } ++ ++ ecc_bit = i; ++ ++ if (config->op == ECC_ENCODE) { ++ /* configure ECC encoder (in bits) */ ++ enc_sz = config->len << 3; ++ ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); ++ reg |= (enc_sz << ECC_MS_SHIFT); ++ writel(reg, ecc->regs + ECC_ENCCNFG); ++ ++ if (config->mode != ECC_NFI_MODE) ++ writel(lower_32_bits(config->addr), ++ ecc->regs + ECC_ENCDIADDR); ++ ++ } else { ++ /* configure ECC decoder (in bits) */ ++ dec_sz = (config->len << 3) + ++ config->strength * ecc->caps->parity_bits; ++ ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); ++ reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; ++ reg |= DEC_EMPTY_EN; ++ writel(reg, ecc->regs + ECC_DECCNFG); ++ ++ if (config->sectors) ++ ecc->sectors = 1 << (config->sectors - 1); ++ } ++ ++ return 0; ++} ++ ++void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, ++ int sectors) ++{ ++ u32 offset, i, err; ++ u32 bitflips = 0; ++ ++ stats->corrected = 0; ++ stats->failed = 0; ++ ++ for (i = 0; i < sectors; i++) { ++ offset = (i >> 2) << 2; ++ err = readl(ecc->regs + ECC_DECENUM0 + offset); ++ err = err >> ((i % 4) * ecc->caps->err_shift); ++ err &= ecc->caps->err_mask; ++ if (err == ecc->caps->err_mask) { ++ /* uncorrectable errors */ ++ stats->failed++; ++ continue; ++ } ++ ++ stats->corrected += err; ++ bitflips = max_t(u32, bitflips, err); ++ } ++ ++ stats->bitflips = bitflips; ++} ++EXPORT_SYMBOL(mtk_ecc_get_stats); ++ ++void mtk_ecc_release(struct mtk_ecc *ecc) ++{ ++ clk_disable_unprepare(ecc->clk); ++ put_device(ecc->dev); ++} ++EXPORT_SYMBOL(mtk_ecc_release); ++ ++static void mtk_ecc_hw_init(struct mtk_ecc *ecc) ++{ ++ mtk_ecc_wait_idle(ecc, ECC_ENCODE); ++ writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); ++ ++ mtk_ecc_wait_idle(ecc, ECC_DECODE); ++ writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); ++} ++ ++static struct mtk_ecc *mtk_ecc_get(struct device_node *np) ++{ ++ struct platform_device *pdev; ++ struct mtk_ecc *ecc; ++ ++ pdev = of_find_device_by_node(np); ++ if (!pdev) ++ return ERR_PTR(-EPROBE_DEFER); ++ ++ ecc = platform_get_drvdata(pdev); ++ if (!ecc) { ++ put_device(&pdev->dev); ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ clk_prepare_enable(ecc->clk); ++ mtk_ecc_hw_init(ecc); ++ ++ return ecc; ++} ++ ++struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) ++{ ++ struct mtk_ecc *ecc = NULL; ++ struct device_node *np; ++ ++ np = of_parse_phandle(of_node, "ecc-engine", 0); ++ if (np) { ++ ecc = mtk_ecc_get(np); ++ of_node_put(np); ++ } ++ ++ return ecc; ++} ++EXPORT_SYMBOL(of_mtk_ecc_get); ++ ++int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) ++{ ++ enum mtk_ecc_operation op = config->op; ++ u16 reg_val; ++ int ret; ++ ++ ret = mutex_lock_interruptible(&ecc->lock); ++ if (ret) { ++ dev_err(ecc->dev, "interrupted when attempting to lock\n"); ++ return ret; ++ } ++ ++ mtk_ecc_wait_idle(ecc, op); ++ ++ ret = mtk_ecc_config(ecc, config); ++ if (ret) { ++ mutex_unlock(&ecc->lock); ++ return ret; ++ } ++ ++ if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { ++ init_completion(&ecc->done); ++ reg_val = ECC_IRQ_EN; ++ /* ++ * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it ++ * means this chip can only generate one ecc irq during page ++ * read / write. If is 0, generate one ecc irq each ecc step. ++ */ ++ if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) ++ reg_val |= ECC_PG_IRQ_SEL; ++ if (op == ECC_ENCODE) ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ else ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_DECIRQ_EN]); ++ } ++ ++ writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(mtk_ecc_enable); ++ ++void mtk_ecc_disable(struct mtk_ecc *ecc) ++{ ++ enum mtk_ecc_operation op = ECC_ENCODE; ++ ++ /* find out the running operation */ ++ if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) ++ op = ECC_DECODE; ++ ++ /* disable it */ ++ mtk_ecc_wait_idle(ecc, op); ++ if (op == ECC_DECODE) { ++ /* ++ * Clear decode IRQ status in case there is a timeout to wait ++ * decode IRQ. ++ */ ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); ++ } else { ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ } ++ ++ writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); ++ ++ mutex_unlock(&ecc->lock); ++} ++EXPORT_SYMBOL(mtk_ecc_disable); ++ ++int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) ++{ ++ int ret; ++ ++ ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); ++ if (!ret) { ++ dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", ++ (op == ECC_ENCODE) ? "encoder" : "decoder"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(mtk_ecc_wait_done); ++ ++int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, ++ u8 *data, u32 bytes) ++{ ++ dma_addr_t addr; ++ u32 len; ++ int ret; ++ ++ addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); ++ ret = dma_mapping_error(ecc->dev, addr); ++ if (ret) { ++ dev_err(ecc->dev, "dma mapping error\n"); ++ return -EINVAL; ++ } ++ ++ config->op = ECC_ENCODE; ++ config->addr = addr; ++ ret = mtk_ecc_enable(ecc, config); ++ if (ret) { ++ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); ++ return ret; ++ } ++ ++ ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); ++ if (ret) ++ goto timeout; ++ ++ mtk_ecc_wait_idle(ecc, ECC_ENCODE); ++ ++ /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ ++ len = (config->strength * ecc->caps->parity_bits + 7) >> 3; ++ ++ /* write the parity bytes generated by the ECC back to temp buffer */ ++ __ioread32_copy(ecc->eccdata, ++ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], ++ round_up(len, 4)); ++ ++ /* copy into possibly unaligned OOB region with actual length */ ++ memcpy(data + bytes, ecc->eccdata, len); ++timeout: ++ ++ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); ++ mtk_ecc_disable(ecc); ++ ++ return ret; ++} ++EXPORT_SYMBOL(mtk_ecc_encode); ++ ++void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) ++{ ++ const u8 *ecc_strength = ecc->caps->ecc_strength; ++ int i; ++ ++ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { ++ if (*p <= ecc_strength[i]) { ++ if (!i) ++ *p = ecc_strength[i]; ++ else if (*p != ecc_strength[i]) ++ *p = ecc_strength[i - 1]; ++ return; ++ } ++ } ++ ++ *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; ++} ++EXPORT_SYMBOL(mtk_ecc_adjust_strength); ++ ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) ++{ ++ return ecc->caps->parity_bits; ++} ++EXPORT_SYMBOL(mtk_ecc_get_parity_bits); ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { ++ .err_mask = 0x3f, ++ .err_shift = 8, ++ .ecc_strength = ecc_strength_mt2701, ++ .ecc_regs = mt2701_ecc_regs, ++ .num_ecc_strength = 20, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, ++ .pg_irq_sel = 0, ++}; ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { ++ .err_mask = 0x7f, ++ .err_shift = 8, ++ .ecc_strength = ecc_strength_mt2712, ++ .ecc_regs = mt2712_ecc_regs, ++ .num_ecc_strength = 23, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, ++ .pg_irq_sel = 1, ++}; ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { ++ .err_mask = 0x1f, ++ .err_shift = 5, ++ .ecc_strength = ecc_strength_mt7622, ++ .ecc_regs = mt7622_ecc_regs, ++ .num_ecc_strength = 5, ++ .ecc_mode_shift = 4, ++ .parity_bits = 13, ++ .pg_irq_sel = 0, ++}; ++ ++static const struct of_device_id mtk_ecc_dt_match[] = { ++ { ++ .compatible = "mediatek,mt2701-ecc", ++ .data = &mtk_ecc_caps_mt2701, ++ }, { ++ .compatible = "mediatek,mt2712-ecc", ++ .data = &mtk_ecc_caps_mt2712, ++ }, { ++ .compatible = "mediatek,mt7622-ecc", ++ .data = &mtk_ecc_caps_mt7622, ++ }, ++ {}, ++}; ++ ++static int mtk_ecc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct mtk_ecc *ecc; ++ struct resource *res; ++ u32 max_eccdata_size; ++ int irq, ret; ++ ++ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); ++ if (!ecc) ++ return -ENOMEM; ++ ++ ecc->caps = of_device_get_match_data(dev); ++ ++ max_eccdata_size = ecc->caps->num_ecc_strength - 1; ++ max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; ++ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; ++ max_eccdata_size = round_up(max_eccdata_size, 4); ++ ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); ++ if (!ecc->eccdata) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ecc->regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ecc->regs)) ++ return PTR_ERR(ecc->regs); ++ ++ ecc->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(ecc->clk)) { ++ dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); ++ return PTR_ERR(ecc->clk); ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = dma_set_mask(dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(dev, "failed to set DMA mask\n"); ++ return ret; ++ } ++ ++ ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); ++ if (ret) { ++ dev_err(dev, "failed to request irq\n"); ++ return -EINVAL; ++ } ++ ++ ecc->dev = dev; ++ mutex_init(&ecc->lock); ++ platform_set_drvdata(pdev, ecc); ++ dev_info(dev, "probed\n"); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mtk_ecc_suspend(struct device *dev) ++{ ++ struct mtk_ecc *ecc = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(ecc->clk); ++ ++ return 0; ++} ++ ++static int mtk_ecc_resume(struct device *dev) ++{ ++ struct mtk_ecc *ecc = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_prepare_enable(ecc->clk); ++ if (ret) { ++ dev_err(dev, "failed to enable clk\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); ++#endif ++ ++MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); ++ ++static struct platform_driver mtk_ecc_driver = { ++ .probe = mtk_ecc_probe, ++ .driver = { ++ .name = "mtk-ecc", ++ .of_match_table = of_match_ptr(mtk_ecc_dt_match), ++#ifdef CONFIG_PM_SLEEP ++ .pm = &mtk_ecc_pm_ops, ++#endif ++ }, ++}; ++ ++module_platform_driver(mtk_ecc_driver); ++ ++MODULE_AUTHOR("Xiaolei Li "); ++MODULE_DESCRIPTION("MTK Nand ECC Driver"); ++MODULE_LICENSE("Dual MIT/GPL"); +--- a/drivers/mtd/nand/raw/Kconfig ++++ b/drivers/mtd/nand/raw/Kconfig +@@ -360,6 +360,7 @@ config MTD_NAND_QCOM + + config MTD_NAND_MTK + tristate "MTK NAND controller" ++ depends on MTD_NAND_ECC_MEDIATEK + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on HAS_IOMEM + help +--- a/drivers/mtd/nand/raw/Makefile ++++ b/drivers/mtd/nand/raw/Makefile +@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n + obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o + obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ + obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o +-obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o ++obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o + obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o + obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o + obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o +--- a/drivers/mtd/nand/raw/mtk_nand.c ++++ b/drivers/mtd/nand/raw/mtk_nand.c +@@ -17,7 +17,7 @@ + #include + #include + #include +-#include "mtk_ecc.h" ++#include + + /* NAND controller register definition */ + #define NFI_CNFG (0x00) +--- a/drivers/mtd/nand/raw/mtk_ecc.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +-/* +- * MTK SDG1 ECC controller +- * +- * Copyright (c) 2016 Mediatek +- * Authors: Xiaolei Li +- * Jorge Ramirez-Ortiz +- */ +- +-#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ +-#define __DRIVERS_MTD_NAND_MTK_ECC_H__ +- +-#include +- +-enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; +-enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; +- +-struct device_node; +-struct mtk_ecc; +- +-struct mtk_ecc_stats { +- u32 corrected; +- u32 bitflips; +- u32 failed; +-}; +- +-struct mtk_ecc_config { +- enum mtk_ecc_operation op; +- enum mtk_ecc_mode mode; +- dma_addr_t addr; +- u32 strength; +- u32 sectors; +- u32 len; +-}; +- +-int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); +-void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); +-int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); +-int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); +-void mtk_ecc_disable(struct mtk_ecc *); +-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); +-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); +- +-struct mtk_ecc *of_mtk_ecc_get(struct device_node *); +-void mtk_ecc_release(struct mtk_ecc *); +- +-#endif +--- /dev/null ++++ b/include/linux/mtd/nand-ecc-mtk.h +@@ -0,0 +1,47 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* ++ * MTK SDG1 ECC controller ++ * ++ * Copyright (c) 2016 Mediatek ++ * Authors: Xiaolei Li ++ * Jorge Ramirez-Ortiz ++ */ ++ ++#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ ++#define __DRIVERS_MTD_NAND_MTK_ECC_H__ ++ ++#include ++ ++enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; ++enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; ++ ++struct device_node; ++struct mtk_ecc; ++ ++struct mtk_ecc_stats { ++ u32 corrected; ++ u32 bitflips; ++ u32 failed; ++}; ++ ++struct mtk_ecc_config { ++ enum mtk_ecc_operation op; ++ enum mtk_ecc_mode mode; ++ dma_addr_t addr; ++ u32 strength; ++ u32 sectors; ++ u32 len; ++}; ++ ++int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); ++void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); ++int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); ++int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); ++void mtk_ecc_disable(struct mtk_ecc *); ++void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); ++ ++struct mtk_ecc *of_mtk_ecc_get(struct device_node *); ++void mtk_ecc_release(struct mtk_ecc *); ++ ++#endif diff --git a/target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch new file mode 100644 index 0000000000..2d380064b8 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch @@ -0,0 +1,1547 @@ +From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Sat, 2 Apr 2022 10:16:11 +0800 +Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface + +This driver implements support for the SPI-NAND mode of MTK NAND Flash +Interface as a SPI-MEM controller with pipelined ECC capability. + +Signed-off-by: Chuanhong Guo +Tested-by: Daniel Golle +--- +Change since v1: + fix CI warnings + +Changes since v2: + use streamed DMA api to avoid an extra memory copy during read + make ECC engine config a per-nand context + take user-requested ECC strength into account + +Change since v3: none +Changes since v4: + fix missing OOB write + print page format with dev_dbg + replace uint*_t copied from vendor driver with u* + +Changes since v5: + add missing nfi mode register configuration in probe + fix an off-by-one bug in mtk_snand_mac_io + + drivers/spi/Kconfig | 10 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++ + 3 files changed, 1481 insertions(+) + create mode 100644 drivers/spi/spi-mtk-snfi.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 6c28ca232444..83c3c2b57a22 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -590,6 +590,16 @@ config SPI_MTK_NOR + SPI interface as well as several SPI NOR specific instructions + via SPI MEM interface. + ++config SPI_MTK_SNFI ++ tristate "MediaTek SPI NAND Flash Interface" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ depends on MTD_NAND_ECC_MEDIATEK ++ help ++ This enables support for SPI-NAND mode on the MediaTek NAND ++ Flash Interface found on MediaTek ARM SoCs. This controller ++ is implemented as a SPI-MEM controller with pipelined ECC ++ capcability. ++ + config SPI_NPCM_FIU + tristate "Nuvoton NPCM FLASH Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 3aa28ed3f761..51541ff17e67 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -76,6 +76,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o + obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o + obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o + obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o ++obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o + obj-$(CONFIG_SPI_MXIC) += spi-mxic.o + obj-$(CONFIG_SPI_MXS) += spi-mxs.o + obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o +diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c +new file mode 100644 +index 000000000000..2c556e304673 +--- /dev/null ++++ b/drivers/spi/spi-mtk-snfi.c +@@ -0,0 +1,1470 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface ++// ++// Copyright (c) 2022 Chuanhong Guo ++// ++// This driver is based on the SPI-NAND mtd driver from Mediatek SDK: ++// ++// Copyright (C) 2020 MediaTek Inc. ++// Author: Weijie Gao ++// ++// This controller organize the page data as several interleaved sectors ++// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size) ++// +---------+------+------+---------+------+------+-----+ ++// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... | ++// +---------+------+------+---------+------+------+-----+ ++// With auto-format turned on, DMA only returns this part: ++// +---------+---------+-----+ ++// | Sector1 | Sector2 | ... | ++// +---------+---------+-----+ ++// The FDM data will be filled to the registers, and ECC parity data isn't ++// accessible. ++// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA ++// in it's original order shown in the first table. ECC can't be turned on when ++// auto-format is off. ++// ++// However, Linux SPI-NAND driver expects the data returned as: ++// +------+-----+ ++// | Page | OOB | ++// +------+-----+ ++// where the page data is continuously stored instead of interleaved. ++// So we assume all instructions matching the page_op template between ECC ++// prepare_io_req and finish_io_req are for page cache r/w. ++// Here's how this spi-mem driver operates when reading: ++// 1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off). ++// 2. Perform page ops and let the controller fill the DMA bounce buffer with ++// de-interleaved sector data and set FDM registers. ++// 3. Return the data as: ++// +---------+---------+-----+------+------+-----+ ++// | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... | ++// +---------+---------+-----+------+------+-----+ ++// 4. For other matching spi_mem ops outside a prepare/finish_io_req pair, ++// read the data with auto-format off into the bounce buffer and copy ++// needed data to the buffer specified in the request. ++// ++// Write requests operates in a similar manner. ++// As a limitation of this strategy, we won't be able to access any ECC parity ++// data at all in Linux. ++// ++// Here's the bad block mark situation on MTK chips: ++// In older chips like mt7622, MTK uses the first FDM byte in the first sector ++// as the bad block mark. After de-interleaving, this byte appears at [pagesize] ++// in the returned data, which is the BBM position expected by kernel. However, ++// the conventional bad block mark is the first byte of the OOB, which is part ++// of the last sector data in the interleaved layout. Instead of fixing their ++// hardware, MTK decided to address this inconsistency in software. On these ++// later chips, the BootROM expects the following: ++// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at ++// (page_size - (nsectors - 1) * spare_size) in the DMA buffer. ++// 2. The original byte stored at that position in the DMA buffer will be stored ++// as the first byte of the FDM section in the last sector. ++// We can't disagree with the BootROM, so after de-interleaving, we need to ++// perform the following swaps in read: ++// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size], ++// which is the expected BBM position by kernel. ++// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to ++// [page_size - (nsectors - 1) * spare_size] ++// Similarly, when writing, we need to perform swaps in the other direction. ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// NFI registers ++#define NFI_CNFG 0x000 ++#define CNFG_OP_MODE_S 12 ++#define CNFG_OP_MODE_CUST 6 ++#define CNFG_OP_MODE_PROGRAM 3 ++#define CNFG_AUTO_FMT_EN BIT(9) ++#define CNFG_HW_ECC_EN BIT(8) ++#define CNFG_DMA_BURST_EN BIT(2) ++#define CNFG_READ_MODE BIT(1) ++#define CNFG_DMA_MODE BIT(0) ++ ++#define NFI_PAGEFMT 0x0004 ++#define NFI_SPARE_SIZE_LS_S 16 ++#define NFI_FDM_ECC_NUM_S 12 ++#define NFI_FDM_NUM_S 8 ++#define NFI_SPARE_SIZE_S 4 ++#define NFI_SEC_SEL_512 BIT(2) ++#define NFI_PAGE_SIZE_S 0 ++#define NFI_PAGE_SIZE_512_2K 0 ++#define NFI_PAGE_SIZE_2K_4K 1 ++#define NFI_PAGE_SIZE_4K_8K 2 ++#define NFI_PAGE_SIZE_8K_16K 3 ++ ++#define NFI_CON 0x008 ++#define CON_SEC_NUM_S 12 ++#define CON_BWR BIT(9) ++#define CON_BRD BIT(8) ++#define CON_NFI_RST BIT(1) ++#define CON_FIFO_FLUSH BIT(0) ++ ++#define NFI_INTR_EN 0x010 ++#define NFI_INTR_STA 0x014 ++#define NFI_IRQ_INTR_EN BIT(31) ++#define NFI_IRQ_CUS_READ BIT(8) ++#define NFI_IRQ_CUS_PG BIT(7) ++ ++#define NFI_CMD 0x020 ++#define NFI_CMD_DUMMY_READ 0x00 ++#define NFI_CMD_DUMMY_WRITE 0x80 ++ ++#define NFI_STRDATA 0x040 ++#define STR_DATA BIT(0) ++ ++#define NFI_STA 0x060 ++#define NFI_NAND_FSM GENMASK(28, 24) ++#define NFI_FSM GENMASK(19, 16) ++#define READ_EMPTY BIT(12) ++ ++#define NFI_FIFOSTA 0x064 ++#define FIFO_WR_REMAIN_S 8 ++#define FIFO_RD_REMAIN_S 0 ++ ++#define NFI_ADDRCNTR 0x070 ++#define SEC_CNTR GENMASK(16, 12) ++#define SEC_CNTR_S 12 ++#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) ++ ++#define NFI_STRADDR 0x080 ++ ++#define NFI_BYTELEN 0x084 ++#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) ++ ++#define NFI_FDM0L 0x0a0 ++#define NFI_FDM0M 0x0a4 ++#define NFI_FDML(n) (NFI_FDM0L + (n)*8) ++#define NFI_FDMM(n) (NFI_FDM0M + (n)*8) ++ ++#define NFI_DEBUG_CON1 0x220 ++#define WBUF_EN BIT(2) ++ ++#define NFI_MASTERSTA 0x224 ++#define MAS_ADDR GENMASK(11, 9) ++#define MAS_RD GENMASK(8, 6) ++#define MAS_WR GENMASK(5, 3) ++#define MAS_RDDLY GENMASK(2, 0) ++#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) ++ ++// SNFI registers ++#define SNF_MAC_CTL 0x500 ++#define MAC_XIO_SEL BIT(4) ++#define SF_MAC_EN BIT(3) ++#define SF_TRIG BIT(2) ++#define WIP_READY BIT(1) ++#define WIP BIT(0) ++ ++#define SNF_MAC_OUTL 0x504 ++#define SNF_MAC_INL 0x508 ++ ++#define SNF_RD_CTL2 0x510 ++#define DATA_READ_DUMMY_S 8 ++#define DATA_READ_MAX_DUMMY 0xf ++#define DATA_READ_CMD_S 0 ++ ++#define SNF_RD_CTL3 0x514 ++ ++#define SNF_PG_CTL1 0x524 ++#define PG_LOAD_CMD_S 8 ++ ++#define SNF_PG_CTL2 0x528 ++ ++#define SNF_MISC_CTL 0x538 ++#define SW_RST BIT(28) ++#define FIFO_RD_LTC_S 25 ++#define PG_LOAD_X4_EN BIT(20) ++#define DATA_READ_MODE_S 16 ++#define DATA_READ_MODE GENMASK(18, 16) ++#define DATA_READ_MODE_X1 0 ++#define DATA_READ_MODE_X2 1 ++#define DATA_READ_MODE_X4 2 ++#define DATA_READ_MODE_DUAL 5 ++#define DATA_READ_MODE_QUAD 6 ++#define PG_LOAD_CUSTOM_EN BIT(7) ++#define DATARD_CUSTOM_EN BIT(6) ++#define CS_DESELECT_CYC_S 0 ++ ++#define SNF_MISC_CTL2 0x53c ++#define PROGRAM_LOAD_BYTE_NUM_S 16 ++#define READ_DATA_BYTE_NUM_S 11 ++ ++#define SNF_DLY_CTL3 0x548 ++#define SFCK_SAM_DLY_S 0 ++ ++#define SNF_STA_CTL1 0x550 ++#define CUS_PG_DONE BIT(28) ++#define CUS_READ_DONE BIT(27) ++#define SPI_STATE_S 0 ++#define SPI_STATE GENMASK(3, 0) ++ ++#define SNF_CFG 0x55c ++#define SPI_MODE BIT(0) ++ ++#define SNF_GPRAM 0x800 ++#define SNF_GPRAM_SIZE 0xa0 ++ ++#define SNFI_POLL_INTERVAL 1000000 ++ ++static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 }; ++ ++struct mtk_snand_caps { ++ u16 sector_size; ++ u16 max_sectors; ++ u16 fdm_size; ++ u16 fdm_ecc_size; ++ u16 fifo_size; ++ ++ bool bbm_swap; ++ bool empty_page_check; ++ u32 mastersta_mask; ++ ++ const u8 *spare_sizes; ++ u32 num_spare_size; ++}; ++ ++static const struct mtk_snand_caps mt7622_snand_caps = { ++ .sector_size = 512, ++ .max_sectors = 8, ++ .fdm_size = 8, ++ .fdm_ecc_size = 1, ++ .fifo_size = 32, ++ .bbm_swap = false, ++ .empty_page_check = false, ++ .mastersta_mask = NFI_MASTERSTA_MASK_7622, ++ .spare_sizes = mt7622_spare_sizes, ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++}; ++ ++static const struct mtk_snand_caps mt7629_snand_caps = { ++ .sector_size = 512, ++ .max_sectors = 8, ++ .fdm_size = 8, ++ .fdm_ecc_size = 1, ++ .fifo_size = 32, ++ .bbm_swap = true, ++ .empty_page_check = false, ++ .mastersta_mask = NFI_MASTERSTA_MASK_7622, ++ .spare_sizes = mt7622_spare_sizes, ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++}; ++ ++struct mtk_snand_conf { ++ size_t page_size; ++ size_t oob_size; ++ u8 nsectors; ++ u8 spare_size; ++}; ++ ++struct mtk_snand { ++ struct spi_controller *ctlr; ++ struct device *dev; ++ struct clk *nfi_clk; ++ struct clk *pad_clk; ++ void __iomem *nfi_base; ++ int irq; ++ struct completion op_done; ++ const struct mtk_snand_caps *caps; ++ struct mtk_ecc_config *ecc_cfg; ++ struct mtk_ecc *ecc; ++ struct mtk_snand_conf nfi_cfg; ++ struct mtk_ecc_stats ecc_stats; ++ struct nand_ecc_engine ecc_eng; ++ bool autofmt; ++ u8 *buf; ++ size_t buf_len; ++}; ++ ++static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand) ++{ ++ struct nand_ecc_engine *eng = nand->ecc.engine; ++ ++ return container_of(eng, struct mtk_snand, ecc_eng); ++} ++ ++static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size) ++{ ++ if (snf->buf_len >= size) ++ return 0; ++ kfree(snf->buf); ++ snf->buf = kmalloc(size, GFP_KERNEL); ++ if (!snf->buf) ++ return -ENOMEM; ++ snf->buf_len = size; ++ memset(snf->buf, 0xff, snf->buf_len); ++ return 0; ++} ++ ++static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg) ++{ ++ return readl(snf->nfi_base + reg); ++} ++ ++static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val) ++{ ++ writel(val, snf->nfi_base + reg); ++} ++ ++static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val) ++{ ++ writew(val, snf->nfi_base + reg); ++} ++ ++static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set) ++{ ++ u32 val; ++ ++ val = readl(snf->nfi_base + reg); ++ val &= ~clr; ++ val |= set; ++ writel(val, snf->nfi_base + reg); ++} ++ ++static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len) ++{ ++ u32 i, val = 0, es = sizeof(u32); ++ ++ for (i = reg; i < reg + len; i++) { ++ if (i == reg || i % es == 0) ++ val = nfi_read32(snf, i & ~(es - 1)); ++ ++ *data++ = (u8)(val >> (8 * (i % es))); ++ } ++} ++ ++static int mtk_nfi_reset(struct mtk_snand *snf) ++{ ++ u32 val, fifo_mask; ++ int ret; ++ ++ nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); ++ ++ ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, ++ !(val & snf->caps->mastersta_mask), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "NFI master is still busy after reset\n"); ++ return ret; ++ } ++ ++ ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val, ++ !(val & (NFI_FSM | NFI_NAND_FSM)), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Failed to reset NFI\n"); ++ return ret; ++ } ++ ++ fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) | ++ ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S); ++ ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, ++ !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "NFI FIFOs are not empty\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mtk_snand_mac_reset(struct mtk_snand *snf) ++{ ++ int ret; ++ u32 val; ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, ++ !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Failed to reset SNFI MAC\n"); ++ ++ nfi_write32(snf, SNF_MISC_CTL, ++ (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S)); ++ ++ return ret; ++} ++ ++static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen) ++{ ++ int ret; ++ u32 val; ++ ++ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); ++ nfi_write32(snf, SNF_MAC_OUTL, outlen); ++ nfi_write32(snf, SNF_MAC_INL, inlen); ++ ++ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, ++ val & WIP_READY, 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for WIP_READY\n"); ++ goto cleanup; ++ } ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP), ++ 0, SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Timed out waiting for WIP cleared\n"); ++ ++cleanup: ++ nfi_write32(snf, SNF_MAC_CTL, 0); ++ ++ return ret; ++} ++ ++static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op) ++{ ++ u32 rx_len = 0; ++ u32 reg_offs = 0; ++ u32 val = 0; ++ const u8 *tx_buf = NULL; ++ u8 *rx_buf = NULL; ++ int i, ret; ++ u8 b; ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ rx_len = op->data.nbytes; ++ rx_buf = op->data.buf.in; ++ } else { ++ tx_buf = op->data.buf.out; ++ } ++ ++ mtk_snand_mac_reset(snf); ++ ++ for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) { ++ b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff; ++ val |= b << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ for (i = 0; i < op->addr.nbytes; i++, reg_offs++) { ++ b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff; ++ val |= b << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) { ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ if (op->data.dir == SPI_MEM_DATA_OUT) { ++ for (i = 0; i < op->data.nbytes; i++, reg_offs++) { ++ val |= tx_buf[i] << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ } ++ ++ if (reg_offs % 4) ++ nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val); ++ ++ for (i = 0; i < reg_offs; i += 4) ++ dev_dbg(snf->dev, "%d: %08X", i, ++ nfi_read32(snf, SNF_GPRAM + i)); ++ ++ dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len); ++ ++ ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len); ++ if (ret) ++ return ret; ++ ++ if (!rx_len) ++ return 0; ++ ++ nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len); ++ return 0; ++} ++ ++static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size, ++ u32 oob_size) ++{ ++ int spare_idx = -1; ++ u32 spare_size, spare_size_shift, pagesize_idx; ++ u32 sector_size_512; ++ u8 nsectors; ++ int i; ++ ++ // skip if it's already configured as required. ++ if (snf->nfi_cfg.page_size == page_size && ++ snf->nfi_cfg.oob_size == oob_size) ++ return 0; ++ ++ nsectors = page_size / snf->caps->sector_size; ++ if (nsectors > snf->caps->max_sectors) { ++ dev_err(snf->dev, "too many sectors required.\n"); ++ goto err; ++ } ++ ++ if (snf->caps->sector_size == 512) { ++ sector_size_512 = NFI_SEC_SEL_512; ++ spare_size_shift = NFI_SPARE_SIZE_S; ++ } else { ++ sector_size_512 = 0; ++ spare_size_shift = NFI_SPARE_SIZE_LS_S; ++ } ++ ++ switch (page_size) { ++ case SZ_512: ++ pagesize_idx = NFI_PAGE_SIZE_512_2K; ++ break; ++ case SZ_2K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_2K_4K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_512_2K; ++ break; ++ case SZ_4K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_4K_8K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_2K_4K; ++ break; ++ case SZ_8K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_8K_16K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_4K_8K; ++ break; ++ case SZ_16K: ++ pagesize_idx = NFI_PAGE_SIZE_8K_16K; ++ break; ++ default: ++ dev_err(snf->dev, "unsupported page size.\n"); ++ goto err; ++ } ++ ++ spare_size = oob_size / nsectors; ++ // If we're using the 1KB sector size, HW will automatically double the ++ // spare size. We should only use half of the value in this case. ++ if (snf->caps->sector_size == 1024) ++ spare_size /= 2; ++ ++ for (i = snf->caps->num_spare_size - 1; i >= 0; i--) { ++ if (snf->caps->spare_sizes[i] <= spare_size) { ++ spare_size = snf->caps->spare_sizes[i]; ++ if (snf->caps->sector_size == 1024) ++ spare_size *= 2; ++ spare_idx = i; ++ break; ++ } ++ } ++ ++ if (spare_idx < 0) { ++ dev_err(snf->dev, "unsupported spare size: %u\n", spare_size); ++ goto err; ++ } ++ ++ nfi_write32(snf, NFI_PAGEFMT, ++ (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | ++ (snf->caps->fdm_size << NFI_FDM_NUM_S) | ++ (spare_idx << spare_size_shift) | ++ (pagesize_idx << NFI_PAGE_SIZE_S) | ++ sector_size_512); ++ ++ snf->nfi_cfg.page_size = page_size; ++ snf->nfi_cfg.oob_size = oob_size; ++ snf->nfi_cfg.nsectors = nsectors; ++ snf->nfi_cfg.spare_size = spare_size; ++ ++ dev_dbg(snf->dev, "page format: (%u + %u) * %u\n", ++ snf->caps->sector_size, spare_size, nsectors); ++ return snand_prepare_bouncebuf(snf, page_size + oob_size); ++err: ++ dev_err(snf->dev, "page size %u + %u is not supported\n", page_size, ++ oob_size); ++ return -EOPNOTSUPP; ++} ++ ++static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobecc) ++{ ++ // ECC area is not accessible ++ return -ERANGE; ++} ++ ++static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobfree) ++{ ++ struct nand_device *nand = mtd_to_nanddev(mtd); ++ struct mtk_snand *ms = nand_to_mtk_snand(nand); ++ ++ if (section >= ms->nfi_cfg.nsectors) ++ return -ERANGE; ++ ++ oobfree->length = ms->caps->fdm_size - 1; ++ oobfree->offset = section * ms->caps->fdm_size + 1; ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { ++ .ecc = mtk_snand_ooblayout_ecc, ++ .free = mtk_snand_ooblayout_free, ++}; ++ ++static int mtk_snand_ecc_init_ctx(struct nand_device *nand) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct nand_ecc_props *conf = &nand->ecc.ctx.conf; ++ struct nand_ecc_props *reqs = &nand->ecc.requirements; ++ struct nand_ecc_props *user = &nand->ecc.user_conf; ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ int step_size = 0, strength = 0, desired_correction = 0, steps; ++ bool ecc_user = false; ++ int ret; ++ u32 parity_bits, max_ecc_bytes; ++ struct mtk_ecc_config *ecc_cfg; ++ ++ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, ++ nand->memorg.oobsize); ++ if (ret) ++ return ret; ++ ++ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); ++ if (!ecc_cfg) ++ return -ENOMEM; ++ ++ nand->ecc.ctx.priv = ecc_cfg; ++ ++ if (user->step_size && user->strength) { ++ step_size = user->step_size; ++ strength = user->strength; ++ ecc_user = true; ++ } else if (reqs->step_size && reqs->strength) { ++ step_size = reqs->step_size; ++ strength = reqs->strength; ++ } ++ ++ if (step_size && strength) { ++ steps = mtd->writesize / step_size; ++ desired_correction = steps * strength; ++ strength = desired_correction / snf->nfi_cfg.nsectors; ++ } ++ ++ ecc_cfg->mode = ECC_NFI_MODE; ++ ecc_cfg->sectors = snf->nfi_cfg.nsectors; ++ ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size; ++ ++ // calculate the max possible strength under current page format ++ parity_bits = mtk_ecc_get_parity_bits(snf->ecc); ++ max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size; ++ ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits; ++ mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength); ++ ++ // if there's a user requested strength, find the minimum strength that ++ // meets the requirement. Otherwise use the maximum strength which is ++ // expected by BootROM. ++ if (ecc_user && strength) { ++ u32 s_next = ecc_cfg->strength - 1; ++ ++ while (1) { ++ mtk_ecc_adjust_strength(snf->ecc, &s_next); ++ if (s_next >= ecc_cfg->strength) ++ break; ++ if (s_next < strength) ++ break; ++ s_next = ecc_cfg->strength - 1; ++ } ++ } ++ ++ mtd_set_ooblayout(mtd, &mtk_snand_ooblayout); ++ ++ conf->step_size = snf->caps->sector_size; ++ conf->strength = ecc_cfg->strength; ++ ++ if (ecc_cfg->strength < strength) ++ dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n", ++ strength); ++ dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n", ++ ecc_cfg->strength, snf->caps->sector_size); ++ ++ return 0; ++} ++ ++static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand) ++{ ++ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); ++ ++ kfree(ecc_cfg); ++} ++ ++static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand, ++ struct nand_page_io_req *req) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); ++ int ret; ++ ++ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, ++ nand->memorg.oobsize); ++ if (ret) ++ return ret; ++ snf->autofmt = true; ++ snf->ecc_cfg = ecc_cfg; ++ return 0; ++} ++ ++static int mtk_snand_ecc_finish_io_req(struct nand_device *nand, ++ struct nand_page_io_req *req) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ ++ snf->ecc_cfg = NULL; ++ snf->autofmt = false; ++ if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ)) ++ return 0; ++ ++ if (snf->ecc_stats.failed) ++ mtd->ecc_stats.failed += snf->ecc_stats.failed; ++ mtd->ecc_stats.corrected += snf->ecc_stats.corrected; ++ return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips; ++} ++ ++static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = { ++ .init_ctx = mtk_snand_ecc_init_ctx, ++ .cleanup_ctx = mtk_snand_ecc_cleanup_ctx, ++ .prepare_io_req = mtk_snand_ecc_prepare_io_req, ++ .finish_io_req = mtk_snand_ecc_finish_io_req, ++}; ++ ++static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf) ++{ ++ u32 vall, valm; ++ u8 *oobptr = buf; ++ int i, j; ++ ++ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { ++ vall = nfi_read32(snf, NFI_FDML(i)); ++ valm = nfi_read32(snf, NFI_FDMM(i)); ++ ++ for (j = 0; j < snf->caps->fdm_size; j++) ++ oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); ++ ++ oobptr += snf->caps->fdm_size; ++ } ++} ++ ++static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf) ++{ ++ u32 fdm_size = snf->caps->fdm_size; ++ const u8 *oobptr = buf; ++ u32 vall, valm; ++ int i, j; ++ ++ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { ++ vall = 0; ++ valm = 0; ++ ++ for (j = 0; j < 8; j++) { ++ if (j < 4) ++ vall |= (j < fdm_size ? oobptr[j] : 0xff) ++ << (j * 8); ++ else ++ valm |= (j < fdm_size ? oobptr[j] : 0xff) ++ << ((j - 4) * 8); ++ } ++ ++ nfi_write32(snf, NFI_FDML(i), vall); ++ nfi_write32(snf, NFI_FDMM(i), valm); ++ ++ oobptr += fdm_size; ++ } ++} ++ ++static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf) ++{ ++ u32 buf_bbm_pos, fdm_bbm_pos; ++ ++ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) ++ return; ++ ++ // swap [pagesize] byte on nand with the first fdm byte ++ // in the last sector. ++ buf_bbm_pos = snf->nfi_cfg.page_size - ++ (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size; ++ fdm_bbm_pos = snf->nfi_cfg.page_size + ++ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; ++ ++ swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]); ++} ++ ++static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) ++{ ++ u32 fdm_bbm_pos1, fdm_bbm_pos2; ++ ++ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) ++ return; ++ ++ // swap the first fdm byte in the first and the last sector. ++ fdm_bbm_pos1 = snf->nfi_cfg.page_size; ++ fdm_bbm_pos2 = snf->nfi_cfg.page_size + ++ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; ++ swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]); ++} ++ ++static int mtk_snand_read_page_cache(struct mtk_snand *snf, ++ const struct spi_mem_op *op) ++{ ++ u8 *buf = snf->buf; ++ u8 *buf_fdm = buf + snf->nfi_cfg.page_size; ++ // the address part to be sent by the controller ++ u32 op_addr = op->addr.val; ++ // where to start copying data from bounce buffer ++ u32 rd_offset = 0; ++ u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth); ++ u32 op_mode = 0; ++ u32 dma_len = snf->buf_len; ++ int ret = 0; ++ u32 rd_mode, rd_bytes, val; ++ dma_addr_t buf_dma; ++ ++ if (snf->autofmt) { ++ u32 last_bit; ++ u32 mask; ++ ++ dma_len = snf->nfi_cfg.page_size; ++ op_mode = CNFG_AUTO_FMT_EN; ++ if (op->data.ecc) ++ op_mode |= CNFG_HW_ECC_EN; ++ // extract the plane bit: ++ // Find the highest bit set in (pagesize+oobsize). ++ // Bits higher than that in op->addr are kept and sent over SPI ++ // Lower bits are used as an offset for copying data from DMA ++ // bounce buffer. ++ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); ++ mask = (1 << last_bit) - 1; ++ rd_offset = op_addr & mask; ++ op_addr &= ~mask; ++ ++ // check if we can dma to the caller memory ++ if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size) ++ buf = op->data.buf.in; ++ } ++ mtk_snand_mac_reset(snf); ++ mtk_nfi_reset(snf); ++ ++ // command and dummy cycles ++ nfi_write32(snf, SNF_RD_CTL2, ++ (dummy_clk << DATA_READ_DUMMY_S) | ++ (op->cmd.opcode << DATA_READ_CMD_S)); ++ ++ // read address ++ nfi_write32(snf, SNF_RD_CTL3, op_addr); ++ ++ // Set read op_mode ++ if (op->data.buswidth == 4) ++ rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD : ++ DATA_READ_MODE_X4; ++ else if (op->data.buswidth == 2) ++ rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL : ++ DATA_READ_MODE_X2; ++ else ++ rd_mode = DATA_READ_MODE_X1; ++ rd_mode <<= DATA_READ_MODE_S; ++ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, ++ rd_mode | DATARD_CUSTOM_EN); ++ ++ // Set bytes to read ++ rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * ++ snf->nfi_cfg.nsectors; ++ nfi_write32(snf, SNF_MISC_CTL2, ++ (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes); ++ ++ // NFI read prepare ++ nfi_write16(snf, NFI_CNFG, ++ (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN | ++ CNFG_READ_MODE | CNFG_DMA_MODE | op_mode); ++ ++ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); ++ ++ buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE); ++ if (dma_mapping_error(snf->dev, buf_dma)) { ++ dev_err(snf->dev, "DMA mapping failed.\n"); ++ goto cleanup; ++ } ++ nfi_write32(snf, NFI_STRADDR, buf_dma); ++ if (op->data.ecc) { ++ snf->ecc_cfg->op = ECC_DECODE; ++ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); ++ if (ret) ++ goto cleanup_dma; ++ } ++ // Prepare for custom read interrupt ++ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); ++ reinit_completion(&snf->op_done); ++ ++ // Trigger NFI into custom mode ++ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); ++ ++ // Start DMA read ++ nfi_rmw32(snf, NFI_CON, 0, CON_BRD); ++ nfi_write16(snf, NFI_STRDATA, STR_DATA); ++ ++ if (!wait_for_completion_timeout( ++ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { ++ dev_err(snf->dev, "DMA timed out for reading from cache.\n"); ++ ret = -ETIMEDOUT; ++ goto cleanup; ++ } ++ ++ // Wait for BUS_SEC_CNTR returning expected value ++ ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, ++ BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n"); ++ goto cleanup2; ++ } ++ ++ // Wait for bus becoming idle ++ ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, ++ !(val & snf->caps->mastersta_mask), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for bus becoming idle\n"); ++ goto cleanup2; ++ } ++ ++ if (op->data.ecc) { ++ ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE); ++ if (ret) { ++ dev_err(snf->dev, "wait ecc done timeout\n"); ++ goto cleanup2; ++ } ++ // save status before disabling ecc ++ mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats, ++ snf->nfi_cfg.nsectors); ++ } ++ ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); ++ ++ if (snf->autofmt) { ++ mtk_snand_read_fdm(snf, buf_fdm); ++ if (snf->caps->bbm_swap) { ++ mtk_snand_bm_swap(snf, buf); ++ mtk_snand_fdm_bm_swap(snf); ++ } ++ } ++ ++ // copy data back ++ if (nfi_read32(snf, NFI_STA) & READ_EMPTY) { ++ memset(op->data.buf.in, 0xff, op->data.nbytes); ++ snf->ecc_stats.bitflips = 0; ++ snf->ecc_stats.failed = 0; ++ snf->ecc_stats.corrected = 0; ++ } else { ++ if (buf == op->data.buf.in) { ++ u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size; ++ u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size; ++ ++ if (req_left) ++ memcpy(op->data.buf.in + snf->nfi_cfg.page_size, ++ buf_fdm, ++ cap_len < req_left ? cap_len : req_left); ++ } else if (rd_offset < snf->buf_len) { ++ u32 cap_len = snf->buf_len - rd_offset; ++ ++ if (op->data.nbytes < cap_len) ++ cap_len = op->data.nbytes; ++ memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len); ++ } ++ } ++cleanup2: ++ if (op->data.ecc) ++ mtk_ecc_disable(snf->ecc); ++cleanup_dma: ++ // unmap dma only if any error happens. (otherwise it's done before ++ // data copying) ++ if (ret) ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); ++cleanup: ++ // Stop read ++ nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); ++ ++ // Clear SNF done flag ++ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); ++ nfi_write32(snf, SNF_STA_CTL1, 0); ++ ++ // Disable interrupt ++ nfi_read32(snf, NFI_INTR_STA); ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); ++ return ret; ++} ++ ++static int mtk_snand_write_page_cache(struct mtk_snand *snf, ++ const struct spi_mem_op *op) ++{ ++ // the address part to be sent by the controller ++ u32 op_addr = op->addr.val; ++ // where to start copying data from bounce buffer ++ u32 wr_offset = 0; ++ u32 op_mode = 0; ++ int ret = 0; ++ u32 wr_mode = 0; ++ u32 dma_len = snf->buf_len; ++ u32 wr_bytes, val; ++ size_t cap_len; ++ dma_addr_t buf_dma; ++ ++ if (snf->autofmt) { ++ u32 last_bit; ++ u32 mask; ++ ++ dma_len = snf->nfi_cfg.page_size; ++ op_mode = CNFG_AUTO_FMT_EN; ++ if (op->data.ecc) ++ op_mode |= CNFG_HW_ECC_EN; ++ ++ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); ++ mask = (1 << last_bit) - 1; ++ wr_offset = op_addr & mask; ++ op_addr &= ~mask; ++ } ++ mtk_snand_mac_reset(snf); ++ mtk_nfi_reset(snf); ++ ++ if (wr_offset) ++ memset(snf->buf, 0xff, wr_offset); ++ ++ cap_len = snf->buf_len - wr_offset; ++ if (op->data.nbytes < cap_len) ++ cap_len = op->data.nbytes; ++ memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len); ++ if (snf->autofmt) { ++ if (snf->caps->bbm_swap) { ++ mtk_snand_fdm_bm_swap(snf); ++ mtk_snand_bm_swap(snf, snf->buf); ++ } ++ mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size); ++ } ++ ++ // Command ++ nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S)); ++ ++ // write address ++ nfi_write32(snf, SNF_PG_CTL2, op_addr); ++ ++ // Set read op_mode ++ if (op->data.buswidth == 4) ++ wr_mode = PG_LOAD_X4_EN; ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, ++ wr_mode | PG_LOAD_CUSTOM_EN); ++ ++ // Set bytes to write ++ wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * ++ snf->nfi_cfg.nsectors; ++ nfi_write32(snf, SNF_MISC_CTL2, ++ (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes); ++ ++ // NFI write prepare ++ nfi_write16(snf, NFI_CNFG, ++ (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | ++ CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode); ++ ++ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); ++ buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE); ++ if (dma_mapping_error(snf->dev, buf_dma)) { ++ dev_err(snf->dev, "DMA mapping failed.\n"); ++ goto cleanup; ++ } ++ nfi_write32(snf, NFI_STRADDR, buf_dma); ++ if (op->data.ecc) { ++ snf->ecc_cfg->op = ECC_ENCODE; ++ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); ++ if (ret) ++ goto cleanup_dma; ++ } ++ // Prepare for custom write interrupt ++ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); ++ reinit_completion(&snf->op_done); ++ ; ++ ++ // Trigger NFI into custom mode ++ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); ++ ++ // Start DMA write ++ nfi_rmw32(snf, NFI_CON, 0, CON_BWR); ++ nfi_write16(snf, NFI_STRDATA, STR_DATA); ++ ++ if (!wait_for_completion_timeout( ++ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { ++ dev_err(snf->dev, "DMA timed out for program load.\n"); ++ ret = -ETIMEDOUT; ++ goto cleanup_ecc; ++ } ++ ++ // Wait for NFI_SEC_CNTR returning expected value ++ ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, ++ NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n"); ++ ++cleanup_ecc: ++ if (op->data.ecc) ++ mtk_ecc_disable(snf->ecc); ++cleanup_dma: ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE); ++cleanup: ++ // Stop write ++ nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); ++ ++ // Clear SNF done flag ++ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); ++ nfi_write32(snf, SNF_STA_CTL1, 0); ++ ++ // Disable interrupt ++ nfi_read32(snf, NFI_INTR_STA); ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0); ++ ++ return ret; ++} ++ ++/** ++ * mtk_snand_is_page_ops() - check if the op is a controller supported page op. ++ * @op spi-mem op to check ++ * ++ * Check whether op can be executed with read_from_cache or program_load ++ * mode in the controller. ++ * This controller can execute typical Read From Cache and Program Load ++ * instructions found on SPI-NAND with 2-byte address. ++ * DTR and cmd buswidth & nbytes should be checked before calling this. ++ * ++ * Return: true if the op matches the instruction template ++ */ ++static bool mtk_snand_is_page_ops(const struct spi_mem_op *op) ++{ ++ if (op->addr.nbytes != 2) ++ return false; ++ ++ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && ++ op->addr.buswidth != 4) ++ return false; ++ ++ // match read from page instructions ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ // check dummy cycle first ++ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > ++ DATA_READ_MAX_DUMMY) ++ return false; ++ // quad io / quad out ++ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) && ++ op->data.buswidth == 4) ++ return true; ++ ++ // dual io / dual out ++ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) && ++ op->data.buswidth == 2) ++ return true; ++ ++ // standard spi ++ if (op->addr.buswidth == 1 && op->data.buswidth == 1) ++ return true; ++ } else if (op->data.dir == SPI_MEM_DATA_OUT) { ++ // check dummy cycle first ++ if (op->dummy.nbytes) ++ return false; ++ // program load quad out ++ if (op->addr.buswidth == 1 && op->data.buswidth == 4) ++ return true; ++ // standard spi ++ if (op->addr.buswidth == 1 && op->data.buswidth == 1) ++ return true; ++ } ++ return false; ++} ++ ++static bool mtk_snand_supports_op(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ if (!spi_mem_default_supports_op(mem, op)) ++ return false; ++ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) ++ return false; ++ if (mtk_snand_is_page_ops(op)) ++ return true; ++ return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) && ++ (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) && ++ (op->data.nbytes == 0 || op->data.buswidth == 1)); ++} ++ ++static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) ++{ ++ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); ++ // page ops transfer size must be exactly ((sector_size + spare_size) * ++ // nsectors). Limit the op size if the caller requests more than that. ++ // exec_op will read more than needed and discard the leftover if the ++ // caller requests less data. ++ if (mtk_snand_is_page_ops(op)) { ++ size_t l; ++ // skip adjust_op_size for page ops ++ if (ms->autofmt) ++ return 0; ++ l = ms->caps->sector_size + ms->nfi_cfg.spare_size; ++ l *= ms->nfi_cfg.nsectors; ++ if (op->data.nbytes > l) ++ op->data.nbytes = l; ++ } else { ++ size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; ++ ++ if (hl >= SNF_GPRAM_SIZE) ++ return -EOPNOTSUPP; ++ if (op->data.nbytes > SNF_GPRAM_SIZE - hl) ++ op->data.nbytes = SNF_GPRAM_SIZE - hl; ++ } ++ return 0; ++} ++ ++static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) ++{ ++ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); ++ ++ dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, ++ op->addr.val, op->addr.buswidth, op->addr.nbytes, ++ op->data.buswidth, op->data.nbytes); ++ if (mtk_snand_is_page_ops(op)) { ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ return mtk_snand_read_page_cache(ms, op); ++ else ++ return mtk_snand_write_page_cache(ms, op); ++ } else { ++ return mtk_snand_mac_io(ms, op); ++ } ++} ++ ++static const struct spi_controller_mem_ops mtk_snand_mem_ops = { ++ .adjust_op_size = mtk_snand_adjust_op_size, ++ .supports_op = mtk_snand_supports_op, ++ .exec_op = mtk_snand_exec_op, ++}; ++ ++static const struct spi_controller_mem_caps mtk_snand_mem_caps = { ++ .ecc = true, ++}; ++ ++static irqreturn_t mtk_snand_irq(int irq, void *id) ++{ ++ struct mtk_snand *snf = id; ++ u32 sta, ien; ++ ++ sta = nfi_read32(snf, NFI_INTR_STA); ++ ien = nfi_read32(snf, NFI_INTR_EN); ++ ++ if (!(sta & ien)) ++ return IRQ_NONE; ++ ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ complete(&snf->op_done); ++ return IRQ_HANDLED; ++} ++ ++static const struct of_device_id mtk_snand_ids[] = { ++ { .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps }, ++ { .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, mtk_snand_ids); ++ ++static int mtk_snand_enable_clk(struct mtk_snand *ms) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(ms->nfi_clk); ++ if (ret) { ++ dev_err(ms->dev, "unable to enable nfi clk\n"); ++ return ret; ++ } ++ ret = clk_prepare_enable(ms->pad_clk); ++ if (ret) { ++ dev_err(ms->dev, "unable to enable pad clk\n"); ++ goto err1; ++ } ++ return 0; ++err1: ++ clk_disable_unprepare(ms->nfi_clk); ++ return ret; ++} ++ ++static void mtk_snand_disable_clk(struct mtk_snand *ms) ++{ ++ clk_disable_unprepare(ms->pad_clk); ++ clk_disable_unprepare(ms->nfi_clk); ++} ++ ++static int mtk_snand_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ const struct of_device_id *dev_id; ++ struct spi_controller *ctlr; ++ struct mtk_snand *ms; ++ int ret; ++ ++ dev_id = of_match_node(mtk_snand_ids, np); ++ if (!dev_id) ++ return -EINVAL; ++ ++ ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms)); ++ if (!ctlr) ++ return -ENOMEM; ++ platform_set_drvdata(pdev, ctlr); ++ ++ ms = spi_controller_get_devdata(ctlr); ++ ++ ms->ctlr = ctlr; ++ ms->caps = dev_id->data; ++ ++ ms->ecc = of_mtk_ecc_get(np); ++ if (IS_ERR(ms->ecc)) ++ return PTR_ERR(ms->ecc); ++ else if (!ms->ecc) ++ return -ENODEV; ++ ++ ms->nfi_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ms->nfi_base)) { ++ ret = PTR_ERR(ms->nfi_base); ++ goto release_ecc; ++ } ++ ++ ms->dev = &pdev->dev; ++ ++ ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk"); ++ if (IS_ERR(ms->nfi_clk)) { ++ ret = PTR_ERR(ms->nfi_clk); ++ dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret); ++ goto release_ecc; ++ } ++ ++ ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk"); ++ if (IS_ERR(ms->pad_clk)) { ++ ret = PTR_ERR(ms->pad_clk); ++ dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret); ++ goto release_ecc; ++ } ++ ++ ret = mtk_snand_enable_clk(ms); ++ if (ret) ++ goto release_ecc; ++ ++ init_completion(&ms->op_done); ++ ++ ms->irq = platform_get_irq(pdev, 0); ++ if (ms->irq < 0) { ++ ret = ms->irq; ++ goto disable_clk; ++ } ++ ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0, ++ "mtk-snand", ms); ++ if (ret) { ++ dev_err(ms->dev, "failed to request snfi irq\n"); ++ goto disable_clk; ++ } ++ ++ ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(ms->dev, "failed to set dma mask\n"); ++ goto disable_clk; ++ } ++ ++ // switch to SNFI mode ++ nfi_write32(ms, SNF_CFG, SPI_MODE); ++ ++ // setup an initial page format for ops matching page_cache_op template ++ // before ECC is called. ++ ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, ++ ms->caps->spare_sizes[0]); ++ if (ret) { ++ dev_err(ms->dev, "failed to set initial page format\n"); ++ goto disable_clk; ++ } ++ ++ // setup ECC engine ++ ms->ecc_eng.dev = &pdev->dev; ++ ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; ++ ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops; ++ ms->ecc_eng.priv = ms; ++ ++ ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register ecc engine.\n"); ++ goto disable_clk; ++ } ++ ++ ctlr->num_chipselect = 1; ++ ctlr->mem_ops = &mtk_snand_mem_ops; ++ ctlr->mem_caps = &mtk_snand_mem_caps; ++ ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ++ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ++ ctlr->dev.of_node = pdev->dev.of_node; ++ ret = spi_register_controller(ctlr); ++ if (ret) { ++ dev_err(&pdev->dev, "spi_register_controller failed.\n"); ++ goto disable_clk; ++ } ++ ++ return 0; ++disable_clk: ++ mtk_snand_disable_clk(ms); ++release_ecc: ++ mtk_ecc_release(ms->ecc); ++ return ret; ++} ++ ++static int mtk_snand_remove(struct platform_device *pdev) ++{ ++ struct spi_controller *ctlr = platform_get_drvdata(pdev); ++ struct mtk_snand *ms = spi_controller_get_devdata(ctlr); ++ ++ spi_unregister_controller(ctlr); ++ mtk_snand_disable_clk(ms); ++ mtk_ecc_release(ms->ecc); ++ kfree(ms->buf); ++ return 0; ++} ++ ++static struct platform_driver mtk_snand_driver = { ++ .probe = mtk_snand_probe, ++ .remove = mtk_snand_remove, ++ .driver = { ++ .name = "mtk-snand", ++ .of_match_table = mtk_snand_ids, ++ }, ++}; ++ ++module_platform_driver(mtk_snand_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhong Guo "); ++MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch new file mode 100644 index 0000000000..80d482b6a5 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch @@ -0,0 +1,35 @@ +From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Mon, 4 Apr 2022 00:05:38 +0800 +Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if + available + +The recently added ECC engine support introduced a generic property +named nand-ecc-engine for ecc engine phandle. This patch adds support +for this new property. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54) +--- + drivers/mtd/nand/ecc-mtk.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c +index c64c3c45cdbc..79c7622af563 100644 +--- a/drivers/mtd/nand/ecc-mtk.c ++++ b/drivers/mtd/nand/ecc-mtk.c +@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) + struct mtk_ecc *ecc = NULL; + struct device_node *np; + +- np = of_parse_phandle(of_node, "ecc-engine", 0); ++ np = of_parse_phandle(of_node, "nand-ecc-engine", 0); ++ /* for backward compatibility */ ++ if (!np) ++ np = of_parse_phandle(of_node, "ecc-engine", 0); + if (np) { + ecc = mtk_ecc_get(np); + of_node_put(np); +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch new file mode 100644 index 0000000000..81452ade25 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch @@ -0,0 +1,40 @@ +From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Sun, 3 Apr 2022 10:19:29 +0800 +Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622 + +This patch adds a device-tree node for the MTK SPI-NAND Flash Interface +for MT7622 device tree. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af) +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +index 890a942ec608..8cdb8cc94bd3 100644 +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -545,6 +545,18 @@ nandc: nfi@1100d000 { + status = "disabled"; + }; + ++ snfi: spi@1100d000 { ++ compatible = "mediatek,mt7622-snand"; ++ reg = <0 0x1100d000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ nand-ecc-engine = <&bch>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + bch: ecc@1100e000 { + compatible = "mediatek,mt7622-ecc"; + reg = <0 0x1100e000 0 0x1000>; +-- +2.35.1 + diff --git a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch index e7c5d9b167..be0018a383 100644 --- a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch +++ b/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch @@ -11,63 +11,80 @@ Signed-off-by: Xiangsheng Hou --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,22 @@ +@@ -272,6 +272,27 @@ status = "disabled"; }; -+ snand: snfi@1100d000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; ++ snfi: spi@1100d000 { + compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>, <0x1100e000 0x1000>; -+ reg-names = "nfi", "ecc"; ++ reg = <0x1100d000 0x1000>; + interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; ++ ++ bch: ecc@1100e000 { ++ compatible = "mediatek,mt7622-ecc"; ++ reg = <0x1100e000 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFIECC_PD>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; + spi: spi@1100a000 { compatible = "mediatek,mt7629-spi", "mediatek,mt7622-spi"; --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -254,6 +254,38 @@ +@@ -254,6 +254,50 @@ }; }; -+&snand { ++&bch { + status = "okay"; -+ mediatek,quad-spi; ++}; + -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; + -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; + -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; ++ partition@0 { ++ label = "Bootloader"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; + -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; ++ partition@100000 { ++ label = "Config"; ++ reg = <0x100000 0x0040000>; ++ }; + -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; ++ partition@140000 { ++ label = "factory"; ++ reg = <0x140000 0x0080000>; ++ }; ++ ++ partition@1c0000 { ++ label = "firmware"; ++ reg = <0x1c0000 0x1000000>; ++ }; + }; + }; +}; diff --git a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch index b8050b3592..134e5997e2 100644 --- a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch +++ b/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch @@ -1,77 +1,64 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -561,6 +561,20 @@ - status = "disabled"; - }; - -+ snand: snfi@1100d000 { -+ compatible = "mediatek,mt7622-snand"; -+ reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - nor_flash: spi@11014000 { - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -539,6 +539,55 @@ +@@ -539,6 +539,65 @@ status = "disabled"; }; -+&snand { -+ mediatek,quad-spi; ++&bch { ++ status = "okay"; ++}; ++ ++&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; + -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; + -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; ++ partition@0 { ++ label = "Preloader"; ++ reg = <0x00000 0x0080000>; ++ read-only; ++ }; + -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; ++ partition@80000 { ++ label = "ATF"; ++ reg = <0x80000 0x0040000>; ++ }; + -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; ++ partition@c0000 { ++ label = "Bootloader"; ++ reg = <0xc0000 0x0080000>; ++ }; + -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; ++ partition@140000 { ++ label = "Config"; ++ reg = <0x140000 0x0080000>; ++ }; + -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; ++ partition@1c0000 { ++ label = "Factory"; ++ reg = <0x1c0000 0x0100000>; ++ }; + -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; ++ partition@200000 { ++ label = "firmware"; ++ reg = <0x2c0000 0x2000000>; ++ }; + -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; ++ partition@2200000 { ++ label = "User_data"; ++ reg = <0x22c0000 0x4000000>; ++ }; + }; + }; +}; diff --git a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch index b65c4a2805..8e6935b434 100644 --- a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ b/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch @@ -1,15 +1,15 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -571,7 +571,7 @@ - reg = <0x140000 0x0080000>; - }; +@@ -580,7 +580,7 @@ + reg = <0x140000 0x0080000>; + }; -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -631,5 +631,6 @@ +- partition@1c0000 { ++ factory: partition@1c0000 { + label = "Factory"; + reg = <0x1c0000 0x0100000>; + }; +@@ -641,5 +641,6 @@ &wmac { pinctrl-names = "default"; pinctrl-0 = <&wmac_pins>; diff --git a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch new file mode 100644 index 0000000000..26ec7eada0 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch @@ -0,0 +1,34 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) + { +@@ -1331,6 +1332,7 @@ static int spinand_probe(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_attach(mtd); + ret = mtd_device_register(mtd, NULL, 0); + if (ret) + goto err_spinand_cleanup; +@@ -1338,6 +1340,7 @@ static int spinand_probe(struct spi_mem + return 0; + + err_spinand_cleanup: ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return ret; +@@ -1356,6 +1359,7 @@ static int spinand_remove(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return 0; diff --git a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch index 03c0771bcf..9c1a8f284a 100644 --- a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch +++ b/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch @@ -1,11 +1,10 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -545,6 +545,8 @@ - pinctrl-0 = <&serial_nand_pins>; - status = "okay"; +@@ -553,6 +553,7 @@ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; ++ mediatek,bmt-v2; -+ mediatek,bmt-v2; -+ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; + partitions { + compatible = "fixed-partitions"; From fe079b7e0ee9aab5f85e419f5e5c5a80c6ad9ae8 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sat, 9 Apr 2022 20:18:40 +0800 Subject: [PATCH 14/75] mediatek: restore support for Fidelix FM35X1GA This patch was dropped when the spi-nand driver got replaced last time. Signed-off-by: Chuanhong Guo --- ...Add-support-for-the-Fidelix-FM35X1GA.patch | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch diff --git a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch new file mode 100644 index 0000000000..4a5d814b3b --- /dev/null +++ b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch @@ -0,0 +1,122 @@ +From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 +From: Davide Fioravanti +Date: Fri, 8 Jan 2021 15:35:24 +0100 +Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA + +Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf + +Signed-off-by: Davide Fioravanti +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 79 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/fidelix.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,3 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o ++spinand-objs := core.o esmt.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -929,6 +929,7 @@ static const struct nand_ops spinand_ops + + static const struct spinand_manufacturer *spinand_manufacturers[] = { + &esmt_c8_spinand_manufacturer, ++ &fidelix_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + ¯onix_spinand_manufacturer, + µn_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/fidelix.c +@@ -0,0 +1,76 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Davide Fioravanti ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_FIDELIX 0xE5 ++#define FIDELIX_ECCSR_MASK 0x0F ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 6; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { ++ .ecc = fm35x1ga_ooblayout_ecc, ++ .free = fm35x1ga_ooblayout_free, ++}; ++ ++static const struct spinand_info fidelix_spinand_table[] = { ++ SPINAND_INFO("FM35X1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), ++}; ++ ++static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer fidelix_spinand_manufacturer = { ++ .id = SPINAND_MFR_FIDELIX, ++ .name = "Fidelix", ++ .chips = fidelix_spinand_table, ++ .nchips = ARRAY_SIZE(fidelix_spinand_table), ++ .ops = &fidelix_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -261,6 +261,7 @@ struct spinand_manufacturer { + + /* SPI NAND manufacturers */ + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; ++extern const struct spinand_manufacturer fidelix_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; + extern const struct spinand_manufacturer micron_spinand_manufacturer; From 6470018c57c01b2a79f96bf3fe31bbd411decf71 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sat, 9 Apr 2022 13:26:50 +0800 Subject: [PATCH 15/75] mediatek: enable snfi for mt7629 Signed-off-by: Chuanhong Guo --- target/linux/mediatek/mt7629/config-5.15 | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15 index 7f4e90a72c..56e5bc6dd0 100644 --- a/target/linux/mediatek/mt7629/config-5.15 +++ b/target/linux/mediatek/mt7629/config-5.15 @@ -1,3 +1,4 @@ +CONFIG_AF_UNIX_OOB=y CONFIG_ALIGNMENT_TRAP=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y @@ -28,18 +29,17 @@ CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y CONFIG_ATAGS=y CONFIG_AUTO_ZRELADDR=y +CONFIG_BINARY_PRINTF=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_CACHE_L2X0=y # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CHR_DEV_SCH=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="rootfstype=squashfs,jffs2" @@ -93,6 +93,7 @@ CONFIG_EDAC_SUPPORT=y CONFIG_EINT_MTK=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y @@ -100,6 +101,7 @@ CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y @@ -108,6 +110,7 @@ CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y @@ -122,6 +125,7 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y CONFIG_GPIOLIB=y +CONFIG_GPIO_CDEV=y CONFIG_HANDLE_DOMAIN_IRQ=y # CONFIG_HARDENED_USERCOPY is not set CONFIG_HARDEN_BRANCH_PREDICTOR=y @@ -143,10 +147,10 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -# CONFIG_LEDS_UBNT_LEDBAR is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LTO_NONE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y # CONFIG_MACH_MT2701 is not set @@ -159,7 +163,6 @@ CONFIG_MACH_MT7629=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_MT6577_AUXADC is not set CONFIG_MEDIATEK_WATCHDOG=y CONFIG_MEMFD_CREATE=y CONFIG_MFD_SYSCON=y @@ -168,10 +171,9 @@ CONFIG_MIGRATION=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MTD_NAND_CORE=y CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y CONFIG_MTD_NAND_MTK_BMT=y -# CONFIG_MTD_PARSER_TRX is not set CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y @@ -187,14 +189,15 @@ CONFIG_MTK_INFRACFG=y # CONFIG_MTK_PMIC_WRAP is not set CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SPI_NAND=y -# CONFIG_MTK_THERMAL is not set CONFIG_MTK_TIMER=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NETFILTER=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_NET_VENDOR_MEDIATEK=y CONFIG_NLS=y CONFIG_NO_HZ_COMMON=y @@ -210,7 +213,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OUTER_CACHE=y @@ -241,6 +243,7 @@ CONFIG_PM=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y CONFIG_PWM_MEDIATEK=y # CONFIG_PWM_MTK_DISP is not set @@ -255,6 +258,7 @@ CONFIG_RPS=y # CONFIG_RTL8367S_GSW is not set CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_8250_NR_UARTS=3 @@ -265,12 +269,14 @@ CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_MT65XX=y CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y CONFIG_SRCU=y CONFIG_STACKTRACE=y # CONFIG_SWAP is not set From c283defa886f790ca3ab1c54f50b1a36d33d50ba Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Thu, 14 Apr 2022 12:45:01 +0800 Subject: [PATCH 16/75] mediatek: switch to 5.15 the SPI-NAND driver switch breaks dts compatibility. It's too much work to backport all ECC framework support to 5.10 so let's switch the target to 5.15 instead. Signed-off-by: Chuanhong Guo --- target/linux/mediatek/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index 2b4f240429..da3cf18cf6 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -8,8 +8,7 @@ BOARDNAME:=MediaTek Ralink ARM SUBTARGETS:=mt7622 mt7623 mt7629 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb -KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.15 +KERNEL_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ From ab7e53e5cce703c7a62efbe1d41fb94c2228a178 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 18 Apr 2022 15:04:25 +0200 Subject: [PATCH 17/75] ipq40xx: 5.10: fix ar40xx driver This commit is completely based on the work of adron-s: https://github.com/openwrt/openwrt/pull/4721#issuecomment-1101108651 The commit fixes the data corruption on TX packets. Packets are transmitted, but their contents are replaced with zeros. This error is caused by the lack of guard (50 ms) intervals between calibration phases. This error is treated by adding mdelay(50) to the calibration function code. In the original qca-ssda code [0], these mdelays were existing, but in the ar41xx.c they are gone. Tested on: - Fritz!Box 4040 - Fritz!Box 7530 - Mikrotik SXTsq 5AC - ZyXEL NBG6617 - [0] https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk/-/blob/NHSS.QSDK.11.4/src/init/ssdk_init.c#L2072 Suggested-by: Serhii Serhieiev Reviewed-by: Robert Marko Signed-off-by: Nick Hainke --- target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.c b/target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.c index f7ce42b9ff..d5ef7af151 100644 --- a/target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.c +++ b/target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.c @@ -936,6 +936,7 @@ ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) */ mdelay(2); } + mdelay(50); /*check malibu psgmii calibration done end..*/ @@ -954,6 +955,7 @@ ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) /* Polling interval to check PSGMII PLL in ESS is ready */ mdelay(2); } + mdelay(50); /* check dakota psgmii calibration done end..*/ @@ -961,6 +963,7 @@ ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) mdiobus_write(bus, 5, 0x1a, 0x3230); /* release phy psgmii RX 20bit */ mdiobus_write(bus, 5, 0x0, 0x005f); + mdelay(200); } static void From b2d802f8398b45ebda0a2658fdf5015169004e07 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Fri, 29 Apr 2022 10:44:51 +0800 Subject: [PATCH 18/75] mediatek: mt7623 enable arch-timer with a patch Last attempt on this has a typo and doen't work. It seems that this is a common problem occurring on every kernel bump, so let's enforce arch timer support for mt7623 with a patch instead. Fixes: 9a22943eb2 ("mediatek: 5.15: re-enable arch timer on MT7623 as well") Signed-off-by: Chuanhong Guo --- target/linux/mediatek/mt7623/config-5.15 | 7 ++---- .../103-mt7623-enable-arch-timer.patch | 25 +++++++++++++++++++ 2 files changed, 27 insertions(+), 5 deletions(-) create mode 100644 target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15 index 62672ec8fd..e39bc5d584 100644 --- a/target/linux/mediatek/mt7623/config-5.15 +++ b/target/linux/mediatek/mt7623/config-5.15 @@ -16,6 +16,8 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM=y CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # CONFIG_ARM_ATAG_DTB_COMPAT is not set CONFIG_ARM_CPU_SUSPEND=y # CONFIG_ARM_CPU_TOPOLOGY is not set @@ -246,7 +248,6 @@ CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARM_ARCH_TIMER=Y CONFIG_HAVE_SMP=y CONFIG_HDMI=y CONFIG_HID=y @@ -300,9 +301,7 @@ CONFIG_JBD2=y # CONFIG_JOYSTICK_ANALOG is not set # CONFIG_JOYSTICK_AS5011 is not set # CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_DB9 is not set # CONFIG_JOYSTICK_FSIA6B is not set -# CONFIG_JOYSTICK_GAMECON is not set # CONFIG_JOYSTICK_GF2K is not set # CONFIG_JOYSTICK_GRIP is not set # CONFIG_JOYSTICK_GRIP_MP is not set @@ -319,9 +318,7 @@ CONFIG_JBD2=y # CONFIG_JOYSTICK_SPACEORB is not set # CONFIG_JOYSTICK_STINGER is not set # CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_TURBOGRAFX is not set # CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_WALKERA0701 is not set # CONFIG_JOYSTICK_WARRIOR is not set # CONFIG_JOYSTICK_XPAD is not set # CONFIG_JOYSTICK_ZHENHUA is not set diff --git a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch new file mode 100644 index 0000000000..ea455c4721 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch @@ -0,0 +1,25 @@ +From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Fri, 29 Apr 2022 10:40:56 +0800 +Subject: [PATCH] arm: mediatek: select arch timer for mt7623 + +Signed-off-by: Chuanhong Guo +--- + arch/arm/mach-mediatek/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig +index 35a3430c7942..8a8d9142260a 100644 +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -26,6 +26,7 @@ config MACH_MT6592 + config MACH_MT7623 + bool "MediaTek MT7623 SoCs support" + default ARCH_MEDIATEK ++ select HAVE_ARM_ARCH_TIMER + + config MACH_MT7629 + bool "MediaTek MT7629 SoCs support" +-- +2.35.1 + From 5de8c3dc1f58f9894dad99ae4777b95131902b0a Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Fri, 29 Apr 2022 11:32:51 +0800 Subject: [PATCH 19/75] mediatek: mt7623: disable ecc engine support There's no board using nand on this target atm. Signed-off-by: Chuanhong Guo --- target/linux/mediatek/mt7623/config-5.15 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15 index e39bc5d584..9fef4bbee3 100644 --- a/target/linux/mediatek/mt7623/config-5.15 +++ b/target/linux/mediatek/mt7623/config-5.15 @@ -380,6 +380,7 @@ CONFIG_MODULES_USE_ELF_REL=y # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_NAND_ECC_MEDIATEK is not set CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPLIT_UIMAGE_FW=y @@ -400,7 +401,6 @@ CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y CONFIG_MTK_SMI=y -# CONFIG_MTK_SPI_NAND is not set CONFIG_MTK_THERMAL=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set From 852126680e21edc71c0c66561ae5a6d7479dcc67 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Fri, 29 Apr 2022 11:47:04 +0800 Subject: [PATCH 20/75] mediatek: mt7629: disable mtk thermal Manually edit kconfig to disable CONFIG_MTK_THERMAL Signed-off-by: Chuanhong Guo --- target/linux/mediatek/mt7629/config-5.15 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15 index 56e5bc6dd0..cb4db9d165 100644 --- a/target/linux/mediatek/mt7629/config-5.15 +++ b/target/linux/mediatek/mt7629/config-5.15 @@ -189,6 +189,7 @@ CONFIG_MTK_INFRACFG=y # CONFIG_MTK_PMIC_WRAP is not set CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y +# CONFIG_MTK_THERMAL is not set CONFIG_MTK_TIMER=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y From 27fac9c08f89ac2bf9556afefe8f98a7387fed9e Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 30 Apr 2022 14:24:41 +0100 Subject: [PATCH 21/75] kernel: backport patch to relax mtdblock NAND warning Instead of warning loudly about mtdblock devices being created, rather just warn if they are actually used. Signed-off-by: Daniel Golle --- .../400-mtdblock-warn-if-opened-on-NAND.patch | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 target/linux/generic/backport-5.15/400-mtdblock-warn-if-opened-on-NAND.patch diff --git a/target/linux/generic/backport-5.15/400-mtdblock-warn-if-opened-on-NAND.patch b/target/linux/generic/backport-5.15/400-mtdblock-warn-if-opened-on-NAND.patch new file mode 100644 index 0000000000..27c0e6c14b --- /dev/null +++ b/target/linux/generic/backport-5.15/400-mtdblock-warn-if-opened-on-NAND.patch @@ -0,0 +1,82 @@ +From 96a3295c351da82d7af99b2fc004a3cf9f4716a9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= +Date: Mon, 28 Mar 2022 18:11:08 +0200 +Subject: [PATCH] mtdblock: warn if opened on NAND +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Warning on every translated mtd partition results in excessive log noise +if this driver is loaded: + + nand: device found, Manufacturer ID: 0xc2, Chip ID: 0xf1 + nand: Macronix MX30LF1G18AC + nand: 128 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64 + mt7621-nand 1e003000.nand: ECC strength adjusted to 4 bits + read_bbt: found bbt at block 1023 + 10 fixed-partitions partitions found on MTD device mt7621-nand + Creating 10 MTD partitions on "mt7621-nand": + 0x000000000000-0x000000080000 : "Bootloader" + mtdblock: MTD device 'Bootloader' is NAND, please consider using UBI block devices instead. + 0x000000080000-0x000000100000 : "Config" + mtdblock: MTD device 'Config' is NAND, please consider using UBI block devices instead. + 0x000000100000-0x000000140000 : "Factory" + mtdblock: MTD device 'Factory' is NAND, please consider using UBI block devices instead. + 0x000000140000-0x000002000000 : "Kernel" + mtdblock: MTD device 'Kernel' is NAND, please consider using UBI block devices instead. + 0x000000540000-0x000002000000 : "ubi" + mtdblock: MTD device 'ubi' is NAND, please consider using UBI block devices instead. + 0x000002140000-0x000004000000 : "Kernel2" + mtdblock: MTD device 'Kernel2' is NAND, please consider using UBI block devices instead. + 0x000004000000-0x000004100000 : "wwan" + mtdblock: MTD device 'wwan' is NAND, please consider using UBI block devices instead. + 0x000004100000-0x000005100000 : "data" + mtdblock: MTD device 'data' is NAND, please consider using UBI block devices instead. + 0x000005100000-0x000005200000 : "rom-d" + mtdblock: MTD device 'rom-d' is NAND, please consider using UBI block devices instead. + 0x000005200000-0x000005280000 : "reserve" + mtdblock: MTD device 'reserve' is NAND, please consider using UBI block devices instead. + mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 21 + +This is more likely to annoy than to help users of embedded distros where +this driver is enabled by default. Making the blockdevs available does +not imply that they are in use, and warning about bootloader partitions +or other devices which obviously never will be mounted is more confusing +than helpful. + +Move the warning to open(), where it will be of more use - actually warning +anyone who mounts a file system on NAND using mtdblock. + +Fixes: e07403a8c6be ("mtdblock: Warn if added for a NAND device") +Signed-off-by: Bjørn Mork +Reviewed-by: Ezequiel Garcia +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20220328161108.87757-1-bjorn@mork.no +--- + drivers/mtd/mtdblock.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/mtd/mtdblock.c ++++ b/drivers/mtd/mtdblock.c +@@ -257,6 +257,10 @@ static int mtdblock_open(struct mtd_blkt + return 0; + } + ++ if (mtd_type_is_nand(mbd->mtd)) ++ pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", ++ mbd->tr->name, mbd->mtd->name); ++ + /* OK, it's not open. Create cache info for it */ + mtdblk->count = 1; + mutex_init(&mtdblk->cache_mutex); +@@ -322,10 +326,6 @@ static void mtdblock_add_mtd(struct mtd_ + if (!(mtd->flags & MTD_WRITEABLE)) + dev->mbd.readonly = 1; + +- if (mtd_type_is_nand(mtd)) +- pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", +- tr->name, mtd->name); +- + if (add_mtd_blktrans_dev(&dev->mbd)) + kfree(dev); + } From 2acf355e56fa099bbd4ac881aed642b8df6022e7 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 30 Apr 2022 15:14:01 +0100 Subject: [PATCH 22/75] kernel: don't parse FIT partition on NAND-backed mtdblock ubiblock devices should be used on NAND flash to store the uImage.FIT in case the bootloader supports that -- otherwise only rootfs is stored in UBI while the uImage.FIT contains only the kernel and dtb. Hence there is no need to enable parsing partitions on NAND mtdblock devices, it is even responsible for the ugly warning on-opening of the mtdblock device now. Just don't do it. Signed-off-by: Daniel Golle --- .../generic/hack-5.15/410-block-fit-partition-parser.patch | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch b/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch index 5edacd5eae..7539bc8627 100644 --- a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch +++ b/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch @@ -112,13 +112,12 @@ dev->gd = gd; --- a/drivers/mtd/mtd_blkdevs.c +++ b/drivers/mtd/mtd_blkdevs.c -@@ -345,6 +345,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt +@@ -345,6 +345,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt gd->first_minor = (new->devnum) << tr->part_bits; gd->minors = 1 << tr->part_bits; gd->fops = &mtd_block_ops; -+#ifdef CONFIG_FIT_PARTITION -+ gd->flags |= GENHD_FL_EXT_DEVT; -+#endif ++ if (IS_ENABLED(CONFIG_FIT_PARTITION) && !mtd_type_is_nand(new->mtd)) ++ gd->flags |= GENHD_FL_EXT_DEVT; if (tr->part_bits) if (new->devnum < 26) From 5d135fcf9d46835caea4eb88820ca129dc1bab96 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 30 Apr 2022 15:41:13 +0100 Subject: [PATCH 23/75] mediatek: backport recent DTS improvements for MT7622 SoC Daniel Golle: 190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch Rui Salvaterra: 191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch 192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch Signed-off-by: Daniel Golle --- ...-dts-mediatek-mt7622-fix-GICv2-range.patch | 106 ++++++++++++++ ...mt7622-specify-the-L2-cache-topology.patch | 132 ++++++++++++++++++ ...2-specify-the-number-of-DMA-requests.patch | 122 ++++++++++++++++ 3 files changed, 360 insertions(+) create mode 100644 target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch create mode 100644 target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch create mode 100644 target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch diff --git a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch new file mode 100644 index 0000000000..39a9770d98 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch @@ -0,0 +1,106 @@ +From patchwork Tue Apr 26 19:51:36 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 12827872 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF + for ; + Tue, 26 Apr 2022 19:53:05 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; + d=lists.infradead.org; s=bombadil.20210309; h=Sender: + Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: + List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: + From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: + Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: + List-Owner; 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+ interrupt-parent = <&gic>; + reg = <0 0x10310000 0 0x1000>, +- <0 0x10320000 0 0x1000>, ++ <0 0x1032f000 0 0x2000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + }; diff --git a/target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch b/target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch new file mode 100644 index 0000000000..8851fefbb3 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch @@ -0,0 +1,132 @@ +From patchwork Thu Apr 28 22:57:55 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Rui Salvaterra +X-Patchwork-Id: 12831311 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 49367C433EF + for ; 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+ Thu, 28 Apr 2022 15:58:06 -0700 (PDT) +From: Rui Salvaterra +To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + linux-kernel@vger.kernel.org +Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, + Rui Salvaterra +Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology +Date: Thu, 28 Apr 2022 23:57:55 +0100 +Message-Id: <20220428225755.785153-1-rsalvaterra@gmail.com> +X-Mailer: git-send-email 2.36.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220428_155811_895571_B63D2806 +X-CRM114-Status: GOOD ( 10.27 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +On an MT7622 system, the kernel complains of not being able to detect the cache +hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in +order to fix this. + +Signed-off-by: Rui Salvaterra +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -80,6 +80,7 @@ + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; ++ next-level-cache = <&L2>; + }; + + cpu1: cpu@1 { +@@ -94,6 +95,12 @@ + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; ++ next-level-cache = <&L2>; ++ }; ++ ++ L2: l2-cache { ++ compatible = "cache"; ++ cache-level = <2>; + }; + }; + diff --git a/target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch b/target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch new file mode 100644 index 0000000000..f8100b20b8 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch @@ -0,0 +1,122 @@ +From patchwork Fri Apr 29 08:42:25 2022 +Content-Type: text/plain; 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+ Fri, 29 Apr 2022 01:42:32 -0700 (PDT) +Received: from crystalwell.adg.lan (a109-49-0-175.cpe.netcabo.pt. + [109.49.0.175]) by smtp.gmail.com with ESMTPSA id + el10-20020a170907284a00b006f3ef214e32sm429064ejc.152.2022.04.29.01.42.31 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Fri, 29 Apr 2022 01:42:31 -0700 (PDT) +From: Rui Salvaterra +To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + linux-kernel@vger.kernel.org +Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, + Rui Salvaterra +Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests +Date: Fri, 29 Apr 2022 09:42:25 +0100 +Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com> +X-Mailer: git-send-email 2.36.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220429_014236_944696_097D1E73 +X-CRM114-Status: UNSURE ( 8.85 ) +X-CRM114-Notice: Please train this message. +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +The MT7622 device tree never bothered to specify the number of virtual DMA +channels for the HSDMA controller, always falling back to the default value of +3. Make this value explicit, in order to avoid the following dmesg notification: + +mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property + +Signed-off-by: Rui Salvaterra +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -940,6 +940,7 @@ + clock-names = "hsdma"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; + #dma-cells = <1>; ++ dma-requests = <3>; + }; + + pcie_mirror: pcie-mirror@10000400 { From 9b4041fa2e10f6417f41fdc727752e60df7da3e6 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 30 Apr 2022 15:17:46 +0100 Subject: [PATCH 24/75] mediatek: refresh patches for Linux 5.15 Run `make target/linux/refresh` to align patches with OpenWrt style. Signed-off-by: Daniel Golle --- .../103-mt7623-enable-arch-timer.patch | 5 ---- ...-infrastructure-to-support-hardware-.patch | 26 ++++++------------- ...ew-helper-to-retrieve-the-ECC-contex.patch | 7 +---- ...vide-a-helper-to-retrieve-a-pileline.patch | 11 ++------ ...mem-Introduce-a-capability-structure.patch | 17 ++++-------- ...ck-the-controller-extra-capabilities.patch | 7 +---- ...l-the-spi_mem_dtr_supports_op-helper.patch | 23 +++++----------- ...an-ecc-parameter-to-the-spi_mem_op-s.patch | 9 +------ ...lay-a-little-bit-the-dirmap-creation.patch | 9 ++----- ...te-direct-mapping-descriptors-for-EC.patch | 15 +++-------- ...d-nand-fix-ecc-parameters-for-mt7622.patch | 13 +++------- ...ver-for-MTK-SPI-NAND-Flash-Interface.patch | 14 ++-------- ...-also-parse-nand-ecc-engine-if-avail.patch | 7 +---- ...dts-mediatek-add-mtk-snfi-for-mt7622.patch | 7 +---- .../121-hack-spi-nand-1b-bbm.patch | 4 +-- .../330-snand-mtk-bmt-support.patch | 6 ++--- ...ek-Split-PCIe-node-for-MT2712-and-MT.patch | 4 +-- ...s-mediatek-add-mt7622-pcie-slot-node.patch | 4 +-- ...dts-mediatek-Update-mt7629-PCIe-node.patch | 4 +-- ...ediatek-add-support-for-coherent-DMA.patch | 4 +-- ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 2 +- .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 2 +- 22 files changed, 53 insertions(+), 147 deletions(-) diff --git a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch index ea455c4721..04df7b927b 100644 --- a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch +++ b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch @@ -8,8 +8,6 @@ Signed-off-by: Chuanhong Guo arch/arm/mach-mediatek/Kconfig | 1 + 1 file changed, 1 insertion(+) -diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig -index 35a3430c7942..8a8d9142260a 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -26,6 +26,7 @@ config MACH_MT6592 @@ -20,6 +18,3 @@ index 35a3430c7942..8a8d9142260a 100644 config MACH_MT7629 bool "MediaTek MT7629 SoCs support" --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch index b6b069d234..7fb62e7403 100644 --- a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch +++ b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch @@ -24,11 +24,9 @@ Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@b include/linux/mtd/nand.h | 28 +++++++++++++ 3 files changed, 123 insertions(+), 3 deletions(-) -diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c -index 5e13a03d2b32..b228b4d13b7a 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c -@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct nand_device *nand) +@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand); break; case NAND_ECC_ENGINE_TYPE_ON_HOST: @@ -39,7 +37,7 @@ index 5e13a03d2b32..b228b4d13b7a 100644 break; default: pr_err("Missing ECC engine type\n"); -@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct nand_device *nand) +@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct { switch (nand->ecc.ctx.conf.engine_type) { case NAND_ECC_ENGINE_TYPE_ON_HOST: @@ -48,7 +46,7 @@ index 5e13a03d2b32..b228b4d13b7a 100644 break; case NAND_ECC_ENGINE_TYPE_NONE: case NAND_ECC_ENGINE_TYPE_SOFT: -@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_device *nand) +@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_ /* Look for the ECC engine to use */ ret = nanddev_get_ecc_engine(nand); if (ret) { @@ -59,8 +57,6 @@ index 5e13a03d2b32..b228b4d13b7a 100644 return ret; } -diff --git a/drivers/mtd/nand/ecc.c b/drivers/mtd/nand/ecc.c -index 6c43dfda01d4..078f5ec38de3 100644 --- a/drivers/mtd/nand/ecc.c +++ b/drivers/mtd/nand/ecc.c @@ -96,6 +96,12 @@ @@ -76,7 +72,7 @@ index 6c43dfda01d4..078f5ec38de3 100644 /** * nand_ecc_init_ctx - Init the ECC engine context -@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand) +@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_ } EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine); @@ -165,15 +161,12 @@ index 6c43dfda01d4..078f5ec38de3 100644 MODULE_LICENSE("GPL"); MODULE_AUTHOR("Miquel Raynal "); MODULE_DESCRIPTION("Generic ECC engine"); -diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h -index 32fc7edf65b3..4ddd20fe9c9e 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h -@@ -263,12 +263,36 @@ struct nand_ecc_engine_ops { - struct nand_page_io_req *req); +@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops { }; -+/** + /** + * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated + * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value + * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly @@ -188,7 +181,7 @@ index 32fc7edf65b3..4ddd20fe9c9e 100644 + NAND_ECC_ENGINE_INTEGRATION_EXTERNAL, +}; + - /** ++/** * struct nand_ecc_engine - ECC engine abstraction for NAND devices + * @dev: Host device + * @node: Private field for registration time @@ -206,7 +199,7 @@ index 32fc7edf65b3..4ddd20fe9c9e 100644 }; void of_get_nand_ecc_user_config(struct nand_device *nand); -@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_device *nand, +@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_ int nand_ecc_finish_io_req(struct nand_device *nand, struct nand_page_io_req *req); bool nand_ecc_is_strong_enough(struct nand_device *nand); @@ -219,6 +212,3 @@ index 32fc7edf65b3..4ddd20fe9c9e 100644 #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch index 6522507786..61a39ee0e5 100644 --- a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch +++ b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch @@ -15,11 +15,9 @@ Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@b include/linux/mtd/nand.h | 5 +++++ 1 file changed, 5 insertions(+) -diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h -index 4ddd20fe9c9e..b617efa0a881 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h -@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos); +@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device * int nanddev_ecc_engine_init(struct nand_device *nand); void nanddev_ecc_engine_cleanup(struct nand_device *nand); @@ -31,6 +29,3 @@ index 4ddd20fe9c9e..b617efa0a881 100644 /* BBT related functions */ enum nand_bbt_block_status { NAND_BBT_BLOCK_STATUS_UNKNOWN, --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch index ce353a9226..29b62880ab 100644 --- a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch +++ b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch @@ -21,11 +21,9 @@ Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@b include/linux/mtd/nand.h | 1 + 2 files changed, 32 insertions(+) -diff --git a/drivers/mtd/nand/ecc.c b/drivers/mtd/nand/ecc.c -index 078f5ec38de3..5250764cedee 100644 --- a/drivers/mtd/nand/ecc.c +++ b/drivers/mtd/nand/ecc.c -@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(struct nand_device *nand) +@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru } EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); @@ -63,11 +61,9 @@ index 078f5ec38de3..5250764cedee 100644 MODULE_LICENSE("GPL"); MODULE_AUTHOR("Miquel Raynal "); MODULE_DESCRIPTION("Generic ECC engine"); -diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h -index b617efa0a881..615b3e3a3920 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h -@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand); +@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_ struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); @@ -75,6 +71,3 @@ index b617efa0a881..615b3e3a3920 100644 #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch index bcd2ee8004..1e7f572dd6 100644 --- a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch +++ b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch @@ -23,15 +23,12 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@b include/linux/spi/spi.h | 3 +++ 2 files changed, 14 insertions(+) -diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h -index 85e2ff7b840d..38e5d45c9842 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h -@@ -285,6 +285,17 @@ struct spi_controller_mem_ops { - unsigned long timeout_ms); +@@ -286,6 +286,17 @@ struct spi_controller_mem_ops { }; -+/** + /** + * struct spi_controller_mem_caps - SPI memory controller capabilities + * @dtr: Supports DTR operations + */ @@ -42,11 +39,10 @@ index 85e2ff7b840d..38e5d45c9842 100644 +#define spi_mem_controller_is_capable(ctlr, cap) \ + ((ctlr)->mem_caps && (ctlr)->mem_caps->cap) + - /** ++/** * struct spi_mem_driver - SPI memory driver * @spidrv: inherit from a SPI driver -diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h -index 6b0b686f6f90..8ac58b1a2a9f 100644 + * @probe: probe a SPI memory. Usually where detection/initialization takes --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -23,6 +23,7 @@ struct software_node; @@ -57,7 +53,7 @@ index 6b0b686f6f90..8ac58b1a2a9f 100644 /* * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, -@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch +@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill * @mem_ops: optimized/dedicated operations for interactions with SPI memory. * This field is optional and should only be implemented if the * controller has native support for memory like operations. @@ -73,6 +69,3 @@ index 6b0b686f6f90..8ac58b1a2a9f 100644 /* gpio chip select */ int *cs_gpios; --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch index 20e7bac651..9f01fdb835 100644 --- a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch +++ b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch @@ -22,11 +22,9 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@b drivers/spi/spi-mem.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) -diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c -index 37f4443ce9a0..86e6597bc3dc 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c -@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); +@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o bool spi_mem_default_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -51,6 +49,3 @@ index 37f4443ce9a0..86e6597bc3dc 100644 return spi_mem_check_buswidth(mem, op); } --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch index efc0ed526c..0c9e723151 100644 --- a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch +++ b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch @@ -23,11 +23,9 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@b include/linux/spi/spi-mem.h | 11 ----------- 4 files changed, 2 insertions(+), 34 deletions(-) -diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c -index 101cc71bffa7..2c98d6a9a2aa 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c -@@ -1252,10 +1252,7 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, +@@ -1230,10 +1230,7 @@ static bool cqspi_supports_mem_op(struct if (!(all_true || all_false)) return false; @@ -39,11 +37,9 @@ index 101cc71bffa7..2c98d6a9a2aa 100644 } static int cqspi_of_get_flash_pdata(struct platform_device *pdev, -diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c -index 86e6597bc3dc..ed966d8129eb 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c -@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem, +@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc return true; } @@ -60,11 +56,9 @@ index 86e6597bc3dc..ed966d8129eb 100644 bool spi_mem_default_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { -diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c -index 45889947afed..e895df09896a 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c -@@ -335,8 +335,6 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, +@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi static bool mxic_spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -73,7 +67,7 @@ index 45889947afed..e895df09896a 100644 if (op->data.buswidth > 8 || op->addr.buswidth > 8 || op->dummy.buswidth > 8 || op->cmd.buswidth > 8) return false; -@@ -348,13 +346,7 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem, +@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str if (op->addr.nbytes > 7) return false; @@ -88,11 +82,9 @@ index 45889947afed..e895df09896a 100644 } static int mxic_spi_mem_exec_op(struct spi_mem *mem, -diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h -index 38e5d45c9842..4a1bfe689872 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h -@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, +@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat bool spi_mem_default_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); @@ -103,7 +95,7 @@ index 38e5d45c9842..4a1bfe689872 100644 #else static inline int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, -@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, +@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct { return false; } @@ -117,6 +109,3 @@ index 38e5d45c9842..4a1bfe689872 100644 #endif /* CONFIG_SPI_MEM */ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch index fd9e9e2c48..6d7e47650b 100644 --- a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch +++ b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch @@ -26,11 +26,9 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@b include/linux/spi/spi-mem.h | 4 ++++ 2 files changed, 9 insertions(+) -diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c -index ed966d8129eb..f38ac31961c9 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c -@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, +@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct return false; } @@ -42,8 +40,6 @@ index ed966d8129eb..f38ac31961c9 100644 return spi_mem_check_buswidth(mem, op); } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); -diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h -index 4a1bfe689872..2ba044d0d5e5 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,7 @@ enum spi_mem_data_dir { @@ -74,6 +70,3 @@ index 4a1bfe689872..2ba044d0d5e5 100644 }; #define spi_mem_controller_is_capable(ctlr, cap) \ --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch index d8c0e1bcd8..192b1221ed 100644 --- a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch +++ b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch @@ -16,11 +16,9 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@b drivers/mtd/nand/spi/core.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c -index 2c8685f1f2fa..bb6b026b558b 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -1208,14 +1208,6 @@ static int spinand_init(struct spinand_device *spinand) +@@ -1210,14 +1210,6 @@ static int spinand_init(struct spinand_d if (ret) goto err_free_bufs; @@ -35,7 +33,7 @@ index 2c8685f1f2fa..bb6b026b558b 100644 ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); if (ret) goto err_manuf_cleanup; -@@ -1250,6 +1242,14 @@ static int spinand_init(struct spinand_device *spinand) +@@ -1252,6 +1244,14 @@ static int spinand_init(struct spinand_d mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; @@ -50,6 +48,3 @@ index 2c8685f1f2fa..bb6b026b558b 100644 return 0; err_cleanup_ecc_engine: --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch index ee3a6d384f..86df0270d8 100644 --- a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch +++ b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch @@ -27,11 +27,9 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@b include/linux/mtd/spinand.h | 2 ++ 2 files changed, 35 insertions(+), 2 deletions(-) -diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c -index bb6b026b558b..ff8336870bc0 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand, +@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st } } @@ -43,7 +41,7 @@ index bb6b026b558b..ff8336870bc0 100644 while (nbytes) { ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); -@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand, +@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str req->ooblen); } @@ -55,7 +53,7 @@ index bb6b026b558b..ff8336870bc0 100644 while (nbytes) { ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); -@@ -865,6 +871,31 @@ static int spinand_create_dirmap(struct spinand_device *spinand, +@@ -865,6 +871,31 @@ static int spinand_create_dirmap(struct spinand->dirmaps[plane].rdesc = desc; @@ -87,11 +85,9 @@ index bb6b026b558b..ff8336870bc0 100644 return 0; } -diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h -index 6988956b8492..3aa28240a77f 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h -@@ -389,6 +389,8 @@ struct spinand_info { +@@ -391,6 +391,8 @@ struct spinand_info { struct spinand_dirmap { struct spi_mem_dirmap_desc *wdesc; struct spi_mem_dirmap_desc *rdesc; @@ -100,6 +96,3 @@ index 6988956b8492..3aa28240a77f 100644 }; /** --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch index 7dbcf2fcda..e1c9493a1c 100644 --- a/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch +++ b/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch @@ -28,8 +28,6 @@ Signed-off-by: Chuanhong Guo drivers/mtd/nand/raw/mtk_ecc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -diff --git a/drivers/mtd/nand/raw/mtk_ecc.c b/drivers/mtd/nand/raw/mtk_ecc.c -index c437d97debb8..ec9d1fb07006 100644 --- a/drivers/mtd/nand/raw/mtk_ecc.c +++ b/drivers/mtd/nand/raw/mtk_ecc.c @@ -43,6 +43,7 @@ @@ -40,7 +38,7 @@ index c437d97debb8..ec9d1fb07006 100644 const u8 *ecc_strength; const u32 *ecc_regs; u8 num_ecc_strength; -@@ -76,7 +77,7 @@ static const u8 ecc_strength_mt2712[] = { +@@ -76,7 +77,7 @@ static const u8 ecc_strength_mt2712[] = }; static const u8 ecc_strength_mt7622[] = { @@ -49,7 +47,7 @@ index c437d97debb8..ec9d1fb07006 100644 }; enum mtk_ecc_regs { -@@ -221,7 +222,7 @@ void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, +@@ -221,7 +222,7 @@ void mtk_ecc_get_stats(struct mtk_ecc *e for (i = 0; i < sectors; i++) { offset = (i >> 2) << 2; err = readl(ecc->regs + ECC_DECENUM0 + offset); @@ -66,7 +64,7 @@ index c437d97debb8..ec9d1fb07006 100644 .ecc_strength = ecc_strength_mt2701, .ecc_regs = mt2701_ecc_regs, .num_ecc_strength = 20, -@@ -459,6 +461,7 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { +@@ -459,6 +461,7 @@ static const struct mtk_ecc_caps mtk_ecc static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { .err_mask = 0x7f, @@ -74,7 +72,7 @@ index c437d97debb8..ec9d1fb07006 100644 .ecc_strength = ecc_strength_mt2712, .ecc_regs = mt2712_ecc_regs, .num_ecc_strength = 23, -@@ -468,10 +471,11 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { +@@ -468,10 +471,11 @@ static const struct mtk_ecc_caps mtk_ecc }; static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { @@ -88,6 +86,3 @@ index c437d97debb8..ec9d1fb07006 100644 .ecc_mode_shift = 4, .parity_bits = 13, .pg_irq_sel = 0, --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch index 2d380064b8..b77b4ad4c4 100644 --- a/target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch +++ b/target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch @@ -33,11 +33,9 @@ Changes since v5: 3 files changed, 1481 insertions(+) create mode 100644 drivers/spi/spi-mtk-snfi.c -diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index 6c28ca232444..83c3c2b57a22 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -590,6 +590,16 @@ config SPI_MTK_NOR +@@ -530,6 +530,16 @@ config SPI_MTK_NOR SPI interface as well as several SPI NOR specific instructions via SPI MEM interface. @@ -54,11 +52,9 @@ index 6c28ca232444..83c3c2b57a22 100644 config SPI_NPCM_FIU tristate "Nuvoton NPCM FLASH Interface Unit" depends on ARCH_NPCM || COMPILE_TEST -diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index 3aa28ed3f761..51541ff17e67 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -76,6 +76,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o +@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52x obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o @@ -66,9 +62,6 @@ index 3aa28ed3f761..51541ff17e67 100644 obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o -diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c -new file mode 100644 -index 000000000000..2c556e304673 --- /dev/null +++ b/drivers/spi/spi-mtk-snfi.c @@ -0,0 +1,1470 @@ @@ -1542,6 +1535,3 @@ index 000000000000..2c556e304673 +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Chuanhong Guo "); +MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch index 80d482b6a5..01d9d12088 100644 --- a/target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch +++ b/target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch @@ -14,11 +14,9 @@ Signed-off-by: Chuanhong Guo drivers/mtd/nand/ecc-mtk.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c -index c64c3c45cdbc..79c7622af563 100644 --- a/drivers/mtd/nand/ecc-mtk.c +++ b/drivers/mtd/nand/ecc-mtk.c -@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) +@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de struct mtk_ecc *ecc = NULL; struct device_node *np; @@ -30,6 +28,3 @@ index c64c3c45cdbc..79c7622af563 100644 if (np) { ecc = mtk_ecc_get(np); of_node_put(np); --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch index 81452ade25..d5285676fe 100644 --- a/target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch +++ b/target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch @@ -12,11 +12,9 @@ Signed-off-by: Chuanhong Guo arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -index 890a942ec608..8cdb8cc94bd3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -545,6 +545,18 @@ nandc: nfi@1100d000 { +@@ -552,6 +552,18 @@ status = "disabled"; }; @@ -35,6 +33,3 @@ index 890a942ec608..8cdb8cc94bd3 100644 bch: ecc@1100e000 { compatible = "mediatek,mt7622-ecc"; reg = <0 0x1100e000 0 0x1000>; --- -2.35.1 - diff --git a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch index eccd363395..770a7ff9bd 100644 --- a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch +++ b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch @@ -1,6 +1,6 @@ --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -715,7 +715,7 @@ static int spinand_mtd_write(struct mtd_ +@@ -714,7 +714,7 @@ static int spinand_mtd_write(struct mtd_ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) { struct spinand_device *spinand = nand_to_spinand(nand); @@ -9,7 +9,7 @@ struct nand_page_io_req req = { .pos = *pos, .ooblen = sizeof(marker), -@@ -726,7 +726,7 @@ static bool spinand_isbad(struct nand_de +@@ -725,7 +725,7 @@ static bool spinand_isbad(struct nand_de spinand_select_target(spinand, pos->target); spinand_read_page(spinand, &req); diff --git a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch index 26ec7eada0..48bfb0d358 100644 --- a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch +++ b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch @@ -8,7 +8,7 @@ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { -@@ -1331,6 +1332,7 @@ static int spinand_probe(struct spi_mem +@@ -1332,6 +1333,7 @@ static int spinand_probe(struct spi_mem if (ret) return ret; @@ -16,7 +16,7 @@ ret = mtd_device_register(mtd, NULL, 0); if (ret) goto err_spinand_cleanup; -@@ -1338,6 +1340,7 @@ static int spinand_probe(struct spi_mem +@@ -1339,6 +1341,7 @@ static int spinand_probe(struct spi_mem return 0; err_spinand_cleanup: @@ -24,7 +24,7 @@ spinand_cleanup(spinand); return ret; -@@ -1356,6 +1359,7 @@ static int spinand_remove(struct spi_mem +@@ -1357,6 +1360,7 @@ static int spinand_remove(struct spi_mem if (ret) return ret; diff --git a/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch b/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch index a1f744f5da..0c9b6d915b 100644 --- a/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch +++ b/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch @@ -138,7 +138,7 @@ Signed-off-by: Matthias Brugger --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -292,18 +292,16 @@ +@@ -302,18 +302,16 @@ }; }; @@ -194,7 +194,7 @@ Signed-off-by: Matthias Brugger &pio { --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -802,75 +802,83 @@ +@@ -807,75 +807,83 @@ #reset-cells = <1>; }; diff --git a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch index 25a5eb87c7..4ac5685c2c 100644 --- a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ b/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -842,6 +842,12 @@ +@@ -847,6 +847,12 @@ #address-cells = <0>; #interrupt-cells = <1>; }; @@ -13,7 +13,7 @@ }; pcie1: pcie@1a145000 { -@@ -880,6 +886,12 @@ +@@ -885,6 +891,12 @@ #address-cells = <0>; #interrupt-cells = <1>; }; diff --git a/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch index 8ce4638357..252ef080f5 100644 --- a/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch +++ b/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch @@ -149,7 +149,7 @@ Signed-off-by: chuanjia.liu &pciephy1 { --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -377,16 +377,21 @@ +@@ -382,16 +382,21 @@ #reset-cells = <1>; }; @@ -177,7 +177,7 @@ Signed-off-by: chuanjia.liu clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, <&pciesys CLK_PCIE_P0_AHB_EN>, <&pciesys CLK_PCIE_P1_AUX_EN>, -@@ -407,21 +412,19 @@ +@@ -412,21 +417,19 @@ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; diff --git a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index 571a5f7d48..8a577459b0 100644 --- a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -830,6 +830,9 @@ +@@ -835,6 +835,9 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; status = "disabled"; @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; -@@ -874,6 +877,9 @@ +@@ -879,6 +882,9 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; status = "disabled"; diff --git a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch index 987513eb45..b15d04f8bb 100644 --- a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ b/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -308,7 +308,7 @@ +@@ -318,7 +318,7 @@ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and * SATA functions. i.e. output-high: PCIe, output-low: SATA */ diff --git a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch index 72211af588..2a863aecf9 100644 --- a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ b/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -635,5 +635,28 @@ +@@ -645,5 +645,28 @@ }; &wmac { From eb96f1413a6a7f5c2a48fece0eaeafb6e88ad62b Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 30 Apr 2022 15:48:58 +0100 Subject: [PATCH 25/75] mediatek: enable multi-core scheduling Set CONFIG_SCHED_MC in config-5.15 to have make the scheduler aware of shared caches. Reported-by: Rui Salvaterra Signed-off-by: Daniel Golle --- target/linux/mediatek/mt7622/config-5.15 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index c613fd0dcb..190782cb78 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -384,6 +384,7 @@ CONFIG_RTC_DRV_MT7622=y CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTL8367S_GSW=y CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y CONFIG_SCSI=y CONFIG_SCSI_COMMON=y # CONFIG_SECTION_MISMATCH_WARN_ONLY is not set From 593fe90b53124af7082b2fe73803e5b1f6793bb9 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 30 Apr 2022 15:51:21 +0100 Subject: [PATCH 26/75] mediatek: remove left-overs from Linux 5.10 Remove patches and configuration for Linux 5.10 which have been left in the tree despite the target having been switched to Linux 5.15. Fixes: c283defa88 ("mediatek: switch to 5.15") Signed-off-by: Daniel Golle --- target/linux/mediatek/mt7622/config-5.10 | 465 ------------- target/linux/mediatek/mt7623/config-5.10 | 633 ------------------ target/linux/mediatek/mt7629/config-5.10 | 305 --------- .../100-dts-update-mt7622-rfb1.patch | 119 ---- .../101-dts-update-mt7629-rfb.patch | 60 -- .../105-dts-mt7622-enable-pstore.patch | 25 - .../110-dts-fix-bpi2-console.patch | 10 - .../111-dts-fix-bpi64-console.patch | 11 - .../112-dts-fix-bpi64-lan-names.patch | 37 - .../113-dts-fix-bpi64-leds-and-buttons.patch | 56 -- .../114-dts-bpi64-disable-rtc.patch | 21 - .../115-dts-bpi64-add-snand-support.patch | 41 -- .../130-dts-mt7629-add-snand-support.patch | 77 --- .../131-dts-mt7622-add-snand-support.patch | 81 --- ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 18 - ...s-mt7623-eip97-inside-secure-support.patch | 23 - .../160-dts-mt7623-bpi-r2-earlycon.patch | 11 - ...1-dts-mt7623-bpi-r2-mmc-device-order.patch | 11 - .../162-dts-mt7623-bpi-r2-led-aliases.patch | 29 - ...163-dts-mt7623-bpi-r2-ethernet-alias.patch | 10 - ...convert-mediatek-musb.txt-to-YAML-sc.patch | 195 ------ ...-mediatek-musb-add-mt8516-compatbile.patch | 25 - ...s-usb-mtk-musb-add-MT7623-compatible.patch | 23 - ...arm-dts-mt7623-add-musb-device-nodes.patch | 69 -- ...80-dts-mt7622-bpi-r64-add-mt7531-irq.patch | 13 - ...-phy-phy-mtk-tphy-Add-hifsys-support.patch | 66 -- .../330-mtk-snand-bmt-support.patch | 36 - .../331-mt7622-rfb1-enable-bmt.patch | 11 - .../360-mtd-add-mtk-snand-driver.patch | 21 - ...ypto-add-eip97-inside-secure-support.patch | 27 - ...01-crypto-fix-eip97-cache-incoherent.patch | 26 - .../patches-5.10/410-bt-mtk-serial-fix.patch | 33 - ...or-add-support-for-Winbond-W25Q512JV.patch | 28 - .../500-gsw-rtl8367s-mt7622-support.patch | 25 - ...mediatek-add-flow-offload-for-mt7623.patch | 24 - ...ngs-PCI-Mediatek-Update-PCIe-binding.patch | 415 ------------ ...e-regmap-to-get-shared-pcie-cfg-base.patch | 217 ------ ...ek-Split-PCIe-node-for-MT2712-MT7622.patch | 417 ------------ ...dts-mediatek-Update-mt7629-PCIe-node.patch | 203 ------ ...diatek-fix-clearing-interrupt-status.patch | 24 - ..._eth_soc-fix-return-values-and-refac.patch | 128 ---- ...pers-to-extract-clause-45-regad-and-.patch | 53 -- ..._eth_soc-implement-Clause-45-MDIO-ac.patch | 128 ---- ...ernet-mtk_eth_soc-announce-2500baseT.patch | 10 - ...ediatek-add-support-for-coherent-DMA.patch | 96 --- .../721-dts-mt7622-mediatek-fix-300mhz.patch | 27 - .../patches-5.10/800-ubnt-ledbar-driver.patch | 29 - ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 65 -- .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 31 - 49 files changed, 4508 deletions(-) delete mode 100644 target/linux/mediatek/mt7622/config-5.10 delete mode 100644 target/linux/mediatek/mt7623/config-5.10 delete mode 100644 target/linux/mediatek/mt7629/config-5.10 delete mode 100644 target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch delete mode 100644 target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch delete mode 100644 target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch delete mode 100644 target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch delete mode 100644 target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch delete mode 100644 target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch delete mode 100644 target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch delete mode 100644 target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch delete mode 100644 target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch delete mode 100644 target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch delete mode 100644 target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch delete mode 100644 target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch delete mode 100644 target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch delete mode 100644 target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch delete mode 100644 target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch delete mode 100644 target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch delete mode 100644 target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch delete mode 100644 target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch delete mode 100644 target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch delete mode 100644 target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch delete mode 100644 target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch delete mode 100644 target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch delete mode 100644 target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch delete mode 100644 target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch delete mode 100644 target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch delete mode 100644 target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch delete mode 100644 target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch delete mode 100644 target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch delete mode 100644 target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch delete mode 100644 target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch delete mode 100644 target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch delete mode 100644 target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch delete mode 100644 target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch delete mode 100644 target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch delete mode 100644 target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch delete mode 100644 target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch delete mode 100644 target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch delete mode 100644 target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch diff --git a/target/linux/mediatek/mt7622/config-5.10 b/target/linux/mediatek/mt7622/config-5.10 deleted file mode 100644 index 89ebc61576..0000000000 --- a/target/linux/mediatek/mt7622/config-5.10 +++ /dev/null @@ -1,465 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_CNP is not set -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_PTR_AUTH is not set -# CONFIG_ARM64_SVE is not set -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -CONFIG_COMMON_CLK_MT7622=y -CONFIG_COMMON_CLK_MT7622_AUDSYS=y -CONFIG_COMMON_CLK_MT7622_ETHSYS=y -CONFIG_COMMON_CLK_MT7622_HIFSYS=y -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8183=y -# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set -# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set -# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set -# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set -# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set -# CONFIG_COMMON_CLK_MT8183_MMSYS is not set -# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set -# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_KPP=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -# CONFIG_KEYBOARD_MTK_PMIC is not set -CONFIG_LEDS_UBNT_LEDBAR=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_EFUSE=y -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SPI_NAND=y -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_CONFIGFS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_OVERLAY=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6797 is not set -CONFIG_PINCTRL_MT7622=y -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_BLK is not set -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZO_COMPRESS is not set -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -# CONFIG_SND_SOC_MT6359 is not set -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-5.10 b/target/linux/mediatek/mt7623/config-5.10 deleted file mode 100644 index 3d017400a0..0000000000 --- a/target/linux/mediatek/mt7623/config-5.10 +++ /dev/null @@ -1,633 +0,0 @@ -# CONFIG_AIO is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_LED=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_CMDLINE_PARSER=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLEANCACHE=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y -CONFIG_COMMON_CLK_MT2701_AUDSYS=y -CONFIG_COMMON_CLK_MT2701_BDPSYS=y -CONFIG_COMMON_CLK_MT2701_ETHSYS=y -CONFIG_COMMON_CLK_MT2701_G3DSYS=y -CONFIG_COMMON_CLK_MT2701_HIFSYS=y -CONFIG_COMMON_CLK_MT2701_IMGSYS=y -CONFIG_COMMON_CLK_MT2701_MMSYS=y -CONFIG_COMMON_CLK_MT2701_VDECSYS=y -# CONFIG_COMMON_CLK_MT7622 is not set -# CONFIG_COMMON_CLK_MT7629 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_MEDIATEK=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_MT6589_UART0=y -# CONFIG_DEBUG_MT8127_UART0 is not set -# CONFIG_DEBUG_MT8135_UART3 is not set -CONFIG_DEBUG_PREEMPT=y -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0x11004000 -CONFIG_DEBUG_UART_VIRT=0xf1004000 -CONFIG_DEBUG_UNCOMPRESS=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_LIMA=y -CONFIG_DRM_LVDS_CODEC=y -CONFIG_DRM_MEDIATEK=y -CONFIG_DRM_MEDIATEK_HDMI=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set -# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set -# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -CONFIG_DRM_PANEL_BRIDGE=y -# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set -# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y -# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set -# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set -# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set -CONFIG_DRM_SCHED=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_ELF_CORE=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_CONSOLE=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HID=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_JOYSTICK=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADC is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_AS5011 is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_DB9 is not set -# CONFIG_JOYSTICK_FSIA6B is not set -# CONFIG_JOYSTICK_GAMECON is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_PSXPAD_SPI is not set -# CONFIG_JOYSTICK_PXRC is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_TURBOGRAFX is not set -# CONFIG_JOYSTICK_WALKERA0701 is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_XPAD is not set -# CONFIG_JOYSTICK_ZHENHUA is not set -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEYBOARD_MTK_PMIC=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_UBNT_LEDBAR is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -CONFIG_MACH_MT7623=y -# CONFIG_MACH_MT7629 is not set -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_MT6397=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_PS2 is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_NAND_MTK_BMT is not set -# CONFIG_MTD_PARSER_TRX is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTK_CMDQ=y -CONFIG_MTK_CMDQ_MBOX=y -CONFIG_MTK_CQDMA=y -CONFIG_MTK_EFUSE=y -# CONFIG_MTK_HSDMA is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_IOMMU=y -CONFIG_MTK_IOMMU_V1=y -CONFIG_MTK_MMSYS=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SMI=y -# CONFIG_MTK_SPI_NAND is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SWITCHDEV=y -# CONFIG_NET_VENDOR_AURORA is not set -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_CONFIGFS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_OVERLAY=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_MTK_HDMI=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT2701=y -CONFIG_PINCTRL_MT6397=y -CONFIG_PINCTRL_MT7623=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_MT6323 is not set -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MT6323=y -# CONFIG_REGULATOR_MT6358 is not set -# CONFIG_REGULATOR_MT6380 is not set -# CONFIG_REGULATOR_MT6397 is not set -# CONFIG_REGULATOR_QCOM_LABIBB is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_MT6397 is not set -# CONFIG_RTC_DRV_MT7622 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250_DMA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -# CONFIG_SND_SOC_MT6359 is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TABLET_SERIAL_WACOM4 is not set -# CONFIG_TABLET_USB_ACECAD is not set -# CONFIG_TABLET_USB_AIPTEK is not set -# CONFIG_TABLET_USB_GTCO is not set -# CONFIG_TABLET_USB_HANWANG is not set -# CONFIG_TABLET_USB_KBTAB is not set -# CONFIG_TABLET_USB_PEGASUS is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TOUCHSCREEN_PROPERTIES=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_F_ACM=y -CONFIG_USB_F_ECM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_G_MULTI=y -CONFIG_USB_G_MULTI_CDC=y -# CONFIG_USB_G_MULTI_RNDIS is not set -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_MUSB_DUAL_ROLE=y -# CONFIG_USB_MUSB_GADGET is not set -CONFIG_USB_MUSB_HDRC=y -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_MEDIATEK=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_U_SERIAL=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-5.10 b/target/linux/mediatek/mt7629/config-5.10 deleted file mode 100644 index 5cd53b1137..0000000000 --- a/target/linux/mediatek/mt7629/config-5.10 +++ /dev/null @@ -1,305 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CACHE_L2X0=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CHR_DEV_SCH=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2701 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7629=y -CONFIG_COMMON_CLK_MT7629_ETHSYS=y -CONFIG_COMMON_CLK_MT7629_HIFSYS=y -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEFAULT_HOSTNAME="(mt7629)" -CONFIG_DIMLIB=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB=y -CONFIG_HANDLE_DOMAIN_IRQ=y -# CONFIG_HARDENED_USERCOPY is not set -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -# CONFIG_LEDS_UBNT_LEDBAR is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -# CONFIG_MACH_MT7623 is not set -CONFIG_MACH_MT7629=y -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_MT6577_AUXADC is not set -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -# CONFIG_MTD_PARSER_TRX is not set -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_EFUSE is not set -CONFIG_MTK_INFRACFG=y -# CONFIG_MTK_PMIC_WRAP is not set -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SPI_NAND=y -# CONFIG_MTK_THERMAL is not set -CONFIG_MTK_TIMER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NETFILTER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT7629=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch deleted file mode 100644 index f4e77cf69c..0000000000 --- a/target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch +++ /dev/null @@ -1,119 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -1,7 +1,6 @@ - /* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -+ * Copyright (c) 2018 MediaTek Inc. -+ * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ -@@ -23,7 +22,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { -@@ -40,23 +39,22 @@ - - gpio-keys { - compatible = "gpio-keys"; -- poll-interval = <100>; - - factory { - label = "factory"; - linux,code = ; -- gpios = <&pio 0 0>; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; -- gpios = <&pio 102 0>; -+ gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - memory { -- reg = <0 0x40000000 0 0x20000000>; -+ reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { -@@ -132,22 +130,22 @@ - - port@0 { - reg = <0>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@1 { - reg = <1>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@2 { - reg = <2>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@3 { - reg = <3>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@4 { -@@ -236,15 +234,28 @@ - - &pcie { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; -+ -+ pcie@1,0 { -+ status = "okay"; -+ }; - }; - - &pio { -+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -+ * SATA functions. i.e. output-high: PCIe, output-low: SATA -+ */ -+ asm_sel { -+ gpio-hog; -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { -@@ -511,11 +522,11 @@ - }; - - &sata { -- status = "okay"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "okay"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch deleted file mode 100644 index 254b5f9eb7..0000000000 --- a/target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -18,6 +18,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; - }; - - gpio-keys { -@@ -70,6 +71,10 @@ - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; -+ -+ nvmem-cells = <&macaddr_factory_2a>; -+ nvmem-cell-names = "mac-address"; -+ - fixed-link { - speed = <2500>; - full-duplex; -@@ -82,6 +87,9 @@ - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; -+ -+ nvmem-cells = <&macaddr_factory_24>; -+ nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { -@@ -133,8 +141,9 @@ - }; - - partition@b0000 { -- label = "kernel"; -+ label = "firmware"; - reg = <0xb0000 0xb50000>; -+ compatible = "denx,fit"; - }; - }; - }; -@@ -272,3 +281,17 @@ - pinctrl-0 = <&watchdog_pins>; - status = "okay"; - }; -+ -+&factory { -+ compatible = "nvmem-cells"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_24: macaddr@24 { -+ reg = <0x24 0x6>; -+ }; -+ -+ macaddr_factory_2a: macaddr@2a { -+ reg = <0x2a 0x6>; -+ }; -+}; diff --git a/target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch deleted file mode 100644 index da42c07728..0000000000 --- a/target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -111,7 +111,7 @@ - }; - - psci { -- compatible = "arm,psci-0.2"; -+ compatible = "arm,psci-1.0"; - method = "smc"; - }; - -@@ -127,6 +127,13 @@ - #size-cells = <2>; - ranges; - -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch deleted file mode 100644 index 8dc53d2985..0000000000 --- a/target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,6 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch deleted file mode 100644 index 07a2eae245..0000000000 --- a/target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -22,7 +22,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { diff --git a/target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch deleted file mode 100644 index 6ce85efde9..0000000000 --- a/target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -18,6 +18,7 @@ - - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; - }; - - chosen { -@@ -160,22 +161,22 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@6 { diff --git a/target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch deleted file mode 100644 index f88dbc7195..0000000000 --- a/target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -19,6 +19,10 @@ - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -42,8 +46,8 @@ - compatible = "gpio-keys"; - - factory { -- label = "factory"; -- linux,code = ; -+ label = "reset"; -+ linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - -@@ -57,17 +61,25 @@ - leds { - compatible = "gpio-leds"; - -- green { -- label = "bpi-r64:pio:green"; -- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; -+ led_system_blue: blue { -+ label = "bpi-r64:pio:blue"; -+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - -- red { -- label = "bpi-r64:pio:red"; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_green: green { -+ label = "bpi-r64:pio:green"; -+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; -+ -+/* -+ * red { -+ * label = "bpi-r64:pio:red"; -+ * gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ * default-state = "off"; -+ * }; -+ */ - }; - - memory { diff --git a/target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch deleted file mode 100644 index 261579bf37..0000000000 --- a/target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -559,12 +559,16 @@ - status = "okay"; - }; - -+&rtc { -+ status = "disabled"; -+}; -+ - &sata { -- status = "disable"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "disable"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch deleted file mode 100644 index 39d81bd5d5..0000000000 --- a/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch +++ /dev/null @@ -1,41 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -259,14 +259,32 @@ - status = "disabled"; - }; - --&nor_flash { -+&snand { - pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -+ pinctrl-0 = <&serial_nand_pins>; -+ mediatek,quad-spi; -+ status = "okay"; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; - -- flash@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch deleted file mode 100644 index e7c5d9b167..0000000000 --- a/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch +++ /dev/null @@ -1,77 +0,0 @@ -From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 -From: Xiangsheng Hou -Date: Thu, 6 Jun 2019 16:29:04 +0800 -Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 - -Signed-off-by: Xiangsheng Hou ---- - arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++ - 3 files changed, 79 insertions(+) - ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,22 @@ - status = "disabled"; - }; - -+ snand: snfi@1100d000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>, <0x1100e000 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -254,6 +254,38 @@ - }; - }; - -+&snand { -+ status = "okay"; -+ mediatek,quad-spi; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; -+ -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; -+ }; -+ }; -+}; -+ - &spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch deleted file mode 100644 index fe136c2474..0000000000 --- a/target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch +++ /dev/null @@ -1,81 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -561,6 +561,20 @@ - status = "disabled"; - }; - -+ snand: snfi@1100d000 { -+ compatible = "mediatek,mt7622-snand"; -+ reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - nor_flash: spi@11014000 { - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -529,6 +529,55 @@ - status = "disabled"; - }; - -+&snand { -+ mediatek,quad-spi; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; -+ -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; -+ -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; -+ -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; -+ }; -+ }; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch deleted file mode 100644 index e1e43ce75d..0000000000 --- a/target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -561,7 +561,7 @@ - reg = <0x140000 0x0080000>; - }; - -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -619,5 +619,6 @@ - }; - - &wmac { -+ mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch deleted file mode 100644 index 38947a3a94..0000000000 --- a/target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -949,17 +949,14 @@ - }; - - crypto: crypto@1b240000 { -- compatible = "mediatek,eip97-crypto"; -+ compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , -- , -- ; -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; -- clock-names = "cryp"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; -- status = "disabled"; - }; - - bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch deleted file mode 100644 index 091cffc3c0..0000000000 --- a/target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,7 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "console=ttyS2,115200n8 console=tty1"; -+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch deleted file mode 100644 index d1bafc1526..0000000000 --- a/target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,8 @@ - - aliases { - serial2 = &uart2; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { diff --git a/target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch deleted file mode 100644 index f6745add5b..0000000000 --- a/target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -17,6 +17,10 @@ - serial2 = &uart2; - mmc0 = &mmc0; - mmc1 = &mmc1; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -112,13 +116,13 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - -- blue { -+ led_system_blue: blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - -- green { -+ led_system_green: green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; diff --git a/target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch deleted file mode 100644 index b1dd75a414..0000000000 --- a/target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,7 @@ - - aliases { - serial2 = &uart2; -+ ethernet0 = &gmac0; - mmc0 = &mmc0; - mmc1 = &mmc1; - led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch b/target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch deleted file mode 100644 index bcdc31a2db..0000000000 --- a/target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch +++ /dev/null @@ -1,195 +0,0 @@ -From f9924caf5d952594b2d912e2ec318189ce64cf04 Mon Sep 17 00:00:00 2001 -From: Chunfeng Yun -Date: Fri, 25 Dec 2020 15:52:55 +0800 -Subject: [PATCH] dt-bindings: usb: convert mediatek, musb.txt to YAML schema - -Convert mediatek,musb.txt to YAML schema mediatek,musb.yaml - -Cc: Min Guo -Reviewed-by: Rob Herring -Signed-off-by: Chunfeng Yun -Link: https://lore.kernel.org/r/20201225075258.33352-8-chunfeng.yun@mediatek.com -Signed-off-by: Greg Kroah-Hartman ---- - .../devicetree/bindings/usb/mediatek,musb.txt | 57 --------- - .../bindings/usb/mediatek,musb.yaml | 113 ++++++++++++++++++ - 2 files changed, 113 insertions(+), 57 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt - create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.yaml - ---- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt -+++ /dev/null -@@ -1,57 +0,0 @@ --MediaTek musb DRD/OTG controller --------------------------------------------- -- --Required properties: -- - compatible : should be one of: -- "mediatek,mt2701-musb" -- ... -- followed by "mediatek,mtk-musb" -- - reg : specifies physical base address and size of -- the registers -- - interrupts : interrupt used by musb controller -- - interrupt-names : must be "mc" -- - phys : PHY specifier for the OTG phy -- - dr_mode : should be one of "host", "peripheral" or "otg", -- refer to usb/generic.txt -- - clocks : a list of phandle + clock-specifier pairs, one for -- each entry in clock-names -- - clock-names : must contain "main", "mcu", "univpll" -- for clocks of controller -- --Optional properties: -- - power-domains : a phandle to USB power domain node to control USB's -- MTCMOS -- --Required child nodes: -- usb connector node as defined in bindings/connector/usb-connector.yaml --Optional properties: -- - id-gpios : input GPIO for USB ID pin. -- - vbus-gpios : input GPIO for USB VBUS pin. -- - vbus-supply : reference to the VBUS regulator, needed when supports -- dual-role mode -- - usb-role-switch : use USB Role Switch to support dual-role switch, see -- usb/generic.txt. -- --Example: -- --usb2: usb@11200000 { -- compatible = "mediatek,mt2701-musb", -- "mediatek,mtk-musb"; -- reg = <0 0x11200000 0 0x1000>; -- interrupts = ; -- interrupt-names = "mc"; -- phys = <&u2port2 PHY_TYPE_USB2>; -- dr_mode = "otg"; -- clocks = <&pericfg CLK_PERI_USB0>, -- <&pericfg CLK_PERI_USB0_MCU>, -- <&pericfg CLK_PERI_USB_SLV>; -- clock-names = "main","mcu","univpll"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -- usb-role-switch; -- connector{ -- compatible = "gpio-usb-b-connector", "usb-b-connector"; -- type = "micro"; -- id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; -- vbus-supply = <&usb_vbus>; -- }; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -@@ -0,0 +1,113 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+# Copyright (c) 2020 MediaTek -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/usb/mediatek,musb.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings -+ -+maintainers: -+ - Min Guo -+ -+properties: -+ $nodename: -+ pattern: '^usb@[0-9a-f]+$' -+ -+ compatible: -+ items: -+ - enum: -+ - mediatek,mt2701-musb -+ - const: mediatek,mtk-musb -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ items: -+ - const: mc -+ -+ clocks: -+ items: -+ - description: The main/core clock -+ - description: The system bus clock -+ - description: The 48Mhz clock -+ -+ clock-names: -+ items: -+ - const: main -+ - const: mcu -+ - const: univpll -+ -+ phys: -+ maxItems: 1 -+ -+ usb-role-switch: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: Support role switch. See usb/generic.txt -+ type: boolean -+ -+ dr_mode: -+ enum: -+ - host -+ - otg -+ - peripheral -+ -+ power-domains: -+ description: A phandle to USB power domain node to control USB's MTCMOS -+ maxItems: 1 -+ -+ connector: -+ $ref: /connector/usb-connector.yaml# -+ description: Connector for dual role switch -+ type: object -+ -+dependencies: -+ usb-role-switch: [ 'connector' ] -+ connector: [ 'usb-role-switch' ] -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - interrupt-names -+ - phys -+ - clocks -+ - clock-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ #include -+ #include -+ -+ usb@11200000 { -+ compatible = "mediatek,mt2701-musb", "mediatek,mtk-musb"; -+ reg = <0x11200000 0x1000>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&u2port2 PHY_TYPE_USB2>; -+ dr_mode = "otg"; -+ clocks = <&pericfg CLK_PERI_USB0>, -+ <&pericfg CLK_PERI_USB0_MCU>, -+ <&pericfg CLK_PERI_USB_SLV>; -+ clock-names = "main","mcu","univpll"; -+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -+ usb-role-switch; -+ -+ connector { -+ compatible = "gpio-usb-b-connector", "usb-b-connector"; -+ type = "micro"; -+ id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; -+ vbus-supply = <&usb_vbus>; -+ }; -+ }; -+... diff --git a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch b/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch deleted file mode 100644 index 3e97d4a0a3..0000000000 --- a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch +++ /dev/null @@ -1,25 +0,0 @@ -From b5a12546e779d4f5586f58e60e0ef5070a833a64 Mon Sep 17 00:00:00 2001 -From: Chunfeng Yun -Date: Mon, 1 Feb 2021 15:00:08 +0800 -Subject: [PATCH] dt-bindings: usb: mediatek: musb: add mt8516 compatbile - -Add support mt8516 compatbile - -Reviewed-by: Rob Herring -Signed-off-by: Chunfeng Yun -Link: https://lore.kernel.org/r/20210201070016.41721-8-chunfeng.yun@mediatek.com -Signed-off-by: Greg Kroah-Hartman ---- - Documentation/devicetree/bindings/usb/mediatek,musb.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -@@ -17,6 +17,7 @@ properties: - compatible: - items: - - enum: -+ - mediatek,mt8516-musb - - mediatek,mt2701-musb - - const: mediatek,mtk-musb - diff --git a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch b/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch deleted file mode 100644 index 44415db5da..0000000000 --- a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch +++ /dev/null @@ -1,23 +0,0 @@ -From b7e4218ece0b7a1b9142491056ae0c4f1af80041 Mon Sep 17 00:00:00 2001 -From: Sungbo Eo -Date: Sun, 8 Aug 2021 21:38:39 +0900 -Subject: [PATCH 1/2] dt-bindings: usb: mtk-musb: add MT7623 compatible - -Document MT7623 compatible for mtk-musb. - -Signed-off-by: Sungbo Eo -Reviewed-by: Matthias Brugger ---- - Documentation/devicetree/bindings/usb/mediatek,musb.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -@@ -19,6 +19,7 @@ properties: - - enum: - - mediatek,mt8516-musb - - mediatek,mt2701-musb -+ - mediatek,mt7623-musb - - const: mediatek,mtk-musb - - reg: diff --git a/target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch b/target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch deleted file mode 100644 index ba1d1fe202..0000000000 --- a/target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001 -From: Sungbo Eo -Date: Sun, 8 Aug 2021 21:38:40 +0900 -Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes - -MT7623 has an musb controller that is compatible with the one from MT2701. - -Signed-off-by: Sungbo Eo ---- - arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7623a.dtsi | 4 ++++ - 2 files changed, 38 insertions(+) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -585,6 +585,40 @@ - status = "disabled"; - }; - -+ usb0: usb@11200000 { -+ compatible = "mediatek,mt7623-musb", -+ "mediatek,mtk-musb"; -+ reg = <0 0x11200000 0 0x1000>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&u2port2 PHY_TYPE_USB2>; -+ dr_mode = "otg"; -+ clocks = <&pericfg CLK_PERI_USB0>, -+ <&pericfg CLK_PERI_USB0_MCU>, -+ <&pericfg CLK_PERI_USB_SLV>; -+ clock-names = "main","mcu","univpll"; -+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -+ status = "disabled"; -+ }; -+ -+ u2phy1: t-phy@11210000 { -+ compatible = "mediatek,mt7623-tphy", -+ "mediatek,generic-tphy-v1"; -+ reg = <0 0x11210000 0 0x0800>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ u2port2: usb-phy@11210800 { -+ reg = <0 0x11210800 0 0x0100>; -+ clocks = <&topckgen CLK_TOP_USB_PHY48M>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ }; -+ - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7623-audsys", - "mediatek,mt2701-audsys", ---- a/arch/arm/boot/dts/mt7623a.dtsi -+++ b/arch/arm/boot/dts/mt7623a.dtsi -@@ -35,6 +35,10 @@ - clock-names = "ethif"; - }; - -+&usb0 { -+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -+}; -+ - &usb1 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; - }; diff --git a/target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch deleted file mode 100644 index 80ceb490d4..0000000000 --- a/target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -160,6 +160,10 @@ - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch deleted file mode 100644 index 95f4be177b..0000000000 --- a/target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 -From: Kristian Evensen -Date: Mon, 30 Apr 2018 14:38:01 +0200 -Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support - ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -15,6 +15,8 @@ - #include - #include - #include -+#include -+#include - - /* version V1 sub-banks offset base address */ - /* banks shared by multiple phys */ -@@ -267,6 +269,9 @@ - #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) - #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) - -+#define HIF_SYSCFG1 0x14 -+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) -+ - enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, -@@ -315,6 +320,7 @@ struct mtk_tphy { - void __iomem *sif_base; /* only shared sif */ - const struct mtk_phy_pdata *pdata; - struct mtk_phy_instance **phys; -+ struct regmap *hif; - int nphys; - int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ - int src_coef; /* coefficient for slew rate calibrate */ -@@ -634,6 +640,10 @@ static void pcie_phy_instance_init(struc - if (tphy->pdata->version != MTK_PHY_V1) - return; - -+ if (tphy->hif) -+ regmap_update_bits(tphy->hif, HIF_SYSCFG1, -+ HIF_SYSCFG1_PHY2_MASK, 0); -+ - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); - tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); - tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); -@@ -1136,6 +1146,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_ref_clk); - device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef); - -+ if (of_find_property(np, "mediatek,phy-switch", NULL)) { -+ tphy->hif = syscon_regmap_lookup_by_phandle(np, -+ "mediatek,phy-switch"); -+ if (IS_ERR(tphy->hif)) { -+ dev_err(&pdev->dev, -+ "missing \"mediatek,phy-switch\" phandle\n"); -+ return PTR_ERR(tphy->hif); -+ } -+ } -+ - port = 0; - for_each_child_of_node(np, child_np) { - struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch b/target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch deleted file mode 100644 index 318c8b2873..0000000000 --- a/target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- a/drivers/mtd/mtk-snand/mtk-snand-mtd.c -+++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -612,6 +613,8 @@ static int mtk_snand_probe(struct platfo - mtd->_block_isbad = mtk_snand_mtd_block_isbad; - mtd->_block_markbad = mtk_snand_mtd_block_markbad; - -+ mtk_bmt_attach(mtd); -+ - ret = mtd_device_register(mtd, NULL, 0); - if (ret) { - dev_err(msm->pdev.dev, "failed to register mtd partition\n"); -@@ -623,6 +626,7 @@ static int mtk_snand_probe(struct platfo - return 0; - - errout4: -+ mtk_bmt_detach(mtd); - devm_kfree(msm->pdev.dev, msm->page_cache); - - errout3: -@@ -650,6 +654,8 @@ static int mtk_snand_remove(struct platf - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); -+ - mtk_snand_cleanup(msm->snf); - - if (msm->irq >= 0) diff --git a/target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch deleted file mode 100644 index a79bd8fcdc..0000000000 --- a/target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -535,6 +535,8 @@ - pinctrl-0 = <&serial_nand_pins>; - status = "okay"; - -+ mediatek,bmt-v2; -+ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; diff --git a/target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch b/target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch deleted file mode 100644 index ebba6ffaad..0000000000 --- a/target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -238,6 +238,8 @@ source "drivers/mtd/ubi/Kconfig" - - source "drivers/mtd/hyperbus/Kconfig" - -+source "drivers/mtd/mtk-snand/Kconfig" -+ - source "drivers/mtd/composite/Kconfig" - - endif # MTD ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -34,5 +34,7 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ - obj-$(CONFIG_MTD_UBI) += ubi/ - obj-$(CONFIG_MTD_HYPERBUS) += hyperbus/ - -+obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/ -+ - # Composite drivers must be loaded last - obj-y += composite/ diff --git a/target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch deleted file mode 100644 index e0941a9550..0000000000 --- a/target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.c -+++ b/drivers/crypto/inside-secure/safexcel.c -@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex - val |= EIP197_MST_CTRL_TX_MAX_CMD(5); - writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); - } -+ /* -+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 -+ */ -+ else { -+ val = 0; -+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); -+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); -+ } - - /* Configure wr/rd cache values */ - writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -314,6 +314,7 @@ - #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) - #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) -+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) - #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) - #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch deleted file mode 100644 index be2bffb749..0000000000 --- a/target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -736,6 +736,9 @@ enum safexcel_eip_version { - /* Priority we use for advertising our algorithms */ - #define SAFEXCEL_CRA_PRIORITY 300 - -+/* System cache line size */ -+#define SYSTEM_CACHELINE_SIZE 64 -+ - /* SM3 digest result for zero length message */ - #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ - "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ ---- a/drivers/crypto/inside-secure/safexcel_hash.c -+++ b/drivers/crypto/inside-secure/safexcel_hash.c -@@ -53,9 +53,9 @@ struct safexcel_ahash_req { - u8 block_sz; /* block size, only set once */ - u8 digest_sz; /* output digest size, only set once */ - __le32 state[SHA3_512_BLOCK_SIZE / -- sizeof(__le32)] __aligned(sizeof(__le32)); -+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); - -- u64 len; -+ u64 len __aligned(SYSTEM_CACHELINE_SIZE); - u64 processed; - - u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch deleted file mode 100644 index 0fa8ff5727..0000000000 --- a/target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/drivers/tty/serial/8250/8250.h -+++ b/drivers/tty/serial/8250/8250.h -@@ -82,6 +82,7 @@ struct serial8250_config { - #define UART_CAP_MINI (1 << 17) /* Mini UART on BCM283X family lacks: - * STOP PARITY EPAR SPAR WLEN5 WLEN6 - */ -+#define UART_CAP_NMOD (1 << 18) /* UART doesn't do termios */ - - #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */ - #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ ---- a/drivers/tty/serial/8250/8250_port.c -+++ b/drivers/tty/serial/8250/8250_port.c -@@ -288,7 +288,7 @@ static const struct serial8250_config ua - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, -- .flags = UART_CAP_FIFO, -+ .flags = UART_CAP_FIFO | UART_CAP_NMOD, - }, - [PORT_NPCM] = { - .name = "Nuvoton 16550", -@@ -2735,6 +2735,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; - -+ if (up->capabilities & UART_CAP_NMOD) { -+ termios->c_cflag = 0; -+ return; -+ } -+ - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch b/target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch deleted file mode 100644 index f8527ba424..0000000000 --- a/target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: David Bauer -To: linux-mtd@lists.infradead.org -Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV -Date: Sat, 13 Feb 2021 16:10:47 +0100 - -The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K -sectors as well as block protection and Dual-/Quad-read. - -Tested on: Ubiquiti UniFi 6 LR - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/winbond.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/spi-nor/winbond.c -+++ b/drivers/mtd/spi-nor/winbond.c -@@ -95,6 +95,10 @@ static const struct flash_info winbond_p - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024, -+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | -+ SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | -+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, - { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, - }; diff --git a/target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch deleted file mode 100644 index c7e65456ba..0000000000 --- a/target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -340,6 +340,12 @@ config ROCKCHIP_PHY - help - Currently supports the integrated Ethernet PHY. - -+config RTL8367S_GSW -+ tristate "rtl8367 Gigabit Switch support for mt7622" -+ depends on NET_VENDOR_MEDIATEK -+ help -+ This driver supports rtl8367s in mt7622 -+ - config SMSC_PHY - tristate "SMSC PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -89,6 +89,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o -+obj-$(CONFIG_RTL8367S_GSW) += rtk/ - obj-$(CONFIG_SMSC_PHY) += smsc.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch b/target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch deleted file mode 100644 index e370d68472..0000000000 --- a/target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 4823778b116c08e9c55dbc5b5042223289ea6a0c Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Wed, 31 Mar 2021 15:34:37 +0200 -Subject: [PATCH] net: mediatek: add flow offload for mt7623 - -mt7623 uses offload version 2 too - -tested on Bananapi-R2 - -Signed-off-by: Frank Wunderlich ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3375,6 +3375,7 @@ static const struct mtk_soc_data mt7623_ - .hw_features = MTK_HW_FEATURES, - .required_clks = MT7623_CLKS_BITMAP, - .required_pctl = true, -+ .offload_version = 2, - }; - - static const struct mtk_soc_data mt7629_data = { diff --git a/target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch b/target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch deleted file mode 100644 index 02e4c130ea..0000000000 --- a/target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch +++ /dev/null @@ -1,415 +0,0 @@ -From patchwork Thu May 28 06:16:45 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Chuanjia Liu -X-Patchwork-Id: 11574793 -Return-Path: - -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 391201392 - for ; - Thu, 28 May 2020 06:20:27 +0000 (UTC) -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by mail.kernel.org (Postfix) with ESMTPS id 104F620657 - for ; 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Thu, 28 May 2020 14:18:47 +0800 -From: -To: , , -Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding -Date: Thu, 28 May 2020 14:16:45 +0800 -Message-ID: <20200528061648.32078-2-chuanjia.liu@mediatek.com> -X-Mailer: git-send-email 2.18.0 -In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -MIME-Version: 1.0 -X-MTK: N -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20200527_231958_261064_608CC03E -X-CRM114-Status: GOOD ( 13.95 ) -X-Spam-Score: -0.2 (/) -X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: - Content analysis details: (-0.2 points) - pts rule name description - ---- ---------------------- - -------------------------------------------------- - -0.0 SPF_PASS SPF: sender matches SPF record - 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record - 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 - encoding - -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from - author's domain - 0.1 DKIM_SIGNED Message has a DKIM or DK signature, - not necessarily - valid - -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature - -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from - envelope-from domain - 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay - lines -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.29 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, - srv_heupstream@mediatek.com, "chuanjia.liu" , - linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, - jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, - yong.wu@mediatek.com, bhelgaas@google.com, - linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org - -From: "chuanjia.liu" - -There are two independent PCIe controllers in MT2712/MT7622 platform, -and each of them should contain an independent MSI domain. - -In current architecture, MSI domain will be inherited from the root -bridge, and all of the devices will share the same MSI domain. -Hence that, the PCIe devices will not work properly if the irq number -which required is more than 32. - -Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and -comply with the hardware design. - -Signed-off-by: chuanjia.liu ---- - .../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++ - .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++------- - 2 files changed, 129 insertions(+), 53 deletions(-) - create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml -@@ -0,0 +1,38 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Mediatek PCIECFG controller -+ -+maintainers: -+ - Chuanjia Liu -+ - Jianjun Wang -+ -+description: | -+ The MediaTek PCIECFG controller controls some feature about -+ LTSSM, ASPM and so on. -+ -+properties: -+ compatible: -+ items: -+ - enum: -+ - mediatek,mt7622-pciecfg -+ - mediatek,mt7629-pciecfg -+ - const: syscon -+ -+ reg: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ -+examples: -+ - | -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,mt7622-pciecfg", "syscon"; -+ reg = <0 0x1a140000 0 0x1000>; -+ }; -+... ---- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt -+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt -@@ -8,7 +8,7 @@ Required properties: - "mediatek,mt7623-pcie" - "mediatek,mt7629-pcie" - - device_type: Must be "pci" --- reg: Base addresses and lengths of the PCIe subsys and root ports. -+- reg: Base addresses and lengths of the root ports. - - reg-names: Names of the above areas to use during resource lookup. - - #address-cells: Address representation for root ports (must be 3) - - #size-cells: Size representation for root ports (must be 2) -@@ -19,10 +19,10 @@ Required properties: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys -- Required entries for MT2712/MT7622: -+ Required entries for MT2712/MT7622/MT7629: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access -- Required entries for MT7622: -+ Required entries for MT7622/MT7629: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off -@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701: - - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - --Required properties for MT2712/MT7622: -+Required properties for MT2712/MT7622/MT7629: - -interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port - -+Required properties for MT7622/MT7629: -+- mediatek,pcie-subsys: Should be a phandle of the pciecfg node. -+ - In addition, the device tree node must have sub-nodes describing each - PCIe port interface, having the following mandatory properties: - -@@ -143,56 +146,73 @@ Examples for MT7623: - - Examples for MT2712: - -- pcie: pcie@11700000 { -+ pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; -- reg = <0 0x11700000 0 0x1000>, -- <0 0x112ff000 0 0x1000>; -- reg-names = "port0", "port1"; -+ reg = <0 0x112ff000 0 0x1000>; -+ reg-names = "port1"; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, -- <&pericfg CLK_PERI_PCIE0>, -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; -- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ clock-names = "sys_ck1", "ahb_ck1"; -+ phys = <&u3port1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -- reg = <0x0000 0 0 0 0>; -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; -+ }; - -- pcie1: pcie@1,0 { -- reg = <0x0800 0 0 0 0>; -+ pcie0: pcie@11700000 { -+ compatible = "mediatek,mt2712-pcie"; -+ device_type = "pci"; -+ reg = <0 0x11700000 0 0x1000>; -+ reg-names = "port0"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -+ <&pericfg CLK_PERI_PCIE0>; -+ clock-names = "sys_ck0", "ahb_ck0"; -+ phys = <&u3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ status = "disabled"; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; -@@ -202,39 +222,31 @@ Examples for MT2712: - - Examples for MT7622: - -- pcie: pcie@1a140000 { -+ pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; -- reg = <0 0x1a140000 0 0x1000>, -- <0 0x1a143000 0 0x1000>, -- <0 0x1a145000 0 0x1000>; -- reg-names = "subsys", "port0", "port1"; -+ reg = <0 0x1a143000 0 0x1000>; -+ reg-names = "port0"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, -- <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, -- <&pciesys CLK_PCIE_P1_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, -- <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, -- <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, -- <&pciesys CLK_PCIE_P1_OBFF_EN>, -- <&pciesys CLK_PCIE_P0_PIPE_EN>, -- <&pciesys CLK_PCIE_P1_PIPE_EN>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", -- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", -- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; -- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ <&pciesys CLK_PCIE_P0_PIPE_EN>; -+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", -+ "axi_ck0", "obff_ck0", "pipe_ck0"; -+ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x8000000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -+ slot0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; -@@ -251,8 +263,34 @@ Examples for MT7622: - #interrupt-cells = <1>; - }; - }; -+ }; -+ -+ pcie1: pcie@1a145000 { -+ compatible = "mediatek,mt7622-pcie"; -+ device_type = "pci"; -+ reg = <0 0x1a145000 0 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, -+ /* designer has connect RC1 with p0_ahb clock */ -+ <&pciesys CLK_PCIE_P0_AHB_EN>, -+ <&pciesys CLK_PCIE_P1_AUX_EN>, -+ <&pciesys CLK_PCIE_P1_AXI_EN>, -+ <&pciesys CLK_PCIE_P1_OBFF_EN>, -+ <&pciesys CLK_PCIE_P1_PIPE_EN>; -+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", -+ "axi_ck1", "obff_ck1", "pipe_ck1"; -+ -+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; diff --git a/target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch b/target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch deleted file mode 100644 index fea9486d30..0000000000 --- a/target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch +++ /dev/null @@ -1,217 +0,0 @@ -From patchwork Thu May 28 06:16:46 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Chuanjia Liu -X-Patchwork-Id: 11574781 -Return-Path: - -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A99B60D - for ; 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Thu, 28 May 2020 14:18:51 +0800 -Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc - (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend - Transport; Thu, 28 May 2020 14:18:49 +0800 -From: -To: , , -Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base -Date: Thu, 28 May 2020 14:16:46 +0800 -Message-ID: <20200528061648.32078-3-chuanjia.liu@mediatek.com> -X-Mailer: git-send-email 2.18.0 -In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -MIME-Version: 1.0 -X-MTK: N -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20200527_231859_251275_BED2B1E2 -X-CRM114-Status: GOOD ( 11.62 ) -X-Spam-Score: -0.2 (/) -X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: - Content analysis details: (-0.2 points) - pts rule name description - ---- ---------------------- - -------------------------------------------------- - -0.0 SPF_PASS SPF: sender matches SPF record - 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record - 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 - encoding - -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from - author's domain - 0.1 DKIM_SIGNED Message has a DKIM or DK signature, - not necessarily - valid - -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature - -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from - envelope-from domain - 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay - lines -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.29 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, - srv_heupstream@mediatek.com, "chuanjia.liu" , - linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, - jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, - yong.wu@mediatek.com, bhelgaas@google.com, - linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org - -From: "chuanjia.liu" - -Use regmap to get shared pcie-cfg base and change -the method to get pcie irq. - -Signed-off-by: chuanjia.liu ---- - drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++------- - 1 file changed, 18 insertions(+), 7 deletions(-) - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -23,6 +24,7 @@ - #include - #include - #include -+#include - #include - - #include "../pci.h" -@@ -207,6 +209,7 @@ struct mtk_pcie_port { - * struct mtk_pcie - PCIe host information - * @dev: pointer to PCIe device - * @base: IO mapped register base -+ * @cfg: IO mapped register map for PCIe config - * @free_ck: free-run reference clock - * @mem: non-prefetchable memory resource - * @ports: pointer to PCIe port information -@@ -215,6 +218,7 @@ struct mtk_pcie_port { - struct mtk_pcie { - struct device *dev; - void __iomem *base; -+ struct regmap *cfg; - struct clk *free_ck; - - struct list_head ports; -@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk - return err; - } - -- port->irq = platform_get_irq(pdev, port->slot); -+ port->irq = platform_get_irq_byname(pdev, "pcie_irq"); - if (port->irq < 0) - return port->irq; - -@@ -676,12 +680,11 @@ static int mtk_pcie_startup_port_v2(stru - if (!mem) - return -EINVAL; - -- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ -- if (pcie->base) { -- val = readl(pcie->base + PCIE_SYS_CFG_V2); -- val |= PCIE_CSR_LTSSM_EN(port->slot) | -- PCIE_CSR_ASPM_L1_EN(port->slot); -- writel(val, pcie->base + PCIE_SYS_CFG_V2); -+ /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */ -+ if (pcie->cfg) { -+ val = PCIE_CSR_LTSSM_EN(port->slot) | -+ PCIE_CSR_ASPM_L1_EN(port->slot); -+ regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); - } - - /* Assert all reset signals */ -@@ -985,6 +988,7 @@ static int mtk_pcie_subsys_powerup(struc - struct device *dev = pcie->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *regs; -+ struct device_node *cfg_node; - int err; - - /* get shared registers, which are optional */ -@@ -997,6 +1001,13 @@ static int mtk_pcie_subsys_powerup(struc - } - } - -+ cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0); -+ if (cfg_node) { -+ pcie->cfg = syscon_node_to_regmap(cfg_node); -+ if (IS_ERR(pcie->cfg)) -+ return PTR_ERR(pcie->cfg); -+ } -+ - pcie->free_ck = devm_clk_get(dev, "free_ck"); - if (IS_ERR(pcie->free_ck)) { - if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) diff --git a/target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch b/target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch deleted file mode 100644 index 197be4bf71..0000000000 --- a/target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch +++ /dev/null @@ -1,417 +0,0 @@ -From patchwork Thu May 28 06:16:47 2020 -Content-Type: text/plain; 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Wed, 27 May 2020 22:19:17 -0800 -Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by - MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id - 15.0.1497.2; Wed, 27 May 2020 23:18:47 -0700 -Received: from mtkcas07.mediatek.inc (172.21.101.84) by - mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id - 15.0.1497.2; Thu, 28 May 2020 14:18:52 +0800 -Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc - (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend - Transport; Thu, 28 May 2020 14:18:51 +0800 -From: -To: , , -Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for - MT2712/MT7622 -Date: Thu, 28 May 2020 14:16:47 +0800 -Message-ID: <20200528061648.32078-4-chuanjia.liu@mediatek.com> -X-Mailer: git-send-email 2.18.0 -In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -MIME-Version: 1.0 -X-MTK: N -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20200527_231859_253529_B6751C5A -X-CRM114-Status: GOOD ( 12.20 ) -X-Spam-Score: -0.2 (/) -X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: - Content analysis details: (-0.2 points) - pts rule name description - ---- ---------------------- - -------------------------------------------------- - -0.0 SPF_PASS SPF: sender matches SPF record - 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record - 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 - encoding - -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from - author's domain - 0.1 DKIM_SIGNED Message has a DKIM or DK signature, - not necessarily - valid - -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature - -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from - envelope-from domain - 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay - lines -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.29 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, - srv_heupstream@mediatek.com, "chuanjia.liu" , - linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, - jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, - yong.wu@mediatek.com, bhelgaas@google.com, - linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org - -From: "chuanjia.liu" - -There are two independent PCIe controllers in MT2712/MT7622 platform, -and each of them should contain an independent MSI domain. - -In current architecture, MSI domain will be inherited from the root -bridge, and all of the devices will share the same MSI domain. -Hence that, the PCIe devices will not work properly if the irq number -which required is more than 32. - -Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and -comply with the hardware design. - -Signed-off-by: chuanjia.liu ---- - arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++++++++-------- - .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 ++-- - arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 +++++++++++------ - 4 files changed, 96 insertions(+), 69 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi -@@ -915,60 +915,73 @@ - }; - }; - -- pcie: pcie@11700000 { -+ pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; -- reg = <0 0x11700000 0 0x1000>, -- <0 0x112ff000 0 0x1000>; -- reg-names = "port0", "port1"; -+ reg = <0 0x112ff000 0 0x1000>; -+ reg-names = "port1"; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, -- <&pericfg CLK_PERI_PCIE0>, -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; -- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ clock-names = "sys_ck1", "ahb_ck1"; -+ phys = <&u3port1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0000 0 0 0 0>; -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; -+ }; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0800 0 0 0 0>; -+ pcie0: pcie@11700000 { -+ compatible = "mediatek,mt2712-pcie"; -+ device_type = "pci"; -+ reg = <0 0x11700000 0 0x1000>; -+ reg-names = "port0"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -+ <&pericfg CLK_PERI_PCIE0>; -+ clock-names = "sys_ck0", "ahb_ck0"; -+ phys = <&u3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ status = "disabled"; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -292,18 +292,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -802,45 +802,41 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,mt7622-pciecfg", "syscon"; -+ reg = <0 0x1a140000 0 0x1000>; -+ }; -+ -+ pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; -- reg = <0 0x1a140000 0 0x1000>, -- <0 0x1a143000 0 0x1000>, -- <0 0x1a145000 0 0x1000>; -- reg-names = "subsys", "port0", "port1"; -+ reg = <0 0x1a143000 0 0x1000>; -+ reg-names = "port0"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, -- <&pciesys CLK_PCIE_P1_MAC_EN>, -- <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, -- <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, -- <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, -- <&pciesys CLK_PCIE_P1_OBFF_EN>, -- <&pciesys CLK_PCIE_P0_PIPE_EN>, -- <&pciesys CLK_PCIE_P1_PIPE_EN>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", -- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", -- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; -+ <&pciesys CLK_PCIE_P0_PIPE_EN>; -+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", -+ "axi_ck0", "obff_ck0", "pipe_ck0"; -+ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; - -- pcie0: pcie@0,0 { -+ slot0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- status = "disabled"; -- - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, -@@ -852,15 +848,39 @@ - #interrupt-cells = <1>; - }; - }; -+ }; - -- pcie1: pcie@1,0 { -+ pcie1: pcie@1a145000 { -+ compatible = "mediatek,mt7622-pcie"; -+ device_type = "pci"; -+ reg = <0 0x1a145000 0 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, -+ /* designer has connect RC1 with p0_ahb clock */ -+ <&pciesys CLK_PCIE_P0_AHB_EN>, -+ <&pciesys CLK_PCIE_P1_AUX_EN>, -+ <&pciesys CLK_PCIE_P1_AXI_EN>, -+ <&pciesys CLK_PCIE_P1_OBFF_EN>, -+ <&pciesys CLK_PCIE_P1_PIPE_EN>; -+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", -+ "axi_ck1", "obff_ck1", "pipe_ck1"; -+ -+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; -+ status = "disabled"; -+ -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- status = "disabled"; -- - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -232,18 +232,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { diff --git a/target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch deleted file mode 100644 index ce72ad659a..0000000000 --- a/target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch +++ /dev/null @@ -1,203 +0,0 @@ -From patchwork Thu May 28 06:16:48 2020 -Content-Type: text/plain; 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- }; - --&pcie { -+&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; -+ status = "okay"; - }; - - &pciephy1 { ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -376,16 +376,21 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,mt7629-pciecfg", "syscon"; -+ reg = <0x1a140000 0x1000>; -+ }; -+ -+ pcie1: pcie@1a145000 { - compatible = "mediatek,mt7629-pcie"; - device_type = "pci"; -- reg = <0x1a140000 0x1000>, -- <0x1a145000 0x1000>; -- reg-names = "subsys","port1"; -+ reg = <0x1a145000 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, -@@ -406,21 +411,19 @@ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; -- - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; diff --git a/target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch deleted file mode 100644 index 031582a788..0000000000 --- a/target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:33:27 +0200 -Subject: [PATCH] pcie-mediatek: fix clearing interrupt status - -Clearing the status needs to happen after running the handler, otherwise -we will get an extra spurious interrupt after the cause has been cleared - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -615,10 +615,10 @@ static void mtk_pcie_intr_handler(struct - if (status & INTX_MASK) { - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ -- writel(1 << bit, port->base + PCIE_INT_STATUS); - virq = irq_find_mapping(port->irq_domain, - bit - INTX_SHIFT); - generic_handle_irq(virq); -+ writel(1 << bit, port->base + PCIE_INT_STATUS); - } - } - diff --git a/target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch b/target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch deleted file mode 100644 index be9dcfc3ed..0000000000 --- a/target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch +++ /dev/null @@ -1,128 +0,0 @@ -From eda80b249df7bbc7b3dd13907343a3e59bfc57fd Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 4 Jan 2022 12:06:22 +0000 -Subject: [PATCH 1/3] net: ethernet: mtk_eth_soc: fix return values and - refactor MDIO ops - -Instead of returning -1 (-EPERM) when MDIO bus is stuck busy -while writing or 0xffff if it happens while reading, return the -appropriate -ETIMEDOUT. Also fix return type to int instead of u32. -Refactor functions to use bitfield helpers instead of having various -masking and shifting constants in the code, which also results in the -register definitions in the header file being more obviously related -to what is stated in the MediaTek's Reference Manual. - -Fixes: 656e705243fd0 ("net-next: mediatek: add support for MT7623 ethernet") -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 53 ++++++++++++--------- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++++-- - 2 files changed, 41 insertions(+), 28 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -94,46 +94,53 @@ static int mtk_mdio_busy_wait(struct mtk - } - - dev_err(eth->dev, "mdio: MDIO timeout\n"); -- return -1; -+ return -ETIMEDOUT; - } - --static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, -- u32 phy_register, u32 write_data) -+static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, -+ u32 write_data) - { -- if (mtk_mdio_busy_wait(eth)) -- return -1; -+ int ret; - -- write_data &= 0xffff; -- -- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | -- (phy_register << PHY_IAC_REG_SHIFT) | -- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), - MTK_PHY_IAC); - -- if (mtk_mdio_busy_wait(eth)) -- return -1; -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; - - return 0; - } - --static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) -+static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) - { -- u32 d; -- -- if (mtk_mdio_busy_wait(eth)) -- return 0xffff; -+ int ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | -- (phy_reg << PHY_IAC_REG_SHIFT) | -- (phy_addr << PHY_IAC_ADDR_SHIFT), -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_C22_READ | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr), - MTK_PHY_IAC); - -- if (mtk_mdio_busy_wait(eth)) -- return 0xffff; -- -- d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; - -- return d; -+ return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; - } - - static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -344,11 +344,17 @@ - /* PHY Indirect Access Control registers */ - #define MTK_PHY_IAC 0x10004 - #define PHY_IAC_ACCESS BIT(31) --#define PHY_IAC_READ BIT(19) --#define PHY_IAC_WRITE BIT(18) --#define PHY_IAC_START BIT(16) --#define PHY_IAC_ADDR_SHIFT 20 --#define PHY_IAC_REG_SHIFT 25 -+#define PHY_IAC_REG_MASK GENMASK(29, 25) -+#define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) -+#define PHY_IAC_ADDR_MASK GENMASK(24, 20) -+#define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) -+#define PHY_IAC_CMD_MASK GENMASK(19, 18) -+#define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) -+#define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) -+#define PHY_IAC_START_MASK GENMASK(17, 16) -+#define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) -+#define PHY_IAC_DATA_MASK GENMASK(15, 0) -+#define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) - #define PHY_IAC_TIMEOUT HZ - - #define MTK_MAC_MISC 0x1000c diff --git a/target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch deleted file mode 100644 index ef2e225717..0000000000 --- a/target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Tue, 4 Jan 2022 12:07:00 +0000 -Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and - devad fields - -Add a couple of helpers and definitions to extract the clause 45 regad -and devad fields from the regnum passed into MDIO drivers. - -Tested-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: Russell King (Oracle) -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - include/linux/mdio.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/include/linux/mdio.h -+++ b/include/linux/mdio.h -@@ -7,6 +7,7 @@ - #define __LINUX_MDIO_H__ - - #include -+#include - #include - - /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit -@@ -14,6 +15,7 @@ - */ - #define MII_ADDR_C45 (1<<30) - #define MII_DEVADDR_C45_SHIFT 16 -+#define MII_DEVADDR_C45_MASK GENMASK(20, 16) - #define MII_REGADDR_C45_MASK GENMASK(15, 0) - - struct gpio_desc; -@@ -342,6 +344,16 @@ static inline u32 mdiobus_c45_addr(int d - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; - } - -+static inline u16 mdiobus_c45_regad(u32 regnum) -+{ -+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -+} -+ -+static inline u16 mdiobus_c45_devad(u32 regnum) -+{ -+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); -+} -+ - static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, - u16 regnum) - { diff --git a/target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch deleted file mode 100644 index 289398ce3a..0000000000 --- a/target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch +++ /dev/null @@ -1,128 +0,0 @@ -From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 4 Jan 2022 12:07:46 +0000 -Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO - access - -Implement read and write access to IEEE 802.3 Clause 45 Ethernet -phy registers while making use of new mdiobus_c45_regad and -mdiobus_c45_devad helpers. - -Tested on the Ubiquiti UniFi 6 LR access point featuring -MediaTek MT7622BV WiSoC with Aquantia AQR112C. - -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 + - 2 files changed, 60 insertions(+), 13 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -106,13 +106,35 @@ static int _mtk_mdio_write(struct mtk_et - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_WRITE | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr) | -- PHY_IAC_DATA(write_data), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -129,12 +151,33 @@ static int _mtk_mdio_read(struct mtk_eth - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_C22_READ | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_READ | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_C22_READ | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -593,6 +636,7 @@ static int mtk_mdio_init(struct mtk_eth - eth->mii_bus->name = "mdio"; - eth->mii_bus->read = mtk_mdio_read; - eth->mii_bus->write = mtk_mdio_write; -+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; - eth->mii_bus->priv = eth; - eth->mii_bus->parent = eth->dev; - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -349,9 +349,12 @@ - #define PHY_IAC_ADDR_MASK GENMASK(24, 20) - #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) - #define PHY_IAC_CMD_MASK GENMASK(19, 18) -+#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) - #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) - #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) -+#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) - #define PHY_IAC_START_MASK GENMASK(17, 16) -+#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) - #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) - #define PHY_IAC_DATA_MASK GENMASK(15, 0) - #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) diff --git a/target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch b/target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch deleted file mode 100644 index e9d4188a45..0000000000 --- a/target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -577,6 +577,7 @@ static void mtk_validate(struct phylink_ - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); -+ phylink_set(mask, 2500baseT_Full); - phylink_set(mask, 2500baseX_Full); - } - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { diff --git a/target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch deleted file mode 100644 index 32fc0a9ad5..0000000000 --- a/target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ /dev/null @@ -1,96 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:42:42 +0200 -Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA - -It improves performance by eliminating the need for a cache flush for DMA on -attached devices - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -813,6 +813,8 @@ - reg = <0 0x1a143000 0 0x1000>; - reg-names = "port0"; - mediatek,pcie-cfg = <&pciecfg>; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; -@@ -830,6 +832,7 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; - - slot0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; -@@ -856,6 +859,8 @@ - reg = <0 0x1a145000 0 0x1000>; - reg-names = "port1"; - mediatek,pcie-cfg = <&pciecfg>; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; -@@ -874,6 +879,7 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; - - slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +140,11 @@ - #define PCIE_LINK_STATUS_V2 0x804 - #define PCIE_PORT_LINKUP_V2 BIT(10) - -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) -+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) -+ - struct mtk_pcie_port; - - /** -@@ -1042,6 +1048,27 @@ static int mtk_pcie_setup(struct mtk_pci - struct mtk_pcie_port *port, *tmp; - int err; - -+ if (of_dma_is_coherent(node)) { -+ struct regmap *con; -+ u32 mask; -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(con)) -+ regmap_write(con, 0, 3); -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,hifsys"); -+ if (IS_ERR(con)) { -+ dev_err(dev, "missing hifsys node\n"); -+ return PTR_ERR(con); -+ } -+ -+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; -+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); -+ } -+ - for_each_available_child_of_node(node, child) { - int slot; - diff --git a/target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch deleted file mode 100644 index f9a5fdbd0d..0000000000 --- a/target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Jip de Beer -Date: Sun, 9 Jan 2022 13:14:04 +0100 -Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts - -The lowest frequency should be 300MHz, since that is the label -assigned to the OPP in the mt7622.dtsi device tree, while there is one -missing zero in the actual value. - -To be clear, the lowest frequency should be 300MHz instead of 30MHz. - -As mentioned @dangowrt on the OpenWrt forum there is no benefit in -leaving 30MHz as the lowest frequency. - -Signed-off-by: Jip de Beer -Signed-off-by: Fritz D. Ansel ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -24,7 +24,7 @@ - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { -- opp-hz = /bits/ 64 <30000000>; -+ opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000>; - }; - diff --git a/target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch b/target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch deleted file mode 100644 index 92264eedf9..0000000000 --- a/target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -929,6 +929,16 @@ config LEDS_ACER_A500 - This option enables support for the Power Button LED of - Acer Iconia Tab A500. - -+config LEDS_UBNT_LEDBAR -+ tristate "LED support for Ubiquiti UniFi 6 LR" -+ depends on LEDS_CLASS && I2C && OF -+ help -+ This option enables support for the Ubiquiti LEDBAR -+ LED driver. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called leds-ubnt-ledbar. -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -93,6 +93,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA) += leds - obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o - obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o - obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o -+obj-$(CONFIG_LEDS_UBNT_LEDBAR) += leds-ubnt-ledbar.o - - # LED SPI Drivers - obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o diff --git a/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch deleted file mode 100644 index 987513eb45..0000000000 --- a/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ /dev/null @@ -1,65 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -308,7 +308,7 @@ - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ -- asm_sel { -+ asmsel: asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dts -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sata>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sata_phy>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dts -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch deleted file mode 100644 index 21fb98c19e..0000000000 --- a/target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -632,5 +632,28 @@ - }; - - &wmac { -+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x44000020 0x0 0x10002000 -+ 0x4400 0x4000000 0x0 0x0 -+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 -+ 0x41c4 0x26000000 0xc0c52600 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0xc6c6 -+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 -+ 0x83838382 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x84002e00 0x90000087 0x8a000000 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0xb000009 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x7707>; -+ - status = "okay"; - }; From 99cd44487e2e7205e1521a52faf498dfda6f100c Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sat, 30 Apr 2022 20:24:07 +0800 Subject: [PATCH 27/75] mediatek: mt7622: add irq for spi-nor controller Save some CPU from unnecessary polling and make SPI flash reading a tiny bit faster. Signed-off-by: Chuanhong Guo --- .../patches-5.15/104-mt7622-add-snor-irq.patch | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch diff --git a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch new file mode 100644 index 0000000000..506db69152 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -577,6 +577,7 @@ + compatible = "mediatek,mt7622-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0xe0>; ++ interrupts = ; + clocks = <&pericfg CLK_PERI_FLASH_PD>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; From 3816b2231cf7c5ae4f9a1bc35ea45c5ce6489a4f Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sat, 30 Apr 2022 22:35:27 +0800 Subject: [PATCH 28/75] mediatek: mt7623: disable various input devices Disable support for joysticks, micee and tablets. There's no actual driver selected in kconfig, and including kernel support is just a waste of space. Besides that, I believe nobody wants these on a router. Signed-off-by: Chuanhong Guo --- target/linux/mediatek/mt7623/config-5.15 | 46 +----------------------- 1 file changed, 1 insertion(+), 45 deletions(-) diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15 index 9fef4bbee3..58e45ba20e 100644 --- a/target/linux/mediatek/mt7623/config-5.15 +++ b/target/linux/mediatek/mt7623/config-5.15 @@ -269,14 +269,8 @@ CONFIG_IIO=y CONFIG_INITRAMFS_SOURCE="" CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_TABLET=y +# CONFIG_INPUT_MISC is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set @@ -295,33 +289,6 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADC is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_AS5011 is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_FSIA6B is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_PSXPAD_SPI is not set -# CONFIG_JOYSTICK_PXRC is not set -# CONFIG_JOYSTICK_QWIIC is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_XPAD is not set -# CONFIG_JOYSTICK_ZHENHUA is not set CONFIG_KALLSYMS=y CONFIG_KCMP=y CONFIG_KEYBOARD_MTK_PMIC=y @@ -374,11 +341,6 @@ CONFIG_MMC_SDHCI=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_PS2 is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_NAND_ECC_MEDIATEK is not set CONFIG_MTD_SPI_NOR=y @@ -549,12 +511,6 @@ CONFIG_SWPHY=y CONFIG_SWP_EMULATE=y CONFIG_SYNC_FILE=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TABLET_SERIAL_WACOM4 is not set -# CONFIG_TABLET_USB_ACECAD is not set -# CONFIG_TABLET_USB_AIPTEK is not set -# CONFIG_TABLET_USB_HANWANG is not set -# CONFIG_TABLET_USB_KBTAB is not set -# CONFIG_TABLET_USB_PEGASUS is not set CONFIG_THERMAL=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 From dcf7285b713e6e6633d7cbc71a9090ae27771e0f Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sat, 30 Apr 2022 22:49:26 +0800 Subject: [PATCH 29/75] mediatek: mt7629: disable auxadc in kconfig manually edit kconfig to disable MT6577_AUXADC Signed-off-by: Chuanhong Guo --- target/linux/mediatek/mt7629/config-5.15 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15 index cb4db9d165..02df7301ec 100644 --- a/target/linux/mediatek/mt7629/config-5.15 +++ b/target/linux/mediatek/mt7629/config-5.15 @@ -163,6 +163,7 @@ CONFIG_MACH_MT7629=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y +# CONFIG_MEDIATEK_MT6577_AUXADC is not set CONFIG_MEDIATEK_WATCHDOG=y CONFIG_MEMFD_CREATE=y CONFIG_MFD_SYSCON=y From d9ea9c06e98b597174e0e94e0a13934637c0c03e Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sat, 30 Apr 2022 23:08:00 +0800 Subject: [PATCH 30/75] mediatek: build ubnt-ledbar as a module The config for LEDS_UBNT_LEDBAR doesn't stay in mt7629 kconfig because of its I2C dependency. Build it as a module and let buildroot handle this config option instead. Signed-off-by: Chuanhong Guo --- target/linux/mediatek/image/mt7622.mk | 4 ++-- target/linux/mediatek/modules.mk | 16 ++++++++++++++++ target/linux/mediatek/mt7622/config-5.15 | 1 - target/linux/mediatek/mt7623/config-5.15 | 1 - 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 8e0126f576..39bc7bc2ea 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -228,7 +228,7 @@ define Device/ubnt_unifi-6-lr DEVICE_DTS_CONFIG := config@1 DEVICE_DTS := mt7622-ubnt-unifi-6-lr DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7915e + DEVICE_PACKAGES := kmod-mt7915e kmod-leds-ubnt-ledbar endef TARGET_DEVICES += ubnt_unifi-6-lr @@ -238,7 +238,7 @@ define Device/ubnt_unifi-6-lr-ubootmod DEVICE_VARIANT := U-Boot mod DEVICE_DTS := mt7622-ubnt-unifi-6-lr-ubootmod DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7915e + DEVICE_PACKAGES := kmod-mt7915e kmod-leds-ubnt-ledbar KERNEL := kernel-bin | lzma KERNEL_INITRAMFS_SUFFIX := -recovery.itb KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k diff --git a/target/linux/mediatek/modules.mk b/target/linux/mediatek/modules.mk index 467934256c..0eb2866cf0 100644 --- a/target/linux/mediatek/modules.mk +++ b/target/linux/mediatek/modules.mk @@ -38,3 +38,19 @@ define KernelPackage/sdhci-mtk endef $(eval $(call KernelPackage,sdhci-mtk)) + +define KernelPackage/leds-ubnt-ledbar + SUBMENU:=LED modules + TITLE:=Ubiquiti UniFi 6 LR LED support + KCONFIG:=CONFIG_LEDS_UBNT_LEDBAR + FILES:= \ + $(LINUX_DIR)/drivers/leds/leds-ubnt-ledbar.ko + AUTOLOAD:=$(call AutoProbe,leds-ubnt-ledbar,1) + DEPENDS:=@TARGET_mediatek_mt7622 +kmod-i2c-core +endef + +define KernelPackage/leds-ubnt-ledbar/description + LED support for Ubiquiti UniFi 6 LR +endef + +$(eval $(call KernelPackage,leds-ubnt-ledbar)) diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index 190782cb78..f89a1810b1 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -222,7 +222,6 @@ CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_JUMP_LABEL=y -CONFIG_LEDS_UBNT_LEDBAR=y CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15 index 58e45ba20e..07068c0d5f 100644 --- a/target/linux/mediatek/mt7623/config-5.15 +++ b/target/linux/mediatek/mt7623/config-5.15 @@ -297,7 +297,6 @@ CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_UBNT_LEDBAR is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y From e08942e76a162962892020a0f7e52ef751ec68e4 Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 27 Apr 2022 14:14:45 -0400 Subject: [PATCH 31/75] kernel: bump 5.10 to 5.10.113 All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200 Run-tested: bcm2711/RPi4B, mt7622/RT3200 Signed-off-by: John Audia --- include/kernel-5.10 | 4 ++-- ...serio-bits-as-platform-configuration.patch | 22 +++++++++---------- ...-function-to-disable-all-macb-clocks.patch | 8 +++---- ...-unprepare-clocks-in-case-of-failure.patch | 4 ++-- ...dd-support-for-sama7g5-gem-interface.patch | 6 ++--- ...d-support-for-sama7g5-emac-interface.patch | 4 ++-- ...ac-add-support-for-sama7g5-based-at_.patch | 8 +++---- ...ac-add-AXI-priority-support-and-reco.patch | 4 ++-- ...ault-usrio-config-to-default-gem-con.patch | 6 ++--- .../910-unaligned_access_hacks.patch | 4 ++-- ...rrypi-ts-Insert-delay-before-polling.patch | 2 +- ...c4-dsi-Introduce-a-variant-structure.patch | 2 +- ...the-dst-buffer-to-of_get_mac_address.patch | 4 ++-- .../pending-5.10/630-packet_socket_type.patch | 6 ++--- ...ng-with-source-address-failed-policy.patch | 18 +++++++-------- 15 files changed, 51 insertions(+), 51 deletions(-) diff --git a/include/kernel-5.10 b/include/kernel-5.10 index 6a0cb0c85a..eff17db834 100644 --- a/include/kernel-5.10 +++ b/include/kernel-5.10 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.10 = .112 -LINUX_KERNEL_HASH-5.10.112 = 8c6c1dc361ebb1ef63a7666b2069c9d7cdcec8ebb706b03780af1c8bb03b4aa5 +LINUX_VERSION-5.10 = .113 +LINUX_KERNEL_HASH-5.10.113 = 82516a02bb52456f6e8057217dde6e02b78003b1e058117557c2ae9661696dfc diff --git a/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch b/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch index 6336c92d1f..79e7e62440 100644 --- a/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch +++ b/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch @@ -49,7 +49,7 @@ Signed-off-by: David S. Miller #ifdef CONFIG_MACB_USE_HWSTAMP --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3823,15 +3823,15 @@ static int macb_init(struct platform_dev +@@ -3831,15 +3831,15 @@ static int macb_init(struct platform_dev if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { val = 0; if (phy_interface_mode_is_rgmii(bp->phy_interface)) @@ -69,7 +69,7 @@ Signed-off-by: David S. Miller macb_or_gem_writel(bp, USRIO, val); } -@@ -4349,6 +4349,13 @@ static int fu540_c000_init(struct platfo +@@ -4357,6 +4357,13 @@ static int fu540_c000_init(struct platfo return macb_init(pdev); } @@ -83,7 +83,7 @@ Signed-off-by: David S. Miller static const struct macb_config fu540_c000_config = { .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | MACB_CAPS_GEM_HAS_PTP, -@@ -4356,12 +4363,14 @@ static const struct macb_config fu540_c0 +@@ -4364,12 +4371,14 @@ static const struct macb_config fu540_c0 .clk_init = fu540_c000_clk_init, .init = fu540_c000_init, .jumbo_max_len = 10240, @@ -98,7 +98,7 @@ Signed-off-by: David S. Miller }; static const struct macb_config sama5d3macb_config = { -@@ -4369,6 +4378,7 @@ static const struct macb_config sama5d3m +@@ -4377,6 +4386,7 @@ static const struct macb_config sama5d3m | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, .clk_init = macb_clk_init, .init = macb_init, @@ -106,7 +106,7 @@ Signed-off-by: David S. Miller }; static const struct macb_config pc302gem_config = { -@@ -4376,6 +4386,7 @@ static const struct macb_config pc302gem +@@ -4384,6 +4394,7 @@ static const struct macb_config pc302gem .dma_burst_length = 16, .clk_init = macb_clk_init, .init = macb_init, @@ -114,7 +114,7 @@ Signed-off-by: David S. Miller }; static const struct macb_config sama5d2_config = { -@@ -4383,6 +4394,7 @@ static const struct macb_config sama5d2_ +@@ -4391,6 +4402,7 @@ static const struct macb_config sama5d2_ .dma_burst_length = 16, .clk_init = macb_clk_init, .init = macb_init, @@ -122,7 +122,7 @@ Signed-off-by: David S. Miller }; static const struct macb_config sama5d3_config = { -@@ -4392,6 +4404,7 @@ static const struct macb_config sama5d3_ +@@ -4400,6 +4412,7 @@ static const struct macb_config sama5d3_ .clk_init = macb_clk_init, .init = macb_init, .jumbo_max_len = 10240, @@ -130,7 +130,7 @@ Signed-off-by: David S. Miller }; static const struct macb_config sama5d4_config = { -@@ -4399,18 +4412,21 @@ static const struct macb_config sama5d4_ +@@ -4407,18 +4420,21 @@ static const struct macb_config sama5d4_ .dma_burst_length = 4, .clk_init = macb_clk_init, .init = macb_init, @@ -152,7 +152,7 @@ Signed-off-by: David S. Miller }; static const struct macb_config zynqmp_config = { -@@ -4421,6 +4437,7 @@ static const struct macb_config zynqmp_c +@@ -4429,6 +4445,7 @@ static const struct macb_config zynqmp_c .clk_init = macb_clk_init, .init = macb_init, .jumbo_max_len = 10240, @@ -160,7 +160,7 @@ Signed-off-by: David S. Miller }; static const struct macb_config zynq_config = { -@@ -4429,6 +4446,7 @@ static const struct macb_config zynq_con +@@ -4437,6 +4454,7 @@ static const struct macb_config zynq_con .dma_burst_length = 16, .clk_init = macb_clk_init, .init = macb_init, @@ -168,7 +168,7 @@ Signed-off-by: David S. Miller }; static const struct of_device_id macb_dt_ids[] = { -@@ -4549,6 +4567,8 @@ static int macb_probe(struct platform_de +@@ -4557,6 +4575,8 @@ static int macb_probe(struct platform_de bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); diff --git a/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch b/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch index 20c9a4b615..a474f2a405 100644 --- a/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch +++ b/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch @@ -14,7 +14,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3598,6 +3598,20 @@ static void macb_probe_queues(void __iom +@@ -3606,6 +3606,20 @@ static void macb_probe_queues(void __iom *num_queues = hweight32(*queue_mask); } @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, struct clk **hclk, struct clk **tx_clk, struct clk **rx_clk, struct clk **tsu_clk) -@@ -4660,11 +4674,7 @@ err_out_free_netdev: +@@ -4668,11 +4682,7 @@ err_out_free_netdev: free_netdev(dev); err_disable_clocks: @@ -48,7 +48,7 @@ Signed-off-by: David S. Miller pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_runtime_dont_use_autosuspend(&pdev->dev); -@@ -4689,11 +4699,8 @@ static int macb_remove(struct platform_d +@@ -4697,11 +4707,8 @@ static int macb_remove(struct platform_d pm_runtime_disable(&pdev->dev); pm_runtime_dont_use_autosuspend(&pdev->dev); if (!pm_runtime_suspended(&pdev->dev)) { @@ -62,7 +62,7 @@ Signed-off-by: David S. Miller pm_runtime_set_suspended(&pdev->dev); } phylink_destroy(bp->phylink); -@@ -4872,13 +4879,10 @@ static int __maybe_unused macb_runtime_s +@@ -4880,13 +4887,10 @@ static int __maybe_unused macb_runtime_s struct net_device *netdev = dev_get_drvdata(dev); struct macb *bp = netdev_priv(netdev); diff --git a/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch b/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch index e87089e393..7456cc6c52 100644 --- a/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch +++ b/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch @@ -14,7 +14,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4330,8 +4330,10 @@ static int fu540_c000_clk_init(struct pl +@@ -4338,8 +4338,10 @@ static int fu540_c000_clk_init(struct pl return err; mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); @@ -27,7 +27,7 @@ Signed-off-by: David S. Miller init.name = "sifive-gemgxl-mgmt"; init.ops = &fu540_c000_ops; -@@ -4342,16 +4344,26 @@ static int fu540_c000_clk_init(struct pl +@@ -4350,16 +4352,26 @@ static int fu540_c000_clk_init(struct pl mgmt->hw.init = &init; *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw); diff --git a/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch b/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch index 3e1d12da7e..64abd3d6c0 100644 --- a/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch +++ b/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch @@ -14,7 +14,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4382,6 +4382,14 @@ static const struct macb_usrio_config ma +@@ -4390,6 +4390,14 @@ static const struct macb_usrio_config ma .refclk = MACB_BIT(CLKEN), }; @@ -29,7 +29,7 @@ Signed-off-by: David S. Miller static const struct macb_config fu540_c000_config = { .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | MACB_CAPS_GEM_HAS_PTP, -@@ -4475,6 +4483,14 @@ static const struct macb_config zynq_con +@@ -4483,6 +4491,14 @@ static const struct macb_config zynq_con .usrio = &macb_default_usrio, }; @@ -44,7 +44,7 @@ Signed-off-by: David S. Miller static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,at32ap7000-macb" }, { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, -@@ -4492,6 +4508,7 @@ static const struct of_device_id macb_dt +@@ -4500,6 +4516,7 @@ static const struct of_device_id macb_dt { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, { .compatible = "cdns,zynq-gem", .data = &zynq_config }, { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, diff --git a/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch b/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch index e8b04742f2..50d31f736b 100644 --- a/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch +++ b/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch @@ -14,7 +14,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4491,6 +4491,14 @@ static const struct macb_config sama7g5_ +@@ -4499,6 +4499,14 @@ static const struct macb_config sama7g5_ .usrio = &sama7g5_usrio, }; @@ -29,7 +29,7 @@ Signed-off-by: David S. Miller static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,at32ap7000-macb" }, { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, -@@ -4509,6 +4517,7 @@ static const struct of_device_id macb_dt +@@ -4517,6 +4525,7 @@ static const struct of_device_id macb_dt { .compatible = "cdns,zynq-gem", .data = &zynq_config }, { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, diff --git a/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch b/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch index f91afdf0aa..40d0206b47 100644 --- a/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch +++ b/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch @@ -238,7 +238,7 @@ Signed-off-by: Vinod Koul while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) cpu_relax(); } -@@ -1760,7 +1810,7 @@ static int at_xdmac_device_pause(struct +@@ -1762,7 +1812,7 @@ static int at_xdmac_device_pause(struct return 0; spin_lock_irqsave(&atchan->lock, flags); @@ -247,7 +247,7 @@ Signed-off-by: Vinod Koul while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) cpu_relax(); -@@ -1783,7 +1833,7 @@ static int at_xdmac_device_resume(struct +@@ -1785,7 +1835,7 @@ static int at_xdmac_device_resume(struct return 0; } @@ -256,7 +256,7 @@ Signed-off-by: Vinod Koul clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); spin_unlock_irqrestore(&atchan->lock, flags); -@@ -1985,6 +2035,10 @@ static int at_xdmac_probe(struct platfor +@@ -1987,6 +2037,10 @@ static int at_xdmac_probe(struct platfor atxdmac->regs = base; atxdmac->irq = irq; @@ -267,7 +267,7 @@ Signed-off-by: Vinod Koul atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); if (IS_ERR(atxdmac->clk)) { dev_err(&pdev->dev, "can't get dma_clk\n"); -@@ -2127,6 +2181,10 @@ static const struct dev_pm_ops atmel_xdm +@@ -2129,6 +2183,10 @@ static const struct dev_pm_ops atmel_xdm static const struct of_device_id atmel_xdmac_dt_ids[] = { { .compatible = "atmel,sama5d4-dma", diff --git a/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch b/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch index 50a0cfc3b5..faca34ff09 100644 --- a/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch +++ b/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch @@ -71,7 +71,7 @@ Signed-off-by: Vinod Koul }; static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) -@@ -1996,6 +2017,30 @@ static int atmel_xdmac_resume(struct dev +@@ -1998,6 +2019,30 @@ static int atmel_xdmac_resume(struct dev } #endif /* CONFIG_PM_SLEEP */ @@ -102,7 +102,7 @@ Signed-off-by: Vinod Koul static int at_xdmac_probe(struct platform_device *pdev) { struct at_xdmac *atxdmac; -@@ -2140,6 +2185,8 @@ static int at_xdmac_probe(struct platfor +@@ -2142,6 +2187,8 @@ static int at_xdmac_probe(struct platfor dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", nr_channels, atxdmac->regs); diff --git a/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch b/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch index b5d4c3237c..721ddaea00 100644 --- a/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch +++ b/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch @@ -20,7 +20,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3860,6 +3860,13 @@ static int macb_init(struct platform_dev +@@ -3868,6 +3868,13 @@ static int macb_init(struct platform_dev return 0; } @@ -34,7 +34,7 @@ Signed-off-by: David S. Miller #if defined(CONFIG_OF) /* 1518 rounded up */ #define AT91ETHER_MAX_RBUFF_SZ 0x600 -@@ -4375,13 +4382,6 @@ static int fu540_c000_init(struct platfo +@@ -4383,13 +4390,6 @@ static int fu540_c000_init(struct platfo return macb_init(pdev); } @@ -48,7 +48,7 @@ Signed-off-by: David S. Miller static const struct macb_usrio_config sama7g5_usrio = { .mii = 0, .rmii = 1, -@@ -4530,6 +4530,7 @@ static const struct macb_config default_ +@@ -4538,6 +4538,7 @@ static const struct macb_config default_ .dma_burst_length = 16, .clk_init = macb_clk_init, .init = macb_init, diff --git a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch index 836c0f6dae..4a85701b0c 100644 --- a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch @@ -799,7 +799,7 @@ *sum = csum_fold(csum_partial(diff, sizeof(diff), --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h -@@ -500,7 +500,7 @@ static inline bool is_etherdev_addr(cons +@@ -499,7 +499,7 @@ static inline bool is_etherdev_addr(cons * @b: Pointer to Ethernet header * * Compare two Ethernet headers, returns 0 if equal. @@ -808,7 +808,7 @@ * aligned OR the platform can handle unaligned access. This is the * case for all packets coming into netif_receive_skb or similar * entry points. -@@ -523,11 +523,12 @@ static inline unsigned long compare_ethe +@@ -522,11 +522,12 @@ static inline unsigned long compare_ethe fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6); return fold; #else diff --git a/target/linux/bcm27xx/patches-5.10/950-0383-drm-panel-raspberrypi-ts-Insert-delay-before-polling.patch b/target/linux/bcm27xx/patches-5.10/950-0383-drm-panel-raspberrypi-ts-Insert-delay-before-polling.patch index ce838a6114..a9a5a01ed2 100644 --- a/target/linux/bcm27xx/patches-5.10/950-0383-drm-panel-raspberrypi-ts-Insert-delay-before-polling.patch +++ b/target/linux/bcm27xx/patches-5.10/950-0383-drm-panel-raspberrypi-ts-Insert-delay-before-polling.patch @@ -16,7 +16,7 @@ Signed-off-by: Dave Stevenson --- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c +++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c -@@ -299,6 +299,7 @@ static int rpi_touchscreen_enable(struct +@@ -299,6 +299,7 @@ static int rpi_touchscreen_prepare(struc int i; rpi_touchscreen_i2c_write(ts, REG_POWERON, 1); diff --git a/target/linux/bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch b/target/linux/bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch index c24bb4417e..4e7671ace1 100644 --- a/target/linux/bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch +++ b/target/linux/bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch @@ -66,7 +66,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-5-maxi struct vc4_dsi_encoder { @@ -837,7 +848,7 @@ static void vc4_dsi_encoder_enable(struc - ret = pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); if (ret) { - DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port); + DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); diff --git a/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch b/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch index fe12ffd9cc..42c16034e4 100644 --- a/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch +++ b/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch @@ -423,7 +423,7 @@ Signed-off-by: David S. Miller if (bgmac->irq < 0) --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4479,7 +4479,6 @@ static int macb_probe(struct platform_de +@@ -4487,7 +4487,6 @@ static int macb_probe(struct platform_de struct net_device *dev; struct resource *regs; void __iomem *mem; @@ -431,7 +431,7 @@ Signed-off-by: David S. Miller struct macb *bp; int err, val; -@@ -4592,15 +4591,11 @@ static int macb_probe(struct platform_de +@@ -4600,15 +4599,11 @@ static int macb_probe(struct platform_de if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR) bp->rx_intr_mask |= MACB_BIT(RXUBR); diff --git a/target/linux/generic/pending-5.10/630-packet_socket_type.patch b/target/linux/generic/pending-5.10/630-packet_socket_type.patch index 5b396c3a8c..26fd8bc754 100644 --- a/target/linux/generic/pending-5.10/630-packet_socket_type.patch +++ b/target/linux/generic/pending-5.10/630-packet_socket_type.patch @@ -87,7 +87,7 @@ Signed-off-by: Felix Fietkau if (!net_eq(dev_net(dev), sock_net(sk))) goto drop; -@@ -3325,6 +3327,7 @@ static int packet_create(struct net *net +@@ -3330,6 +3332,7 @@ static int packet_create(struct net *net mutex_init(&po->pg_vec_lock); po->rollover = NULL; po->prot_hook.func = packet_rcv; @@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau if (sock->type == SOCK_PACKET) po->prot_hook.func = packet_rcv_spkt; -@@ -3969,6 +3972,16 @@ packet_setsockopt(struct socket *sock, i +@@ -3974,6 +3977,16 @@ packet_setsockopt(struct socket *sock, i po->xmit = val ? packet_direct_xmit : dev_queue_xmit; return 0; } @@ -112,7 +112,7 @@ Signed-off-by: Felix Fietkau default: return -ENOPROTOOPT; } -@@ -4025,6 +4038,13 @@ static int packet_getsockopt(struct sock +@@ -4030,6 +4043,13 @@ static int packet_getsockopt(struct sock case PACKET_VNET_HDR: val = po->has_vnet_hdr; break; diff --git a/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch index d85735531b..ffdfaf6c23 100644 --- a/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch +++ b/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski case RTN_THROW: case RTN_UNREACHABLE: default: -@@ -4448,6 +4467,17 @@ static int ip6_pkt_prohibit_out(struct n +@@ -4449,6 +4468,17 @@ static int ip6_pkt_prohibit_out(struct n return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES); } @@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski /* * Allocate a dst for local (unicast / anycast) address. */ -@@ -4928,7 +4958,8 @@ static int rtm_to_fib6_config(struct sk_ +@@ -4929,7 +4959,8 @@ static int rtm_to_fib6_config(struct sk_ if (rtm->rtm_type == RTN_UNREACHABLE || rtm->rtm_type == RTN_BLACKHOLE || rtm->rtm_type == RTN_PROHIBIT || @@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski cfg->fc_flags |= RTF_REJECT; if (rtm->rtm_type == RTN_LOCAL) -@@ -6127,6 +6158,8 @@ static int ip6_route_dev_notify(struct n +@@ -6128,6 +6159,8 @@ static int ip6_route_dev_notify(struct n #ifdef CONFIG_IPV6_MULTIPLE_TABLES net->ipv6.ip6_prohibit_entry->dst.dev = dev; net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); @@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski net->ipv6.ip6_blk_hole_entry->dst.dev = dev; net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); #endif -@@ -6138,6 +6171,7 @@ static int ip6_route_dev_notify(struct n +@@ -6139,6 +6172,7 @@ static int ip6_route_dev_notify(struct n in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev); #ifdef CONFIG_IPV6_MULTIPLE_TABLES in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev); @@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev); #endif } -@@ -6329,6 +6363,8 @@ static int __net_init ip6_route_net_init +@@ -6330,6 +6364,8 @@ static int __net_init ip6_route_net_init #ifdef CONFIG_IPV6_MULTIPLE_TABLES net->ipv6.fib6_has_custom_rules = false; @@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template, sizeof(*net->ipv6.ip6_prohibit_entry), GFP_KERNEL); -@@ -6339,11 +6375,21 @@ static int __net_init ip6_route_net_init +@@ -6340,11 +6376,21 @@ static int __net_init ip6_route_net_init ip6_template_metrics, true); INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached); @@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, ip6_template_metrics, true); -@@ -6370,6 +6416,8 @@ out: +@@ -6371,6 +6417,8 @@ out: return ret; #ifdef CONFIG_IPV6_MULTIPLE_TABLES @@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski out_ip6_prohibit_entry: kfree(net->ipv6.ip6_prohibit_entry); out_ip6_null_entry: -@@ -6389,6 +6437,7 @@ static void __net_exit ip6_route_net_exi +@@ -6390,6 +6438,7 @@ static void __net_exit ip6_route_net_exi kfree(net->ipv6.ip6_null_entry); #ifdef CONFIG_IPV6_MULTIPLE_TABLES kfree(net->ipv6.ip6_prohibit_entry); @@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski kfree(net->ipv6.ip6_blk_hole_entry); #endif dst_entries_destroy(&net->ipv6.ip6_dst_ops); -@@ -6466,6 +6515,9 @@ void __init ip6_route_init_special_entri +@@ -6467,6 +6516,9 @@ void __init ip6_route_init_special_entri init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); From 714b88c1ab2a59c2b4408e5ef4a153a87a135e39 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 30 Apr 2022 20:17:24 +0200 Subject: [PATCH 32/75] kernel: 5.15: add missing symbol CONFIG_QCOM_SPMI_ADC_TM5 gets uncovered while building IPQ40xx with 5.15. Signed-off-by: Robert Marko --- target/linux/generic/config-5.15 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index 7cffea43a5..bc5ecb4d72 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -4837,6 +4837,7 @@ CONFIG_PWRSEQ_SIMPLE=y # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set # CONFIG_QCOM_SPMI_ADC5 is not set +# CONFIG_QCOM_SPMI_ADC_TM5 is not set # CONFIG_QCOM_SPMI_IADC is not set # CONFIG_QCOM_SPMI_TEMP_ALARM is not set # CONFIG_QCOM_SPMI_VADC is not set From aeaa816cd2bd22de165c71a41d8d198a9235e971 Mon Sep 17 00:00:00 2001 From: Huangbin Zhan Date: Sun, 24 Apr 2022 09:58:25 +0800 Subject: [PATCH 33/75] build: don't remove BUILD_LOG_DIR in _clean targetclean should not remove BUILD_LOG Fixes: db34b93331e9 (add a version that can be bumped to force toolchain/target rebuild) Signed-off-by: Huangbin Zhan --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d85df6c3cf..3ac110367d 100644 --- a/Makefile +++ b/Makefile @@ -51,7 +51,7 @@ printdb: prepare: $(target/stamp-compile) _clean: FORCE - rm -rf $(BUILD_DIR) $(STAGING_DIR) $(BIN_DIR) $(OUTPUT_DIR)/packages/$(ARCH_PACKAGES) $(BUILD_LOG_DIR) $(TOPDIR)/staging_dir/packages + rm -rf $(BUILD_DIR) $(STAGING_DIR) $(BIN_DIR) $(OUTPUT_DIR)/packages/$(ARCH_PACKAGES) $(TOPDIR)/staging_dir/packages clean: _clean rm -rf $(BUILD_LOG_DIR) From 1d06277407d3e294589ecde46328303a9f3803fd Mon Sep 17 00:00:00 2001 From: Martin Kennedy Date: Tue, 26 Apr 2022 17:04:06 -0400 Subject: [PATCH 34/75] mpc85xx: Fix output location of padded dtb In commit 7e614820a892 ("mpc85xx: add support for Extreme Networks WS-AP3825i"), we borrowed a recipe convention from apm821xx for device tree blob padding. Unfortunately, in the apm821xx target, the image recipes name the device tree blob differently, meaning that in mpc85xx, the padded dtb is never consumed. Change the definition of `Build/dtb` so that it outputs the padded dtb to the correct location for it to be consumed. Also, rename the recipe to `Build/pad-dtb`, so it is clear we are building and padding the device tree blob. This change fixes Github issue #9779 [1]. [1]: https://github.com/openwrt/openwrt/issues/9779 Fixes: 7e614820a892 ("mpc85xx: add support for Extreme Networks WS-AP3825i") Signed-off-by: Martin Kennedy --- target/linux/mpc85xx/image/Makefile | 4 ++-- target/linux/mpc85xx/image/p1020.mk | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/linux/mpc85xx/image/Makefile b/target/linux/mpc85xx/image/Makefile index e1d1bc6948..d502650a32 100644 --- a/target/linux/mpc85xx/image/Makefile +++ b/target/linux/mpc85xx/image/Makefile @@ -5,8 +5,8 @@ include $(INCLUDE_DIR)/image.mk DEVICE_VARS += DTB_SIZE -define Build/dtb - $(call Image/BuildDTB,$(DTS_DIR)/$(DEVICE_DTS).dts,$@.dtb,,--space $(DTB_SIZE)) +define Build/pad-dtb + $(call Image/BuildDTB,$(DTS_DIR)/$(DEVICE_DTS).dts,$(dir $@)/image-$(DEVICE_DTS).dtb,,--space $(DTB_SIZE)) endef define Device/Default diff --git a/target/linux/mpc85xx/image/p1020.mk b/target/linux/mpc85xx/image/p1020.mk index 234bdc26a1..6fdbfd664a 100644 --- a/target/linux/mpc85xx/image/p1020.mk +++ b/target/linux/mpc85xx/image/p1020.mk @@ -74,7 +74,7 @@ define Device/extreme-networks_ws-ap3825i DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct BLOCKSIZE := 128k DTB_SIZE := 20480 - KERNEL = kernel-bin | lzma | dtb | fit lzma $(KDIR)/image-$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | lzma | pad-dtb | fit lzma $(KDIR)/image-$$(DEVICE_DTS).dtb IMAGES := sysupgrade.bin IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata endef From 57b6dcd826b13eab2101f9c8e96d43ab251e8dc1 Mon Sep 17 00:00:00 2001 From: Davide Fioravanti Date: Mon, 18 Apr 2022 16:54:40 +0200 Subject: [PATCH 35/75] ramips: create shared DTSI for Wavlink WN53XAX devices Most of the definitions for WN531A6 will be shared with WN533A8 in a future commit, so put them in a shared DTSI. Signed-off-by: Davide Fioravanti --- .../ramips/dts/mt7621_wavlink_wl-wn531a6.dts | 197 ++---------------- .../ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi | 194 +++++++++++++++++ 2 files changed, 207 insertions(+), 184 deletions(-) create mode 100644 target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi diff --git a/target/linux/ramips/dts/mt7621_wavlink_wl-wn531a6.dts b/target/linux/ramips/dts/mt7621_wavlink_wl-wn531a6.dts index f8c6bffb40..0d6c81cf62 100644 --- a/target/linux/ramips/dts/mt7621_wavlink_wl-wn531a6.dts +++ b/target/linux/ramips/dts/mt7621_wavlink_wl-wn531a6.dts @@ -1,203 +1,32 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "mt7621.dtsi" - -#include -#include +#include "mt7621_wavlink_wl-wn53xax.dtsi" / { compatible = "wavlink,wl-wn531a6", "mediatek,mt7621-soc"; model = "Wavlink WL-WN531A6"; - - aliases { - led-boot = &led_status_red; - led-failsafe = &led_status_red; - led-running = &led_status_blue; - led-upgrade = &led_status_red; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "Reset Button"; - gpios = <&gpio 18 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - touch { /* RH6015C touch sensor -> GPIO 14 */ - label = "Touch Button"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - turbo { - label = "Turbo Button"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "WPS Button"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_status_blue: status_blue { - label = "blue:power"; - gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - }; - - led_status_red: status_red { - label = "red:power"; - gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - }; - - wifi2g { - label = "blue:wifi2g"; - gpios = <&gpio 23 GPIO_ACTIVE_LOW>; - linux,default-trigger = "phy0tpt"; - }; - }; }; -&i2c { - status = "okay"; +&wifi0{ + ieee80211-freq-limit = <2400000 2500000>; }; -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "config"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x50000 0xeb0000>; - }; - - partition@f00000 { - label = "vendor"; - reg = <0xf00000 0x100000>; - read-only; - }; - }; - }; +&wifi1{ + ieee80211-freq-limit = <5000000 6000000>; }; -&pcie { - status = "okay"; +&port0{ + label = "lan1"; }; -&pcie0 { - mt76@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x0>; - ieee80211-freq-limit = <2400000 2500000>; - }; +&port1{ + label = "lan2"; }; -&pcie1 { - mt76@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x8000>; - ieee80211-freq-limit = <5000000 6000000>; - }; +&port2{ + label = "lan3"; }; -ðernet { - pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>; -}; - -&gmac0 { - nvmem-cells = <&macaddr_factory_e000>; - nvmem-cell-names = "mac-address"; -}; - -&switch0 { - ports { - port@0 { - status = "okay"; - label = "lan1"; - }; - - port@1 { - status = "okay"; - label = "lan2"; - }; - - port@2 { - status = "okay"; - label = "lan3"; - }; - - port@3 { - status = "okay"; - label = "lan4"; - }; - - port@4 { - status = "okay"; - label = "wan"; - nvmem-cells = <&macaddr_factory_e006>; - nvmem-cell-names = "mac-address"; - }; - }; -}; - -&state_default { - gpio { - groups = "rgmii2", "jtag", "wdt"; - function = "gpio"; - }; -}; - -&uartlite2 { - status = "okay"; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_e000: macaddr@e000 { - reg = <0xe000 0x6>; - }; - - macaddr_factory_e006: macaddr@e006 { - reg = <0xe006 0x6>; - }; +&port3{ + label = "lan4"; }; diff --git a/target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi b/target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi new file mode 100644 index 0000000000..843e9a30c7 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621.dtsi" + +#include +#include + +/ { + aliases { + led-boot = &led_status_red; + led-failsafe = &led_status_red; + led-running = &led_status_blue; + led-upgrade = &led_status_red; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset Button"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + touch { /* RH6015C touch sensor -> GPIO 14 */ + label = "Touch Button"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + turbo { + label = "Turbo Button"; + gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "WPS Button"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_blue: status_blue { + label = "blue:power"; + gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + }; + + led_status_red: status_red { + label = "red:power"; + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + }; + + wifi2g { + label = "blue:wifi2g"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; +}; + +&i2c { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "config"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0xeb0000>; + }; + + partition@f00000 { + label = "vendor"; + reg = <0xf00000 0x100000>; + read-only; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pcie0 { + wifi0: mt76@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x0>; + }; +}; + +&pcie1 { + wifi1: mt76@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x8000>; + }; +}; + +ðernet { + pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_e000>; + nvmem-cell-names = "mac-address"; +}; + +&switch0 { + ports { + port0: port@0 { + status = "okay"; + }; + + port1: port@1 { + status = "okay"; + }; + + port2: port@2 { + status = "okay"; + }; + + port3: port@3 { + status = "okay"; + }; + + port@4 { + status = "okay"; + label = "wan"; + nvmem-cells = <&macaddr_factory_e006>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&state_default { + gpio { + groups = "rgmii2", "jtag", "wdt"; + function = "gpio"; + }; +}; + +&uartlite2 { + status = "okay"; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_e000: macaddr@e000 { + reg = <0xe000 0x6>; + }; + + macaddr_factory_e006: macaddr@e006 { + reg = <0xe006 0x6>; + }; +}; From 32e6942d72b6426d65eaa4dc7f2ba949b3c32985 Mon Sep 17 00:00:00 2001 From: Davide Fioravanti Date: Mon, 18 Apr 2022 17:35:33 +0200 Subject: [PATCH 36/75] ramips: add support for Wavlink WL-WN533A8 The Wavlink WL-WN533A8 is an AC3000 router with 5 gigabit ethernet ports and one USB 3.0 port. It's also known as Wavlink QUANTUM T8. Hardware -------- SoC: Mediatek MT7621A RAM: 128MB (Nanya NT5CB64M16GP-EK) FLASH: 16MB NOR (GigaDevice GD25Q127CSIG3) ETH: - 5x 10/100/1000 Mbps Ethernet (4x LAN + 1x WAN) WIFI: - 1x MT7615DN (2x 2x2:2) 2.4GHz and 5GHz DBDC - 1x MT7615NE (4x4:4) 5GHz - 8 external antennas BTN: - 1x Reset button - 1x WPS button - 1x Turbo button - 1x Touchlink button - 1x ON/OFF switch LEDS: - 1x Red led (system status) - 1x Blue led (system status) - 7x Blue leds (wifi led + 5 ethernet ports + power) USB: - 1x USB 3.0 port UART: - 57600-8-N-1 J4 Everything works correctly. Installation ------------ Flash the initramfs image in the OEM firmware interface (http://192.168.10.1/update.shtml). When Openwrt boots, flash the sysupgrade image otherwise you won't be able to keep configuration between reboots. (Procedure tested on fw M33A8.V5030.190716 and M33A8.V5030.201204) Restore OEM Firmware -------------------- Flash the firmware update available online directly from LUCI. You can download it from: https://www.wavlink.com/en_us/firmware/details/f2d247ecba.html Warning: Remember to not keep settings! Warning2: Remember to force the flash. Notes ----- 1) Router mac addresses: LAN XX:XX:XX:XX:XX:63 (factory @ 0xe006) WAN XX:XX:XX:XX:XX:64 (factory @ 0xe000) WIFI 2G/5G XX:XX:XX:XX:XX:65 (factory @ 0x04) WIFI 5G XX:XX:XX:XX:XX:66 (factory @ 0x8004) LABEL XX:XX:XX:XX:XX:65 In OEM firmware the DBDC wifi interfaces have these mac addresses: 2G) 82:XX:XX:XX:XX:65 5G) 80:XX:XX:XX:XX:65 While in OpenWrt the addresses are: 2G) 80:XX:XX:XX:XX:65 5G) 02:XX:XX:XX:XX:65 2) radio0 will show as 2G/5G interface but only 2G is really usable. 3) There is just one wifi led for all wifi interfaces. It currently shows only the radio0 GHz wifi activity. 4) My unit was shipped with M33A8.V5030.190716 firmware which contains the http://192.168.10.1/webcmd.shtml page. Entering "telnetd" in the input box it will start the telnet daemon. Now you can access the telnet console on port 2323 with these credentials: username: admin2860 password: admin 5) The M33A8.V5030.201204 firmware version, doesn't contain anymore the webcmd.shtml page. If your router is shipped with a previous firmware version and you want to back it up, you can follow the back up procedure of the WS-WN583A6. Signed-off-by: Davide Fioravanti --- .../ramips/dts/mt7621_wavlink_wl-wn533a8.dts | 32 +++++++++++++++++++ target/linux/ramips/image/mt7621.mk | 10 ++++++ .../mt7621/base-files/etc/board.d/02_network | 1 + 3 files changed, 43 insertions(+) create mode 100644 target/linux/ramips/dts/mt7621_wavlink_wl-wn533a8.dts diff --git a/target/linux/ramips/dts/mt7621_wavlink_wl-wn533a8.dts b/target/linux/ramips/dts/mt7621_wavlink_wl-wn533a8.dts new file mode 100644 index 0000000000..9a601d6d18 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_wavlink_wl-wn533a8.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621_wavlink_wl-wn53xax.dtsi" + +/ { + compatible = "wavlink,wl-wn533a8", "mediatek,mt7621-soc"; + model = "Wavlink WL-WN533A8"; +}; + +&wifi0{ + ieee80211-freq-limit = <2400000 5490000>; +}; + +&wifi1{ + ieee80211-freq-limit = <5490000 6000000>; +}; + +&port0{ + label = "lan4"; +}; + +&port1{ + label = "lan3"; +}; + +&port2{ + label = "lan2"; +}; + +&port3{ + label = "lan1"; +}; diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 3793bf69d6..5844682a40 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -1762,6 +1762,16 @@ define Device/wavlink_wl-wn531a6 endef TARGET_DEVICES += wavlink_wl-wn531a6 +define Device/wavlink_wl-wn533a8 + $(Device/dsa-migration) + DEVICE_VENDOR := Wavlink + DEVICE_MODEL := WL-WN533A8 + KERNEL_INITRAMFS_SUFFIX := -WN533A8$$(KERNEL_SUFFIX) + DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 + IMAGE_SIZE := 15040k +endef +TARGET_DEVICES += wavlink_wl-wn533a8 + define Device/wevo_11acnas $(Device/dsa-migration) $(Device/uimage-lzma-loader) diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index 75842f4cbc..688c39940d 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -166,6 +166,7 @@ ramips_setup_macs() ;; jcg,y2|\ wavlink,wl-wn531a6|\ + wavlink,wl-wn533a8|\ winstars,ws-wn583a6|\ zbtlink,zbt-we1326|\ zbtlink,zbt-wg3526-16m|\ From 063e9047cc8b247ea4b04ee3248b99f3212a42f8 Mon Sep 17 00:00:00 2001 From: Foica David Date: Thu, 21 Apr 2022 04:20:57 +0300 Subject: [PATCH 37/75] ath79: add support for TP-Link Deco M4R v1 and v2 This commit adds support for the TP-Link Deco M4R (it can also be M4, TP-Link uses both names) v1 and v2. It is similar hardware-wise to the Archer C6 v2. Software-wise it is very different. V2 has a bit different layout from V1 but the chips are the same and the OEM firmware is the same for both versions. Specifications: SoC: QCA9563-AL3A RAM: Zentel A3R1GE40JBF Wireless 2.4GHz: QCA9563-AL3A (main SoC) Wireless 5GHz: QCA9886 Ethernet Switch: QCA8337N-AL3C Flash: 16 MB SPI NOR Flashing: The device's bootloader only accepts images that are signed using TP-Link's RSA key, therefore this way of flashing is not possible. The device has a web GUI that should be accessible after setting up the device using the app (it requires the app to set it up first because the web GUI asks for the TP-Link account password) but for unknown reasons, the web GUI also refuses custom images. There is a debug firmware image that has been shared on the device's OpenWrt forum thread that has telnet unlocked, which the bootloader will accept because it is signed. It can be used to transfer an OpenWrt image file over to the device and then be used with mtd to flash the device. Pre-requisites: - Debug firmware. - A way of transferring the file to the router, you can use an FTP server as an example. - Set a static IP of 192.168.0.2/255.255.255.0 on your computer. - OpenWrt image. Installation: - Unplug your router and turn it upside down. Using a long and thin object like a SIM unlock tool, press and hold the reset button on the router and replug it. Keep holding it until the LED flashes yellow. - Open 192.168.0.1. You should see the bootloader recovery's webpage. Choose the debug firmware that you downloaded and flash it. Wait until the router reboots (at this stage you can remove the static IP). - Open a terminal window and connect to the router via telnet (the primary router should have a 192.168.0.1 IP address, secondary routers are different). - Transfer the file over to the router, you can use curl to download it from the internet (use the insecure flag and make sure your source accepts insecure downloads) or from an FTP server. - The router's default mtd partition scheme has kernel and rootfs separated. We can use dd to split the OpenWrt image file and flash it with mtd: dd if=openwrt.bin of=kernel.bin skip=0 count=8192 bs=256 dd if=openwrt.bin of=rootfs.bin skip=8192 bs=256 - Once the images are ready, you have to flash the device using mtd (make sure to flash the correct partitions or you may be left with a hard bricked router): mtd write kernel.bin kernel mtd write rootfs.bin rootfs - Flashing is done, reboot the device now. Signed-off-by: Foica David --- .../ath79/dts/qca9563_tplink_deco-m4r-v1.dts | 147 ++++++++++++++++++ .../generic/base-files/etc/board.d/02_network | 4 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 6 + target/linux/ath79/image/generic-tp-link.mk | 12 ++ 4 files changed, 169 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts diff --git a/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts new file mode 100644 index 0000000000..26bb906910 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +#include "qca956x.dtsi" + +/ { + compatible = "tplink,deco-m4r-v1", "qca,qca9563"; + model = "TP-Link Deco M4R v1"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + leds { + compatible = "gpio-leds"; + + wlan2g { + label = "red:wlan2g"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_power: power { + label = "green:power"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + wlan5g { + label = "blue:wlan5g"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; + + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + phy-mask = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "sgmii"; + qca,mib-poll-interval = <500>; + + qca,ar8327-initvals = < + 0x04 0x00080080 /* PORT0 PAD MODE CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +&spi { + status = "okay"; + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot: partition@0 { + label = "u-boot"; + reg = <0x000000 0x080000>; + read-only; + }; + + partition@80000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x080000 0xe00000>; + }; + + partition@e80000 { + label = "product-info"; + reg = <0xe80000 0x05000>; + read-only; + }; + + config: partition@e85000 { + label = "config"; + reg = <0xe85000 0x16b000>; + read-only; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +ð0 { + status = "okay"; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_config_8>; + nvmem-cell-names = "mac-address"; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + nvmem-cells = <&macaddr_config_8>; + nvmem-cell-names = "mac-address"; +}; + +&config { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_8: macaddr@8 { + reg = <0x8 0x6>; + }; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index a6427efe2b..78e2624fe7 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -508,6 +508,10 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "1:lan" "2:lan" ;; + tplink,deco-m4r-v1) + ucidef_add_switch "switch0" \ + "0@eth0" "3:lan:1" "5:lan:2" + ;; hiwifi,hc6361|\ xiaomi,mi-router-4q|\ zbtlink,zbt-wd323) diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 00aa34f0a8..668fd76af3 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -269,6 +269,12 @@ case "$FIRMWARE" in ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ /lib/firmware/ath10k/QCA9984/hw1.0/board.bin ;; + tplink,deco-m4r-v1) + caldata_extract "art" 0x5000 0x2f20 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary config 0x8) -1) + ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ + /lib/firmware/ath10k/QCA9888/hw2.0/board.bin + ;; yuncore,a782|\ yuncore,xd4200) caldata_extract "art" 0x5000 0x2f20 diff --git a/target/linux/ath79/image/generic-tp-link.mk b/target/linux/ath79/image/generic-tp-link.mk index ce0f81be6e..8f4bf90b83 100644 --- a/target/linux/ath79/image/generic-tp-link.mk +++ b/target/linux/ath79/image/generic-tp-link.mk @@ -459,6 +459,18 @@ define Device/tplink_eap245-v3 endef TARGET_DEVICES += tplink_eap245-v3 +define Device/tplink_deco-m4r-v1 + $(Device/tplink-safeloader-uimage) + SOC := qca9563 + IMAGE_SIZE := 13824k + DEVICE_MODEL := Deco M4R + DEVICE_VARIANT := v1 + DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct + SUPPORTED_DEVICES += deco-m4r-v1 + TPLINK_BOARD_ID := DECO-M4R-V1 +endef +TARGET_DEVICES += tplink_deco-m4r-v1 + define Device/tplink_re350k-v1 $(Device/tplink-safeloader) SOC := qca9558 From 6e9c814022e41a7cfa4db3b1a41e257fd1515bea Mon Sep 17 00:00:00 2001 From: PtilopsisLeucotis Date: Sat, 16 Apr 2022 13:21:58 +0300 Subject: [PATCH 38/75] ath79: add USB power control for GL-AR300M series Add USB power control in DTS for GL.iNet models: - AR300M; - AR300M-Ext; - AR300M16; - AR300M16-Ext. Signed-off-by: PtilopsisLeucotis --- .../linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts | 6 ++++++ target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi | 11 +++++++++++ 2 files changed, 17 insertions(+) diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts index cf531ed8c4..a34abb1dd2 100644 --- a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts +++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts @@ -7,6 +7,8 @@ model = "GL.iNet GL-AR300M-Lite"; }; +/delete-node/ ®_usb_vbus; + /delete-node/ &nand_flash; &nor_firmware { @@ -27,3 +29,7 @@ &led_wlan { label = "green:wlan"; }; + +&usb0 { + /delete-property/ vbus-supply; +}; diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi index d4e1e6b237..2eaff61f50 100644 --- a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi +++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi @@ -37,6 +37,16 @@ }; }; + reg_usb_vbus: reg_usb_vbus { + compatible = "regulator-fixed"; + + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + leds { compatible = "gpio-leds"; @@ -134,6 +144,7 @@ &usb0 { #address-cells = <1>; #size-cells = <0>; + vbus-supply = <®_usb_vbus>; status = "okay"; }; From 88527294cda0a46d927b3bca6dbaab507fa1cb96 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 20 Mar 2022 17:57:22 +0100 Subject: [PATCH 39/75] ath79: add Netgear WNDAP360 SoC: Atheros AR7161 RAM: DDR 128 MiB (hynix h5dU5162ETR-E3C) Flash: SPI-NOR 8 MiB (mx25l6406em2i-12g) WLAN: 2.4/5 GHz 2.4 GHz: Atheros AR9220 5 GHz: Atheros AR9223 Ethernet: 4x 10/100/1000 Mbps (Atheros AR8021) LEDs/Keys: 2/2 (Internet + System LED, Mesh button + Reset pin) UART: RJ45 9600,8N1 Power: 12 VDC, 1.0 A Installation instruction: 0. Make sure you have latest original firmware (3.7.11.4) 1. Connect to the Serial Port with a Serial Cable RJ45 to DB9/RS232 (9600,8N1) screen /dev/ttyUSB0 9600,cs8,-parenb,-cstopb,-hupcl,-crtscts,clocal 2. Configure your IP-Address to 192.168.1.42 3. When device boots hit spacebar 3. Configure the device for tftpboot setenv ipaddr 192.168.1.1 setenv serverip 192.168.1.42 saveenv 4. Reset the device reset 5. Hit again the spacebar 6. Now load the image via tftp: tftpboot 0x81000000 INITRAMFS.bin 7. Boot the image: bootm 0x81000000 8. Copy the squashfs-image to the device. 9. Do a sysupgrade. https://openwrt.org/toh/netgear/wndap360 The device should be converted from kmod-owl-loader to nvmem-cells in the future. Nvmem cells were not working. Maybe ATH9K_PCI_NO_EEPROM is missing. That is why this commit is still using kmod-owl-loader. In the future the device tree may look like this: &ath9k0 { nvmem-cells = <&macaddr_art_120c>, <&cal_art_1000>; nvmem-cell-names = "mac-address", "calibration"; }; &ath9k1 { nvmem-cells = <&macaddr_art_520c>, <&cal_art_5000>; nvmem-cell-names = "mac-address", "calibration"; }; &art { ... cal_art_1000: cal@1000 { reg = <0x1000 0xeb8>; }; cal_art_5000: cal@5000 { reg = <0x5000 0xeb8>; }; }; Signed-off-by: Nick Hainke --- .../ath79/dts/ar7161_netgear_wndap360.dts | 169 ++++++++++++++++++ .../generic/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/firmware/10-ath9k-eeprom | 6 +- target/linux/ath79/image/generic.mk | 15 ++ 4 files changed, 189 insertions(+), 2 deletions(-) create mode 100644 target/linux/ath79/dts/ar7161_netgear_wndap360.dts diff --git a/target/linux/ath79/dts/ar7161_netgear_wndap360.dts b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts new file mode 100644 index 0000000000..aeb7c56773 --- /dev/null +++ b/target/linux/ath79/dts/ar7161_netgear_wndap360.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "ar7100.dtsi" + +#include +#include + +/ { + compatible = "netgear,wndap360", "qca,ar7161"; + model = "Netgear WNDAP360"; + + aliases { + led-boot = &led_power_orange; + led-failsafe = &led_power_orange; + led-running = &led_power_orange; + led-upgrade = &led_power_orange; + }; + + extosc: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ref"; + clock-frequency = <40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led_power_orange: power_orange { + label = "orange:power"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + }; + + ath9k-leds { + compatible = "gpio-leds"; + + wifi_2g_green { + label = "green:wlan2g"; + gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + wifi_5g_green { + label = "green:wlan5g"; + gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy-mask = <0x0f>; + phy1: ethernet-phy@1 { + reg = <0x1>; + }; +}; + +ð0 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x040000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x010000>; + read-only; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0x790000>; + }; + + partition@7e0000 { + label = "nvram"; + reg = <0x7e0000 0x010000>; + read-only; + }; + + art: partition@7f0000 { + label = "art"; + reg = <0x7f0000 0x010000>; + read-only; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + + ath9k0: wifi@0,11 { + compatible = "pci168c,0029"; + reg = <0x8800 0 0 0 0>; + qca,no-eeprom; + nvmem-cells = <&macaddr_art_120c>; + nvmem-cell-names = "mac-address"; + #gpio-cells = <2>; + gpio-controller; + }; + + ath9k1: wifi@0,12 { + compatible = "pci168c,0029"; + reg = <0x9000 0 0 0 0>; + qca,no-eeprom; + nvmem-cells = <&macaddr_art_520c>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_120c: macaddr@120c { + reg = <0x120c 0x6>; + }; + + macaddr_art_520c: macaddr@520c { + reg = <0x520c 0x6>; + }; +}; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index 78e2624fe7..a4eb2ae06b 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -49,6 +49,7 @@ ath79_setup_interfaces() netgear,ex6400|\ netgear,ex7300|\ netgear,ex7300-v2|\ + netgear,wndap360|\ ocedo,koala|\ ocedo,raccoon|\ onion,omega|\ diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom index 22e162692e..a19d2e95dc 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -152,7 +152,8 @@ case "$FIRMWARE" in "ath9k-eeprom-pci-0000:00:11.0.bin") case $board in buffalo,wzr-600dhp|\ - buffalo,wzr-hp-ag300h) + buffalo,wzr-hp-ag300h|\ + netgear,wndap360) caldata_extract "art" 0x1000 0xeb8 ;; dlink,dir-825-b1) @@ -170,7 +171,8 @@ case "$FIRMWARE" in "ath9k-eeprom-pci-0000:00:12.0.bin") case $board in buffalo,wzr-600dhp|\ - buffalo,wzr-hp-ag300h) + buffalo,wzr-hp-ag300h|\ + netgear,wndap360) caldata_extract "art" 0x5000 0xeb8 ;; dlink,dir-825-b1) diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk index edf6b7ee5e..4f36a08ff4 100644 --- a/target/linux/ath79/image/generic.mk +++ b/target/linux/ath79/image/generic.mk @@ -1654,6 +1654,21 @@ define Device/netgear_ex7300-v2 endef TARGET_DEVICES += netgear_ex7300-v2 +define Device/netgear_wndap360 + $(Device/netgear_generic) + SOC := ar7161 + DEVICE_MODEL := WNDAP360 + DEVICE_PACKAGES := kmod-leds-reset kmod-owl-loader + IMAGE_SIZE := 7744k + BLOCKSIZE := 256k + KERNEL := kernel-bin | append-dtb | gzip | uImage gzip + KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \ + check-size | append-metadata +endef +TARGET_DEVICES += netgear_wndap360 + define Device/netgear_wndr3x00 $(Device/netgear_generic) SOC := ar7161 From b3c2072504867b8ca00dde37f531edf0cfbe3359 Mon Sep 17 00:00:00 2001 From: Josef Schlehofer Date: Fri, 29 Apr 2022 17:52:29 +0200 Subject: [PATCH 40/75] uboot-mvebu: add patch to enable setexpr for clearfog boards Option CMD_SETEXPR is already default in U-boot [1], since this was disabled since initial version for this board, there is send this patch to U-boot mailing list to enable it. It is required to use in OpenWrt bootscript for these boards [2]. [1] https://source.denx.de/u-boot/u-boot/-/blob/e95afa56753cebcd20a5114b6d121f281b789006/cmd/Kconfig#L1504 [2] https://github.com/openwrt/openwrt/blob/852126680e21edc71c0c66561ae5a6d7479dcc67/target/linux/mvebu/image/clearfog.bootscript#L7 Signed-off-by: Josef Schlehofer --- ...fog_defconfig-enable-setexpr-command.patch | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 package/boot/uboot-mvebu/patches/103-arm-mvebu-clearfog_defconfig-enable-setexpr-command.patch diff --git a/package/boot/uboot-mvebu/patches/103-arm-mvebu-clearfog_defconfig-enable-setexpr-command.patch b/package/boot/uboot-mvebu/patches/103-arm-mvebu-clearfog_defconfig-enable-setexpr-command.patch new file mode 100644 index 0000000000..dae43ea942 --- /dev/null +++ b/package/boot/uboot-mvebu/patches/103-arm-mvebu-clearfog_defconfig-enable-setexpr-command.patch @@ -0,0 +1,31 @@ +From 40a67a9403deafdac05564b7350af49a71e12373 Mon Sep 17 00:00:00 2001 +From: Josef Schlehofer +Date: Fri, 29 Apr 2022 17:34:53 +0200 +Subject: [PATCH] arm: mvebu: clearfog_defconfig: enable setexpr command + +This command is useful in U-boot scripts and it is being used by +OpenWrt bootscript for this board [1]. Otherwise shell scripting +commands are enabled by default in cmd/Kconfig. + +[1] https://github.com/openwrt/openwrt/blob/852126680e21edc71c0c66561ae5a6d7479dcc67/target/linux/mvebu/image/clearfog.bootscript#L7 + +[2] https://source.denx.de/u-boot/u-boot/-/blob/e95afa56753cebcd20a5114b6d121f281b789006/cmd/Kconfig#L1504 + +Fixes: 0299c90f396c5b2971a4bac596339f4b03661c27 ("arm: mvebu: Add +SolidRun ClearFog Armada 38x initial support") + +Signed-off-by: Josef Schlehofer +--- + configs/clearfog_defconfig | 1 - + 1 file changed, 1 deletion(-) + +--- a/configs/clearfog_defconfig ++++ b/configs/clearfog_defconfig +@@ -35,7 +35,6 @@ CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y + CONFIG_CMD_SPI=y + CONFIG_CMD_USB=y +-# CONFIG_CMD_SETEXPR is not set + CONFIG_CMD_TFTPPUT=y + CONFIG_CMD_CACHE=y + CONFIG_CMD_TIME=y From 69cef74c671cb7fa738a5a4c9a283c29f45326c7 Mon Sep 17 00:00:00 2001 From: Josef Schlehofer Date: Thu, 28 Apr 2022 15:50:20 +0200 Subject: [PATCH 41/75] uboot-mvebu: remove enabled CONFIG_CMD_SETEXPR We don't need to make sure that we want to have enabled CONFIG_CMD_SETEXPR by default, since this is already done in U-boot [1]. This was actually needed only for clearfog board [2], which was added in commit: da0005a6d08ae33d958a6d8a6c0c12dc07b5b2b8 ("uboot-mvebu: add patch to enable setexpr for clearfog boards) and send to U-boot to fix it properly. After a while, there was added support for Turris Omnia, which uses setexpr as well [3], but for this board, there are no fixes needed in U-boot and that's why we can remove this option here. It is helpful with shell scripting. If some downstream distributions are using it, they should correct it in defconfig for related boards. [1] https://source.denx.de/u-boot/u-boot/-/blob/e95afa56753cebcd20a5114b6d121f281b789006/cmd/Kconfig#L1504 [2] https://github.com/openwrt/openwrt/blob/852126680e21edc71c0c66561ae5a6d7479dcc67/target/linux/mvebu/image/clearfog.bootscript#L7 [3] https://github.com/openwrt/openwrt/blob/852126680e21edc71c0c66561ae5a6d7479dcc67/target/linux/mvebu/image/turris-omnia.bootscript#L2 Signed-off-by: Josef Schlehofer --- package/boot/uboot-mvebu/Makefile | 7 ------- 1 file changed, 7 deletions(-) diff --git a/package/boot/uboot-mvebu/Makefile b/package/boot/uboot-mvebu/Makefile index 566f45ffed..a154d15dc1 100644 --- a/package/boot/uboot-mvebu/Makefile +++ b/package/boot/uboot-mvebu/Makefile @@ -62,13 +62,6 @@ UBOOT_TARGETS:= \ espressobin \ uDPU -define Build/Configure - # enable additional options beyond _defconfig - echo CONFIG_CMD_SETEXPR=y >> $(PKG_BUILD_DIR)/configs/$(UBOOT_CONFIG)_defconfig - - $(call Build/Configure/U-Boot) -endef - define Package/u-boot/install $(if $(findstring cortexa53,$(BUILD_SUBTARGET)),,$(Package/u-boot/install/default)) endef From 4f51f1fc9b3597d24de442cfff253fddce478d17 Mon Sep 17 00:00:00 2001 From: Josef Schlehofer Date: Thu, 28 Apr 2022 13:34:35 +0200 Subject: [PATCH 42/75] uboot-mvebu: update to version v2022.04 Release announcement: https://lore.kernel.org/u-boot/20220404143253.GQ14476@bill-the-cat/ Release notes between tags: https://source.denx.de/u-boot/u-boot/-/compare/v2022.01...v2022.04?from_project_id=531 All patches were removed, since they are included in this release. Run tested: Turris Omnia, mvebu/cortex-a9, OpenWrt daily snapshots Signed-off-by: Josef Schlehofer --- package/boot/uboot-mvebu/Makefile | 4 +- ...0-ddr-marvell-a38x-fix-split-out-mix.patch | 116 ------------------ ...8x-fix-synchronous-asynchronous-mode.patch | 98 --------------- ...-Do-not-allocate-8kB-buffer-on-stack.patch | 92 -------------- ...enon_sdhci-remove-wait_dat0-SDHCI-OP.patch | 64 ---------- ...-fix-BYTE_HOMOGENEOUS_SPLIT_OUT-deci.patch | 65 ---------- ...d-option-to-reset-the-board-on-DDR-t.patch | 49 -------- ..._omnia-Reset-the-board-immediately-o.patch | 38 ------ 8 files changed, 2 insertions(+), 524 deletions(-) delete mode 100644 package/boot/uboot-mvebu/patches/010-ddr-marvell-a38x-fix-split-out-mix.patch delete mode 100644 package/boot/uboot-mvebu/patches/011-ddr-marvell-a38x-fix-synchronous-asynchronous-mode.patch delete mode 100644 package/boot/uboot-mvebu/patches/012-nvme-Do-not-allocate-8kB-buffer-on-stack.patch delete mode 100644 package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch delete mode 100644 package/boot/uboot-mvebu/patches/100-ddr-marvell-a38x-fix-BYTE_HOMOGENEOUS_SPLIT_OUT-deci.patch delete mode 100644 package/boot/uboot-mvebu/patches/101-arm-mvebu-spl-Add-option-to-reset-the-board-on-DDR-t.patch delete mode 100644 package/boot/uboot-mvebu/patches/102-arm-mvebu-turris_omnia-Reset-the-board-immediately-o.patch diff --git a/package/boot/uboot-mvebu/Makefile b/package/boot/uboot-mvebu/Makefile index a154d15dc1..25abcbeb4f 100644 --- a/package/boot/uboot-mvebu/Makefile +++ b/package/boot/uboot-mvebu/Makefile @@ -8,10 +8,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2022.01 +PKG_VERSION:=2022.04 PKG_RELEASE:=$(AUTORELEASE) -PKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413 +PKG_HASH:=68e065413926778e276ec3abd28bb32fa82abaa4a6898d570c1f48fbdb08bcd0 include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/uboot-mvebu/patches/010-ddr-marvell-a38x-fix-split-out-mix.patch b/package/boot/uboot-mvebu/patches/010-ddr-marvell-a38x-fix-split-out-mix.patch deleted file mode 100644 index 17ff86223c..0000000000 --- a/package/boot/uboot-mvebu/patches/010-ddr-marvell-a38x-fix-split-out-mix.patch +++ /dev/null @@ -1,116 +0,0 @@ -From 3fc92a215b69ad448c151489228eb340df9a8703 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Wed, 12 Jan 2022 17:06:59 +0100 -Subject: [PATCH] ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This is a cleaned up and fixed version of a patch - mv_ddr: a380: fix SPLIT_OUT_MIX state decision - - in each pattern cycle the bus state can be changed - in order to avoide it, need to back to the same bus state on each - pattern cycle -by - Moti Boskula - -The original patch is not in Marvell's mv-ddr-marvell repository. It was -gives to us by Marvell to fix an issues with DDR training on some -boards, but it cannot be applied as is to mv-ddr-marvell, because it is -a very dirty draft patch that would certainly break other things, mainly -DDR4 training code in mv-ddr-marvell, since it changes common functions. - -I have cleaned up the patch and removed stuff that seemed unnecessary -(when removed, it still fixed things). Note that I don't understand -completely what the code does exactly, since I haven't studied the DDR -training code extensively (and I suspect that no one besides some few -people in Marvell understand the code completely). - -Anyway after the cleanup the patch still fixes isssues with DDR training -on the failing boards. - -There was also a problem with the original patch on some of the Allied -Telesis' x530 boards, reported by Chris Packham. I have asked Chris to -send me some logs, and managed to fix it: -- if you look at the change, you'll notice that it introduces - subtraction of cur_start_win[] and cur_end_win[] members, depending on - a bit set in the current_byte_status variable -- the original patch subtracted cur_start_win[] if either - BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but - subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX) - was set -- from Chris Packham logs I discovered that the x530 board where the - original patch introduced DDR training failure, only the - BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the - patch is needed only the BYTE_SPLIT_OUT_MIX is set in the - current_byte_status variable -- this led me to the hypothesis that both cur_start_win[] and - cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is - set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all -- this hypothesis also gains credibility when considering the commit - title ("fix SPLIT_OUT_MIX state decision") - -Hopefully this will fix things without breaking anything else. - -Signed-off-by: Marek Behún -Reviewed-by: Stefan Roese -Tested-by: Chris Packham ---- - .../a38x/ddr3_training_centralization.c | 26 +++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c -+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c -@@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 d - enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; - u32 if_id, pattern_id, bit_id; - u8 bus_id; -+ u8 current_byte_status; - u8 cur_start_win[BUS_WIDTH_IN_BITS]; - u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; - u8 cur_end_win[BUS_WIDTH_IN_BITS]; -@@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 d - result[search_dir_id][7])); - } - -+ current_byte_status = -+ mv_ddr_tip_sub_phy_byte_status_get(if_id, -+ bus_id); -+ - for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; - bit_id++) { - /* check if this code is valid for 2 edge, probably not :( */ -@@ -174,11 +179,32 @@ static int ddr3_tip_centralization(u32 d - [HWS_LOW2HIGH] - [bit_id], - EDGE_1); -+ if (current_byte_status & -+ BYTE_SPLIT_OUT_MIX) { -+ if (cur_start_win[bit_id] >= 64) -+ cur_start_win[bit_id] -= 64; -+ else -+ cur_start_win[bit_id] = 0; -+ DEBUG_CENTRALIZATION_ENGINE -+ (DEBUG_LEVEL_INFO, -+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from start\n", -+ pattern_id, if_id, bus_id, bit_id)); -+ } - cur_end_win[bit_id] = - GET_TAP_RESULT(result - [HWS_HIGH2LOW] - [bit_id], - EDGE_1); -+ if (cur_end_win[bit_id] >= 64 && -+ (current_byte_status & -+ BYTE_SPLIT_OUT_MIX)) { -+ cur_end_win[bit_id] -= 64; -+ DEBUG_CENTRALIZATION_ENGINE -+ (DEBUG_LEVEL_INFO, -+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from end\n", -+ pattern_id, if_id, bus_id, bit_id)); -+ } -+ - /* window length */ - current_window[bit_id] = - cur_end_win[bit_id] - diff --git a/package/boot/uboot-mvebu/patches/011-ddr-marvell-a38x-fix-synchronous-asynchronous-mode.patch b/package/boot/uboot-mvebu/patches/011-ddr-marvell-a38x-fix-synchronous-asynchronous-mode.patch deleted file mode 100644 index 9da1459a7d..0000000000 --- a/package/boot/uboot-mvebu/patches/011-ddr-marvell-a38x-fix-synchronous-asynchronous-mode.patch +++ /dev/null @@ -1,98 +0,0 @@ -From eadc4f512fb43bba2fa4e842c982da919da664be Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Tue, 4 Jan 2022 15:57:49 +0100 -Subject: [PATCH] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode - determination -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async -mode"), Asynchornous Mode was only used when the CPU Subsystem Clock -Options[4:0] field in the SAR1 register was set to value 0x13: CPU at -2 GHz and DDR at 933 MHz. - -Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async -mode") added support for Asynchornous Modes with frequencies other than -933 MHz (but at least 467 MHz), but the code it added to check for -whether Asynchornous Mode should be used is wrong: it checks whether the -frequency setting in board DDR topology map is set to value other than -MV_DDR_FREQ_SAR. - -Thus boards which define a specific value, greater than 400 MHz, for DDR -frequency in their board topology (e.g. Turris Omnia defines -MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that -commit. - -The A38x Functional Specification, section 10.12 DRAM Clocking, says: - In Synchornous mode, the DRAM and CPU clocks are edge aligned and run - in 1:2 or 1:3 CPU to DRAM frequency ratios. - -Change the check for whether Asynchornous Mode should be used according -to this explanation in Functional Specification. - -Signed-off-by: Marek Behún -Tested-by: Chris Packham -Reviewed-by: Stefan Roese ---- - drivers/ddr/marvell/a38x/mv_ddr_plat.c | 19 ++++++++----------- - 1 file changed, 8 insertions(+), 11 deletions(-) - ---- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c -+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c -@@ -167,8 +167,6 @@ static u16 a38x_vco_freq_per_sar_ref_clk - }; - - --static u32 async_mode_at_tf; -- - static u32 dq_bit_map_2_phy_pin[] = { - 1, 0, 2, 6, 9, 8, 3, 7, /* 0 */ - 8, 9, 1, 7, 2, 6, 3, 0, /* 1 */ -@@ -734,7 +732,8 @@ static int ddr3_tip_a38x_set_divider(u8 - u32 divider = 0; - u32 sar_val, ref_clk_satr; - u32 async_val; -- u32 freq = mv_ddr_freq_get(frequency); -+ u32 cpu_freq; -+ u32 ddr_freq = mv_ddr_freq_get(frequency); - - if (if_id != 0) { - DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, -@@ -751,11 +750,14 @@ static int ddr3_tip_a38x_set_divider(u8 - ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); - if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == - DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ) -- divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq; -+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val]; - else -- divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq; -+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val]; -+ -+ divider = cpu_freq / ddr_freq; - -- if ((async_mode_at_tf == 1) && (freq > 400)) { -+ if (((cpu_freq % ddr_freq != 0) || (divider != 2 && divider != 3)) && -+ (ddr_freq > 400)) { - /* Set async mode */ - dunit_write(0x20220, 0x1000, 0x1000); - dunit_write(0xe42f4, 0x200, 0x200); -@@ -869,8 +871,6 @@ int ddr3_tip_ext_write(u32 dev_num, u32 - - int mv_ddr_early_init(void) - { -- struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); -- - /* FIXME: change this configuration per ddr type - * configure a380 and a390 to work with receiver odt timing - * the odt_config is defined: -@@ -882,9 +882,6 @@ int mv_ddr_early_init(void) - - mv_ddr_sw_db_init(0, 0); - -- if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR) -- async_mode_at_tf = 1; -- - return MV_OK; - } - diff --git a/package/boot/uboot-mvebu/patches/012-nvme-Do-not-allocate-8kB-buffer-on-stack.patch b/package/boot/uboot-mvebu/patches/012-nvme-Do-not-allocate-8kB-buffer-on-stack.patch deleted file mode 100644 index 20046c67b6..0000000000 --- a/package/boot/uboot-mvebu/patches/012-nvme-Do-not-allocate-8kB-buffer-on-stack.patch +++ /dev/null @@ -1,92 +0,0 @@ -From d17ab6e1289b1d705c75de8a2351218962fb7352 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 9 Dec 2021 11:06:39 +0100 -Subject: [PATCH] nvme: Do not allocate 8kB buffer on stack -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Calling 'nvme scan' followed by 'nvme detail' crashes U-Boot on Turris -Omnia with the following error: - - undefined instruction - pc : [<0a000000>] lr : [<7ff80bfc>] - reloc pc : [<8a8c0000>] lr : [<00840bfc>] - sp : 7fb2b908 ip : 0000002a fp : 02000000 - r10: 04000000 r9 : 7fb2fed0 r8 : e1000000 - r7 : 0c000000 r6 : 03000000 r5 : 06000000 r4 : 01000000 - r3 : 7fb30928 r2 : 7fb30928 r1 : 00000000 r0 : 00000000 - Flags: nZCv IRQs off FIQs off Mode SVC_32 - Code: 0f0fb4f0 0f0fb4f0 0f0fb4f0 0f0fb4f0 (f0f04b0f) - Resetting CPU ... - -This happens when nvme_print_info() tries to return to the caller. It -looks like this error is caused by trying to allocate 8 KiB of memory -on the stack by the two uses of ALLOC_CACHE_ALIGN_BUFFER(). - -Use malloc_cache_aligned() to allocate this memory dynamically instead. - -This fixes 'nvme detail' on Turris Omnia. - -Note that similar change was applied to file drivers/nvme/nvme.c in past by -commit 2f83481dff9c ("nvme: use page-aligned buffer for identify command"). - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/nvme/nvme_show.c | 35 ++++++++++++++++++++++++++--------- - 1 file changed, 26 insertions(+), 9 deletions(-) - ---- a/drivers/nvme/nvme_show.c -+++ b/drivers/nvme/nvme_show.c -@@ -106,24 +106,41 @@ int nvme_print_info(struct udevice *udev - { - struct nvme_ns *ns = dev_get_priv(udev); - struct nvme_dev *dev = ns->dev; -- ALLOC_CACHE_ALIGN_BUFFER(char, buf_ns, sizeof(struct nvme_id_ns)); -- struct nvme_id_ns *id = (struct nvme_id_ns *)buf_ns; -- ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl)); -- struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl; -+ struct nvme_id_ctrl *ctrl; -+ struct nvme_id_ns *id; -+ int ret = 0; - -- if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl)) -- return -EIO; -+ ctrl = memalign(dev->page_size, sizeof(struct nvme_id_ctrl)); -+ if (!ctrl) -+ return -ENOMEM; -+ -+ if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl)) { -+ ret = -EIO; -+ goto free_ctrl; -+ } - - print_optional_admin_cmd(le16_to_cpu(ctrl->oacs), ns->devnum); - print_optional_nvm_cmd(le16_to_cpu(ctrl->oncs), ns->devnum); - print_format_nvme_attributes(ctrl->fna, ns->devnum); - -- if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id)) -- return -EIO; -+ id = memalign(dev->page_size, sizeof(struct nvme_id_ns)); -+ if (!id) { -+ ret = -ENOMEM; -+ goto free_ctrl; -+ } -+ -+ if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id)) { -+ ret = -EIO; -+ goto free_id; -+ } - - print_formats(id, ns); - print_data_protect_cap(id->dpc, ns->devnum); - print_metadata_cap(id->mc, ns->devnum); - -- return 0; -+free_id: -+ free(id); -+free_ctrl: -+ free(ctrl); -+ return ret; - } diff --git a/package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch b/package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch deleted file mode 100644 index 3277638784..0000000000 --- a/package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0f3466f52fbacce67e147b9234e6323edff26a6d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 11 Mar 2022 19:14:07 +0100 -Subject: [PATCH] mmc: xenon_sdhci: remove wait_dat0 SDHCI OP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Generic SDHCI driver received support for checking the busy status by -polling the DAT[0] level instead of waiting for the worst MMC switch time. - -Unfortunately, it appears that this does not work for Xenon controllers -despite being a part of the standard SDHCI registers and the Armada 3720 -datasheet itself telling that BIT(20) is useful for detecting the DAT[0] -busy signal. - -I have tried increasing the timeout value, but I have newer managed to -catch DAT_LEVEL bits change from 0 at all. - -This issue appears to hit most if not all SoC-s supported by Xenon driver, -at least A3720, A8040 and CN9130 have non working eMMC currently. - -So, until a better solution is found drop the wait_dat0 OP for Xenon. -I was able to only test it on A3720, but it should work for others as well. - -Fixes: 40e6f52454fc ("drivers: mmc: Add wait_dat0 support for sdhci driver") -Signed-off-by: Robert Marko -Reviewed-by: Marek Behún -Reviewed-by: Jaehoon Chung -Reviewed-by: Stefan Roese ---- - drivers/mmc/xenon_sdhci.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/mmc/xenon_sdhci.c -+++ b/drivers/mmc/xenon_sdhci.c -@@ -439,6 +439,8 @@ static const struct sdhci_ops xenon_sdhc - .set_ios_post = xenon_sdhci_set_ios_post - }; - -+static struct dm_mmc_ops xenon_mmc_ops; -+ - static int xenon_sdhci_probe(struct udevice *dev) - { - struct xenon_sdhci_plat *plat = dev_get_plat(dev); -@@ -452,6 +454,9 @@ static int xenon_sdhci_probe(struct udev - host->mmc->dev = dev; - upriv->mmc = host->mmc; - -+ xenon_mmc_ops = sdhci_ops; -+ xenon_mmc_ops.wait_dat0 = NULL; -+ - /* Set quirks */ - host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR; - -@@ -568,7 +573,7 @@ U_BOOT_DRIVER(xenon_sdhci_drv) = { - .id = UCLASS_MMC, - .of_match = xenon_sdhci_ids, - .of_to_plat = xenon_sdhci_of_to_plat, -- .ops = &sdhci_ops, -+ .ops = &xenon_mmc_ops, - .bind = xenon_sdhci_bind, - .probe = xenon_sdhci_probe, - .remove = xenon_sdhci_remove, diff --git a/package/boot/uboot-mvebu/patches/100-ddr-marvell-a38x-fix-BYTE_HOMOGENEOUS_SPLIT_OUT-deci.patch b/package/boot/uboot-mvebu/patches/100-ddr-marvell-a38x-fix-BYTE_HOMOGENEOUS_SPLIT_OUT-deci.patch deleted file mode 100644 index 4b8706e56f..0000000000 --- a/package/boot/uboot-mvebu/patches/100-ddr-marvell-a38x-fix-BYTE_HOMOGENEOUS_SPLIT_OUT-deci.patch +++ /dev/null @@ -1,65 +0,0 @@ -From c11428c7def52671f57089701efe878f7071b696 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Thu, 17 Feb 2022 01:08:37 +0100 -Subject: [PATCH 1/3] ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT - decision -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -In commit 3fc92a215b69 ("ddr: marvell: a38x: fix SPLIT_OUT_MIX state -decision") I ported a cleaned up and changed version of patch - mv_ddr: a380: fix SPLIT_OUT_MIX state decision - -In the port we removed checking for BYTE_HOMOGENEOUS_SPLIT_OUT bit, -because: -- the fix seemed to work without it -- the bit was checked for only at one place out of two, while the second - bit, BYTE_SPLIT_OUT_MIX, was checked for in both cases -- without the removal it didn't work on Allied Telesis' x530 board - -We recently had a chance to test on more boards, and it seems that the -change needs to be opposite: instead of removing the check for -BYTE_HOMOGENEOUS_SPLIT_OUT from the first if() statement, the check -needs to be added also to the second one - it needs to be at both -places. - -With this change all the Turris Omnia boards I have had available to -test seem to work, I didn't encounter not even one failed DDR training. - -As last time, I am noting that I do not understand what this code is -actually doing, I haven't studied the DDR training algorithm and -I suspect that no one will be able to explain it to U-Boot contributors, -so we are left with this blind poking in the code with testing whether -it works on several boards and hoping it doesn't break anything for -anyone :-(. - -Signed-off-by: Marek Behún -Tested-by: Chris Packham -Reviewed-by: Stefan Roese ---- - drivers/ddr/marvell/a38x/ddr3_training_centralization.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c -+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c -@@ -180,7 +180,8 @@ static int ddr3_tip_centralization(u32 d - [bit_id], - EDGE_1); - if (current_byte_status & -- BYTE_SPLIT_OUT_MIX) { -+ (BYTE_SPLIT_OUT_MIX | -+ BYTE_HOMOGENEOUS_SPLIT_OUT)) { - if (cur_start_win[bit_id] >= 64) - cur_start_win[bit_id] -= 64; - else -@@ -197,7 +198,8 @@ static int ddr3_tip_centralization(u32 d - EDGE_1); - if (cur_end_win[bit_id] >= 64 && - (current_byte_status & -- BYTE_SPLIT_OUT_MIX)) { -+ (BYTE_SPLIT_OUT_MIX | -+ BYTE_HOMOGENEOUS_SPLIT_OUT))) { - cur_end_win[bit_id] -= 64; - DEBUG_CENTRALIZATION_ENGINE - (DEBUG_LEVEL_INFO, diff --git a/package/boot/uboot-mvebu/patches/101-arm-mvebu-spl-Add-option-to-reset-the-board-on-DDR-t.patch b/package/boot/uboot-mvebu/patches/101-arm-mvebu-spl-Add-option-to-reset-the-board-on-DDR-t.patch deleted file mode 100644 index d7ba3ec68f..0000000000 --- a/package/boot/uboot-mvebu/patches/101-arm-mvebu-spl-Add-option-to-reset-the-board-on-DDR-t.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 74767a3875c99b1a3d2818456a5fdc02ec1e4f93 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Thu, 17 Feb 2022 13:54:42 +0100 -Subject: [PATCH 2/3] arm: mvebu: spl: Add option to reset the board on DDR - training failure -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Some boards may occacionally fail DDR training. Currently we hang() in -this case. Add an option that makes the board do an immediate reset in -such a case, so that a new training is tried as soon as possible, -instead of hanging and possibly waiting for watchdog to reset the board. - -(If the DDR training fails while booting the image via UART, we will - still hang - it doesn't make sense to reset in such a case, because - after reset the board will try booting from another medium, and the - UART booting utility does not expect that.) - -Signed-off-by: Marek Behún -Reviewed-by: Pali Rohár -Reviewed-by: Stefan Roese ---- - arch/arm/mach-mvebu/spl.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-mvebu/spl.c -+++ b/arch/arm/mach-mvebu/spl.c -@@ -4,6 +4,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -290,7 +291,11 @@ void board_init_f(ulong dummy) - ret = ddr3_init(); - if (ret) { - debug("ddr3_init() failed: %d\n", ret); -- hang(); -+ if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) && -+ get_boot_device() != BOOT_DEVICE_UART) -+ reset_cpu(); -+ else -+ hang(); - } - #endif - diff --git a/package/boot/uboot-mvebu/patches/102-arm-mvebu-turris_omnia-Reset-the-board-immediately-o.patch b/package/boot/uboot-mvebu/patches/102-arm-mvebu-turris_omnia-Reset-the-board-immediately-o.patch deleted file mode 100644 index 30215aa4e2..0000000000 --- a/package/boot/uboot-mvebu/patches/102-arm-mvebu-turris_omnia-Reset-the-board-immediately-o.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 930c46e86123aeea1c73ae55d70ff3dcfc077992 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Thu, 17 Feb 2022 13:54:43 +0100 -Subject: [PATCH 3/3] arm: mvebu: turris_omnia: Reset the board immediately on - DDR training failure -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The state of the current DDR training code for Armada 38x is such that -we cannot be sure it will always train successfully - although after the -last change we were yet unable to find a board that failed DDR training, -from experience in the last 2 years we know that it is possible. - -The experience also tells us that in many cases the board fails training -only sometimes, and after a reset the training is successful. - -Enable the new option that makes the board reset itself on DDR training -failure immediately. Until now we called hang() in such a case, which -meant that the board was reset by the MCU after 120 seconds. - -Signed-off-by: Marek Behún -Reviewed-by: Stefan Roese -Reviewed-by: Pali Rohár ---- - configs/turris_omnia_defconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/configs/turris_omnia_defconfig -+++ b/configs/turris_omnia_defconfig -@@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_SYS_MEMTEST_START=0x00800000 - CONFIG_SYS_MEMTEST_END=0x00ffffff - CONFIG_TARGET_TURRIS_OMNIA=y -+CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y - CONFIG_ENV_SIZE=0x10000 - CONFIG_ENV_OFFSET=0xF0000 - CONFIG_ENV_SECT_SIZE=0x10000 From 1aac1b36d3cf44c8bfa8d4a6d8df6e815fc06529 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kerma=20G=C3=A9rald?= Date: Fri, 29 Apr 2022 00:08:09 +0200 Subject: [PATCH 43/75] f2fs-tools: fix resize.f2fs (#9800) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit resolve issue - https://github.com/openwrt/openwrt/issues/9800 add the upstream patch: - f2fs-tools.git/patch/?id=f056fbeff08d30a6d9acdb9e06704461ceee3500 Signed-off-by: Kerma Gérald --- package/utils/f2fs-tools/Makefile | 2 +- ...esize_f2fs-fix_wrong_ovp_calculation.patch | 46 +++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 package/utils/f2fs-tools/patches/200-resize_f2fs-fix_wrong_ovp_calculation.patch diff --git a/package/utils/f2fs-tools/Makefile b/package/utils/f2fs-tools/Makefile index 44ab63c403..3c53f27d79 100644 --- a/package/utils/f2fs-tools/Makefile +++ b/package/utils/f2fs-tools/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=f2fs-tools PKG_VERSION:=1.14.0 -PKG_RELEASE:=2 +PKG_RELEASE:=3 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git/snapshot/ diff --git a/package/utils/f2fs-tools/patches/200-resize_f2fs-fix_wrong_ovp_calculation.patch b/package/utils/f2fs-tools/patches/200-resize_f2fs-fix_wrong_ovp_calculation.patch new file mode 100644 index 0000000000..0b433f76c4 --- /dev/null +++ b/package/utils/f2fs-tools/patches/200-resize_f2fs-fix_wrong_ovp_calculation.patch @@ -0,0 +1,46 @@ +From f056fbeff08d30a6d9acdb9e06704461ceee3500 Mon Sep 17 00:00:00 2001 +From: Jaegeuk Kim +Date: Thu, 1 Apr 2021 20:13:55 -0700 +Subject: resize.f2fs: fix wrong ovp calculation + +beroal reported a mount failure due to broken valid_user_blocks. +[ 6890.647749] F2FS-fs (loop0): Wrong valid_user_blocks: 16040048, +user_block_count: 10016768 + +From fsck, + +segment_count_main [0x 9a95 : 39573] +-> 39573 * 2MB = 78GB as user space + +overprov_segment_count [0x 4e29 : 20009] +-> 20009 * 2MB = 40GB as overprovisioned space which user can't see. + +But, +[FSCK] valid_block_count matching with CP [Ok..] [0xf4c070] +-> 0xf4c070 = 16040048 + +valid_block_count [0x f4c070 : 16040048] +-> So, this is correct. + +It turns out resize.f2fs gave very large and wrong overprovisioning space +result in shortage of user blocks. The root cause was f2fs_get_usable_segments() +didn't consider resize case which needs segment_count_main from new superblock. + +Fixes: f8410857b7a8 ("f2fs-tools: zns zone-capacity support") +Signed-off-by: Jaegeuk Kim +--- + lib/libf2fs_zoned.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/lib/libf2fs_zoned.c ++++ b/lib/libf2fs_zoned.c +@@ -495,6 +495,9 @@ uint32_t f2fs_get_usable_segments(struct + int i, j; + uint32_t usable_segs = 0, zone_segs; + ++ if (c.func == RESIZE) ++ return get_sb(segment_count_main); ++ + for (i = 0; i < c.ndevs; i++) { + if (c.devices[i].zoned_model != F2FS_ZONED_HM) { + usable_segs += c.devices[i].total_segments; From ab4eafbed974c6ead13b11a50b3032670c26540a Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 10 Apr 2022 09:00:59 +0200 Subject: [PATCH 44/75] mdadm: update to 4.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refreshed patches: - 100-cross_compile.patch Manually refreshed patches: - 200-reduce_size.patch Removed patches: - 101-mdadm.h-Undefine-dprintf-before-redefining.patch - 102-Add-missing-include-file-sys-sysmacros.h.patch Changes: e30ca260 Release mdadm-4.2 8c80d305 Monitor: print message before quit for no array to monitor ced5fa8b mdadm: block creation with long names b71de056 Correct checking if file descriptors are valid b2e4f084 Incremental: Close unclosed mdfd in IncrementalScan() 195d1d76 imsm: assert if there is migration but prev_map doesn't exist 75f3ba25 imsm: free allocated memory in imsm_fix_size_mismatch bce0eab3 Release mdadm-4.2-rc3 4389ce73 imsm: introduce helpers to manage file descriptors 8e1a258e mdadm/Detail: Can't show container name correctly when unpluging disks a35aa68f mdadm/lib: Define a new helper function is_dev_alived 1c66260d Fix 2 dc stream buffer d64a37b9 Assemble: apply sysfs rules 5f6dedfb Fix potential overlap dest buffer a0422106 disallow create or grow clustered bitmap with writemostly set cf16a350 Fix buffer size warning for strcpy 60815698 Refactor parse_num and use it to parse optarg. f7889e51 Fix error message when creating raid 4, 5 and 10 54604768 mdadm: fix coredump of mdadm --monitor -r feeb2785 Utils: Change sprintf to snprintf b8bbf264 Release mdadm-4.2-rc2 e6878148 Assemble: skip devices that don't match uuid instead of aborting the assembly. 0663137c Add monitor delay parameter to mdadm.conf 2b2c5668 tests: Avoid passing chunk size when creating RAID 1 7d374a18 Fix memory leak after "mdadm --detail" 92a647c8 Assemble: start dirty and degraded array. 1c275381 imsm: fix num_data_stripes after raid0 takeover 5b30a34a Add error handling for chunk size in RAID1 3a85bf0e imsm: Fix possible memory leaks and refactor freeing struct dl ccd61ebf mdadm: Fix building errors 601ffa78 Don't associate spares with other arrays during RAID Examine 8d69bf14 Remove Spare drives line from details for external metadata 7d8935cb imsm: correct offset for 4k disks in --examine output dca80fcd Use dev_open in validate geometry container f421731c mdadm/super1: It needs to specify int32 for bitmap_offset 1f5d54a0 Manage: Call validate_geometry when adding drive to external container 8662f92d imsm: Limit support to the lowest namespace fcebeb77 imsm: add devpath_to_char method 7c798f87 imsm: add generic method to resolve "device" links 0530e2e0 Prevent user from using --stop with ambiguous args 83b3de77 Fix some building errors ff904202 imsm: change wrong size verification c11b1c3c Release mdadm-4.2-rc1 aec01630 super-intel.c: Handle errors from calls to get_dev_sector_size() 78c93b00 mdadm: fix growing containers af3396da Monitor: make libudev dependency optional f94df5cf imsm: support for third Sata controller d835518b imsm: nvme multipath support 4036e7ee imsm: extend curr_migr_unit to u64 bdbe7f81 Grow: Block reshape when external metadata and write-intent bitmap 848d71c9 Create: Block automatic enabling bitmap for external metadata 19ad203e imsm: Update-subarray for write-intent bitmap dc95f821 Add "bitmap" to allowed command-line values 69d40de4 imsm: Adding a spare to an existing array with bitmap fbc42556 imsm: Write-intent bitmap support b554ab5c Enable bitmap support for external metadata b090e910 Modify mdstat parsing for volumes with the bitmap db537788 It should be FAILED when raid has not enough active disks c7b8547c imsm: add verbose flag to compare_super 49b69533 mdmonitor: check if udev has finished events processing 0d583954 Document PPL in man md 2f86fda3 imsm: use saved fds during migration f7a6246b super1.c: avoid useless sync when bitmap switches from clustered to none e6561c4d super1: fix Floating point exception 8818d4e7 Grow: be careful of corrupt dev_roles list 4ae96c80 mdadm: fix reshape from RAID5 to RAID6 with backup file 1fe2e100 mdadm/bitmap: locate bitmap calcuate bitmap position wrongly 75562b57 Dump: get stat from a wrong metadata file when restoring metadata 69068584 Incremental: Remove redundant spare movement logic a64f1263 udev: start grow service automatically b4a5ad49 Make target to install binaries only 9c030dad mdadm/Detail: show correct state for clustered array ff6bb131 mdadm: Unify forks behaviour a8f3cfd5 imsm: limit support to first NVMe namespace ca4b156b Monitor: don't use default modes when creating a file b65c1f4a imsm: remove redundant calls to imsm_get_map 895ffd99 imsm: update num_data_stripes according to dev_size ce559078 Create.c: close mdfd and generate uevent c3129b39 Detail: fix segfault during IMSM raid creation 97b51a2c Super1: allow RAID0 layout setting to be removed. 7f3b2d1d Check if other Monitor instance running before fork. cab9c67d mdmonitor: set small delay once 007087d0 Monitor: stop notifing about containers. e2308733 Monitor: refresh mdstat fd after select 2ce09172 Don't create bitmap for raid5 with journal disk 64bf4dff Detail: show correct raid level when the array is inactive 5f418455 manual: update --examine-badblocks 5e592e1e mdadm/md.4: update path to in-kernel-tree documentation 138a9e9b Specify nodes number when updating cluster nodes 77b72fa8 mdadm/Grow: prevent md's fd from being occupied during delayed time bcf40dbb Update link to Intel page for IMSM 8e41153c Use more secure HTTPS URLs 2cf04330 Detect too-small device: error rather than underflow/crash 7758ada9 Block overwriting existing links while manual assembly d92cee7b restripe: fix ignoring return value of ‘read’ and lseek 7d90f760 Include count for \0 character when using strncpy to implement strdup. f4c8a605 uuid.c: split uuid stuffs from util.c 03ab9763 Makefile: add EXTRAVERSION support 3b7aae92 mdcheck: Log when done 7b99edab Assemble.c: respect force flag. ec7d7cee clean up meaning of small typo 5cfb79de Assemble: print error message if mdadm fails assembling with --uuid option 12724c01 Manage, imsm: Write metadata before add 1c294b5d Detail: adding sync status for cluster device 185ec439 Monitor: improve check_one_sharer() for checking duplicated process e1b92ee0 udev: Ignore change event for imsm ba1b3bc8 imsm: show Subarray and Volume ID in --examine output e48aed3c imsm: support the Array Creation Time field in metadata 9e449405 Detail: show correct bitmap info for cluster raid device 06a6101c imsm: Correct minimal device size. 45c43276 imsm: Remove --dump/--restore implementation 3364781b imsm: pass subarray id to kill_subarray function fd38b8ea Remove the legacy whitespace 2551061c mdadm.8: add note information for raid0 growing operation 1e93d0d1 imsm: fill working_disks according to metadata. 42e641ab Add support for Tebibytes 4431efeb imsm: Update grow manual. e1512e7b mdcheck service can't start succesfully because of syntax error 1a874930 Change warning message aced6fc9 Respect $(CROSS_COMPILE) when $(CC) is the default 027c099f Assemble: add support for RAID0 layouts. 329dfc28 Create: add support for RAID0 layouts. 6da53c0e imsm: Change the way of printing nvme drives in detail-platform. b771faef imsm: return correct uuid for volume in detail 4b31846f Remove unused code 9cf361f8 Fix up a few formatting issues 02af3793 Remove last traces of HOT_ADD_DISK 1cc3965d Manage: Remove the legacy code for md driver prior to 0.90.03 761e3bd9 super-intel: don't mark structs 'packed' unnecessarily 85b83a79 SUSE-mdadm_env.sh: handle MDADM_CHECK_DURATION 4ca799c5 mdcheck: use ${} to pass variable to mdcheck 6636788a mdcheck: when mdcheck_start is enabled, enable mdcheck_continue too. 1a1ced1e imsm: allow to specify second volume size b6180160 imsm: save current_vol number 7bd59e79 udev: allow for udev attribute reading bug. 61109314 Don't need to check recovery after re-add when no I/O writes to raid 8063fd0f Init devlist as an array e53cb968 mdadm/md.4: add the descriptions for bitmap sysfs nodes 2c2d9c48 mdadm: force a uuid swap on big endian 43ebc910 mdadm: Introduce new array state 'broken' for raid0/linear fd5b09c9 mdadm: check value returned by snprintf against errors 91c97c54 imsm: close removed drive fd. 1a52f1fc udev: add --no-devices option for calling 'mdadm --detail' d11abe4b mdadm: add --no-devices to avoid component devices detail information 452dc4d1 mdadm.h: include sysmacros.h unconditionally b0681598 mdadm: load default sysfs attributes after assemblation 486720e0 super-intel: Use put_unaligned in split_ull 7039d1f8 mdadm.h: Introduced unaligned {get,put}_unaligned{16,32}() a4f7290c super-intel: Fix issue with abs() being irrelevant 4ec389e3 Enable probe_roms to scan more than 6 roms. ae7d61e3 mdmon: fix wrong array state when disk fails during mdmon startup 3c9b46cf udev: Add udev rules to create by-partuuid for md device 22dc741f Create: Block rounding size to max 05501181 imsm: fix spare activation for old matrix arrays 227aeaa8 add missing units to --examine 2b57e4fe Assemble: Fix starting array with initial reshape checkpoint d2e11da4 mdmon: wait for previous mdmon to exit during takeover 69d08478 mdmon: don't attempt to manage new arrays when terminating 76b906d2 mdadm/tests: add one test case for failfast of raid1 cab114c5 Fix reshape for decreasing data offset e3615ecb Detail.c: do not skip first character when calling xstrdup in Detail() ebf3be99 Fix spelling typos. 9f421827 imsm: fix reshape for >2TB drives a4e96fd8 imsm: finish recovery when drive with rebuild fails 757e5543 policy.c: Fix for compiler error 467e6a1b policy.c: prevent NULL pointer referencing 76d505de Grow: report correct new chunk size. 085df422 Grow: avoid overflow in compute_backup_blocks() 563ac108 Assemble: mask FAILFAST and WRITEMOSTLY flags when finding the most recent device d7a1fda2 imsm: update metadata correctly while raid10 double degradation 7cd7e91a Monitor: add system timer to run --oneshot periodically 4199d3c6 mdcheck: add systemd unit files to run mdcheck. cd72f9d1 policy: support devices with multiple paths. 6b611284 Document PART-POLICY lines 0833f9c3 Assemble: keep MD_DISK_FAILFAST and MD_DISK_WRITEMOSTLY flag Signed-off-by: Nick Hainke --- package/utils/mdadm/Makefile | 15 +++++--- .../mdadm/patches/100-cross_compile.patch | 2 +- ...h-Undefine-dprintf-before-redefining.patch | 38 ------------------- ...missing-include-file-sys-sysmacros.h.patch | 29 -------------- .../utils/mdadm/patches/200-reduce_size.patch | 20 +++++----- 5 files changed, 21 insertions(+), 83 deletions(-) delete mode 100644 package/utils/mdadm/patches/101-mdadm.h-Undefine-dprintf-before-redefining.patch delete mode 100644 package/utils/mdadm/patches/102-Add-missing-include-file-sys-sysmacros.h.patch diff --git a/package/utils/mdadm/Makefile b/package/utils/mdadm/Makefile index f6696bf21c..553728194e 100644 --- a/package/utils/mdadm/Makefile +++ b/package/utils/mdadm/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mdadm -PKG_VERSION:=4.1 -PKG_RELEASE:=2 +PKG_VERSION:=4.2 +PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@KERNEL/linux/utils/raid/mdadm -PKG_HASH:=ab7688842908d3583a704d491956f31324c3a5fc9f6a04653cb75d19f1934f4a +PKG_HASH:=461c215670864bb74a4d1a3620684aa2b2f8296dffa06743f26dda5557acf01d PKG_MAINTAINER:=Felix Fietkau PKG_CPE_ID:=cpe:/a:mdadm_project:mdadm @@ -48,11 +48,16 @@ TARGET_CFLAGS += \ -DCONFFILE='\"/var/etc/mdadm.conf\"' \ -DMAP_DIR='\"/var/run/mdadm\"' \ -DMDMON_DIR='\"/var/run/mdadm\"' \ - -DFAILED_SLOTS_DIR='\"/var/run/mdadm/failed-slots\"' + -DFAILED_SLOTS_DIR='\"/var/run/mdadm/failed-slots\"' \ + -DNO_LIBUDEV + +TARGET_CXFLAGS = -DNO_LIBUDEV TARGET_LDFLAGS += -Wl,--gc-sections -MAKE_FLAGS += CHECK_RUN_DIR=0 +MAKE_FLAGS += \ + CHECK_RUN_DIR=0 \ + CXFLAGS="$(TARGET_CXFLAGS)" define Build/Compile $(call Build/Compile/Default,mdadm) diff --git a/package/utils/mdadm/patches/100-cross_compile.patch b/package/utils/mdadm/patches/100-cross_compile.patch index 0a5fa017c6..790d7755b0 100644 --- a/package/utils/mdadm/patches/100-cross_compile.patch +++ b/package/utils/mdadm/patches/100-cross_compile.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -97,7 +97,7 @@ DLM:=$(shell [ -f /usr/include/libdlm.h +@@ -99,7 +99,7 @@ DLM:=$(shell [ -f /usr/include/libdlm.h DIRFLAGS = -DMAP_DIR=\"$(MAP_DIR)\" -DMAP_FILE=\"$(MAP_FILE)\" DIRFLAGS += -DMDMON_DIR=\"$(MDMON_DIR)\" DIRFLAGS += -DFAILED_SLOTS_DIR=\"$(FAILED_SLOTS_DIR)\" diff --git a/package/utils/mdadm/patches/101-mdadm.h-Undefine-dprintf-before-redefining.patch b/package/utils/mdadm/patches/101-mdadm.h-Undefine-dprintf-before-redefining.patch deleted file mode 100644 index 356d0deec8..0000000000 --- a/package/utils/mdadm/patches/101-mdadm.h-Undefine-dprintf-before-redefining.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6d369e8f226594632ce4260129509daf7030de0a Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Mon, 9 May 2016 22:03:57 +0000 -Subject: [PATCH] mdadm.h: Undefine dprintf before redefining - -dprintf is also defined in libc see -usr/include/bits/stdio2.h, this comes into -play especially when fortify sources is enabled -and compilers like clang reports the override - -In file included from policy.c:25: -./mdadm.h:1562:9: error: 'dprintf' macro redefined [-Werror,-Wmacro-redefined] - ^ -/mnt/oe/openembedded-core/build/tmp-glibc/sysroots/qemux86/usr/include/bits/stdio2.h:145:12: note: previous definition is here - -Signed-off-by: Khem Raj ---- -Upstream-Status: Pending - - mdadm.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/mdadm.h -+++ b/mdadm.h -@@ -1649,11 +1649,13 @@ static inline char *to_subarray(struct m - } - - #ifdef DEBUG -+#undef dprintf - #define dprintf(fmt, arg...) \ - fprintf(stderr, "%s: %s: "fmt, Name, __func__, ##arg) - #define dprintf_cont(fmt, arg...) \ - fprintf(stderr, fmt, ##arg) - #else -+#undef dprintf - #define dprintf(fmt, arg...) \ - ({ if (0) fprintf(stderr, "%s: %s: " fmt, Name, __func__, ##arg); 0; }) - #define dprintf_cont(fmt, arg...) \ diff --git a/package/utils/mdadm/patches/102-Add-missing-include-file-sys-sysmacros.h.patch b/package/utils/mdadm/patches/102-Add-missing-include-file-sys-sysmacros.h.patch deleted file mode 100644 index 891b5c62f0..0000000000 --- a/package/utils/mdadm/patches/102-Add-missing-include-file-sys-sysmacros.h.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 452dc4d13a012cdcb05088c0dbc699959c4d6c73 Mon Sep 17 00:00:00 2001 -From: Baruch Siach -Date: Tue, 6 Aug 2019 16:05:23 +0300 -Subject: mdadm.h: include sysmacros.h unconditionally - -musl libc now also requires sys/sysmacros.h for the major/minor macros. -All supported libc implementations carry sys/sysmacros.h, including -diet-libc, klibc, and uclibc-ng. - -Cc: Hauke Mehrtens -Signed-off-by: Baruch Siach -Signed-off-by: Jes Sorensen ---- - mdadm.h | 2 -- - 1 file changed, 2 deletions(-) - ---- a/mdadm.h -+++ b/mdadm.h -@@ -45,10 +45,8 @@ extern __off64_t lseek64 __P ((int __fd, - #include - #include - #include --#ifdef __GLIBC__ - /* Newer glibc requires sys/sysmacros.h directly for makedev() */ - #include --#endif - #ifdef __dietlibc__ - #include - /* dietlibc has deprecated random and srandom!! */ diff --git a/package/utils/mdadm/patches/200-reduce_size.patch b/package/utils/mdadm/patches/200-reduce_size.patch index 6905c2ccfe..163e125c22 100644 --- a/package/utils/mdadm/patches/200-reduce_size.patch +++ b/package/utils/mdadm/patches/200-reduce_size.patch @@ -1,19 +1,19 @@ --- a/Incremental.c +++ b/Incremental.c -@@ -1619,6 +1619,10 @@ static int Incremental_container(struct - if (ra_all == ra_blocked) - return 0; +@@ -983,6 +983,10 @@ static int array_try_spare(char *devname + goto next; + } -+#ifndef MDADM_FULL -+ return 0; -+#endif ++ #ifndef MDADM_FULL ++ return 0; ++ #endif + - /* Now move all suitable spares from spare container */ - domains = domain_from_array(list, st->ss->name); - memcpy(suuid, uuid_zero, sizeof(int[4])); + dl = domain_from_array(sra, st2->ss->name); + if (domain_test(dl, pol, st2->ss->name) != 1) { + /* domain test fails */ --- a/util.c +++ b/util.c -@@ -1220,7 +1220,9 @@ void wait_for(char *dev, int fd) +@@ -1147,7 +1147,9 @@ void wait_for(char *dev, int fd) struct superswitch *superlist[] = { &super0, &super1, From f953a1a4bfba2fa70c12bb80938aa66481a673b6 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sat, 30 Apr 2022 10:42:33 +0200 Subject: [PATCH 45/75] ramips: zbt-wg2626: Add the reset gpio for PCIe port 1 The 2.4GHz interface doesn't come up properly with the log showing: mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) As seen on other MT7621 boards this is caused by a missing reset GPIO. The MT7621 dtsi set GPIO 19 as PCIe reset GPIO, which on this board reset the 5GHz interface on port 0. Add GPIO 8 to the PCIe reset GPIO list to also reset the 2.4GHz interface on port 1. Signed-off-by: Alban Bedel --- target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts index a1d6af9466..da22dc3797 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts @@ -88,6 +88,9 @@ &pcie { status = "okay"; + + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>, + <&gpio 8 GPIO_ACTIVE_LOW>; }; &pcie0 { From d806c3caf3170aff6feeb0b2eabf5bb57af3bb53 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sat, 23 Apr 2022 11:28:51 +0200 Subject: [PATCH 46/75] ramips: zbt-wg2626: Fix the LAN ports names The current names don't match with the labels on the case, reverse the LAN ports order so they match. Signed-off-by: Alban Bedel --- target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts index da22dc3797..e764cb636b 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts @@ -122,22 +122,22 @@ ports { port@0 { status = "okay"; - label = "lan1"; + label = "lan4"; }; port@1 { status = "okay"; - label = "lan2"; + label = "lan3"; }; port@2 { status = "okay"; - label = "lan3"; + label = "lan2"; }; port@3 { status = "okay"; - label = "lan4"; + label = "lan1"; }; port@4 { From 87318eb1793611a5690730ea6e38b168bd7e7355 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 20 Nov 2021 23:05:02 +0100 Subject: [PATCH 47/75] ipq40xx: 5:15: copy config and patch from 5.10 Copy config and patch from 5.10 to 5.15 Signed-off-by: Ansuel Smith --- target/linux/ipq40xx/config-5.15 | 496 +++++ .../files-5.15/drivers/net/mdio/ar40xx.c | 1890 +++++++++++++++++ .../files-5.15/drivers/net/mdio/ar40xx.h | 342 +++ ...com-ipq4019-add-USB-devicetree-nodes.patch | 99 + ...ARM-dts-qcom-ipq4019-add-more-labels.patch | 44 + ...com-ipq4019-add-SDHCI-VQMMC-LDO-node.patch | 35 + .../104-clk-fix-apss-cpu-overclocking.patch | 115 + .../105-ipq40xx-fix-sleep-clock.patch | 26 + .../300-clk-qcom-ipq4019-add-ess-reset.patch | 52 + ...-compressed-add-appended-DTB-section.patch | 48 + ...d-set-ipq40xx-watchdog-to-allow-boot.patch | 66 + ...msm-use-sdhci_set_clock-instead-of-s.patch | 24 + .../420-firmware-qcom-scm-disable-SDI.patch | 47 + ...-firmware-qcom-scm-cold-boot-address.patch | 121 ++ ...702-dts-ipq4019-add-PHY-switch-nodes.patch | 46 + ...4019-needs-rfs-vlan_tag-callbacks-in.patch | 53 + .../705-net-add-qualcomm-ar40xx-phy.patch | 27 + .../706-dt-bindings-net-add-QCA807x-PHY.patch | 61 + ...7-net-phy-Add-Qualcom-QCA807x-driver.patch | 50 + ...8-arm-dts-ipq4019-QCA807x-properties.patch | 62 + ...add-qualcomm-essedma-ethernet-driver.patch | 37 + ...ts-ipq4019-add-ethernet-essedma-node.patch | 92 + .../850-soc-add-qualcomm-syscon.patch | 180 ++ .../900-dts-ipq4019-ap-dk01.1.patch | 176 ++ .../901-arm-boot-add-dts-files.patch | 89 + .../902-dts-ipq4019-ap-dk04.1.patch | 167 ++ 26 files changed, 4445 insertions(+) create mode 100644 target/linux/ipq40xx/config-5.15 create mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.c create mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.h create mode 100644 target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch create mode 100644 target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch create mode 100644 target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch create mode 100644 target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch create mode 100644 target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch create mode 100644 target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch create mode 100644 target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch create mode 100644 target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch create mode 100644 target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch create mode 100644 target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch create mode 100644 target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch create mode 100644 target/linux/ipq40xx/patches-5.15/702-dts-ipq4019-add-PHY-switch-nodes.patch create mode 100644 target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch create mode 100644 target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch create mode 100644 target/linux/ipq40xx/patches-5.15/706-dt-bindings-net-add-QCA807x-PHY.patch create mode 100644 target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch create mode 100644 target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch create mode 100644 target/linux/ipq40xx/patches-5.15/710-net-add-qualcomm-essedma-ethernet-driver.patch create mode 100644 target/linux/ipq40xx/patches-5.15/711-dts-ipq4019-add-ethernet-essedma-node.patch create mode 100644 target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch create mode 100644 target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch create mode 100644 target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch create mode 100644 target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch diff --git a/target/linux/ipq40xx/config-5.15 b/target/linux/ipq40xx/config-5.15 new file mode 100644 index 0000000000..779c86fc95 --- /dev/null +++ b/target/linux/ipq40xx/config-5.15 @@ -0,0 +1,496 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_APQ_GCC_8084 is not set +# CONFIG_APQ_MMCC_8084 is not set +CONFIG_AR40XX_PHY=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_IPQ40XX=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +# CONFIG_ARCH_MDM9615 is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_ARCH_MSM8960 is not set +# CONFIG_ARCH_MSM8974 is not set +# CONFIG_ARCH_MSM8X60 is not set +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_CPUIDLE=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_QCOM_CPUFREQ_HW is not set +# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set +# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT803X_PHY=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BCH=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_CMDLINE_PARSER=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_QCOM=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRYPTO_AES_ARM=y +CONFIG_CRYPTO_AES_ARM_BS=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEV_QCE=y +# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set +# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set +CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y +CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y +CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 +CONFIG_CRYPTO_DEV_QCOM_RNG=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM=y +CONFIG_CRYPTO_SIMD=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MISC=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_ESSEDMA=y +CONFIG_EXTCON=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_74X164=y +CONFIG_GPIO_WATCHDOG=y +CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OPTEE=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +# CONFIG_I2C_QCOM_CCI is not set +CONFIG_I2C_QUP=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +# CONFIG_IPQ_APSS_PLL is not set +CONFIG_IPQ_GCC_4019=y +# CONFIG_IPQ_GCC_6018 is not set +# CONFIG_IPQ_GCC_806X is not set +# CONFIG_IPQ_GCC_8074 is not set +# CONFIG_IPQ_LCC_806X is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_KPSS_XCC is not set +# CONFIG_KRAITCC is not set +CONFIG_LEDS_LP5523=y +CONFIG_LEDS_LP5562=y +CONFIG_LEDS_LP55XX_COMMON=y +CONFIG_LEDS_TLC591XX=y +CONFIG_LIBFDT=y +CONFIG_LLD_VERSION=0 +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_GPIO=y +CONFIG_MDIO_IPQ4019=y +# CONFIG_MDM_GCC_9615 is not set +# CONFIG_MDM_LCC_9615 is not set +CONFIG_MEMFD_CREATE=y +# CONFIG_MFD_HI6421_SPMI is not set +# CONFIG_MFD_QCOM_RPM is not set +# CONFIG_MFD_SPMI_PMIC is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_MSM=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MSM_GCC_8660 is not set +# CONFIG_MSM_GCC_8916 is not set +# CONFIG_MSM_GCC_8939 is not set +# CONFIG_MSM_GCC_8960 is not set +# CONFIG_MSM_GCC_8974 is not set +# CONFIG_MSM_GCC_8994 is not set +# CONFIG_MSM_GCC_8996 is not set +# CONFIG_MSM_GCC_8998 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_LCC_8960 is not set +# CONFIG_MSM_MMCC_8960 is not set +# CONFIG_MSM_MMCC_8974 is not set +# CONFIG_MSM_MMCC_8996 is not set +# CONFIG_MSM_MMCC_8998 is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_SPLIT_WRGG_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NLS=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_NVMEM=y +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OPTEE=y +CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_QCOM=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +CONFIG_PHY_QCOM_IPQ4019_USB=y +# CONFIG_PHY_QCOM_IPQ806X_SATA is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set +# CONFIG_PHY_QCOM_PCIE2 is not set +# CONFIG_PHY_QCOM_QMP is not set +# CONFIG_PHY_QCOM_QUSB2 is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_SS is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_APQ8064 is not set +# CONFIG_PINCTRL_APQ8084 is not set +CONFIG_PINCTRL_IPQ4019=y +# CONFIG_PINCTRL_IPQ6018 is not set +# CONFIG_PINCTRL_IPQ8064 is not set +# CONFIG_PINCTRL_IPQ8074 is not set +# CONFIG_PINCTRL_MDM9615 is not set +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8226 is not set +# CONFIG_PINCTRL_MSM8660 is not set +# CONFIG_PINCTRL_MSM8916 is not set +# CONFIG_PINCTRL_MSM8960 is not set +# CONFIG_PINCTRL_MSM8976 is not set +# CONFIG_PINCTRL_MSM8994 is not set +# CONFIG_PINCTRL_MSM8996 is not set +# CONFIG_PINCTRL_MSM8998 is not set +# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set +# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +# CONFIG_PINCTRL_QCS404 is not set +# CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SDM660 is not set +# CONFIG_PINCTRL_SDM845 is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PINCTRL_SM8250 is not set +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_QCA807X_PHY=y +CONFIG_QCOM_A53PLL=y +CONFIG_QCOM_BAM_DMA=y +# CONFIG_QCOM_COMMAND_DB is not set +# CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_EBI2 is not set +# CONFIG_QCOM_GENI_SE is not set +# CONFIG_QCOM_GSBI is not set +# CONFIG_QCOM_HFPLL is not set +# CONFIG_QCOM_IOMMU is not set +# CONFIG_QCOM_LLCC is not set +# CONFIG_QCOM_OCMEM is not set +# CONFIG_QCOM_PDC is not set +CONFIG_QCOM_QFPROM=y +# CONFIG_QCOM_RMTFS_MEM is not set +# CONFIG_QCOM_RPMH is not set +CONFIG_QCOM_SCM=y +# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +CONFIG_QCOM_SMEM=y +# CONFIG_QCOM_SMSM is not set +# CONFIG_QCOM_SOCINFO is not set +CONFIG_QCOM_TCSR=y +# CONFIG_QCOM_TSENS is not set +CONFIG_QCOM_WDT=y +# CONFIG_QCS_GCC_404 is not set +# CONFIG_QCS_Q6SSTOP_404 is not set +# CONFIG_QCS_TURING_404 is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_QCOM_LABIBB is not set +# CONFIG_REGULATOR_QCOM_SPMI is not set +# CONFIG_REGULATOR_QCOM_USB_VBUS is not set +CONFIG_REGULATOR_VCTRL=y +CONFIG_REGULATOR_VQMMC_IPQ4019=y +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_QCOM_AOSS is not set +# CONFIG_RESET_QCOM_PDC is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_SC_DISPCC_7180 is not set +# CONFIG_SC_GCC_7180 is not set +# CONFIG_SC_GPUCC_7180 is not set +# CONFIG_SC_LPASS_CORECC_7180 is not set +# CONFIG_SC_MSS_7180 is not set +# CONFIG_SC_VIDEOCC_7180 is not set +# CONFIG_SDM_CAMCC_845 is not set +# CONFIG_SDM_DISPCC_845 is not set +# CONFIG_SDM_GCC_660 is not set +# CONFIG_SDM_GCC_845 is not set +# CONFIG_SDM_GPUCC_845 is not set +# CONFIG_SDM_LPASSCC_845 is not set +# CONFIG_SDM_VIDEOCC_845 is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +# CONFIG_SM_GCC_8150 is not set +# CONFIG_SM_GCC_8250 is not set +# CONFIG_SM_GPUCC_8150 is not set +# CONFIG_SM_GPUCC_8250 is not set +# CONFIG_SM_VIDEOCC_8150 is not set +# CONFIG_SM_VIDEOCC_8250 is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_QUP=y +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +CONFIG_SPMI_MSM_PMIC_ARB=y +# CONFIG_SPMI_PMIC_CLKDIV is not set +CONFIG_SRCU=y +CONFIG_SWCONFIG=y +CONFIG_SWCONFIG_LEDS=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TEE=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.c b/target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.c new file mode 100644 index 0000000000..f7ce42b9ff --- /dev/null +++ b/target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.c @@ -0,0 +1,1890 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ar40xx.h" + +static struct ar40xx_priv *ar40xx_priv; + +#define MIB_DESC(_s , _o, _n) \ + { \ + .size = (_s), \ + .offset = (_o), \ + .name = (_n), \ + } + +static const struct ar40xx_mib_desc ar40xx_mibs[] = { + MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"), + MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"), + MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"), + MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"), + MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"), + MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"), + MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"), + MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"), + MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"), + MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"), + MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"), + MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"), + MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"), + MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"), + MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"), + MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"), + MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"), + MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"), + MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"), + MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"), + MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"), + MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"), + MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"), + MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"), + MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"), + MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"), + MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"), + MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"), + MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"), + MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"), + MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"), + MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"), + MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"), + MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"), + MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"), + MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"), + MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"), + MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"), + MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"), +}; + +static u32 +ar40xx_read(struct ar40xx_priv *priv, int reg) +{ + return readl(priv->hw_addr + reg); +} + +static u32 +ar40xx_psgmii_read(struct ar40xx_priv *priv, int reg) +{ + return readl(priv->psgmii_hw_addr + reg); +} + +static void +ar40xx_write(struct ar40xx_priv *priv, int reg, u32 val) +{ + writel(val, priv->hw_addr + reg); +} + +static u32 +ar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val) +{ + u32 ret; + + ret = ar40xx_read(priv, reg); + ret &= ~mask; + ret |= val; + ar40xx_write(priv, reg, ret); + return ret; +} + +static void +ar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val) +{ + writel(val, priv->psgmii_hw_addr + reg); +} + +static void +ar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr, + u16 dbg_addr, u16 dbg_data) +{ + struct mii_bus *bus = priv->mii_bus; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr); + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data); + mutex_unlock(&bus->mdio_lock); +} + +static void +ar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr, + u16 dbg_addr, u16 *dbg_data) +{ + struct mii_bus *bus = priv->mii_bus; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr); + *dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA); + mutex_unlock(&bus->mdio_lock); +} + +static void +ar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id, + u16 mmd_num, u16 reg_id, u16 reg_val) +{ + struct mii_bus *bus = priv->mii_bus; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_id, + AR40XX_MII_ATH_MMD_ADDR, mmd_num); + bus->write(bus, phy_id, + AR40XX_MII_ATH_MMD_DATA, reg_id); + bus->write(bus, phy_id, + AR40XX_MII_ATH_MMD_ADDR, + 0x4000 | mmd_num); + bus->write(bus, phy_id, + AR40XX_MII_ATH_MMD_DATA, reg_val); + mutex_unlock(&bus->mdio_lock); +} + +static u16 +ar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id, + u16 mmd_num, u16 reg_id) +{ + u16 value; + struct mii_bus *bus = priv->mii_bus; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_id, + AR40XX_MII_ATH_MMD_ADDR, mmd_num); + bus->write(bus, phy_id, + AR40XX_MII_ATH_MMD_DATA, reg_id); + bus->write(bus, phy_id, + AR40XX_MII_ATH_MMD_ADDR, + 0x4000 | mmd_num); + value = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA); + mutex_unlock(&bus->mdio_lock); + return value; +} + +/* Start of swconfig support */ + +static void +ar40xx_phy_poll_reset(struct ar40xx_priv *priv) +{ + u32 i, in_reset, retries = 500; + struct mii_bus *bus = priv->mii_bus; + + /* Assume RESET was recently issued to some or all of the phys */ + in_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0); + + while (retries--) { + /* 1ms should be plenty of time. + * 802.3 spec allows for a max wait time of 500ms + */ + usleep_range(1000, 2000); + + for (i = 0; i < AR40XX_NUM_PHYS; i++) { + int val; + + /* skip devices which have completed reset */ + if (!(in_reset & BIT(i))) + continue; + + val = mdiobus_read(bus, i, MII_BMCR); + if (val < 0) + continue; + + /* mark when phy is no longer in reset state */ + if (!(val & BMCR_RESET)) + in_reset &= ~BIT(i); + } + + if (!in_reset) + return; + } + + dev_warn(&bus->dev, "Failed to reset all phys! (in_reset: 0x%x)\n", + in_reset); +} + +static void +ar40xx_phy_init(struct ar40xx_priv *priv) +{ + int i; + struct mii_bus *bus; + u16 val; + + bus = priv->mii_bus; + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) { + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val); + val &= ~AR40XX_PHY_MANU_CTRL_EN; + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val); + mdiobus_write(bus, i, + MII_ADVERTISE, ADVERTISE_ALL | + ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL); + mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); + } + + ar40xx_phy_poll_reset(priv); +} + +static void +ar40xx_port_phy_linkdown(struct ar40xx_priv *priv) +{ + struct mii_bus *bus; + int i; + u16 val; + + bus = priv->mii_bus; + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) { + mdiobus_write(bus, i, MII_CTRL1000, 0); + mdiobus_write(bus, i, MII_ADVERTISE, 0); + mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val); + val |= AR40XX_PHY_MANU_CTRL_EN; + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val); + /* disable transmit */ + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val); + val &= 0xf00f; + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val); + } +} + +static void +ar40xx_set_mirror_regs(struct ar40xx_priv *priv) +{ + int port; + + /* reset all mirror registers */ + ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0, + AR40XX_FWD_CTRL0_MIRROR_PORT, + (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S)); + for (port = 0; port < AR40XX_NUM_PORTS; port++) { + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port), + AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0); + + ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port), + AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0); + } + + /* now enable mirroring if necessary */ + if (priv->source_port >= AR40XX_NUM_PORTS || + priv->monitor_port >= AR40XX_NUM_PORTS || + priv->source_port == priv->monitor_port) { + return; + } + + ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0, + AR40XX_FWD_CTRL0_MIRROR_PORT, + (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S)); + + if (priv->mirror_rx) + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0, + AR40XX_PORT_LOOKUP_ING_MIRROR_EN); + + if (priv->mirror_tx) + ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port), + 0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN); +} + +static int +ar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + u8 ports = priv->vlan_table[val->port_vlan]; + int i; + + val->len = 0; + for (i = 0; i < dev->ports; i++) { + struct switch_port *p; + + if (!(ports & BIT(i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if ((priv->vlan_tagged & BIT(i)) || + (priv->pvid[i] != val->port_vlan)) + p->flags = BIT(SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + return 0; +} + +static int +ar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + u8 *vt = &priv->vlan_table[val->port_vlan]; + int i; + + *vt = 0; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) { + if (val->port_vlan == priv->pvid[p->id]) + priv->vlan_tagged |= BIT(p->id); + } else { + priv->vlan_tagged &= ~BIT(p->id); + priv->pvid[p->id] = val->port_vlan; + } + + *vt |= BIT(p->id); + } + return 0; +} + +static int +ar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int i; + + for (i = 0; i < timeout; i++) { + u32 t; + + t = ar40xx_read(priv, reg); + if ((t & mask) == val) + return 0; + + usleep_range(1000, 2000); + } + + return -ETIMEDOUT; +} + +static int +ar40xx_mib_op(struct ar40xx_priv *priv, u32 op) +{ + int ret; + + lockdep_assert_held(&priv->mib_lock); + + /* Capture the hardware statistics for all ports */ + ar40xx_rmw(priv, AR40XX_REG_MIB_FUNC, + AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S)); + + /* Wait for the capturing to complete. */ + ret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC, + AR40XX_MIB_BUSY, 0, 10); + + return ret; +} + +static void +ar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush) +{ + unsigned int base; + u64 *mib_stats; + int i; + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs); + + WARN_ON(port >= priv->dev.ports); + + lockdep_assert_held(&priv->mib_lock); + + base = AR40XX_REG_PORT_STATS_START + + AR40XX_REG_PORT_STATS_LEN * port; + + mib_stats = &priv->mib_stats[port * num_mibs]; + if (flush) { + u32 len; + + len = num_mibs * sizeof(*mib_stats); + memset(mib_stats, 0, len); + return; + } + for (i = 0; i < num_mibs; i++) { + const struct ar40xx_mib_desc *mib; + u64 t; + + mib = &ar40xx_mibs[i]; + t = ar40xx_read(priv, base + mib->offset); + if (mib->size == 2) { + u64 hi; + + hi = ar40xx_read(priv, base + mib->offset + 4); + t |= hi << 32; + } + + mib_stats[i] += t; + } +} + +static int +ar40xx_mib_capture(struct ar40xx_priv *priv) +{ + return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE); +} + +static int +ar40xx_mib_flush(struct ar40xx_priv *priv) +{ + return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH); +} + +static int +ar40xx_sw_set_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + unsigned int len; + int ret; + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs); + + mutex_lock(&priv->mib_lock); + + len = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats); + memset(priv->mib_stats, 0, len); + ret = ar40xx_mib_flush(priv); + + mutex_unlock(&priv->mib_lock); + return ret; +} + +static int +ar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + priv->vlan = !!val->value.i; + return 0; +} + +static int +ar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + val->value.i = priv->vlan; + return 0; +} + +static int +ar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + priv->mirror_rx = !!val->value.i; + ar40xx_set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int +ar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + val->value.i = priv->mirror_rx; + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int +ar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + priv->mirror_tx = !!val->value.i; + ar40xx_set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int +ar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + val->value.i = priv->mirror_tx; + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int +ar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + priv->monitor_port = val->value.i; + ar40xx_set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int +ar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + val->value.i = priv->monitor_port; + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int +ar40xx_sw_set_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + priv->source_port = val->value.i; + ar40xx_set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int +ar40xx_sw_get_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + mutex_lock(&priv->reg_mutex); + val->value.i = priv->source_port; + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int +ar40xx_sw_set_linkdown(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + if (val->value.i == 1) + ar40xx_port_phy_linkdown(priv); + else + ar40xx_phy_init(priv); + + return 0; +} + +static int +ar40xx_sw_set_port_reset_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + int port; + int ret; + + port = val->port_vlan; + if (port >= dev->ports) + return -EINVAL; + + mutex_lock(&priv->mib_lock); + ret = ar40xx_mib_capture(priv); + if (ret) + goto unlock; + + ar40xx_mib_fetch_port_stat(priv, port, true); + +unlock: + mutex_unlock(&priv->mib_lock); + return ret; +} + +static int +ar40xx_sw_get_port_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + u64 *mib_stats; + int port; + int ret; + char *buf = priv->buf; + int i, len = 0; + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs); + + port = val->port_vlan; + if (port >= dev->ports) + return -EINVAL; + + mutex_lock(&priv->mib_lock); + ret = ar40xx_mib_capture(priv); + if (ret) + goto unlock; + + ar40xx_mib_fetch_port_stat(priv, port, false); + + len += snprintf(buf + len, sizeof(priv->buf) - len, + "Port %d MIB counters\n", + port); + + mib_stats = &priv->mib_stats[port * num_mibs]; + for (i = 0; i < num_mibs; i++) + len += snprintf(buf + len, sizeof(priv->buf) - len, + "%-12s: %llu\n", + ar40xx_mibs[i].name, + mib_stats[i]); + + val->value.s = buf; + val->len = len; + +unlock: + mutex_unlock(&priv->mib_lock); + return ret; +} + +static int +ar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + priv->vlan_id[val->port_vlan] = val->value.i; + return 0; +} + +static int +ar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + val->value.i = priv->vlan_id[val->port_vlan]; + return 0; +} + +static int +ar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + *vlan = priv->pvid[port]; + return 0; +} + +static int +ar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + /* make sure no invalid PVIDs get set */ + if (vlan >= dev->vlans) + return -EINVAL; + + priv->pvid[port] = vlan; + return 0; +} + +static void +ar40xx_read_port_link(struct ar40xx_priv *priv, int port, + struct switch_port_link *link) +{ + u32 status; + u32 speed; + + memset(link, 0, sizeof(*link)); + + status = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port)); + + link->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN); + if (link->aneg || (port != AR40XX_PORT_CPU)) + link->link = !!(status & AR40XX_PORT_STATUS_LINK_UP); + else + link->link = true; + + if (!link->link) + return; + + link->duplex = !!(status & AR40XX_PORT_DUPLEX); + link->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW); + link->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW); + + speed = (status & AR40XX_PORT_SPEED) >> + AR40XX_PORT_STATUS_SPEED_S; + + switch (speed) { + case AR40XX_PORT_SPEED_10M: + link->speed = SWITCH_PORT_SPEED_10; + break; + case AR40XX_PORT_SPEED_100M: + link->speed = SWITCH_PORT_SPEED_100; + break; + case AR40XX_PORT_SPEED_1000M: + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } +} + +static int +ar40xx_sw_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + + ar40xx_read_port_link(priv, port, link); + return 0; +} + +static const struct switch_attr ar40xx_sw_attr_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = ar40xx_sw_set_vlan, + .get = ar40xx_sw_get_vlan, + .max = 1 + }, + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mibs", + .description = "Reset all MIB counters", + .set = ar40xx_sw_set_reset_mibs, + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_rx", + .description = "Enable mirroring of RX packets", + .set = ar40xx_sw_set_mirror_rx_enable, + .get = ar40xx_sw_get_mirror_rx_enable, + .max = 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_tx", + .description = "Enable mirroring of TX packets", + .set = ar40xx_sw_set_mirror_tx_enable, + .get = ar40xx_sw_get_mirror_tx_enable, + .max = 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "mirror_monitor_port", + .description = "Mirror monitor port", + .set = ar40xx_sw_set_mirror_monitor_port, + .get = ar40xx_sw_get_mirror_monitor_port, + .max = AR40XX_NUM_PORTS - 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "mirror_source_port", + .description = "Mirror source port", + .set = ar40xx_sw_set_mirror_source_port, + .get = ar40xx_sw_get_mirror_source_port, + .max = AR40XX_NUM_PORTS - 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "linkdown", + .description = "Link down all the PHYs", + .set = ar40xx_sw_set_linkdown, + .max = 1 + }, +}; + +static const struct switch_attr ar40xx_sw_attr_port[] = { + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mib", + .description = "Reset single port MIB counters", + .set = ar40xx_sw_set_port_reset_mib, + }, + { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get port's MIB counters", + .set = NULL, + .get = ar40xx_sw_get_port_mib, + }, +}; + +const struct switch_attr ar40xx_sw_attr_vlan[] = { + { + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "VLAN ID (0-4094)", + .set = ar40xx_sw_set_vid, + .get = ar40xx_sw_get_vid, + .max = 4094, + }, +}; + +/* End of swconfig support */ + +static int +ar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val) +{ + int timeout = 20; + u32 t; + + while (1) { + t = ar40xx_read(priv, reg); + if ((t & mask) == val) + return 0; + + if (timeout-- <= 0) + break; + + usleep_range(10, 20); + } + + pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n", + (unsigned int)reg, t, mask, val); + return -ETIMEDOUT; +} + +static int +ar40xx_atu_flush(struct ar40xx_priv *priv) +{ + int ret; + + ret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC, + AR40XX_ATU_FUNC_BUSY, 0); + if (!ret) + ar40xx_write(priv, AR40XX_REG_ATU_FUNC, + AR40XX_ATU_FUNC_OP_FLUSH | + AR40XX_ATU_FUNC_BUSY); + + return ret; +} + +static void +ar40xx_ess_reset(struct ar40xx_priv *priv) +{ + reset_control_assert(priv->ess_rst); + mdelay(10); + reset_control_deassert(priv->ess_rst); + /* Waiting for all inner tables init done. + * It cost 5~10ms. + */ + mdelay(10); + + pr_info("ESS reset ok!\n"); +} + +/* Start of psgmii self test */ + +static void +ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) +{ + u32 n; + struct mii_bus *bus = priv->mii_bus; + /* reset phy psgmii */ + /* fix phy psgmii RX 20bit */ + mdiobus_write(bus, 5, 0x0, 0x005b); + /* reset phy psgmii */ + mdiobus_write(bus, 5, 0x0, 0x001b); + /* release reset phy psgmii */ + mdiobus_write(bus, 5, 0x0, 0x005b); + + for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) { + u16 status; + + status = ar40xx_phy_mmd_read(priv, 5, 1, 0x28); + if (status & BIT(0)) + break; + /* Polling interval to check PSGMII PLL in malibu is ready + * the worst time is 8.67ms + * for 25MHz reference clock + * [512+(128+2048)*49]*80ns+100us + */ + mdelay(2); + } + + /*check malibu psgmii calibration done end..*/ + + /*freeze phy psgmii RX CDR*/ + mdiobus_write(bus, 5, 0x1a, 0x2230); + + ar40xx_ess_reset(priv); + + /*check psgmii calibration done start*/ + for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) { + u32 status; + + status = ar40xx_psgmii_read(priv, 0xa0); + if (status & BIT(0)) + break; + /* Polling interval to check PSGMII PLL in ESS is ready */ + mdelay(2); + } + + /* check dakota psgmii calibration done end..*/ + + /* relesae phy psgmii RX CDR */ + mdiobus_write(bus, 5, 0x1a, 0x3230); + /* release phy psgmii RX 20bit */ + mdiobus_write(bus, 5, 0x0, 0x005f); +} + +static void +ar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy) +{ + int j; + u32 tx_ok, tx_error; + u32 rx_ok, rx_error; + u32 tx_ok_high16; + u32 rx_ok_high16; + u32 tx_all_ok, rx_all_ok; + struct mii_bus *bus = priv->mii_bus; + + mdiobus_write(bus, phy, 0x0, 0x9000); + mdiobus_write(bus, phy, 0x0, 0x4140); + + for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) { + u16 status; + + status = mdiobus_read(bus, phy, 0x11); + if (status & AR40XX_PHY_SPEC_STATUS_LINK) + break; + /* the polling interval to check if the PHY link up or not + * maxwait_timer: 750 ms +/-10 ms + * minwait_timer : 1 us +/- 0.1us + * time resides in minwait_timer ~ maxwait_timer + * see IEEE 802.3 section 40.4.5.2 + */ + mdelay(8); + } + + /* enable check */ + ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000); + ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003); + + /* start traffic */ + ar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000); + /* wait for all traffic end + * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms + */ + mdelay(50); + + /* check counter */ + tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e); + tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d); + tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f); + rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b); + rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a); + rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c); + tx_all_ok = tx_ok + (tx_ok_high16 << 16); + rx_all_ok = rx_ok + (rx_ok_high16 << 16); + if (tx_all_ok == 0x1000 && tx_error == 0) { + /* success */ + priv->phy_t_status &= (~BIT(phy)); + } else { + pr_info("PHY %d single test PSGMII issue happen!\n", phy); + priv->phy_t_status |= BIT(phy); + } + + mdiobus_write(bus, phy, 0x0, 0x1840); +} + +static void +ar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv) +{ + int phy, j; + struct mii_bus *bus = priv->mii_bus; + + mdiobus_write(bus, 0x1f, 0x0, 0x9000); + mdiobus_write(bus, 0x1f, 0x0, 0x4140); + + for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) { + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { + u16 status; + + status = mdiobus_read(bus, phy, 0x11); + if (!(status & BIT(10))) + break; + } + + if (phy >= (AR40XX_NUM_PORTS - 1)) + break; + /* The polling interva to check if the PHY link up or not */ + mdelay(8); + } + /* enable check */ + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000); + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003); + + /* start traffic */ + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000); + /* wait for all traffic end + * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms + */ + mdelay(50); + + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { + u32 tx_ok, tx_error; + u32 rx_ok, rx_error; + u32 tx_ok_high16; + u32 rx_ok_high16; + u32 tx_all_ok, rx_all_ok; + + /* check counter */ + tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e); + tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d); + tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f); + rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b); + rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a); + rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c); + tx_all_ok = tx_ok + (tx_ok_high16<<16); + rx_all_ok = rx_ok + (rx_ok_high16<<16); + if (tx_all_ok == 0x1000 && tx_error == 0) { + /* success */ + priv->phy_t_status &= ~BIT(phy + 8); + } else { + pr_info("PHY%d test see issue!\n", phy); + priv->phy_t_status |= BIT(phy + 8); + } + } + + pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status); +} + +void +ar40xx_psgmii_self_test(struct ar40xx_priv *priv) +{ + u32 i, phy; + struct mii_bus *bus = priv->mii_bus; + + ar40xx_malibu_psgmii_ess_reset(priv); + + /* switch to access MII reg for copper */ + mdiobus_write(bus, 4, 0x1f, 0x8500); + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { + /*enable phy mdio broadcast write*/ + ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f); + } + /* force no link by power down */ + mdiobus_write(bus, 0x1f, 0x0, 0x1840); + /*packet number*/ + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000); + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0); + + /*fix mdi status */ + mdiobus_write(bus, 0x1f, 0x10, 0x6800); + for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) { + priv->phy_t_status = 0; + + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1), + AR40XX_PORT_LOOKUP_LOOPBACK, + AR40XX_PORT_LOOKUP_LOOPBACK); + } + + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) + ar40xx_psgmii_single_phy_testing(priv, phy); + + ar40xx_psgmii_all_phy_testing(priv); + + if (priv->phy_t_status) + ar40xx_malibu_psgmii_ess_reset(priv); + else + break; + } + + if (i >= AR40XX_PSGMII_CALB_NUM) + pr_info("PSGMII cannot recover\n"); + else + pr_debug("PSGMII recovered after %d times reset\n", i); + + /* configuration recover */ + /* packet number */ + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0); + /* disable check */ + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0); + /* disable traffic */ + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0); +} + +void +ar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv) +{ + int phy; + struct mii_bus *bus = priv->mii_bus; + + /* disable phy internal loopback */ + mdiobus_write(bus, 0x1f, 0x10, 0x6860); + mdiobus_write(bus, 0x1f, 0x0, 0x9040); + + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) { + /* disable mac loop back */ + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1), + AR40XX_PORT_LOOKUP_LOOPBACK, 0); + /* disable phy mdio broadcast write */ + ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f); + } + + /* clear fdb entry */ + ar40xx_atu_flush(priv); +} + +/* End of psgmii self test */ + +static void +ar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode) +{ + if (mode == PORT_WRAPPER_PSGMII) { + ar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200); + ar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380); + } +} + +static +int ar40xx_cpuport_setup(struct ar40xx_priv *priv) +{ + u32 t; + + t = AR40XX_PORT_STATUS_TXFLOW | + AR40XX_PORT_STATUS_RXFLOW | + AR40XX_PORT_TXHALF_FLOW | + AR40XX_PORT_DUPLEX | + AR40XX_PORT_SPEED_1000M; + ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t); + usleep_range(10, 20); + + t |= AR40XX_PORT_TX_EN | + AR40XX_PORT_RX_EN; + ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t); + + return 0; +} + +static void +ar40xx_init_port(struct ar40xx_priv *priv, int port) +{ + u32 t; + + ar40xx_write(priv, AR40XX_REG_PORT_STATUS(port), 0); + + ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0); + + ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0); + + t = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S; + ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t); + + t = AR40XX_PORT_LOOKUP_LEARN; + t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S; + ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t); +} + +void +ar40xx_init_globals(struct ar40xx_priv *priv) +{ + u32 t; + + /* enable CPU port and disable mirror port */ + t = AR40XX_FWD_CTRL0_CPU_PORT_EN | + AR40XX_FWD_CTRL0_MIRROR_PORT; + ar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t); + + /* forward multicast and broadcast frames to CPU */ + t = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) | + (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) | + (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S); + ar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t); + + /* enable jumbo frames */ + ar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE, + AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2); + + /* Enable MIB counters */ + ar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0, + AR40XX_MODULE_EN_MIB); + + /* Disable AZ */ + ar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0); + + /* set flowctrl thershold for cpu port */ + t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) | + AR40XX_PORT0_FC_THRESH_OFF_DFLT; + ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t); +} + +static int +ar40xx_hw_init(struct ar40xx_priv *priv) +{ + u32 i; + + ar40xx_ess_reset(priv); + + if (!priv->mii_bus) + return -1; + + ar40xx_psgmii_self_test(priv); + ar40xx_psgmii_self_test_clean(priv); + + ar40xx_mac_mode_init(priv, priv->mac_mode); + + for (i = 0; i < priv->dev.ports; i++) + ar40xx_init_port(priv, i); + + ar40xx_init_globals(priv); + + return 0; +} + +/* Start of qm error WAR */ + +static +int ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id) +{ + u32 reg; + + if (port_id < 0 || port_id > 6) + return -1; + + reg = AR40XX_REG_PORT_STATUS(port_id); + return ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED, + (AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX)); +} + +static +int ar40xx_get_qm_status(struct ar40xx_priv *priv, + u32 port_id, u32 *qm_buffer_err) +{ + u32 reg; + u32 qm_val; + + if (port_id < 1 || port_id > 5) { + *qm_buffer_err = 0; + return -1; + } + + if (port_id < 4) { + reg = AR40XX_REG_QM_PORT0_3_QNUM; + ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg); + qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE); + /* every 8 bits for each port */ + *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF; + } else { + reg = AR40XX_REG_QM_PORT4_6_QNUM; + ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg); + qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE); + /* every 8 bits for each port */ + *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF; + } + + return 0; +} + +static void +ar40xx_sw_mac_polling_task(struct ar40xx_priv *priv) +{ + static int task_count; + u32 i; + u32 reg, value; + u32 link, speed, duplex; + u32 qm_buffer_err; + u16 port_phy_status[AR40XX_NUM_PORTS]; + static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0}; + static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0}; + struct mii_bus *bus = NULL; + + if (!priv || !priv->mii_bus) + return; + + bus = priv->mii_bus; + + ++task_count; + + for (i = 1; i < AR40XX_NUM_PORTS; ++i) { + port_phy_status[i] = + mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS); + + speed = FIELD_GET(AR40XX_PHY_SPEC_STATUS_SPEED, + port_phy_status[i]); + link = FIELD_GET(AR40XX_PHY_SPEC_STATUS_LINK, + port_phy_status[i]); + duplex = FIELD_GET(AR40XX_PHY_SPEC_STATUS_DUPLEX, + port_phy_status[i]); + + if (link != priv->ar40xx_port_old_link[i]) { + ++link_cnt[i]; + /* Up --> Down */ + if ((priv->ar40xx_port_old_link[i] == + AR40XX_PORT_LINK_UP) && + (link == AR40XX_PORT_LINK_DOWN)) { + /* LINK_EN disable(MAC force mode)*/ + reg = AR40XX_REG_PORT_STATUS(i); + ar40xx_rmw(priv, reg, + AR40XX_PORT_AUTO_LINK_EN, 0); + + /* Check queue buffer */ + qm_err_cnt[i] = 0; + ar40xx_get_qm_status(priv, i, &qm_buffer_err); + if (qm_buffer_err) { + priv->ar40xx_port_qm_buf[i] = + AR40XX_QM_NOT_EMPTY; + } else { + u16 phy_val = 0; + + priv->ar40xx_port_qm_buf[i] = + AR40XX_QM_EMPTY; + ar40xx_force_1g_full(priv, i); + /* Ref:QCA8337 Datasheet,Clearing + * MENU_CTRL_EN prevents phy to + * stuck in 100BT mode when + * bringing up the link + */ + ar40xx_phy_dbg_read(priv, i-1, + AR40XX_PHY_DEBUG_0, + &phy_val); + phy_val &= (~AR40XX_PHY_MANU_CTRL_EN); + ar40xx_phy_dbg_write(priv, i-1, + AR40XX_PHY_DEBUG_0, + phy_val); + } + priv->ar40xx_port_old_link[i] = link; + } else if ((priv->ar40xx_port_old_link[i] == + AR40XX_PORT_LINK_DOWN) && + (link == AR40XX_PORT_LINK_UP)) { + /* Down --> Up */ + if (priv->port_link_up[i] < 1) { + ++priv->port_link_up[i]; + } else { + /* Change port status */ + reg = AR40XX_REG_PORT_STATUS(i); + value = ar40xx_read(priv, reg); + priv->port_link_up[i] = 0; + + value &= ~(AR40XX_PORT_DUPLEX | + AR40XX_PORT_SPEED); + value |= speed | (duplex ? BIT(6) : 0); + ar40xx_write(priv, reg, value); + /* clock switch need such time + * to avoid glitch + */ + usleep_range(100, 200); + + value |= AR40XX_PORT_AUTO_LINK_EN; + ar40xx_write(priv, reg, value); + /* HW need such time to make sure link + * stable before enable MAC + */ + usleep_range(100, 200); + + if (speed == AR40XX_PORT_SPEED_100M) { + u16 phy_val = 0; + /* Enable @100M, if down to 10M + * clock will change smoothly + */ + ar40xx_phy_dbg_read(priv, i-1, + 0, + &phy_val); + phy_val |= + AR40XX_PHY_MANU_CTRL_EN; + ar40xx_phy_dbg_write(priv, i-1, + 0, + phy_val); + } + priv->ar40xx_port_old_link[i] = link; + } + } + } + + if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) { + /* Check QM */ + ar40xx_get_qm_status(priv, i, &qm_buffer_err); + if (qm_buffer_err) { + ++qm_err_cnt[i]; + } else { + priv->ar40xx_port_qm_buf[i] = + AR40XX_QM_EMPTY; + qm_err_cnt[i] = 0; + ar40xx_force_1g_full(priv, i); + } + } + } +} + +static void +ar40xx_qm_err_check_work_task(struct work_struct *work) +{ + struct ar40xx_priv *priv = container_of(work, struct ar40xx_priv, + qm_dwork.work); + + mutex_lock(&priv->qm_lock); + + ar40xx_sw_mac_polling_task(priv); + + mutex_unlock(&priv->qm_lock); + + schedule_delayed_work(&priv->qm_dwork, + msecs_to_jiffies(AR40XX_QM_WORK_DELAY)); +} + +static int +ar40xx_qm_err_check_work_start(struct ar40xx_priv *priv) +{ + mutex_init(&priv->qm_lock); + + INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task); + + schedule_delayed_work(&priv->qm_dwork, + msecs_to_jiffies(AR40XX_QM_WORK_DELAY)); + + return 0; +} + +/* End of qm error WAR */ + +static int +ar40xx_vlan_init(struct ar40xx_priv *priv) +{ + int port; + unsigned long bmp; + + /* By default Enable VLAN */ + priv->vlan = 1; + priv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp; + priv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp; + priv->vlan_tagged = priv->cpu_bmp; + bmp = priv->lan_bmp; + for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS) + priv->pvid[port] = AR40XX_LAN_VLAN; + + bmp = priv->wan_bmp; + for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS) + priv->pvid[port] = AR40XX_WAN_VLAN; + + return 0; +} + +static void +ar40xx_mib_work_func(struct work_struct *work) +{ + struct ar40xx_priv *priv; + int err; + + priv = container_of(work, struct ar40xx_priv, mib_work.work); + + mutex_lock(&priv->mib_lock); + + err = ar40xx_mib_capture(priv); + if (err) + goto next_port; + + ar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false); + +next_port: + priv->mib_next_port++; + if (priv->mib_next_port >= priv->dev.ports) + priv->mib_next_port = 0; + + mutex_unlock(&priv->mib_lock); + + schedule_delayed_work(&priv->mib_work, + msecs_to_jiffies(AR40XX_MIB_WORK_DELAY)); +} + +static void +ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members) +{ + u32 t; + u32 egress, ingress; + u32 pvid = priv->vlan_id[priv->pvid[port]]; + + if (priv->vlan) { + egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD; + + ingress = AR40XX_IN_SECURE; + } else { + egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH; + ingress = AR40XX_IN_PORT_ONLY; + } + + t = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S; + t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S; + ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t); + + t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP; + t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S; + + ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t); + + t = members; + t |= AR40XX_PORT_LOOKUP_LEARN; + t |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S; + t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S; + ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t); +} + +static void +ar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val) +{ + if (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1, + AR40XX_VTU_FUNC1_BUSY, 0)) + return; + + if ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD) + ar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val); + + op |= AR40XX_VTU_FUNC1_BUSY; + ar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op); +} + +static void +ar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask) +{ + u32 op; + u32 val; + int i; + + op = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S); + val = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL; + for (i = 0; i < AR40XX_NUM_PORTS; i++) { + u32 mode; + + if ((port_mask & BIT(i)) == 0) + mode = AR40XX_VTU_FUNC0_EG_MODE_NOT; + else if (priv->vlan == 0) + mode = AR40XX_VTU_FUNC0_EG_MODE_KEEP; + else if ((priv->vlan_tagged & BIT(i)) || + (priv->vlan_id[priv->pvid[i]] != vid)) + mode = AR40XX_VTU_FUNC0_EG_MODE_TAG; + else + mode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG; + + val |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i); + } + ar40xx_vtu_op(priv, op, val); +} + +static void +ar40xx_vtu_flush(struct ar40xx_priv *priv) +{ + ar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0); +} + +static int +ar40xx_sw_hw_apply(struct switch_dev *dev) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + u8 portmask[AR40XX_NUM_PORTS]; + int i, j; + + mutex_lock(&priv->reg_mutex); + /* flush all vlan entries */ + ar40xx_vtu_flush(priv); + + memset(portmask, 0, sizeof(portmask)); + if (priv->vlan) { + for (j = 0; j < AR40XX_MAX_VLANS; j++) { + u8 vp = priv->vlan_table[j]; + + if (!vp) + continue; + + for (i = 0; i < dev->ports; i++) { + u8 mask = BIT(i); + + if (vp & mask) + portmask[i] |= vp & ~mask; + } + + ar40xx_vtu_load_vlan(priv, priv->vlan_id[j], + priv->vlan_table[j]); + } + } else { + /* 8021q vlan disabled */ + for (i = 0; i < dev->ports; i++) { + if (i == AR40XX_PORT_CPU) + continue; + + portmask[i] = BIT(AR40XX_PORT_CPU); + portmask[AR40XX_PORT_CPU] |= BIT(i); + } + } + + /* update the port destination mask registers and tag settings */ + for (i = 0; i < dev->ports; i++) + ar40xx_setup_port(priv, i, portmask[i]); + + ar40xx_set_mirror_regs(priv); + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int +ar40xx_sw_reset_switch(struct switch_dev *dev) +{ + struct ar40xx_priv *priv = swdev_to_ar40xx(dev); + int i, rv; + + mutex_lock(&priv->reg_mutex); + memset(&priv->vlan, 0, sizeof(struct ar40xx_priv) - + offsetof(struct ar40xx_priv, vlan)); + + for (i = 0; i < AR40XX_MAX_VLANS; i++) + priv->vlan_id[i] = i; + + ar40xx_vlan_init(priv); + + priv->mirror_rx = false; + priv->mirror_tx = false; + priv->source_port = 0; + priv->monitor_port = 0; + + mutex_unlock(&priv->reg_mutex); + + rv = ar40xx_sw_hw_apply(dev); + return rv; +} + +static int +ar40xx_start(struct ar40xx_priv *priv) +{ + int ret; + + ret = ar40xx_hw_init(priv); + if (ret) + return ret; + + ret = ar40xx_sw_reset_switch(&priv->dev); + if (ret) + return ret; + + /* at last, setup cpu port */ + ret = ar40xx_cpuport_setup(priv); + if (ret) + return ret; + + schedule_delayed_work(&priv->mib_work, + msecs_to_jiffies(AR40XX_MIB_WORK_DELAY)); + + ar40xx_qm_err_check_work_start(priv); + + return 0; +} + +static const struct switch_dev_ops ar40xx_sw_ops = { + .attr_global = { + .attr = ar40xx_sw_attr_globals, + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals), + }, + .attr_port = { + .attr = ar40xx_sw_attr_port, + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_port), + }, + .attr_vlan = { + .attr = ar40xx_sw_attr_vlan, + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan), + }, + .get_port_pvid = ar40xx_sw_get_pvid, + .set_port_pvid = ar40xx_sw_set_pvid, + .get_vlan_ports = ar40xx_sw_get_ports, + .set_vlan_ports = ar40xx_sw_set_ports, + .apply_config = ar40xx_sw_hw_apply, + .reset_switch = ar40xx_sw_reset_switch, + .get_port_link = ar40xx_sw_get_port_link, +}; + +/* Platform driver probe function */ + +static int ar40xx_probe(struct platform_device *pdev) +{ + struct device_node *switch_node; + struct device_node *psgmii_node; + struct device_node *mdio_node; + const __be32 *mac_mode; + struct clk *ess_clk; + struct switch_dev *swdev; + struct ar40xx_priv *priv; + u32 len; + u32 num_mibs; + struct resource psgmii_base = {0}; + struct resource switch_base = {0}; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + ar40xx_priv = priv; + + switch_node = of_node_get(pdev->dev.of_node); + if (of_address_to_resource(switch_node, 0, &switch_base) != 0) + return -EIO; + + priv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base); + if (IS_ERR(priv->hw_addr)) { + dev_err(&pdev->dev, "Failed to ioremap switch_base!\n"); + return PTR_ERR(priv->hw_addr); + } + + /*psgmii dts get*/ + psgmii_node = of_find_node_by_name(NULL, "ess-psgmii"); + if (!psgmii_node) { + dev_err(&pdev->dev, "Failed to find ess-psgmii node!\n"); + return -EINVAL; + } + + if (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0) + return -EIO; + + priv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base); + if (IS_ERR(priv->psgmii_hw_addr)) { + dev_err(&pdev->dev, "psgmii ioremap fail!\n"); + return PTR_ERR(priv->psgmii_hw_addr); + } + + mac_mode = of_get_property(switch_node, "switch_mac_mode", &len); + if (!mac_mode) { + dev_err(&pdev->dev, "Failed to read switch_mac_mode\n"); + return -EINVAL; + } + priv->mac_mode = be32_to_cpup(mac_mode); + + ess_clk = of_clk_get_by_name(switch_node, "ess_clk"); + if (ess_clk) + clk_prepare_enable(ess_clk); + + priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst"); + if (IS_ERR(priv->ess_rst)) { + dev_err(&pdev->dev, "Failed to get ess_rst control!\n"); + return PTR_ERR(priv->ess_rst); + } + + if (of_property_read_u32(switch_node, "switch_cpu_bmp", + &priv->cpu_bmp) || + of_property_read_u32(switch_node, "switch_lan_bmp", + &priv->lan_bmp) || + of_property_read_u32(switch_node, "switch_wan_bmp", + &priv->wan_bmp)) { + dev_err(&pdev->dev, "Failed to read port properties\n"); + return -EIO; + } + + mutex_init(&priv->reg_mutex); + mutex_init(&priv->mib_lock); + INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func); + + /* register switch */ + swdev = &priv->dev; + + mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq4019-mdio"); + if (!mdio_node) { + dev_err(&pdev->dev, "Probe failed - Cannot find mdio node by phandle!\n"); + ret = -ENODEV; + goto err_missing_phy; + } + + priv->mii_bus = of_mdio_find_bus(mdio_node); + + if (priv->mii_bus == NULL) { + dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n"); + ret = -ENODEV; + goto err_missing_phy; + } + + swdev->alias = dev_name(&priv->mii_bus->dev); + + swdev->cpu_port = AR40XX_PORT_CPU; + swdev->name = "QCA AR40xx"; + swdev->vlans = AR40XX_MAX_VLANS; + swdev->ports = AR40XX_NUM_PORTS; + swdev->ops = &ar40xx_sw_ops; + ret = register_switch(swdev, NULL); + if (ret < 0) { + dev_err(&pdev->dev, "Switch registration failed!\n"); + return ret; + } + + num_mibs = ARRAY_SIZE(ar40xx_mibs); + len = priv->dev.ports * num_mibs * + sizeof(*priv->mib_stats); + priv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!priv->mib_stats) { + ret = -ENOMEM; + goto err_unregister_switch; + } + + ar40xx_start(priv); + + return 0; + +err_unregister_switch: + unregister_switch(&priv->dev); +err_missing_phy: + platform_set_drvdata(pdev, NULL); + return ret; +} + +static int ar40xx_remove(struct platform_device *pdev) +{ + struct ar40xx_priv *priv = platform_get_drvdata(pdev); + + cancel_delayed_work_sync(&priv->qm_dwork); + cancel_delayed_work_sync(&priv->mib_work); + + unregister_switch(&priv->dev); + + return 0; +} + +static const struct of_device_id ar40xx_of_mtable[] = { + {.compatible = "qcom,ess-switch" }, + {} +}; + +struct platform_driver ar40xx_drv = { + .probe = ar40xx_probe, + .remove = ar40xx_remove, + .driver = { + .name = "ar40xx", + .of_match_table = ar40xx_of_mtable, + }, +}; + +module_platform_driver(ar40xx_drv); + +MODULE_DESCRIPTION("IPQ40XX ESS driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.h b/target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.h new file mode 100644 index 0000000000..7ba40ccf75 --- /dev/null +++ b/target/linux/ipq40xx/files-5.15/drivers/net/mdio/ar40xx.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + #ifndef __AR40XX_H +#define __AR40XX_H + +#define AR40XX_MAX_VLANS 128 +#define AR40XX_NUM_PORTS 6 +#define AR40XX_NUM_PHYS 5 + +#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) + +struct ar40xx_priv { + struct switch_dev dev; + + u8 __iomem *hw_addr; + u8 __iomem *psgmii_hw_addr; + u32 mac_mode; + struct reset_control *ess_rst; + u32 cpu_bmp; + u32 lan_bmp; + u32 wan_bmp; + + struct mii_bus *mii_bus; + struct phy_device *phy; + + /* mutex for qm task */ + struct mutex qm_lock; + struct delayed_work qm_dwork; + u32 port_link_up[AR40XX_NUM_PORTS]; + u32 ar40xx_port_old_link[AR40XX_NUM_PORTS]; + u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS]; + + u32 phy_t_status; + + /* mutex for switch reg access */ + struct mutex reg_mutex; + + /* mutex for mib task */ + struct mutex mib_lock; + struct delayed_work mib_work; + int mib_next_port; + u64 *mib_stats; + + char buf[2048]; + + /* all fields below will be cleared on reset */ + bool vlan; + u16 vlan_id[AR40XX_MAX_VLANS]; + u8 vlan_table[AR40XX_MAX_VLANS]; + u8 vlan_tagged; + u16 pvid[AR40XX_NUM_PORTS]; + + /* mirror */ + bool mirror_rx; + bool mirror_tx; + int source_port; + int monitor_port; +}; + +#define AR40XX_PORT_LINK_UP 1 +#define AR40XX_PORT_LINK_DOWN 0 +#define AR40XX_QM_NOT_EMPTY 1 +#define AR40XX_QM_EMPTY 0 + +#define AR40XX_LAN_VLAN 1 +#define AR40XX_WAN_VLAN 2 + +enum ar40xx_port_wrapper_cfg { + PORT_WRAPPER_PSGMII = 0, +}; + +struct ar40xx_mib_desc { + u32 size; + u32 offset; + const char *name; +}; + +#define AR40XX_PORT_CPU 0 + +#define AR40XX_PSGMII_MODE_CONTROL 0x1b4 +#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0) + +#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288 + +#define AR40XX_MII_ATH_MMD_ADDR 0x0d +#define AR40XX_MII_ATH_MMD_DATA 0x0e +#define AR40XX_MII_ATH_DBG_ADDR 0x1d +#define AR40XX_MII_ATH_DBG_DATA 0x1e + +#define AR40XX_STATS_RXBROAD 0x00 +#define AR40XX_STATS_RXPAUSE 0x04 +#define AR40XX_STATS_RXMULTI 0x08 +#define AR40XX_STATS_RXFCSERR 0x0c +#define AR40XX_STATS_RXALIGNERR 0x10 +#define AR40XX_STATS_RXRUNT 0x14 +#define AR40XX_STATS_RXFRAGMENT 0x18 +#define AR40XX_STATS_RX64BYTE 0x1c +#define AR40XX_STATS_RX128BYTE 0x20 +#define AR40XX_STATS_RX256BYTE 0x24 +#define AR40XX_STATS_RX512BYTE 0x28 +#define AR40XX_STATS_RX1024BYTE 0x2c +#define AR40XX_STATS_RX1518BYTE 0x30 +#define AR40XX_STATS_RXMAXBYTE 0x34 +#define AR40XX_STATS_RXTOOLONG 0x38 +#define AR40XX_STATS_RXGOODBYTE 0x3c +#define AR40XX_STATS_RXBADBYTE 0x44 +#define AR40XX_STATS_RXOVERFLOW 0x4c +#define AR40XX_STATS_FILTERED 0x50 +#define AR40XX_STATS_TXBROAD 0x54 +#define AR40XX_STATS_TXPAUSE 0x58 +#define AR40XX_STATS_TXMULTI 0x5c +#define AR40XX_STATS_TXUNDERRUN 0x60 +#define AR40XX_STATS_TX64BYTE 0x64 +#define AR40XX_STATS_TX128BYTE 0x68 +#define AR40XX_STATS_TX256BYTE 0x6c +#define AR40XX_STATS_TX512BYTE 0x70 +#define AR40XX_STATS_TX1024BYTE 0x74 +#define AR40XX_STATS_TX1518BYTE 0x78 +#define AR40XX_STATS_TXMAXBYTE 0x7c +#define AR40XX_STATS_TXOVERSIZE 0x80 +#define AR40XX_STATS_TXBYTE 0x84 +#define AR40XX_STATS_TXCOLLISION 0x8c +#define AR40XX_STATS_TXABORTCOL 0x90 +#define AR40XX_STATS_TXMULTICOL 0x94 +#define AR40XX_STATS_TXSINGLECOL 0x98 +#define AR40XX_STATS_TXEXCDEFER 0x9c +#define AR40XX_STATS_TXDEFER 0xa0 +#define AR40XX_STATS_TXLATECOL 0xa4 + +#define AR40XX_REG_MODULE_EN 0x030 +#define AR40XX_MODULE_EN_MIB BIT(0) + +#define AR40XX_REG_MIB_FUNC 0x034 +#define AR40XX_MIB_BUSY BIT(17) +#define AR40XX_MIB_CPU_KEEP BIT(20) +#define AR40XX_MIB_FUNC BITS(24, 3) +#define AR40XX_MIB_FUNC_S 24 +#define AR40XX_MIB_FUNC_NO_OP 0x0 +#define AR40XX_MIB_FUNC_FLUSH 0x1 + +#define AR40XX_ESS_SERVICE_TAG 0x48 +#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17) + +#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) +#define AR40XX_PORT_SPEED BITS(0, 2) +#define AR40XX_PORT_STATUS_SPEED_S 0 +#define AR40XX_PORT_TX_EN BIT(2) +#define AR40XX_PORT_RX_EN BIT(3) +#define AR40XX_PORT_STATUS_TXFLOW BIT(4) +#define AR40XX_PORT_STATUS_RXFLOW BIT(5) +#define AR40XX_PORT_DUPLEX BIT(6) +#define AR40XX_PORT_TXHALF_FLOW BIT(7) +#define AR40XX_PORT_STATUS_LINK_UP BIT(8) +#define AR40XX_PORT_AUTO_LINK_EN BIT(9) +#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12) + +#define AR40XX_REG_MAX_FRAME_SIZE 0x078 +#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14) + +#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) + +#define AR40XX_REG_EEE_CTRL 0x100 +#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) + +#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) +#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12) +#define AR40XX_PORT_VLAN0_DEF_SVID_S 0 +#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12) +#define AR40XX_PORT_VLAN0_DEF_CVID_S 16 + +#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) +#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9) +#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7) +#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6) +#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2) +#define AR40XX_PORT_VLAN1_OUT_MODE_S 12 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1 +#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3 + +#define AR40XX_REG_VTU_FUNC0 0x0610 +#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14) +#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) +#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0 +#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1 +#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2 +#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3 +#define AR40XX_VTU_FUNC0_IVL BIT(19) +#define AR40XX_VTU_FUNC0_VALID BIT(20) + +#define AR40XX_REG_VTU_FUNC1 0x0614 +#define AR40XX_VTU_FUNC1_OP BITS(0, 3) +#define AR40XX_VTU_FUNC1_OP_NOOP 0 +#define AR40XX_VTU_FUNC1_OP_FLUSH 1 +#define AR40XX_VTU_FUNC1_OP_LOAD 2 +#define AR40XX_VTU_FUNC1_OP_PURGE 3 +#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4 +#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5 +#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6 +#define AR40XX_VTU_FUNC1_FULL BIT(4) +#define AR40XX_VTU_FUNC1_PORT BIT(8, 4) +#define AR40XX_VTU_FUNC1_PORT_S 8 +#define AR40XX_VTU_FUNC1_VID BIT(16, 12) +#define AR40XX_VTU_FUNC1_VID_S 16 +#define AR40XX_VTU_FUNC1_BUSY BIT(31) + +#define AR40XX_REG_FWD_CTRL0 0x620 +#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10) +#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4) +#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4 + +#define AR40XX_REG_FWD_CTRL1 0x624 +#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7) +#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0 +#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7) +#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8 +#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7) +#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16 +#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7) +#define AR40XX_FWD_CTRL1_IGMP_S 24 + +#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) +#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7) +#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2) +#define AR40XX_PORT_LOOKUP_IN_MODE_S 8 +#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3) +#define AR40XX_PORT_LOOKUP_STATE_S 16 +#define AR40XX_PORT_LOOKUP_LEARN BIT(20) +#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21) +#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25) + +#define AR40XX_REG_ATU_FUNC 0x60c +#define AR40XX_ATU_FUNC_OP BITS(0, 4) +#define AR40XX_ATU_FUNC_OP_NOOP 0x0 +#define AR40XX_ATU_FUNC_OP_FLUSH 0x1 +#define AR40XX_ATU_FUNC_OP_LOAD 0x2 +#define AR40XX_ATU_FUNC_OP_PURGE 0x3 +#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4 +#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5 +#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6 +#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7 +#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8 +#define AR40XX_ATU_FUNC_BUSY BIT(31) + +#define AR40XX_REG_QM_DEBUG_ADDR 0x820 +#define AR40XX_REG_QM_DEBUG_VALUE 0x824 +#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d +#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e + +#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) + +#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4) +#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60 +#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90 + +#define AR40XX_PHY_DEBUG_0 0 +#define AR40XX_PHY_MANU_CTRL_EN BIT(12) + +#define AR40XX_PHY_DEBUG_2 2 + +#define AR40XX_PHY_SPEC_STATUS 0x11 +#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10) +#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13) +#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2) + +/* port forwarding state */ +enum { + AR40XX_PORT_STATE_DISABLED = 0, + AR40XX_PORT_STATE_BLOCK = 1, + AR40XX_PORT_STATE_LISTEN = 2, + AR40XX_PORT_STATE_LEARN = 3, + AR40XX_PORT_STATE_FORWARD = 4 +}; + +/* ingress 802.1q mode */ +enum { + AR40XX_IN_PORT_ONLY = 0, + AR40XX_IN_PORT_FALLBACK = 1, + AR40XX_IN_VLAN_ONLY = 2, + AR40XX_IN_SECURE = 3 +}; + +/* egress 802.1q mode */ +enum { + AR40XX_OUT_KEEP = 0, + AR40XX_OUT_STRIP_VLAN = 1, + AR40XX_OUT_ADD_VLAN = 2 +}; + +/* port speed */ +enum { + AR40XX_PORT_SPEED_10M = 0, + AR40XX_PORT_SPEED_100M = 1, + AR40XX_PORT_SPEED_1000M = 2, + AR40XX_PORT_SPEED_ERR = 3, +}; + +#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */ + +#define AR40XX_QM_WORK_DELAY 100 + +#define AR40XX_MIB_FUNC_CAPTURE 0x3 + +#define AR40XX_REG_PORT_STATS_START 0x1000 +#define AR40XX_REG_PORT_STATS_LEN 0x100 + +#define AR40XX_PORTS_ALL 0x3f + +#define AR40XX_PSGMII_ID 5 +#define AR40XX_PSGMII_CALB_NUM 100 +#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d +#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c +#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a +#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380 +#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280 +#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a +#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb +#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a +#define AR40XX_MALIBU_PHY_LAST_ADDR 4 + +static inline struct ar40xx_priv * +swdev_to_ar40xx(struct switch_dev *swdev) +{ + return container_of(swdev, struct ar40xx_priv, dev); +} + +#endif diff --git a/target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch b/target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch new file mode 100644 index 0000000000..890611387c --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch @@ -0,0 +1,99 @@ +From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 9 Sep 2020 18:38:31 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes + +Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI. + +Signed-off-by: John Crispin +Signed-off-by: Robert Marko +Cc: Luka Perkov +Reviewed-by: Vinod Koul +Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr +Signed-off-by: Bjorn Andersson +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++ + 1 file changed, 74 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -605,5 +605,79 @@ + reg = <4>; + }; + }; ++ ++ usb3_ss_phy: ssphy@9a000 { ++ compatible = "qcom,usb-ss-ipq4019-phy"; ++ #phy-cells = <0>; ++ reg = <0x9a000 0x800>; ++ reg-names = "phy_base"; ++ resets = <&gcc USB3_UNIPHY_PHY_ARES>; ++ reset-names = "por_rst"; ++ status = "disabled"; ++ }; ++ ++ usb3_hs_phy: hsphy@a6000 { ++ compatible = "qcom,usb-hs-ipq4019-phy"; ++ #phy-cells = <0>; ++ reg = <0xa6000 0x40>; ++ reg-names = "phy_base"; ++ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; ++ reset-names = "por_rst", "srif_rst"; ++ status = "disabled"; ++ }; ++ ++ usb3: usb3@8af8800 { ++ compatible = "qcom,dwc3"; ++ reg = <0x8af8800 0x100>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&gcc GCC_USB3_MASTER_CLK>, ++ <&gcc GCC_USB3_SLEEP_CLK>, ++ <&gcc GCC_USB3_MOCK_UTMI_CLK>; ++ clock-names = "master", "sleep", "mock_utmi"; ++ ranges; ++ status = "disabled"; ++ ++ dwc3@8a00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x8a00000 0xf8000>; ++ interrupts = ; ++ phys = <&usb3_hs_phy>, <&usb3_ss_phy>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ dr_mode = "host"; ++ }; ++ }; ++ ++ usb2_hs_phy: hsphy@a8000 { ++ compatible = "qcom,usb-hs-ipq4019-phy"; ++ #phy-cells = <0>; ++ reg = <0xa8000 0x40>; ++ reg-names = "phy_base"; ++ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; ++ reset-names = "por_rst", "srif_rst"; ++ status = "disabled"; ++ }; ++ ++ usb2: usb2@60f8800 { ++ compatible = "qcom,dwc3"; ++ reg = <0x60f8800 0x100>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&gcc GCC_USB2_MASTER_CLK>, ++ <&gcc GCC_USB2_SLEEP_CLK>, ++ <&gcc GCC_USB2_MOCK_UTMI_CLK>; ++ clock-names = "master", "sleep", "mock_utmi"; ++ ranges; ++ status = "disabled"; ++ ++ dwc3@6000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x6000000 0xf8000>; ++ interrupts = ; ++ phys = <&usb2_hs_phy>; ++ phy-names = "usb2-phy"; ++ dr_mode = "host"; ++ }; ++ }; + }; + }; diff --git a/target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch b/target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch new file mode 100644 index 0000000000..d623a9c7b3 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch @@ -0,0 +1,44 @@ +From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 9 Sep 2020 21:56:37 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels + +Lets add labels to more commonly used nodes for easier modification in board DTS files. + +Signed-off-by: Robert Marko +Cc: Luka Perkov +Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr +Signed-off-by: Bjorn Andersson +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -190,7 +190,7 @@ + reg = <0x1800000 0x60000>; + }; + +- rng@22000 { ++ prng: rng@22000 { + compatible = "qcom,prng"; + reg = <0x22000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; +@@ -300,7 +300,7 @@ + status = "disabled"; + }; + +- crypto@8e3a000 { ++ crypto: crypto@8e3a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x08e3a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, +@@ -386,7 +386,7 @@ + dma-names = "rx", "tx"; + }; + +- watchdog@b017000 { ++ watchdog: watchdog@b017000 { + compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; + reg = <0xb017000 0x40>; + clocks = <&sleep_clk>; diff --git a/target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch b/target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch new file mode 100644 index 0000000000..1d93fb800a --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch @@ -0,0 +1,35 @@ +From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 7 Sep 2020 12:19:37 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node + +Since we now have driver for the SDHCI VQMMC LDO needed +for I/0 voltage levels lets introduce the necessary node for it. + +Signed-off-by: Robert Marko +Cc: Luka Perkov +Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr +Signed-off-by: Bjorn Andersson +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -209,6 +209,16 @@ + interrupts = ; + }; + ++ vqmmc: regulator@1948000 { ++ compatible = "qcom,vqmmc-ipq4019-regulator"; ++ reg = <0x01948000 0x4>; ++ regulator-name = "vqmmc"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ status = "disabled"; ++ }; ++ + sdhci: sdhci@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7824900 0x11c>, <0x7824000 0x800>; diff --git a/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch b/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch new file mode 100644 index 0000000000..25a2020bd2 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch @@ -0,0 +1,115 @@ +From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Sun, 11 Mar 2018 14:41:31 +0100 +Subject: [PATCH 2/2] clk: fix apss cpu overclocking + +There's an interaction issue between the clk changes:" +clk: qcom: ipq4019: Add the apss cpu pll divider clock node +clk: qcom: ipq4019: remove fixed clocks and add pll clocks +" and the cpufreq-dt. + +cpufreq-dt is now spamming the kernel-log with the following: + +[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP +for freq 761142857 (-34) + +This only happens on certain devices like the Compex WPJ428 +and AVM FritzBox!4040. However, other devices like the Asus +RT-AC58U and Meraki MR33 work just fine. + +The issue stem from the fact that all higher CPU-Clocks +are achieved by switching the clock-parent to the P_DDRPLLAPSS +(ddrpllapss). Which is set by Qualcomm's proprietary bootcode +as part of the DDR calibration. + +For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked +at round 533 MHz (ddrpllsdcc = 190285714 Hz). + +whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is +clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz). + +This patch attempts to fix the issue by modifying +clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate() +to use a new qcom_find_freq_close() function, which returns the closest +matching frequency, instead of the next higher. This way, the SoC in +the FB4040 (with its max clock speed of 710.4 MHz) will no longer +try to overclock to 761 MHz. + +Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node") +Signed-off-by: Christian Lamparter +Signed-off-by: John Crispin +--- + drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++--- + 1 file changed, 31 insertions(+), 3 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq4019.c ++++ b/drivers/clk/qcom/gcc-ipq4019.c +@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe + .reg = 0x2f020, + }; + ++ ++const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f, ++ unsigned long rate) ++{ ++ const struct freq_tbl *last = NULL; ++ ++ for ( ; f->freq; f++) { ++ if (rate == f->freq) ++ return f; ++ ++ if (f->freq > rate) { ++ if (!last || ++ (f->freq - rate) < (rate - last->freq)) ++ return f; ++ else ++ return last; ++ } ++ last = f; ++ } ++ ++ return last; ++} ++ + /* + * Round rate function for APSS CPU PLL Clock divider. + * It looks up the frequency table and returns the next higher frequency +@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc + struct clk_hw *p_hw; + const struct freq_tbl *f; + +- f = qcom_find_freq(pll->freq_tbl, rate); ++ f = qcom_find_freq_close(pll->freq_tbl, rate); + if (!f) + return -EINVAL; + +@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c + u32 mask; + int ret; + +- f = qcom_find_freq(pll->freq_tbl, rate); ++ f = qcom_find_freq_close(pll->freq_tbl, rate); + if (!f) + return -EINVAL; + +@@ -1305,6 +1328,7 @@ static unsigned long + clk_cpu_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { ++ const struct freq_tbl *f; + struct clk_fepll *pll = to_clk_fepll(hw); + u32 cdiv, pre_div; + u64 rate; +@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h + rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; + do_div(rate, pre_div); + +- return rate; ++ f = qcom_find_freq_close(pll->freq_tbl, rate); ++ if (!f) ++ return rate; ++ ++ return f->freq; + }; + + static const struct clk_ops clk_regmap_cpu_div_ops = { diff --git a/target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch b/target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch new file mode 100644 index 0000000000..7a304f69ca --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch @@ -0,0 +1,26 @@ +From a63c7162a1dae9f1185897641dc3e47e295563d6 Mon Sep 17 00:00:00 2001 +From: Pavel Kubelun +Date: Mon, 6 May 2019 20:55:16 +0300 +Subject: [PATCH] ARM: dts: qcom: ipq4019: fix sleep clock + +It seems like sleep_clk was copied from ipq806x. +Fix ipq40xx sleep_clk to the value QSDK defines. + +Link: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?id=d92ec59973484acc86dd24b67f10f8911b4b4b7d +Link: https://patchwork.kernel.org/comment/22721613/ +Suggested-by: Bjorn Andersson [clock-output-names] +Signed-off-by: Pavel Kubelun +Signed-off-by: Christian Lamparter [just fixed the value] +--- +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -142,7 +142,8 @@ + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; +- clock-frequency = <32768>; ++ clock-frequency = <32000>; ++ clock-output-names = "gcc_sleep_clk_src"; + #clock-cells = <0>; + }; + diff --git a/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch b/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch new file mode 100644 index 0000000000..4297f32e05 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch @@ -0,0 +1,52 @@ +From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001 +From: Ram Chandra Jangir +Date: Tue, 28 Mar 2017 22:35:33 +0530 +Subject: [PATCH] clk: qcom: ipq4019: add ess reset + +Added the ESS reset in IPQ4019 GCC. + +Signed-off-by: Ram Chandra Jangir +--- + drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++ + include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++ + 2 files changed, 22 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq4019.c ++++ b/drivers/clk/qcom/gcc-ipq4019.c +@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i + [GCC_TCSR_BCR] = {0x22000, 0}, + [GCC_MPM_BCR] = {0x24000, 0}, + [GCC_SPDM_BCR] = {0x25000, 0}, ++ [ESS_MAC1_ARES] = {0x1200C, 0}, ++ [ESS_MAC2_ARES] = {0x1200C, 1}, ++ [ESS_MAC3_ARES] = {0x1200C, 2}, ++ [ESS_MAC4_ARES] = {0x1200C, 3}, ++ [ESS_MAC5_ARES] = {0x1200C, 4}, ++ [ESS_PSGMII_ARES] = {0x1200C, 5}, ++ [ESS_MAC1_CLK_DIS] = {0x1200C, 8}, ++ [ESS_MAC2_CLK_DIS] = {0x1200C, 9}, ++ [ESS_MAC3_CLK_DIS] = {0x1200C, 10}, ++ [ESS_MAC4_CLK_DIS] = {0x1200C, 11}, ++ [ESS_MAC5_CLK_DIS] = {0x1200C, 12}, + }; + + static const struct regmap_config gcc_ipq4019_regmap_config = { +--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h +@@ -165,5 +165,16 @@ + #define GCC_QDSS_BCR 69 + #define GCC_MPM_BCR 70 + #define GCC_SPDM_BCR 71 ++#define ESS_MAC1_ARES 72 ++#define ESS_MAC2_ARES 73 ++#define ESS_MAC3_ARES 74 ++#define ESS_MAC4_ARES 75 ++#define ESS_MAC5_ARES 76 ++#define ESS_PSGMII_ARES 77 ++#define ESS_MAC1_CLK_DIS 78 ++#define ESS_MAC2_CLK_DIS 79 ++#define ESS_MAC3_CLK_DIS 80 ++#define ESS_MAC4_CLK_DIS 81 ++#define ESS_MAC5_CLK_DIS 82 + + #endif diff --git a/target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch b/target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch new file mode 100644 index 0000000000..99e33632c4 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch @@ -0,0 +1,48 @@ +From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 30 Oct 2020 13:36:31 +0100 +Subject: [PATCH] arm: compressed: add appended DTB section + +This adds a appended_dtb section to the ARM decompressor +linker script. + +This allows using the existing ARM zImage appended DTB support for +appending a DTB to the raw ELF kernel. + +Its size is set to 1MB max to match the zImage appended DTB size limit. + +To use it to pass the DTB to the kernel, objcopy is used: + +objcopy --set-section-flags=.appended_dtb=alloc,contents \ + --update-section=.appended_dtb=.dtb vmlinux + +This is based off the following patch: +https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69 + +Signed-off-by: Robert Marko +--- + arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/compressed/vmlinux.lds.S ++++ b/arch/arm/boot/compressed/vmlinux.lds.S +@@ -101,6 +101,13 @@ SECTIONS + + _edata = .; + ++ .appended_dtb : { ++ /* leave space for appended DTB */ ++ . += 0x100000; ++ } ++ ++ _edata_dtb = .; ++ + /* + * The image_end section appears after any additional loadable sections + * that the linker may decide to insert in the binary image. Having +@@ -138,4 +145,4 @@ SECTIONS + + ARM_ASSERTS + } +-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect"); ++ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect"); diff --git a/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch b/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch new file mode 100644 index 0000000000..1aa5a9f386 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch @@ -0,0 +1,66 @@ +From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001 +From: John Thomson +Date: Fri, 23 Oct 2020 19:42:36 +1000 +Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot + +For IPQ40XX systems where the SoC watchdog is activated before linux, +the watchdog timer may be too small for linux to finish uncompress, +boot, and watchdog management start. +If the watchdog is enabled, set the timeout for it to 30 seconds. +The functionality and offsets were copied from: +drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start +The watchdog memory address was taken from: +arch/arm/boot/dts/qcom-ipq4019.dtsi + +This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's +RouterBoot bootloader. + +Signed-off-by: John Thomson +--- + arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +--- a/arch/arm/boot/compressed/head.S ++++ b/arch/arm/boot/compressed/head.S +@@ -602,6 +602,41 @@ not_relocated: mov r0, #0 + bic r4, r4, #1 + blne cache_on + ++/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds ++ * if it is enabled, so that there is time for kernel ++ * to decompress, boot, and take over the watchdog. ++ * data and functionality from drivers/watchdog/qcom-wdt.c ++ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi ++ */ ++#ifdef CONFIG_ARCH_IPQ40XX ++watchdog_set: ++ /* offsets: ++ * 0x04 reset (=1 resets countdown) ++ * 0x08 enable (=0 disables) ++ * 0x0c status (=1 when SoC was reset by watchdog) ++ * 0x10 bark (=timeout warning in ticks) ++ * 0x14 bite (=timeout reset in ticks) ++ * clock rate is 1<<15 hertz ++ */ ++ .equ watchdog, 0x0b017000 @Store watchdog base address ++ movw r0, #:lower16:watchdog ++ movt r0, #:upper16:watchdog ++ ldr r1, [r0, #0x08] @Get enabled? ++ cmp r1, #1 @If not enabled, do not change ++ bne watchdog_finished ++ mov r1, #0 ++ str r1, [r0, #0x08] @Disable the watchdog ++ mov r1, #1 ++ str r1, [r0, #0x04] @Pet the watchdog ++ mov r1, #30 @30 seconds timeout ++ lsl r1, r1, #15 @converted to ticks ++ str r1, [r0, #0x10] @Set the bark timeout ++ str r1, [r0, #0x14] @Set the bite timeout ++ mov r1, #1 ++ str r1, [r0, #0x08] @Enable the watchdog ++watchdog_finished: ++#endif /* CONFIG_ARCH_IPQ40XX */ ++ + /* + * The C runtime environment should now be setup sufficiently. + * Set up some pointers, and start decompressing. diff --git a/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch b/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch new file mode 100644 index 0000000000..fd46d54916 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch @@ -0,0 +1,24 @@ +From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 14 Dec 2020 13:35:35 +0100 +Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock + +When using sdhci_msm_set_clock clock setting will fail, so lets +use the generic sdhci_set_clock. + +Signed-off-by: Robert Marko +--- + drivers/mmc/host/sdhci-msm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mmc/host/sdhci-msm.c ++++ b/drivers/mmc/host/sdhci-msm.c +@@ -2191,7 +2191,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat + + static const struct sdhci_ops sdhci_msm_ops = { + .reset = sdhci_msm_reset, +- .set_clock = sdhci_msm_set_clock, ++ .set_clock = sdhci_set_clock, + .get_min_clock = sdhci_msm_get_min_clock, + .get_max_clock = sdhci_msm_get_max_clock, + .set_bus_width = sdhci_set_bus_width, diff --git a/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch b/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch new file mode 100644 index 0000000000..eb474500b1 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch @@ -0,0 +1,47 @@ +--- a/drivers/firmware/qcom_scm.c ++++ b/drivers/firmware/qcom_scm.c +@@ -404,6 +404,20 @@ static int __qcom_scm_set_dload_mode(str + return qcom_scm_call_atomic(__scm->dev, &desc, NULL); + } + ++static int __qcom_scm_disable_sdi(struct device *dev) ++{ ++ struct qcom_scm_desc desc = { ++ .svc = QCOM_SCM_SVC_BOOT, ++ .cmd = QCOM_SCM_BOOT_CONFIG_SDI, ++ .arginfo = QCOM_SCM_ARGS(2), ++ .args[0] = 1 /* 1: disable watchdog debug */, ++ .args[1] = 0 /* 0: disable SDI */, ++ .owner = ARM_SMCCC_OWNER_SIP, ++ }; ++ ++ return qcom_scm_call(__scm->dev, &desc, NULL); ++} ++ + static void qcom_scm_set_download_mode(bool enable) + { + bool avail; +@@ -1256,6 +1270,13 @@ static int qcom_scm_probe(struct platfor + if (download_mode) + qcom_scm_set_download_mode(true); + ++ /* ++ * Factory firmware leaves SDI (a debug interface), which prevents ++ * clean reboot. ++ */ ++ if (of_machine_is_compatible("google,wifi")) ++ __qcom_scm_disable_sdi(__scm->dev); ++ + return 0; + } + +--- a/drivers/firmware/qcom_scm.h ++++ b/drivers/firmware/qcom_scm.h +@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device + #define QCOM_SCM_SVC_BOOT 0x01 + #define QCOM_SCM_BOOT_SET_ADDR 0x01 + #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 ++#define QCOM_SCM_BOOT_CONFIG_SDI 0x09 + #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 + #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a + #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 diff --git a/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch b/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch new file mode 100644 index 0000000000..accf3e9686 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch @@ -0,0 +1,121 @@ +--- a/drivers/firmware/qcom_scm-legacy.c ++++ b/drivers/firmware/qcom_scm-legacy.c +@@ -13,6 +13,9 @@ + #include + #include + ++#include ++#include ++ + #include "qcom_scm.h" + + static DEFINE_MUTEX(qcom_scm_lock); +@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct + } while (res->a0 == QCOM_SCM_INTERRUPTED); + } + ++static void qcom_scm_inv_range(unsigned long start, unsigned long end) ++{ ++ u32 cacheline_size, ctr; ++ ++ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); ++ cacheline_size = 4 << ((ctr >> 16) & 0xf); ++ ++ start = round_down(start, cacheline_size); ++ end = round_up(end, cacheline_size); ++ outer_inv_range(start, end); ++ while (start < end) { ++ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) ++ : "memory"); ++ start += cacheline_size; ++ } ++ dsb(); ++ isb(); ++} ++ + /** + * qcom_scm_call() - Sends a command to the SCM and waits for the command to + * finish processing. +@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev, + + rsp = scm_legacy_command_to_response(cmd); + +- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE); +- if (dma_mapping_error(dev, cmd_phys)) { +- kfree(cmd); +- return -ENOMEM; ++ if (dev) { ++ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE); ++ if (dma_mapping_error(dev, cmd_phys)) { ++ kfree(cmd); ++ return -ENOMEM; ++ } ++ } else { ++ cmd_phys = virt_to_phys(cmd); ++ __cpuc_flush_dcache_area(cmd, alloc_len); ++ outer_flush_range(cmd_phys, cmd_phys + alloc_len); + } + + smc.args[0] = 1; +@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev, + goto out; + + do { +- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len, +- sizeof(*rsp), DMA_FROM_DEVICE); ++ if (dev) { ++ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + ++ cmd_len, sizeof(*rsp), ++ DMA_FROM_DEVICE); ++ } else { ++ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + ++ cmd_len; ++ qcom_scm_inv_range(start, start + sizeof(*rsp)); ++ } + } while (!rsp->is_complete); + +- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len + +- le32_to_cpu(rsp->buf_offset), +- resp_len, DMA_FROM_DEVICE); ++ if (dev) { ++ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len + ++ le32_to_cpu(rsp->buf_offset), ++ resp_len, DMA_FROM_DEVICE); ++ } else { ++ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len + ++ le32_to_cpu(rsp->buf_offset); ++ qcom_scm_inv_range(start, start + resp_len); ++ } + + if (res) { + res_buf = scm_legacy_get_response_buffer(rsp); +@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev, + res->result[i] = le32_to_cpu(res_buf[i]); + } + out: +- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE); ++ if (dev) ++ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE); + kfree(cmd); + return ret; + } +--- a/drivers/firmware/qcom_scm.c ++++ b/drivers/firmware/qcom_scm.c +@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en + desc.args[0] = flags; + desc.args[1] = virt_to_phys(entry); + ++ /* ++ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs ++ * require ugly DMA invalidation support that was dropped upstream a ++ * while ago. For more info, see: ++ * ++ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API? ++ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/ ++ */ ++ if (of_machine_is_compatible("google,wifi")) ++ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); ++ + return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); + } + EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); diff --git a/target/linux/ipq40xx/patches-5.15/702-dts-ipq4019-add-PHY-switch-nodes.patch b/target/linux/ipq40xx/patches-5.15/702-dts-ipq4019-add-PHY-switch-nodes.patch new file mode 100644 index 0000000000..d95e75107b --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/702-dts-ipq4019-add-PHY-switch-nodes.patch @@ -0,0 +1,46 @@ +From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Sun, 20 Nov 2016 02:20:54 +0100 +Subject: [PATCH] dts: ipq4019: add PHY/switch nodes + +This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii" +nodes which are needed for the ar40xx.c driver to initialize the +switch. + +Signed-off-by: Christian Lamparter +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -617,6 +617,29 @@ + }; + }; + ++ ess-switch@c000000 { ++ compatible = "qcom,ess-switch"; ++ reg = <0xc000000 0x80000>; ++ switch_access_mode = "local bus"; ++ resets = <&gcc ESS_RESET>; ++ reset-names = "ess_rst"; ++ clocks = <&gcc GCC_ESS_CLK>; ++ clock-names = "ess_clk"; ++ switch_cpu_bmp = <0x1>; ++ switch_lan_bmp = <0x1e>; ++ switch_wan_bmp = <0x20>; ++ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */ ++ switch_initvlas = <0x7c 0x54>; ++ status = "disabled"; ++ }; ++ ++ ess-psgmii@98000 { ++ compatible = "qcom,ess-psgmii"; ++ reg = <0x98000 0x800>; ++ psgmii_access_mode = "local bus"; ++ status = "disabled"; ++ }; ++ + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; diff --git a/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch b/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch new file mode 100644 index 0000000000..c0d99594da --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch @@ -0,0 +1,53 @@ +From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001 +From: Rakesh Nair +Date: Wed, 20 Jul 2016 15:02:01 +0530 +Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in + netdev_ops + +Add callback support to get default vlan tag and register +receive flow steering filter. + +Used by IPQ4019 ess-edma driver. + +BUG=chrome-os-partner:33096 +TEST=none + +Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75 +Signed-off-by: Rakesh Nair +Reviewed-on: https://chromium-review.googlesource.com/362203 +Commit-Ready: Grant Grundler +Tested-by: Grant Grundler +Reviewed-by: Grant Grundler +--- + include/linux/netdevice.h | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -765,6 +765,16 @@ struct xps_map { + #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \ + - sizeof(struct xps_map)) / sizeof(u16)) + ++#ifdef CONFIG_RFS_ACCEL ++typedef int (*set_rfs_filter_callback_t)(struct net_device *dev, ++ __be32 src, ++ __be32 dst, ++ __be16 sport, ++ __be16 dport, ++ u8 proto, ++ u16 rxq_index, ++ u32 action); ++#endif + /* + * This structure holds all XPS maps for device. Maps are indexed by CPU. + */ +@@ -1445,6 +1455,9 @@ struct net_device_ops { + const struct sk_buff *skb, + u16 rxq_index, + u32 flow_id); ++ int (*ndo_register_rfs_filter)(struct net_device *dev, ++ set_rfs_filter_callback_t set_filter); ++ int (*ndo_get_default_vlan_tag)(struct net_device *net); + #endif + int (*ndo_add_slave)(struct net_device *dev, + struct net_device *slave_dev, diff --git a/target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch b/target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch new file mode 100644 index 0000000000..cd0b10c6c8 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/mdio/Kconfig ++++ b/drivers/net/mdio/Kconfig +@@ -27,6 +27,13 @@ config OF_MDIO + help + OpenFirmware MDIO bus (Ethernet PHY) accessors + ++config AR40XX_PHY ++ tristate "Driver for Qualcomm Atheros IPQ40XX switches" ++ depends on HAS_IOMEM && OF && OF_MDIO ++ select SWCONFIG ++ help ++ This is the driver for Qualcomm Atheros IPQ40XX ESS switches. ++ + if MDIO_BUS + + config MDIO_DEVRES +--- a/drivers/net/mdio/Makefile ++++ b/drivers/net/mdio/Makefile +@@ -21,6 +21,8 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i. + obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o + obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o + ++obj-$(CONFIG_AR40XX_PHY) += ar40xx.o ++ + obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o + obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o + obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o diff --git a/target/linux/ipq40xx/patches-5.15/706-dt-bindings-net-add-QCA807x-PHY.patch b/target/linux/ipq40xx/patches-5.15/706-dt-bindings-net-add-QCA807x-PHY.patch new file mode 100644 index 0000000000..dfb8d692ab --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/706-dt-bindings-net-add-QCA807x-PHY.patch @@ -0,0 +1,61 @@ +From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 1 Oct 2020 15:05:35 +0200 +Subject: [PATCH] dt-bindings: net: add QCA807x PHY + +Add DT bindings for Qualcomm QCA807x PHY series. + +Signed-off-by: Robert Marko +--- + include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + create mode 100644 include/dt-bindings/net/qcom-qca807x.h + +--- /dev/null ++++ b/include/dt-bindings/net/qcom-qca807x.h +@@ -0,0 +1,45 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Device Tree constants for the Qualcomm QCA807X PHYs ++ */ ++ ++#ifndef _DT_BINDINGS_QCOM_QCA807X_H ++#define _DT_BINDINGS_QCOM_QCA807X_H ++ ++#define PSGMII_QSGMII_TX_DRIVER_140MV 0 ++#define PSGMII_QSGMII_TX_DRIVER_160MV 1 ++#define PSGMII_QSGMII_TX_DRIVER_180MV 2 ++#define PSGMII_QSGMII_TX_DRIVER_200MV 3 ++#define PSGMII_QSGMII_TX_DRIVER_220MV 4 ++#define PSGMII_QSGMII_TX_DRIVER_240MV 5 ++#define PSGMII_QSGMII_TX_DRIVER_260MV 6 ++#define PSGMII_QSGMII_TX_DRIVER_280MV 7 ++#define PSGMII_QSGMII_TX_DRIVER_300MV 8 ++#define PSGMII_QSGMII_TX_DRIVER_320MV 9 ++#define PSGMII_QSGMII_TX_DRIVER_400MV 10 ++#define PSGMII_QSGMII_TX_DRIVER_500MV 11 ++/* Default value */ ++#define PSGMII_QSGMII_TX_DRIVER_600MV 12 ++ ++/* Full amplitude, full bias current */ ++#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0 ++/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */ ++#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1 ++/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */ ++#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2 ++/* Both amplitude and bias current follow DSP */ ++#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3 ++/* Full amplitude, half bias current */ ++#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4 ++/* Amplitude follow DSP setting; 1/4 bias current when cable<10m, ++ * otherwise half bias current ++ */ ++#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5 ++/* Full amplitude; same bias current setting with “010” and “011”, ++ * but half more bias is reduced when cable <10m ++ */ ++#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6 ++/* Amplitude follow DSP; same bias current setting with “110”, default value */ ++#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7 ++ ++#endif diff --git a/target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch b/target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch new file mode 100644 index 0000000000..ba441022f3 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch @@ -0,0 +1,50 @@ +From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 7 Oct 2020 17:38:48 +0200 +Subject: [PATCH] net: phy: Add Qualcom QCA807x driver + +This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s. + +They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. + +They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber. + +Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber. + +Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s. +But some vendors used these to driver generic LED-s controlled by userspace, +so lets enable registering each PHY as GPIO controller and add driver for it. + +These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards. + +Signed-off-by: Robert Marko +--- + drivers/net/phy/Kconfig | 6 ++++++ + drivers/net/phy/Makefile | 1 + + 2 files changed, 7 insertions(+) + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -320,6 +320,12 @@ config AT803X_PHY + Currently supports the AR8030, AR8031, AR8033, AR8035 and internal + QCA8337(Internal qca8k PHY) model + ++config QCA807X_PHY ++ tristate "Qualcomm QCA807X PHYs" ++ depends on OF_MDIO ++ help ++ Currently supports the QCA8072 and QCA8075 models. ++ + config QSEMI_PHY + tristate "Quality Semiconductor PHYs" + help +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -86,6 +86,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/ + obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o + obj-$(CONFIG_QSEMI_PHY) += qsemi.o ++obj-$(CONFIG_QCA807X_PHY) += qca807x.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_RENESAS_PHY) += uPD60620.o + obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch b/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch new file mode 100644 index 0000000000..c08f3a83e6 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch @@ -0,0 +1,62 @@ +From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 2 Oct 2020 10:43:26 +0200 +Subject: [PATCH] arm: dts: ipq4019: QCA807x properties + +This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI. + +Signed-off-by: Robert Marko +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + / { + #address-cells = <1>; +@@ -598,22 +599,39 @@ + + ethphy0: ethernet-phy@0 { + reg = <0>; ++ ++ qcom,control-dac = ; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; ++ ++ qcom,control-dac = ; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; ++ ++ qcom,control-dac = ; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; ++ ++ qcom,control-dac = ; + }; + + ethphy4: ethernet-phy@4 { + reg = <4>; ++ ++ qcom,control-dac = ; ++ }; ++ ++ psgmiiphy: psgmii-phy@5 { ++ reg = <5>; ++ ++ qcom,tx-driver-strength = ; ++ qcom,psgmii-az; + }; + }; + diff --git a/target/linux/ipq40xx/patches-5.15/710-net-add-qualcomm-essedma-ethernet-driver.patch b/target/linux/ipq40xx/patches-5.15/710-net-add-qualcomm-essedma-ethernet-driver.patch new file mode 100644 index 0000000000..793ce72142 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/710-net-add-qualcomm-essedma-ethernet-driver.patch @@ -0,0 +1,37 @@ +From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Thu, 19 Jan 2017 02:01:31 +0100 +Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver + +Signed-off-by: Christian Lamparter +--- + drivers/net/ethernet/qualcomm/Kconfig | 9 +++++++++ + drivers/net/ethernet/qualcomm/Makefile | 1 + + 2 files changed, 10 insertions(+) + +--- a/drivers/net/ethernet/qualcomm/Kconfig ++++ b/drivers/net/ethernet/qualcomm/Kconfig +@@ -62,4 +62,14 @@ config QCOM_EMAC + + source "drivers/net/ethernet/qualcomm/rmnet/Kconfig" + ++config ESSEDMA ++ tristate "Qualcomm Atheros ESS Edma support" ++ depends on OF_MDIO ++ help ++ This driver supports ethernet edma adapter. ++ Say Y to build this driver. ++ ++ To compile this driver as a module, choose M here. The module ++ will be called essedma.ko. ++ + endif # NET_VENDOR_QUALCOMM +--- a/drivers/net/ethernet/qualcomm/Makefile ++++ b/drivers/net/ethernet/qualcomm/Makefile +@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o + qcauart-objs := qca_uart.o + + obj-y += emac/ ++obj-$(CONFIG_ESSEDMA) += essedma/ + + obj-$(CONFIG_RMNET) += rmnet/ diff --git a/target/linux/ipq40xx/patches-5.15/711-dts-ipq4019-add-ethernet-essedma-node.patch b/target/linux/ipq40xx/patches-5.15/711-dts-ipq4019-add-ethernet-essedma-node.patch new file mode 100644 index 0000000000..3567eb7810 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/711-dts-ipq4019-add-ethernet-essedma-node.patch @@ -0,0 +1,92 @@ +From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Sun, 20 Nov 2016 01:01:10 +0100 +Subject: [PATCH] dts: ipq4019: add ethernet essedma node + +This patch adds the device-tree node for the ethernet +interfaces. + +Note: The driver isn't anywhere close to be upstream, +so the info might change. + +Signed-off-by: Christian Lamparter +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 60 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -39,6 +39,8 @@ + spi1 = &blsp1_spi2; + i2c0 = &blsp1_i2c3; + i2c1 = &blsp1_i2c4; ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; + }; + + cpus { +@@ -658,6 +660,64 @@ + status = "disabled"; + }; + ++ edma@c080000 { ++ compatible = "qcom,ess-edma"; ++ reg = <0xc080000 0x8000>; ++ qcom,page-mode = <0>; ++ qcom,rx_head_buf_size = <1540>; ++ qcom,mdio_supported; ++ qcom,poll_required = <1>; ++ qcom,num_gmac = <2>; ++ interrupts = <0 65 IRQ_TYPE_EDGE_RISING ++ 0 66 IRQ_TYPE_EDGE_RISING ++ 0 67 IRQ_TYPE_EDGE_RISING ++ 0 68 IRQ_TYPE_EDGE_RISING ++ 0 69 IRQ_TYPE_EDGE_RISING ++ 0 70 IRQ_TYPE_EDGE_RISING ++ 0 71 IRQ_TYPE_EDGE_RISING ++ 0 72 IRQ_TYPE_EDGE_RISING ++ 0 73 IRQ_TYPE_EDGE_RISING ++ 0 74 IRQ_TYPE_EDGE_RISING ++ 0 75 IRQ_TYPE_EDGE_RISING ++ 0 76 IRQ_TYPE_EDGE_RISING ++ 0 77 IRQ_TYPE_EDGE_RISING ++ 0 78 IRQ_TYPE_EDGE_RISING ++ 0 79 IRQ_TYPE_EDGE_RISING ++ 0 80 IRQ_TYPE_EDGE_RISING ++ 0 240 IRQ_TYPE_EDGE_RISING ++ 0 241 IRQ_TYPE_EDGE_RISING ++ 0 242 IRQ_TYPE_EDGE_RISING ++ 0 243 IRQ_TYPE_EDGE_RISING ++ 0 244 IRQ_TYPE_EDGE_RISING ++ 0 245 IRQ_TYPE_EDGE_RISING ++ 0 246 IRQ_TYPE_EDGE_RISING ++ 0 247 IRQ_TYPE_EDGE_RISING ++ 0 248 IRQ_TYPE_EDGE_RISING ++ 0 249 IRQ_TYPE_EDGE_RISING ++ 0 250 IRQ_TYPE_EDGE_RISING ++ 0 251 IRQ_TYPE_EDGE_RISING ++ 0 252 IRQ_TYPE_EDGE_RISING ++ 0 253 IRQ_TYPE_EDGE_RISING ++ 0 254 IRQ_TYPE_EDGE_RISING ++ 0 255 IRQ_TYPE_EDGE_RISING>; ++ ++ status = "disabled"; ++ ++ gmac0: gmac0 { ++ local-mac-address = [00 00 00 00 00 00]; ++ vlan_tag = <1 0x1f>; ++ }; ++ ++ gmac1: gmac1 { ++ local-mac-address = [00 00 00 00 00 00]; ++ qcom,phy_mdio_addr = <4>; ++ qcom,poll_required = <1>; ++ qcom,forced_speed = <1000>; ++ qcom,forced_duplex = <1>; ++ vlan_tag = <2 0x20>; ++ }; ++ }; ++ + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; diff --git a/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch new file mode 100644 index 0000000000..df0b70d72e --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch @@ -0,0 +1,180 @@ +From: Christian Lamparter +Subject: SoC: add qualcomm syscon +--- a/drivers/soc/qcom/Makefile ++++ b/drivers/soc/qcom/Makefile +@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o + obj-$(CONFIG_QCOM_SMSM) += smsm.o + obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o + obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o ++obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o + obj-$(CONFIG_QCOM_APR) += apr.o + obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o + obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o +--- a/drivers/soc/qcom/Kconfig ++++ b/drivers/soc/qcom/Kconfig +@@ -189,6 +189,13 @@ config QCOM_SOCINFO + Say yes here to support the Qualcomm socinfo driver, providing + information about the SoC to user space. + ++config QCOM_TCSR ++ tristate "QCOM Top Control and Status Registers" ++ depends on ARCH_QCOM ++ help ++ Say y here to enable TCSR support. The TCSR provides control ++ functions for various peripherals. ++ + config QCOM_WCNSS_CTRL + tristate "Qualcomm WCNSS control driver" + depends on ARCH_QCOM || COMPILE_TEST +--- /dev/null ++++ b/drivers/soc/qcom/qcom_tcsr.c +@@ -0,0 +1,98 @@ ++/* ++ * Copyright (c) 2014, The Linux foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License rev 2 and ++ * only rev 2 as published by the free Software foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TCSR_USB_PORT_SEL 0xb0 ++#define TCSR_USB_HSPHY_CONFIG 0xC ++ ++#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0 ++#define TCSR_ESS_INTERFACE_SEL_MASK 0xf ++ ++#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0 ++#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4 ++#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4 ++ ++static int tcsr_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ const struct device_node *node = pdev->dev.of_node; ++ void __iomem *base; ++ u32 val; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { ++ dev_err(&pdev->dev, "setting usb port select = %d\n", val); ++ writel(val, base + TCSR_USB_PORT_SEL); ++ } ++ ++ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) { ++ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val); ++ writel(val, base + TCSR_USB_HSPHY_CONFIG); ++ } ++ ++ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) { ++ u32 tmp = 0; ++ dev_info(&pdev->dev, "setting ess interface select = %x\n", val); ++ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET); ++ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK); ++ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK); ++ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET); ++ } ++ ++ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) { ++ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val); ++ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET); ++ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET); ++ } ++ ++ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) { ++ dev_info(&pdev->dev, ++ "setting wifi_noc_memtype_m0_m2 = %x\n", val); ++ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2); ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id tcsr_dt_match[] = { ++ { .compatible = "qcom,tcsr", }, ++ { }, ++}; ++ ++MODULE_DEVICE_TABLE(of, tcsr_dt_match); ++ ++static struct platform_driver tcsr_driver = { ++ .driver = { ++ .name = "tcsr", ++ .owner = THIS_MODULE, ++ .of_match_table = tcsr_dt_match, ++ }, ++ .probe = tcsr_probe, ++}; ++ ++module_platform_driver(tcsr_driver); ++ ++MODULE_AUTHOR("Andy Gross "); ++MODULE_DESCRIPTION("QCOM TCSR driver"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/include/dt-bindings/soc/qcom,tcsr.h +@@ -0,0 +1,48 @@ ++/* Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#ifndef __DT_BINDINGS_QCOM_TCSR_H ++#define __DT_BINDINGS_QCOM_TCSR_H ++ ++#define TCSR_USB_SELECT_USB3_P0 0x1 ++#define TCSR_USB_SELECT_USB3_P1 0x2 ++#define TCSR_USB_SELECT_USB3_DUAL 0x3 ++ ++/* IPQ40xx HS PHY Mode Select */ ++#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7 ++#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7 ++ ++/* IPQ40xx ess interface mode select */ ++#define TCSR_ESS_PSGMII 0 ++#define TCSR_ESS_PSGMII_RGMII5 1 ++#define TCSR_ESS_PSGMII_RMII0 2 ++#define TCSR_ESS_PSGMII_RMII1 4 ++#define TCSR_ESS_PSGMII_RMII0_RMII1 6 ++#define TCSR_ESS_PSGMII_RGMII4 9 ++ ++/* ++ * IPQ40xx WiFi Global Config ++ * Bit 30:AXID_EN ++ * Enable AXI master bus Axid translating to confirm all txn submitted by order ++ * Bit 24: Use locally generated socslv_wxi_bvalid ++ * 1: use locally generate socslv_wxi_bvalid for performance. ++ * 0: use SNOC socslv_wxi_bvalid. ++ */ ++#define TCSR_WIFI_GLB_CFG 0x41000000 ++ ++/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */ ++#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222 ++ ++/* TCSR A/B REG */ ++#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 ++#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 ++ ++#endif diff --git a/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch b/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch new file mode 100644 index 0000000000..5a245eb431 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch @@ -0,0 +1,176 @@ +--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +@@ -15,6 +15,7 @@ + */ + + #include "qcom-ipq4019.dtsi" ++#include + + / { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; +@@ -29,6 +30,32 @@ + }; + + soc { ++ tcsr@194b000 { ++ /* select hostmode */ ++ compatible = "qcom,tcsr"; ++ reg = <0x194b000 0x100>; ++ qcom,usb-hsphy-mode-select = ; ++ status = "okay"; ++ }; ++ ++ ess_tcsr@1953000 { ++ compatible = "qcom,tcsr"; ++ reg = <0x1953000 0x1000>; ++ qcom,ess-interface-select = ; ++ }; ++ ++ tcsr@1949000 { ++ compatible = "qcom,tcsr"; ++ reg = <0x1949000 0x100>; ++ qcom,wifi_glb_cfg = ; ++ }; ++ ++ tcsr@1957000 { ++ compatible = "qcom,tcsr"; ++ reg = <0x1957000 0x100>; ++ qcom,wifi_noc_memtype_m0_m2 = ; ++ }; ++ + rng@22000 { + status = "ok"; + }; +@@ -74,14 +101,6 @@ + pinctrl-names = "default"; + status = "ok"; + cs-gpios = <&tlmm 54 0>; +- +- mx25l25635e@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- reg = <0>; +- compatible = "mx25l25635e"; +- spi-max-frequency = <24000000>; +- }; + }; + + serial@78af000 { +@@ -109,5 +128,41 @@ + wifi@a800000 { + status = "ok"; + }; ++ ++ mdio@90000 { ++ status = "okay"; ++ }; ++ ++ ess-switch@c000000 { ++ status = "okay"; ++ }; ++ ++ ess-psgmii@98000 { ++ status = "okay"; ++ }; ++ ++ edma@c080000 { ++ status = "okay"; ++ }; ++ ++ usb3_ss_phy: ssphy@9a000 { ++ status = "okay"; ++ }; ++ ++ usb3_hs_phy: hsphy@a6000 { ++ status = "okay"; ++ }; ++ ++ usb3: usb3@8af8800 { ++ status = "okay"; ++ }; ++ ++ usb2_hs_phy: hsphy@a8000 { ++ status = "okay"; ++ }; ++ ++ usb2: usb2@60f8800 { ++ status = "okay"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts ++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts +@@ -18,5 +18,73 @@ + + / { + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; ++ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1"; + ++ memory { ++ device_type = "memory"; ++ reg = <0x80000000 0x10000000>; ++ }; ++}; ++ ++&blsp1_spi1 { ++ mx25l25635f@0 { ++ compatible = "mx25l25635f", "jedec,spi-nor"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0>; ++ spi-max-frequency = <24000000>; ++ ++ SBL1@0 { ++ label = "SBL1"; ++ reg = <0x0 0x40000>; ++ read-only; ++ }; ++ MIBIB@40000 { ++ label = "MIBIB"; ++ reg = <0x40000 0x20000>; ++ read-only; ++ }; ++ QSEE@60000 { ++ label = "QSEE"; ++ reg = <0x60000 0x60000>; ++ read-only; ++ }; ++ CDT@c0000 { ++ label = "CDT"; ++ reg = <0xc0000 0x10000>; ++ read-only; ++ }; ++ DDRPARAMS@d0000 { ++ label = "DDRPARAMS"; ++ reg = <0xd0000 0x10000>; ++ read-only; ++ }; ++ APPSBLENV@e0000 { ++ label = "APPSBLENV"; ++ reg = <0xe0000 0x10000>; ++ read-only; ++ }; ++ APPSBL@f0000 { ++ label = "APPSBL"; ++ reg = <0xf0000 0x80000>; ++ read-only; ++ }; ++ ART@170000 { ++ label = "ART"; ++ reg = <0x170000 0x10000>; ++ read-only; ++ }; ++ kernel@180000 { ++ label = "kernel"; ++ reg = <0x180000 0x400000>; ++ }; ++ rootfs@580000 { ++ label = "rootfs"; ++ reg = <0x580000 0x1600000>; ++ }; ++ firmware@180000 { ++ label = "firmware"; ++ reg = <0x180000 0x1a00000>; ++ }; ++ }; + }; diff --git a/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch b/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch new file mode 100644 index 0000000000..a6a082a2c8 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch @@ -0,0 +1,89 @@ +From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 9 Mar 2017 11:03:18 +0100 +Subject: [PATCH] arm: boot: add dts files + +Signed-off-by: John Crispin +--- + arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -903,11 +903,76 @@ dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-ifc6540.dtb \ + qcom-apq8084-mtp.dtb \ ++ qcom-ipq4018-a42.dtb \ ++ qcom-ipq4018-ap120c-ac.dtb \ ++ qcom-ipq4018-dap-2610.dtb \ ++ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \ ++ qcom-ipq4018-magic-2-wifi-next.dtb \ ++ qcom-ipq4018-ea6350v3.dtb \ ++ qcom-ipq4018-eap1300.dtb \ ++ qcom-ipq4018-ecw5211.dtb \ ++ qcom-ipq4018-emd1.dtb \ ++ qcom-ipq4018-emr3500.dtb \ ++ qcom-ipq4018-ens620ext.dtb \ ++ qcom-ipq4018-ex6100v2.dtb \ ++ qcom-ipq4018-ex6150v2.dtb \ ++ qcom-ipq4018-fritzbox-4040.dtb \ ++ qcom-ipq4018-gl-ap1300.dtb \ ++ qcom-ipq4018-jalapeno.dtb \ ++ qcom-ipq4018-meshpoint-one.dtb \ ++ qcom-ipq4018-cap-ac.dtb \ ++ qcom-ipq4018-hap-ac2.dtb \ ++ qcom-ipq4018-sxtsq-5-ac.dtb \ ++ qcom-ipq4018-nbg6617.dtb \ ++ qcom-ipq4019-oap100.dtb \ ++ qcom-ipq4018-pa1200.dtb \ ++ qcom-ipq4018-rt-ac58u.dtb \ ++ qcom-ipq4018-rutx10.dtb \ ++ qcom-ipq4018-wac510.dtb \ ++ qcom-ipq4018-wre6606.dtb \ ++ qcom-ipq4018-wrtq-329acn.dtb \ + qcom-ipq4019-ap.dk01.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c3.dtb \ + qcom-ipq4019-ap.dk07.1-c1.dtb \ + qcom-ipq4019-ap.dk07.1-c2.dtb \ ++ qcom-ipq4019-a62.dtb \ ++ qcom-ipq4019-cm520-79f.dtb \ ++ qcom-ipq4019-e2600ac-c1.dtb \ ++ qcom-ipq4019-e2600ac-c2.dtb \ ++ qcom-ipq4019-ea8300.dtb \ ++ qcom-ipq4019-eap2200.dtb \ ++ qcom-ipq4019-fritzbox-7530.dtb \ ++ qcom-ipq4019-fritzrepeater-1200.dtb \ ++ qcom-ipq4019-fritzrepeater-3000.dtb \ ++ qcom-ipq4019-habanero-dvk.dtb \ ++ qcom-ipq4019-hap-ac3.dtb \ ++ qcom-ipq4019-map-ac2200.dtb \ ++ qcom-ipq4019-lhgg-60ad.dtb \ ++ qcom-ipq4019-mf286d.dtb \ ++ qcom-ipq4019-mr8300.dtb \ ++ qcom-ipq4019-pa2200.dtb \ ++ qcom-ipq4019-r619ac-64m.dtb \ ++ qcom-ipq4019-r619ac-128m.dtb \ ++ qcom-ipq4019-rbr50.dtb \ ++ qcom-ipq4019-rbs50.dtb \ ++ qcom-ipq4019-rt-ac42u.dtb \ ++ qcom-ipq4019-rtl30vw.dtb \ ++ qcom-ipq4019-srr60.dtb \ ++ qcom-ipq4019-srs60.dtb \ ++ qcom-ipq4019-u4019-32m.dtb \ ++ qcom-ipq4019-wifi.dtb \ ++ qcom-ipq4019-wpj419.dtb \ ++ qcom-ipq4019-wtr-m2133hp.dtb \ ++ qcom-ipq4019-x1pro.dtb \ ++ qcom-ipq4028-wpj428.dtb \ ++ qcom-ipq4029-ap-303.dtb \ ++ qcom-ipq4029-ap-303h.dtb \ ++ qcom-ipq4029-ap-365.dtb \ ++ qcom-ipq4029-gl-b1300.dtb \ ++ qcom-ipq4019-gl-b2200.dtb \ ++ qcom-ipq4029-gl-s1300.dtb \ ++ qcom-ipq4029-mr33.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-rb3011.dtb \ + qcom-msm8660-surf.dtb \ diff --git a/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch b/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch new file mode 100644 index 0000000000..ca32144846 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch @@ -0,0 +1,167 @@ +--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +@@ -17,53 +17,79 @@ + stdout-path = "serial0:115200n8"; + }; + +- memory { +- device_type = "memory"; +- reg = <0x80000000 0x10000000>; /* 256MB */ +- }; +- + soc { ++ rng@22000 { ++ status = "okay"; ++ }; ++ + pinctrl@1000000 { + serial_0_pins: serial0-pinmux { +- pins = "gpio16", "gpio17"; +- function = "blsp_uart0"; +- bias-disable; ++ mux { ++ pins = "gpio16", "gpio17"; ++ function = "blsp_uart0"; ++ bias-disable; ++ }; + }; + + serial_1_pins: serial1-pinmux { +- pins = "gpio8", "gpio9", +- "gpio10", "gpio11"; +- function = "blsp_uart1"; +- bias-disable; ++ mux { ++ pins = "gpio8", "gpio9"; ++ function = "blsp_uart1"; ++ bias-disable; ++ }; + }; + + spi_0_pins: spi-0-pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; +- bias-disable; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio12"; ++ }; ++ pinconf { ++ pins = "gpio13", "gpio14", "gpio15"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ pinconf_cs { ++ pins = "gpio12"; ++ drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + i2c_0_pins: i2c-0-pinmux { +- pins = "gpio20", "gpio21"; +- function = "blsp_i2c0"; +- bias-disable; ++ pinmux { ++ function = "blsp_i2c0"; ++ pins = "gpio10", "gpio11"; ++ }; ++ pinconf { ++ pins = "gpio10", "gpio11"; ++ drive-strength = <16>; ++ bias-disable; ++ }; + }; + + nand_pins: nand-pins { +- pins = "gpio53", "gpio55", "gpio56", +- "gpio57", "gpio58", "gpio59", +- "gpio60", "gpio62", "gpio63", +- "gpio64", "gpio65", "gpio66", +- "gpio67", "gpio68", "gpio69"; +- function = "qpic"; ++ pullups { ++ pins = "gpio52", "gpio53", "gpio58", ++ "gpio59"; ++ function = "qpic"; ++ bias-pull-up; ++ }; ++ ++ pulldowns { ++ pins = "gpio54", "gpio55", "gpio56", ++ "gpio57", "gpio60", "gpio61", ++ "gpio62", "gpio63", "gpio64", ++ "gpio65", "gpio66", "gpio67", ++ "gpio68", "gpio69"; ++ function = "qpic"; ++ bias-pull-down; ++ }; + }; + }; + +@@ -89,11 +115,11 @@ + status = "ok"; + cs-gpios = <&tlmm 12 0>; + +- m25p80@0 { ++ mx25l25635e@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; +- compatible = "n25q128a11"; ++ compatible = "mx25l25635e"; + spi-max-frequency = <24000000>; + }; + }; +@@ -103,9 +129,48 @@ + perst-gpio = <&tlmm 38 0x1>; + }; + ++ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */ ++ pinctrl-0 = <&i2c_0_pins>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ }; ++ + qpic-nand@79b0000 { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + }; ++ ++ usb3_ss_phy: ssphy@9a000 { ++ status = "okay"; ++ }; ++ ++ usb3_hs_phy: hsphy@a6000 { ++ status = "okay"; ++ }; ++ ++ usb3: usb3@8af8800 { ++ status = "okay"; ++ }; ++ ++ usb2_hs_phy: hsphy@a8000 { ++ status = "okay"; ++ }; ++ ++ usb2: usb2@60f8800 { ++ status = "okay"; ++ }; ++ ++ cryptobam: dma@8e04000 { ++ status = "okay"; ++ }; ++ ++ crypto@8e3a000 { ++ status = "okay"; ++ }; ++ ++ watchdog@b017000 { ++ status = "okay"; ++ }; + }; + }; From 29e177e4ee7260b16350660d7d94dc333931c46a Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 20 Nov 2021 23:06:34 +0100 Subject: [PATCH 48/75] ipq40xx: 5:15: refresh patches - Drop upstream patch - Refresh dts patch Signed-off-by: Ansuel Smith --- ...com-ipq4019-add-USB-devicetree-nodes.patch | 99 ------------------- ...ARM-dts-qcom-ipq4019-add-more-labels.patch | 44 --------- ...com-ipq4019-add-SDHCI-VQMMC-LDO-node.patch | 35 ------- .../901-arm-boot-add-dts-files.patch | 9 +- 4 files changed, 4 insertions(+), 183 deletions(-) delete mode 100644 target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch diff --git a/target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch b/target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch deleted file mode 100644 index 890611387c..0000000000 --- a/target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch +++ /dev/null @@ -1,99 +0,0 @@ -From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 9 Sep 2020 18:38:31 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes - -Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI. - -Signed-off-by: John Crispin -Signed-off-by: Robert Marko -Cc: Luka Perkov -Reviewed-by: Vinod Koul -Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr -Signed-off-by: Bjorn Andersson ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++ - 1 file changed, 74 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -605,5 +605,79 @@ - reg = <4>; - }; - }; -+ -+ usb3_ss_phy: ssphy@9a000 { -+ compatible = "qcom,usb-ss-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0x9a000 0x800>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB3_UNIPHY_PHY_ARES>; -+ reset-names = "por_rst"; -+ status = "disabled"; -+ }; -+ -+ usb3_hs_phy: hsphy@a6000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0xa6000 0x40>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+ status = "disabled"; -+ }; -+ -+ usb3: usb3@8af8800 { -+ compatible = "qcom,dwc3"; -+ reg = <0x8af8800 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&gcc GCC_USB3_MASTER_CLK>, -+ <&gcc GCC_USB3_SLEEP_CLK>, -+ <&gcc GCC_USB3_MOCK_UTMI_CLK>; -+ clock-names = "master", "sleep", "mock_utmi"; -+ ranges; -+ status = "disabled"; -+ -+ dwc3@8a00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x8a00000 0xf8000>; -+ interrupts = ; -+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ dr_mode = "host"; -+ }; -+ }; -+ -+ usb2_hs_phy: hsphy@a8000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0xa8000 0x40>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+ status = "disabled"; -+ }; -+ -+ usb2: usb2@60f8800 { -+ compatible = "qcom,dwc3"; -+ reg = <0x60f8800 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&gcc GCC_USB2_MASTER_CLK>, -+ <&gcc GCC_USB2_SLEEP_CLK>, -+ <&gcc GCC_USB2_MOCK_UTMI_CLK>; -+ clock-names = "master", "sleep", "mock_utmi"; -+ ranges; -+ status = "disabled"; -+ -+ dwc3@6000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x6000000 0xf8000>; -+ interrupts = ; -+ phys = <&usb2_hs_phy>; -+ phy-names = "usb2-phy"; -+ dr_mode = "host"; -+ }; -+ }; - }; - }; diff --git a/target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch b/target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch deleted file mode 100644 index d623a9c7b3..0000000000 --- a/target/linux/ipq40xx/patches-5.15/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch +++ /dev/null @@ -1,44 +0,0 @@ -From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 9 Sep 2020 21:56:37 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels - -Lets add labels to more commonly used nodes for easier modification in board DTS files. - -Signed-off-by: Robert Marko -Cc: Luka Perkov -Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr -Signed-off-by: Bjorn Andersson ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -190,7 +190,7 @@ - reg = <0x1800000 0x60000>; - }; - -- rng@22000 { -+ prng: rng@22000 { - compatible = "qcom,prng"; - reg = <0x22000 0x140>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; -@@ -300,7 +300,7 @@ - status = "disabled"; - }; - -- crypto@8e3a000 { -+ crypto: crypto@8e3a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0x08e3a000 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, -@@ -386,7 +386,7 @@ - dma-names = "rx", "tx"; - }; - -- watchdog@b017000 { -+ watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; - reg = <0xb017000 0x40>; - clocks = <&sleep_clk>; diff --git a/target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch b/target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch deleted file mode 100644 index 1d93fb800a..0000000000 --- a/target/linux/ipq40xx/patches-5.15/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch +++ /dev/null @@ -1,35 +0,0 @@ -From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 7 Sep 2020 12:19:37 +0200 -Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node - -Since we now have driver for the SDHCI VQMMC LDO needed -for I/0 voltage levels lets introduce the necessary node for it. - -Signed-off-by: Robert Marko -Cc: Luka Perkov -Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr -Signed-off-by: Bjorn Andersson ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -209,6 +209,16 @@ - interrupts = ; - }; - -+ vqmmc: regulator@1948000 { -+ compatible = "qcom,vqmmc-ipq4019-regulator"; -+ reg = <0x01948000 0x4>; -+ regulator-name = "vqmmc"; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-always-on; -+ status = "disabled"; -+ }; -+ - sdhci: sdhci@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x11c>, <0x7824000 0x800>; diff --git a/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch b/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch index a6a082a2c8..671df84c59 100644 --- a/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch +++ b/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch @@ -10,10 +10,10 @@ Signed-off-by: John Crispin --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -903,11 +903,76 @@ dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-apq8074-dragonboard.dtb \ - qcom-apq8084-ifc6540.dtb \ - qcom-apq8084-mtp.dtb \ +@@ -902,11 +902,65 @@ dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-ipq4018-ap120c-ac.dtb \ + qcom-ipq4018-ap120c-ac-bit.dtb \ + qcom-ipq4018-jalapeno.dtb \ + qcom-ipq4018-a42.dtb \ + qcom-ipq4018-ap120c-ac.dtb \ + qcom-ipq4018-dap-2610.dtb \ @@ -29,7 +29,6 @@ Signed-off-by: John Crispin + qcom-ipq4018-ex6150v2.dtb \ + qcom-ipq4018-fritzbox-4040.dtb \ + qcom-ipq4018-gl-ap1300.dtb \ -+ qcom-ipq4018-jalapeno.dtb \ + qcom-ipq4018-meshpoint-one.dtb \ + qcom-ipq4018-cap-ac.dtb \ + qcom-ipq4018-hap-ac2.dtb \ From 07ddbb99616ab7635235c1912768bf5b434fa99c Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 20 Nov 2021 23:07:21 +0100 Subject: [PATCH 49/75] ipq40xx: 5:15: refresh config Refresh config for kernel 5.15 using make kernel_menuconfig Signed-off-by: Ansuel Smith --- target/linux/ipq40xx/config-5.15 | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/target/linux/ipq40xx/config-5.15 b/target/linux/ipq40xx/config-5.15 index 779c86fc95..ed839df77e 100644 --- a/target/linux/ipq40xx/config-5.15 +++ b/target/linux/ipq40xx/config-5.15 @@ -1,3 +1,4 @@ +CONFIG_AF_UNIX_OOB=y CONFIG_ALIGNMENT_TRAP=y # CONFIG_APQ_GCC_8084 is not set # CONFIG_APQ_MMCC_8084 is not set @@ -46,13 +47,12 @@ CONFIG_ARM_VIRT_EXT=y CONFIG_AT803X_PHY=y CONFIG_AUTO_ZRELADDR=y CONFIG_BCH=y +CONFIG_BINARY_PRINTF=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_CMDLINE_PARSER=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_MQ_PCI=y CONFIG_BOUNCE=y # CONFIG_CACHE_L2X0 is not set -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_QCOM=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE_PARTITION=y @@ -96,13 +96,17 @@ CONFIG_CPU_V7=y CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC8=y CONFIG_CRYPTO_AES_ARM=y CONFIG_CRYPTO_AES_ARM_BS=y +# CONFIG_CRYPTO_BLAKE2B_NEON is not set +# CONFIG_CRYPTO_BLAKE2S_ARM is not set CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_DEV_QCE=y +# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set # CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set # CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y @@ -129,12 +133,15 @@ CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA256_ARM=y +CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SIMD=y CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_DEBUG_MISC=y +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y @@ -150,8 +157,10 @@ CONFIG_EDAC_SUPPORT=y CONFIG_EEPROM_AT24=y CONFIG_ESSEDMA=y CONFIG_EXTCON=y +# CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y @@ -165,6 +174,7 @@ CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y @@ -181,6 +191,7 @@ CONFIG_GENERIC_VDSO_32=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_GPIO_74X164=y +CONFIG_GPIO_CDEV=y CONFIG_GPIO_WATCHDOG=y CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y CONFIG_HANDLE_DOMAIN_IRQ=y @@ -221,6 +232,7 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_WORK=y +CONFIG_KMAP_LOCAL=y # CONFIG_KPSS_XCC is not set # CONFIG_KRAITCC is not set CONFIG_LEDS_LP5523=y @@ -231,6 +243,7 @@ CONFIG_LIBFDT=y CONFIG_LLD_VERSION=0 CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LTO_NONE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MDIO_BITBANG=y @@ -277,6 +290,7 @@ CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_BCH=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_QCOM=y +# CONFIG_MTD_QCOMSMEM_PARTS is not set CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y @@ -292,6 +306,8 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEON=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y CONFIG_NLS=y CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y @@ -371,8 +387,10 @@ CONFIG_POWER_SUPPLY=y CONFIG_PPS=y CONFIG_PRINTK_TIME=y CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_QCA807X_PHY=y CONFIG_QCOM_A53PLL=y +# CONFIG_QCOM_ADM is not set CONFIG_QCOM_BAM_DMA=y # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set @@ -445,6 +463,7 @@ CONFIG_SMP_ON_UP=y # CONFIG_SM_GPUCC_8250 is not set # CONFIG_SM_VIDEOCC_8150 is not set # CONFIG_SM_VIDEOCC_8250 is not set +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_BITBANG=y From 7a72fcc1c5800de2d966ccb773c1022103aadbcf Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 20 Nov 2021 23:08:25 +0100 Subject: [PATCH 50/75] ipq40xx: fix wrong nand definition for wpj419 Fix wrong nand definition for wpj419 that differ from the upstream node name. Signed-off-by: Ansuel Smith --- .../files/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts index 09cbfaca91..4a4c18322f 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts @@ -352,12 +352,6 @@ perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>; wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>; }; - - nand: qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; - }; }; keys { @@ -371,6 +365,12 @@ }; }; +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &gmac0 { qcom,phy_mdio_addr = <4>; qcom,poll_required = <1>; From 7c692f685bcb73530620f0250d7d2197475a0277 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 20 Nov 2021 23:10:20 +0100 Subject: [PATCH 51/75] ipq40xx: refresh ess driver and phy with new api Kernel 5.15 have some new api for ethtool and phy. Add ifdef to fix compilation error. Signed-off-by: Ansuel Smith Reviewed-by: Robert Marko --- .../ethernet/qualcomm/essedma/edma_ethtool.c | 12 +++++++ .../ipq40xx/files/drivers/net/phy/qca807x.c | 36 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c index f84cd5aa62..65706cfae1 100644 --- a/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c +++ b/target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c @@ -244,8 +244,14 @@ static int edma_set_settings(struct net_device *netdev, /* edma_get_coalesce * get interrupt mitigation */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0) +static int edma_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec, + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack) +#else static int edma_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec) +#endif { u32 reg_val; @@ -266,8 +272,14 @@ static int edma_get_coalesce(struct net_device *netdev, /* edma_set_coalesce * set interrupt mitigation */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0) +static int edma_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec, + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack) +#else static int edma_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec) +#endif { if (ec->tx_coalesce_usecs) edma_change_tx_coalesce(ec->tx_coalesce_usecs); diff --git a/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c b/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c index 16d7a80455..8d523548e5 100644 --- a/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c +++ b/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c @@ -610,6 +610,7 @@ static int qca807x_config_intr(struct phy_device *phydev) return ret; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0) static int qca807x_ack_intr(struct phy_device *phydev) { int ret; @@ -618,6 +619,33 @@ static int qca807x_ack_intr(struct phy_device *phydev) return (ret < 0) ? ret : 0; } +#else +static irqreturn_t qca807x_handle_interrupt(struct phy_device *phydev) +{ + int irq_status, int_enabled; + + irq_status = phy_read(phydev, QCA807X_INTR_STATUS); + if (irq_status < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + /* Read the current enabled interrupts */ + int_enabled = phy_read(phydev, QCA807X_INTR_ENABLE); + if (int_enabled < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + /* See if this was one of our enabled interrupts */ + if (!(irq_status & int_enabled)) + return IRQ_NONE; + + phy_trigger_machine(phydev); + + return IRQ_HANDLED; +} +#endif static int qca807x_led_config(struct phy_device *phydev) { @@ -779,7 +807,11 @@ static struct phy_driver qca807x_drivers[] = { .config_init = qca807x_config, .read_status = qca807x_read_status, .config_intr = qca807x_config_intr, +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0) .ack_interrupt = qca807x_ack_intr, +#else + .handle_interrupt = qca807x_handle_interrupt, +#endif .soft_reset = genphy_soft_reset, .get_tunable = qca807x_get_tunable, .set_tunable = qca807x_set_tunable, @@ -799,7 +831,11 @@ static struct phy_driver qca807x_drivers[] = { .config_init = qca807x_config, .read_status = qca807x_read_status, .config_intr = qca807x_config_intr, +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0) .ack_interrupt = qca807x_ack_intr, +#else + .handle_interrupt = qca807x_handle_interrupt, +#endif .soft_reset = genphy_soft_reset, .get_tunable = qca807x_get_tunable, .set_tunable = qca807x_set_tunable, From 7517955eac8c7bf0672cc6ab190029b2122d8d89 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Mon, 28 Mar 2022 00:12:55 +0200 Subject: [PATCH 52/75] ipq40xx: 5.15: refresh kernel patches Refresh kernel patches. Signed-off-by: Ansuel Smith Reviewed-by: Robert Marko --- .../patches-5.15/104-clk-fix-apss-cpu-overclocking.patch | 8 ++++---- .../patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch | 2 +- ...rm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch | 2 +- ...sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch | 2 +- .../patches-5.15/420-firmware-qcom-scm-disable-SDI.patch | 2 +- .../421-firmware-qcom-scm-cold-boot-address.patch | 2 +- .../703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch | 6 +++--- .../patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch | 8 ++++---- .../707-net-phy-Add-Qualcom-QCA807x-driver.patch | 6 +++--- .../patches-5.15/850-soc-add-qualcomm-syscon.patch | 2 +- .../ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch | 6 +++--- .../ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch | 4 ++-- .../ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch | 2 +- 13 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch b/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch index 25a2020bd2..2de03f7ae0 100644 --- a/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch +++ b/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch @@ -83,16 +83,16 @@ Signed-off-by: John Crispin if (!f) return -EINVAL; -@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c +@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c + const struct freq_tbl *f; u32 mask; - int ret; - f = qcom_find_freq(pll->freq_tbl, rate); + f = qcom_find_freq_close(pll->freq_tbl, rate); if (!f) return -EINVAL; -@@ -1305,6 +1328,7 @@ static unsigned long +@@ -1304,6 +1327,7 @@ static unsigned long clk_cpu_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -100,7 +100,7 @@ Signed-off-by: John Crispin struct clk_fepll *pll = to_clk_fepll(hw); u32 cdiv, pre_div; u64 rate; -@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h +@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; do_div(rate, pre_div); diff --git a/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch b/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch index 4297f32e05..eb015251a1 100644 --- a/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch +++ b/target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch @@ -13,7 +13,7 @@ Signed-off-by: Ram Chandra Jangir --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c -@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i +@@ -1735,6 +1735,17 @@ static const struct qcom_reset_map gcc_i [GCC_TCSR_BCR] = {0x22000, 0}, [GCC_MPM_BCR] = {0x24000, 0}, [GCC_SPDM_BCR] = {0x25000, 0}, diff --git a/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch b/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch index 1aa5a9f386..51891c1f22 100644 --- a/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch +++ b/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch @@ -22,7 +22,7 @@ Signed-off-by: John Thomson --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S -@@ -602,6 +602,41 @@ not_relocated: mov r0, #0 +@@ -624,6 +624,41 @@ not_relocated: mov r0, #0 bic r4, r4, #1 blne cache_on diff --git a/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch b/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch index fd46d54916..843291e871 100644 --- a/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch +++ b/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch @@ -13,7 +13,7 @@ Signed-off-by: Robert Marko --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c -@@ -2191,7 +2191,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat +@@ -2445,7 +2445,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat static const struct sdhci_ops sdhci_msm_ops = { .reset = sdhci_msm_reset, diff --git a/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch b/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch index eb474500b1..b2d7a403cf 100644 --- a/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch +++ b/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch @@ -21,7 +21,7 @@ static void qcom_scm_set_download_mode(bool enable) { bool avail; -@@ -1256,6 +1270,13 @@ static int qcom_scm_probe(struct platfor +@@ -1320,6 +1334,13 @@ static int qcom_scm_probe(struct platfor if (download_mode) qcom_scm_set_download_mode(true); diff --git a/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch b/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch index accf3e9686..13ebb5b000 100644 --- a/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch +++ b/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch @@ -34,7 +34,7 @@ +} + /** - * qcom_scm_call() - Sends a command to the SCM and waits for the command to + * scm_legacy_call() - Sends a command to the SCM and waits for the command to * finish processing. @@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev, diff --git a/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch b/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch index c0d99594da..8825b07cdb 100644 --- a/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch +++ b/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch @@ -24,7 +24,7 @@ Reviewed-by: Grant Grundler --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -765,6 +765,16 @@ struct xps_map { +@@ -771,6 +771,16 @@ struct xps_map { #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \ - sizeof(struct xps_map)) / sizeof(u16)) @@ -40,8 +40,8 @@ Reviewed-by: Grant Grundler +#endif /* * This structure holds all XPS maps for device. Maps are indexed by CPU. - */ -@@ -1445,6 +1455,9 @@ struct net_device_ops { + * +@@ -1477,6 +1487,9 @@ struct net_device_ops { const struct sk_buff *skb, u16 rxq_index, u32 flow_id); diff --git a/target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch b/target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch index cd0b10c6c8..46d311a9b9 100644 --- a/target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch +++ b/target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch @@ -1,8 +1,8 @@ --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig -@@ -27,6 +27,13 @@ config OF_MDIO +@@ -41,6 +41,13 @@ config ACPI_MDIO help - OpenFirmware MDIO bus (Ethernet PHY) accessors + ACPI MDIO bus (Ethernet PHY) accessors +config AR40XX_PHY + tristate "Driver for Qualcomm Atheros IPQ40XX switches" @@ -16,12 +16,12 @@ config MDIO_DEVRES --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile -@@ -21,6 +21,8 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i. +@@ -23,6 +23,8 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i. obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o +obj-$(CONFIG_AR40XX_PHY) += ar40xx.o + obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o + obj-$(CONFIG_MDIO_BUS_MUX_BCM6368) += mdio-mux-bcm6368.o obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o - obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o diff --git a/target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch b/target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch index ba441022f3..eba1d3454e 100644 --- a/target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch +++ b/target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch @@ -25,7 +25,7 @@ Signed-off-by: Robert Marko --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -320,6 +320,12 @@ config AT803X_PHY +@@ -346,6 +346,12 @@ config AT803X_PHY Currently supports the AR8030, AR8031, AR8033, AR8035 and internal QCA8337(Internal qca8k PHY) model @@ -40,8 +40,8 @@ Signed-off-by: Robert Marko help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -86,6 +86,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/ - obj-$(CONFIG_NATIONAL_PHY) += national.o +@@ -90,6 +90,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o +obj-$(CONFIG_QCA807X_PHY) += qca807x.o diff --git a/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch index df0b70d72e..b39237b1dd 100644 --- a/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch +++ b/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch @@ -12,7 +12,7 @@ Subject: SoC: add qualcomm syscon obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig -@@ -189,6 +189,13 @@ config QCOM_SOCINFO +@@ -190,6 +190,13 @@ config QCOM_SOCINFO Say yes here to support the Qualcomm socinfo driver, providing information about the SoC to user space. diff --git a/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch b/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch index 5a245eb431..650bdafe0e 100644 --- a/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch +++ b/target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch @@ -39,11 +39,11 @@ + }; + rng@22000 { - status = "ok"; + status = "okay"; }; @@ -74,14 +101,6 @@ pinctrl-names = "default"; - status = "ok"; + status = "okay"; cs-gpios = <&tlmm 54 0>; - - mx25l25635e@0 { @@ -58,7 +58,7 @@ serial@78af000 { @@ -109,5 +128,41 @@ wifi@a800000 { - status = "ok"; + status = "okay"; }; + + mdio@90000 { diff --git a/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch b/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch index 671df84c59..af1c695c26 100644 --- a/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch +++ b/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch @@ -10,7 +10,7 @@ Signed-off-by: John Crispin --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -902,11 +902,65 @@ dtb-$(CONFIG_ARCH_QCOM) += \ +@@ -951,11 +951,75 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4018-ap120c-ac.dtb \ qcom-ipq4018-ap120c-ac-bit.dtb \ qcom-ipq4018-jalapeno.dtb \ @@ -85,4 +85,4 @@ Signed-off-by: John Crispin + qcom-ipq4029-mr33.dtb \ qcom-ipq8064-ap148.dtb \ qcom-ipq8064-rb3011.dtb \ - qcom-msm8660-surf.dtb \ + qcom-msm8226-samsung-s3ve3g.dtb \ diff --git a/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch b/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch index ca32144846..05778a638f 100644 --- a/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch +++ b/target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch @@ -103,7 +103,7 @@ }; @@ -89,11 +115,11 @@ - status = "ok"; + status = "okay"; cs-gpios = <&tlmm 12 0>; - m25p80@0 { From 17b7756b5a20f6426f06991b92d6527f27ad1a65 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Mon, 28 Mar 2022 02:55:40 +0200 Subject: [PATCH 53/75] ipq40xx: 5.15: add testing kernel version Add 5.15 kernel as a testing kernel version in the Makefile. Linksys EA6350v3/EA8300/MR8300 will not build with buildbot settings and should be disabled when the target is switched, unless the image size is reduced again. Signed-off-by: Ansuel Smith Reviewed-by: Robert Marko [add comment for increased kernel size] Signed-off-by: Sungbo Eo --- target/linux/ipq40xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ipq40xx/Makefile b/target/linux/ipq40xx/Makefile index 9bdb55d783..7df920e2d8 100644 --- a/target/linux/ipq40xx/Makefile +++ b/target/linux/ipq40xx/Makefile @@ -9,7 +9,7 @@ CPU_SUBTYPE:=neon-vfpv4 SUBTARGETS:=generic chromium mikrotik KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 KERNELNAME:=zImage Image dtbs From 2114b22ef3444fe524c5688e45dd4ff0585465fb Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 25 Apr 2022 13:09:18 +0200 Subject: [PATCH 54/75] ipq40xx: 5.15: drop upstreamed sleep clock patch Patch that corrects sleep clock frequency has already been backported to 5.15 stable so remove the duplicate patch. Signed-off-by: Robert Marko --- .../105-ipq40xx-fix-sleep-clock.patch | 26 ------------------- 1 file changed, 26 deletions(-) delete mode 100644 target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch diff --git a/target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch b/target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch deleted file mode 100644 index 7a304f69ca..0000000000 --- a/target/linux/ipq40xx/patches-5.15/105-ipq40xx-fix-sleep-clock.patch +++ /dev/null @@ -1,26 +0,0 @@ -From a63c7162a1dae9f1185897641dc3e47e295563d6 Mon Sep 17 00:00:00 2001 -From: Pavel Kubelun -Date: Mon, 6 May 2019 20:55:16 +0300 -Subject: [PATCH] ARM: dts: qcom: ipq4019: fix sleep clock - -It seems like sleep_clk was copied from ipq806x. -Fix ipq40xx sleep_clk to the value QSDK defines. - -Link: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?id=d92ec59973484acc86dd24b67f10f8911b4b4b7d -Link: https://patchwork.kernel.org/comment/22721613/ -Suggested-by: Bjorn Andersson [clock-output-names] -Signed-off-by: Pavel Kubelun -Signed-off-by: Christian Lamparter [just fixed the value] ---- ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -142,7 +142,8 @@ - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; -- clock-frequency = <32768>; -+ clock-frequency = <32000>; -+ clock-output-names = "gcc_sleep_clk_src"; - #clock-cells = <0>; - }; - From 376834a7433b5707445f0b2dd0a3806d5cb045d4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 25 Apr 2022 13:10:15 +0200 Subject: [PATCH 55/75] ipq40xx: 5.15: refresh config Refresh 5.15 kernel config for IPQ40xx due to large number of generic config changes. Signed-off-by: Robert Marko --- target/linux/ipq40xx/config-5.15 | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/target/linux/ipq40xx/config-5.15 b/target/linux/ipq40xx/config-5.15 index ed839df77e..a84ff564de 100644 --- a/target/linux/ipq40xx/config-5.15 +++ b/target/linux/ipq40xx/config-5.15 @@ -1,4 +1,3 @@ -CONFIG_AF_UNIX_OOB=y CONFIG_ALIGNMENT_TRAP=y # CONFIG_APQ_GCC_8084 is not set # CONFIG_APQ_MMCC_8084 is not set @@ -47,7 +46,6 @@ CONFIG_ARM_VIRT_EXT=y CONFIG_AT803X_PHY=y CONFIG_AUTO_ZRELADDR=y CONFIG_BCH=y -CONFIG_BINARY_PRINTF=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_MQ_PCI=y @@ -99,8 +97,6 @@ CONFIG_CRC32_SLICEBY8=y CONFIG_CRC8=y CONFIG_CRYPTO_AES_ARM=y CONFIG_CRYPTO_AES_ARM_BS=y -# CONFIG_CRYPTO_BLAKE2B_NEON is not set -# CONFIG_CRYPTO_BLAKE2S_ARM is not set CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_DEFLATE=y @@ -117,7 +113,6 @@ CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y @@ -125,7 +120,6 @@ CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y @@ -140,8 +134,6 @@ CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_DEBUG_MISC=y -# CONFIG_DMABUF_DEBUG is not set -# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y @@ -157,7 +149,6 @@ CONFIG_EDAC_SUPPORT=y CONFIG_EEPROM_AT24=y CONFIG_ESSEDMA=y CONFIG_EXTCON=y -# CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FWNODE_MDIO=y @@ -167,6 +158,7 @@ CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y @@ -233,6 +225,7 @@ CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_WORK=y CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y # CONFIG_KPSS_XCC is not set # CONFIG_KRAITCC is not set CONFIG_LEDS_LP5523=y @@ -240,10 +233,8 @@ CONFIG_LEDS_LP5562=y CONFIG_LEDS_LP55XX_COMMON=y CONFIG_LEDS_TLC591XX=y CONFIG_LIBFDT=y -CONFIG_LLD_VERSION=0 CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LTO_NONE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MDIO_BITBANG=y @@ -307,7 +298,6 @@ CONFIG_NEON=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y -CONFIG_NET_SOCK_MSG=y CONFIG_NLS=y CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y @@ -324,7 +314,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OPTEE=y From daee22c7c0a6801a5e6de26a6039424d045788e7 Mon Sep 17 00:00:00 2001 From: Sungbo Eo Date: Sun, 1 May 2022 02:14:23 +0900 Subject: [PATCH 56/75] ipq40xx: 5.15: refresh subtarget config Update config with `make kernel_oldconfig CONFIG_TARGET=subtarget`. Signed-off-by: Sungbo Eo --- target/linux/ipq40xx/chromium/config-default | 2 +- target/linux/ipq40xx/mikrotik/config-default | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/ipq40xx/chromium/config-default b/target/linux/ipq40xx/chromium/config-default index 83a42dfb66..d78ca0ab28 100644 --- a/target/linux/ipq40xx/chromium/config-default +++ b/target/linux/ipq40xx/chromium/config-default @@ -1,6 +1,6 @@ CONFIG_BLK_DEV_SD=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y CONFIG_SG_POOL=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_HOST=y diff --git a/target/linux/ipq40xx/mikrotik/config-default b/target/linux/ipq40xx/mikrotik/config-default index dd0c69b748..1268d2c810 100644 --- a/target/linux/ipq40xx/mikrotik/config-default +++ b/target/linux/ipq40xx/mikrotik/config-default @@ -1,5 +1,5 @@ CONFIG_MIKROTIK=y CONFIG_MIKROTIK_RB_SYSFS=y CONFIG_MTD_ROUTERBOOT_PARTS=y -CONFIG_MTD_SPLIT_MINOR_FW=y CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y +CONFIG_MTD_SPLIT_MINOR_FW=y From 8e6ee6cbaf3269d81410322ab464f920432eb843 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Fri, 22 Apr 2022 09:05:52 +0200 Subject: [PATCH 57/75] kirkwood: copy config and patches to 5.15 This patch makes only a copy of 5.10 config and patches. Patches merged in upstream was omited. Signed-off-by: Pawel Dembicki --- target/linux/kirkwood/config-5.15 | 292 ++++++++++++++++++ .../kirkwood/patches-5.15/100-ib62x0.patch | 53 ++++ .../kirkwood/patches-5.15/101-iconnect.patch | 80 +++++ .../kirkwood/patches-5.15/102-dockstar.patch | 62 ++++ .../patches-5.15/103-iomega-ix2-200.patch | 67 ++++ .../patches-5.15/105-linksys-viper-dts.patch | 59 ++++ .../kirkwood/patches-5.15/106-goflexnet.patch | 53 ++++ ...-zyxel-nsa3x0-common-nand-partitions.patch | 48 +++ .../kirkwood/patches-5.15/107-03-nsa325.patch | 54 ++++ .../patches-5.15/109-pogoplug_v4.patch | 87 ++++++ .../kirkwood/patches-5.15/110-pogo_e02.patch | 68 ++++ .../kirkwood/patches-5.15/111-l-50.patch | 47 +++ .../patches-5.15/112-sheevaplug.patch | 47 +++ .../patches-5.15/113-readynas_duo_v2.patch | 76 +++++ ...able-sata-port-specific-led-triggers.patch | 10 + .../202-linksys-find-active-root.patch | 62 ++++ .../patches-5.15/203-blackarmor-nas220.patch | 99 ++++++ 17 files changed, 1264 insertions(+) create mode 100644 target/linux/kirkwood/config-5.15 create mode 100644 target/linux/kirkwood/patches-5.15/100-ib62x0.patch create mode 100644 target/linux/kirkwood/patches-5.15/101-iconnect.patch create mode 100644 target/linux/kirkwood/patches-5.15/102-dockstar.patch create mode 100644 target/linux/kirkwood/patches-5.15/103-iomega-ix2-200.patch create mode 100644 target/linux/kirkwood/patches-5.15/105-linksys-viper-dts.patch create mode 100644 target/linux/kirkwood/patches-5.15/106-goflexnet.patch create mode 100644 target/linux/kirkwood/patches-5.15/107-01-zyxel-nsa3x0-common-nand-partitions.patch create mode 100644 target/linux/kirkwood/patches-5.15/107-03-nsa325.patch create mode 100644 target/linux/kirkwood/patches-5.15/109-pogoplug_v4.patch create mode 100644 target/linux/kirkwood/patches-5.15/110-pogo_e02.patch create mode 100644 target/linux/kirkwood/patches-5.15/111-l-50.patch create mode 100644 target/linux/kirkwood/patches-5.15/112-sheevaplug.patch create mode 100644 target/linux/kirkwood/patches-5.15/113-readynas_duo_v2.patch create mode 100644 target/linux/kirkwood/patches-5.15/201-enable-sata-port-specific-led-triggers.patch create mode 100644 target/linux/kirkwood/patches-5.15/202-linksys-find-active-root.patch create mode 100644 target/linux/kirkwood/patches-5.15/203-blackarmor-nas220.patch diff --git a/target/linux/kirkwood/config-5.15 b/target/linux/kirkwood/config-5.15 new file mode 100644 index 0000000000..4963712ef4 --- /dev/null +++ b/target/linux/kirkwood/config-5.15 @@ -0,0 +1,292 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +# CONFIG_ARMADA_37XX_WATCHDOG is not set +# CONFIG_ARMADA_THERMAL is not set +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_THUMB is not set +CONFIG_ARM_UNWIND=y +CONFIG_ATA=y +CONFIG_ATAGS=y +CONFIG_ATA_LEDS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FEROCEON=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEV_MARVELL=y +CONFIG_CRYPTO_DEV_MARVELL_CESA=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART0_ALTERNATE=y +# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +CONFIG_DEBUG_UART_8250_SHIFT=2 +CONFIG_DEBUG_UART_PHYS=0xf1012000 +CONFIG_DEBUG_UART_VIRT=0xfed12000 +CONFIG_DEBUG_UNCOMPRESS=y +# CONFIG_DLCI is not set +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +# CONFIG_EARLY_PRINTK is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_PCI=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_MVEBU=y +CONFIG_GRO_CELLS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OMAP=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_PXA is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KIRKWOOD_CLK=y +CONFIG_KIRKWOOD_THERMAL=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_NETXBIG=y +CONFIG_LEDS_NS2=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_KIRKWOOD=y +CONFIG_MACH_MVEBU_ANY=y +CONFIG_MANGLE_BOOTARGS=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_MARVELL is not set +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MV643XX_ETH=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +# CONFIG_MVNETA is not set +# CONFIG_MVPP2 is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MV88E6XXX=y +CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y +CONFIG_NET_DSA_TAG_DSA=y +CONFIG_NET_DSA_TAG_EDSA=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_ORION_IRQCHIP=y +CONFIG_ORION_TIMER=y +CONFIG_ORION_WATCHDOG=y +CONFIG_OUTER_CACHE=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_BRIDGE_EMUL=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +# CONFIG_PHY_MVEBU_A3700_UTMI is not set +# CONFIG_PHY_MVEBU_A38X_COMPHY is not set +CONFIG_PHY_MVEBU_SATA=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_KIRKWOOD=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_SX150X=y +CONFIG_PLAT_ORION=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_LINKSTATION=y +CONFIG_POWER_SUPPLY=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_SATA_HOST=y +CONFIG_SATA_PMP=y +CONFIG_SCSI=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_MVEBU_UART is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_ARMADA_3700 is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_ORION=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +CONFIG_SWPHY=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_LED_TRIG=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/kirkwood/patches-5.15/100-ib62x0.patch b/target/linux/kirkwood/patches-5.15/100-ib62x0.patch new file mode 100644 index 0000000000..0637c24b63 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/100-ib62x0.patch @@ -0,0 +1,53 @@ +--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts ++++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts +@@ -6,7 +6,14 @@ + + / { + model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; +- compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ compatible = "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ ++ aliases { ++ led-boot = &led_green_os; ++ led-failsafe = &led_red_os; ++ led-running = &led_green_os; ++ led-upgrade = &led_red_os; ++ }; + + memory { + device_type = "memory"; +@@ -81,12 +88,12 @@ + &pmx_led_usb_transfer>; + pinctrl-names = "default"; + +- green-os { ++ led_green_os: green-os { + label = "ib62x0:green:os"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- red-os { ++ led_red_os: red-os { + label = "ib62x0:red:os"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; +@@ -118,13 +125,13 @@ + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x600000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@700000 { +- label = "root"; +- reg = <0x0700000 0xf900000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0xfe00000>; + }; + + }; diff --git a/target/linux/kirkwood/patches-5.15/101-iconnect.patch b/target/linux/kirkwood/patches-5.15/101-iconnect.patch new file mode 100644 index 0000000000..935e2dfcf5 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/101-iconnect.patch @@ -0,0 +1,80 @@ +--- a/arch/arm/boot/dts/kirkwood-iconnect.dts ++++ b/arch/arm/boot/dts/kirkwood-iconnect.dts +@@ -8,6 +8,13 @@ + model = "Iomega Iconnect"; + compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power_blue; ++ led-failsafe = &led_power_red; ++ led-running = &led_power_blue; ++ led-upgrade = &led_power_red; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -16,8 +23,6 @@ + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; +- linux,initrd-start = <0x4500040>; +- linux,initrd-end = <0x4800000>; + }; + + ocp@f1000000 { +@@ -89,12 +94,12 @@ + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; +- power-blue { ++ led_power_blue: power-blue { + label = "power:blue"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- power-red { ++ led_power_red: power-red { + label = "power:red"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; +@@ -146,28 +151,23 @@ + status = "okay"; + + partition@0 { +- label = "uboot"; +- reg = <0x0000000 0xc0000>; ++ label = "u-boot"; ++ reg = <0x0000000 0xe0000>; + }; + +- partition@a0000 { +- label = "env"; +- reg = <0xa0000 0x20000>; ++ partition@e0000 { ++ label = "u-boot environment"; ++ reg = <0xe0000 0x100000>; + }; + + partition@100000 { +- label = "zImage"; +- reg = <0x100000 0x300000>; +- }; +- +- partition@540000 { +- label = "initrd"; +- reg = <0x540000 0x300000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@980000 { +- label = "boot"; +- reg = <0x980000 0x1f400000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x1fe00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.15/102-dockstar.patch b/target/linux/kirkwood/patches-5.15/102-dockstar.patch new file mode 100644 index 0000000000..127f84962c --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/102-dockstar.patch @@ -0,0 +1,62 @@ +--- a/arch/arm/boot/dts/kirkwood-dockstar.dts ++++ b/arch/arm/boot/dts/kirkwood-dockstar.dts +@@ -8,6 +8,13 @@ + model = "Seagate FreeAgent Dockstar"; + compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -42,12 +49,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_orange>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -78,18 +85,22 @@ + + partition@0 { + label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; ++ reg = <0x0000000 0xe0000>; ++ }; ++ ++ partition@e0000 { ++ label = "u-boot environment"; ++ reg = <0xe0000 0x100000>; + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@500000 { +- label = "data"; +- reg = <0x0500000 0xfb00000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0xfe00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.15/103-iomega-ix2-200.patch b/target/linux/kirkwood/patches-5.15/103-iomega-ix2-200.patch new file mode 100644 index 0000000000..9313b4bc3e --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/103-iomega-ix2-200.patch @@ -0,0 +1,67 @@ +--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts ++++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +@@ -8,6 +8,13 @@ + model = "Iomega StorCenter ix2-200"; + compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power; ++ led-failsafe = &led_health; ++ led-running = &led_power; ++ led-upgrade = &led_health; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -127,16 +134,16 @@ + &pmx_led_rebuild &pmx_led_health >; + pinctrl-names = "default"; + +- power_led { ++ led_power: power_led { + label = "status:white:power_led"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; + rebuild_led { + label = "status:white:rebuild_led"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; +- health_led { ++ led_health: health_led { + label = "status:red:health_led"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; +@@ -186,18 +193,18 @@ + }; + + partition@a0000 { +- label = "env"; ++ label = "u-boot environment"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@100000 { +- label = "uImage"; ++ label = "kernel"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { +- label = "rootfs"; ++ label = "ubi"; + reg = <0x400000 0x1C00000>; + }; + }; +@@ -211,7 +218,7 @@ + }; + + ð0 { +- status = "okay"; ++ status = "disabled"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; diff --git a/target/linux/kirkwood/patches-5.15/105-linksys-viper-dts.patch b/target/linux/kirkwood/patches-5.15/105-linksys-viper-dts.patch new file mode 100644 index 0000000000..d56a469d94 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/105-linksys-viper-dts.patch @@ -0,0 +1,59 @@ +--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts ++++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts +@@ -24,6 +24,10 @@ + }; + + aliases { ++ led-boot = &led_white_health; ++ led-failsafe = &led_white_health; ++ led-running = &led_white_health; ++ led-upgrade = &led_white_health; + serial0 = &uart0; + }; + +@@ -56,9 +60,10 @@ + pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; + pinctrl-names = "default"; + +- white-health { ++ led_white_health: white-health { + label = "viper:white:health"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; + + white-pulse { +@@ -114,23 +119,23 @@ + }; + + partition@200000 { +- label = "kernel"; +- reg = <0x200000 0x2A0000>; ++ label = "kernel1"; ++ reg = <0x200000 0x1A00000>; + }; + +- partition@4a0000 { +- label = "rootfs"; +- reg = <0x4A0000 0x1760000>; ++ partition@500000 { ++ label = "rootfs1"; ++ reg = <0x500000 0x1700000>; + }; + + partition@1c00000 { +- label = "alt_kernel"; +- reg = <0x1C00000 0x2A0000>; ++ label = "kernel2"; ++ reg = <0x1C00000 0x1A00000>; + }; + +- partition@1ea0000 { +- label = "alt_rootfs"; +- reg = <0x1EA0000 0x1760000>; ++ partition@1f00000 { ++ label = "rootfs2"; ++ reg = <0x1F00000 0x1700000>; + }; + + partition@3600000 { diff --git a/target/linux/kirkwood/patches-5.15/106-goflexnet.patch b/target/linux/kirkwood/patches-5.15/106-goflexnet.patch new file mode 100644 index 0000000000..82cf90841e --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/106-goflexnet.patch @@ -0,0 +1,53 @@ +--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts ++++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts +@@ -8,6 +8,13 @@ + model = "Seagate GoFlex Net"; + compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -85,12 +92,12 @@ + >; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -159,18 +166,8 @@ + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; +- }; +- +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0xd800000>; ++ label = "ubi"; ++ reg = <0x0100000 0x0ff00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.15/107-01-zyxel-nsa3x0-common-nand-partitions.patch b/target/linux/kirkwood/patches-5.15/107-01-zyxel-nsa3x0-common-nand-partitions.patch new file mode 100644 index 0000000000..df654033fd --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/107-01-zyxel-nsa3x0-common-nand-partitions.patch @@ -0,0 +1,48 @@ +--- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi ++++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +@@ -112,40 +112,16 @@ + + partition@0 { + label = "uboot"; +- reg = <0x0000000 0x0100000>; ++ reg = <0x0000000 0x00c0000>; + read-only; + }; + partition@100000 { + label = "uboot_env"; +- reg = <0x0100000 0x0080000>; ++ reg = <0x00c0000 0x0080000>; + }; +- partition@180000 { +- label = "key_store"; +- reg = <0x0180000 0x0080000>; +- }; +- partition@200000 { +- label = "info"; +- reg = <0x0200000 0x0080000>; +- }; +- partition@280000 { +- label = "etc"; +- reg = <0x0280000 0x0a00000>; +- }; +- partition@c80000 { +- label = "kernel_1"; +- reg = <0x0c80000 0x0a00000>; +- }; +- partition@1680000 { +- label = "rootfs1"; +- reg = <0x1680000 0x2fc0000>; +- }; +- partition@4640000 { +- label = "kernel_2"; +- reg = <0x4640000 0x0a00000>; +- }; +- partition@5040000 { +- label = "rootfs2"; +- reg = <0x5040000 0x2fc0000>; ++ partition@140000 { ++ label = "ubi"; ++ reg = <0x0140000 0x7ec0000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.15/107-03-nsa325.patch b/target/linux/kirkwood/patches-5.15/107-03-nsa325.patch new file mode 100644 index 0000000000..374c0895a9 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/107-03-nsa325.patch @@ -0,0 +1,54 @@ +--- a/arch/arm/boot/dts/kirkwood-nsa325.dts ++++ b/arch/arm/boot/dts/kirkwood-nsa325.dts +@@ -15,6 +15,13 @@ + model = "ZyXEL NSA325"; + compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_green_sys; ++ led-failsafe = &led_orange_sys; ++ led-running = &led_green_sys; ++ led-upgrade = &led_orange_sys; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; +@@ -162,17 +169,19 @@ + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + +- green-sys { ++ led_green_sys: green-sys { + label = "nsa325:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; +- orange-sys { ++ led_orange_sys: orange-sys { + label = "nsa325:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd1 { + label = "nsa325:green:hdd1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "ata1"; + }; + red-hdd1 { + label = "nsa325:red:hdd1"; +@@ -181,6 +190,7 @@ + green-hdd2 { + label = "nsa325:green:hdd2"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "ata2"; + }; + red-hdd2 { + label = "nsa325:red:hdd2"; +@@ -189,6 +199,7 @@ + green-usb { + label = "nsa325:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "usb-host"; + }; + green-copy { + label = "nsa325:green:copy"; diff --git a/target/linux/kirkwood/patches-5.15/109-pogoplug_v4.patch b/target/linux/kirkwood/patches-5.15/109-pogoplug_v4.patch new file mode 100644 index 0000000000..4273eb9af1 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/109-pogoplug_v4.patch @@ -0,0 +1,87 @@ +--- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts ++++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts +@@ -18,12 +18,20 @@ + compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { ++ bootargs = "console=ttyS0,115200"; + stdout-path = "uart0:115200n8"; + }; + +@@ -37,8 +45,8 @@ + eject { + debounce-interval = <50>; + wakeup-source; +- linux,code = ; +- label = "Eject Button"; ++ linux,code = ; ++ label = "Reset"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; +@@ -48,12 +56,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_red>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "pogoplugv4:green:health"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogoplugv4:red:fault"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; +@@ -137,29 +145,19 @@ + #size-cells = <1>; + + partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x200000>; ++ label = "uboot"; ++ reg = <0x00000000 0x1c0000>; + read-only; + }; + +- partition@200000 { +- label = "uImage"; +- reg = <0x00200000 0x300000>; +- }; +- +- partition@500000 { +- label = "uImage2"; +- reg = <0x00500000 0x300000>; +- }; +- +- partition@800000 { +- label = "failsafe"; +- reg = <0x00800000 0x800000>; ++ partition@1c0000 { ++ label = "uboot_env"; ++ reg = <0x001c0000 0x40000>; + }; + +- partition@1000000 { +- label = "root"; +- reg = <0x01000000 0x7000000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x00200000 0x7e00000>; + }; + }; + }; diff --git a/target/linux/kirkwood/patches-5.15/110-pogo_e02.patch b/target/linux/kirkwood/patches-5.15/110-pogo_e02.patch new file mode 100644 index 0000000000..fc384d3521 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/110-pogo_e02.patch @@ -0,0 +1,68 @@ +--- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts ++++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts +@@ -20,6 +20,13 @@ + compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -33,12 +40,12 @@ + gpio-leds { + compatible = "gpio-leds"; + +- health { ++ led_health: health { + label = "pogo_e02:green:health"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogo_e02:orange:fault"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; +@@ -95,24 +102,24 @@ + status = "okay"; + + partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; ++ label = "uboot"; ++ reg = <0x0 0xe0000>; + read-only; + }; + +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; ++ partition@e0000 { ++ label = "uboot_env"; ++ reg = <0xe0000 0x20000>; + }; + +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; ++ partition@100000 { ++ label = "second_stage_uboot"; ++ reg = <0x100000 0x100000>; + }; + +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0x5b00000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.15/111-l-50.patch b/target/linux/kirkwood/patches-5.15/111-l-50.patch new file mode 100644 index 0000000000..bc933cb610 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/111-l-50.patch @@ -0,0 +1,47 @@ +--- a/arch/arm/boot/dts/kirkwood-l-50.dts ++++ b/arch/arm/boot/dts/kirkwood-l-50.dts +@@ -18,6 +18,13 @@ + reg = <0x00000000 0x20000000>; + }; + ++ aliases { ++ led-boot = &led_status_green; ++ led-failsafe = &led_status_red; ++ led-running = &led_status_green; ++ led-upgrade = &led_status_red; ++ }; ++ + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; +@@ -95,12 +102,12 @@ + leds { + compatible = "gpio-leds"; + +- status_green { ++ led_status_green: status_green { + label = "l-50:green:status"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + +- status_red { ++ led_status_red: status_red { + label = "l-50:red:status"; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; +@@ -349,13 +356,8 @@ + }; + + partition@100000 { +- label = "kernel-1"; +- reg = <0x00100000 0x00800000>; +- }; +- +- partition@900000 { +- label = "rootfs-1"; +- reg = <0x00900000 0x07100000>; ++ label = "ubi"; ++ reg = <0x00100000 0x07900000>; + }; + + partition@7a00000 { diff --git a/target/linux/kirkwood/patches-5.15/112-sheevaplug.patch b/target/linux/kirkwood/patches-5.15/112-sheevaplug.patch new file mode 100644 index 0000000000..d1ff9884a0 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/112-sheevaplug.patch @@ -0,0 +1,47 @@ +--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi ++++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +@@ -78,13 +78,8 @@ + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@500000 { +- label = "root"; +- reg = <0x0500000 0x1fb00000>; ++ label = "ubi"; ++ reg = <0x0100000 0x1ff00000>; + }; + }; + +--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts ++++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts +@@ -13,6 +13,13 @@ + model = "Globalscale Technologies SheevaPlug"; + compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_health; ++ led-running = &led_health; ++ led-upgrade = &led_health; ++ }; ++ + ocp@f1000000 { + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio>; +@@ -28,10 +35,10 @@ + pinctrl-0 = <&pmx_led_blue &pmx_led_red>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "sheevaplug:blue:health"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; + + misc { diff --git a/target/linux/kirkwood/patches-5.15/113-readynas_duo_v2.patch b/target/linux/kirkwood/patches-5.15/113-readynas_duo_v2.patch new file mode 100644 index 0000000000..c6452c55a3 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/113-readynas_duo_v2.patch @@ -0,0 +1,76 @@ +--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts ++++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +@@ -19,6 +19,13 @@ + reg = <0x00000000 0x10000000>; + }; + ++ aliases { ++ led-boot = &led_power; ++ led-failsafe = &led_power; ++ led-running = &led_power; ++ led-upgrade = &led_power; ++ }; ++ + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; +@@ -115,7 +122,7 @@ + &pmx_led_blue_backup >; + pinctrl-names = "default"; + +- power_led { ++ led_power: power_led { + label = "status:blue:power_led"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + default-state = "keep"; +@@ -129,11 +136,13 @@ + disk1_led { + label = "status:blue:disk1_led"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "ata1"; + }; + + disk2_led { + label = "status:blue:disk2_led"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "ata2"; + }; + + backup_led { +@@ -150,7 +159,13 @@ + + power-button { + label = "Power Button"; +- linux,code = ; ++ /* Power button and INT pin from PHY are both connected ++ * to this GPIO. Every network restart causes PHY restart ++ * and button is pressed. It's difficult to use it as ++ * KEY_POWER without changes in kernel (or netifd) so ++ * the button is configured as regular one. ++ */ ++ linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + +@@ -208,18 +223,13 @@ + }; + + partition@200000 { +- label = "uImage"; ++ label = "kernel"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { +- label = "minirootfs"; +- reg = <0x0800000 0x1000000>; +- }; +- +- partition@1800000 { +- label = "jffs2"; +- reg = <0x1800000 0x6800000>; ++ label = "ubi"; ++ reg = <0x0800000 0x7800000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.15/201-enable-sata-port-specific-led-triggers.patch b/target/linux/kirkwood/patches-5.15/201-enable-sata-port-specific-led-triggers.patch new file mode 100644 index 0000000000..35db065727 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/201-enable-sata-port-specific-led-triggers.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/mach-mvebu/Kconfig ++++ b/arch/arm/mach-mvebu/Kconfig +@@ -116,6 +116,7 @@ config MACH_DOVE + config MACH_KIRKWOOD + bool "Marvell Kirkwood boards" + depends on ARCH_MULTI_V5 ++ select ARCH_WANT_LIBATA_LEDS + select CPU_FEROCEON + select GPIOLIB + select KIRKWOOD_CLK diff --git a/target/linux/kirkwood/patches-5.15/202-linksys-find-active-root.patch b/target/linux/kirkwood/patches-5.15/202-linksys-find-active-root.patch new file mode 100644 index 0000000000..515bb21707 --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/202-linksys-find-active-root.patch @@ -0,0 +1,62 @@ +The WRT1900AC among other Linksys routers uses a dual-firmware layout. +Dynamically rename the active partition to "ubi". + +Signed-off-by: Imre Kaloz +--- +--- a/drivers/mtd/parsers/ofpart_core.c ++++ b/drivers/mtd/parsers/ofpart_core.c +@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static int mangled_rootblock; ++ + static int parse_fixed_partitions(struct mtd_info *master, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -47,6 +49,7 @@ static int parse_fixed_partitions(struct + struct mtd_partition *parts; + struct device_node *mtd_node; + struct device_node *ofpart_node; ++ const char *owrtpart = "ubi"; + const char *partname; + struct device_node *pp; + int nr_parts, i, ret = 0; +@@ -133,9 +136,15 @@ static int parse_fixed_partitions(struct + parts[i].size = of_read_number(reg + a_cells, s_cells); + parts[i].of_node = pp; + +- partname = of_get_property(pp, "label", &len); +- if (!partname) +- partname = of_get_property(pp, "name", &len); ++ if (mangled_rootblock && (i == mangled_rootblock)) { ++ partname = owrtpart; ++ } else { ++ partname = of_get_property(pp, "label", &len); ++ ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ } ++ + parts[i].name = partname; + + if (of_get_property(pp, "read-only", &len)) +@@ -252,6 +261,18 @@ static int __init ofpart_parser_init(voi + return 0; + } + ++static int __init active_root(char *str) ++{ ++ get_option(&str, &mangled_rootblock); ++ ++ if (!mangled_rootblock) ++ return 1; ++ ++ return 1; ++} ++ ++__setup("mangled_rootblock=", active_root); ++ + static void __exit ofpart_parser_exit(void) + { + deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/kirkwood/patches-5.15/203-blackarmor-nas220.patch b/target/linux/kirkwood/patches-5.15/203-blackarmor-nas220.patch new file mode 100644 index 0000000000..e04a28206a --- /dev/null +++ b/target/linux/kirkwood/patches-5.15/203-blackarmor-nas220.patch @@ -0,0 +1,99 @@ +--- a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts ++++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts +@@ -17,6 +17,13 @@ + compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_status_amber; ++ led-failsafe = &led_status_amber; ++ led-running = &led_status_blue; ++ led-upgrade = &led_status_amber; ++ }; ++ + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -36,14 +43,14 @@ + compatible = "gpio-keys"; + + reset { +- label = "Reset"; +- linux,code = ; ++ label = "Reset Button"; ++ linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + +- button { +- label = "Power"; +- linux,code = ; ++ power { ++ label = "Power Button"; ++ linux,code = ; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + }; +@@ -51,11 +58,27 @@ + gpio-leds { + compatible = "gpio-leds"; + +- blue-power { ++ led_power_blue: power_blue { + label = "nas220:blue:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; ++ ++ disk_blue { ++ label = "nas220:blue:disk"; ++ gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "disk-activity"; ++ }; ++ ++ led_status_blue: status_blue { ++ label = "nas220:blue:status"; ++ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led_status_amber: status_amber { ++ label = "nas220:amber:status"; ++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; ++ }; + }; + + regulators { +@@ -153,6 +176,33 @@ + + &nand { + status = "okay"; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ ++ partition@0 { ++ label = "uboot"; ++ reg = <0x0 0xa0000>; ++ read-only; ++ }; ++ ++ partition@a0000 { ++ label = "uboot-env"; ++ reg = <0xa0000 0x10000>; ++ read-only; ++ }; ++ ++ partition@b0000 { ++ label = "reserved"; ++ reg = <0xb0000 0x10000>; ++ read-only; ++ }; ++ ++ partition@c0000 { ++ label = "ubi"; ++ reg = <0xc0000 0x1e80000>; ++ }; ++ }; + }; + + &mdio { From 62be521ca7dbfe2d4a9a2523ebf5a9a6bb9f2133 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Fri, 22 Apr 2022 09:24:34 +0200 Subject: [PATCH 58/75] generic: 5.15: add missing symbol Found durring kirkwood refreshing. Signed-off-by: Pawel Dembicki --- target/linux/generic/config-5.15 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15 index bc5ecb4d72..35be3aa406 100644 --- a/target/linux/generic/config-5.15 +++ b/target/linux/generic/config-5.15 @@ -4635,6 +4635,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_MTK_HDMI is not set # CONFIG_PHY_MTK_MIPI_DSI is not set +# CONFIG_PHY_MVEBU_CP110_UTMI is not set # CONFIG_PHY_OCELOT_SERDES is not set # CONFIG_PHY_PISTACHIO_USB is not set # CONFIG_PHY_PXA_28NM_HSIC is not set From 11fdfc2eca3a718f44cfc4108b3a233900c6660e Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Fri, 22 Apr 2022 09:26:20 +0200 Subject: [PATCH 59/75] kirkwood: refresh 5.15 kernel config Done by "make kernel_oldconfig". Signed-off-by: Pawel Dembicki --- target/linux/kirkwood/config-5.15 | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/linux/kirkwood/config-5.15 b/target/linux/kirkwood/config-5.15 index 4963712ef4..2fb7c11160 100644 --- a/target/linux/kirkwood/config-5.15 +++ b/target/linux/kirkwood/config-5.15 @@ -35,10 +35,8 @@ CONFIG_AUTO_ZRELADDR=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_CACHE_FEROCEON_L2=y # CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y @@ -82,7 +80,6 @@ CONFIG_DEBUG_UART_8250_SHIFT=2 CONFIG_DEBUG_UART_PHYS=0xf1012000 CONFIG_DEBUG_UART_VIRT=0xfed12000 CONFIG_DEBUG_UNCOMPRESS=y -# CONFIG_DLCI is not set CONFIG_DMA_OPS=y CONFIG_DMA_REMAP=y CONFIG_DNOTIFY=y @@ -93,6 +90,7 @@ CONFIG_EDAC_SUPPORT=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FORCE_PCI=y +CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ATOMIC64=y @@ -105,6 +103,7 @@ CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PINCONF=y @@ -115,6 +114,7 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GLOB=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y CONFIG_GPIO_MVEBU=y CONFIG_GRO_CELLS=y CONFIG_HANDLE_DOMAIN_IRQ=y @@ -183,9 +183,10 @@ CONFIG_NEED_PER_CPU_KM=y CONFIG_NET_DEVLINK=y CONFIG_NET_DSA=y CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y CONFIG_NET_DSA_TAG_DSA=y +CONFIG_NET_DSA_TAG_DSA_COMMON=y CONFIG_NET_DSA_TAG_EDSA=y +CONFIG_NET_SELFTESTS=y CONFIG_NET_SWITCHDEV=y CONFIG_NLS=y CONFIG_NVMEM=y @@ -197,7 +198,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_ORION_IRQCHIP=y @@ -227,6 +227,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_LINKSTATION=y CONFIG_POWER_SUPPLY=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_RATIONAL=y CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y @@ -239,6 +240,7 @@ CONFIG_RTC_MC146818_LIB=y CONFIG_SATA_HOST=y CONFIG_SATA_PMP=y CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_MCTRL_GPIO=y From 55553a45f8620b716eb3e8a67db3f426bc481a5b Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 25 Apr 2022 09:36:39 +0200 Subject: [PATCH 60/75] kirkwood: set testing kernel version to 5.15 This patch configures kernel testing version for kirkwood target. Compile tested: all Run tested: Endian 4i Signed-off-by: Pawel Dembicki --- target/linux/kirkwood/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/kirkwood/Makefile b/target/linux/kirkwood/Makefile index e972b8e587..c7a25451c9 100644 --- a/target/linux/kirkwood/Makefile +++ b/target/linux/kirkwood/Makefile @@ -11,6 +11,7 @@ FEATURES:=usb nand squashfs ramdisk CPU_TYPE:=xscale KERNEL_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk From 65dc9e0980255b15402c45b840f239b85be59b3d Mon Sep 17 00:00:00 2001 From: Tamas Balogh Date: Fri, 15 Apr 2022 11:16:37 +0200 Subject: [PATCH 61/75] ramips: ethernet: ralink: add led_source dts-binding this adds the new dts-binding "mediatek,led_source" currently for MT7628AN and MT7688 built-in switches, which is documented as a 3-bit field configuring the switch LEDs for various control schemes from 0 to 3. Normally this is not needed, but e.g. for Asus RT-AC1200-V2 it is a must to set it to the anyway undocumented value of 4, to have the switch LEDs react correctly on link/act events. This is an MT7628DAN device, but I doubt this is a speciality of this particular SoC. Also added the RT305X_ESW_LED_OFF value to LED states. Did also rename the register RT5350_EWS_REG_LED_POLARITY to RT5350_EWS_REG_LED_CONTROL, which is the correct name. Also making use of defines for some hardcoded values. Signed-off-by: Tamas Balogh --- .../drivers/net/ethernet/ralink/esw_rt3050.c | 27 ++++++++++++------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c index 75b6707be2..fe787fe92f 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c @@ -79,6 +79,7 @@ #define RT305X_ESW_LED_100MACT 8 /* Additional led states not in datasheet: */ #define RT305X_ESW_LED_BLINK 10 +#define RT305X_ESW_LED_OFF 11 #define RT305X_ESW_LED_ON 12 #define RT305X_ESW_LINK_S 25 @@ -174,7 +175,7 @@ #define RT305X_ESW_NUM_LEDS 5 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x)) -#define RT5350_EWS_REG_LED_POLARITY 0x168 +#define RT5350_EWS_REG_LED_CONTROL 0x168 enum { /* Global attributes. */ @@ -227,6 +228,7 @@ struct rt305x_esw { unsigned int reg_initval_fct2; unsigned int reg_initval_fpa2; unsigned int reg_led_polarity; + unsigned int reg_led_source; struct switch_dev swdev; bool global_vlan_enable; @@ -517,11 +519,11 @@ static void esw_hw_init(struct rt305x_esw *esw) esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA); /* Force Link/Activity on ports */ - esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED); - esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED); - esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED); - esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED); - esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED); + esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P0LED); + esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P1LED); + esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P2LED); + esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P3LED); + esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P4LED); /* Copy disabled port configuration from device tree setup */ port_disable = esw->port_disable; @@ -589,7 +591,7 @@ static void esw_hw_init(struct rt305x_esw *esw) /* set the led polarity */ esw_w32(esw, esw->reg_led_polarity & 0x1F, - RT5350_EWS_REG_LED_POLARITY); + RT5350_EWS_REG_LED_CONTROL); /* local registers */ rt305x_mii_write(esw, 0, 31, 0x8000); @@ -644,9 +646,10 @@ static void esw_hw_init(struct rt305x_esw *esw) esw_reset_ephy(esw); - /* set the led polarity */ - esw_w32(esw, esw->reg_led_polarity & 0x1F, - RT5350_EWS_REG_LED_POLARITY); + /* set the led polarity and led source */ + esw_w32(esw, (esw->reg_led_polarity & 0x1F) | + ((esw->reg_led_source << 8) & 0x700), + RT5350_EWS_REG_LED_CONTROL); rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */ rt305x_mii_write(esw, 0, 26, 0x0020); @@ -1435,6 +1438,10 @@ static int esw_probe(struct platform_device *pdev) if (reg_init) esw->reg_led_polarity = be32_to_cpu(*reg_init); + reg_init = of_get_property(np, "mediatek,led_source", NULL); + if (reg_init) + esw->reg_led_source = be32_to_cpu(*reg_init); + esw->rst_esw = devm_reset_control_get(&pdev->dev, "esw"); if (IS_ERR(esw->rst_esw)) esw->rst_esw = NULL; From 4e8d095013fb822eaa4fd6b4512a434fc17ac901 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 1 May 2022 17:00:47 +0100 Subject: [PATCH 62/75] fstools: update to git HEAD f0fc66a libfstools: check for overlay mounting errors 128ecaf Update / fix extroot comments 8a0ba3b libfstools: get rid of "extroot_prefix" global variable 649cd3f libfstools: use variable for overlay mount-point 922f1b3 libfstools: avoid segfault in find_mount_point ce5eacb libfstools: mtd: improve error handling 898b328 blockd: restore device_move semantics 0917d22 block: don't probe mtdblock on NAND (with legacy exceptions) Signed-off-by: Daniel Golle --- package/system/fstools/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/system/fstools/Makefile b/package/system/fstools/Makefile index bc15bfdaf5..eb7d5ac635 100644 --- a/package/system/fstools/Makefile +++ b/package/system/fstools/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/fstools.git -PKG_MIRROR_HASH:=e4d8fcdf8f83749553be109c7c39141cc4495ac46d476c8d2dc6a0d8dccfb741 -PKG_SOURCE_DATE:=2021-11-16 -PKG_SOURCE_VERSION:=77c02889177c43df8ebe07bce4d55b7f7358118f +PKG_MIRROR_HASH:=e63ad1c66ec31b45d815112bf3e25b3b0ea58962323624192a658a84b004a30d +PKG_SOURCE_DATE:=2022-05-01 +PKG_SOURCE_VERSION:=0917d223d14bca9edd3f8c91e2828a7a960a21d1 CMAKE_INSTALL:=1 PKG_LICENSE:=GPL-2.0 From 7d02fc0951ffcff3ba885374b108d20de92eddbe Mon Sep 17 00:00:00 2001 From: Rodrigo Balerdi Date: Mon, 2 May 2022 05:33:01 -0300 Subject: [PATCH 63/75] base-files: fix sysupgrade for kernel-out-of-UBI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit ecbcc0b59551 bricks devices on which the raw kernel and UBI mtd partitions overlap. This is the case of the ZyXEL NR7101 for example. Its OEM bootloader has no UBI support. OpenWrt splits the stock kernel mtd partition into a raw kernel part used by the bootloader and a UBI part used to store rootfs and rootfs_data. Running mtd erase on the complete partition during sysupgrade erases the UBI part and results in a soft brick. Arguably the best solution would be to fix the partition layouts so that kernel and UBI partitions do not overlap, also including a stock_kernel partition to help reverting to stock firmware. This would have the added benefit of protecting UBI from kernel images that are excessively large. Fixes: ecbcc0b59551 ("base-files: safer sysupgrade.tar for kernel-out-of-UBI") Reported-by: Bjørn Mork Signed-off-by: Rodrigo Balerdi --- package/base-files/files/lib/upgrade/nand.sh | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/package/base-files/files/lib/upgrade/nand.sh b/package/base-files/files/lib/upgrade/nand.sh index 5ecdb0ff23..c9960bf9d4 100644 --- a/package/base-files/files/lib/upgrade/nand.sh +++ b/package/base-files/files/lib/upgrade/nand.sh @@ -305,7 +305,11 @@ nand_upgrade_tar() { local ubi_kernel_length if [ "$kernel_length" ]; then if [ "$kernel_mtd" ]; then - mtd erase "$CI_KERNPART" + # On some devices, the raw kernel and ubi partitions overlap. + # These devices brick if the kernel partition is erased. + # Hence only invalidate kernel for now. + dd if=/dev/zero bs=4096 count=1 2>/dev/null | \ + mtd write - "$CI_KERNPART" else ubi_kernel_length="$kernel_length" fi @@ -322,7 +326,7 @@ nand_upgrade_tar() { if [ "$kernel_length" ]; then if [ "$kernel_mtd" ]; then tar xf "$tar_file" "$board_dir/kernel" -O | \ - mtd -n write - "$CI_KERNPART" + mtd write - "$CI_KERNPART" else local kern_ubivol="$( nand_find_volume $ubidev "$CI_KERNPART" )" tar xf "$tar_file" "$board_dir/kernel" -O | \ From 5109bd164c8f2273329483f990188fb36cf3ad68 Mon Sep 17 00:00:00 2001 From: Dominick Grift Date: Sun, 1 May 2022 19:54:04 +0200 Subject: [PATCH 64/75] base-files: address sed in-place without SELinux awareness sed(1) in busybox does not support this functionality: https://git.savannah.gnu.org/cgit/sed.git/tree/sed/execute.c#n598 This causes /etc/group to become mislabeled when a package requests that a uid/gid be added on OpenWrt with SELinux Signed-off-by: Daniel Golle [move restorecon inside lock] Signed-off-by: Dominick Grift --- package/base-files/files/lib/functions.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/package/base-files/files/lib/functions.sh b/package/base-files/files/lib/functions.sh index ee0c33845c..9db0871d6c 100644 --- a/package/base-files/files/lib/functions.sh +++ b/package/base-files/files/lib/functions.sh @@ -386,6 +386,7 @@ group_add_user() { echo "$grp" | grep -q ":$" && delim="" [ -n "$IPKG_INSTROOT" ] || lock /var/lock/passwd sed -i "s/$grp/$grp$delim$2/g" ${IPKG_INSTROOT}/etc/group + selinuxenabled 2>/dev/null && restorecon /etc/group [ -n "$IPKG_INSTROOT" ] || lock -u /var/lock/passwd } From 0276fab64933dc42bad865974dc224e2672f99fe Mon Sep 17 00:00:00 2001 From: Bruno Victal Date: Fri, 15 Apr 2022 15:30:01 +0100 Subject: [PATCH 65/75] dnsmasq: fix jail_mount for serversfile Fix 'serversfile' option not being jail_mounted by the init script. Signed-off-by: Bruno Victal --- package/network/services/dnsmasq/files/dnsmasq.init | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/package/network/services/dnsmasq/files/dnsmasq.init b/package/network/services/dnsmasq/files/dnsmasq.init index 040ceaea2f..c4ca3eb2db 100755 --- a/package/network/services/dnsmasq/files/dnsmasq.init +++ b/package/network/services/dnsmasq/files/dnsmasq.init @@ -972,7 +972,14 @@ dnsmasq_start() config_list_foreach "$cfg" "addnhosts" append_addnhosts config_list_foreach "$cfg" "bogusnxdomain" append_bogusnxdomain append_parm "$cfg" "leasefile" "--dhcp-leasefile" "/tmp/dhcp.leases" - append_parm "$cfg" "serversfile" "--servers-file" + + local serversfile + config_get serversfile "$cfg" "serversfile" + [ -n "$serversfile" ] && { + xappend "--servers-file=$serversfile" + append EXTRA_MOUNT "$serversfile" + } + append_parm "$cfg" "tftp_root" "--tftp-root" append_parm "$cfg" "dhcp_boot" "--dhcp-boot" append_parm "$cfg" "local_ttl" "--local-ttl" From 6d7272852e0b2634b2fa93a131ea8659ec87f079 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 2 May 2022 19:58:56 +0100 Subject: [PATCH 66/75] base-files: add missing $IPKG_INSTROOT to restorecon call Update to overlooked v2 version of Dominick Grift's patch. Fixes: 5109bd164c ("base-files: address sed in-place without SELinux awareness") Signed-off-by: Daniel Golle --- package/base-files/files/lib/functions.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/package/base-files/files/lib/functions.sh b/package/base-files/files/lib/functions.sh index 9db0871d6c..da2dd5b346 100644 --- a/package/base-files/files/lib/functions.sh +++ b/package/base-files/files/lib/functions.sh @@ -386,7 +386,9 @@ group_add_user() { echo "$grp" | grep -q ":$" && delim="" [ -n "$IPKG_INSTROOT" ] || lock /var/lock/passwd sed -i "s/$grp/$grp$delim$2/g" ${IPKG_INSTROOT}/etc/group - selinuxenabled 2>/dev/null && restorecon /etc/group + if [ -x /usr/sbin/selinuxenabled ] && selinuxenabled; then + selinuxenabled 2>/dev/null && restorecon ${IPKG_INSTROOT}/etc/group + fi [ -n "$IPKG_INSTROOT" ] || lock -u /var/lock/passwd } From e3f9af4fb6e4ba8bf54cb4240f318ad32260a6fa Mon Sep 17 00:00:00 2001 From: Enrico Mioso Date: Thu, 28 Apr 2022 08:57:24 +0200 Subject: [PATCH 67/75] ipq40xx: fix BDF file for pcie wifi chip on the GL.Inet GL-B2200 After the switch to pre-calibration, ath10k would fail to initialize the PCIE Wi-Fi on the GL-B200 as follows: ath10k_pci 0000:01:00.0: enabling device (0140 -> 0142) ath10k_pci 0000:01:00.0: qca9888 hw2.0 target 0x01000000 chip_id 0x00000000 sub 0000:0000 [...] ath10k_pci 0000:01:00.0: failed to fetch board data for bus=pci,bmi-chip-id=0,bmi-board-id=16,variant=GL-B2200 from ath10k/QCA9888/hw2.0/board-2.bin ath10k_pci 0000:01:00.0: failed to fetch board-2.bin or board.bin from ath10k/QCA9888/hw2.0 ath10k_pci 0000:01:00.0: failed to fetch board file: -12 ath10k_pci 0000:01:00.0: could not probe fw (-12) Repackage the BDF file after renaming relevant fields and files to allow for the Wi-Fi interface to start again. Fixes: 80d34d9d593 ("ipq40xx: document pcie wifi chip on the GL.Inet GL-B2200") CC: Christian Lamparter CC: Robert Marko Reviewed-by: Robert Marko Signed-off-by: Enrico Mioso --- .../ipq-wifi/board-glinet_gl-b2200.qca9888 | Bin 12200 -> 12164 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/package/firmware/ipq-wifi/board-glinet_gl-b2200.qca9888 b/package/firmware/ipq-wifi/board-glinet_gl-b2200.qca9888 index 4f0a521f35935d4be1fb01b66dd9954a48eade52..f0a493ace340de0fe84d89d46cc07209df1b6883 100644 GIT binary patch delta 79 zcmZ1x-x5DT!X-nW0SwH5WKwCdZ9#ITPEu~BZgNIufo^7stpS*ql%H6X0^%B)>69fF YWhUm8*t+}ZIvE)m806+|Y|zjL0EmDWzyJUM delta 115 zcmZpPUlBh+BBMv20Ssb*WKwCdZ9#ITPFZSRN`8^8p_xUpPD*N7W^$^nfq|)+PH|~c qab Date: Sat, 16 Apr 2022 15:10:39 +0200 Subject: [PATCH 68/75] selinux-policy: update to version 1.1 try to clean up some labeling inconsistencies iwinfo loose ends ucode loose ends Makefile: adjust mintesttgt (adds blockmount/blockd) nftables: reads inherited netifd pipe ucode: reads inherited netifd pipes mountroot: fowner sandbox: writes inherited dropbear pipes unbound related to /tmp/etc/ssl unbound loose ends adds a sslconftmpfile for /tmp/etc/ssl README: maintain a wish list in the README iwinfo: netifd forgot write gptfdisk loose ends iwinfo: netifd wpad reads/writes inherited netifd fifo files netifd (mac80211.sh) executes iwinfo luci: executes wireguard luci-cgi: audits xtables execute access rcuhttpd: lists ssl certfile dirs iwinfo, wifi,nftables usage of ttyd pty if available urandomseed: seedrng needs cap_sys_admin iwinfo iwinfo, nftables and some chronyd rules related to ntp nts server nftables, wifi and adds iwinfo skel nftables, rpcd, ucode nftables, ucode and seedrng ucode, fw3/nftables, luci adds ucode skel and some fw3/nftables related urandomseed: some seedrng rules fw3 adds some support for fw4 urandomseed: /etc/seedrng is for seed.credit hotplugcal: runs ucode which is interpreter like adds a nftables skeleton and makes xtables optional agent: allow all agents to write inherited dropbear pipes urandomseed: this seems to be replaced by seedrng kmodloader: label /etc/modules.conf kmodloader.conffile Revert "shelexecfile: remove auditallow rule" Makefile: sort the modules to process by secilc Moves back to git.defensec.nl unbound odhcpd (ip) reads net proc tcp dump shelexecfile: remove auditallow rule rrd.cil: fixes indent Target rddtool from cgi-io instead of runnit it without transition rrd.cil related rrd, rpcd, cgiio clean ups related to luci-app-statistics Rules for rrd files and luci-statistics unboundcontrol ordering Several missing permissions blockmount, dnsmasq, hotplugcall, rpcd, unbound adds mctp_socket (linux 5.15) ip: forgot tc-tiny type transition to go along with the fc spec ip: adds a fc spec for tc-tiny (called by sqm) adds ttyACM fc spec and various assorted loose ends .gitattributes: do not export the github workflows workflow use selinux 3.3 project moved back to https://git.defensec.nl/selinux-policy.git Signed-off-by: Dominick Grift --- package/system/selinux-policy/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/system/selinux-policy/Makefile b/package/system/selinux-policy/Makefile index 0b85920170..10eff7be57 100644 --- a/package/system/selinux-policy/Makefile +++ b/package/system/selinux-policy/Makefile @@ -7,9 +7,9 @@ include $(TOPDIR)/rules.mk PKG_NAME:=selinux-policy PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/DefenSec/selinux-policy -PKG_VERSION:=1.0 -PKG_MIRROR_HASH:=2358a064d1231d39e6292d646e1a38898d949b8bef6558ac1e0992d3b5bca33f +PKG_SOURCE_URL:=https://git.defensec.nl/selinux-policy.git +PKG_VERSION:=1.1 +PKG_MIRROR_HASH:=657ec1ff51ab946753fb3559384511a536ac1e018691f3e49cbab21c55d23e08 PKG_SOURCE_VERSION:=v$(PKG_VERSION) PKG_BUILD_DEPENDS:=secilc/host policycoreutils/host From 7b07c3cff57f057d6780d34adeb23c06123732db Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 2 May 2022 21:07:16 +0100 Subject: [PATCH 69/75] base-files: simplify restorecon logic Remove forgotten redundant selinuxenabled call and skip the whole thing in case $IPKG_INSTROOT is set as labels are anyway applied only later on in fakeroot when squashfs is created. Fixes: 6d7272852e ("base-files: add missing $IPKG_INSTROOT to restorecon call") Signed-off-by: Daniel Golle --- package/base-files/files/lib/functions.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/base-files/files/lib/functions.sh b/package/base-files/files/lib/functions.sh index da2dd5b346..4b1b838572 100644 --- a/package/base-files/files/lib/functions.sh +++ b/package/base-files/files/lib/functions.sh @@ -386,8 +386,8 @@ group_add_user() { echo "$grp" | grep -q ":$" && delim="" [ -n "$IPKG_INSTROOT" ] || lock /var/lock/passwd sed -i "s/$grp/$grp$delim$2/g" ${IPKG_INSTROOT}/etc/group - if [ -x /usr/sbin/selinuxenabled ] && selinuxenabled; then - selinuxenabled 2>/dev/null && restorecon ${IPKG_INSTROOT}/etc/group + if [ -z "$IPKG_INSTROOT" ] && [ -x /usr/sbin/selinuxenabled ] && selinuxenabled; then + restorecon /etc/group fi [ -n "$IPKG_INSTROOT" ] || lock -u /var/lock/passwd } From fb011118664756ee33bf16a39bf6e73d02cc2d3f Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 3 May 2022 02:07:40 +0100 Subject: [PATCH 70/75] procd: update to git HEAD 652e6df init: restore SELinux labels after policy is loaded Signed-off-by: Daniel Golle --- package/system/procd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/system/procd/Makefile b/package/system/procd/Makefile index bcc10444c0..5a355ce377 100644 --- a/package/system/procd/Makefile +++ b/package/system/procd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git -PKG_MIRROR_HASH:=28630389c91e6025a718abcbd100534d72446afce3c5956f94d6972e56ed7c5f -PKG_SOURCE_DATE:=2022-04-13 -PKG_SOURCE_VERSION:=eb03f03105a857a0b7310e4c93bff46aa29f3a40 +PKG_MIRROR_HASH:=26c4dd6cfb27ef8f5ef55f7c8d4622ff91e3490917e4fb03f54b138737113251 +PKG_SOURCE_DATE:=2022-05-03 +PKG_SOURCE_VERSION:=652e6df06f8413f19a4786a275862cfe76628093 CMAKE_INSTALL:=1 PKG_LICENSE:=GPL-2.0 From 4509b790f09183b2ac757371f6d79052f232e4cd Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 3 May 2022 02:10:37 +0100 Subject: [PATCH 71/75] fstools: update to git HEAD 9e11b37 fstools: remove SELinux restorecon hack Signed-off-by: Daniel Golle --- package/system/fstools/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/system/fstools/Makefile b/package/system/fstools/Makefile index eb7d5ac635..3b10ee7f1f 100644 --- a/package/system/fstools/Makefile +++ b/package/system/fstools/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/fstools.git -PKG_MIRROR_HASH:=e63ad1c66ec31b45d815112bf3e25b3b0ea58962323624192a658a84b004a30d -PKG_SOURCE_DATE:=2022-05-01 -PKG_SOURCE_VERSION:=0917d223d14bca9edd3f8c91e2828a7a960a21d1 +PKG_MIRROR_HASH:=c6239a75f6a3b5b010a48d195006550b0e2154f5b22611484c4979f552c0da7d +PKG_SOURCE_DATE:=2022-05-03 +PKG_SOURCE_VERSION:=9e11b3723ce30b9b8c94ad7d15072a10cf13c0b4 CMAKE_INSTALL:=1 PKG_LICENSE:=GPL-2.0 From 51c442c265a8661427441193e7dc585b1539a915 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 4 May 2022 01:32:17 +0100 Subject: [PATCH 72/75] uqmi: update to git HEAD 56cb2d4 nas: add decoding of cell_id 9a9019a uqmi: wms - added storage to read text messages Signed-off-by: Daniel Golle --- package/network/utils/uqmi/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/utils/uqmi/Makefile b/package/network/utils/uqmi/Makefile index 088543e7e6..c4ca98012a 100644 --- a/package/network/utils/uqmi/Makefile +++ b/package/network/utils/uqmi/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/uqmi.git -PKG_SOURCE_DATE:=2022-03-12 -PKG_SOURCE_VERSION:=44dd095794a5327611d0ee1a58b0a6333d397b64 -PKG_MIRROR_HASH:=1f7890c659981e1da5c6d73911c30e24722818ff52d58f41d80cc96b62d53311 +PKG_SOURCE_DATE:=2022-05-04 +PKG_SOURCE_VERSION:=56cb2d4056fef132ccf78dfb6f3074ae5d109992 +PKG_MIRROR_HASH:=cc832b5318805df8c8387a3650f250dee72d5f1dbda4e4866b5503e186b2210c PKG_MAINTAINER:=Matti Laakso PKG_LICENSE:=GPL-2.0 From 2f484aeff5fe5ba3a832f98ca409adde3257e832 Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Mon, 25 Apr 2022 21:43:50 +0200 Subject: [PATCH 73/75] ltq-atm/ltq-ptm: avoid unnecessary build dependencies Right now, both ltq-adsl-mei and ltq-vdsl-mei are always built, even when they aren't necessary for the selected variant. This can cause the build to fail, for example ltq-vdsl-mei doesn't build successfully here on xway target due to the vectoring callback. Make these dependencies conditional on the specific package variants, so they are only built when actually needed. Signed-off-by: Jan Hoffmann Tested-by: Martin Blumenstingl --- package/kernel/lantiq/ltq-atm/Makefile | 13 +++++++++---- package/kernel/lantiq/ltq-ptm/Makefile | 4 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/package/kernel/lantiq/ltq-atm/Makefile b/package/kernel/lantiq/ltq-atm/Makefile index f675269ca3..b81f3bb293 100644 --- a/package/kernel/lantiq/ltq-atm/Makefile +++ b/package/kernel/lantiq/ltq-atm/Makefile @@ -22,13 +22,18 @@ define KernelPackage/ltq-atm-template URL:=http://www.lantiq.com/ VARIANT:=$(1) DEPENDS:=@$(2) +kmod-atm +br2684ctl +ifeq ($(1),vr9) + DEPENDS+= +PACKAGE_kmod-ltq-atm-$(1):kmod-ltq-vdsl-vr9-mei +else + DEPENDS+= +PACKAGE_kmod-ltq-atm-$(1):kmod-ltq-adsl-$(1)-mei +endif FILES:=$(PKG_BUILD_DIR)/ltq_atm_$(1).ko endef -KernelPackage/ltq-atm-danube=$(call KernelPackage/ltq-atm-template,danube,(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy) +kmod-ltq-adsl-danube-mei) -KernelPackage/ltq-atm-ar9=$(call KernelPackage/ltq-atm-template,ar9,TARGET_lantiq_xway +kmod-ltq-adsl-ar9-mei) -KernelPackage/ltq-atm-ase=$(call KernelPackage/ltq-atm-template,ase,TARGET_lantiq_ase +kmod-ltq-adsl-ase-mei) -KernelPackage/ltq-atm-vr9=$(call KernelPackage/ltq-atm-template,vr9,TARGET_lantiq_xrx200 +kmod-ltq-vdsl-vr9-mei) +KernelPackage/ltq-atm-danube=$(call KernelPackage/ltq-atm-template,danube,(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy)) +KernelPackage/ltq-atm-ar9=$(call KernelPackage/ltq-atm-template,ar9,TARGET_lantiq_xway) +KernelPackage/ltq-atm-ase=$(call KernelPackage/ltq-atm-template,ase,TARGET_lantiq_ase) +KernelPackage/ltq-atm-vr9=$(call KernelPackage/ltq-atm-template,vr9,TARGET_lantiq_xrx200) define Build/Configure endef diff --git a/package/kernel/lantiq/ltq-ptm/Makefile b/package/kernel/lantiq/ltq-ptm/Makefile index 33a23d6853..b726cb1560 100644 --- a/package/kernel/lantiq/ltq-ptm/Makefile +++ b/package/kernel/lantiq/ltq-ptm/Makefile @@ -24,9 +24,9 @@ define KernelPackage/ltq-ptm-template VARIANT:=$(1) DEPENDS:=@TARGET_lantiq_$(2) ifeq ($(1),vr9) - DEPENDS+= +kmod-ltq-vdsl-vr9-mei + DEPENDS+= +PACKAGE_kmod-ltq-ptm-$(1):kmod-ltq-vdsl-vr9-mei else - DEPENDS+= +kmod-ltq-adsl-$(1)-mei + DEPENDS+= +PACKAGE_kmod-ltq-ptm-$(1):kmod-ltq-adsl-$(1)-mei endif ifeq ($(1),ase) DEPENDS+=@BROKEN From db4bf4b968c0da035d98e7771fc993af9d6f742b Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Mon, 25 Apr 2022 21:52:39 +0200 Subject: [PATCH 74/75] ltq-vdsl/ltq-adsl: fix elapsed time calculation The driver maintains elapsed times by repeatedly accumulating the time since the previous update in a loop. For the elapsed showtime time, the time difference is truncated to seconds before adding it, leading to a sizable error over time. Move the truncation to before calculation of the time difference in order to remove this error. Also maintain the total elapsed time in the same way in full seconds, to prevent the unsigned 32-bit counter from wrapping around after about 50 days. Testing on a VR9 device shows that the reported line uptime now matches the actual elapsed wall time. The ADSL variant is only compile-tested, but it should also work as the relevant code is identical. Signed-off-by: Jan Hoffmann Tested-by: Martin Blumenstingl --- package/kernel/lantiq/ltq-adsl/Makefile | 2 +- .../patches/200-fix-elapsed-time.patch | 122 ++++++++++++++++++ package/kernel/lantiq/ltq-vdsl/Makefile | 2 +- .../patches/200-fix-elapsed-time.patch | 122 ++++++++++++++++++ 4 files changed, 246 insertions(+), 2 deletions(-) create mode 100644 package/kernel/lantiq/ltq-adsl/patches/200-fix-elapsed-time.patch create mode 100644 package/kernel/lantiq/ltq-vdsl/patches/200-fix-elapsed-time.patch diff --git a/package/kernel/lantiq/ltq-adsl/Makefile b/package/kernel/lantiq/ltq-adsl/Makefile index 31874acaca..ac96674933 100644 --- a/package/kernel/lantiq/ltq-adsl/Makefile +++ b/package/kernel/lantiq/ltq-adsl/Makefile @@ -10,7 +10,7 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=ltq-adsl PKG_VERSION:=3.24.4.4 -PKG_RELEASE:=3 +PKG_RELEASE:=4 PKG_SOURCE:=drv_dsl_cpe_api_danube-$(PKG_VERSION).tar.gz PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/ltq-dsl-$(BUILD_VARIANT)/drv_dsl_cpe_api-$(PKG_VERSION) PKG_SOURCE_URL:=@OPENWRT diff --git a/package/kernel/lantiq/ltq-adsl/patches/200-fix-elapsed-time.patch b/package/kernel/lantiq/ltq-adsl/patches/200-fix-elapsed-time.patch new file mode 100644 index 0000000000..42ec214371 --- /dev/null +++ b/package/kernel/lantiq/ltq-adsl/patches/200-fix-elapsed-time.patch @@ -0,0 +1,122 @@ +--- a/src/include/drv_dsl_cpe_pm_core.h ++++ b/src/include/drv_dsl_cpe_pm_core.h +@@ -1525,9 +1525,9 @@ typedef struct + DSL_boolean_t bShowtimeProcessingStart; + /** Showtime reached flag*/ + DSL_boolean_t bShowtimeInvTrigger; +- /** Current Showtime synchronization time to be used, (msec) */ ++ /** Current Showtime synchronization time to be used, (sec) */ + DSL_uint32_t nCurrShowtimeTime; +- /** Showtime synchronization time to be used, (msec) */ ++ /** Showtime synchronization time to be used, (sec) */ + DSL_uint32_t nElapsedShowtimeTime; + /** Actual Line state*/ + DSL_LineStateValue_t nLineState; +--- a/src/pm/drv_dsl_cpe_api_pm.c ++++ b/src/pm/drv_dsl_cpe_api_pm.c +@@ -1445,7 +1445,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersTo + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection); + +@@ -1501,7 +1501,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersEx + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL_EXT(pCounters->nChannel); + +@@ -2418,7 +2418,7 @@ DSL_Error_t DSL_DRV_PM_DataPathCountersT + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pDpCounters = DSL_DRV_PM_PTR_DATAPATH_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection); + +@@ -3190,7 +3190,7 @@ DSL_Error_t DSL_DRV_PM_DataPathFailureCo + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pDpCounters = DSL_DRV_PM_PTR_DATAPATH_FAILURE_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection); + +@@ -3950,7 +3950,7 @@ DSL_Error_t DSL_DRV_PM_LineSecCountersTo + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pLineCounters = DSL_DRV_PM_PTR_LINE_SEC_COUNTERS_TOTAL(pCounters->nDirection); + +@@ -4602,7 +4602,7 @@ DSL_Error_t DSL_DRV_PM_LineInitCountersT + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pLinitCounters = DSL_DRV_PM_PTR_LINE_INIT_COUNTERS_TOTAL(); + +@@ -5131,7 +5131,7 @@ DSL_Error_t DSL_DRV_PM_LineEventShowtime + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pLfCounters = DSL_DRV_PM_PTR_LINE_EVENT_SHOWTIME_COUNTERS_TOTAL(pCounters->nDirection); + +@@ -5670,7 +5670,7 @@ DSL_Error_t DSL_DRV_PM_ReTxCountersTotal + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pReTxCounters = DSL_DRV_PM_PTR_RETX_COUNTERS_TOTAL(pCounters->nDirection); + +--- a/src/pm/drv_dsl_cpe_pm_core.c ++++ b/src/pm/drv_dsl_cpe_pm_core.c +@@ -61,6 +61,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp + { + DSL_Error_t nErrCode = DSL_SUCCESS; + DSL_uint32_t msecTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE, ++ secTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE/DSL_PM_MSEC, + nCurrMsTime = 0; + #ifdef INCLUDE_DSL_CPE_PM_HISTORY + DSL_uint32_t nCurrSysTime = 0, nPrevElapsedTime = 0; +@@ -100,10 +101,13 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp + { + /* Get elapsed time [msec] since the last entry*/ + msecTimeFrame = nCurrMsTime - DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck; ++ ++ /* Get elapsed time [sec] since the last entry*/ ++ secTimeFrame = (nCurrMsTime/DSL_PM_MSEC) - (DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck/DSL_PM_MSEC); + } + + /* Get Total Elapsed Time Since the PM module startup*/ +- DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += msecTimeFrame; ++ DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += secTimeFrame; + + /* Set last time check to the current time*/ + DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck = nCurrMsTime; +@@ -141,7 +145,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp + else + { + /* Update current showtime elapsed time*/ +- DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime += (msecTimeFrame/DSL_PM_MSEC); ++ DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime += secTimeFrame; + DSL_DRV_PM_CONTEXT(pContext)->nElapsedShowtimeTime = + DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime; + } diff --git a/package/kernel/lantiq/ltq-vdsl/Makefile b/package/kernel/lantiq/ltq-vdsl/Makefile index 248615fb59..da924e861e 100644 --- a/package/kernel/lantiq/ltq-vdsl/Makefile +++ b/package/kernel/lantiq/ltq-vdsl/Makefile @@ -9,7 +9,7 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=ltq-vdsl-vr9 PKG_VERSION:=4.17.18.6 -PKG_RELEASE:=6 +PKG_RELEASE:=7 PKG_BASE_NAME:=drv_dsl_cpe_api PKG_SOURCE:=$(PKG_BASE_NAME)_vrx-$(PKG_VERSION).tar.gz diff --git a/package/kernel/lantiq/ltq-vdsl/patches/200-fix-elapsed-time.patch b/package/kernel/lantiq/ltq-vdsl/patches/200-fix-elapsed-time.patch new file mode 100644 index 0000000000..3ec85460b2 --- /dev/null +++ b/package/kernel/lantiq/ltq-vdsl/patches/200-fix-elapsed-time.patch @@ -0,0 +1,122 @@ +--- a/src/include/drv_dsl_cpe_pm_core.h ++++ b/src/include/drv_dsl_cpe_pm_core.h +@@ -1552,9 +1552,9 @@ typedef struct + DSL_boolean_t bShowtimeProcessingStart; + /** Showtime reached flag*/ + DSL_boolean_t bShowtimeInvTrigger; +- /** Current Showtime synchronization time to be used, (msec) */ ++ /** Current Showtime synchronization time to be used, (sec) */ + DSL_uint32_t nCurrShowtimeTime; +- /** Showtime synchronization time to be used, (msec) */ ++ /** Showtime synchronization time to be used, (sec) */ + DSL_uint32_t nElapsedShowtimeTime; + /** Actual Line state*/ + DSL_LineStateValue_t nLineState; +--- a/src/pm/drv_dsl_cpe_api_pm.c ++++ b/src/pm/drv_dsl_cpe_api_pm.c +@@ -1475,7 +1475,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersTo + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection); + +@@ -1535,7 +1535,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersEx + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL_EXT(pCounters->nChannel); + +@@ -2518,7 +2518,7 @@ DSL_Error_t DSL_DRV_PM_DataPathCountersT + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pDpCounters = DSL_DRV_PM_PTR_DATAPATH_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection); + +@@ -3352,7 +3352,7 @@ DSL_Error_t DSL_DRV_PM_DataPathFailureCo + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pDpCounters = DSL_DRV_PM_PTR_DATAPATH_FAILURE_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection); + +@@ -4130,7 +4130,7 @@ DSL_Error_t DSL_DRV_PM_LineSecCountersTo + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pLineCounters = DSL_DRV_PM_PTR_LINE_SEC_COUNTERS_TOTAL(pCounters->nDirection); + +@@ -4787,7 +4787,7 @@ DSL_Error_t DSL_DRV_PM_LineInitCountersT + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pLinitCounters = DSL_DRV_PM_PTR_LINE_INIT_COUNTERS_TOTAL(); + +@@ -5240,7 +5240,7 @@ DSL_Error_t DSL_DRV_PM_LineEventShowtime + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pLfCounters = DSL_DRV_PM_PTR_LINE_EVENT_SHOWTIME_COUNTERS_TOTAL(pCounters->nDirection); + +@@ -5720,7 +5720,7 @@ DSL_Error_t DSL_DRV_PM_ReTxCountersTotal + } + + /* Fill Total Counters elapsed time*/ +- pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC; ++ pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime; + + pReTxCounters = DSL_DRV_PM_PTR_RETX_COUNTERS_TOTAL(pCounters->nDirection); + +--- a/src/pm/drv_dsl_cpe_pm_core.c ++++ b/src/pm/drv_dsl_cpe_pm_core.c +@@ -60,6 +60,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp + { + DSL_Error_t nErrCode = DSL_SUCCESS; + DSL_uint32_t msecTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE, ++ secTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE/DSL_PM_MSEC, + nCurrMsTime = 0; + #ifdef INCLUDE_DSL_CPE_PM_HISTORY + DSL_uint32_t nCurrSysTime = 0, nPrevElapsedTime = 0; +@@ -99,10 +100,13 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp + { + /* Get elapsed time [msec] since the last entry*/ + msecTimeFrame = nCurrMsTime - DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck; ++ ++ /* Get elapsed time [sec] since the last entry*/ ++ secTimeFrame = (nCurrMsTime/DSL_PM_MSEC) - (DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck/DSL_PM_MSEC); + } + + /* Get Total Elapsed Time Since the PM module startup*/ +- DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += msecTimeFrame; ++ DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += secTimeFrame; + + /* Set last time check to the current time*/ + DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck = nCurrMsTime; +@@ -140,7 +144,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp + else + { + /* Update current showtime elapsed time*/ +- DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime += (msecTimeFrame/DSL_PM_MSEC); ++ DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime += secTimeFrame; + DSL_DRV_PM_CONTEXT(pContext)->nElapsedShowtimeTime = + DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime; + } From 1daaef31b35201a9c15a2084e25dac41b48c1867 Mon Sep 17 00:00:00 2001 From: Jan Hoffmann Date: Wed, 27 Apr 2022 19:40:50 +0200 Subject: [PATCH 75/75] ltq-vdsl-app: disconnect when service is stopped Stop the connection when the control daemon is terminated. The code is a modified version of the termination routine in version 4.23.1 of the daemon (which doesn't support VR9 modems anymore). This could also be implemented by calling the acos and acs commands via dsl_cpe_pipe.sh in the init script. However, doing it in the daemon itself has the advantage of also working if it is terminated in another way (for example during sysupgrade). Signed-off-by: Jan Hoffmann Tested-by: Martin Blumenstingl --- .../ltq-vdsl-app/patches/200-autoboot.patch | 75 +++++++++++++++++++ .../ltq-vdsl-app/patches/201-sigterm.patch | 2 +- .../ltq-vdsl-app/patches/300-ubus.patch | 4 +- 3 files changed, 78 insertions(+), 3 deletions(-) diff --git a/package/network/config/ltq-vdsl-app/patches/200-autoboot.patch b/package/network/config/ltq-vdsl-app/patches/200-autoboot.patch index 5b882bf30f..cc6feb94aa 100644 --- a/package/network/config/ltq-vdsl-app/patches/200-autoboot.patch +++ b/package/network/config/ltq-vdsl-app/patches/200-autoboot.patch @@ -1,3 +1,10 @@ +This enables automatic connection after the control daemon is started, +and also stops the connection on termination. + +Using the autoboot restart command is necessary because the stop command +doesn't actually stop the connection, and would also leave the driver in +a state where an explicit start command is necessary to connect again. + --- a/src/dsl_cpe_init_cfg.c +++ b/src/dsl_cpe_init_cfg.c @@ -27,7 +27,7 @@ DSL_InitData_t gInitCfgData = @@ -9,3 +16,71 @@ DSL_CPE_AUTOBOOT_CFG_SET(DSL_FALSE, DSL_FALSE, DSL_FALSE), DSL_CPE_TEST_MODE_CTRL_SET(DSL_TESTMODE_DISABLE), DSL_CPE_LINE_ACTIVATE_CTRL_SET(DSL_G997_INHIBIT_LDSF, DSL_G997_INHIBIT_ACSF, DSL_G997_NORMAL_STARTUP), +--- a/src/dsl_cpe_control.c ++++ b/src/dsl_cpe_control.c +@@ -6515,10 +6515,13 @@ DSL_CPE_STATIC void DSL_CPE_Termination + DSL_CPE_STATIC DSL_void_t DSL_CPE_Termination (void) + { + #ifdef INCLUDE_DSL_CPE_CLI_SUPPORT +- DSL_int_t nDevice = 0; + DSL_char_t buf[32] = "quit"; + #endif + ++ DSL_Error_t nRet = DSL_SUCCESS; ++ DSL_int_t nDevice = 0; ++ DSL_AutobootConfig_t sAutobootCfg; ++ DSL_AutobootControl_t sAutobootCtl; + DSL_CPE_Control_Context_t *pCtrlCtx; + + pCtrlCtx = DSL_CPE_GetGlobalContext(); +@@ -6527,6 +6530,50 @@ DSL_CPE_STATIC DSL_void_t DSL_CPE_Termi + pCtrlCtx->bRun = DSL_FALSE; + } + ++ for (nDevice = 0; nDevice < DSL_CPE_MAX_DSL_ENTITIES; ++nDevice) ++ { ++ g_bWaitBeforeConfigWrite[nDevice] = DSL_TRUE; ++ g_bWaitBeforeLinkActivation[nDevice] = DSL_TRUE; ++ g_bWaitBeforeRestart[nDevice] = DSL_TRUE; ++ ++ g_bAutoContinueWaitBeforeConfigWrite[nDevice] = DSL_FALSE; ++ g_bAutoContinueWaitBeforeLinkActivation[nDevice] = DSL_FALSE; ++ g_bAutoContinueWaitBeforeRestart[nDevice] = DSL_FALSE; ++ ++ memset(&sAutobootCfg, 0x0, sizeof(DSL_AutobootConfig_t)); ++ sAutobootCfg.data.nStateMachineOptions.bWaitBeforeConfigWrite = DSL_TRUE; ++ sAutobootCfg.data.nStateMachineOptions.bWaitBeforeLinkActivation = DSL_TRUE; ++ sAutobootCfg.data.nStateMachineOptions.bWaitBeforeRestart = DSL_TRUE; ++ ++ nRet = (DSL_Error_t)DSL_CPE_Ioctl( ++ DSL_CPE_GetGlobalContext()->fd[nDevice], ++ DSL_FIO_AUTOBOOT_CONFIG_SET, (DSL_int_t)&sAutobootCfg); ++ ++ if (nRet < DSL_SUCCESS) ++ { ++ DSL_CCA_DEBUG(DSL_CCA_DBG_ERR, (DSL_CPE_PREFIX ++ "Autoboot configuration for device (%d) failed!, nRet = %d!" ++ DSL_CPE_CRLF, nDevice, sAutobootCtl.accessCtl.nReturn)); ++ } ++ ++ memset(&sAutobootCtl, 0, sizeof(DSL_AutobootControl_t)); ++ sAutobootCtl.data.nCommand = DSL_AUTOBOOT_CTRL_RESTART; ++ ++ nRet = (DSL_Error_t)DSL_CPE_Ioctl( ++ DSL_CPE_GetGlobalContext()->fd[nDevice], ++ DSL_FIO_AUTOBOOT_CONTROL_SET, (DSL_int_t)&sAutobootCtl); ++ ++ if (nRet < DSL_SUCCESS) ++ { ++ DSL_CCA_DEBUG(DSL_CCA_DBG_ERR, (DSL_CPE_PREFIX ++ "Autoboot restart for device (%d) failed!, nRet = %d!" ++ DSL_CPE_CRLF, nDevice, sAutobootCtl.accessCtl.nReturn)); ++ } ++ } ++ ++ DSL_CCA_DEBUG(DSL_CCA_DBG_MSG, (DSL_CPE_PREFIX ++ "Autoboot restart executed" DSL_CPE_CRLF)); ++ + #ifdef INCLUDE_DSL_CPE_CLI_SUPPORT + for (nDevice = 0; nDevice < DSL_CPE_MAX_DSL_ENTITIES; nDevice++) + { diff --git a/package/network/config/ltq-vdsl-app/patches/201-sigterm.patch b/package/network/config/ltq-vdsl-app/patches/201-sigterm.patch index 68a416ce24..4e97835983 100644 --- a/package/network/config/ltq-vdsl-app/patches/201-sigterm.patch +++ b/package/network/config/ltq-vdsl-app/patches/201-sigterm.patch @@ -9,7 +9,7 @@ { DSL_CCA_DEBUG(DSL_CCA_DBG_MSG, (DSL_CPE_PREFIX "terminated" DSL_CPE_CRLF)); DSL_CPE_Termination (); -@@ -6756,6 +6756,7 @@ DSL_int_t dsl_cpe_daemon ( +@@ -6803,6 +6803,7 @@ DSL_int_t dsl_cpe_daemon ( #ifndef RTEMS signal (SIGINT, DSL_CPE_TerminationHandler); diff --git a/package/network/config/ltq-vdsl-app/patches/300-ubus.patch b/package/network/config/ltq-vdsl-app/patches/300-ubus.patch index f218ea2208..d257ca2fc4 100644 --- a/package/network/config/ltq-vdsl-app/patches/300-ubus.patch +++ b/package/network/config/ltq-vdsl-app/patches/300-ubus.patch @@ -10,7 +10,7 @@ DSL_char_t *g_sFirmwareName1 = DSL_NULL; DSL_FirmwareFeatures_t g_nFwFeatures1 = {DSL_FW_XDSLMODE_CLEANED, DSL_FW_XDSLFEATURE_CLEANED, DSL_FW_XDSLFEATURE_CLEANED}; -@@ -6759,6 +6762,8 @@ DSL_int_t dsl_cpe_daemon ( +@@ -6806,6 +6809,8 @@ DSL_int_t dsl_cpe_daemon ( signal (SIGTERM, DSL_CPE_TerminationHandler); #endif /* RTEMS*/ @@ -19,7 +19,7 @@ /* Open DSL_CPE_MAX_DSL_ENTITIES devices*/ for (nDevice = 0; nDevice < DSL_CPE_MAX_DSL_ENTITIES; nDevice++) { -@@ -7213,6 +7218,7 @@ DSL_int_t dsl_cpe_daemon ( +@@ -7260,6 +7265,7 @@ DSL_int_t dsl_cpe_daemon ( #endif /* INCLUDE_DSL_CPE_CLI_SUPPORT */ DSL_CPE_CONTROL_EXIT: