From 7850e197670afff38426075953ba6a71f0f431c8 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 23 Sep 2024 00:47:40 +0200 Subject: [PATCH 01/11] linux-firmware: Update to version 20240909 This updates the following firmware files: amd64-microcode/lib/firmware/amd-ucode/microcode_amd_fam17h.bin amd64-microcode/lib/firmware/amd-ucode/microcode_amd_fam19h.bin amdgpu-firmware/lib/firmware/amdgpu/* ar3k-firmware/lib/firmware/qca/hpnv21.bin ar3k-firmware/lib/firmware/qca/hpnv21g.bin ar3k-firmware/lib/firmware/qca/nvm_usb_00130201.bin ar3k-firmware/lib/firmware/qca/nvm_usb_00130201_010a.bin ar3k-firmware/lib/firmware/qca/nvm_usb_00130201_010b.bin ar3k-firmware/lib/firmware/qca/nvm_usb_00130201_gf.bin ar3k-firmware/lib/firmware/qca/nvm_usb_00130201_gf_010a.bin ar3k-firmware/lib/firmware/qca/nvm_usb_00130201_gf_010b.bin ar3k-firmware/lib/firmware/qca/rampatch_usb_00130201.bin ath11k-firmware-wcn6855/lib/firmware/ath11k/WCN6855/hw2.0/amss.bin ath11k-firmware-wcn6855/lib/firmware/ath11k/WCN6855/hw2.0/board-2.bin ath11k-firmware-wcn6855/lib/firmware/ath11k/WCN6855/hw2.0/m3.bin ath11k-firmware-wcn6855/lib/firmware/ath11k/WCN6855/hw2.1/amss.bin ath11k-firmware-wcn6855/lib/firmware/ath11k/WCN6855/hw2.1/board-2.bin ath11k-firmware-wcn6855/lib/firmware/ath11k/WCN6855/hw2.1/m3.bin ath12k-firmware-wcn7850/lib/firmware/ath12k/WCN7850/hw2.0/board-2.bin ibt-firmware/lib/firmware/intel/ibt-0040-0041.sfi ibt-firmware/lib/firmware/intel/ibt-0040-4150.sfi ibt-firmware/lib/firmware/intel/ibt-0041-0041.sfi ibt-firmware/lib/firmware/intel/ibt-0180-0041.sfi ibt-firmware/lib/firmware/intel/ibt-0180-1050.sfi ibt-firmware/lib/firmware/intel/ibt-0180-4150.sfi ibt-firmware/lib/firmware/intel/ibt-0291-0291.sfi ibt-firmware/lib/firmware/intel/ibt-1040-0041.sfi ibt-firmware/lib/firmware/intel/ibt-1040-1050.sfi ibt-firmware/lib/firmware/intel/ibt-1040-4150.sfi ibt-firmware/lib/firmware/intel/ibt-17-16-1.sfi ibt-firmware/lib/firmware/intel/ibt-17-2.sfi ibt-firmware/lib/firmware/intel/ibt-18-16-1.sfi ibt-firmware/lib/firmware/intel/ibt-18-2.sfi intel-igpu-firmware-guc/lib/firmware/i915/adlp_guc_70.bin intel-igpu-firmware-guc/lib/firmware/i915/dg1_guc_70.bin intel-igpu-firmware-guc/lib/firmware/i915/dg2_guc_70.bin intel-igpu-firmware-guc/lib/firmware/i915/mtl_guc_70.bin intel-igpu-firmware-guc/lib/firmware/i915/tgl_guc_70.bin intel-igpu-firmware-huc/lib/firmware/i915/dg2_huc_gsc.bin iwlwifi-firmware-ax200/lib/firmware/iwlwifi-cc-a0-77.ucode iwlwifi-firmware-ax201/lib/firmware/iwlwifi-QuZ-a0-hr-b0-77.ucode iwlwifi-firmware-ax210/lib/firmware/iwlwifi-ty-a0-gf-a0.pnvm iwlwifi-firmware-be200/lib/firmware/iwlwifi-gl-c0-fm-c0.pnvm mt7921bt-firmware/lib/firmware/mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin mt7922bt-firmware/lib/firmware/mediatek/BT_RAM_CODE_MT7922_1_1_hdr.bin r8169-firmware/lib/firmware/rtl_nic/rtl8126a-3.fw Link: https://github.com/openwrt/openwrt/pull/16458 Signed-off-by: Hauke Mehrtens --- package/firmware/linux-firmware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile index f256a1efe4..43a9833555 100644 --- a/package/firmware/linux-firmware/Makefile +++ b/package/firmware/linux-firmware/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=linux-firmware -PKG_VERSION:=20240513 +PKG_VERSION:=20240909 PKG_RELEASE:=1 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz -PKG_HASH:=9f05edb99668135d37cedc4fdd18aac2802dc9e4566e086e6c6c2e321f3ecc4e +PKG_HASH:=943fbd19883cf8eadf89e0b22422549db056557b1ecd30a56400615971369671 PKG_MAINTAINER:=Felix Fietkau From 2eb39308c946b99947136e4c841959e0a8c4537d Mon Sep 17 00:00:00 2001 From: John Audia Date: Mon, 23 Sep 2024 08:00:50 -0400 Subject: [PATCH 02/11] x86: generic: disable rust support Add missing ksym CONFIG_RUST Building r27563 without this commit will fail due to this ksym being undefined in the generic config. Build system: x86/64 Build-tested: x86/64/AMD Cezanne Run-tested: x86/64/AMD Cezanne Signed-off-by: John Audia Link: https://github.com/openwrt/openwrt/pull/16464 Signed-off-by: Robert Marko --- target/linux/generic/config-6.6 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/config-6.6 b/target/linux/generic/config-6.6 index d5c40eae91..c8bca0d0ff 100644 --- a/target/linux/generic/config-6.6 +++ b/target/linux/generic/config-6.6 @@ -5146,6 +5146,7 @@ CONFIG_RTC_SYSTOHC_DEVICE="rtc0" # CONFIG_RTL_CARDS is not set # CONFIG_RTS5208 is not set CONFIG_RT_MUTEXES=y +# CONFIG_RUST is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_RV is not set CONFIG_RXKAD=y From 7c9998f7133b0fdc08956634de792ea41a2e0e6a Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 7 Sep 2024 14:11:19 -0700 Subject: [PATCH 03/11] gpio-button-hotplug: use dev_err_probe Avoids having to handle EPROBE_DEFER manually. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/16456 Signed-off-by: Robert Marko --- package/kernel/gpio-button-hotplug/Makefile | 2 +- .../kernel/gpio-button-hotplug/src/gpio-button-hotplug.c | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/package/kernel/gpio-button-hotplug/Makefile b/package/kernel/gpio-button-hotplug/Makefile index 04cbb69ada..5b4085887d 100644 --- a/package/kernel/gpio-button-hotplug/Makefile +++ b/package/kernel/gpio-button-hotplug/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=gpio-button-hotplug -PKG_RELEASE:=3 +PKG_RELEASE:=4 PKG_LICENSE:=GPL-2.0 include $(INCLUDE_DIR)/package.mk diff --git a/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c b/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c index 17748219e8..de100777f2 100644 --- a/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c +++ b/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c @@ -525,10 +525,9 @@ static int gpio_keys_button_probe(struct platform_device *pdev, button->active_low ? GPIOF_ACTIVE_LOW : 0), desc); if (error) { - if (error != -EPROBE_DEFER) { - dev_err(dev, "unable to claim gpio %d, err=%d\n", - button->gpio, error); - } + dev_err_probe(dev, error, + "unable to claim gpio %d", + button->gpio); goto out; } From 7f46e231eb9864c90db296afea3abd0010b9b5e5 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 23 Sep 2024 18:16:51 +0200 Subject: [PATCH 04/11] generic: phy: aquantia: fix MDI pair property parsing of_property_read_u32 returns -EINVAL when property does not exist, according to the documentation -ENOENT is not a valid return code. So, instead of checking for -ENOENT check for -EINVAL as otherwise the blamed commit breaks AQR probe since it will return -EINVAL during probe. Fixes: cb2a11f49c98 ("generic: phy: aquantia: add pending patch to force MDI pair order") Link: https://github.com/openwrt/openwrt/pull/16466 Signed-off-by: Robert Marko --- .../752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch b/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch index 97e2953a50..f3ae893b32 100644 --- a/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch +++ b/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch @@ -74,7 +74,7 @@ Signed-off-by: Daniel Golle + ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); + + /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ -+ if (ret == -ENOENT) ++ if (ret == -EINVAL) + return 0; + + if (ret) From e05b24175d7a27a7cbbe3e456bb0ceb1e7c47e10 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 23 Sep 2024 13:15:57 +0800 Subject: [PATCH 05/11] rockchip: reorder nanopc t6 patches Reorder nanopc t6 patches to 055 to avoid conflict with nanopi r6c patches. Fixes: 55c46cbabd76 ("rockchip: add FriendlyElec NanoPi R6C") Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/16461 Signed-off-by: Nick Hainke --- ...1-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch} | 0 ...-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch} | 0 ...m64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch} | 0 ...v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch} | 0 ...m64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch} | 0 ...6-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch} | 0 ...6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch} | 0 ...09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch} | 0 ...-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch} | 0 ...1-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch} | 0 ...055-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch} | 0 ...5-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch} | 0 ...-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch} | 0 ...64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch} | 0 14 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/rockchip/patches-6.6/{054-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch => 055-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch => 055-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch => 055-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch => 055-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch => 055-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch => 055-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch => 055-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch => 055-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch => 055-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch => 055-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch => 055-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch => 055-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch => 055-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch} (100%) rename target/linux/rockchip/patches-6.6/{054-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch => 055-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch} (100%) diff --git a/target/linux/rockchip/patches-6.6/054-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/055-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch rename to target/linux/rockchip/patches-6.6/055-01-v6.8-arm64-dts-rockchip-Support-poweroff-on-NanoPC-T6.patch diff --git a/target/linux/rockchip/patches-6.6/054-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch b/target/linux/rockchip/patches-6.6/055-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch rename to target/linux/rockchip/patches-6.6/055-02-v6.9-arm64-dts-rockchip-nanopc-t6-sdmmc-beautification.patch diff --git a/target/linux/rockchip/patches-6.6/054-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch b/target/linux/rockchip/patches-6.6/055-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch rename to target/linux/rockchip/patches-6.6/055-03-v6.9-arm64-dts-rockchip-correct-gpio_pwrctrl1-typo-on-nanopc-t.patch diff --git a/target/linux/rockchip/patches-6.6/054-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch b/target/linux/rockchip/patches-6.6/055-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch rename to target/linux/rockchip/patches-6.6/055-04-v6.9-arm64-dts-rockchip-enable-NanoPC-T6-MiniPCIe-power.patch diff --git a/target/linux/rockchip/patches-6.6/054-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch b/target/linux/rockchip/patches-6.6/055-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch rename to target/linux/rockchip/patches-6.6/055-05-v6.9-arm64-dts-rockchip-add-sdmmc-card-detect-to-the-nanopc-t6.patch diff --git a/target/linux/rockchip/patches-6.6/054-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch b/target/linux/rockchip/patches-6.6/055-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch rename to target/linux/rockchip/patches-6.6/055-06-v6.9-arm64-dts-rockchip-fix-nanopc-t6-sdmmc-regulator.patch diff --git a/target/linux/rockchip/patches-6.6/054-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch b/target/linux/rockchip/patches-6.6/055-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch rename to target/linux/rockchip/patches-6.6/055-08-v6.12-arm64-dts-rockchip-prepare-NanoPC-T6-for-LTS-board.patch diff --git a/target/linux/rockchip/patches-6.6/054-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch b/target/linux/rockchip/patches-6.6/055-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch rename to target/linux/rockchip/patches-6.6/055-09-v6.12-arm64-dts-rockchip-move-NanoPC-T6-parts-to-DTS.patch diff --git a/target/linux/rockchip/patches-6.6/054-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/055-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch rename to target/linux/rockchip/patches-6.6/055-10-v6.12-arm64-dts-rockchip-add-SPI-flash-on-NanoPC-T6.patch diff --git a/target/linux/rockchip/patches-6.6/054-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/055-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch rename to target/linux/rockchip/patches-6.6/055-11-v6.12-arm64-dts-rockchip-add-IR-receiver-to-NanoPC-T6.patch diff --git a/target/linux/rockchip/patches-6.6/054-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/055-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch rename to target/linux/rockchip/patches-6.6/055-12-v6.12-arm64-dts-rockchip-enable-GPU-on-NanoPC-T6.patch diff --git a/target/linux/rockchip/patches-6.6/054-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/055-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch rename to target/linux/rockchip/patches-6.6/055-13-v6.12-arm64-dts-rockchip-enable-USB-C-on-NanoPC-T6.patch diff --git a/target/linux/rockchip/patches-6.6/054-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch b/target/linux/rockchip/patches-6.6/055-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch rename to target/linux/rockchip/patches-6.6/055-14-v6.12-arm64-dts-rockchip-add-Mask-Rom-key-on-NanoPC-T6.patch diff --git a/target/linux/rockchip/patches-6.6/054-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch b/target/linux/rockchip/patches-6.6/055-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/054-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch rename to target/linux/rockchip/patches-6.6/055-15-v6.12-arm64-dts-rockchip-use-correct-fcs-suspend-voltage-selecto.patch From 0c1332d034b8e3f33666dccfe4a78b26df408230 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 23 Sep 2024 13:37:02 +0800 Subject: [PATCH 06/11] uboot-rockchip: add ArmSoM Sige7 support Add support for the ArmSoM Sige7 board. Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/16462 Signed-off-by: Nick Hainke --- package/boot/uboot-rockchip/Makefile | 8 + ...24.10-rc1-backport-upstream-dts-sync.patch | 694 ++++++++++++++++++ ...ckchip-add-ArmSoM-Sige7-Rk3588-board.patch | 257 +++++++ 3 files changed, 959 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/108-v2024.10-rc1-board-rockchip-add-ArmSoM-Sige7-Rk3588-board.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index f6399d374d..a4d81a94e1 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -259,6 +259,13 @@ define U-Boot/rock5b-rk3588 radxa_rock-5b endef +define U-Boot/sige7-rk3588 + $(U-Boot/rk3588/Default) + NAME:=Sige7 + BUILD_DEVICES:= \ + armsom_sige7 +endef + # RK3588S boards @@ -309,6 +316,7 @@ UBOOT_TARGETS := \ rock-3b-rk3568 \ nanopc-t6-rk3588 \ rock5b-rk3588 \ + sige7-rk3588 \ nanopi-r6c-rk3588s \ nanopi-r6s-rk3588s \ rock5a-rk3588s diff --git a/package/boot/uboot-rockchip/patches/000-v2024.10-rc1-backport-upstream-dts-sync.patch b/package/boot/uboot-rockchip/patches/000-v2024.10-rc1-backport-upstream-dts-sync.patch index 4c018ea700..afe651afc8 100644 --- a/package/boot/uboot-rockchip/patches/000-v2024.10-rc1-backport-upstream-dts-sync.patch +++ b/package/boot/uboot-rockchip/patches/000-v2024.10-rc1-backport-upstream-dts-sync.patch @@ -10,6 +10,700 @@ Subject: [PATCH] Squashed 'dts/upstream/' changes from create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6c.dts create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6s.dts +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts +@@ -0,0 +1,691 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ model = "ArmSoM Sige7"; ++ compatible = "armsom,sige7", "rockchip,rk3588"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ dais = <&i2s0_8ch_p0>; ++ label = "rk3588-es8316"; ++ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_g>; ++ ++ led_green: led-0 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led_red: led-1 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ }; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 95 145 195 255>; ++ fan-supply = <&vcc5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ #cooling-cells = <2>; ++ }; ++ ++ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc3v3_pcie30: vcc3v3-pcie30-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ ++ es8316: audio-codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ ++/* phy1 - right ethernet port */ ++&pcie2x1l0 { ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++/* phy2 - WiFi */ ++&pcie2x1l1 { ++ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++/* phy0 - left ethernet port */ ++&pcie2x1l2 { ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_g: led-rgb-g { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_rgb_r: led-rgb-r { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <200000000>; ++ no-sdio; ++ no-mmc; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&spi2 { ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ status = "okay"; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6c.dts @@ -0,0 +1,14 @@ diff --git a/package/boot/uboot-rockchip/patches/108-v2024.10-rc1-board-rockchip-add-ArmSoM-Sige7-Rk3588-board.patch b/package/boot/uboot-rockchip/patches/108-v2024.10-rc1-board-rockchip-add-ArmSoM-Sige7-Rk3588-board.patch new file mode 100644 index 0000000000..7fa4d679e4 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/108-v2024.10-rc1-board-rockchip-add-ArmSoM-Sige7-Rk3588-board.patch @@ -0,0 +1,257 @@ +From 40b573e4f6ed629eab54633f8836a2be5e5aa75a Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Wed, 29 May 2024 01:04:06 +0800 +Subject: [PATCH] board: rockchip: add ArmSoM Sige7 Rk3588 board + +ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by +ArmSoM. + +There are two variants depending on the DRAM size : 8G and 16G. + +Specification: + + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB memory LPDDR4x + Mali G610MC4 GPU + 2x MIPI CSI 2 multiple lanes connector + 64GB/128GB on board eMMC + uSD slot + 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C + 1x HDMI 2.1 output + 2x 2.5 Gbps Ethernet port + 40-pin IO header including UART, SPI and I2C + USB PD over USB Type-C + Size: 92mm x 62mm + +Kernel commit: +81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board) + +Signed-off-by: Jianfeng Liu +Reviewed-by: Kever Yang +--- + MAINTAINERS | 1 + + arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 6 ++ + arch/arm/mach-rockchip/rk3588/Kconfig | 26 ++++++ + board/armsom/sige7-rk3588/Kconfig | 12 +++ + board/armsom/sige7-rk3588/MAINTAINERS | 7 ++ + configs/sige7-rk3588_defconfig | 93 ++++++++++++++++++++ + doc/board/rockchip/rockchip.rst | 1 + + include/configs/sige7-rk3588.h | 15 ++++ + 8 files changed, 161 insertions(+) + create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi + create mode 100644 board/armsom/sige7-rk3588/Kconfig + create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS + create mode 100644 configs/sige7-rk3588_defconfig + create mode 100644 include/configs/sige7-rk3588.h + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -533,6 +533,7 @@ F: arch/arm/include/asm/arch-rockchip/ + F: arch/arm/mach-rockchip/ + F: board/amarula/vyasa-rk3288/ + F: board/anbernic/rgxx3_rk3566/ ++F: board/armsom/sige7-rk3588/ + F: board/chipspark/popmetal_rk3288 + F: board/engicam/px30_core/ + F: board/firefly/ +--- /dev/null ++++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2024 ArmSoM Technology Co., Ltd. ++ */ ++ ++#include "rk3588-u-boot.dtsi" +--- a/arch/arm/mach-rockchip/rk3588/Kconfig ++++ b/arch/arm/mach-rockchip/rk3588/Kconfig +@@ -185,6 +185,31 @@ config TARGET_ROCK5B_RK3588 + USB PD over USB Type-C + Size: 100mm x 72mm (Pico-ITX form factor) + ++config TARGET_SIGE7_RK3588 ++ bool "ArmSoM Sige7 RK3588 board" ++ select BOARD_LATE_INIT ++ help ++ ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) ++ by ArmSoM. ++ ++ There are two variants depending on the DRAM size : 8G and 16G. ++ ++ Specification: ++ ++ Rockchip Rk3588 SoC ++ 4x ARM Cortex-A76, 4x ARM Cortex-A55 ++ 8/16GB memory LPDDR4x ++ Mali G610MC4 GPU ++ 2x MIPI CSI 2 multiple lanes connector ++ 64GB/128GB on board eMMC ++ uSD slot ++ 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C ++ 1x HDMI 2.1 output ++ 2x 2.5 Gbps Ethernet port ++ 40-pin IO header including UART, SPI and I2C ++ USB PD over USB Type-C ++ Size: 92mm x 62mm ++ + config TARGET_QUARTZPRO64_RK3588 + bool "Pine64 QuartzPro64 RK3588 board" + select BOARD_LATE_INIT +@@ -254,6 +279,7 @@ config ROCKCHIP_COMMON_STACK_ADDR + config TEXT_BASE + default 0x00a00000 + ++source "board/armsom/sige7-rk3588/Kconfig" + source "board/edgeble/neural-compute-module-6/Kconfig" + source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" + source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" +--- /dev/null ++++ b/board/armsom/sige7-rk3588/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_SIGE7_RK3588 ++ ++config SYS_BOARD ++ default "sige7-rk3588" ++ ++config SYS_VENDOR ++ default "armsom" ++ ++config SYS_CONFIG_NAME ++ default "sige7-rk3588" ++ ++endif +--- /dev/null ++++ b/board/armsom/sige7-rk3588/MAINTAINERS +@@ -0,0 +1,7 @@ ++SIGE7-RK3588 ++M: Jianfeng Liu ++S: Maintained ++F: board/armsom/sige7-rk3588 ++F: include/configs/sige7-rk3588.h ++F: configs/sige7-rk3588_defconfig ++F: arch/arm/dts/rk3588-armsom-sige7* +--- /dev/null ++++ b/configs/sige7-rk3588_defconfig +@@ -0,0 +1,93 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-armsom-sige7" ++CONFIG_ROCKCHIP_RK3588=y ++CONFIG_SPL_SERIAL=y ++CONFIG_TARGET_SIGE7_RK3588=y ++CONFIG_DEBUG_UART_BASE=0xFEB50000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_ROCKUSB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_AHCI_PCI=y ++CONFIG_DWC_AHCI=y ++CONFIG_SPL_CLK=y ++# CONFIG_USB_FUNCTION_FASTBOOT is not set ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PHYLIB=y ++CONFIG_RTL8169=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_PHY_ROCKCHIP_USBDP=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_SCSI=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_SPL_USB_DWC3_GENERIC=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_LAN75XX=y ++CONFIG_USB_ETHER_LAN78XX=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_ERRNO_STR=y +--- a/doc/board/rockchip/rockchip.rst ++++ b/doc/board/rockchip/rockchip.rst +@@ -122,6 +122,7 @@ List of mainline supported Rockchip boar + - Radxa ROCK 3B (rock-3b-rk3568) + + * rk3588 ++ - ArmSoM Sige7 (sige7-rk3588) + - Rockchip EVB (evb-rk3588) + - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) + - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) +--- /dev/null ++++ b/include/configs/sige7-rk3588.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2024 ArmSoM Technology Co., Ltd. ++ */ ++ ++#ifndef __SIGE7_RK3588_H ++#define __SIGE7_RK3588_H ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#endif /* __SIGE7_RK3588_H */ From 76a75b43ba1bf0bdfd5c27b5685e641f9131b6f8 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 23 Sep 2024 13:46:22 +0800 Subject: [PATCH 07/11] rockchip: add ArmSoM Sige7 support This board is also as known as Bananapi BPi-M7. Hardware -------- RockChip RK3588 ARM64 (8 cores) 8/16/32GB LPDDR4/LPDDR4x RAM 2x 2500 Base-T (PCIe, rtl8125b) 2 LEDs (RED / GREEN) 16GB/32GB/64GB/128GB eMMC on-board Micro-SD Slot USB 2.0 Port USB 3.0 Port M.2 M-Key 40-Pin Header USB PD 2.0 9/12/15V Power Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: Tianling Shen Link: https://github.com/openwrt/openwrt/pull/16462 Signed-off-by: Nick Hainke --- .../armv8/base-files/etc/board.d/02_network | 14 +- .../etc/hotplug.d/net/40-net-smp-affinity | 1 + target/linux/rockchip/image/armv8.mk | 11 + ...-dts-rockchip-Add-ArmSom-Sige7-board.patch | 778 ++++++++++++++++++ ...ble-thermal-management-on-all-RK358.patch} | 13 + ...date-LED-properties-for-ArmSom-Sige7.patch | 25 + ...hip-lower-mmc-speed-for-ArmSom-Sige7.patch | 26 + 7 files changed, 862 insertions(+), 6 deletions(-) create mode 100644 target/linux/rockchip/patches-6.6/056-01-v6.10-arm64-dts-rockchip-Add-ArmSom-Sige7-board.patch rename target/linux/rockchip/patches-6.6/{052-16-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch => 056-02-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch} (90%) create mode 100644 target/linux/rockchip/patches-6.6/125-arm64-dts-rockchip-Update-LED-properties-for-ArmSom-Sige7.patch create mode 100644 target/linux/rockchip/patches-6.6/126-arm64-dts-rockchip-lower-mmc-speed-for-ArmSom-Sige7.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 193bfd9024..192b825244 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -7,12 +7,7 @@ rockchip_setup_interfaces() local board="$1" case "$board" in - friendlyarm,nanopc-t6|\ - friendlyarm,nanopi-r5c|\ - radxa,e25|\ - radxa,rock-3b) - ucidef_set_interfaces_lan_wan 'eth0' 'eth1' - ;; + armsom,sige7|\ friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2c-plus|\ friendlyarm,nanopi-r2s|\ @@ -24,6 +19,12 @@ rockchip_setup_interfaces() xunlong,orangepi-r1-plus-lts) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; + friendlyarm,nanopc-t6|\ + friendlyarm,nanopi-r5c|\ + radxa,e25|\ + radxa,rock-3b) + ucidef_set_interfaces_lan_wan 'eth0' 'eth1' + ;; friendlyarm,nanopi-r5s) ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' ;; @@ -47,6 +48,7 @@ rockchip_setup_macs() local label_mac="" case "$board" in + armsom,sige7|\ friendlyarm,nanopc-t6|\ friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s) diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index c876bfe0ae..f65d008ef4 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -29,6 +29,7 @@ set_interface_core() { } case "$(board_name)" in +armsom,sige7|\ friendlyarm,nanopc-t6|\ friendlyarm,nanopi-r5c|\ friendlyarm,nanopi-r6c|\ diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index c867037d0e..39eb3bb034 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -5,6 +5,17 @@ # FIT will be loaded at 0x02080000. Leave 16M for that, align it to 2M and load the kernel after it. KERNEL_LOADADDR := 0x03200000 +define Device/armsom_sige7 + DEVICE_VENDOR := ArmSoM + DEVICE_MODEL := Sige7 + DEVICE_ALT0_VENDOR := Bananapi + DEVICE_ALT0_MODEL := BPi-M7 + SOC := rk3588 + DEVICE_DTS := rockchip/rk3588-armsom-sige7 + DEVICE_PACKAGES := kmod-r8169 +endef +TARGET_DEVICES += armsom_sige7 + define Device/firefly_roc-rk3328-cc DEVICE_VENDOR := Firefly DEVICE_MODEL := ROC-RK3328-CC diff --git a/target/linux/rockchip/patches-6.6/056-01-v6.10-arm64-dts-rockchip-Add-ArmSom-Sige7-board.patch b/target/linux/rockchip/patches-6.6/056-01-v6.10-arm64-dts-rockchip-Add-ArmSom-Sige7-board.patch new file mode 100644 index 0000000000..bc1845b0d3 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/056-01-v6.10-arm64-dts-rockchip-Add-ArmSom-Sige7-board.patch @@ -0,0 +1,778 @@ +From 81c828a67c78bb03ea75819c417c93c7f3d637b5 Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Sat, 20 Apr 2024 11:43:00 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add ArmSom Sige7 board +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Specification: + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16/32GB Memory LPDDR4/LPDDR4x + Mali G610MP4 GPU + 2× MIPI-CSI Connector + 1× MIPI-DSI Connector + 1x M.2 Key M (PCIe 3.0 4-lanes) + 2x RTL8125 2.5G Ethernet + Onboard AP6275P for WIFI6/BT5 + 32GB/64GB/128GB eMMC + MicroSD card slot + 1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C + 1x HDMI Output, 1x type-C DP Output + +Functions work normally: + USB2.0 Host + USB3.0 Type-A Host + M.2 Key M (PCIe 3.0 4-lanes) + 2x RTL8125 2.5G Ethernet + eMMC + MicroSD card + +More information can be obtained from the following website + https://docs.armsom.org/armsom-sige7 + +Signed-off-by: Jianfeng Liu +Reviewed-by: Weizhao Ouyang +Link: https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1994@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++ + 2 files changed, 722 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ra + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +@@ -0,0 +1,721 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ model = "ArmSoM Sige7"; ++ compatible = "armsom,sige7", "rockchip,rk3588"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ dais = <&i2s0_8ch_p0>; ++ label = "rk3588-es8316"; ++ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_g>; ++ ++ led_green: led-0 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led_red: led-1 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ }; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 95 145 195 255>; ++ fan-supply = <&vcc5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ #cooling-cells = <2>; ++ }; ++ ++ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc3v3_pcie30: vcc3v3-pcie30-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ ++ es8316: audio-codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ ++/* phy1 - right ethernet port */ ++&pcie2x1l0 { ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++/* phy2 - WiFi */ ++&pcie2x1l1 { ++ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++/* phy0 - left ethernet port */ ++&pcie2x1l2 { ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_g: led-rgb-g { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_rgb_r: led-rgb-r { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <200000000>; ++ no-sdio; ++ no-mmc; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&spi2 { ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ status = "okay"; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&usbdp_phy1 { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/052-16-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch b/target/linux/rockchip/patches-6.6/056-02-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch similarity index 90% rename from target/linux/rockchip/patches-6.6/052-16-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch rename to target/linux/rockchip/patches-6.6/056-02-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch index d59574bc49..d0b8336ef2 100644 --- a/target/linux/rockchip/patches-6.6/052-16-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch +++ b/target/linux/rockchip/patches-6.6/056-02-v6.11-arm64-dts-rockchip-enable-thermal-management-on-all-RK358.patch @@ -25,6 +25,19 @@ Signed-off-by: Heiko Stuebner arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ 8 files changed, 32 insertions(+) +--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +@@ -673,6 +673,10 @@ + }; + }; + ++&tsadc { ++ status = "okay"; ++}; ++ + &u2phy0 { + status = "okay"; + }; --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -807,6 +807,10 @@ diff --git a/target/linux/rockchip/patches-6.6/125-arm64-dts-rockchip-Update-LED-properties-for-ArmSom-Sige7.patch b/target/linux/rockchip/patches-6.6/125-arm64-dts-rockchip-Update-LED-properties-for-ArmSom-Sige7.patch new file mode 100644 index 0000000000..051efa7dbd --- /dev/null +++ b/target/linux/rockchip/patches-6.6/125-arm64-dts-rockchip-Update-LED-properties-for-ArmSom-Sige7.patch @@ -0,0 +1,25 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Mon Sep 23 13:22:56 2024 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for ArmSom + Sige7 + +Add OpenWrt's LED aliases for showing system status. + +Signed-off-by: Tianling Shen +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +@@ -13,6 +13,11 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; ++ ++ led-boot = &led_red; ++ led-failsafe = &led_red; ++ led-running = &led_red; ++ led-upgrade = &led_red; + }; + + chosen { diff --git a/target/linux/rockchip/patches-6.6/126-arm64-dts-rockchip-lower-mmc-speed-for-ArmSom-Sige7.patch b/target/linux/rockchip/patches-6.6/126-arm64-dts-rockchip-lower-mmc-speed-for-ArmSom-Sige7.patch new file mode 100644 index 0000000000..01f1c74370 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/126-arm64-dts-rockchip-lower-mmc-speed-for-ArmSom-Sige7.patch @@ -0,0 +1,26 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Mon Sep 23 13:22:56 2024 +0800 +Subject: [PATCH] arm64: dts: rockchip: lower mmc speed for ArmSom Sige7 + +The previously stated speed of sdr-104 in is too high for the hardware +to reliably communicate with some fast SD cards. +Rockchip boards have a common bug when operating uhs speed, which will +hang the system during a soft reboot. + +To be on the safe side, lower the speed to workaround. + +Signed-off-by: Tianling Shen +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +@@ -346,7 +346,7 @@ + max-frequency = <200000000>; + no-sdio; + no-mmc; +- sd-uhs-sdr104; ++ sd-uhs-sdr50; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; From 3b221ba5afe42bc32e878299d7d2275702536684 Mon Sep 17 00:00:00 2001 From: Rodrigo Balerdi Date: Mon, 23 Sep 2024 07:31:08 -0300 Subject: [PATCH 08/11] ipq807x: sax1v1k: fix sysupgrade not touching rootfs_data Before this commit, sysupgrade saved the settings backup data to the area following rootfs even though the device has an actual rootfs_data partition. The backup data was completely ignored on the following boot, but since rootfs_data was not being cleared during sysupgrade, the issue was not noticed earlier. Note that this commit changes the filesystem of rootfs_data from ext4 to F2FS (if OEM partitioning is used). Signed-off-by: Rodrigo Balerdi Link: https://github.com/openwrt/openwrt/pull/16463 Signed-off-by: Robert Marko --- target/linux/qualcommax/image/ipq807x.mk | 2 +- .../ipq807x/base-files/lib/upgrade/platform.sh | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/target/linux/qualcommax/image/ipq807x.mk b/target/linux/qualcommax/image/ipq807x.mk index b62734334d..faefb479c2 100644 --- a/target/linux/qualcommax/image/ipq807x.mk +++ b/target/linux/qualcommax/image/ipq807x.mk @@ -340,7 +340,7 @@ define Device/spectrum_sax1v1k DEVICE_DTS_CONFIG := config@rt5010w-d187-rev6 SOC := ipq8072 IMAGES := sysupgrade.bin - DEVICE_PACKAGES := ipq-wifi-spectrum_sax1v1k + DEVICE_PACKAGES := kmod-fs-f2fs f2fs-tools ipq-wifi-spectrum_sax1v1k endef TARGET_DEVICES += spectrum_sax1v1k diff --git a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh index 92ef5fef2c..808acac684 100644 --- a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh +++ b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh @@ -184,8 +184,7 @@ platform_do_upgrade() { nand_do_upgrade "$1" ;; prpl,haze|\ - qnap,301w|\ - spectrum,sax1v1k) + qnap,301w) kernelname="0:HLOS" rootfsname="rootfs" mmc_do_upgrade "$1" @@ -212,6 +211,12 @@ platform_do_upgrade() { CI_ROOT_UBIPART="rootfs" nand_do_upgrade "$1" ;; + spectrum,sax1v1k) + CI_KERNPART="0:HLOS" + CI_ROOTPART="rootfs" + CI_DATAPART="rootfs_data" + emmc_do_upgrade "$1" + ;; yuncore,ax880) active="$(fw_printenv -n active)" if [ "$active" -eq "1" ]; then @@ -260,3 +265,11 @@ platform_do_upgrade() { ;; esac } + +platform_copy_config() { + case "$(board_name)" in + spectrum,sax1v1k) + emmc_copy_config + ;; + esac +} From 1f4bd694aa5339f8ba9637c3b96fa5c662ef4b8b Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 24 Sep 2024 09:03:57 +0200 Subject: [PATCH 09/11] mac80211: introduce EHT rate support in AQL airtime Backport required by mt76 for decent throughput with EHT rates Signed-off-by: Felix Fietkau --- ...troduce-EHT-rate-support-in-AQL-airt.patch | 233 ++++++++++++++++++ 1 file changed, 233 insertions(+) create mode 100644 package/kernel/mac80211/patches/subsys/350-wifi-mac80211-introduce-EHT-rate-support-in-AQL-airt.patch diff --git a/package/kernel/mac80211/patches/subsys/350-wifi-mac80211-introduce-EHT-rate-support-in-AQL-airt.patch b/package/kernel/mac80211/patches/subsys/350-wifi-mac80211-introduce-EHT-rate-support-in-AQL-airt.patch new file mode 100644 index 0000000000..0a3c8ec53b --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/350-wifi-mac80211-introduce-EHT-rate-support-in-AQL-airt.patch @@ -0,0 +1,233 @@ +From: Ming Yen Hsieh +Date: Wed, 4 Sep 2024 19:12:56 +0800 +Subject: [PATCH] wifi: mac80211: introduce EHT rate support in AQL airtime + +Add definitions related to EHT mode and airtime calculation +according to the 802.11BE_D4.0. + +Co-developed-by: Bo Jiao +Signed-off-by: Bo Jiao +Signed-off-by: Deren Wu +Signed-off-by: Quan Zhou +Signed-off-by: Ming Yen Hsieh +Link: https://patch.msgid.link/20240904111256.11734-1-mingyen.hsieh@mediatek.com +Signed-off-by: Johannes Berg +--- + +--- a/net/mac80211/airtime.c ++++ b/net/mac80211/airtime.c +@@ -55,10 +55,21 @@ + #define HE_DURATION_S(shift, streams, gi, bps) \ + (HE_DURATION(streams, gi, bps) >> shift) + ++/* gi in HE/EHT is identical. It matches enum nl80211_eht_gi as well */ ++#define EHT_GI_08 HE_GI_08 ++#define EHT_GI_16 HE_GI_16 ++#define EHT_GI_32 HE_GI_32 ++ ++#define EHT_DURATION(streams, gi, bps) \ ++ HE_DURATION(streams, gi, bps) ++#define EHT_DURATION_S(shift, streams, gi, bps) \ ++ HE_DURATION_S(shift, streams, gi, bps) ++ + #define BW_20 0 + #define BW_40 1 + #define BW_80 2 + #define BW_160 3 ++#define BW_320 4 + + /* + * Define group sort order: HT40 -> SGI -> #streams +@@ -68,17 +79,26 @@ + #define IEEE80211_VHT_STREAM_GROUPS 8 /* BW(=4) * SGI(=2) */ + + #define IEEE80211_HE_MAX_STREAMS 8 ++#define IEEE80211_HE_STREAM_GROUPS 12 /* BW(=4) * GI(=3) */ ++ ++#define IEEE80211_EHT_MAX_STREAMS 8 ++#define IEEE80211_EHT_STREAM_GROUPS 15 /* BW(=5) * GI(=3) */ + + #define IEEE80211_HT_GROUPS_NB (IEEE80211_MAX_STREAMS * \ + IEEE80211_HT_STREAM_GROUPS) + #define IEEE80211_VHT_GROUPS_NB (IEEE80211_MAX_STREAMS * \ + IEEE80211_VHT_STREAM_GROUPS) ++#define IEEE80211_HE_GROUPS_NB (IEEE80211_HE_MAX_STREAMS * \ ++ IEEE80211_HE_STREAM_GROUPS) ++#define IEEE80211_EHT_GROUPS_NB (IEEE80211_EHT_MAX_STREAMS * \ ++ IEEE80211_EHT_STREAM_GROUPS) + + #define IEEE80211_HT_GROUP_0 0 + #define IEEE80211_VHT_GROUP_0 (IEEE80211_HT_GROUP_0 + IEEE80211_HT_GROUPS_NB) + #define IEEE80211_HE_GROUP_0 (IEEE80211_VHT_GROUP_0 + IEEE80211_VHT_GROUPS_NB) ++#define IEEE80211_EHT_GROUP_0 (IEEE80211_HE_GROUP_0 + IEEE80211_HE_GROUPS_NB) + +-#define MCS_GROUP_RATES 12 ++#define MCS_GROUP_RATES 14 + + #define HT_GROUP_IDX(_streams, _sgi, _ht40) \ + IEEE80211_HT_GROUP_0 + \ +@@ -203,6 +223,69 @@ + #define HE_GROUP(_streams, _gi, _bw) \ + __HE_GROUP(_streams, _gi, _bw, \ + HE_GROUP_SHIFT(_streams, _gi, _bw)) ++ ++#define EHT_BW2VBPS(_bw, r5, r4, r3, r2, r1) \ ++ ((_bw) == BW_320 ? r5 : BW2VBPS(_bw, r4, r3, r2, r1)) ++ ++#define EHT_GROUP_IDX(_streams, _gi, _bw) \ ++ (IEEE80211_EHT_GROUP_0 + \ ++ IEEE80211_EHT_MAX_STREAMS * 3 * (_bw) + \ ++ IEEE80211_EHT_MAX_STREAMS * (_gi) + \ ++ (_streams) - 1) ++ ++#define __EHT_GROUP(_streams, _gi, _bw, _s) \ ++ [EHT_GROUP_IDX(_streams, _gi, _bw)] = { \ ++ .shift = _s, \ ++ .duration = { \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 1960, 980, 490, 234, 117)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 3920, 1960, 980, 468, 234)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 5880, 2937, 1470, 702, 351)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 7840, 3920, 1960, 936, 468)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 11760, 5880, 2940, 1404, 702)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 15680, 7840, 3920, 1872, 936)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 17640, 8820, 4410, 2106, 1053)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 19600, 9800, 4900, 2340, 1170)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 23520, 11760, 5880, 2808, 1404)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 26133, 13066, 6533, 3120, 1560)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 29400, 14700, 7350, 3510, 1755)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 32666, 16333, 8166, 3900, 1950)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 35280, 17640, 8820, 4212, 2106)), \ ++ EHT_DURATION_S(_s, _streams, _gi, \ ++ EHT_BW2VBPS(_bw, 39200, 19600, 9800, 4680, 2340)) \ ++ } \ ++} ++ ++#define EHT_GROUP_SHIFT(_streams, _gi, _bw) \ ++ GROUP_SHIFT(EHT_DURATION(_streams, _gi, \ ++ EHT_BW2VBPS(_bw, 1960, 980, 490, 234, 117))) ++ ++#define EHT_GROUP(_streams, _gi, _bw) \ ++ __EHT_GROUP(_streams, _gi, _bw, \ ++ EHT_GROUP_SHIFT(_streams, _gi, _bw)) ++ ++#define EHT_GROUP_RANGE(_gi, _bw) \ ++ EHT_GROUP(1, _gi, _bw), \ ++ EHT_GROUP(2, _gi, _bw), \ ++ EHT_GROUP(3, _gi, _bw), \ ++ EHT_GROUP(4, _gi, _bw), \ ++ EHT_GROUP(5, _gi, _bw), \ ++ EHT_GROUP(6, _gi, _bw), \ ++ EHT_GROUP(7, _gi, _bw), \ ++ EHT_GROUP(8, _gi, _bw) ++ + struct mcs_group { + u8 shift; + u16 duration[MCS_GROUP_RATES]; +@@ -376,6 +459,26 @@ static const struct mcs_group airtime_mc + HE_GROUP(6, HE_GI_32, BW_160), + HE_GROUP(7, HE_GI_32, BW_160), + HE_GROUP(8, HE_GI_32, BW_160), ++ ++ EHT_GROUP_RANGE(EHT_GI_08, BW_20), ++ EHT_GROUP_RANGE(EHT_GI_16, BW_20), ++ EHT_GROUP_RANGE(EHT_GI_32, BW_20), ++ ++ EHT_GROUP_RANGE(EHT_GI_08, BW_40), ++ EHT_GROUP_RANGE(EHT_GI_16, BW_40), ++ EHT_GROUP_RANGE(EHT_GI_32, BW_40), ++ ++ EHT_GROUP_RANGE(EHT_GI_08, BW_80), ++ EHT_GROUP_RANGE(EHT_GI_16, BW_80), ++ EHT_GROUP_RANGE(EHT_GI_32, BW_80), ++ ++ EHT_GROUP_RANGE(EHT_GI_08, BW_160), ++ EHT_GROUP_RANGE(EHT_GI_16, BW_160), ++ EHT_GROUP_RANGE(EHT_GI_32, BW_160), ++ ++ EHT_GROUP_RANGE(EHT_GI_08, BW_320), ++ EHT_GROUP_RANGE(EHT_GI_16, BW_320), ++ EHT_GROUP_RANGE(EHT_GI_32, BW_320), + }; + + static u32 +@@ -422,6 +525,9 @@ static u32 ieee80211_get_rate_duration(s + case RATE_INFO_BW_160: + bw = BW_160; + break; ++ case RATE_INFO_BW_320: ++ bw = BW_320; ++ break; + default: + WARN_ON_ONCE(1); + return 0; +@@ -443,14 +549,27 @@ static u32 ieee80211_get_rate_duration(s + idx = status->rate_idx; + group = HE_GROUP_IDX(streams, status->he_gi, bw); + break; ++ case RX_ENC_EHT: ++ streams = status->nss; ++ idx = status->rate_idx; ++ group = EHT_GROUP_IDX(streams, status->eht.gi, bw); ++ break; + default: + WARN_ON_ONCE(1); + return 0; + } + +- if (WARN_ON_ONCE((status->encoding != RX_ENC_HE && streams > 4) || +- (status->encoding == RX_ENC_HE && streams > 8))) +- return 0; ++ switch (status->encoding) { ++ case RX_ENC_EHT: ++ case RX_ENC_HE: ++ if (WARN_ON_ONCE(streams > 8)) ++ return 0; ++ break; ++ default: ++ if (WARN_ON_ONCE(streams > 4)) ++ return 0; ++ break; ++ } + + if (idx >= MCS_GROUP_RATES) + return 0; +@@ -517,7 +636,9 @@ static bool ieee80211_fill_rate_info(str + stat->nss = ri->nss; + stat->rate_idx = ri->mcs; + +- if (ri->flags & RATE_INFO_FLAGS_HE_MCS) ++ if (ri->flags & RATE_INFO_FLAGS_EHT_MCS) ++ stat->encoding = RX_ENC_EHT; ++ else if (ri->flags & RATE_INFO_FLAGS_HE_MCS) + stat->encoding = RX_ENC_HE; + else if (ri->flags & RATE_INFO_FLAGS_VHT_MCS) + stat->encoding = RX_ENC_VHT; +@@ -529,7 +650,14 @@ static bool ieee80211_fill_rate_info(str + if (ri->flags & RATE_INFO_FLAGS_SHORT_GI) + stat->enc_flags |= RX_ENC_FLAG_SHORT_GI; + +- stat->he_gi = ri->he_gi; ++ switch (stat->encoding) { ++ case RX_ENC_EHT: ++ stat->eht.gi = ri->eht_gi; ++ break; ++ default: ++ stat->he_gi = ri->he_gi; ++ break; ++ } + + if (stat->encoding != RX_ENC_LEGACY) + return true; From d39078c785d37961e8b9a96ba3612bc67c10bf2f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 15 Sep 2024 23:10:15 +0800 Subject: [PATCH 10/11] kernel: r8125: add CONFLICT to rss variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rss variant should conflict with the default. Signed-off-by: Chukun Pan Link: https://github.com/openwrt/openwrt/pull/16460 Signed-off-by: Álvaro Fernández Rojas --- package/kernel/r8125/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/kernel/r8125/Makefile b/package/kernel/r8125/Makefile index f05ec0d842..ef95b52e67 100644 --- a/package/kernel/r8125/Makefile +++ b/package/kernel/r8125/Makefile @@ -27,6 +27,7 @@ endef define KernelPackage/r8125-rss $(call KernelPackage/r8125) + CONFLICTS:=kmod-r8125 TITLE+= (RSS) VARIANT:=rss endef From b83c7448d3ecd82d6c9e02aded784d6bc3c9ce3c Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 16 Sep 2024 23:10:20 +0800 Subject: [PATCH 11/11] kernel: r8126: add CONFLICT to rss variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rss variant should conflict with the default. Signed-off-by: Chukun Pan Link: https://github.com/openwrt/openwrt/pull/16460 Signed-off-by: Álvaro Fernández Rojas --- package/kernel/r8126/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/kernel/r8126/Makefile b/package/kernel/r8126/Makefile index 3cd77294b1..c269cdcadc 100644 --- a/package/kernel/r8126/Makefile +++ b/package/kernel/r8126/Makefile @@ -27,6 +27,7 @@ endef define KernelPackage/r8126-rss $(call KernelPackage/r8126) + CONFLICTS:=kmod-r8126 TITLE+= (RSS) VARIANT:=rss endef