From b7cf706539eb3a788441c8a8debaa8c36e5c54cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Fri, 10 Nov 2023 21:42:34 +0000 Subject: [PATCH 1/4] debugcc: add licensing information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Information about package license is important, so lets add it. Fixes: 79ee0d2ceead ("debugcc: add new package to debug IPQ based SoC clocks") Signed-off-by: Petr Štetiar --- package/utils/debugcc/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/package/utils/debugcc/Makefile b/package/utils/debugcc/Makefile index 961c041047..2a72f17730 100644 --- a/package/utils/debugcc/Makefile +++ b/package/utils/debugcc/Makefile @@ -9,6 +9,9 @@ PKG_SOURCE_DATE:=2023-11-10 PKG_SOURCE_VERSION:=d15bea7c05f224a85dd1fcec24b0f153dbad9f6e PKG_MIRROR_HASH:=b6bd181db4992cf429343cd7d0fdde0f937a8f1811f5fe9e7855a0d76b0d88a0 +PKG_LICENSE:=BSD-3-Clause +PKG_LICENSE_FILES:=LICENSE + PKG_MAINTAINER:=Christian Marangi include $(INCLUDE_DIR)/package.mk From a69367933dfefe1b72d949c70d7f1080db896d58 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 11 Nov 2023 23:38:30 +0100 Subject: [PATCH 2/4] netifd: update to Git HEAD (2023-11-11) c739dee0a37b system-linux: refresh MAC address on DSA port conduit change Signed-off-by: Christian Marangi --- package/network/config/netifd/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/config/netifd/Makefile b/package/network/config/netifd/Makefile index 826889aca6..eb4363e9c6 100644 --- a/package/network/config/netifd/Makefile +++ b/package/network/config/netifd/Makefile @@ -5,9 +5,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git -PKG_SOURCE_DATE:=2023-11-10 -PKG_SOURCE_VERSION:=35facc8306f590a7330789ab6d5785c0d43073ef -PKG_MIRROR_HASH:=4f73591ae1873e18df235349e478f2196ca0d3123c313a04149dc9d5e2bfb403 +PKG_SOURCE_DATE:=2023-11-11 +PKG_SOURCE_VERSION:=c739dee0a37bc593aaed7ae3f0a61e3d7c1fb1ac +PKG_MIRROR_HASH:=5e3dc0ce4774cd738b2d6363b642ee0501bd6b7f8061d5d82151af2069e7fbfd PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=GPL-2.0 From 8cce00bc9dddc3fc47d63625b0f512693c27ce2f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 11 Nov 2023 18:34:27 +0100 Subject: [PATCH 3/4] qca-ssdk: fix unsupported scenario with PORT1 not declared in switch bmp Commit 947b44d9ae17 ("ipq807x: fix wrong define for LAN and WAN ess mask") started fixing wrong switch_lan_bmp that defined lan there weren't actually present. This displayed a fragility in the malibu phy init code in qca-ssdk. Add patch to fix this. Quoting the patch detailed description: I'm very confused by this and to me it's not clear the real usage of this logic. From what I can see the usage of this is EXTREMELY FRAGILE and results in dangerous results if the OEM (or anyone that by chance try to implement things in a logical manner) deviates from the default values from the "magical template". To be in more details. With QSDK 12.4, some tweaks were done to improve autoneg and now on every call of port status, the phydev is tried to add. This resulted in the call and log spam of an error with ports that are actually not present on the system with qsdk reporting phydev is NULL. This itself is not an error and printing the error is correct. What is actually an error from ages is setting generic bitmap reporting presence of port that are actually not present. This is very common on OEM where the switch_lan_bmp is always a variant of 0x1e (that on bitmap results in PORT1 PORT2 PORT3 PORT4 present) or 0x3e (PORT1 PORT2 PORT3 PORT4 PORT5). Reality is that many device are used as AP with one LAN port or one WAN port. (or even exotic configuration with PORT1 not present and PORT2 PORT3 PORT4 present (Xiaomi 3600) With this finding one can say... ok nice, then lets update the DT and set the correct bitmap... Again world is a bad place and reality is that this cause wonderful regression in some case of by extreme luck the first ever connected port working and the rest of the switch dead. The problem has been bisected to all the device that doesn't have the PORT1 declared in any of the bitmap. With this perfection in mind, on to the REAL problem. malibu_phy_hw_init FOR SOME REASON, set a global variable first_phy_addr to the first detected PHY addr that coincidentally is always PORT1. PORT1 addr is 0x0. The entire code in malibu_phy use this variable to derive the phy addrs in some function. Declaring a bitmap where the PORT1 is missing (or worse PORT4 the only one connected) result in first_phy_addr set to 1 or whatever phy addr is detected first setting wrong value all over the init stage. To fix this, just drop this variable and hardcode everything to assume the first phy adrr is ALWAYS 0 and remove calculation and use define for special case. With the following change normal switch traffic is restored and ports function is recovered. Fixes: #13945 Fixes: 947b44d9ae17 ("ipq807x: fix wrong define for LAN and WAN ess mask") Signed-off-by: Christian Marangi --- package/kernel/qca-ssdk/Makefile | 2 +- ...ibu-phy-drop-usage-of-first_phy_addr.patch | 264 ++++++++++++++++++ 2 files changed, 265 insertions(+), 1 deletion(-) create mode 100644 package/kernel/qca-ssdk/patches/100-malibu-phy-drop-usage-of-first_phy_addr.patch diff --git a/package/kernel/qca-ssdk/Makefile b/package/kernel/qca-ssdk/Makefile index f5d8260503..4107208c0e 100644 --- a/package/kernel/qca-ssdk/Makefile +++ b/package/kernel/qca-ssdk/Makefile @@ -1,7 +1,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=qca-ssdk -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git PKG_SOURCE_PROTO:=git diff --git a/package/kernel/qca-ssdk/patches/100-malibu-phy-drop-usage-of-first_phy_addr.patch b/package/kernel/qca-ssdk/patches/100-malibu-phy-drop-usage-of-first_phy_addr.patch new file mode 100644 index 0000000000..905f1cde01 --- /dev/null +++ b/package/kernel/qca-ssdk/patches/100-malibu-phy-drop-usage-of-first_phy_addr.patch @@ -0,0 +1,264 @@ +From 46ed8163ac0d9a11a629f1c446e8c5e711cf35d6 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Sat, 11 Nov 2023 18:13:02 +0100 +Subject: [PATCH] malibu-phy: drop usage of first_phy_addr + +I'm very confused by this and to me it's not clear the real usage of +this logic. + +From what I can see the usage of this is EXTREMELY FRAGILE and results +in dangerous results if the OEM (or anyone that by chance try to +implement things in a logical manner) deviates from the default values +from the "magical template". + +To be in more details. With QSDK 12.4, some tweaks were done to improve +autoneg and now on every call of port status, the phydev is tried to +add. This resulted in the call and log spam of an error with ports that +are actually not present on the system with qsdk reporting phydev is +NULL. This itself is not an error and printing the error is correct. + +What is actually an error from ages is setting generic bitmap reporting +presence of port that are actually not present. This is very common on +OEM where the switch_lan_bmp is always a variant of 0x1e (that on bitmap +results in PORT1 PORT2 PORT3 PORT4 present) or 0x3e (PORT1 PORT2 PORT3 +PORT4 PORT5). Reality is that many device are used as AP with one LAN +port or one WAN port. (or even exotic configuration with PORT1 not +present and PORT2 PORT3 PORT4 present (Xiaomi 3600) + +With this finding one can say... ok nice, then lets update the DT and +set the correct bitmap... + +Again world is a bad place and reality is that this cause wonderful +regression in some case of by extreme luck the first ever connected +port working and the rest of the switch dead. + +The problem has been bisected to all the device that doesn't have the +PORT1 declared in any of the bitmap. + +With this perfection in mind, on to the REAL problem. + +malibu_phy_hw_init FOR SOME REASON, set a global variable first_phy_addr +to the first detected PHY addr that coincidentally is always PORT1. +PORT1 addr is 0x0. The entire code in malibu_phy use this variable to +derive the phy addrs in some function. + +Declaring a bitmap where the PORT1 is missing (or worse PORT4 the only +one connected) result in first_phy_addr set to 1 or whatever phy addr is +detected first setting wrong value all over the init stage. + +To fix this, just drop this variable and hardcode everything to assume +the first phy adrr is ALWAYS 0 and remove calculation and use define for +special case. + +With the following change normal switch traffic is restored and ports +function is recovered. + +Signed-off-by: Christian Marangi +--- + src/hsl/phy/malibu_phy.c | 63 +++++++++++++++++----------------------- + 1 file changed, 26 insertions(+), 37 deletions(-) + +--- a/src/hsl/phy/malibu_phy.c ++++ b/src/hsl/phy/malibu_phy.c +@@ -26,8 +26,9 @@ + #include "qcaphy_common.h" + #include "ssdk_plat.h" + +-static a_uint32_t first_phy_addr = MAX_PHY_ADDR; + static a_uint32_t combo_phy_addr = MAX_PHY_ADDR; ++#define PORT4_PHY_ID 0x4 ++#define PORT5_PHY_ID 0x5 + #define COMBO_PHY_ID combo_phy_addr + + /****************************************************************************** +@@ -1250,10 +1251,10 @@ sw_error_t + malibu_phy_serdes_reset(a_uint32_t dev_id) + { + +- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC, ++ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_PSGMII_ADDR_INC, + MALIBU_MODE_RESET_REG, MALIBU_MODE_CHANAGE_RESET); + mdelay(100); +- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC, ++ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_PSGMII_ADDR_INC, + MALIBU_MODE_RESET_REG, MALIBU_MODE_RESET_DEFAULT_VALUE); + + return SW_OK; +@@ -1271,8 +1272,7 @@ malibu_phy_interface_set_mode(a_uint32_t + a_uint16_t phy_data = 0; + static fal_port_interface_mode_t phy_mode = PORT_INTERFACE_MODE_MAX; + +- if ((phy_addr < first_phy_addr) || +- (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) ++ if (phy_addr > MALIBU_PHY_MAX_ADDR_INC) + return SW_NOT_SUPPORTED; + /*if interface_mode have been configured, then no need to configure again*/ + if(phy_mode == interface_mode) +@@ -1295,20 +1295,19 @@ malibu_phy_interface_set_mode(a_uint32_t + return SW_BAD_PARAM; + } + +- hsl_phy_modify_mii(dev_id, +- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG, ++ hsl_phy_modify_mii(dev_id, MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG, + BITS(0, 4), phy_data); + + /* reset operation */ + malibu_phy_serdes_reset(dev_id); + + if (interface_mode == PHY_PSGMII_FIBER) { +- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, ++ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_MAX_ADDR_INC, + MALIBU_PHY_CHIP_CONFIG, MALIBU_MODECTRL_DFLT); +- hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, ++ hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_MAX_ADDR_INC, + MALIBU_PHY_CONTROL, MALIBU_MIICTRL_DFLT); + hsl_phy_phydev_autoneg_update(dev_id, +- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, A_FALSE, 0); ++ MALIBU_PHY_MAX_ADDR_INC, A_FALSE, 0); + } + phy_mode = interface_mode; + SSDK_DEBUG("malibu phy is configured as phy_mode:0x%x\n", phy_mode); +@@ -1329,13 +1328,12 @@ malibu_phy_interface_get_mode(a_uint32_t + a_uint16_t phy_data; + a_uint16_t copper_mode; + +- if ((phy_addr < first_phy_addr) || +- (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) { ++ if (phy_addr > MALIBU_PHY_MAX_ADDR_INC) { + return SW_NOT_SUPPORTED; + } + + phy_data = hsl_phy_mii_reg_read(dev_id, +- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG); ++ MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG); + copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf); + phy_data &= 0x000f; + +@@ -1344,13 +1342,13 @@ malibu_phy_interface_get_mode(a_uint32_t + *interface_mode = PHY_PSGMII_BASET; + break; + case MALIBU_PHY_PSGMII_BX1000: +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode = PHY_PSGMII_BX1000; + else + *interface_mode = PHY_PSGMII_BASET; + break; + case MALIBU_PHY_PSGMII_FX100: +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode = PHY_PSGMII_FX100; + else + *interface_mode = PHY_PSGMII_BASET; +@@ -1359,14 +1357,14 @@ malibu_phy_interface_get_mode(a_uint32_t + if (copper_mode) { + *interface_mode = PHY_PSGMII_BASET; + } else { +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode = PHY_PSGMII_FIBER; + else + *interface_mode = PHY_PSGMII_BASET; + } + break; + case MALIBU_PHY_SGMII_BASET: +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode = PHY_SGMII_BASET; + else + *interface_mode = PORT_QSGMII; +@@ -1392,13 +1390,12 @@ malibu_phy_interface_get_mode_status(a_u + a_uint16_t phy_data, phy_mode, phy_mode_status; + a_uint16_t copper_mode; + +- if ((phy_addr < first_phy_addr) || +- (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) { ++ if (phy_addr > MALIBU_PHY_MAX_ADDR_INC) { + return SW_NOT_SUPPORTED; + } + + phy_data = hsl_phy_mii_reg_read(dev_id, +- first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG); ++ MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG); + copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf); + phy_mode = phy_data & 0x000f; + phy_mode_status = (phy_data & 0x00f0) >> 0x4; +@@ -1407,7 +1404,7 @@ malibu_phy_interface_get_mode_status(a_u + if (copper_mode) { + *interface_mode_status = PHY_PSGMII_BASET; + } else { +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode_status = PHY_PSGMII_FIBER; + else + *interface_mode_status = PHY_PSGMII_BASET; +@@ -1418,19 +1415,19 @@ malibu_phy_interface_get_mode_status(a_u + *interface_mode_status = PHY_PSGMII_BASET; + break; + case MALIBU_PHY_PSGMII_BX1000: +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode_status = PHY_PSGMII_BX1000; + else + *interface_mode_status = PHY_PSGMII_BASET; + break; + case MALIBU_PHY_PSGMII_FX100: +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode_status = PHY_PSGMII_FX100; + else + *interface_mode_status = PHY_PSGMII_BASET; + break; + case MALIBU_PHY_SGMII_BASET: +- if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) ++ if (phy_addr == MALIBU_PHY_MAX_ADDR_INC) + *interface_mode_status = PHY_SGMII_BASET; + else + *interface_mode_status = PORT_QSGMII; +@@ -1795,10 +1792,6 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_ + { + phy_cnt ++; + phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); +- if (phy_addr < first_phy_addr) +- { +- first_phy_addr = phy_addr; +- } + /*enable phy power saving function by default */ + malibu_phy_set_8023az(dev_id, phy_addr, A_TRUE); + malibu_phy_set_powersave(dev_id, phy_addr, A_TRUE); +@@ -1824,29 +1817,25 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_ + MALIBU_EXTENDED_NEXT_PAGE_EN, 0); + } + } +- /* qca 8072 two ports phy chip's firstly address to init phy chip */ +- if ((phy_cnt == QCA8072_PHY_NUM) && (first_phy_addr >= 0x3)) { +- first_phy_addr = first_phy_addr - 0x3; +- } + + /*workaround to enable AZ transmitting ability*/ +- hsl_phy_mmd_reg_write(dev_id, first_phy_addr + 5, A_FALSE, MALIBU_PHY_MMD1_NUM, ++ hsl_phy_mmd_reg_write(dev_id, PORT5_PHY_ID, A_FALSE, MALIBU_PHY_MMD1_NUM, + MALIBU_PSGMII_MODE_CTRL, MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE); + + /* adjust psgmii serdes tx amp */ +- hsl_phy_mii_reg_write(dev_id, first_phy_addr + 5, ++ hsl_phy_mii_reg_write(dev_id, PORT5_PHY_ID, + MALIBU_PSGMII_TX_DRIVER_1_CTRL, MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP); + + /* to avoid psgmii module goes into hibernation, work with psgmii self test*/ +- hsl_phy_modify_mmd(dev_id, first_phy_addr + 4, A_FALSE, MALIBU_PHY_MMD3_NUM, ++ hsl_phy_modify_mmd(dev_id, PORT4_PHY_ID, A_FALSE, MALIBU_PHY_MMD3_NUM, + MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, BIT(1), 0); + + mode = ssdk_dt_global_get_mac_mode(dev_id, 0); + if (mode == PORT_WRAPPER_PSGMII_FIBER) +- malibu_phy_interface_set_mode(dev_id, first_phy_addr, PHY_PSGMII_FIBER); ++ malibu_phy_interface_set_mode(dev_id, 0x0, PHY_PSGMII_FIBER); + + /*init combo phy address*/ +- combo_phy_addr = first_phy_addr+4; ++ combo_phy_addr = PORT4_PHY_ID; + + return SW_OK; + } From 36b1dd75fd9da1ea13f1ce1ee679c6b3c9c402cc Mon Sep 17 00:00:00 2001 From: Hannu Nyman Date: Sat, 11 Nov 2023 19:03:57 +0200 Subject: [PATCH 4/4] ath10k-ct: Restore functionality after switch to 6.4 version Adjust our local ath10k-ct patches to the change from the -ct 6.2 version to 6.4. This restores e.g. the LED functionality. Fixes: 7d3651f1b9b ("ath10k-ct: switch to 6.4") Signed-off-by: Hannu Nyman --- ...k-read-qcom-coexist-support-as-a-u32.patch | 4 +- ...rolling-support-for-various-chipsets.patch | 72 +++++++++---------- ...02-ath10k-use-tpt-trigger-by-default.patch | 20 +++--- ...0-0010-ath10k-limit-htt-rx-ring-size.patch | 4 +- ...60-0011-ath10k-limit-pci-buffer-size.patch | 4 +- ...k-always-use-mac80211-loss-detection.patch | 8 +-- 6 files changed, 56 insertions(+), 56 deletions(-) diff --git a/package/kernel/ath10k-ct/patches/130-ath10k-read-qcom-coexist-support-as-a-u32.patch b/package/kernel/ath10k-ct/patches/130-ath10k-read-qcom-coexist-support-as-a-u32.patch index 77e2724991..891973f38d 100644 --- a/package/kernel/ath10k-ct/patches/130-ath10k-read-qcom-coexist-support-as-a-u32.patch +++ b/package/kernel/ath10k-ct/patches/130-ath10k-read-qcom-coexist-support-as-a-u32.patch @@ -39,8 +39,8 @@ that the feature is properly initialized: Signed-off-by: Vincent Tremblay ---- a/ath10k-6.2/core.c -+++ b/ath10k-6.2/core.c +--- a/ath10k-6.4/core.c ++++ b/ath10k-6.4/core.c @@ -2869,14 +2869,14 @@ done: static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) { diff --git a/package/kernel/ath10k-ct/patches/201-ath10k-add-LED-and-GPIO-controlling-support-for-various-chipsets.patch b/package/kernel/ath10k-ct/patches/201-ath10k-add-LED-and-GPIO-controlling-support-for-various-chipsets.patch index 844c089e88..8eb587b877 100644 --- a/package/kernel/ath10k-ct/patches/201-ath10k-add-LED-and-GPIO-controlling-support-for-various-chipsets.patch +++ b/package/kernel/ath10k-ct/patches/201-ath10k-add-LED-and-GPIO-controlling-support-for-various-chipsets.patch @@ -66,24 +66,24 @@ v13: * cleanup includes - ath10k-6.2/Kconfig | 10 +++ - ath10k-6.2/Makefile | 1 + - ath10k-6.2/core.c | 22 +++++++ - ath10k-6.2/core.h | 9 ++- - ath10k-6.2/hw.h | 1 + - ath10k-6.2/leds.c | 103 ++++++++++++++++++++++++++++++ - ath10k-6.2/leds.h | 45 +++++++++++++ - ath10k-6.2/mac.c | 1 + - ath10k-6.2/wmi-ops.h | 32 ++++++++++ - ath10k-6.2/wmi-tlv.c | 2 + - ath10k-6.2/wmi.c | 54 ++++++++++++++++ - ath10k-6.2/wmi.h | 35 ++++++++++ + ath10k-6.4/Kconfig | 10 +++ + ath10k-6.4/Makefile | 1 + + ath10k-6.4/core.c | 22 +++++++ + ath10k-6.4/core.h | 9 ++- + ath10k-6.4/hw.h | 1 + + ath10k-6.4/leds.c | 103 ++++++++++++++++++++++++++++++ + ath10k-6.4/leds.h | 45 +++++++++++++ + ath10k-6.4/mac.c | 1 + + ath10k-6.4/wmi-ops.h | 32 ++++++++++ + ath10k-6.4/wmi-tlv.c | 2 + + ath10k-6.4/wmi.c | 54 ++++++++++++++++ + ath10k-6.4/wmi.h | 35 ++++++++++ 12 files changed, 314 insertions(+), 1 deletion(-) - create mode 100644 ath10k-6.2/leds.c - create mode 100644 ath10k-6.2/leds.h + create mode 100644 ath10k-6.4/leds.c + create mode 100644 ath10k-6.4/leds.h ---- a/ath10k-6.2/Kconfig -+++ b/ath10k-6.2/Kconfig +--- a/ath10k-6.4/Kconfig ++++ b/ath10k-6.4/Kconfig @@ -67,6 +67,16 @@ config ATH10K_DEBUGFS If unsure, say Y to make it easier to debug problems. @@ -101,8 +101,8 @@ v13: config ATH10K_SPECTRAL bool "Atheros ath10k spectral scan support" depends on ATH10K_DEBUGFS ---- a/ath10k-6.2/Makefile -+++ b/ath10k-6.2/Makefile +--- a/ath10k-6.4/Makefile ++++ b/ath10k-6.4/Makefile @@ -20,6 +20,7 @@ ath10k_core-$(CONFIG_ATH10K_SPECTRAL) += ath10k_core-$(CONFIG_NL80211_TESTMODE) += testmode.o ath10k_core-$(CONFIG_ATH10K_TRACING) += trace.o @@ -111,8 +111,8 @@ v13: ath10k_core-$(CONFIG_MAC80211_DEBUGFS) += debugfs_sta.o ath10k_core-$(CONFIG_PM) += wow.o ath10k_core-$(CONFIG_ATH10K_CE) += ce.o ---- a/ath10k-6.2/core.c -+++ b/ath10k-6.2/core.c +--- a/ath10k-6.4/core.c ++++ b/ath10k-6.4/core.c @@ -28,6 +28,7 @@ #include "testmode.h" #include "wmi-ops.h" @@ -200,8 +200,8 @@ v13: ath10k_thermal_unregister(ar); /* Stop spectral before unregistering from mac80211 to remove the * relayfs debugfs file cleanly. Otherwise the parent debugfs tree ---- a/ath10k-6.2/core.h -+++ b/ath10k-6.2/core.h +--- a/ath10k-6.4/core.h ++++ b/ath10k-6.4/core.h @@ -14,6 +14,7 @@ #include #include @@ -224,8 +224,8 @@ v13: /* protected by data_lock */ u32 rx_crc_err_drop; u32 fw_crash_counter; ---- a/ath10k-6.2/hw.h -+++ b/ath10k-6.2/hw.h +--- a/ath10k-6.4/hw.h ++++ b/ath10k-6.4/hw.h @@ -523,6 +523,7 @@ struct ath10k_hw_params { const char *name; u32 patch_load_addr; @@ -235,7 +235,7 @@ v13: /* Type of hw cycle counter wraparound logic, for more info --- /dev/null -+++ b/ath10k-6.2/leds.c ++++ b/ath10k-6.4/leds.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2005-2011 Atheros Communications Inc. @@ -341,7 +341,7 @@ v13: +} + --- /dev/null -+++ b/ath10k-6.2/leds.h ++++ b/ath10k-6.4/leds.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. @@ -384,8 +384,8 @@ v13: + +#endif +#endif /* _LEDS_H_ */ ---- a/ath10k-6.2/mac.c -+++ b/ath10k-6.2/mac.c +--- a/ath10k-6.4/mac.c ++++ b/ath10k-6.4/mac.c @@ -25,6 +25,7 @@ #include "wmi-tlv.h" #include "wmi-ops.h" @@ -394,8 +394,8 @@ v13: /*********/ /* Rates */ ---- a/ath10k-6.2/wmi-ops.h -+++ b/ath10k-6.2/wmi-ops.h +--- a/ath10k-6.4/wmi-ops.h ++++ b/ath10k-6.4/wmi-ops.h @@ -228,7 +228,10 @@ struct wmi_ops { const struct wmi_bb_timing_cfg_arg *arg); struct sk_buff *(*gen_per_peer_per_tid_cfg)(struct ath10k *ar, @@ -443,8 +443,8 @@ v13: static inline int ath10k_wmi_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level) { ---- a/ath10k-6.2/wmi-tlv.c -+++ b/ath10k-6.2/wmi-tlv.c +--- a/ath10k-6.4/wmi-tlv.c ++++ b/ath10k-6.4/wmi-tlv.c @@ -4601,6 +4601,8 @@ static const struct wmi_ops wmi_tlv_ops .gen_echo = ath10k_wmi_tlv_op_gen_echo, .gen_vdev_spectral_conf = ath10k_wmi_tlv_op_gen_vdev_spectral_conf, @@ -454,8 +454,8 @@ v13: }; static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = { ---- a/ath10k-6.2/wmi.c -+++ b/ath10k-6.2/wmi.c +--- a/ath10k-6.4/wmi.c ++++ b/ath10k-6.4/wmi.c @@ -8438,6 +8438,49 @@ ath10k_wmi_op_gen_peer_set_param(struct return skb; } @@ -552,8 +552,8 @@ v13: }; int ath10k_wmi_attach(struct ath10k *ar) ---- a/ath10k-6.2/wmi.h -+++ b/ath10k-6.2/wmi.h +--- a/ath10k-6.4/wmi.h ++++ b/ath10k-6.4/wmi.h @@ -3133,6 +3133,41 @@ enum wmi_10_4_feature_mask { }; diff --git a/package/kernel/ath10k-ct/patches/202-ath10k-use-tpt-trigger-by-default.patch b/package/kernel/ath10k-ct/patches/202-ath10k-use-tpt-trigger-by-default.patch index 8ac2776f92..4f9cf83c48 100644 --- a/package/kernel/ath10k-ct/patches/202-ath10k-use-tpt-trigger-by-default.patch +++ b/package/kernel/ath10k-ct/patches/202-ath10k-use-tpt-trigger-by-default.patch @@ -9,13 +9,13 @@ traffic. Signed-off-by: Mathias Kresin --- - ath10k-6.2/core.h | 4 ++++ - ath10k-6.2/leds.c | 4 +--- - ath10k-6.2/mac.c | 2 +- + ath10k-6.4/core.h | 4 ++++ + ath10k-6.4/leds.c | 4 +--- + ath10k-6.4/mac.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) ---- a/ath10k-6.2/core.h -+++ b/ath10k-6.2/core.h +--- a/ath10k-6.4/core.h ++++ b/ath10k-6.4/core.h @@ -1701,6 +1701,10 @@ struct ath10k { u8 csi_data[4096]; u16 csi_data_len; @@ -27,8 +27,8 @@ Signed-off-by: Mathias Kresin /* must be last */ u8 drv_priv[] __aligned(sizeof(void *)); }; ---- a/ath10k-6.2/leds.c -+++ b/ath10k-6.2/leds.c +--- a/ath10k-6.4/leds.c ++++ b/ath10k-6.4/leds.c @@ -81,9 +81,7 @@ int ath10k_leds_register(struct ath10k * ar->leds.cdev.name = ar->leds.label; @@ -40,9 +40,9 @@ Signed-off-by: Mathias Kresin ret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev); if (ret) ---- a/ath10k-6.2/mac.c -+++ b/ath10k-6.2/mac.c -@@ -11617,7 +11617,7 @@ int ath10k_mac_register(struct ath10k *a +--- a/ath10k-6.4/mac.c ++++ b/ath10k-6.4/mac.c +@@ -11616,7 +11616,7 @@ int ath10k_mac_register(struct ath10k *a ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; #ifdef CPTCFG_MAC80211_LEDS diff --git a/package/kernel/ath10k-ct/patches/960-0010-ath10k-limit-htt-rx-ring-size.patch b/package/kernel/ath10k-ct/patches/960-0010-ath10k-limit-htt-rx-ring-size.patch index 1471902be3..b0e6ef76fa 100644 --- a/package/kernel/ath10k-ct/patches/960-0010-ath10k-limit-htt-rx-ring-size.patch +++ b/package/kernel/ath10k-ct/patches/960-0010-ath10k-limit-htt-rx-ring-size.patch @@ -1,5 +1,5 @@ ---- a/ath10k-6.2/htt.h -+++ b/ath10k-6.2/htt.h +--- a/ath10k-6.4/htt.h ++++ b/ath10k-6.4/htt.h @@ -237,7 +237,11 @@ enum htt_rx_ring_flags { }; diff --git a/package/kernel/ath10k-ct/patches/960-0011-ath10k-limit-pci-buffer-size.patch b/package/kernel/ath10k-ct/patches/960-0011-ath10k-limit-pci-buffer-size.patch index 145b2e7c35..82109995d9 100644 --- a/package/kernel/ath10k-ct/patches/960-0011-ath10k-limit-pci-buffer-size.patch +++ b/package/kernel/ath10k-ct/patches/960-0011-ath10k-limit-pci-buffer-size.patch @@ -1,5 +1,5 @@ ---- a/ath10k-6.2/pci.c -+++ b/ath10k-6.2/pci.c +--- a/ath10k-6.4/pci.c ++++ b/ath10k-6.4/pci.c @@ -131,7 +131,11 @@ static const struct ce_attr pci_host_ce_ .flags = CE_ATTR_FLAGS, .src_nentries = 0, diff --git a/package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch b/package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch index 40f262464b..8aef577deb 100644 --- a/package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch +++ b/package/kernel/ath10k-ct/patches/988-ath10k-always-use-mac80211-loss-detection.patch @@ -13,12 +13,12 @@ own loss detection mechanism. Signed-off-by: David Bauer --- - ath10k-6.2/mac.c | 1 - + ath10k-6.4/mac.c | 1 - 1 file changed, 1 deletion(-) ---- a/ath10k-6.2/mac.c -+++ b/ath10k-6.2/mac.c -@@ -11306,7 +11306,6 @@ int ath10k_mac_register(struct ath10k *a +--- a/ath10k-6.4/mac.c ++++ b/ath10k-6.4/mac.c +@@ -11305,7 +11305,6 @@ int ath10k_mac_register(struct ath10k *a ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); ieee80211_hw_set(ar->hw, QUEUE_CONTROL); ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG);