From b2058f5be42cfea0aa893aa691a3a56042948ddd Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 16 Jun 2023 23:16:30 +0800 Subject: [PATCH] mediatek: filogic: add JCG Q30 support Hardware specification: SoC: MediaTek MT7981B 2x A53 Flash: Winbond 128MB RAM: DDR3 256MB Ethernet: 4x 10/100/1000 Mbps Switch: MediaTek MT7531AE WiFi: MediaTek MT7976C Button: Reset Power: DC 12V 1A Flash instructions: 1. Connect to your PC via the Gigabit port of the router, set a static ip on the ethernet interface of your PC. (ip 192.168.1.254, gateway 192.168.1.1) 2. Attach UART, pause at u-boot menu. 3. Select "Upgrade ATF BL2", then use preloader.bin 4. Select "Upgrade ATF FIP", then use bl31-uboot.fip 5. Download the initramfs image, and type "reset", waiting for tftp recovery to complete. 6. After openwrt boots up, perform sysupgrade. Note: 1. Since NMBM is disabled, we must back up all partitions. 2. Although we can upgrade new firmware in the stock firmware, we need the special fit image signature of MediaTek and dual boot (hack kernel) to make u-boot boot it. So just abandon these hacks and flash it via the serial port. Signed-off-by: Chukun Pan (cherry picked from commit 626344c9926dcf2db2e10681c19aab0328fee160) --- package/boot/uboot-mediatek/Makefile | 2 +- .../mediatek/dts/mt7981b-jcg-q30-ubootmod.dts | 256 ++---------------- target/linux/mediatek/dts/mt7981b-jcg-q30.dts | 240 ++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 6 +- .../base-files/lib/upgrade/platform.sh | 1 + target/linux/mediatek/image/filogic.mk | 29 ++ 7 files changed, 300 insertions(+), 235 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7981b-jcg-q30.dts diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 5e7766c369..db403611be 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -559,7 +559,7 @@ UBOOT_TARGETS := \ mt7981_cmcc_rax3000m-emmc \ mt7981_cmcc_rax3000m-nand \ mt7981_h3c_magic-nx30-pro \ - mt7981_jcg_q30-pro \ + mt7981_jcg_q30 \ mt7981_rfb-spim-nand \ mt7981_rfb-emmc \ mt7981_rfb-nor \ diff --git a/target/linux/mediatek/dts/mt7981b-jcg-q30-ubootmod.dts b/target/linux/mediatek/dts/mt7981b-jcg-q30-ubootmod.dts index 8e4ddf10b6..04a93a096d 100644 --- a/target/linux/mediatek/dts/mt7981b-jcg-q30-ubootmod.dts +++ b/target/linux/mediatek/dts/mt7981b-jcg-q30-ubootmod.dts @@ -4,246 +4,38 @@ */ /dts-v1/; -#include -#include - -#include "mt7981.dtsi" +#include "mt7981-jcg-q30.dts" / { model = "JCG Q30 (custom U-Boot layout)"; compatible = "jcg,q30-ubootmod", "mediatek,mt7981"; +}; - aliases { - led-boot = &status_red_led; - led-failsafe = &status_red_led; - led-running = &status_blue_led; - led-upgrade = &status_blue_led; - serial0 = &uart0; +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; +}; + +&spi0_flash_pins { + conf-pu { + /delete-property/ mediatek,pull-up-adv; + bias-pull-up = ; }; - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x10000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-reset { - label = "reset"; - linux,code = ; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "wps"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status_red_led: led-0 { - label = "red:status"; - gpios = <&pio 8 GPIO_ACTIVE_HIGH>; - }; - - status_blue_led: led-1 { - label = "blue:status"; - gpios = <&pio 13 GPIO_ACTIVE_LOW>; - }; + conf-pd { + /delete-property/ mediatek,pull-up-adv; + bias-pull-up = ; }; }; -ð { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - nvmem-cells = <&macaddr_factory_a002a 0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; -}; - -&mdio_bus { - switch: switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - - spi-cal-enable; - spi-cal-mode = "read-data"; - spi-cal-datalen = <7>; - spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; - spi-cal-addrlen = <5>; - spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; - - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x100000>; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x100000 0x80000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x200000>; - - compatible = "nvmem-cells"; - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_a002a: macaddr@a002a { - compatible = "mac-base"; - reg = <0xa002a 0x6>; - #nvmem-cell-cells = <1>; - }; - - macaddr_factory_a0024: macaddr@a0024 { - compatible = "mac-base"; - reg = <0xa0024 0x6>; - #nvmem-cell-cells = <1>; - }; - }; - }; - - partition@380000 { - label = "FIP"; - reg = <0x380000 0x200000>; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x6e80000>; - }; - }; - }; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - - nvmem-cells = <&macaddr_factory_a0024 0>; - nvmem-cell-names = "mac-address"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = <8>; - bias-pull-up = <103>; - }; - - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = <8>; - bias-pull-down = <103>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&wifi { - status = "okay"; - - mediatek,mtd-eeprom = <&factory 0x0>; +&ubi { + reg = <0x580000 0x6e80000>; }; diff --git a/target/linux/mediatek/dts/mt7981b-jcg-q30.dts b/target/linux/mediatek/dts/mt7981b-jcg-q30.dts new file mode 100644 index 0000000000..a22919263d --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-jcg-q30.dts @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include + +#include "mt7981.dtsi" + +/ { + model = "JCG Q30"; + compatible = "jcg,q30", "mediatek,mt7981"; + + aliases { + led-boot = &status_red_led; + led-failsafe = &status_red_led; + led-running = &status_blue_led; + led-upgrade = &status_blue_led; + serial0 = &uart0; + label-mac-device = &gmac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_red_led: led-0 { + label = "red:status"; + gpios = <&pio 8 GPIO_ACTIVE_HIGH>; + }; + + status_blue_led: led-1 { + label = "blue:status"; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cells = <&macaddr_factory_a002a 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; +}; + +&mdio_bus { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x00000 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + compatible = "nvmem-cells"; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_a002a: macaddr@a002a { + compatible = "mac-base"; + reg = <0xa002a 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_a0024: macaddr@a0024 { + compatible = "mac-base"; + reg = <0xa0024 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + ubi: partition@580000 { + label = "ubi"; + reg = <0x580000 0x7000000>; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + + nvmem-cells = <&macaddr_factory_a0024 0>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index a95c5a2364..ea48ccf7b9 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -40,6 +40,7 @@ mediatek_setup_interfaces() cetron,ct3003-ubootmod|\ cmcc,a10-ubootmod|\ cudy,wr3000-v1|\ + jcg,q30|\ jcg,q30-ubootmod|\ livinet,zr-3020|\ livinet,zr-3020-ubootmod|\ diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index c6a4307305..6707a0ffb9 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -90,9 +90,11 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; + jcg,q30|\ jcg,q30-ubootmod) - [ "$PHYNBR" = "1" ] && \ - macaddr_setbit_la "$(mtd_get_mac_binary Factory 0x4)" > /sys${DEVPATH}/macaddress + # Originally, phy1 is phy0 mac with LA bit set. However, this would conflict + # addresses on multiple VIFs with the other radio. Use label mac to set LA bit. + [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(get_mac_label) > /sys${DEVPATH}/macaddress ;; livinet,zr-3020|\ livinet,zr-3020-ubootmod) diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index d034a81d66..2436832bb2 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -109,6 +109,7 @@ platform_do_upgrade() { nand_do_upgrade "$1" ;; h3c,magic-nx30-pro|\ + jcg,q30|\ mediatek,mt7981-rfb|\ qihoo,360t7|\ tplink,tl-xdr4288|\ diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index d288c1e661..1826438760 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -472,6 +472,35 @@ define Device/imou_lc-hx3001-ubootmod endef TARGET_DEVICES += imou_lc-hx3001-ubootmod +define Device/jcg_q30 + DEVICE_VENDOR := JCG + DEVICE_MODEL := Q30 (OpenWrt U-Boot layout) + DEVICE_ALT0_VENDOR := JCG + DEVICE_ALT0_MODEL := Q30 Pro (OpenWrt U-Boot layout) + DEVICE_ALT1_VENDOR := CMCC + DEVICE_ALT1_MODEL := MR3000D-CIq (OpenWrt U-Boot layout) + SUPPORTED_DEVICES += jcg,q30-pro + DEVICE_DTS := mt7981b-jcg-q30 + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot jcg_q30 +endef +TARGET_DEVICES += jcg_q30 + define Device/jcg_q30-ubootmod DEVICE_VENDOR := JCG DEVICE_MODEL := Q30 (custom U-Boot layout)