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rockchip: 5.15: refresh patches

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Removed upstream patches:
- 006-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch
- 101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch
- 102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch
- 104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch
- 600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch

Manually rebased patches:
- 103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
- 203-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
- 204-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch

All other patches were automatically refreshed.

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2022-03-29 03:16:53 +08:00
parent 01d390e9c3
commit b45e271e95
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
23 changed files with 54 additions and 438 deletions
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2
target/linux/rockchip/patches-5.15/005-rockchip-rk3328-add-compatible-to-NanoPi-R2S-etherne.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -138,6 +138,8 @@
@@ -156,6 +156,8 @@
#size-cells = <0>;
rtl8211e: ethernet-phy@1 {

177
target/linux/rockchip/patches-5.15/006-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch
View File

@ -1,177 +0,0 @@
From db792e9adbf85ffc9d6b0b060ac3c8e3148c8992 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Fri, 19 Mar 2021 13:16:27 +0800
Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S
This adds support for the NanoPi R4S from FriendlyArm.
Rockchip RK3399 SoC
1GB DDR3 or 4GB LPDDR4 RAM
Gigabit Ethernet (WAN)
Gigabit Ethernet (PCIe) (LAN)
USB 3.0 Port x 2
MicroSD slot
Reset button
WAN - LAN - SYS LED
Co-developed-by: Jensen Huang <jensenhuang@friendlyarm.com>
Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
[minor adjustments]
Co-developed-by: Marty Jones <mj8263788@gmail.com>
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[further adjustments, fixed format issues]
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20210319051627.814-2-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 133 +++++++++++++++++++++
2 files changed, 134 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ *
+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
+ * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
+ * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R4S";
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
+
+ /delete-node/ display-subsystem;
+
+ gpio-leds {
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+
+ /delete-node/ led-0;
+
+ lan_led: led-lan {
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "green:lan";
+ };
+
+ sys_led: led-sys {
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "red:sys";
+ default-state = "on";
+ };
+
+ wan_led: led-wan {
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ label = "green:wan";
+ };
+ };
+
+ gpio-keys {
+ pinctrl-0 = <&reset_button_pin>;
+
+ /delete-node/ power;
+
+ reset {
+ debounce-interval = <50>;
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&emmc_phy {
+ status = "disabled";
+};
+
+&i2c4 {
+ status = "disabled";
+};
+
+&pcie0 {
+ max-link-speed = <1>;
+ num-lanes = <1>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+};
+
+&pinctrl {
+ gpio-leds {
+ /delete-node/ status-led-pin;
+
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led_pin: sys-led-pin {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rockchip-key {
+ /delete-node/ power-key;
+
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdhci {
+ status = "disabled";
+};
+
+&sdio0 {
+ status = "disabled";
+};
+
+&u2phy0_host {
+ phy-supply = <&vdd_5v>;
+};
+
+&u2phy1_host {
+ status = "disabled";
+};
+
+&uart0 {
+ status = "disabled";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_sys>;
+};

6
target/linux/rockchip/patches-5.15/100-rockchip-use-system-LED-for-OpenWrt.patch
View File

@ -15,9 +15,9 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -13,6 +13,13 @@
model = "FriendlyElec NanoPi R2S";
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
@@ -18,6 +18,13 @@
mmc0 = &sdmmc;
};
+ aliases {
+ led-boot = &sys_led;

70
target/linux/rockchip/patches-5.15/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch
View File

@ -1,70 +0,0 @@
From: William Wu <william.wu@rock-chips.com>
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
---
NOTE: This binding still has issues. From the original thread:
the rk3328 usb3-phy has an issue with detecting any plugin events
after a previous device got removed - see the inno-usb3-phy driver
in the vendor kernel.
The current state is good-enough for enabling the USB3 attached LAN
port of the NanoPi R2S. However, it might explode depending on your
use-case. You've been warned.
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -985,22 +985,30 @@
};
usbdrd3: usb@ff600000 {
- compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
- reg = <0x0 0xff600000 0x0 0x100000>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
<&cru ACLK_USB3OTG>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk";
- dr_mode = "otg";
- phy_type = "utmi_wide";
- snps,dis-del-phy-power-chg-quirk;
- snps,dis_enblslpm_quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
status = "disabled";
+
+ usbdrd_dwc3: dwc3@ff600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff600000 0x0 0x100000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
};
gic: interrupt-controller@ff811000 {

60
target/linux/rockchip/patches-5.15/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch
View File

@ -1,60 +0,0 @@
From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Fri, 10 Jul 2020 21:12:16 +0200
Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S
Enable the USB3 port on the FriendlyARM NanoPi R2S.
This is required for the USB3 attached LAN port to work.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
.../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -103,6 +103,18 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ vdd_5v_lan: vdd-5v-lan {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&lan_vdd_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vdd_5v_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
};
&cpu0 {
@@ -313,6 +325,12 @@
};
};
+ lan {
+ lan_vdd_pin: lan-vdd-pin {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -379,3 +397,12 @@
&usb_host0_ohci {
status = "okay";
};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ dr_mode = "host";
+ status = "okay";
+};

18
target/linux/rockchip/patches-5.15/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
View File

@ -14,15 +14,17 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -405,4 +405,11 @@
&usbdrd_dwc3 {
dr_mode = "host";
status = "okay";
+
+ usb_eth: usb-eth@2 {
@@ -403,9 +403,11 @@
#size-cells = <0>;
/* Second port is for USB 3.0 */
- rtl8153: device@2 {
- compatible = "usbbda,8153";
+ rtl8153: usb-eth@2 {
+ compatible = "realtek,rtl8153";
+ reg = <2>;
reg = <2>;
+
+ realtek,led-data = <0x87>;
+ };
};
};

32
target/linux/rockchip/patches-5.15/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch
View File

@ -1,32 +0,0 @@
From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001
From: Vicente Bergas <vicencb@gmail.com>
Date: Tue, 1 Dec 2020 16:41:32 +0100
Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4
Based on the board schematics at
https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf
on page 19 there is an USB Type-A receptacle being used as an USB-OTG port.
But the Type-A connector is not valid for OTG operation, for this reason
there is a switch to select host or device role.
This is non-compliant and error prone because switching is manual.
So, use host mode as it corresponds for a Type-A receptacle.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
@@ -680,7 +680,7 @@
&usbdrd_dwc3_0 {
status = "okay";
- dr_mode = "otg";
+ dr_mode = "host";
};
&usbdrd3_1 {

2
target/linux/rockchip/patches-5.15/105-nanopi-r4s-sd-signalling.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -121,6 +121,11 @@
@@ -137,6 +137,11 @@
status = "disabled";
};

2
target/linux/rockchip/patches-5.15/107-mmc-core-set-initial-signal-voltage-on-power-off.patch
View File

@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1354,6 +1354,8 @@ void mmc_power_off(struct mmc_host *host
@@ -1358,6 +1358,8 @@ void mmc_power_off(struct mmc_host *host
mmc_pwrseq_power_off(host);

2
target/linux/rockchip/patches-5.15/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch
View File

@ -9,7 +9,7 @@ Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -169,6 +169,10 @@
@@ -175,6 +175,10 @@
};
};

4
target/linux/rockchip/patches-5.15/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch
View File

@ -1,13 +1,13 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
@@ -0,0 +1,39 @@

10
target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
@ -51,12 +51,12 @@
+ label = "nanopi-r2c:green:lan";
+};
+
+&sys_led {
+ label = "nanopi-r2c:red:sys";
+&rtl8153 {
+ realtek,led-data = <0x78>;
+};
+
+&usb_eth {
+ realtek,led-data = <0x78>;
+&sys_led {
+ label = "nanopi-r2c:red:sys";
+};
+
+&wan_led {

12
target/linux/rockchip/patches-5.15/204-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch
View File

@ -1,13 +1,13 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,66 @@
@ -66,12 +66,12 @@
+ label = "orangepi-r1-plus-lts:green:lan";
+};
+
+&sys_led {
+ label = "orangepi-r1-plus-lts:red:sys";
+&rtl8153 {
+ realtek,led-data = <0x78>;
+};
+
+&usb_eth {
+ realtek,led-data = <0x78>;
+&sys_led {
+ label = "orangepi-r1-plus-lts:red:sys";
+};
+
+&wan_led {

39
target/linux/rockchip/patches-5.15/600-net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch
View File

@ -1,39 +0,0 @@
From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Mon, 5 Jul 2021 17:03:00 +0800
Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs
Signed-off-by: hmz007 <hmz007@gmail.com>
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 346 ++++++++++++++++++++++++++++++++++
include/linux/motorcomm_phy.h | 68 +++++++
4 files changed, 420 insertions(+)
create mode 100644 drivers/net/phy/motorcomm.c
create mode 100644 include/linux/motorcomm_phy.h
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -297,6 +297,11 @@ config MICROSEMI_PHY
help
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
+config MOTORCOMM_PHY
+ tristate "Motorcomm PHYs"
+ help
+ Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
+
config NATIONAL_PHY
tristate "National Semiconductor PHYs"
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -82,6 +82,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o
obj-$(CONFIG_MICROSEMI_PHY) += mscc/
+obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o

4
target/linux/rockchip/patches-5.15/801-char-add-support-for-rockchip-hardware-random-number.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: wevsty <ty@wevs.org>
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -398,6 +398,19 @@ config HW_RANDOM_STM32
@@ -385,6 +385,19 @@ config HW_RANDOM_STM32
If unsure, say N.
@ -35,7 +35,7 @@ Signed-off-by: wevsty <ty@wevs.org>
depends on HW_RANDOM && MACH_PIC32
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o

4
target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
View File

@ -11,7 +11,7 @@ Signed-off-by: wevsty <ty@wevs.org>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -297,6 +297,17 @@
@@ -279,6 +279,17 @@
status = "disabled";
};
@ -31,7 +31,7 @@ Signed-off-by: wevsty <ty@wevs.org>
reg = <0x0 0xff100000 0x0 0x1000>;
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1905,6 +1905,16 @@
@@ -1937,6 +1937,16 @@
};
};

8
target/linux/rockchip/patches-5.15/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch
View File

@ -13,9 +13,9 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -131,6 +131,18 @@ config ARM_TEGRA20_DEVFREQ
It reads Memory Controller counters and adjusts the operating
frequencies and voltages with OPP support.
@@ -120,6 +120,18 @@ config ARM_TEGRA_DEVFREQ
It reads ACTMON counters of memory controllers and adjusts the
operating frequencies and voltages with OPP support.
+config ARM_RK3328_DMC_DEVFREQ
+ tristate "ARM RK3328 DMC DEVFREQ Driver"
@ -40,5 +40,5 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o
# DEVFREQ Event Drivers

16
target/linux/rockchip/patches-5.15/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
View File

@ -15,11 +15,9 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
include/soc/rockchip/rockchip_sip.h | 11 +++
4 files changed, 147 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index 9273bce4d7b6..555aaf4e758d 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr
.get_parent = rockchip_ddrclk_get_parent,
};
@ -153,7 +151,7 @@ index 9273bce4d7b6..555aaf4e758d 100644
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
const char *const *parent_names,
u8 num_parents, int mux_offset,
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk
case ROCKCHIP_DDRCLK_SIP:
init.ops = &rockchip_ddrclk_sip_ops;
break;
@ -163,11 +161,9 @@ index 9273bce4d7b6..555aaf4e758d 100644
default:
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
kfree(ddrclk);
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index c186a1985bf4..ac6e6163a232 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -314,9 +314,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328
RK3328_CLKGATE_CON(14), 1, GFLAGS),
/* PD_DDR */
@ -181,11 +177,9 @@ index c186a1985bf4..ac6e6163a232 100644
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 6, GFLAGS),
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 2271a84124b0..7405aaf965ec 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -362,7 +362,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
@@ -399,7 +399,8 @@ struct clk *rockchip_clk_register_mmc(co
* DDRCLK flags, including method of setting the rate
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
*/
@ -195,8 +189,6 @@ index 2271a84124b0..7405aaf965ec 100644
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
const char *const *parent_names,
diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
index c46a9ae2a2ab..fa7e0a2d72cc 100644
--- a/include/soc/rockchip/rockchip_sip.h
+++ b/include/soc/rockchip/rockchip_sip.h
@@ -16,5 +16,16 @@

4
target/linux/rockchip/patches-5.15/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch
View File

@ -11,8 +11,8 @@ Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -1022,6 +1022,13 @@
};
@@ -1010,6 +1010,13 @@
status = "disabled";
};
+ dfi: dfi@ff790000 {

12
target/linux/rockchip/patches-5.15/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
View File

@ -24,9 +24,9 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
#include "rk3328.dtsi"
/ {
@@ -115,6 +116,72 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -121,6 +122,72 @@
regulator-boot-on;
vin-supply = <&vdd_5v>;
};
+
+ dmc: dmc {
@ -97,7 +97,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
};
&cpu0 {
@@ -137,6 +204,10 @@
@@ -143,6 +210,10 @@
status = "disabled";
};
@ -108,7 +108,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
@@ -202,6 +273,7 @@
@@ -208,6 +279,7 @@
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
@ -116,7 +116,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
@@ -216,6 +288,7 @@
@@ -222,6 +294,7 @@
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;

2
target/linux/rockchip/patches-5.15/911-kernel-dma-adjust-default-coherent_pool-to-2MiB.patch
View File

@ -9,7 +9,7 @@ Subject: [PATCH] kernel: dma: adjust default coherent_pool to 2MiB
--- a/kernel/dma/pool.c
+++ b/kernel/dma/pool.c
@@ -192,13 +192,11 @@ static int __init dma_atomic_pool_init(v
@@ -189,13 +189,11 @@ static int __init dma_atomic_pool_init(v
int ret = 0;
/*

2
target/linux/rockchip/patches-5.15/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
View File

@ -41,4 +41,4 @@ Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
+ };
};
amba: bus {
analog_sound: analog-sound {

4
target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
View File

@ -16,7 +16,7 @@ Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
@@ -33,6 +33,14 @@
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1125000>;
opp-microvolt = <1125000 1125000 1250000>;
};
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
@ -31,7 +31,7 @@ Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
cluster1_opp: opp-table1 {
@@ -72,6 +80,14 @@
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1200000>;
opp-microvolt = <1200000 1200000 1250000>;
};
+ opp08 {
+ opp-hz = /bits/ 64 <2016000000>;