diff --git a/package/boot/tfa-layerscape/Makefile b/package/boot/tfa-layerscape/Makefile index 6f0e175885..31a900412e 100644 --- a/package/boot/tfa-layerscape/Makefile +++ b/package/boot/tfa-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=tfa-layerscape -PKG_VERSION:=LSDK-20.12 +PKG_VERSION:=LSDK-21.08 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/atf -PKG_SOURCE_VERSION:=LSDK-20.12 -PKG_MIRROR_HASH:=8e3a0bd33c00657beeb2df88a881b1831aeb790751cacd4c4fdf33ffa01e956e +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=500da1f5743255b2c301b89fba4df31d05a7dfbc731fbf137a88caf86f5568d0 PKG_BUILD_DEPENDS:=tfa-layerscape/host include $(INCLUDE_DIR)/host-build.mk @@ -27,14 +27,14 @@ define Host/Compile CFLAGS="$(HOST_CFLAGS)" \ LDFLAGS="$(HOST_LDFLAGS)" $(MAKE) -C \ - $(HOST_BUILD_DIR)/plat/nxp/tools \ + $(HOST_BUILD_DIR)/tools/nxp \ CFLAGS="$(HOST_CFLAGS)" endef define Host/Install $(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/fiptool/fiptool $(STAGING_DIR_HOST)/bin/fiptool-layerscape - $(INSTALL_BIN) $(HOST_BUILD_DIR)/plat/nxp/tools/create_pbl $(STAGING_DIR_HOST)/bin/tfa-create-pbl - $(INSTALL_BIN) $(HOST_BUILD_DIR)/plat/nxp/tools/byte_swap $(STAGING_DIR_HOST)/bin/tfa-byte-swap + $(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/nxp/create_pbl $(STAGING_DIR_HOST)/bin/tfa-create-pbl + $(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/nxp/byte_swap $(STAGING_DIR_HOST)/bin/tfa-byte-swap endef define Package/tfa-generic diff --git a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch index 0567e5869b..4b74048754 100644 --- a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch +++ b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch @@ -1,32 +1,45 @@ --- a/Makefile +++ b/Makefile -@@ -448,10 +448,6 @@ endif - CRTTOOLPATH ?= tools/cert_create - CRTTOOL ?= ${CRTTOOLPATH}/cert_create${BIN_EXT} +@@ -801,10 +801,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$ + ENCTOOLPATH ?= tools/encrypt_fw + ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT} -# Variables for use with Firmware Image Package -FIPTOOLPATH ?= tools/fiptool -FIPTOOL ?= ${FIPTOOLPATH}/fiptool${BIN_EXT} - - ################################################################################ - # Include BL specific makefiles - ################################################################################ -@@ -661,14 +657,12 @@ endif + # Variables for use with sptool + SPTOOLPATH ?= tools/sptool + SPTOOL ?= ${SPTOOLPATH}/sptool${BIN_EXT} +@@ -1160,13 +1156,6 @@ endif clean: @echo " CLEAN" $(call SHELL_REMOVE_DIR,${BUILD_PLAT}) +-ifdef UNIX_MK - ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean +-else +-# Clear the MAKEFLAGS as we do not want +-# to pass the gnumake flags to nmake. +- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) clean +-endif ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean - - realclean distclean: + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean + ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean +@@ -1175,13 +1164,6 @@ realclean distclean: @echo " REALCLEAN" $(call SHELL_REMOVE_DIR,${BUILD_BASE}) $(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*) +-ifdef UNIX_MK - ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean +-else +-# Clear the MAKEFLAGS as we do not want +-# to pass the gnumake flags to nmake. +- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean +-endif + ${Q}${MAKE} --no-print-directory -C ${SPTOOLPATH} clean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean - - checkcodebase: locate-checkpatch -@@ -717,7 +711,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean +@@ -1238,7 +1220,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} @${ECHO_BLANK_LINE} endif @@ -35,7 +48,7 @@ ${Q}${FIPTOOL} create ${FIP_ARGS} $@ ${Q}${FIPTOOL} info $@ @${ECHO_BLANK_LINE} -@@ -733,21 +727,16 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT +@@ -1254,7 +1236,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT @${ECHO_BLANK_LINE} endif @@ -44,26 +57,37 @@ ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@ ${Q}${FIPTOOL} info $@ @${ECHO_BLANK_LINE} +@@ -1279,24 +1261,10 @@ ${BUILD_PLAT}/${DDR_FIP_NAME}: ${DDR_FIP @echo "Built $@ successfully" @${ECHO_BLANK_LINE} -fiptool: ${FIPTOOL} fip: ${BUILD_PLAT}/${FIP_NAME} fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME} + fip_ddr: ${BUILD_PLAT}/${DDR_FIP_NAME} -.PHONY: ${FIPTOOL} -${FIPTOOL}: -- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${FIPTOOLPATH} +- @${ECHO_BLANK_LINE} +- @echo "Building $@" +-ifdef UNIX_MK +- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH} +-else +-# Clear the MAKEFLAGS as we do not want +-# to pass the gnumake flags to nmake. +- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) +-endif +- @${ECHO_BLANK_LINE} - - cscope: - @echo " CSCOPE" - ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files + sptool: ${SPTOOL} + .PHONY: ${SPTOOL} + ${SPTOOL}: --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile -@@ -37,7 +37,7 @@ all: ${PROJECT} fip_create +@@ -38,7 +38,7 @@ all: ${PROJECT} ${PROJECT}: ${OBJECTS} Makefile - @echo " LD $@" + @echo " HOSTLD $@" - ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} + ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS) @${ECHO_BLANK_LINE} diff --git a/package/boot/tfa-layerscape/patches/003-plat-nxp-tools-fix-create_pbl-and-byte_swap-host-bui.patch b/package/boot/tfa-layerscape/patches/003-plat-nxp-tools-fix-create_pbl-and-byte_swap-host-bui.patch index 2b19d53c71..167549d55b 100644 --- a/package/boot/tfa-layerscape/patches/003-plat-nxp-tools-fix-create_pbl-and-byte_swap-host-bui.patch +++ b/package/boot/tfa-layerscape/patches/003-plat-nxp-tools-fix-create_pbl-and-byte_swap-host-bui.patch @@ -1,19 +1,19 @@ From 8a458876013991fe2f288bbe4694264b16c3b9e9 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 26 Jul 2019 15:44:10 +0800 -Subject: [PATCH 3/3] plat/nxp/tools: fix create_pbl and byte_swap host build +Subject: [PATCH 3/3] tools/nxp: fix create_pbl and byte_swap host build Not compile create_pbl and byte_swap in the process of cross compilation Signed-off-by: Biwen Li --- - plat/nxp/tools/pbl_ch2.mk | 3 --- - plat/nxp/tools/pbl_ch3.mk | 5 ----- + tools/nxp/pbl_ch2.mk | 3 --- + tools/nxp/pbl_ch3.mk | 5 ----- 2 files changed, 8 deletions(-) ---- a/plat/nxp/tools/pbl_ch2.mk -+++ b/plat/nxp/tools/pbl_ch2.mk -@@ -20,8 +20,6 @@ ifeq ($(RCW),"") +--- a/tools/nxp/pbl_ch2.mk ++++ b/tools/nxp/pbl_ch2.mk +@@ -19,8 +19,6 @@ ifeq ($(RCW),"") else # Generate header for bl2.bin $(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE} @@ -22,7 +22,7 @@ Signed-off-by: Biwen Li # Add bl2.bin to RCW ${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\ -o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;\ -@@ -43,7 +41,6 @@ ifeq ($(RCW),"") +@@ -42,7 +40,6 @@ ifeq ($(RCW),"") ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}" else # -a option appends the image for Chassis 3 devices in case of non secure boot @@ -30,9 +30,9 @@ Signed-off-by: Biwen Li ${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \ -o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ; # Swapping of RCW is required for QSPi Chassis 2 devices ---- a/plat/nxp/tools/pbl_ch3.mk -+++ b/plat/nxp/tools/pbl_ch3.mk -@@ -27,9 +27,6 @@ else +--- a/tools/nxp/pbl_ch3.mk ++++ b/tools/nxp/pbl_ch3.mk +@@ -26,9 +26,6 @@ else # Generate header for bl2.bin $(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE} @@ -42,7 +42,7 @@ Signed-off-by: Biwen Li # Add Block Copy command for bl2.bin to RCW ${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\ -o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};\ -@@ -57,8 +54,6 @@ else #SECURE_BOOT +@@ -56,8 +53,6 @@ else #SECURE_BOOT ifeq ($(RCW),"") ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}" else diff --git a/package/boot/tfa-layerscape/patches/010-gcc11.patch b/package/boot/tfa-layerscape/patches/010-gcc11.patch deleted file mode 100644 index 1cdc21a493..0000000000 --- a/package/boot/tfa-layerscape/patches/010-gcc11.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/common/runtime_svc.c -+++ b/common/runtime_svc.c -@@ -38,7 +38,7 @@ uintptr_t handle_runtime_svc(uint32_t smc_fid, - u_register_t x1, x2, x3, x4; - int index; - unsigned int idx; -- const rt_svc_desc_t *rt_svc_descs; -+ rt_svc_desc_t *rt_svc_descs = NULL; - - assert(handle); - idx = get_unique_oen_from_smc_fid(smc_fid); -@@ -48,7 +48,7 @@ uintptr_t handle_runtime_svc(uint32_t smc_fid, - if (index < 0 || index >= (int)RT_SVC_DECS_NUM) - SMC_RET1(handle, SMC_UNK); - -- rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; -+ memcpy(rt_svc_descs, (rt_svc_desc_t *)RT_SVC_DESCS_START, MAX_RT_SVCS); - - get_smc_params_from_ctx(handle, x1, x2, x3, x4); - diff --git a/package/boot/uboot-layerscape/Makefile b/package/boot/uboot-layerscape/Makefile index f02356791d..6681f21e2b 100644 --- a/package/boot/uboot-layerscape/Makefile +++ b/package/boot/uboot-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-layerscape -PKG_VERSION:=LSDK-20.04-update-290520 +PKG_VERSION:=LSDK-21.08 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot -PKG_SOURCE_VERSION:=1e55b2f9e7f56b76569089b9e950f49c1579580e -PKG_MIRROR_HASH:=46aace27e1367f40b424a64215d524a99c3bd62f49057550039e72d5a1ab7edb +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=874e871755ef84ebbf35cc247f0979ec18ed1946e4dca71006a83463b2899db1 include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/uboot-layerscape/files/fsl_ls1012a-frdm-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1012a-frdm-uEnv.txt index b0923b5922..b5da9971b6 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1012a-frdm-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1012a-frdm-uEnv.txt @@ -6,3 +6,4 @@ qspi_boot=sf probe 0:0;sf read $loadaddr 1000000 2800000;bootm $loadaddr bootargs=rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),-(firmware) bootcmd=echo starting OpenWrt ...;pfe stop;run qspi_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1012a-frwy-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1012a-frwy-sdboot-uEnv.txt index 1fcd769dc9..592158955e 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1012a-frwy-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1012a-frwy-sdboot-uEnv.txt @@ -6,3 +6,4 @@ sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 bootcmd=echo starting openwrt ...;pfe stop;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1012a-rdb-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1012a-rdb-uEnv.txt index 1d108a1b03..8d57d51ece 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1012a-rdb-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1012a-rdb-uEnv.txt @@ -5,3 +5,4 @@ qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 bootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) bootcmd=echo starting openwrt ...;pfe stop;run qspi_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1021a-iot-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1021a-iot-sdboot-uEnv.txt index ed8661bc6e..55620d6725 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1021a-iot-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1021a-iot-sdboot-uEnv.txt @@ -6,3 +6,4 @@ sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 bootcmd=echo starting openwrt ...;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-sdboot-uEnv.txt index ed8661bc6e..55620d6725 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-sdboot-uEnv.txt @@ -6,3 +6,4 @@ sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 bootcmd=echo starting openwrt ...;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-uEnv.txt index 6e39e05525..6d4647b1fd 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1021a-twr-uEnv.txt @@ -5,3 +5,4 @@ nor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $lo bootargs=root=/dev/mtdblock6 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(rcw),2m(u-boot),1m(u-boot-env),11m(reserved-1),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) cma=64M@0x0-0xb0000000 bootcmd=echo starting openwrt ...;run nor_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-sdboot-uEnv.txt index 6034033876..3c39c2263d 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-sdboot-uEnv.txt @@ -7,3 +7,4 @@ sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 bootcmd=echo starting openwrt ...;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-uEnv.txt index b381bde18f..acb61ca00a 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-uEnv.txt @@ -6,3 +6,4 @@ nor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $lo bootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) bootcmd=echo starting openwrt ...;run nor_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-sdboot-uEnv.txt index ed16dde984..303157cb80 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-sdboot-uEnv.txt @@ -6,3 +6,4 @@ sd_boot=ext4load mmc 0:1 ${loadaddr} fitImage;bootm ${loadaddr} bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 bootcmd=echo starting openwrt ...;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-uEnv.txt index 9daba4aedb..5461bba9b6 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-uEnv.txt @@ -6,3 +6,4 @@ qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) bootcmd=echo starting openwrt ...;run qspi_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-sdboot-uEnv.txt index 6034033876..3c39c2263d 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-sdboot-uEnv.txt @@ -7,3 +7,4 @@ sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 bootcmd=echo starting openwrt ...;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-uEnv.txt index d24f9ec201..e52e48802b 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-uEnv.txt @@ -6,3 +6,4 @@ qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) bootcmd=echo starting openwrt ...;run qspi_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-sdboot-uEnv.txt index b25e9c8ee7..f616cb1398 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-sdboot-uEnv.txt @@ -8,3 +8,4 @@ sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 bootcmd=echo starting openwrt ...;run mc_init;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-uEnv.txt index 6ac6216d64..210c18721d 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-uEnv.txt @@ -8,3 +8,4 @@ qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 bootargs=root=/dev/mtdblock10 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=20c0000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) bootcmd=echo starting openwrt ...;run mc_init;run qspi_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_ls2088a-rdb-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_ls2088a-rdb-uEnv.txt index eb10a88d77..946029d1f1 100644 --- a/package/boot/uboot-layerscape/files/fsl_ls2088a-rdb-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_ls2088a-rdb-uEnv.txt @@ -8,3 +8,4 @@ nor_boot=cp.b 580f00000 $fdtaddr 100000;cp.b 581000000 $loadaddr 1000000;bootm $ bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS1,115200 mtdparts=580000000.nor:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) bootcmd=echo starting openwrt ...;run mc_init;run nor_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-sdboot-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-sdboot-uEnv.txt index 6b4e920c9e..d137319915 100644 --- a/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-sdboot-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-sdboot-uEnv.txt @@ -7,3 +7,4 @@ sd_boot=ext4load mmc 0:1 ${loadaddr} fitImage;bootm ${loadaddr} bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=pl011,mmio32,0x21c0000 console=ttyAMA0,115200 bootcmd=echo starting openwrt ...;run mc_init;run sd_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-uEnv.txt b/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-uEnv.txt index 08757b4460..41fde35c88 100644 --- a/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-uEnv.txt +++ b/package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-uEnv.txt @@ -7,3 +7,4 @@ xspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=pl011,mmio32,0x21c0000 console=ttyAMA0,115200 mtdparts=20c0000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) bootcmd=echo starting openwrt ...;run mc_init;run xspi_boot bootdelay=3 +fsl_bootcmd_mcinitcmd_set=y diff --git a/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch b/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch new file mode 100644 index 0000000000..25a6b16363 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch @@ -0,0 +1,33 @@ +From 089b90b11008ec95a56da12e31d11e3f31a9bb26 Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Wed, 17 Nov 2021 07:29:55 +0100 +Subject: [PATCH] board: ls1046ardb: force PCI device enumeration + +Commit 045ecf899252 ("configs: enable DM_ETH support for LS1046ARDB") +resulted in the PCI bus no longer being implicitly enumerated. + +However, this is necessary for the fdt pcie fixups to work. + +Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb: +transition to DM_ETH"), pci_init() is now called in the board_init() +routine when CONFIG_DM_ETH is active. + +Signed-off-by: Martin Schiller +CC: Priyanka Jain +--- + board/freescale/ls1046ardb/ls1046ardb.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/board/freescale/ls1046ardb/ls1046ardb.c ++++ b/board/freescale/ls1046ardb/ls1046ardb.c +@@ -88,6 +88,10 @@ int board_init(void) + ppa_init(); + #endif + ++#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) ++ pci_init(); ++#endif ++ + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); + diff --git a/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch b/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch new file mode 100644 index 0000000000..d38102a13c --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch @@ -0,0 +1,34 @@ +From 64d2dffa8b51c1beb7e472690dcac965ac0f7ac4 Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Tue, 23 Nov 2021 07:24:19 +0100 +Subject: [PATCH] board: ls1043ardb: force PCI device enumeration + +Commit eb1986804d1d ("configs: enable DM_ETH support for LS1043ARDB") +resulted in the PCI bus no longer being implicitly enumerated. + +However, this is necessary for the fdt pcie fixups to work. + +Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb: +transition to DM_ETH"), pci_init() is now called in the board_init() +routine when CONFIG_DM_ETH is active. + +Signed-off-by: Martin Schiller +CC: Priyanka Jain +CC: Camelia Groza +--- + board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/board/freescale/ls1043ardb/ls1043ardb.c ++++ b/board/freescale/ls1043ardb/ls1043ardb.c +@@ -214,6 +214,10 @@ int board_init(void) + ppa_init(); + #endif + ++#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) ++ pci_init(); ++#endif ++ + #ifdef CONFIG_U_QE + u_qe_init(); + #endif diff --git a/package/boot/uboot-layerscape/patches/010-fix_dtc_compilation_on_host_gcc10.patch b/package/boot/uboot-layerscape/patches/010-fix_dtc_compilation_on_host_gcc10.patch deleted file mode 100644 index 6abb151608..0000000000 --- a/package/boot/uboot-layerscape/patches/010-fix_dtc_compilation_on_host_gcc10.patch +++ /dev/null @@ -1,46 +0,0 @@ -From e33a814e772cdc36436c8c188d8c42d019fda639 Mon Sep 17 00:00:00 2001 -From: Dirk Mueller -Date: Tue, 14 Jan 2020 18:53:41 +0100 -Subject: [PATCH] scripts/dtc: Remove redundant YYLOC global declaration - -gcc 10 will default to -fno-common, which causes this error at link -time: - - (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here - -This is because both dtc-lexer as well as dtc-parser define the same -global symbol yyloc. Before with -fcommon those were merged into one -defintion. The proper solution would be to to mark this as "extern", -however that leads to: - - dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls] - 26 | extern YYLTYPE yylloc; - | ^~~~~~ -In file included from dtc-lexer.l:24: -dtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here - 127 | extern YYLTYPE yylloc; - | ^~~~~~ -cc1: all warnings being treated as errors - -which means the declaration is completely redundant and can just be -dropped. - -Signed-off-by: Dirk Mueller -Signed-off-by: David Gibson -[robh: cherry-pick from upstream] -Cc: stable@vger.kernel.org -Signed-off-by: Rob Herring ---- - scripts/dtc/dtc-lexer.l | 1 - - 1 file changed, 1 deletion(-) - ---- a/scripts/dtc/dtc-lexer.l -+++ b/scripts/dtc/dtc-lexer.l -@@ -38,7 +38,6 @@ LINECOMMENT "//".*\n - #include "srcpos.h" - #include "dtc-parser.tab.h" - --YYLTYPE yylloc; - extern bool treesource_error; - - /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ diff --git a/package/firmware/layerscape/fman-ucode/Makefile b/package/firmware/layerscape/fman-ucode/Makefile index 69cc761110..f2dda04e81 100644 --- a/package/firmware/layerscape/fman-ucode/Makefile +++ b/package/firmware/layerscape/fman-ucode/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=fman-ucode -PKG_VERSION:=LSDK-20.04 -PKG_RELEASE:=2 +PKG_VERSION:=LSDK-21.08 +PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/NXP/qoriq-fm-ucode.git -PKG_SOURCE_VERSION:=c275e91392e2adab1ed22f3867b8269ca3c54014 -PKG_MIRROR_HASH:=90b619ed501462b92f34f2fabfa09d6aaa5235990891d1c3132821c7d18a39bd +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=dc905ebe71cde24e9ebbe10a7b1f08cd2ecf142e39fe1535aa5fe3f349b031b9 PKG_FLAGS:=nonshared diff --git a/package/firmware/layerscape/ls-ddr-phy/Makefile b/package/firmware/layerscape/ls-ddr-phy/Makefile index 68142b4bbf..3ae0344e78 100644 --- a/package/firmware/layerscape/ls-ddr-phy/Makefile +++ b/package/firmware/layerscape/ls-ddr-phy/Makefile @@ -6,13 +6,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-ddr-phy -PKG_VERSION:=LSDK-20.04-update-290520 +PKG_VERSION:=LSDK-21.08 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/NXP/ddr-phy-binary.git -PKG_SOURCE_VERSION:=fbc036b88acb6c06ffed02c898cbae9856ec75ba -PKG_MIRROR_HASH:=84e2bdea99384211971bb23ba9ed18b5839628ff2aa0738d2978bbdf841638cb +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=6ad8bba23a70ed50716c56093a4ee7eef3153f8c3b7446c4520412c83799bb08 PKG_BUILD_DEPENDS:=tfa-layerscape/host PKG_LICENSE:=EULA diff --git a/package/firmware/layerscape/ls-dpl/Makefile b/package/firmware/layerscape/ls-dpl/Makefile index 8ba5fafb2b..8c6a88aab2 100644 --- a/package/firmware/layerscape/ls-dpl/Makefile +++ b/package/firmware/layerscape/ls-dpl/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-dpl -PKG_VERSION:=LSDK-20.04 +PKG_VERSION:=LSDK-21.08 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/mc-utils -PKG_SOURCE_VERSION:=8672a5f5abcd3a354dcab07e03f2a8a69b2e962d -PKG_MIRROR_HASH:=4b8ad3148aee1e0c034206543472aebb435655fd03a661c4c1be545dcac7ddf0 +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=56ea7db52c1bee43c2823cff0cabc64d76b24296dfa347c9a95bc4a9542d4ed8 PKG_FLAGS:=nonshared @@ -34,17 +34,17 @@ MAKE_VARS+= \ define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) - $(CP) $(PKG_BUILD_DIR)/config/ls1088a/RDB/dpl-eth.0x1D_0x0D.dtb \ + $(CP) $(PKG_BUILD_DIR)/config/ls1088a/LS1088A-RDB/dpl-eth.0x1D_0x0D.dtb \ $(STAGING_DIR_IMAGE)/fsl_ls1088a-rdb-dpl.dtb - $(CP) $(PKG_BUILD_DIR)/config/ls1088a/RDB/dpc.0x1D-0x0D.dtb \ + $(CP) $(PKG_BUILD_DIR)/config/ls1088a/LS1088A-RDB/dpc.0x1D-0x0D.dtb \ $(STAGING_DIR_IMAGE)/fsl_ls1088a-rdb-dpc.dtb - $(CP) $(PKG_BUILD_DIR)/config/ls2088a/RDB/dpl-eth.0x2A_0x41.dtb \ + $(CP) $(PKG_BUILD_DIR)/config/ls2088a/LS2088A-RDB/dpl-eth.0x2A_0x41.dtb \ $(STAGING_DIR_IMAGE)/fsl_ls2088a-rdb-dpl.dtb - $(CP) $(PKG_BUILD_DIR)/config/ls2088a/RDB/dpc.0x2A_0x41.dtb \ + $(CP) $(PKG_BUILD_DIR)/config/ls2088a/LS2088A-RDB/dpc.0x2A_0x41.dtb \ $(STAGING_DIR_IMAGE)/fsl_ls2088a-rdb-dpc.dtb - $(CP) $(PKG_BUILD_DIR)/config/lx2160a/RDB/dpl-eth.19.dtb \ + $(CP) $(PKG_BUILD_DIR)/config/lx2160a/LX2160A-RDB/dpl-eth.19.dtb \ $(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-dpl.dtb - $(CP) $(PKG_BUILD_DIR)/config/lx2160a/RDB/dpc-usxgmii.dtb \ + $(CP) $(PKG_BUILD_DIR)/config/lx2160a/LX2160A-RDB/dpc-usxgmii.dtb \ $(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-dpc.dtb endef diff --git a/package/firmware/layerscape/ls-mc/Makefile b/package/firmware/layerscape/ls-mc/Makefile index 3b2cdebbf1..9dbc81809d 100644 --- a/package/firmware/layerscape/ls-mc/Makefile +++ b/package/firmware/layerscape/ls-mc/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-mc -PKG_VERSION:=LSDK-20.04 +PKG_VERSION:=LSDK-21.08 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/NXP/qoriq-mc-binary.git -PKG_SOURCE_VERSION:=f73683596a7b72124d67b62e64f3dc2bb36b9321 -PKG_MIRROR_HASH:=1cba30c2a6814763c3e155c1cc5fa21998bb6ad5814fcb09e99f98bf36f65d9e +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=a8b2398f7958bfc3d45b239d33e0ecd27bd46e8f34693d545590a870be22ca2b PKG_FLAGS:=nonshared @@ -32,11 +32,11 @@ endef define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) - $(CP) $(PKG_BUILD_DIR)/ls1088a/mc_10.20.4_ls1088a.itb \ + $(CP) $(PKG_BUILD_DIR)/ls1088a/mc_ls1088a_10.28.1.itb \ $(STAGING_DIR_IMAGE)/fsl_ls1088a-rdb-mc.itb - $(CP) $(PKG_BUILD_DIR)/ls2088a/mc_10.20.4_ls2088a.itb \ + $(CP) $(PKG_BUILD_DIR)/ls2088a/mc_ls2088a_10.28.1.itb \ $(STAGING_DIR_IMAGE)/fsl_ls2088a-rdb-mc.itb - $(CP) $(PKG_BUILD_DIR)/lx2160a/mc_10.20.4_lx2160a.itb \ + $(CP) $(PKG_BUILD_DIR)/lx216xa/mc_lx2160a_10.28.1.itb \ $(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-mc.itb endef diff --git a/package/firmware/layerscape/ls-rcw/Makefile b/package/firmware/layerscape/ls-rcw/Makefile index fdc5c0ce24..b9a6059d0d 100644 --- a/package/firmware/layerscape/ls-rcw/Makefile +++ b/package/firmware/layerscape/ls-rcw/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ls-rcw -PKG_VERSION:=LSDK-20.04-update-290520 +PKG_VERSION:=LSDK-21.08 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/rcw -PKG_SOURCE_VERSION:=e0fab6d9b61003caef577f7474c2fac61e6ba2ff -PKG_MIRROR_HASH:=b6bc66e27b7c6db31101fdc2e6be7255181861bd38d8f25eb5eb80c468983eb2 +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=c0202d07223bb5ab43d0c0145c0d83e2b8c34c559bba0ec3c2c2aa562623f546 PKG_FLAGS:=nonshared diff --git a/package/firmware/layerscape/ls-rcw/patches/0001-Remove-tclsh-checking.patch b/package/firmware/layerscape/ls-rcw/patches/0001-Remove-tclsh-checking.patch deleted file mode 100644 index 069686ab55..0000000000 --- a/package/firmware/layerscape/ls-rcw/patches/0001-Remove-tclsh-checking.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 786d501c32b9341d381b3371234213f92d948b66 Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Fri, 13 Mar 2020 18:15:36 +0800 -Subject: [PATCH] Remove tclsh checking - -The tclsh is no longer needed for byte swapping. - -Signed-off-by: Yangbo Lu ---- - Makefile | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/Makefile b/Makefile -index 9183e19..2832ab2 100644 ---- a/Makefile -+++ b/Makefile -@@ -12,15 +12,9 @@ BOARDS = b4420qds b4860qds \ - t1024qds t1023rdb t1024rdb t1040rdb t1042rdb t1042rdb_pi t1040qds \ - t2080rdb t2080qds t2081qds t4240qds t4240rdb t1040d4rdb t1042d4rdb - --TCLSH := $(shell command -v tclsh 2> /dev/null) -- - VER = $(shell git describe --tags) - - all install clean: --ifndef TCLSH -- $(error "tclsh is not available. please install it.") -- exit 1 --endif - @for board in $(BOARDS); do \ - $(MAKE) -C $$board $@ DESTDIR=$(DESTDIR)/$$board; \ - done --- -2.7.4 - diff --git a/package/firmware/layerscape/ppfe-firmware/Makefile b/package/firmware/layerscape/ppfe-firmware/Makefile index 96246fa0d9..4e6b69596c 100644 --- a/package/firmware/layerscape/ppfe-firmware/Makefile +++ b/package/firmware/layerscape/ppfe-firmware/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ppfe -PKG_VERSION:=LSDK-20.04 -PKG_RELEASE:=1 +PKG_VERSION:=LSDK-21.08 +PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/NXP/qoriq-engine-pfe-bin.git -PKG_SOURCE_VERSION:=d3a8ef0760c54ddc243039c86389497e37be90ab -PKG_MIRROR_HASH:=64be93b8249d298e7b5fd0846787835f0659b6ab6c55b40b809366c79e272eb8 +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=ba524b8a56c66cf8e7ebb8e742b0d6b66f9177b6fa821c405a09b6c8919e3db0 PKG_FLAGS:=nonshared diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile index e3cf2d3800..251f2f8f8b 100644 --- a/package/kernel/mac80211/Makefile +++ b/package/kernel/mac80211/Makefile @@ -10,10 +10,10 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=mac80211 -PKG_VERSION:=5.15-rc6-1 +PKG_VERSION:=5.15.8-1 PKG_RELEASE:=1 -PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15-rc6/ -PKG_HASH:=9282612c4c02ef9fc9d74405303033f6b53914cd63d631eef0f43155fcd38932 +PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.8/ +PKG_HASH:=9f71b659c034f19d156532ec780fcb606cee3c4ccc42e2f8ef18dd3e9f1b6820 PKG_SOURCE:=backports-$(PKG_VERSION).tar.xz PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/backports-$(PKG_VERSION) diff --git a/package/kernel/mac80211/patches/ath10k/081-ath10k-fix-module-load-regression-with-iram-recovery-feature.patch b/package/kernel/mac80211/patches/ath10k/081-ath10k-fix-module-load-regression-with-iram-recovery-feature.patch deleted file mode 100644 index 7a7d08be48..0000000000 --- a/package/kernel/mac80211/patches/ath10k/081-ath10k-fix-module-load-regression-with-iram-recovery-feature.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 6f8c8bf4c7c9be1c42088689fd4370e06b46608a Mon Sep 17 00:00:00 2001 -From: Abinaya Kalaiselvan -Date: Wed, 20 Oct 2021 11:59:07 +0300 -Subject: ath10k: fix module load regression with iram-recovery feature - -Commit 9af7c32ceca8 ("ath10k: add target IRAM recovery feature support") -introduced a new firmware feature flag ATH10K_FW_FEATURE_IRAM_RECOVERY. But -this caused ath10k_pci module load to fail if ATH10K_FW_CRASH_DUMP_RAM_DATA bit -was not enabled in the ath10k coredump_mask module parameter: - -[ 2209.328190] ath10k_pci 0000:02:00.0: qca9984/qca9994 hw1.0 target 0x01000000 chip_id 0x00000000 sub 168c:cafe -[ 2209.434414] ath10k_pci 0000:02:00.0: kconfig debug 1 debugfs 1 tracing 1 dfs 1 testmode 1 -[ 2209.547191] ath10k_pci 0000:02:00.0: firmware ver 10.4-3.9.0.2-00099 api 5 features no-p2p,mfp,peer-flow-ctrl,btcoex-param,allows-mesh-bcast,no-ps,peer-fixed-rate,iram-recovery crc32 cbade90a -[ 2210.896485] ath10k_pci 0000:02:00.0: board_file api 1 bmi_id 0:1 crc32 a040efc2 -[ 2213.603339] ath10k_pci 0000:02:00.0: failed to copy target iram contents: -12 -[ 2213.839027] ath10k_pci 0000:02:00.0: could not init core (-12) -[ 2213.933910] ath10k_pci 0000:02:00.0: could not probe fw (-12) - -And by default coredump_mask does not have ATH10K_FW_CRASH_DUMP_RAM_DATA -enabled so anyone using a firmware with iram-recovery feature would fail. To my -knowledge only QCA9984 firmwares starting from release 10.4-3.9.0.2-00099 -enabled the feature. - -The reason for regression was that ath10k_core_copy_target_iram() used -ath10k_coredump_get_mem_layout() to get the memory layout, but when -ATH10K_FW_CRASH_DUMP_RAM_DATA was disabled it would get just NULL and bail out -with an error. - -While looking at all this I noticed another bug: if CONFIG_DEV_COREDUMP is -disabled but the firmware has iram-recovery enabled the module load fails with -similar error messages. I fixed that by returning 0 from -ath10k_core_copy_target_iram() when _ath10k_coredump_get_mem_layout() returns -NULL. - -Tested-on: QCA9984 hw2.0 PCI 10.4-3.9.0.2-00139 - -Fixes: 9af7c32ceca8 ("ath10k: add target IRAM recovery feature support") -Signed-off-by: Abinaya Kalaiselvan -Signed-off-by: Jouni Malinen -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20211020075054.23061-1-kvalo@codeaurora.org ---- - drivers/net/wireless/ath/ath10k/core.c | 11 +++++++++-- - drivers/net/wireless/ath/ath10k/coredump.c | 11 ++++++++--- - drivers/net/wireless/ath/ath10k/coredump.h | 7 +++++++ - 3 files changed, 24 insertions(+), 5 deletions(-) - ---- a/drivers/net/wireless/ath/ath10k/core.c -+++ b/drivers/net/wireless/ath/ath10k/core.c -@@ -2690,9 +2690,16 @@ static int ath10k_core_copy_target_iram( - int i, ret; - u32 len, remaining_len; - -- hw_mem = ath10k_coredump_get_mem_layout(ar); -+ /* copy target iram feature must work also when -+ * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so -+ * _ath10k_coredump_get_mem_layout() to accomplist that -+ */ -+ hw_mem = _ath10k_coredump_get_mem_layout(ar); - if (!hw_mem) -- return -ENOMEM; -+ /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then -+ * just silently disable the feature by doing nothing -+ */ -+ return 0; - - for (i = 0; i < hw_mem->region_table.size; i++) { - tmp = &hw_mem->region_table.regions[i]; ---- a/drivers/net/wireless/ath/ath10k/coredump.c -+++ b/drivers/net/wireless/ath/ath10k/coredump.c -@@ -1447,11 +1447,17 @@ static u32 ath10k_coredump_get_ramdump_s - - const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k *ar) - { -- int i; -- - if (!test_bit(ATH10K_FW_CRASH_DUMP_RAM_DATA, &ath10k_coredump_mask)) - return NULL; - -+ return _ath10k_coredump_get_mem_layout(ar); -+} -+EXPORT_SYMBOL(ath10k_coredump_get_mem_layout); -+ -+const struct ath10k_hw_mem_layout *_ath10k_coredump_get_mem_layout(struct ath10k *ar) -+{ -+ int i; -+ - if (WARN_ON(ar->target_version == 0)) - return NULL; - -@@ -1464,7 +1470,6 @@ const struct ath10k_hw_mem_layout *ath10 - - return NULL; - } --EXPORT_SYMBOL(ath10k_coredump_get_mem_layout); - - struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar) - { ---- a/drivers/net/wireless/ath/ath10k/coredump.h -+++ b/drivers/net/wireless/ath/ath10k/coredump.h -@@ -176,6 +176,7 @@ int ath10k_coredump_register(struct ath1 - void ath10k_coredump_unregister(struct ath10k *ar); - void ath10k_coredump_destroy(struct ath10k *ar); - -+const struct ath10k_hw_mem_layout *_ath10k_coredump_get_mem_layout(struct ath10k *ar); - const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k *ar); - - #else /* CONFIG_DEV_COREDUMP */ -@@ -213,6 +214,12 @@ ath10k_coredump_get_mem_layout(struct at - { - return NULL; - } -+ -+static inline const struct ath10k_hw_mem_layout * -+_ath10k_coredump_get_mem_layout(struct ath10k *ar) -+{ -+ return NULL; -+} - - #endif /* CONFIG_DEV_COREDUMP */ - diff --git a/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch b/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch index e4e72786fe..b60db19464 100644 --- a/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch +++ b/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -9820,6 +9820,21 @@ static int ath10k_mac_init_rd(struct ath +@@ -9843,6 +9843,21 @@ static int ath10k_mac_init_rd(struct ath return 0; } @@ -22,7 +22,7 @@ int ath10k_mac_register(struct ath10k *ar) { static const u32 cipher_suites[] = { -@@ -10172,6 +10187,12 @@ int ath10k_mac_register(struct ath10k *a +@@ -10195,6 +10210,12 @@ int ath10k_mac_register(struct ath10k *a ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; diff --git a/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch b/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch index cc491feace..65d67b2e03 100644 --- a/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch +++ b/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch @@ -467,7 +467,7 @@ v13: static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = { --- a/drivers/net/wireless/ath/ath10k/wmi.c +++ b/drivers/net/wireless/ath/ath10k/wmi.c -@@ -7468,6 +7468,49 @@ ath10k_wmi_op_gen_peer_set_param(struct +@@ -7472,6 +7472,49 @@ ath10k_wmi_op_gen_peer_set_param(struct return skb; } @@ -517,7 +517,7 @@ v13: static struct sk_buff * ath10k_wmi_op_gen_set_psmode(struct ath10k *ar, u32 vdev_id, enum wmi_sta_ps_mode psmode) -@@ -9156,6 +9199,9 @@ static const struct wmi_ops wmi_ops = { +@@ -9160,6 +9203,9 @@ static const struct wmi_ops wmi_ops = { .fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill, .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, .gen_echo = ath10k_wmi_op_gen_echo, @@ -527,7 +527,7 @@ v13: /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ -@@ -9226,6 +9272,8 @@ static const struct wmi_ops wmi_10_1_ops +@@ -9230,6 +9276,8 @@ static const struct wmi_ops wmi_10_1_ops .fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill, .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, .gen_echo = ath10k_wmi_op_gen_echo, @@ -536,7 +536,7 @@ v13: /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ -@@ -9298,6 +9346,8 @@ static const struct wmi_ops wmi_10_2_ops +@@ -9302,6 +9350,8 @@ static const struct wmi_ops wmi_10_2_ops .gen_delba_send = ath10k_wmi_op_gen_delba_send, .fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill, .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, @@ -545,7 +545,7 @@ v13: /* .gen_pdev_enable_adaptive_cca not implemented */ }; -@@ -9369,6 +9419,8 @@ static const struct wmi_ops wmi_10_2_4_o +@@ -9373,6 +9423,8 @@ static const struct wmi_ops wmi_10_2_4_o ath10k_wmi_op_gen_pdev_enable_adaptive_cca, .get_vdev_subtype = ath10k_wmi_10_2_4_op_get_vdev_subtype, .gen_bb_timing = ath10k_wmi_10_2_4_op_gen_bb_timing, @@ -554,7 +554,7 @@ v13: /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ -@@ -9450,6 +9502,8 @@ static const struct wmi_ops wmi_10_4_ops +@@ -9454,6 +9506,8 @@ static const struct wmi_ops wmi_10_4_ops .gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info, .gen_echo = ath10k_wmi_op_gen_echo, .gen_pdev_get_tpc_config = ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config, @@ -565,7 +565,7 @@ v13: int ath10k_wmi_attach(struct ath10k *ar) --- a/drivers/net/wireless/ath/ath10k/wmi.h +++ b/drivers/net/wireless/ath/ath10k/wmi.h -@@ -3027,6 +3027,41 @@ enum wmi_10_4_feature_mask { +@@ -3030,6 +3030,41 @@ enum wmi_10_4_feature_mask { }; diff --git a/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch b/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch index 1529abfad0..da31ad578a 100644 --- a/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch +++ b/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch @@ -42,7 +42,7 @@ Signed-off-by: Mathias Kresin if (ret) --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -10189,7 +10189,7 @@ int ath10k_mac_register(struct ath10k *a +@@ -10212,7 +10212,7 @@ int ath10k_mac_register(struct ath10k *a ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; #ifdef CPTCFG_MAC80211_LEDS diff --git a/package/kernel/mac80211/patches/ath10k/980-ath10k-fix-max-antenna-gain-unit.patch b/package/kernel/mac80211/patches/ath10k/980-ath10k-fix-max-antenna-gain-unit.patch deleted file mode 100644 index f3f3b1b921..0000000000 --- a/package/kernel/mac80211/patches/ath10k/980-ath10k-fix-max-antenna-gain-unit.patch +++ /dev/null @@ -1,49 +0,0 @@ -From: Sven Eckelmann -Date: Tue, 11 Jun 2019 13:58:35 +0200 -Subject: ath10k: fix max antenna gain unit - -Most of the txpower for the ath10k firmware is stored as twicepower (0.5 dB -steps). This isn't the case for max_antenna_gain - which is still expected -by the firmware as dB. - -The firmware is converting it from dB to the internal (twicepower) -representation when it calculates the limits of a channel. This can be seen -in tpc_stats when configuring "12" as max_antenna_gain. Instead of the -expected 12 (6 dB), the tpc_stats shows 24 (12 dB). - -Tested on QCA9888 and IPQ4019 with firmware 10.4-3.5.3-00057. - -Fixes: 02256930d9b8 ("ath10k: use proper tx power unit") -Signed-off-by: Sven Eckelmann - -Forwarded: https://patchwork.kernel.org/patch/10986723/ - ---- a/drivers/net/wireless/ath/ath10k/mac.c -+++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -1049,7 +1049,7 @@ static int ath10k_monitor_vdev_start(str - arg.channel.min_power = 0; - arg.channel.max_power = channel->max_power * 2; - arg.channel.max_reg_power = channel->max_reg_power * 2; -- arg.channel.max_antenna_gain = channel->max_antenna_gain * 2; -+ arg.channel.max_antenna_gain = channel->max_antenna_gain; - - reinit_completion(&ar->vdev_setup_done); - reinit_completion(&ar->vdev_delete_done); -@@ -1495,7 +1495,7 @@ static int ath10k_vdev_start_restart(str - arg.channel.min_power = 0; - arg.channel.max_power = chandef->chan->max_power * 2; - arg.channel.max_reg_power = chandef->chan->max_reg_power * 2; -- arg.channel.max_antenna_gain = chandef->chan->max_antenna_gain * 2; -+ arg.channel.max_antenna_gain = chandef->chan->max_antenna_gain; - - if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { - arg.ssid = arvif->u.ap.ssid; -@@ -3423,7 +3423,7 @@ static int ath10k_update_channel_list(st - ch->min_power = 0; - ch->max_power = channel->max_power * 2; - ch->max_reg_power = channel->max_reg_power * 2; -- ch->max_antenna_gain = channel->max_antenna_gain * 2; -+ ch->max_antenna_gain = channel->max_antenna_gain; - ch->reg_class_id = 0; /* FIXME */ - - /* FIXME: why use only legacy modes, why not any diff --git a/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch b/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch index 9f7ac903eb..a45addf119 100644 --- a/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch +++ b/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch @@ -28,7 +28,7 @@ Forwarded: no --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -1017,6 +1017,40 @@ static inline int ath10k_vdev_setup_sync +@@ -1021,6 +1021,40 @@ static inline int ath10k_vdev_setup_sync return ar->last_wmi_vdev_start_status; } @@ -69,7 +69,7 @@ Forwarded: no static int ath10k_monitor_vdev_start(struct ath10k *ar, int vdev_id) { struct cfg80211_chan_def *chandef = NULL; -@@ -1049,7 +1083,8 @@ static int ath10k_monitor_vdev_start(str +@@ -1053,7 +1087,8 @@ static int ath10k_monitor_vdev_start(str arg.channel.min_power = 0; arg.channel.max_power = channel->max_power * 2; arg.channel.max_reg_power = channel->max_reg_power * 2; @@ -79,7 +79,7 @@ Forwarded: no reinit_completion(&ar->vdev_setup_done); reinit_completion(&ar->vdev_delete_done); -@@ -1495,7 +1530,8 @@ static int ath10k_vdev_start_restart(str +@@ -1499,7 +1534,8 @@ static int ath10k_vdev_start_restart(str arg.channel.min_power = 0; arg.channel.max_power = chandef->chan->max_power * 2; arg.channel.max_reg_power = chandef->chan->max_reg_power * 2; @@ -89,7 +89,7 @@ Forwarded: no if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { arg.ssid = arvif->u.ap.ssid; -@@ -3423,7 +3459,8 @@ static int ath10k_update_channel_list(st +@@ -3427,7 +3463,8 @@ static int ath10k_update_channel_list(st ch->min_power = 0; ch->max_power = channel->max_power * 2; ch->max_reg_power = channel->max_reg_power * 2; diff --git a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch index 85c5a9deb6..5b64f560fd 100644 --- a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch +++ b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch @@ -125,9 +125,9 @@ REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c -@@ -536,6 +536,11 @@ irqreturn_t ath_isr(int irq, void *dev) - if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) +@@ -538,6 +538,11 @@ irqreturn_t ath_isr(int irq, void *dev) return IRQ_HANDLED; + } + if (test_bit(ATH_DIAG_TRIGGER_ERROR, &ah->diag)) { + status |= ATH9K_INT_FATAL; diff --git a/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch b/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch index 1010f75807..cb6374feb0 100644 --- a/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch +++ b/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch @@ -339,7 +339,7 @@ static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u32 queues, bool drop); -@@ -657,6 +658,7 @@ void ath_reset_work(struct work_struct * +@@ -659,6 +660,7 @@ void ath_reset_work(struct work_struct * static int ath9k_start(struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; @@ -347,7 +347,7 @@ struct ath_hw *ah = sc->sc_ah; struct ath_common *common = ath9k_hw_common(ah); struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; -@@ -735,6 +737,11 @@ static int ath9k_start(struct ieee80211_ +@@ -737,6 +739,11 @@ static int ath9k_start(struct ieee80211_ AR_GPIO_OUTPUT_MUX_AS_OUTPUT); } diff --git a/package/kernel/mac80211/patches/build/010-headers-Add-devm_platform_get_and_ioremap_resource.patch b/package/kernel/mac80211/patches/build/010-headers-Add-devm_platform_get_and_ioremap_resource.patch deleted file mode 100644 index a06c619471..0000000000 --- a/package/kernel/mac80211/patches/build/010-headers-Add-devm_platform_get_and_ioremap_resource.patch +++ /dev/null @@ -1,79 +0,0 @@ -From d49395058c6bd4fb7b8bcc5ff7b4d7fbd9b6f97b Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 24 Oct 2021 14:49:55 +0200 -Subject: [PATCH] headers: Add devm_platform_get_and_ioremap_resource() - -This function is copied from kernel 5.7 and used by mt76, ath10k and -ath11k. devm_platform_ioremap_resource() was changed to make sue of -this new function. - -Signed-off-by: Hauke Mehrtens ---- - .../backport-include/linux/platform_device.h | 45 ++++++++++++++++--- - 1 file changed, 38 insertions(+), 7 deletions(-) - ---- a/backport-include/linux/platform_device.h -+++ b/backport-include/linux/platform_device.h -@@ -33,7 +33,39 @@ module_exit(__platform_driver##_exit); - platform_driver_unregister) - #endif - -+#if LINUX_VERSION_IS_LESS(5,7,0) -+#ifdef CONFIG_HAS_IOMEM -+#define devm_platform_get_and_ioremap_resource LINUX_BACKPORT(devm_platform_get_and_ioremap_resource) -+/** -+ * devm_platform_get_and_ioremap_resource - call devm_ioremap_resource() for a -+ * platform device and get resource -+ * -+ * @pdev: platform device to use both for memory resource lookup as well as -+ * resource management -+ * @index: resource index -+ * @res: optional output parameter to store a pointer to the obtained resource. -+ * -+ * Return: a pointer to the remapped memory or an ERR_PTR() encoded error code -+ * on failure. -+ */ -+static inline void __iomem * -+devm_platform_get_and_ioremap_resource(struct platform_device *pdev, -+ unsigned int index, struct resource **res) -+{ -+ struct resource *r; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, index); -+ if (res) -+ *res = r; -+ return devm_ioremap_resource(&pdev->dev, r); -+} -+#endif /* CONFIG_HAS_IOMEM */ -+#endif /* < 5.7 */ -+ - #if LINUX_VERSION_IS_LESS(5,1,0) -+ -+#ifdef CONFIG_HAS_IOMEM -+#define devm_platform_ioremap_resource LINUX_BACKPORT(devm_platform_ioremap_resource) - /** - * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform - * device -@@ -41,16 +73,15 @@ module_exit(__platform_driver##_exit); - * @pdev: platform device to use both for memory resource lookup as well as - * resource management - * @index: resource index -+ * -+ * Return: a pointer to the remapped memory or an ERR_PTR() encoded error code -+ * on failure. - */ --#ifdef CONFIG_HAS_IOMEM --#define devm_platform_ioremap_resource LINUX_BACKPORT(devm_platform_ioremap_resource) --static inline void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, -+static inline void __iomem * -+devm_platform_ioremap_resource(struct platform_device *pdev, - unsigned int index) - { -- struct resource *res; -- -- res = platform_get_resource(pdev, IORESOURCE_MEM, index); -- return devm_ioremap_resource(&pdev->dev, res); -+ return devm_platform_get_and_ioremap_resource(pdev, index, NULL); - } - #endif /* CONFIG_HAS_IOMEM */ - #endif diff --git a/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch b/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch index 02b2947ebf..638da14346 100644 --- a/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch +++ b/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch @@ -2,7 +2,7 @@ Used for AP+STA support in OpenWrt - preserve AP mode keys across STA reconnects --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c -@@ -1314,7 +1314,6 @@ static int ieee80211_stop_ap(struct wiph +@@ -1316,7 +1316,6 @@ static int ieee80211_stop_ap(struct wiph sdata->vif.bss_conf.ftmr_params = NULL; __sta_info_flush(sdata, true); diff --git a/package/kernel/mac80211/patches/subsys/210-ap_scan.patch b/package/kernel/mac80211/patches/subsys/210-ap_scan.patch index 5d1823e5c6..0c06829ce4 100644 --- a/package/kernel/mac80211/patches/subsys/210-ap_scan.patch +++ b/package/kernel/mac80211/patches/subsys/210-ap_scan.patch @@ -1,6 +1,6 @@ --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c -@@ -2495,7 +2495,7 @@ static int ieee80211_scan(struct wiphy * +@@ -2497,7 +2497,7 @@ static int ieee80211_scan(struct wiphy * * the frames sent while scanning on other channel will be * lost) */ diff --git a/package/kernel/mac80211/patches/subsys/300-mac80211-drop-check-for-DONT_REORDER-in-__ieee80211_.patch b/package/kernel/mac80211/patches/subsys/300-mac80211-drop-check-for-DONT_REORDER-in-__ieee80211_.patch deleted file mode 100644 index b55da2b1aa..0000000000 --- a/package/kernel/mac80211/patches/subsys/300-mac80211-drop-check-for-DONT_REORDER-in-__ieee80211_.patch +++ /dev/null @@ -1,37 +0,0 @@ -From: Felix Fietkau -Date: Wed, 10 Nov 2021 22:17:13 +0100 -Subject: [PATCH] mac80211: drop check for DONT_REORDER in - __ieee80211_select_queue - -When __ieee80211_select_queue is called, skb->cb has not been cleared yet, -which means that info->control.flags can contain garbage. -In some cases this leads to IEEE80211_TX_CTRL_DONT_REORDER being set, causing -packets marked for other queues to randomly end up in BE instead. - -This flag only needs to be checked in ieee80211_select_queue_80211, since -the radiotap parser is the only piece of code that sets it - -Fixes: 66d06c84730c ("mac80211: adhere to Tx control flag that prevents frame reordering") -Cc: stable@vger.kernel.org -Signed-off-by: Felix Fietkau ---- - ---- a/net/mac80211/wme.c -+++ b/net/mac80211/wme.c -@@ -143,7 +143,6 @@ u16 ieee80211_select_queue_80211(struct - u16 __ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, - struct sta_info *sta, struct sk_buff *skb) - { -- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); - struct mac80211_qos_map *qos_map; - bool qos; - -@@ -156,7 +155,7 @@ u16 __ieee80211_select_queue(struct ieee - else - qos = false; - -- if (!qos || (info->control.flags & IEEE80211_TX_CTRL_DONT_REORDER)) { -+ if (!qos) { - skb->priority = 0; /* required for correct WPA/11i MIC */ - return IEEE80211_AC_BE; - } diff --git a/package/kernel/mac80211/patches/subsys/301-mac80211-fix-rate-control-for-retransmitted-frames.patch b/package/kernel/mac80211/patches/subsys/301-mac80211-fix-rate-control-for-retransmitted-frames.patch index 42f7d6bfe7..98dfe88cbd 100644 --- a/package/kernel/mac80211/patches/subsys/301-mac80211-fix-rate-control-for-retransmitted-frames.patch +++ b/package/kernel/mac80211/patches/subsys/301-mac80211-fix-rate-control-for-retransmitted-frames.patch @@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c -@@ -1825,15 +1825,15 @@ static int invoke_tx_handlers_late(struc +@@ -1821,15 +1821,15 @@ static int invoke_tx_handlers_late(struc struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb); ieee80211_tx_result res = TX_CONTINUE; diff --git a/package/kernel/mac80211/patches/subsys/306-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch b/package/kernel/mac80211/patches/subsys/306-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch index 68fa8a91c2..1ceb2be25c 100644 --- a/package/kernel/mac80211/patches/subsys/306-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch +++ b/package/kernel/mac80211/patches/subsys/306-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch @@ -52,7 +52,7 @@ Signed-off-by: Xing Song --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c -@@ -2947,6 +2947,7 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 +@@ -2948,6 +2948,7 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 if (!fwd_skb) goto out; diff --git a/package/kernel/mac80211/patches/subsys/307-mac80211-do-not-access-the-IV-when-it-was-stripped.patch b/package/kernel/mac80211/patches/subsys/307-mac80211-do-not-access-the-IV-when-it-was-stripped.patch deleted file mode 100644 index 7b662acdc5..0000000000 --- a/package/kernel/mac80211/patches/subsys/307-mac80211-do-not-access-the-IV-when-it-was-stripped.patch +++ /dev/null @@ -1,26 +0,0 @@ -From: Xing Song -Date: Mon, 1 Nov 2021 10:46:57 +0800 -Subject: [PATCH] mac80211: do not access the IV when it was stripped - -ieee80211_get_keyid() will return false value if IV has been stripped, -such as return 0 for IP/ARP frames due to LLC header, and return -EINVAL -for disassociation frames due to its length... etc. Don't try to access -it if it's not present. - -Signed-off-by: Xing Song -Link: https://lore.kernel.org/r/20211101024657.143026-1-xing.song@mediatek.com -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/rx.c -+++ b/net/mac80211/rx.c -@@ -1952,7 +1952,8 @@ ieee80211_rx_h_decrypt(struct ieee80211_ - int keyid = rx->sta->ptk_idx; - sta_ptk = rcu_dereference(rx->sta->ptk[keyid]); - -- if (ieee80211_has_protected(fc)) { -+ if (ieee80211_has_protected(fc) && -+ !(status->flag & RX_FLAG_IV_STRIPPED)) { - cs = rx->sta->cipher_scheme; - keyid = ieee80211_get_keyid(rx->skb, cs); - diff --git a/package/kernel/mac80211/patches/subsys/308-mac80211-fix-radiotap-header-generation.patch b/package/kernel/mac80211/patches/subsys/308-mac80211-fix-radiotap-header-generation.patch deleted file mode 100644 index a408c3d802..0000000000 --- a/package/kernel/mac80211/patches/subsys/308-mac80211-fix-radiotap-header-generation.patch +++ /dev/null @@ -1,49 +0,0 @@ -From: Johannes Berg -Date: Tue, 9 Nov 2021 10:02:04 +0100 -Subject: [PATCH] mac80211: fix radiotap header generation - -In commit 8c89f7b3d3f2 ("mac80211: Use flex-array for radiotap header -bitmap") we accidentally pointed the position to the wrong place, so -we overwrite a present bitmap, and thus cause all kinds of trouble. - -To see the issue, note that the previous code read: - - pos = (void *)(it_present + 1); - -The requirement now is that we need to calculate pos via it_optional, -to not trigger the compiler hardening checks, as: - - pos = (void *)&rthdr->it_optional[...]; - -Rewriting the original expression, we get (obviously, since that just -adds "+ x - x" terms): - - pos = (void *)(it_present + 1 + rthdr->it_optional - rthdr->it_optional) - -and moving the "+ rthdr->it_optional" outside to be used as an array: - - pos = (void *)&rthdr->it_optional[it_present + 1 - rthdr->it_optional]; - -The original is off by one, fix it. - -Cc: stable@vger.kernel.org -Fixes: 8c89f7b3d3f2 ("mac80211: Use flex-array for radiotap header bitmap") -Reported-by: Sid Hayn -Signed-off-by: Johannes Berg -Tested-by: Sid Hayn -Reviewed-by: Kees Cook -Link: https://lore.kernel.org/r/20211109100203.c61007433ed6.I1dade57aba7de9c4f48d68249adbae62636fd98c@changeid -Signed-off-by: Johannes Berg ---- - ---- a/net/mac80211/rx.c -+++ b/net/mac80211/rx.c -@@ -364,7 +364,7 @@ ieee80211_add_rx_radiotap_header(struct - * the compiler to think we have walked past the end of the - * struct member. - */ -- pos = (void *)&rthdr->it_optional[it_present - rthdr->it_optional]; -+ pos = (void *)&rthdr->it_optional[it_present + 1 - rthdr->it_optional]; - - /* the order of the following fields is important */ - diff --git a/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch b/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch index b9fd8e3ea2..3df4062ec5 100644 --- a/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch +++ b/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch @@ -5,7 +5,7 @@ and we should ignore this. --- a/net/wireless/core.c +++ b/net/wireless/core.c -@@ -629,21 +629,6 @@ static int wiphy_verify_combinations(str +@@ -630,21 +630,6 @@ static int wiphy_verify_combinations(str c->limits[j].max > 1)) return -EINVAL; diff --git a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch index 821032fa89..e0a259cde5 100644 --- a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch +++ b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch @@ -57,7 +57,7 @@ __NL80211_ATTR_AFTER_LAST, --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c -@@ -2760,6 +2760,19 @@ static int ieee80211_get_tx_power(struct +@@ -2764,6 +2764,19 @@ static int ieee80211_get_tx_power(struct return 0; } @@ -77,7 +77,7 @@ static void ieee80211_rfkill_poll(struct wiphy *wiphy) { struct ieee80211_local *local = wiphy_priv(wiphy); -@@ -4395,6 +4408,7 @@ const struct cfg80211_ops mac80211_confi +@@ -4399,6 +4412,7 @@ const struct cfg80211_ops mac80211_confi .set_wiphy_params = ieee80211_set_wiphy_params, .set_tx_power = ieee80211_set_tx_power, .get_tx_power = ieee80211_get_tx_power, @@ -137,7 +137,7 @@ }; /* policy for the key attributes */ -@@ -3324,6 +3325,22 @@ static int nl80211_set_wiphy(struct sk_b +@@ -3328,6 +3329,22 @@ static int nl80211_set_wiphy(struct sk_b if (result) goto out; } diff --git a/package/libs/libnl-tiny/Makefile b/package/libs/libnl-tiny/Makefile index bdb496c48e..317d24b4d3 100644 --- a/package/libs/libnl-tiny/Makefile +++ b/package/libs/libnl-tiny/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=libnl-tiny -PKG_RELEASE:=2 +PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/libnl-tiny.git -PKG_SOURCE_DATE:=2020-08-05 -PKG_SOURCE_VERSION:=c291088f631d1694f7ba0444b59677b194348da8 -PKG_MIRROR_HASH:=99bcce12701bb34dadb39689d95c2c5cf1e27719d0ecfd645d3957a8947025ac +PKG_SOURCE_DATE:=2021-11-21 +PKG_SOURCE_VERSION:=8e0555fb39f51a5d6436b4f1370850caa03611ea +PKG_MIRROR_HASH:=2cfbcc62384535674a2c0157cb24a0736520fcb66ed50be23bf9141c8488885f CMAKE_INSTALL:=1 PKG_LICENSE:=LGPL-2.1 diff --git a/package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch b/package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch new file mode 100644 index 0000000000..feb3b091c1 --- /dev/null +++ b/package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch @@ -0,0 +1,92 @@ +--- a/src/ap/hostapd.h ++++ b/src/ap/hostapd.h +@@ -441,6 +441,21 @@ struct hostapd_sta_info { + }; + + /** ++ * struct hostapd_openwrt_stats - OpenWrt custom STA/AP statistics ++ */ ++struct hostapd_openwrt_stats { ++ struct { ++ u64 neighbor_report_tx; ++ } rrm; ++ ++ struct { ++ u64 bss_transition_query_rx; ++ u64 bss_transition_request_tx; ++ u64 bss_transition_response_rx; ++ } wnm; ++}; ++ ++/** + * struct hostapd_iface - hostapd per-interface data structure + */ + struct hostapd_iface { +@@ -562,6 +577,9 @@ struct hostapd_iface { + u64 last_channel_time_busy; + u8 channel_utilization; + ++ /* OpenWrt specific statistics */ ++ struct hostapd_openwrt_stats openwrt_stats; ++ + unsigned int chan_util_samples_sum; + unsigned int chan_util_num_sample_periods; + unsigned int chan_util_average; +--- a/src/ap/wnm_ap.c ++++ b/src/ap/wnm_ap.c +@@ -386,6 +386,7 @@ static int ieee802_11_send_bss_trans_mgm + mgmt->u.action.u.bss_tm_req.validity_interval = 1; + pos = mgmt->u.action.u.bss_tm_req.variable; + ++ hapd->iface->openwrt_stats.wnm.bss_transition_request_tx++; + wpa_printf(MSG_DEBUG, "WNM: Send BSS Transition Management Request to " + MACSTR " dialog_token=%u req_mode=0x%x disassoc_timer=%u " + "validity_interval=%u", +@@ -646,10 +647,12 @@ int ieee802_11_rx_wnm_action_ap(struct h + + switch (action) { + case WNM_BSS_TRANS_MGMT_QUERY: ++ hapd->iface->openwrt_stats.wnm.bss_transition_query_rx++; + ieee802_11_rx_bss_trans_mgmt_query(hapd, mgmt->sa, payload, + plen); + return 0; + case WNM_BSS_TRANS_MGMT_RESP: ++ hapd->iface->openwrt_stats.wnm.bss_transition_response_rx++; + ieee802_11_rx_bss_trans_mgmt_resp(hapd, mgmt->sa, payload, + plen); + return 0; +@@ -696,6 +699,7 @@ int wnm_send_disassoc_imminent(struct ho + + pos = mgmt->u.action.u.bss_tm_req.variable; + ++ hapd->iface->openwrt_stats.wnm.bss_transition_request_tx++; + wpa_printf(MSG_DEBUG, "WNM: Send BSS Transition Management Request frame to indicate imminent disassociation (disassoc_timer=%d) to " + MACSTR, disassoc_timer, MAC2STR(sta->addr)); + if (hostapd_drv_send_mlme(hapd, buf, pos - buf, 0, NULL, 0, 0) < 0) { +@@ -777,6 +781,7 @@ int wnm_send_ess_disassoc_imminent(struc + return -1; + } + ++ hapd->iface->openwrt_stats.wnm.bss_transition_request_tx++; + if (disassoc_timer) { + /* send disassociation frame after time-out */ + set_disassoc_timer(hapd, sta, disassoc_timer); +@@ -856,6 +861,7 @@ int wnm_send_bss_tm_req(struct hostapd_d + } + os_free(buf); + ++ hapd->iface->openwrt_stats.wnm.bss_transition_request_tx++; + if (disassoc_timer) { + /* send disassociation frame after time-out */ + set_disassoc_timer(hapd, sta, disassoc_timer); +--- a/src/ap/rrm.c ++++ b/src/ap/rrm.c +@@ -269,6 +269,8 @@ static void hostapd_send_nei_report_resp + } + } + ++ hapd->iface->openwrt_stats.rrm.neighbor_report_tx++; ++ + hostapd_drv_send_action(hapd, hapd->iface->freq, 0, addr, + wpabuf_head(buf), wpabuf_len(buf)); + wpabuf_free(buf); diff --git a/package/network/services/hostapd/src/src/ap/ubus.c b/package/network/services/hostapd/src/src/ap/ubus.c index e0d3d2ae90..db38ed2941 100644 --- a/package/network/services/hostapd/src/src/ap/ubus.c +++ b/package/network/services/hostapd/src/src/ap/ubus.c @@ -406,7 +406,7 @@ hostapd_bss_get_status(struct ubus_context *ctx, struct ubus_object *obj, struct blob_attr *msg) { struct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj); - void *airtime_table, *dfs_table; + void *airtime_table, *dfs_table, *rrm_table, *wnm_table; struct os_reltime now; char ssid[SSID_MAX_LEN + 1]; char phy_name[17]; @@ -430,6 +430,18 @@ hostapd_bss_get_status(struct ubus_context *ctx, struct ubus_object *obj, snprintf(phy_name, 17, "%s", hapd->iface->phy); blobmsg_add_string(&b, "phy", phy_name); + /* RRM */ + rrm_table = blobmsg_open_table(&b, "rrm"); + blobmsg_add_u64(&b, "neighbor_report_tx", hapd->iface->openwrt_stats.rrm.neighbor_report_tx); + blobmsg_close_table(&b, rrm_table); + + /* WNM */ + wnm_table = blobmsg_open_table(&b, "wnm"); + blobmsg_add_u64(&b, "bss_transition_query_rx", hapd->iface->openwrt_stats.wnm.bss_transition_query_rx); + blobmsg_add_u64(&b, "bss_transition_request_tx", hapd->iface->openwrt_stats.wnm.bss_transition_request_tx); + blobmsg_add_u64(&b, "bss_transition_response_rx", hapd->iface->openwrt_stats.wnm.bss_transition_response_rx); + blobmsg_close_table(&b, wnm_table); + /* Airtime */ airtime_table = blobmsg_open_table(&b, "airtime"); blobmsg_add_u64(&b, "time", hapd->iface->last_channel_time); diff --git a/package/network/utils/iw/Makefile b/package/network/utils/iw/Makefile index 8e11046189..da2b556416 100644 --- a/package/network/utils/iw/Makefile +++ b/package/network/utils/iw/Makefile @@ -8,13 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=iw -PKG_VERSION:=5.9-8fab0c9e -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/linux/kernel/git/jberg/iw.git -PKG_SOURCE_VERSION:=8fab0c9ee9db217587a58efcc37421c86edcb638 -PKG_MIRROR_HASH:=797b322bc03952f3127ae0a7da476c14ada1bbe9a9ae234a56dd6f864c568e16 +PKG_VERSION:=5.16 +PKG_RELEASE:=1 + +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz +PKG_SOURCE_URL:=@KERNEL/software/network/iw +PKG_HASH:=4c44e42762f903f9094ba5a598998c800a97a62afd6fd31ec1e0a799e308659c PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=GPL-2.0 diff --git a/package/network/utils/iw/patches/001-nl80211_h_sync.patch b/package/network/utils/iw/patches/001-nl80211_h_sync.patch index f788e6915f..6d81dd0da1 100644 --- a/package/network/utils/iw/patches/001-nl80211_h_sync.patch +++ b/package/network/utils/iw/patches/001-nl80211_h_sync.patch @@ -1,375 +1,203 @@ --- a/nl80211.h +++ b/nl80211.h -@@ -11,7 +11,7 @@ - * Copyright 2008 Jouni Malinen - * Copyright 2008 Colin McCabe - * Copyright 2015-2017 Intel Deutschland GmbH -- * Copyright (C) 2018-2020 Intel Corporation -+ * Copyright (C) 2018-2021 Intel Corporation +@@ -301,29 +301,6 @@ + */ + + /** +- * DOC: FILS shared key crypto offload +- * +- * This feature is applicable to drivers running in AP mode. +- * +- * FILS shared key crypto offload can be advertised by drivers by setting +- * @NL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD flag. The drivers that support +- * FILS shared key crypto offload should be able to encrypt and decrypt +- * association frames for FILS shared key authentication as per IEEE 802.11ai. +- * With this capability, for FILS key derivation, drivers depend on userspace. +- * +- * After FILS key derivation, userspace shares the FILS AAD details with the +- * driver and the driver stores the same to use in decryption of association +- * request and in encryption of association response. The below parameters +- * should be given to the driver in %NL80211_CMD_SET_FILS_AAD. +- * %NL80211_ATTR_MAC - STA MAC address, used for storing FILS AAD per STA +- * %NL80211_ATTR_FILS_KEK - Used for encryption or decryption +- * %NL80211_ATTR_FILS_NONCES - Used for encryption or decryption +- * (STA Nonce 16 bytes followed by AP Nonce 16 bytes) +- * +- * Once the association is done, the driver cleans the FILS AAD data. +- */ +- +-/** + * enum nl80211_commands - supported nl80211 commands * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above -@@ -655,6 +655,9 @@ - * When a security association was established on an 802.1X network using - * fast transition, this event should be followed by an - * %NL80211_CMD_PORT_AUTHORIZED event. -+ * Following a %NL80211_CMD_ROAM event userspace can issue -+ * %NL80211_CMD_GET_SCAN in order to obtain the scan information for the -+ * new BSS the card/driver roamed to. - * @NL80211_CMD_DISCONNECT: drop a given connection; also used to notify - * userspace that a connection was dropped by the AP or due to other - * reasons, for this the %NL80211_ATTR_DISCONNECTED_BY_AP and -@@ -757,7 +760,8 @@ - * of any other interfaces, and other interfaces will again take - * precedence when they are used. + * @NL80211_CMD_UNSPEC: unspecified command to catch errors +@@ -360,10 +337,7 @@ + * @NL80211_CMD_DEL_INTERFACE: Virtual interface was deleted, has attributes + * %NL80211_ATTR_IFINDEX and %NL80211_ATTR_WIPHY. Can also be sent from + * userspace to request deletion of a virtual interface, then requires +- * attribute %NL80211_ATTR_IFINDEX. If multiple BSSID advertisements are +- * enabled using %NL80211_ATTR_MBSSID_CONFIG, %NL80211_ATTR_MBSSID_ELEMS, +- * and if this command is used for the transmitting interface, then all +- * the non-transmitting interfaces are deleted as well. ++ * attribute %NL80211_ATTR_IFINDEX. * -- * @NL80211_CMD_SET_WDS_PEER: Set the MAC address of the peer on a WDS interface. -+ * @NL80211_CMD_SET_WDS_PEER: Set the MAC address of the peer on a WDS interface -+ * (no longer supported). + * @NL80211_CMD_GET_KEY: Get sequence counter information for a key specified + * by %NL80211_ATTR_KEY_IDX and/or %NL80211_ATTR_MAC. +@@ -1226,12 +1200,6 @@ + * @NL80211_CMD_COLOR_CHANGE_COMPLETED: Notify userland that the color change + * has completed * - * @NL80211_CMD_SET_MULTICAST_TO_UNICAST: Configure if this AP should perform - * multicast to unicast conversion. When enabled, all multicast packets -@@ -1177,6 +1181,25 @@ - * includes the contents of the frame. %NL80211_ATTR_ACK flag is included - * if the recipient acknowledged the frame. - * -+ * @NL80211_CMD_SET_SAR_SPECS: SAR power limitation configuration is -+ * passed using %NL80211_ATTR_SAR_SPEC. %NL80211_ATTR_WIPHY is used to -+ * specify the wiphy index to be applied to. -+ * -+ * @NL80211_CMD_OBSS_COLOR_COLLISION: This notification is sent out whenever -+ * mac80211/drv detects a bss color collision. -+ * -+ * @NL80211_CMD_COLOR_CHANGE_REQUEST: This command is used to indicate that -+ * userspace wants to change the BSS color. -+ * -+ * @NL80211_CMD_COLOR_CHANGE_STARTED: Notify userland, that a color change has -+ * started -+ * -+ * @NL80211_CMD_COLOR_CHANGE_ABORTED: Notify userland, that the color change has -+ * been aborted -+ * -+ * @NL80211_CMD_COLOR_CHANGE_COMPLETED: Notify userland that the color change -+ * has completed -+ * +- * @NL80211_CMD_SET_FILS_AAD: Set FILS AAD data to the driver using - +- * &NL80211_ATTR_MAC - for STA MAC address +- * &NL80211_ATTR_FILS_KEK - for KEK +- * &NL80211_ATTR_FILS_NONCES - for FILS Nonces +- * (STA Nonce 16 bytes followed by AP Nonce 16 bytes) +- * * @NL80211_CMD_MAX: highest used command number * @__NL80211_CMD_AFTER_LAST: internal use */ -@@ -1407,6 +1430,16 @@ enum nl80211_commands { +@@ -1472,8 +1440,6 @@ enum nl80211_commands { + NL80211_CMD_COLOR_CHANGE_ABORTED, + NL80211_CMD_COLOR_CHANGE_COMPLETED, - NL80211_CMD_CONTROL_PORT_FRAME_TX_STATUS, - -+ NL80211_CMD_SET_SAR_SPECS, -+ -+ NL80211_CMD_OBSS_COLOR_COLLISION, -+ -+ NL80211_CMD_COLOR_CHANGE_REQUEST, -+ -+ NL80211_CMD_COLOR_CHANGE_STARTED, -+ NL80211_CMD_COLOR_CHANGE_ABORTED, -+ NL80211_CMD_COLOR_CHANGE_COMPLETED, -+ +- NL80211_CMD_SET_FILS_AAD, +- /* add new commands above here */ /* used to define NL80211_CMD_MAX below */ -@@ -1750,8 +1783,9 @@ enum nl80211_commands { - * specify just a single bitrate, which is to be used for the beacon. - * The driver must also specify support for this with the extended - * features NL80211_EXT_FEATURE_BEACON_RATE_LEGACY, -- * NL80211_EXT_FEATURE_BEACON_RATE_HT and -- * NL80211_EXT_FEATURE_BEACON_RATE_VHT. -+ * NL80211_EXT_FEATURE_BEACON_RATE_HT, -+ * NL80211_EXT_FEATURE_BEACON_RATE_VHT and -+ * NL80211_EXT_FEATURE_BEACON_RATE_HE. +@@ -2627,17 +2593,8 @@ enum nl80211_commands { + * @NL80211_ATTR_COLOR_CHANGE_ELEMS: Nested set of attributes containing the IE + * information for the time while performing a color switch. * - * @NL80211_ATTR_FRAME_MATCH: A binary attribute which typically must contain - * at least one byte, currently used with @NL80211_CMD_REGISTER_FRAME. -@@ -1955,8 +1989,15 @@ enum nl80211_commands { - * @NL80211_ATTR_PROBE_RESP: Probe Response template data. Contains the entire - * probe-response frame. The DA field in the 802.11 header is zero-ed out, - * to be filled by the FW. -- * @NL80211_ATTR_DISABLE_HT: Force HT capable interfaces to disable -- * this feature. Currently, only supported in mac80211 drivers. -+ * @NL80211_ATTR_DISABLE_HT: Force HT capable interfaces to disable -+ * this feature during association. This is a flag attribute. -+ * Currently only supported in mac80211 drivers. -+ * @NL80211_ATTR_DISABLE_VHT: Force VHT capable interfaces to disable -+ * this feature during association. This is a flag attribute. -+ * Currently only supported in mac80211 drivers. -+ * @NL80211_ATTR_DISABLE_HE: Force HE capable interfaces to disable -+ * this feature during association. This is a flag attribute. -+ * Currently only supported in mac80211 drivers. - * @NL80211_ATTR_HT_CAPABILITY_MASK: Specify which bits of the - * ATTR_HT_CAPABILITY to which attention should be paid. - * Currently, only mac80211 NICs support this feature. -@@ -2077,7 +2118,8 @@ enum nl80211_commands { - * until the channel switch event. - * @NL80211_ATTR_CH_SWITCH_BLOCK_TX: flag attribute specifying that transmission - * must be blocked on the current channel (before the channel switch -- * operation). -+ * operation). Also included in the channel switch started event if quiet -+ * was requested by the AP. - * @NL80211_ATTR_CSA_IES: Nested set of attributes containing the IE information - * for the time while performing a channel switch. - * @NL80211_ATTR_CNTDWN_OFFS_BEACON: An array of offsets (u16) to the channel -@@ -2527,6 +2569,33 @@ enum nl80211_commands { - * override mask. Used with NL80211_ATTR_S1G_CAPABILITY in - * NL80211_CMD_ASSOCIATE or NL80211_CMD_CONNECT. - * -+ * @NL80211_ATTR_SAE_PWE: Indicates the mechanism(s) allowed for SAE PWE -+ * derivation in WPA3-Personal networks which are using SAE authentication. -+ * This is a u8 attribute that encapsulates one of the values from -+ * &enum nl80211_sae_pwe_mechanism. -+ * -+ * @NL80211_ATTR_SAR_SPEC: SAR power limitation specification when -+ * used with %NL80211_CMD_SET_SAR_SPECS. The message contains fields -+ * of %nl80211_sar_attrs which specifies the sar type and related -+ * sar specs. Sar specs contains array of %nl80211_sar_specs_attrs. -+ * -+ * @NL80211_ATTR_RECONNECT_REQUESTED: flag attribute, used with deauth and -+ * disassoc events to indicate that an immediate reconnect to the AP -+ * is desired. -+ * -+ * @NL80211_ATTR_OBSS_COLOR_BITMAP: bitmap of the u64 BSS colors for the -+ * %NL80211_CMD_OBSS_COLOR_COLLISION event. -+ * -+ * @NL80211_ATTR_COLOR_CHANGE_COUNT: u8 attribute specifying the number of TBTT's -+ * until the color switch event. -+ * @NL80211_ATTR_COLOR_CHANGE_COLOR: u8 attribute specifying the color that we are -+ * switching to -+ * @NL80211_ATTR_COLOR_CHANGE_ELEMS: Nested set of attributes containing the IE -+ * information for the time while performing a color switch. -+ * +- * @NL80211_ATTR_MBSSID_CONFIG: Nested attribute for multiple BSSID +- * advertisements (MBSSID) parameters in AP mode. +- * Kernel uses this attribute to indicate the driver's support for MBSSID +- * and enhanced multi-BSSID advertisements (EMA AP) to the userspace. +- * Userspace should use this attribute to configure per interface MBSSID +- * parameters. +- * See &enum nl80211_mbssid_config_attributes for details. +- * +- * @NL80211_ATTR_MBSSID_ELEMS: Nested parameter to pass multiple BSSID elements. +- * Mandatory parameter for the transmitting interface to enable MBSSID. +- * Optional for the non-transmitting interfaces. + * @NL80211_ATTR_WIPHY_ANTENNA_GAIN: Configured antenna gain. Used to reduce + * transmit power to stay within regulatory limits. u32, dBi. -+ * + * * @NUM_NL80211_ATTR: total number of nl80211_attrs available * @NL80211_ATTR_MAX: highest attribute number currently defined - * @__NL80211_ATTR_AFTER_LAST: internal use -@@ -3016,6 +3085,22 @@ enum nl80211_attrs { - NL80211_ATTR_S1G_CAPABILITY, - NL80211_ATTR_S1G_CAPABILITY_MASK, +@@ -3142,8 +3099,7 @@ enum nl80211_attrs { + NL80211_ATTR_COLOR_CHANGE_COLOR, + NL80211_ATTR_COLOR_CHANGE_ELEMS, -+ NL80211_ATTR_SAE_PWE, -+ -+ NL80211_ATTR_RECONNECT_REQUESTED, -+ -+ NL80211_ATTR_SAR_SPEC, -+ -+ NL80211_ATTR_DISABLE_HE, -+ -+ NL80211_ATTR_OBSS_COLOR_BITMAP, -+ -+ NL80211_ATTR_COLOR_CHANGE_COUNT, -+ NL80211_ATTR_COLOR_CHANGE_COLOR, -+ NL80211_ATTR_COLOR_CHANGE_ELEMS, -+ +- NL80211_ATTR_MBSSID_CONFIG, +- NL80211_ATTR_MBSSID_ELEMS, + NL80211_ATTR_WIPHY_ANTENNA_GAIN, -+ + /* add attributes here, update the policy in nl80211.c */ - __NL80211_ATTR_AFTER_LAST, -@@ -3613,6 +3698,8 @@ enum nl80211_mpath_info { - * defined - * @NL80211_BAND_IFTYPE_ATTR_HE_6GHZ_CAPA: HE 6GHz band capabilities (__le16), - * given for all 6 GHz band channels -+ * @NL80211_BAND_IFTYPE_ATTR_VENDOR_ELEMS: vendor element capabilities that are -+ * advertised on this band/for this iftype (binary) - * @__NL80211_BAND_IFTYPE_ATTR_AFTER_LAST: internal use +@@ -4978,7 +4934,6 @@ enum nl80211_txrate_gi { + * @NL80211_BAND_60GHZ: around 60 GHz band (58.32 - 69.12 GHz) + * @NL80211_BAND_6GHZ: around 6 GHz band (5.9 - 7.2 GHz) + * @NL80211_BAND_S1GHZ: around 900MHz, supported by S1G PHYs +- * @NL80211_BAND_LC: light communication band (placeholder) + * @NUM_NL80211_BANDS: number of bands, avoid using this in userspace + * since newer kernel versions may support more bands */ - enum nl80211_band_iftype_attr { -@@ -3624,6 +3711,7 @@ enum nl80211_band_iftype_attr { - NL80211_BAND_IFTYPE_ATTR_HE_CAP_MCS_SET, - NL80211_BAND_IFTYPE_ATTR_HE_CAP_PPE, - NL80211_BAND_IFTYPE_ATTR_HE_6GHZ_CAPA, -+ NL80211_BAND_IFTYPE_ATTR_VENDOR_ELEMS, +@@ -4988,7 +4943,6 @@ enum nl80211_band { + NL80211_BAND_60GHZ, + NL80211_BAND_6GHZ, + NL80211_BAND_S1GHZ, +- NL80211_BAND_LC, - /* keep last */ - __NL80211_BAND_IFTYPE_ATTR_AFTER_LAST, -@@ -5896,6 +5984,22 @@ enum nl80211_feature_flags { - * @NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP: Driver/device supports - * unsolicited broadcast probe response transmission + NUM_NL80211_BANDS, + }; +@@ -6046,11 +6000,6 @@ enum nl80211_feature_flags { + * @NL80211_EXT_FEATURE_BSS_COLOR: The driver supports BSS color collision + * detection and change announcemnts. * -+ * @NL80211_EXT_FEATURE_BEACON_RATE_HE: Driver supports beacon rate -+ * configuration (AP/mesh) with HE rates. -+ * -+ * @NL80211_EXT_FEATURE_SECURE_LTF: Device supports secure LTF measurement -+ * exchange protocol. -+ * -+ * @NL80211_EXT_FEATURE_SECURE_RTT: Device supports secure RTT measurement -+ * exchange protocol. -+ * -+ * @NL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE: Device supports management -+ * frame protection for all management frames exchanged during the -+ * negotiation and range measurement procedure. -+ * -+ * @NL80211_EXT_FEATURE_BSS_COLOR: The driver supports BSS color collision -+ * detection and change announcemnts. -+ * +- * @NL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD: Driver running in AP mode supports +- * FILS encryption and decryption for (Re)Association Request and Response +- * frames. Userspace has to share FILS AAD details to the driver by using +- * @NL80211_CMD_SET_FILS_AAD. +- * * @NUM_NL80211_EXT_FEATURES: number of extended features. * @MAX_NL80211_EXT_FEATURES: highest extended feature index. */ -@@ -5956,6 +6060,11 @@ enum nl80211_ext_feature_index { - NL80211_EXT_FEATURE_SAE_OFFLOAD_AP, - NL80211_EXT_FEATURE_FILS_DISCOVERY, - NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP, -+ NL80211_EXT_FEATURE_BEACON_RATE_HE, -+ NL80211_EXT_FEATURE_SECURE_LTF, -+ NL80211_EXT_FEATURE_SECURE_RTT, -+ NL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE, -+ NL80211_EXT_FEATURE_BSS_COLOR, +@@ -6116,7 +6065,6 @@ enum nl80211_ext_feature_index { + NL80211_EXT_FEATURE_SECURE_RTT, + NL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE, + NL80211_EXT_FEATURE_BSS_COLOR, +- NL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD, /* add new features before the definition below */ NUM_NL80211_EXT_FEATURES, -@@ -6253,11 +6362,13 @@ struct nl80211_vendor_cmd_info { - * @NL80211_TDLS_PEER_HT: TDLS peer is HT capable. - * @NL80211_TDLS_PEER_VHT: TDLS peer is VHT capable. - * @NL80211_TDLS_PEER_WMM: TDLS peer is WMM capable. -+ * @NL80211_TDLS_PEER_HE: TDLS peer is HE capable. - */ - enum nl80211_tdls_peer_capability { - NL80211_TDLS_PEER_HT = 1<<0, - NL80211_TDLS_PEER_VHT = 1<<1, - NL80211_TDLS_PEER_WMM = 1<<2, -+ NL80211_TDLS_PEER_HE = 1<<3, +@@ -7406,60 +7354,4 @@ enum nl80211_sar_specs_attrs { + NL80211_SAR_ATTR_SPECS_MAX = __NL80211_SAR_ATTR_SPECS_LAST - 1, }; - /** -@@ -6849,6 +6960,12 @@ enum nl80211_peer_measurement_ftm_capa { - * if neither %NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED nor - * %NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED is set, EDCA based - * ranging will be used. -+ * @NL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK: negotiate for LMR feedback. Only -+ * valid if either %NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED or -+ * %NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED is set. -+ * @NL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR: optional. The BSS color of the -+ * responder. Only valid if %NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED -+ * or %NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED is set. - * - * @NUM_NL80211_PMSR_FTM_REQ_ATTR: internal - * @NL80211_PMSR_FTM_REQ_ATTR_MAX: highest attribute number -@@ -6867,6 +6984,8 @@ enum nl80211_peer_measurement_ftm_req { - NL80211_PMSR_FTM_REQ_ATTR_REQUEST_CIVICLOC, - NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED, - NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED, -+ NL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK, -+ NL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR, - - /* keep last */ - NUM_NL80211_PMSR_FTM_REQ_ATTR, -@@ -7124,4 +7243,115 @@ enum nl80211_unsol_bcast_probe_resp_attr - NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_MAX = - __NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_LAST - 1 - }; -+ -+/** -+ * enum nl80211_sae_pwe_mechanism - The mechanism(s) allowed for SAE PWE -+ * derivation. Applicable only when WPA3-Personal SAE authentication is -+ * used. -+ * -+ * @NL80211_SAE_PWE_UNSPECIFIED: not specified, used internally to indicate that -+ * attribute is not present from userspace. -+ * @NL80211_SAE_PWE_HUNT_AND_PECK: hunting-and-pecking loop only -+ * @NL80211_SAE_PWE_HASH_TO_ELEMENT: hash-to-element only -+ * @NL80211_SAE_PWE_BOTH: both hunting-and-pecking loop and hash-to-element -+ * can be used. -+ */ -+enum nl80211_sae_pwe_mechanism { -+ NL80211_SAE_PWE_UNSPECIFIED, -+ NL80211_SAE_PWE_HUNT_AND_PECK, -+ NL80211_SAE_PWE_HASH_TO_ELEMENT, -+ NL80211_SAE_PWE_BOTH, -+}; -+ -+/** -+ * enum nl80211_sar_type - type of SAR specs -+ * -+ * @NL80211_SAR_TYPE_POWER: power limitation specified in 0.25dBm unit -+ * -+ */ -+enum nl80211_sar_type { -+ NL80211_SAR_TYPE_POWER, -+ -+ /* add new type here */ -+ -+ /* Keep last */ -+ NUM_NL80211_SAR_TYPE, -+}; -+ -+/** -+ * enum nl80211_sar_attrs - Attributes for SAR spec -+ * -+ * @NL80211_SAR_ATTR_TYPE: the SAR type as defined in &enum nl80211_sar_type. -+ * -+ * @NL80211_SAR_ATTR_SPECS: Nested array of SAR power -+ * limit specifications. Each specification contains a set -+ * of %nl80211_sar_specs_attrs. -+ * -+ * For SET operation, it contains array of %NL80211_SAR_ATTR_SPECS_POWER -+ * and %NL80211_SAR_ATTR_SPECS_RANGE_INDEX. -+ * -+ * For sar_capa dump, it contains array of -+ * %NL80211_SAR_ATTR_SPECS_START_FREQ -+ * and %NL80211_SAR_ATTR_SPECS_END_FREQ. -+ * -+ * @__NL80211_SAR_ATTR_LAST: Internal -+ * @NL80211_SAR_ATTR_MAX: highest sar attribute -+ * -+ * These attributes are used with %NL80211_CMD_SET_SAR_SPEC -+ */ -+enum nl80211_sar_attrs { -+ __NL80211_SAR_ATTR_INVALID, -+ -+ NL80211_SAR_ATTR_TYPE, -+ NL80211_SAR_ATTR_SPECS, -+ -+ __NL80211_SAR_ATTR_LAST, -+ NL80211_SAR_ATTR_MAX = __NL80211_SAR_ATTR_LAST - 1, -+}; -+ -+/** -+ * enum nl80211_sar_specs_attrs - Attributes for SAR power limit specs -+ * -+ * @NL80211_SAR_ATTR_SPECS_POWER: Required (s32)value to specify the actual -+ * power limit value in units of 0.25 dBm if type is -+ * NL80211_SAR_TYPE_POWER. (i.e., a value of 44 represents 11 dBm). -+ * 0 means userspace doesn't have SAR limitation on this associated range. -+ * -+ * @NL80211_SAR_ATTR_SPECS_RANGE_INDEX: Required (u32) value to specify the -+ * index of exported freq range table and the associated power limitation -+ * is applied to this range. -+ * -+ * Userspace isn't required to set all the ranges advertised by WLAN driver, -+ * and userspace can skip some certain ranges. These skipped ranges don't -+ * have SAR limitations, and they are same as setting the -+ * %NL80211_SAR_ATTR_SPECS_POWER to any unreasonable high value because any -+ * value higher than regulatory allowed value just means SAR power -+ * limitation is removed, but it's required to set at least one range. -+ * It's not allowed to set duplicated range in one SET operation. -+ * -+ * Every SET operation overwrites previous SET operation. -+ * -+ * @NL80211_SAR_ATTR_SPECS_START_FREQ: Required (u32) value to specify the start -+ * frequency of this range edge when registering SAR capability to wiphy. -+ * It's not a channel center frequency. The unit is kHz. -+ * -+ * @NL80211_SAR_ATTR_SPECS_END_FREQ: Required (u32) value to specify the end -+ * frequency of this range edge when registering SAR capability to wiphy. -+ * It's not a channel center frequency. The unit is kHz. -+ * -+ * @__NL80211_SAR_ATTR_SPECS_LAST: Internal -+ * @NL80211_SAR_ATTR_SPECS_MAX: highest sar specs attribute -+ */ -+enum nl80211_sar_specs_attrs { -+ __NL80211_SAR_ATTR_SPECS_INVALID, -+ -+ NL80211_SAR_ATTR_SPECS_POWER, -+ NL80211_SAR_ATTR_SPECS_RANGE_INDEX, -+ NL80211_SAR_ATTR_SPECS_START_FREQ, -+ NL80211_SAR_ATTR_SPECS_END_FREQ, -+ -+ __NL80211_SAR_ATTR_SPECS_LAST, -+ NL80211_SAR_ATTR_SPECS_MAX = __NL80211_SAR_ATTR_SPECS_LAST - 1, -+}; -+ +-/** +- * enum nl80211_mbssid_config_attributes - multiple BSSID (MBSSID) and enhanced +- * multi-BSSID advertisements (EMA) in AP mode. +- * Kernel uses some of these attributes to advertise driver's support for +- * MBSSID and EMA. +- * Remaining attributes should be used by the userspace to configure the +- * features. +- * +- * @__NL80211_MBSSID_CONFIG_ATTR_INVALID: Invalid +- * +- * @NL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES: Used by the kernel to advertise +- * the maximum number of MBSSID interfaces supported by the driver. +- * Driver should indicate MBSSID support by setting +- * wiphy->mbssid_max_interfaces to a value more than or equal to 2. +- * +- * @NL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY: Used by the kernel +- * to advertise the maximum profile periodicity supported by the driver +- * if EMA is enabled. Driver should indicate EMA support to the userspace +- * by setting wiphy->ema_max_profile_periodicity to +- * a non-zero value. +- * +- * @NL80211_MBSSID_CONFIG_ATTR_INDEX: Mandatory parameter to pass the index of +- * this BSS (u8) in the multiple BSSID set. +- * Value must be set to 0 for the transmitting interface and non-zero for +- * all non-transmitting interfaces. The userspace will be responsible +- * for using unique indices for the interfaces. +- * Range: 0 to wiphy->mbssid_max_interfaces-1. +- * +- * @NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX: Mandatory parameter for +- * a non-transmitted profile which provides the interface index (u32) of +- * the transmitted profile. The value must match one of the interface +- * indices advertised by the kernel. Optional if the interface being set up +- * is the transmitting one, however, if provided then the value must match +- * the interface index of the same. +- * +- * @NL80211_MBSSID_CONFIG_ATTR_EMA: Flag used to enable EMA AP feature. +- * Setting this flag is permitted only if the driver advertises EMA support +- * by setting wiphy->ema_max_profile_periodicity to non-zero. +- * +- * @__NL80211_MBSSID_CONFIG_ATTR_LAST: Internal +- * @NL80211_MBSSID_CONFIG_ATTR_MAX: highest attribute +- */ +-enum nl80211_mbssid_config_attributes { +- __NL80211_MBSSID_CONFIG_ATTR_INVALID, +- +- NL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES, +- NL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY, +- NL80211_MBSSID_CONFIG_ATTR_INDEX, +- NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX, +- NL80211_MBSSID_CONFIG_ATTR_EMA, +- +- /* keep last */ +- __NL80211_MBSSID_CONFIG_ATTR_LAST, +- NL80211_MBSSID_CONFIG_ATTR_MAX = __NL80211_MBSSID_CONFIG_ATTR_LAST - 1, +-}; +- #endif /* __LINUX_NL80211_H */ +--- a/info.c ++++ b/info.c +@@ -701,7 +701,6 @@ broken_combination: + ext_feat_print(tb, OPERATING_CHANNEL_VALIDATION, "Operating Channel Validation (OCV) support"); + ext_feat_print(tb, 4WAY_HANDSHAKE_AP_PSK, "AP mode PSK offload support"); + ext_feat_print(tb, BSS_COLOR, "BSS coloring support"); +- ext_feat_print(tb, FILS_CRYPTO_OFFLOAD, "FILS crypto offload"); + } + + if (tb_msg[NL80211_ATTR_COALESCE_RULE]) { diff --git a/package/network/utils/iw/patches/010-Revert-iw-allow-specifying-CFLAGS-LIBS-externally.patch b/package/network/utils/iw/patches/010-Revert-iw-allow-specifying-CFLAGS-LIBS-externally.patch new file mode 100644 index 0000000000..1254efa9c7 --- /dev/null +++ b/package/network/utils/iw/patches/010-Revert-iw-allow-specifying-CFLAGS-LIBS-externally.patch @@ -0,0 +1,68 @@ +From 1f3706d10812d70adefe32fe0d7d3a3ec25374f0 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 21 Nov 2021 00:02:57 +0100 +Subject: Revert "iw: allow specifying CFLAGS/LIBS externally" + +This reverts commit 1325244b77d56fd7a16d1e35fdae0efc151920b1. + +The OpenWrt build system provides the CFLAGS and LIBS names from the +package Makefile to overwrite them for libnl-tiny. This is not possible +after this upstream change which we revert here any more + +Signed-off-by: Hauke Mehrtens +--- + Makefile | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +--- a/Makefile ++++ b/Makefile +@@ -45,30 +45,30 @@ NLLIBNAME = libnl-1 + endif + + ifeq ($(NL2FOUND),Y) +-override CFLAGS += -DCONFIG_LIBNL20 +-override LIBS += -lnl-genl ++CFLAGS += -DCONFIG_LIBNL20 ++LIBS += -lnl-genl + NLLIBNAME = libnl-2.0 + endif + + ifeq ($(NL3xFOUND),Y) + # libnl 3.2 might be found as 3.2 and 3.0 + NL3FOUND = N +-override CFLAGS += -DCONFIG_LIBNL30 +-override LIBS += -lnl-genl-3 ++CFLAGS += -DCONFIG_LIBNL30 ++LIBS += -lnl-genl-3 + NLLIBNAME = libnl-3.0 + endif + + ifeq ($(NL3FOUND),Y) +-override CFLAGS += -DCONFIG_LIBNL30 +-override LIBS += -lnl-genl ++CFLAGS += -DCONFIG_LIBNL30 ++LIBS += -lnl-genl + NLLIBNAME = libnl-3.0 + endif + + # nl-3.1 has a broken libnl-gnl-3.1.pc file + # as show by pkg-config --debug --libs --cflags --exact-version=3.1 libnl-genl-3.1;echo $? + ifeq ($(NL31FOUND),Y) +-override CFLAGS += -DCONFIG_LIBNL30 +-override LIBS += -lnl-genl ++CFLAGS += -DCONFIG_LIBNL30 ++LIBS += -lnl-genl + NLLIBNAME = libnl-3.1 + endif + +@@ -76,8 +76,8 @@ ifeq ($(NLLIBNAME),) + $(error Cannot find development files for any supported version of libnl) + endif + +-override LIBS += $(shell $(PKG_CONFIG) --libs $(NLLIBNAME)) +-override CFLAGS += $(shell $(PKG_CONFIG) --cflags $(NLLIBNAME)) ++LIBS += $(shell $(PKG_CONFIG) --libs $(NLLIBNAME)) ++CFLAGS += $(shell $(PKG_CONFIG) --cflags $(NLLIBNAME)) + endif # NO_PKG_CONFIG + + ifeq ($(V),1) diff --git a/package/network/utils/iw/patches/200-reduce_size.patch b/package/network/utils/iw/patches/200-reduce_size.patch index c50a4a4d38..d0e837c695 100644 --- a/package/network/utils/iw/patches/200-reduce_size.patch +++ b/package/network/utils/iw/patches/200-reduce_size.patch @@ -38,7 +38,7 @@ --- a/info.c +++ b/info.c -@@ -216,6 +216,7 @@ next: +@@ -215,6 +215,7 @@ next: } } @@ -46,7 +46,7 @@ if (tb_band[NL80211_BAND_ATTR_RATES]) { printf("\t\tBitrates (non-HT):\n"); nla_for_each_nested(nl_rate, tb_band[NL80211_BAND_ATTR_RATES], rem_rate) { -@@ -232,6 +233,7 @@ next: +@@ -231,6 +232,7 @@ next: printf("\n"); } } @@ -54,7 +54,7 @@ } } -@@ -297,6 +299,7 @@ next: +@@ -296,6 +298,7 @@ next: printf("\tCoverage class: %d (up to %dm)\n", coverage, 450 * coverage); } @@ -62,7 +62,7 @@ if (tb_msg[NL80211_ATTR_CIPHER_SUITES]) { int num = nla_len(tb_msg[NL80211_ATTR_CIPHER_SUITES]) / sizeof(__u32); int i; -@@ -308,6 +311,7 @@ next: +@@ -307,6 +310,7 @@ next: cipher_name(ciphers[i])); } } @@ -70,21 +70,19 @@ if (tb_msg[NL80211_ATTR_WIPHY_ANTENNA_AVAIL_TX] && tb_msg[NL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX]) -@@ -327,11 +331,13 @@ next: - printf("\t\t * %s\n", iftype_name(nla_type(nl_mode))); - } +@@ -324,9 +328,11 @@ next: + print_iftype_list("\tSupported interface modes", "\t\t", + tb_msg[NL80211_ATTR_SUPPORTED_IFTYPES]); +#ifdef IW_FULL - if (tb_msg[NL80211_ATTR_SOFTWARE_IFTYPES]) { - printf("\tsoftware interface modes (can always be added):\n"); - nla_for_each_nested(nl_mode, tb_msg[NL80211_ATTR_SOFTWARE_IFTYPES], rem_mode) - printf("\t\t * %s\n", iftype_name(nla_type(nl_mode))); - } + if (tb_msg[NL80211_ATTR_SOFTWARE_IFTYPES]) + print_iftype_list("\tsoftware interface modes (can always be added)", + "\t\t", tb_msg[NL80211_ATTR_SOFTWARE_IFTYPES]); +#endif if (tb_msg[NL80211_ATTR_INTERFACE_COMBINATIONS]) { struct nlattr *nl_combi; -@@ -428,6 +434,7 @@ broken_combination: +@@ -416,6 +422,7 @@ broken_combination: printf("\tinterface combinations are not supported\n"); } @@ -92,7 +90,7 @@ if (tb_msg[NL80211_ATTR_SUPPORTED_COMMANDS]) { printf("\tSupported commands:\n"); nla_for_each_nested(nl_cmd, tb_msg[NL80211_ATTR_SUPPORTED_COMMANDS], rem_cmd) -@@ -525,6 +532,7 @@ broken_combination: +@@ -513,6 +520,7 @@ broken_combination: printf("\t\t * wake up on TCP connection\n"); } } @@ -100,7 +98,7 @@ if (tb_msg[NL80211_ATTR_ROAM_SUPPORT]) printf("\tDevice supports roaming.\n"); -@@ -563,6 +571,7 @@ broken_combination: +@@ -551,6 +559,7 @@ broken_combination: } } @@ -108,7 +106,7 @@ if (tb_msg[NL80211_ATTR_FEATURE_FLAGS]) { unsigned int features = nla_get_u32(tb_msg[NL80211_ATTR_FEATURE_FLAGS]); -@@ -627,6 +636,7 @@ broken_combination: +@@ -615,6 +624,7 @@ broken_combination: if (features & NL80211_FEATURE_ND_RANDOM_MAC_ADDR) printf("\tDevice supports randomizing MAC-addr in net-detect scans.\n"); } @@ -116,7 +114,7 @@ if (tb_msg[NL80211_ATTR_TDLS_SUPPORT]) printf("\tDevice supports T-DLS.\n"); -@@ -762,6 +772,7 @@ TOPLEVEL(list, NULL, NL80211_CMD_GET_WIP +@@ -751,6 +761,7 @@ TOPLEVEL(list, NULL, NL80211_CMD_GET_WIP "List all wireless devices and their capabilities."); TOPLEVEL(phy, NULL, NL80211_CMD_GET_WIPHY, NLM_F_DUMP, CIB_NONE, handle_info, NULL); @@ -124,7 +122,7 @@ static int handle_commands(struct nl80211_state *state, struct nl_msg *msg, int argc, char **argv, enum id_input id) { -@@ -773,6 +784,7 @@ static int handle_commands(struct nl8021 +@@ -762,6 +773,7 @@ static int handle_commands(struct nl8021 } TOPLEVEL(commands, NULL, NL80211_CMD_GET_WIPHY, 0, CIB_NONE, handle_commands, "list all known commands and their decimal & hex value"); diff --git a/package/network/utils/layerscape/restool/Makefile b/package/network/utils/layerscape/restool/Makefile index 6335f98f9f..bb2eac48cd 100644 --- a/package/network/utils/layerscape/restool/Makefile +++ b/package/network/utils/layerscape/restool/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=restool -PKG_VERSION:=LSDK-20.12 +PKG_VERSION:=LSDK-21.08 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/restool -PKG_SOURCE_VERSION:=LSDK-20.12 -PKG_MIRROR_HASH:=aeba5add9d06c2a3cdac1cc2953d98f00acaa0038dbaf725b468f3e99e5fdd93 +PKG_SOURCE_VERSION:=LSDK-21.08 +PKG_MIRROR_HASH:=d793defa2e4cf907bebe7761d88feb2ac94e0ecdaabdb3bbc9dda83a82046bc5 PKG_FLAGS:=nonshared diff --git a/target/linux/bcm4908/Makefile b/target/linux/bcm4908/Makefile index 59a4c2707f..fcfe04962b 100644 --- a/target/linux/bcm4908/Makefile +++ b/target/linux/bcm4908/Makefile @@ -20,7 +20,7 @@ include $(INCLUDE_DIR)/target.mk KERNELNAME:=Image dtbs DEFAULT_PACKAGES += \ - bcm4908img \ + bcm4908img fdt-utils uboot-envtools \ kmod-gpio-button-hotplug \ kmod-usb-ohci kmod-usb2 kmod-usb3 diff --git a/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh index 512dad1891..c92dcd1e4e 100644 --- a/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh @@ -143,7 +143,9 @@ platform_other_check_image() { echo "Found $BCM53XX_FW_FORMAT firmware for device $BCM53XX_FW_BOARD_ID" local expected_image="$(platform_expected_image)" - [ -n "$expected_image" -a -n "$BCM53XX_FW_BOARD_ID" -a "$expected_image" != "$BCM53XX_FW_FORMAT $BCM53XX_FW_BOARD_ID" ] && { + local tmp_format=$BCM53XX_FW_FORMAT + [ "$tmp_format" = "lxlold" ] && tmp_format="lxl" + [ -n "$expected_image" -a -n "$BCM53XX_FW_BOARD_ID" -a "$expected_image" != "$tmp_format $BCM53XX_FW_BOARD_ID" ] && { echo "Firmware doesn't match device ($expected_image)" error=1 } diff --git a/target/linux/generic/backport-5.4/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch b/target/linux/generic/backport-5.4/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch new file mode 100644 index 0000000000..961140aabb --- /dev/null +++ b/target/linux/generic/backport-5.4/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch @@ -0,0 +1,88 @@ +From: Felix Fietkau +Date: Mon, 8 Feb 2021 11:34:08 -0800 +Subject: [PATCH] net: extract napi poll functionality to __napi_poll() + +This commit introduces a new function __napi_poll() which does the main +logic of the existing napi_poll() function, and will be called by other +functions in later commits. +This idea and implementation is done by Felix Fietkau and +is proposed as part of the patch to move napi work to work_queue +context. +This commit by itself is a code restructure. + +Signed-off-by: Felix Fietkau +Signed-off-by: Wei Wang +Reviewed-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -6322,15 +6322,10 @@ void netif_napi_del(struct napi_struct * + } + EXPORT_SYMBOL(netif_napi_del); + +-static int napi_poll(struct napi_struct *n, struct list_head *repoll) ++static int __napi_poll(struct napi_struct *n, bool *repoll) + { +- void *have; + int work, weight; + +- list_del_init(&n->poll_list); +- +- have = netpoll_poll_lock(n); +- + weight = n->weight; + + /* This NAPI_STATE_SCHED test is for avoiding a race +@@ -6348,7 +6343,7 @@ static int napi_poll(struct napi_struct + WARN_ON_ONCE(work > weight); + + if (likely(work < weight)) +- goto out_unlock; ++ return work; + + /* Drivers must not modify the NAPI state if they + * consume the entire weight. In such cases this code +@@ -6357,7 +6352,7 @@ static int napi_poll(struct napi_struct + */ + if (unlikely(napi_disable_pending(n))) { + napi_complete(n); +- goto out_unlock; ++ return work; + } + + if (n->gro_bitmask) { +@@ -6375,12 +6370,29 @@ static int napi_poll(struct napi_struct + if (unlikely(!list_empty(&n->poll_list))) { + pr_warn_once("%s: Budget exhausted after napi rescheduled\n", + n->dev ? n->dev->name : "backlog"); +- goto out_unlock; ++ return work; + } + +- list_add_tail(&n->poll_list, repoll); ++ *repoll = true; ++ ++ return work; ++} ++ ++static int napi_poll(struct napi_struct *n, struct list_head *repoll) ++{ ++ bool do_repoll = false; ++ void *have; ++ int work; ++ ++ list_del_init(&n->poll_list); ++ ++ have = netpoll_poll_lock(n); ++ ++ work = __napi_poll(n, &do_repoll); ++ ++ if (do_repoll) ++ list_add_tail(&n->poll_list, repoll); + +-out_unlock: + netpoll_poll_unlock(have); + + return work; diff --git a/target/linux/generic/backport-5.4/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch b/target/linux/generic/backport-5.4/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch new file mode 100644 index 0000000000..c9bd4abb53 --- /dev/null +++ b/target/linux/generic/backport-5.4/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch @@ -0,0 +1,261 @@ +From: Wei Wang +Date: Mon, 8 Feb 2021 11:34:09 -0800 +Subject: [PATCH] net: implement threaded-able napi poll loop support + +This patch allows running each napi poll loop inside its own +kernel thread. +The kthread is created during netif_napi_add() if dev->threaded +is set. And threaded mode is enabled in napi_enable(). We will +provide a way to set dev->threaded and enable threaded mode +without a device up/down in the following patch. + +Once that threaded mode is enabled and the kthread is +started, napi_schedule() will wake-up such thread instead +of scheduling the softirq. + +The threaded poll loop behaves quite likely the net_rx_action, +but it does not have to manipulate local irqs and uses +an explicit scheduling point based on netdev_budget. + +Co-developed-by: Paolo Abeni +Signed-off-by: Paolo Abeni +Co-developed-by: Hannes Frederic Sowa +Signed-off-by: Hannes Frederic Sowa +Co-developed-by: Jakub Kicinski +Signed-off-by: Jakub Kicinski +Signed-off-by: Wei Wang +Reviewed-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -340,6 +340,7 @@ struct napi_struct { + struct list_head dev_list; + struct hlist_node napi_hash_node; + unsigned int napi_id; ++ struct task_struct *thread; + }; + + enum { +@@ -350,6 +351,7 @@ enum { + NAPI_STATE_HASHED, /* In NAPI hash (busy polling possible) */ + NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */ + NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */ ++ NAPI_STATE_THREADED, /* The poll is performed inside its own thread*/ + }; + + enum { +@@ -360,6 +362,7 @@ enum { + NAPIF_STATE_HASHED = BIT(NAPI_STATE_HASHED), + NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL), + NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL), ++ NAPIF_STATE_THREADED = BIT(NAPI_STATE_THREADED), + }; + + enum gro_result { +@@ -504,20 +507,7 @@ bool napi_hash_del(struct napi_struct *n + */ + void napi_disable(struct napi_struct *n); + +-/** +- * napi_enable - enable NAPI scheduling +- * @n: NAPI context +- * +- * Resume NAPI from being scheduled on this context. +- * Must be paired with napi_disable. +- */ +-static inline void napi_enable(struct napi_struct *n) +-{ +- BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); +- smp_mb__before_atomic(); +- clear_bit(NAPI_STATE_SCHED, &n->state); +- clear_bit(NAPI_STATE_NPSVC, &n->state); +-} ++void napi_enable(struct napi_struct *n); + + /** + * napi_synchronize - wait until NAPI is not running +@@ -1783,6 +1773,8 @@ enum netdev_ml_priv_type { + * + * @wol_enabled: Wake-on-LAN is enabled + * ++ * @threaded: napi threaded mode is enabled ++ * + * FIXME: cleanup struct net_device such that network protocol info + * moves out. + */ +@@ -2075,6 +2067,7 @@ struct net_device { + struct lock_class_key addr_list_lock_key; + bool proto_down; + unsigned wol_enabled:1; ++ unsigned threaded:1; + }; + #define to_net_dev(d) container_of(d, struct net_device, dev) + +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -91,6 +91,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1289,6 +1290,27 @@ void netdev_notify_peers(struct net_devi + } + EXPORT_SYMBOL(netdev_notify_peers); + ++static int napi_threaded_poll(void *data); ++ ++static int napi_kthread_create(struct napi_struct *n) ++{ ++ int err = 0; ++ ++ /* Create and wake up the kthread once to put it in ++ * TASK_INTERRUPTIBLE mode to avoid the blocked task ++ * warning and work with loadavg. ++ */ ++ n->thread = kthread_run(napi_threaded_poll, n, "napi/%s-%d", ++ n->dev->name, n->napi_id); ++ if (IS_ERR(n->thread)) { ++ err = PTR_ERR(n->thread); ++ pr_err("kthread_run failed with err %d\n", err); ++ n->thread = NULL; ++ } ++ ++ return err; ++} ++ + static int __dev_open(struct net_device *dev, struct netlink_ext_ack *extack) + { + const struct net_device_ops *ops = dev->netdev_ops; +@@ -3885,6 +3907,21 @@ int gro_normal_batch __read_mostly = 8; + static inline void ____napi_schedule(struct softnet_data *sd, + struct napi_struct *napi) + { ++ struct task_struct *thread; ++ ++ if (test_bit(NAPI_STATE_THREADED, &napi->state)) { ++ /* Paired with smp_mb__before_atomic() in ++ * napi_enable(). Use READ_ONCE() to guarantee ++ * a complete read on napi->thread. Only call ++ * wake_up_process() when it's not NULL. ++ */ ++ thread = READ_ONCE(napi->thread); ++ if (thread) { ++ wake_up_process(thread); ++ return; ++ } ++ } ++ + list_add_tail(&napi->poll_list, &sd->poll_list); + __raise_softirq_irqoff(NET_RX_SOFTIRQ); + } +@@ -6276,6 +6313,12 @@ void netif_napi_add(struct net_device *d + set_bit(NAPI_STATE_NPSVC, &napi->state); + list_add_rcu(&napi->dev_list, &dev->napi_list); + napi_hash_add(napi); ++ /* Create kthread for this napi if dev->threaded is set. ++ * Clear dev->threaded if kthread creation failed so that ++ * threaded mode will not be enabled in napi_enable(). ++ */ ++ if (dev->threaded && napi_kthread_create(napi)) ++ dev->threaded = 0; + } + EXPORT_SYMBOL(netif_napi_add); + +@@ -6292,9 +6335,28 @@ void napi_disable(struct napi_struct *n) + hrtimer_cancel(&n->timer); + + clear_bit(NAPI_STATE_DISABLE, &n->state); ++ clear_bit(NAPI_STATE_THREADED, &n->state); + } + EXPORT_SYMBOL(napi_disable); + ++/** ++ * napi_enable - enable NAPI scheduling ++ * @n: NAPI context ++ * ++ * Resume NAPI from being scheduled on this context. ++ * Must be paired with napi_disable. ++ */ ++void napi_enable(struct napi_struct *n) ++{ ++ BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); ++ smp_mb__before_atomic(); ++ clear_bit(NAPI_STATE_SCHED, &n->state); ++ clear_bit(NAPI_STATE_NPSVC, &n->state); ++ if (n->dev->threaded && n->thread) ++ set_bit(NAPI_STATE_THREADED, &n->state); ++} ++EXPORT_SYMBOL(napi_enable); ++ + static void flush_gro_hash(struct napi_struct *napi) + { + int i; +@@ -6319,6 +6381,11 @@ void netif_napi_del(struct napi_struct * + + flush_gro_hash(napi); + napi->gro_bitmask = 0; ++ ++ if (napi->thread) { ++ kthread_stop(napi->thread); ++ napi->thread = NULL; ++ } + } + EXPORT_SYMBOL(netif_napi_del); + +@@ -6398,6 +6465,51 @@ static int napi_poll(struct napi_struct + return work; + } + ++static int napi_thread_wait(struct napi_struct *napi) ++{ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ while (!kthread_should_stop() && !napi_disable_pending(napi)) { ++ if (test_bit(NAPI_STATE_SCHED, &napi->state)) { ++ WARN_ON(!list_empty(&napi->poll_list)); ++ __set_current_state(TASK_RUNNING); ++ return 0; ++ } ++ ++ schedule(); ++ set_current_state(TASK_INTERRUPTIBLE); ++ } ++ __set_current_state(TASK_RUNNING); ++ return -1; ++} ++ ++static int napi_threaded_poll(void *data) ++{ ++ struct napi_struct *napi = data; ++ void *have; ++ ++ while (!napi_thread_wait(napi)) { ++ for (;;) { ++ bool repoll = false; ++ ++ local_bh_disable(); ++ ++ have = netpoll_poll_lock(napi); ++ __napi_poll(napi, &repoll); ++ netpoll_poll_unlock(have); ++ ++ __kfree_skb_flush(); ++ local_bh_enable(); ++ ++ if (!repoll) ++ break; ++ ++ cond_resched(); ++ } ++ } ++ return 0; ++} ++ + static __latent_entropy void net_rx_action(struct softirq_action *h) + { + struct softnet_data *sd = this_cpu_ptr(&softnet_data); diff --git a/target/linux/generic/backport-5.4/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch b/target/linux/generic/backport-5.4/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch new file mode 100644 index 0000000000..d8b932978c --- /dev/null +++ b/target/linux/generic/backport-5.4/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch @@ -0,0 +1,177 @@ +From: Wei Wang +Date: Mon, 8 Feb 2021 11:34:10 -0800 +Subject: [PATCH] net: add sysfs attribute to control napi threaded mode + +This patch adds a new sysfs attribute to the network device class. +Said attribute provides a per-device control to enable/disable the +threaded mode for all the napi instances of the given network device, +without the need for a device up/down. +User sets it to 1 or 0 to enable or disable threaded mode. +Note: when switching between threaded and the current softirq based mode +for a napi instance, it will not immediately take effect if the napi is +currently being polled. The mode switch will happen for the next time +napi_schedule() is called. + +Co-developed-by: Paolo Abeni +Signed-off-by: Paolo Abeni +Co-developed-by: Hannes Frederic Sowa +Signed-off-by: Hannes Frederic Sowa +Co-developed-by: Felix Fietkau +Signed-off-by: Felix Fietkau +Signed-off-by: Wei Wang +Reviewed-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/Documentation/ABI/testing/sysfs-class-net ++++ b/Documentation/ABI/testing/sysfs-class-net +@@ -301,3 +301,18 @@ Contact: netdev@vger.kernel.org + Description: + 32-bit unsigned integer counting the number of times the link has + been down ++ ++What: /sys/class/net//threaded ++Date: Jan 2021 ++KernelVersion: 5.12 ++Contact: netdev@vger.kernel.org ++Description: ++ Boolean value to control the threaded mode per device. User could ++ set this value to enable/disable threaded mode for all napi ++ belonging to this device, without the need to do device up/down. ++ ++ Possible values: ++ == ================================== ++ 0 threaded mode disabled for this dev ++ 1 threaded mode enabled for this dev ++ == ================================== +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -498,6 +498,8 @@ static inline bool napi_complete(struct + */ + bool napi_hash_del(struct napi_struct *napi); + ++int dev_set_threaded(struct net_device *dev, bool threaded); ++ + /** + * napi_disable - prevent NAPI from scheduling + * @n: NAPI context +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -3911,8 +3911,9 @@ static inline void ____napi_schedule(str + + if (test_bit(NAPI_STATE_THREADED, &napi->state)) { + /* Paired with smp_mb__before_atomic() in +- * napi_enable(). Use READ_ONCE() to guarantee +- * a complete read on napi->thread. Only call ++ * napi_enable()/dev_set_threaded(). ++ * Use READ_ONCE() to guarantee a complete ++ * read on napi->thread. Only call + * wake_up_process() when it's not NULL. + */ + thread = READ_ONCE(napi->thread); +@@ -6290,6 +6291,49 @@ static void init_gro_hash(struct napi_st + napi->gro_bitmask = 0; + } + ++int dev_set_threaded(struct net_device *dev, bool threaded) ++{ ++ struct napi_struct *napi; ++ int err = 0; ++ ++ if (dev->threaded == threaded) ++ return 0; ++ ++ if (threaded) { ++ list_for_each_entry(napi, &dev->napi_list, dev_list) { ++ if (!napi->thread) { ++ err = napi_kthread_create(napi); ++ if (err) { ++ threaded = false; ++ break; ++ } ++ } ++ } ++ } ++ ++ dev->threaded = threaded; ++ ++ /* Make sure kthread is created before THREADED bit ++ * is set. ++ */ ++ smp_mb__before_atomic(); ++ ++ /* Setting/unsetting threaded mode on a napi might not immediately ++ * take effect, if the current napi instance is actively being ++ * polled. In this case, the switch between threaded mode and ++ * softirq mode will happen in the next round of napi_schedule(). ++ * This should not cause hiccups/stalls to the live traffic. ++ */ ++ list_for_each_entry(napi, &dev->napi_list, dev_list) { ++ if (threaded) ++ set_bit(NAPI_STATE_THREADED, &napi->state); ++ else ++ clear_bit(NAPI_STATE_THREADED, &napi->state); ++ } ++ ++ return err; ++} ++ + void netif_napi_add(struct net_device *dev, struct napi_struct *napi, + int (*poll)(struct napi_struct *, int), int weight) + { +--- a/net/core/net-sysfs.c ++++ b/net/core/net-sysfs.c +@@ -557,6 +557,45 @@ static ssize_t phys_switch_id_show(struc + } + static DEVICE_ATTR_RO(phys_switch_id); + ++static ssize_t threaded_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct net_device *netdev = to_net_dev(dev); ++ ssize_t ret = -EINVAL; ++ ++ if (!rtnl_trylock()) ++ return restart_syscall(); ++ ++ if (dev_isalive(netdev)) ++ ret = sprintf(buf, fmt_dec, netdev->threaded); ++ ++ rtnl_unlock(); ++ return ret; ++} ++ ++static int modify_napi_threaded(struct net_device *dev, unsigned long val) ++{ ++ int ret; ++ ++ if (list_empty(&dev->napi_list)) ++ return -EOPNOTSUPP; ++ ++ if (val != 0 && val != 1) ++ return -EOPNOTSUPP; ++ ++ ret = dev_set_threaded(dev, val); ++ ++ return ret; ++} ++ ++static ssize_t threaded_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t len) ++{ ++ return netdev_store(dev, attr, buf, len, modify_napi_threaded); ++} ++static DEVICE_ATTR_RW(threaded); ++ + static struct attribute *net_class_attrs[] __ro_after_init = { + &dev_attr_netdev_group.attr, + &dev_attr_type.attr, +@@ -587,6 +626,7 @@ static struct attribute *net_class_attrs + &dev_attr_proto_down.attr, + &dev_attr_carrier_up_count.attr, + &dev_attr_carrier_down_count.attr, ++ &dev_attr_threaded.attr, + NULL, + }; + ATTRIBUTE_GROUPS(net_class); diff --git a/target/linux/generic/backport-5.4/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch b/target/linux/generic/backport-5.4/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch new file mode 100644 index 0000000000..19c5a53a27 --- /dev/null +++ b/target/linux/generic/backport-5.4/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch @@ -0,0 +1,93 @@ +From: Wei Wang +Date: Mon, 1 Mar 2021 17:21:13 -0800 +Subject: [PATCH] net: fix race between napi kthread mode and busy poll + +Currently, napi_thread_wait() checks for NAPI_STATE_SCHED bit to +determine if the kthread owns this napi and could call napi->poll() on +it. However, if socket busy poll is enabled, it is possible that the +busy poll thread grabs this SCHED bit (after the previous napi->poll() +invokes napi_complete_done() and clears SCHED bit) and tries to poll +on the same napi. napi_disable() could grab the SCHED bit as well. +This patch tries to fix this race by adding a new bit +NAPI_STATE_SCHED_THREADED in napi->state. This bit gets set in +____napi_schedule() if the threaded mode is enabled, and gets cleared +in napi_complete_done(), and we only poll the napi in kthread if this +bit is set. This helps distinguish the ownership of the napi between +kthread and other scenarios and fixes the race issue. + +Fixes: 29863d41bb6e ("net: implement threaded-able napi poll loop support") +Reported-by: Martin Zaharinov +Suggested-by: Jakub Kicinski +Signed-off-by: Wei Wang +Cc: Alexander Duyck +Cc: Eric Dumazet +Cc: Paolo Abeni +Cc: Hannes Frederic Sowa +--- + +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -352,6 +352,7 @@ enum { + NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */ + NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */ + NAPI_STATE_THREADED, /* The poll is performed inside its own thread*/ ++ NAPI_STATE_SCHED_THREADED, /* Napi is currently scheduled in threaded mode */ + }; + + enum { +@@ -363,6 +364,7 @@ enum { + NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL), + NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL), + NAPIF_STATE_THREADED = BIT(NAPI_STATE_THREADED), ++ NAPIF_STATE_SCHED_THREADED = BIT(NAPI_STATE_SCHED_THREADED), + }; + + enum gro_result { +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -3918,6 +3918,8 @@ static inline void ____napi_schedule(str + */ + thread = READ_ONCE(napi->thread); + if (thread) { ++ if (thread->state != TASK_INTERRUPTIBLE) ++ set_bit(NAPI_STATE_SCHED_THREADED, &napi->state); + wake_up_process(thread); + return; + } +@@ -6078,7 +6080,8 @@ bool napi_complete_done(struct napi_stru + + WARN_ON_ONCE(!(val & NAPIF_STATE_SCHED)); + +- new = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED); ++ new = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED | ++ NAPIF_STATE_SCHED_THREADED); + + /* If STATE_MISSED was set, leave STATE_SCHED set, + * because we will call napi->poll() one more time. +@@ -6511,16 +6514,25 @@ static int napi_poll(struct napi_struct + + static int napi_thread_wait(struct napi_struct *napi) + { ++ bool woken = false; ++ + set_current_state(TASK_INTERRUPTIBLE); + + while (!kthread_should_stop() && !napi_disable_pending(napi)) { +- if (test_bit(NAPI_STATE_SCHED, &napi->state)) { ++ /* Testing SCHED_THREADED bit here to make sure the current ++ * kthread owns this napi and could poll on this napi. ++ * Testing SCHED bit is not enough because SCHED bit might be ++ * set by some other busy poll thread or by napi_disable(). ++ */ ++ if (test_bit(NAPI_STATE_SCHED_THREADED, &napi->state) || woken) { + WARN_ON(!list_empty(&napi->poll_list)); + __set_current_state(TASK_RUNNING); + return 0; + } + + schedule(); ++ /* woken being true indicates this thread owns this napi. */ ++ woken = true; + set_current_state(TASK_INTERRUPTIBLE); + } + __set_current_state(TASK_RUNNING); diff --git a/target/linux/generic/backport-5.4/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch b/target/linux/generic/backport-5.4/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch new file mode 100644 index 0000000000..108cf809f8 --- /dev/null +++ b/target/linux/generic/backport-5.4/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch @@ -0,0 +1,53 @@ +From: Paolo Abeni +Date: Fri, 9 Apr 2021 17:24:17 +0200 +Subject: [PATCH] net: fix hangup on napi_disable for threaded napi + +napi_disable() is subject to an hangup, when the threaded +mode is enabled and the napi is under heavy traffic. + +If the relevant napi has been scheduled and the napi_disable() +kicks in before the next napi_threaded_wait() completes - so +that the latter quits due to the napi_disable_pending() condition, +the existing code leaves the NAPI_STATE_SCHED bit set and the +napi_disable() loop waiting for such bit will hang. + +This patch addresses the issue by dropping the NAPI_STATE_DISABLE +bit test in napi_thread_wait(). The later napi_threaded_poll() +iteration will take care of clearing the NAPI_STATE_SCHED. + +This also addresses a related problem reported by Jakub: +before this patch a napi_disable()/napi_enable() pair killed +the napi thread, effectively disabling the threaded mode. +On the patched kernel napi_disable() simply stops scheduling +the relevant thread. + +v1 -> v2: + - let the main napi_thread_poll() loop clear the SCHED bit + +Reported-by: Jakub Kicinski +Fixes: 29863d41bb6e ("net: implement threaded-able napi poll loop support") +Signed-off-by: Paolo Abeni +Reviewed-by: Eric Dumazet +Link: https://lore.kernel.org/r/883923fa22745a9589e8610962b7dc59df09fb1f.1617981844.git.pabeni@redhat.com +Signed-off-by: Jakub Kicinski +--- + +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -6518,7 +6518,7 @@ static int napi_thread_wait(struct napi_ + + set_current_state(TASK_INTERRUPTIBLE); + +- while (!kthread_should_stop() && !napi_disable_pending(napi)) { ++ while (!kthread_should_stop()) { + /* Testing SCHED_THREADED bit here to make sure the current + * kthread owns this napi and could poll on this napi. + * Testing SCHED bit is not enough because SCHED bit might be +@@ -6536,6 +6536,7 @@ static int napi_thread_wait(struct napi_ + set_current_state(TASK_INTERRUPTIBLE); + } + __set_current_state(TASK_RUNNING); ++ + return -1; + } + diff --git a/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch b/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch index a8181bca94..34ad5a1f4e 100644 --- a/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch +++ b/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch @@ -66,7 +66,7 @@ Signed-off-by: David S. Miller --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -5432,8 +5432,7 @@ static inline void skb_gro_reset_offset( +@@ -5472,8 +5472,7 @@ static inline void skb_gro_reset_offset( NAPI_GRO_CB(skb)->frag0 = NULL; NAPI_GRO_CB(skb)->frag0_len = 0; diff --git a/target/linux/generic/backport-5.4/900-v5.9-0001-dt-bindings-Add-multicolor-class-dt-bindings-documen.patch b/target/linux/generic/backport-5.4/900-v5.9-0001-dt-bindings-Add-multicolor-class-dt-bindings-documen.patch new file mode 100644 index 0000000000..acc32b69fb --- /dev/null +++ b/target/linux/generic/backport-5.4/900-v5.9-0001-dt-bindings-Add-multicolor-class-dt-bindings-documen.patch @@ -0,0 +1,76 @@ +From 5c7f8ffe741daae7f8d811a2037b2693f02c90c5 Mon Sep 17 00:00:00 2001 +From: Dan Murphy +Date: Mon, 13 Jul 2020 10:45:31 -0500 +Subject: [PATCH] dt: bindings: Add multicolor class dt bindings documention +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add DT bindings for the LEDs multicolor class framework. +Add multicolor ID to the color ID list for device tree bindings. + +CC: Rob Herring +Reviewed-by: Rob Herring +Acked-by: Pavel Machek +Acked-by: Jacek Anaszewski +Signed-off-by: Dan Murphy +Reviewed-by: Marek Behún +Signed-off-by: Pavel Machek +--- + .../bindings/leds/leds-class-multicolor.yaml | 37 +++++++++++++++++++ + include/dt-bindings/leds/common.h | 3 +- + 2 files changed, 39 insertions(+), 1 deletion(-) + create mode 100644 Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml +@@ -0,0 +1,37 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/leds/leds-class-multicolor.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Common properties for the multicolor LED class. ++ ++maintainers: ++ - Dan Murphy ++ ++description: | ++ Bindings for multi color LEDs show how to describe current outputs of ++ either integrated multi-color LED elements (like RGB, RGBW, RGBWA-UV ++ etc.) or standalone LEDs, to achieve logically grouped multi-color LED ++ modules. This is achieved by adding multi-led nodes layer to the ++ monochrome LED bindings. ++ The nodes and properties defined in this document are unique to the multicolor ++ LED class. Common LED nodes and properties are inherited from the common.txt ++ within this documentation directory. ++ ++patternProperties: ++ "^multi-led@([0-9a-f])$": ++ type: object ++ description: Represents the LEDs that are to be grouped. ++ properties: ++ color: ++ const: 8 # LED_COLOR_ID_MULTI ++ description: | ++ For multicolor LED support this property should be defined as ++ LED_COLOR_ID_MULTI which can be found in include/linux/leds/common.h. ++ ++ $ref: "common.yaml#" ++ ++ required: ++ - color ++... +--- a/include/dt-bindings/leds/common.h ++++ b/include/dt-bindings/leds/common.h +@@ -29,7 +29,8 @@ + #define LED_COLOR_ID_VIOLET 5 + #define LED_COLOR_ID_YELLOW 6 + #define LED_COLOR_ID_IR 7 +-#define LED_COLOR_ID_MAX 8 ++#define LED_COLOR_ID_MULTI 8 ++#define LED_COLOR_ID_MAX 9 + + /* Standard LED functions */ + #define LED_FUNCTION_ACTIVITY "activity" diff --git a/target/linux/generic/backport-5.4/900-v5.9-0002-leds-Add-multicolor-ID-to-the-color-ID-list.patch b/target/linux/generic/backport-5.4/900-v5.9-0002-leds-Add-multicolor-ID-to-the-color-ID-list.patch new file mode 100644 index 0000000000..5de5dbda04 --- /dev/null +++ b/target/linux/generic/backport-5.4/900-v5.9-0002-leds-Add-multicolor-ID-to-the-color-ID-list.patch @@ -0,0 +1,29 @@ +From 10d3e0d815879129e916cd83e1034438e06efdaa Mon Sep 17 00:00:00 2001 +From: Dan Murphy +Date: Mon, 13 Jul 2020 10:45:32 -0500 +Subject: [PATCH] leds: Add multicolor ID to the color ID list +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add a new color ID that is declared as MULTICOLOR as with the +multicolor framework declaring a definitive color is not accurate +as the node can contain multiple colors. + +Signed-off-by: Dan Murphy +Reviewed-by: Marek Behún +Signed-off-by: Pavel Machek +--- + drivers/leds/led-core.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/leds/led-core.c ++++ b/drivers/leds/led-core.c +@@ -34,6 +34,7 @@ const char * const led_colors[LED_COLOR_ + [LED_COLOR_ID_VIOLET] = "violet", + [LED_COLOR_ID_YELLOW] = "yellow", + [LED_COLOR_ID_IR] = "ir", ++ [LED_COLOR_ID_MULTI] = "multicolor", + }; + EXPORT_SYMBOL_GPL(led_colors); + diff --git a/target/linux/generic/backport-5.4/900-v5.9-0003-leds-add-RGB-color-option-as-that-is-different-from-.patch b/target/linux/generic/backport-5.4/900-v5.9-0003-leds-add-RGB-color-option-as-that-is-different-from-.patch new file mode 100644 index 0000000000..17c28149f6 --- /dev/null +++ b/target/linux/generic/backport-5.4/900-v5.9-0003-leds-add-RGB-color-option-as-that-is-different-from-.patch @@ -0,0 +1,48 @@ +From 54212f5a1ba3123281877e54c1e5f672bf7563d8 Mon Sep 17 00:00:00 2001 +From: Pavel Machek +Date: Mon, 3 Aug 2020 13:20:06 +0200 +Subject: [PATCH] leds: add RGB color option, as that is different from + multicolor. + +Multicolor is a bit too abstract. Yes, we can have +Green-Magenta-Ultraviolet LED, but so far all the LEDs we support are +RGB, and not even RGB-White or RGB-Yellow variants emerged. + +Multicolor is not a good fit for RGB LED. It does not really know +about LED color. In particular, there's no way to make LED "white". + +Userspace is interested in knowing "this LED can produce arbitrary +color", which not all multicolor LEDs can. + +Signed-off-by: Pavel Machek +--- + drivers/leds/led-core.c | 1 + + drivers/leds/leds-lp55xx-common.c | 2 +- + include/dt-bindings/leds/common.h | 6 ++++-- + 3 files changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/leds/led-core.c ++++ b/drivers/leds/led-core.c +@@ -35,6 +35,7 @@ const char * const led_colors[LED_COLOR_ + [LED_COLOR_ID_YELLOW] = "yellow", + [LED_COLOR_ID_IR] = "ir", + [LED_COLOR_ID_MULTI] = "multicolor", ++ [LED_COLOR_ID_RGB] = "rgb", + }; + EXPORT_SYMBOL_GPL(led_colors); + +--- a/include/dt-bindings/leds/common.h ++++ b/include/dt-bindings/leds/common.h +@@ -29,8 +29,10 @@ + #define LED_COLOR_ID_VIOLET 5 + #define LED_COLOR_ID_YELLOW 6 + #define LED_COLOR_ID_IR 7 +-#define LED_COLOR_ID_MULTI 8 +-#define LED_COLOR_ID_MAX 9 ++#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ ++#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color, ++ so this would include RGBW and similar */ ++#define LED_COLOR_ID_MAX 10 + + /* Standard LED functions */ + #define LED_FUNCTION_ACTIVITY "activity" diff --git a/target/linux/generic/hack-5.4/721-phy_packets.patch b/target/linux/generic/hack-5.4/721-phy_packets.patch index 268e9df051..89ff8ea41a 100644 --- a/target/linux/generic/hack-5.4/721-phy_packets.patch +++ b/target/linux/generic/hack-5.4/721-phy_packets.patch @@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -1549,6 +1549,7 @@ enum netdev_priv_flags { +@@ -1540,6 +1540,7 @@ enum netdev_priv_flags { IFF_FAILOVER_SLAVE = 1<<28, IFF_L3MDEV_RX_HANDLER = 1<<29, IFF_LIVE_RENAME_OK = 1<<30, @@ -23,7 +23,7 @@ Signed-off-by: Felix Fietkau }; #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN -@@ -1581,6 +1582,7 @@ enum netdev_priv_flags { +@@ -1572,6 +1573,7 @@ enum netdev_priv_flags { #define IFF_FAILOVER_SLAVE IFF_FAILOVER_SLAVE #define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER #define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK @@ -31,7 +31,7 @@ Signed-off-by: Felix Fietkau /* Specifies the type of the struct net_device::ml_priv pointer */ enum netdev_ml_priv_type { -@@ -1889,6 +1891,11 @@ struct net_device { +@@ -1882,6 +1884,11 @@ struct net_device { const struct tlsdev_ops *tlsdev_ops; #endif @@ -43,7 +43,7 @@ Signed-off-by: Felix Fietkau const struct header_ops *header_ops; unsigned int flags; -@@ -1971,6 +1978,10 @@ struct net_device { +@@ -1964,6 +1971,10 @@ struct net_device { struct mpls_dev __rcu *mpls_ptr; #endif @@ -101,7 +101,7 @@ Signed-off-by: Felix Fietkau help --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -3200,10 +3200,20 @@ static int xmit_one(struct sk_buff *skb, +@@ -3221,10 +3221,20 @@ static int xmit_one(struct sk_buff *skb, if (dev_nit_active(dev)) dev_queue_xmit_nit(skb, dev); diff --git a/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch b/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch index 02600ebed0..f5d9dcde99 100644 --- a/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch +++ b/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch @@ -23,7 +23,7 @@ Signed-off-by: Pablo Neira Ayuso --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -928,6 +928,13 @@ struct devlink; +@@ -922,6 +922,13 @@ struct devlink; struct tlsdev_ops; @@ -37,7 +37,7 @@ Signed-off-by: Pablo Neira Ayuso /* * This structure defines the management hooks for network devices. * The following hooks can be defined; unless noted otherwise, they are -@@ -1160,6 +1167,10 @@ struct tlsdev_ops; +@@ -1154,6 +1161,10 @@ struct tlsdev_ops; * int (*ndo_bridge_dellink)(struct net_device *dev, struct nlmsghdr *nlh, * u16 flags); * @@ -48,7 +48,7 @@ Signed-off-by: Pablo Neira Ayuso * int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier); * Called to change device carrier. Soft-devices (like dummy, team, etc) * which do not represent real hardware may define this to allow their -@@ -1407,6 +1418,8 @@ struct net_device_ops { +@@ -1401,6 +1412,8 @@ struct net_device_ops { int (*ndo_bridge_dellink)(struct net_device *dev, struct nlmsghdr *nlh, u16 flags); diff --git a/target/linux/generic/pending-5.4/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch b/target/linux/generic/pending-5.4/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch index 9f113c7108..b808c0257d 100644 --- a/target/linux/generic/pending-5.4/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch +++ b/target/linux/generic/pending-5.4/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch @@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -929,6 +929,7 @@ struct tlsdev_ops; +@@ -923,6 +923,7 @@ struct tlsdev_ops; struct flow_offload; @@ -23,7 +23,7 @@ Signed-off-by: Felix Fietkau enum flow_offload_type { FLOW_OFFLOAD_ADD = 0, -@@ -1167,8 +1168,15 @@ enum flow_offload_type { +@@ -1161,8 +1162,15 @@ enum flow_offload_type { * int (*ndo_bridge_dellink)(struct net_device *dev, struct nlmsghdr *nlh, * u16 flags); * @@ -40,7 +40,7 @@ Signed-off-by: Felix Fietkau * Adds/deletes flow entry to/from net device flowtable. * * int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier); -@@ -1418,8 +1426,11 @@ struct net_device_ops { +@@ -1412,8 +1420,11 @@ struct net_device_ops { int (*ndo_bridge_dellink)(struct net_device *dev, struct nlmsghdr *nlh, u16 flags); diff --git a/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch index b1ac7ffca0..45f643b650 100644 --- a/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch +++ b/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -1931,6 +1931,8 @@ struct net_device { +@@ -1927,6 +1927,8 @@ struct net_device { struct netdev_hw_addr_list mc; struct netdev_hw_addr_list dev_addrs; @@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau __u16 tc_index; /* traffic control index */ --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -5498,6 +5498,9 @@ static enum gro_result dev_gro_receive(s +@@ -5538,6 +5538,9 @@ static enum gro_result dev_gro_receive(s int same_flow; int grow; @@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau if (netif_elide_gro(skb->dev)) goto normal; -@@ -7300,6 +7303,48 @@ static void __netdev_adjacent_dev_unlink +@@ -7481,6 +7484,48 @@ static void __netdev_adjacent_dev_unlink &upper_dev->adj_list.lower); } @@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau static int __netdev_upper_dev_link(struct net_device *dev, struct net_device *upper_dev, bool master, void *upper_priv, void *upper_info, -@@ -7350,6 +7395,7 @@ static int __netdev_upper_dev_link(struc +@@ -7531,6 +7576,7 @@ static int __netdev_upper_dev_link(struc if (ret) return ret; @@ -99,7 +99,7 @@ Signed-off-by: Felix Fietkau ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, &changeupper_info.info); ret = notifier_to_errno(ret); -@@ -7443,6 +7489,7 @@ void netdev_upper_dev_unlink(struct net_ +@@ -7624,6 +7670,7 @@ void netdev_upper_dev_unlink(struct net_ __netdev_adjacent_dev_unlink_neighbour(dev, upper_dev); @@ -107,7 +107,7 @@ Signed-off-by: Felix Fietkau call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, &changeupper_info.info); -@@ -8173,6 +8220,7 @@ int dev_set_mac_address(struct net_devic +@@ -8354,6 +8401,7 @@ int dev_set_mac_address(struct net_devic if (err) return err; dev->addr_assign_type = NET_ADDR_SET; diff --git a/target/linux/generic/pending-5.4/690-net-add-support-for-threaded-NAPI-polling.patch b/target/linux/generic/pending-5.4/690-net-add-support-for-threaded-NAPI-polling.patch deleted file mode 100644 index 0e97f2140c..0000000000 --- a/target/linux/generic/pending-5.4/690-net-add-support-for-threaded-NAPI-polling.patch +++ /dev/null @@ -1,355 +0,0 @@ -From: Felix Fietkau -Date: Sun, 26 Jul 2020 14:03:21 +0200 -Subject: [PATCH] net: add support for threaded NAPI polling - -For some drivers (especially 802.11 drivers), doing a lot of work in the NAPI -poll function does not perform well. Since NAPI poll is bound to the CPU it -was scheduled from, we can easily end up with a few very busy CPUs spending -most of their time in softirq/ksoftirqd and some idle ones. - -Introduce threaded NAPI for such drivers based on a workqueue. The API is the -same except for using netif_threaded_napi_add instead of netif_napi_add. - -In my tests with mt76 on MT7621 using threaded NAPI + a thread for tx scheduling -improves LAN->WLAN bridging throughput by 10-50%. Throughput without threaded -NAPI is wildly inconsistent, depending on the CPU that runs the tx scheduling -thread. - -With threaded NAPI it seems stable and consistent (and higher than the best -results I got without it). - -Based on a patch by Hillf Danton - -Cc: Hillf Danton -Signed-off-by: Felix Fietkau ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -340,6 +340,7 @@ struct napi_struct { - struct list_head dev_list; - struct hlist_node napi_hash_node; - unsigned int napi_id; -+ struct work_struct work; - }; - - enum { -@@ -350,6 +351,7 @@ enum { - NAPI_STATE_HASHED, /* In NAPI hash (busy polling possible) */ - NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */ - NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */ -+ NAPI_STATE_THREADED, /* Use threaded NAPI */ - }; - - enum { -@@ -360,6 +362,7 @@ enum { - NAPIF_STATE_HASHED = BIT(NAPI_STATE_HASHED), - NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL), - NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL), -+ NAPIF_STATE_THREADED = BIT(NAPI_STATE_THREADED), - }; - - enum gro_result { -@@ -2101,6 +2104,7 @@ struct net_device { - struct lock_class_key addr_list_lock_key; - bool proto_down; - unsigned wol_enabled:1; -+ unsigned threaded:1; - }; - #define to_net_dev(d) container_of(d, struct net_device, dev) - -@@ -2281,6 +2285,26 @@ void netif_napi_add(struct net_device *d - int (*poll)(struct napi_struct *, int), int weight); - - /** -+ * netif_threaded_napi_add - initialize a NAPI context -+ * @dev: network device -+ * @napi: NAPI context -+ * @poll: polling function -+ * @weight: default weight -+ * -+ * This variant of netif_napi_add() should be used from drivers using NAPI -+ * with CPU intensive poll functions. -+ * This will schedule polling from a high priority workqueue -+ */ -+static inline void netif_threaded_napi_add(struct net_device *dev, -+ struct napi_struct *napi, -+ int (*poll)(struct napi_struct *, int), -+ int weight) -+{ -+ set_bit(NAPI_STATE_THREADED, &napi->state); -+ netif_napi_add(dev, napi, poll, weight); -+} -+ -+/** - * netif_tx_napi_add - initialize a NAPI context - * @dev: network device - * @napi: NAPI context ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -156,6 +156,7 @@ static DEFINE_SPINLOCK(offload_lock); - struct list_head ptype_base[PTYPE_HASH_SIZE] __read_mostly; - struct list_head ptype_all __read_mostly; /* Taps */ - static struct list_head offload_base __read_mostly; -+static struct workqueue_struct *napi_workq __read_mostly; - - static int netif_rx_internal(struct sk_buff *skb); - static int call_netdevice_notifiers_info(unsigned long val, -@@ -5940,6 +5941,11 @@ void __napi_schedule(struct napi_struct - { - unsigned long flags; - -+ if (test_bit(NAPI_STATE_THREADED, &n->state)) { -+ queue_work(napi_workq, &n->work); -+ return; -+ } -+ - local_irq_save(flags); - ____napi_schedule(this_cpu_ptr(&softnet_data), n); - local_irq_restore(flags); -@@ -5991,6 +5997,10 @@ EXPORT_SYMBOL(napi_schedule_prep); - */ - void __napi_schedule_irqoff(struct napi_struct *n) - { -+ if (test_bit(NAPI_STATE_THREADED, &n->state)) { -+ queue_work(napi_workq, &n->work); -+ return; -+ } - if (!IS_ENABLED(CONFIG_PREEMPT_RT)) - ____napi_schedule(this_cpu_ptr(&softnet_data), n); - else -@@ -6255,9 +6265,89 @@ static void init_gro_hash(struct napi_st - napi->gro_bitmask = 0; - } - -+static int __napi_poll(struct napi_struct *n, bool *repoll) -+{ -+ int work, weight; -+ -+ weight = n->weight; -+ -+ /* This NAPI_STATE_SCHED test is for avoiding a race -+ * with netpoll's poll_napi(). Only the entity which -+ * obtains the lock and sees NAPI_STATE_SCHED set will -+ * actually make the ->poll() call. Therefore we avoid -+ * accidentally calling ->poll() when NAPI is not scheduled. -+ */ -+ work = 0; -+ if (test_bit(NAPI_STATE_SCHED, &n->state)) { -+ work = n->poll(n, weight); -+ trace_napi_poll(n, work, weight); -+ } -+ -+ WARN_ON_ONCE(work > weight); -+ -+ if (likely(work < weight)) -+ return work; -+ -+ /* Drivers must not modify the NAPI state if they -+ * consume the entire weight. In such cases this code -+ * still "owns" the NAPI instance and therefore can -+ * move the instance around on the list at-will. -+ */ -+ if (unlikely(napi_disable_pending(n))) { -+ napi_complete(n); -+ return work; -+ } -+ -+ if (n->gro_bitmask) { -+ /* flush too old packets -+ * If HZ < 1000, flush all packets. -+ */ -+ napi_gro_flush(n, HZ >= 1000); -+ } -+ -+ gro_normal_list(n); -+ -+ *repoll = true; -+ -+ return work; -+} -+ -+static void napi_workfn(struct work_struct *work) -+{ -+ struct napi_struct *n = container_of(work, struct napi_struct, work); -+ void *have; -+ -+ for (;;) { -+ bool repoll = false; -+ -+ local_bh_disable(); -+ -+ have = netpoll_poll_lock(n); -+ __napi_poll(n, &repoll); -+ netpoll_poll_unlock(have); -+ -+ local_bh_enable(); -+ -+ if (!repoll) -+ return; -+ -+ if (!need_resched()) -+ continue; -+ -+ /* -+ * have to pay for the latency of task switch even if -+ * napi is scheduled -+ */ -+ queue_work(napi_workq, work); -+ return; -+ } -+} -+ - void netif_napi_add(struct net_device *dev, struct napi_struct *napi, - int (*poll)(struct napi_struct *, int), int weight) - { -+ if (dev->threaded) -+ set_bit(NAPI_STATE_THREADED, &napi->state); - INIT_LIST_HEAD(&napi->poll_list); - hrtimer_init(&napi->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); - napi->timer.function = napi_watchdog; -@@ -6274,6 +6364,7 @@ void netif_napi_add(struct net_device *d - #ifdef CONFIG_NETPOLL - napi->poll_owner = -1; - #endif -+ INIT_WORK(&napi->work, napi_workfn); - set_bit(NAPI_STATE_SCHED, &napi->state); - set_bit(NAPI_STATE_NPSVC, &napi->state); - list_add_rcu(&napi->dev_list, &dev->napi_list); -@@ -6314,6 +6405,7 @@ static void flush_gro_hash(struct napi_s - void netif_napi_del(struct napi_struct *napi) - { - might_sleep(); -+ cancel_work_sync(&napi->work); - if (napi_hash_del(napi)) - synchronize_net(); - list_del_init(&napi->dev_list); -@@ -6326,50 +6418,18 @@ EXPORT_SYMBOL(netif_napi_del); - - static int napi_poll(struct napi_struct *n, struct list_head *repoll) - { -+ bool do_repoll = false; - void *have; -- int work, weight; -+ int work; - - list_del_init(&n->poll_list); - - have = netpoll_poll_lock(n); - -- weight = n->weight; -- -- /* This NAPI_STATE_SCHED test is for avoiding a race -- * with netpoll's poll_napi(). Only the entity which -- * obtains the lock and sees NAPI_STATE_SCHED set will -- * actually make the ->poll() call. Therefore we avoid -- * accidentally calling ->poll() when NAPI is not scheduled. -- */ -- work = 0; -- if (test_bit(NAPI_STATE_SCHED, &n->state)) { -- work = n->poll(n, weight); -- trace_napi_poll(n, work, weight); -- } -- -- WARN_ON_ONCE(work > weight); -+ work = __napi_poll(n, &do_repoll); - -- if (likely(work < weight)) -- goto out_unlock; -- -- /* Drivers must not modify the NAPI state if they -- * consume the entire weight. In such cases this code -- * still "owns" the NAPI instance and therefore can -- * move the instance around on the list at-will. -- */ -- if (unlikely(napi_disable_pending(n))) { -- napi_complete(n); -+ if (!do_repoll) - goto out_unlock; -- } -- -- if (n->gro_bitmask) { -- /* flush too old packets -- * If HZ < 1000, flush all packets. -- */ -- napi_gro_flush(n, HZ >= 1000); -- } -- -- gro_normal_list(n); - - /* Some drivers may have called napi_schedule - * prior to exhausting their budget. -@@ -10349,6 +10409,10 @@ static int __init net_dev_init(void) - sd->backlog.weight = weight_p; - } - -+ napi_workq = alloc_workqueue("napi_workq", WQ_UNBOUND | WQ_HIGHPRI, -+ WQ_UNBOUND_MAX_ACTIVE | WQ_SYSFS); -+ BUG_ON(!napi_workq); -+ - dev_boot_phase = 0; - - /* The loopback device is special if any other network devices ---- a/net/core/net-sysfs.c -+++ b/net/core/net-sysfs.c -@@ -470,6 +470,52 @@ static ssize_t proto_down_store(struct d - } - NETDEVICE_SHOW_RW(proto_down, fmt_dec); - -+static int change_napi_threaded(struct net_device *dev, unsigned long val) -+{ -+ struct napi_struct *napi; -+ -+ if (list_empty(&dev->napi_list)) -+ return -EOPNOTSUPP; -+ -+ list_for_each_entry(napi, &dev->napi_list, dev_list) { -+ if (val) -+ set_bit(NAPI_STATE_THREADED, &napi->state); -+ else -+ clear_bit(NAPI_STATE_THREADED, &napi->state); -+ } -+ -+ return 0; -+} -+ -+static ssize_t napi_threaded_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+ return netdev_store(dev, attr, buf, len, change_napi_threaded); -+} -+ -+static ssize_t napi_threaded_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct net_device *netdev = to_net_dev(dev); -+ struct napi_struct *napi; -+ bool enabled = false; -+ -+ if (!rtnl_trylock()) -+ return restart_syscall(); -+ -+ list_for_each_entry(napi, &netdev->napi_list, dev_list) { -+ if (test_bit(NAPI_STATE_THREADED, &napi->state)) -+ enabled = true; -+ } -+ -+ rtnl_unlock(); -+ -+ return sprintf(buf, fmt_dec, enabled); -+} -+static DEVICE_ATTR_RW(napi_threaded); -+ - static ssize_t phys_port_id_show(struct device *dev, - struct device_attribute *attr, char *buf) - { -@@ -581,6 +627,7 @@ static struct attribute *net_class_attrs - &dev_attr_flags.attr, - &dev_attr_tx_queue_len.attr, - &dev_attr_gro_flush_timeout.attr, -+ &dev_attr_napi_threaded.attr, - &dev_attr_phys_port_id.attr, - &dev_attr_phys_port_name.attr, - &dev_attr_phys_switch_id.attr, diff --git a/target/linux/ipq40xx/patches-5.4/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch b/target/linux/ipq40xx/patches-5.4/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch index 167673bd11..1e22abdf51 100644 --- a/target/linux/ipq40xx/patches-5.4/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch +++ b/target/linux/ipq40xx/patches-5.4/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch @@ -24,7 +24,7 @@ Reviewed-by: Grant Grundler --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -776,6 +776,16 @@ struct xps_map { +@@ -767,6 +767,16 @@ struct xps_map { #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \ - sizeof(struct xps_map)) / sizeof(u16)) @@ -41,7 +41,7 @@ Reviewed-by: Grant Grundler /* * This structure holds all XPS maps for device. Maps are indexed by CPU. */ -@@ -1379,6 +1389,9 @@ struct net_device_ops { +@@ -1370,6 +1380,9 @@ struct net_device_ops { const struct sk_buff *skb, u16 rxq_index, u32 flow_id); diff --git a/target/linux/layerscape/Makefile b/target/linux/layerscape/Makefile index 71034224ab..8b8ca29317 100644 --- a/target/linux/layerscape/Makefile +++ b/target/linux/layerscape/Makefile @@ -7,6 +7,7 @@ include $(TOPDIR)/rules.mk BOARD:=layerscape BOARDNAME:=NXP Layerscape KERNEL_PATCHVER:=5.4 +KERNEL_TESTING_PATCHVER:=5.10 FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4 rootfs-part boot-part SUBTARGETS:=armv8_64b armv7 diff --git a/target/linux/layerscape/armv7/config-5.10 b/target/linux/layerscape/armv7/config-5.10 new file mode 100644 index 0000000000..0b539d8b27 --- /dev/null +++ b/target/linux/layerscape/armv7/config-5.10 @@ -0,0 +1,679 @@ +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +# CONFIG_AD525X_DPOT_SPI is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_APDS9802ALS=y +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_643719=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_798181=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set +# CONFIG_ARM_IMX_BUS_DEVFREQ is not set +# CONFIG_ARM_IMX_CPUFREQ_DT is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_LPAE=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BATTERY_SBS=y +CONFIG_BCM_NET_PHYLIB=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_CMDLINE_PARSER=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=262144 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_BOUNCE=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_BROADCOM_PHY=y +CONFIG_CACHE_L2X0=y +CONFIG_CDROM=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHR_DEV_SG=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_IMX_GPT=y +CONFIG_CLKSRC_MMIO=y +# CONFIG_CLK_IMX8MM is not set +# CONFIG_CLK_IMX8MN is not set +# CONFIG_CLK_IMX8MP is not set +# CONFIG_CLK_IMX8MQ is not set +CONFIG_CLK_QORIQ=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=64 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_COMMON_CLK=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRASH_CORE=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DW_DMAC=y +CONFIG_DW_DMAC_CORE=y +CONFIG_DW_WATCHDOG=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_93CX6=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_FAILOVER=y +CONFIG_FAT_FS=y +# CONFIG_FEC is not set +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_FREEZER=y +CONFIG_FSL_EDMA=y +CONFIG_FSL_GUTS=y +CONFIG_FSL_IFC=y +# CONFIG_FSL_PPFE is not set +CONFIG_FSL_PQ_MDIO=y +CONFIG_FSL_RCPM=y +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FTRACE=y +# CONFIG_FTRACE_SYSCALLS is not set +CONFIG_FUSE_FS=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GIANFAR=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HVC_DRIVER=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_DEMUX_PINCTRL=y +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_IMX=y +# CONFIG_I2C_IMX_LPI2C is not set +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_PINCTRL=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=y +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_XILINX=y +CONFIG_ICPLUS_PHY=y +CONFIG_ICS932S401=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_IMX2_WDT=y +# CONFIG_IMX7ULP_WDT is not set +# CONFIG_IMX8MM_THERMAL is not set +CONFIG_IMX_DMA=y +# CONFIG_IMX_GPCV2_PM_DOMAINS is not set +CONFIG_IMX_INTMUX=y +# CONFIG_IMX_IRQSTEER is not set +CONFIG_IMX_SDMA=y +# CONFIG_IMX_WEIM is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +# CONFIG_INPUT_MISC is not set +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IPC_NS=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_ISL29003=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KCMP=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_LIBFDT=y +CONFIG_LLD_VERSION=0 +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LS_EXTIRQ=y +CONFIG_LS_SCFG_MSI=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MANDATORY_FILE_LOCKING=y +CONFIG_MARVELL_PHY=y +CONFIG_MCPM=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_GPIO is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_VEXPRESS_SYSREG is not set +CONFIG_MICREL_PHY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=16 +# CONFIG_MMC_MXC is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_ESDHC_IMX is not set +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MSDOS_FS=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MX3_IPU=y +CONFIG_MX3_IPU_IRQS=4 +CONFIG_MXC_CLK=y +# CONFIG_MXS_DMA is not set +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_NS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=16 +CONFIG_NTFS_FS=y +CONFIG_NVMEM=y +# CONFIG_NVMEM_IMX_IIM is not set +# CONFIG_NVMEM_SNVS_LPGPR is not set +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PACKET_DIAG=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +# CONFIG_PCI_IMX6 is not set +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PID_NS=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_IMX8MM is not set +# CONFIG_PINCTRL_IMX8MN is not set +# CONFIG_PINCTRL_IMX8MP is not set +# CONFIG_PINCTRL_IMX8MQ is not set +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_BRCMKONA=y +CONFIG_POWER_RESET_BRCMSTB=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_842_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZO_COMPRESS is not set +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_QORIQ=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_REALTEK_PHY=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_EM3027=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=y +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +CONFIG_RTC_DRV_PCF2127=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCSI=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EM=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_BCM63XX=y +CONFIG_SERIAL_BCM63XX_CONSOLE=y +CONFIG_SERIAL_CONEXANT_DIGICOLOR=y +CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_IMX_EARLYCON=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_ST_ASC=y +CONFIG_SERIAL_ST_ASC_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SMSC_PHY=y +CONFIG_SOCK_DIAG=y +CONFIG_SOC_BRCMSTB=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_IMX50 is not set +# CONFIG_SOC_IMX51 is not set +# CONFIG_SOC_IMX53 is not set +# CONFIG_SOC_IMX6Q is not set +# CONFIG_SOC_IMX6SL is not set +# CONFIG_SOC_IMX6SLL is not set +# CONFIG_SOC_IMX6SX is not set +# CONFIG_SOC_IMX6UL is not set +# CONFIG_SOC_IMX7D is not set +# CONFIG_SOC_IMX7ULP is not set +# CONFIG_SOC_IMX8M is not set +CONFIG_SOC_LS1021A=y +# CONFIG_SOC_VF610 is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_CADENCE=y +CONFIG_SPI_DYNAMIC=y +# CONFIG_SPI_FSL_LPSPI is not set +# CONFIG_SPI_FSL_QUADSPI is not set +# CONFIG_SPI_IMX is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_XILINX=y +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +CONFIG_STAGING_BOARD=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYNC_FILE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNIX_DIAG=y +CONFIG_UNWINDER_ARM=y +CONFIG_USB_SUPPORT=y +CONFIG_USER_NS=y +CONFIG_USE_OF=y +CONFIG_UTS_NS=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VITESSE_PHY=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XILINX_WATCHDOG=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/layerscape/armv8_64b/config-5.10 b/target/linux/layerscape/armv8_64b/config-5.10 new file mode 100644 index 0000000000..585efe096a --- /dev/null +++ b/target/linux/layerscape/armv8_64b/config-5.10 @@ -0,0 +1,853 @@ +CONFIG_64BIT=y +CONFIG_AQUANTIA_PHY=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_CNP=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_MODULE_PLTS=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_UAO=y +CONFIG_ARM64_VA_BITS=48 +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_ARM64_VHE=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_FSL_MC=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_ARM_PL172_MPMC is not set +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_SMMU=y +# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_V3=y +# CONFIG_ARM_SMMU_V3_SVA is not set +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATA=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_BATTERY_BQ27XXX=y +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_BATTERY_BQ27XXX_I2C=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=262144 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BTRFS_FS=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23144=y +CONFIG_CAVIUM_ERRATUM_23154=y +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLK_LS1028A_PLLDIG=y +CONFIG_CLK_QORIQ=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_CS2000_CP=y +# CONFIG_COMMON_CLK_FSL_SAI is not set +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRASH_CORE=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_T10DIF=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CROS_EC is not set +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DIMLIB=y +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_CMA=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DPAA2_CONSOLE=y +CONFIG_DPAA_ERRATUM_A050385=y +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_ELF_CORE=y +# CONFIG_EMBEDDED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXTCON=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_F2FS_FS=y +CONFIG_FAILOVER=y +CONFIG_FANOTIFY=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FREEZER=y +# CONFIG_FSL_BMAN_TEST is not set +CONFIG_FSL_DPAA=y +CONFIG_FSL_DPAA2=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_DPAA2_ETHSW=y +CONFIG_FSL_DPAA2_PTP_CLOCK=y +# CONFIG_FSL_DPAA2_QDMA is not set +# CONFIG_FSL_DPAA_CHECKING is not set +CONFIG_FSL_DPAA_ETH=y +CONFIG_FSL_EDMA=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC_MDIO=y +CONFIG_FSL_ENETC_PTP_CLOCK=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_FSL_FMAN=y +CONFIG_FSL_GUTS=y +CONFIG_FSL_IFC=y +CONFIG_FSL_MC_BUS=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +# CONFIG_FSL_QMAN_TEST is not set +CONFIG_FSL_RCPM=y +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FUSE_FS=y +CONFIG_FW_CACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_GARP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +# CONFIG_GIANFAR is not set +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HID=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GENERIC=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HOLES_IN_ZONE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_IRQ=y +CONFIG_HVC_XEN=y +CONFIG_HVC_XEN_FRONTEND=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_IMX=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMX2_WDT=y +CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_TCP_DIAG=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y +CONFIG_INTERVAL_TREE=y +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_IO_PGTABLE=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IPC_NS=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_BYPASS_MANAGER=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JBD2=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KCMP=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KSM=y +CONFIG_LIBCRC32C=y +CONFIG_LIBFDT=y +CONFIG_LLD_VERSION=0 +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LS_EXTIRQ=y +CONFIG_LS_SCFG_MSI=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MANDATORY_FILE_LOCKING=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_GPIO is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMTEST=y +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_VEXPRESS_SYSREG is not set +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +CONFIG_MPILIB=y +CONFIG_MRP=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384 +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTIPLEXER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MUX_ADG792A is not set +# CONFIG_MUX_ADGS1408 is not set +# CONFIG_MUX_GPIO is not set +CONFIG_MUX_MMIO=y +CONFIG_MV_XOR_V2=y +CONFIG_NAMESPACES=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_NS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NODES_SHIFT=2 +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=64 +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_NVMEM=y +# CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OF_NUMA=y +CONFIG_PACKET_DIAG=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_REPORTING=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PARAVIRT=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_PCIE_MOBIVEIL=y +CONFIG_PCIE_MOBIVEIL_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCI_ATS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HISI=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCS_LYNX=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_XGENE=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_PID_NS=y +CONFIG_PL330_DMA=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROFILING=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_QORIQ=y +CONFIG_QCOM_HIDMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QORIQ_CPUFREQ=y +CONFIG_QORIQ_THERMAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_RAID6_PQ=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=y +CONFIG_RTC_DRV_PCF2127=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_THERMAL_PRESSURE=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +# CONFIG_SCSI_SAS_ATA is not set +CONFIG_SCSI_SAS_ATTRS=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SC16IS7XX=y +CONFIG_SERIAL_SC16IS7XX_CORE=y +# CONFIG_SERIAL_SC16IS7XX_I2C is not set +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIO=y +CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +CONFIG_SMP=y +CONFIG_SOCK_DIAG=y +CONFIG_SOC_BUS=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_PL022=y +CONFIG_SPMI=y +# CONFIG_SPMI_HISI3670 is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +# CONFIG_SQUASHFS_XZ is not set +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SRAM=y +CONFIG_SRCU=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWIOTLB_XEN=y +CONFIG_SWPHY=y +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_HYPERVISOR=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_UACCE is not set +CONFIG_UBIFS_FS=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UIO=y +CONFIG_UIO_AEC=y +CONFIG_UIO_CIF=y +CONFIG_UIO_DMEM_GENIRQ=y +CONFIG_UIO_MF624=y +CONFIG_UIO_NETX=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_PRUSS is not set +CONFIG_UIO_SERCOS3=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNIX_DIAG=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB_SUPPORT=y +CONFIG_USER_NS=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_UTS_NS=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_VFAT_FS=y +CONFIG_VFIO=y +CONFIG_VFIO_FSL_MC=y +CONFIG_VFIO_IOMMU_TYPE1=y +# CONFIG_VFIO_MDEV is not set +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI_MMAP=y +# CONFIG_VFIO_PLATFORM is not set +CONFIG_VFIO_VIRQFD=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_VIRTIO_IOMMU is not set +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VITESSE_PHY=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XARRAY_MULTI=y +CONFIG_XEN=y +CONFIG_XENFS=y +CONFIG_XEN_AUTO_XLATE=y +CONFIG_XEN_BACKEND=y +CONFIG_XEN_BALLOON=y +# CONFIG_XEN_BLKDEV_BACKEND is not set +CONFIG_XEN_BLKDEV_FRONTEND=y +CONFIG_XEN_COMPAT_XENFS=y +CONFIG_XEN_DEV_EVTCHN=y +CONFIG_XEN_DOM0=y +CONFIG_XEN_FBDEV_FRONTEND=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +# CONFIG_XEN_NETDEV_BACKEND is not set +CONFIG_XEN_NETDEV_FRONTEND=y +CONFIG_XEN_PRIVCMD=y +# CONFIG_XEN_PVCALLS_BACKEND is not set +# CONFIG_XEN_SCSI_FRONTEND is not set +CONFIG_XEN_SYS_HYPERVISOR=y +# CONFIG_XEN_WDT is not set +CONFIG_XEN_XENBUS_FRONTEND=y +CONFIG_XFS_FS=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/layerscape/image/armv7.mk b/target/linux/layerscape/image/armv7.mk index da9484764c..fe396212e7 100644 --- a/target/linux/layerscape/image/armv7.mk +++ b/target/linux/layerscape/image/armv7.mk @@ -10,7 +10,6 @@ define Device/Default KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb KERNEL_NAME := zImage KERNEL_LOADADDR := 0x80008000 - KERNEL_ENTRY_POINT := 0x80008000 DEVICE_DTS = $(lastword $(subst _, ,$(1))) IMAGE_SIZE := 64m IMAGE/sysupgrade.bin = \ diff --git a/target/linux/layerscape/image/armv8_64b.mk b/target/linux/layerscape/image/armv8_64b.mk index 89c81e5cb4..a4d1bfab3b 100644 --- a/target/linux/layerscape/image/armv8_64b.mk +++ b/target/linux/layerscape/image/armv8_64b.mk @@ -8,8 +8,11 @@ define Device/Default FILESYSTEMS := squashfs KERNEL := kernel-bin | gzip | uImage gzip KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb +ifdef CONFIG_LINUX_5_4 KERNEL_LOADADDR := 0x80080000 - KERNEL_ENTRY_POINT := 0x80080000 +else + KERNEL_LOADADDR := 0x80000000 +endif DEVICE_DTS = freescale/$(subst _,-,$(1)) IMAGE_SIZE := 64m IMAGE/sysupgrade.bin = \ @@ -112,7 +115,11 @@ define Device/fsl_ls1043a-rdb kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 +ifdef CONFIG_LINUX_5_4 DEVICE_DTS := freescale/fsl-ls1043a-rdb-sdk +else + DEVICE_DTS := freescale/fsl-ls1043a-rdb +endif IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -138,7 +145,11 @@ define Device/fsl_ls1043a-rdb-sdboot kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 +ifdef CONFIG_LINUX_5_4 DEVICE_DTS := freescale/fsl-ls1043a-rdb-sdk +else + DEVICE_DTS := freescale/fsl-ls1043a-rdb +endif IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ @@ -158,7 +169,11 @@ define Device/fsl_ls1046a-frwy DEVICE_PACKAGES += \ layerscape-fman \ tfa-ls1046a-frwy +ifdef CONFIG_LINUX_5_4 DEVICE_DTS := freescale/fsl-ls1046a-frwy-sdk +else + DEVICE_DTS := freescale/fsl-ls1046a-frwy +endif IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -179,7 +194,11 @@ define Device/fsl_ls1046a-frwy-sdboot DEVICE_PACKAGES += \ layerscape-fman \ tfa-ls1046a-frwy-sdboot +ifdef CONFIG_LINUX_5_4 DEVICE_DTS := freescale/fsl-ls1046a-frwy-sdk +else + DEVICE_DTS := freescale/fsl-ls1046a-frwy +endif IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ @@ -204,7 +223,11 @@ define Device/fsl_ls1046a-rdb kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 +ifdef CONFIG_LINUX_5_4 DEVICE_DTS := freescale/fsl-ls1046a-rdb-sdk +else + DEVICE_DTS := freescale/fsl-ls1046a-rdb +endif IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -230,7 +253,11 @@ define Device/fsl_ls1046a-rdb-sdboot kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 +ifdef CONFIG_LINUX_5_4 DEVICE_DTS := freescale/fsl-ls1046a-rdb-sdk +else + DEVICE_DTS := freescale/fsl-ls1046a-rdb +endif IMAGE/sdcard.img.gz := \ ls-clean | \ ls-append-sdhead $(1) | pad-to 4K | \ diff --git a/target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch b/target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch new file mode 100644 index 0000000000..9dcd9348b2 --- /dev/null +++ b/target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch @@ -0,0 +1,26 @@ +From 5b35aae22b4ca2400e49561c9267aa01346f91d4 Mon Sep 17 00:00:00 2001 +From: Mathew McBride +Date: Tue, 17 Apr 2018 10:01:03 +1000 +Subject: [PATCH] add DTS for Traverse LS1043 Boards + +Signed-off-by: Mathew McBride +[rebase] +Signed-off-by: Yangbo Lu +--- + arch/arm64/boot/dts/freescale/Makefile | 3 +++ + arch/arm64/boot/dts/freescale/traverse-ls1043s.dts | 29 ++++++++++++++++++++++ + arch/arm64/boot/dts/freescale/traverse-ls1043v.dts | 29 ++++++++++++++++++++++ + 3 files changed, 61 insertions(+) + +--- a/arch/arm64/boot/dts/freescale/Makefile ++++ b/arch/arm64/boot/dts/freescale/Makefile +@@ -28,6 +28,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2 + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb + ++dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb ++dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb ++ + dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb diff --git a/target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch b/target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch new file mode 100644 index 0000000000..c7ecb98567 --- /dev/null +++ b/target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch @@ -0,0 +1,291 @@ +From 55e00e402d6143aeb153761f8144d9fee5f1f009 Mon Sep 17 00:00:00 2001 +From: Biwen Li +Date: Fri, 26 Oct 2018 16:00:37 +0800 +Subject: [PATCH] arm: dts: ls1021a: Add LS1021A-IOT board support + +Signed-off-by: Biwen Li +[rebase] +Signed-off-by: Yangbo Lu +--- + arch/arm/boot/dts/Makefile | 3 +- + arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++++++++++ + 2 files changed, 264 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -665,7 +665,8 @@ dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-moxa-uc-8410a.dtb \ + ls1021a-qds.dtb \ + ls1021a-tsn.dtb \ +- ls1021a-twr.dtb ++ ls1021a-twr.dtb \ ++ ls1021a-iot.dtb + dtb-$(CONFIG_SOC_VF610) += \ + vf500-colibri-eval-v3.dtb \ + vf610-bk4.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/ls1021a-iot.dts +@@ -0,0 +1,262 @@ ++/* ++ * Copyright 2013-2016 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++/dts-v1/; ++#include "ls1021a.dtsi" ++ ++/ { ++ model = "LS1021A IOT Board"; ++ ++ sys_mclk: clock-mclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24576000>; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ reg_3p3v: regulator@0 { ++ compatible = "regulator-fixed"; ++ reg = <0>; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_2p5v: regulator@1 { ++ compatible = "regulator-fixed"; ++ reg = <1>; ++ regulator-name = "2P5V"; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-always-on; ++ }; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,widgets = ++ "Microphone", "Microphone Jack", ++ "Headphone", "Headphone Jack", ++ "Speaker", "Speaker Ext", ++ "Line", "Line In Jack"; ++ simple-audio-card,routing = ++ "MIC_IN", "Microphone Jack", ++ "Microphone Jack", "Mic Bias", ++ "LINE_IN", "Line In Jack", ++ "Headphone Jack", "HP_OUT", ++ "Speaker Ext", "LINE_OUT"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&sai2>; ++ frame-master; ++ bitclock-master; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&codec>; ++ frame-master; ++ bitclock-master; ++ }; ++ }; ++ ++ firmware { ++ optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ }; ++}; ++ ++&enet0 { ++ tbi-handle = <&tbi1>; ++ phy-handle = <&phy1>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&enet1 { ++ tbi-handle = <&tbi1>; ++ phy-handle = <&phy3>; ++ phy-connection-type = "sgmii"; ++ status = "okay"; ++}; ++ ++&enet2 { ++ fixed-link = <0 1 1000 0 0>; ++ phy-connection-type = "rgmii-id"; ++ status = "okay"; ++}; ++ ++&can0{ ++ status = "disabled"; ++}; ++ ++&can1{ ++ status = "disabled"; ++}; ++ ++&can2{ ++ status = "disabled"; ++}; ++ ++&can3{ ++ status = "okay"; ++}; ++ ++&esdhc{ ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ max1239@35 { ++ compatible = "maxim,max1239"; ++ reg = <0x35>; ++ #io-channel-cells = <1>; ++ }; ++ ++ codec: sgtl5000@2a { ++ #sound-dai-cells=<0x0>; ++ compatible = "fsl,sgtl5000"; ++ reg = <0x2a>; ++ VDDA-supply = <®_3p3v>; ++ VDDIO-supply = <®_2p5v>; ++ clocks = <&sys_mclk 1>; ++ }; ++ ++ pca9555: pca9555@23 { ++ compatible = "nxp,pca9555"; ++ /*pinctrl-names = "default";*/ ++ /*interrupt-parent = <&gpio2>; ++ interrupts = <19 0x2>;*/ ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ reg = <0x23>; ++ }; ++ ++ ina220@44 { ++ compatible = "ti,ina220"; ++ reg = <0x44>; ++ shunt-resistor = <1000>; ++ }; ++ ++ ina220@45 { ++ compatible = "ti,ina220"; ++ reg = <0x45>; ++ shunt-resistor = <1000>; ++ }; ++ ++ lm75b@48 { ++ compatible = "nxp,lm75a"; ++ reg = <0x48>; ++ }; ++ ++ adt7461a@4c { ++ compatible = "adt7461a"; ++ reg = <0x4c>; ++ }; ++ ++ hdmi: sii9022a@39 { ++ compatible = "fsl,sii902x"; ++ reg = <0x39>; ++ interrupts = ; ++ }; ++}; ++ ++&i2c1 { ++ status = "disabled"; ++}; ++ ++&ifc { ++ status = "disabled"; ++}; ++ ++&lpuart0 { ++ status = "okay"; ++}; ++ ++&mdio0 { ++ phy0: ethernet-phy@0 { ++ reg = <0x0>; ++ }; ++ phy1: ethernet-phy@1 { ++ reg = <0x1>; ++ }; ++ phy2: ethernet-phy@2 { ++ reg = <0x2>; ++ }; ++ phy3: ethernet-phy@3 { ++ reg = <0x3>; ++ }; ++ tbi1: tbi-phy@1f { ++ reg = <0x1f>; ++ device_type = "tbi-phy"; ++ }; ++}; ++ ++&qspi { ++ num-cs = <2>; ++ status = "okay"; ++ ++ qflash0: s25fl128s@0 { ++ compatible = "spansion,s25fl129p1"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <20000000>; ++ reg = <0>; ++ }; ++}; ++ ++&sai2 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&dcu { ++ display = <&display>; ++ status = "okay"; ++ ++ display: display@0 { ++ bits-per-pixel = <24>; ++ ++ display-timings { ++ native-mode = <&timing0>; ++ ++ timing0: mode0 { ++ clock-frequency = <25000000>; ++ hactive = <640>; ++ vactive = <480>; ++ hback-porch = <80>; ++ hfront-porch = <80>; ++ vback-porch = <16>; ++ vfront-porch = <16>; ++ hsync-len = <12>; ++ vsync-len = <2>; ++ hsync-active = <1>; ++ vsync-active = <1>; ++ }; ++ }; ++ }; ++}; diff --git a/target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch new file mode 100644 index 0000000000..ef645f123d --- /dev/null +++ b/target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch @@ -0,0 +1,295 @@ +From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001 +From: Calvin Johnson +Date: Sat, 16 Sep 2017 14:20:23 +0530 +Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support + +Update ls1012a dtsi and platform dts files with support for ppfe. + +Signed-off-by: Calvin Johnson +Signed-off-by: Anjaneyulu Jagarlmudi +--- + .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++ + .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++ + .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++ + 5 files changed, 205 insertions(+) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +@@ -13,6 +13,11 @@ + model = "LS1012A Freedom Board"; + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; + ++ aliases { ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; ++ }; ++ + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -74,6 +79,44 @@ + }; + }; + ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; ++ + &qspi { + status = "okay"; + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +@@ -14,6 +14,11 @@ + / { + model = "LS1012A FRWY Board"; + compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; ++ ++ aliases { ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; ++ }; + }; + + &duart0 { +@@ -24,6 +29,44 @@ + status = "okay"; + }; + ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; ++ + &qspi { + status = "okay"; + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +@@ -13,6 +13,11 @@ + model = "LS1012A QDS Board"; + compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; + ++ aliases { ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; ++ }; ++ + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -127,6 +132,44 @@ + }; + }; + }; ++ ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x2>; ++ phy-mode = "sgmii-2500"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x3>; ++ phy-mode = "sgmii-2500"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; + + &qspi { + status = "okay"; +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +@@ -12,6 +12,15 @@ + / { + model = "LS1012A RDB Board"; + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; ++ ++ aliases { ++ ethernet0 = &pfe_mac0; ++ ethernet1 = &pfe_mac1; ++ }; ++}; ++ ++&pcie1 { ++ status = "okay"; + }; + + &duart0 { +@@ -35,6 +44,44 @@ + status = "okay"; + }; + ++&pfe { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pfe_mac0: ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x1>; /* enabled/disabled */ ++ }; ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ ++ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "rgmii-txid"; ++ fsl,pfe-phy-if-flags = <0x0>; ++ ++ mdio@0 { ++ reg = <0x0>; /* enabled/disabled */ ++ }; ++ }; ++}; ++ + &qspi { + status = "okay"; + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +@@ -531,6 +531,35 @@ + }; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ pfe_reserved: packetbuffer@83400000 { ++ reg = <0 0x83400000 0 0xc00000>; ++ }; ++ }; ++ ++ pfe: pfe@04000000 { ++ compatible = "fsl,pfe"; ++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ ++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ ++ reg-names = "pfe", "pfe-ddr"; ++ fsl,pfe-num-interfaces = <0x2>; ++ interrupts = <0 172 0x4>, /* HIF interrupt */ ++ <0 173 0x4>, /*HIF_NOCPY interrupt */ ++ <0 174 0x4>; /* WoL interrupt */ ++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; ++ memory-region = <&pfe_reserved>; ++ fsl,pfe-scfg = <&scfg 0>; ++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; ++ clocks = <&clockgen 4 0>; ++ clock-names = "pfe"; ++ ++ status = "okay"; ++ }; ++ + firmware { + optee { + compatible = "linaro,optee-tz"; diff --git a/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch new file mode 100644 index 0000000000..71c86e55fd --- /dev/null +++ b/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch @@ -0,0 +1,12036 @@ +From ab06204b9ae48324ed5b7e7026cce47ecd0a376d Mon Sep 17 00:00:00 2001 +From: Martin Schiller +Date: Mon, 8 Nov 2021 14:56:10 +0100 +Subject: [PATCH] staging: add fsl_ppfe driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This patch is the squashed version of all ppfe related commits from +LSDK-21.08. + +See the following git log for further details: + +commit bc389fa57819620b61f86a39444cf22c70e291ad +Author: Calvin Johnson +Date: Sat Sep 16 07:05:49 2017 +0530 + + net: fsl_ppfe: dts binding for ppfe + + Signed-off-by: Calvin Johnson + Signed-off-by: Anjaneyulu Jagarlmudi + +commit d3822b65f897e4c421c72bd215f34e41d8c4a40e +Author: Calvin Johnson +Date: Sat Sep 16 14:21:37 2017 +0530 + + staging: fsl_ppfe/eth: header files for pfe driver + + This patch has all pfe header files. + + Signed-off-by: Calvin Johnson + Signed-off-by: Anjaneyulu Jagarlmudi + +commit 9184a85f93816a8b81cb363464925757185b7138 +Author: Calvin Johnson +Date: Sat Sep 16 14:22:17 2017 +0530 + + staging: fsl_ppfe/eth: introduce pfe driver + + This patch introduces Linux support for NXP's LS1012A Packet + Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding + engine to provide high performance Ethernet interfaces. The device + includes two Ethernet ports. + + Signed-off-by: Calvin Johnson + Signed-off-by: Anjaneyulu Jagarlmudi + +commit 63f6117f1c9af34bc333425507a8b858fcd61951 +Author: Calvin Johnson +Date: Wed Oct 11 19:23:38 2017 +0530 + + staging: fsl_ppfe/eth: fix RGMII tx delay issue + + Recently logic to enable RGMII tx delay was changed by + below patch. + + https://patchwork.kernel.org/patch/9447581/ + + Based on the patch, appropriate change is made in PFE driver. + + Signed-off-by: Calvin Johnson + Signed-off-by: Anjaneyulu Jagarlmudi + +commit adf71df9d53026513da71892a27c455ae23a6d06 +Author: Calvin Johnson +Date: Wed Oct 18 14:29:30 2017 +0530 + + staging: fsl_ppfe/eth: remove unused functions + + Remove unused functions hif_xmit_pkt & hif_lib_xmit_pkt. + + Signed-off-by: Calvin Johnson + +commit ea632882dacf4ec21f84fa73ebff7d89d46fbeb3 +Author: Calvin Johnson +Date: Wed Oct 18 18:34:41 2017 +0530 + + staging: fsl_ppfe/eth: fix read/write/ack idx issue + + While fixing checkpatch errors some of the index increments + were commented out. They are enabled. + + Signed-off-by: Calvin Johnson + +commit 75dc5856eafe3ec988aa52f498ad683332e5a528 +Author: Calvin Johnson +Date: Fri Oct 27 11:20:47 2017 +0530 + + staging: fsl_ppfe/eth: Make phy_ethtool_ksettings_get return void + + Make return value void since function never return meaningful value + + Signed-off-by: Calvin Johnson + +commit fd60dff2329a4c20f5638147db315879d4b92097 +Author: Calvin Johnson +Date: Wed Nov 15 13:45:27 2017 +0530 + + staging: fsl_ppfe/eth: add function to update tmu credits + + __hif_lib_update_credit function is used to update the tmu credits. + If tx_qos is set, tmu credit is updated based on the number of packets + transmitted by tmu. + + Signed-off-by: Calvin Johnson + Signed-off-by: Anjaneyulu Jagarlmudi + +commit 259418d3755afeabca062df4c177cb6617be7e2b +Author: Kavi Akhila-B46177 +Date: Thu Nov 2 12:05:35 2017 +0530 + + staging: fsl_ppfe/eth: Avoid packet drop at TMU queues + + Added flow control between TMU queues and PFE Linux driver, + based on TMU credits availability. + Added tx_qos module parameter to control this behavior. + Use queue-0 as default queue to transmit packets. + + Signed-off-by: Calvin Johnson + Signed-off-by: Akhila Kavi + Signed-off-by: Anjaneyulu Jagarlmudi + +commit 48f8aa50bdcccdec699550d10e274711f9f8cb4d +Author: Bhaskar Upadhaya +Date: Wed Nov 29 12:08:00 2017 +0530 + + staging: fsl_ppfe/eth: Enable PFE in clause 45 mode + + when we opearate in clause 45 mode, we need to call + the function get_phy_device() with its 3rd argument as + "true" and then the resultant phy device needs to be + register with phy layer via phy_device_register() + + Signed-off-by: Bhaskar Upadhaya + +commit 217cf01a1eb7c0a1f44c250ab05bb832287069ca +Author: Bhaskar Upadhaya +Date: Wed Nov 29 12:21:43 2017 +0530 + + staging: fsl_ppfe/eth: Disable autonegotiation for 2.5G SGMII + + PCS initialization sequence for 2.5G SGMII interface governs + auto negotiation to be in disabled mode + + Signed-off-by: Bhaskar Upadhaya + +commit 0758955e5d8be44260c3b6877ff78e18c2dc2706 +Author: Calvin Johnson +Date: Thu Mar 8 13:58:38 2018 +0530 + + staging: fsl_ppfe/eth: calculate PFE_PKT_SIZE with SKB_DATA_ALIGN + + pfe packet size was calculated without considering skb data alignment + and this resulted in jumbo frames crashing kernel when the + cacheline size increased from 64 to 128 bytes with + commit 97303480753e ("arm64: Increase the max granular size"). + + Modify pfe packet size caclulation to include skb data alignment of + sizeof(struct skb_shared_info). + + Signed-off-by: Calvin Johnson + +commit d336c470781a28fe44a494b4f537a4dbac9fd1dd +Author: Akhil Goyal +Date: Fri Apr 13 15:41:28 2018 +0530 + + staging: fsl_ppfe/eth: support for userspace networking + + This patch adds the userspace mode support to fsl_ppfe network driver. + In the new mode, basic hardware initialization is performed in kernel, while + the datapath and HIF handling is the responsibility of the userspace. + + The new command line parameter is added to initialize the ppfe module + in userspace mode. By default the module remains in kernelspace networking + mode. + To enable userspace mode, use "insmod pfe.ko us=1" + + Signed-off-by: Akhil Goyal + Signed-off-by: Gagandeep Singh + +commit 30f97a6ae76cf7a284fee4b8ad30bce24568ac53 +Author: Calvin Johnson +Date: Mon Apr 30 11:40:01 2018 +0530 + + staging: fsl_ppfe/eth: unregister netdev after pfe_phy_exit + + rmmod pfe.ko throws below warning: + + kernfs: can not remove 'phydev', no directory + ------------[ cut here ]------------ + WARNING: CPU: 0 PID: 2230 at fs/kernfs/dir.c:1481 + kernfs_remove_by_name_ns+0x90/0xa0 + + This is caused when the unregistered netdev structure is accessed to + disconnect phy. + + Resolve the issue by unregistering netdev after disconnecting phy. + + Signed-off-by: Calvin Johnson + +commit 1b7daa665cd53fe51f19689c5b209fd89551f131 +Author: anuj batham +Date: Fri Apr 27 14:38:09 2018 +0530 + + staging: fsl_ppfe/eth: HW parse results for DPDK + + HW Parse results are included in the packet headroom. + Length and Offset calculation now accommodates parse info size. + + Signed-off-by: Archana Madhavan + +commit 0aeb9981d44aad6a45eb8f3ead37f91258be173f +Author: Calvin Johnson +Date: Wed Jun 20 10:22:32 2018 +0530 + + staging: fsl_ppfe/eth: reorganize pfe_netdev_ops + + Reorganize members of struct pfe_netdev_ops to match with the order + of members in struct net_device_ops defined in include/linux/netdevice.h + + Signed-off-by: Calvin Johnson + +commit 1cbccc5028c337e7c88bf61cf89038cfad449d34 +Author: Calvin Johnson +Date: Wed Jun 20 10:22:50 2018 +0530 + + staging: fsl_ppfe/eth: use mask for rx max frame len + + Define and use PFE_RCR_MAX_FL_MASK to properly set Rx max frame + length of MAC Receive Control Register. + + Signed-off-by: Calvin Johnson + +commit d8c8ed721470bd47ad5414d8fdc5d093cdd247f7 +Author: Calvin Johnson +Date: Wed Jun 20 10:23:01 2018 +0530 + + staging: fsl_ppfe/eth: define pfe ndo_change_mtu function + + Define ndo_change_mtu function for pfe. This sets the max Rx frame + length to the new mtu. + + Signed-off-by: Calvin Johnson + +commit f5f50edda84cf9305db06310536525c206970d6c +Author: Calvin Johnson +Date: Wed Jun 20 10:23:16 2018 +0530 + + staging: fsl_ppfe/eth: remove jumbo frame enable from gemac init + + MAC Receive Control Register was configured to allow jumbo frames. + This is removed as jumbo frames can be supported anytime by changing + mtu which will in turn modify MAX_FL field of MAC RCR. + Jumbo frames caused pfe to hang on LS1012A rev 1.0 Silicon due to + erratum A-010897. + + Signed-off-by: Calvin Johnson + +commit 53e3c57af87d72ee0299a723499bd911cb1ed25a +Author: Calvin Johnson +Date: Wed Jun 20 10:23:32 2018 +0530 + + staging: fsl_ppfe/eth: disable CRC removal + + Disable CRC removal from the packet, so that packets are forwarded + as is to Linux. + CRC configuration in MAC will be reflected in the packet received + to Linux. + + Signed-off-by: Calvin Johnson + +commit eb55f7878a6ece7edbecd648e147a5683da18c76 +Author: Calvin Johnson +Date: Wed Jun 20 10:23:41 2018 +0530 + + staging: fsl_ppfe/eth: handle ls1012a errata_a010897 + + On LS1012A rev 1.0, Jumbo frames are not supported as it causes + the PFE controller to hang. A reset of the entire chip is required + to resume normal operation. + + To handle this errata, frames with length > 1900 are truncated for + rev 1.0 of LS1012A. + + Signed-off-by: Calvin Johnson + +commit c7b4f5f8f74925ce1d209ee4fcd5973d5cc5b61c +Author: Calvin Johnson +Date: Thu Oct 4 09:38:34 2018 +0530 + + staging: fsl_ppfe/eth: replace magic numbers + + Replace magic numbers and some cosmetic changes. + + Signed-off-by: Calvin Johnson + +commit c0ed379aa248dd70b2acf5dd8908bec1f6de5487 +Author: Calvin Johnson +Date: Thu Oct 4 09:39:00 2018 +0530 + + staging: fsl_ppfe/eth: resolve indentation warning + + Resolve the following indentation warning: + + drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c: + In function ‘pfe_get_gemac_if_proprties’: + drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:96:2: + warning: this ‘else’ clause does not guard... + [-Wmisleading-indentation] + else + ^~~~ + drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:98:3: + note: ...this statement, but the latter is misleadingly indented as + if it were guarded by the ‘else’ + pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id; + ^~~~~ + + Signed-off-by: Calvin Johnson + +commit c509cb585af2848dbb4ab194bf0fa435e356cb0a +Author: Calvin Johnson +Date: Thu Oct 4 09:38:17 2018 +0530 + + staging: fsl_ppfe/eth: add fixed-link support + + In cases where MAC is not connected to a normal MDIO-managed PHY + device, and instead to a switch, it is configured as a "fixed-link". + Code to handle this scenario is added here. + + phy_node in the dtb is checked to identify a fixed-link. + On identification of a fixed-link, it is registered and connected. + + Signed-off-by: Calvin Johnson + +commit 5e93b6ed52d4cdce12a481866c6f211299940734 +Author: Shreyansh Jain +Date: Wed Jun 6 14:19:34 2018 +0530 + + staging: fsl_ppfe: add support for a char dev for link status + + Read and IOCTL support is added. Application would need to open, + read/ioctl the /dev/pfe_us_cdev device. + select is pending as it requires a wait_queue. + + Signed-off-by: Shreyansh Jain + Signed-off-by: Calvin Johnson + +commit 48e064df94157b0c34f2d75e164ea5c7f4970b7b +Author: Akhil Goyal +Date: Thu Jul 5 20:14:21 2018 +0530 + + staging: fsl_ppfe: enable hif event from userspace + + HIF interrupts are enabled using ioctl from user space, + and epoll wait from user space wakes up when there is an HIF + interrupt. + + Signed-off-by: Akhil Goyal + +commit d16d91d3250abec31422b28ff04a973b8b3d73c5 +Author: Akhil Goyal +Date: Fri Jul 20 16:43:25 2018 +0530 + + staging: fsl_ppfe: performance tuning for user space + + interrupt coalescing of 100 usec is added. + + Signed-off-by: Akhil Goyal + Signed-off-by: Sachin Saxena + +commit eadb4c9d3e37c44659284fc9190d7e4f04b12aa0 +Author: Calvin Johnson +Date: Tue Nov 20 21:50:23 2018 +0530 + + staging: fsl_ppfe/eth: Update to use SPDX identifiers + + Replace license text with corresponding SPDX identifiers and update the + format of existing SPDX identifiers to follow the new guideline + Documentation/process/license-rules.rst. + + Signed-off-by: Calvin Johnson + +commit a468be7bda6fd98afab1cccb4e7151f23ca096e9 +Author: Calvin Johnson +Date: Tue Nov 20 21:50:40 2018 +0530 + + staging: fsl_ppfe/eth: misc clean up + + - remove redundant hwfeature init + - remove unused vars from ls1012a_eth_platform_data + - To handle ls1012a errata_a010897, PPFE driver requires GUTS driver + to be compiled in. Select FSL_GUTS when PPFE driver is compiled. + + Signed-off-by: Calvin Johnson + +commit 0e37bfbeda9510688ad987251aa07e3c88d6ba41 +Author: Calvin Johnson +Date: Tue Nov 20 21:50:51 2018 +0530 + + staging: fsl_ppfe/eth: reorganize platform phy parameters + + - Use "phy-handle" and of_* functions to get phy node and fixed-link + parameters + + - Reorganize phy parameters and initialize them only if phy-handle + or fixed-link is defined in the dtb. + + - correct typo pfe_get_gemac_if_proprties to pfe_get_gemac_if_properties + + Signed-off-by: Calvin Johnson + +commit c8703ab06e644e853b12baf082dd703f6a4440a5 +Author: Calvin Johnson +Date: Fri Nov 23 23:58:28 2018 +0530 + + staging: fsl_ppfe/eth: support single interface initialization + + - arrange members of struct mii_bus in sequence matching phy.h + - if mdio node is defined, use of_mdiobus_register to register + child nodes (phy devices) available on the mdio bus. + - remove of_phy_register_fixed_link from pfe_phy_init as it is being + handled in pfe_get_gemac_if_properties + - remove mdio enabled check + - skip phy init, if no PHY or fixed-link + + Signed-off-by: Calvin Johnson + +commit 89804e2d74002d01ea3f174048176e498298329a +Author: Calvin Johnson +Date: Tue Nov 20 21:51:53 2018 +0530 + + net: fsl_ppfe: update dts properties for phy + + Use commonly used phy-handle property and mdio subnode to handle + phy properties. + + Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags. + + Signed-off-by: Calvin Johnson + +commit 5b0cc262ba7791fb0fae1f81f9619f54a15a75ba +Author: Calvin Johnson +Date: Fri Dec 7 19:30:03 2018 +0530 + + staging: fsl_ppfe/eth: remove unused code + + - remove gemac-bus-id related code that is unused. + - remove unused prototype gemac_set_mdc_div. + + Signed-off-by: Calvin Johnson + +commit a5a237f331ab7fcd85b95466f481ddb7023aecc3 +Author: Calvin Johnson +Date: Mon Dec 10 10:22:33 2018 +0530 + + staging: fsl_ppfe/eth: separate mdio init from mac init + + - separate mdio initialization from mac initialization + - Define pfe_mdio_priv_s structure to hold mii_bus structure and other + related data. + - Modify functions to work with the separted mdio init model. + + Signed-off-by: Calvin Johnson + +commit 262a03c082de5a93efd7f54bec48b39cda9042a8 +Author: Calvin Johnson +Date: Wed Mar 27 13:25:57 2019 +0530 + + staging: fsl_ppfe/eth: adapt to link mode based phydev changes + + Setting link mode bits have changed with the integration of + commit (3c1bcc8 net: ethernet: Convert phydev advertize and + supported from u32 to link mode). Adapt to the new method of + setting and clearing the link mode bits. + + Signed-off-by: Calvin Johnson + +commit 75f911d8ae45215f1c188191da92905ad3f7ad4a +Author: Calvin Johnson +Date: Wed Mar 27 19:31:35 2019 +0530 + + staging: fsl_ppfe/eth: use generic soc_device infra instead of fsl_guts_get_svr() + + Commit ("soc: fsl: guts: make fsl_guts_get_svr() static") has + made fsl_guts_get_svr() static and hence use generic soc_device + infrastructure to check SoC revision. + + Signed-off-by: Calvin Johnson + +commit 0a0ca3d898d15b3d7a206597a68f28134d4dfebd +Author: Calvin Johnson +Date: Tue Mar 26 16:52:22 2019 +0530 + + staging: fsl_ppfe/eth: use memremap() to map RAM area used by PFE + + RAM area used by PFE should be mapped using memremap() instead of + directly traslating physical addr to virtual. This will ensure proper + checks are done before the area is used. + + Signed-off-by: Calvin Johnson + +commit bfc0c2fedb76ad9c888db421b435d51e33fe276a +Author: Li Yang +Date: Tue Jun 11 18:24:37 2019 -0500 + + staging: fsl_ppfe/eth: remove 'fallback' argument from dev->ndo_select_queue() + + To be consistent with upstream API change. + + Signed-off-by: Li Yang + +commit cfd0841983961067efe69379371ddcb49b230dac +Author: Ting Liu +Date: Mon Jun 17 09:27:53 2019 +0200 + + staging: fsl_ppfe/eth: prefix header search paths with $(srctree)/ + + Currently, the rules for configuring search paths in Kbuild have + changed: https://lkml.org/lkml/2019/5/13/37 + + This will lead the below error: + + fatal error: pfe/pfe.h: No such file or directory + + Fix it by adding $(srctree)/ prefix to the search paths. + + Signed-off-by: Ting Liu + +commit 4be722099e4b6bdff2e683234ffaa2dc62fc773d +Author: Calvin Johnson +Date: Wed Nov 1 11:11:30 2017 +0530 + + staging: fsl_ppfe/eth: add pfe support to Kconfig and Makefile + + Signed-off-by: Calvin Johnson + [ Aisheng: fix minor conflict due to removed VBOXSF_FS ] + Signed-off-by: Dong Aisheng + +commit 5a2c9482ec3959dc2010f99897359b9e4006d2a4 +Author: Nagesh Koneti +Date: Wed Sep 25 12:01:19 2019 +0530 + + staging: fsl_ppfe/eth: Disable termination of CRC fwd. + + LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x. + The issue is triggered by the (spec-compliant) operation of the AR803x PHY + on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error + packet by MAC, so for these error packets FCS should be validated and + discard only real error packets in PFE Rx packet path. + + Signed-off-by: Nagesh Koneti + Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”> + +commit 36344cfc28f4cbdf606330ab8929e10d0778a087 +Author: Li Yang +Date: Sun Dec 8 18:19:18 2019 -0600 + + net: ppfe: Cope with of_get_phy_mode() API change + + Signed-off-by: Li Yang + +commit ee2a796cf8990ac06f329c580f18fffefbac6a9a +Author: Anji Jagarlmudi +Date: Wed Jan 8 19:06:12 2020 +0530 + + staging: fsl_ppfe/eth: Enhance error checking in platform probe + + Fix the kernel crash when MAC addr is not passed in dtb. + + Signed-off-by: Anji Jagarlmudi + +commit 2e8ca14ea6cc8d6816f2a445f3610f6b5b852e7c +Author: Anji Jagarlmudi +Date: Mon Apr 6 19:46:05 2020 +0530 + + staging: fsl_ppfe/eth: reject unsupported coalescing params + + Set ethtool_ops->supported_coalesce_params to let + the core reject unsupported coalescing parameters. + + Signed-off-by: Anji Jagarlmudi + +commit 7ce4dd75c94d8a7dbe4e4ad747b4ddc5be6d83b4 +Author: Chaitanya Sakinam +Date: Sat Mar 28 00:30:53 2020 +0530 + + staging: fsl_ppfe/eth:check "reg" property before pfe_get_gemac_if_properties() + + It has been observed that the function pfe_get_gemac_if_properties() is + been called blindly for the next two child nodes. There might be some + cases where it may go wrong and that lead to missing interfaces. + with these changes it is ensured thats not the case. + + Signed-off-by: Chaitanya Sakinam + Signed-off-by: Anji J + +commit 7ba7cfb799c8928f4963f86a1ad47e2dd56022b2 +Author: Chaitanya Sakinam +Date: Sat Mar 28 00:34:13 2020 +0530 + + staging: fsl_ppfe/eth: "struct firmware" dereference is reduced in many functions + + firmware structure's data variable is the actual elf data. It has been + dereferenced in multiple functions and this has been reduced. + + Signed-off-by: Chaitanya Sakinam + Signed-off-by: Anji J + +commit 443538bb09b979fcc98a58e18a3eb8cebe25ad4f +Author: Chaitanya Sakinam +Date: Sun Mar 29 18:05:50 2020 +0530 + + staging: fsl_ppfe/eth: LF-27 load pfe binaries from FDT + + FDT prepared in uboot now has pfe firmware part of it. + These changes will read the firmware by default from it and tries to load + the elf into the PFE PEs. This help build the pfe driver pasrt of kernel. + + Signed-off-by: Chaitanya Sakinam + Signed-off-by: Anji J + +commit 2b1f551c2aee4550ffca5f86031bc4f5e6ccb848 +Author: Chaitanya Sakinam +Date: Tue Jun 9 15:33:42 2020 +0530 + + staging: fsl_ppfe/eth: proper handling for RGMII delay mode + + The correct setting for the RGMII ports on LS1012ARDB is to + enable delay on both Tx and Rx. So the phy mode to be matched + is PHY_INTERFACE_MODE_RGMII_ID. + + Signed-off-by: Chaitanya Sakinam + Signed-off-by: Anji Jagarlmudi + +commit a95d84b87e743bd7c57b287901524f2cffbf38d7 +Author: Dong Aisheng +Date: Wed Jul 15 16:06:24 2020 +0800 + + LF-1762-2 staging: fsl_ppfe: replace '---help---' in Kconfig files with 'help' + + Update Kconfig to cope with upstream change + commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over + '---help---'"). + + Signed-off-by: Dong Aisheng + +commit 546ef027c2b0768517d903429d56bcd89b919e6d +Author: Chaitanya Sakinam +Date: Wed Jul 15 10:36:07 2020 +0530 + + staging: fsl_ppfe/eth: Nesting level does not match indentation + + corrected nesting level + LF-1661 and Coverity CID: 8879316 + + Signed-off-by: Chaitanya Sakinam + +commit c76a95f776e0f3e1a2c8abc1748c662151e29be5 +Author: Chaitanya Sakinam +Date: Wed Jul 15 11:19:57 2020 +0530 + + staging: fsl_ppfe/eth: Initialized scalar variable + + Proper initialization of scalar variable + LF-1657 and Coverity CID: 3335133 + + Signed-off-by: Chaitanya Sakinam + +commit f48286af915f664c15aa327aaf6d9b61d33eea67 +Author: Chaitanya Sakinam +Date: Wed Jul 15 11:47:50 2020 +0530 + + staging: fsl_ppfe/eth: misspelt variable name + + variable name corrected + LF-1656 and Coverity CID: 3335119 + + Signed-off-by: Chaitanya Sakinam + +commit a5e006f71fce8e76831704b31218f3d57c0b9924 +Author: Chaitanya Sakinam +Date: Wed Jul 15 12:10:47 2020 +0530 + + staging: fsl_ppfe/eth: Avoiding out-of-bound writes + + avoid out-of-bound writes with proper error handling + LF-1654, LF-1652 and Coverity CID: 3335106, 3335090 + + Signed-off-by: Chaitanya Sakinam + +commit 957fde83420b6a74a5e96b2f27183274b04211d9 +Author: Chaitanya Sakinam +Date: Wed Jul 15 13:09:35 2020 +0530 + + staging: fsl_ppfe/eth: Initializing scalar variable + + proper initialization of scalar variable. + LF-1653 and Coverity CID: 3335101 + + Signed-off-by: Chaitanya Sakinam + +commit fae95666a4c992b7f9035ee978e3e289495cbd47 +Author: Chaitanya Sakinam +Date: Wed Jul 15 13:45:50 2020 +0530 + + staging: fsl_ppfe/eth: checking return value + + proper checks added and handled for return value. + LF-1644 and Coverity CID: 241888 + + Signed-off-by: Chaitanya Sakinam + +commit 5bf7baddb22ecafd6064c9062a804bcd17a326cc +Author: Chaitanya Sakinam +Date: Wed Jul 15 14:04:10 2020 +0530 + + staging: fsl_ppfe/eth: Avoid out-of-bound access + + proper handling to avoid out-of-bound access + LF-1642, LF-1641 and Coverity CID: 240910, 240891 + + Signed-off-by: Chaitanya Sakinam + +commit b15d480d66277fc00bc610a91af56263733a4e13 +Author: Chaitanya Sakinam +Date: Fri Jul 31 10:19:00 2020 +0530 + + staging: fsl_ppfe/eth: Avoiding out-of-bound writes + + avoid out-of-bound writes with proper error handling + LF-1654, LF-1652 and Coverity CID: 3335106, 3335090 + + Signed-off-by: Chaitanya Sakinam + +commit 188992fc4d4173c6bb36e924b5833bb092f7d602 +Author: Chaitanya Sakinam +Date: Fri Jul 31 10:23:59 2020 +0530 + + staging: fsl_ppfe/eth: return value init in error case + + proper err return in error case. + LF-1806 and Coverity CID: 10468592 + + Signed-off-by: Chaitanya Sakinam + +commit 26d6dd0bd1331dd07764914033fd8e98777fc165 +Author: Chaitanya Sakinam +Date: Thu Aug 13 12:04:48 2020 +0530 + + staging: fsl_ppfe/eth: Avoid recursion in header inclusion + + Avoiding header inclusions that are not necessary and also that are + causing header inclusion recursion. + + LF-2102 and Coverity CID: 240838 + + Signed-off-by: Chaitanya Sakinam + +commit f18618582d078b87c9ee2e93ebbffee44cd76ec0 +Author: Chaitanya Sakinam +Date: Thu Aug 13 12:28:25 2020 +0530 + + staging: fsl_ppfe/eth: Avoiding return value overwrite + + avoid return value overwrite at the end of function. + LF-2136, LF-2137 and Coverity CID: 8879341, 8879364 + + Signed-off-by: Chaitanya Sakinam + +commit 4cd4e5f325516d91c630311af4d36472ce19124e +Author: Chaitanya Sakinam +Date: Wed Sep 9 17:50:10 2020 +0530 + + staging: fsl_ppfe/eth: LF-27 enabling PFE firmware load from FDT + + The macro, "LOAD_PFEFIRMWARE_FROM_FILESYSTEM" is been disabled to load + the firmware from FDT by default. Enabling the macro will load the + firmware from filesystem. + + Also, the Makefile is now tuned to build pfe as per the config option + + Signed-off-by: Chaitanya Sakinam + +commit 175a310323ccfab0025f2da56799bb3939b65c9d +Author: Chaitanya Sakinam +Date: Thu Apr 9 18:17:48 2020 +0530 + + staging: fsl_ppfe/eth: Ethtool stats correction for IEEE_rx_drop counter + + Due to carrier extended bug the phy counter IEEE_rx_drop counter is + incremented some times and phy reports the packet has crc error. + Because of this PFE revalidates all the packets that are marked crc + error by phy. Now, the counter phy reports is till bogus and this + patch decrements the counter by pfe revalidated (and are crc ok) + counter amount. + + Signed-off-by: Chaitanya Sakinam + +commit a4683911f7a7d71762a90dabf72faadab5766774 +Author: Chaitanya Sakinam +Date: Wed Sep 30 17:20:19 2020 +0530 + + staging: fsl_ppfe/eth: PFE firmware load enhancements + + PFE driver enhancements to load the PE firmware from filesystem + when the firmware is not found in FDT. + + Signed-off-by: Chaitanya Sakinam +--- + .../devicetree/bindings/net/fsl_ppfe/pfe.txt | 199 ++ + MAINTAINERS | 8 + + drivers/staging/Kconfig | 2 + + drivers/staging/Makefile | 1 + + drivers/staging/fsl_ppfe/Kconfig | 21 + + drivers/staging/fsl_ppfe/Makefile | 20 + + drivers/staging/fsl_ppfe/TODO | 2 + + drivers/staging/fsl_ppfe/include/pfe/cbus.h | 78 + + .../staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 + + .../fsl_ppfe/include/pfe/cbus/class_csr.h | 289 ++ + .../fsl_ppfe/include/pfe/cbus/emac_mtip.h | 242 ++ + .../staging/fsl_ppfe/include/pfe/cbus/gpi.h | 86 + + .../staging/fsl_ppfe/include/pfe/cbus/hif.h | 100 + + .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 50 + + .../fsl_ppfe/include/pfe/cbus/tmu_csr.h | 168 ++ + .../fsl_ppfe/include/pfe/cbus/util_csr.h | 61 + + drivers/staging/fsl_ppfe/include/pfe/pfe.h | 372 +++ + drivers/staging/fsl_ppfe/pfe_cdev.c | 258 ++ + drivers/staging/fsl_ppfe/pfe_cdev.h | 41 + + drivers/staging/fsl_ppfe/pfe_ctrl.c | 226 ++ + drivers/staging/fsl_ppfe/pfe_ctrl.h | 100 + + drivers/staging/fsl_ppfe/pfe_debugfs.c | 99 + + drivers/staging/fsl_ppfe/pfe_debugfs.h | 13 + + drivers/staging/fsl_ppfe/pfe_eth.c | 2587 +++++++++++++++++ + drivers/staging/fsl_ppfe/pfe_eth.h | 175 ++ + drivers/staging/fsl_ppfe/pfe_firmware.c | 398 +++ + drivers/staging/fsl_ppfe/pfe_firmware.h | 21 + + drivers/staging/fsl_ppfe/pfe_hal.c | 1517 ++++++++++ + drivers/staging/fsl_ppfe/pfe_hif.c | 1064 +++++++ + drivers/staging/fsl_ppfe/pfe_hif.h | 199 ++ + drivers/staging/fsl_ppfe/pfe_hif_lib.c | 628 ++++ + drivers/staging/fsl_ppfe/pfe_hif_lib.h | 229 ++ + drivers/staging/fsl_ppfe/pfe_hw.c | 164 ++ + drivers/staging/fsl_ppfe/pfe_hw.h | 15 + + .../staging/fsl_ppfe/pfe_ls1012a_platform.c | 383 +++ + drivers/staging/fsl_ppfe/pfe_mod.c | 158 + + drivers/staging/fsl_ppfe/pfe_mod.h | 103 + + drivers/staging/fsl_ppfe/pfe_perfmon.h | 26 + + drivers/staging/fsl_ppfe/pfe_sysfs.c | 840 ++++++ + drivers/staging/fsl_ppfe/pfe_sysfs.h | 17 + + 40 files changed, 11015 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt + create mode 100644 drivers/staging/fsl_ppfe/Kconfig + create mode 100644 drivers/staging/fsl_ppfe/Makefile + create mode 100644 drivers/staging/fsl_ppfe/TODO + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h + create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h + create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c + create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt +@@ -0,0 +1,199 @@ ++============================================================================= ++NXP Programmable Packet Forwarding Engine Device Bindings ++ ++CONTENTS ++ - PFE Node ++ - Ethernet Node ++ ++============================================================================= ++PFE Node ++ ++DESCRIPTION ++ ++PFE Node has all the properties associated with Packet Forwarding Engine block. ++ ++PROPERTIES ++ ++- compatible ++ Usage: required ++ Value type: ++ Definition: Must include "fsl,pfe" ++ ++- reg ++ Usage: required ++ Value type: ++ Definition: A standard property. ++ Specifies the offset of the following registers: ++ - PFE configuration registers ++ - DDR memory used by PFE ++ ++- fsl,pfe-num-interfaces ++ Usage: required ++ Value type: ++ Definition: Must be present. Value can be either one or two. ++ ++- interrupts ++ Usage: required ++ Value type: ++ Definition: Three interrupts are specified in this property. ++ - HIF interrupt ++ - HIF NO COPY interrupt ++ - Wake On LAN interrupt ++ ++- interrupt-names ++ Usage: required ++ Value type: ++ Definition: Following strings are defined for the 3 interrupts. ++ "pfe_hif" - HIF interrupt ++ "pfe_hif_nocpy" - HIF NO COPY interrupt ++ "pfe_wol" - Wake On LAN interrupt ++ ++- memory-region ++ Usage: required ++ Value type: ++ Definition: phandle to a node describing reserved memory used by pfe. ++ Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt ++ ++- fsl,pfe-scfg ++ Usage: required ++ Value type: ++ Definition: phandle for scfg. ++ ++- fsl,rcpm-wakeup ++ Usage: required ++ Value type: ++ Definition: phandle for rcpm. ++ ++- clocks ++ Usage: required ++ Value type: ++ Definition: phandle for clockgen. ++ ++- clock-names ++ Usage: required ++ Value type: ++ Definition: phandle for clock name. ++ ++EXAMPLE ++ ++pfe: pfe@04000000 { ++ compatible = "fsl,pfe"; ++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ ++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ ++ reg-names = "pfe", "pfe-ddr"; ++ fsl,pfe-num-interfaces = <0x2>; ++ interrupts = <0 172 0x4>, /* HIF interrupt */ ++ <0 173 0x4>, /*HIF_NOCPY interrupt */ ++ <0 174 0x4>; /* WoL interrupt */ ++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; ++ memory-region = <&pfe_reserved>; ++ fsl,pfe-scfg = <&scfg 0>; ++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; ++ clocks = <&clockgen 4 0>; ++ clock-names = "pfe"; ++ ++ status = "okay"; ++ pfe_mac0: ethernet@0 { ++ }; ++ ++ pfe_mac1: ethernet@1 { ++ }; ++}; ++ ++============================================================================= ++Ethernet Node ++ ++DESCRIPTION ++ ++Ethernet Node has all the properties associated with PFE used by platforms to ++connect to PHY: ++ ++PROPERTIES ++ ++- compatible ++ Usage: required ++ Value type: ++ Definition: Must include "fsl,pfe-gemac-port" ++ ++- reg ++ Usage: required ++ Value type: ++ Definition: A standard property. ++ Specifies the gemacid of the interface. ++ ++- fsl,gemac-bus-id ++ Usage: required ++ Value type: ++ Definition: Must be present. Value should be the id of the bus ++ connected to gemac. ++ ++- fsl,gemac-phy-id (deprecated binding) ++ Usage: required ++ Value type: ++ Definition: This binding shouldn't be used with new platforms. ++ Must be present. Value should be the id of the phy ++ connected to gemac. ++ ++- fsl,mdio-mux-val ++ Usage: required ++ Value type: ++ Definition: Must be present. Value can be either 0 or 2 or 3. ++ This value is used to configure the mux to enable mdio. ++ ++- phy-mode ++ Usage: required ++ Value type: ++ Definition: Must include "sgmii" ++ ++- fsl,pfe-phy-if-flags (deprecated binding) ++ Usage: required ++ Value type: ++ Definition: This binding shouldn't be used with new platforms. ++ Must be present. Value should be 0 by default. ++ If there is not phy connected, this need to be 1. ++ ++- phy-handle ++ Usage: optional ++ Value type: ++ Definition: phandle to the PHY device connected to this device. ++ ++- mdio : A required subnode which specifies the mdio bus in the PFE and used as ++a container for phy nodes according to ../phy.txt. ++ ++EXAMPLE ++ ++ethernet@0 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ phy-handle = <&sgmii_phy1>; ++}; ++ ++ ++ethernet@1 { ++ compatible = "fsl,pfe-gemac-port"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x1>; /* GEM_ID */ ++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ ++ fsl,mdio-mux-val = <0x0>; ++ phy-mode = "sgmii"; ++ phy-handle = <&sgmii_phy2>; ++}; ++ ++mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sgmii_phy1: ethernet-phy@2 { ++ reg = <0x2>; ++ }; ++ ++ sgmii_phy2: ethernet-phy@1 { ++ reg = <0x1>; ++ }; ++}; +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -7068,6 +7068,14 @@ F: drivers/ptp/ptp_qoriq.c + F: drivers/ptp/ptp_qoriq_debugfs.c + F: include/linux/fsl/ptp_qoriq.h + ++FREESCALE QORIQ PPFE ETHERNET DRIVER ++M: Anji Jagarlmudi ++M: Calvin Johnson ++L: netdev@vger.kernel.org ++S: Maintained ++F: drivers/staging/fsl_ppfe ++F: Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt ++ + FREESCALE QUAD SPI DRIVER + M: Han Xu + L: linux-spi@vger.kernel.org +--- a/drivers/staging/Kconfig ++++ b/drivers/staging/Kconfig +@@ -118,4 +118,6 @@ source "drivers/staging/wfx/Kconfig" + + source "drivers/staging/hikey9xx/Kconfig" + ++source "drivers/staging/fsl_ppfe/Kconfig" ++ + endif # STAGING +--- a/drivers/staging/Makefile ++++ b/drivers/staging/Makefile +@@ -49,3 +49,4 @@ obj-$(CONFIG_KPC2000) += kpc2000/ + obj-$(CONFIG_QLGE) += qlge/ + obj-$(CONFIG_WFX) += wfx/ + obj-y += hikey9xx/ ++obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/Kconfig +@@ -0,0 +1,21 @@ ++# ++# Freescale Programmable Packet Forwarding Engine driver ++# ++config FSL_PPFE ++ tristate "Freescale PPFE Driver" ++ select FSL_GUTS ++ default n ++ help ++ Freescale LS1012A SoC has a Programmable Packet Forwarding Engine. ++ It provides two high performance ethernet interfaces. ++ This driver initializes, programs and controls the PPFE. ++ Use this driver to enable network connectivity on LS1012A platforms. ++ ++if FSL_PPFE ++ ++config FSL_PPFE_UTIL_DISABLED ++ bool "Disable PPFE UTIL Processor Engine" ++ help ++ UTIL PE has to be enabled only if required. ++ ++endif # FSL_PPFE +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for Freesecale PPFE driver ++# ++ ++ccflags-y += -I $(srctree)/$(src)/include -I $(srctree)/$(src) ++ ++obj-$(CONFIG_FSL_PPFE) += pfe.o ++ ++pfe-y += pfe_mod.o \ ++ pfe_hw.o \ ++ pfe_firmware.o \ ++ pfe_ctrl.o \ ++ pfe_hif.o \ ++ pfe_hif_lib.o\ ++ pfe_eth.o \ ++ pfe_sysfs.o \ ++ pfe_debugfs.o \ ++ pfe_ls1012a_platform.o \ ++ pfe_hal.o \ ++ pfe_cdev.o +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/TODO +@@ -0,0 +1,2 @@ ++TODO: ++ - provide pfe pe monitoring support +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h +@@ -0,0 +1,78 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _CBUS_H_ ++#define _CBUS_H_ ++ ++#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) ++#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) ++#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) ++#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) ++#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) ++#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) ++#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) ++#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) ++#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) ++#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) ++#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) ++#define LMEM_SIZE 0x10000 ++#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) ++#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) ++#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) ++#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) ++#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) ++#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) ++ ++/* ++ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR ++ * XXX_MEM_ACCESS_ADDR register bit definitions. ++ */ ++#define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */ ++#define PE_MEM_ACCESS_IMEM BIT(15) ++#define PE_MEM_ACCESS_DMEM BIT(16) ++ ++/* Byte Enables of the Internal memory access. These are interpred in BE */ ++#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \ ++ ({ typeof(size) size_ = (size); \ ++ (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; }) ++ ++#include "cbus/emac_mtip.h" ++#include "cbus/gpi.h" ++#include "cbus/bmu.h" ++#include "cbus/hif.h" ++#include "cbus/tmu_csr.h" ++#include "cbus/class_csr.h" ++#include "cbus/hif_nocpy.h" ++#include "cbus/util_csr.h" ++ ++/* PFE cores states */ ++#define CORE_DISABLE 0x00000000 ++#define CORE_ENABLE 0x00000001 ++#define CORE_SW_RESET 0x00000002 ++ ++/* LMEM defines */ ++#define LMEM_HDR_SIZE 0x0010 ++#define LMEM_BUF_SIZE_LN2 0x7 ++#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) ++ ++/* DDR defines */ ++#define DDR_HDR_SIZE 0x0100 ++#define DDR_BUF_SIZE_LN2 0xb ++#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) ++ ++#endif /* _CBUS_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _BMU_H_ ++#define _BMU_H_ ++ ++#define BMU_VERSION 0x000 ++#define BMU_CTRL 0x004 ++#define BMU_UCAST_CONFIG 0x008 ++#define BMU_UCAST_BASE_ADDR 0x00c ++#define BMU_BUF_SIZE 0x010 ++#define BMU_BUF_CNT 0x014 ++#define BMU_THRES 0x018 ++#define BMU_INT_SRC 0x020 ++#define BMU_INT_ENABLE 0x024 ++#define BMU_ALLOC_CTRL 0x030 ++#define BMU_FREE_CTRL 0x034 ++#define BMU_FREE_ERR_ADDR 0x038 ++#define BMU_CURR_BUF_CNT 0x03c ++#define BMU_MCAST_CNT 0x040 ++#define BMU_MCAST_ALLOC_CTRL 0x044 ++#define BMU_REM_BUF_CNT 0x048 ++#define BMU_LOW_WATERMARK 0x050 ++#define BMU_HIGH_WATERMARK 0x054 ++#define BMU_INT_MEM_ACCESS 0x100 ++ ++struct BMU_CFG { ++ unsigned long baseaddr; ++ u32 count; ++ u32 size; ++ u32 low_watermark; ++ u32 high_watermark; ++}; ++ ++#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2 ++#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2 ++ ++#define BMU2_MCAST_ALLOC_CTRL (BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL) ++ ++#endif /* _BMU_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h +@@ -0,0 +1,289 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _CLASS_CSR_H_ ++#define _CLASS_CSR_H_ ++ ++/* @file class_csr.h. ++ * class_csr - block containing all the classifier control and status register. ++ * Mapped on CBUS and accessible from all PE's and ARM. ++ */ ++#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000) ++#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004) ++#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010) ++ ++/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */ ++#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) ++ ++/* LMEM header size for the Classifier block.\ Data in the LMEM ++ * is written from this offset. ++ */ ++#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) ++ ++/* DDR header size for the Classifier block.\ Data in the DDR ++ * is written from this offset. ++ */ ++#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) ++ ++#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) ++ ++/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */ ++#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) ++ ++/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */ ++#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) ++ ++/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */ ++#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) ++ ++/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */ ++ ++/* @name Class PE memory access. Allows external PE's and HOST to ++ * read/write PMEM/DMEM memory ranges for each classifier PE. ++ */ ++/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, ++ * See \ref XXX_MEM_ACCESS_ADDR for details. ++ */ ++#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) ++ ++/* Internal Memory Access Write Data [31:0] */ ++#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) ++ ++/* Internal Memory Access Read Data [31:0] */ ++#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) ++#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114) ++#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118) ++ ++#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c) ++#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120) ++#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124) ++#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128) ++#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c) ++#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130) ++#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134) ++#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138) ++#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c) ++#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140) ++#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144) ++#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148) ++#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c) ++#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150) ++#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154) ++#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158) ++#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c) ++#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160) ++#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164) ++#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168) ++#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c) ++#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170) ++#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174) ++#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178) ++#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c) ++#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180) ++#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184) ++#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188) ++#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c) ++#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190) ++#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194) ++#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198) ++#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c) ++#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0) ++#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4) ++#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8) ++#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac) ++#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0) ++#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4) ++#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8) ++#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc) ++#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0) ++#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4) ++#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8) ++#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc) ++#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0) ++#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4) ++#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8) ++#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc) ++#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0) ++#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4) ++#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8) ++#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec) ++#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0) ++#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4) ++#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8) ++ ++#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200) ++#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204) ++#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208) ++#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c) ++#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210) ++#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214) ++#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218) ++#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c) ++#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220) ++#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224) ++ ++#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228) ++ ++#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c) ++#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230) ++ ++/* (route_entry_size[9:0], route_hash_size[23:16] ++ * (this is actually ln2(size))) ++ */ ++#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) ++ ++#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff) ++#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16) ++ ++#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238) ++ ++#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c) ++#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240) ++#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244) ++#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248) ++#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c) ++#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250) ++#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254) ++ ++#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258) ++#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) ++/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */ ++ ++#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c) ++ ++#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260) ++#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264) ++#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268) ++#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c) ++#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270) ++#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274) ++#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278) ++#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c) ++#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280) ++#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284) ++#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288) ++#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c) ++ ++#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290) ++#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294) ++ ++#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298) ++#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c) ++ ++#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0) ++ ++#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4) ++#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8) ++#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac) ++#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0) ++#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4) ++#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8) ++ ++#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc) ++ ++/* CLASS defines */ ++#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */ ++#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */ ++ ++/* Can be configured */ ++#define CLASS_PBUF0_BASE_ADDR 0x000 ++/* Can be configured */ ++#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) ++/* Can be configured */ ++#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) ++/* Can be configured */ ++#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) ++ ++#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + \ ++ CLASS_PBUF_HEADER_OFFSET) ++ ++#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | \ ++ CLASS_PBUF0_BASE_ADDR) ++#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | \ ++ CLASS_PBUF2_BASE_ADDR) ++ ++#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\ ++ CLASS_PBUF0_HEADER_BASE_ADDR) ++#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\ ++ CLASS_PBUF2_HEADER_BASE_ADDR) ++ ++#define CLASS_ROUTE_SIZE 128 ++#define CLASS_MAX_ROUTE_SIZE 256 ++#define CLASS_ROUTE_HASH_BITS 20 ++#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1) ++ ++/* Can be configured */ ++#define CLASS_ROUTE0_BASE_ADDR 0x400 ++/* Can be configured */ ++#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) ++/* Can be configured */ ++#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) ++/* Can be configured */ ++#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) ++ ++#define CLASS_SA_SIZE 128 ++#define CLASS_IPSEC_SA0_BASE_ADDR 0x600 ++/* not used */ ++#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE) ++/* not used */ ++#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE) ++/* not used */ ++#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE) ++ ++/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */ ++#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE * 4) - \ ++ (CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE)) ++#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \ ++ CLASS_SA_SIZE)) ++ ++#define TWO_LEVEL_ROUTE BIT(0) ++#define PHYNO_IN_HASH BIT(1) ++#define HW_ROUTE_FETCH BIT(3) ++#define HW_BRIDGE_FETCH BIT(5) ++#define IP_ALIGNED BIT(6) ++#define ARC_HIT_CHECK_EN BIT(7) ++#define CLASS_TOE BIT(11) ++#define HASH_NORMAL (0 << 12) ++#define HASH_CRC_PORT BIT(12) ++#define HASH_CRC_IP (2 << 12) ++#define HASH_CRC_PORT_IP (3 << 12) ++#define QB2BUS_LE BIT(15) ++ ++#define TCP_CHKSUM_DROP BIT(0) ++#define UDP_CHKSUM_DROP BIT(1) ++#define IPV4_CHKSUM_DROP BIT(9) ++ ++/*CLASS_HIF_PARSE bits*/ ++#define HIF_PKT_CLASS_EN BIT(0) ++#define HIF_PKT_OFFSET(ofst) (((ofst) & 0xF) << 1) ++ ++struct class_cfg { ++ u32 toe_mode; ++ unsigned long route_table_baseaddr; ++ u32 route_table_hash_bits; ++ u32 pe_sys_clk_ratio; ++ u32 resume; ++}; ++ ++#endif /* _CLASS_CSR_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h +@@ -0,0 +1,242 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _EMAC_H_ ++#define _EMAC_H_ ++ ++#include ++ ++#define EMAC_IEVENT_REG 0x004 ++#define EMAC_IMASK_REG 0x008 ++#define EMAC_R_DES_ACTIVE_REG 0x010 ++#define EMAC_X_DES_ACTIVE_REG 0x014 ++#define EMAC_ECNTRL_REG 0x024 ++#define EMAC_MII_DATA_REG 0x040 ++#define EMAC_MII_CTRL_REG 0x044 ++#define EMAC_MIB_CTRL_STS_REG 0x064 ++#define EMAC_RCNTRL_REG 0x084 ++#define EMAC_TCNTRL_REG 0x0C4 ++#define EMAC_PHY_ADDR_LOW 0x0E4 ++#define EMAC_PHY_ADDR_HIGH 0x0E8 ++#define EMAC_GAUR 0x120 ++#define EMAC_GALR 0x124 ++#define EMAC_TFWR_STR_FWD 0x144 ++#define EMAC_RX_SECTION_FULL 0x190 ++#define EMAC_RX_SECTION_EMPTY 0x194 ++#define EMAC_TX_SECTION_EMPTY 0x1A0 ++#define EMAC_TRUNC_FL 0x1B0 ++ ++#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ ++#define RMON_T_PACKETS 0x204 /* RMON TX packet count */ ++#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ ++#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ ++#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ ++#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ ++#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ ++#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ ++#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ ++#define RMON_T_COL 0x224 /* RMON TX collision count */ ++#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ ++#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ ++#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ ++#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ ++#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ ++#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ ++#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ ++#define RMON_T_OCTETS 0x244 /* RMON TX octets */ ++#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ ++#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ ++#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ ++#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ ++#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ ++#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ ++#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ ++#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ ++#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ ++#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ ++#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ ++#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ ++#define RMON_R_PACKETS 0x284 /* RMON RX packet count */ ++#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ ++#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ ++#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ ++#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ ++#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ ++#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ ++#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ ++#define RMON_R_RESVD_O 0x2a4 /* Reserved */ ++#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ ++#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ ++#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ ++#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ ++#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ ++#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ ++#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ ++#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ ++#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ ++#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ ++#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ ++#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ ++#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ ++#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ ++#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ ++ ++#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/ ++#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/ ++ ++/* GEMAC definitions and settings */ ++ ++#define EMAC_PORT_0 0 ++#define EMAC_PORT_1 1 ++ ++/* GEMAC Bit definitions */ ++#define EMAC_IEVENT_HBERR 0x80000000 ++#define EMAC_IEVENT_BABR 0x40000000 ++#define EMAC_IEVENT_BABT 0x20000000 ++#define EMAC_IEVENT_GRA 0x10000000 ++#define EMAC_IEVENT_TXF 0x08000000 ++#define EMAC_IEVENT_TXB 0x04000000 ++#define EMAC_IEVENT_RXF 0x02000000 ++#define EMAC_IEVENT_RXB 0x01000000 ++#define EMAC_IEVENT_MII 0x00800000 ++#define EMAC_IEVENT_EBERR 0x00400000 ++#define EMAC_IEVENT_LC 0x00200000 ++#define EMAC_IEVENT_RL 0x00100000 ++#define EMAC_IEVENT_UN 0x00080000 ++ ++#define EMAC_IMASK_HBERR 0x80000000 ++#define EMAC_IMASK_BABR 0x40000000 ++#define EMAC_IMASKT_BABT 0x20000000 ++#define EMAC_IMASK_GRA 0x10000000 ++#define EMAC_IMASKT_TXF 0x08000000 ++#define EMAC_IMASK_TXB 0x04000000 ++#define EMAC_IMASKT_RXF 0x02000000 ++#define EMAC_IMASK_RXB 0x01000000 ++#define EMAC_IMASK_MII 0x00800000 ++#define EMAC_IMASK_EBERR 0x00400000 ++#define EMAC_IMASK_LC 0x00200000 ++#define EMAC_IMASKT_RL 0x00100000 ++#define EMAC_IMASK_UN 0x00080000 ++ ++#define EMAC_RCNTRL_MAX_FL_SHIFT 16 ++#define EMAC_RCNTRL_LOOP 0x00000001 ++#define EMAC_RCNTRL_DRT 0x00000002 ++#define EMAC_RCNTRL_MII_MODE 0x00000004 ++#define EMAC_RCNTRL_PROM 0x00000008 ++#define EMAC_RCNTRL_BC_REJ 0x00000010 ++#define EMAC_RCNTRL_FCE 0x00000020 ++#define EMAC_RCNTRL_RGMII 0x00000040 ++#define EMAC_RCNTRL_SGMII 0x00000080 ++#define EMAC_RCNTRL_RMII 0x00000100 ++#define EMAC_RCNTRL_RMII_10T 0x00000200 ++#define EMAC_RCNTRL_CRC_FWD 0x00004000 ++ ++#define EMAC_TCNTRL_GTS 0x00000001 ++#define EMAC_TCNTRL_HBC 0x00000002 ++#define EMAC_TCNTRL_FDEN 0x00000004 ++#define EMAC_TCNTRL_TFC_PAUSE 0x00000008 ++#define EMAC_TCNTRL_RFC_PAUSE 0x00000010 ++ ++#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */ ++#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */ ++#define EMAC_ECNTRL_MAGIC_ENA 0x00000004 ++#define EMAC_ECNTRL_SLEEP 0x00000008 ++#define EMAC_ECNTRL_SPEED 0x00000020 ++#define EMAC_ECNTRL_DBSWAP 0x00000100 ++ ++#define EMAC_X_WMRK_STRFWD 0x00000100 ++ ++#define EMAC_X_DES_ACTIVE_TDAR 0x01000000 ++#define EMAC_R_DES_ACTIVE_RDAR 0x01000000 ++ ++#define EMAC_RX_SECTION_EMPTY_V 0x00010006 ++/* ++ * The possible operating speeds of the MAC, currently supporting 10, 100 and ++ * 1000Mb modes. ++ */ ++enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS}; ++ ++/* MII-related definitios */ ++#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ ++#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ ++#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */ ++#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ ++#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */ ++#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ ++#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ ++#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */ ++#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ ++ ++#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ ++#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */ ++#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ ++#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */ ++ ++#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \ ++ EMAC_MII_DATA_RA_SHIFT) ++#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \ ++ EMAC_MII_DATA_PA_SHIFT) ++#define EMAC_MII_DATA(v) ((v) & 0xffff) ++ ++#define EMAC_MII_SPEED_SHIFT 1 ++#define EMAC_HOLDTIME_SHIFT 8 ++#define EMAC_HOLDTIME_MASK 0x7 ++#define EMAC_HOLDTIME(v) (((v) & EMAC_HOLDTIME_MASK) << \ ++ EMAC_HOLDTIME_SHIFT) ++ ++/* ++ * The Address organisation for the MAC device. All addresses are split into ++ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of ++ * the address and the other field are the high order bits - this may be 16-bits ++ * in the case of MAC addresses, or 32-bits for the hash address. ++ * In terms of memory storage, the first item (bottom) is assumed to be at a ++ * lower address location than 'top'. i.e. top should be at address location of ++ * 'bottom' + 4 bytes. ++ */ ++struct pfe_mac_addr { ++ u32 bottom; /* Lower 32-bits of address. */ ++ u32 top; /* Upper 32-bits of address. */ ++}; ++ ++/* ++ * The following is the organisation of the address filters section of the MAC ++ * registers. The Cadence MAC contains four possible specific address match ++ * addresses, if an incoming frame corresponds to any one of these four ++ * addresses then the frame will be copied to memory. ++ * It is not necessary for all four of the address match registers to be ++ * programmed, this is application dependent. ++ */ ++struct spec_addr { ++ struct pfe_mac_addr one; /* Specific address register 1. */ ++ struct pfe_mac_addr two; /* Specific address register 2. */ ++ struct pfe_mac_addr three; /* Specific address register 3. */ ++ struct pfe_mac_addr four; /* Specific address register 4. */ ++}; ++ ++struct gemac_cfg { ++ u32 mode; ++ u32 speed; ++ u32 duplex; ++}; ++ ++/* EMAC Hash size */ ++#define EMAC_HASH_REG_BITS 64 ++ ++#define EMAC_SPEC_ADDR_MAX 4 ++ ++#endif /* _EMAC_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h +@@ -0,0 +1,86 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _GPI_H_ ++#define _GPI_H_ ++ ++#define GPI_VERSION 0x00 ++#define GPI_CTRL 0x04 ++#define GPI_RX_CONFIG 0x08 ++#define GPI_HDR_SIZE 0x0c ++#define GPI_BUF_SIZE 0x10 ++#define GPI_LMEM_ALLOC_ADDR 0x14 ++#define GPI_LMEM_FREE_ADDR 0x18 ++#define GPI_DDR_ALLOC_ADDR 0x1c ++#define GPI_DDR_FREE_ADDR 0x20 ++#define GPI_CLASS_ADDR 0x24 ++#define GPI_DRX_FIFO 0x28 ++#define GPI_TRX_FIFO 0x2c ++#define GPI_INQ_PKTPTR 0x30 ++#define GPI_DDR_DATA_OFFSET 0x34 ++#define GPI_LMEM_DATA_OFFSET 0x38 ++#define GPI_TMLF_TX 0x4c ++#define GPI_DTX_ASEQ 0x50 ++#define GPI_FIFO_STATUS 0x54 ++#define GPI_FIFO_DEBUG 0x58 ++#define GPI_TX_PAUSE_TIME 0x5c ++#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60 ++#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64 ++#define GPI_TOE_CHKSUM_EN 0x68 ++#define GPI_OVERRUN_DROPCNT 0x6c ++#define GPI_CSR_MTIP_PAUSE_REG 0x74 ++#define GPI_CSR_MTIP_PAUSE_QUANTUM 0x78 ++#define GPI_CSR_RX_CNT 0x7c ++#define GPI_CSR_TX_CNT 0x80 ++#define GPI_CSR_DEBUG1 0x84 ++#define GPI_CSR_DEBUG2 0x88 ++ ++struct gpi_cfg { ++ u32 lmem_rtry_cnt; ++ u32 tmlf_txthres; ++ u32 aseq_len; ++ u32 mtip_pause_reg; ++}; ++ ++/* GPI commons defines */ ++#define GPI_LMEM_BUF_EN 0x1 ++#define GPI_DDR_BUF_EN 0x1 ++ ++/* EGPI 1 defines */ ++#define EGPI1_LMEM_RTRY_CNT 0x40 ++#define EGPI1_TMLF_TXTHRES 0xBC ++#define EGPI1_ASEQ_LEN 0x50 ++ ++/* EGPI 2 defines */ ++#define EGPI2_LMEM_RTRY_CNT 0x40 ++#define EGPI2_TMLF_TXTHRES 0xBC ++#define EGPI2_ASEQ_LEN 0x40 ++ ++/* EGPI 3 defines */ ++#define EGPI3_LMEM_RTRY_CNT 0x40 ++#define EGPI3_TMLF_TXTHRES 0xBC ++#define EGPI3_ASEQ_LEN 0x40 ++ ++/* HGPI defines */ ++#define HGPI_LMEM_RTRY_CNT 0x40 ++#define HGPI_TMLF_TXTHRES 0xBC ++#define HGPI_ASEQ_LEN 0x40 ++ ++#define EGPI_PAUSE_TIME 0x000007D0 ++#define EGPI_PAUSE_ENABLE 0x40000000 ++#endif /* _GPI_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h +@@ -0,0 +1,100 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _HIF_H_ ++#define _HIF_H_ ++ ++/* @file hif.h. ++ * hif - PFE hif block control and status register. ++ * Mapped on CBUS and accessible from all PE's and ARM. ++ */ ++#define HIF_VERSION (HIF_BASE_ADDR + 0x00) ++#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04) ++#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08) ++#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c) ++#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10) ++#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14) ++#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20) ++#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24) ++#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30) ++#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34) ++#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38) ++#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c) ++#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40) ++#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44) ++#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48) ++#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c) ++#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50) ++ ++/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */ ++#define HIF_INT BIT(0) ++#define HIF_RXBD_INT BIT(1) ++#define HIF_RXPKT_INT BIT(2) ++#define HIF_TXBD_INT BIT(3) ++#define HIF_TXPKT_INT BIT(4) ++ ++/* HIF_TX_CTRL bits */ ++#define HIF_CTRL_DMA_EN BIT(0) ++#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1) ++#define HIF_CTRL_BDP_CH_START_WSTB BIT(2) ++ ++/* HIF_RX_STATUS bits */ ++#define BDP_CSR_RX_DMA_ACTV BIT(16) ++ ++/* HIF_INT_ENABLE bits */ ++#define HIF_INT_EN BIT(0) ++#define HIF_RXBD_INT_EN BIT(1) ++#define HIF_RXPKT_INT_EN BIT(2) ++#define HIF_TXBD_INT_EN BIT(3) ++#define HIF_TXPKT_INT_EN BIT(4) ++ ++/* HIF_POLL_CTRL bits*/ ++#define HIF_RX_POLL_CTRL_CYCLE 0x0400 ++#define HIF_TX_POLL_CTRL_CYCLE 0x0400 ++ ++/* HIF_INT_COAL bits*/ ++#define HIF_INT_COAL_ENABLE BIT(31) ++ ++/* Buffer descriptor control bits */ ++#define BD_CTRL_BUFLEN_MASK 0x3fff ++#define BD_BUF_LEN(x) ((x) & BD_CTRL_BUFLEN_MASK) ++#define BD_CTRL_CBD_INT_EN BIT(16) ++#define BD_CTRL_PKT_INT_EN BIT(17) ++#define BD_CTRL_LIFM BIT(18) ++#define BD_CTRL_LAST_BD BIT(19) ++#define BD_CTRL_DIR BIT(20) ++#define BD_CTRL_LMEM_CPY BIT(21) /* Valid only for HIF_NOCPY */ ++#define BD_CTRL_PKT_XFER BIT(24) ++#define BD_CTRL_DESC_EN BIT(31) ++#define BD_CTRL_PARSE_DISABLE BIT(25) ++#define BD_CTRL_BRFETCH_DISABLE BIT(26) ++#define BD_CTRL_RTFETCH_DISABLE BIT(27) ++ ++/* Buffer descriptor status bits*/ ++#define BD_STATUS_CONN_ID(x) ((x) & 0xffff) ++#define BD_STATUS_DIR_PROC_ID BIT(16) ++#define BD_STATUS_CONN_ID_EN BIT(17) ++#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18) ++#define BD_STATUS_LE_DATA BIT(21) ++#define BD_STATUS_CHKSUM_EN BIT(22) ++ ++/* HIF Buffer descriptor status bits */ ++#define DIR_PROC_ID BIT(16) ++#define PROC_ID(id) ((id) << 18) ++ ++#endif /* _HIF_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h +@@ -0,0 +1,50 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _HIF_NOCPY_H_ ++#define _HIF_NOCPY_H_ ++ ++#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00) ++#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04) ++#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08) ++#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c) ++#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10) ++#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14) ++#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20) ++#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24) ++#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30) ++#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34) ++#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38) ++#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c) ++#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40) ++#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44) ++#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48) ++#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c) ++#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50) ++#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54) ++#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60) ++#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64) ++#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68) ++#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70) ++#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74) ++#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c) ++#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80) ++#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84) ++#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90) ++ ++#endif /* _HIF_NOCPY_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h +@@ -0,0 +1,168 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _TMU_CSR_H_ ++#define _TMU_CSR_H_ ++ ++#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000) ++#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004) ++#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008) ++#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c) ++#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010) ++#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014) ++#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018) ++#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c) ++#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020) ++#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024) ++#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028) ++#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c) ++#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030) ++#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034) ++#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038) ++#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c) ++#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040) ++#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044) ++#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048) ++#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c) ++#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050) ++#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054) ++#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058) ++#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c) ++#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060) ++#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064) ++#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068) ++#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c) ++#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070) ++#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074) ++#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078) ++#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c) ++#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080) ++#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084) ++#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088) ++#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c) ++#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090) ++#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094) ++#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098) ++#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c) ++#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0) ++#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4) ++#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8) ++#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac) ++#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0) ++#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY0 ++ */ ++#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8) ++ ++#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc) ++#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0) ++#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4) ++#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8) ++#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc) ++#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0) ++#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4) ++#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8) ++#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc) ++#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0) ++ ++/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory ++ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of ++ * the internal memory. This address is used to access both the PM and DM of ++ * all the PE's ++ */ ++#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4) ++ ++/* Internal Memory Access Write Data */ ++#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8) ++/* Internal Memory Access Read Data. The commands are blocked ++ * at the mem_access only ++ */ ++#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec) ++ ++/* [31:0] PHY0 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0) ++/* [31:0] PHY1 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4) ++/* [31:0] PHY2 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8) ++/* [31:0] PHY3 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc) ++#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100) ++#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104) ++ ++#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108) ++#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c) ++#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110) ++ ++#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114) ++#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118) ++#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c) ++/* [31:0] PHY4 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY1 ++ */ ++#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY2 ++ */ ++#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c) ++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. ++ * This is a global Enable for all schedulers in PHY3 ++ */ ++#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140) ++#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144) ++/* [31:0] PHY5 in queue address (must be initialized with one of the ++ * xxx_INQ_PKTPTR cbus addresses) ++ */ ++#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148) ++ ++#define SW_RESET BIT(0) /* Global software reset */ ++#define INQ_RESET BIT(2) ++#define TEQ_RESET BIT(3) ++#define TDQ_RESET BIT(4) ++#define PE_RESET BIT(5) ++#define MEM_INIT BIT(6) ++#define MEM_INIT_DONE BIT(7) ++#define LLM_INIT BIT(8) ++#define LLM_INIT_DONE BIT(9) ++#define ECC_MEM_INIT_DONE BIT(10) ++ ++struct tmu_cfg { ++ u32 pe_sys_clk_ratio; ++ unsigned long llm_base_addr; ++ u32 llm_queue_len; ++}; ++ ++/* Not HW related for pfe_ctrl / pfe common defines */ ++#define DEFAULT_MAX_QDEPTH 80 ++#define DEFAULT_Q0_QDEPTH 511 /*We keep one large queue for host tx qos */ ++#define DEFAULT_TMU3_QDEPTH 127 ++ ++#endif /* _TMU_CSR_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h +@@ -0,0 +1,61 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _UTIL_CSR_H_ ++#define _UTIL_CSR_H_ ++ ++#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000) ++#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004) ++#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010) ++ ++#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014) ++ ++#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020) ++#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024) ++#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060) ++#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064) ++ ++#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100) ++#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104) ++#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108) ++ ++#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114) ++#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118) ++ ++#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200) ++#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204) ++#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208) ++#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c) ++#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210) ++#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214) ++#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218) ++#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c) ++#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220) ++#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224) ++ ++#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228) ++#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c) ++#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230) ++ ++#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234) ++ ++struct util_cfg { ++ u32 pe_sys_clk_ratio; ++}; ++ ++#endif /* _UTIL_CSR_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h +@@ -0,0 +1,372 @@ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _PFE_H_ ++#define _PFE_H_ ++ ++#include "cbus.h" ++ ++#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) ++/* ++ * Only valid for mem access register interface ++ */ ++#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) ++#define CLASS_DMEM_SIZE 0x00002000 ++#define CLASS_IMEM_SIZE 0x00008000 ++ ++#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) ++/* ++ * Only valid for mem access register interface ++ */ ++#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) ++#define TMU_DMEM_SIZE 0x00000800 ++#define TMU_IMEM_SIZE 0x00002000 ++ ++#define UTIL_DMEM_BASE_ADDR 0x00000000 ++#define UTIL_DMEM_SIZE 0x00002000 ++ ++#define PE_LMEM_BASE_ADDR 0xc3010000 ++#define PE_LMEM_SIZE 0x8000 ++#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE) ++ ++#define DMEM_BASE_ADDR 0x00000000 ++#define DMEM_SIZE 0x2000 /* TMU has less... */ ++#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE) ++ ++#define PMEM_BASE_ADDR 0x00010000 ++#define PMEM_SIZE 0x8000 /* TMU has less... */ ++#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE) ++ ++/* These check memory ranges from PE point of view/memory map */ ++#define IS_DMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + (len)) <= DMEM_END); }) ++ ++#define IS_PMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + (len)) <= PMEM_END); }) ++ ++#define IS_PE_LMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= \ ++ PE_LMEM_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + \ ++ (len)) <= PE_LMEM_END); }) ++ ++#define IS_PFE_LMEM(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= \ ++ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \ ++ (((unsigned long)(addr_) + (len)) <= \ ++ CBUS_VIRT_TO_PFE(LMEM_END)); }) ++ ++#define __IS_PHYS_DDR(addr, len) \ ++ ({ typeof(addr) addr_ = (addr); \ ++ ((unsigned long)(addr_) >= \ ++ DDR_PHYS_BASE_ADDR) && \ ++ (((unsigned long)(addr_) + (len)) <= \ ++ DDR_PHYS_END); }) ++ ++#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len) ++ ++/* ++ * If using a run-time virtual address for the cbus base address use this code ++ */ ++extern void *cbus_base_addr; ++extern void *ddr_base_addr; ++extern unsigned long ddr_phys_base_addr; ++extern unsigned int ddr_size; ++ ++#define CBUS_BASE_ADDR cbus_base_addr ++#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr ++#define DDR_BASE_ADDR ddr_base_addr ++#define DDR_SIZE ddr_size ++ ++#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE) ++ ++#define LS1012A_PFE_RESET_WA /* ++ * PFE doesn't have global reset and re-init ++ * should takecare few things to make PFE ++ * functional after reset ++ */ ++#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* CBUS physical base address ++ * as seen by PE's. ++ */ ++/* CBUS physical base address as seen by PE's. */ ++#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000 ++ ++#define DDR_PHYS_TO_PFE(p) (((unsigned long int)(p)) & 0x7FFFFFFF) ++#define DDR_PFE_TO_PHYS(p) (((unsigned long int)(p)) | 0x80000000) ++#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + \ ++ PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE) ++/* Translates to PFE address map */ ++ ++#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR) ++#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR) ++#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p))) ++ ++#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + \ ++ PFE_CBUS_PHYS_BASE_ADDR) ++#define CBUS_PFE_TO_VIRT(p) (((unsigned long int)(p) - \ ++ PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR) ++ ++/* The below part of the code is used in QOS control driver from host */ ++#define TMU_APB_BASE_ADDR 0xc1000000 /* TMU base address seen by ++ * pe's ++ */ ++ ++enum { ++ CLASS0_ID = 0, ++ CLASS1_ID, ++ CLASS2_ID, ++ CLASS3_ID, ++ CLASS4_ID, ++ CLASS5_ID, ++ TMU0_ID, ++ TMU1_ID, ++ TMU2_ID, ++ TMU3_ID, ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ UTIL_ID, ++#endif ++ MAX_PE ++}; ++ ++#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) |\ ++ BIT(CLASS2_ID) | BIT(CLASS3_ID) |\ ++ BIT(CLASS4_ID) | BIT(CLASS5_ID)) ++#define CLASS_MAX_ID CLASS5_ID ++ ++#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) |\ ++ BIT(TMU3_ID)) ++ ++#define TMU_MAX_ID TMU3_ID ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++#define UTIL_MASK BIT(UTIL_ID) ++#endif ++ ++struct pe_status { ++ u32 cpu_state; ++ u32 activity_counter; ++ u32 rx; ++ union { ++ u32 tx; ++ u32 tmu_qstatus; ++ }; ++ u32 drop; ++#if defined(CFG_PE_DEBUG) ++ u32 debug_indicator; ++ u32 debug[16]; ++#endif ++} __aligned(16); ++ ++struct pe_sync_mailbox { ++ u32 stop; ++ u32 stopped; ++}; ++ ++/* Drop counter definitions */ ++ ++#define CLASS_NUM_DROP_COUNTERS 13 ++#define UTIL_NUM_DROP_COUNTERS 8 ++ ++/* PE information. ++ * Structure containing PE's specific information. It is used to create ++ * generic C functions common to all PE's. ++ * Before using the library functions this structure needs to be initialized ++ * with the different registers virtual addresses ++ * (according to the ARM MMU mmaping). The default initialization supports a ++ * virtual == physical mapping. ++ */ ++struct pe_info { ++ u32 dmem_base_addr; /* PE's dmem base address */ ++ u32 pmem_base_addr; /* PE's pmem base address */ ++ u32 pmem_size; /* PE's pmem size */ ++ ++ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA register ++ * address ++ */ ++ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR register ++ * address ++ */ ++ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA register ++ * address ++ */ ++}; ++ ++void pe_lmem_read(u32 *dst, u32 len, u32 offset); ++void pe_lmem_write(u32 *src, u32 len, u32 offset); ++ ++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); ++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); ++ ++u32 pe_pmem_read(int id, u32 addr, u8 size); ++ ++void pe_dmem_write(int id, u32 val, u32 addr, u8 size); ++u32 pe_dmem_read(int id, u32 addr, u8 size); ++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len); ++void class_pe_lmem_memset(u32 dst, int val, unsigned int len); ++void class_bus_write(u32 val, u32 addr, u8 size); ++u32 class_bus_read(u32 addr, u8 size); ++ ++#define class_bus_readl(addr) class_bus_read(addr, 4) ++#define class_bus_readw(addr) class_bus_read(addr, 2) ++#define class_bus_readb(addr) class_bus_read(addr, 1) ++ ++#define class_bus_writel(val, addr) class_bus_write(val, addr, 4) ++#define class_bus_writew(val, addr) class_bus_write(val, addr, 2) ++#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1) ++ ++#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4) ++#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2) ++#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1) ++ ++#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4) ++#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2) ++#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1) ++ ++/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */ ++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr, ++ struct device *dev); ++ ++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, ++ unsigned int ddr_size); ++void bmu_init(void *base, struct BMU_CFG *cfg); ++void bmu_reset(void *base); ++void bmu_enable(void *base); ++void bmu_disable(void *base); ++void bmu_set_config(void *base, struct BMU_CFG *cfg); ++ ++/* ++ * An enumerated type for loopback values. This can be one of three values, no ++ * loopback -normal operation, local loopback with internal loopback module of ++ * MAC or PHY loopback which is through the external PHY. ++ */ ++#ifndef __MAC_LOOP_ENUM__ ++#define __MAC_LOOP_ENUM__ ++enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL}; ++#endif ++ ++void gemac_init(void *base, void *config); ++void gemac_disable_rx_checksum_offload(void *base); ++void gemac_enable_rx_checksum_offload(void *base); ++void gemac_set_speed(void *base, enum mac_speed gem_speed); ++void gemac_set_duplex(void *base, int duplex); ++void gemac_set_mode(void *base, int mode); ++void gemac_enable(void *base); ++void gemac_tx_disable(void *base); ++void gemac_tx_enable(void *base); ++void gemac_disable(void *base); ++void gemac_reset(void *base); ++void gemac_set_address(void *base, struct spec_addr *addr); ++struct spec_addr gemac_get_address(void *base); ++void gemac_set_loop(void *base, enum mac_loop gem_loop); ++void gemac_set_laddr1(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddr2(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddr3(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddr4(void *base, struct pfe_mac_addr *address); ++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address, ++ unsigned int entry_index); ++void gemac_clear_laddr1(void *base); ++void gemac_clear_laddr2(void *base); ++void gemac_clear_laddr3(void *base); ++void gemac_clear_laddr4(void *base); ++void gemac_clear_laddrN(void *base, unsigned int entry_index); ++struct pfe_mac_addr gemac_get_hash(void *base); ++void gemac_set_hash(void *base, struct pfe_mac_addr *hash); ++struct pfe_mac_addr gem_get_laddr1(void *base); ++struct pfe_mac_addr gem_get_laddr2(void *base); ++struct pfe_mac_addr gem_get_laddr3(void *base); ++struct pfe_mac_addr gem_get_laddr4(void *base); ++struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index); ++void gemac_set_config(void *base, struct gemac_cfg *cfg); ++void gemac_allow_broadcast(void *base); ++void gemac_no_broadcast(void *base); ++void gemac_enable_1536_rx(void *base); ++void gemac_disable_1536_rx(void *base); ++void gemac_set_rx_max_fl(void *base, int mtu); ++void gemac_enable_rx_jmb(void *base); ++void gemac_disable_rx_jmb(void *base); ++void gemac_enable_stacked_vlan(void *base); ++void gemac_disable_stacked_vlan(void *base); ++void gemac_enable_pause_rx(void *base); ++void gemac_disable_pause_rx(void *base); ++void gemac_enable_copy_all(void *base); ++void gemac_disable_copy_all(void *base); ++void gemac_set_bus_width(void *base, int width); ++void gemac_set_wol(void *base, u32 wol_conf); ++ ++void gpi_init(void *base, struct gpi_cfg *cfg); ++void gpi_reset(void *base); ++void gpi_enable(void *base); ++void gpi_disable(void *base); ++void gpi_set_config(void *base, struct gpi_cfg *cfg); ++ ++void class_init(struct class_cfg *cfg); ++void class_reset(void); ++void class_enable(void); ++void class_disable(void); ++void class_set_config(struct class_cfg *cfg); ++ ++void tmu_reset(void); ++void tmu_init(struct tmu_cfg *cfg); ++void tmu_enable(u32 pe_mask); ++void tmu_disable(u32 pe_mask); ++u32 tmu_qstatus(u32 if_id); ++u32 tmu_pkts_processed(u32 if_id); ++ ++void util_init(struct util_cfg *cfg); ++void util_reset(void); ++void util_enable(void); ++void util_disable(void); ++ ++void hif_init(void); ++void hif_tx_enable(void); ++void hif_tx_disable(void); ++void hif_rx_enable(void); ++void hif_rx_disable(void); ++ ++/* Get Chip Revision level ++ * ++ */ ++static inline unsigned int CHIP_REVISION(void) ++{ ++ /*For LS1012A return always 1 */ ++ return 1; ++} ++ ++/* Start HIF rx DMA ++ * ++ */ ++static inline void hif_rx_dma_start(void) ++{ ++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL); ++} ++ ++/* Start HIF tx DMA ++ * ++ */ ++static inline void hif_tx_dma_start(void) ++{ ++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL); ++} ++ ++#endif /* _PFE_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_cdev.c +@@ -0,0 +1,258 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2018 NXP ++ */ ++ ++/* @pfe_cdev.c. ++ * Dummy device representing the PFE US in userspace. ++ * - used for interacting with the kernel layer for link status ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "pfe_cdev.h" ++#include "pfe_mod.h" ++ ++static int pfe_majno; ++static struct class *pfe_char_class; ++static struct device *pfe_char_dev; ++struct eventfd_ctx *g_trigger; ++ ++struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT]; ++ ++static int pfe_cdev_open(struct inode *inp, struct file *fp) ++{ ++ pr_debug("PFE CDEV device opened.\n"); ++ return 0; ++} ++ ++static ssize_t pfe_cdev_read(struct file *fp, char *buf, ++ size_t len, loff_t *off) ++{ ++ int ret = 0; ++ ++ pr_info("PFE CDEV attempt copying (%lu) size of user.\n", ++ sizeof(link_states)); ++ ++ pr_debug("Dump link_state on screen before copy_to_user\n"); ++ for (; ret < PFE_CDEV_ETH_COUNT; ret++) { ++ pr_debug("%u %u", link_states[ret].phy_id, ++ link_states[ret].state); ++ pr_debug("\n"); ++ } ++ ++ /* Copy to user the value in buffer sized len */ ++ ret = copy_to_user(buf, &link_states, sizeof(link_states)); ++ if (ret != 0) { ++ pr_err("Failed to send (%d)bytes of (%lu) requested.\n", ++ ret, len); ++ return -EFAULT; ++ } ++ ++ /* offset set back to 0 as there is contextual reading offset */ ++ *off = 0; ++ pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states)); ++ ++ return sizeof(link_states); ++} ++ ++/** ++ * This function is for getting some commands from user through non-IOCTL ++ * channel. It can used to configure the device. ++ * TODO: To be filled in future, if require duplex communication with user ++ * space. ++ */ ++static ssize_t pfe_cdev_write(struct file *fp, const char *buf, ++ size_t len, loff_t *off) ++{ ++ pr_info("PFE CDEV Write operation not supported!\n"); ++ ++ return -EFAULT; ++} ++ ++static int pfe_cdev_release(struct inode *inp, struct file *fp) ++{ ++ if (g_trigger) { ++ free_irq(pfe->hif_irq, g_trigger); ++ eventfd_ctx_put(g_trigger); ++ g_trigger = NULL; ++ } ++ ++ pr_info("PFE_CDEV: Device successfully closed\n"); ++ return 0; ++} ++ ++/* ++ * hif_us_isr- ++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block ++ */ ++static irqreturn_t hif_us_isr(int irq, void *arg) ++{ ++ struct eventfd_ctx *trigger = (struct eventfd_ctx *)arg; ++ int int_status; ++ int int_enable_mask; ++ ++ /*Read hif interrupt source register */ ++ int_status = readl_relaxed(HIF_INT_SRC); ++ int_enable_mask = readl_relaxed(HIF_INT_ENABLE); ++ ++ if ((int_status & HIF_INT) == 0) ++ return IRQ_NONE; ++ ++ if (int_status & HIF_RXPKT_INT) { ++ int_enable_mask &= ~(HIF_RXPKT_INT); ++ /* Disable interrupts, they will be enabled after ++ * they are serviced ++ */ ++ writel_relaxed(int_enable_mask, HIF_INT_ENABLE); ++ ++ eventfd_signal(trigger, 1); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++#define PFE_INTR_COAL_USECS 100 ++static long pfe_cdev_ioctl(struct file *fp, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret = -EFAULT; ++ int __user *argp = (int __user *)arg; ++ ++ pr_debug("PFE CDEV IOCTL Called with cmd=(%u)\n", cmd); ++ ++ switch (cmd) { ++ case PFE_CDEV_ETH0_STATE_GET: ++ /* Return an unsigned int (link state) for ETH0 */ ++ *argp = link_states[0].state; ++ pr_debug("Returning state=%d for ETH0\n", *argp); ++ ret = 0; ++ break; ++ case PFE_CDEV_ETH1_STATE_GET: ++ /* Return an unsigned int (link state) for ETH0 */ ++ *argp = link_states[1].state; ++ pr_debug("Returning state=%d for ETH1\n", *argp); ++ ret = 0; ++ break; ++ case PFE_CDEV_HIF_INTR_EN: ++ /* Return success/failure */ ++ g_trigger = eventfd_ctx_fdget(*argp); ++ if (IS_ERR(g_trigger)) ++ return PTR_ERR(g_trigger); ++ ret = request_irq(pfe->hif_irq, hif_us_isr, 0, "pfe_hif", ++ g_trigger); ++ if (ret) { ++ pr_err("%s: failed to get the hif IRQ = %d\n", ++ __func__, pfe->hif_irq); ++ eventfd_ctx_put(g_trigger); ++ g_trigger = NULL; ++ } ++ writel((PFE_INTR_COAL_USECS * (pfe->ctrl.sys_clk / 1000)) | ++ HIF_INT_COAL_ENABLE, HIF_INT_COAL); ++ ++ pr_debug("request_irq for hif interrupt: %d\n", pfe->hif_irq); ++ ret = 0; ++ break; ++ default: ++ pr_info("Unsupport cmd (%d) for PFE CDEV.\n", cmd); ++ break; ++ }; ++ ++ return ret; ++} ++ ++static unsigned int pfe_cdev_poll(struct file *fp, ++ struct poll_table_struct *wait) ++{ ++ pr_info("PFE CDEV poll method not supported\n"); ++ return 0; ++} ++ ++static const struct file_operations pfe_cdev_fops = { ++ .open = pfe_cdev_open, ++ .read = pfe_cdev_read, ++ .write = pfe_cdev_write, ++ .release = pfe_cdev_release, ++ .unlocked_ioctl = pfe_cdev_ioctl, ++ .poll = pfe_cdev_poll, ++}; ++ ++int pfe_cdev_init(void) ++{ ++ int ret; ++ ++ pr_debug("PFE CDEV initialization begin\n"); ++ ++ /* Register the major number for the device */ ++ pfe_majno = register_chrdev(0, PFE_CDEV_NAME, &pfe_cdev_fops); ++ if (pfe_majno < 0) { ++ pr_err("Unable to register PFE CDEV. PFE CDEV not available\n"); ++ ret = pfe_majno; ++ goto cleanup; ++ } ++ ++ pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno); ++ ++ /* Register the class for the device */ ++ pfe_char_class = class_create(THIS_MODULE, PFE_CLASS_NAME); ++ if (IS_ERR(pfe_char_class)) { ++ pr_err( ++ "Failed to init class for PFE CDEV. PFE CDEV not available.\n"); ++ ret = PTR_ERR(pfe_char_class); ++ goto cleanup; ++ } ++ ++ pr_debug("PFE CDEV Class created successfully.\n"); ++ ++ /* Create the device without any parent and without any callback data */ ++ pfe_char_dev = device_create(pfe_char_class, NULL, ++ MKDEV(pfe_majno, 0), NULL, ++ PFE_CDEV_NAME); ++ if (IS_ERR(pfe_char_dev)) { ++ pr_err("Unable to PFE CDEV device. PFE CDEV not available.\n"); ++ ret = PTR_ERR(pfe_char_dev); ++ goto cleanup; ++ } ++ ++ /* Information structure being shared with the userspace */ ++ memset(link_states, 0, sizeof(struct pfe_shared_info) * ++ PFE_CDEV_ETH_COUNT); ++ ++ pr_info("PFE CDEV created: %s\n", PFE_CDEV_NAME); ++ ++ ret = 0; ++ return ret; ++ ++cleanup: ++ if (!IS_ERR(pfe_char_class)) ++ class_destroy(pfe_char_class); ++ ++ if (pfe_majno > 0) ++ unregister_chrdev(pfe_majno, PFE_CDEV_NAME); ++ ++ return ret; ++} ++ ++void pfe_cdev_exit(void) ++{ ++ if (!IS_ERR(pfe_char_dev)) ++ device_destroy(pfe_char_class, MKDEV(pfe_majno, 0)); ++ ++ if (!IS_ERR(pfe_char_class)) { ++ class_unregister(pfe_char_class); ++ class_destroy(pfe_char_class); ++ } ++ ++ if (pfe_majno > 0) ++ unregister_chrdev(pfe_majno, PFE_CDEV_NAME); ++ ++ /* reset the variables */ ++ pfe_majno = 0; ++ pfe_char_class = NULL; ++ pfe_char_dev = NULL; ++ ++ pr_info("PFE CDEV Removed.\n"); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_cdev.h +@@ -0,0 +1,41 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2018 NXP ++ */ ++ ++#ifndef _PFE_CDEV_H_ ++#define _PFE_CDEV_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFE_CDEV_NAME "pfe_us_cdev" ++#define PFE_CLASS_NAME "ppfe_us" ++ ++/* Extracted from ls1012a_pfe_platform_data, there are 3 interfaces which are ++ * supported by PFE driver. Should be updated if number of eth devices are ++ * changed. ++ */ ++#define PFE_CDEV_ETH_COUNT 3 ++ ++struct pfe_shared_info { ++ uint32_t phy_id; /* Link phy ID */ ++ uint8_t state; /* Has either 0 or 1 */ ++}; ++ ++extern struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT]; ++ ++/* IOCTL Commands */ ++#define PFE_CDEV_ETH0_STATE_GET _IOR('R', 0, int) ++#define PFE_CDEV_ETH1_STATE_GET _IOR('R', 1, int) ++#define PFE_CDEV_HIF_INTR_EN _IOWR('R', 2, int) ++ ++int pfe_cdev_init(void); ++void pfe_cdev_exit(void); ++ ++#endif /* _PFE_CDEV_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c +@@ -0,0 +1,226 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++#include "pfe_ctrl.h" ++ ++#define TIMEOUT_MS 1000 ++ ++int relax(unsigned long end) ++{ ++ if (time_after(jiffies, end)) { ++ if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000)) ++ return -1; ++ ++ if (need_resched()) ++ schedule(); ++ } ++ ++ return 0; ++} ++ ++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl) ++{ ++ int id; ++ ++ mutex_lock(&ctrl->mutex); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) ++ pe_dmem_write(id, cpu_to_be32(0x1), CLASS_DM_RESUME, 4); ++ ++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { ++ if (id == TMU2_ID) ++ continue; ++ pe_dmem_write(id, cpu_to_be32(0x1), TMU_DM_RESUME, 4); ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), UTIL_DM_RESUME, 4); ++#endif ++ mutex_unlock(&ctrl->mutex); ++} ++ ++void pfe_ctrl_resume(struct pfe_ctrl *ctrl) ++{ ++ int pe_mask = CLASS_MASK | TMU_MASK; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe_mask |= UTIL_MASK; ++#endif ++ mutex_lock(&ctrl->mutex); ++ pe_start(&pfe->ctrl, pe_mask); ++ mutex_unlock(&ctrl->mutex); ++} ++ ++/* PE sync stop. ++ * Stops packet processing for a list of PE's (specified using a bitmask). ++ * The caller must hold ctrl->mutex. ++ * ++ * @param ctrl Control context ++ * @param pe_mask Mask of PE id's to stop ++ * ++ */ ++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask) ++{ ++ struct pe_sync_mailbox *mbox; ++ int pe_stopped = 0; ++ unsigned long end = jiffies + 2; ++ int i; ++ ++ pe_mask &= 0x2FF; /*Exclude Util + TMU2 */ ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x1), (unsigned ++ long)&mbox->stop, 4); ++ } ++ ++ while (pe_stopped != pe_mask) { ++ for (i = 0; i < MAX_PE; i++) ++ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ if (pe_dmem_read(i, (unsigned ++ long)&mbox->stopped, 4) & ++ cpu_to_be32(0x1)) ++ pe_stopped |= (1 << i); ++ } ++ ++ if (relax(end) < 0) ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped); ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned ++ long)&mbox->stop, 4); ++ } ++ ++ return -EIO; ++} ++ ++/* PE start. ++ * Starts packet processing for a list of PE's (specified using a bitmask). ++ * The caller must hold ctrl->mutex. ++ * ++ * @param ctrl Control context ++ * @param pe_mask Mask of PE id's to start ++ * ++ */ ++void pe_start(struct pfe_ctrl *ctrl, int pe_mask) ++{ ++ struct pe_sync_mailbox *mbox; ++ int i; ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned ++ long)&mbox->stop, 4); ++ } ++} ++ ++/* This function will ensure all PEs are put in to idle state */ ++int pe_reset_all(struct pfe_ctrl *ctrl) ++{ ++ struct pe_sync_mailbox *mbox; ++ int pe_stopped = 0; ++ unsigned long end = jiffies + 2; ++ int i; ++ int pe_mask = CLASS_MASK | TMU_MASK; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe_mask |= UTIL_MASK; ++#endif ++ ++ for (i = 0; i < MAX_PE; i++) ++ if (pe_mask & (1 << i)) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ pe_dmem_write(i, cpu_to_be32(0x2), (unsigned ++ long)&mbox->stop, 4); ++ } ++ ++ while (pe_stopped != pe_mask) { ++ for (i = 0; i < MAX_PE; i++) ++ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) { ++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; ++ ++ if (pe_dmem_read(i, (unsigned long) ++ &mbox->stopped, 4) & ++ cpu_to_be32(0x1)) ++ pe_stopped |= (1 << i); ++ } ++ ++ if (relax(end) < 0) ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped); ++ return -EIO; ++} ++ ++int pfe_ctrl_init(struct pfe *pfe) ++{ ++ struct pfe_ctrl *ctrl = &pfe->ctrl; ++ int id; ++ ++ pr_info("%s\n", __func__); ++ ++ mutex_init(&ctrl->mutex); ++ spin_lock_init(&ctrl->lock); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ ctrl->sync_mailbox_baseaddr[id] = CLASS_DM_SYNC_MBOX; ++ ctrl->msg_mailbox_baseaddr[id] = CLASS_DM_MSG_MBOX; ++ } ++ ++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { ++ if (id == TMU2_ID) ++ continue; ++ ctrl->sync_mailbox_baseaddr[id] = TMU_DM_SYNC_MBOX; ++ ctrl->msg_mailbox_baseaddr[id] = TMU_DM_MSG_MBOX; ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ ctrl->sync_mailbox_baseaddr[UTIL_ID] = UTIL_DM_SYNC_MBOX; ++ ctrl->msg_mailbox_baseaddr[UTIL_ID] = UTIL_DM_MSG_MBOX; ++#endif ++ ++ ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR; ++ ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr + ++ ROUTE_TABLE_BASEADDR; ++ ++ ctrl->dev = pfe->dev; ++ ++ pr_info("%s finished\n", __func__); ++ ++ return 0; ++} ++ ++void pfe_ctrl_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h +@@ -0,0 +1,100 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_CTRL_H_ ++#define _PFE_CTRL_H_ ++ ++#include ++ ++#include "pfe/pfe.h" ++ ++#define DMA_BUF_SIZE_128 0x80 /* enough for 1 conntracks */ ++#define DMA_BUF_SIZE_256 0x100 ++/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */ ++#define DMA_BUF_SIZE_512 0x200 ++/* 512bytes dma allocated buffers used by rtp relay feature */ ++#define DMA_BUF_MIN_ALIGNMENT 8 ++#define DMA_BUF_BOUNDARY (4 * 1024) ++/* bursts can not cross 4k boundary */ ++ ++#define CMD_TX_ENABLE 0x0501 ++#define CMD_TX_DISABLE 0x0502 ++ ++#define CMD_RX_LRO 0x0011 ++#define CMD_PKTCAP_ENABLE 0x0d01 ++#define CMD_QM_EXPT_RATE 0x020c ++ ++#define CLASS_DM_SH_STATIC (0x800) ++#define CLASS_DM_CPU_TICKS (CLASS_DM_SH_STATIC) ++#define CLASS_DM_SYNC_MBOX (0x808) ++#define CLASS_DM_MSG_MBOX (0x810) ++#define CLASS_DM_DROP_CNTR (0x820) ++#define CLASS_DM_RESUME (0x854) ++#define CLASS_DM_PESTATUS (0x860) ++#define CLASS_DM_CRC_VALIDATED (0x14b0) ++ ++#define TMU_DM_SH_STATIC (0x80) ++#define TMU_DM_CPU_TICKS (TMU_DM_SH_STATIC) ++#define TMU_DM_SYNC_MBOX (0x88) ++#define TMU_DM_MSG_MBOX (0x90) ++#define TMU_DM_RESUME (0xA0) ++#define TMU_DM_PESTATUS (0xB0) ++#define TMU_DM_CONTEXT (0x300) ++#define TMU_DM_TX_TRANS (0x480) ++ ++#define UTIL_DM_SH_STATIC (0x0) ++#define UTIL_DM_CPU_TICKS (UTIL_DM_SH_STATIC) ++#define UTIL_DM_SYNC_MBOX (0x8) ++#define UTIL_DM_MSG_MBOX (0x10) ++#define UTIL_DM_DROP_CNTR (0x20) ++#define UTIL_DM_RESUME (0x40) ++#define UTIL_DM_PESTATUS (0x50) ++ ++struct pfe_ctrl { ++ struct mutex mutex; /* to serialize pfe control access */ ++ spinlock_t lock; ++ ++ void *dma_pool; ++ void *dma_pool_512; ++ void *dma_pool_128; ++ ++ struct device *dev; ++ ++ void *hash_array_baseaddr; /* ++ * Virtual base address of ++ * the conntrack hash array ++ */ ++ unsigned long hash_array_phys_baseaddr; /* ++ * Physical base address of ++ * the conntrack hash array ++ */ ++ ++ int (*event_cb)(u16, u16, u16*); ++ ++ unsigned long sync_mailbox_baseaddr[MAX_PE]; /* ++ * Sync mailbox PFE ++ * internal address, ++ * initialized ++ * when parsing elf images ++ */ ++ unsigned long msg_mailbox_baseaddr[MAX_PE]; /* ++ * Msg mailbox PFE internal ++ * address, initialized ++ * when parsing elf images ++ */ ++ unsigned int sys_clk; /* AXI clock value, in KHz */ ++}; ++ ++int pfe_ctrl_init(struct pfe *pfe); ++void pfe_ctrl_exit(struct pfe *pfe); ++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask); ++void pe_start(struct pfe_ctrl *ctrl, int pe_mask); ++int pe_reset_all(struct pfe_ctrl *ctrl); ++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl); ++void pfe_ctrl_resume(struct pfe_ctrl *ctrl); ++int relax(unsigned long end); ++ ++#endif /* _PFE_CTRL_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c +@@ -0,0 +1,99 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++static int dmem_show(struct seq_file *s, void *unused) ++{ ++ u32 dmem_addr, val; ++ int id = (long int)s->private; ++ int i; ++ ++ for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) { ++ seq_printf(s, "%04x:", dmem_addr); ++ ++ for (i = 0; i < 8; i++) { ++ val = pe_dmem_read(id, dmem_addr + i * 4, 4); ++ seq_printf(s, " %02x %02x %02x %02x", val & 0xff, ++ (val >> 8) & 0xff, (val >> 16) & 0xff, ++ (val >> 24) & 0xff); ++ } ++ ++ seq_puts(s, "\n"); ++ } ++ ++ return 0; ++} ++ ++static int dmem_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, dmem_show, inode->i_private); ++} ++ ++static const struct file_operations dmem_fops = { ++ .open = dmem_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++int pfe_debugfs_init(struct pfe *pfe) ++{ ++ struct dentry *d; ++ ++ pr_info("%s\n", __func__); ++ ++ pfe->dentry = debugfs_create_dir("pfe", NULL); ++ if (IS_ERR_OR_NULL(pfe->dentry)) ++ goto err_dir; ++ ++ d = debugfs_create_file("pe0_dmem", 0444, pfe->dentry, (void *)0, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe1_dmem", 0444, pfe->dentry, (void *)1, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe2_dmem", 0444, pfe->dentry, (void *)2, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe3_dmem", 0444, pfe->dentry, (void *)3, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe4_dmem", 0444, pfe->dentry, (void *)4, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ d = debugfs_create_file("pe5_dmem", 0444, pfe->dentry, (void *)5, ++ &dmem_fops); ++ if (IS_ERR_OR_NULL(d)) ++ goto err_pe; ++ ++ return 0; ++ ++err_pe: ++ debugfs_remove_recursive(pfe->dentry); ++ ++err_dir: ++ return -1; ++} ++ ++void pfe_debugfs_exit(struct pfe *pfe) ++{ ++ debugfs_remove_recursive(pfe->dentry); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_DEBUGFS_H_ ++#define _PFE_DEBUGFS_H_ ++ ++int pfe_debugfs_init(struct pfe *pfe); ++void pfe_debugfs_exit(struct pfe *pfe); ++ ++#endif /* _PFE_DEBUGFS_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_eth.c +@@ -0,0 +1,2587 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++/* @pfe_eth.c. ++ * Ethernet driver for to handle exception path for PFE. ++ * - uses HIF functions to send/receive packets. ++ * - uses ctrl function to start/stop interfaces. ++ * - uses direct register accesses to control phy operation. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_NF_CONNTRACK_MARK) ++#include ++#endif ++ ++#include "pfe_mod.h" ++#include "pfe_eth.h" ++#include "pfe_cdev.h" ++ ++#define LS1012A_REV_1_0 0x87040010 ++ ++bool pfe_use_old_dts_phy; ++bool pfe_errata_a010897; ++ ++static void *cbus_emac_base[3]; ++static void *cbus_gpi_base[3]; ++ ++/* Forward Declaration */ ++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv); ++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv); ++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int ++ from_tx, int n_desc); ++ ++/* MDIO registers */ ++#define MDIO_SGMII_CR 0x00 ++#define MDIO_SGMII_SR 0x01 ++#define MDIO_SGMII_DEV_ABIL_SGMII 0x04 ++#define MDIO_SGMII_LINK_TMR_L 0x12 ++#define MDIO_SGMII_LINK_TMR_H 0x13 ++#define MDIO_SGMII_IF_MODE 0x14 ++ ++/* SGMII Control defines */ ++#define SGMII_CR_RST 0x8000 ++#define SGMII_CR_AN_EN 0x1000 ++#define SGMII_CR_RESTART_AN 0x0200 ++#define SGMII_CR_FD 0x0100 ++#define SGMII_CR_SPEED_SEL1_1G 0x0040 ++#define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ ++ SGMII_CR_SPEED_SEL1_1G) ++ ++/* SGMII IF Mode */ ++#define SGMII_DUPLEX_HALF 0x10 ++#define SGMII_SPEED_10MBPS 0x00 ++#define SGMII_SPEED_100MBPS 0x04 ++#define SGMII_SPEED_1GBPS 0x08 ++#define SGMII_USE_SGMII_AN 0x02 ++#define SGMII_EN 0x01 ++ ++/* SGMII Device Ability for SGMII */ ++#define SGMII_DEV_ABIL_ACK 0x4000 ++#define SGMII_DEV_ABIL_EEE_CLK_STP_EN 0x0100 ++#define SGMII_DEV_ABIL_SGMII 0x0001 ++ ++unsigned int gemac_regs[] = { ++ 0x0004, /* Interrupt event */ ++ 0x0008, /* Interrupt mask */ ++ 0x0024, /* Ethernet control */ ++ 0x0064, /* MIB Control/Status */ ++ 0x0084, /* Receive control/status */ ++ 0x00C4, /* Transmit control */ ++ 0x00E4, /* Physical address low */ ++ 0x00E8, /* Physical address high */ ++ 0x0144, /* Transmit FIFO Watermark and Store and Forward Control*/ ++ 0x0190, /* Receive FIFO Section Full Threshold */ ++ 0x01A0, /* Transmit FIFO Section Empty Threshold */ ++ 0x01B0, /* Frame Truncation Length */ ++}; ++ ++const struct soc_device_attribute ls1012a_rev1_soc_attr[] = { ++ { .family = "QorIQ LS1012A", ++ .soc_id = "svr:0x87040010", ++ .revision = "1.0", ++ .data = NULL }, ++ { }, ++}; ++ ++/********************************************************************/ ++/* SYSFS INTERFACE */ ++/********************************************************************/ ++ ++#ifdef PFE_ETH_NAPI_STATS ++/* ++ * pfe_eth_show_napi_stats ++ */ ++static ssize_t pfe_eth_show_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "sched: %u\n", ++ priv->napi_counters[NAPI_SCHED_COUNT]); ++ len += sprintf(buf + len, "poll: %u\n", ++ priv->napi_counters[NAPI_POLL_COUNT]); ++ len += sprintf(buf + len, "packet: %u\n", ++ priv->napi_counters[NAPI_PACKET_COUNT]); ++ len += sprintf(buf + len, "budget: %u\n", ++ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]); ++ len += sprintf(buf + len, "desc: %u\n", ++ priv->napi_counters[NAPI_DESC_COUNT]); ++ ++ return len; ++} ++ ++/* ++ * pfe_eth_set_napi_stats ++ */ ++static ssize_t pfe_eth_set_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ++ memset(priv->napi_counters, 0, sizeof(priv->napi_counters)); ++ ++ return count; ++} ++#endif ++#ifdef PFE_ETH_TX_STATS ++/* pfe_eth_show_tx_stats ++ * ++ */ ++static ssize_t pfe_eth_show_tx_stats(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ssize_t len = 0; ++ int i; ++ ++ len += sprintf(buf + len, "TX queues stats:\n"); ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ i); ++ ++ len += sprintf(buf + len, "\n"); ++ __netif_tx_lock_bh(tx_queue); ++ ++ hif_tx_lock(&pfe->hif); ++ len += sprintf(buf + len, ++ "Queue %2d : credits = %10d\n" ++ , i, hif_lib_tx_credit_avail(pfe, priv->id, i)); ++ len += sprintf(buf + len, ++ " tx packets = %10d\n" ++ , pfe->tmu_credit.tx_packets[priv->id][i]); ++ hif_tx_unlock(&pfe->hif); ++ ++ /* Don't output additionnal stats if queue never used */ ++ if (!pfe->tmu_credit.tx_packets[priv->id][i]) ++ goto skip; ++ ++ len += sprintf(buf + len, ++ " clean_fail = %10d\n" ++ , priv->clean_fail[i]); ++ len += sprintf(buf + len, ++ " stop_queue = %10d\n" ++ , priv->stop_queue_total[i]); ++ len += sprintf(buf + len, ++ " stop_queue_hif = %10d\n" ++ , priv->stop_queue_hif[i]); ++ len += sprintf(buf + len, ++ " stop_queue_hif_client = %10d\n" ++ , priv->stop_queue_hif_client[i]); ++ len += sprintf(buf + len, ++ " stop_queue_credit = %10d\n" ++ , priv->stop_queue_credit[i]); ++skip: ++ __netif_tx_unlock_bh(tx_queue); ++ } ++ return len; ++} ++ ++/* pfe_eth_set_tx_stats ++ * ++ */ ++static ssize_t pfe_eth_set_tx_stats(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ int i; ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ i); ++ ++ __netif_tx_lock_bh(tx_queue); ++ priv->clean_fail[i] = 0; ++ priv->stop_queue_total[i] = 0; ++ priv->stop_queue_hif[i] = 0; ++ priv->stop_queue_hif_client[i] = 0; ++ priv->stop_queue_credit[i] = 0; ++ __netif_tx_unlock_bh(tx_queue); ++ } ++ ++ return count; ++} ++#endif ++/* pfe_eth_show_txavail ++ * ++ */ ++static ssize_t pfe_eth_show_txavail(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ ssize_t len = 0; ++ int i; ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ i); ++ ++ __netif_tx_lock_bh(tx_queue); ++ ++ len += sprintf(buf + len, "%d", ++ hif_lib_tx_avail(&priv->client, i)); ++ ++ __netif_tx_unlock_bh(tx_queue); ++ ++ if (i == (emac_txq_cnt - 1)) ++ len += sprintf(buf + len, "\n"); ++ else ++ len += sprintf(buf + len, " "); ++ } ++ ++ return len; ++} ++ ++/* pfe_eth_show_default_priority ++ * ++ */ ++static ssize_t pfe_eth_show_default_priority(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ unsigned long flags; ++ int rc; ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ rc = sprintf(buf, "%d\n", priv->default_priority); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ return rc; ++} ++ ++/* pfe_eth_set_default_priority ++ * ++ */ ++ ++static ssize_t pfe_eth_set_default_priority(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ priv->default_priority = kstrtoul(buf, 0, 0); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ return count; ++} ++ ++static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL); ++static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority, ++ pfe_eth_set_default_priority); ++ ++#ifdef PFE_ETH_NAPI_STATS ++static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats, ++ pfe_eth_set_napi_stats); ++#endif ++ ++#ifdef PFE_ETH_TX_STATS ++static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats, ++ pfe_eth_set_tx_stats); ++#endif ++ ++/* ++ * pfe_eth_sysfs_init ++ * ++ */ ++static int pfe_eth_sysfs_init(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int err; ++ ++ /* Initialize the default values */ ++ ++ /* ++ * By default, packets without conntrack will use this default low ++ * priority queue ++ */ ++ priv->default_priority = 0; ++ ++ /* Create our sysfs files */ ++ err = device_create_file(&ndev->dev, &dev_attr_default_priority); ++ if (err) { ++ netdev_err(ndev, ++ "failed to create default_priority sysfs files\n"); ++ goto err_priority; ++ } ++ ++ err = device_create_file(&ndev->dev, &dev_attr_txavail); ++ if (err) { ++ netdev_err(ndev, ++ "failed to create default_priority sysfs files\n"); ++ goto err_txavail; ++ } ++ ++#ifdef PFE_ETH_NAPI_STATS ++ err = device_create_file(&ndev->dev, &dev_attr_napi_stats); ++ if (err) { ++ netdev_err(ndev, "failed to create napi stats sysfs files\n"); ++ goto err_napi; ++ } ++#endif ++ ++#ifdef PFE_ETH_TX_STATS ++ err = device_create_file(&ndev->dev, &dev_attr_tx_stats); ++ if (err) { ++ netdev_err(ndev, "failed to create tx stats sysfs files\n"); ++ goto err_tx; ++ } ++#endif ++ ++ return 0; ++ ++#ifdef PFE_ETH_TX_STATS ++err_tx: ++#endif ++#ifdef PFE_ETH_NAPI_STATS ++ device_remove_file(&ndev->dev, &dev_attr_napi_stats); ++ ++err_napi: ++#endif ++ device_remove_file(&ndev->dev, &dev_attr_txavail); ++ ++err_txavail: ++ device_remove_file(&ndev->dev, &dev_attr_default_priority); ++ ++err_priority: ++ return -1; ++} ++ ++/* pfe_eth_sysfs_exit ++ * ++ */ ++void pfe_eth_sysfs_exit(struct net_device *ndev) ++{ ++#ifdef PFE_ETH_TX_STATS ++ device_remove_file(&ndev->dev, &dev_attr_tx_stats); ++#endif ++ ++#ifdef PFE_ETH_NAPI_STATS ++ device_remove_file(&ndev->dev, &dev_attr_napi_stats); ++#endif ++ device_remove_file(&ndev->dev, &dev_attr_txavail); ++ device_remove_file(&ndev->dev, &dev_attr_default_priority); ++} ++ ++/*************************************************************************/ ++/* ETHTOOL INTERCAE */ ++/*************************************************************************/ ++ ++/*MTIP GEMAC */ ++static const struct fec_stat { ++ char name[ETH_GSTRING_LEN]; ++ u16 offset; ++} fec_stats[] = { ++ /* RMON TX */ ++ { "tx_dropped", RMON_T_DROP }, ++ { "tx_packets", RMON_T_PACKETS }, ++ { "tx_broadcast", RMON_T_BC_PKT }, ++ { "tx_multicast", RMON_T_MC_PKT }, ++ { "tx_crc_errors", RMON_T_CRC_ALIGN }, ++ { "tx_undersize", RMON_T_UNDERSIZE }, ++ { "tx_oversize", RMON_T_OVERSIZE }, ++ { "tx_fragment", RMON_T_FRAG }, ++ { "tx_jabber", RMON_T_JAB }, ++ { "tx_collision", RMON_T_COL }, ++ { "tx_64byte", RMON_T_P64 }, ++ { "tx_65to127byte", RMON_T_P65TO127 }, ++ { "tx_128to255byte", RMON_T_P128TO255 }, ++ { "tx_256to511byte", RMON_T_P256TO511 }, ++ { "tx_512to1023byte", RMON_T_P512TO1023 }, ++ { "tx_1024to2047byte", RMON_T_P1024TO2047 }, ++ { "tx_GTE2048byte", RMON_T_P_GTE2048 }, ++ { "tx_octets", RMON_T_OCTETS }, ++ ++ /* IEEE TX */ ++ { "IEEE_tx_drop", IEEE_T_DROP }, ++ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, ++ { "IEEE_tx_1col", IEEE_T_1COL }, ++ { "IEEE_tx_mcol", IEEE_T_MCOL }, ++ { "IEEE_tx_def", IEEE_T_DEF }, ++ { "IEEE_tx_lcol", IEEE_T_LCOL }, ++ { "IEEE_tx_excol", IEEE_T_EXCOL }, ++ { "IEEE_tx_macerr", IEEE_T_MACERR }, ++ { "IEEE_tx_cserr", IEEE_T_CSERR }, ++ { "IEEE_tx_sqe", IEEE_T_SQE }, ++ { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, ++ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, ++ ++ /* RMON RX */ ++ { "rx_packets", RMON_R_PACKETS }, ++ { "rx_broadcast", RMON_R_BC_PKT }, ++ { "rx_multicast", RMON_R_MC_PKT }, ++ { "rx_crc_errors", RMON_R_CRC_ALIGN }, ++ { "rx_undersize", RMON_R_UNDERSIZE }, ++ { "rx_oversize", RMON_R_OVERSIZE }, ++ { "rx_fragment", RMON_R_FRAG }, ++ { "rx_jabber", RMON_R_JAB }, ++ { "rx_64byte", RMON_R_P64 }, ++ { "rx_65to127byte", RMON_R_P65TO127 }, ++ { "rx_128to255byte", RMON_R_P128TO255 }, ++ { "rx_256to511byte", RMON_R_P256TO511 }, ++ { "rx_512to1023byte", RMON_R_P512TO1023 }, ++ { "rx_1024to2047byte", RMON_R_P1024TO2047 }, ++ { "rx_GTE2048byte", RMON_R_P_GTE2048 }, ++ { "rx_octets", RMON_R_OCTETS }, ++ ++ /* IEEE RX */ ++ { "IEEE_rx_drop", IEEE_R_DROP }, ++ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, ++ { "IEEE_rx_crc", IEEE_R_CRC }, ++ { "IEEE_rx_align", IEEE_R_ALIGN }, ++ { "IEEE_rx_macerr", IEEE_R_MACERR }, ++ { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, ++ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, ++}; ++ ++static void pfe_eth_fill_stats(struct net_device *ndev, struct ethtool_stats ++ *stats, u64 *data) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int i; ++ u64 pfe_crc_validated = 0; ++ int id; ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ pfe_crc_validated += be32_to_cpu(pe_dmem_read(id, ++ CLASS_DM_CRC_VALIDATED + (priv->id * 4), 4)); ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { ++ data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset); ++ ++ if (fec_stats[i].offset == IEEE_R_DROP) ++ data[i] -= pfe_crc_validated; ++ } ++} ++ ++static void pfe_eth_gstrings(struct net_device *netdev, ++ u32 stringset, u8 *data) ++{ ++ int i; ++ ++ switch (stringset) { ++ case ETH_SS_STATS: ++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) ++ memcpy(data + i * ETH_GSTRING_LEN, ++ fec_stats[i].name, ETH_GSTRING_LEN); ++ break; ++ } ++} ++ ++static int pfe_eth_stats_count(struct net_device *ndev, int sset) ++{ ++ switch (sset) { ++ case ETH_SS_STATS: ++ return ARRAY_SIZE(fec_stats); ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++ ++/* ++ * pfe_eth_gemac_reglen - Return the length of the register structure. ++ * ++ */ ++static int pfe_eth_gemac_reglen(struct net_device *ndev) ++{ ++ pr_info("%s()\n", __func__); ++ return (sizeof(gemac_regs) / sizeof(u32)); ++} ++ ++/* ++ * pfe_eth_gemac_get_regs - Return the gemac register structure. ++ * ++ */ ++static void pfe_eth_gemac_get_regs(struct net_device *ndev, struct ethtool_regs ++ *regs, void *regbuf) ++{ ++ int i; ++ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ u32 *buf = (u32 *)regbuf; ++ ++ pr_info("%s()\n", __func__); ++ for (i = 0; i < sizeof(gemac_regs) / sizeof(u32); i++) ++ buf[i] = readl(priv->EMAC_baseaddr + gemac_regs[i]); ++} ++ ++/* ++ * pfe_eth_set_wol - Set the magic packet option, in WoL register. ++ * ++ */ ++static int pfe_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ if (wol->wolopts & ~WAKE_MAGIC) ++ return -EOPNOTSUPP; ++ ++ /* for MTIP we store wol->wolopts */ ++ priv->wol = wol->wolopts; ++ ++ device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); ++ ++ return 0; ++} ++ ++/* ++ * ++ * pfe_eth_get_wol - Get the WoL options. ++ * ++ */ ++static void pfe_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo ++ *wol) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ wol->supported = WAKE_MAGIC; ++ wol->wolopts = 0; ++ ++ if (priv->wol & WAKE_MAGIC) ++ wol->wolopts = WAKE_MAGIC; ++ ++ memset(&wol->sopass, 0, sizeof(wol->sopass)); ++} ++ ++/* ++ * pfe_eth_get_drvinfo - Fills in the drvinfo structure with some basic info ++ * ++ */ ++static void pfe_eth_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo ++ *drvinfo) ++{ ++ strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); ++ strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version)); ++ strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); ++ strlcpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info)); ++} ++ ++/* ++ * pfe_eth_set_settings - Used to send commands to PHY. ++ * ++ */ ++static int pfe_eth_set_settings(struct net_device *ndev, ++ const struct ethtool_link_ksettings *cmd) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct phy_device *phydev = priv->phydev; ++ ++ if (!phydev) ++ return -ENODEV; ++ ++ return phy_ethtool_ksettings_set(phydev, cmd); ++} ++ ++/* ++ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd ++ * structure. ++ * ++ */ ++static int pfe_eth_get_settings(struct net_device *ndev, ++ struct ethtool_link_ksettings *cmd) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct phy_device *phydev = priv->phydev; ++ ++ if (!phydev) ++ return -ENODEV; ++ ++ phy_ethtool_ksettings_get(phydev, cmd); ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_get_msglevel - Gets the debug message mask. ++ * ++ */ ++static uint32_t pfe_eth_get_msglevel(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ return priv->msg_enable; ++} ++ ++/* ++ * pfe_eth_set_msglevel - Sets the debug message mask. ++ * ++ */ ++static void pfe_eth_set_msglevel(struct net_device *ndev, uint32_t data) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ priv->msg_enable = data; ++} ++ ++#define HIF_RX_COAL_MAX_CLKS (~(1 << 31)) ++#define HIF_RX_COAL_CLKS_PER_USEC (pfe->ctrl.sys_clk / 1000) ++#define HIF_RX_COAL_MAX_USECS (HIF_RX_COAL_MAX_CLKS / \ ++ HIF_RX_COAL_CLKS_PER_USEC) ++ ++/* ++ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer. ++ * ++ */ ++static int pfe_eth_set_coalesce(struct net_device *ndev, ++ struct ethtool_coalesce *ec) ++{ ++ if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS) ++ return -EINVAL; ++ ++ if (!ec->rx_coalesce_usecs) { ++ writel(0, HIF_INT_COAL); ++ return 0; ++ } ++ ++ writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) | ++ HIF_INT_COAL_ENABLE, HIF_INT_COAL); ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value. ++ * ++ */ ++static int pfe_eth_get_coalesce(struct net_device *ndev, ++ struct ethtool_coalesce *ec) ++{ ++ int reg_val = readl(HIF_INT_COAL); ++ ++ if (reg_val & HIF_INT_COAL_ENABLE) ++ ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) / ++ HIF_RX_COAL_CLKS_PER_USEC; ++ else ++ ec->rx_coalesce_usecs = 0; ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_set_pauseparam - Sets pause parameters ++ * ++ */ ++static int pfe_eth_set_pauseparam(struct net_device *ndev, ++ struct ethtool_pauseparam *epause) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ if (epause->tx_pause != epause->rx_pause) { ++ netdev_info(ndev, ++ "hardware only support enable/disable both tx and rx\n"); ++ return -EINVAL; ++ } ++ ++ priv->pause_flag = 0; ++ priv->pause_flag |= epause->rx_pause ? PFE_PAUSE_FLAG_ENABLE : 0; ++ priv->pause_flag |= epause->autoneg ? PFE_PAUSE_FLAG_AUTONEG : 0; ++ ++ if (epause->rx_pause || epause->autoneg) { ++ gemac_enable_pause_rx(priv->EMAC_baseaddr); ++ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) | ++ EGPI_PAUSE_ENABLE), ++ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME); ++ if (priv->phydev) { ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->advertising); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->advertising); ++ } ++ } else { ++ gemac_disable_pause_rx(priv->EMAC_baseaddr); ++ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) & ++ ~EGPI_PAUSE_ENABLE), ++ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME); ++ if (priv->phydev) { ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->supported); ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ priv->phydev->advertising); ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ priv->phydev->advertising); ++ } ++ } ++ ++ return 0; ++} ++ ++/* ++ * pfe_eth_get_pauseparam - Gets pause parameters ++ * ++ */ ++static void pfe_eth_get_pauseparam(struct net_device *ndev, ++ struct ethtool_pauseparam *epause) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ epause->autoneg = (priv->pause_flag & PFE_PAUSE_FLAG_AUTONEG) != 0; ++ epause->tx_pause = (priv->pause_flag & PFE_PAUSE_FLAG_ENABLE) != 0; ++ epause->rx_pause = epause->tx_pause; ++} ++ ++/* ++ * pfe_eth_get_hash ++ */ ++#define PFE_HASH_BITS 6 /* #bits in hash */ ++#define CRC32_POLY 0xEDB88320 ++ ++static int pfe_eth_get_hash(u8 *addr) ++{ ++ unsigned int i, bit, data, crc, hash; ++ ++ /* calculate crc32 value of mac address */ ++ crc = 0xffffffff; ++ ++ for (i = 0; i < 6; i++) { ++ data = addr[i]; ++ for (bit = 0; bit < 8; bit++, data >>= 1) { ++ crc = (crc >> 1) ^ ++ (((crc ^ data) & 1) ? CRC32_POLY : 0); ++ } ++ } ++ ++ /* ++ * only upper 6 bits (PFE_HASH_BITS) are used ++ * which point to specific bit in the hash registers ++ */ ++ hash = (crc >> (32 - PFE_HASH_BITS)) & 0x3f; ++ ++ return hash; ++} ++ ++const struct ethtool_ops pfe_ethtool_ops = { ++ .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, ++ .get_drvinfo = pfe_eth_get_drvinfo, ++ .get_regs_len = pfe_eth_gemac_reglen, ++ .get_regs = pfe_eth_gemac_get_regs, ++ .get_link = ethtool_op_get_link, ++ .get_wol = pfe_eth_get_wol, ++ .set_wol = pfe_eth_set_wol, ++ .set_pauseparam = pfe_eth_set_pauseparam, ++ .get_pauseparam = pfe_eth_get_pauseparam, ++ .get_strings = pfe_eth_gstrings, ++ .get_sset_count = pfe_eth_stats_count, ++ .get_ethtool_stats = pfe_eth_fill_stats, ++ .get_msglevel = pfe_eth_get_msglevel, ++ .set_msglevel = pfe_eth_set_msglevel, ++ .set_coalesce = pfe_eth_set_coalesce, ++ .get_coalesce = pfe_eth_get_coalesce, ++ .get_link_ksettings = pfe_eth_get_settings, ++ .set_link_ksettings = pfe_eth_set_settings, ++}; ++ ++/* pfe_eth_mdio_reset ++ */ ++int pfe_eth_mdio_reset(struct mii_bus *bus) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ u32 phy_speed; ++ ++ ++ mutex_lock(&bus->mdio_lock); ++ ++ /* ++ * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) ++ * ++ * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while ++ * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. ++ */ ++ phy_speed = (DIV_ROUND_UP((pfe->ctrl.sys_clk * 1000), 4000000) ++ << EMAC_MII_SPEED_SHIFT); ++ phy_speed |= EMAC_HOLDTIME(0x5); ++ __raw_writel(phy_speed, priv->mdio_base + EMAC_MII_CTRL_REG); ++ ++ mutex_unlock(&bus->mdio_lock); ++ ++ return 0; ++} ++ ++/* pfe_eth_mdio_timeout ++ * ++ */ ++static int pfe_eth_mdio_timeout(struct pfe_mdio_priv_s *priv, int timeout) ++{ ++ while (!(__raw_readl(priv->mdio_base + EMAC_IEVENT_REG) & ++ EMAC_IEVENT_MII)) { ++ if (timeout-- <= 0) ++ return -1; ++ usleep_range(10, 20); ++ } ++ __raw_writel(EMAC_IEVENT_MII, priv->mdio_base + EMAC_IEVENT_REG); ++ return 0; ++} ++ ++static int pfe_eth_mdio_mux(u8 muxval) ++{ ++ struct i2c_adapter *a; ++ struct i2c_msg msg; ++ unsigned char buf[2]; ++ int ret; ++ ++ a = i2c_get_adapter(0); ++ if (!a) ++ return -ENODEV; ++ ++ /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */ ++ buf[0] = 0x54; /* reg number */ ++ buf[1] = (muxval << 6) | 0x3; /* data */ ++ msg.addr = 0x66; ++ msg.buf = buf; ++ msg.len = 2; ++ msg.flags = 0; ++ ret = i2c_transfer(a, &msg, 1); ++ i2c_put_adapter(a); ++ if (ret != 1) ++ return -ENODEV; ++ return 0; ++} ++ ++static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id, ++ int dev_addr, int regnum) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ ++ __raw_writel(EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(dev_addr) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(regnum), ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ ++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { ++ dev_err(&bus->dev, "phy MDIO address write timeout\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, ++ u16 value) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ ++ /*To access external PHYs on QDS board mux needs to be configured*/ ++ if ((mii_id) && (pfe->mdio_muxval[mii_id])) ++ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); ++ ++ if (regnum & MII_ADDR_C45) { ++ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, ++ regnum & 0xffff); ++ __raw_writel(EMAC_MII_DATA_OP_CL45_WR | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ } else { ++ /* start a write op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ } ++ ++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { ++ dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum) ++{ ++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; ++ u16 value = 0; ++ ++ /*To access external PHYs on QDS board mux needs to be configured*/ ++ if ((mii_id) && (pfe->mdio_muxval[mii_id])) ++ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); ++ ++ if (regnum & MII_ADDR_C45) { ++ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, ++ regnum & 0xffff); ++ __raw_writel(EMAC_MII_DATA_OP_CL45_RD | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | ++ EMAC_MII_DATA_TA, ++ priv->mdio_base + EMAC_MII_DATA_REG); ++ } else { ++ /* start a read op */ ++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | ++ EMAC_MII_DATA_PA(mii_id) | ++ EMAC_MII_DATA_RA(regnum) | ++ EMAC_MII_DATA_TA, priv->mdio_base + ++ EMAC_MII_DATA_REG); ++ } ++ ++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { ++ dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__); ++ return -1; ++ } ++ ++ value = EMAC_MII_DATA(__raw_readl(priv->mdio_base + ++ EMAC_MII_DATA_REG)); ++ return value; ++} ++ ++static int pfe_eth_mdio_init(struct pfe *pfe, ++ struct ls1012a_pfe_platform_data *pfe_info, ++ int ii) ++{ ++ struct pfe_mdio_priv_s *priv = NULL; ++ struct ls1012a_mdio_platform_data *mdio_info; ++ struct mii_bus *bus; ++ struct device_node *mdio_node; ++ int rc = 0; ++ ++ mdio_info = (struct ls1012a_mdio_platform_data *) ++ pfe_info->ls1012a_mdio_pdata; ++ mdio_info->id = ii; ++ ++ bus = mdiobus_alloc_size(sizeof(struct pfe_mdio_priv_s)); ++ if (!bus) { ++ pr_err("mdiobus_alloc() failed\n"); ++ rc = -ENOMEM; ++ goto err_mdioalloc; ++ } ++ ++ bus->name = "ls1012a MDIO Bus"; ++ snprintf(bus->id, MII_BUS_ID_SIZE, "ls1012a-%x", mdio_info->id); ++ ++ bus->read = &pfe_eth_mdio_read; ++ bus->write = &pfe_eth_mdio_write; ++ bus->reset = &pfe_eth_mdio_reset; ++ bus->parent = pfe->dev; ++ bus->phy_mask = mdio_info->phy_mask; ++ bus->irq[0] = mdio_info->irq[0]; ++ priv = bus->priv; ++ priv->mdio_base = cbus_emac_base[ii]; ++ ++ priv->mdc_div = mdio_info->mdc_div; ++ if (!priv->mdc_div) ++ priv->mdc_div = 64; ++ ++ dev_info(bus->parent, "%s: mdc_div: %d, phy_mask: %x\n", ++ __func__, priv->mdc_div, bus->phy_mask); ++ mdio_node = of_get_child_by_name(pfe->dev->of_node, "mdio"); ++ if ((mdio_info->id == 0) && mdio_node) { ++ rc = of_mdiobus_register(bus, mdio_node); ++ of_node_put(mdio_node); ++ } else { ++ rc = mdiobus_register(bus); ++ } ++ ++ if (rc) { ++ dev_err(bus->parent, "mdiobus_register(%s) failed\n", ++ bus->name); ++ goto err_mdioregister; ++ } ++ ++ priv->mii_bus = bus; ++ pfe->mdio.mdio_priv[ii] = priv; ++ ++ pfe_eth_mdio_reset(bus); ++ ++ return 0; ++ ++err_mdioregister: ++ mdiobus_free(bus); ++err_mdioalloc: ++ return rc; ++} ++ ++/* pfe_eth_mdio_exit ++ */ ++static void pfe_eth_mdio_exit(struct pfe *pfe, ++ int ii) ++{ ++ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[ii]; ++ struct mii_bus *bus = mdio_priv->mii_bus; ++ ++ if (!bus) ++ return; ++ mdiobus_unregister(bus); ++ mdiobus_free(bus); ++} ++ ++/* pfe_get_phydev_speed ++ */ ++static int pfe_get_phydev_speed(struct phy_device *phydev) ++{ ++ switch (phydev->speed) { ++ case 10: ++ return SPEED_10M; ++ case 100: ++ return SPEED_100M; ++ case 1000: ++ default: ++ return SPEED_1000M; ++ } ++} ++ ++/* pfe_set_rgmii_speed ++ */ ++#define RGMIIPCR 0x434 ++/* RGMIIPCR bit definitions*/ ++#define SCFG_RGMIIPCR_EN_AUTO (0x00000008) ++#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004) ++#define SCFG_RGMIIPCR_SETSP_100M (0x00000000) ++#define SCFG_RGMIIPCR_SETSP_10M (0x00000002) ++#define SCFG_RGMIIPCR_SETFD (0x00000001) ++ ++#define MDIOSELCR 0x484 ++#define MDIOSEL_SERDES 0x0 ++#define MDIOSEL_EXTPHY 0x80000000 ++ ++static void pfe_set_rgmii_speed(struct phy_device *phydev) ++{ ++ u32 rgmii_pcr; ++ ++ regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr); ++ rgmii_pcr &= ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M); ++ ++ switch (phydev->speed) { ++ case 10: ++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M; ++ break; ++ case 1000: ++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M; ++ break; ++ case 100: ++ default: ++ /* Default is 100M */ ++ break; ++ } ++ regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr); ++} ++ ++/* pfe_get_phydev_duplex ++ */ ++static int pfe_get_phydev_duplex(struct phy_device *phydev) ++{ ++ /*return (phydev->duplex == DUPLEX_HALF) ? DUP_HALF:DUP_FULL ; */ ++ return DUPLEX_FULL; ++} ++ ++/* pfe_eth_adjust_link ++ */ ++static void pfe_eth_adjust_link(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ unsigned long flags; ++ struct phy_device *phydev = priv->phydev; ++ int new_state = 0; ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ++ if (phydev->link) { ++ /* ++ * Now we make sure that we can be in full duplex mode. ++ * If not, we operate in half-duplex mode. ++ */ ++ if (phydev->duplex != priv->oldduplex) { ++ new_state = 1; ++ gemac_set_duplex(priv->EMAC_baseaddr, ++ pfe_get_phydev_duplex(phydev)); ++ priv->oldduplex = phydev->duplex; ++ } ++ ++ if (phydev->speed != priv->oldspeed) { ++ new_state = 1; ++ gemac_set_speed(priv->EMAC_baseaddr, ++ pfe_get_phydev_speed(phydev)); ++ if (priv->einfo->mii_config == ++ PHY_INTERFACE_MODE_RGMII_ID) ++ pfe_set_rgmii_speed(phydev); ++ priv->oldspeed = phydev->speed; ++ } ++ ++ if (!priv->oldlink) { ++ new_state = 1; ++ priv->oldlink = 1; ++ } ++ ++ } else if (priv->oldlink) { ++ new_state = 1; ++ priv->oldlink = 0; ++ priv->oldspeed = 0; ++ priv->oldduplex = -1; ++ } ++ ++ if (new_state && netif_msg_link(priv)) ++ phy_print_status(phydev); ++ ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ /* Now, dump the details to the cdev. ++ * XXX: Locking would be required? (uniprocess arch) ++ * Or, maybe move it in spinlock above ++ */ ++ if (us && priv->einfo->gem_id < PFE_CDEV_ETH_COUNT) { ++ pr_debug("Changing link state from (%u) to (%u) for ID=(%u)\n", ++ link_states[priv->einfo->gem_id].state, ++ phydev->link, ++ priv->einfo->gem_id); ++ link_states[priv->einfo->gem_id].phy_id = priv->einfo->gem_id; ++ link_states[priv->einfo->gem_id].state = phydev->link; ++ } ++} ++ ++/* pfe_phy_exit ++ */ ++static void pfe_phy_exit(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ phy_disconnect(priv->phydev); ++ priv->phydev = NULL; ++} ++ ++/* pfe_eth_stop ++ */ ++static void pfe_eth_stop(struct net_device *ndev, int wake) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ if (wake) { ++ gemac_tx_disable(priv->EMAC_baseaddr); ++ } else { ++ gemac_disable(priv->EMAC_baseaddr); ++ gpi_disable(priv->GPI_baseaddr); ++ ++ if (priv->phydev) ++ phy_stop(priv->phydev); ++ } ++} ++ ++/* pfe_eth_start ++ */ ++static int pfe_eth_start(struct pfe_eth_priv_s *priv) ++{ ++ netif_info(priv, drv, priv->ndev, "%s\n", __func__); ++ ++ if (priv->phydev) ++ phy_start(priv->phydev); ++ ++ gpi_enable(priv->GPI_baseaddr); ++ gemac_enable(priv->EMAC_baseaddr); ++ ++ return 0; ++} ++ ++/* ++ * Configure on chip serdes through mdio ++ */ ++static void ls1012a_configure_serdes(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *eth_priv = netdev_priv(ndev); ++ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[eth_priv->id]; ++ int sgmii_2500 = 0; ++ struct mii_bus *bus = mdio_priv->mii_bus; ++ u16 value = 0; ++ ++ if (eth_priv->einfo->mii_config == PHY_INTERFACE_MODE_2500SGMII) ++ sgmii_2500 = 1; ++ ++ netif_info(eth_priv, drv, ndev, "%s\n", __func__); ++ /* PCS configuration done with corresponding GEMAC */ ++ ++ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR); ++ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR); ++ ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST); ++ ++ if (sgmii_2500) { ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS ++ | SGMII_EN); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII, ++ SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7); ++ /* Autonegotiation need to be disabled for 2.5G SGMII mode*/ ++ value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G; ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value); ++ } else { ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, ++ SGMII_SPEED_1GBPS ++ | SGMII_USE_SGMII_AN ++ | SGMII_EN); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII, ++ SGMII_DEV_ABIL_EEE_CLK_STP_EN ++ | 0xa0 ++ | SGMII_DEV_ABIL_SGMII); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400); ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0); ++ value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G; ++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value); ++ } ++} ++ ++/* ++ * pfe_phy_init ++ * ++ */ ++static int pfe_phy_init(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct phy_device *phydev; ++ char phy_id[MII_BUS_ID_SIZE + 3]; ++ char bus_id[MII_BUS_ID_SIZE]; ++ phy_interface_t interface; ++ ++ priv->oldlink = 0; ++ priv->oldspeed = 0; ++ priv->oldduplex = -1; ++ ++ snprintf(bus_id, MII_BUS_ID_SIZE, "ls1012a-%d", 0); ++ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, ++ priv->einfo->phy_id); ++ netif_info(priv, drv, ndev, "%s: %s\n", __func__, phy_id); ++ interface = priv->einfo->mii_config; ++ if ((interface == PHY_INTERFACE_MODE_SGMII) || ++ (interface == PHY_INTERFACE_MODE_2500SGMII)) { ++ /*Configure SGMII PCS */ ++ if (pfe->scfg) { ++ /* Config MDIO from serdes */ ++ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES); ++ } ++ ls1012a_configure_serdes(ndev); ++ } ++ ++ if (pfe->scfg) { ++ /*Config MDIO from PAD */ ++ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY); ++ } ++ ++ priv->oldlink = 0; ++ priv->oldspeed = 0; ++ priv->oldduplex = -1; ++ pr_info("%s interface %x\n", __func__, interface); ++ ++ if (priv->phy_node) { ++ phydev = of_phy_connect(ndev, priv->phy_node, ++ pfe_eth_adjust_link, 0, ++ priv->einfo->mii_config); ++ if (!(phydev)) { ++ netdev_err(ndev, "Unable to connect to phy\n"); ++ return -ENODEV; ++ } ++ ++ } else { ++ phydev = phy_connect(ndev, phy_id, ++ &pfe_eth_adjust_link, interface); ++ if (IS_ERR(phydev)) { ++ netdev_err(ndev, "Unable to connect to phy\n"); ++ return PTR_ERR(phydev); ++ } ++ } ++ ++ priv->phydev = phydev; ++ phydev->irq = PHY_POLL; ++ ++ return 0; ++} ++ ++/* pfe_gemac_init ++ */ ++static int pfe_gemac_init(struct pfe_eth_priv_s *priv) ++{ ++ struct gemac_cfg cfg; ++ ++ netif_info(priv, ifup, priv->ndev, "%s\n", __func__); ++ ++ cfg.mode = 0; ++ cfg.speed = SPEED_1000M; ++ cfg.duplex = DUPLEX_FULL; ++ ++ gemac_set_config(priv->EMAC_baseaddr, &cfg); ++ gemac_allow_broadcast(priv->EMAC_baseaddr); ++ gemac_enable_1536_rx(priv->EMAC_baseaddr); ++ gemac_enable_stacked_vlan(priv->EMAC_baseaddr); ++ gemac_enable_pause_rx(priv->EMAC_baseaddr); ++ gemac_set_bus_width(priv->EMAC_baseaddr, 64); ++ ++ /*GEM will perform checksum verifications*/ ++ if (priv->ndev->features & NETIF_F_RXCSUM) ++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); ++ else ++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); ++ ++ return 0; ++} ++ ++/* pfe_eth_event_handler ++ */ ++static int pfe_eth_event_handler(void *data, int event, int qno) ++{ ++ struct pfe_eth_priv_s *priv = data; ++ ++ switch (event) { ++ case EVENT_RX_PKT_IND: ++ ++ if (qno == 0) { ++ if (napi_schedule_prep(&priv->high_napi)) { ++ netif_info(priv, intr, priv->ndev, ++ "%s: schedule high prio poll\n" ++ , __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ ++ __napi_schedule(&priv->high_napi); ++ } ++ } else if (qno == 1) { ++ if (napi_schedule_prep(&priv->low_napi)) { ++ netif_info(priv, intr, priv->ndev, ++ "%s: schedule low prio poll\n" ++ , __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ __napi_schedule(&priv->low_napi); ++ } ++ } else if (qno == 2) { ++ if (napi_schedule_prep(&priv->lro_napi)) { ++ netif_info(priv, intr, priv->ndev, ++ "%s: schedule lro prio poll\n" ++ , __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ __napi_schedule(&priv->lro_napi); ++ } ++ } ++ ++ break; ++ ++ case EVENT_TXDONE_IND: ++ pfe_eth_flush_tx(priv); ++ hif_lib_event_handler_start(&priv->client, EVENT_TXDONE_IND, 0); ++ break; ++ case EVENT_HIGH_RX_WM: ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ ndev->mtu = new_mtu; ++ new_mtu += ETH_HLEN + ETH_FCS_LEN; ++ gemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu); ++ ++ return 0; ++} ++ ++/* pfe_eth_open ++ */ ++static int pfe_eth_open(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct hif_client_s *client; ++ int rc; ++ ++ netif_info(priv, ifup, ndev, "%s\n", __func__); ++ ++ /* Register client driver with HIF */ ++ client = &priv->client; ++ memset(client, 0, sizeof(*client)); ++ client->id = PFE_CL_GEM0 + priv->id; ++ client->tx_qn = emac_txq_cnt; ++ client->rx_qn = EMAC_RXQ_CNT; ++ client->priv = priv; ++ client->pfe = priv->pfe; ++ client->event_handler = pfe_eth_event_handler; ++ ++ client->tx_qsize = EMAC_TXQ_DEPTH; ++ client->rx_qsize = EMAC_RXQ_DEPTH; ++ ++ rc = hif_lib_client_register(client); ++ if (rc) { ++ netdev_err(ndev, "%s: hif_lib_client_register(%d) failed\n", ++ __func__, client->id); ++ goto err0; ++ } ++ ++ netif_info(priv, drv, ndev, "%s: registered client: %p\n", __func__, ++ client); ++ ++ pfe_gemac_init(priv); ++ ++ if (!is_valid_ether_addr(ndev->dev_addr)) { ++ netdev_err(ndev, "%s: invalid MAC address\n", __func__); ++ rc = -EADDRNOTAVAIL; ++ goto err1; ++ } ++ ++ gemac_set_laddrN(priv->EMAC_baseaddr, ++ (struct pfe_mac_addr *)ndev->dev_addr, 1); ++ ++ napi_enable(&priv->high_napi); ++ napi_enable(&priv->low_napi); ++ napi_enable(&priv->lro_napi); ++ ++ rc = pfe_eth_start(priv); ++ ++ netif_tx_wake_all_queues(ndev); ++ ++ return rc; ++ ++err1: ++ hif_lib_client_unregister(&priv->client); ++ ++err0: ++ return rc; ++} ++ ++/* ++ * pfe_eth_shutdown ++ */ ++int pfe_eth_shutdown(struct net_device *ndev, int wake) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int i, qstatus, id; ++ unsigned long next_poll = jiffies + 1, end = jiffies + ++ (TX_POLL_TIMEOUT_MS * HZ) / 1000; ++ int tx_pkts, prv_tx_pkts; ++ ++ netif_info(priv, ifdown, ndev, "%s\n", __func__); ++ ++ for (i = 0; i < emac_txq_cnt; i++) ++ hrtimer_cancel(&priv->fast_tx_timeout[i].timer); ++ ++ netif_tx_stop_all_queues(ndev); ++ ++ do { ++ tx_pkts = 0; ++ pfe_eth_flush_tx(priv); ++ ++ for (i = 0; i < emac_txq_cnt; i++) ++ tx_pkts += hif_lib_tx_pending(&priv->client, i); ++ ++ if (tx_pkts) { ++ /*Don't wait forever, break if we cross max timeout */ ++ if (time_after(jiffies, end)) { ++ pr_err( ++ "(%s)Tx is not complete after %dmsec\n", ++ ndev->name, TX_POLL_TIMEOUT_MS); ++ break; ++ } ++ ++ pr_info("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n" ++ , __func__, ndev->name, tx_pkts); ++ if (need_resched()) ++ schedule(); ++ } ++ ++ } while (tx_pkts); ++ ++ end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000; ++ ++ prv_tx_pkts = tmu_pkts_processed(priv->id); ++ /* ++ * Wait till TMU transmits all pending packets ++ * poll tmu_qstatus and pkts processed by TMU for every 10ms ++ * Consider TMU is busy, If we see TMU qeueu pending or any packets ++ * processed by TMU ++ */ ++ while (1) { ++ if (time_after(jiffies, next_poll)) { ++ tx_pkts = tmu_pkts_processed(priv->id); ++ qstatus = tmu_qstatus(priv->id) & 0x7ffff; ++ ++ if (!qstatus && (tx_pkts == prv_tx_pkts)) ++ break; ++ /* Don't wait forever, break if we cross max ++ * timeout(TX_POLL_TIMEOUT_MS) ++ */ ++ if (time_after(jiffies, end)) { ++ pr_err("TMU%d is busy after %dmsec\n", ++ priv->id, TX_POLL_TIMEOUT_MS); ++ break; ++ } ++ prv_tx_pkts = tx_pkts; ++ next_poll++; ++ } ++ if (need_resched()) ++ schedule(); ++ } ++ /* Wait for some more time to complete transmitting packet if any */ ++ next_poll = jiffies + 1; ++ while (1) { ++ if (time_after(jiffies, next_poll)) ++ break; ++ if (need_resched()) ++ schedule(); ++ } ++ ++ pfe_eth_stop(ndev, wake); ++ ++ napi_disable(&priv->lro_napi); ++ napi_disable(&priv->low_napi); ++ napi_disable(&priv->high_napi); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ pe_dmem_write(id, 0, CLASS_DM_CRC_VALIDATED ++ + (priv->id * 4), 4); ++ } ++ ++ hif_lib_client_unregister(&priv->client); ++ ++ return 0; ++} ++ ++/* pfe_eth_close ++ * ++ */ ++static int pfe_eth_close(struct net_device *ndev) ++{ ++ pfe_eth_shutdown(ndev, 0); ++ ++ return 0; ++} ++ ++/* pfe_eth_suspend ++ * ++ * return value : 1 if netdevice is configured to wakeup system ++ * 0 otherwise ++ */ ++int pfe_eth_suspend(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int retval = 0; ++ ++ if (priv->wol) { ++ gemac_set_wol(priv->EMAC_baseaddr, priv->wol); ++ retval = 1; ++ } ++ pfe_eth_shutdown(ndev, priv->wol); ++ ++ return retval; ++} ++ ++/* pfe_eth_resume ++ * ++ */ ++int pfe_eth_resume(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ if (priv->wol) ++ gemac_set_wol(priv->EMAC_baseaddr, 0); ++ gemac_tx_enable(priv->EMAC_baseaddr); ++ ++ return pfe_eth_open(ndev); ++} ++ ++/* pfe_eth_get_queuenum ++ */ ++static int pfe_eth_get_queuenum(struct pfe_eth_priv_s *priv, struct sk_buff ++ *skb) ++{ ++ int queuenum = 0; ++ unsigned long flags; ++ ++ /* Get the Fast Path queue number */ ++ /* ++ * Use conntrack mark (if conntrack exists), then packet mark (if any), ++ * then fallback to default ++ */ ++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK) ++ if (skb->_nfct) { ++ enum ip_conntrack_info cinfo; ++ struct nf_conn *ct; ++ ++ ct = nf_ct_get(skb, &cinfo); ++ ++ if (ct) { ++ u32 connmark; ++ ++ connmark = ct->mark; ++ ++ if ((connmark & 0x80000000) && priv->id != 0) ++ connmark >>= 16; ++ ++ queuenum = connmark & EMAC_QUEUENUM_MASK; ++ } ++ } else {/* continued after #endif ... */ ++#endif ++ if (skb->mark) { ++ queuenum = skb->mark & EMAC_QUEUENUM_MASK; ++ } else { ++ spin_lock_irqsave(&priv->lock, flags); ++ queuenum = priv->default_priority & EMAC_QUEUENUM_MASK; ++ spin_unlock_irqrestore(&priv->lock, flags); ++ } ++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK) ++ } ++#endif ++ return queuenum; ++} ++ ++/* pfe_eth_might_stop_tx ++ * ++ */ ++static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum, ++ struct netdev_queue *tx_queue, ++ unsigned int n_desc, ++ unsigned int n_segs) ++{ ++ ktime_t kt; ++ int tried = 0; ++ ++try_again: ++ if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) || ++ (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) || ++ (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) { ++ if (!tried) { ++ __hif_lib_update_credit(&priv->client, queuenum); ++ tried = 1; ++ goto try_again; ++ } ++#ifdef PFE_ETH_TX_STATS ++ if (__hif_tx_avail(&pfe->hif) < n_desc) { ++ priv->stop_queue_hif[queuenum]++; ++ } else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) { ++ priv->stop_queue_hif_client[queuenum]++; ++ } else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < ++ n_segs) { ++ priv->stop_queue_credit[queuenum]++; ++ } ++ priv->stop_queue_total[queuenum]++; ++#endif ++ netif_tx_stop_queue(tx_queue); ++ ++ kt = ktime_set(0, LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS * ++ NSEC_PER_MSEC); ++ hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt, ++ HRTIMER_MODE_REL); ++ return -1; ++ } else { ++ return 0; ++ } ++} ++ ++#define SA_MAX_OP 2 ++/* pfe_hif_send_packet ++ * ++ * At this level if TX fails we drop the packet ++ */ ++static void pfe_hif_send_packet(struct sk_buff *skb, struct pfe_eth_priv_s ++ *priv, int queuenum) ++{ ++ struct skb_shared_info *sh = skb_shinfo(skb); ++ unsigned int nr_frags; ++ u32 ctrl = 0; ++ ++ netif_info(priv, tx_queued, priv->ndev, "%s\n", __func__); ++ ++ if (skb_is_gso(skb)) { ++ priv->stats.tx_dropped++; ++ return; ++ } ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ ctrl = HIF_CTRL_TX_CHECKSUM; ++ ++ nr_frags = sh->nr_frags; ++ ++ if (nr_frags) { ++ skb_frag_t *f; ++ int i; ++ ++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, ++ skb_headlen(skb), ctrl, HIF_FIRST_BUFFER, ++ skb); ++ ++ for (i = 0; i < nr_frags - 1; i++) { ++ f = &sh->frags[i]; ++ __hif_lib_xmit_pkt(&priv->client, queuenum, ++ skb_frag_address(f), ++ skb_frag_size(f), ++ 0x0, 0x0, skb); ++ } ++ ++ f = &sh->frags[i]; ++ ++ __hif_lib_xmit_pkt(&priv->client, queuenum, ++ skb_frag_address(f), skb_frag_size(f), ++ 0x0, HIF_LAST_BUFFER | HIF_DATA_VALID, ++ skb); ++ ++ netif_info(priv, tx_queued, priv->ndev, ++ "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n", ++ __func__, skb, nr_frags, skb->len); ++ } else { ++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, ++ skb->len, ctrl, HIF_FIRST_BUFFER | ++ HIF_LAST_BUFFER | HIF_DATA_VALID, ++ skb); ++ netif_info(priv, tx_queued, priv->ndev, ++ "%s: pkt sent successfully skb:%p len:%d\n", ++ __func__, skb, skb->len); ++ } ++ hif_tx_dma_start(); ++ priv->stats.tx_packets++; ++ priv->stats.tx_bytes += skb->len; ++ hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1); ++} ++ ++/* pfe_eth_flush_txQ ++ */ ++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int ++ from_tx, int n_desc) ++{ ++ struct sk_buff *skb; ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ tx_q_num); ++ unsigned int flags; ++ ++ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__); ++ ++ if (!from_tx) ++ __netif_tx_lock_bh(tx_queue); ++ ++ /* Clean HIF and client queue */ ++ while ((skb = hif_lib_tx_get_next_complete(&priv->client, ++ tx_q_num, &flags, ++ HIF_TX_DESC_NT))) { ++ if (flags & HIF_DATA_VALID) ++ dev_kfree_skb_any(skb); ++ } ++ if (!from_tx) ++ __netif_tx_unlock_bh(tx_queue); ++} ++ ++/* pfe_eth_flush_tx ++ */ ++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv) ++{ ++ int ii; ++ ++ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__); ++ ++ for (ii = 0; ii < emac_txq_cnt; ii++) { ++ pfe_eth_flush_txQ(priv, ii, 0, 0); ++ __hif_lib_update_credit(&priv->client, ii); ++ } ++} ++ ++void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int ++ *n_segs) ++{ ++ struct skb_shared_info *sh = skb_shinfo(skb); ++ ++ /* Scattered data */ ++ if (sh->nr_frags) { ++ *n_desc = sh->nr_frags + 1; ++ *n_segs = 1; ++ /* Regular case */ ++ } else { ++ *n_desc = 1; ++ *n_segs = 1; ++ } ++} ++ ++/* pfe_eth_send_packet ++ */ ++static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int tx_q_num = skb_get_queue_mapping(skb); ++ int n_desc, n_segs; ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ tx_q_num); ++ ++ netif_info(priv, tx_queued, ndev, "%s\n", __func__); ++ ++ if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ + ++ sizeof(unsigned long)))) { ++ netif_warn(priv, tx_err, priv->ndev, "%s: copying skb\n", ++ __func__); ++ ++ if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned ++ long)), 0, GFP_ATOMIC)) { ++ /* No need to re-transmit, no way to recover*/ ++ kfree_skb(skb); ++ priv->stats.tx_dropped++; ++ return NETDEV_TX_OK; ++ } ++ } ++ ++ pfe_tx_get_req_desc(skb, &n_desc, &n_segs); ++ ++ hif_tx_lock(&pfe->hif); ++ if (unlikely(pfe_eth_might_stop_tx(priv, tx_q_num, tx_queue, n_desc, ++ n_segs))) { ++#ifdef PFE_ETH_TX_STATS ++ if (priv->was_stopped[tx_q_num]) { ++ priv->clean_fail[tx_q_num]++; ++ priv->was_stopped[tx_q_num] = 0; ++ } ++#endif ++ hif_tx_unlock(&pfe->hif); ++ return NETDEV_TX_BUSY; ++ } ++ ++ pfe_hif_send_packet(skb, priv, tx_q_num); ++ ++ hif_tx_unlock(&pfe->hif); ++ ++ tx_queue->trans_start = jiffies; ++ ++#ifdef PFE_ETH_TX_STATS ++ priv->was_stopped[tx_q_num] = 0; ++#endif ++ ++ return NETDEV_TX_OK; ++} ++ ++/* pfe_eth_select_queue ++ * ++ */ ++static u16 pfe_eth_select_queue(struct net_device *ndev, struct sk_buff *skb, ++ struct net_device *sb_dev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ return pfe_eth_get_queuenum(priv, skb); ++} ++ ++/* pfe_eth_get_stats ++ */ ++static struct net_device_stats *pfe_eth_get_stats(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ return &priv->stats; ++} ++ ++/* pfe_eth_set_mac_address ++ */ ++static int pfe_eth_set_mac_address(struct net_device *ndev, void *addr) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct sockaddr *sa = addr; ++ ++ netif_info(priv, drv, ndev, "%s\n", __func__); ++ ++ if (!is_valid_ether_addr(sa->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy(ndev->dev_addr, sa->sa_data, ETH_ALEN); ++ ++ gemac_set_laddrN(priv->EMAC_baseaddr, ++ (struct pfe_mac_addr *)ndev->dev_addr, 1); ++ ++ return 0; ++} ++ ++/* pfe_eth_enet_addr_byte_mac ++ */ ++int pfe_eth_enet_addr_byte_mac(u8 *enet_byte_addr, ++ struct pfe_mac_addr *enet_addr) ++{ ++ if (!enet_byte_addr || !enet_addr) { ++ return -1; ++ ++ } else { ++ enet_addr->bottom = enet_byte_addr[0] | ++ (enet_byte_addr[1] << 8) | ++ (enet_byte_addr[2] << 16) | ++ (enet_byte_addr[3] << 24); ++ enet_addr->top = enet_byte_addr[4] | ++ (enet_byte_addr[5] << 8); ++ return 0; ++ } ++} ++ ++/* pfe_eth_set_multi ++ */ ++static void pfe_eth_set_multi(struct net_device *ndev) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ struct pfe_mac_addr hash_addr; /* hash register structure */ ++ /* specific mac address register structure */ ++ struct pfe_mac_addr spec_addr; ++ int result; /* index into hash register to set.. */ ++ int uc_count = 0; ++ struct netdev_hw_addr *ha; ++ ++ if (ndev->flags & IFF_PROMISC) { ++ netif_info(priv, drv, ndev, "entering promiscuous mode\n"); ++ ++ priv->promisc = 1; ++ gemac_enable_copy_all(priv->EMAC_baseaddr); ++ } else { ++ priv->promisc = 0; ++ gemac_disable_copy_all(priv->EMAC_baseaddr); ++ } ++ ++ /* Enable broadcast frame reception if required. */ ++ if (ndev->flags & IFF_BROADCAST) { ++ gemac_allow_broadcast(priv->EMAC_baseaddr); ++ } else { ++ netif_info(priv, drv, ndev, ++ "disabling broadcast frame reception\n"); ++ ++ gemac_no_broadcast(priv->EMAC_baseaddr); ++ } ++ ++ if (ndev->flags & IFF_ALLMULTI) { ++ /* Set the hash to rx all multicast frames */ ++ hash_addr.bottom = 0xFFFFFFFF; ++ hash_addr.top = 0xFFFFFFFF; ++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); ++ netdev_for_each_uc_addr(ha, ndev) { ++ if (uc_count >= MAX_UC_SPEC_ADDR_REG) ++ break; ++ pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr); ++ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr, ++ uc_count + 2); ++ uc_count++; ++ } ++ } else if ((netdev_mc_count(ndev) > 0) || (netdev_uc_count(ndev))) { ++ u8 *addr; ++ ++ hash_addr.bottom = 0; ++ hash_addr.top = 0; ++ ++ netdev_for_each_mc_addr(ha, ndev) { ++ addr = ha->addr; ++ ++ netif_info(priv, drv, ndev, ++ "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n", ++ addr[0], addr[1], addr[2], ++ addr[3], addr[4], addr[5]); ++ ++ result = pfe_eth_get_hash(addr); ++ ++ if (result < EMAC_HASH_REG_BITS) { ++ if (result < 32) ++ hash_addr.bottom |= (1 << result); ++ else ++ hash_addr.top |= (1 << (result - 32)); ++ } else { ++ break; ++ } ++ } ++ ++ uc_count = -1; ++ netdev_for_each_uc_addr(ha, ndev) { ++ addr = ha->addr; ++ ++ if (++uc_count < MAX_UC_SPEC_ADDR_REG) { ++ netdev_info(ndev, ++ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n", ++ addr[0], addr[1], addr[2], ++ addr[3], addr[4], addr[5]); ++ pfe_eth_enet_addr_byte_mac(addr, &spec_addr); ++ gemac_set_laddrN(priv->EMAC_baseaddr, ++ &spec_addr, uc_count + 2); ++ } else { ++ netif_info(priv, drv, ndev, ++ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n", ++ addr[0], addr[1], addr[2], ++ addr[3], addr[4], addr[5]); ++ ++ result = pfe_eth_get_hash(addr); ++ if (result >= EMAC_HASH_REG_BITS) { ++ break; ++ ++ } else { ++ if (result < 32) ++ hash_addr.bottom |= (1 << ++ result); ++ else ++ hash_addr.top |= (1 << ++ (result - 32)); ++ } ++ } ++ } ++ ++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); ++ } ++ ++ if (!(netdev_uc_count(ndev) >= MAX_UC_SPEC_ADDR_REG)) { ++ /* ++ * Check if there are any specific address HW registers that ++ * need to be flushed ++ */ ++ for (uc_count = netdev_uc_count(ndev); uc_count < ++ MAX_UC_SPEC_ADDR_REG; uc_count++) ++ gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2); ++ } ++ ++ if (ndev->flags & IFF_LOOPBACK) ++ gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL); ++} ++ ++/* pfe_eth_set_features ++ */ ++static int pfe_eth_set_features(struct net_device *ndev, netdev_features_t ++ features) ++{ ++ struct pfe_eth_priv_s *priv = netdev_priv(ndev); ++ int rc = 0; ++ ++ if (features & NETIF_F_RXCSUM) ++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); ++ else ++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); ++ return rc; ++} ++ ++/* pfe_eth_fast_tx_timeout ++ */ ++static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer) ++{ ++ struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct ++ pfe_eth_fast_timer, ++ timer); ++ struct pfe_eth_priv_s *priv = container_of(fast_tx_timeout->base, ++ struct pfe_eth_priv_s, ++ fast_tx_timeout); ++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, ++ fast_tx_timeout->queuenum); ++ ++ if (netif_tx_queue_stopped(tx_queue)) { ++#ifdef PFE_ETH_TX_STATS ++ priv->was_stopped[fast_tx_timeout->queuenum] = 1; ++#endif ++ netif_tx_wake_queue(tx_queue); ++ } ++ ++ return HRTIMER_NORESTART; ++} ++ ++/* pfe_eth_fast_tx_timeout_init ++ */ ++static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv) ++{ ++ int i; ++ ++ for (i = 0; i < emac_txq_cnt; i++) { ++ priv->fast_tx_timeout[i].queuenum = i; ++ hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC, ++ HRTIMER_MODE_REL); ++ priv->fast_tx_timeout[i].timer.function = ++ pfe_eth_fast_tx_timeout; ++ priv->fast_tx_timeout[i].base = priv->fast_tx_timeout; ++ } ++} ++ ++static struct sk_buff *pfe_eth_rx_skb(struct net_device *ndev, ++ struct pfe_eth_priv_s *priv, ++ unsigned int qno) ++{ ++ void *buf_addr; ++ unsigned int rx_ctrl; ++ unsigned int desc_ctrl = 0; ++ struct hif_ipsec_hdr *ipsec_hdr = NULL; ++ struct sk_buff *skb; ++ struct sk_buff *skb_frag, *skb_frag_last = NULL; ++ int length = 0, offset; ++ ++ skb = priv->skb_inflight[qno]; ++ ++ if (skb) { ++ skb_frag_last = skb_shinfo(skb)->frag_list; ++ if (skb_frag_last) { ++ while (skb_frag_last->next) ++ skb_frag_last = skb_frag_last->next; ++ } ++ } ++ ++ while (!(desc_ctrl & CL_DESC_LAST)) { ++ buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length, ++ &offset, &rx_ctrl, &desc_ctrl, ++ (void **)&ipsec_hdr); ++ if (!buf_addr) ++ goto incomplete; ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_DESC_COUNT]++; ++#endif ++ ++ /* First frag */ ++ if (desc_ctrl & CL_DESC_FIRST) { ++ skb = build_skb(buf_addr, 0); ++ if (unlikely(!skb)) ++ goto pkt_drop; ++ ++ skb_reserve(skb, offset); ++ skb_put(skb, length); ++ skb->dev = ndev; ++ ++ if ((ndev->features & NETIF_F_RXCSUM) && (rx_ctrl & ++ HIF_CTRL_RX_CHECKSUMMED)) ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ else ++ skb_checksum_none_assert(skb); ++ ++ } else { ++ /* Next frags */ ++ if (unlikely(!skb)) { ++ pr_err("%s: NULL skb_inflight\n", ++ __func__); ++ goto pkt_drop; ++ } ++ ++ skb_frag = build_skb(buf_addr, 0); ++ ++ if (unlikely(!skb_frag)) { ++ kfree(buf_addr); ++ goto pkt_drop; ++ } ++ ++ skb_reserve(skb_frag, offset); ++ skb_put(skb_frag, length); ++ ++ skb_frag->dev = ndev; ++ ++ if (skb_shinfo(skb)->frag_list) ++ skb_frag_last->next = skb_frag; ++ else ++ skb_shinfo(skb)->frag_list = skb_frag; ++ ++ skb->truesize += skb_frag->truesize; ++ skb->data_len += length; ++ skb->len += length; ++ skb_frag_last = skb_frag; ++ } ++ } ++ ++ priv->skb_inflight[qno] = NULL; ++ return skb; ++ ++incomplete: ++ priv->skb_inflight[qno] = skb; ++ return NULL; ++ ++pkt_drop: ++ priv->skb_inflight[qno] = NULL; ++ ++ if (skb) ++ kfree_skb(skb); ++ else ++ kfree(buf_addr); ++ ++ priv->stats.rx_errors++; ++ ++ return NULL; ++} ++ ++/* pfe_eth_poll ++ */ ++static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi, ++ unsigned int qno, int budget) ++{ ++ struct net_device *ndev = priv->ndev; ++ struct sk_buff *skb; ++ int work_done = 0; ++ unsigned int len; ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_POLL_COUNT]++; ++#endif ++ ++ do { ++ skb = pfe_eth_rx_skb(ndev, priv, qno); ++ ++ if (!skb) ++ break; ++ ++ len = skb->len; ++ ++ /* Packet will be processed */ ++ skb->protocol = eth_type_trans(skb, ndev); ++ ++ netif_receive_skb(skb); ++ ++ priv->stats.rx_packets++; ++ priv->stats.rx_bytes += len; ++ ++ work_done++; ++ ++#ifdef PFE_ETH_NAPI_STATS ++ priv->napi_counters[NAPI_PACKET_COUNT]++; ++#endif ++ ++ } while (work_done < budget); ++ ++ /* ++ * If no Rx receive nor cleanup work was done, exit polling mode. ++ * No more netif_running(dev) check is required here , as this is ++ * checked in net/core/dev.c (2.6.33.5 kernel specific). ++ */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ ++ hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND, ++ qno); ++ } ++#ifdef PFE_ETH_NAPI_STATS ++ else ++ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++; ++#endif ++ ++ return work_done; ++} ++ ++/* ++ * pfe_eth_lro_poll ++ */ ++static int pfe_eth_lro_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, ++ lro_napi); ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++ return pfe_eth_poll(priv, napi, 2, budget); ++} ++ ++/* pfe_eth_low_poll ++ */ ++static int pfe_eth_low_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, ++ low_napi); ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++ return pfe_eth_poll(priv, napi, 1, budget); ++} ++ ++/* pfe_eth_high_poll ++ */ ++static int pfe_eth_high_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, ++ high_napi); ++ ++ netif_info(priv, intr, priv->ndev, "%s\n", __func__); ++ ++ return pfe_eth_poll(priv, napi, 0, budget); ++} ++ ++static const struct net_device_ops pfe_netdev_ops = { ++ .ndo_open = pfe_eth_open, ++ .ndo_stop = pfe_eth_close, ++ .ndo_start_xmit = pfe_eth_send_packet, ++ .ndo_select_queue = pfe_eth_select_queue, ++ .ndo_set_rx_mode = pfe_eth_set_multi, ++ .ndo_set_mac_address = pfe_eth_set_mac_address, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_change_mtu = pfe_eth_change_mtu, ++ .ndo_get_stats = pfe_eth_get_stats, ++ .ndo_set_features = pfe_eth_set_features, ++}; ++ ++/* pfe_eth_init_one ++ */ ++static int pfe_eth_init_one(struct pfe *pfe, ++ struct ls1012a_pfe_platform_data *pfe_info, ++ int id) ++{ ++ struct net_device *ndev = NULL; ++ struct pfe_eth_priv_s *priv = NULL; ++ struct ls1012a_eth_platform_data *einfo; ++ int err; ++ ++ einfo = (struct ls1012a_eth_platform_data *) ++ pfe_info->ls1012a_eth_pdata; ++ ++ /* einfo never be NULL, but no harm in having this check */ ++ if (!einfo) { ++ pr_err( ++ "%s: pfe missing additional gemacs platform data\n" ++ , __func__); ++ err = -ENODEV; ++ goto err0; ++ } ++ ++ if (us) ++ emac_txq_cnt = EMAC_TXQ_CNT; ++ /* Create an ethernet device instance */ ++ ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt); ++ ++ if (!ndev) { ++ pr_err("%s: gemac %d device allocation failed\n", ++ __func__, einfo[id].gem_id); ++ err = -ENOMEM; ++ goto err0; ++ } ++ ++ priv = netdev_priv(ndev); ++ priv->ndev = ndev; ++ priv->id = einfo[id].gem_id; ++ priv->pfe = pfe; ++ priv->phy_node = einfo[id].phy_node; ++ ++ SET_NETDEV_DEV(priv->ndev, priv->pfe->dev); ++ ++ pfe->eth.eth_priv[id] = priv; ++ ++ /* Set the info in the priv to the current info */ ++ priv->einfo = &einfo[id]; ++ priv->EMAC_baseaddr = cbus_emac_base[id]; ++ priv->GPI_baseaddr = cbus_gpi_base[id]; ++ ++ spin_lock_init(&priv->lock); ++ ++ pfe_eth_fast_tx_timeout_init(priv); ++ ++ /* Copy the station address into the dev structure, */ ++ memcpy(ndev->dev_addr, einfo[id].mac_addr, ETH_ALEN); ++ ++ if (us) ++ goto phy_init; ++ ++ ndev->mtu = 1500; ++ ++ /* Set MTU limits */ ++ ndev->min_mtu = ETH_MIN_MTU; ++ ++/* ++ * Jumbo frames are not supported on LS1012A rev-1.0. ++ * So max mtu should be restricted to supported frame length. ++ */ ++ if (pfe_errata_a010897) ++ ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN; ++ else ++ ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN; ++ ++ /*Enable after checksum offload is validated */ ++ ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | ++ NETIF_F_IPV6_CSUM | NETIF_F_SG; ++ ++ /* enabled by default */ ++ ndev->features = ndev->hw_features; ++ ++ priv->usr_features = ndev->features; ++ ++ ndev->netdev_ops = &pfe_netdev_ops; ++ ++ ndev->ethtool_ops = &pfe_ethtool_ops; ++ ++ /* Enable basic messages by default */ ++ priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK | ++ NETIF_MSG_PROBE; ++ ++ netif_napi_add(ndev, &priv->low_napi, pfe_eth_low_poll, ++ HIF_RX_POLL_WEIGHT - 16); ++ netif_napi_add(ndev, &priv->high_napi, pfe_eth_high_poll, ++ HIF_RX_POLL_WEIGHT - 16); ++ netif_napi_add(ndev, &priv->lro_napi, pfe_eth_lro_poll, ++ HIF_RX_POLL_WEIGHT - 16); ++ ++ err = register_netdev(ndev); ++ if (err) { ++ netdev_err(ndev, "register_netdev() failed\n"); ++ goto err1; ++ } ++ ++ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) || ++ ((pfe_use_old_dts_phy) && ++ (priv->einfo->phy_flags & GEMAC_NO_PHY))) { ++ pr_info("%s: No PHY or fixed-link\n", __func__); ++ goto skip_phy_init; ++ } ++ ++phy_init: ++ device_init_wakeup(&ndev->dev, WAKE_MAGIC); ++ ++ err = pfe_phy_init(ndev); ++ if (err) { ++ netdev_err(ndev, "%s: pfe_phy_init() failed\n", ++ __func__); ++ goto err2; ++ } ++ ++ if (us) { ++ if (priv->phydev) ++ phy_start(priv->phydev); ++ return 0; ++ } ++ ++ netif_carrier_on(ndev); ++ ++skip_phy_init: ++ /* Create all the sysfs files */ ++ if (pfe_eth_sysfs_init(ndev)) ++ goto err3; ++ ++ netif_info(priv, probe, ndev, "%s: created interface, baseaddr: %p\n", ++ __func__, priv->EMAC_baseaddr); ++ ++ return 0; ++ ++err3: ++ pfe_phy_exit(priv->ndev); ++err2: ++ if (us) ++ goto err1; ++ unregister_netdev(ndev); ++err1: ++ free_netdev(priv->ndev); ++err0: ++ return err; ++} ++ ++/* pfe_eth_init ++ */ ++int pfe_eth_init(struct pfe *pfe) ++{ ++ int ii = 0; ++ int err; ++ struct ls1012a_pfe_platform_data *pfe_info; ++ ++ pr_info("%s\n", __func__); ++ ++ cbus_emac_base[0] = EMAC1_BASE_ADDR; ++ cbus_emac_base[1] = EMAC2_BASE_ADDR; ++ ++ cbus_gpi_base[0] = EGPI1_BASE_ADDR; ++ cbus_gpi_base[1] = EGPI2_BASE_ADDR; ++ ++ pfe_info = (struct ls1012a_pfe_platform_data *) ++ pfe->dev->platform_data; ++ if (!pfe_info) { ++ pr_err("%s: pfe missing additional platform data\n", __func__); ++ err = -ENODEV; ++ goto err_pdata; ++ } ++ ++ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) { ++ err = pfe_eth_mdio_init(pfe, pfe_info, ii); ++ if (err) { ++ pr_err("%s: pfe_eth_mdio_init() failed\n", __func__); ++ goto err_mdio_init; ++ } ++ } ++ ++ if (soc_device_match(ls1012a_rev1_soc_attr)) ++ pfe_errata_a010897 = true; ++ else ++ pfe_errata_a010897 = false; ++ ++ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) { ++ err = pfe_eth_init_one(pfe, pfe_info, ii); ++ if (err) ++ goto err_eth_init; ++ } ++ ++ return 0; ++ ++err_eth_init: ++ while (ii--) { ++ pfe_eth_exit_one(pfe->eth.eth_priv[ii]); ++ pfe_eth_mdio_exit(pfe, ii); ++ } ++ ++err_mdio_init: ++err_pdata: ++ return err; ++} ++ ++/* pfe_eth_exit_one ++ */ ++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv) ++{ ++ netif_info(priv, probe, priv->ndev, "%s\n", __func__); ++ ++ if (!us) ++ pfe_eth_sysfs_exit(priv->ndev); ++ ++ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) || ++ ((pfe_use_old_dts_phy) && ++ (priv->einfo->phy_flags & GEMAC_NO_PHY))) { ++ pr_info("%s: No PHY or fixed-link\n", __func__); ++ goto skip_phy_exit; ++ } ++ ++ pfe_phy_exit(priv->ndev); ++ ++skip_phy_exit: ++ if (!us) ++ unregister_netdev(priv->ndev); ++ ++ free_netdev(priv->ndev); ++} ++ ++/* pfe_eth_exit ++ */ ++void pfe_eth_exit(struct pfe *pfe) ++{ ++ int ii; ++ ++ pr_info("%s\n", __func__); ++ ++ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--) ++ pfe_eth_exit_one(pfe->eth.eth_priv[ii]); ++ ++ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--) ++ pfe_eth_mdio_exit(pfe, ii); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_eth.h +@@ -0,0 +1,175 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_ETH_H_ ++#define _PFE_ETH_H_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFE_ETH_NAPI_STATS ++#define PFE_ETH_TX_STATS ++ ++#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE) ++#define LRO_LEN_COUNT_MAX 32 ++#define LRO_NB_COUNT_MAX 32 ++ ++#define PFE_PAUSE_FLAG_ENABLE 1 ++#define PFE_PAUSE_FLAG_AUTONEG 2 ++ ++/* GEMAC configured by SW */ ++/* GEMAC configured by phy lines (not for MII/GMII) */ ++ ++#define GEMAC_SW_FULL_DUPLEX BIT(9) ++#define GEMAC_SW_SPEED_10M (0 << 12) ++#define GEMAC_SW_SPEED_100M BIT(12) ++#define GEMAC_SW_SPEED_1G (2 << 12) ++ ++#define GEMAC_NO_PHY BIT(0) ++ ++struct ls1012a_eth_platform_data { ++ /* board specific information */ ++ phy_interface_t mii_config; ++ u32 phy_flags; ++ u32 gem_id; ++ u32 phy_id; ++ u32 mdio_muxval; ++ u8 mac_addr[ETH_ALEN]; ++ struct device_node *phy_node; ++}; ++ ++struct ls1012a_mdio_platform_data { ++ int id; ++ int irq[32]; ++ u32 phy_mask; ++ int mdc_div; ++}; ++ ++struct ls1012a_pfe_platform_data { ++ struct ls1012a_eth_platform_data ls1012a_eth_pdata[3]; ++ struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3]; ++}; ++ ++#define NUM_GEMAC_SUPPORT 2 ++#define DRV_NAME "pfe-eth" ++#define DRV_VERSION "1.0" ++ ++#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS 3 ++#define TX_POLL_TIMEOUT_MS 1000 ++ ++#define EMAC_TXQ_CNT 16 ++#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT) ++ ++#define JUMBO_FRAME_SIZE_V1 1900 ++#define JUMBO_FRAME_SIZE_V2 10258 ++/* ++ * Client Tx queue threshold, for txQ flush condition. ++ * It must be smaller than the queue size (in case we ever change it in the ++ * future). ++ */ ++#define HIF_CL_TX_FLUSH_MARK 32 ++ ++/* ++ * Max number of TX resources (HIF descriptors or skbs) that will be released ++ * in a single go during batch recycling. ++ * Should be lower than the flush mark so the SW can provide the HW with a ++ * continuous stream of packets instead of bursts. ++ */ ++#define TX_FREE_MAX_COUNT 16 ++#define EMAC_RXQ_CNT 3 ++#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT ++/* make sure clients can receive a full burst of packets */ ++#define EMAC_RMON_TXBYTES_POS 0x00 ++#define EMAC_RMON_RXBYTES_POS 0x14 ++ ++#define EMAC_QUEUENUM_MASK (emac_txq_cnt - 1) ++#define EMAC_MDIO_TIMEOUT 1000 ++#define MAX_UC_SPEC_ADDR_REG 31 ++ ++struct pfe_eth_fast_timer { ++ int queuenum; ++ struct hrtimer timer; ++ void *base; ++}; ++ ++struct pfe_eth_priv_s { ++ struct pfe *pfe; ++ struct hif_client_s client; ++ struct napi_struct lro_napi; ++ struct napi_struct low_napi; ++ struct napi_struct high_napi; ++ int low_tmu_q; ++ int high_tmu_q; ++ struct net_device_stats stats; ++ struct net_device *ndev; ++ int id; ++ int promisc; ++ unsigned int msg_enable; ++ unsigned int usr_features; ++ ++ spinlock_t lock; /* protect member variables */ ++ unsigned int event_status; ++ int irq; ++ void *EMAC_baseaddr; ++ void *GPI_baseaddr; ++ /* PHY stuff */ ++ struct phy_device *phydev; ++ int oldspeed; ++ int oldduplex; ++ int oldlink; ++ struct device_node *phy_node; ++ struct clk *gemtx_clk; ++ int wol; ++ int pause_flag; ++ ++ int default_priority; ++ struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT]; ++ ++ struct ls1012a_eth_platform_data *einfo; ++ struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6]; ++ ++#ifdef PFE_ETH_TX_STATS ++ unsigned int stop_queue_total[EMAC_TXQ_CNT]; ++ unsigned int stop_queue_hif[EMAC_TXQ_CNT]; ++ unsigned int stop_queue_hif_client[EMAC_TXQ_CNT]; ++ unsigned int stop_queue_credit[EMAC_TXQ_CNT]; ++ unsigned int clean_fail[EMAC_TXQ_CNT]; ++ unsigned int was_stopped[EMAC_TXQ_CNT]; ++#endif ++ ++#ifdef PFE_ETH_NAPI_STATS ++ unsigned int napi_counters[NAPI_MAX_COUNT]; ++#endif ++ unsigned int frags_inflight[EMAC_RXQ_CNT + 6]; ++}; ++ ++struct pfe_eth { ++ struct pfe_eth_priv_s *eth_priv[3]; ++}; ++ ++struct pfe_mdio_priv_s { ++ void __iomem *mdio_base; ++ int mdc_div; ++ struct mii_bus *mii_bus; ++}; ++ ++struct pfe_mdio { ++ struct pfe_mdio_priv_s *mdio_priv[3]; ++}; ++ ++int pfe_eth_init(struct pfe *pfe); ++void pfe_eth_exit(struct pfe *pfe); ++int pfe_eth_suspend(struct net_device *dev); ++int pfe_eth_resume(struct net_device *dev); ++int pfe_eth_mdio_reset(struct mii_bus *bus); ++ ++#endif /* _PFE_ETH_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_firmware.c +@@ -0,0 +1,398 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++/* ++ * @file ++ * Contains all the functions to handle parsing and loading of PE firmware ++ * files. ++ */ ++#include ++ ++#include "pfe_mod.h" ++#include "pfe_firmware.h" ++#include "pfe/pfe.h" ++#include ++#include ++ ++static struct elf32_shdr *get_elf_section_header(const u8 *fw, ++ const char *section) ++{ ++ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw; ++ struct elf32_shdr *shdr; ++ struct elf32_shdr *shdr_shstr; ++ Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff); ++ Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize); ++ Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum); ++ Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx); ++ Elf32_Off shstr_offset; ++ Elf32_Word sh_name; ++ const char *name; ++ int i; ++ ++ /* Section header strings */ ++ shdr_shstr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff + e_shstrndx ++ * e_shentsize); ++ shstr_offset = be32_to_cpu(shdr_shstr->sh_offset); ++ ++ for (i = 0; i < e_shnum; i++) { ++ shdr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff ++ + i * e_shentsize); ++ ++ sh_name = be32_to_cpu(shdr->sh_name); ++ ++ name = (const char *)((u8 *)elf_hdr + shstr_offset + sh_name); ++ ++ if (!strcmp(name, section)) ++ return shdr; ++ } ++ ++ pr_err("%s: didn't find section %s\n", __func__, section); ++ ++ return NULL; ++} ++ ++#if defined(CFG_DIAGS) ++static int pfe_get_diags_info(const u8 *fw, struct pfe_diags_info ++ *diags_info) ++{ ++ struct elf32_shdr *shdr; ++ unsigned long offset, size; ++ ++ shdr = get_elf_section_header(fw, ".pfe_diags_str"); ++ if (shdr) { ++ offset = be32_to_cpu(shdr->sh_offset); ++ size = be32_to_cpu(shdr->sh_size); ++ diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr); ++ diags_info->diags_str_size = size; ++ diags_info->diags_str_array = kmalloc(size, GFP_KERNEL); ++ memcpy(diags_info->diags_str_array, fw + offset, size); ++ ++ return 0; ++ } else { ++ return -1; ++ } ++} ++#endif ++ ++static void pfe_check_version_info(const u8 *fw) ++{ ++ /*static char *version = NULL;*/ ++ const u8 *elf_data = fw; ++ static char *version; ++ ++ struct elf32_shdr *shdr = get_elf_section_header(fw, ".version"); ++ ++ if (shdr) { ++ if (!version) { ++ /* ++ * this is the first fw we load, use its version ++ * string as reference (whatever it is) ++ */ ++ version = (char *)(elf_data + ++ be32_to_cpu(shdr->sh_offset)); ++ ++ pr_info("PFE binary version: %s\n", version); ++ } else { ++ /* ++ * already have loaded at least one firmware, check ++ * sequence can start now ++ */ ++ if (strcmp(version, (char *)(elf_data + ++ be32_to_cpu(shdr->sh_offset)))) { ++ pr_info( ++ "WARNING: PFE firmware binaries from incompatible version\n"); ++ } ++ } ++ } else { ++ /* ++ * version cannot be verified, a potential issue that should ++ * be reported ++ */ ++ pr_info( ++ "WARNING: PFE firmware binaries from incompatible version\n"); ++ } ++} ++ ++/* PFE elf firmware loader. ++ * Loads an elf firmware image into a list of PE's (specified using a bitmask) ++ * ++ * @param pe_mask Mask of PE id's to load firmware to ++ * @param fw Pointer to the firmware image ++ * ++ * @return 0 on success, a negative value on error ++ * ++ */ ++int pfe_load_elf(int pe_mask, const u8 *fw, struct pfe *pfe) ++{ ++ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw; ++ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum); ++ struct elf32_shdr *shdr = (struct elf32_shdr *)(fw + ++ be32_to_cpu(elf_hdr->e_shoff)); ++ int id, section; ++ int rc; ++ ++ pr_info("%s\n", __func__); ++ ++ /* Some sanity checks */ ++ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) { ++ pr_err("%s: incorrect elf magic number\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) { ++ pr_err("%s: incorrect elf class(%x)\n", __func__, ++ elf_hdr->e_ident[EI_CLASS]); ++ return -EINVAL; ++ } ++ ++ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) { ++ pr_err("%s: incorrect elf data(%x)\n", __func__, ++ elf_hdr->e_ident[EI_DATA]); ++ return -EINVAL; ++ } ++ ++ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) { ++ pr_err("%s: incorrect elf file type(%x)\n", __func__, ++ be16_to_cpu(elf_hdr->e_type)); ++ return -EINVAL; ++ } ++ ++ for (section = 0; section < sections; section++, shdr++) { ++ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | ++ SHF_EXECINSTR))) ++ continue; ++ ++ for (id = 0; id < MAX_PE; id++) ++ if (pe_mask & (1 << id)) { ++ rc = pe_load_elf_section(id, elf_hdr, shdr, ++ pfe->dev); ++ if (rc < 0) ++ goto err; ++ } ++ } ++ ++ pfe_check_version_info(fw); ++ ++ return 0; ++ ++err: ++ return rc; ++} ++ ++int get_firmware_in_fdt(const u8 **pe_fw, const char *name) ++{ ++ struct device_node *np; ++ const unsigned int *len; ++ const void *data; ++ ++ if (!strcmp(name, CLASS_FIRMWARE_FILENAME)) { ++ /* The firmware should be inside the device tree. */ ++ np = of_find_compatible_node(NULL, NULL, ++ "fsl,pfe-class-firmware"); ++ if (!np) { ++ pr_info("Failed to find the node\n"); ++ return -ENOENT; ++ } ++ ++ data = of_get_property(np, "fsl,class-firmware", NULL); ++ if (data) { ++ len = of_get_property(np, "length", NULL); ++ pr_info("CLASS fw of length %d bytes loaded from FDT.\n", ++ be32_to_cpu(*len)); ++ } else { ++ pr_info("fsl,class-firmware not found!!!!\n"); ++ return -ENOENT; ++ } ++ of_node_put(np); ++ *pe_fw = data; ++ } else if (!strcmp(name, TMU_FIRMWARE_FILENAME)) { ++ np = of_find_compatible_node(NULL, NULL, ++ "fsl,pfe-tmu-firmware"); ++ if (!np) { ++ pr_info("Failed to find the node\n"); ++ return -ENOENT; ++ } ++ ++ data = of_get_property(np, "fsl,tmu-firmware", NULL); ++ if (data) { ++ len = of_get_property(np, "length", NULL); ++ pr_info("TMU fw of length %d bytes loaded from FDT.\n", ++ be32_to_cpu(*len)); ++ } else { ++ pr_info("fsl,tmu-firmware not found!!!!\n"); ++ return -ENOENT; ++ } ++ of_node_put(np); ++ *pe_fw = data; ++ } else if (!strcmp(name, UTIL_FIRMWARE_FILENAME)) { ++ np = of_find_compatible_node(NULL, NULL, ++ "fsl,pfe-util-firmware"); ++ if (!np) { ++ pr_info("Failed to find the node\n"); ++ return -ENOENT; ++ } ++ ++ data = of_get_property(np, "fsl,util-firmware", NULL); ++ if (data) { ++ len = of_get_property(np, "length", NULL); ++ pr_info("UTIL fw of length %d bytes loaded from FDT.\n", ++ be32_to_cpu(*len)); ++ } else { ++ pr_info("fsl,util-firmware not found!!!!\n"); ++ return -ENOENT; ++ } ++ of_node_put(np); ++ *pe_fw = data; ++ } else { ++ pr_err("firmware:%s not known\n", name); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* PFE firmware initialization. ++ * Loads different firmware files from filesystem. ++ * Initializes PE IMEM/DMEM and UTIL-PE DDR ++ * Initializes control path symbol addresses (by looking them up in the elf ++ * firmware files ++ * Takes PE's out of reset ++ * ++ * @return 0 on success, a negative value on error ++ * ++ */ ++int pfe_firmware_init(struct pfe *pfe) ++{ ++ const struct firmware *class_fw, *tmu_fw; ++ const u8 *class_elf_fw, *tmu_elf_fw; ++ int rc = 0, fs_load = 0; ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ const struct firmware *util_fw; ++ const u8 *util_elf_fw; ++ ++#endif ++ ++ pr_info("%s\n", __func__); ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) || ++ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME) || ++ get_firmware_in_fdt(&util_elf_fw, UTIL_FIRMWARE_FILENAME)) ++#else ++ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) || ++ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME)) ++#endif ++ { ++ pr_info("%s:PFE firmware not found in FDT.\n", __func__); ++ pr_info("%s:Trying to load firmware from filesystem...!\n", __func__); ++ ++ /* look for firmware in filesystem...!*/ ++ fs_load = 1; ++ if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) { ++ pr_err("%s: request firmware %s failed\n", __func__, ++ CLASS_FIRMWARE_FILENAME); ++ rc = -ETIMEDOUT; ++ goto err0; ++ } ++ class_elf_fw = class_fw->data; ++ ++ if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) { ++ pr_err("%s: request firmware %s failed\n", __func__, ++ TMU_FIRMWARE_FILENAME); ++ rc = -ETIMEDOUT; ++ goto err1; ++ } ++ tmu_elf_fw = tmu_fw->data; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (request_firmware(&util_fw, UTIL_FIRMWARE_FILENAME, pfe->dev)) { ++ pr_err("%s: request firmware %s failed\n", __func__, ++ UTIL_FIRMWARE_FILENAME); ++ rc = -ETIMEDOUT; ++ goto err2; ++ } ++ util_elf_fw = util_fw->data; ++#endif ++ } ++ ++ rc = pfe_load_elf(CLASS_MASK, class_elf_fw, pfe); ++ if (rc < 0) { ++ pr_err("%s: class firmware load failed\n", __func__); ++ goto err3; ++ } ++ ++#if defined(CFG_DIAGS) ++ rc = pfe_get_diags_info(class_elf_fw, &pfe->diags.class_diags_info); ++ if (rc < 0) { ++ pr_warn( ++ "PFE diags won't be available for class PEs\n"); ++ rc = 0; ++ } ++#endif ++ ++ rc = pfe_load_elf(TMU_MASK, tmu_elf_fw, pfe); ++ if (rc < 0) { ++ pr_err("%s: tmu firmware load failed\n", __func__); ++ goto err3; ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ rc = pfe_load_elf(UTIL_MASK, util_elf_fw, pfe); ++ if (rc < 0) { ++ pr_err("%s: util firmware load failed\n", __func__); ++ goto err3; ++ } ++ ++#if defined(CFG_DIAGS) ++ rc = pfe_get_diags_info(util_elf_fw, &pfe->diags.util_diags_info); ++ if (rc < 0) { ++ pr_warn( ++ "PFE diags won't be available for util PE\n"); ++ rc = 0; ++ } ++#endif ++ ++ util_enable(); ++#endif ++ ++ tmu_enable(0xf); ++ class_enable(); ++ ++err3: ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (fs_load) ++ release_firmware(util_fw); ++err2: ++#endif ++ if (fs_load) ++ release_firmware(tmu_fw); ++ ++err1: ++ if (fs_load) ++ release_firmware(class_fw); ++ ++err0: ++ return rc; ++} ++ ++/* PFE firmware cleanup ++ * Puts PE's in reset ++ * ++ * ++ */ ++void pfe_firmware_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ if (pe_reset_all(&pfe->ctrl) != 0) ++ pr_err("Error: Failed to stop PEs, PFE reload may not work correctly\n"); ++ ++ class_disable(); ++ tmu_disable(0xf); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ util_disable(); ++#endif ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_firmware.h +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_FIRMWARE_H_ ++#define _PFE_FIRMWARE_H_ ++ ++#define CLASS_FIRMWARE_FILENAME "ppfe_class_ls1012a.elf" ++#define TMU_FIRMWARE_FILENAME "ppfe_tmu_ls1012a.elf" ++#define UTIL_FIRMWARE_FILENAME "ppfe_util_ls1012a.elf" ++ ++#define PFE_FW_CHECK_PASS 0 ++#define PFE_FW_CHECK_FAIL 1 ++#define NUM_PFE_FW 3 ++ ++int pfe_firmware_init(struct pfe *pfe); ++void pfe_firmware_exit(struct pfe *pfe); ++ ++#endif /* _PFE_FIRMWARE_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hal.c +@@ -0,0 +1,1517 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include "pfe_mod.h" ++#include "pfe/pfe.h" ++ ++/* A-010897: Jumbo frame is not supported */ ++extern bool pfe_errata_a010897; ++ ++#define PFE_RCR_MAX_FL_MASK 0xC000FFFF ++ ++void *cbus_base_addr; ++void *ddr_base_addr; ++unsigned long ddr_phys_base_addr; ++unsigned int ddr_size; ++ ++static struct pe_info pe[MAX_PE]; ++ ++/* Initializes the PFE library. ++ * Must be called before using any of the library functions. ++ * ++ * @param[in] cbus_base CBUS virtual base address (as mapped in ++ * the host CPU address space) ++ * @param[in] ddr_base PFE DDR range virtual base address (as ++ * mapped in the host CPU address space) ++ * @param[in] ddr_phys_base PFE DDR range physical base address (as ++ * mapped in platform) ++ * @param[in] size PFE DDR range size (as defined by the host ++ * software) ++ */ ++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, ++ unsigned int size) ++{ ++ cbus_base_addr = cbus_base; ++ ddr_base_addr = ddr_base; ++ ddr_phys_base_addr = ddr_phys_base; ++ ddr_size = size; ++ ++ pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0); ++ pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0); ++ pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1); ++ pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1); ++ pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2); ++ pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2); ++ pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3); ++ pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3); ++ pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4); ++ pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4); ++ pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5); ++ pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5); ++ pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE; ++ pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; ++ pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; ++ pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; ++ ++ pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0); ++ pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0); ++ pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE; ++ pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; ++ pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; ++ pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; ++ ++ pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1); ++ pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1); ++ pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE; ++ pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; ++ pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; ++ pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; ++ ++ pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3); ++ pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3); ++ pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE; ++ pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; ++ pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; ++ pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR; ++ pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA; ++ pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR; ++ pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA; ++#endif ++} ++ ++/* Writes a buffer to PE internal memory from the host ++ * through indirect access registers. ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] src Buffer source address ++ * @param[in] mem_access_addr DMEM destination address (must be 32bit ++ * aligned) ++ * @param[in] len Number of bytes to copy ++ */ ++void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned ++int len) ++{ ++ u32 offset = 0, val, addr; ++ unsigned int len32 = len >> 2; ++ int i; ++ ++ addr = mem_access_addr | PE_MEM_ACCESS_WRITE | ++ PE_MEM_ACCESS_BYTE_ENABLE(0, 4); ++ ++ for (i = 0; i < len32; i++, offset += 4, src += 4) { ++ val = *(u32 *)src; ++ writel(cpu_to_be32(val), pe[id].mem_access_wdata); ++ writel(addr + offset, pe[id].mem_access_addr); ++ } ++ ++ len = (len & 0x3); ++ if (len) { ++ val = 0; ++ ++ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | ++ PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset; ++ ++ for (i = 0; i < len; i++, src++) ++ val |= (*(u8 *)src) << (8 * i); ++ ++ writel(cpu_to_be32(val), pe[id].mem_access_wdata); ++ writel(addr, pe[id].mem_access_addr); ++ } ++} ++ ++/* Writes a buffer to PE internal data memory (DMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] src Buffer source address ++ * @param[in] dst DMEM destination address (must be 32bit ++ * aligned) ++ * @param[in] len Number of bytes to copy ++ */ ++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) ++{ ++ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | ++ PE_MEM_ACCESS_DMEM, src, len); ++} ++ ++/* Writes a buffer to PE internal program memory (PMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., TMU3_ID) ++ * @param[in] src Buffer source address ++ * @param[in] dst PMEM destination address (must be 32bit ++ * aligned) ++ * @param[in] len Number of bytes to copy ++ */ ++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) ++{ ++ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size ++ - 1)) | PE_MEM_ACCESS_IMEM, src, len); ++} ++ ++/* Reads PE internal program memory (IMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., TMU3_ID) ++ * @param[in] addr PMEM read address (must be aligned on size) ++ * @param[in] size Number of bytes to read (maximum 4, must not ++ * cross 32bit boundaries) ++ * @return the data read (in PE endianness, i.e BE). ++ */ ++u32 pe_pmem_read(int id, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ u32 mask = 0xffffffff >> ((4 - size) << 3); ++ u32 val; ++ ++ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) ++ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); ++ ++ writel(addr, pe[id].mem_access_addr); ++ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); ++ ++ return (val >> (offset << 3)) & mask; ++} ++ ++/* Writes PE internal data memory (DMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] addr DMEM write address (must be aligned on size) ++ * @param[in] val Value to write (in PE endianness, i.e BE) ++ * @param[in] size Number of bytes to write (maximum 4, must not ++ * cross 32bit boundaries) ++ */ ++void pe_dmem_write(int id, u32 val, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ ++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | ++ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); ++ ++ /* Indirect access interface is byte swapping data being written */ ++ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata); ++ writel(addr, pe[id].mem_access_addr); ++} ++ ++/* Reads PE internal data memory (DMEM) from the host ++ * through indirect access registers. ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] addr DMEM read address (must be aligned on size) ++ * @param[in] size Number of bytes to read (maximum 4, must not ++ * cross 32bit boundaries) ++ * @return the data read (in PE endianness, i.e BE). ++ */ ++u32 pe_dmem_read(int id, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ u32 mask = 0xffffffff >> ((4 - size) << 3); ++ u32 val; ++ ++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM | ++ PE_MEM_ACCESS_BYTE_ENABLE(offset, size); ++ ++ writel(addr, pe[id].mem_access_addr); ++ ++ /* Indirect access interface is byte swapping data being read */ ++ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); ++ ++ return (val >> (offset << 3)) & mask; ++} ++ ++/* This function is used to write to CLASS internal bus peripherals (ccu, ++ * pe-lem) from the host ++ * through indirect access registers. ++ * @param[in] val value to write ++ * @param[in] addr Address to write to (must be aligned on size) ++ * @param[in] size Number of bytes to write (1, 2 or 4) ++ * ++ */ ++void class_bus_write(u32 val, u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ ++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); ++ ++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | ++ (size << 24); ++ ++ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA); ++ writel(addr, CLASS_BUS_ACCESS_ADDR); ++} ++ ++/* Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host ++ * through indirect access registers. ++ * @param[in] addr Address to read from (must be aligned on size) ++ * @param[in] size Number of bytes to read (1, 2 or 4) ++ * @return the read data ++ * ++ */ ++u32 class_bus_read(u32 addr, u8 size) ++{ ++ u32 offset = addr & 0x3; ++ u32 mask = 0xffffffff >> ((4 - size) << 3); ++ u32 val; ++ ++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); ++ ++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24); ++ ++ writel(addr, CLASS_BUS_ACCESS_ADDR); ++ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA)); ++ ++ return (val >> (offset << 3)) & mask; ++} ++ ++/* Writes data to the cluster memory (PE_LMEM) ++ * @param[in] dst PE LMEM destination address (must be 32bit aligned) ++ * @param[in] src Buffer source address ++ * @param[in] len Number of bytes to copy ++ */ ++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len) ++{ ++ u32 len32 = len >> 2; ++ int i; ++ ++ for (i = 0; i < len32; i++, src += 4, dst += 4) ++ class_bus_write(*(u32 *)src, dst, 4); ++ ++ if (len & 0x2) { ++ class_bus_write(*(u16 *)src, dst, 2); ++ src += 2; ++ dst += 2; ++ } ++ ++ if (len & 0x1) { ++ class_bus_write(*(u8 *)src, dst, 1); ++ src++; ++ dst++; ++ } ++} ++ ++/* Writes value to the cluster memory (PE_LMEM) ++ * @param[in] dst PE LMEM destination address (must be 32bit aligned) ++ * @param[in] val Value to write ++ * @param[in] len Number of bytes to write ++ */ ++void class_pe_lmem_memset(u32 dst, int val, unsigned int len) ++{ ++ u32 len32 = len >> 2; ++ int i; ++ ++ val = val | (val << 8) | (val << 16) | (val << 24); ++ ++ for (i = 0; i < len32; i++, dst += 4) ++ class_bus_write(val, dst, 4); ++ ++ if (len & 0x2) { ++ class_bus_write(val, dst, 2); ++ dst += 2; ++ } ++ ++ if (len & 0x1) { ++ class_bus_write(val, dst, 1); ++ dst++; ++ } ++} ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ ++/* Writes UTIL program memory (DDR) from the host. ++ * ++ * @param[in] addr Address to write (virtual, must be aligned on size) ++ * @param[in] val Value to write (in PE endianness, i.e BE) ++ * @param[in] size Number of bytes to write (2 or 4) ++ */ ++static void util_pmem_write(u32 val, void *addr, u8 size) ++{ ++ void *addr64 = (void *)((unsigned long)addr & ~0x7); ++ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size; ++ ++ /* ++ * IMEM should be loaded as a 64bit swapped value in a 64bit aligned ++ * location ++ */ ++ if (size == 4) ++ writel(be32_to_cpu(val), addr64 + off); ++ else ++ writew(be16_to_cpu((u16)val), addr64 + off); ++} ++ ++/* Writes a buffer to UTIL program memory (DDR) from the host. ++ * ++ * @param[in] dst Address to write (virtual, must be at least 16bit ++ * aligned) ++ * @param[in] src Buffer to write (in PE endianness, i.e BE, must have ++ * same alignment as dst) ++ * @param[in] len Number of bytes to write (must be at least 16bit ++ * aligned) ++ */ ++static void util_pmem_memcpy(void *dst, const void *src, unsigned int len) ++{ ++ unsigned int len32; ++ int i; ++ ++ if ((unsigned long)src & 0x2) { ++ util_pmem_write(*(u16 *)src, dst, 2); ++ src += 2; ++ dst += 2; ++ len -= 2; ++ } ++ ++ len32 = len >> 2; ++ ++ for (i = 0; i < len32; i++, dst += 4, src += 4) ++ util_pmem_write(*(u32 *)src, dst, 4); ++ ++ if (len & 0x2) ++ util_pmem_write(*(u16 *)src, dst, len & 0x2); ++} ++#endif ++ ++/* Loads an elf section into pmem ++ * Code needs to be at least 16bit aligned and only PROGBITS sections are ++ * supported ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., ++ * TMU3_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_pmem_section(int id, const void *data, ++ struct elf32_shdr *shdr) ++{ ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (id == UTIL_ID) { ++ pr_err("%s: unsupported pmem section for UTIL\n", ++ __func__); ++ return -EINVAL; ++ } ++#endif ++ ++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" ++ , __func__, addr, (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x1) { ++ pr_err("%s: load address(%x) is not 16bit aligned\n", ++ __func__, addr); ++ return -EINVAL; ++ } ++ ++ if (size & 0x1) { ++ pr_err("%s: load size(%x) is not 16bit aligned\n", ++ __func__, size); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ pe_pmem_memcpy_to32(id, addr, data + offset, size); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into dmem ++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly ++ * initialized to 0 ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_dmem_section(int id, const void *data, ++ struct elf32_shdr *shdr) ++{ ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ u32 size32 = size >> 2; ++ int i; ++ ++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", ++ __func__, addr, (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x3) { ++ pr_err("%s: load address(%x) is not 32bit aligned\n", ++ __func__, addr); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ pe_dmem_memcpy_to32(id, addr, data + offset, size); ++ break; ++ ++ case SHT_NOBITS: ++ for (i = 0; i < size32; i++, addr += 4) ++ pe_dmem_write(id, 0, addr, 4); ++ ++ if (size & 0x3) ++ pe_dmem_write(id, 0, addr, size & 0x3); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into DDR ++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly ++ * initialized to 0 ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_ddr_section(int id, const void *data, ++ struct elf32_shdr *shdr, ++ struct device *dev) { ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ u32 flags = be32_to_cpu(shdr->sh_flags); ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ if (flags & SHF_EXECINSTR) { ++ if (id <= CLASS_MAX_ID) { ++ /* DO the loading only once in DDR */ ++ if (id == CLASS0_ID) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) rcvd\n", ++ __func__, addr, ++ (unsigned long)data + offset); ++ if (((unsigned long)(data + offset) ++ & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" ++ , __func__, addr, ++ (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x1) { ++ pr_err( ++ "%s: load address(%x) is not 16bit aligned\n" ++ , __func__, addr); ++ return -EINVAL; ++ } ++ ++ if (size & 0x1) { ++ pr_err( ++ "%s: load length(%x) is not 16bit aligned\n" ++ , __func__, size); ++ return -EINVAL; ++ } ++ memcpy(DDR_PHYS_TO_VIRT( ++ DDR_PFE_TO_PHYS(addr)), ++ data + offset, size); ++ } ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ } else if (id == UTIL_ID) { ++ if (((unsigned long)(data + offset) & 0x3) ++ != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" ++ , __func__, addr, ++ (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x1) { ++ pr_err( ++ "%s: load address(%x) is not 16bit aligned\n" ++ , __func__, addr); ++ return -EINVAL; ++ } ++ ++ if (size & 0x1) { ++ pr_err( ++ "%s: load length(%x) is not 16bit aligned\n" ++ , __func__, size); ++ return -EINVAL; ++ } ++ ++ util_pmem_memcpy(DDR_PHYS_TO_VIRT( ++ DDR_PFE_TO_PHYS(addr)), ++ data + offset, size); ++ } ++#endif ++ } else { ++ pr_err( ++ "%s: unsupported ddr section type(%x) for PE(%d)\n" ++ , __func__, type, id); ++ return -EINVAL; ++ } ++ ++ } else { ++ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data ++ + offset, size); ++ } ++ ++ break; ++ ++ case SHT_NOBITS: ++ memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into pe lmem ++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly ++ * initialized to 0 ++ * ++ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++static int pe_load_pe_lmem_section(int id, const void *data, ++ struct elf32_shdr *shdr) ++{ ++ u32 offset = be32_to_cpu(shdr->sh_offset); ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ u32 type = be32_to_cpu(shdr->sh_type); ++ ++ if (id > CLASS_MAX_ID) { ++ pr_err( ++ "%s: unsupported pe-lmem section type(%x) for PE(%d)\n", ++ __func__, type, id); ++ return -EINVAL; ++ } ++ ++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { ++ pr_err( ++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", ++ __func__, addr, (unsigned long)data + offset); ++ ++ return -EINVAL; ++ } ++ ++ if (addr & 0x3) { ++ pr_err("%s: load address(%x) is not 32bit aligned\n", ++ __func__, addr); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case SHT_PROGBITS: ++ class_pe_lmem_memcpy_to32(addr, data + offset, size); ++ break; ++ ++ case SHT_NOBITS: ++ class_pe_lmem_memset(addr, 0, size); ++ break; ++ ++ default: ++ pr_err("%s: unsupported section type(%x)\n", __func__, ++ type); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Loads an elf section into a PE ++ * For now only supports loading a section to dmem (all PE's), pmem (class and ++ * tmu PE's), ++ * DDDR (util PE code) ++ * ++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ++ * ..., UTIL_ID) ++ * @param[in] data pointer to the elf firmware ++ * @param[in] shdr pointer to the elf section header ++ * ++ */ ++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr, ++ struct device *dev) { ++ u32 addr = be32_to_cpu(shdr->sh_addr); ++ u32 size = be32_to_cpu(shdr->sh_size); ++ ++ if (IS_DMEM(addr, size)) ++ return pe_load_dmem_section(id, data, shdr); ++ else if (IS_PMEM(addr, size)) ++ return pe_load_pmem_section(id, data, shdr); ++ else if (IS_PFE_LMEM(addr, size)) ++ return 0; ++ else if (IS_PHYS_DDR(addr, size)) ++ return pe_load_ddr_section(id, data, shdr, dev); ++ else if (IS_PE_LMEM(addr, size)) ++ return pe_load_pe_lmem_section(id, data, shdr); ++ ++ pr_err("%s: unsupported memory range(%x)\n", __func__, ++ addr); ++ return 0; ++} ++ ++/**************************** BMU ***************************/ ++ ++/* Initializes a BMU block. ++ * @param[in] base BMU block base address ++ * @param[in] cfg BMU configuration ++ */ ++void bmu_init(void *base, struct BMU_CFG *cfg) ++{ ++ bmu_disable(base); ++ ++ bmu_set_config(base, cfg); ++ ++ bmu_reset(base); ++} ++ ++/* Resets a BMU block. ++ * @param[in] base BMU block base address ++ */ ++void bmu_reset(void *base) ++{ ++ writel(CORE_SW_RESET, base + BMU_CTRL); ++ ++ /* Wait for self clear */ ++ while (readl(base + BMU_CTRL) & CORE_SW_RESET) ++ ; ++} ++ ++/* Enabled a BMU block. ++ * @param[in] base BMU block base address ++ */ ++void bmu_enable(void *base) ++{ ++ writel(CORE_ENABLE, base + BMU_CTRL); ++} ++ ++/* Disables a BMU block. ++ * @param[in] base BMU block base address ++ */ ++void bmu_disable(void *base) ++{ ++ writel(CORE_DISABLE, base + BMU_CTRL); ++} ++ ++/* Sets the configuration of a BMU block. ++ * @param[in] base BMU block base address ++ * @param[in] cfg BMU configuration ++ */ ++void bmu_set_config(void *base, struct BMU_CFG *cfg) ++{ ++ writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR); ++ writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG); ++ writel(cfg->size & 0xffff, base + BMU_BUF_SIZE); ++ ++ /* Interrupts are never used */ ++ writel(cfg->low_watermark, base + BMU_LOW_WATERMARK); ++ writel(cfg->high_watermark, base + BMU_HIGH_WATERMARK); ++ writel(0x0, base + BMU_INT_ENABLE); ++} ++ ++/**************************** MTIP GEMAC ***************************/ ++ ++/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP, ++ * TCP or UDP checksums are discarded ++ * ++ * @param[in] base GEMAC base address. ++ */ ++void gemac_enable_rx_checksum_offload(void *base) ++{ ++ /*Do not find configuration to do this */ ++} ++ ++/* Disable Rx Checksum Engine. ++ * ++ * @param[in] base GEMAC base address. ++ */ ++void gemac_disable_rx_checksum_offload(void *base) ++{ ++ /*Do not find configuration to do this */ ++} ++ ++/* GEMAC set speed. ++ * @param[in] base GEMAC base address ++ * @param[in] speed GEMAC speed (10, 100 or 1000 Mbps) ++ */ ++void gemac_set_speed(void *base, enum mac_speed gem_speed) ++{ ++ u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; ++ u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; ++ ++ switch (gem_speed) { ++ case SPEED_10M: ++ rcr |= EMAC_RCNTRL_RMII_10T; ++ break; ++ ++ case SPEED_1000M: ++ ecr |= EMAC_ECNTRL_SPEED; ++ break; ++ ++ case SPEED_100M: ++ default: ++ /*It is in 100M mode */ ++ break; ++ } ++ writel(ecr, (base + EMAC_ECNTRL_REG)); ++ writel(rcr, (base + EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC set duplex. ++ * @param[in] base GEMAC base address ++ * @param[in] duplex GEMAC duplex mode (Full, Half) ++ */ ++void gemac_set_duplex(void *base, int duplex) ++{ ++ if (duplex == DUPLEX_HALF) { ++ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base ++ + EMAC_TCNTRL_REG); ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base ++ + EMAC_RCNTRL_REG)); ++ } else{ ++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base ++ + EMAC_TCNTRL_REG); ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base ++ + EMAC_RCNTRL_REG)); ++ } ++} ++ ++/* GEMAC set mode. ++ * @param[in] base GEMAC base address ++ * @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII) ++ */ ++void gemac_set_mode(void *base, int mode) ++{ ++ u32 val = readl(base + EMAC_RCNTRL_REG); ++ ++ /*Remove loopbank*/ ++ val &= ~EMAC_RCNTRL_LOOP; ++ ++ /* Enable flow control and MII mode.PFE firmware always expects ++ CRC should be forwarded by MAC to validate CRC in software.*/ ++ val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE); ++ ++ writel(val, base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable(void *base) ++{ ++ writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base + ++ EMAC_ECNTRL_REG); ++} ++ ++/* GEMAC disable function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable(void *base) ++{ ++ writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base + ++ EMAC_ECNTRL_REG); ++} ++ ++/* GEMAC TX disable function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_tx_disable(void *base) ++{ ++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + ++ EMAC_TCNTRL_REG); ++} ++ ++void gemac_tx_enable(void *base) ++{ ++ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base + ++ EMAC_TCNTRL_REG); ++} ++ ++/* Sets the hash register of the MAC. ++ * This register is used for matching unicast and multicast frames. ++ * ++ * @param[in] base GEMAC base address. ++ * @param[in] hash 64-bit hash to be configured. ++ */ ++void gemac_set_hash(void *base, struct pfe_mac_addr *hash) ++{ ++ writel(hash->bottom, base + EMAC_GALR); ++ writel(hash->top, base + EMAC_GAUR); ++} ++ ++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address, ++ unsigned int entry_index) ++{ ++ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX)) ++ return; ++ ++ entry_index = entry_index - 1; ++ if (entry_index < 1) { ++ writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW); ++ writel((htonl(address->top) | 0x8808), base + ++ EMAC_PHY_ADDR_HIGH); ++ } else { ++ writel(htonl(address->bottom), base + ((entry_index - 1) * 8) ++ + EMAC_SMAC_0_0); ++ writel((htonl(address->top) | 0x8808), base + ((entry_index - ++ 1) * 8) + EMAC_SMAC_0_1); ++ } ++} ++ ++void gemac_clear_laddrN(void *base, unsigned int entry_index) ++{ ++ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX)) ++ return; ++ ++ entry_index = entry_index - 1; ++ if (entry_index < 1) { ++ writel(0, base + EMAC_PHY_ADDR_LOW); ++ writel(0, base + EMAC_PHY_ADDR_HIGH); ++ } else { ++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0); ++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1); ++ } ++} ++ ++/* Set the loopback mode of the MAC. This can be either no loopback for ++ * normal operation, local loopback through MAC internal loopback module or PHY ++ * loopback for external loopback through a PHY. This asserts the external ++ * loop pin. ++ * ++ * @param[in] base GEMAC base address. ++ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC ++ * Loopback, ++ * LB_EXT - PHY Loopback. ++ */ ++void gemac_set_loop(void *base, enum mac_loop gem_loop) ++{ ++ pr_info("%s()\n", __func__); ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + ++ EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC allow frames ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_copy_all(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + ++ EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC do not allow frames ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable_copy_all(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + ++ EMAC_RCNTRL_REG)); ++} ++ ++/* GEMAC allow broadcast function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_allow_broadcast(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base + ++ EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC no broadcast function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_no_broadcast(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + ++ EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable 1536 rx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_1536_rx(void *base) ++{ ++ /* Set 1536 as Maximum frame length */ ++ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK) ++ | (1536 << 16), base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC set rx Max frame length. ++ * @param[in] base GEMAC base address ++ * @param[in] mtu new mtu ++ */ ++void gemac_set_rx_max_fl(void *base, int mtu) ++{ ++ /* Set mtu as Maximum frame length */ ++ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK) ++ | (mtu << 16), base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable stacked vlan function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_stacked_vlan(void *base) ++{ ++ /* MTIP doesn't support stacked vlan */ ++} ++ ++/* GEMAC enable pause rx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_pause_rx(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE, ++ base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC disable pause rx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable_pause_rx(void *base) ++{ ++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE, ++ base + EMAC_RCNTRL_REG); ++} ++ ++/* GEMAC enable pause tx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_enable_pause_tx(void *base) ++{ ++ writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY); ++} ++ ++/* GEMAC disable pause tx function. ++ * @param[in] base GEMAC base address ++ */ ++void gemac_disable_pause_tx(void *base) ++{ ++ writel(0x0, base + EMAC_RX_SECTION_EMPTY); ++} ++ ++/* GEMAC wol configuration ++ * @param[in] base GEMAC base address ++ * @param[in] wol_conf WoL register configuration ++ */ ++void gemac_set_wol(void *base, u32 wol_conf) ++{ ++ u32 val = readl(base + EMAC_ECNTRL_REG); ++ ++ if (wol_conf) ++ val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); ++ else ++ val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); ++ writel(val, base + EMAC_ECNTRL_REG); ++} ++ ++/* Sets Gemac bus width to 64bit ++ * @param[in] base GEMAC base address ++ * @param[in] width gemac bus width to be set possible values are 32/64/128 ++ */ ++void gemac_set_bus_width(void *base, int width) ++{ ++} ++ ++/* Sets Gemac configuration. ++ * @param[in] base GEMAC base address ++ * @param[in] cfg GEMAC configuration ++ */ ++void gemac_set_config(void *base, struct gemac_cfg *cfg) ++{ ++ /*GEMAC config taken from VLSI */ ++ writel(0x00000004, base + EMAC_TFWR_STR_FWD); ++ writel(0x00000005, base + EMAC_RX_SECTION_FULL); ++ ++ if (pfe_errata_a010897) ++ writel(0x0000076c, base + EMAC_TRUNC_FL); ++ else ++ writel(0x00003fff, base + EMAC_TRUNC_FL); ++ ++ writel(0x00000030, base + EMAC_TX_SECTION_EMPTY); ++ writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG); ++ ++ gemac_set_mode(base, cfg->mode); ++ ++ gemac_set_speed(base, cfg->speed); ++ ++ gemac_set_duplex(base, cfg->duplex); ++} ++ ++/**************************** GPI ***************************/ ++ ++/* Initializes a GPI block. ++ * @param[in] base GPI base address ++ * @param[in] cfg GPI configuration ++ */ ++void gpi_init(void *base, struct gpi_cfg *cfg) ++{ ++ gpi_reset(base); ++ ++ gpi_disable(base); ++ ++ gpi_set_config(base, cfg); ++} ++ ++/* Resets a GPI block. ++ * @param[in] base GPI base address ++ */ ++void gpi_reset(void *base) ++{ ++ writel(CORE_SW_RESET, base + GPI_CTRL); ++} ++ ++/* Enables a GPI block. ++ * @param[in] base GPI base address ++ */ ++void gpi_enable(void *base) ++{ ++ writel(CORE_ENABLE, base + GPI_CTRL); ++} ++ ++/* Disables a GPI block. ++ * @param[in] base GPI base address ++ */ ++void gpi_disable(void *base) ++{ ++ writel(CORE_DISABLE, base + GPI_CTRL); ++} ++ ++/* Sets the configuration of a GPI block. ++ * @param[in] base GPI base address ++ * @param[in] cfg GPI configuration ++ */ ++void gpi_set_config(void *base, struct gpi_cfg *cfg) ++{ ++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base ++ + GPI_LMEM_ALLOC_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base ++ + GPI_LMEM_FREE_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base ++ + GPI_DDR_ALLOC_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base ++ + GPI_DDR_FREE_ADDR); ++ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR); ++ writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET); ++ writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET); ++ writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET); ++ writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET); ++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE); ++ writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE); ++ ++ writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | ++ GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG); ++ writel(cfg->tmlf_txthres, base + GPI_TMLF_TX); ++ writel(cfg->aseq_len, base + GPI_DTX_ASEQ); ++ writel(1, base + GPI_TOE_CHKSUM_EN); ++ ++ if (cfg->mtip_pause_reg) { ++ writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG); ++ writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME); ++ } ++} ++ ++/**************************** CLASSIFIER ***************************/ ++ ++/* Initializes CLASSIFIER block. ++ * @param[in] cfg CLASSIFIER configuration ++ */ ++void class_init(struct class_cfg *cfg) ++{ ++ class_reset(); ++ ++ class_disable(); ++ ++ class_set_config(cfg); ++} ++ ++/* Resets CLASSIFIER block. ++ * ++ */ ++void class_reset(void) ++{ ++ writel(CORE_SW_RESET, CLASS_TX_CTRL); ++} ++ ++/* Enables all CLASS-PE's cores. ++ * ++ */ ++void class_enable(void) ++{ ++ writel(CORE_ENABLE, CLASS_TX_CTRL); ++} ++ ++/* Disables all CLASS-PE's cores. ++ * ++ */ ++void class_disable(void) ++{ ++ writel(CORE_DISABLE, CLASS_TX_CTRL); ++} ++ ++/* ++ * Sets the configuration of the CLASSIFIER block. ++ * @param[in] cfg CLASSIFIER configuration ++ */ ++void class_set_config(struct class_cfg *cfg) ++{ ++ u32 val; ++ ++ /* Initialize route table */ ++ if (!cfg->resume) ++ memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 << ++ cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ writel(cfg->pe_sys_clk_ratio, CLASS_PE_SYS_CLK_RATIO); ++#endif ++ ++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE); ++ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE); ++ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | ++ CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits), ++ CLASS_ROUTE_HASH_ENTRY_SIZE); ++ writel(HIF_PKT_CLASS_EN | HIF_PKT_OFFSET(sizeof(struct hif_hdr)), ++ CLASS_HIF_PARSE); ++ ++ val = HASH_CRC_PORT_IP | QB2BUS_LE; ++ ++#if defined(CONFIG_IP_ALIGNED) ++ val |= IP_ALIGNED; ++#endif ++ ++ /* ++ * Class PE packet steering will only work if TOE mode, bridge fetch or ++ * route fetch are enabled (see class/qb_fet.v). Route fetch would ++ * trigger additional memory copies (likely from DDR because of hash ++ * table size, which cannot be reduced because PE software still ++ * relies on hash value computed in HW), so when not in TOE mode we ++ * simply enable HW bridge fetch even though we don't use it. ++ */ ++ if (cfg->toe_mode) ++ val |= CLASS_TOE; ++ else ++ val |= HW_BRIDGE_FETCH; ++ ++ writel(val, CLASS_ROUTE_MULTI); ++ ++ writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr), ++ CLASS_ROUTE_TABLE_BASE); ++ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0); ++ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1); ++ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0); ++ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1); ++ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR); ++ ++ writel(23, CLASS_AFULL_THRES); ++ writel(23, CLASS_TSQ_FIFO_THRES); ++ ++ writel(24, CLASS_MAX_BUF_CNT); ++ writel(24, CLASS_TSQ_MAX_CNT); ++} ++ ++/**************************** TMU ***************************/ ++ ++void tmu_reset(void) ++{ ++ writel(SW_RESET, TMU_CTRL); ++} ++ ++/* Initializes TMU block. ++ * @param[in] cfg TMU configuration ++ */ ++void tmu_init(struct tmu_cfg *cfg) ++{ ++ int q, phyno; ++ ++ tmu_disable(0xF); ++ mdelay(10); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ /* keep in soft reset */ ++ writel(SW_RESET, TMU_CTRL); ++#endif ++ writel(0x3, TMU_SYS_GENERIC_CONTROL); ++ writel(750, TMU_INQ_WATERMARK); ++ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + ++ GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + ++ GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + ++ GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR); ++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), ++ TMU_BMU_INQ_ADDR); ++ ++ writel(0x3FF, TMU_TDQ0_SCH_CTRL); /* ++ * enabling all 10 ++ * schedulers [9:0] of each TDQ ++ */ ++ writel(0x3FF, TMU_TDQ1_SCH_CTRL); ++ writel(0x3FF, TMU_TDQ3_SCH_CTRL); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ writel(cfg->pe_sys_clk_ratio, TMU_PE_SYS_CLK_RATIO); ++#endif ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr), TMU_LLM_BASE_ADDR); ++ /* Extra packet pointers will be stored from this address onwards */ ++ ++ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN); ++ writel(5, TMU_TDQ_IIFG_CFG); ++ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE); ++ ++ writel(0x0, TMU_CTRL); ++ ++ /* MEM init */ ++ pr_info("%s: mem init\n", __func__); ++ writel(MEM_INIT, TMU_CTRL); ++ ++ while (!(readl(TMU_CTRL) & MEM_INIT_DONE)) ++ ; ++ ++ /* LLM init */ ++ pr_info("%s: lmem init\n", __func__); ++ writel(LLM_INIT, TMU_CTRL); ++ ++ while (!(readl(TMU_CTRL) & LLM_INIT_DONE)) ++ ; ++#endif ++ /* set up each queue for tail drop */ ++ for (phyno = 0; phyno < 4; phyno++) { ++ if (phyno == 2) ++ continue; ++ for (q = 0; q < 16; q++) { ++ u32 qdepth; ++ ++ writel((phyno << 8) | q, TMU_TEQ_CTRL); ++ writel(1 << 22, TMU_TEQ_QCFG); /*Enable tail drop */ ++ ++ if (phyno == 3) ++ qdepth = DEFAULT_TMU3_QDEPTH; ++ else ++ qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH : ++ DEFAULT_MAX_QDEPTH; ++ ++ /* LOG: 68855 */ ++ /* ++ * The following is a workaround for the reordered ++ * packet and BMU2 buffer leakage issue. ++ */ ++ if (CHIP_REVISION() == 0) ++ qdepth = 31; ++ ++ writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2); ++ writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3); ++ } ++ } ++ ++#ifdef CFG_LRO ++ /* Set TMU-3 queue 5 (LRO) in no-drop mode */ ++ writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL); ++ writel(0, TMU_TEQ_QCFG); ++#endif ++ ++ writel(0x05, TMU_TEQ_DISABLE_DROPCHK); ++ ++ writel(0x0, TMU_CTRL); ++} ++ ++/* Enables TMU-PE cores. ++ * @param[in] pe_mask TMU PE mask ++ */ ++void tmu_enable(u32 pe_mask) ++{ ++ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL); ++} ++ ++/* Disables TMU cores. ++ * @param[in] pe_mask TMU PE mask ++ */ ++void tmu_disable(u32 pe_mask) ++{ ++ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL); ++} ++ ++/* This will return the tmu queue status ++ * @param[in] if_id gem interface id or TMU index ++ * @return returns the bit mask of busy queues, zero means all ++ * queues are empty ++ */ ++u32 tmu_qstatus(u32 if_id) ++{ ++ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS + ++ offsetof(struct pe_status, tmu_qstatus), 4)); ++} ++ ++u32 tmu_pkts_processed(u32 if_id) ++{ ++ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS + ++ offsetof(struct pe_status, rx), 4)); ++} ++ ++/**************************** UTIL ***************************/ ++ ++/* Resets UTIL block. ++ */ ++void util_reset(void) ++{ ++ writel(CORE_SW_RESET, UTIL_TX_CTRL); ++} ++ ++/* Initializes UTIL block. ++ * @param[in] cfg UTIL configuration ++ */ ++void util_init(struct util_cfg *cfg) ++{ ++ writel(cfg->pe_sys_clk_ratio, UTIL_PE_SYS_CLK_RATIO); ++} ++ ++/* Enables UTIL-PE core. ++ * ++ */ ++void util_enable(void) ++{ ++ writel(CORE_ENABLE, UTIL_TX_CTRL); ++} ++ ++/* Disables UTIL-PE core. ++ * ++ */ ++void util_disable(void) ++{ ++ writel(CORE_DISABLE, UTIL_TX_CTRL); ++} ++ ++/**************************** HIF ***************************/ ++/* Initializes HIF copy block. ++ * ++ */ ++void hif_init(void) ++{ ++ /*Initialize HIF registers*/ ++ writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE, ++ HIF_POLL_CTRL); ++} ++ ++/* Enable hif tx DMA and interrupt ++ * ++ */ ++void hif_tx_enable(void) ++{ ++ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL); ++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), ++ HIF_INT_ENABLE); ++} ++ ++/* Disable hif tx DMA and interrupt ++ * ++ */ ++void hif_tx_disable(void) ++{ ++ u32 hif_int; ++ ++ writel(0, HIF_TX_CTRL); ++ ++ hif_int = readl(HIF_INT_ENABLE); ++ hif_int &= HIF_TXPKT_INT_EN; ++ writel(hif_int, HIF_INT_ENABLE); ++} ++ ++/* Enable hif rx DMA and interrupt ++ * ++ */ ++void hif_rx_enable(void) ++{ ++ hif_rx_dma_start(); ++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), ++ HIF_INT_ENABLE); ++} ++ ++/* Disable hif rx DMA and interrupt ++ * ++ */ ++void hif_rx_disable(void) ++{ ++ u32 hif_int; ++ ++ writel(0, HIF_RX_CTRL); ++ ++ hif_int = readl(HIF_INT_ENABLE); ++ hif_int &= HIF_RXPKT_INT_EN; ++ writel(hif_int, HIF_INT_ENABLE); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif.c +@@ -0,0 +1,1064 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++#define HIF_INT_MASK (HIF_INT | HIF_RXPKT_INT | HIF_TXPKT_INT) ++ ++unsigned char napi_first_batch; ++ ++static void pfe_tx_do_cleanup(unsigned long data); ++ ++static int pfe_hif_alloc_descr(struct pfe_hif *hif) ++{ ++ void *addr; ++ dma_addr_t dma_addr; ++ int err = 0; ++ ++ pr_info("%s\n", __func__); ++ addr = dma_alloc_coherent(pfe->dev, ++ HIF_RX_DESC_NT * sizeof(struct hif_desc) + ++ HIF_TX_DESC_NT * sizeof(struct hif_desc), ++ &dma_addr, GFP_KERNEL); ++ ++ if (!addr) { ++ pr_err("%s: Could not allocate buffer descriptors!\n" ++ , __func__); ++ err = -ENOMEM; ++ goto err0; ++ } ++ ++ hif->descr_baseaddr_p = dma_addr; ++ hif->descr_baseaddr_v = addr; ++ hif->rx_ring_size = HIF_RX_DESC_NT; ++ hif->tx_ring_size = HIF_TX_DESC_NT; ++ ++ return 0; ++ ++err0: ++ return err; ++} ++ ++#if defined(LS1012A_PFE_RESET_WA) ++static void pfe_hif_disable_rx_desc(struct pfe_hif *hif) ++{ ++ int ii; ++ struct hif_desc *desc = hif->rx_base; ++ ++ /*Mark all descriptors as LAST_BD */ ++ for (ii = 0; ii < hif->rx_ring_size; ii++) { ++ desc->ctrl |= BD_CTRL_LAST_BD; ++ desc++; ++ } ++} ++ ++struct class_rx_hdr_t { ++ u32 next_ptr; /* ptr to the start of the first DDR buffer */ ++ u16 length; /* total packet length */ ++ u16 phyno; /* input physical port number */ ++ u32 status; /* gemac status bits */ ++ u32 status2; /* reserved for software usage */ ++}; ++ ++/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled) ++ * except overflow ++ */ ++#define STATUS_BAD_FRAME_ERR BIT(16) ++#define STATUS_LENGTH_ERR BIT(17) ++#define STATUS_CRC_ERR BIT(18) ++#define STATUS_TOO_SHORT_ERR BIT(19) ++#define STATUS_TOO_LONG_ERR BIT(20) ++#define STATUS_CODE_ERR BIT(21) ++#define STATUS_MC_HASH_MATCH BIT(22) ++#define STATUS_CUMULATIVE_ARC_HIT BIT(23) ++#define STATUS_UNICAST_HASH_MATCH BIT(24) ++#define STATUS_IP_CHECKSUM_CORRECT BIT(25) ++#define STATUS_TCP_CHECKSUM_CORRECT BIT(26) ++#define STATUS_UDP_CHECKSUM_CORRECT BIT(27) ++#define STATUS_OVERFLOW_ERR BIT(28) /* GPI error */ ++#define MIN_PKT_SIZE 64 ++ ++static inline void copy_to_lmem(u32 *dst, u32 *src, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i += sizeof(u32)) { ++ *dst = htonl(*src); ++ dst++; src++; ++ } ++} ++ ++static void send_dummy_pkt_to_hif(void) ++{ ++ void *lmem_ptr, *ddr_ptr, *lmem_virt_addr; ++ u32 physaddr; ++ struct class_rx_hdr_t local_hdr; ++ static u32 dummy_pkt[] = { ++ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608, ++ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0, ++ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000, ++ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f }; ++ ++ ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL)); ++ if (!ddr_ptr) ++ return; ++ ++ lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL)); ++ if (!lmem_ptr) ++ return; ++ ++ pr_info("Sending a dummy pkt to HIF %p %p\n", ddr_ptr, lmem_ptr); ++ physaddr = (u32)DDR_VIRT_TO_PFE(ddr_ptr); ++ ++ lmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long int)lmem_ptr); ++ ++ local_hdr.phyno = htons(0); /* RX_PHY_0 */ ++ local_hdr.length = htons(MIN_PKT_SIZE); ++ ++ local_hdr.next_ptr = htonl((u32)physaddr); ++ /*Mark checksum is correct */ ++ local_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT | ++ STATUS_UDP_CHECKSUM_CORRECT | ++ STATUS_TCP_CHECKSUM_CORRECT | ++ STATUS_UNICAST_HASH_MATCH | ++ STATUS_CUMULATIVE_ARC_HIT)); ++ local_hdr.status2 = 0; ++ ++ copy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr, ++ sizeof(local_hdr)); ++ ++ copy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt, ++ 0x40); ++ ++ writel((unsigned long int)lmem_ptr, CLASS_INQ_PKTPTR); ++} ++ ++void pfe_hif_rx_idle(struct pfe_hif *hif) ++{ ++ int hif_stop_loop = 10; ++ u32 rx_status; ++ ++ pfe_hif_disable_rx_desc(hif); ++ pr_info("Bringing hif to idle state..."); ++ writel(0, HIF_INT_ENABLE); ++ /*If HIF Rx BDP is busy send a dummy packet */ ++ do { ++ rx_status = readl(HIF_RX_STATUS); ++ if (rx_status & BDP_CSR_RX_DMA_ACTV) ++ send_dummy_pkt_to_hif(); ++ ++ usleep_range(100, 150); ++ } while (--hif_stop_loop); ++ ++ if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV) ++ pr_info("Failed\n"); ++ else ++ pr_info("Done\n"); ++} ++#endif ++ ++static void pfe_hif_free_descr(struct pfe_hif *hif) ++{ ++ pr_info("%s\n", __func__); ++ ++ dma_free_coherent(pfe->dev, ++ hif->rx_ring_size * sizeof(struct hif_desc) + ++ hif->tx_ring_size * sizeof(struct hif_desc), ++ hif->descr_baseaddr_v, hif->descr_baseaddr_p); ++} ++ ++void pfe_hif_desc_dump(struct pfe_hif *hif) ++{ ++ struct hif_desc *desc; ++ unsigned long desc_p; ++ int ii = 0; ++ ++ pr_info("%s\n", __func__); ++ ++ desc = hif->rx_base; ++ desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + ++ hif->descr_baseaddr_p); ++ ++ pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p); ++ for (ii = 0; ii < hif->rx_ring_size; ii++) { ++ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", ++ readl(&desc->status), readl(&desc->ctrl), ++ readl(&desc->data), readl(&desc->next)); ++ desc++; ++ } ++ ++ desc = hif->tx_base; ++ desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + ++ hif->descr_baseaddr_p); ++ ++ pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p); ++ for (ii = 0; ii < hif->tx_ring_size; ii++) { ++ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", ++ readl(&desc->status), readl(&desc->ctrl), ++ readl(&desc->data), readl(&desc->next)); ++ desc++; ++ } ++} ++ ++/* pfe_hif_release_buffers */ ++static void pfe_hif_release_buffers(struct pfe_hif *hif) ++{ ++ struct hif_desc *desc; ++ int i = 0; ++ ++ hif->rx_base = hif->descr_baseaddr_v; ++ ++ pr_info("%s\n", __func__); ++ ++ /*Free Rx buffers */ ++ desc = hif->rx_base; ++ for (i = 0; i < hif->rx_ring_size; i++) { ++ if (readl(&desc->data)) { ++ if ((i < hif->shm->rx_buf_pool_cnt) && ++ (!hif->shm->rx_buf_pool[i])) { ++ /* ++ * dma_unmap_single(hif->dev, desc->data, ++ * hif->rx_buf_len[i], DMA_FROM_DEVICE); ++ */ ++ dma_unmap_single(hif->dev, ++ DDR_PFE_TO_PHYS( ++ readl(&desc->data)), ++ hif->rx_buf_len[i], ++ DMA_FROM_DEVICE); ++ hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i]; ++ } else { ++ pr_err("%s: buffer pool already full\n" ++ , __func__); ++ } ++ } ++ ++ writel(0, &desc->data); ++ writel(0, &desc->status); ++ writel(0, &desc->ctrl); ++ desc++; ++ } ++} ++ ++/* ++ * pfe_hif_init_buffers ++ * This function initializes the HIF Rx/Tx ring descriptors and ++ * initialize Rx queue with buffers. ++ */ ++static int pfe_hif_init_buffers(struct pfe_hif *hif) ++{ ++ struct hif_desc *desc, *first_desc_p; ++ u32 data; ++ int i = 0; ++ ++ pr_info("%s\n", __func__); ++ ++ /* Check enough Rx buffers available in the shared memory */ ++ if (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size) ++ return -ENOMEM; ++ ++ hif->rx_base = hif->descr_baseaddr_v; ++ memset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc)); ++ ++ /*Initialize Rx descriptors */ ++ desc = hif->rx_base; ++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p; ++ ++ for (i = 0; i < hif->rx_ring_size; i++) { ++ /* Initialize Rx buffers from the shared memory */ ++ ++ data = (u32)dma_map_single(hif->dev, hif->shm->rx_buf_pool[i], ++ pfe_pkt_size, DMA_FROM_DEVICE); ++ hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i]; ++ hif->rx_buf_len[i] = pfe_pkt_size; ++ hif->shm->rx_buf_pool[i] = NULL; ++ ++ if (likely(dma_mapping_error(hif->dev, data) == 0)) { ++ writel(DDR_PHYS_TO_PFE(data), &desc->data); ++ } else { ++ pr_err("%s : low on mem\n", __func__); ++ ++ goto err; ++ } ++ ++ writel(0, &desc->status); ++ ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ wmb(); ++ ++ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM ++ | BD_CTRL_DIR | BD_CTRL_DESC_EN ++ | BD_BUF_LEN(pfe_pkt_size)), &desc->ctrl); ++ ++ /* Chain descriptors */ ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next); ++ desc++; ++ } ++ ++ /* Overwrite last descriptor to chain it to first one*/ ++ desc--; ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next); ++ ++ hif->rxtoclean_index = 0; ++ ++ /*Initialize Rx buffer descriptor ring base address */ ++ writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR); ++ ++ hif->tx_base = hif->rx_base + hif->rx_ring_size; ++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p + ++ hif->rx_ring_size; ++ memset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc)); ++ ++ /*Initialize tx descriptors */ ++ desc = hif->tx_base; ++ ++ for (i = 0; i < hif->tx_ring_size; i++) { ++ /* Chain descriptors */ ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next); ++ writel(0, &desc->ctrl); ++ desc++; ++ } ++ ++ /* Overwrite last descriptor to chain it to first one */ ++ desc--; ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next); ++ hif->txavail = hif->tx_ring_size; ++ hif->txtosend = 0; ++ hif->txtoclean = 0; ++ hif->txtoflush = 0; ++ ++ /*Initialize Tx buffer descriptor ring base address */ ++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR); ++ ++ return 0; ++ ++err: ++ pfe_hif_release_buffers(hif); ++ return -ENOMEM; ++} ++ ++/* ++ * pfe_hif_client_register ++ * ++ * This function used to register a client driver with the HIF driver. ++ * ++ * Return value: ++ * 0 - on Successful registration ++ */ ++static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id, ++ struct hif_client_shm *client_shm) ++{ ++ struct hif_client *client = &hif->client[client_id]; ++ u32 i, cnt; ++ struct rx_queue_desc *rx_qbase; ++ struct tx_queue_desc *tx_qbase; ++ struct hif_rx_queue *rx_queue; ++ struct hif_tx_queue *tx_queue; ++ int err = 0; ++ ++ pr_info("%s\n", __func__); ++ ++ spin_lock_bh(&hif->tx_lock); ++ ++ if (test_bit(client_id, &hif->shm->g_client_status[0])) { ++ pr_err("%s: client %d already registered\n", ++ __func__, client_id); ++ err = -1; ++ goto unlock; ++ } ++ ++ memset(client, 0, sizeof(struct hif_client)); ++ ++ /* Initialize client Rx queues baseaddr, size */ ++ ++ cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl); ++ /* Check if client is requesting for more queues than supported */ ++ if (cnt > HIF_CLIENT_QUEUES_MAX) ++ cnt = HIF_CLIENT_QUEUES_MAX; ++ ++ client->rx_qn = cnt; ++ rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase; ++ for (i = 0; i < cnt; i++) { ++ rx_queue = &client->rx_q[i]; ++ rx_queue->base = rx_qbase + i * client_shm->rx_qsize; ++ rx_queue->size = client_shm->rx_qsize; ++ rx_queue->write_idx = 0; ++ } ++ ++ /* Initialize client Tx queues baseaddr, size */ ++ cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl); ++ ++ /* Check if client is requesting for more queues than supported */ ++ if (cnt > HIF_CLIENT_QUEUES_MAX) ++ cnt = HIF_CLIENT_QUEUES_MAX; ++ ++ client->tx_qn = cnt; ++ tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase; ++ for (i = 0; i < cnt; i++) { ++ tx_queue = &client->tx_q[i]; ++ tx_queue->base = tx_qbase + i * client_shm->tx_qsize; ++ tx_queue->size = client_shm->tx_qsize; ++ tx_queue->ack_idx = 0; ++ } ++ ++ set_bit(client_id, &hif->shm->g_client_status[0]); ++ ++unlock: ++ spin_unlock_bh(&hif->tx_lock); ++ ++ return err; ++} ++ ++/* ++ * pfe_hif_client_unregister ++ * ++ * This function used to unregister a client from the HIF driver. ++ * ++ */ ++static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id) ++{ ++ pr_info("%s\n", __func__); ++ ++ /* ++ * Mark client as no longer available (which prevents further packet ++ * receive for this client) ++ */ ++ spin_lock_bh(&hif->tx_lock); ++ ++ if (!test_bit(client_id, &hif->shm->g_client_status[0])) { ++ pr_err("%s: client %d not registered\n", __func__, ++ client_id); ++ ++ spin_unlock_bh(&hif->tx_lock); ++ return; ++ } ++ ++ clear_bit(client_id, &hif->shm->g_client_status[0]); ++ ++ spin_unlock_bh(&hif->tx_lock); ++} ++ ++/* ++ * client_put_rxpacket- ++ * This functions puts the Rx pkt in the given client Rx queue. ++ * It actually swap the Rx pkt in the client Rx descriptor buffer ++ * and returns the free buffer from it. ++ * ++ * If the function returns NULL means client Rx queue is full and ++ * packet couldn't send to client queue. ++ */ ++static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len, ++ u32 flags, u32 client_ctrl, u32 *rem_len) ++{ ++ void *free_pkt = NULL; ++ struct rx_queue_desc *desc = queue->base + queue->write_idx; ++ ++ if (readl(&desc->ctrl) & CL_DESC_OWN) { ++ if (page_mode) { ++ int rem_page_size = PAGE_SIZE - ++ PRESENT_OFST_IN_PAGE(pkt); ++ int cur_pkt_size = ROUND_MIN_RX_SIZE(len + ++ pfe_pkt_headroom); ++ *rem_len = (rem_page_size - cur_pkt_size); ++ if (*rem_len) { ++ free_pkt = pkt + cur_pkt_size; ++ get_page(virt_to_page(free_pkt)); ++ } else { ++ free_pkt = (void ++ *)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE); ++ *rem_len = pfe_pkt_size; ++ } ++ } else { ++ free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC | ++ GFP_DMA_PFE); ++ *rem_len = PFE_BUF_SIZE - pfe_pkt_headroom; ++ } ++ ++ if (free_pkt) { ++ desc->data = pkt; ++ desc->client_ctrl = client_ctrl; ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ smp_wmb(); ++ writel(CL_DESC_BUF_LEN(len) | flags, &desc->ctrl); ++ queue->write_idx = (queue->write_idx + 1) ++ & (queue->size - 1); ++ ++ free_pkt += pfe_pkt_headroom; ++ } ++ } ++ ++ return free_pkt; ++} ++ ++/* ++ * pfe_hif_rx_process- ++ * This function does pfe hif rx queue processing. ++ * Dequeue packet from Rx queue and send it to corresponding client queue ++ */ ++static int pfe_hif_rx_process(struct pfe_hif *hif, int budget) ++{ ++ struct hif_desc *desc; ++ struct hif_hdr *pkt_hdr; ++ struct __hif_hdr hif_hdr; ++ void *free_buf; ++ int rtc, len, rx_processed = 0; ++ struct __hif_desc local_desc; ++ int flags; ++ unsigned int desc_p; ++ unsigned int buf_size = 0; ++ ++ spin_lock_bh(&hif->lock); ++ ++ rtc = hif->rxtoclean_index; ++ ++ while (rx_processed < budget) { ++ desc = hif->rx_base + rtc; ++ ++ __memcpy12(&local_desc, desc); ++ ++ /* ACK pending Rx interrupt */ ++ if (local_desc.ctrl & BD_CTRL_DESC_EN) { ++ writel(HIF_INT | HIF_RXPKT_INT, HIF_INT_SRC); ++ ++ if (rx_processed == 0) { ++ if (napi_first_batch == 1) { ++ desc_p = hif->descr_baseaddr_p + ++ ((unsigned long int)(desc) - ++ (unsigned long ++ int)hif->descr_baseaddr_v); ++ napi_first_batch = 0; ++ } ++ } ++ ++ __memcpy12(&local_desc, desc); ++ ++ if (local_desc.ctrl & BD_CTRL_DESC_EN) ++ break; ++ } ++ ++ napi_first_batch = 0; ++ ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_DESC_COUNT]++; ++#endif ++ len = BD_BUF_LEN(local_desc.ctrl); ++ /* ++ * dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), ++ * hif->rx_buf_len[rtc], DMA_FROM_DEVICE); ++ */ ++ dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), ++ hif->rx_buf_len[rtc], DMA_FROM_DEVICE); ++ ++ pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc]; ++ ++ /* Track last HIF header received */ ++ if (!hif->started) { ++ hif->started = 1; ++ ++ __memcpy8(&hif_hdr, pkt_hdr); ++ ++ hif->qno = hif_hdr.hdr.q_num; ++ hif->client_id = hif_hdr.hdr.client_id; ++ hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) | ++ hif_hdr.hdr.client_ctrl; ++ flags = CL_DESC_FIRST; ++ ++ } else { ++ flags = 0; ++ } ++ ++ if (local_desc.ctrl & BD_CTRL_LIFM) ++ flags |= CL_DESC_LAST; ++ ++ /* Check for valid client id and still registered */ ++ if ((hif->client_id >= HIF_CLIENTS_MAX) || ++ !(test_bit(hif->client_id, ++ &hif->shm->g_client_status[0]))) { ++ printk_ratelimited("%s: packet with invalid client id %d q_num %d\n", ++ __func__, ++ hif->client_id, ++ hif->qno); ++ ++ free_buf = pkt_hdr; ++ ++ goto pkt_drop; ++ } ++ ++ /* Check to valid queue number */ ++ if (hif->client[hif->client_id].rx_qn <= hif->qno) { ++ pr_info("%s: packet with invalid queue: %d\n" ++ , __func__, hif->qno); ++ hif->qno = 0; ++ } ++ ++ free_buf = ++ client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno], ++ (void *)pkt_hdr, len, flags, ++ hif->client_ctrl, &buf_size); ++ ++ hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND, ++ hif->qno); ++ ++ if (unlikely(!free_buf)) { ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++; ++#endif ++ /* ++ * If we want to keep in polling mode to retry later, ++ * we need to tell napi that we consumed ++ * the full budget or we will hit a livelock scenario. ++ * The core code keeps this napi instance ++ * at the head of the list and none of the other ++ * instances get to run ++ */ ++ rx_processed = budget; ++ ++ if (flags & CL_DESC_FIRST) ++ hif->started = 0; ++ ++ break; ++ } ++ ++pkt_drop: ++ /*Fill free buffer in the descriptor */ ++ hif->rx_buf_addr[rtc] = free_buf; ++ hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size); ++ writel((DDR_PHYS_TO_PFE ++ ((u32)dma_map_single(hif->dev, ++ free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE))), ++ &desc->data); ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ wmb(); ++ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR | ++ BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc])), ++ &desc->ctrl); ++ ++ rtc = (rtc + 1) & (hif->rx_ring_size - 1); ++ ++ if (local_desc.ctrl & BD_CTRL_LIFM) { ++ if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) { ++ rx_processed++; ++ ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_PACKET_COUNT]++; ++#endif ++ } ++ hif->started = 0; ++ } ++ } ++ ++ hif->rxtoclean_index = rtc; ++ spin_unlock_bh(&hif->lock); ++ ++ /* we made some progress, re-start rx dma in case it stopped */ ++ hif_rx_dma_start(); ++ ++ return rx_processed; ++} ++ ++/* ++ * client_ack_txpacket- ++ * This function ack the Tx packet in the give client Tx queue by resetting ++ * ownership bit in the descriptor. ++ */ ++static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id, ++ unsigned int q_no) ++{ ++ struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no]; ++ struct tx_queue_desc *desc = queue->base + queue->ack_idx; ++ ++ if (readl(&desc->ctrl) & CL_DESC_OWN) { ++ writel((readl(&desc->ctrl) & ~CL_DESC_OWN), &desc->ctrl); ++ queue->ack_idx = (queue->ack_idx + 1) & (queue->size - 1); ++ ++ return 0; ++ ++ } else { ++ /*This should not happen */ ++ pr_err("%s: %d %d %d %d %d %p %d\n", __func__, ++ hif->txtosend, hif->txtoclean, hif->txavail, ++ client_id, q_no, queue, queue->ack_idx); ++ WARN(1, "%s: doesn't own this descriptor", __func__); ++ return 1; ++ } ++} ++ ++void __hif_tx_done_process(struct pfe_hif *hif, int count) ++{ ++ struct hif_desc *desc; ++ struct hif_desc_sw *desc_sw; ++ int ttc, tx_avl; ++ int pkts_done[HIF_CLIENTS_MAX] = {0, 0}; ++ ++ ttc = hif->txtoclean; ++ tx_avl = hif->txavail; ++ ++ while ((tx_avl < hif->tx_ring_size) && count--) { ++ desc = hif->tx_base + ttc; ++ ++ if (readl(&desc->ctrl) & BD_CTRL_DESC_EN) ++ break; ++ ++ desc_sw = &hif->tx_sw_queue[ttc]; ++ ++ if (desc_sw->data) { ++ /* ++ * dmap_unmap_single(hif->dev, desc_sw->data, ++ * desc_sw->len, DMA_TO_DEVICE); ++ */ ++ dma_unmap_single(hif->dev, desc_sw->data, ++ desc_sw->len, DMA_TO_DEVICE); ++ } ++ ++ if (desc_sw->client_id >= HIF_CLIENTS_MAX) { ++ pr_err("Invalid cl id %d\n", desc_sw->client_id); ++ break; ++ } ++ ++ pkts_done[desc_sw->client_id]++; ++ ++ client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no); ++ ++ ttc = (ttc + 1) & (hif->tx_ring_size - 1); ++ tx_avl++; ++ } ++ ++ if (pkts_done[0]) ++ hif_lib_indicate_client(0, EVENT_TXDONE_IND, 0); ++ if (pkts_done[1]) ++ hif_lib_indicate_client(1, EVENT_TXDONE_IND, 0); ++ ++ hif->txtoclean = ttc; ++ hif->txavail = tx_avl; ++ ++ if (!count) { ++ tasklet_schedule(&hif->tx_cleanup_tasklet); ++ } else { ++ /*Enable Tx done interrupt */ ++ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_TXPKT_INT, ++ HIF_INT_ENABLE); ++ } ++} ++ ++static void pfe_tx_do_cleanup(unsigned long data) ++{ ++ struct pfe_hif *hif = (struct pfe_hif *)data; ++ ++ writel(HIF_INT | HIF_TXPKT_INT, HIF_INT_SRC); ++ ++ hif_tx_done_process(hif, 64); ++} ++ ++/* ++ * __hif_xmit_pkt - ++ * This function puts one packet in the HIF Tx queue ++ */ ++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int ++ q_no, void *data, u32 len, unsigned int flags) ++{ ++ struct hif_desc *desc; ++ struct hif_desc_sw *desc_sw; ++ ++ desc = hif->tx_base + hif->txtosend; ++ desc_sw = &hif->tx_sw_queue[hif->txtosend]; ++ ++ desc_sw->len = len; ++ desc_sw->client_id = client_id; ++ desc_sw->q_no = q_no; ++ desc_sw->flags = flags; ++ ++ if (flags & HIF_DONT_DMA_MAP) { ++ desc_sw->data = 0; ++ writel((u32)DDR_PHYS_TO_PFE(data), &desc->data); ++ } else { ++ desc_sw->data = dma_map_single(hif->dev, data, len, ++ DMA_TO_DEVICE); ++ writel((u32)DDR_PHYS_TO_PFE(desc_sw->data), &desc->data); ++ } ++ ++ hif->txtosend = (hif->txtosend + 1) & (hif->tx_ring_size - 1); ++ hif->txavail--; ++ ++ if ((!((flags & HIF_DATA_VALID) && (flags & ++ HIF_LAST_BUFFER)))) ++ goto skip_tx; ++ ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ wmb(); ++ ++ do { ++ desc_sw = &hif->tx_sw_queue[hif->txtoflush]; ++ desc = hif->tx_base + hif->txtoflush; ++ ++ if (desc_sw->flags & HIF_LAST_BUFFER) { ++ writel((BD_CTRL_LIFM | ++ BD_CTRL_BRFETCH_DISABLE | BD_CTRL_RTFETCH_DISABLE ++ | BD_CTRL_PARSE_DISABLE | BD_CTRL_DESC_EN | ++ BD_CTRL_PKT_INT_EN | BD_BUF_LEN(desc_sw->len)), ++ &desc->ctrl); ++ } else { ++ writel((BD_CTRL_DESC_EN | ++ BD_BUF_LEN(desc_sw->len)), &desc->ctrl); ++ } ++ hif->txtoflush = (hif->txtoflush + 1) & (hif->tx_ring_size - 1); ++ } ++ while (hif->txtoflush != hif->txtosend) ++ ; ++ ++skip_tx: ++ return; ++} ++ ++static irqreturn_t wol_isr(int irq, void *dev_id) ++{ ++ pr_info("WoL\n"); ++ gemac_set_wol(EMAC1_BASE_ADDR, 0); ++ gemac_set_wol(EMAC2_BASE_ADDR, 0); ++ return IRQ_HANDLED; ++} ++ ++/* ++ * hif_isr- ++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block ++ */ ++static irqreturn_t hif_isr(int irq, void *dev_id) ++{ ++ struct pfe_hif *hif = (struct pfe_hif *)dev_id; ++ int int_status; ++ int int_enable_mask; ++ ++ /*Read hif interrupt source register */ ++ int_status = readl_relaxed(HIF_INT_SRC); ++ int_enable_mask = readl_relaxed(HIF_INT_ENABLE); ++ ++ if ((int_status & HIF_INT) == 0) ++ return IRQ_NONE; ++ ++ int_status &= ~(HIF_INT); ++ ++ if (int_status & HIF_RXPKT_INT) { ++ int_status &= ~(HIF_RXPKT_INT); ++ int_enable_mask &= ~(HIF_RXPKT_INT); ++ ++ napi_first_batch = 1; ++ ++ if (napi_schedule_prep(&hif->napi)) { ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_SCHED_COUNT]++; ++#endif ++ __napi_schedule(&hif->napi); ++ } ++ } ++ ++ if (int_status & HIF_TXPKT_INT) { ++ int_status &= ~(HIF_TXPKT_INT); ++ int_enable_mask &= ~(HIF_TXPKT_INT); ++ /*Schedule tx cleanup tassklet */ ++ tasklet_schedule(&hif->tx_cleanup_tasklet); ++ } ++ ++ /*Disable interrupts, they will be enabled after they are serviced */ ++ writel_relaxed(int_enable_mask, HIF_INT_ENABLE); ++ ++ if (int_status) { ++ pr_info("%s : Invalid interrupt : %d\n", __func__, ++ int_status); ++ writel(int_status, HIF_INT_SRC); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2) ++{ ++ unsigned int client_id = data1; ++ ++ if (client_id >= HIF_CLIENTS_MAX) { ++ pr_err("%s: client id %d out of bounds\n", __func__, ++ client_id); ++ return; ++ } ++ ++ switch (req) { ++ case REQUEST_CL_REGISTER: ++ /* Request for register a client */ ++ pr_info("%s: register client_id %d\n", ++ __func__, client_id); ++ pfe_hif_client_register(hif, client_id, (struct ++ hif_client_shm *)&hif->shm->client[client_id]); ++ break; ++ ++ case REQUEST_CL_UNREGISTER: ++ pr_info("%s: unregister client_id %d\n", ++ __func__, client_id); ++ ++ /* Request for unregister a client */ ++ pfe_hif_client_unregister(hif, client_id); ++ ++ break; ++ ++ default: ++ pr_err("%s: unsupported request %d\n", ++ __func__, req); ++ break; ++ } ++ ++ /* ++ * Process client Tx queues ++ * Currently we don't have checking for tx pending ++ */ ++} ++ ++/* ++ * pfe_hif_rx_poll ++ * This function is NAPI poll function to process HIF Rx queue. ++ */ ++static int pfe_hif_rx_poll(struct napi_struct *napi, int budget) ++{ ++ struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi); ++ int work_done; ++ ++#ifdef HIF_NAPI_STATS ++ hif->napi_counters[NAPI_POLL_COUNT]++; ++#endif ++ ++ work_done = pfe_hif_rx_process(hif, budget); ++ ++ if (work_done < budget) { ++ napi_complete(napi); ++ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_RXPKT_INT, ++ HIF_INT_ENABLE); ++ } ++#ifdef HIF_NAPI_STATS ++ else ++ hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++; ++#endif ++ ++ return work_done; ++} ++ ++/* ++ * pfe_hif_init ++ * This function initializes the baseaddresses and irq, etc. ++ */ ++int pfe_hif_init(struct pfe *pfe) ++{ ++ struct pfe_hif *hif = &pfe->hif; ++ int err; ++ ++ pr_info("%s\n", __func__); ++ ++ hif->dev = pfe->dev; ++ hif->irq = pfe->hif_irq; ++ ++ err = pfe_hif_alloc_descr(hif); ++ if (err) ++ goto err0; ++ ++ if (pfe_hif_init_buffers(hif)) { ++ pr_err("%s: Could not initialize buffer descriptors\n" ++ , __func__); ++ err = -ENOMEM; ++ goto err1; ++ } ++ ++ /* Initialize NAPI for Rx processing */ ++ init_dummy_netdev(&hif->dummy_dev); ++ netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll, ++ HIF_RX_POLL_WEIGHT); ++ napi_enable(&hif->napi); ++ ++ spin_lock_init(&hif->tx_lock); ++ spin_lock_init(&hif->lock); ++ ++ hif_init(); ++ hif_rx_enable(); ++ hif_tx_enable(); ++ ++ /* Disable tx done interrupt */ ++ writel(HIF_INT_MASK, HIF_INT_ENABLE); ++ ++ gpi_enable(HGPI_BASE_ADDR); ++ ++ err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif); ++ if (err) { ++ pr_err("%s: failed to get the hif IRQ = %d\n", ++ __func__, hif->irq); ++ goto err1; ++ } ++ ++ err = request_irq(pfe->wol_irq, wol_isr, 0, "pfe_wol", pfe); ++ if (err) { ++ pr_err("%s: failed to get the wol IRQ = %d\n", ++ __func__, pfe->wol_irq); ++ goto err1; ++ } ++ ++ tasklet_init(&hif->tx_cleanup_tasklet, ++ (void(*)(unsigned long))pfe_tx_do_cleanup, ++ (unsigned long)hif); ++ ++ return 0; ++err1: ++ pfe_hif_free_descr(hif); ++err0: ++ return err; ++} ++ ++/* pfe_hif_exit- */ ++void pfe_hif_exit(struct pfe *pfe) ++{ ++ struct pfe_hif *hif = &pfe->hif; ++ ++ pr_info("%s\n", __func__); ++ ++ tasklet_kill(&hif->tx_cleanup_tasklet); ++ ++ spin_lock_bh(&hif->lock); ++ hif->shm->g_client_status[0] = 0; ++ /* Make sure all clients are disabled*/ ++ hif->shm->g_client_status[1] = 0; ++ ++ spin_unlock_bh(&hif->lock); ++ ++ /*Disable Rx/Tx */ ++ gpi_disable(HGPI_BASE_ADDR); ++ hif_rx_disable(); ++ hif_tx_disable(); ++ ++ napi_disable(&hif->napi); ++ netif_napi_del(&hif->napi); ++ ++ free_irq(pfe->wol_irq, pfe); ++ free_irq(hif->irq, hif); ++ ++ pfe_hif_release_buffers(hif); ++ pfe_hif_free_descr(hif); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif.h +@@ -0,0 +1,199 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_HIF_H_ ++#define _PFE_HIF_H_ ++ ++#include ++ ++#define HIF_NAPI_STATS ++ ++#define HIF_CLIENT_QUEUES_MAX 16 ++#define HIF_RX_POLL_WEIGHT 64 ++ ++#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */ ++#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1) ++#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \ ++ & HIF_RX_PKT_MIN_SIZE_MASK) ++#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \ ++ - 1)) & HIF_RX_PKT_MIN_SIZE_MASK) ++ ++enum { ++ NAPI_SCHED_COUNT = 0, ++ NAPI_POLL_COUNT, ++ NAPI_PACKET_COUNT, ++ NAPI_DESC_COUNT, ++ NAPI_FULL_BUDGET_COUNT, ++ NAPI_CLIENT_FULL_COUNT, ++ NAPI_MAX_COUNT ++}; ++ ++/* ++ * HIF_TX_DESC_NT value should be always greter than 4, ++ * Otherwise HIF_TX_POLL_MARK will become zero. ++ */ ++#define HIF_RX_DESC_NT 256 ++#define HIF_TX_DESC_NT 2048 ++ ++#define HIF_FIRST_BUFFER BIT(0) ++#define HIF_LAST_BUFFER BIT(1) ++#define HIF_DONT_DMA_MAP BIT(2) ++#define HIF_DATA_VALID BIT(3) ++#define HIF_TSO BIT(4) ++ ++enum { ++ PFE_CL_GEM0 = 0, ++ PFE_CL_GEM1, ++ HIF_CLIENTS_MAX ++}; ++ ++/*structure to store client queue info */ ++struct hif_rx_queue { ++ struct rx_queue_desc *base; ++ u32 size; ++ u32 write_idx; ++}; ++ ++struct hif_tx_queue { ++ struct tx_queue_desc *base; ++ u32 size; ++ u32 ack_idx; ++}; ++ ++/*Structure to store the client info */ ++struct hif_client { ++ int rx_qn; ++ struct hif_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; ++ int tx_qn; ++ struct hif_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; ++}; ++ ++/*HIF hardware buffer descriptor */ ++struct hif_desc { ++ u32 ctrl; ++ u32 status; ++ u32 data; ++ u32 next; ++}; ++ ++struct __hif_desc { ++ u32 ctrl; ++ u32 status; ++ u32 data; ++}; ++ ++struct hif_desc_sw { ++ dma_addr_t data; ++ u16 len; ++ u8 client_id; ++ u8 q_no; ++ u16 flags; ++}; ++ ++struct hif_hdr { ++ u8 client_id; ++ u8 q_num; ++ u16 client_ctrl; ++ u16 client_ctrl1; ++}; ++ ++struct __hif_hdr { ++ union { ++ struct hif_hdr hdr; ++ u32 word[2]; ++ }; ++}; ++ ++struct hif_ipsec_hdr { ++ u16 sa_handle[2]; ++} __packed; ++ ++/* HIF_CTRL_TX... defines */ ++#define HIF_CTRL_TX_CHECKSUM BIT(2) ++ ++/* HIF_CTRL_RX... defines */ ++#define HIF_CTRL_RX_OFFSET_OFST (24) ++#define HIF_CTRL_RX_CHECKSUMMED BIT(2) ++#define HIF_CTRL_RX_CONTINUED BIT(1) ++ ++struct pfe_hif { ++ /* To store registered clients in hif layer */ ++ struct hif_client client[HIF_CLIENTS_MAX]; ++ struct hif_shm *shm; ++ int irq; ++ ++ void *descr_baseaddr_v; ++ unsigned long descr_baseaddr_p; ++ ++ struct hif_desc *rx_base; ++ u32 rx_ring_size; ++ u32 rxtoclean_index; ++ void *rx_buf_addr[HIF_RX_DESC_NT]; ++ int rx_buf_len[HIF_RX_DESC_NT]; ++ unsigned int qno; ++ unsigned int client_id; ++ unsigned int client_ctrl; ++ unsigned int started; ++ ++ struct hif_desc *tx_base; ++ u32 tx_ring_size; ++ u32 txtosend; ++ u32 txtoclean; ++ u32 txavail; ++ u32 txtoflush; ++ struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT]; ++ ++/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */ ++ spinlock_t tx_lock; ++/* lock synchronizes hif rx queue processing */ ++ spinlock_t lock; ++ struct net_device dummy_dev; ++ struct napi_struct napi; ++ struct device *dev; ++ ++#ifdef HIF_NAPI_STATS ++ unsigned int napi_counters[NAPI_MAX_COUNT]; ++#endif ++ struct tasklet_struct tx_cleanup_tasklet; ++}; ++ ++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int ++ q_no, void *data, u32 len, unsigned int flags); ++int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, ++ void *data, unsigned int len); ++void __hif_tx_done_process(struct pfe_hif *hif, int count); ++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int ++ data2); ++int pfe_hif_init(struct pfe *pfe); ++void pfe_hif_exit(struct pfe *pfe); ++void pfe_hif_rx_idle(struct pfe_hif *hif); ++static inline void hif_tx_done_process(struct pfe_hif *hif, int count) ++{ ++ spin_lock_bh(&hif->tx_lock); ++ __hif_tx_done_process(hif, count); ++ spin_unlock_bh(&hif->tx_lock); ++} ++ ++static inline void hif_tx_lock(struct pfe_hif *hif) ++{ ++ spin_lock_bh(&hif->tx_lock); ++} ++ ++static inline void hif_tx_unlock(struct pfe_hif *hif) ++{ ++ spin_unlock_bh(&hif->tx_lock); ++} ++ ++static inline int __hif_tx_avail(struct pfe_hif *hif) ++{ ++ return hif->txavail; ++} ++ ++#define __memcpy8(dst, src) memcpy(dst, src, 8) ++#define __memcpy12(dst, src) memcpy(dst, src, 12) ++#define __memcpy(dst, src, len) memcpy(dst, src, len) ++ ++#endif /* _PFE_HIF_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c +@@ -0,0 +1,628 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++#include "pfe_hif.h" ++#include "pfe_hif_lib.h" ++ ++unsigned int lro_mode; ++unsigned int page_mode; ++unsigned int tx_qos = 1; ++module_param(tx_qos, uint, 0444); ++MODULE_PARM_DESC(tx_qos, "0: disable ,\n" ++ "1: enable (default), guarantee no packet drop at TMU level\n"); ++unsigned int pfe_pkt_size; ++unsigned int pfe_pkt_headroom; ++unsigned int emac_txq_cnt; ++ ++/* ++ * @pfe_hal_lib.c. ++ * Common functions used by HIF client drivers ++ */ ++ ++/*HIF shared memory Global variable */ ++struct hif_shm ghif_shm; ++ ++/* Cleanup the HIF shared memory, release HIF rx_buffer_pool. ++ * This function should be called after pfe_hif_exit ++ * ++ * @param[in] hif_shm Shared memory address location in DDR ++ */ ++static void pfe_hif_shm_clean(struct hif_shm *hif_shm) ++{ ++ int i; ++ void *pkt; ++ ++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { ++ pkt = hif_shm->rx_buf_pool[i]; ++ if (pkt) { ++ hif_shm->rx_buf_pool[i] = NULL; ++ pkt -= pfe_pkt_headroom; ++ ++ if (page_mode) ++ put_page(virt_to_page(pkt)); ++ else ++ kfree(pkt); ++ } ++ } ++} ++ ++/* Initialize shared memory used between HIF driver and clients, ++ * allocate rx_buffer_pool required for HIF Rx descriptors. ++ * This function should be called before initializing HIF driver. ++ * ++ * @param[in] hif_shm Shared memory address location in DDR ++ * @rerurn 0 - on succes, <0 on fail to initialize ++ */ ++static int pfe_hif_shm_init(struct hif_shm *hif_shm) ++{ ++ int i; ++ void *pkt; ++ ++ memset(hif_shm, 0, sizeof(struct hif_shm)); ++ hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT; ++ ++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { ++ if (page_mode) { ++ pkt = (void *)__get_free_page(GFP_KERNEL | ++ GFP_DMA_PFE); ++ } else { ++ pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE); ++ } ++ ++ if (pkt) ++ hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom; ++ else ++ goto err0; ++ } ++ ++ return 0; ++ ++err0: ++ pr_err("%s Low memory\n", __func__); ++ pfe_hif_shm_clean(hif_shm); ++ return -ENOMEM; ++} ++ ++/*This function sends indication to HIF driver ++ * ++ * @param[in] hif hif context ++ */ ++static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int ++ data2) ++{ ++ hif_process_client_req(hif, req, data1, data2); ++} ++ ++void hif_lib_indicate_client(int client_id, int event_type, int qno) ++{ ++ struct hif_client_s *client = pfe->hif_client[client_id]; ++ ++ if (!client || (event_type >= HIF_EVENT_MAX) || (qno >= ++ HIF_CLIENT_QUEUES_MAX)) ++ return; ++ ++ if (!test_and_set_bit(qno, &client->queue_mask[event_type])) ++ client->event_handler(client->priv, event_type, qno); ++} ++ ++/*This function releases Rx queue descriptors memory and pre-filled buffers ++ * ++ * @param[in] client hif_client context ++ */ ++static void hif_lib_client_release_rx_buffers(struct hif_client_s *client) ++{ ++ struct rx_queue_desc *desc; ++ int qno, ii; ++ void *buf; ++ ++ for (qno = 0; qno < client->rx_qn; qno++) { ++ desc = client->rx_q[qno].base; ++ ++ for (ii = 0; ii < client->rx_q[qno].size; ii++) { ++ buf = (void *)desc->data; ++ if (buf) { ++ buf -= pfe_pkt_headroom; ++ ++ if (page_mode) ++ free_page((unsigned long)buf); ++ else ++ kfree(buf); ++ ++ desc->ctrl = 0; ++ } ++ ++ desc++; ++ } ++ } ++ ++ kfree(client->rx_qbase); ++} ++ ++/*This function allocates memory for the rxq descriptors and pre-fill rx queues ++ * with buffers. ++ * @param[in] client client context ++ * @param[in] q_size size of the rxQ, all queues are of same size ++ */ ++static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int ++ q_size) ++{ ++ struct rx_queue_desc *desc; ++ struct hif_client_rx_queue *queue; ++ int ii, qno; ++ ++ /*Allocate memory for the client queues */ ++ client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct ++ rx_queue_desc), GFP_KERNEL); ++ if (!client->rx_qbase) ++ goto err; ++ ++ for (qno = 0; qno < client->rx_qn; qno++) { ++ queue = &client->rx_q[qno]; ++ ++ queue->base = client->rx_qbase + qno * q_size * sizeof(struct ++ rx_queue_desc); ++ queue->size = q_size; ++ queue->read_idx = 0; ++ queue->write_idx = 0; ++ ++ pr_debug("rx queue: %d, base: %p, size: %d\n", qno, ++ queue->base, queue->size); ++ } ++ ++ for (qno = 0; qno < client->rx_qn; qno++) { ++ queue = &client->rx_q[qno]; ++ desc = queue->base; ++ ++ for (ii = 0; ii < queue->size; ii++) { ++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | ++ CL_DESC_OWN; ++ desc++; ++ } ++ } ++ ++ return 0; ++ ++err: ++ return 1; ++} ++ ++ ++static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue) ++{ ++ pr_debug("%s\n", __func__); ++ ++ /* ++ * Check if there are any pending packets. Client must flush the tx ++ * queues before unregistering, by calling by calling ++ * hif_lib_tx_get_next_complete() ++ * ++ * Hif no longer calls since we are no longer registered ++ */ ++ if (queue->tx_pending) ++ pr_err("%s: pending transmit packets\n", __func__); ++} ++ ++static void hif_lib_client_release_tx_buffers(struct hif_client_s *client) ++{ ++ int qno; ++ ++ pr_debug("%s\n", __func__); ++ ++ for (qno = 0; qno < client->tx_qn; qno++) ++ hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]); ++ ++ kfree(client->tx_qbase); ++} ++ ++static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int ++ q_size) ++{ ++ struct hif_client_tx_queue *queue; ++ int qno; ++ ++ client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct ++ tx_queue_desc), GFP_KERNEL); ++ if (!client->tx_qbase) ++ return 1; ++ ++ for (qno = 0; qno < client->tx_qn; qno++) { ++ queue = &client->tx_q[qno]; ++ ++ queue->base = client->tx_qbase + qno * q_size * sizeof(struct ++ tx_queue_desc); ++ queue->size = q_size; ++ queue->read_idx = 0; ++ queue->write_idx = 0; ++ queue->tx_pending = 0; ++ queue->nocpy_flag = 0; ++ queue->prev_tmu_tx_pkts = 0; ++ queue->done_tmu_tx_pkts = 0; ++ ++ pr_debug("tx queue: %d, base: %p, size: %d\n", qno, ++ queue->base, queue->size); ++ } ++ ++ return 0; ++} ++ ++static int hif_lib_event_dummy(void *priv, int event_type, int qno) ++{ ++ return 0; ++} ++ ++int hif_lib_client_register(struct hif_client_s *client) ++{ ++ struct hif_shm *hif_shm; ++ struct hif_client_shm *client_shm; ++ int err, i; ++ /* int loop_cnt = 0; */ ++ ++ pr_debug("%s\n", __func__); ++ ++ /*Allocate memory before spin_lock*/ ++ if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) { ++ err = -ENOMEM; ++ goto err_rx; ++ } ++ ++ if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) { ++ err = -ENOMEM; ++ goto err_tx; ++ } ++ ++ spin_lock_bh(&pfe->hif.lock); ++ if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) || ++ (pfe->hif_client[client->id])) { ++ err = -EINVAL; ++ goto err; ++ } ++ ++ hif_shm = client->pfe->hif.shm; ++ ++ if (!client->event_handler) ++ client->event_handler = hif_lib_event_dummy; ++ ++ /*Initialize client specific shared memory */ ++ client_shm = (struct hif_client_shm *)&hif_shm->client[client->id]; ++ client_shm->rx_qbase = (unsigned long int)client->rx_qbase; ++ client_shm->rx_qsize = client->rx_qsize; ++ client_shm->tx_qbase = (unsigned long int)client->tx_qbase; ++ client_shm->tx_qsize = client->tx_qsize; ++ client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) | ++ (client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST); ++ /* spin_lock_init(&client->rx_lock); */ ++ ++ for (i = 0; i < HIF_EVENT_MAX; i++) { ++ client->queue_mask[i] = 0; /* ++ * By default all events are ++ * unmasked ++ */ ++ } ++ ++ /*Indicate to HIF driver*/ ++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0); ++ ++ pr_debug("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n", ++ __func__, client, client->id, client->tx_qsize, ++ client->rx_qsize); ++ ++ client->cpu_id = -1; ++ ++ pfe->hif_client[client->id] = client; ++ spin_unlock_bh(&pfe->hif.lock); ++ ++ return 0; ++ ++err: ++ spin_unlock_bh(&pfe->hif.lock); ++ hif_lib_client_release_tx_buffers(client); ++ ++err_tx: ++ hif_lib_client_release_rx_buffers(client); ++ ++err_rx: ++ return err; ++} ++ ++int hif_lib_client_unregister(struct hif_client_s *client) ++{ ++ struct pfe *pfe = client->pfe; ++ u32 client_id = client->id; ++ ++ pr_info( ++ "%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n" ++ , __func__, client, client->id, client->tx_qsize, ++ client->rx_qsize); ++ ++ spin_lock_bh(&pfe->hif.lock); ++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0); ++ ++ hif_lib_client_release_tx_buffers(client); ++ hif_lib_client_release_rx_buffers(client); ++ pfe->hif_client[client_id] = NULL; ++ spin_unlock_bh(&pfe->hif.lock); ++ ++ return 0; ++} ++ ++int hif_lib_event_handler_start(struct hif_client_s *client, int event, ++ int qno) ++{ ++ struct hif_client_rx_queue *queue = &client->rx_q[qno]; ++ struct rx_queue_desc *desc = queue->base + queue->read_idx; ++ ++ if ((event >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX)) { ++ pr_debug("%s: Unsupported event : %d queue number : %d\n", ++ __func__, event, qno); ++ return -1; ++ } ++ ++ test_and_clear_bit(qno, &client->queue_mask[event]); ++ ++ switch (event) { ++ case EVENT_RX_PKT_IND: ++ if (!(desc->ctrl & CL_DESC_OWN)) ++ hif_lib_indicate_client(client->id, ++ EVENT_RX_PKT_IND, qno); ++ break; ++ ++ case EVENT_HIGH_RX_WM: ++ case EVENT_TXDONE_IND: ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++/* ++ * This function gets one packet from the specified client queue ++ * It also refill the rx buffer ++ */ ++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int ++ *ofst, unsigned int *rx_ctrl, ++ unsigned int *desc_ctrl, void **priv_data) ++{ ++ struct hif_client_rx_queue *queue = &client->rx_q[qno]; ++ struct rx_queue_desc *desc; ++ void *pkt = NULL; ++ ++ /* ++ * Following lock is to protect rx queue access from, ++ * hif_lib_event_handler_start. ++ * In general below lock is not required, because hif_lib_xmit_pkt and ++ * hif_lib_event_handler_start are called from napi poll and which is ++ * not re-entrant. But if some client use in different way this lock is ++ * required. ++ */ ++ /*spin_lock_irqsave(&client->rx_lock, flags); */ ++ desc = queue->base + queue->read_idx; ++ if (!(desc->ctrl & CL_DESC_OWN)) { ++ pkt = desc->data - pfe_pkt_headroom; ++ ++ *rx_ctrl = desc->client_ctrl; ++ *desc_ctrl = desc->ctrl; ++ ++ if (desc->ctrl & CL_DESC_FIRST) { ++ u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST; ++ ++ if (size) { ++ size += PFE_PARSE_INFO_SIZE; ++ *len = CL_DESC_BUF_LEN(desc->ctrl) - ++ PFE_PKT_HEADER_SZ - size; ++ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ ++ + size; ++ *priv_data = desc->data + PFE_PKT_HEADER_SZ; ++ } else { ++ *len = CL_DESC_BUF_LEN(desc->ctrl) - ++ PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE; ++ *ofst = pfe_pkt_headroom ++ + PFE_PKT_HEADER_SZ ++ + PFE_PARSE_INFO_SIZE; ++ *priv_data = NULL; ++ } ++ ++ } else { ++ *len = CL_DESC_BUF_LEN(desc->ctrl); ++ *ofst = pfe_pkt_headroom; ++ } ++ ++ /* ++ * Needed so we don't free a buffer/page ++ * twice on module_exit ++ */ ++ desc->data = NULL; ++ ++ /* ++ * Ensure everything else is written to DDR before ++ * writing bd->ctrl ++ */ ++ smp_wmb(); ++ ++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN; ++ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1); ++ } ++ ++ /*spin_unlock_irqrestore(&client->rx_lock, flags); */ ++ return pkt; ++} ++ ++static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int ++ client_id, unsigned int qno, ++ u32 client_ctrl) ++{ ++ /* Optimize the write since the destinaton may be non-cacheable */ ++ if (!((unsigned long)pkt_hdr & 0x3)) { ++ ((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) | ++ client_id; ++ } else { ++ ((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF); ++ ((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF); ++ } ++} ++ ++/*This function puts the given packet in the specific client queue */ ++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void ++ *data, unsigned int len, u32 client_ctrl, ++ unsigned int flags, void *client_data) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ struct tx_queue_desc *desc = queue->base + queue->write_idx; ++ ++ /* First buffer */ ++ if (flags & HIF_FIRST_BUFFER) { ++ data -= sizeof(struct hif_hdr); ++ len += sizeof(struct hif_hdr); ++ ++ hif_hdr_write(data, client->id, qno, client_ctrl); ++ } ++ ++ desc->data = client_data; ++ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags); ++ ++ __hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags); ++ ++ queue->write_idx = (queue->write_idx + 1) & (queue->size - 1); ++ queue->tx_pending++; ++ queue->jiffies_last_packet = jiffies; ++} ++ ++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, ++ unsigned int *flags, int count) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ struct tx_queue_desc *desc = queue->base + queue->read_idx; ++ ++ pr_debug("%s: qno : %d rd_indx: %d pending:%d\n", __func__, qno, ++ queue->read_idx, queue->tx_pending); ++ ++ if (!queue->tx_pending) ++ return NULL; ++ ++ if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) { ++ u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID + ++ client->id, TMU_DM_TX_TRANS, 4)); ++ ++ if (queue->prev_tmu_tx_pkts > tmu_tx_pkts) ++ queue->done_tmu_tx_pkts = UINT_MAX - ++ queue->prev_tmu_tx_pkts + tmu_tx_pkts; ++ else ++ queue->done_tmu_tx_pkts = tmu_tx_pkts - ++ queue->prev_tmu_tx_pkts; ++ ++ queue->prev_tmu_tx_pkts = tmu_tx_pkts; ++ ++ if (!queue->done_tmu_tx_pkts) ++ return NULL; ++ } ++ ++ if (desc->ctrl & CL_DESC_OWN) ++ return NULL; ++ ++ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1); ++ queue->tx_pending--; ++ ++ *flags = CL_DESC_GET_FLAGS(desc->ctrl); ++ ++ if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER)) ++ queue->done_tmu_tx_pkts--; ++ ++ return desc->data; ++} ++ ++static void hif_lib_tmu_credit_init(struct pfe *pfe) ++{ ++ int i, q; ++ ++ for (i = 0; i < NUM_GEMAC_SUPPORT; i++) ++ for (q = 0; q < emac_txq_cnt; q++) { ++ pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ? ++ DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH; ++ pfe->tmu_credit.tx_credit[i][q] = ++ pfe->tmu_credit.tx_credit_max[i][q]; ++ } ++} ++ ++/* __hif_lib_update_credit ++ * ++ * @param[in] client hif client context ++ * @param[in] queue queue number in match with TMU ++ */ ++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue) ++{ ++ unsigned int tmu_tx_packets, tmp; ++ ++ if (tx_qos) { ++ tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID + ++ client->id, (TMU_DM_TX_TRANS + (queue * 4)), 4)); ++ ++ /* tx_packets counter overflowed */ ++ if (tmu_tx_packets > ++ pfe->tmu_credit.tx_packets[client->id][queue]) { ++ tmp = UINT_MAX - tmu_tx_packets + ++ pfe->tmu_credit.tx_packets[client->id][queue]; ++ ++ pfe->tmu_credit.tx_credit[client->id][queue] = ++ pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp; ++ } else { ++ /* TMU tx <= pfe_eth tx, normal case or both OF since ++ * last time ++ */ ++ pfe->tmu_credit.tx_credit[client->id][queue] = ++ pfe->tmu_credit.tx_credit_max[client->id][queue] - ++ (pfe->tmu_credit.tx_packets[client->id][queue] - ++ tmu_tx_packets); ++ } ++ } ++} ++ ++int pfe_hif_lib_init(struct pfe *pfe) ++{ ++ int rc; ++ ++ pr_info("%s\n", __func__); ++ ++ if (lro_mode) { ++ page_mode = 1; ++ pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE); ++ pfe_pkt_headroom = 0; ++ } else { ++ page_mode = 0; ++ pfe_pkt_size = PFE_PKT_SIZE; ++ pfe_pkt_headroom = PFE_PKT_HEADROOM; ++ } ++ ++ if (tx_qos) ++ emac_txq_cnt = EMAC_TXQ_CNT / 2; ++ else ++ emac_txq_cnt = EMAC_TXQ_CNT; ++ ++ hif_lib_tmu_credit_init(pfe); ++ pfe->hif.shm = &ghif_shm; ++ rc = pfe_hif_shm_init(pfe->hif.shm); ++ ++ return rc; ++} ++ ++void pfe_hif_lib_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ pfe_hif_shm_clean(pfe->hif.shm); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h +@@ -0,0 +1,229 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_HIF_LIB_H_ ++#define _PFE_HIF_LIB_H_ ++ ++#include "pfe_hif.h" ++ ++#define HIF_CL_REQ_TIMEOUT 10 ++#define GFP_DMA_PFE 0 ++#define PFE_PARSE_INFO_SIZE 16 ++ ++enum { ++ REQUEST_CL_REGISTER = 0, ++ REQUEST_CL_UNREGISTER, ++ HIF_REQUEST_MAX ++}; ++ ++enum { ++ /* Event to indicate that client rx queue is reached water mark level */ ++ EVENT_HIGH_RX_WM = 0, ++ /* Event to indicate that, packet received for client */ ++ EVENT_RX_PKT_IND, ++ /* Event to indicate that, packet tx done for client */ ++ EVENT_TXDONE_IND, ++ HIF_EVENT_MAX ++}; ++ ++/*structure to store client queue info */ ++ ++/*structure to store client queue info */ ++struct hif_client_rx_queue { ++ struct rx_queue_desc *base; ++ u32 size; ++ u32 read_idx; ++ u32 write_idx; ++}; ++ ++struct hif_client_tx_queue { ++ struct tx_queue_desc *base; ++ u32 size; ++ u32 read_idx; ++ u32 write_idx; ++ u32 tx_pending; ++ unsigned long jiffies_last_packet; ++ u32 nocpy_flag; ++ u32 prev_tmu_tx_pkts; ++ u32 done_tmu_tx_pkts; ++}; ++ ++struct hif_client_s { ++ int id; ++ int tx_qn; ++ int rx_qn; ++ void *rx_qbase; ++ void *tx_qbase; ++ int tx_qsize; ++ int rx_qsize; ++ int cpu_id; ++ struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; ++ struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; ++ int (*event_handler)(void *priv, int event, int data); ++ unsigned long queue_mask[HIF_EVENT_MAX]; ++ struct pfe *pfe; ++ void *priv; ++}; ++ ++/* ++ * Client specific shared memory ++ * It contains number of Rx/Tx queues, base addresses and queue sizes ++ */ ++struct hif_client_shm { ++ u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */ ++ unsigned long rx_qbase; /*Rx queue base address */ ++ u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */ ++ unsigned long tx_qbase; /* Tx queue base address */ ++ u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */ ++}; ++ ++/*Client shared memory ctrl bit description */ ++#define CLIENT_CTRL_RX_Q_CNT_OFST 0 ++#define CLIENT_CTRL_TX_Q_CNT_OFST 8 ++#define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \ ++ & 0xFF) ++#define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \ ++ & 0xFF) ++ ++/* ++ * Shared memory used to communicate between HIF driver and host/client drivers ++ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be ++ * initialized with host buffers and buffers count in the pool. ++ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT. ++ * ++ */ ++struct hif_shm { ++ u32 rx_buf_pool_cnt; /*Number of rx buffers available*/ ++ /*Rx buffers required to initialize HIF rx descriptors */ ++ void *rx_buf_pool[HIF_RX_DESC_NT]; ++ unsigned long g_client_status[2]; /*Global client status bit mask */ ++ /* Client specific shared memory */ ++ struct hif_client_shm client[HIF_CLIENTS_MAX]; ++}; ++ ++#define CL_DESC_OWN BIT(31) ++/* This sets owner ship to HIF driver */ ++#define CL_DESC_LAST BIT(30) ++/* This indicates last packet for multi buffers handling */ ++#define CL_DESC_FIRST BIT(29) ++/* This indicates first packet for multi buffers handling */ ++ ++#define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF) ++#define CL_DESC_FLAGS(x) (((x) & 0xF) << 16) ++#define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF) ++ ++struct rx_queue_desc { ++ void *data; ++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ ++ u32 client_ctrl; ++}; ++ ++struct tx_queue_desc { ++ void *data; ++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ ++}; ++ ++/* HIF Rx is not working properly for 2-byte aligned buffers and ++ * ip_header should be 4byte aligned for better iperformance. ++ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned. ++ */ ++#define PFE_PKT_HEADER_SZ sizeof(struct hif_hdr) ++/* must be big enough for headroom, pkt size and skb shared info */ ++#define PFE_BUF_SIZE 2048 ++#define PFE_PKT_HEADROOM 128 ++ ++#define SKB_SHARED_INFO_SIZE SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) ++#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM \ ++ - SKB_SHARED_INFO_SIZE) ++#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */ ++#define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */ ++#define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */ ++#define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \ ++ + MAX_L4_HDR_SIZE) ++/* Used in page mode to clamp packet size to the maximum supported by the hif ++ *hw interface (<16KiB) ++ */ ++#define MAX_PFE_PKT_SIZE 16380UL ++ ++extern unsigned int pfe_pkt_size; ++extern unsigned int pfe_pkt_headroom; ++extern unsigned int page_mode; ++extern unsigned int lro_mode; ++extern unsigned int tx_qos; ++extern unsigned int emac_txq_cnt; ++ ++int pfe_hif_lib_init(struct pfe *pfe); ++void pfe_hif_lib_exit(struct pfe *pfe); ++int hif_lib_client_register(struct hif_client_s *client); ++int hif_lib_client_unregister(struct hif_client_s *client); ++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void ++ *data, unsigned int len, u32 client_ctrl, ++ unsigned int flags, void *client_data); ++int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, ++ unsigned int len, u32 client_ctrl, void *client_data); ++void hif_lib_indicate_client(int cl_id, int event, int data); ++int hif_lib_event_handler_start(struct hif_client_s *client, int event, int ++ data); ++int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno); ++int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno); ++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, ++ unsigned int *flags, int count); ++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int ++ *ofst, unsigned int *rx_ctrl, ++ unsigned int *desc_ctrl, void **priv_data); ++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue); ++void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id); ++void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int ++ enable); ++static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int ++ qno) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ ++ return (queue->size - queue->tx_pending); ++} ++ ++static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned ++ int qno) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ ++ return queue->write_idx; ++} ++ ++static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int ++ qno) ++{ ++ struct hif_client_tx_queue *queue = &client->tx_q[qno]; ++ ++ return queue->tx_pending; ++} ++ ++#define hif_lib_tx_credit_avail(pfe, id, qno) \ ++ ((pfe)->tmu_credit.tx_credit[id][qno]) ++ ++#define hif_lib_tx_credit_max(pfe, id, qno) \ ++ ((pfe)->tmu_credit.tx_credit_max[id][qno]) ++ ++/* ++ * Test comment ++ */ ++#define hif_lib_tx_credit_use(pfe, id, qno, credit) \ ++ ({ typeof(pfe) pfe_ = pfe; \ ++ typeof(id) id_ = id; \ ++ typeof(qno) qno_ = qno; \ ++ typeof(credit) credit_ = credit; \ ++ do { \ ++ if (tx_qos) { \ ++ (pfe_)->tmu_credit.tx_credit[id_][qno_]\ ++ -= credit_; \ ++ (pfe_)->tmu_credit.tx_packets[id_][qno_]\ ++ += credit_; \ ++ } \ ++ } while (0); \ ++ }) ++ ++#endif /* _PFE_HIF_LIB_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hw.c +@@ -0,0 +1,164 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include "pfe_mod.h" ++#include "pfe_hw.h" ++ ++/* Functions to handle most of pfe hw register initialization */ ++int pfe_hw_init(struct pfe *pfe, int resume) ++{ ++ struct class_cfg class_cfg = { ++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, ++ .route_table_baseaddr = pfe->ddr_phys_baseaddr + ++ ROUTE_TABLE_BASEADDR, ++ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS, ++ }; ++ ++ struct tmu_cfg tmu_cfg = { ++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, ++ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR, ++ .llm_queue_len = TMU_LLM_QUEUE_LEN, ++ }; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ struct util_cfg util_cfg = { ++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, ++ }; ++#endif ++ ++ struct BMU_CFG bmu1_cfg = { ++ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + ++ BMU1_LMEM_BASEADDR), ++ .count = BMU1_BUF_COUNT, ++ .size = BMU1_BUF_SIZE, ++ .low_watermark = 10, ++ .high_watermark = 15, ++ }; ++ ++ struct BMU_CFG bmu2_cfg = { ++ .baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr + ++ BMU2_DDR_BASEADDR), ++ .count = BMU2_BUF_COUNT, ++ .size = BMU2_BUF_SIZE, ++ .low_watermark = 250, ++ .high_watermark = 253, ++ }; ++ ++ struct gpi_cfg egpi1_cfg = { ++ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT, ++ .tmlf_txthres = EGPI1_TMLF_TXTHRES, ++ .aseq_len = EGPI1_ASEQ_LEN, ++ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC1_BASE_ADDR + ++ EMAC_TCNTRL_REG), ++ }; ++ ++ struct gpi_cfg egpi2_cfg = { ++ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT, ++ .tmlf_txthres = EGPI2_TMLF_TXTHRES, ++ .aseq_len = EGPI2_ASEQ_LEN, ++ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC2_BASE_ADDR + ++ EMAC_TCNTRL_REG), ++ }; ++ ++ struct gpi_cfg hgpi_cfg = { ++ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT, ++ .tmlf_txthres = HGPI_TMLF_TXTHRES, ++ .aseq_len = HGPI_ASEQ_LEN, ++ .mtip_pause_reg = 0, ++ }; ++ ++ pr_info("%s\n", __func__); ++ ++#if !defined(LS1012A_PFE_RESET_WA) ++ /* LS1012A needs this to make PE work correctly */ ++ writel(0x3, CLASS_PE_SYS_CLK_RATIO); ++ writel(0x3, TMU_PE_SYS_CLK_RATIO); ++ writel(0x3, UTIL_PE_SYS_CLK_RATIO); ++ usleep_range(10, 20); ++#endif ++ ++ pr_info("CLASS version: %x\n", readl(CLASS_VERSION)); ++ pr_info("TMU version: %x\n", readl(TMU_VERSION)); ++ ++ pr_info("BMU1 version: %x\n", readl(BMU1_BASE_ADDR + ++ BMU_VERSION)); ++ pr_info("BMU2 version: %x\n", readl(BMU2_BASE_ADDR + ++ BMU_VERSION)); ++ ++ pr_info("EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR + ++ GPI_VERSION)); ++ pr_info("EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR + ++ GPI_VERSION)); ++ pr_info("HGPI version: %x\n", readl(HGPI_BASE_ADDR + ++ GPI_VERSION)); ++ ++ pr_info("HIF version: %x\n", readl(HIF_VERSION)); ++ pr_info("HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION)); ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ pr_info("UTIL version: %x\n", readl(UTIL_VERSION)); ++#endif ++ while (!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE)) ++ ; ++ ++ hif_rx_disable(); ++ hif_tx_disable(); ++ ++ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg); ++ ++ pr_info("bmu_init(1) done\n"); ++ ++ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg); ++ ++ pr_info("bmu_init(2) done\n"); ++ ++ class_cfg.resume = resume ? 1 : 0; ++ ++ class_init(&class_cfg); ++ ++ pr_info("class_init() done\n"); ++ ++ tmu_init(&tmu_cfg); ++ ++ pr_info("tmu_init() done\n"); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ util_init(&util_cfg); ++ ++ pr_info("util_init() done\n"); ++#endif ++ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg); ++ ++ pr_info("gpi_init(1) done\n"); ++ ++ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg); ++ ++ pr_info("gpi_init(2) done\n"); ++ ++ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg); ++ ++ pr_info("gpi_init(hif) done\n"); ++ ++ bmu_enable(BMU1_BASE_ADDR); ++ ++ pr_info("bmu_enable(1) done\n"); ++ ++ bmu_enable(BMU2_BASE_ADDR); ++ ++ pr_info("bmu_enable(2) done\n"); ++ ++ return 0; ++} ++ ++void pfe_hw_exit(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ bmu_disable(BMU1_BASE_ADDR); ++ bmu_reset(BMU1_BASE_ADDR); ++ ++ bmu_disable(BMU2_BASE_ADDR); ++ bmu_reset(BMU2_BASE_ADDR); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_hw.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_HW_H_ ++#define _PFE_HW_H_ ++ ++#define PE_SYS_CLK_RATIO 1 /* SYS/AXI = 250MHz, HFE = 500MHz */ ++ ++int pfe_hw_init(struct pfe *pfe, int resume); ++void pfe_hw_exit(struct pfe *pfe); ++ ++#endif /* _PFE_HW_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c +@@ -0,0 +1,383 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++extern bool pfe_use_old_dts_phy; ++struct ls1012a_pfe_platform_data pfe_platform_data; ++ ++static int pfe_get_gemac_if_properties(struct device_node *gem, ++ int port, ++ struct ls1012a_pfe_platform_data *pdata) ++{ ++ struct device_node *phy_node = NULL; ++ int size; ++ int phy_id = 0; ++ const u32 *addr; ++ int err; ++ ++ addr = of_get_property(gem, "reg", &size); ++ if (addr) ++ port = be32_to_cpup(addr); ++ else ++ goto err; ++ ++ pdata->ls1012a_eth_pdata[port].gem_id = port; ++ ++ of_get_mac_address(gem, pdata->ls1012a_eth_pdata[port].mac_addr); ++ ++ phy_node = of_parse_phandle(gem, "phy-handle", 0); ++ pdata->ls1012a_eth_pdata[port].phy_node = phy_node; ++ if (phy_node) { ++ pfe_use_old_dts_phy = false; ++ goto process_phynode; ++ } else if (of_phy_is_fixed_link(gem)) { ++ pfe_use_old_dts_phy = false; ++ if (of_phy_register_fixed_link(gem) < 0) { ++ pr_err("broken fixed-link specification\n"); ++ goto err; ++ } ++ phy_node = of_node_get(gem); ++ pdata->ls1012a_eth_pdata[port].phy_node = phy_node; ++ } else if (of_get_property(gem, "fsl,pfe-phy-if-flags", &size)) { ++ pfe_use_old_dts_phy = true; ++ /* Use old dts properties for phy handling */ ++ addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size); ++ pdata->ls1012a_eth_pdata[port].phy_flags = be32_to_cpup(addr); ++ ++ addr = of_get_property(gem, "fsl,gemac-phy-id", &size); ++ if (!addr) { ++ pr_err("%s:%d Invalid gemac-phy-id....\n", __func__, ++ __LINE__); ++ } else { ++ phy_id = be32_to_cpup(addr); ++ pdata->ls1012a_eth_pdata[port].phy_id = phy_id; ++ pdata->ls1012a_mdio_pdata[0].phy_mask &= ~(1 << phy_id); ++ } ++ ++ /* If PHY is enabled, read mdio properties */ ++ if (pdata->ls1012a_eth_pdata[port].phy_flags & GEMAC_NO_PHY) ++ goto done; ++ ++ } else { ++ pr_info("%s: No PHY or fixed-link\n", __func__); ++ return 0; ++ } ++ ++process_phynode: ++ err = of_get_phy_mode(gem, &pdata->ls1012a_eth_pdata[port].mii_config); ++ if (err) ++ pr_err("%s:%d Incorrect Phy mode....\n", __func__, ++ __LINE__); ++ ++ addr = of_get_property(gem, "fsl,mdio-mux-val", &size); ++ if (!addr) { ++ pr_err("%s: Invalid mdio-mux-val....\n", __func__); ++ } else { ++ phy_id = be32_to_cpup(addr); ++ pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id; ++ } ++ ++ if (pdata->ls1012a_eth_pdata[port].phy_id < 32) ++ pfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] = ++ pdata->ls1012a_eth_pdata[port].mdio_muxval; ++ ++ ++ pdata->ls1012a_mdio_pdata[port].irq[0] = PHY_POLL; ++ ++done: ++ return 0; ++ ++err: ++ return -1; ++} ++ ++/* ++ * ++ * pfe_platform_probe - ++ * ++ * ++ */ ++static int pfe_platform_probe(struct platform_device *pdev) ++{ ++ struct resource res; ++ int ii = 0, rc, interface_count = 0, size = 0; ++ const u32 *prop; ++ struct device_node *np, *gem = NULL; ++ struct clk *pfe_clk; ++ ++ np = pdev->dev.of_node; ++ ++ if (!np) { ++ pr_err("Invalid device node\n"); ++ return -EINVAL; ++ } ++ ++ pfe = kzalloc(sizeof(*pfe), GFP_KERNEL); ++ if (!pfe) { ++ rc = -ENOMEM; ++ goto err_alloc; ++ } ++ ++ platform_set_drvdata(pdev, pfe); ++ ++ if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { ++ rc = -ENOMEM; ++ pr_err("unable to configure DMA mask.\n"); ++ goto err_ddr; ++ } ++ ++ if (of_address_to_resource(np, 1, &res)) { ++ rc = -ENOMEM; ++ pr_err("failed to get ddr resource\n"); ++ goto err_ddr; ++ } ++ ++ pfe->ddr_phys_baseaddr = res.start; ++ pfe->ddr_size = resource_size(&res); ++ ++ pfe->ddr_baseaddr = memremap(res.start, resource_size(&res), ++ MEMREMAP_WB); ++ if (!pfe->ddr_baseaddr) { ++ pr_err("memremap() ddr failed\n"); ++ rc = -ENOMEM; ++ goto err_ddr; ++ } ++ ++ pfe->scfg = ++ syscon_regmap_lookup_by_phandle(pdev->dev.of_node, ++ "fsl,pfe-scfg"); ++ if (IS_ERR(pfe->scfg)) { ++ dev_err(&pdev->dev, "No syscfg phandle specified\n"); ++ return PTR_ERR(pfe->scfg); ++ } ++ ++ pfe->cbus_baseaddr = of_iomap(np, 0); ++ if (!pfe->cbus_baseaddr) { ++ rc = -ENOMEM; ++ pr_err("failed to get axi resource\n"); ++ goto err_axi; ++ } ++ ++ pfe->hif_irq = platform_get_irq(pdev, 0); ++ if (pfe->hif_irq < 0) { ++ pr_err("platform_get_irq for hif failed\n"); ++ rc = pfe->hif_irq; ++ goto err_hif_irq; ++ } ++ ++ pfe->wol_irq = platform_get_irq(pdev, 2); ++ if (pfe->wol_irq < 0) { ++ pr_err("platform_get_irq for WoL failed\n"); ++ rc = pfe->wol_irq; ++ goto err_hif_irq; ++ } ++ ++ /* Read interface count */ ++ prop = of_get_property(np, "fsl,pfe-num-interfaces", &size); ++ if (!prop) { ++ pr_err("Failed to read number of interfaces\n"); ++ rc = -ENXIO; ++ goto err_prop; ++ } ++ ++ interface_count = be32_to_cpup(prop); ++ if (interface_count <= 0) { ++ pr_err("No ethernet interface count : %d\n", ++ interface_count); ++ rc = -ENXIO; ++ goto err_prop; ++ } ++ ++ pfe_platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff; ++ ++ while ((gem = of_get_next_child(np, gem))) { ++ if (of_find_property(gem, "reg", &size)) { ++ pfe_get_gemac_if_properties(gem, ii, ++ &pfe_platform_data); ++ ii++; ++ } ++ } ++ ++ if (interface_count != ii) ++ pr_info("missing some of gemac interface properties.\n"); ++ ++ pfe->dev = &pdev->dev; ++ ++ pfe->dev->platform_data = &pfe_platform_data; ++ ++ /* declare WoL capabilities */ ++ device_init_wakeup(&pdev->dev, true); ++ ++ /* find the clocks */ ++ pfe_clk = devm_clk_get(pfe->dev, "pfe"); ++ if (IS_ERR(pfe_clk)) ++ return PTR_ERR(pfe_clk); ++ ++ /* PFE clock is (platform clock / 2) */ ++ /* save sys_clk value as KHz */ ++ pfe->ctrl.sys_clk = clk_get_rate(pfe_clk) / (2 * 1000); ++ ++ rc = pfe_probe(pfe); ++ if (rc < 0) ++ goto err_probe; ++ ++ return 0; ++ ++err_probe: ++err_prop: ++err_hif_irq: ++ iounmap(pfe->cbus_baseaddr); ++ ++err_axi: ++ memunmap(pfe->ddr_baseaddr); ++ ++err_ddr: ++ platform_set_drvdata(pdev, NULL); ++ ++ kfree(pfe); ++ ++err_alloc: ++ return rc; ++} ++ ++/* ++ * pfe_platform_remove - ++ */ ++static int pfe_platform_remove(struct platform_device *pdev) ++{ ++ struct pfe *pfe = platform_get_drvdata(pdev); ++ int rc; ++ ++ pr_info("%s\n", __func__); ++ ++ rc = pfe_remove(pfe); ++ ++ iounmap(pfe->cbus_baseaddr); ++ ++ memunmap(pfe->ddr_baseaddr); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ kfree(pfe); ++ ++ return rc; ++} ++ ++#ifdef CONFIG_PM ++#ifdef CONFIG_PM_SLEEP ++int pfe_platform_suspend(struct device *dev) ++{ ++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); ++ struct net_device *netdev; ++ int i; ++ ++ pfe->wake = 0; ++ ++ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) { ++ netdev = pfe->eth.eth_priv[i]->ndev; ++ ++ netif_device_detach(netdev); ++ ++ if (netif_running(netdev)) ++ if (pfe_eth_suspend(netdev)) ++ pfe->wake = 1; ++ } ++ ++ /* Shutdown PFE only if we're not waking up the system */ ++ if (!pfe->wake) { ++#if defined(LS1012A_PFE_RESET_WA) ++ pfe_hif_rx_idle(&pfe->hif); ++#endif ++ pfe_ctrl_suspend(&pfe->ctrl); ++ pfe_firmware_exit(pfe); ++ ++ pfe_hif_exit(pfe); ++ pfe_hif_lib_exit(pfe); ++ ++ pfe_hw_exit(pfe); ++ } ++ ++ return 0; ++} ++ ++static int pfe_platform_resume(struct device *dev) ++{ ++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); ++ struct net_device *netdev; ++ int i; ++ ++ if (!pfe->wake) { ++ pfe_hw_init(pfe, 1); ++ pfe_hif_lib_init(pfe); ++ pfe_hif_init(pfe); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ util_enable(); ++#endif ++ tmu_enable(0xf); ++ class_enable(); ++ pfe_ctrl_resume(&pfe->ctrl); ++ } ++ ++ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) { ++ netdev = pfe->eth.eth_priv[i]->ndev; ++ ++ if (pfe->mdio.mdio_priv[i]->mii_bus) ++ pfe_eth_mdio_reset(pfe->mdio.mdio_priv[i]->mii_bus); ++ ++ if (netif_running(netdev)) ++ pfe_eth_resume(netdev); ++ ++ netif_device_attach(netdev); ++ } ++ return 0; ++} ++#else ++#define pfe_platform_suspend NULL ++#define pfe_platform_resume NULL ++#endif ++ ++static const struct dev_pm_ops pfe_platform_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume) ++}; ++#endif ++ ++static const struct of_device_id pfe_match[] = { ++ { ++ .compatible = "fsl,pfe", ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, pfe_match); ++ ++static struct platform_driver pfe_platform_driver = { ++ .probe = pfe_platform_probe, ++ .remove = pfe_platform_remove, ++ .driver = { ++ .name = "pfe", ++ .of_match_table = pfe_match, ++#ifdef CONFIG_PM ++ .pm = &pfe_platform_pm_ops, ++#endif ++ }, ++}; ++ ++module_platform_driver(pfe_platform_driver); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("PFE Ethernet driver"); ++MODULE_AUTHOR("NXP DNCPE"); +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_mod.c +@@ -0,0 +1,158 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include "pfe_mod.h" ++#include "pfe_cdev.h" ++ ++unsigned int us; ++module_param(us, uint, 0444); ++MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n" ++ "1: module enabled for userspace networking\n"); ++struct pfe *pfe; ++ ++/* ++ * pfe_probe - ++ */ ++int pfe_probe(struct pfe *pfe) ++{ ++ int rc; ++ ++ if (pfe->ddr_size < DDR_MAX_SIZE) { ++ pr_err("%s: required DDR memory (%x) above platform ddr memory (%x)\n", ++ __func__, (unsigned int)DDR_MAX_SIZE, pfe->ddr_size); ++ rc = -ENOMEM; ++ goto err_hw; ++ } ++ ++ if (((int)(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) & ++ (8 * SZ_1M - 1)) != 0) { ++ pr_err("%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n", ++ __func__, (int)pfe->ddr_phys_baseaddr + ++ BMU2_DDR_BASEADDR); ++ rc = -ENOMEM; ++ goto err_hw; ++ } ++ ++ pr_info("cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n", ++ (unsigned long)pfe->cbus_baseaddr, ++ (unsigned long)pfe->ddr_baseaddr, ++ pfe->ddr_phys_baseaddr, pfe->ddr_size); ++ ++ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, ++ pfe->ddr_phys_baseaddr, pfe->ddr_size); ++ ++ rc = pfe_hw_init(pfe, 0); ++ if (rc < 0) ++ goto err_hw; ++ ++ if (us) ++ goto firmware_init; ++ ++ rc = pfe_hif_lib_init(pfe); ++ if (rc < 0) ++ goto err_hif_lib; ++ ++ rc = pfe_hif_init(pfe); ++ if (rc < 0) ++ goto err_hif; ++ ++firmware_init: ++ rc = pfe_firmware_init(pfe); ++ if (rc < 0) ++ goto err_firmware; ++ ++ rc = pfe_ctrl_init(pfe); ++ if (rc < 0) ++ goto err_ctrl; ++ ++ rc = pfe_eth_init(pfe); ++ if (rc < 0) ++ goto err_eth; ++ ++ rc = pfe_sysfs_init(pfe); ++ if (rc < 0) ++ goto err_sysfs; ++ ++ rc = pfe_debugfs_init(pfe); ++ if (rc < 0) ++ goto err_debugfs; ++ ++ if (us) { ++ /* Creating a character device */ ++ rc = pfe_cdev_init(); ++ if (rc < 0) ++ goto err_cdev; ++ } ++ ++ return 0; ++ ++err_cdev: ++ pfe_debugfs_exit(pfe); ++ ++err_debugfs: ++ pfe_sysfs_exit(pfe); ++ ++err_sysfs: ++ pfe_eth_exit(pfe); ++ ++err_eth: ++ pfe_ctrl_exit(pfe); ++ ++err_ctrl: ++ pfe_firmware_exit(pfe); ++ ++err_firmware: ++ if (us) ++ goto err_hif_lib; ++ ++ pfe_hif_exit(pfe); ++ ++err_hif: ++ pfe_hif_lib_exit(pfe); ++ ++err_hif_lib: ++ pfe_hw_exit(pfe); ++ ++err_hw: ++ return rc; ++} ++ ++/* ++ * pfe_remove - ++ */ ++int pfe_remove(struct pfe *pfe) ++{ ++ pr_info("%s\n", __func__); ++ ++ if (us) ++ pfe_cdev_exit(); ++ ++ pfe_debugfs_exit(pfe); ++ ++ pfe_sysfs_exit(pfe); ++ ++ pfe_eth_exit(pfe); ++ ++ pfe_ctrl_exit(pfe); ++ ++#if defined(LS1012A_PFE_RESET_WA) ++ pfe_hif_rx_idle(&pfe->hif); ++#endif ++ pfe_firmware_exit(pfe); ++ ++ if (us) ++ goto hw_exit; ++ ++ pfe_hif_exit(pfe); ++ ++ pfe_hif_lib_exit(pfe); ++ ++hw_exit: ++ pfe_hw_exit(pfe); ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_mod.h +@@ -0,0 +1,103 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_MOD_H_ ++#define _PFE_MOD_H_ ++ ++#include ++#include ++ ++extern unsigned int us; ++ ++struct pfe; ++ ++#include "pfe_hw.h" ++#include "pfe_firmware.h" ++#include "pfe_ctrl.h" ++#include "pfe_hif.h" ++#include "pfe_hif_lib.h" ++#include "pfe_eth.h" ++#include "pfe_sysfs.h" ++#include "pfe_perfmon.h" ++#include "pfe_debugfs.h" ++ ++#define PHYID_MAX_VAL 32 ++ ++struct pfe_tmu_credit { ++ /* Number of allowed TX packet in-flight, matches TMU queue size */ ++ unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; ++ unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; ++ unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; ++}; ++ ++struct pfe { ++ struct regmap *scfg; ++ unsigned long ddr_phys_baseaddr; ++ void *ddr_baseaddr; ++ unsigned int ddr_size; ++ void *cbus_baseaddr; ++ void *apb_baseaddr; ++ unsigned long iram_phys_baseaddr; ++ void *iram_baseaddr; ++ unsigned long ipsec_phys_baseaddr; ++ void *ipsec_baseaddr; ++ int hif_irq; ++ int wol_irq; ++ int hif_client_irq; ++ struct device *dev; ++ struct dentry *dentry; ++ struct pfe_ctrl ctrl; ++ struct pfe_hif hif; ++ struct pfe_eth eth; ++ struct pfe_mdio mdio; ++ struct hif_client_s *hif_client[HIF_CLIENTS_MAX]; ++#if defined(CFG_DIAGS) ++ struct pfe_diags diags; ++#endif ++ struct pfe_tmu_credit tmu_credit; ++ struct pfe_cpumon cpumon; ++ struct pfe_memmon memmon; ++ int wake; ++ int mdio_muxval[PHYID_MAX_VAL]; ++ struct clk *hfe_clock; ++}; ++ ++extern struct pfe *pfe; ++ ++int pfe_probe(struct pfe *pfe); ++int pfe_remove(struct pfe *pfe); ++ ++/* DDR Mapping in reserved memory*/ ++#define ROUTE_TABLE_BASEADDR 0 ++#define ROUTE_TABLE_HASH_BITS 15 /* 32K entries */ ++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) \ ++ * CLASS_ROUTE_SIZE) ++#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE) ++#define BMU2_BUF_COUNT (4096 - 256) ++/* This is to get a total DDR size of 12MiB */ ++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT) ++#define UTIL_CODE_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE) ++#define UTIL_CODE_SIZE (128 * SZ_1K) ++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE) ++#define UTIL_DDR_DATA_SIZE (64 * SZ_1K) ++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE) ++#define CLASS_DDR_DATA_SIZE (32 * SZ_1K) ++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE) ++#define TMU_DDR_DATA_SIZE (32 * SZ_1K) ++#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE) ++#define TMU_LLM_QUEUE_LEN (8 * 512) ++/* Must be power of two and at least 16 * 8 = 128 bytes */ ++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) ++/* (4 TMU's x 16 queues x queue_len) */ ++ ++#define DDR_MAX_SIZE (TMU_LLM_BASEADDR + TMU_LLM_SIZE) ++ ++/* LMEM Mapping */ ++#define BMU1_LMEM_BASEADDR 0 ++#define BMU1_BUF_COUNT 256 ++#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT) ++ ++#endif /* _PFE_MOD_H */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_PERFMON_H_ ++#define _PFE_PERFMON_H_ ++ ++#include "pfe/pfe.h" ++ ++#define CT_CPUMON_INTERVAL (1 * TIMER_TICKS_PER_SEC) ++ ++struct pfe_cpumon { ++ u32 cpu_usage_pct[MAX_PE]; ++ u32 class_usage_pct; ++}; ++ ++struct pfe_memmon { ++ u32 kernel_memory_allocated; ++}; ++ ++int pfe_perfmon_init(struct pfe *pfe); ++void pfe_perfmon_exit(struct pfe *pfe); ++ ++#endif /* _PFE_PERFMON_H_ */ +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c +@@ -0,0 +1,840 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#include ++#include ++ ++#include "pfe_mod.h" ++ ++#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8 ++#define NUM_QUEUES 16 ++ ++static char register_name[20][5] = { ++ "EPC", "ECAS", "EID", "ED", ++ "r0", "r1", "r2", "r3", ++ "r4", "r5", "r6", "r7", ++ "r8", "r9", "r10", "r11", ++ "r12", "r13", "r14", "r15", ++}; ++ ++static char exception_name[14][20] = { ++ "Reset", ++ "HardwareFailure", ++ "NMI", ++ "InstBreakpoint", ++ "DataBreakpoint", ++ "Unsupported", ++ "PrivilegeViolation", ++ "InstBusError", ++ "DataBusError", ++ "AlignmentError", ++ "ArithmeticError", ++ "SystemCall", ++ "MemoryManagement", ++ "Interrupt", ++}; ++ ++static unsigned long class_do_clear; ++static unsigned long tmu_do_clear; ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static unsigned long util_do_clear; ++#endif ++ ++static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long ++ do_clear) ++{ ++ ssize_t len = 0; ++ u32 val; ++ char statebuf[5]; ++ struct pfe_cpumon *cpumon = &pfe->cpumon; ++ u32 debug_indicator; ++ u32 debug[20]; ++ ++ if (id < CLASS0_ID || id >= MAX_PE) ++ return len; ++ ++ *(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4); ++ dmem_addr += 4; ++ ++ statebuf[4] = '\0'; ++ len += sprintf(buf + len, "state=%4s ", statebuf); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ dmem_addr += 4; ++ len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val)); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ if (do_clear && val) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ dmem_addr += 4; ++ len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val)); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ if (do_clear && val) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ dmem_addr += 4; ++ if (id >= TMU0_ID && id <= TMU_MAX_ID) ++ len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val)); ++ else ++ len += sprintf(buf + len, "tx=%u", cpu_to_be32(val)); ++ ++ val = pe_dmem_read(id, dmem_addr, 4); ++ if (do_clear && val) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ dmem_addr += 4; ++ if (val) ++ len += sprintf(buf + len, " drop=%u", cpu_to_be32(val)); ++ ++ len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]); ++ ++ len += sprintf(buf + len, "\n"); ++ ++ debug_indicator = pe_dmem_read(id, dmem_addr, 4); ++ dmem_addr += 4; ++ if (!strncmp((char *)&debug_indicator, "DBUG", 4)) { ++ int j, last = 0; ++ ++ for (j = 0; j < 16; j++) { ++ debug[j] = pe_dmem_read(id, dmem_addr, 4); ++ if (debug[j]) { ++ if (do_clear) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ last = j + 1; ++ } ++ dmem_addr += 4; ++ } ++ for (j = 0; j < last; j++) { ++ len += sprintf(buf + len, "%08x%s", ++ cpu_to_be32(debug[j]), ++ (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " "); ++ } ++ } ++ ++ if (!strncmp(statebuf, "DEAD", 4)) { ++ u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS; ++ ++ len += sprintf(buf + len, "Exception details:\n"); ++ for (i = 0; i < 20; i++) { ++ debug[i] = pe_dmem_read(id, dump, 4); ++ dump += 4; ++ if (i == 2) ++ len += sprintf(buf + len, "%4s = %08x (=%s) ", ++ register_name[i], cpu_to_be32(debug[i]), ++ exception_name[min((u32) ++ cpu_to_be32(debug[i]), (u32)13)]); ++ else ++ len += sprintf(buf + len, "%4s = %08x%s", ++ register_name[i], cpu_to_be32(debug[i]), ++ (i & 0x3) == 0x3 || i == 19 ? "\n" : " "); ++ } ++ } ++ ++ return len; ++} ++ ++static ssize_t class_phy_stats(char *buf, int phy) ++{ ++ ssize_t len = 0; ++ int off1 = phy * 0x28; ++ int off2 = phy * 0x10; ++ ++ if (phy == 3) ++ off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS; ++ ++ len += sprintf(buf + len, "phy: %d\n", phy); ++ len += sprintf(buf + len, ++ " rx: %10u, tx: %10u, intf: %10u, ipv4: %10u, ipv6: %10u\n", ++ readl(CLASS_PHY1_RX_PKTS + off1), ++ readl(CLASS_PHY1_TX_PKTS + off1), ++ readl(CLASS_PHY1_INTF_MATCH_PKTS + off1), ++ readl(CLASS_PHY1_V4_PKTS + off1), ++ readl(CLASS_PHY1_V6_PKTS + off1)); ++ ++ len += sprintf(buf + len, ++ " icmp: %10u, igmp: %10u, tcp: %10u, udp: %10u\n", ++ readl(CLASS_PHY1_ICMP_PKTS + off2), ++ readl(CLASS_PHY1_IGMP_PKTS + off2), ++ readl(CLASS_PHY1_TCP_PKTS + off2), ++ readl(CLASS_PHY1_UDP_PKTS + off2)); ++ ++ len += sprintf(buf + len, " err\n"); ++ len += sprintf(buf + len, ++ " lp: %10u, intf: %10u, l3: %10u, chcksum: %10u, ttl: %10u\n", ++ readl(CLASS_PHY1_LP_FAIL_PKTS + off1), ++ readl(CLASS_PHY1_INTF_FAIL_PKTS + off1), ++ readl(CLASS_PHY1_L3_FAIL_PKTS + off1), ++ readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1), ++ readl(CLASS_PHY1_TTL_ERR_PKTS + off1)); ++ ++ return len; ++} ++ ++/* qm_read_drop_stat ++ * This function is used to read the drop statistics from the TMU ++ * hw drop counter. Since the hw counter is always cleared afer ++ * reading, this function maintains the previous drop count, and ++ * adds the new value to it. That value can be retrieved by ++ * passing a pointer to it with the total_drops arg. ++ * ++ * @param tmu TMU number (0 - 3) ++ * @param queue queue number (0 - 15) ++ * @param total_drops pointer to location to store total drops (or NULL) ++ * @param do_reset if TRUE, clear total drops after updating ++ */ ++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset) ++{ ++ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES]; ++ u32 val; ++ ++ writel((tmu << 8) | queue, TMU_TEQ_CTRL); ++ writel((tmu << 8) | queue, TMU_LLM_CTRL); ++ val = readl(TMU_TEQ_DROP_STAT); ++ qtotal[tmu][queue] += val; ++ if (total_drops) ++ *total_drops = qtotal[tmu][queue]; ++ if (do_reset) ++ qtotal[tmu][queue] = 0; ++ return val; ++} ++ ++static ssize_t tmu_queue_stats(char *buf, int tmu, int queue) ++{ ++ ssize_t len = 0; ++ u32 drops; ++ ++ len += sprintf(buf + len, "%d-%02d, ", tmu, queue); ++ ++ drops = qm_read_drop_stat(tmu, queue, NULL, 0); ++ ++ /* Select queue */ ++ writel((tmu << 8) | queue, TMU_TEQ_CTRL); ++ writel((tmu << 8) | queue, TMU_LLM_CTRL); ++ ++ len += sprintf(buf + len, ++ "(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n", ++ drops, readl(TMU_TEQ_TRANS_STAT), ++ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR), ++ readl(TMU_LLM_QUE_DROPCNT)); ++ ++ return len; ++} ++ ++static ssize_t tmu_queues(char *buf, int tmu) ++{ ++ ssize_t len = 0; ++ int queue; ++ ++ for (queue = 0; queue < 16; queue++) ++ len += tmu_queue_stats(buf + len, tmu, queue); ++ ++ return len; ++} ++ ++static ssize_t block_version(char *buf, void *addr) ++{ ++ ssize_t len = 0; ++ u32 val; ++ ++ val = readl(addr); ++ len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n", ++ (val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff); ++ ++ return len; ++} ++ ++static ssize_t bmu(char *buf, int id, void *base) ++{ ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "%s: %d\n ", __func__, id); ++ ++ len += block_version(buf + len, base + BMU_VERSION); ++ ++ len += sprintf(buf + len, " buf size: %x\n", (1 << readl(base + ++ BMU_BUF_SIZE))); ++ len += sprintf(buf + len, " buf count: %x\n", readl(base + ++ BMU_BUF_CNT)); ++ len += sprintf(buf + len, " buf rem: %x\n", readl(base + ++ BMU_REM_BUF_CNT)); ++ len += sprintf(buf + len, " buf curr: %x\n", readl(base + ++ BMU_CURR_BUF_CNT)); ++ len += sprintf(buf + len, " free err: %x\n", readl(base + ++ BMU_FREE_ERR_ADDR)); ++ ++ return len; ++} ++ ++static ssize_t gpi(char *buf, int id, void *base) ++{ ++ ssize_t len = 0; ++ u32 val; ++ ++ len += sprintf(buf + len, "%s%d:\n ", __func__, id); ++ len += block_version(buf + len, base + GPI_VERSION); ++ ++ len += sprintf(buf + len, " tx under stick: %x\n", readl(base + ++ GPI_FIFO_STATUS)); ++ val = readl(base + GPI_FIFO_DEBUG); ++ len += sprintf(buf + len, " tx pkts: %x\n", (val >> 23) & ++ 0x3f); ++ len += sprintf(buf + len, " rx pkts: %x\n", (val >> 18) & ++ 0x3f); ++ len += sprintf(buf + len, " tx bytes: %x\n", (val >> 9) & ++ 0x1ff); ++ len += sprintf(buf + len, " rx bytes: %x\n", (val >> 0) & ++ 0x1ff); ++ len += sprintf(buf + len, " overrun: %x\n", readl(base + ++ GPI_OVERRUN_DROPCNT)); ++ ++ return len; ++} ++ ++static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ class_do_clear = kstrtoul(buf, 0, 0); ++ return count; ++} ++ ++static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ int id; ++ u32 val; ++ struct pfe_cpumon *cpumon = &pfe->cpumon; ++ ++ len += block_version(buf + len, CLASS_VERSION); ++ ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ len += sprintf(buf + len, "%d: ", id - CLASS0_ID); ++ ++ val = readl(CLASS_PE0_DEBUG + id * 4); ++ len += sprintf(buf + len, "pc=1%04x ", val & 0xffff); ++ ++ len += display_pe_status(buf + len, id, CLASS_DM_PESTATUS, ++ class_do_clear); ++ } ++ len += sprintf(buf + len, "aggregate load=%d%%\n\n", ++ cpumon->class_usage_pct); ++ ++ len += sprintf(buf + len, "pe status: 0x%x\n", ++ readl(CLASS_PE_STATUS)); ++ len += sprintf(buf + len, "max buf cnt: 0x%x afull thres: 0x%x\n", ++ readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES)); ++ len += sprintf(buf + len, "tsq max cnt: 0x%x tsq fifo thres: 0x%x\n", ++ readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES)); ++ len += sprintf(buf + len, "state: 0x%x\n", readl(CLASS_STATE)); ++ ++ len += class_phy_stats(buf + len, 0); ++ len += class_phy_stats(buf + len, 1); ++ len += class_phy_stats(buf + len, 2); ++ len += class_phy_stats(buf + len, 3); ++ ++ return len; ++} ++ ++static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ tmu_do_clear = kstrtoul(buf, 0, 0); ++ return count; ++} ++ ++static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ int id; ++ u32 val; ++ ++ len += block_version(buf + len, TMU_VERSION); ++ ++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { ++ if (id == TMU2_ID) ++ continue; ++ len += sprintf(buf + len, "%d: ", id - TMU0_ID); ++ ++ len += display_pe_status(buf + len, id, TMU_DM_PESTATUS, ++ tmu_do_clear); ++ } ++ ++ len += sprintf(buf + len, "pe status: %x\n", readl(TMU_PE_STATUS)); ++ len += sprintf(buf + len, "inq fifo cnt: %x\n", ++ readl(TMU_PHY_INQ_FIFO_CNT)); ++ val = readl(TMU_INQ_STAT); ++ len += sprintf(buf + len, "inq wr ptr: %x\n", val & 0x3ff); ++ len += sprintf(buf + len, "inq rd ptr: %x\n", val >> 10); ++ ++ return len; ++} ++ ++static unsigned long drops_do_clear; ++static u32 class_drop_counter[CLASS_NUM_DROP_COUNTERS]; ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static u32 util_drop_counter[UTIL_NUM_DROP_COUNTERS]; ++#endif ++ ++char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = { ++ "ICC", ++ "Host Pkt Error", ++ "Rx Error", ++ "IPsec Outbound", ++ "IPsec Inbound", ++ "EXPT IPsec Error", ++ "Reassembly", ++ "Fragmenter", ++ "NAT-T", ++ "Socket", ++ "Multicast", ++ "NAT-PT", ++ "Tx Disabled", ++}; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = { ++ "IPsec Outbound", ++ "IPsec Inbound", ++ "IPsec Rate Limiter", ++ "Fragmenter", ++ "Socket", ++ "Tx Disabled", ++ "Rx Error", ++}; ++#endif ++ ++static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ drops_do_clear = kstrtoul(buf, 0, 0); ++ return count; ++} ++ ++static u32 tmu_drops[4][16]; ++static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ int id, dropnum; ++ int tmu, queue; ++ u32 val; ++ u32 dmem_addr; ++ int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0; ++ struct pfe_ctrl *ctrl = &pfe->ctrl; ++ ++ memset(class_drop_counter, 0, sizeof(class_drop_counter)); ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ if (drops_do_clear) ++ pe_sync_stop(ctrl, (1 << id)); ++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; ++ dropnum++) { ++ dmem_addr = CLASS_DM_DROP_CNTR; ++ val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4)); ++ class_drop_counter[dropnum] += val; ++ num_class_drops += val; ++ if (drops_do_clear) ++ pe_dmem_write(id, 0, dmem_addr, 4); ++ } ++ if (drops_do_clear) ++ pe_start(ctrl, (1 << id)); ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (drops_do_clear) ++ pe_sync_stop(ctrl, (1 << UTIL_ID)); ++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) { ++ dmem_addr = UTIL_DM_DROP_CNTR; ++ val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4)); ++ util_drop_counter[dropnum] = val; ++ num_util_drops += val; ++ if (drops_do_clear) ++ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4); ++ } ++ if (drops_do_clear) ++ pe_start(ctrl, (1 << UTIL_ID)); ++#endif ++ for (tmu = 0; tmu < 4; tmu++) { ++ for (queue = 0; queue < 16; queue++) { ++ qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue], ++ drops_do_clear); ++ num_tmu_drops += tmu_drops[tmu][queue]; ++ } ++ } ++ ++ if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0) ++ len += sprintf(buf + len, "No PE drops\n\n"); ++ ++ if (num_class_drops > 0) { ++ len += sprintf(buf + len, "Class PE drops --\n"); ++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; ++ dropnum++) { ++ if (class_drop_counter[dropnum] > 0) ++ len += sprintf(buf + len, " %s: %d\n", ++ class_drop_description[dropnum], ++ class_drop_counter[dropnum]); ++ } ++ len += sprintf(buf + len, "\n"); ++ } ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (num_util_drops > 0) { ++ len += sprintf(buf + len, "Util PE drops --\n"); ++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) { ++ if (util_drop_counter[dropnum] > 0) ++ len += sprintf(buf + len, " %s: %d\n", ++ util_drop_description[dropnum], ++ util_drop_counter[dropnum]); ++ } ++ len += sprintf(buf + len, "\n"); ++ } ++#endif ++ if (num_tmu_drops > 0) { ++ len += sprintf(buf + len, "TMU drops --\n"); ++ for (tmu = 0; tmu < 4; tmu++) { ++ for (queue = 0; queue < 16; queue++) { ++ if (tmu_drops[tmu][queue] > 0) ++ len += sprintf(buf + len, ++ " TMU%d-Q%d: %d\n" ++ , tmu, queue, tmu_drops[tmu][queue]); ++ } ++ } ++ len += sprintf(buf + len, "\n"); ++ } ++ ++ return len; ++} ++ ++static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 0); ++} ++ ++static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 1); ++} ++ ++static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 2); ++} ++ ++static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ return tmu_queues(buf, 3); ++} ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ util_do_clear = kstrtoul(buf, NULL, 0); ++ return count; ++} ++ ++static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ struct pfe_ctrl *ctrl = &pfe->ctrl; ++ ++ len += block_version(buf + len, UTIL_VERSION); ++ ++ pe_sync_stop(ctrl, (1 << UTIL_ID)); ++ len += display_pe_status(buf + len, UTIL_ID, UTIL_DM_PESTATUS, ++ util_do_clear); ++ pe_start(ctrl, (1 << UTIL_ID)); ++ ++ len += sprintf(buf + len, "pe status: %x\n", readl(UTIL_PE_STATUS)); ++ len += sprintf(buf + len, "max buf cnt: %x\n", ++ readl(UTIL_MAX_BUF_CNT)); ++ len += sprintf(buf + len, "tsq max cnt: %x\n", ++ readl(UTIL_TSQ_MAX_CNT)); ++ ++ return len; ++} ++#endif ++ ++static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ ++ len += bmu(buf + len, 1, BMU1_BASE_ADDR); ++ len += bmu(buf + len, 2, BMU2_BASE_ADDR); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "hif:\n "); ++ len += block_version(buf + len, HIF_VERSION); ++ ++ len += sprintf(buf + len, " tx curr bd: %x\n", ++ readl(HIF_TX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " tx status: %x\n", ++ readl(HIF_TX_STATUS)); ++ len += sprintf(buf + len, " tx dma status: %x\n", ++ readl(HIF_TX_DMA_STATUS)); ++ ++ len += sprintf(buf + len, " rx curr bd: %x\n", ++ readl(HIF_RX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " rx status: %x\n", ++ readl(HIF_RX_STATUS)); ++ len += sprintf(buf + len, " rx dma status: %x\n", ++ readl(HIF_RX_DMA_STATUS)); ++ ++ len += sprintf(buf + len, "hif nocopy:\n "); ++ len += block_version(buf + len, HIF_NOCPY_VERSION); ++ ++ len += sprintf(buf + len, " tx curr bd: %x\n", ++ readl(HIF_NOCPY_TX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " tx status: %x\n", ++ readl(HIF_NOCPY_TX_STATUS)); ++ len += sprintf(buf + len, " tx dma status: %x\n", ++ readl(HIF_NOCPY_TX_DMA_STATUS)); ++ ++ len += sprintf(buf + len, " rx curr bd: %x\n", ++ readl(HIF_NOCPY_RX_CURR_BD_ADDR)); ++ len += sprintf(buf + len, " rx status: %x\n", ++ readl(HIF_NOCPY_RX_STATUS)); ++ len += sprintf(buf + len, " rx dma status: %x\n", ++ readl(HIF_NOCPY_RX_DMA_STATUS)); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ ssize_t len = 0; ++ ++ len += gpi(buf + len, 0, EGPI1_BASE_ADDR); ++ len += gpi(buf + len, 1, EGPI2_BASE_ADDR); ++ len += gpi(buf + len, 3, HGPI_BASE_ADDR); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute ++ *attr, char *buf) ++{ ++ ssize_t len = 0; ++ struct pfe_memmon *memmon = &pfe->memmon; ++ ++ len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n", ++ memmon->kernel_memory_allocated, ++ (memmon->kernel_memory_allocated + 1023) / 1024); ++ ++ return len; ++} ++ ++static ssize_t pfe_show_crc_revalidated(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ u64 crc_validated = 0; ++ ssize_t len = 0; ++ int id, phyid; ++ ++ len += sprintf(buf + len, "FCS re-validated by PFE:\n"); ++ ++ for (phyid = 0; phyid < 2; phyid++) { ++ crc_validated = 0; ++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { ++ crc_validated += be32_to_cpu(pe_dmem_read(id, ++ CLASS_DM_CRC_VALIDATED + (phyid * 4), 4)); ++ } ++ len += sprintf(buf + len, "MAC %d:\n count:%10llu\n", ++ phyid, crc_validated); ++ } ++ ++ return len; ++} ++ ++#ifdef HIF_NAPI_STATS ++static ssize_t pfe_show_hif_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct pfe *pfe = platform_get_drvdata(pdev); ++ ssize_t len = 0; ++ ++ len += sprintf(buf + len, "sched: %u\n", ++ pfe->hif.napi_counters[NAPI_SCHED_COUNT]); ++ len += sprintf(buf + len, "poll: %u\n", ++ pfe->hif.napi_counters[NAPI_POLL_COUNT]); ++ len += sprintf(buf + len, "packet: %u\n", ++ pfe->hif.napi_counters[NAPI_PACKET_COUNT]); ++ len += sprintf(buf + len, "budget: %u\n", ++ pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]); ++ len += sprintf(buf + len, "desc: %u\n", ++ pfe->hif.napi_counters[NAPI_DESC_COUNT]); ++ len += sprintf(buf + len, "full: %u\n", ++ pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]); ++ ++ return len; ++} ++ ++static ssize_t pfe_set_hif_napi_stats(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct pfe *pfe = platform_get_drvdata(pdev); ++ ++ memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters)); ++ ++ return count; ++} ++ ++static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats, ++ pfe_set_hif_napi_stats); ++#endif ++ ++static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class); ++static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util); ++#endif ++static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL); ++static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL); ++static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL); ++static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops); ++static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL); ++static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL); ++static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL); ++static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL); ++static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL); ++static DEVICE_ATTR(fcs_revalidated, 0444, pfe_show_crc_revalidated, NULL); ++ ++int pfe_sysfs_init(struct pfe *pfe) ++{ ++ if (device_create_file(pfe->dev, &dev_attr_class)) ++ goto err_class; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu)) ++ goto err_tmu; ++ ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ if (device_create_file(pfe->dev, &dev_attr_util)) ++ goto err_util; ++#endif ++ ++ if (device_create_file(pfe->dev, &dev_attr_bmu)) ++ goto err_bmu; ++ ++ if (device_create_file(pfe->dev, &dev_attr_hif)) ++ goto err_hif; ++ ++ if (device_create_file(pfe->dev, &dev_attr_gpi)) ++ goto err_gpi; ++ ++ if (device_create_file(pfe->dev, &dev_attr_drops)) ++ goto err_drops; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu0_queues)) ++ goto err_tmu0_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu1_queues)) ++ goto err_tmu1_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu2_queues)) ++ goto err_tmu2_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_tmu3_queues)) ++ goto err_tmu3_queues; ++ ++ if (device_create_file(pfe->dev, &dev_attr_pfemem)) ++ goto err_pfemem; ++ ++ if (device_create_file(pfe->dev, &dev_attr_fcs_revalidated)) ++ goto err_crc_revalidated; ++ ++#ifdef HIF_NAPI_STATS ++ if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats)) ++ goto err_hif_napi_stats; ++#endif ++ ++ return 0; ++ ++#ifdef HIF_NAPI_STATS ++err_hif_napi_stats: ++ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated); ++#endif ++ ++err_crc_revalidated: ++ device_remove_file(pfe->dev, &dev_attr_pfemem); ++ ++err_pfemem: ++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); ++ ++err_tmu3_queues: ++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); ++ ++err_tmu2_queues: ++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); ++ ++err_tmu1_queues: ++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); ++ ++err_tmu0_queues: ++ device_remove_file(pfe->dev, &dev_attr_drops); ++ ++err_drops: ++ device_remove_file(pfe->dev, &dev_attr_gpi); ++ ++err_gpi: ++ device_remove_file(pfe->dev, &dev_attr_hif); ++ ++err_hif: ++ device_remove_file(pfe->dev, &dev_attr_bmu); ++ ++err_bmu: ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ device_remove_file(pfe->dev, &dev_attr_util); ++ ++err_util: ++#endif ++ device_remove_file(pfe->dev, &dev_attr_tmu); ++ ++err_tmu: ++ device_remove_file(pfe->dev, &dev_attr_class); ++ ++err_class: ++ return -1; ++} ++ ++void pfe_sysfs_exit(struct pfe *pfe) ++{ ++#ifdef HIF_NAPI_STATS ++ device_remove_file(pfe->dev, &dev_attr_hif_napi_stats); ++#endif ++ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated); ++ device_remove_file(pfe->dev, &dev_attr_pfemem); ++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); ++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); ++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); ++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); ++ device_remove_file(pfe->dev, &dev_attr_drops); ++ device_remove_file(pfe->dev, &dev_attr_gpi); ++ device_remove_file(pfe->dev, &dev_attr_hif); ++ device_remove_file(pfe->dev, &dev_attr_bmu); ++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) ++ device_remove_file(pfe->dev, &dev_attr_util); ++#endif ++ device_remove_file(pfe->dev, &dev_attr_tmu); ++ device_remove_file(pfe->dev, &dev_attr_class); ++} +--- /dev/null ++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright 2015-2016 Freescale Semiconductor, Inc. ++ * Copyright 2017 NXP ++ */ ++ ++#ifndef _PFE_SYSFS_H_ ++#define _PFE_SYSFS_H_ ++ ++#include ++ ++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset); ++ ++int pfe_sysfs_init(struct pfe *pfe); ++void pfe_sysfs_exit(struct pfe *pfe); ++ ++#endif /* _PFE_SYSFS_H_ */ diff --git a/target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch new file mode 100644 index 0000000000..53677c0416 --- /dev/null +++ b/target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch @@ -0,0 +1,32 @@ +From c918c472546afa83a619ae3cb1a9d7d346c6e288 Mon Sep 17 00:00:00 2001 +From: Bhaskar Upadhaya +Date: Wed, 29 Nov 2017 15:27:57 +0530 +Subject: [PATCH 154/173] phy: Add 2.5G SGMII interface mode + +Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII) +in existing phy_interface list + +Signed-off-by: Bhaskar Upadhaya +--- + include/linux/phy.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -146,6 +146,7 @@ typedef enum { + PHY_INTERFACE_MODE_USXGMII, + /* 10GBASE-KR - with Clause 73 AN */ + PHY_INTERFACE_MODE_10GKR, ++ PHY_INTERFACE_MODE_2500SGMII, + PHY_INTERFACE_MODE_MAX, + } phy_interface_t; + +@@ -221,6 +222,8 @@ static inline const char *phy_modes(phy_ + return "10gbase-kr"; + case PHY_INTERFACE_MODE_100BASEX: + return "100base-x"; ++ case PHY_INTERFACE_MODE_2500SGMII: ++ return "sgmii-2500"; + default: + return "unknown"; + } diff --git a/target/linux/ramips/Makefile b/target/linux/ramips/Makefile index d3f2d4b8fc..c9fc1aa58a 100644 --- a/target/linux/ramips/Makefile +++ b/target/linux/ramips/Makefile @@ -10,8 +10,7 @@ BOARDNAME:=MediaTek Ralink MIPS SUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883 FEATURES:=squashfs gpio -KERNEL_PATCHVER:=5.4 -KERNEL_TESTING_PATCHVER:=5.10 +KERNEL_PATCHVER:=5.10 define Target/Description Build firmware images for Ralink RT288x/RT3xxx based boards. diff --git a/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts b/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts index 2b8ad2759c..1d29bed6f0 100644 --- a/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts +++ b/target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts @@ -4,6 +4,7 @@ #include #include +#include / { compatible = "dlink,dir-510l", "ralink,mt7620a-soc"; @@ -85,7 +86,9 @@ }; partition@210000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x210000 0xde0000>; }; diff --git a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts index c63a85dd88..8ae566d448 100644 --- a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts +++ b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts @@ -4,6 +4,7 @@ #include #include +#include / { compatible = "dlink,dwr-118-a1", "ralink,mt7620a-soc"; @@ -106,7 +107,9 @@ }; partition@10000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x10000 0xfe0000>; }; diff --git a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts index 711f9f7c9a..42f5c86160 100644 --- a/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts +++ b/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts @@ -2,6 +2,7 @@ #include #include +#include / { compatible = "dlink,dwr-118-a2", "ralink,mt7620a-soc"; @@ -103,7 +104,9 @@ }; partition@10000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x10000 0xfe0000>; }; diff --git a/target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts b/target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts index e80719a4e7..77b94a1190 100644 --- a/target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts +++ b/target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts @@ -4,6 +4,7 @@ #include #include +#include / { compatible = "dlink,dwr-960", "ralink,mt7620a-soc"; @@ -143,7 +144,9 @@ }; partition@10000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x10000 0xfe0000>; }; diff --git a/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts b/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts index 2c2e485f43..07355a05a5 100644 --- a/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts +++ b/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts @@ -2,6 +2,7 @@ #include #include +#include / { compatible = "lava,lr-25g001", "ralink,mt7620a-soc"; @@ -83,7 +84,9 @@ }; partition@10000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x10000 0xfe0000>; }; diff --git a/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts b/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts index d659262b0e..1c1a700630 100644 --- a/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts +++ b/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts @@ -2,6 +2,7 @@ #include #include +#include / { compatible = "dlink,dwr-116-a1", "ralink,mt7620n-soc"; @@ -69,7 +70,9 @@ }; partition@10000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x10000 0x7e0000>; }; diff --git a/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts b/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts index d37bdb4013..95a93ea4de 100644 --- a/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts +++ b/target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts @@ -2,6 +2,7 @@ #include #include +#include / { compatible = "dlink,dwr-921-c1", "ralink,mt7620n-soc"; @@ -111,7 +112,9 @@ }; partition@10000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x10000 0xfe0000>; }; diff --git a/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts b/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts index d3ca0dd53f..22bff2c948 100644 --- a/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts +++ b/target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts @@ -4,6 +4,7 @@ #include #include +#include / { compatible = "dlink,dwr-922-e2", "ralink,mt7620n-soc"; @@ -114,7 +115,9 @@ }; partition@10000 { - compatible = "amit,jimage"; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = ; + openwrt,offset = <0x10000>; label = "firmware"; reg = <0x10000 0xfe0000>; }; diff --git a/target/linux/ramips/image/Makefile b/target/linux/ramips/image/Makefile index d523a62e0b..ac256cf1ae 100644 --- a/target/linux/ramips/image/Makefile +++ b/target/linux/ramips/image/Makefile @@ -89,6 +89,16 @@ define Build/mkdlinkfw-factory mv $@.new $@ endef +define Build/mkdlinkfw-loader + -$(STAGING_DIR_HOST)/bin/mkdlinkfw \ + -k $(KDIR)/loader-$(DEVICE_NAME).bin \ + -r $@ \ + -o $@.new \ + $(if $(DLINK_IMAGE_OFFSET), -O $(DLINK_IMAGE_OFFSET)) \ + -s $(DLINK_FIRMWARE_SIZE) + mv $@.new $@ +endef + define Build/netis-tail echo -n $(1) >> $@ echo -n $(UIMAGE_NAME)-yun | $(MKHASH) md5 | \ diff --git a/target/linux/ramips/image/mt7620.mk b/target/linux/ramips/image/mt7620.mk index 1d3c76d297..2567c11276 100644 --- a/target/linux/ramips/image/mt7620.mk +++ b/target/linux/ramips/image/mt7620.mk @@ -61,13 +61,18 @@ TARGET_DEVICES += alfa-network_tube-e4g define Device/amit_jboot DLINK_IMAGE_OFFSET := 0x10000 - KERNEL := $(KERNEL_DTB) - KERNEL_SIZE := 2048k + KERNEL := $(KERNEL_DTB) | uImage lzma -M 0x4f4b4c49 + LOADER_FLASH_OFFS := 0x20000 + LOADER_TYPE := bin + COMPILE := loader-$(1).bin + COMPILE/loader-$(1).bin := loader-okli-compile | pad-to 64k | lzma | \ + pad-to 65480 IMAGES += factory.bin - IMAGE/sysupgrade.bin := mkdlinkfw | pad-rootfs | append-metadata - IMAGE/factory.bin := mkdlinkfw | pad-rootfs | mkdlinkfw-factory + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | mkdlinkfw-loader | \ + pad-rootfs | append-metadata + IMAGE/factory.bin := append-kernel | append-rootfs | mkdlinkfw-loader | \ + pad-rootfs | mkdlinkfw-factory DEVICE_PACKAGES := jboot-tools kmod-usb2 kmod-usb-ohci - DEFAULT := n endef define Device/asus_rp-n53 @@ -194,6 +199,7 @@ define Device/dlink_dir-510l $(Device/amit_jboot) SOC := mt7620a IMAGE_SIZE := 14208k + LOADER_FLASH_OFFS := 0x220000 DEVICE_VENDOR := D-Link DEVICE_MODEL := DIR-510L DEVICE_PACKAGES += kmod-mt76x0e diff --git a/target/linux/ramips/mt7620/base-files/etc/board.d/02_network b/target/linux/ramips/mt7620/base-files/etc/board.d/02_network index 2d91911766..a00f168672 100644 --- a/target/linux/ramips/mt7620/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7620/base-files/etc/board.d/02_network @@ -90,15 +90,15 @@ ramips_setup_interfaces() ucidef_add_switch "switch0" \ "1:lan" "2:lan" "3:lan" "4:lan" "0:wan" "6@eth0" ;; + buffalo,whr-1166d) + ucidef_add_switch "switch0" \ + "0:lan" "1:lan" "2:lan" "3:lan" "5:wan" "6@eth0" + ;; buffalo,whr-300hp2|\ buffalo,whr-600d) ucidef_add_switch "switch0" \ "0:lan:1" "1:lan:2" "2:lan:3" "3:lan:4" "4:wan:5" "6@eth0" ;; - buffalo,whr-1166d) - ucidef_add_switch "switch0" \ - "0:lan" "1:lan" "2:lan" "3:lan" "5:wan" "6@eth0" - ;; comfast,cf-wr800n|\ hnet,c108) ucidef_add_switch "switch0" \ @@ -146,7 +146,8 @@ ramips_setup_interfaces() "5:lan" "6@eth0" ucidef_add_switch_attr "switch1" "enable" "false" ;; - fon,fon2601) + fon,fon2601|\ + vonets,var11n-300) ucidef_add_switch "switch0" \ "0:lan" "4:wan" "6@eth0" ;; @@ -205,8 +206,8 @@ ramips_setup_interfaces() ucidef_add_switch "switch0" \ "0:lan:3" "1:lan:2" "2:lan:1" "3:wan" "6@eth0" ;; - tplink,archer-c20i|\ tplink,archer-c20-v1|\ + tplink,archer-c20i|\ tplink,archer-c50-v1) ucidef_add_switch "switch0" \ "1:lan:3" "2:lan:4" "3:lan:1" "4:lan:2" "0:wan" "6@eth0" @@ -216,10 +217,6 @@ ramips_setup_interfaces() "0:lan" "1:lan" "2:lan" "3:lan" "6t@eth0" ucidef_set_interface_wan "usb0" ;; - vonets,var11n-300) - ucidef_add_switch "switch0" \ - "0:lan" "4:wan" "6@eth0" - ;; wavlink,wl-wn579x3) ucidef_add_switch "switch0" \ "5:lan" "4:wan" "6@eth0" @@ -341,6 +338,7 @@ ramips_setup_macs() wan_mac=$(macaddr_add "$(mtd_get_mac_binary u-boot 0x1fc20)" 2) ;; lb-link,bl-w1200|\ + netis,wf2770|\ phicomm,k2-v22.4|\ phicomm,k2-v22.5|\ phicomm,k2g|\ @@ -359,10 +357,6 @@ ramips_setup_macs() linksys,e1700) wan_mac=$(mtd_get_mac_ascii config WAN_MAC_ADDR) ;; - netis,wf2770) - wan_mac=$(mtd_get_mac_binary factory 0x2e) - label_mac=$wan_mac - ;; tplink,archer-c2-v1|\ tplink,archer-c20-v1|\ tplink,archer-c20i|\ diff --git a/target/linux/ramips/mt7620/config-5.4 b/target/linux/ramips/mt7620/config-5.4 deleted file mode 100644 index d6d8ef483f..0000000000 --- a/target/linux/ramips/mt7620/config-5.4 +++ /dev/null @@ -1,195 +0,0 @@ -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -# CONFIG_DTB_MT7620A_EVAL is not set -# CONFIG_DTB_OMEGA2P is not set -CONFIG_DTB_RT_NONE=y -# CONFIG_DTB_VOCORE2 is not set -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_MT7621 is not set -CONFIG_GPIO_RALINK=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MT7621_WDT is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384 -CONFIG_MTD_SPLIT_JIMAGE_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_GSW_MT7620=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_MT7620=y -CONFIG_NET_RALINK_MT7620=y -# CONFIG_NET_RALINK_RT3050 is not set -CONFIG_NET_RALINK_SOC=y -# CONFIG_NET_VENDOR_MEDIATEK is not set -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac index 711af4e3af..8b7c7ab7f0 100644 --- a/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac +++ b/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -39,4 +39,9 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress ;; + tenbay,t-mb5eu-v01) + hw_mac_addr="$(mtd_get_mac_binary factory 0x4)" + [ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr "1" > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr "-1" > /sys${DEVPATH}/macaddress + ;; esac diff --git a/target/linux/ramips/mt7621/config-5.4 b/target/linux/ramips/mt7621/config-5.4 deleted file mode 100644 index 1be4db73fa..0000000000 --- a/target/linux/ramips/mt7621/config-5.4 +++ /dev/null @@ -1,282 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOARD_SCACHE=y -CONFIG_BOUNCE=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MIPS_GIC=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DIMLIB=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -# CONFIG_DTB_GNUBEE1 is not set -# CONFIG_DTB_GNUBEE2 is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_IPI=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MT7621=y -# CONFIG_GPIO_RALINK is not set -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIGHMEM=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_MT7621=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LED_TRIGGER_PHY=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIKROTIK=y -CONFIG_MIKROTIK_RB_SYSFS=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -CONFIG_MIPS_CM=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_CPC=y -CONFIG_MIPS_CPS=y -# CONFIG_MIPS_CPS_NS16550_BOOL is not set -CONFIG_MIPS_CPU_SCACHE=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_GIC=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_NR_CPU_NR_MAP=4 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MT7621_WDT=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MT7621=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_ROUTERBOOT_PARTS=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_MINOR_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_TRX_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_VIRT_CONCAT=y -# CONFIG_MTK_HSDMA is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_RALINK is not set -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_DRIVERS_GENERIC=y -CONFIG_PCI_MT7621=y -CONFIG_PCI_MT7621_PHY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_RALINK_USB is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AW9523=y -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_SX150X=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RALINK=y -# CONFIG_RALINK_WDT is not set -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BQ32K=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SCHED_SMT=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -# CONFIG_SOC_MT7620 is not set -CONFIG_SOC_MT7621=y -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT7621=y -# CONFIG_SPI_RT2880 is not set -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MIPS_CPS=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WEAK_ORDERING=y -CONFIG_WEAK_REORDERING_BEYOND_LLSC=y -CONFIG_XPS=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ramips/mt76x8/config-5.4 b/target/linux/ramips/mt76x8/config-5.4 deleted file mode 100644 index d655d7ff83..0000000000 --- a/target/linux/ramips/mt76x8/config-5.4 +++ /dev/null @@ -1,192 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -# CONFIG_DTB_MT7620A_EVAL is not set -# CONFIG_DTB_OMEGA2P is not set -CONFIG_DTB_RT_NONE=y -# CONFIG_DTB_VOCORE2 is not set -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MT7621=y -# CONFIG_GPIO_RALINK is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MT7621_WDT=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_TRX_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_ESW_RT3050=y -# CONFIG_NET_RALINK_MT7620 is not set -CONFIG_NET_RALINK_RT3050=y -CONFIG_NET_RALINK_SOC=y -# CONFIG_NET_VENDOR_MEDIATEK is not set -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PWM_MEDIATEK is not set -CONFIG_RALINK=y -# CONFIG_RALINK_WDT is not set -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT7621=y -# CONFIG_SPI_RT2880 is not set -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/patches-5.4/0001-MIPS-cmdline-Clean-up-boot_command_line-initializati.patch b/target/linux/ramips/patches-5.4/0001-MIPS-cmdline-Clean-up-boot_command_line-initializati.patch deleted file mode 100644 index eedc7498be..0000000000 --- a/target/linux/ramips/patches-5.4/0001-MIPS-cmdline-Clean-up-boot_command_line-initializati.patch +++ /dev/null @@ -1,192 +0,0 @@ -From: Paul Burton -Date: Wed, 9 Oct 2019 23:09:45 +0000 -Subject: MIPS: cmdline: Clean up boot_command_line initialization - -Our current code to initialize boot_command_line is a mess. Some of this -is due to the addition of too many options over the years, and some of -this is due to workarounds for early_init_dt_scan_chosen() performing -actions specific to options from other architectures that probably -shouldn't be in generic code. - -Clean this up by introducing a new bootcmdline_init() function that -simplifies the initialization somewhat. The major changes are: - -- Because bootcmdline_init() is a function it can return early in the - CONFIG_CMDLINE_OVERRIDE case. - -- We clear boot_command_line rather than inheriting whatever - early_init_dt_scan_chosen() may have left us. This means we no longer - need to set boot_command_line to a space character in an attempt to - prevent early_init_dt_scan_chosen() from copying CONFIG_CMDLINE into - boot_command_line without us knowing about it. - -- Indirection via USE_PROM_CMDLINE, USE_DTB_CMDLINE, EXTEND_WITH_PROM & - BUILTIN_EXTEND_WITH_PROM macros is removed; they seemingly served only - to obfuscate the code. - -- The logic is cleaner, clearer & commented. - -Two minor drawbacks of this approach are: - -1) We call of_scan_flat_dt(), which means we scan through the DT again. - The overhead is fairly minimal & shouldn't be noticeable. - -2) cmdline_scan_chosen() duplicates a small amount of the logic from - early_init_dt_scan_chosen(). Alternatives might be to allow the - generic FDT code to keep & expose a copy of the arguments taken from - the /chosen node's bootargs property, or to introduce a function like - early_init_dt_scan_chosen() that retrieves them without modification - to handle CONFIG_CMDLINE. Neither of these sounds particularly - cleaner though, and this way we at least keep the extra work in - arch/mips. - -Origin: upstream, https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7784cac697351f0cc0a4bb619594c0c99348c5aa -Signed-off-by: Paul Burton -Cc: linux-mips@vger.kernel.org - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -538,11 +538,88 @@ static void __init check_kernel_sections - } - } - --#define USE_PROM_CMDLINE IS_ENABLED(CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER) --#define USE_DTB_CMDLINE IS_ENABLED(CONFIG_MIPS_CMDLINE_FROM_DTB) --#define EXTEND_WITH_PROM IS_ENABLED(CONFIG_MIPS_CMDLINE_DTB_EXTEND) --#define BUILTIN_EXTEND_WITH_PROM \ -- IS_ENABLED(CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND) -+static void __init bootcmdline_append(const char *s, size_t max) -+{ -+ if (!s[0] || !max) -+ return; -+ -+ if (boot_command_line[0]) -+ strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); -+ -+ strlcat(boot_command_line, s, max); -+} -+ -+static int __init bootcmdline_scan_chosen(unsigned long node, const char *uname, -+ int depth, void *data) -+{ -+ bool *dt_bootargs = data; -+ const char *p; -+ int l; -+ -+ if (depth != 1 || !data || -+ (strcmp(uname, "chosen") != 0 && strcmp(uname, "chosen@0") != 0)) -+ return 0; -+ -+ p = of_get_flat_dt_prop(node, "bootargs", &l); -+ if (p != NULL && l > 0) { -+ bootcmdline_append(p, min(l, COMMAND_LINE_SIZE)); -+ *dt_bootargs = true; -+ } -+ -+ return 1; -+} -+ -+static void __init bootcmdline_init(char **cmdline_p) -+{ -+ bool dt_bootargs = false; -+ -+ /* -+ * If CMDLINE_OVERRIDE is enabled then initializing the command line is -+ * trivial - we simply use the built-in command line unconditionally & -+ * unmodified. -+ */ -+ if (IS_ENABLED(CONFIG_CMDLINE_OVERRIDE)) { -+ strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); -+ return; -+ } -+ -+ /* -+ * If the user specified a built-in command line & -+ * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is -+ * prepended to arguments from the bootloader or DT so we'll copy them -+ * to the start of boot_command_line here. Otherwise, empty -+ * boot_command_line to undo anything early_init_dt_scan_chosen() did. -+ */ -+ if (IS_ENABLED(CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND)) -+ strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); -+ else -+ boot_command_line[0] = 0; -+ -+ /* -+ * If we're configured to take boot arguments from DT, look for those -+ * now. -+ */ -+ if (IS_ENABLED(CONFIG_MIPS_CMDLINE_FROM_DTB)) -+ of_scan_flat_dt(bootcmdline_scan_chosen, &dt_bootargs); -+ -+ /* -+ * If we didn't get any arguments from DT (regardless of whether that's -+ * because we weren't configured to look for them, or because we looked -+ * & found none) then we'll take arguments from the bootloader. -+ * plat_mem_setup() should have filled arcs_cmdline with arguments from -+ * the bootloader. -+ */ -+ if (IS_ENABLED(CONFIG_MIPS_CMDLINE_DTB_EXTEND) || !dt_bootargs) -+ bootcmdline_append(arcs_cmdline, COMMAND_LINE_SIZE); -+ -+ /* -+ * If the user specified a built-in command line & we didn't already -+ * prepend it, we append it to boot_command_line here. -+ */ -+ if (IS_ENABLED(CONFIG_CMDLINE_BOOL) && -+ !IS_ENABLED(CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND)) -+ bootcmdline_append(builtin_cmdline, COMMAND_LINE_SIZE); -+} - - /* - * arch_mem_init - initialize memory management subsystem -@@ -570,48 +647,12 @@ static void __init arch_mem_init(char ** - { - extern void plat_mem_setup(void); - -- /* -- * Initialize boot_command_line to an innocuous but non-empty string in -- * order to prevent early_init_dt_scan_chosen() from copying -- * CONFIG_CMDLINE into it without our knowledge. We handle -- * CONFIG_CMDLINE ourselves below & don't want to duplicate its -- * content because repeating arguments can be problematic. -- */ -- strlcpy(boot_command_line, " ", COMMAND_LINE_SIZE); -- - /* call board setup routine */ - plat_mem_setup(); - memblock_set_bottom_up(true); - --#if defined(CONFIG_CMDLINE_BOOL) && defined(CONFIG_CMDLINE_OVERRIDE) -- strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); --#else -- if ((USE_PROM_CMDLINE && arcs_cmdline[0]) || -- (USE_DTB_CMDLINE && !boot_command_line[0])) -- strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE); -- -- if (EXTEND_WITH_PROM && arcs_cmdline[0]) { -- if (boot_command_line[0]) -- strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); -- strlcat(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE); -- } -- --#if defined(CONFIG_CMDLINE_BOOL) -- if (builtin_cmdline[0]) { -- if (boot_command_line[0]) -- strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); -- strlcat(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); -- } -- -- if (BUILTIN_EXTEND_WITH_PROM && arcs_cmdline[0]) { -- if (boot_command_line[0]) -- strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); -- strlcat(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE); -- } --#endif --#endif -+ bootcmdline_init(cmdline_p); - strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); -- - *cmdline_p = command_line; - - parse_early_param(); diff --git a/target/linux/ramips/patches-5.4/0002-MIPS-Always-define-builtin_cmdline.patch b/target/linux/ramips/patches-5.4/0002-MIPS-Always-define-builtin_cmdline.patch deleted file mode 100644 index 03124d07d1..0000000000 --- a/target/linux/ramips/patches-5.4/0002-MIPS-Always-define-builtin_cmdline.patch +++ /dev/null @@ -1,44 +0,0 @@ -From b7340422cc16c5deff100812f38114bb5ec81203 Mon Sep 17 00:00:00 2001 -From: Paul Burton -Date: Sat, 12 Oct 2019 20:43:36 +0000 -Subject: [PATCH] MIPS: Always define builtin_cmdline - -Commit 7784cac69735 ("MIPS: cmdline: Clean up boot_command_line -initialization") made use of builtin_cmdline conditional upon plain C if -statements rather than preprocessor #ifdef's. This caused build failures -for configurations with CONFIG_CMDLINE_BOOL=n where builtin_cmdline -wasn't defined, for example: - - arch/mips/kernel/setup.c: In function 'bootcmdline_init': ->> arch/mips/kernel/setup.c:582:30: error: 'builtin_cmdline' undeclared - (first use in this function); did you mean 'builtin_driver'? - strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); - ^~~~~~~~~~~~~~~ - builtin_driver - arch/mips/kernel/setup.c:582:30: note: each undeclared identifier is - reported only once for each function it appears in - -Fix this by defining builtin_cmdline as an empty string in the affected -configurations. All of the paths that use it should be optimized out -anyway so the data itself gets optimized away too. - -Signed-off-by: Paul Burton -Fixes: 7784cac69735 ("MIPS: cmdline: Clean up boot_command_line initialization") -Reported-by: kbuild test robot -Reported-by: Nathan Chancellor -Cc: linux-mips@vger.kernel.org ---- - arch/mips/kernel/setup.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -68,6 +68,8 @@ char __initdata arcs_cmdline[COMMAND_LIN - - #ifdef CONFIG_CMDLINE_BOOL - static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE; -+#else -+static const char builtin_cmdline[] __initconst = ""; - #endif - - /* diff --git a/target/linux/ramips/patches-5.4/0003-MIPS-Fix-memory-reservation-in-bootmem_init-for-cert.patch b/target/linux/ramips/patches-5.4/0003-MIPS-Fix-memory-reservation-in-bootmem_init-for-cert.patch deleted file mode 100644 index 63429f49b0..0000000000 --- a/target/linux/ramips/patches-5.4/0003-MIPS-Fix-memory-reservation-in-bootmem_init-for-cert.patch +++ /dev/null @@ -1,45 +0,0 @@ -From: Tobias Wolf -Subject: [v2] MIPS: Fix memory reservation in bootmem_init for certain non-usermem setups - -Commit 67a3ba25aa95 ("MIPS: Fix incorrect mem=X@Y handling") introduced a new -issue for rt288x where "PHYS_OFFSET" is 0x0 but the calculated "ramstart" is -not. As the prerequisite of custom memory map has been removed, this results -in the full memory range of 0x0 - 0x8000000 to be marked as reserved for this -platform. - -v2: Correctly compare that usermem is not null. - -This patch adds the originally intended prerequisite again. - -Signed-off-by: Tobias Wolf ---- - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -287,6 +287,8 @@ static unsigned long __init init_initrd( - * Initialize the bootmem allocator. It also setup initrd related data - * if needed. - */ -+static int usermem __initdata; -+ - #if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_NUMA)) - - static void __init bootmem_init(void) -@@ -325,7 +327,7 @@ static void __init bootmem_init(void) - /* - * Reserve any memory between the start of RAM and PHYS_OFFSET - */ -- if (ramstart > PHYS_OFFSET) -+ if (usermem && ramstart > PHYS_OFFSET) - memblock_reserve(PHYS_OFFSET, ramstart - PHYS_OFFSET); - - if (PFN_UP(ramstart) > ARCH_PFN_OFFSET) { -@@ -386,8 +388,6 @@ static void __init bootmem_init(void) - - #endif /* CONFIG_SGI_IP27 */ - --static int usermem __initdata; -- - static int __init early_parse_mem(char *p) - { - phys_addr_t start, size; diff --git a/target/linux/ramips/patches-5.4/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-5.4/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch deleted file mode 100644 index 773c74f4e9..0000000000 --- a/target/linux/ramips/patches-5.4/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch +++ /dev/null @@ -1,82 +0,0 @@ -From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 14 Jul 2013 23:08:11 +0200 -Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k - irq - -Signed-off-by: John Crispin ---- - arch/mips/ralink/Kconfig | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -1,12 +1,17 @@ - # SPDX-License-Identifier: GPL-2.0 - if RALINK - -+config CEVT_SYSTICK_QUIRK -+ bool -+ default n -+ - config CLKEVT_RT3352 - bool - depends on SOC_RT305X || SOC_MT7620 - default y - select TIMER_OF - select CLKSRC_MMIO -+ select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC - bool ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -15,6 +15,26 @@ - #include - #include - -+static int mips_state_oneshot(struct clock_event_device *evt) -+{ -+ if (!cp0_timer_irq_installed) { -+ cp0_timer_irq_installed = 1; -+ setup_irq(evt->irq, &c0_compare_irqaction); -+ } -+ -+ return 0; -+} -+ -+static int mips_state_shutdown(struct clock_event_device *evt) -+{ -+ if (cp0_timer_irq_installed) { -+ cp0_timer_irq_installed = 0; -+ remove_irq(evt->irq, &c0_compare_irqaction); -+ } -+ -+ return 0; -+} -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -281,17 +301,21 @@ int r4k_clockevent_init(void) - cd->rating = 300; - cd->irq = irq; - cd->cpumask = cpumask_of(cpu); -+ cd->set_state_shutdown = mips_state_shutdown; -+ cd->set_state_oneshot = mips_state_oneshot; - cd->set_next_event = mips_next_event; - cd->event_handler = mips_event_handler; - - clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff); - -+#ifndef CONFIG_CEVT_SYSTICK_QUIRK - if (cp0_timer_irq_installed) - return 0; - - cp0_timer_irq_installed = 1; - - setup_irq(irq, &c0_compare_irqaction); -+#endif - - return 0; - } diff --git a/target/linux/ramips/patches-5.4/0006-MIPS-ralink-add-cpu-frequency-scaling.patch b/target/linux/ramips/patches-5.4/0006-MIPS-ralink-add-cpu-frequency-scaling.patch deleted file mode 100644 index a3b8e4d250..0000000000 --- a/target/linux/ramips/patches-5.4/0006-MIPS-ralink-add-cpu-frequency-scaling.patch +++ /dev/null @@ -1,200 +0,0 @@ -From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 28 Jul 2013 16:26:41 +0200 -Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling - -This feature will break udelay() and cause the delay loop to have longer delays -when the frequency is scaled causing a performance hit. - -Signed-off-by: John Crispin ---- - arch/mips/ralink/cevt-rt3352.c | 38 ++++++++++++++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/arch/mips/ralink/cevt-rt3352.c -+++ b/arch/mips/ralink/cevt-rt3352.c -@@ -29,6 +29,10 @@ - /* enable the counter */ - #define CFG_CNT_EN 0x1 - -+/* mt7620 frequency scaling defines */ -+#define CLK_LUT_CFG 0x40 -+#define SLEEP_EN BIT(31) -+ - struct systick_device { - void __iomem *membase; - struct clock_event_device dev; -@@ -36,21 +40,53 @@ struct systick_device { - int freq_scale; - }; - -+static void (*systick_freq_scaling)(struct systick_device *sdev, int status); -+ - static int systick_set_oneshot(struct clock_event_device *evt); - static int systick_shutdown(struct clock_event_device *evt); - -+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) -+{ -+ if (sdev->freq_scale == status) -+ return; -+ -+ sdev->freq_scale = status; -+ -+ pr_info("%s: %s autosleep mode\n", sdev->dev.name, -+ (status) ? ("enable") : ("disable")); -+ if (status) -+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG); -+ else -+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG); -+} -+ -+static inline unsigned int read_count(struct systick_device *sdev) -+{ -+ return ioread32(sdev->membase + SYSTICK_COUNT); -+} -+ -+static inline unsigned int read_compare(struct systick_device *sdev) -+{ -+ return ioread32(sdev->membase + SYSTICK_COMPARE); -+} -+ -+static inline void write_compare(struct systick_device *sdev, unsigned int val) -+{ -+ iowrite32(val, sdev->membase + SYSTICK_COMPARE); -+} -+ - static int systick_next_event(unsigned long delta, - struct clock_event_device *evt) - { - struct systick_device *sdev; -- u32 count; -+ int res; - - sdev = container_of(evt, struct systick_device, dev); -- count = ioread32(sdev->membase + SYSTICK_COUNT); -- count = (count + delta) % SYSTICK_FREQ; -- iowrite32(count, sdev->membase + SYSTICK_COMPARE); -+ delta += read_count(sdev); -+ write_compare(sdev, delta); -+ res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0; - -- return 0; -+ return res; - } - - static void systick_event_handler(struct clock_event_device *dev) -@@ -60,20 +96,25 @@ static void systick_event_handler(struct - - static irqreturn_t systick_interrupt(int irq, void *dev_id) - { -- struct clock_event_device *dev = (struct clock_event_device *) dev_id; -+ int ret = 0; -+ struct clock_event_device *cdev; -+ struct systick_device *sdev; - -- dev->event_handler(dev); -+ if (read_c0_cause() & STATUSF_IP7) { -+ cdev = (struct clock_event_device *) dev_id; -+ sdev = container_of(cdev, struct systick_device, dev); -+ -+ /* Clear Count/Compare Interrupt */ -+ write_compare(sdev, read_compare(sdev)); -+ cdev->event_handler(cdev); -+ ret = 1; -+ } - -- return IRQ_HANDLED; -+ return IRQ_RETVAL(ret); - } - - static struct systick_device systick = { - .dev = { -- /* -- * cevt-r4k uses 300, make sure systick -- * gets used if available -- */ -- .rating = 310, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = systick_next_event, - .set_state_shutdown = systick_shutdown, -@@ -95,9 +136,15 @@ static int systick_shutdown(struct clock - sdev = container_of(evt, struct systick_device, dev); - - if (sdev->irq_requested) -- free_irq(systick.dev.irq, &systick_irqaction); -+ remove_irq(systick.dev.irq, &systick_irqaction); - sdev->irq_requested = 0; -- iowrite32(0, systick.membase + SYSTICK_CONFIG); -+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); -+ -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 0); -+ -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 1); - - return 0; - } -@@ -117,34 +164,48 @@ static int systick_set_oneshot(struct cl - return 0; - } - -+static const struct of_device_id systick_match[] = { -+ { .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling}, -+ {}, -+}; -+ - static int __init ralink_systick_init(struct device_node *np) - { -+ const struct of_device_id *match; -+ int rating = 200; - int ret; - - systick.membase = of_iomap(np, 0); - if (!systick.membase) - return -ENXIO; - -- systick_irqaction.name = np->name; -- systick.dev.name = np->name; -- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60); -- systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev); -- systick.dev.max_delta_ticks = 0x7fff; -- systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev); -- systick.dev.min_delta_ticks = 0x3; -+ match = of_match_node(systick_match, np); -+ if (match) { -+ systick_freq_scaling = match->data; -+ /* -+ * cevt-r4k uses 300, make sure systick -+ * gets used if available -+ */ -+ rating = 310; -+ } -+ -+ /* enable counter than register clock source */ -+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); -+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, -+ SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up); -+ -+ /* register clock event */ - systick.dev.irq = irq_of_parse_and_map(np, 0); - if (!systick.dev.irq) { - pr_err("%pOFn: request_irq failed", np); - return -EINVAL; - } - -- ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, -- SYSTICK_FREQ, 301, 16, -- clocksource_mmio_readl_up); -- if (ret) -- return ret; -- -- clockevents_register_device(&systick.dev); -+ systick_irqaction.name = np->name; -+ systick.dev.name = np->name; -+ systick.dev.rating = rating; -+ systick.dev.cpumask = cpumask_of(0); -+ clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff); - - pr_info("%pOFn: running - mult: %d, shift: %d\n", - np, systick.dev.mult, systick.dev.shift); diff --git a/target/linux/ramips/patches-5.4/0007-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch b/target/linux/ramips/patches-5.4/0007-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch deleted file mode 100644 index c05ee8018d..0000000000 --- a/target/linux/ramips/patches-5.4/0007-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 67b7bff0fd364c194e653f69baa623ba2141bd4c Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 4 Aug 2014 18:46:02 +0200 -Subject: [PATCH 07/53] MIPS: ralink: copy the commandline from the devicetree - -Signed-off-by: John Crispin ---- - arch/mips/ralink/of.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/mips/ralink/of.c -+++ b/arch/mips/ralink/of.c -@@ -82,6 +82,8 @@ void __init plat_mem_setup(void) - - __dt_setup_arch(dtb); - -+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); -+ - of_scan_flat_dt(early_init_dt_find_memory, NULL); - if (memory_dtb) - of_scan_flat_dt(early_init_dt_scan_memory, NULL); diff --git a/target/linux/ramips/patches-5.4/0010-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-5.4/0010-MIPS-add-bootargs-override-property.patch deleted file mode 100644 index c19a0fb480..0000000000 --- a/target/linux/ramips/patches-5.4/0010-MIPS-add-bootargs-override-property.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Thu, 31 Dec 2020 18:49:12 +0100 -Subject: [PATCH] MIPS: add bootargs-override property - -Add support for the bootargs-override property to the chosen node -similar to the one used on ipq806x or mpc85xx. - -This is necessary, as the U-Boot used on some boards, notably the -Ubiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen -node leading to a kernel panic when loading OpenWrt. - -Signed-off-by: David Bauer ---- - arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -571,8 +571,28 @@ static int __init bootcmdline_scan_chose - return 1; - } - -+static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname, -+ int depth, void *data) -+{ -+ bool *dt_bootargs = data; -+ const char *p; -+ int l; -+ -+ if (depth != 1 || !data || strcmp(uname, "chosen") != 0) -+ return 0; -+ -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) { -+ strlcpy(boot_command_line, p, COMMAND_LINE_SIZE); -+ *dt_bootargs = true; -+ } -+ -+ return 1; -+} -+ - static void __init bootcmdline_init(char **cmdline_p) - { -+ bool dt_bootargs_override = false; - bool dt_bootargs = false; - - /* -@@ -586,6 +606,14 @@ static void __init bootcmdline_init(char - } - - /* -+ * If bootargs-override in the chosen node is set, use this as the -+ * command line -+ */ -+ of_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override); -+ if (dt_bootargs_override) -+ return; -+ -+ /* - * If the user specified a built-in command line & - * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is - * prepended to arguments from the bootloader or DT so we'll copy them diff --git a/target/linux/ramips/patches-5.4/0013-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-5.4/0013-owrt-hack-fix-mt7688-cache-issue.patch deleted file mode 100644 index bedea14506..0000000000 --- a/target/linux/ramips/patches-5.4/0013-owrt-hack-fix-mt7688-cache-issue.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:15:32 +0100 -Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue - -Signed-off-by: John Crispin ---- - arch/mips/kernel/setup.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -723,8 +723,6 @@ static void __init arch_mem_init(char ** - memblock_reserve(crashk_res.start, - crashk_res.end - crashk_res.start + 1); - #endif -- device_tree_init(); -- - /* - * In order to reduce the possibility of kernel panic when failed to - * get IO TLB memory under CONFIG_SWIOTLB, it is better to allocate -@@ -841,6 +839,7 @@ void __init setup_arch(char **cmdline_p) - - cpu_cache_init(); - paging_init(); -+ device_tree_init(); - } - - unsigned long kernelsp[NR_CPUS]; diff --git a/target/linux/ramips/patches-5.4/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch b/target/linux/ramips/patches-5.4/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch deleted file mode 100644 index 1dc54ccf23..0000000000 --- a/target/linux/ramips/patches-5.4/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:18:05 +0100 -Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by - default - -Signed-off-by: John Crispin ---- - arch/mips/ralink/Kconfig | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -14,9 +14,9 @@ config CLKEVT_RT3352 - select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC -- bool -+ bool "illegal access irq" - depends on SOC_RT305X -- default y -+ default n - - config IRQ_INTC - bool diff --git a/target/linux/ramips/patches-5.4/0024-GPIO-add-named-gpio-exports.patch b/target/linux/ramips/patches-5.4/0024-GPIO-add-named-gpio-exports.patch deleted file mode 100644 index 805836fcca..0000000000 --- a/target/linux/ramips/patches-5.4/0024-GPIO-add-named-gpio-exports.patch +++ /dev/null @@ -1,165 +0,0 @@ -From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 12 Aug 2014 20:49:27 +0200 -Subject: [PATCH 24/53] GPIO: add named gpio exports - -Signed-off-by: John Crispin ---- - drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ - drivers/gpio/gpiolib-sysfs.c | 10 +++++- - include/asm-generic/gpio.h | 6 ++++ - include/linux/gpio/consumer.h | 8 +++++ - 4 files changed, 91 insertions(+), 1 deletion(-) - ---- a/drivers/gpio/gpiolib-of.c -+++ b/drivers/gpio/gpiolib-of.c -@@ -19,6 +19,8 @@ - #include - #include - #include -+#include -+#include - - #include "gpiolib.h" - #include "gpiolib-of.h" -@@ -915,3 +917,68 @@ void of_gpiochip_remove(struct gpio_chip - { - of_node_put(chip->of_node); - } -+ -+static struct of_device_id gpio_export_ids[] = { -+ { .compatible = "gpio-export" }, -+ { /* sentinel */ } -+}; -+ -+static int of_gpio_export_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct device_node *cnp; -+ u32 val; -+ int nb = 0; -+ -+ for_each_child_of_node(np, cnp) { -+ const char *name = NULL; -+ int gpio; -+ bool dmc; -+ int max_gpio = 1; -+ int i; -+ -+ of_property_read_string(cnp, "gpio-export,name", &name); -+ -+ if (!name) -+ max_gpio = of_gpio_count(cnp); -+ -+ for (i = 0; i < max_gpio; i++) { -+ unsigned flags = 0; -+ enum of_gpio_flags of_flags; -+ -+ gpio = of_get_gpio_flags(cnp, i, &of_flags); -+ if (!gpio_is_valid(gpio)) -+ return gpio; -+ -+ if (of_flags == OF_GPIO_ACTIVE_LOW) -+ flags |= GPIOF_ACTIVE_LOW; -+ -+ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) -+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ else -+ flags |= GPIOF_IN; -+ -+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) -+ continue; -+ -+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); -+ gpio_export_with_name(gpio, dmc, name); -+ nb++; -+ } -+ } -+ -+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); -+ -+ return 0; -+} -+ -+static struct platform_driver gpio_export_driver = { -+ .driver = { -+ .name = "gpio-export", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(gpio_export_ids), -+ }, -+ .probe = of_gpio_export_probe, -+}; -+ -+module_platform_driver(gpio_export_driver); ---- a/drivers/gpio/gpiolib-sysfs.c -+++ b/drivers/gpio/gpiolib-sysfs.c -@@ -571,7 +571,7 @@ static struct class gpio_class = { - * - * Returns zero on success, else an error. - */ --int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) - { - struct gpio_chip *chip; - struct gpio_device *gdev; -@@ -633,6 +633,8 @@ int gpiod_export(struct gpio_desc *desc, - offset = gpio_chip_hwgpio(desc); - if (chip->names && chip->names[offset]) - ioname = chip->names[offset]; -+ if (name) -+ ioname = name; - - dev = device_create_with_groups(&gpio_class, &gdev->dev, - MKDEV(0, 0), data, gpio_groups, -@@ -654,6 +656,12 @@ err_unlock: - gpiod_dbg(desc, "%s: status %d\n", __func__, status); - return status; - } -+EXPORT_SYMBOL_GPL(__gpiod_export); -+ -+int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+{ -+ return __gpiod_export(desc, direction_may_change, NULL); -+} - EXPORT_SYMBOL_GPL(gpiod_export); - - static int match_export(struct device *dev, const void *desc) ---- a/include/asm-generic/gpio.h -+++ b/include/asm-generic/gpio.h -@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g - return gpiod_export(gpio_to_desc(gpio), direction_may_change); - } - -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); -+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) -+{ -+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); -+} -+ - static inline int gpio_export_link(struct device *dev, const char *name, - unsigned gpio) - { ---- a/include/linux/gpio/consumer.h -+++ b/include/linux/gpio/consumer.h -@@ -668,6 +668,7 @@ static inline void devm_acpi_dev_remove_ - - #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) - -+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); - int gpiod_export(struct gpio_desc *desc, bool direction_may_change); - int gpiod_export_link(struct device *dev, const char *name, - struct gpio_desc *desc); -@@ -675,6 +676,13 @@ void gpiod_unexport(struct gpio_desc *de - - #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ - -+static inline int _gpiod_export(struct gpio_desc *desc, -+ bool direction_may_change, -+ const char *name) -+{ -+ return -ENOSYS; -+} -+ - static inline int gpiod_export(struct gpio_desc *desc, - bool direction_may_change) - { diff --git a/target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch b/target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch deleted file mode 100644 index 93dabf8776..0000000000 --- a/target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch +++ /dev/null @@ -1,59 +0,0 @@ -From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 28 Jul 2013 19:45:30 +0200 -Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink - -Describe gpio-ralink binding. - -Signed-off-by: John Crispin -Cc: linux-mips@linux-mips.org -Cc: devicetree@vger.kernel.org -Cc: linux-gpio@vger.kernel.org ---- - .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++ - 1 file changed, 40 insertions(+) - create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -@@ -0,0 +1,40 @@ -+Ralink SoC GPIO controller bindings -+ -+Required properties: -+- compatible: -+ - "ralink,rt2880-gpio" for Ralink controllers -+- #gpio-cells : Should be two. -+ - first cell is the pin number -+ - second cell is used to specify optional parameters (unused) -+- gpio-controller : Marks the device node as a GPIO controller -+- reg : Physical base address and length of the controller's registers -+- interrupt-parent: phandle to the INTC device node -+- interrupts : Specify the INTC interrupt number -+- ngpios : Specify the number of GPIOs -+- ralink,register-map : The register layout depends on the GPIO bank and actual -+ SoC type. Register offsets need to be in this order. -+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ] -+ -+Optional properties: -+- ralink,gpio-base : Specify the GPIO chips base number -+ -+Example: -+ -+ gpio0: gpio@600 { -+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio"; -+ -+ #gpio-cells = <2>; -+ gpio-controller; -+ -+ reg = <0x600 0x34>; -+ -+ interrupt-parent = <&intc>; -+ interrupts = <6>; -+ -+ ngpios = <24>; -+ ralink,gpio-base = <0>; -+ ralink,register-map = [ 00 04 08 0c -+ 20 24 28 2c -+ 30 34 ]; -+ -+ }; diff --git a/target/linux/ramips/patches-5.4/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch b/target/linux/ramips/patches-5.4/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch deleted file mode 100644 index 525c1976f9..0000000000 --- a/target/linux/ramips/patches-5.4/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch +++ /dev/null @@ -1,416 +0,0 @@ -From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 4 Aug 2014 20:36:29 +0200 -Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC - -Add gpio driver for Ralink SoC. This driver makes the gpio core on -RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work. - -Signed-off-by: John Crispin -Cc: linux-mips@linux-mips.org -Cc: linux-gpio@vger.kernel.org ---- - arch/mips/include/asm/mach-ralink/gpio.h | 24 ++ - drivers/gpio/Kconfig | 6 + - drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++ - 4 files changed, 386 insertions(+) - create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h - create mode 100644 drivers/gpio/gpio-ralink.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-ralink/gpio.h -@@ -0,0 +1,24 @@ -+/* -+ * Ralink SoC GPIO API support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MACH_RALINK_GPIO_H -+#define __ASM_MACH_RALINK_GPIO_H -+ -+#define ARCH_NR_GPIOS 128 -+#include -+ -+#define gpio_get_value __gpio_get_value -+#define gpio_set_value __gpio_set_value -+#define gpio_cansleep __gpio_cansleep -+#define gpio_to_irq __gpio_to_irq -+ -+#endif /* __ASM_MACH_RALINK_GPIO_H */ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -471,6 +471,12 @@ config GPIO_SNPS_CREG - where only several fields in register belong to GPIO lines and - each GPIO line owns a field with different length and on/off value. - -+config GPIO_RALINK -+ bool "Ralink GPIO Support" -+ depends on RALINK -+ help -+ Say yes here to support the Ralink SoC GPIO device -+ - config GPIO_SPEAR_SPICS - bool "ST SPEAr13xx SPI Chip Select as GPIO support" - depends on PLAT_SPEAR ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -112,6 +112,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos - obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o - obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o - obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o -+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o - obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o - obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o - obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o ---- /dev/null -+++ b/drivers/gpio/gpio-ralink.c -@@ -0,0 +1,341 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2009-2011 Gabor Juhos -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+enum ralink_gpio_reg { -+ GPIO_REG_INT = 0, -+ GPIO_REG_EDGE, -+ GPIO_REG_RENA, -+ GPIO_REG_FENA, -+ GPIO_REG_DATA, -+ GPIO_REG_DIR, -+ GPIO_REG_POL, -+ GPIO_REG_SET, -+ GPIO_REG_RESET, -+ GPIO_REG_TOGGLE, -+ GPIO_REG_MAX -+}; -+ -+struct ralink_gpio_chip { -+ struct gpio_chip chip; -+ u8 regs[GPIO_REG_MAX]; -+ -+ spinlock_t lock; -+ void __iomem *membase; -+ struct irq_domain *domain; -+ int irq; -+ -+ u32 rising; -+ u32 falling; -+}; -+ -+#define MAP_MAX 4 -+static struct irq_domain *irq_map[MAP_MAX]; -+static int irq_map_count; -+static atomic_t irq_refcount = ATOMIC_INIT(0); -+ -+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip) -+{ -+ struct ralink_gpio_chip *rg; -+ -+ rg = container_of(chip, struct ralink_gpio_chip, chip); -+ -+ return rg; -+} -+ -+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val) -+{ -+ iowrite32(val, rg->membase + rg->regs[reg]); -+} -+ -+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg) -+{ -+ return ioread32(rg->membase + rg->regs[reg]); -+} -+ -+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset)); -+} -+ -+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset)); -+} -+ -+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ t = rt_gpio_r32(rg, GPIO_REG_DIR); -+ t &= ~BIT(offset); -+ rt_gpio_w32(rg, GPIO_REG_DIR, t); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int ralink_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ ralink_gpio_set(chip, offset, value); -+ t = rt_gpio_r32(rg, GPIO_REG_DIR); -+ t |= BIT(offset); -+ rt_gpio_w32(rg, GPIO_REG_DIR, t); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ if (rg->irq < 1) -+ return -1; -+ -+ return irq_create_mapping(rg->domain, pin); -+} -+ -+static void ralink_gpio_irq_handler(struct irq_desc *desc) -+{ -+ int i; -+ -+ for (i = 0; i < irq_map_count; i++) { -+ struct irq_domain *domain = irq_map[i]; -+ struct ralink_gpio_chip *rg; -+ unsigned long pending; -+ int bit; -+ -+ rg = (struct ralink_gpio_chip *) domain->host_data; -+ pending = rt_gpio_r32(rg, GPIO_REG_INT); -+ -+ for_each_set_bit(bit, &pending, rg->chip.ngpio) { -+ u32 map = irq_find_mapping(domain, bit); -+ generic_handle_irq(map); -+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit)); -+ } -+ } -+} -+ -+static void ralink_gpio_irq_unmask(struct irq_data *d) -+{ -+ struct ralink_gpio_chip *rg; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ rise = rt_gpio_r32(rg, GPIO_REG_RENA); -+ fall = rt_gpio_r32(rg, GPIO_REG_FENA); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising)); -+ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static void ralink_gpio_irq_mask(struct irq_data *d) -+{ -+ struct ralink_gpio_chip *rg; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ rise = rt_gpio_r32(rg, GPIO_REG_RENA); -+ fall = rt_gpio_r32(rg, GPIO_REG_FENA); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq)); -+ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type) -+{ -+ struct ralink_gpio_chip *rg; -+ u32 mask = BIT(d->hwirq); -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ -+ if (type == IRQ_TYPE_PROBE) { -+ if ((rg->rising | rg->falling) & mask) -+ return 0; -+ -+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; -+ } -+ -+ if (type & IRQ_TYPE_EDGE_RISING) -+ rg->rising |= mask; -+ else -+ rg->rising &= ~mask; -+ -+ if (type & IRQ_TYPE_EDGE_FALLING) -+ rg->falling |= mask; -+ else -+ rg->falling &= ~mask; -+ -+ return 0; -+} -+ -+static struct irq_chip ralink_gpio_irq_chip = { -+ .name = "GPIO", -+ .irq_unmask = ralink_gpio_irq_unmask, -+ .irq_mask = ralink_gpio_irq_mask, -+ .irq_mask_ack = ralink_gpio_irq_mask, -+ .irq_set_type = ralink_gpio_irq_type, -+}; -+ -+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -+{ -+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq); -+ irq_set_handler_data(irq, d); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops irq_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = gpio_map, -+}; -+ -+static void ralink_gpio_irq_init(struct device_node *np, -+ struct ralink_gpio_chip *rg) -+{ -+ if (irq_map_count >= MAP_MAX) -+ return; -+ -+ rg->irq = irq_of_parse_and_map(np, 0); -+ if (!rg->irq) -+ return; -+ -+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, -+ &irq_domain_ops, rg); -+ if (!rg->domain) { -+ dev_err(rg->chip.parent, "irq_domain_add_linear failed\n"); -+ return; -+ } -+ -+ irq_map[irq_map_count++] = rg->domain; -+ -+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0); -+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0); -+ -+ if (!atomic_read(&irq_refcount)) -+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler); -+ atomic_inc(&irq_refcount); -+ -+ dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio); -+} -+ -+static int ralink_gpio_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ struct ralink_gpio_chip *rg; -+ const __be32 *ngpio, *gpiobase; -+ -+ if (!res) { -+ dev_err(&pdev->dev, "failed to find resource\n"); -+ return -ENOMEM; -+ } -+ -+ rg = devm_kzalloc(&pdev->dev, -+ sizeof(struct ralink_gpio_chip), GFP_KERNEL); -+ if (!rg) -+ return -ENOMEM; -+ -+ rg->membase = devm_ioremap_resource(&pdev->dev, res); -+ if (!rg->membase) { -+ dev_err(&pdev->dev, "cannot remap I/O memory region\n"); -+ return -ENOMEM; -+ } -+ -+ if (of_property_read_u8_array(np, "ralink,register-map", -+ rg->regs, GPIO_REG_MAX)) { -+ dev_err(&pdev->dev, "failed to read register definition\n"); -+ return -EINVAL; -+ } -+ -+ ngpio = of_get_property(np, "ngpios", NULL); -+ if (!ngpio) { -+ dev_err(&pdev->dev, "failed to read number of pins\n"); -+ return -EINVAL; -+ } -+ -+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL); -+ if (gpiobase) -+ rg->chip.base = be32_to_cpu(*gpiobase); -+ else -+ rg->chip.base = -1; -+ -+ spin_lock_init(&rg->lock); -+ -+ rg->chip.parent = &pdev->dev; -+ rg->chip.label = dev_name(&pdev->dev); -+ rg->chip.of_node = np; -+ rg->chip.ngpio = be32_to_cpu(*ngpio); -+ rg->chip.direction_input = ralink_gpio_direction_input; -+ rg->chip.direction_output = ralink_gpio_direction_output; -+ rg->chip.get = ralink_gpio_get; -+ rg->chip.set = ralink_gpio_set; -+ rg->chip.request = gpiochip_generic_request; -+ rg->chip.to_irq = ralink_gpio_to_irq; -+ rg->chip.free = gpiochip_generic_free; -+ -+ /* set polarity to low for all lines */ -+ rt_gpio_w32(rg, GPIO_REG_POL, 0); -+ -+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); -+ -+ ralink_gpio_irq_init(np, rg); -+ -+ return gpiochip_add(&rg->chip); -+} -+ -+static const struct of_device_id ralink_gpio_match[] = { -+ { .compatible = "ralink,rt2880-gpio" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ralink_gpio_match); -+ -+static struct platform_driver ralink_gpio_driver = { -+ .probe = ralink_gpio_probe, -+ .driver = { -+ .name = "rt2880_gpio", -+ .owner = THIS_MODULE, -+ .of_match_table = ralink_gpio_match, -+ }, -+}; -+ -+static int __init ralink_gpio_init(void) -+{ -+ return platform_driver_register(&ralink_gpio_driver); -+} -+ -+subsys_initcall(ralink_gpio_init); diff --git a/target/linux/ramips/patches-5.4/0029-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch b/target/linux/ramips/patches-5.4/0029-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch deleted file mode 100644 index 8520ce32ff..0000000000 --- a/target/linux/ramips/patches-5.4/0029-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001 -From: Daniel Santos -Date: Sun, 4 Nov 2018 20:24:32 -0600 -Subject: gpio-ralink: Add support for GPIO as interrupt-controller - -Signed-off-by: Daniel Santos ---- - Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++ - drivers/gpio/gpio-ralink.c | 2 +- - 2 files changed, 7 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -@@ -17,6 +17,9 @@ Required properties: - - Optional properties: - - ralink,gpio-base : Specify the GPIO chips base number -+- interrupt-controller : marks this as an interrupt controller -+- #interrupt-cells : a standard two-cell interrupt flag, see -+ interrupt-controller/interrupts.txt - - Example: - -@@ -28,6 +31,9 @@ Example: - - reg = <0x600 0x34>; - -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ - interrupt-parent = <&intc>; - interrupts = <6>; - ---- a/drivers/gpio/gpio-ralink.c -+++ b/drivers/gpio/gpio-ralink.c -@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d - } - - static const struct irq_domain_ops irq_domain_ops = { -- .xlate = irq_domain_xlate_onecell, -+ .xlate = irq_domain_xlate_twocell, - .map = gpio_map, - }; - diff --git a/target/linux/ramips/patches-5.4/0031-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-5.4/0031-uvc-add-iPassion-iP2970-support.patch deleted file mode 100644 index f088babc4e..0000000000 --- a/target/linux/ramips/patches-5.4/0031-uvc-add-iPassion-iP2970-support.patch +++ /dev/null @@ -1,246 +0,0 @@ -From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 19 Sep 2013 01:50:59 +0200 -Subject: [PATCH 31/53] uvc: add iPassion iP2970 support - -Signed-off-by: John Crispin ---- - drivers/media/usb/uvc/uvc_driver.c | 12 +++ - drivers/media/usb/uvc/uvc_status.c | 2 + - drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++ - drivers/media/usb/uvc/uvcvideo.h | 5 +- - 4 files changed, 165 insertions(+), 1 deletion(-) - ---- a/drivers/media/usb/uvc/uvc_driver.c -+++ b/drivers/media/usb/uvc/uvc_driver.c -@@ -2916,6 +2916,18 @@ static const struct usb_device_id uvc_id - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 0, - .driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) }, -+ /* iPassion iP2970 */ -+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE -+ | USB_DEVICE_ID_MATCH_INT_INFO, -+ .idVendor = 0x1B3B, -+ .idProduct = 0x2970, -+ .bInterfaceClass = USB_CLASS_VIDEO, -+ .bInterfaceSubClass = 1, -+ .bInterfaceProtocol = 0, -+ .driver_info = UVC_QUIRK_PROBE_MINMAX -+ | UVC_QUIRK_STREAM_NO_FID -+ | UVC_QUIRK_MOTION -+ | UVC_QUIRK_SINGLE_ISO }, - /* Generic USB Video Class */ - { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) }, - { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) }, ---- a/drivers/media/usb/uvc/uvc_status.c -+++ b/drivers/media/usb/uvc/uvc_status.c -@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u - if (uvc_event_control(urb, status, len)) - /* The URB will be resubmitted in work context. */ - return; -+ dev->motion = 1; - break; - } - -@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d - } - - pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress); -+ dev->motion = 0; - - /* For high-speed interrupt endpoints, the bInterval value is used as - * an exponent of two. Some developers forgot about it. ---- a/drivers/media/usb/uvc/uvc_video.c -+++ b/drivers/media/usb/uvc/uvc_video.c -@@ -16,6 +16,11 @@ - #include - #include - #include -+#include -+#include -+#include -+#include -+#include - - #include - -@@ -1188,9 +1193,149 @@ static void uvc_video_decode_data(struct - uvc_urb->async_operations++; - } - -+struct bh_priv { -+ unsigned long seen; -+}; -+ -+struct bh_event { -+ const char *name; -+ struct sk_buff *skb; -+ struct work_struct work; -+}; -+ -+#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args ) -+#define BH_DBG(fmt, args...) do {} while (0) -+#define BH_SKB_SIZE 2048 -+ -+extern u64 uevent_next_seqnum(void); -+static int seen = 0; -+ -+static int bh_event_add_var(struct bh_event *event, int argv, -+ const char *format, ...) -+{ -+ static char buf[128]; -+ char *s; -+ va_list args; -+ int len; -+ -+ if (argv) -+ return 0; -+ -+ va_start(args, format); -+ len = vsnprintf(buf, sizeof(buf), format, args); -+ va_end(args); -+ -+ if (len >= sizeof(buf)) { -+ BH_ERR("buffer size too small\n"); -+ WARN_ON(1); -+ return -ENOMEM; -+ } -+ -+ s = skb_put(event->skb, len + 1); -+ strcpy(s, buf); -+ -+ BH_DBG("added variable '%s'\n", s); -+ -+ return 0; -+} -+ -+static int motion_hotplug_fill_event(struct bh_event *event) -+{ -+ int s = jiffies; -+ int ret; -+ -+ if (!seen) -+ seen = jiffies; -+ -+ ret = bh_event_add_var(event, 0, "HOME=%s", "/"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "PATH=%s", -+ "/sbin:/bin:/usr/sbin:/usr/bin"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "ACTION=motion"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen); -+ if (ret) -+ return ret; -+ seen = s; -+ -+ ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum()); -+ -+ return ret; -+} -+ -+static void motion_hotplug_work(struct work_struct *work) -+{ -+ struct bh_event *event = container_of(work, struct bh_event, work); -+ int ret = 0; -+ -+ event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL); -+ if (!event->skb) -+ goto out_free_event; -+ -+ ret = bh_event_add_var(event, 0, "%s@", "add"); -+ if (ret) -+ goto out_free_skb; -+ -+ ret = motion_hotplug_fill_event(event); -+ if (ret) -+ goto out_free_skb; -+ -+ NETLINK_CB(event->skb).dst_group = 1; -+ broadcast_uevent(event->skb, 0, 1, GFP_KERNEL); -+ -+out_free_skb: -+ if (ret) { -+ BH_ERR("work error %d\n", ret); -+ kfree_skb(event->skb); -+ } -+out_free_event: -+ kfree(event); -+} -+ -+static int motion_hotplug_create_event(void) -+{ -+ struct bh_event *event; -+ -+ event = kzalloc(sizeof(*event), GFP_KERNEL); -+ if (!event) -+ return -ENOMEM; -+ -+ event->name = "motion"; -+ -+ INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work); -+ schedule_work(&event->work); -+ -+ return 0; -+} -+ -+#define MOTION_FLAG_OFFSET 4 - static void uvc_video_decode_end(struct uvc_streaming *stream, - struct uvc_buffer *buf, const u8 *data, int len) - { -+ if ((stream->dev->quirks & UVC_QUIRK_MOTION) && -+ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) { -+ u8 *mem; -+ buf->state = UVC_BUF_STATE_READY; -+ mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET); -+ if ( stream->dev->motion ) { -+ stream->dev->motion = 0; -+ motion_hotplug_create_event(); -+ } else { -+ *mem &= 0x7f; -+ } -+ } -+ - /* Mark the buffer as done if the EOF marker is set. */ - if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) { - uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n"); -@@ -1747,6 +1892,8 @@ static int uvc_init_video_isoc(struct uv - if (npackets == 0) - return -ENOMEM; - -+ if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO) -+ npackets = 1; - size = npackets * psize; - - for_each_uvc_urb(uvc_urb, stream) { ---- a/drivers/media/usb/uvc/uvcvideo.h -+++ b/drivers/media/usb/uvc/uvcvideo.h -@@ -199,7 +199,9 @@ - #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT 0x00000400 - #define UVC_QUIRK_FORCE_Y8 0x00000800 - #define UVC_QUIRK_FORCE_BPP 0x00001000 -- -+#define UVC_QUIRK_MOTION 0x00001000 -+#define UVC_QUIRK_SINGLE_ISO 0x00002000 -+ - /* Format flags */ - #define UVC_FMT_FLAG_COMPRESSED 0x00000001 - #define UVC_FMT_FLAG_STREAM 0x00000002 -@@ -666,6 +668,7 @@ struct uvc_device { - u8 *status; - struct input_dev *input; - char input_phys[64]; -+ int motion; - - struct uvc_ctrl_work { - struct work_struct work; diff --git a/target/linux/ramips/patches-5.4/0037-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-5.4/0037-mtd-cfi-cmdset-0002-force-word-write.patch deleted file mode 100644 index 7011bbe50b..0000000000 --- a/target/linux/ramips/patches-5.4/0037-mtd-cfi-cmdset-0002-force-word-write.patch +++ /dev/null @@ -1,20 +0,0 @@ -From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 15 Jul 2013 00:39:21 +0200 -Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write - ---- - drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -40,7 +40,7 @@ - #include - - #define AMD_BOOTLOC_BUG --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MAX_RETRIES 3 - diff --git a/target/linux/ramips/patches-5.4/0041-DT-Add-documentation-for-spi-rt2880.patch b/target/linux/ramips/patches-5.4/0041-DT-Add-documentation-for-spi-rt2880.patch deleted file mode 100644 index e2643e3f25..0000000000 --- a/target/linux/ramips/patches-5.4/0041-DT-Add-documentation-for-spi-rt2880.patch +++ /dev/null @@ -1,44 +0,0 @@ -From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 9 Aug 2013 20:12:59 +0200 -Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880 - -Describe the SPI master found on the MIPS based Ralink RT2880 SoC. - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++ - 1 file changed, 28 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt -@@ -0,0 +1,28 @@ -+Ralink SoC RT2880 SPI master controller. -+ -+This SPI controller is found on most wireless SoCs made by ralink. -+ -+Required properties: -+- compatible : "ralink,rt2880-spi" -+- reg : The register base for the controller. -+- #address-cells : <1>, as required by generic SPI binding. -+- #size-cells : <0>, also as required by generic SPI binding. -+ -+Child nodes as per the generic SPI binding. -+ -+Example: -+ -+ spi@b00 { -+ compatible = "ralink,rt2880-spi"; -+ reg = <0xb00 0x100>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ m25p80@0 { -+ compatible = "m25p80"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ }; -+ diff --git a/target/linux/ramips/patches-5.4/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-5.4/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch deleted file mode 100644 index 652371617a..0000000000 --- a/target/linux/ramips/patches-5.4/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch +++ /dev/null @@ -1,574 +0,0 @@ -From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 11:15:12 +0100 -Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver - -Add the driver needed to make SPI work on Ralink SoC. - -Signed-off-by: Gabor Juhos -Acked-by: John Crispin ---- - drivers/spi/Kconfig | 6 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 537 insertions(+) - create mode 100644 drivers/spi/spi-rt2880.c - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -605,6 +605,12 @@ config SPI_QCOM_GENI - This driver can also be built as a module. If so, the module - will be called spi-geni-qcom. - -+config SPI_RT2880 -+ tristate "Ralink RT288x SPI Controller" -+ depends on RALINK -+ help -+ This selects a driver for the Ralink RT288x/RT305x SPI Controller. -+ - config SPI_S3C24XX - tristate "Samsung S3C24XX series SPI" - depends on ARCH_S3C24XX ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -87,6 +87,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o - obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o - obj-$(CONFIG_SPI_RSPI) += spi-rspi.o -+obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o - obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o - spi-s3c24xx-hw-y := spi-s3c24xx.o - spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o ---- /dev/null -+++ b/drivers/spi/spi-rt2880.c -@@ -0,0 +1,530 @@ -+/* -+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver -+ * -+ * Copyright (C) 2011 Sergiy -+ * Copyright (C) 2011-2013 Gabor Juhos -+ * -+ * Some parts are based on spi-orion.c: -+ * Author: Shadi Ammouri -+ * Copyright (C) 2007-2008 Marvell Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "spi-rt2880" -+ -+#define RAMIPS_SPI_STAT 0x00 -+#define RAMIPS_SPI_CFG 0x10 -+#define RAMIPS_SPI_CTL 0x14 -+#define RAMIPS_SPI_DATA 0x20 -+#define RAMIPS_SPI_ADDR 0x24 -+#define RAMIPS_SPI_BS 0x28 -+#define RAMIPS_SPI_USER 0x2C -+#define RAMIPS_SPI_TXFIFO 0x30 -+#define RAMIPS_SPI_RXFIFO 0x34 -+#define RAMIPS_SPI_FIFO_STAT 0x38 -+#define RAMIPS_SPI_MODE 0x3C -+#define RAMIPS_SPI_DEV_OFFSET 0x40 -+#define RAMIPS_SPI_DMA 0x80 -+#define RAMIPS_SPI_DMASTAT 0x84 -+#define RAMIPS_SPI_ARBITER 0xF0 -+ -+/* SPISTAT register bit field */ -+#define SPISTAT_BUSY BIT(0) -+ -+/* SPICFG register bit field */ -+#define SPICFG_ADDRMODE BIT(12) -+#define SPICFG_RXENVDIS BIT(11) -+#define SPICFG_RXCAP BIT(10) -+#define SPICFG_SPIENMODE BIT(9) -+#define SPICFG_MSBFIRST BIT(8) -+#define SPICFG_SPICLKPOL BIT(6) -+#define SPICFG_RXCLKEDGE_FALLING BIT(5) -+#define SPICFG_TXCLKEDGE_FALLING BIT(4) -+#define SPICFG_HIZSPI BIT(3) -+#define SPICFG_SPICLK_PRESCALE_MASK 0x7 -+#define SPICFG_SPICLK_DIV2 0 -+#define SPICFG_SPICLK_DIV4 1 -+#define SPICFG_SPICLK_DIV8 2 -+#define SPICFG_SPICLK_DIV16 3 -+#define SPICFG_SPICLK_DIV32 4 -+#define SPICFG_SPICLK_DIV64 5 -+#define SPICFG_SPICLK_DIV128 6 -+#define SPICFG_SPICLK_DISABLE 7 -+ -+/* SPICTL register bit field */ -+#define SPICTL_START BIT(4) -+#define SPICTL_HIZSDO BIT(3) -+#define SPICTL_STARTWR BIT(2) -+#define SPICTL_STARTRD BIT(1) -+#define SPICTL_SPIENA BIT(0) -+ -+/* SPIUSER register bit field */ -+#define SPIUSER_USERMODE BIT(21) -+#define SPIUSER_INSTR_PHASE BIT(20) -+#define SPIUSER_ADDR_PHASE_MASK 0x7 -+#define SPIUSER_ADDR_PHASE_OFFSET 17 -+#define SPIUSER_MODE_PHASE BIT(16) -+#define SPIUSER_DUMMY_PHASE_MASK 0x3 -+#define SPIUSER_DUMMY_PHASE_OFFSET 14 -+#define SPIUSER_DATA_PHASE_MASK 0x3 -+#define SPIUSER_DATA_PHASE_OFFSET 12 -+#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET) -+#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET) -+#define SPIUSER_ADDR_TYPE_OFFSET 9 -+#define SPIUSER_MODE_TYPE_OFFSET 6 -+#define SPIUSER_DUMMY_TYPE_OFFSET 3 -+#define SPIUSER_DATA_TYPE_OFFSET 0 -+#define SPIUSER_TRANSFER_MASK 0x7 -+#define SPIUSER_TRANSFER_SINGLE BIT(0) -+#define SPIUSER_TRANSFER_DUAL BIT(1) -+#define SPIUSER_TRANSFER_QUAD BIT(2) -+ -+#define SPIUSER_TRANSFER_TYPE(type) ( \ -+ (type << SPIUSER_ADDR_TYPE_OFFSET) | \ -+ (type << SPIUSER_MODE_TYPE_OFFSET) | \ -+ (type << SPIUSER_DUMMY_TYPE_OFFSET) | \ -+ (type << SPIUSER_DATA_TYPE_OFFSET) \ -+) -+ -+/* SPIFIFOSTAT register bit field */ -+#define SPIFIFOSTAT_TXEMPTY BIT(19) -+#define SPIFIFOSTAT_RXEMPTY BIT(18) -+#define SPIFIFOSTAT_TXFULL BIT(17) -+#define SPIFIFOSTAT_RXFULL BIT(16) -+#define SPIFIFOSTAT_FIFO_MASK 0xff -+#define SPIFIFOSTAT_TX_OFFSET 8 -+#define SPIFIFOSTAT_RX_OFFSET 0 -+ -+#define SPI_FIFO_DEPTH 16 -+ -+/* SPIMODE register bit field */ -+#define SPIMODE_MODE_OFFSET 24 -+#define SPIMODE_DUMMY_OFFSET 0 -+ -+/* SPIARB register bit field */ -+#define SPICTL_ARB_EN BIT(31) -+#define SPICTL_CSCTL1 BIT(16) -+#define SPI1_POR BIT(1) -+#define SPI0_POR BIT(0) -+ -+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \ -+ SPI_CS_HIGH) -+ -+static atomic_t hw_reset_count = ATOMIC_INIT(0); -+ -+struct rt2880_spi { -+ struct spi_master *master; -+ void __iomem *base; -+ u32 speed; -+ u16 wait_loops; -+ u16 mode; -+ struct clk *clk; -+}; -+ -+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg) -+{ -+ return ioread32(rs->base + reg); -+} -+ -+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, -+ const u32 val) -+{ -+ iowrite32(val, rs->base + reg); -+} -+ -+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask) -+{ -+ void __iomem *addr = rs->base + reg; -+ -+ iowrite32((ioread32(addr) | mask), addr); -+} -+ -+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask) -+{ -+ void __iomem *addr = rs->base + reg; -+ -+ iowrite32((ioread32(addr) & ~mask), addr); -+} -+ -+static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed) -+{ -+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi); -+ u32 rate; -+ u32 prescale; -+ -+ /* -+ * the supported rates are: 2, 4, 8, ... 128 -+ * round up as we look for equal or less speed -+ */ -+ rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed); -+ rate = roundup_pow_of_two(rate); -+ -+ /* Convert the rate to SPI clock divisor value. */ -+ prescale = ilog2(rate / 2); -+ -+ /* some tolerance. double and add 100 */ -+ rs->wait_loops = (8 * HZ * loops_per_jiffy) / -+ (clk_get_rate(rs->clk) / rate); -+ rs->wait_loops = (rs->wait_loops << 1) + 100; -+ rs->speed = speed; -+ -+ dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n", -+ clk_get_rate(rs->clk) / rate, speed, rate, prescale, -+ rs->wait_loops); -+ -+ return prescale; -+} -+ -+static u32 get_arbiter_offset(struct spi_master *master) -+{ -+ u32 offset; -+ -+ offset = RAMIPS_SPI_ARBITER; -+ if (master->bus_num == 1) -+ offset -= RAMIPS_SPI_DEV_OFFSET; -+ -+ return offset; -+} -+ -+static void rt2880_spi_set_cs(struct spi_device *spi, bool enable) -+{ -+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi); -+ -+ if (enable) -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); -+ else -+ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); -+} -+ -+static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len) -+{ -+ int loop = rs->wait_loops * len; -+ -+ while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop) -+ cpu_relax(); -+ -+ if (loop) -+ return 0; -+ -+ return -ETIMEDOUT; -+} -+ -+static void rt2880_dump_reg(struct spi_master *master) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ -+ dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \ -+ "data: %08x, arb: %08x\n", -+ rt2880_spi_read(rs, RAMIPS_SPI_STAT), -+ rt2880_spi_read(rs, RAMIPS_SPI_CFG), -+ rt2880_spi_read(rs, RAMIPS_SPI_CTL), -+ rt2880_spi_read(rs, RAMIPS_SPI_DATA), -+ rt2880_spi_read(rs, get_arbiter_offset(master))); -+} -+ -+static int rt2880_spi_transfer_one(struct spi_master *master, -+ struct spi_device *spi, struct spi_transfer *xfer) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ unsigned len; -+ const u8 *tx = xfer->tx_buf; -+ u8 *rx = xfer->rx_buf; -+ int err = 0; -+ -+ /* change clock speed */ -+ if (unlikely(rs->speed != xfer->speed_hz)) { -+ u32 reg; -+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG); -+ reg &= ~SPICFG_SPICLK_PRESCALE_MASK; -+ reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz); -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg); -+ } -+ -+ if (tx) { -+ len = xfer->len; -+ while (len-- > 0) { -+ rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++); -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR); -+ err = rt2880_spi_wait_ready(rs, 1); -+ if (err) { -+ dev_err(&spi->dev, "TX failed, err=%d\n", err); -+ goto out; -+ } -+ } -+ } -+ -+ if (rx) { -+ len = xfer->len; -+ while (len-- > 0) { -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD); -+ err = rt2880_spi_wait_ready(rs, 1); -+ if (err) { -+ dev_err(&spi->dev, "RX failed, err=%d\n", err); -+ goto out; -+ } -+ *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA); -+ } -+ } -+ -+out: -+ return err; -+} -+ -+/* copy from spi.c */ -+static void spi_set_cs(struct spi_device *spi, bool enable) -+{ -+ if (spi->mode & SPI_CS_HIGH) -+ enable = !enable; -+ -+ if (spi->cs_gpio >= 0) -+ gpio_set_value(spi->cs_gpio, !enable); -+ else if (spi->master->set_cs) -+ spi->master->set_cs(spi, !enable); -+} -+ -+static int rt2880_spi_setup(struct spi_device *spi) -+{ -+ struct spi_master *master = spi->master; -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ u32 reg, old_reg, arbit_off; -+ -+ if ((spi->max_speed_hz > master->max_speed_hz) || -+ (spi->max_speed_hz < master->min_speed_hz)) { -+ dev_err(&spi->dev, "invalide requested speed %d Hz\n", -+ spi->max_speed_hz); -+ return -EINVAL; -+ } -+ -+ if (!(master->bits_per_word_mask & -+ BIT(spi->bits_per_word - 1))) { -+ dev_err(&spi->dev, "invalide bits_per_word %d\n", -+ spi->bits_per_word); -+ return -EINVAL; -+ } -+ -+ /* the hardware seems can't work on mode0 force it to mode3 */ -+ if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) { -+ dev_warn(&spi->dev, "force spi mode3\n"); -+ spi->mode |= SPI_MODE_3; -+ } -+ -+ /* chip polarity */ -+ arbit_off = get_arbiter_offset(master); -+ reg = old_reg = rt2880_spi_read(rs, arbit_off); -+ if (spi->mode & SPI_CS_HIGH) { -+ switch (master->bus_num) { -+ case 1: -+ reg |= SPI1_POR; -+ break; -+ default: -+ reg |= SPI0_POR; -+ break; -+ } -+ } else { -+ switch (master->bus_num) { -+ case 1: -+ reg &= ~SPI1_POR; -+ break; -+ default: -+ reg &= ~SPI0_POR; -+ break; -+ } -+ } -+ -+ /* enable spi1 */ -+ if (master->bus_num == 1) -+ reg |= SPICTL_ARB_EN; -+ -+ if (reg != old_reg) -+ rt2880_spi_write(rs, arbit_off, reg); -+ -+ /* deselected the spi device */ -+ spi_set_cs(spi, false); -+ -+ rt2880_dump_reg(master); -+ -+ return 0; -+} -+ -+static int rt2880_spi_prepare_message(struct spi_master *master, -+ struct spi_message *msg) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ struct spi_device *spi = msg->spi; -+ u32 reg; -+ -+ if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz)) -+ return 0; -+ -+#if 0 -+ /* set spido to tri-state */ -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO); -+#endif -+ -+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG); -+ -+ reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL | -+ SPICFG_RXCLKEDGE_FALLING | -+ SPICFG_TXCLKEDGE_FALLING | -+ SPICFG_SPICLK_PRESCALE_MASK); -+ -+ /* MSB */ -+ if (!(spi->mode & SPI_LSB_FIRST)) -+ reg |= SPICFG_MSBFIRST; -+ -+ /* spi mode */ -+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { -+ case SPI_MODE_0: -+ reg |= SPICFG_TXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_1: -+ reg |= SPICFG_RXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_2: -+ reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_3: -+ reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING; -+ break; -+ } -+ rs->mode = spi->mode; -+ -+#if 0 -+ /* set spiclk and spiena to tri-state */ -+ reg |= SPICFG_HIZSPI; -+#endif -+ -+ /* clock divide */ -+ reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz); -+ -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg); -+ -+ return 0; -+} -+ -+static int rt2880_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct rt2880_spi *rs; -+ void __iomem *base; -+ struct resource *r; -+ struct clk *clk; -+ int ret; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, r); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "unable to get SYS clock\n"); -+ return PTR_ERR(clk); -+ } -+ -+ ret = clk_prepare_enable(clk); -+ if (ret) -+ goto err_clk; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*rs)); -+ if (master == NULL) { -+ dev_dbg(&pdev->dev, "master allocation failed\n"); -+ ret = -ENOMEM; -+ goto err_clk; -+ } -+ -+ master->dev.of_node = pdev->dev.of_node; -+ master->mode_bits = RT2880_SPI_MODE_BITS; -+ master->bits_per_word_mask = SPI_BPW_MASK(8); -+ master->min_speed_hz = clk_get_rate(clk) / 128; -+ master->max_speed_hz = clk_get_rate(clk) / 2; -+ master->flags = SPI_MASTER_HALF_DUPLEX; -+ master->setup = rt2880_spi_setup; -+ master->prepare_message = rt2880_spi_prepare_message; -+ master->set_cs = rt2880_spi_set_cs; -+ master->transfer_one = rt2880_spi_transfer_one, -+ -+ dev_set_drvdata(&pdev->dev, master); -+ -+ rs = spi_master_get_devdata(master); -+ rs->master = master; -+ rs->base = base; -+ rs->clk = clk; -+ -+ if (atomic_inc_return(&hw_reset_count) == 1) -+ device_reset(&pdev->dev); -+ -+ ret = devm_spi_register_master(&pdev->dev, master); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "devm_spi_register_master error.\n"); -+ goto err_master; -+ } -+ -+ return ret; -+ -+err_master: -+ spi_master_put(master); -+ kfree(master); -+err_clk: -+ clk_disable_unprepare(clk); -+ -+ return ret; -+} -+ -+static int rt2880_spi_remove(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct rt2880_spi *rs; -+ -+ master = dev_get_drvdata(&pdev->dev); -+ rs = spi_master_get_devdata(master); -+ -+ clk_disable_unprepare(rs->clk); -+ atomic_dec(&hw_reset_count); -+ -+ return 0; -+} -+ -+MODULE_ALIAS("platform:" DRIVER_NAME); -+ -+static const struct of_device_id rt2880_spi_match[] = { -+ { .compatible = "ralink,rt2880-spi" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, rt2880_spi_match); -+ -+static struct platform_driver rt2880_spi_driver = { -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = rt2880_spi_match, -+ }, -+ .probe = rt2880_spi_probe, -+ .remove = rt2880_spi_remove, -+}; -+ -+module_platform_driver(rt2880_spi_driver); -+ -+MODULE_DESCRIPTION("Ralink SPI driver"); -+MODULE_AUTHOR("Sergiy "); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ramips/patches-5.4/0044-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-5.4/0044-i2c-MIPS-adds-ralink-I2C-driver.patch deleted file mode 100644 index e3bb7f2488..0000000000 --- a/target/linux/ramips/patches-5.4/0044-i2c-MIPS-adds-ralink-I2C-driver.patch +++ /dev/null @@ -1,507 +0,0 @@ -From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:52:56 +0100 -Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++ - drivers/i2c/busses/Kconfig | 4 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++ - 4 files changed, 359 insertions(+) - create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt - create mode 100644 drivers/i2c/busses/i2c-ralink.c - ---- /dev/null -+++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt -@@ -0,0 +1,27 @@ -+I2C for Ralink platforms -+ -+Required properties : -+- compatible : Must be "link,rt3052-i2c" -+- reg: physical base address of the controller and length of memory mapped -+ region. -+- #address-cells = <1>; -+- #size-cells = <0>; -+ -+Optional properties: -+- Child nodes conforming to i2c bus binding -+ -+Example : -+ -+palmbus@10000000 { -+ i2c@900 { -+ compatible = "link,rt3052-i2c"; -+ reg = <0x900 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hwmon@4b { -+ compatible = "national,lm92"; -+ reg = <0x4b>; -+ }; -+ }; -+}; ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -922,6 +922,11 @@ config I2C_RK3X - This driver can also be built as a module. If so, the module will - be called i2c-rk3x. - -+config I2C_RALINK -+ tristate "Ralink I2C Controller" -+ depends on RALINK && !SOC_MT7621 -+ select OF_I2C -+ - config HAVE_S3C2410_I2C - bool - help ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -91,6 +91,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o - obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o - obj-$(CONFIG_I2C_PXA) += i2c-pxa.o - obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o -+obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o - obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o - obj-$(CONFIG_I2C_QUP) += i2c-qup.o - obj-$(CONFIG_I2C_RIIC) += i2c-riic.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-ralink.c -@@ -0,0 +1,435 @@ -+/* -+ * drivers/i2c/busses/i2c-ralink.c -+ * -+ * Copyright (C) 2013 Steven Liu -+ * Copyright (C) 2016 Michael Lee -+ * -+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus. -+ * (C) 2014 Sittisak -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define REG_CONFIG_REG 0x00 -+#define REG_CLKDIV_REG 0x04 -+#define REG_DEVADDR_REG 0x08 -+#define REG_ADDR_REG 0x0C -+#define REG_DATAOUT_REG 0x10 -+#define REG_DATAIN_REG 0x14 -+#define REG_STATUS_REG 0x18 -+#define REG_STARTXFR_REG 0x1C -+#define REG_BYTECNT_REG 0x20 -+ -+/* REG_CONFIG_REG */ -+#define I2C_ADDRLEN_OFFSET 5 -+#define I2C_DEVADLEN_OFFSET 2 -+#define I2C_ADDRLEN_MASK 0x3 -+#define I2C_ADDR_DIS BIT(1) -+#define I2C_DEVADDR_DIS BIT(0) -+#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET) -+#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET) -+#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7) -+ -+/* REG_CLKDIV_REG */ -+#define I2C_CLKDIV_MASK 0xffff -+ -+/* REG_DEVADDR_REG */ -+#define I2C_DEVADDR_MASK 0x7f -+ -+/* REG_ADDR_REG */ -+#define I2C_ADDR_MASK 0xff -+ -+/* REG_STATUS_REG */ -+#define I2C_STARTERR BIT(4) -+#define I2C_ACKERR BIT(3) -+#define I2C_DATARDY BIT(2) -+#define I2C_SDOEMPTY BIT(1) -+#define I2C_BUSY BIT(0) -+ -+/* REG_STARTXFR_REG */ -+#define NOSTOP_CMD BIT(2) -+#define NODATA_CMD BIT(1) -+#define READ_CMD BIT(0) -+ -+/* REG_BYTECNT_REG */ -+#define BYTECNT_MAX 64 -+#define SET_BYTECNT(x) (x - 1) -+ -+/* timeout waiting for I2C devices to respond (clock streching) */ -+#define TIMEOUT_MS 1000 -+#define DELAY_INTERVAL_US 100 -+ -+struct rt_i2c { -+ void __iomem *base; -+ struct clk *clk; -+ struct device *dev; -+ struct i2c_adapter adap; -+ u32 cur_clk; -+ u32 clk_div; -+ u32 flags; -+}; -+ -+static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg) -+{ -+ iowrite32(val, i2c->base + reg); -+} -+ -+static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg) -+{ -+ return ioread32(i2c->base + reg); -+} -+ -+static int poll_down_timeout(void __iomem *addr, u32 mask) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); -+ -+ do { -+ if (!(readl_relaxed(addr) & mask)) -+ return 0; -+ -+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); -+ } while (time_before(jiffies, timeout)); -+ -+ return (readl_relaxed(addr) & mask) ? -EAGAIN : 0; -+} -+ -+static int rt_i2c_wait_idle(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "idle err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static int poll_up_timeout(void __iomem *addr, u32 mask) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); -+ u32 status; -+ -+ do { -+ status = readl_relaxed(addr); -+ -+ /* check error status */ -+ if (status & I2C_STARTERR) -+ return -EAGAIN; -+ else if (status & I2C_ACKERR) -+ return -ENXIO; -+ else if (status & mask) -+ return 0; -+ -+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); -+ } while (time_before(jiffies, timeout)); -+ -+ return -ETIMEDOUT; -+} -+ -+static int rt_i2c_wait_rx_done(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "rx err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static int rt_i2c_wait_tx_done(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "tx err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static void rt_i2c_reset(struct rt_i2c *i2c) -+{ -+ device_reset(i2c->adap.dev.parent); -+ barrier(); -+ rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG); -+} -+ -+static void rt_i2c_dump_reg(struct rt_i2c *i2c) -+{ -+ dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \ -+ "addr %08x, dataout %08x, datain %08x, " \ -+ "status %08x, startxfr %08x, bytecnt %08x\n", -+ rt_i2c_r32(i2c, REG_CONFIG_REG), -+ rt_i2c_r32(i2c, REG_CLKDIV_REG), -+ rt_i2c_r32(i2c, REG_DEVADDR_REG), -+ rt_i2c_r32(i2c, REG_ADDR_REG), -+ rt_i2c_r32(i2c, REG_DATAOUT_REG), -+ rt_i2c_r32(i2c, REG_DATAIN_REG), -+ rt_i2c_r32(i2c, REG_STATUS_REG), -+ rt_i2c_r32(i2c, REG_STARTXFR_REG), -+ rt_i2c_r32(i2c, REG_BYTECNT_REG)); -+} -+ -+static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, -+ int num) -+{ -+ struct rt_i2c *i2c; -+ struct i2c_msg *pmsg; -+ unsigned char addr; -+ int i, j, ret; -+ u32 cmd; -+ -+ i2c = i2c_get_adapdata(adap); -+ -+ for (i = 0; i < num; i++) { -+ pmsg = &msgs[i]; -+ if (i == (num - 1)) -+ cmd = 0; -+ else -+ cmd = NOSTOP_CMD; -+ -+ dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n", -+ pmsg->addr, pmsg->len, pmsg->flags, -+ (cmd == 0)? 1 : 0); -+ -+ /* wait hardware idle */ -+ if ((ret = rt_i2c_wait_idle(i2c))) -+ goto err_timeout; -+ -+ if (pmsg->flags & I2C_M_TEN) { -+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG); -+ /* 10 bits address */ -+ addr = 0x78 | ((pmsg->addr >> 8) & 0x03); -+ rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK, -+ REG_DEVADDR_REG); -+ rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK, -+ REG_ADDR_REG); -+ } else { -+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS, -+ REG_CONFIG_REG); -+ /* 7 bits address */ -+ rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK, -+ REG_DEVADDR_REG); -+ } -+ -+ /* buffer length */ -+ if (pmsg->len == 0) -+ cmd |= NODATA_CMD; -+ else -+ rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len), -+ REG_BYTECNT_REG); -+ -+ j = 0; -+ if (pmsg->flags & I2C_M_RD) { -+ cmd |= READ_CMD; -+ /* start transfer */ -+ barrier(); -+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG); -+ do { -+ /* wait */ -+ if ((ret = rt_i2c_wait_rx_done(i2c))) -+ goto err_timeout; -+ /* read data */ -+ if (pmsg->len) -+ pmsg->buf[j] = rt_i2c_r32(i2c, -+ REG_DATAIN_REG); -+ j++; -+ } while (j < pmsg->len); -+ } else { -+ do { -+ /* write data */ -+ if (pmsg->len) -+ rt_i2c_w32(i2c, pmsg->buf[j], -+ REG_DATAOUT_REG); -+ /* start transfer */ -+ if (j == 0) { -+ barrier(); -+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG); -+ } -+ /* wait */ -+ if ((ret = rt_i2c_wait_tx_done(i2c))) -+ goto err_timeout; -+ j++; -+ } while (j < pmsg->len); -+ } -+ } -+ /* the return value is number of executed messages */ -+ ret = i; -+ -+ return ret; -+ -+err_timeout: -+ rt_i2c_dump_reg(i2c); -+ rt_i2c_reset(i2c); -+ return ret; -+} -+ -+static u32 rt_i2c_func(struct i2c_adapter *a) -+{ -+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -+} -+ -+static const struct i2c_algorithm rt_i2c_algo = { -+ .master_xfer = rt_i2c_master_xfer, -+ .functionality = rt_i2c_func, -+}; -+ -+static const struct of_device_id i2c_rt_dt_ids[] = { -+ { .compatible = "ralink,rt2880-i2c" }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids); -+ -+static struct i2c_adapter_quirks rt_i2c_quirks = { -+ .max_write_len = BYTECNT_MAX, -+ .max_read_len = BYTECNT_MAX, -+}; -+ -+static int rt_i2c_init(struct rt_i2c *i2c) -+{ -+ u32 reg; -+ -+ /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */ -+ i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) / -+ (2 * i2c->cur_clk); -+ if (i2c->clk_div < 8) -+ i2c->clk_div = 8; -+ if (i2c->clk_div > I2C_CLKDIV_MASK) -+ i2c->clk_div = I2C_CLKDIV_MASK; -+ -+ /* check support combinde/repeated start message */ -+ rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG); -+ reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD; -+ -+ rt_i2c_reset(i2c); -+ -+ return reg; -+} -+ -+static int rt_i2c_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ struct rt_i2c *i2c; -+ struct i2c_adapter *adap; -+ const struct of_device_id *match; -+ int ret, restart; -+ -+ match = of_match_device(i2c_rt_dt_ids, &pdev->dev); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no memory resource found\n"); -+ return -ENODEV; -+ } -+ -+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL); -+ if (!i2c) { -+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n"); -+ return -ENOMEM; -+ } -+ -+ i2c->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(i2c->base)) -+ return PTR_ERR(i2c->base); -+ -+ i2c->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(i2c->clk)) { -+ dev_err(&pdev->dev, "no clock defined\n"); -+ return -ENODEV; -+ } -+ clk_prepare_enable(i2c->clk); -+ i2c->dev = &pdev->dev; -+ -+ if (of_property_read_u32(pdev->dev.of_node, -+ "clock-frequency", &i2c->cur_clk)) -+ i2c->cur_clk = 100000; -+ -+ adap = &i2c->adap; -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; -+ adap->algo = &rt_i2c_algo; -+ adap->retries = 3; -+ adap->dev.parent = &pdev->dev; -+ i2c_set_adapdata(adap, i2c); -+ adap->dev.of_node = pdev->dev.of_node; -+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); -+ adap->quirks = &rt_i2c_quirks; -+ -+ platform_set_drvdata(pdev, i2c); -+ -+ restart = rt_i2c_init(i2c); -+ -+ ret = i2c_add_adapter(adap); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to add adapter\n"); -+ clk_disable_unprepare(i2c->clk); -+ return ret; -+ } -+ -+ dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n", -+ i2c->cur_clk/1000, restart ? "" : "not "); -+ -+ return ret; -+} -+ -+static int rt_i2c_remove(struct platform_device *pdev) -+{ -+ struct rt_i2c *i2c = platform_get_drvdata(pdev); -+ -+ i2c_del_adapter(&i2c->adap); -+ clk_disable_unprepare(i2c->clk); -+ -+ return 0; -+} -+ -+static struct platform_driver rt_i2c_driver = { -+ .probe = rt_i2c_probe, -+ .remove = rt_i2c_remove, -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "i2c-ralink", -+ .of_match_table = i2c_rt_dt_ids, -+ }, -+}; -+ -+static int __init i2c_rt_init (void) -+{ -+ return platform_driver_register(&rt_i2c_driver); -+} -+subsys_initcall(i2c_rt_init); -+ -+static void __exit i2c_rt_exit (void) -+{ -+ platform_driver_unregister(&rt_i2c_driver); -+} -+module_exit(i2c_rt_exit); -+ -+MODULE_AUTHOR("Steven Liu "); -+MODULE_DESCRIPTION("Ralink I2c host driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:Ralink-I2C"); diff --git a/target/linux/ramips/patches-5.4/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.4/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch deleted file mode 100644 index f3912a1054..0000000000 --- a/target/linux/ramips/patches-5.4/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 13 Nov 2014 19:08:40 +0100 -Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC - -Signed-off-by: John Crispin ---- - drivers/mmc/host/Kconfig | 2 + - drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/mtk-mmc/Kconfig | 16 + - drivers/mmc/host/mtk-mmc/Makefile | 42 + - drivers/mmc/host/mtk-mmc/board.h | 137 ++ - drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++ - drivers/mmc/host/mtk-mmc/dbg.h | 156 ++ - drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++ - drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++ - 9 files changed, 4762 insertions(+) - create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig - create mode 100644 drivers/mmc/host/mtk-mmc/Makefile - create mode 100644 drivers/mmc/host/mtk-mmc/board.h - create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c - create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h - create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h - create mode 100644 drivers/mmc/host/mtk-mmc/sd.c - ---- a/drivers/mmc/host/Kconfig -+++ b/drivers/mmc/host/Kconfig -@@ -1019,3 +1019,5 @@ config MMC_SDHCI_AM654 - If you have a controller with this interface, say Y or M here. - - If unsure, say N. -+ -+source "drivers/mmc/host/mtk-mmc/Kconfig" ---- a/drivers/mmc/host/Makefile -+++ b/drivers/mmc/host/Makefile -@@ -3,6 +3,7 @@ - # Makefile for MMC/SD host controller drivers - # - -+obj-$(CONFIG_MTK_MMC) += mtk-mmc/ - obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o - armmmci-y := mmci.o - armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o diff --git a/target/linux/ramips/patches-5.4/0048-asoc-add-mt7620-support.patch b/target/linux/ramips/patches-5.4/0048-asoc-add-mt7620-support.patch deleted file mode 100644 index 4b9c877a7f..0000000000 --- a/target/linux/ramips/patches-5.4/0048-asoc-add-mt7620-support.patch +++ /dev/null @@ -1,1028 +0,0 @@ -From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:31:47 +0100 -Subject: [PATCH 48/53] asoc: add mt7620 support - -Signed-off-by: John Crispin ---- - arch/mips/ralink/of.c | 2 + - sound/soc/Kconfig | 1 + - sound/soc/Makefile | 1 + - sound/soc/ralink/Kconfig | 15 ++ - sound/soc/ralink/Makefile | 11 + - sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++ - sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++ - 7 files changed, 699 insertions(+) - create mode 100644 sound/soc/ralink/Kconfig - create mode 100644 sound/soc/ralink/Makefile - create mode 100644 sound/soc/ralink/mt7620-i2s.c - create mode 100644 sound/soc/ralink/mt7620-wm8960.c - ---- a/sound/soc/Kconfig -+++ b/sound/soc/Kconfig -@@ -60,6 +60,7 @@ source "sound/soc/mxs/Kconfig" - source "sound/soc/pxa/Kconfig" - source "sound/soc/qcom/Kconfig" - source "sound/soc/rockchip/Kconfig" -+source "sound/soc/ralink/Kconfig" - source "sound/soc/samsung/Kconfig" - source "sound/soc/sh/Kconfig" - source "sound/soc/sirf/Kconfig" ---- a/sound/soc/Makefile -+++ b/sound/soc/Makefile -@@ -43,6 +43,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/ - obj-$(CONFIG_SND_SOC) += pxa/ - obj-$(CONFIG_SND_SOC) += qcom/ - obj-$(CONFIG_SND_SOC) += rockchip/ -+obj-$(CONFIG_SND_SOC) += ralink/ - obj-$(CONFIG_SND_SOC) += samsung/ - obj-$(CONFIG_SND_SOC) += sh/ - obj-$(CONFIG_SND_SOC) += sirf/ ---- /dev/null -+++ b/sound/soc/ralink/Kconfig -@@ -0,0 +1,8 @@ -+config SND_RALINK_SOC_I2S -+ depends on RALINK && SND_SOC && !SOC_RT288X -+ select SND_SOC_GENERIC_DMAENGINE_PCM -+ select REGMAP_MMIO -+ tristate "SoC Audio (I2S protocol) for Ralink SoC" -+ help -+ Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek -+ based boards. ---- /dev/null -+++ b/sound/soc/ralink/Makefile -@@ -0,0 +1,6 @@ -+# -+# Ralink/MediaTek Platform Support -+# -+snd-soc-ralink-i2s-objs := ralink-i2s.o -+ -+obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o ---- /dev/null -+++ b/sound/soc/ralink/ralink-i2s.c -@@ -0,0 +1,965 @@ -+/* -+ * Copyright (C) 2010, Lars-Peter Clausen -+ * Copyright (C) 2016 Michael Lee -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "ralink-i2s" -+ -+#define I2S_REG_CFG0 0x00 -+#define I2S_REG_INT_STATUS 0x04 -+#define I2S_REG_INT_EN 0x08 -+#define I2S_REG_FF_STATUS 0x0c -+#define I2S_REG_WREG 0x10 -+#define I2S_REG_RREG 0x14 -+#define I2S_REG_CFG1 0x18 -+#define I2S_REG_DIVCMP 0x20 -+#define I2S_REG_DIVINT 0x24 -+ -+/* I2S_REG_CFG0 */ -+#define I2S_REG_CFG0_EN BIT(31) -+#define I2S_REG_CFG0_DMA_EN BIT(30) -+#define I2S_REG_CFG0_BYTE_SWAP BIT(28) -+#define I2S_REG_CFG0_TX_EN BIT(24) -+#define I2S_REG_CFG0_RX_EN BIT(20) -+#define I2S_REG_CFG0_SLAVE BIT(16) -+#define I2S_REG_CFG0_RX_THRES 12 -+#define I2S_REG_CFG0_TX_THRES 4 -+#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \ -+ (4 << I2S_REG_CFG0_TX_THRES) -+#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \ -+ (4 << I2S_REG_CFG0_TX_THRES) -+/* RT305x */ -+#define I2S_REG_CFG0_CLK_DIS BIT(8) -+#define I2S_REG_CFG0_TXCH_SWAP BIT(3) -+#define I2S_REG_CFG0_TXCH1_OFF BIT(2) -+#define I2S_REG_CFG0_TXCH0_OFF BIT(1) -+#define I2S_REG_CFG0_SLAVE_EN BIT(0) -+/* RT3883 */ -+#define I2S_REG_CFG0_RXCH_SWAP BIT(11) -+#define I2S_REG_CFG0_RXCH1_OFF BIT(10) -+#define I2S_REG_CFG0_RXCH0_OFF BIT(9) -+#define I2S_REG_CFG0_WS_INV BIT(0) -+/* MT7628 */ -+#define I2S_REG_CFG0_FMT_LE BIT(29) -+#define I2S_REG_CFG0_SYS_BE BIT(28) -+#define I2S_REG_CFG0_NORM_24 BIT(18) -+#define I2S_REG_CFG0_DATA_24 BIT(17) -+ -+/* I2S_REG_INT_STATUS */ -+#define I2S_REG_INT_RX_FAULT BIT(7) -+#define I2S_REG_INT_RX_OVRUN BIT(6) -+#define I2S_REG_INT_RX_UNRUN BIT(5) -+#define I2S_REG_INT_RX_THRES BIT(4) -+#define I2S_REG_INT_TX_FAULT BIT(3) -+#define I2S_REG_INT_TX_OVRUN BIT(2) -+#define I2S_REG_INT_TX_UNRUN BIT(1) -+#define I2S_REG_INT_TX_THRES BIT(0) -+#define I2S_REG_INT_TX_MASK 0xf -+#define I2S_REG_INT_RX_MASK 0xf0 -+ -+/* I2S_REG_INT_STATUS */ -+#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf) -+#define I2S_TX_AVCNT(x) (x & 0xf) -+/* MT7628 */ -+#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f) -+#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f) -+ -+/* I2S_REG_CFG1 */ -+#define I2S_REG_CFG1_LBK BIT(31) -+#define I2S_REG_CFG1_EXTLBK BIT(30) -+/* RT3883 */ -+#define I2S_REG_CFG1_LEFT_J BIT(0) -+#define I2S_REG_CFG1_RIGHT_J BIT(1) -+#define I2S_REG_CFG1_FMT_MASK 0x3 -+ -+/* I2S_REG_DIVCMP */ -+#define I2S_REG_DIVCMP_CLKEN BIT(31) -+#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff -+ -+/* I2S_REG_DIVINT */ -+#define I2S_REG_DIVINT_MASK 0x3ff -+ -+/* BCLK dividers */ -+#define RALINK_I2S_DIVCMP 0 -+#define RALINK_I2S_DIVINT 1 -+ -+/* FIFO */ -+#define RALINK_I2S_FIFO_SIZE 32 -+ -+/* feature flags */ -+#define RALINK_FLAGS_TXONLY BIT(0) -+#define RALINK_FLAGS_LEFT_J BIT(1) -+#define RALINK_FLAGS_RIGHT_J BIT(2) -+#define RALINK_FLAGS_ENDIAN BIT(3) -+#define RALINK_FLAGS_24BIT BIT(4) -+ -+#define RALINK_I2S_INT_EN 0 -+ -+struct ralink_i2s_stats { -+ u32 dmafault; -+ u32 overrun; -+ u32 underrun; -+ u32 belowthres; -+}; -+ -+struct ralink_i2s { -+ struct device *dev; -+ void __iomem *regs; -+ struct clk *clk; -+ struct regmap *regmap; -+ u32 flags; -+ unsigned int fmt; -+ u16 txdma_req; -+ u16 rxdma_req; -+ -+ struct snd_dmaengine_dai_dma_data playback_dma_data; -+ struct snd_dmaengine_dai_dma_data capture_dma_data; -+ -+ struct dentry *dbg_dir; -+ struct dentry *dbg_stats; -+ struct ralink_i2s_stats txstats; -+ struct ralink_i2s_stats rxstats; -+}; -+ -+static void ralink_i2s_dump_regs(struct ralink_i2s *i2s) -+{ -+ u32 buf[10]; -+ int ret; -+ -+ ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0, -+ buf, ARRAY_SIZE(buf)); -+ -+ dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \ -+ "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \ -+ "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n", -+ buf[0], buf[1], buf[2], buf[3], buf[4], -+ buf[5], buf[6], buf[8], buf[9]); -+} -+ -+static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai, -+ int clk_id, unsigned int freq, int dir) -+{ -+ return 0; -+} -+ -+static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned long clk = clk_get_rate(i2s->clk); -+ int div; -+ uint32_t data; -+ -+ /* disable clock at slave mode */ -+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) == -+ SND_SOC_DAIFMT_CBM_CFM) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_CLK_DIS, -+ I2S_REG_CFG0_CLK_DIS); -+ return 0; -+ } -+ -+ /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */ -+ div = (clk / rate ) - 1; -+ -+ data = rt_sysc_r32(0x30); -+ data &= (0xff << 8); -+ data |= (0x1 << 15) | (div << 8); -+ rt_sysc_w32(data, 0x30); -+ -+ /* enable clock */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0); -+ -+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n", -+ clk, rate, div); -+ -+ return 0; -+} -+ -+static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned long clk = clk_get_rate(i2s->clk); -+ int divint, divcomp; -+ -+ /* disable clock at slave mode */ -+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) == -+ SND_SOC_DAIFMT_CBM_CFM) { -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, -+ I2S_REG_DIVCMP_CLKEN, 0); -+ return 0; -+ } -+ -+ /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */ -+ clk = clk / (2 * 2 * width); -+ divint = clk / rate; -+ divcomp = ((clk % rate) * 512) / rate; -+ -+ if ((divint > I2S_REG_DIVINT_MASK) || -+ (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK)) -+ return -EINVAL; -+ -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVINT, -+ I2S_REG_DIVINT_MASK, divint); -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, -+ I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp); -+ -+ /* enable clock */ -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN, -+ I2S_REG_DIVCMP_CLKEN); -+ -+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n", -+ clk_get_rate(i2s->clk), rate, divint, divcomp); -+ -+ return 0; -+} -+ -+static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int cfg0 = 0, cfg1 = 0; -+ -+ /* set master/slave audio interface */ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBM_CFM: -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ cfg0 |= I2S_REG_CFG0_SLAVE_EN; -+ else -+ cfg0 |= I2S_REG_CFG0_SLAVE; -+ break; -+ case SND_SOC_DAIFMT_CBS_CFS: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* interface format */ -+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ break; -+ case SND_SOC_DAIFMT_RIGHT_J: -+ if (i2s->flags & RALINK_FLAGS_RIGHT_J) { -+ cfg1 |= I2S_REG_CFG1_RIGHT_J; -+ break; -+ } -+ return -EINVAL; -+ case SND_SOC_DAIFMT_LEFT_J: -+ if (i2s->flags & RALINK_FLAGS_LEFT_J) { -+ cfg1 |= I2S_REG_CFG1_LEFT_J; -+ break; -+ } -+ return -EINVAL; -+ default: -+ return -EINVAL; -+ } -+ -+ /* clock inversion */ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_NB_NF: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SLAVE_EN, cfg0); -+ } else { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SLAVE, cfg0); -+ } -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG1, -+ I2S_REG_CFG1_FMT_MASK, cfg1); -+ i2s->fmt = fmt; -+ -+ return 0; -+} -+ -+static int ralink_i2s_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ if (dai->active) -+ return 0; -+ -+ /* setup status interrupt */ -+#if (RALINK_I2S_INT_EN) -+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff); -+#else -+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0); -+#endif -+ -+ /* enable */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN | -+ I2S_REG_CFG0_THRES_MASK, -+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN | -+ I2S_REG_CFG0_DFT_THRES); -+ -+ return 0; -+} -+ -+static void ralink_i2s_shutdown(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ /* If both streams are stopped, disable module and clock */ -+ if (dai->active) -+ return; -+ -+ /* -+ * datasheet mention when disable all control regs are cleared -+ * to initial values. need reinit at startup. -+ */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0); -+} -+ -+static int ralink_i2s_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ int width; -+ int ret; -+ -+ width = params_width(params); -+ switch (width) { -+ case 16: -+ if (i2s->flags & RALINK_FLAGS_24BIT) -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_DATA_24, 0); -+ break; -+ case 24: -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_DATA_24, -+ I2S_REG_CFG0_DATA_24); -+ break; -+ } -+ return -EINVAL; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (params_channels(params)) { -+ case 2: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (i2s->flags & RALINK_FLAGS_ENDIAN) { -+ /* system endian */ -+#ifdef SNDRV_LITTLE_ENDIAN -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SYS_BE, 0); -+#else -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SYS_BE, -+ I2S_REG_CFG0_SYS_BE); -+#endif -+ -+ /* data endian */ -+ switch (params_format(params)) { -+ case SNDRV_PCM_FORMAT_S16_LE: -+ case SNDRV_PCM_FORMAT_S24_LE: -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_FMT_LE, -+ I2S_REG_CFG0_FMT_LE); -+ break; -+ case SNDRV_PCM_FORMAT_S16_BE: -+ case SNDRV_PCM_FORMAT_S24_BE: -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_FMT_LE, 0); -+ break; -+ default: -+ return -EINVAL; -+ } -+ } -+ -+ /* setup bclk rate */ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params)); -+ else -+ ret = ralink_i2s_set_bclk(dai, width, params_rate(params)); -+ -+ return ret; -+} -+ -+static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int mask, val; -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ mask = I2S_REG_CFG0_TX_EN; -+ else -+ mask = I2S_REG_CFG0_RX_EN; -+ -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ case SNDRV_PCM_TRIGGER_RESUME: -+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: -+ val = mask; -+ break; -+ case SNDRV_PCM_TRIGGER_STOP: -+ case SNDRV_PCM_TRIGGER_SUSPEND: -+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: -+ val = 0; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val); -+ -+ return 0; -+} -+ -+static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s, -+ struct resource *res) -+{ -+ struct snd_dmaengine_dai_dma_data *dma_data; -+ -+ /* Playback */ -+ dma_data = &i2s->playback_dma_data; -+ dma_data->addr = res->start + I2S_REG_WREG; -+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ dma_data->maxburst = 1; -+ dma_data->slave_id = i2s->txdma_req; -+ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ return; -+ -+ /* Capture */ -+ dma_data = &i2s->capture_dma_data; -+ dma_data->addr = res->start + I2S_REG_RREG; -+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ dma_data->maxburst = 1; -+ dma_data->slave_id = i2s->rxdma_req; -+} -+ -+static int ralink_i2s_dai_probe(struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, -+ &i2s->capture_dma_data); -+ -+ return 0; -+} -+ -+static int ralink_i2s_dai_remove(struct snd_soc_dai *dai) -+{ -+ return 0; -+} -+ -+static const struct snd_soc_dai_ops ralink_i2s_dai_ops = { -+ .set_sysclk = ralink_i2s_set_sysclk, -+ .set_fmt = ralink_i2s_set_fmt, -+ .startup = ralink_i2s_startup, -+ .shutdown = ralink_i2s_shutdown, -+ .hw_params = ralink_i2s_hw_params, -+ .trigger = ralink_i2s_trigger, -+}; -+ -+static struct snd_soc_dai_driver ralink_i2s_dai = { -+ .name = DRV_NAME, -+ .probe = ralink_i2s_dai_probe, -+ .remove = ralink_i2s_dai_remove, -+ .ops = &ralink_i2s_dai_ops, -+ .capture = { -+ .stream_name = "I2S Capture", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rate_min = 5512, -+ .rate_max = 192000, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ }, -+ .playback = { -+ .stream_name = "I2S Playback", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rate_min = 5512, -+ .rate_max = 192000, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ }, -+ .symmetric_rates = 1, -+}; -+ -+static struct snd_pcm_hardware ralink_pcm_hardware = { -+ .info = SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_MMAP_VALID | -+ SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_BLOCK_TRANSFER, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ .channels_min = 2, -+ .channels_max = 2, -+ .period_bytes_min = PAGE_SIZE, -+ .period_bytes_max = PAGE_SIZE * 2, -+ .periods_min = 2, -+ .periods_max = 128, -+ .buffer_bytes_max = 128 * 1024, -+ .fifo_size = RALINK_I2S_FIFO_SIZE, -+}; -+ -+static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = { -+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, -+ .pcm_hardware = &ralink_pcm_hardware, -+ .prealloc_buffer_size = 256 * PAGE_SIZE, -+}; -+ -+static const struct snd_soc_component_driver ralink_i2s_component = { -+ .name = DRV_NAME, -+}; -+ -+static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg) -+{ -+ return true; -+} -+ -+static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case I2S_REG_INT_STATUS: -+ case I2S_REG_FF_STATUS: -+ return true; -+ } -+ return false; -+} -+ -+static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case I2S_REG_FF_STATUS: -+ case I2S_REG_RREG: -+ return false; -+ } -+ return true; -+} -+ -+static const struct regmap_config ralink_i2s_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .writeable_reg = ralink_i2s_writeable_reg, -+ .readable_reg = ralink_i2s_readable_reg, -+ .volatile_reg = ralink_i2s_volatile_reg, -+ .max_register = I2S_REG_DIVINT, -+}; -+ -+#if (RALINK_I2S_INT_EN) -+static irqreturn_t ralink_i2s_irq(int irq, void *devid) -+{ -+ struct ralink_i2s *i2s = devid; -+ u32 status; -+ -+ regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status); -+ if (unlikely(!status)) -+ return IRQ_NONE; -+ -+ /* tx stats */ -+ if (status & I2S_REG_INT_TX_MASK) { -+ if (status & I2S_REG_INT_TX_THRES) -+ i2s->txstats.belowthres++; -+ if (status & I2S_REG_INT_TX_UNRUN) -+ i2s->txstats.underrun++; -+ if (status & I2S_REG_INT_TX_OVRUN) -+ i2s->txstats.overrun++; -+ if (status & I2S_REG_INT_TX_FAULT) -+ i2s->txstats.dmafault++; -+ } -+ -+ /* rx stats */ -+ if (status & I2S_REG_INT_RX_MASK) { -+ if (status & I2S_REG_INT_RX_THRES) -+ i2s->rxstats.belowthres++; -+ if (status & I2S_REG_INT_RX_UNRUN) -+ i2s->rxstats.underrun++; -+ if (status & I2S_REG_INT_RX_OVRUN) -+ i2s->rxstats.overrun++; -+ if (status & I2S_REG_INT_RX_FAULT) -+ i2s->rxstats.dmafault++; -+ } -+ -+ /* clean status bits */ -+ regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status); -+ -+ return IRQ_HANDLED; -+} -+#endif -+ -+#if IS_ENABLED(CONFIG_DEBUG_FS) -+static int ralink_i2s_stats_show(struct seq_file *s, void *unused) -+{ -+ struct ralink_i2s *i2s = s->private; -+ -+ seq_printf(s, "tx stats\n"); -+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres); -+ seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun); -+ seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun); -+ seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault); -+ -+ seq_printf(s, "rx stats\n"); -+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres); -+ seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun); -+ seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun); -+ seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault); -+ -+ ralink_i2s_dump_regs(i2s); -+ -+ return 0; -+} -+ -+static int ralink_i2s_stats_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, ralink_i2s_stats_show, inode->i_private); -+} -+ -+static const struct file_operations ralink_i2s_stats_ops = { -+ .open = ralink_i2s_stats_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s) -+{ -+ i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL); -+ if (!i2s->dbg_dir) -+ return -ENOMEM; -+ -+ i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO, -+ i2s->dbg_dir, i2s, &ralink_i2s_stats_ops); -+ if (!i2s->dbg_stats) { -+ debugfs_remove(i2s->dbg_dir); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s) -+{ -+ debugfs_remove(i2s->dbg_stats); -+ debugfs_remove(i2s->dbg_dir); -+} -+#else -+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s) -+{ -+ return 0; -+} -+ -+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s) -+{ -+} -+#endif -+ -+/* -+ * TODO: these refclk setup functions should use -+ * clock framework instead. hardcode it now. -+ */ -+static void rt3350_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data |= (0x1 << 8); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void rt3883_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x3 << 13); -+ data |= (0x1 << 13); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void rt3552_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0xf << 8); -+ data |= (0x3 << 8); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7620_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x7 << 9); -+ data |= 0x1 << 9; -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7621_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x1f << 18); -+ data |= (0x19 << 18); -+ data &= ~(0x1f << 12); -+ data |= (0x1 << 12); -+ data &= ~(0x7 << 9); -+ data |= (0x5 << 9); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7628_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set i2s and refclk digital pad */ -+ data = rt_sysc_r32(0x3c); -+ data |= 0x1f; -+ rt_sysc_w32(data, 0x3c); -+ -+ /* Adjust REFCLK0's driving strength */ -+ data = rt_sysc_r32(0x1354); -+ data &= ~(0x1 << 5); -+ rt_sysc_w32(data, 0x1354); -+ data = rt_sysc_r32(0x1364); -+ data |= ~(0x1 << 5); -+ rt_sysc_w32(data, 0x1364); -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x7 << 9); -+ data |= 0x1 << 9; -+ rt_sysc_w32(data, 0x2c); -+} -+ -+struct rt_i2s_data { -+ u32 flags; -+ void (*refclk_setup)(void); -+}; -+ -+struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY }; -+struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY, -+ .refclk_setup = rt3350_refclk_setup }; -+struct rt_i2s_data rt3883_i2s_data = { -+ .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J), -+ .refclk_setup = rt3883_refclk_setup }; -+struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup}; -+struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup}; -+struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup}; -+struct rt_i2s_data mt7628_i2s_data = { -+ .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT | -+ RALINK_FLAGS_LEFT_J), -+ .refclk_setup = mt7628_refclk_setup}; -+ -+static const struct of_device_id ralink_i2s_match_table[] = { -+ { .compatible = "ralink,rt3050-i2s", -+ .data = (void *)&rt3050_i2s_data }, -+ { .compatible = "ralink,rt3350-i2s", -+ .data = (void *)&rt3350_i2s_data }, -+ { .compatible = "ralink,rt3883-i2s", -+ .data = (void *)&rt3883_i2s_data }, -+ { .compatible = "ralink,rt3352-i2s", -+ .data = (void *)&rt3352_i2s_data }, -+ { .compatible = "mediatek,mt7620-i2s", -+ .data = (void *)&mt7620_i2s_data }, -+ { .compatible = "mediatek,mt7621-i2s", -+ .data = (void *)&mt7621_i2s_data }, -+ { .compatible = "mediatek,mt7628-i2s", -+ .data = (void *)&mt7628_i2s_data }, -+}; -+MODULE_DEVICE_TABLE(of, ralink_i2s_match_table); -+ -+static int ralink_i2s_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *match; -+ struct device_node *np = pdev->dev.of_node; -+ struct ralink_i2s *i2s; -+ struct resource *res; -+ int irq, ret; -+ u32 dma_req; -+ struct rt_i2s_data *data; -+ -+ i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); -+ if (!i2s) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, i2s); -+ i2s->dev = &pdev->dev; -+ -+ match = of_match_device(ralink_i2s_match_table, &pdev->dev); -+ if (!match) -+ return -EINVAL; -+ data = (struct rt_i2s_data *)match->data; -+ i2s->flags = data->flags; -+ /* setup out 12Mhz refclk to codec as mclk */ -+ if (data->refclk_setup) -+ data->refclk_setup(); -+ -+ if (of_property_read_u32(np, "txdma-req", &dma_req)) { -+ dev_err(&pdev->dev, "no txdma-req define\n"); -+ return -EINVAL; -+ } -+ i2s->txdma_req = (u16)dma_req; -+ if (!(i2s->flags & RALINK_FLAGS_TXONLY)) { -+ if (of_property_read_u32(np, "rxdma-req", &dma_req)) { -+ dev_err(&pdev->dev, "no rxdma-req define\n"); -+ return -EINVAL; -+ } -+ i2s->rxdma_req = (u16)dma_req; -+ } -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ i2s->regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(i2s->regs)) -+ return PTR_ERR(i2s->regs); -+ -+ i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs, -+ &ralink_i2s_regmap_config); -+ if (IS_ERR(i2s->regmap)) { -+ dev_err(&pdev->dev, "regmap init failed\n"); -+ return PTR_ERR(i2s->regmap); -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(&pdev->dev, "failed to get irq\n"); -+ return -EINVAL; -+ } -+ -+#if (RALINK_I2S_INT_EN) -+ ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq, -+ 0, dev_name(&pdev->dev), i2s); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request irq\n"); -+ return ret; -+ } -+#endif -+ -+ i2s->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(i2s->clk)) { -+ dev_err(&pdev->dev, "no clock defined\n"); -+ return PTR_ERR(i2s->clk); -+ } -+ -+ ret = clk_prepare_enable(i2s->clk); -+ if (ret) -+ return ret; -+ -+ ralink_i2s_init_dma_data(i2s, res); -+ -+ device_reset(&pdev->dev); -+ -+ ret = ralink_i2s_debugfs_create(i2s); -+ if (ret) { -+ dev_err(&pdev->dev, "create debugfs failed\n"); -+ goto err_clk_disable; -+ } -+ -+ /* enable 24bits support */ -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE; -+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE; -+ } -+ -+ /* enable big endian support */ -+ if (i2s->flags & RALINK_FLAGS_ENDIAN) { -+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ ralink_i2s_dai.capture.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ ralink_i2s_dai.playback.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ ralink_pcm_hardware.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ } -+ } -+ -+ /* disable capture support */ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture), -+ 0); -+ -+ ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component, -+ &ralink_i2s_dai, 1); -+ if (ret) -+ goto err_debugfs; -+ -+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, -+ &ralink_dmaengine_pcm_config, -+ SND_DMAENGINE_PCM_FLAG_COMPAT); -+ if (ret) -+ goto err_debugfs; -+ -+ dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000); -+ -+ return 0; -+ -+err_debugfs: -+ ralink_i2s_debugfs_remove(i2s); -+ -+err_clk_disable: -+ clk_disable_unprepare(i2s->clk); -+ -+ return ret; -+} -+ -+static int ralink_i2s_remove(struct platform_device *pdev) -+{ -+ struct ralink_i2s *i2s = platform_get_drvdata(pdev); -+ -+ ralink_i2s_debugfs_remove(i2s); -+ clk_disable_unprepare(i2s->clk); -+ -+ return 0; -+} -+ -+static struct platform_driver ralink_i2s_driver = { -+ .probe = ralink_i2s_probe, -+ .remove = ralink_i2s_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .of_match_table = ralink_i2s_match_table, -+ }, -+}; -+module_platform_driver(ralink_i2s_driver); -+ -+MODULE_AUTHOR("Lars-Peter Clausen, "); -+MODULE_DESCRIPTION("Ralink/MediaTek I2S driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:" DRV_NAME); diff --git a/target/linux/ramips/patches-5.4/0051-serial-add-ugly-custom-baud-rate-hack.patch b/target/linux/ramips/patches-5.4/0051-serial-add-ugly-custom-baud-rate-hack.patch deleted file mode 100644 index 7192d61323..0000000000 --- a/target/linux/ramips/patches-5.4/0051-serial-add-ugly-custom-baud-rate-hack.patch +++ /dev/null @@ -1,22 +0,0 @@ -From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:31:08 +0100 -Subject: [PATCH 51/53] serial: add ugly custom baud rate hack - -Signed-off-by: John Crispin ---- - drivers/tty/serial/serial_core.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/tty/serial/serial_core.c -+++ b/drivers/tty/serial/serial_core.c -@@ -423,6 +423,9 @@ uart_get_baud_rate(struct uart_port *por - break; - } - -+ if (tty_termios_baud_rate(termios) == 2500000) -+ return 250000; -+ - for (try = 0; try < 2; try++) { - baud = tty_termios_baud_rate(termios); - diff --git a/target/linux/ramips/patches-5.4/0052-pwm-add-mediatek-support.patch b/target/linux/ramips/patches-5.4/0052-pwm-add-mediatek-support.patch deleted file mode 100644 index d2c5724c06..0000000000 --- a/target/linux/ramips/patches-5.4/0052-pwm-add-mediatek-support.patch +++ /dev/null @@ -1,217 +0,0 @@ -From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:16:50 +0100 -Subject: [PATCH 52/53] pwm: add mediatek support - -Signed-off-by: John Crispin ---- - drivers/pwm/Kconfig | 9 +++ - drivers/pwm/Makefile | 1 + - drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 183 insertions(+) - create mode 100644 drivers/pwm/pwm-mediatek.c - ---- a/drivers/pwm/Kconfig -+++ b/drivers/pwm/Kconfig -@@ -316,6 +316,15 @@ config PWM_MEDIATEK - To compile this driver as a module, choose M here: the module - will be called pwm-mediatek. - -+config PWM_MEDIATEK_RAMIPS -+ tristate "Mediatek PWM support" -+ depends on RALINK && OF -+ help -+ Generic PWM framework driver for Mediatek ARM SoC. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called pwm-mxs. -+ - config PWM_MXS - tristate "Freescale MXS PWM support" - depends on ARCH_MXS && OF ---- a/drivers/pwm/Makefile -+++ b/drivers/pwm/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p - obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o - obj-$(CONFIG_PWM_MESON) += pwm-meson.o - obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o -+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o - obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o - obj-$(CONFIG_PWM_MXS) += pwm-mxs.o - obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o ---- /dev/null -+++ b/drivers/pwm/pwm-mediatek-ramips.c -@@ -0,0 +1,173 @@ -+/* -+ * Mediatek Pulse Width Modulator driver -+ * -+ * Copyright (C) 2015 John Crispin -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NUM_PWM 4 -+ -+/* PWM registers and bits definitions */ -+#define PWMCON 0x00 -+#define PWMHDUR 0x04 -+#define PWMLDUR 0x08 -+#define PWMGDUR 0x0c -+#define PWMWAVENUM 0x28 -+#define PWMDWIDTH 0x2c -+#define PWMTHRES 0x30 -+ -+/** -+ * struct mtk_pwm_chip - struct representing pwm chip -+ * -+ * @mmio_base: base address of pwm chip -+ * @chip: linux pwm chip representation -+ */ -+struct mtk_pwm_chip { -+ void __iomem *mmio_base; -+ struct pwm_chip chip; -+}; -+ -+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) -+{ -+ return container_of(chip, struct mtk_pwm_chip, chip); -+} -+ -+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, -+ unsigned long offset) -+{ -+ return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, -+ unsigned int num, unsigned long offset, -+ unsigned long val) -+{ -+ iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, -+ int duty_ns, int period_ns) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 resolution = 100 / 4; -+ u32 clkdiv = 0; -+ -+ while (period_ns / resolution > 8191) { -+ clkdiv++; -+ resolution *= 2; -+ } -+ -+ if (clkdiv > 7) -+ return -1; -+ -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); -+ return 0; -+} -+ -+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val |= BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+ -+ return 0; -+} -+ -+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val &= ~BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+} -+ -+static const struct pwm_ops mtk_pwm_ops = { -+ .config = mtk_pwm_config, -+ .enable = mtk_pwm_enable, -+ .disable = mtk_pwm_disable, -+ .owner = THIS_MODULE, -+}; -+ -+static int mtk_pwm_probe(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc; -+ struct resource *r; -+ int ret; -+ -+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); -+ if (!pc) -+ return -ENOMEM; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); -+ if (IS_ERR(pc->mmio_base)) -+ return PTR_ERR(pc->mmio_base); -+ -+ platform_set_drvdata(pdev, pc); -+ -+ pc->chip.dev = &pdev->dev; -+ pc->chip.ops = &mtk_pwm_ops; -+ pc->chip.base = -1; -+ pc->chip.npwm = NUM_PWM; -+ -+ ret = pwmchip_add(&pc->chip); -+ if (ret < 0) -+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int mtk_pwm_remove(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); -+ int i; -+ -+ for (i = 0; i < NUM_PWM; i++) -+ pwm_disable(&pc->chip.pwms[i]); -+ -+ return pwmchip_remove(&pc->chip); -+} -+ -+static const struct of_device_id mtk_pwm_of_match[] = { -+ { .compatible = "mediatek,mt7628-pwm" }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); -+ -+static struct platform_driver mtk_pwm_driver = { -+ .driver = { -+ .name = "mtk-pwm", -+ .owner = THIS_MODULE, -+ .of_match_table = mtk_pwm_of_match, -+ }, -+ .probe = mtk_pwm_probe, -+ .remove = mtk_pwm_remove, -+}; -+ -+module_platform_driver(mtk_pwm_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_ALIAS("platform:mtk-pwm"); diff --git a/target/linux/ramips/patches-5.4/0069-awake-rt305x-dwc2-controller.patch b/target/linux/ramips/patches-5.4/0069-awake-rt305x-dwc2-controller.patch deleted file mode 100644 index 7110a5b808..0000000000 --- a/target/linux/ramips/patches-5.4/0069-awake-rt305x-dwc2-controller.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/drivers/usb/dwc2/platform.c -+++ b/drivers/usb/dwc2/platform.c -@@ -431,6 +431,12 @@ static int dwc2_driver_probe(struct plat - if (retval) - return retval; - -+ /* Enable USB port before any regs access */ -+ if (readl(hsotg->regs + PCGCTL) & 0x0f) { -+ writel(0x00, hsotg->regs + PCGCTL); -+ /* TODO: mdelay(25) here? vendor driver don't use it */ -+ } -+ - hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); - - retval = dwc2_get_dr_mode(hsotg); diff --git a/target/linux/ramips/patches-5.4/0070-weak_reordering.patch b/target/linux/ramips/patches-5.4/0070-weak_reordering.patch deleted file mode 100644 index fe3fdec289..0000000000 --- a/target/linux/ramips/patches-5.4/0070-weak_reordering.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -57,6 +57,7 @@ choice - select COMMON_CLK - select CLKSRC_MIPS_GIC - select HAVE_PCI if PCI_MT7621 -+ select WEAK_REORDERING_BEYOND_LLSC - endchoice - - choice diff --git a/target/linux/ramips/patches-5.4/0098-disable_cm.patch b/target/linux/ramips/patches-5.4/0098-disable_cm.patch deleted file mode 100644 index 1f3367568f..0000000000 --- a/target/linux/ramips/patches-5.4/0098-disable_cm.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/mips/kernel/mips-cm.c -+++ b/arch/mips/kernel/mips-cm.c -@@ -232,6 +232,7 @@ int mips_cm_probe(void) - - /* disable CM regions */ - write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR); -+ /* - write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK); - write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR); - write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK); -@@ -239,7 +240,7 @@ int mips_cm_probe(void) - write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK); - write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR); - write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK); -- -+*/ - /* probe for an L2-only sync region */ - mips_cm_probe_l2sync(); - diff --git a/target/linux/ramips/patches-5.4/0100-staging-mt7621-pci-simplify-mt7621_pcie_init_virtual.patch b/target/linux/ramips/patches-5.4/0100-staging-mt7621-pci-simplify-mt7621_pcie_init_virtual.patch deleted file mode 100644 index b9bcd63488..0000000000 --- a/target/linux/ramips/patches-5.4/0100-staging-mt7621-pci-simplify-mt7621_pcie_init_virtual.patch +++ /dev/null @@ -1,133 +0,0 @@ -From b327cd58c3fec1c6382128e929eab9bc0d68e912 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sun, 8 Mar 2020 10:19:27 +0100 -Subject: [PATCH] staging: mt7621-pci: simplify - 'mt7621_pcie_init_virtual_bridges' function - -Function 'mt7621_pcie_init_virtual_bridges' is a bit mess and can be -refactorized properly in a cleaner way. Introduce new 'pcie_rmw' inline -function helper to do clear and set the correct bits this function needs -to work. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200308091928.17177-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 85 +++++++++++++-------------------- - 1 file changed, 33 insertions(+), 52 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -57,13 +57,13 @@ - #define RALINK_PCI_IOBASE 0x002C - - /* PCICFG virtual bridges */ --#define MT7621_BR0_MASK GENMASK(19, 16) --#define MT7621_BR1_MASK GENMASK(23, 20) --#define MT7621_BR2_MASK GENMASK(27, 24) --#define MT7621_BR_ALL_MASK GENMASK(27, 16) --#define MT7621_BR0_SHIFT 16 --#define MT7621_BR1_SHIFT 20 --#define MT7621_BR2_SHIFT 24 -+#define PCIE_P2P_MAX 3 -+#define PCIE_P2P_BR_DEVNUM_SHIFT(p) (16 + (p) * 4) -+#define PCIE_P2P_BR_DEVNUM0_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(0) -+#define PCIE_P2P_BR_DEVNUM1_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(1) -+#define PCIE_P2P_BR_DEVNUM2_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(2) -+#define PCIE_P2P_BR_DEVNUM_MASK 0xf -+#define PCIE_P2P_BR_DEVNUM_MASK_FULL (0xfff << PCIE_P2P_BR_DEVNUM0_SHIFT) - - /* PCIe RC control registers */ - #define MT7621_PCIE_OFFSET 0x2000 -@@ -154,6 +154,15 @@ static inline void pcie_write(struct mt7 - writel(val, pcie->base + reg); - } - -+static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set) -+{ -+ u32 val = readl(pcie->base + reg); -+ -+ val &= ~clr; -+ val |= set; -+ writel(val, pcie->base + reg); -+} -+ - static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg) - { - return readl(port->base + reg); -@@ -554,7 +563,9 @@ static void mt7621_pcie_enable_ports(str - static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie) - { - u32 pcie_link_status = 0; -- u32 val = 0; -+ u32 n; -+ int i; -+ u32 p2p_br_devnum[PCIE_P2P_MAX]; - struct mt7621_pcie_port *port; - - list_for_each_entry(port, &pcie->ports, list) { -@@ -567,50 +578,20 @@ static int mt7621_pcie_init_virtual_brid - if (pcie_link_status == 0) - return -1; - -- /* -- * pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num -- * 3'b000 x x x -- * 3'b001 x x 0 -- * 3'b010 x 0 x -- * 3'b011 x 1 0 -- * 3'b100 0 x x -- * 3'b101 1 x 0 -- * 3'b110 1 0 x -- * 3'b111 2 1 0 -- */ -- switch (pcie_link_status) { -- case 2: -- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); -- val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK); -- val |= 0x1 << MT7621_BR0_SHIFT; -- val |= 0x0 << MT7621_BR1_SHIFT; -- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); -- break; -- case 4: -- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); -- val &= ~MT7621_BR_ALL_MASK; -- val |= 0x1 << MT7621_BR0_SHIFT; -- val |= 0x2 << MT7621_BR1_SHIFT; -- val |= 0x0 << MT7621_BR2_SHIFT; -- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); -- break; -- case 5: -- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); -- val &= ~MT7621_BR_ALL_MASK; -- val |= 0x0 << MT7621_BR0_SHIFT; -- val |= 0x2 << MT7621_BR1_SHIFT; -- val |= 0x1 << MT7621_BR2_SHIFT; -- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); -- break; -- case 6: -- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR); -- val &= ~MT7621_BR_ALL_MASK; -- val |= 0x2 << MT7621_BR0_SHIFT; -- val |= 0x0 << MT7621_BR1_SHIFT; -- val |= 0x1 << MT7621_BR2_SHIFT; -- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR); -- break; -- } -+ n = 0; -+ for (i = 0; i < PCIE_P2P_MAX; i++) -+ if (pcie_link_status & BIT(i)) -+ p2p_br_devnum[i] = n++; -+ -+ for (i = 0; i < PCIE_P2P_MAX; i++) -+ if ((pcie_link_status & BIT(i)) == 0) -+ p2p_br_devnum[i] = n++; -+ -+ pcie_rmw(pcie, RALINK_PCI_CONFIG_ADDR, -+ PCIE_P2P_BR_DEVNUM_MASK_FULL, -+ (p2p_br_devnum[0] << PCIE_P2P_BR_DEVNUM0_SHIFT) | -+ (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) | -+ (p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT)); - - return 0; - } diff --git a/target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch b/target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch deleted file mode 100644 index 3939280a16..0000000000 --- a/target/linux/ramips/patches-5.4/0101-staging-mt7621-pci-enable-clock-bit-for-each-port.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 550fabd71d7fcdfe099bbf41e00e28719737161e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Tue, 10 Mar 2020 12:34:59 +0100 -Subject: [PATCH] staging: mt7621-pci: enable clock bit for each port - -The clock related code concerns me from the very beginning because -there are some set ups got from legacy driver that are not documented -anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1' -register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed -at all and the proper thing to do is just enable the clock bit for each -pcie port. Hence remove useless code and do the right thing which is -setting up the clock bit for each port enabled. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 17 ++++++----------- - 1 file changed, 6 insertions(+), 11 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -45,8 +45,6 @@ - - /* rt_sysc_membase relative registers */ - #define RALINK_CLKCFG1 0x30 --#define RALINK_PCIE_CLK_GEN 0x7c --#define RALINK_PCIE_CLK_GEN1 0x80 - - /* Host-PCI bridge registers */ - #define RALINK_PCI_PCICFG_ADDR 0x0000 -@@ -85,10 +83,6 @@ - #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) - #define PCIE_PORT_LINKUP BIT(0) - --#define PCIE_CLK_GEN_EN BIT(31) --#define PCIE_CLK_GEN_DIS 0 --#define PCIE_CLK_GEN1_DIS GENMASK(30, 24) --#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25)) - #define MEMORY_BASE 0x0 - #define PERST_MODE_MASK GENMASK(11, 10) - #define PERST_MODE_GPIO BIT(10) -@@ -233,6 +227,11 @@ static inline bool mt7621_pcie_port_is_l - return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0; - } - -+static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port) -+{ -+ rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1); -+} -+ - static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port) - { - rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1); -@@ -501,11 +500,6 @@ static void mt7621_pcie_init_ports(struc - } - } - -- rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); -- rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); -- rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); -- rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); -- msleep(50); - reset_control_deassert(pcie->rst); - } - -@@ -542,6 +536,7 @@ static void mt7621_pcie_enable_ports(str - - list_for_each_entry(port, &pcie->ports, list) { - if (port->enabled) { -+ mt7621_pcie_port_clk_enable(port); - mt7621_pcie_enable_port(port); - dev_info(dev, "PCIE%d enabled\n", num_slots_enabled); - num_slots_enabled++; diff --git a/target/linux/ramips/patches-5.4/0102-staging-mt7621-pci-use-gpios-for-properly-reset.patch b/target/linux/ramips/patches-5.4/0102-staging-mt7621-pci-use-gpios-for-properly-reset.patch deleted file mode 100644 index 1b7828f1e6..0000000000 --- a/target/linux/ramips/patches-5.4/0102-staging-mt7621-pci-use-gpios-for-properly-reset.patch +++ /dev/null @@ -1,222 +0,0 @@ -From 227a8bf421ff8b085444e51e471ef06a87228cfd Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 13 Mar 2020 21:09:08 +0100 -Subject: [PATCH] staging: mt7621-pci: use gpios for properly reset - -Original driver code was using three gpio's for reset -asserts and deasserts the pcis. Instead of using that -a general reset control with a perst gpio was introduced -and it seems it is partially working but sometimes there -are some unexpected hangs on boot. This commit make use of -the three original gpios using 'reset-gpios' property of -the device tree and removes the reset line and perst gpio. -According to the mediatek aplication note v0.1 there are -three gpios used for pcie ports reset control: gpio#19, -gpio#8 and gpio#7 for slots 0, 1 and 2 respectively. -This schema can be used separately for mt7621A but in some -boards due to pin share issue, if the PCM and I2S function -are enable at the same time, there are no enough GPIO to -control per-port PCIe reset. In those cases gpio#19 is enought -for reset the three ports together. Because of this we just -try to get the three gpios but if some of them fail we are not -failing in boot process, just prints a kernel notice and take -after into account if the descriptor is or not valid in order -to use it. All of them are set as GPIO output low configuration. -The gpio descriptor's API takes device tree property into account -and invert value if the pin is configured as active low. -So we also have to properly request pins from device tree -and set values correct in assert and deassert functions. -After this changes the order to make all assert and -deassert in the 'probe' process makes more sense: -* Parse device tree. -* make assert of the RC's and EP's before doing anything else. -* make deassert of the RC's before initializing the phy. -* Init the phy. -* make deassert of the EP's before initialize pci ports. -* Normal PCI initialization. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200313200913.24321-2-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 84 ++++++++++++++++++++------------- - 1 file changed, 51 insertions(+), 33 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -95,6 +95,7 @@ - * @pcie: pointer to PCIe host info - * @phy: pointer to PHY control block - * @pcie_rst: pointer to port reset control -+ * @gpio_rst: gpio reset - * @slot: port slot - * @enabled: indicates if port is enabled - */ -@@ -104,6 +105,7 @@ struct mt7621_pcie_port { - struct mt7621_pcie *pcie; - struct phy *phy; - struct reset_control *pcie_rst; -+ struct gpio_desc *gpio_rst; - u32 slot; - bool enabled; - }; -@@ -117,8 +119,6 @@ struct mt7621_pcie_port { - * @offset: IO / Memory offset - * @dev: Pointer to PCIe device - * @ports: pointer to PCIe port information -- * @perst: gpio reset -- * @rst: pointer to pcie reset - * @resets_inverted: depends on chip revision - * reset lines are inverted. - */ -@@ -133,8 +133,6 @@ struct mt7621_pcie { - resource_size_t io; - } offset; - struct list_head ports; -- struct gpio_desc *perst; -- struct reset_control *rst; - bool resets_inverted; - }; - -@@ -210,16 +208,16 @@ static void write_config(struct mt7621_p - pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); - } - --static inline void mt7621_perst_gpio_pcie_assert(struct mt7621_pcie *pcie) -+static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port) - { -- gpiod_set_value(pcie->perst, 0); -- mdelay(PERST_DELAY_US); -+ if (port->gpio_rst) -+ gpiod_set_value(port->gpio_rst, 1); - } - --static inline void mt7621_perst_gpio_pcie_deassert(struct mt7621_pcie *pcie) -+static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port) - { -- gpiod_set_value(pcie->perst, 1); -- mdelay(PERST_DELAY_US); -+ if (port->gpio_rst) -+ gpiod_set_value(port->gpio_rst, 0); - } - - static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port) -@@ -367,6 +365,13 @@ static int mt7621_pcie_parse_port(struct - if (IS_ERR(port->phy)) - return PTR_ERR(port->phy); - -+ port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, -+ GPIOD_OUT_LOW); -+ if (IS_ERR(port->gpio_rst)) { -+ dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot); -+ return PTR_ERR(port->gpio_rst); -+ } -+ - port->slot = slot; - port->pcie = pcie; - -@@ -383,12 +388,6 @@ static int mt7621_pcie_parse_dt(struct m - struct resource regs; - int err; - -- pcie->perst = devm_gpiod_get(dev, "perst", GPIOD_OUT_HIGH); -- if (IS_ERR(pcie->perst)) { -- dev_err(dev, "failed to get gpio perst\n"); -- return PTR_ERR(pcie->perst); -- } -- - err = of_address_to_resource(node, 0, ®s); - if (err) { - dev_err(dev, "missing \"reg\" property\n"); -@@ -399,12 +398,6 @@ static int mt7621_pcie_parse_dt(struct m - if (IS_ERR(pcie->base)) - return PTR_ERR(pcie->base); - -- pcie->rst = devm_reset_control_get_exclusive(dev, "pcie"); -- if (PTR_ERR(pcie->rst) == -EPROBE_DEFER) { -- dev_err(dev, "failed to get pcie reset control\n"); -- return PTR_ERR(pcie->rst); -- } -- - for_each_available_child_of_node(node, child) { - int slot; - -@@ -458,16 +451,49 @@ static int mt7621_pcie_init_port(struct - return 0; - } - -+static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie) -+{ -+ struct mt7621_pcie_port *port; -+ -+ list_for_each_entry(port, &pcie->ports, list) { -+ /* PCIe RC reset assert */ -+ mt7621_control_assert(port); -+ -+ /* PCIe EP reset assert */ -+ mt7621_rst_gpio_pcie_assert(port); -+ } -+ -+ mdelay(PERST_DELAY_US); -+} -+ -+static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie) -+{ -+ struct mt7621_pcie_port *port; -+ -+ list_for_each_entry(port, &pcie->ports, list) -+ mt7621_control_deassert(port); -+} -+ -+static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie) -+{ -+ struct mt7621_pcie_port *port; -+ -+ list_for_each_entry(port, &pcie->ports, list) -+ mt7621_rst_gpio_pcie_deassert(port); -+ -+ mdelay(PERST_DELAY_US); -+} -+ - static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) - { - struct device *dev = pcie->dev; - struct mt7621_pcie_port *port, *tmp; -- u32 val = 0; - int err; - - rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE); - -- mt7621_perst_gpio_pcie_assert(pcie); -+ mt7621_pcie_reset_assert(pcie); -+ mt7621_pcie_reset_rc_deassert(pcie); - - list_for_each_entry_safe(port, tmp, &pcie->ports, list) { - u32 slot = port->slot; -@@ -476,16 +502,10 @@ static void mt7621_pcie_init_ports(struc - if (err) { - dev_err(dev, "Initiating port %d failed\n", slot); - list_del(&port->list); -- } else { -- val = read_config(pcie, slot, PCIE_FTS_NUM); -- dev_info(dev, "Port %d N_FTS = %x\n", slot, -- (unsigned int)val); - } - } - -- reset_control_assert(pcie->rst); -- -- mt7621_perst_gpio_pcie_deassert(pcie); -+ mt7621_pcie_reset_ep_deassert(pcie); - - list_for_each_entry(port, &pcie->ports, list) { - u32 slot = port->slot; -@@ -499,8 +519,6 @@ static void mt7621_pcie_init_ports(struc - port->enabled = false; - } - } -- -- reset_control_deassert(pcie->rst); - } - - static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) diff --git a/target/linux/ramips/patches-5.4/0103-staging-mt7621-pci-change-value-for-PERST_DELAY_MS.patch b/target/linux/ramips/patches-5.4/0103-staging-mt7621-pci-change-value-for-PERST_DELAY_MS.patch deleted file mode 100644 index 3d86355b29..0000000000 --- a/target/linux/ramips/patches-5.4/0103-staging-mt7621-pci-change-value-for-PERST_DELAY_MS.patch +++ /dev/null @@ -1,45 +0,0 @@ -From e462e7d3211479df42357a620fa788a2257556b7 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 13 Mar 2020 21:09:09 +0100 -Subject: [PATCH] staging: mt7621-pci: change value for 'PERST_DELAY_MS' - -Value of 'PERST_DELAY_MS' is too high and it is ok just -to set up to 100 ms. Update also define name from -'PERST_DELAY_US' into 'PERST_DELAY_MS' - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200313200913.24321-3-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -86,7 +86,7 @@ - #define MEMORY_BASE 0x0 - #define PERST_MODE_MASK GENMASK(11, 10) - #define PERST_MODE_GPIO BIT(10) --#define PERST_DELAY_US 1000 -+#define PERST_DELAY_MS 100 - - /** - * struct mt7621_pcie_port - PCIe port information -@@ -463,7 +463,7 @@ static void mt7621_pcie_reset_assert(str - mt7621_rst_gpio_pcie_assert(port); - } - -- mdelay(PERST_DELAY_US); -+ mdelay(PERST_DELAY_MS); - } - - static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie) -@@ -481,7 +481,7 @@ static void mt7621_pcie_reset_ep_deasser - list_for_each_entry(port, &pcie->ports, list) - mt7621_rst_gpio_pcie_deassert(port); - -- mdelay(PERST_DELAY_US); -+ mdelay(PERST_DELAY_MS); - } - - static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) diff --git a/target/linux/ramips/patches-5.4/0104-staging-mt7621-pci-release-gpios-after-pci-initializ.patch b/target/linux/ramips/patches-5.4/0104-staging-mt7621-pci-release-gpios-after-pci-initializ.patch deleted file mode 100644 index f24bf833c9..0000000000 --- a/target/linux/ramips/patches-5.4/0104-staging-mt7621-pci-release-gpios-after-pci-initializ.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 4d6a758f2cd2122a7d895f913854c13da62ba6df Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 13 Mar 2020 21:09:12 +0100 -Subject: [PATCH] staging: mt7621-pci: release gpios after pci initialization - -R3G's LEDs fail to initialize because one of them uses GPIO8 -Hence, release the GPIO resources after PCIe initialization -and properly release also in driver error path. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200313200913.24321-6-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 23 ++++++++++++++++++----- - 1 file changed, 18 insertions(+), 5 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -484,6 +484,15 @@ static void mt7621_pcie_reset_ep_deasser - mdelay(PERST_DELAY_MS); - } - -+static void mt7621_pcie_release_gpios(struct mt7621_pcie *pcie) -+{ -+ struct mt7621_pcie_port *port; -+ -+ list_for_each_entry(port, &pcie->ports, list) -+ if (port->gpio_rst) -+ gpiod_put(port->gpio_rst); -+} -+ - static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) - { - struct device *dev = pcie->dev; -@@ -683,7 +692,8 @@ static int mt7621_pci_probe(struct platf - err = mt7621_pcie_init_virtual_bridges(pcie); - if (err) { - dev_err(dev, "Nothing is connected in virtual bridges. Exiting..."); -- return 0; -+ err = 0; -+ goto out_release_gpios; - } - - mt7621_pcie_enable_ports(pcie); -@@ -691,7 +701,7 @@ static int mt7621_pci_probe(struct platf - err = mt7621_pci_parse_request_of_pci_ranges(pcie); - if (err) { - dev_err(dev, "Error requesting pci resources from ranges"); -- return err; -+ goto out_release_gpios; - } - - setup_cm_memory_region(pcie); -@@ -699,16 +709,19 @@ static int mt7621_pci_probe(struct platf - err = mt7621_pcie_request_resources(pcie, &res); - if (err) { - dev_err(dev, "Error requesting resources\n"); -- return err; -+ goto out_release_gpios; - } - - err = mt7621_pcie_register_host(bridge, &res); - if (err) { - dev_err(dev, "Error registering host\n"); -- return err; -+ goto out_release_gpios; - } - -- return 0; -+out_release_gpios: -+ mt7621_pcie_release_gpios(pcie); -+ -+ return err; - } - - static const struct of_device_id mt7621_pci_ids[] = { diff --git a/target/linux/ramips/patches-5.4/0105-staging-mt7621-pci-delete-no-more-needed-mt7621_rese.patch b/target/linux/ramips/patches-5.4/0105-staging-mt7621-pci-delete-no-more-needed-mt7621_rese.patch deleted file mode 100644 index fc509e945b..0000000000 --- a/target/linux/ramips/patches-5.4/0105-staging-mt7621-pci-delete-no-more-needed-mt7621_rese.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 4be54c3a495f08c05a8e485566e5b88cd3537f16 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 13 Mar 2020 21:09:13 +0100 -Subject: [PATCH] staging: mt7621-pci: delete no more needed - 'mt7621_reset_port' - -After review all the resets at the beggining the function -'mt7621_reset_port' is not needed anymore. Hence delete it -and its uses. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200313200913.24321-7-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 13 ------------- - 1 file changed, 13 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -255,13 +255,6 @@ static inline void mt7621_control_deasse - reset_control_assert(port->pcie_rst); - } - --static void mt7621_reset_port(struct mt7621_pcie_port *port) --{ -- mt7621_control_assert(port); -- msleep(100); -- mt7621_control_deassert(port); --} -- - static void setup_cm_memory_region(struct mt7621_pcie *pcie) - { - struct resource *mem_resource = &pcie->mem; -@@ -427,12 +420,6 @@ static int mt7621_pcie_init_port(struct - u32 slot = port->slot; - int err; - -- /* -- * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at -- * the end of the chip_id has inverted PCI resets. -- */ -- mt7621_reset_port(port); -- - err = phy_init(port->phy); - if (err) { - dev_err(dev, "failed to initialize port%d phy\n", slot); diff --git a/target/linux/ramips/patches-5.4/0106-staging-mt7621-pci-phy-add-mt7621_phy_rmw-to-simplif.patch b/target/linux/ramips/patches-5.4/0106-staging-mt7621-pci-phy-add-mt7621_phy_rmw-to-simplif.patch deleted file mode 100644 index 234af32308..0000000000 --- a/target/linux/ramips/patches-5.4/0106-staging-mt7621-pci-phy-add-mt7621_phy_rmw-to-simplif.patch +++ /dev/null @@ -1,234 +0,0 @@ -From bf0c6782e5b9a6deee4e223655325dc004fae8dd Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sun, 15 Mar 2020 17:01:54 +0100 -Subject: [PATCH] staging: mt7621-pci-phy: add 'mt7621_phy_rmw' to simplify - code - -In order to simplify driver code and decrease a bit LOC add new -function 'mt7621_phy_rmw' where clear and set bits are passed as -arguments. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200315160154.10292-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 158 +++++++++++------------- - 1 file changed, 71 insertions(+), 87 deletions(-) - ---- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -@@ -120,17 +120,25 @@ static inline void phy_write(struct mt76 - regmap_write(phy->regmap, reg, val); - } - -+static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy, -+ u32 reg, u32 clr, u32 set) -+{ -+ u32 val = phy_read(phy, reg); -+ -+ val &= ~clr; -+ val |= set; -+ phy_write(phy, val, reg); -+} -+ - static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy, - struct mt7621_pci_phy_instance *instance) - { - u32 offset = (instance->index != 1) ? - RG_PE1_PIPE_REG : RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH; -- u32 reg; - -- reg = phy_read(phy, offset); -- reg &= ~(RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); -- reg |= (RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); -- phy_write(phy, reg, offset); -+ mt7621_phy_rmw(phy, offset, -+ RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC, -+ RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); - } - - static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy, -@@ -139,97 +147,77 @@ static void mt7621_set_phy_for_ssc(struc - struct device *dev = phy->dev; - u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); - u32 offset; -- u32 val; - - reg = (reg >> 6) & 0x7; - /* Set PCIe Port PHY to disable SSC */ - /* Debug Xtal Type */ -- val = phy_read(phy, RG_PE1_FRC_H_XTAL_REG); -- val &= ~(RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE); -- val |= RG_PE1_FRC_H_XTAL_TYPE; -- val |= RG_PE1_H_XTAL_TYPE_VAL(0x00); -- phy_write(phy, val, RG_PE1_FRC_H_XTAL_REG); -+ mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG, -+ RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE, -+ RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00)); - - /* disable port */ - offset = (instance->index != 1) ? - RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; -- val = phy_read(phy, offset); -- val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); -- val |= RG_PE1_FRC_PHY_EN; -- phy_write(phy, val, offset); -- -- /* Set Pre-divider ratio (for host mode) */ -- val = phy_read(phy, RG_PE1_H_PLL_REG); -- val &= ~(RG_PE1_H_PLL_PREDIV); -+ mt7621_phy_rmw(phy, offset, -+ RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); - - if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ -- val |= RG_PE1_H_PLL_PREDIV_VAL(0x01); -- phy_write(phy, val, RG_PE1_H_PLL_REG); -+ /* Set Pre-divider ratio (for host mode) */ -+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, -+ RG_PE1_H_PLL_PREDIV, -+ RG_PE1_H_PLL_PREDIV_VAL(0x01)); - dev_info(dev, "Xtal is 40MHz\n"); -- } else { /* 25MHz | 20MHz Xtal */ -- val |= RG_PE1_H_PLL_PREDIV_VAL(0x00); -- phy_write(phy, val, RG_PE1_H_PLL_REG); -- if (reg >= 6) { -- dev_info(dev, "Xtal is 25MHz\n"); -- -- /* Select feedback clock */ -- val = phy_read(phy, RG_PE1_H_PLL_FBKSEL_REG); -- val &= ~(RG_PE1_H_PLL_FBKSEL); -- val |= RG_PE1_H_PLL_FBKSEL_VAL(0x01); -- phy_write(phy, val, RG_PE1_H_PLL_FBKSEL_REG); -- -- /* DDS NCPO PCW (for host mode) */ -- val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG); -- val &= ~(RG_PE1_H_LCDDS_SSC_PRD); -- val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000); -- phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG); -- -- /* DDS SSC dither period control */ -- val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG); -- val &= ~(RG_PE1_H_LCDDS_SSC_PRD); -- val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d); -- phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG); -- -- /* DDS SSC dither amplitude control */ -- val = phy_read(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG); -- val &= ~(RG_PE1_H_LCDDS_SSC_DELTA | -- RG_PE1_H_LCDDS_SSC_DELTA1); -- val |= RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a); -- val |= RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a); -- phy_write(phy, val, RG_PE1_H_LCDDS_SSC_DELTA_REG); -- } else { -- dev_info(dev, "Xtal is 20MHz\n"); -- } -+ } else if (reg >= 6) { /* 25MHz Xal */ -+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, -+ RG_PE1_H_PLL_PREDIV, -+ RG_PE1_H_PLL_PREDIV_VAL(0x00)); -+ /* Select feedback clock */ -+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG, -+ RG_PE1_H_PLL_FBKSEL, -+ RG_PE1_H_PLL_FBKSEL_VAL(0x01)); -+ /* DDS NCPO PCW (for host mode) */ -+ mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG, -+ RG_PE1_H_LCDDS_SSC_PRD, -+ RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000)); -+ /* DDS SSC dither period control */ -+ mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG, -+ RG_PE1_H_LCDDS_SSC_PRD, -+ RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d)); -+ /* DDS SSC dither amplitude control */ -+ mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG, -+ RG_PE1_H_LCDDS_SSC_DELTA | -+ RG_PE1_H_LCDDS_SSC_DELTA1, -+ RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a) | -+ RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a)); -+ dev_info(dev, "Xtal is 25MHz\n"); -+ } else { /* 20MHz Xtal */ -+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, -+ RG_PE1_H_PLL_PREDIV, -+ RG_PE1_H_PLL_PREDIV_VAL(0x00)); -+ -+ dev_info(dev, "Xtal is 20MHz\n"); - } - - /* DDS clock inversion */ -- val = phy_read(phy, RG_PE1_LCDDS_CLK_PH_INV_REG); -- val &= ~(RG_PE1_LCDDS_CLK_PH_INV); -- val |= RG_PE1_LCDDS_CLK_PH_INV; -- phy_write(phy, val, RG_PE1_LCDDS_CLK_PH_INV_REG); -+ mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG, -+ RG_PE1_LCDDS_CLK_PH_INV, RG_PE1_LCDDS_CLK_PH_INV); - - /* Set PLL bits */ -- val = phy_read(phy, RG_PE1_H_PLL_REG); -- val &= ~(RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR | -- RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN); -- val |= RG_PE1_H_PLL_BC_VAL(0x02); -- val |= RG_PE1_H_PLL_BP_VAL(0x06); -- val |= RG_PE1_H_PLL_IR_VAL(0x02); -- val |= RG_PE1_H_PLL_IC_VAL(0x01); -- val |= RG_PE1_PLL_DIVEN_VAL(0x02); -- phy_write(phy, val, RG_PE1_H_PLL_REG); -- -- val = phy_read(phy, RG_PE1_H_PLL_BR_REG); -- val &= ~(RG_PE1_H_PLL_BR); -- val |= RG_PE1_H_PLL_BR_VAL(0x00); -- phy_write(phy, val, RG_PE1_H_PLL_BR_REG); -+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, -+ RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR | -+ RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN, -+ RG_PE1_H_PLL_BC_VAL(0x02) | RG_PE1_H_PLL_BP_VAL(0x06) | -+ RG_PE1_H_PLL_IR_VAL(0x02) | RG_PE1_H_PLL_IC_VAL(0x01) | -+ RG_PE1_PLL_DIVEN_VAL(0x02)); -+ -+ mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, -+ RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00)); - - if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ - /* set force mode enable of da_pe1_mstckdiv */ -- val = phy_read(phy, RG_PE1_MSTCKDIV_REG); -- val &= ~(RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV); -- val |= (RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV); -- phy_write(phy, val, RG_PE1_MSTCKDIV_REG); -+ mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, -+ RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV, -+ RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV); - } - } - -@@ -252,13 +240,11 @@ static int mt7621_pci_phy_power_on(struc - struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent); - u32 offset = (instance->index != 1) ? - RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; -- u32 val; - - /* Enable PHY and disable force mode */ -- val = phy_read(mphy, offset); -- val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); -- val |= (RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); -- phy_write(mphy, val, offset); -+ mt7621_phy_rmw(mphy, offset, -+ RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, -+ RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); - - return 0; - } -@@ -269,13 +255,11 @@ static int mt7621_pci_phy_power_off(stru - struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent); - u32 offset = (instance->index != 1) ? - RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; -- u32 val; - - /* Disable PHY */ -- val = phy_read(mphy, offset); -- val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); -- val |= RG_PE1_FRC_PHY_EN; -- phy_write(mphy, val, offset); -+ mt7621_phy_rmw(mphy, offset, -+ RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, -+ RG_PE1_FRC_PHY_EN); - - return 0; - } diff --git a/target/linux/ramips/patches-5.4/0107-staging-mt7621-pci-fix-io-space-and-properly-set-res.patch b/target/linux/ramips/patches-5.4/0107-staging-mt7621-pci-fix-io-space-and-properly-set-res.patch deleted file mode 100644 index 393fd4d5dd..0000000000 --- a/target/linux/ramips/patches-5.4/0107-staging-mt7621-pci-fix-io-space-and-properly-set-res.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 3faf4e1c537de86058fc22a851cd979489b9185e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Wed, 18 Mar 2020 10:44:45 +0100 -Subject: [PATCH] staging: mt7621-pci: fix io space and properly set resource - limits - -Function 'mt7621_pci_parse_request_of_pci_ranges' is using -'of_pci_range_to_resource' to get both mem and io resources. -Internally this function calls to 'pci_address_to_pio' which -returns -1 if io space address is an address > IO_SPACE_LIMIT -which is 0xFFFF for mips. This mt7621 soc has io space in physical -address 0x1e160000. In order to fix this, overwrite invalid io -0xffffffff with properly values from the device tree and set -mapped address of this resource as io port base memory address -calling 'set_io_port_base' function. There is also need to properly -setup resource limits and io and memory windows with properly -parsed values instead of set them as 'no limit' which it is wrong. -For any reason I don't really know legacy driver sets up mem window -as 0xFFFFFFFF and any other value seems to does not work as expected, -so set up also here with same values. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200318094445.19669-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 43 +++++++++++++++++++-------------- - 1 file changed, 25 insertions(+), 18 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -118,6 +118,7 @@ struct mt7621_pcie_port { - * @busn: bus range - * @offset: IO / Memory offset - * @dev: Pointer to PCIe device -+ * @io_map_base: virtual memory base address for io - * @ports: pointer to PCIe port information - * @resets_inverted: depends on chip revision - * reset lines are inverted. -@@ -132,6 +133,7 @@ struct mt7621_pcie { - resource_size_t mem; - resource_size_t io; - } offset; -+ unsigned long io_map_base; - struct list_head ports; - bool resets_inverted; - }; -@@ -291,22 +293,21 @@ static int mt7621_pci_parse_request_of_p - } - - for_each_of_pci_range(&parser, &range) { -- struct resource *res = NULL; -- - switch (range.flags & IORESOURCE_TYPE_BITS) { - case IORESOURCE_IO: -- ioremap(range.cpu_addr, range.size); -- res = &pcie->io; -+ pcie->io_map_base = -+ (unsigned long)ioremap(range.cpu_addr, -+ range.size); -+ of_pci_range_to_resource(&range, node, &pcie->io); -+ pcie->io.start = range.cpu_addr; -+ pcie->io.end = range.cpu_addr + range.size - 1; - pcie->offset.io = 0x00000000UL; - break; - case IORESOURCE_MEM: -- res = &pcie->mem; -+ of_pci_range_to_resource(&range, node, &pcie->mem); - pcie->offset.mem = 0x00000000UL; - break; - } -- -- if (res) -- of_pci_range_to_resource(&range, node, res); - } - - err = of_pci_parse_bus_range(node, &pcie->busn); -@@ -318,6 +319,8 @@ static int mt7621_pci_parse_request_of_p - pcie->busn.flags = IORESOURCE_BUS; - } - -+ set_io_port_base(pcie->io_map_base); -+ - return 0; - } - -@@ -548,6 +551,10 @@ static void mt7621_pcie_enable_ports(str - u32 slot; - u32 val; - -+ /* Setup MEMWIN and IOWIN */ -+ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); -+ pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE); -+ - list_for_each_entry(port, &pcie->ports, list) { - if (port->enabled) { - mt7621_pcie_port_clk_enable(port); -@@ -668,11 +675,17 @@ static int mt7621_pci_probe(struct platf - return err; - } - -+ err = mt7621_pci_parse_request_of_pci_ranges(pcie); -+ if (err) { -+ dev_err(dev, "Error requesting pci resources from ranges"); -+ goto out_release_gpios; -+ } -+ - /* set resources limits */ -- iomem_resource.start = 0; -- iomem_resource.end = ~0UL; /* no limit */ -- ioport_resource.start = 0; -- ioport_resource.end = ~0UL; /* no limit */ -+ iomem_resource.start = pcie->mem.start; -+ iomem_resource.end = pcie->mem.end; -+ ioport_resource.start = pcie->io.start; -+ ioport_resource.end = pcie->io.end; - - mt7621_pcie_init_ports(pcie); - -@@ -685,12 +698,6 @@ static int mt7621_pci_probe(struct platf - - mt7621_pcie_enable_ports(pcie); - -- err = mt7621_pci_parse_request_of_pci_ranges(pcie); -- if (err) { -- dev_err(dev, "Error requesting pci resources from ranges"); -- goto out_release_gpios; -- } -- - setup_cm_memory_region(pcie); - - err = mt7621_pcie_request_resources(pcie, &res); diff --git a/target/linux/ramips/patches-5.4/0108-staging-mt7621-pci-fix-register-to-set-up-virtual-br.patch b/target/linux/ramips/patches-5.4/0108-staging-mt7621-pci-fix-register-to-set-up-virtual-br.patch deleted file mode 100644 index 5b4c461b2f..0000000000 --- a/target/linux/ramips/patches-5.4/0108-staging-mt7621-pci-fix-register-to-set-up-virtual-br.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0a3085ae142d8f5cf905b104bc66db3721a2fa33 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Thu, 19 Mar 2020 10:57:33 +0100 -Subject: [PATCH] staging: mt7621-pci: fix register to set up virtual bridges - -Instead of being using PCI Configuration and Status Register to -set up virtual bridges we are using CONFIG_ADDR Register which is -wrong. Hence, set the correct value. - -Fixes: 9a5e71a68d20 ("staging: mt7621-pci: simplify 'mt7621_pcie_init_virtual_bridges' function") -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200319095733.1557-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -603,7 +603,7 @@ static int mt7621_pcie_init_virtual_brid - if ((pcie_link_status & BIT(i)) == 0) - p2p_br_devnum[i] = n++; - -- pcie_rmw(pcie, RALINK_PCI_CONFIG_ADDR, -+ pcie_rmw(pcie, RALINK_PCI_PCICFG_ADDR, - PCIE_P2P_BR_DEVNUM_MASK_FULL, - (p2p_br_devnum[0] << PCIE_P2P_BR_DEVNUM0_SHIFT) | - (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) | diff --git a/target/linux/ramips/patches-5.4/0109-staging-mt7621-pci-don-t-return-if-get-gpio-fails.patch b/target/linux/ramips/patches-5.4/0109-staging-mt7621-pci-don-t-return-if-get-gpio-fails.patch deleted file mode 100644 index 55abb8999f..0000000000 --- a/target/linux/ramips/patches-5.4/0109-staging-mt7621-pci-don-t-return-if-get-gpio-fails.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 23a788c23ed10e0d79092fcb693dcf0e357e1f7e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Thu, 19 Mar 2020 17:14:16 +0100 -Subject: [PATCH] staging: mt7621-pci: don't return if get gpio fails - -In some platforms gpio's are not used for reset but -for other purposes. Because of that when we try to -get them are valid gpio's but are already assigned -to do other function. To avoid those kind of problems -in those platforms just notice the fail in the kernel -but continue doing normal boot. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200319161416.19033-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -363,10 +363,8 @@ static int mt7621_pcie_parse_port(struct - - port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, - GPIOD_OUT_LOW); -- if (IS_ERR(port->gpio_rst)) { -- dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot); -- return PTR_ERR(port->gpio_rst); -- } -+ if (IS_ERR(port->gpio_rst)) -+ dev_notice(dev, "Failed to get GPIO for PCIe%d\n", slot); - - port->slot = slot; - port->pcie = pcie; diff --git a/target/linux/ramips/patches-5.4/0110-staging-mt7621-pci-phy-avoid-to-create-to-different-.patch b/target/linux/ramips/patches-5.4/0110-staging-mt7621-pci-phy-avoid-to-create-to-different-.patch deleted file mode 100644 index 6d84bfdd5b..0000000000 --- a/target/linux/ramips/patches-5.4/0110-staging-mt7621-pci-phy-avoid-to-create-to-different-.patch +++ /dev/null @@ -1,272 +0,0 @@ -From 91eb47531421f0e8c9bc4594b4a7caa0e59dc83e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 20 Mar 2020 12:01:19 +0100 -Subject: [PATCH] staging: mt7621-pci-phy: avoid to create to different phys - for a dual port one - -This soc has two phy's for the pcie one of them using just a different -register for settig it up but sharing all the rest of the config. Until -now we was presenting this schema as three different phy's in the device -tree using the 'phy-cells' node property to discriminate an index and -setting up a complete phy for the dual port index. This sometimes worked -properly but reconfiguring the same registers twice presents sometimes -some unstable pcie links and the ports was not properly being detected. -The problems only appears on hard resets and soft resets was properly -working. Instead of having this schema just set two phy's in the device -ree and use the 'phy-cells' property to say if the port has or not a dual -port. Doing this configuration and set up becomes easier, LOC is decreased -and the behaviour also gets deterministic with properly and stable pcie -links in both hard and soft resets. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200320110123.9907-2-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 144 ++++++++++-------------- - 1 file changed, 59 insertions(+), 85 deletions(-) - ---- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -@@ -78,31 +78,21 @@ - #define MAX_PHYS 2 - - /** -- * struct mt7621_pci_phy_instance - Mt7621 Pcie PHY device -- * @phy: pointer to the kernel PHY device -- * @port_base: base register -- * @index: internal ID to identify the Mt7621 PCIe PHY -- */ --struct mt7621_pci_phy_instance { -- struct phy *phy; -- void __iomem *port_base; -- u32 index; --}; -- --/** - * struct mt7621_pci_phy - Mt7621 Pcie PHY core - * @dev: pointer to device - * @regmap: kernel regmap pointer -- * @phys: pointer to Mt7621 PHY device -- * @nphys: number of PHY devices for this core -+ * @phy: pointer to the kernel PHY device -+ * @port_base: base register -+ * @has_dual_port: if the phy has dual ports. - * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst' - * needs to be executed. Depends on chip revision. - */ - struct mt7621_pci_phy { - struct device *dev; - struct regmap *regmap; -- struct mt7621_pci_phy_instance **phys; -- int nphys; -+ struct phy *phy; -+ void __iomem *port_base; -+ bool has_dual_port; - bool bypass_pipe_rst; - }; - -@@ -130,23 +120,23 @@ static inline void mt7621_phy_rmw(struct - phy_write(phy, val, reg); - } - --static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy, -- struct mt7621_pci_phy_instance *instance) -+static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) - { -- u32 offset = (instance->index != 1) ? -- RG_PE1_PIPE_REG : RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH; -+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST); -+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC); - -- mt7621_phy_rmw(phy, offset, -- RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC, -- RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); -+ if (phy->has_dual_port) { -+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, -+ 0, RG_PE1_PIPE_RST); -+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH, -+ 0, RG_PE1_PIPE_CMD_FRC); -+ } - } - --static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy, -- struct mt7621_pci_phy_instance *instance) -+static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) - { - struct device *dev = phy->dev; - u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); -- u32 offset; - - reg = (reg >> 6) & 0x7; - /* Set PCIe Port PHY to disable SSC */ -@@ -156,10 +146,13 @@ static void mt7621_set_phy_for_ssc(struc - RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00)); - - /* disable port */ -- offset = (instance->index != 1) ? -- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; -- mt7621_phy_rmw(phy, offset, -- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); -+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG, -+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); -+ -+ if (phy->has_dual_port) { -+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, -+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); -+ } - - if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ - /* Set Pre-divider ratio (for host mode) */ -@@ -223,43 +216,44 @@ static void mt7621_set_phy_for_ssc(struc - - static int mt7621_pci_phy_init(struct phy *phy) - { -- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy); -- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent); -+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); - - if (mphy->bypass_pipe_rst) -- mt7621_bypass_pipe_rst(mphy, instance); -+ mt7621_bypass_pipe_rst(mphy); - -- mt7621_set_phy_for_ssc(mphy, instance); -+ mt7621_set_phy_for_ssc(mphy); - - return 0; - } - - static int mt7621_pci_phy_power_on(struct phy *phy) - { -- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy); -- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent); -- u32 offset = (instance->index != 1) ? -- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; -+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); - - /* Enable PHY and disable force mode */ -- mt7621_phy_rmw(mphy, offset, -- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, -- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN); -+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG, -+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN); -+ -+ if (mphy->has_dual_port) { -+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, -+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN); -+ } - - return 0; - } - - static int mt7621_pci_phy_power_off(struct phy *phy) - { -- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy); -- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent); -- u32 offset = (instance->index != 1) ? -- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH; -+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy); - - /* Disable PHY */ -- mt7621_phy_rmw(mphy, offset, -- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, -- RG_PE1_FRC_PHY_EN); -+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG, -+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); -+ -+ if (mphy->has_dual_port) { -+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH, -+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); -+ } - - return 0; - } -@@ -282,13 +276,15 @@ static struct phy *mt7621_pcie_phy_of_xl - { - struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev); - -- if (args->args_count == 0) -- return mt7621_phy->phys[0]->phy; -- - if (WARN_ON(args->args[0] >= MAX_PHYS)) - return ERR_PTR(-ENODEV); - -- return mt7621_phy->phys[args->args[0]]->phy; -+ mt7621_phy->has_dual_port = args->args[0]; -+ -+ dev_info(dev, "PHY for 0x%08x (dual port = %d)\n", -+ (unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port); -+ -+ return mt7621_phy->phy; - } - - static const struct soc_device_attribute mt7621_pci_quirks_match[] = { -@@ -309,19 +305,11 @@ static int mt7621_pci_phy_probe(struct p - struct phy_provider *provider; - struct mt7621_pci_phy *phy; - struct resource *res; -- int port; -- void __iomem *port_base; - - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - -- phy->nphys = MAX_PHYS; -- phy->phys = devm_kcalloc(dev, phy->nphys, -- sizeof(*phy->phys), GFP_KERNEL); -- if (!phy->phys) -- return -ENOMEM; -- - attr = soc_device_match(mt7621_pci_quirks_match); - if (attr) - phy->bypass_pipe_rst = true; -@@ -335,39 +323,25 @@ static int mt7621_pci_phy_probe(struct p - return -ENXIO; - } - -- port_base = devm_ioremap_resource(dev, res); -- if (IS_ERR(port_base)) { -+ phy->port_base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(phy->port_base)) { - dev_err(dev, "failed to remap phy regs\n"); -- return PTR_ERR(port_base); -+ return PTR_ERR(phy->port_base); - } - -- phy->regmap = devm_regmap_init_mmio(phy->dev, port_base, -+ phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base, - &mt7621_pci_phy_regmap_config); - if (IS_ERR(phy->regmap)) - return PTR_ERR(phy->regmap); - -- for (port = 0; port < MAX_PHYS; port++) { -- struct mt7621_pci_phy_instance *instance; -- struct phy *pphy; -- -- instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); -- if (!instance) -- return -ENOMEM; -- -- phy->phys[port] = instance; -- -- pphy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops); -- if (IS_ERR(phy)) { -- dev_err(dev, "failed to create phy\n"); -- return PTR_ERR(phy); -- } -- -- instance->port_base = port_base; -- instance->phy = pphy; -- instance->index = port; -- phy_set_drvdata(pphy, instance); -+ phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops); -+ if (IS_ERR(phy)) { -+ dev_err(dev, "failed to create phy\n"); -+ return PTR_ERR(phy); - } - -+ phy_set_drvdata(phy->phy, phy); -+ - provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate); - - return PTR_ERR_OR_ZERO(provider); diff --git a/target/linux/ramips/patches-5.4/0111-staging-mt7621-pci-use-only-two-phys-from-device-tre.patch b/target/linux/ramips/patches-5.4/0111-staging-mt7621-pci-use-only-two-phys-from-device-tre.patch deleted file mode 100644 index 61aa80eb76..0000000000 --- a/target/linux/ramips/patches-5.4/0111-staging-mt7621-pci-use-only-two-phys-from-device-tre.patch +++ /dev/null @@ -1,42 +0,0 @@ -From c752b54bda4d772426c5eeb56978d2e41bd525b4 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 20 Mar 2020 12:01:21 +0100 -Subject: [PATCH] staging: mt7621-pci: use only two phys from device tree - -In order to align work with the mt7621-pci-phy part of -the driver and device tree which is now using only two -real phys one of them dual ported properly parse the -device tree and don't call phy initialization for the -slot 1 because is being taking into account when the -phy for the slot 0 is instantiated. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200320110123.9907-4-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -358,7 +358,7 @@ static int mt7621_pcie_parse_port(struct - - snprintf(name, sizeof(name), "pcie-phy%d", slot); - port->phy = devm_phy_get(dev, name); -- if (IS_ERR(port->phy)) -+ if (IS_ERR(port->phy) && slot != 1) - return PTR_ERR(port->phy); - - port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, -@@ -495,6 +495,11 @@ static void mt7621_pcie_init_ports(struc - list_for_each_entry_safe(port, tmp, &pcie->ports, list) { - u32 slot = port->slot; - -+ if (slot == 1) { -+ port->enabled = true; -+ continue; -+ } -+ - err = mt7621_pcie_init_port(port); - if (err) { - dev_err(dev, "Initiating port %d failed\n", slot); diff --git a/target/linux/ramips/patches-5.4/0112-staging-mt7621-pci-change-variable-to-print-for-slot.patch b/target/linux/ramips/patches-5.4/0112-staging-mt7621-pci-change-variable-to-print-for-slot.patch deleted file mode 100644 index 383c896a3e..0000000000 --- a/target/linux/ramips/patches-5.4/0112-staging-mt7621-pci-change-variable-to-print-for-slot.patch +++ /dev/null @@ -1,26 +0,0 @@ -From b59343b7de448c30e5b098484a7c7c5cb300df2f Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 20 Mar 2020 12:01:22 +0100 -Subject: [PATCH] staging: mt7621-pci: change variable to print for slot - -We are using the counter to print the slot which has been -enabled. Use the correct associated slot for the port instead. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200320110123.9907-5-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -562,7 +562,7 @@ static void mt7621_pcie_enable_ports(str - if (port->enabled) { - mt7621_pcie_port_clk_enable(port); - mt7621_pcie_enable_port(port); -- dev_info(dev, "PCIE%d enabled\n", num_slots_enabled); -+ dev_info(dev, "PCIE%d enabled\n", port->slot); - num_slots_enabled++; - } - } diff --git a/target/linux/ramips/patches-5.4/0113-staging-mt7621-pci-be-sure-gpio-descriptor-is-null-o.patch b/target/linux/ramips/patches-5.4/0113-staging-mt7621-pci-be-sure-gpio-descriptor-is-null-o.patch deleted file mode 100644 index bf6fdf1d49..0000000000 --- a/target/linux/ramips/patches-5.4/0113-staging-mt7621-pci-be-sure-gpio-descriptor-is-null-o.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 87068309300c707d659ce79232eae827604804a4 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 20 Mar 2020 12:01:23 +0100 -Subject: [PATCH] staging: mt7621-pci: be sure gpio descriptor is null on fails - -Function 'devm_gpiod_get_index_optional' returns NULL if the -descriptor is invalid and the error associated for the error -pointer is ENOENT. Sometimes if the pin is just assigned the -error associated for the pointer might not be ENOENT but other. -In order to avoid weirds behaviours if this happen set descriptor -to NULL in the driver port structure. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200320110123.9907-6-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -363,8 +363,10 @@ static int mt7621_pcie_parse_port(struct - - port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, - GPIOD_OUT_LOW); -- if (IS_ERR(port->gpio_rst)) -+ if (IS_ERR(port->gpio_rst)) { - dev_notice(dev, "Failed to get GPIO for PCIe%d\n", slot); -+ port->gpio_rst = NULL; -+ } - - port->slot = slot; - port->pcie = pcie; diff --git a/target/linux/ramips/patches-5.4/0114-staging-mt7621-pci-avoid-to-poweroff-the-phy-for-slo.patch b/target/linux/ramips/patches-5.4/0114-staging-mt7621-pci-avoid-to-poweroff-the-phy-for-slo.patch deleted file mode 100644 index d733e58537..0000000000 --- a/target/linux/ramips/patches-5.4/0114-staging-mt7621-pci-avoid-to-poweroff-the-phy-for-slo.patch +++ /dev/null @@ -1,79 +0,0 @@ -From d81fe3c13aa6f4ab1ec318212d2007175e6d05aa Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 20 Mar 2020 16:38:37 +0100 -Subject: [PATCH] staging: mt7621-pci: avoid to poweroff the phy for slot one - -Phy for slot 0 and 1 is shared and handled properly in slot 0. -If there is only one port in use,(slot 0) we shall not call the -'phy_power_off' function with an invalid slot because kernel -will crash with an unaligned access fault like the following: - -mt7621-pci 1e140000.pcie: Error applying setting, reverse things back -mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1) -mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0) -mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz -mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz -mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) -Unhandled kernel unaligned access[#1]: -CPU: 3 PID: 111 Comm: kworker/3:2 Not tainted 5.6.0-rc3-00347-g825c6f470c62-dirty #9 -Workqueue: events deferred_probe_work_func -$ 0 : 00000000 00000001 5f60d043 8fe1ba80 -$ 4 : 0000010d 01eb9000 00000000 00000000 -$ 8 : 294b4c00 80940000 00000008 000000ce -$12 : 2e303030 00000000 00000000 65696370 -$16 : ffffffed 0000010d 8e373cd0 8214c1e0 -$20 : 00000000 82144c80 82144680 8214c250 -$24 : 00000018 803ef8f4 -$28 : 8e372000 8e373c60 8214c080 803940e8 -Hi : 00000125 -Lo : 122f2000 -epc : 807b3328 mutex_lock+0x8/0x44 -ra : 803940e8 phy_power_off+0x28/0xb0 -Status: 1100fc03 KERNEL EXL IE -Cause : 00800010 (ExcCode 04) -BadVA : 0000010d -PrId : 0001992f (MIPS 1004Kc) -Modules linked in: -Process kworker/3:2 (pid: 111, threadinfo=(ptrval), task=(ptrval), tls=00000000) -Stack : 8e373cd0 803fe4f4 8e372000 8e373c90 8214c080 804fde1c 8e373c98 808d62f4 - 8e373c78 00000000 8214c254 804fe648 1e160000 804f27b8 00000001 808d62f4 - 00000000 00000001 8214c228 808d62f4 80930000 809a0000 8fd47e10 808d63d4 - 808d62d4 8fd47e10 808d0000 808d0000 8e373cd0 8e373cd0 809e2a74 809db510 - 809db510 00000006 00000001 00000000 00000000 00000000 01000000 1e1440ff - ... -Call Trace: -[<807b3328>] mutex_lock+0x8/0x44 -[<803940e8>] phy_power_off+0x28/0xb0 -[<804fe648>] mt7621_pci_probe+0xc20/0xd18 -[<80402ab8>] platform_drv_probe+0x40/0x94 -[<80400a74>] really_probe+0x104/0x364 -[<803feb74>] bus_for_each_drv+0x84/0xdc -[<80400924>] __device_attach+0xdc/0x120 -[<803ffb5c>] bus_probe_device+0xa0/0xbc -[<80400124>] deferred_probe_work_func+0x7c/0xbc -[<800420e8>] process_one_work+0x230/0x450 -[<80042638>] worker_thread+0x330/0x5fc -[<80048eb0>] kthread+0x12c/0x134 -[<80007438>] ret_from_kernel_thread+0x14/0x1c -Code: 24050002 27bdfff8 8f830000 14a00005 00000000 00600825 e0810000 1020fffa - -Fixes: bf516f413f4e ("staging: mt7621-pci: use only two phys from device tree") -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200320153837.20415-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -517,7 +517,8 @@ static void mt7621_pcie_init_ports(struc - if (!mt7621_pcie_port_is_linkup(port)) { - dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", - slot); -- phy_power_off(port->phy); -+ if (slot != 1) -+ phy_power_off(port->phy); - mt7621_control_assert(port); - mt7621_pcie_port_clk_disable(port); - port->enabled = false; diff --git a/target/linux/ramips/patches-5.4/0115-staging-mt7621-pci-delete-release-gpios-related-code.patch b/target/linux/ramips/patches-5.4/0115-staging-mt7621-pci-delete-release-gpios-related-code.patch deleted file mode 100644 index 5bfd205691..0000000000 --- a/target/linux/ramips/patches-5.4/0115-staging-mt7621-pci-delete-release-gpios-related-code.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 9d789a7728c37e8730b6a9cca60cf155f18537ea Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sat, 21 Mar 2020 08:26:50 +0100 -Subject: [PATCH] staging: mt7621-pci: delete release gpios related code - -Making gpio8 and gpio9 vendor specific and putting them -into the specific dts file makes not needed to release -gpios anymore because we are not occupying those pins -in the first place if it is not necessary. When the -device tree is parsed we can also check and return for -the error because we rely in the fact that the related -device for the board is correct. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200321072650.7784-3-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 27 +++++++-------------------- - 1 file changed, 7 insertions(+), 20 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -364,8 +364,8 @@ static int mt7621_pcie_parse_port(struct - port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, - GPIOD_OUT_LOW); - if (IS_ERR(port->gpio_rst)) { -- dev_notice(dev, "Failed to get GPIO for PCIe%d\n", slot); -- port->gpio_rst = NULL; -+ dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot); -+ return PTR_ERR(port->gpio_rst); - } - - port->slot = slot; -@@ -474,15 +474,6 @@ static void mt7621_pcie_reset_ep_deasser - mdelay(PERST_DELAY_MS); - } - --static void mt7621_pcie_release_gpios(struct mt7621_pcie *pcie) --{ -- struct mt7621_pcie_port *port; -- -- list_for_each_entry(port, &pcie->ports, list) -- if (port->gpio_rst) -- gpiod_put(port->gpio_rst); --} -- - static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) - { - struct device *dev = pcie->dev; -@@ -684,7 +675,7 @@ static int mt7621_pci_probe(struct platf - err = mt7621_pci_parse_request_of_pci_ranges(pcie); - if (err) { - dev_err(dev, "Error requesting pci resources from ranges"); -- goto out_release_gpios; -+ return err; - } - - /* set resources limits */ -@@ -698,8 +689,7 @@ static int mt7621_pci_probe(struct platf - err = mt7621_pcie_init_virtual_bridges(pcie); - if (err) { - dev_err(dev, "Nothing is connected in virtual bridges. Exiting..."); -- err = 0; -- goto out_release_gpios; -+ return 0; - } - - mt7621_pcie_enable_ports(pcie); -@@ -709,19 +699,16 @@ static int mt7621_pci_probe(struct platf - err = mt7621_pcie_request_resources(pcie, &res); - if (err) { - dev_err(dev, "Error requesting resources\n"); -- goto out_release_gpios; -+ return err; - } - - err = mt7621_pcie_register_host(bridge, &res); - if (err) { - dev_err(dev, "Error registering host\n"); -- goto out_release_gpios; -+ return err; - } - --out_release_gpios: -- mt7621_pcie_release_gpios(pcie); -- -- return err; -+ return 0; - } - - static const struct of_device_id mt7621_pci_ids[] = { diff --git a/target/linux/ramips/patches-5.4/0116-staging-mt7621-pci-use-builtin_platform_driver.patch b/target/linux/ramips/patches-5.4/0116-staging-mt7621-pci-use-builtin_platform_driver.patch deleted file mode 100644 index b333bb326b..0000000000 --- a/target/linux/ramips/patches-5.4/0116-staging-mt7621-pci-use-builtin_platform_driver.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 60a15339ceab9fc2a6cdc85fd54b66b2c947ab4e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sat, 21 Mar 2020 14:36:21 +0100 -Subject: [PATCH] staging: mt7621-pci: use builtin_platform_driver() - -Macro builtin_platform_driver can be used for builtin drivers -that don't do anything in driver init. So, use the macro -builtin_platform_driver and remove some boilerplate code. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200321133624.31388-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -725,9 +725,4 @@ static struct platform_driver mt7621_pci - }, - }; - --static int __init mt7621_pci_init(void) --{ -- return platform_driver_register(&mt7621_pci_driver); --} -- --module_init(mt7621_pci_init); -+builtin_platform_driver(mt7621_pci_driver); diff --git a/target/linux/ramips/patches-5.4/0117-staging-mt7621-pci-phy-use-builtin_platform_driver.patch b/target/linux/ramips/patches-5.4/0117-staging-mt7621-pci-phy-use-builtin_platform_driver.patch deleted file mode 100644 index e55def40f5..0000000000 --- a/target/linux/ramips/patches-5.4/0117-staging-mt7621-pci-phy-use-builtin_platform_driver.patch +++ /dev/null @@ -1,32 +0,0 @@ -From ffe3dee4081055b4f58bc50dd3f5c97de42cf126 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sat, 21 Mar 2020 14:36:23 +0100 -Subject: [PATCH] staging: mt7621-pci-phy: use builtin_platform_driver() - -Macro builtin_platform_driver can be used for builtin drivers -that don't do anything in driver init. So, use the macro -builtin_platform_driver and remove some boilerplate code. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200321133624.31388-3-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -@@ -361,12 +361,7 @@ static struct platform_driver mt7621_pci - }, - }; - --static int __init mt7621_pci_phy_drv_init(void) --{ -- return platform_driver_register(&mt7621_pci_phy_driver); --} -- --module_init(mt7621_pci_phy_drv_init); -+builtin_platform_driver(mt7621_pci_phy_driver); - - MODULE_AUTHOR("Sergio Paracuellos "); - MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver"); diff --git a/target/linux/ramips/patches-5.4/0118-staging-mt7621-pci-phy-re-do-xtal_mode-detection.patch b/target/linux/ramips/patches-5.4/0118-staging-mt7621-pci-phy-re-do-xtal_mode-detection.patch deleted file mode 100644 index 9eb8345144..0000000000 --- a/target/linux/ramips/patches-5.4/0118-staging-mt7621-pci-phy-re-do-xtal_mode-detection.patch +++ /dev/null @@ -1,68 +0,0 @@ -From ff83e3023cb8fc3b5dfc12e0c91bf1eb9dc4c4c6 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sat, 21 Mar 2020 14:36:24 +0100 -Subject: [PATCH] staging: mt7621-pci-phy: re-do 'xtal_mode' detection - -Detection of the Xtal mode is using magic numbers that -can be avoided using properly some definitions and a more -accurate variable name from 'reg' into 'xtal_mode'. This -increase readability. - -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200321133624.31388-4-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 15 ++++++++++----- - 1 file changed, 10 insertions(+), 5 deletions(-) - ---- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c -@@ -75,6 +75,9 @@ - - #define RG_PE1_FRC_MSTCKDIV BIT(5) - -+#define XTAL_MODE_SEL_SHIFT 6 -+#define XTAL_MODE_SEL_MASK 0x7 -+ - #define MAX_PHYS 2 - - /** -@@ -136,9 +139,11 @@ static void mt7621_bypass_pipe_rst(struc - static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) - { - struct device *dev = phy->dev; -- u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); -+ u32 xtal_mode; -+ -+ xtal_mode = (rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0) -+ >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; - -- reg = (reg >> 6) & 0x7; - /* Set PCIe Port PHY to disable SSC */ - /* Debug Xtal Type */ - mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG, -@@ -154,13 +159,13 @@ static void mt7621_set_phy_for_ssc(struc - RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); - } - -- if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ -+ if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ - /* Set Pre-divider ratio (for host mode) */ - mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, - RG_PE1_H_PLL_PREDIV, - RG_PE1_H_PLL_PREDIV_VAL(0x01)); - dev_info(dev, "Xtal is 40MHz\n"); -- } else if (reg >= 6) { /* 25MHz Xal */ -+ } else if (xtal_mode >= 6) { /* 25MHz Xal */ - mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, - RG_PE1_H_PLL_PREDIV, - RG_PE1_H_PLL_PREDIV_VAL(0x00)); -@@ -206,7 +211,7 @@ static void mt7621_set_phy_for_ssc(struc - mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, - RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00)); - -- if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ -+ if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ - /* set force mode enable of da_pe1_mstckdiv */ - mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, - RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV, diff --git a/target/linux/ramips/patches-5.4/0119-staging-mt7621-pci-avoid-to-set-iomem_resource-addre.patch b/target/linux/ramips/patches-5.4/0119-staging-mt7621-pci-avoid-to-set-iomem_resource-addre.patch deleted file mode 100644 index 9af46f4196..0000000000 --- a/target/linux/ramips/patches-5.4/0119-staging-mt7621-pci-avoid-to-set-iomem_resource-addre.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 4f0f36b67564311a4ce4441510ef94848febbab2 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sun, 22 Mar 2020 08:21:28 +0100 -Subject: [PATCH] staging: mt7621-pci: avoid to set 'iomem_resource' addresses - -Setting up kernel resource 'iomem_resource' for PCI with -addresses parsed from device tree gots into a conflict within -the usb xhci driver: - -xhci-mtk 1e1c0000.xhci: can't request region for resource [mem 0x1e1c0000-0x1e1c0fff] -xhci-mtk: probe of 1e1c0000.xhci failed with error -16 - -Don't assign it and maintain the default addresses for this -resource seems to fix the problem. Checking legacy driver it -is being only setting the 'ioport_resource'. - -Fixes: 09dd629eeabb ("staging: mt7621-pci: fix io space and properly set resource limits") -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200322072128.4454-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -679,8 +679,6 @@ static int mt7621_pci_probe(struct platf - } - - /* set resources limits */ -- iomem_resource.start = pcie->mem.start; -- iomem_resource.end = pcie->mem.end; - ioport_resource.start = pcie->io.start; - ioport_resource.end = pcie->io.end; - diff --git a/target/linux/ramips/patches-5.4/0120-staging-mt7621-pci-properly-power-off-dual-ported-pc.patch b/target/linux/ramips/patches-5.4/0120-staging-mt7621-pci-properly-power-off-dual-ported-pc.patch deleted file mode 100644 index 9efcb8011a..0000000000 --- a/target/linux/ramips/patches-5.4/0120-staging-mt7621-pci-properly-power-off-dual-ported-pc.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 5fcded5e857cf66c9592e4be28c4dab4520c9177 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Thu, 9 Apr 2020 13:16:52 +0200 -Subject: [PATCH] staging: mt7621-pci: properly power off dual-ported pcie phy - -Pcie phy for pcie0 and pcie1 is shared using a dual ported -one. Current code was assuming that if nothing is connected -in pcie0 it won't be also nothing connected in pcie1. This -assumtion is wrong for some devices such us 'Mikrotik rbm33g' -and 'ZyXEL LTE3301-PLUS' where only connecting a card to the -second bus on the phy is possible. For such devices kernel -hangs in the same point because of the wrong poweroff of the -phy getting the following trace: - -mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1) -mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0) -mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz -mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz -mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK) -[hangs] - -The wrong assumption is located in the 'mt7621_pcie_init_ports' -function where we are just making a power off of the phy for -slots 0 and 2 if nothing is connected in them. Hence, only -poweroff the phy if nothing is connected in both slot 0 and -slot 1 avoiding the kernel to hang. - -Fixes: 5737cfe87a9c ("staging: mt7621-pci: avoid to poweroff the phy for slot one") -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200409111652.30964-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -502,17 +502,25 @@ static void mt7621_pcie_init_ports(struc - - mt7621_pcie_reset_ep_deassert(pcie); - -+ tmp = NULL; - list_for_each_entry(port, &pcie->ports, list) { - u32 slot = port->slot; - - if (!mt7621_pcie_port_is_linkup(port)) { - dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", - slot); -- if (slot != 1) -- phy_power_off(port->phy); - mt7621_control_assert(port); - mt7621_pcie_port_clk_disable(port); - port->enabled = false; -+ -+ if (slot == 0) { -+ tmp = port; -+ continue; -+ } -+ -+ if (slot == 1 && tmp && !tmp->enabled) -+ phy_power_off(tmp->phy); -+ - } - } - } diff --git a/target/linux/ramips/patches-5.4/0121-staging-mt7621-pci-fix-PCIe-interrupt-mapping.patch b/target/linux/ramips/patches-5.4/0121-staging-mt7621-pci-fix-PCIe-interrupt-mapping.patch deleted file mode 100644 index 68de6df2db..0000000000 --- a/target/linux/ramips/patches-5.4/0121-staging-mt7621-pci-fix-PCIe-interrupt-mapping.patch +++ /dev/null @@ -1,157 +0,0 @@ -From fab6710e4c51f4eb622f95a08322ab5fdbe3f295 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 13 Apr 2020 07:59:42 +0200 -Subject: [PATCH] staging: mt7621-pci: fix PCIe interrupt mapping - -MT7621 has three assigned interrupts for the pcie. This -interrupts should properly being mapped taking into account -which devices are finally connected in which bus according -to link status. So the irq mappings should be as follows -according to link status (three bits indicating which devices -are link up): - -* For PCIe Bus 1 slot 0: - - status = 0x2 || status = 0x6 => IRQ = pcie1_irq (24). - - status = 0x4 => IRQ = pcie2_irq (25). - - default => IRQ = pcie0_irq (23). -* For PCIe Bus 2 slot 0: - - status = 0x5 || status = 0x6 => IRQ = pcie2_irq (25). - - default => IRQ = pcie1_irq (24). -* For PCIe Bus 2 slot 1: - - status = 0x5 || status = 0x6 => IRQ = pcie2_irq (25). - - default => IRQ = pcie1_irq (24). -* For PCIe Bus 3 any slot: - - default => IRQ = pcie2_irq (25). - -Because of this, the function 'of_irq_parse_and_map_pci' cannot -be used and we need to change device tree information from using -the 'interrupt-map' and 'interrupt-map-mask' properties into an -'interrupts' property to be able to get irq information from the -ports using the 'platform_get_irq' and storing an 'irq-map' into -the pcie driver data node to properly map correct irq using a -new 'mt7621_map_irq' function where this map will be read and the -correct irq returned. - -Fixes: 46d093124df4 ("staging: mt7621-pci: improve interrupt mapping") -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20200413055942.2714-1-sergio.paracuellos@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/mt7621-dts/mt7621.dtsi | 9 +++---- - drivers/staging/mt7621-pci/pci-mt7621.c | 36 +++++++++++++++++++++++-- - 2 files changed, 38 insertions(+), 7 deletions(-) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -97,6 +97,7 @@ - * @pcie_rst: pointer to port reset control - * @gpio_rst: gpio reset - * @slot: port slot -+ * @irq: GIC irq - * @enabled: indicates if port is enabled - */ - struct mt7621_pcie_port { -@@ -107,6 +108,7 @@ struct mt7621_pcie_port { - struct reset_control *pcie_rst; - struct gpio_desc *gpio_rst; - u32 slot; -+ int irq; - bool enabled; - }; - -@@ -120,6 +122,7 @@ struct mt7621_pcie_port { - * @dev: Pointer to PCIe device - * @io_map_base: virtual memory base address for io - * @ports: pointer to PCIe port information -+ * @irq_map: irq mapping info according pcie link status - * @resets_inverted: depends on chip revision - * reset lines are inverted. - */ -@@ -135,6 +138,7 @@ struct mt7621_pcie { - } offset; - unsigned long io_map_base; - struct list_head ports; -+ int irq_map[PCIE_P2P_MAX]; - bool resets_inverted; - }; - -@@ -279,6 +283,16 @@ static void setup_cm_memory_region(struc - } - } - -+static int mt7621_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) -+{ -+ struct mt7621_pcie *pcie = pdev->bus->sysdata; -+ struct device *dev = pcie->dev; -+ int irq = pcie->irq_map[slot]; -+ -+ dev_info(dev, "bus=%d slot=%d irq=%d\n", pdev->bus->number, slot, irq); -+ return irq; -+} -+ - static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie) - { - struct device *dev = pcie->dev; -@@ -330,6 +344,7 @@ static int mt7621_pcie_parse_port(struct - { - struct mt7621_pcie_port *port; - struct device *dev = pcie->dev; -+ struct platform_device *pdev = to_platform_device(dev); - struct device_node *pnode = dev->of_node; - struct resource regs; - char name[10]; -@@ -371,6 +386,12 @@ static int mt7621_pcie_parse_port(struct - port->slot = slot; - port->pcie = pcie; - -+ port->irq = platform_get_irq(pdev, slot); -+ if (port->irq < 0) { -+ dev_err(dev, "Failed to get IRQ for PCIe%d\n", slot); -+ return -ENXIO; -+ } -+ - INIT_LIST_HEAD(&port->list); - list_add_tail(&port->list, &pcie->ports); - -@@ -585,13 +606,15 @@ static int mt7621_pcie_init_virtual_brid - { - u32 pcie_link_status = 0; - u32 n; -- int i; -+ int i = 0; - u32 p2p_br_devnum[PCIE_P2P_MAX]; -+ int irqs[PCIE_P2P_MAX]; - struct mt7621_pcie_port *port; - - list_for_each_entry(port, &pcie->ports, list) { - u32 slot = port->slot; - -+ irqs[i++] = port->irq; - if (port->enabled) - pcie_link_status |= BIT(slot); - } -@@ -614,6 +637,15 @@ static int mt7621_pcie_init_virtual_brid - (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) | - (p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT)); - -+ /* Assign IRQs */ -+ n = 0; -+ for (i = 0; i < PCIE_P2P_MAX; i++) -+ if (pcie_link_status & BIT(i)) -+ pcie->irq_map[n++] = irqs[i]; -+ -+ for (i = n; i < PCIE_P2P_MAX; i++) -+ pcie->irq_map[i] = -1; -+ - return 0; - } - -@@ -638,7 +670,7 @@ static int mt7621_pcie_register_host(str - host->busnr = pcie->busn.start; - host->dev.parent = pcie->dev; - host->ops = &mt7621_pci_ops; -- host->map_irq = of_irq_parse_and_map_pci; -+ host->map_irq = mt7621_map_irq; - host->swizzle_irq = pci_common_swizzle; - host->sysdata = pcie; - diff --git a/target/linux/ramips/patches-5.4/0122-mips-ralink-enable-zboot-support.patch b/target/linux/ramips/patches-5.4/0122-mips-ralink-enable-zboot-support.patch deleted file mode 100644 index 1123cce3a5..0000000000 --- a/target/linux/ramips/patches-5.4/0122-mips-ralink-enable-zboot-support.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 1f0400d0e2c410b04f246aefb2e9b5155eb4b0bf Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Tue, 13 Oct 2020 10:05:47 +0800 -Subject: mips: ralink: enable zboot support - -Some of these ralink devices come with an ancient u-boot which can't -extract LZMA properly when image gets too big. -Enable zboot support to get a self-extracting kernel instead of relying -on broken u-boot support. - -Signed-off-by: Chuanhong Guo -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -631,6 +631,7 @@ config RALINK - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_MIPS16 -+ select SYS_SUPPORTS_ZBOOT - select SYS_HAS_EARLY_PRINTK - select CLKDEV_LOOKUP - select ARCH_HAS_RESET_CONTROLLER diff --git a/target/linux/ramips/patches-5.4/0123-mips-ralink-manage-low-reset-lines.patch b/target/linux/ramips/patches-5.4/0123-mips-ralink-manage-low-reset-lines.patch deleted file mode 100644 index bdf98f223c..0000000000 --- a/target/linux/ramips/patches-5.4/0123-mips-ralink-manage-low-reset-lines.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 3f9ef7785a9cd69cb75f5e2ea4ca79a24752e496 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Wed, 3 Feb 2021 10:21:41 +0100 -Subject: MIPS: ralink: manage low reset lines - -Reset lines with indices smaller than 8 are currently considered invalid -by the rt2880-reset reset controller. - -The MT7621 SoC uses a number of these low reset lines. The DTS defines -reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2. -As a result of the above restriction, these resets cannot be asserted or -de-asserted by the reset controller. In cases where the bootloader does -not de-assert these lines, this results in e.g. the MT7621's internal -switch staying in reset. - -Change the reset controller to only ignore the system reset, so all -reset lines with index greater than 0 are considered valid. - -Signed-off-by: Sander Vanheule -Acked-by: John Crispin -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ralink/reset.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/ralink/reset.c -+++ b/arch/mips/ralink/reset.c -@@ -27,7 +27,7 @@ static int ralink_assert_device(struct r - { - u32 val; - -- if (id < 8) -+ if (id == 0) - return -1; - - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); -@@ -42,7 +42,7 @@ static int ralink_deassert_device(struct - { - u32 val; - -- if (id < 8) -+ if (id == 0) - return -1; - - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); diff --git a/target/linux/ramips/patches-5.4/0200-linkit_bootstrap.patch b/target/linux/ramips/patches-5.4/0200-linkit_bootstrap.patch deleted file mode 100644 index 9142faaf43..0000000000 --- a/target/linux/ramips/patches-5.4/0200-linkit_bootstrap.patch +++ /dev/null @@ -1,97 +0,0 @@ ---- a/drivers/misc/Makefile -+++ b/drivers/misc/Makefile -@@ -52,6 +52,7 @@ obj-$(CONFIG_ECHO) += echo/ - obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o - obj-$(CONFIG_CXL_BASE) += cxl/ - obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o -+obj-$(CONFIG_SOC_MT7620) += linkit.o - obj-$(CONFIG_OCXL) += ocxl/ - obj-y += cardreader/ - obj-$(CONFIG_PVPANIC) += pvpanic.o ---- /dev/null -+++ b/drivers/misc/linkit.c -@@ -0,0 +1,84 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * publishhed by the Free Software Foundation. -+ * -+ * Copyright (C) 2015 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define LINKIT_LATCH_GPIO 11 -+ -+struct linkit_hw_data { -+ char board[16]; -+ char rev[16]; -+}; -+ -+static void sanify_string(char *s) -+{ -+ int i; -+ -+ for (i = 0; i < 15; i++) -+ if (s[i] <= 0x20) -+ s[i] = '\0'; -+ s[15] = '\0'; -+} -+ -+static int linkit_probe(struct platform_device *pdev) -+{ -+ struct linkit_hw_data hw; -+ struct mtd_info *mtd; -+ size_t retlen; -+ int ret; -+ -+ mtd = get_mtd_device_nm("factory"); -+ if (IS_ERR(mtd)) -+ return PTR_ERR(mtd); -+ -+ ret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw); -+ put_mtd_device(mtd); -+ -+ sanify_string(hw.board); -+ sanify_string(hw.rev); -+ -+ dev_info(&pdev->dev, "Version : %s\n", hw.board); -+ dev_info(&pdev->dev, "Revision : %s\n", hw.rev); -+ -+ if (!strcmp(hw.board, "LINKITS7688")) { -+ dev_info(&pdev->dev, "setting up bootstrap latch\n"); -+ -+ if (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, "bootstrap")) { -+ dev_err(&pdev->dev, "failed to setup bootstrap gpio\n"); -+ return -1; -+ } -+ gpio_direction_output(LINKIT_LATCH_GPIO, 0); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id linkit_match[] = { -+ { .compatible = "mediatek,linkit" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, linkit_match); -+ -+static struct platform_driver linkit_driver = { -+ .probe = linkit_probe, -+ .driver = { -+ .name = "mtk-linkit", -+ .owner = THIS_MODULE, -+ .of_match_table = linkit_match, -+ }, -+}; -+ -+int __init linkit_init(void) -+{ -+ return platform_driver_register(&linkit_driver); -+} -+late_initcall_sync(linkit_init); diff --git a/target/linux/ramips/patches-5.4/0300-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch b/target/linux/ramips/patches-5.4/0300-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch deleted file mode 100644 index ba844fed0f..0000000000 --- a/target/linux/ramips/patches-5.4/0300-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch +++ /dev/null @@ -1,1400 +0,0 @@ -From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 1 Apr 2020 02:07:58 +0800 -Subject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand - flash controller - -This patch adds NAND flash controller driver for MediaTek MT7621 SoC. - -The NAND flash controller is similar with controllers described in -mtk_nand.c, except that the controller from MT7621 doesn't support DMA -transmission, and some registers' offset and fields are different. - -Signed-off-by: Weijie Gao ---- - drivers/mtd/nand/raw/Kconfig | 8 + - drivers/mtd/nand/raw/Makefile | 1 + - drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 1357 insertions(+) - create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c - ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -391,6 +391,14 @@ config MTD_NAND_QCOM - Enables support for NAND flash chips on SoCs containing the EBI2 NAND - controller. This controller is found on IPQ806x SoC. - -+config MTD_NAND_MT7621 -+ tristate "MT7621 NAND controller" -+ depends on SOC_MT7621 || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ Enables support for NAND controller on MT7621 SoC. -+ This driver uses PIO mode for data transmission instead of DMA mode. -+ - config MTD_NAND_MTK - tristate "MTK NAND controller" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -52,6 +52,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n - obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ - obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o -+obj-$(CONFIG_MTD_NAND_MT7621) += mt7621_nand.o - obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o - obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o - obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o ---- /dev/null -+++ b/drivers/mtd/nand/raw/mt7621_nand.c -@@ -0,0 +1,1350 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * MediaTek MT7621 NAND Flash Controller driver -+ * -+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. -+ * -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* NFI core registers */ -+#define NFI_CNFG 0x000 -+#define CNFG_OP_MODE_S 12 -+#define CNFG_OP_MODE_M GENMASK(14, 12) -+#define CNFG_OP_CUSTOM 6 -+#define CNFG_AUTO_FMT_EN BIT(9) -+#define CNFG_HW_ECC_EN BIT(8) -+#define CNFG_BYTE_RW BIT(6) -+#define CNFG_READ_MODE BIT(1) -+ -+#define NFI_PAGEFMT 0x004 -+#define PAGEFMT_FDM_ECC_S 12 -+#define PAGEFMT_FDM_ECC_M GENMASK(15, 12) -+#define PAGEFMT_FDM_S 8 -+#define PAGEFMT_FDM_M GENMASK(11, 8) -+#define PAGEFMT_SPARE_S 4 -+#define PAGEFMT_SPARE_M GENMASK(5, 4) -+#define PAGEFMT_PAGE_S 0 -+#define PAGEFMT_PAGE_M GENMASK(1, 0) -+ -+#define NFI_CON 0x008 -+#define CON_NFI_SEC_S 12 -+#define CON_NFI_SEC_M GENMASK(15, 12) -+#define CON_NFI_BWR BIT(9) -+#define CON_NFI_BRD BIT(8) -+#define CON_NFI_RST BIT(1) -+#define CON_FIFO_FLUSH BIT(0) -+ -+#define NFI_ACCCON 0x00c -+#define ACCCON_POECS_S 28 -+#define ACCCON_POECS_MAX 0x0f -+#define ACCCON_POECS_DEF 3 -+#define ACCCON_PRECS_S 22 -+#define ACCCON_PRECS_MAX 0x3f -+#define ACCCON_PRECS_DEF 3 -+#define ACCCON_C2R_S 16 -+#define ACCCON_C2R_MAX 0x3f -+#define ACCCON_C2R_DEF 7 -+#define ACCCON_W2R_S 12 -+#define ACCCON_W2R_MAX 0x0f -+#define ACCCON_W2R_DEF 7 -+#define ACCCON_WH_S 8 -+#define ACCCON_WH_MAX 0x0f -+#define ACCCON_WH_DEF 15 -+#define ACCCON_WST_S 4 -+#define ACCCON_WST_MAX 0x0f -+#define ACCCON_WST_DEF 15 -+#define ACCCON_WST_MIN 3 -+#define ACCCON_RLT_S 0 -+#define ACCCON_RLT_MAX 0x0f -+#define ACCCON_RLT_DEF 15 -+#define ACCCON_RLT_MIN 3 -+ -+#define NFI_CMD 0x020 -+ -+#define NFI_ADDRNOB 0x030 -+#define ADDR_ROW_NOB_S 4 -+#define ADDR_ROW_NOB_M GENMASK(6, 4) -+#define ADDR_COL_NOB_S 0 -+#define ADDR_COL_NOB_M GENMASK(2, 0) -+ -+#define NFI_COLADDR 0x034 -+#define NFI_ROWADDR 0x038 -+ -+#define NFI_STRDATA 0x040 -+#define STR_DATA BIT(0) -+ -+#define NFI_CNRNB 0x044 -+#define CB2R_TIME_S 4 -+#define CB2R_TIME_M GENMASK(7, 4) -+#define STR_CNRNB BIT(0) -+ -+#define NFI_DATAW 0x050 -+#define NFI_DATAR 0x054 -+ -+#define NFI_PIO_DIRDY 0x058 -+#define PIO_DIRDY BIT(0) -+ -+#define NFI_STA 0x060 -+#define STA_NFI_FSM_S 16 -+#define STA_NFI_FSM_M GENMASK(19, 16) -+#define STA_FSM_CUSTOM_DATA 14 -+#define STA_BUSY BIT(8) -+#define STA_ADDR BIT(1) -+#define STA_CMD BIT(0) -+ -+#define NFI_ADDRCNTR 0x070 -+#define SEC_CNTR_S 12 -+#define SEC_CNTR_M GENMASK(15, 12) -+#define SEC_ADDR_S 0 -+#define SEC_ADDR_M GENMASK(9, 0) -+ -+#define NFI_CSEL 0x090 -+#define CSEL_S 0 -+#define CSEL_M GENMASK(1, 0) -+ -+#define NFI_FDM0L 0x0a0 -+#define NFI_FDML(n) (0x0a0 + ((n) << 3)) -+ -+#define NFI_FDM0M 0x0a4 -+#define NFI_FDMM(n) (0x0a4 + ((n) << 3)) -+ -+#define NFI_MASTER_STA 0x210 -+#define MAS_ADDR GENMASK(11, 9) -+#define MAS_RD GENMASK(8, 6) -+#define MAS_WR GENMASK(5, 3) -+#define MAS_RDDLY GENMASK(2, 0) -+ -+/* ECC engine registers */ -+#define ECC_ENCCON 0x000 -+#define ENC_EN BIT(0) -+ -+#define ECC_ENCCNFG 0x004 -+#define ENC_CNFG_MSG_S 16 -+#define ENC_CNFG_MSG_M GENMASK(28, 16) -+#define ENC_MODE_S 4 -+#define ENC_MODE_M GENMASK(5, 4) -+#define ENC_MODE_NFI 1 -+#define ENC_TNUM_S 0 -+#define ENC_TNUM_M GENMASK(2, 0) -+ -+#define ECC_ENCIDLE 0x00c -+#define ENC_IDLE BIT(0) -+ -+#define ECC_DECCON 0x100 -+#define DEC_EN BIT(0) -+ -+#define ECC_DECCNFG 0x104 -+#define DEC_EMPTY_EN BIT(31) -+#define DEC_CS_S 16 -+#define DEC_CS_M GENMASK(28, 16) -+#define DEC_CON_S 12 -+#define DEC_CON_M GENMASK(13, 12) -+#define DEC_CON_EL 2 -+#define DEC_MODE_S 4 -+#define DEC_MODE_M GENMASK(5, 4) -+#define DEC_MODE_NFI 1 -+#define DEC_TNUM_S 0 -+#define DEC_TNUM_M GENMASK(2, 0) -+ -+#define ECC_DECIDLE 0x10c -+#define DEC_IDLE BIT(1) -+ -+#define ECC_DECENUM 0x114 -+#define ERRNUM_S 2 -+#define ERRNUM_M GENMASK(3, 0) -+ -+#define ECC_DECDONE 0x118 -+#define DEC_DONE7 BIT(7) -+#define DEC_DONE6 BIT(6) -+#define DEC_DONE5 BIT(5) -+#define DEC_DONE4 BIT(4) -+#define DEC_DONE3 BIT(3) -+#define DEC_DONE2 BIT(2) -+#define DEC_DONE1 BIT(1) -+#define DEC_DONE0 BIT(0) -+ -+#define ECC_DECEL(n) (0x11c + (n) * 4) -+#define DEC_EL_ODD_S 16 -+#define DEC_EL_EVEN_S 0 -+#define DEC_EL_M 0x1fff -+#define DEC_EL_BYTE_POS_S 3 -+#define DEC_EL_BIT_POS_M GENMASK(3, 0) -+ -+#define ECC_FDMADDR 0x13c -+ -+/* ENCIDLE and DECIDLE */ -+#define ECC_IDLE BIT(0) -+ -+#define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \ -+ ((tpoecs) << ACCCON_POECS_S | (tprecs) << ACCCON_PRECS_S | \ -+ (tc2r) << ACCCON_C2R_S | (tw2r) << ACCCON_W2R_S | \ -+ (twh) << ACCCON_WH_S | (twst) << ACCCON_WST_S | (trlt)) -+ -+#define MASTER_STA_MASK (MAS_ADDR | MAS_RD | MAS_WR | \ -+ MAS_RDDLY) -+#define NFI_RESET_TIMEOUT 1000000 -+#define NFI_CORE_TIMEOUT 500000 -+#define ECC_ENGINE_TIMEOUT 500000 -+ -+#define ECC_SECTOR_SIZE 512 -+#define ECC_PARITY_BITS 13 -+ -+#define NFI_FDM_SIZE 8 -+ -+#define MT7621_NFC_NAME "mt7621-nand" -+ -+struct mt7621_nfc { -+ struct nand_controller controller; -+ struct nand_chip nand; -+ struct clk *nfi_clk; -+ struct device *dev; -+ -+ void __iomem *nfi_regs; -+ void __iomem *ecc_regs; -+ -+ u32 spare_per_sector; -+}; -+ -+static const u16 mt7621_nfi_page_size[] = { SZ_512, SZ_2K, SZ_4K }; -+static const u8 mt7621_nfi_spare_size[] = { 16, 26, 27, 28 }; -+static const u8 mt7621_ecc_strength[] = { 4, 6, 8, 10, 12 }; -+ -+static inline u32 nfi_read32(struct mt7621_nfc *nfc, u32 reg) -+{ -+ return readl(nfc->nfi_regs + reg); -+} -+ -+static inline void nfi_write32(struct mt7621_nfc *nfc, u32 reg, u32 val) -+{ -+ writel(val, nfc->nfi_regs + reg); -+} -+ -+static inline u16 nfi_read16(struct mt7621_nfc *nfc, u32 reg) -+{ -+ return readw(nfc->nfi_regs + reg); -+} -+ -+static inline void nfi_write16(struct mt7621_nfc *nfc, u32 reg, u16 val) -+{ -+ writew(val, nfc->nfi_regs + reg); -+} -+ -+static inline void ecc_write16(struct mt7621_nfc *nfc, u32 reg, u16 val) -+{ -+ writew(val, nfc->ecc_regs + reg); -+} -+ -+static inline u32 ecc_read32(struct mt7621_nfc *nfc, u32 reg) -+{ -+ return readl(nfc->ecc_regs + reg); -+} -+ -+static inline void ecc_write32(struct mt7621_nfc *nfc, u32 reg, u32 val) -+{ -+ return writel(val, nfc->ecc_regs + reg); -+} -+ -+static inline u8 *oob_fdm_ptr(struct nand_chip *nand, int sect) -+{ -+ return nand->oob_poi + sect * NFI_FDM_SIZE; -+} -+ -+static inline u8 *oob_ecc_ptr(struct mt7621_nfc *nfc, int sect) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ -+ return nand->oob_poi + nand->ecc.steps * NFI_FDM_SIZE + -+ sect * (nfc->spare_per_sector - NFI_FDM_SIZE); -+} -+ -+static inline u8 *page_data_ptr(struct nand_chip *nand, const u8 *buf, -+ int sect) -+{ -+ return (u8 *)buf + sect * nand->ecc.size; -+} -+ -+static int mt7621_ecc_wait_idle(struct mt7621_nfc *nfc, u32 reg) -+{ -+ struct device *dev = nfc->dev; -+ u32 val; -+ int ret; -+ -+ ret = readw_poll_timeout_atomic(nfc->ecc_regs + reg, val, -+ val & ECC_IDLE, 10, -+ ECC_ENGINE_TIMEOUT); -+ if (ret) { -+ dev_warn(dev, "ECC engine timed out entering idle mode\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int mt7621_ecc_decoder_wait_done(struct mt7621_nfc *nfc, u32 sect) -+{ -+ struct device *dev = nfc->dev; -+ u32 val; -+ int ret; -+ -+ ret = readw_poll_timeout_atomic(nfc->ecc_regs + ECC_DECDONE, val, -+ val & (1 << sect), 10, -+ ECC_ENGINE_TIMEOUT); -+ -+ if (ret) { -+ dev_warn(dev, "ECC decoder for sector %d timed out\n", -+ sect); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static void mt7621_ecc_encoder_op(struct mt7621_nfc *nfc, bool enable) -+{ -+ mt7621_ecc_wait_idle(nfc, ECC_ENCIDLE); -+ ecc_write16(nfc, ECC_ENCCON, enable ? ENC_EN : 0); -+} -+ -+static void mt7621_ecc_decoder_op(struct mt7621_nfc *nfc, bool enable) -+{ -+ mt7621_ecc_wait_idle(nfc, ECC_DECIDLE); -+ ecc_write16(nfc, ECC_DECCON, enable ? DEC_EN : 0); -+} -+ -+static int mt7621_ecc_correct_check(struct mt7621_nfc *nfc, u8 *sector_buf, -+ u8 *fdm_buf, u32 sect) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ u32 decnum, num_error_bits, fdm_end_bits; -+ u32 error_locations, error_bit_loc; -+ u32 error_byte_pos, error_bit_pos; -+ int bitflips = 0; -+ u32 i; -+ -+ decnum = ecc_read32(nfc, ECC_DECENUM); -+ num_error_bits = (decnum >> (sect << ERRNUM_S)) & ERRNUM_M; -+ fdm_end_bits = (nand->ecc.size + NFI_FDM_SIZE) << 3; -+ -+ if (!num_error_bits) -+ return 0; -+ -+ if (num_error_bits == ERRNUM_M) -+ return -1; -+ -+ for (i = 0; i < num_error_bits; i++) { -+ error_locations = ecc_read32(nfc, ECC_DECEL(i / 2)); -+ error_bit_loc = (error_locations >> ((i % 2) * DEC_EL_ODD_S)) & -+ DEC_EL_M; -+ error_byte_pos = error_bit_loc >> DEC_EL_BYTE_POS_S; -+ error_bit_pos = error_bit_loc & DEC_EL_BIT_POS_M; -+ -+ if (error_bit_loc < (nand->ecc.size << 3)) { -+ if (sector_buf) { -+ sector_buf[error_byte_pos] ^= -+ (1 << error_bit_pos); -+ } -+ } else if (error_bit_loc < fdm_end_bits) { -+ if (fdm_buf) { -+ fdm_buf[error_byte_pos - nand->ecc.size] ^= -+ (1 << error_bit_pos); -+ } -+ } -+ -+ bitflips++; -+ } -+ -+ return bitflips; -+} -+ -+static int mt7621_nfc_wait_write_completion(struct mt7621_nfc *nfc, -+ struct nand_chip *nand) -+{ -+ struct device *dev = nfc->dev; -+ u16 val; -+ int ret; -+ -+ ret = readw_poll_timeout_atomic(nfc->nfi_regs + NFI_ADDRCNTR, val, -+ ((val & SEC_CNTR_M) >> SEC_CNTR_S) >= nand->ecc.steps, 10, -+ NFI_CORE_TIMEOUT); -+ -+ if (ret) { -+ dev_warn(dev, "NFI core write operation timed out\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return ret; -+} -+ -+static void mt7621_nfc_hw_reset(struct mt7621_nfc *nfc) -+{ -+ u32 val; -+ int ret; -+ -+ /* reset all registers and force the NFI master to terminate */ -+ nfi_write16(nfc, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); -+ -+ /* wait for the master to finish the last transaction */ -+ ret = readw_poll_timeout(nfc->nfi_regs + NFI_MASTER_STA, val, -+ !(val & MASTER_STA_MASK), 50, -+ NFI_RESET_TIMEOUT); -+ if (ret) { -+ dev_warn(nfc->dev, "Failed to reset NFI master in %dms\n", -+ NFI_RESET_TIMEOUT); -+ } -+ -+ /* ensure any status register affected by the NFI master is reset */ -+ nfi_write16(nfc, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); -+ nfi_write16(nfc, NFI_STRDATA, 0); -+} -+ -+static inline void mt7621_nfc_hw_init(struct mt7621_nfc *nfc) -+{ -+ u32 acccon; -+ -+ /* -+ * CNRNB: nand ready/busy register -+ * ------------------------------- -+ * 7:4: timeout register for polling the NAND busy/ready signal -+ * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles. -+ */ -+ nfi_write16(nfc, NFI_CNRNB, CB2R_TIME_M | STR_CNRNB); -+ -+ mt7621_nfc_hw_reset(nfc); -+ -+ /* Apply default access timing */ -+ acccon = ACCTIMING(ACCCON_POECS_DEF, ACCCON_PRECS_DEF, ACCCON_C2R_DEF, -+ ACCCON_W2R_DEF, ACCCON_WH_DEF, ACCCON_WST_DEF, -+ ACCCON_RLT_DEF); -+ -+ nfi_write32(nfc, NFI_ACCCON, acccon); -+} -+ -+static int mt7621_nfc_send_command(struct mt7621_nfc *nfc, u8 command) -+{ -+ struct device *dev = nfc->dev; -+ u32 val; -+ int ret; -+ -+ nfi_write32(nfc, NFI_CMD, command); -+ -+ ret = readl_poll_timeout_atomic(nfc->nfi_regs + NFI_STA, val, -+ !(val & STA_CMD), 10, -+ NFI_CORE_TIMEOUT); -+ if (ret) { -+ dev_warn(dev, "NFI core timed out entering command mode\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int mt7621_nfc_send_address_byte(struct mt7621_nfc *nfc, int addr) -+{ -+ struct device *dev = nfc->dev; -+ u32 val; -+ int ret; -+ -+ nfi_write32(nfc, NFI_COLADDR, addr); -+ nfi_write32(nfc, NFI_ROWADDR, 0); -+ nfi_write16(nfc, NFI_ADDRNOB, 1); -+ -+ ret = readl_poll_timeout_atomic(nfc->nfi_regs + NFI_STA, val, -+ !(val & STA_ADDR), 10, -+ NFI_CORE_TIMEOUT); -+ if (ret) { -+ dev_warn(dev, "NFI core timed out entering address mode\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int mt7621_nfc_send_address(struct mt7621_nfc *nfc, const u8 *addr, -+ unsigned int naddrs) -+{ -+ int ret; -+ -+ while (naddrs) { -+ ret = mt7621_nfc_send_address_byte(nfc, *addr); -+ if (ret) -+ return ret; -+ -+ addr++; -+ naddrs--; -+ } -+ -+ return 0; -+} -+ -+static void mt7621_nfc_wait_pio_ready(struct mt7621_nfc *nfc) -+{ -+ struct device *dev = nfc->dev; -+ int ret; -+ u16 val; -+ -+ ret = readw_poll_timeout_atomic(nfc->nfi_regs + NFI_PIO_DIRDY, val, -+ val & PIO_DIRDY, 10, -+ NFI_CORE_TIMEOUT); -+ if (ret < 0) -+ dev_err(dev, "NFI core PIO mode not ready\n"); -+} -+ -+static u32 mt7621_nfc_pio_read(struct mt7621_nfc *nfc, bool br) -+{ -+ u32 reg; -+ -+ /* after each byte read, the NFI_STA reg is reset by the hardware */ -+ reg = (nfi_read32(nfc, NFI_STA) & STA_NFI_FSM_M) >> STA_NFI_FSM_S; -+ if (reg != STA_FSM_CUSTOM_DATA) { -+ reg = nfi_read16(nfc, NFI_CNFG); -+ reg |= CNFG_READ_MODE | CNFG_BYTE_RW; -+ if (!br) -+ reg &= ~CNFG_BYTE_RW; -+ nfi_write16(nfc, NFI_CNFG, reg); -+ -+ /* -+ * set to max sector to allow the HW to continue reading over -+ * unaligned accesses -+ */ -+ nfi_write16(nfc, NFI_CON, CON_NFI_SEC_M | CON_NFI_BRD); -+ -+ /* trigger to fetch data */ -+ nfi_write16(nfc, NFI_STRDATA, STR_DATA); -+ } -+ -+ mt7621_nfc_wait_pio_ready(nfc); -+ -+ return nfi_read32(nfc, NFI_DATAR); -+} -+ -+static void mt7621_nfc_read_data(struct mt7621_nfc *nfc, u8 *buf, u32 len) -+{ -+ while (((uintptr_t)buf & 3) && len) { -+ *buf = mt7621_nfc_pio_read(nfc, true); -+ buf++; -+ len--; -+ } -+ -+ while (len >= 4) { -+ *(u32 *)buf = mt7621_nfc_pio_read(nfc, false); -+ buf += 4; -+ len -= 4; -+ } -+ -+ while (len) { -+ *buf = mt7621_nfc_pio_read(nfc, true); -+ buf++; -+ len--; -+ } -+} -+ -+static void mt7621_nfc_read_data_discard(struct mt7621_nfc *nfc, u32 len) -+{ -+ while (len >= 4) { -+ mt7621_nfc_pio_read(nfc, false); -+ len -= 4; -+ } -+ -+ while (len) { -+ mt7621_nfc_pio_read(nfc, true); -+ len--; -+ } -+} -+ -+static void mt7621_nfc_pio_write(struct mt7621_nfc *nfc, u32 val, bool bw) -+{ -+ u32 reg; -+ -+ reg = (nfi_read32(nfc, NFI_STA) & STA_NFI_FSM_M) >> STA_NFI_FSM_S; -+ if (reg != STA_FSM_CUSTOM_DATA) { -+ reg = nfi_read16(nfc, NFI_CNFG); -+ reg &= ~(CNFG_READ_MODE | CNFG_BYTE_RW); -+ if (bw) -+ reg |= CNFG_BYTE_RW; -+ nfi_write16(nfc, NFI_CNFG, reg); -+ -+ nfi_write16(nfc, NFI_CON, CON_NFI_SEC_M | CON_NFI_BWR); -+ nfi_write16(nfc, NFI_STRDATA, STR_DATA); -+ } -+ -+ mt7621_nfc_wait_pio_ready(nfc); -+ nfi_write32(nfc, NFI_DATAW, val); -+} -+ -+static void mt7621_nfc_write_data(struct mt7621_nfc *nfc, const u8 *buf, -+ u32 len) -+{ -+ while (((uintptr_t)buf & 3) && len) { -+ mt7621_nfc_pio_write(nfc, *buf, true); -+ buf++; -+ len--; -+ } -+ -+ while (len >= 4) { -+ mt7621_nfc_pio_write(nfc, *(const u32 *)buf, false); -+ buf += 4; -+ len -= 4; -+ } -+ -+ while (len) { -+ mt7621_nfc_pio_write(nfc, *buf, true); -+ buf++; -+ len--; -+ } -+} -+ -+static void mt7621_nfc_write_data_empty(struct mt7621_nfc *nfc, u32 len) -+{ -+ while (len >= 4) { -+ mt7621_nfc_pio_write(nfc, 0xffffffff, false); -+ len -= 4; -+ } -+ -+ while (len) { -+ mt7621_nfc_pio_write(nfc, 0xff, true); -+ len--; -+ } -+} -+ -+static int mt7621_nfc_dev_ready(struct mt7621_nfc *nfc, -+ unsigned int timeout_ms) -+{ -+ u32 val; -+ -+ return readl_poll_timeout_atomic(nfc->nfi_regs + NFI_STA, val, -+ !(val & STA_BUSY), 10, -+ timeout_ms * 1000); -+} -+ -+static int mt7621_nfc_exec_instr(struct nand_chip *nand, -+ const struct nand_op_instr *instr) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ -+ switch (instr->type) { -+ case NAND_OP_CMD_INSTR: -+ mt7621_nfc_hw_reset(nfc); -+ nfi_write16(nfc, NFI_CNFG, CNFG_OP_CUSTOM << CNFG_OP_MODE_S); -+ return mt7621_nfc_send_command(nfc, instr->ctx.cmd.opcode); -+ case NAND_OP_ADDR_INSTR: -+ return mt7621_nfc_send_address(nfc, instr->ctx.addr.addrs, -+ instr->ctx.addr.naddrs); -+ case NAND_OP_DATA_IN_INSTR: -+ mt7621_nfc_read_data(nfc, instr->ctx.data.buf.in, -+ instr->ctx.data.len); -+ return 0; -+ case NAND_OP_DATA_OUT_INSTR: -+ mt7621_nfc_write_data(nfc, instr->ctx.data.buf.out, -+ instr->ctx.data.len); -+ return 0; -+ case NAND_OP_WAITRDY_INSTR: -+ return mt7621_nfc_dev_ready(nfc, -+ instr->ctx.waitrdy.timeout_ms); -+ default: -+ WARN_ONCE(1, "unsupported NAND instruction type: %d\n", -+ instr->type); -+ -+ return -EINVAL; -+ } -+} -+ -+static int mt7621_nfc_exec_op(struct nand_chip *nand, -+ const struct nand_operation *op, bool check_only) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ int i, ret; -+ -+ if (check_only) -+ return 0; -+ -+ /* Only CS0 available */ -+ nfi_write16(nfc, NFI_CSEL, 0); -+ -+ for (i = 0; i < op->ninstrs; i++) { -+ ret = mt7621_nfc_exec_instr(nand, &op->instrs[i]); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int mt7621_nfc_setup_data_interface(struct nand_chip *nand, int csline, -+ const struct nand_data_interface *conf) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ const struct nand_sdr_timings *timings; -+ u32 acccon, temp, rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt; -+ -+ if (!nfc->nfi_clk) -+ return -ENOTSUPP; -+ -+ timings = nand_get_sdr_timings(conf); -+ if (IS_ERR(timings)) -+ return -ENOTSUPP; -+ -+ rate = clk_get_rate(nfc->nfi_clk); -+ -+ /* turn clock rate into KHZ */ -+ rate /= 1000; -+ -+ tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000; -+ tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000); -+ tpoecs = min_t(u32, tpoecs, ACCCON_POECS_MAX); -+ -+ tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000; -+ tprecs = DIV_ROUND_UP(tprecs * rate, 1000000); -+ tprecs = min_t(u32, tprecs, ACCCON_PRECS_MAX); -+ -+ /* sdr interface has no tCR which means CE# low to RE# low */ -+ tc2r = 0; -+ -+ tw2r = timings->tWHR_min / 1000; -+ tw2r = DIV_ROUND_UP(tw2r * rate, 1000000); -+ tw2r = DIV_ROUND_UP(tw2r - 1, 2); -+ tw2r = min_t(u32, tw2r, ACCCON_W2R_MAX); -+ -+ twh = max(timings->tREH_min, timings->tWH_min) / 1000; -+ twh = DIV_ROUND_UP(twh * rate, 1000000) - 1; -+ twh = min_t(u32, twh, ACCCON_WH_MAX); -+ -+ /* Calculate real WE#/RE# hold time in nanosecond */ -+ temp = (twh + 1) * 1000000 / rate; -+ /* nanosecond to picosecond */ -+ temp *= 1000; -+ -+ /* -+ * WE# low level time should be expaned to meet WE# pulse time -+ * and WE# cycle time at the same time. -+ */ -+ if (temp < timings->tWC_min) -+ twst = timings->tWC_min - temp; -+ else -+ twst = 0; -+ twst = max(timings->tWP_min, twst) / 1000; -+ twst = DIV_ROUND_UP(twst * rate, 1000000) - 1; -+ twst = min_t(u32, twst, ACCCON_WST_MAX); -+ -+ /* -+ * RE# low level time should be expaned to meet RE# pulse time -+ * and RE# cycle time at the same time. -+ */ -+ if (temp < timings->tRC_min) -+ trlt = timings->tRC_min - temp; -+ else -+ trlt = 0; -+ trlt = max(trlt, timings->tRP_min) / 1000; -+ trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1; -+ trlt = min_t(u32, trlt, ACCCON_RLT_MAX); -+ -+ if (csline == NAND_DATA_IFACE_CHECK_ONLY) { -+ if (twst < ACCCON_WST_MIN || trlt < ACCCON_RLT_MIN) -+ return -ENOTSUPP; -+ } -+ -+ acccon = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt); -+ -+ dev_info(nfc->dev, "Using programmed access timing: %08x\n", acccon); -+ -+ nfi_write32(nfc, NFI_ACCCON, acccon); -+ -+ return 0; -+} -+ -+static int mt7621_nfc_calc_ecc_strength(struct mt7621_nfc *nfc, -+ u32 avail_ecc_bytes) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ struct mtd_info *mtd = nand_to_mtd(nand); -+ u32 strength; -+ int i; -+ -+ strength = avail_ecc_bytes * 8 / ECC_PARITY_BITS; -+ -+ /* Find the closest supported ecc strength */ -+ for (i = ARRAY_SIZE(mt7621_ecc_strength) - 1; i >= 0; i--) { -+ if (mt7621_ecc_strength[i] <= strength) -+ break; -+ } -+ -+ if (unlikely(i < 0)) { -+ dev_err(nfc->dev, "OOB size (%u) is not supported\n", -+ mtd->oobsize); -+ return -EINVAL; -+ } -+ -+ nand->ecc.strength = mt7621_ecc_strength[i]; -+ nand->ecc.bytes = -+ DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8); -+ -+ dev_info(nfc->dev, "ECC strength adjusted to %u bits\n", -+ nand->ecc.strength); -+ -+ return i; -+} -+ -+static int mt7621_nfc_set_spare_per_sector(struct mt7621_nfc *nfc) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ struct mtd_info *mtd = nand_to_mtd(nand); -+ u32 size; -+ int i; -+ -+ size = nand->ecc.bytes + NFI_FDM_SIZE; -+ -+ /* Find the closest supported spare size */ -+ for (i = 0; i < ARRAY_SIZE(mt7621_nfi_spare_size); i++) { -+ if (mt7621_nfi_spare_size[i] >= size) -+ break; -+ } -+ -+ if (unlikely(i >= ARRAY_SIZE(mt7621_nfi_spare_size))) { -+ dev_err(nfc->dev, "OOB size (%u) is not supported\n", -+ mtd->oobsize); -+ return -EINVAL; -+ } -+ -+ nfc->spare_per_sector = mt7621_nfi_spare_size[i]; -+ -+ return i; -+} -+ -+static int mt7621_nfc_ecc_init(struct mt7621_nfc *nfc) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ struct mtd_info *mtd = nand_to_mtd(nand); -+ u32 spare_per_sector, encode_block_size, decode_block_size; -+ u32 ecc_enccfg, ecc_deccfg; -+ int ecc_cap; -+ -+ /* Only hardware ECC mode is supported */ -+ if (nand->ecc.mode != NAND_ECC_HW_SYNDROME) { -+ dev_err(nfc->dev, "Only hardware ECC mode is supported\n"); -+ return -EINVAL; -+ } -+ -+ nand->ecc.size = ECC_SECTOR_SIZE; -+ nand->ecc.steps = mtd->writesize / nand->ecc.size; -+ -+ spare_per_sector = mtd->oobsize / nand->ecc.steps; -+ -+ ecc_cap = mt7621_nfc_calc_ecc_strength(nfc, -+ spare_per_sector - NFI_FDM_SIZE); -+ if (ecc_cap < 0) -+ return ecc_cap; -+ -+ /* Sector + FDM */ -+ encode_block_size = (nand->ecc.size + NFI_FDM_SIZE) * 8; -+ ecc_enccfg = ecc_cap | (ENC_MODE_NFI << ENC_MODE_S) | -+ (encode_block_size << ENC_CNFG_MSG_S); -+ -+ /* Sector + FDM + ECC parity bits */ -+ decode_block_size = ((nand->ecc.size + NFI_FDM_SIZE) * 8) + -+ nand->ecc.strength * ECC_PARITY_BITS; -+ ecc_deccfg = ecc_cap | (DEC_MODE_NFI << DEC_MODE_S) | -+ (decode_block_size << DEC_CS_S) | -+ (DEC_CON_EL << DEC_CON_S) | DEC_EMPTY_EN; -+ -+ mt7621_ecc_encoder_op(nfc, false); -+ ecc_write32(nfc, ECC_ENCCNFG, ecc_enccfg); -+ -+ mt7621_ecc_decoder_op(nfc, false); -+ ecc_write32(nfc, ECC_DECCNFG, ecc_deccfg); -+ -+ return 0; -+} -+ -+static int mt7621_nfc_set_page_format(struct mt7621_nfc *nfc) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ struct mtd_info *mtd = nand_to_mtd(nand); -+ int i, spare_size; -+ u32 pagefmt; -+ -+ spare_size = mt7621_nfc_set_spare_per_sector(nfc); -+ if (spare_size < 0) -+ return spare_size; -+ -+ for (i = 0; i < ARRAY_SIZE(mt7621_nfi_page_size); i++) { -+ if (mt7621_nfi_page_size[i] == mtd->writesize) -+ break; -+ } -+ -+ if (unlikely(i >= ARRAY_SIZE(mt7621_nfi_page_size))) { -+ dev_err(nfc->dev, "Page size (%u) is not supported\n", -+ mtd->writesize); -+ return -EINVAL; -+ } -+ -+ pagefmt = i | (spare_size << PAGEFMT_SPARE_S) | -+ (NFI_FDM_SIZE << PAGEFMT_FDM_S) | -+ (NFI_FDM_SIZE << PAGEFMT_FDM_ECC_S); -+ -+ nfi_write16(nfc, NFI_PAGEFMT, pagefmt); -+ -+ return 0; -+} -+ -+static int mt7621_nfc_attach_chip(struct nand_chip *nand) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ int ret; -+ -+ if (nand->options & NAND_BUSWIDTH_16) { -+ dev_err(nfc->dev, "16-bit buswidth is not supported"); -+ return -EINVAL; -+ } -+ -+ ret = mt7621_nfc_ecc_init(nfc); -+ if (ret) -+ return ret; -+ -+ return mt7621_nfc_set_page_format(nfc); -+} -+ -+static const struct nand_controller_ops mt7621_nfc_controller_ops = { -+ .attach_chip = mt7621_nfc_attach_chip, -+ .exec_op = mt7621_nfc_exec_op, -+ .setup_data_interface = mt7621_nfc_setup_data_interface, -+}; -+ -+static int mt7621_nfc_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oob_region) -+{ -+ struct nand_chip *nand = mtd_to_nand(mtd); -+ -+ if (section >= nand->ecc.steps) -+ return -ERANGE; -+ -+ oob_region->length = NFI_FDM_SIZE - 1; -+ oob_region->offset = section * NFI_FDM_SIZE + 1; -+ -+ return 0; -+} -+ -+static int mt7621_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oob_region) -+{ -+ struct nand_chip *nand = mtd_to_nand(mtd); -+ -+ if (section) -+ return -ERANGE; -+ -+ oob_region->offset = NFI_FDM_SIZE * nand->ecc.steps; -+ oob_region->length = mtd->oobsize - oob_region->offset; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops mt7621_nfc_ooblayout_ops = { -+ .free = mt7621_nfc_ooblayout_free, -+ .ecc = mt7621_nfc_ooblayout_ecc, -+}; -+ -+static void mt7621_nfc_write_fdm(struct mt7621_nfc *nfc) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ u32 vall, valm; -+ u8 *oobptr; -+ int i, j; -+ -+ for (i = 0; i < nand->ecc.steps; i++) { -+ vall = 0; -+ valm = 0; -+ oobptr = oob_fdm_ptr(nand, i); -+ -+ for (j = 0; j < 4; j++) -+ vall |= (u32)oobptr[j] << (j * 8); -+ -+ for (j = 0; j < 4; j++) -+ valm |= (u32)oobptr[j + 4] << ((j - 4) * 8); -+ -+ nfi_write32(nfc, NFI_FDML(i), vall); -+ nfi_write32(nfc, NFI_FDMM(i), valm); -+ } -+} -+ -+static void mt7621_nfc_read_sector_fdm(struct mt7621_nfc *nfc, u32 sect) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ u32 vall, valm; -+ u8 *oobptr; -+ int i; -+ -+ vall = nfi_read32(nfc, NFI_FDML(sect)); -+ valm = nfi_read32(nfc, NFI_FDMM(sect)); -+ oobptr = oob_fdm_ptr(nand, sect); -+ -+ for (i = 0; i < 4; i++) -+ oobptr[i] = (vall >> (i * 8)) & 0xff; -+ -+ for (i = 0; i < 4; i++) -+ oobptr[i + 4] = (valm >> (i * 8)) & 0xff; -+} -+ -+static int mt7621_nfc_read_page_hwecc(struct nand_chip *nand, uint8_t *buf, -+ int oob_required, int page) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ struct mtd_info *mtd = nand_to_mtd(nand); -+ int bitflips = 0; -+ int rc, i; -+ -+ nand_read_page_op(nand, page, 0, NULL, 0); -+ -+ nfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S) | -+ CNFG_READ_MODE | CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); -+ -+ mt7621_ecc_decoder_op(nfc, true); -+ -+ nfi_write16(nfc, NFI_CON, -+ CON_NFI_BRD | (nand->ecc.steps << CON_NFI_SEC_S)); -+ -+ for (i = 0; i < nand->ecc.steps; i++) { -+ if (buf) -+ mt7621_nfc_read_data(nfc, page_data_ptr(nand, buf, i), -+ nand->ecc.size); -+ else -+ mt7621_nfc_read_data_discard(nfc, nand->ecc.size); -+ -+ rc = mt7621_ecc_decoder_wait_done(nfc, i); -+ -+ mt7621_nfc_read_sector_fdm(nfc, i); -+ -+ if (rc < 0) { -+ bitflips = -EIO; -+ continue; -+ } -+ -+ rc = mt7621_ecc_correct_check(nfc, -+ buf ? page_data_ptr(nand, buf, i) : NULL, -+ oob_fdm_ptr(nand, i), i); -+ -+ if (rc < 0) { -+ dev_warn(nfc->dev, -+ "Uncorrectable ECC error at page %d.%d\n", -+ page, i); -+ bitflips = -EBADMSG; -+ mtd->ecc_stats.failed++; -+ } else if (bitflips >= 0) { -+ bitflips += rc; -+ mtd->ecc_stats.corrected += rc; -+ } -+ } -+ -+ mt7621_ecc_decoder_op(nfc, false); -+ -+ nfi_write16(nfc, NFI_CON, 0); -+ -+ return bitflips; -+} -+ -+static int mt7621_nfc_read_page_raw(struct nand_chip *nand, uint8_t *buf, -+ int oob_required, int page) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ int i; -+ -+ nand_read_page_op(nand, page, 0, NULL, 0); -+ -+ nfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S) | -+ CNFG_READ_MODE); -+ -+ nfi_write16(nfc, NFI_CON, -+ CON_NFI_BRD | (nand->ecc.steps << CON_NFI_SEC_S)); -+ -+ for (i = 0; i < nand->ecc.steps; i++) { -+ /* Read data */ -+ if (buf) -+ mt7621_nfc_read_data(nfc, page_data_ptr(nand, buf, i), -+ nand->ecc.size); -+ else -+ mt7621_nfc_read_data_discard(nfc, nand->ecc.size); -+ -+ /* Read FDM */ -+ mt7621_nfc_read_data(nfc, oob_fdm_ptr(nand, i), NFI_FDM_SIZE); -+ -+ /* Read ECC parity data */ -+ mt7621_nfc_read_data(nfc, oob_ecc_ptr(nfc, i), -+ nfc->spare_per_sector - NFI_FDM_SIZE); -+ } -+ -+ nfi_write16(nfc, NFI_CON, 0); -+ -+ return 0; -+} -+ -+static int mt7621_nfc_read_oob_hwecc(struct nand_chip *nand, int page) -+{ -+ return mt7621_nfc_read_page_hwecc(nand, NULL, 1, page); -+} -+ -+static int mt7621_nfc_read_oob_raw(struct nand_chip *nand, int page) -+{ -+ return mt7621_nfc_read_page_raw(nand, NULL, 1, page); -+} -+ -+static int mt7621_nfc_check_empty_page(struct nand_chip *nand, const u8 *buf) -+{ -+ struct mtd_info *mtd = nand_to_mtd(nand); -+ uint32_t i, j; -+ u8 *oobptr; -+ -+ if (buf) { -+ for (i = 0; i < mtd->writesize; i++) -+ if (buf[i] != 0xff) -+ return 0; -+ } -+ -+ for (i = 0; i < nand->ecc.steps; i++) { -+ oobptr = oob_fdm_ptr(nand, i); -+ for (j = 0; j < NFI_FDM_SIZE; j++) -+ if (oobptr[j] != 0xff) -+ return 0; -+ } -+ -+ return 1; -+} -+ -+static int mt7621_nfc_write_page_hwecc(struct nand_chip *nand, -+ const uint8_t *buf, int oob_required, -+ int page) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ struct mtd_info *mtd = nand_to_mtd(nand); -+ -+ if (mt7621_nfc_check_empty_page(nand, buf)) { -+ /* -+ * MT7621 ECC engine always generates parity code for input -+ * pages, even for empty pages. Doing so will write back ECC -+ * parity code to the oob region, which means such pages will -+ * no longer be empty pages. -+ * -+ * To avoid this, stop write operation if current page is an -+ * empty page. -+ */ -+ return 0; -+ } -+ -+ nand_prog_page_begin_op(nand, page, 0, NULL, 0); -+ -+ nfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S) | -+ CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); -+ -+ mt7621_ecc_encoder_op(nfc, true); -+ -+ mt7621_nfc_write_fdm(nfc); -+ -+ nfi_write16(nfc, NFI_CON, -+ CON_NFI_BWR | (nand->ecc.steps << CON_NFI_SEC_S)); -+ -+ if (buf) -+ mt7621_nfc_write_data(nfc, buf, mtd->writesize); -+ else -+ mt7621_nfc_write_data_empty(nfc, mtd->writesize); -+ -+ mt7621_nfc_wait_write_completion(nfc, nand); -+ -+ mt7621_ecc_encoder_op(nfc, false); -+ -+ nfi_write16(nfc, NFI_CON, 0); -+ -+ return nand_prog_page_end_op(nand); -+} -+ -+static int mt7621_nfc_write_page_raw(struct nand_chip *nand, -+ const uint8_t *buf, int oob_required, -+ int page) -+{ -+ struct mt7621_nfc *nfc = nand_get_controller_data(nand); -+ int i; -+ -+ nand_prog_page_begin_op(nand, page, 0, NULL, 0); -+ -+ nfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S)); -+ -+ nfi_write16(nfc, NFI_CON, -+ CON_NFI_BWR | (nand->ecc.steps << CON_NFI_SEC_S)); -+ -+ for (i = 0; i < nand->ecc.steps; i++) { -+ /* Write data */ -+ if (buf) -+ mt7621_nfc_write_data(nfc, page_data_ptr(nand, buf, i), -+ nand->ecc.size); -+ else -+ mt7621_nfc_write_data_empty(nfc, nand->ecc.size); -+ -+ /* Write FDM */ -+ mt7621_nfc_write_data(nfc, oob_fdm_ptr(nand, i), -+ NFI_FDM_SIZE); -+ -+ /* Write dummy ECC parity data */ -+ mt7621_nfc_write_data_empty(nfc, nfc->spare_per_sector - -+ NFI_FDM_SIZE); -+ } -+ -+ mt7621_nfc_wait_write_completion(nfc, nand); -+ -+ nfi_write16(nfc, NFI_CON, 0); -+ -+ return nand_prog_page_end_op(nand); -+} -+ -+static int mt7621_nfc_write_oob_hwecc(struct nand_chip *nand, int page) -+{ -+ return mt7621_nfc_write_page_hwecc(nand, NULL, 1, page); -+} -+ -+static int mt7621_nfc_write_oob_raw(struct nand_chip *nand, int page) -+{ -+ return mt7621_nfc_write_page_raw(nand, NULL, 1, page); -+} -+ -+static int mt7621_nfc_init_chip(struct mt7621_nfc *nfc) -+{ -+ struct nand_chip *nand = &nfc->nand; -+ struct mtd_info *mtd; -+ int ret; -+ -+ nand->controller = &nfc->controller; -+ nand_set_controller_data(nand, (void *)nfc); -+ nand_set_flash_node(nand, nfc->dev->of_node); -+ -+ nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_NO_SUBPAGE_WRITE; -+ if (!nfc->nfi_clk) -+ nand->options |= NAND_KEEP_TIMINGS; -+ -+ nand->ecc.mode = NAND_ECC_HW_SYNDROME; -+ nand->ecc.read_page = mt7621_nfc_read_page_hwecc; -+ nand->ecc.read_page_raw = mt7621_nfc_read_page_raw; -+ nand->ecc.write_page = mt7621_nfc_write_page_hwecc; -+ nand->ecc.write_page_raw = mt7621_nfc_write_page_raw; -+ nand->ecc.read_oob = mt7621_nfc_read_oob_hwecc; -+ nand->ecc.read_oob_raw = mt7621_nfc_read_oob_raw; -+ nand->ecc.write_oob = mt7621_nfc_write_oob_hwecc; -+ nand->ecc.write_oob_raw = mt7621_nfc_write_oob_raw; -+ -+ mtd = nand_to_mtd(nand); -+ mtd->owner = THIS_MODULE; -+ mtd->dev.parent = nfc->dev; -+ mtd->name = MT7621_NFC_NAME; -+ mtd_set_ooblayout(mtd, &mt7621_nfc_ooblayout_ops); -+ -+ mt7621_nfc_hw_init(nfc); -+ -+ ret = nand_scan(nand, 1); -+ if (ret) -+ return ret; -+ -+ ret = mtd_device_register(mtd, NULL, 0); -+ if (ret) { -+ dev_err(nfc->dev, "Failed to register MTD: %d\n", ret); -+ nand_release(nand); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int mt7621_nfc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct mt7621_nfc *nfc; -+ struct resource *res; -+ int ret; -+ -+ nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); -+ if (!nfc) -+ return -ENOMEM; -+ -+ nand_controller_init(&nfc->controller); -+ nfc->controller.ops = &mt7621_nfc_controller_ops; -+ nfc->dev = dev; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nfi"); -+ nfc->nfi_regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(nfc->nfi_regs)) { -+ ret = PTR_ERR(nfc->nfi_regs); -+ return ret; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecc"); -+ nfc->ecc_regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(nfc->ecc_regs)) { -+ ret = PTR_ERR(nfc->ecc_regs); -+ return ret; -+ } -+ -+ nfc->nfi_clk = devm_clk_get(dev, "nfi_clk"); -+ if (IS_ERR(nfc->nfi_clk)) { -+ dev_warn(dev, "nfi clk not provided\n"); -+ nfc->nfi_clk = NULL; -+ } else { -+ ret = clk_prepare_enable(nfc->nfi_clk); -+ if (ret) { -+ dev_err(dev, "Failed to enable nfi core clock\n"); -+ return ret; -+ } -+ } -+ -+ platform_set_drvdata(pdev, nfc); -+ -+ ret = mt7621_nfc_init_chip(nfc); -+ if (ret) { -+ dev_err(dev, "Failed to initialize nand chip\n"); -+ goto clk_disable; -+ } -+ -+ return 0; -+ -+clk_disable: -+ clk_disable_unprepare(nfc->nfi_clk); -+ -+ return ret; -+} -+ -+static int mt7621_nfc_remove(struct platform_device *pdev) -+{ -+ struct mt7621_nfc *nfc = platform_get_drvdata(pdev); -+ -+ nand_release(&nfc->nand); -+ clk_disable_unprepare(nfc->nfi_clk); -+ -+ return 0; -+} -+ -+static const struct of_device_id mt7621_nfc_id_table[] = { -+ { .compatible = "mediatek,mt7621-nfc" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, match); -+ -+static struct platform_driver mt7621_nfc_driver = { -+ .probe = mt7621_nfc_probe, -+ .remove = mt7621_nfc_remove, -+ .driver = { -+ .name = MT7621_NFC_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = mt7621_nfc_id_table, -+ }, -+}; -+module_platform_driver(mt7621_nfc_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Weijie Gao "); -+MODULE_DESCRIPTION("MediaTek MT7621 NAND Flash Controller driver"); diff --git a/target/linux/ramips/patches-5.4/0301-dt-bindings-add-documentation-for-mt7621-nand-driver.patch b/target/linux/ramips/patches-5.4/0301-dt-bindings-add-documentation-for-mt7621-nand-driver.patch deleted file mode 100644 index 3d122c10c0..0000000000 --- a/target/linux/ramips/patches-5.4/0301-dt-bindings-add-documentation-for-mt7621-nand-driver.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 1 Apr 2020 02:07:59 +0800 -Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver - -This patch adds documentation for MediaTek MT7621 NAND flash controller -driver. - -Signed-off-by: Weijie Gao ---- - .../bindings/mtd/mediatek,mt7621-nfc.yaml | 68 ++++++++++++++++++++++ - 1 file changed, 68 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml -@@ -0,0 +1,68 @@ -+# SPDX-License-Identifier: GPL-2.0 -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding -+ -+maintainers: -+ - Weijie Gao -+ -+description: | -+ This driver uses a single node to describe both NAND Flash controller -+ interface (NFI) and ECC engine for MT7621 SoC. -+ MT7621 supports only one chip select. -+ -+properties: -+ "#address-cells": false -+ "#size-cells": false -+ -+ compatible: -+ enum: -+ - mediatek,mt7621-nfc -+ -+ reg: -+ items: -+ - description: Register base of NFI core -+ - description: Register base of ECC engine -+ -+ reg-names: -+ items: -+ - const: nfi -+ - const: ecc -+ -+ clocks: -+ items: -+ - description: Source clock for NFI core, fixed 125MHz -+ -+ clock-names: -+ items: -+ - const: nfi_clk -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - clocks -+ - clock-names -+ -+examples: -+ - | -+ nficlock: nficlock { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ -+ clock-frequency = <125000000>; -+ }; -+ -+ nand@1e003000 { -+ compatible = "mediatek,mt7621-nfc"; -+ -+ reg = <0x1e003000 0x800 -+ 0x1e003800 0x800>; -+ reg-names = "nfi", "ecc"; -+ -+ clocks = <&nficlock>; -+ clock-names = "nfi_clk"; -+ }; diff --git a/target/linux/ramips/patches-5.4/100-mt7621-core-detect-hack.patch b/target/linux/ramips/patches-5.4/100-mt7621-core-detect-hack.patch deleted file mode 100644 index 1c8b61f8ef..0000000000 --- a/target/linux/ramips/patches-5.4/100-mt7621-core-detect-hack.patch +++ /dev/null @@ -1,61 +0,0 @@ -There is a variant of MT7621 which contains only one CPU core instead of 2. -This is not reflected in the config register, so the kernel detects more -physical cores, which leads to a hang on SMP bringup. -Add a hack to detect missing cores. - -Signed-off-by: Felix Fietkau - ---- a/arch/mips/kernel/smp-cps.c -+++ b/arch/mips/kernel/smp-cps.c -@@ -43,6 +43,11 @@ static unsigned core_vpe_count(unsigned - return mips_cps_numvps(cluster, core); - } - -+bool __weak plat_cpu_core_present(int core) -+{ -+ return true; -+} -+ - static void __init cps_smp_setup(void) - { - unsigned int nclusters, ncores, nvpes, core_vpes; -@@ -60,6 +65,8 @@ static void __init cps_smp_setup(void) - - ncores = mips_cps_numcores(cl); - for (c = 0; c < ncores; c++) { -+ if (!plat_cpu_core_present(c)) -+ continue; - core_vpes = core_vpe_count(cl, c); - - if (c > 0) ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - - #include - -@@ -160,6 +161,20 @@ void __init ralink_of_remap(void) - panic("Failed to remap core resources"); - } - -+bool plat_cpu_core_present(int core) -+{ -+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); -+ -+ if (!core) -+ return true; -+ launch += core * 2; /* 2 VPEs per core */ -+ if (!(launch->flags & LAUNCH_FREADY)) -+ return false; -+ if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE)) -+ return false; -+ return true; -+} -+ - void prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); diff --git a/target/linux/ramips/patches-5.4/101-mt7621-timer.patch b/target/linux/ramips/patches-5.4/101-mt7621-timer.patch deleted file mode 100644 index 8528b71c88..0000000000 --- a/target/linux/ramips/patches-5.4/101-mt7621-timer.patch +++ /dev/null @@ -1,87 +0,0 @@ ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -7,6 +7,7 @@ - - #include - #include -+#include - - #include - #include -@@ -14,6 +15,7 @@ - #include - #include - #include -+#include - - #include - -@@ -175,6 +177,58 @@ bool plat_cpu_core_present(int core) - return true; - } - -+#define LPS_PREC 8 -+/* -+* Re-calibration lpj(loop-per-jiffy). -+* (derived from kernel/calibrate.c) -+*/ -+static int udelay_recal(void) -+{ -+ unsigned int i, lpj = 0; -+ unsigned long ticks, loopbit; -+ int lps_precision = LPS_PREC; -+ -+ lpj = (1<<12); -+ -+ while ((lpj <<= 1) != 0) { -+ /* wait for "start of" clock tick */ -+ ticks = jiffies; -+ while (ticks == jiffies) -+ /* nothing */; -+ -+ /* Go .. */ -+ ticks = jiffies; -+ __delay(lpj); -+ ticks = jiffies - ticks; -+ if (ticks) -+ break; -+ } -+ -+ /* -+ * Do a binary approximation to get lpj set to -+ * equal one clock (up to lps_precision bits) -+ */ -+ lpj >>= 1; -+ loopbit = lpj; -+ while (lps_precision-- && (loopbit >>= 1)) { -+ lpj |= loopbit; -+ ticks = jiffies; -+ while (ticks == jiffies) -+ /* nothing */; -+ ticks = jiffies; -+ __delay(lpj); -+ if (jiffies != ticks) /* longer than 1 tick */ -+ lpj &= ~loopbit; -+ } -+ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj); -+ -+ for(i=0; i< NR_CPUS; i++) -+ cpu_data[i].udelay_val = lpj; -+ -+ return 0; -+} -+device_initcall(udelay_recal); -+ - void prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -58,6 +58,7 @@ choice - select CLKSRC_MIPS_GIC - select HAVE_PCI if PCI_MT7621 - select WEAK_REORDERING_BEYOND_LLSC -+ select GENERIC_CLOCKEVENTS_BROADCAST - endchoice - - choice diff --git a/target/linux/ramips/patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch deleted file mode 100644 index 0c997a3f28..0000000000 --- a/target/linux/ramips/patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch +++ /dev/null @@ -1,224 +0,0 @@ ---- a/arch/mips/include/asm/mach-ralink/mt7621.h -+++ b/arch/mips/include/asm/mach-ralink/mt7621.h -@@ -17,6 +17,10 @@ - #define SYSC_REG_CHIP_REV 0x0c - #define SYSC_REG_SYSTEM_CONFIG0 0x10 - #define SYSC_REG_SYSTEM_CONFIG1 0x14 -+#define SYSC_REG_CLKCFG0 0x2c -+#define SYSC_REG_CUR_CLK_STS 0x44 -+ -+#define MEMC_REG_CPU_PLL 0x648 - - #define CHIP_REV_PKG_MASK 0x1 - #define CHIP_REV_PKG_SHIFT 16 -@@ -24,6 +28,22 @@ - #define CHIP_REV_VER_SHIFT 8 - #define CHIP_REV_ECO_MASK 0xf - -+#define XTAL_MODE_SEL_MASK 0x7 -+#define XTAL_MODE_SEL_SHIFT 6 -+ -+#define CPU_CLK_SEL_MASK 0x3 -+#define CPU_CLK_SEL_SHIFT 30 -+ -+#define CUR_CPU_FDIV_MASK 0x1f -+#define CUR_CPU_FDIV_SHIFT 8 -+#define CUR_CPU_FFRAC_MASK 0x1f -+#define CUR_CPU_FFRAC_SHIFT 0 -+ -+#define CPU_PLL_PREDIV_MASK 0x3 -+#define CPU_PLL_PREDIV_SHIFT 12 -+#define CPU_PLL_FBDIV_MASK 0x7f -+#define CPU_PLL_FBDIV_SHIFT 4 -+ - #define MT7621_DRAM_BASE 0x0 - #define MT7621_DDR2_SIZE_MIN 32 - #define MT7621_DDR2_SIZE_MAX 256 ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -8,6 +8,10 @@ - #include - #include - #include -+#include -+#include -+#include -+#include - - #include - #include -@@ -16,16 +20,12 @@ - #include - #include - #include -+#include - - #include - - #include "common.h" - --#define SYSC_REG_SYSCFG 0x10 --#define SYSC_REG_CPLL_CLKCFG0 0x2c --#define SYSC_REG_CUR_CLK_STS 0x44 --#define CPU_CLK_SEL (BIT(30) | BIT(31)) -- - #define MT7621_GPIO_MODE_UART1 1 - #define MT7621_GPIO_MODE_I2C 2 - #define MT7621_GPIO_MODE_UART3_MASK 0x3 -@@ -111,49 +111,89 @@ static struct rt2880_pmx_group mt7621_pi - { 0 } - }; - -+static struct clk *clks[MT7621_CLK_MAX]; -+static struct clk_onecell_data clk_data = { -+ .clks = clks, -+ .clk_num = ARRAY_SIZE(clks), -+}; -+ - phys_addr_t mips_cpc_default_phys_base(void) - { - panic("Cannot detect cpc address"); - } - --void __init ralink_clk_init(void) -+static struct clk *__init mt7621_add_sys_clkdev( -+ const char *id, unsigned long rate) - { -- int cpu_fdiv = 0; -- int cpu_ffrac = 0; -- int fbdiv = 0; -- u32 clk_sts, syscfg; -- u8 clk_sel = 0, xtal_mode; -- u32 cpu_clk; -+ struct clk *clk; -+ int err; -+ -+ clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); -+ if (IS_ERR(clk)) -+ panic("failed to allocate %s clock structure", id); -+ -+ err = clk_register_clkdev(clk, id, NULL); -+ if (err) -+ panic("unable to register %s clock device", id); - -- if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) -- clk_sel = 1; -+ return clk; -+} -+ -+void __init ralink_clk_init(void) -+{ -+ u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; -+ u32 pll, prediv, fbdiv; -+ u32 xtal_clk, cpu_clk, bus_clk; -+ const static u32 prediv_tbl[] = {0, 1, 2, 2}; -+ -+ syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); -+ xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; -+ -+ clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0); -+ clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; -+ -+ curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); -+ ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; -+ ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; -+ -+ if (xtal_sel <= 2) -+ xtal_clk = 20 * 1000 * 1000; -+ else if (xtal_sel <= 5) -+ xtal_clk = 40 * 1000 * 1000; -+ else -+ xtal_clk = 25 * 1000 * 1000; - - switch (clk_sel) { - case 0: -- clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); -- cpu_fdiv = ((clk_sts >> 8) & 0x1F); -- cpu_ffrac = (clk_sts & 0x1F); -- cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000; -+ cpu_clk = 500 * 1000 * 1000; - break; -- - case 1: -- fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; -- syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); -- xtal_mode = (syscfg >> 6) & 0x7; -- if (xtal_mode >= 6) { -- /* 25Mhz Xtal */ -- cpu_clk = 25 * fbdiv * 1000 * 1000; -- } else if (xtal_mode >= 3) { -- /* 40Mhz Xtal */ -- cpu_clk = 40 * fbdiv * 1000 * 1000; -- } else { -- /* 20Mhz Xtal */ -- cpu_clk = 20 * fbdiv * 1000 * 1000; -- } -+ pll = rt_memc_r32(MEMC_REG_CPU_PLL); -+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; -+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; -+ cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; - break; -+ default: -+ cpu_clk = xtal_clk; - } -+ -+ cpu_clk = cpu_clk / ffiv * ffrac; -+ bus_clk = cpu_clk / 4; -+ -+ clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk); -+ clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk); -+ -+ pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000); -+ mips_hpt_frequency = cpu_clk / 2; - } - -+static void __init mt7621_clocks_init_dt(struct device_node *np) -+{ -+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -+} -+ -+CLK_OF_DECLARE(ar7100, "mediatek,mt7621-pll", mt7621_clocks_init_dt); -+ - void __init ralink_of_remap(void) - { - rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); ---- a/arch/mips/ralink/timer-gic.c -+++ b/arch/mips/ralink/timer-gic.c -@@ -9,14 +9,14 @@ - - #include - #include --#include -+#include - - #include "common.h" - - void __init plat_time_init(void) - { - ralink_of_remap(); -- -+ ralink_clk_init(); - of_clk_init(NULL); - timer_probe(); - } ---- /dev/null -+++ b/include/dt-bindings/clock/mt7621-clk.h -@@ -0,0 +1,18 @@ -+/* -+ * Copyright (C) 2018 Weijie Gao -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __DT_BINDINGS_MT7621_CLK_H -+#define __DT_BINDINGS_MT7621_CLK_H -+ -+#define MT7621_CLK_CPU 0 -+#define MT7621_CLK_BUS 1 -+ -+#define MT7621_CLK_MAX 2 -+ -+#endif /* __DT_BINDINGS_MT7621_CLK_H */ diff --git a/target/linux/ramips/patches-5.4/105-mt7621-memory-detect.patch b/target/linux/ramips/patches-5.4/105-mt7621-memory-detect.patch deleted file mode 100644 index 277d2aa43c..0000000000 --- a/target/linux/ramips/patches-5.4/105-mt7621-memory-detect.patch +++ /dev/null @@ -1,125 +0,0 @@ -From b5a52351a66f3c2a7a207548aa87d78ff2d336c0 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Wed, 10 Jul 2019 00:24:48 +0800 -Subject: [PATCH] MIPS: ralink: mt7621: add memory detection support - -mt7621 has the following memory map: -0x0-0x1c000000: lower 448m memory -0x1c000000-0x2000000: peripheral registers -0x20000000-0x2400000: higher 64m memory - -detect_memory_region in arch/mips/kernel/setup.c only add the first -memory region and isn't suitable for 512m memory detection because -it may accidentally read the memory area for peripheral registers. - -This commit adds memory detection capability for mt7621: -1. add the highmem area when 512m is detected. -2. guard memcmp from accessing peripheral registers: - This only happens when some weird user decided to change - kernel load address to 256m or higher address. Since this - is a quite unusual case, we just skip 512m testing and return - 256m as memory size. - -Signed-off-by: Chuanhong Guo ---- - arch/mips/include/asm/mach-ralink/mt7621.h | 7 ++--- - arch/mips/ralink/mt7621.c | 30 +++++++++++++++++++--- - 2 files changed, 30 insertions(+), 7 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/mt7621.h -+++ b/arch/mips/include/asm/mach-ralink/mt7621.h -@@ -44,9 +44,10 @@ - #define CPU_PLL_FBDIV_MASK 0x7f - #define CPU_PLL_FBDIV_SHIFT 4 - --#define MT7621_DRAM_BASE 0x0 --#define MT7621_DDR2_SIZE_MIN 32 --#define MT7621_DDR2_SIZE_MAX 256 -+#define MT7621_LOWMEM_BASE 0x0 -+#define MT7621_LOWMEM_MAX_SIZE 0x1C000000 -+#define MT7621_HIGHMEM_BASE 0x20000000 -+#define MT7621_HIGHMEM_SIZE 0x4000000 - - #define MT7621_CHIP_NAME0 0x3637544D - #define MT7621_CHIP_NAME1 0x20203132 ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -13,6 +13,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -55,6 +56,8 @@ - #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 - #define MT7621_GPIO_MODE_SDHCI_GPIO 1 - -+static void *detect_magic __initdata = detect_memory_region; -+ - static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; - static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; - static struct rt2880_pmx_func uart3_grp[] = { -@@ -139,6 +142,28 @@ static struct clk *__init mt7621_add_sys - return clk; - } - -+void __init mt7621_memory_detect(void) -+{ -+ void *dm = &detect_magic; -+ phys_addr_t size; -+ -+ for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) { -+ if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic))) -+ break; -+ } -+ -+ if ((size == 256 * SZ_1M) && -+ (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) && -+ __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) { -+ add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE, -+ BOOT_MEM_RAM); -+ add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE, -+ BOOT_MEM_RAM); -+ } else { -+ add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM); -+ } -+} -+ - void __init ralink_clk_init(void) - { - u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; -@@ -317,10 +342,7 @@ void prom_soc_init(struct ralink_soc_inf - (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, - (rev & CHIP_REV_ECO_MASK)); - -- soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; -- soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; -- soc_info->mem_base = MT7621_DRAM_BASE; -- -+ soc_info->mem_detect = mt7621_memory_detect; - rt2880_pinmux_data = mt7621_pinmux_data; - - ---- a/arch/mips/ralink/common.h -+++ b/arch/mips/ralink/common.h -@@ -17,6 +17,7 @@ struct ralink_soc_info { - unsigned long mem_size; - unsigned long mem_size_min; - unsigned long mem_size_max; -+ void (*mem_detect)(void); - }; - extern struct ralink_soc_info soc_info; - ---- a/arch/mips/ralink/of.c -+++ b/arch/mips/ralink/of.c -@@ -87,6 +87,8 @@ void __init plat_mem_setup(void) - of_scan_flat_dt(early_init_dt_find_memory, NULL); - if (memory_dtb) - of_scan_flat_dt(early_init_dt_scan_memory, NULL); -+ else if (soc_info.mem_detect) -+ soc_info.mem_detect(); - else if (soc_info.mem_size) - add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M, - BOOT_MEM_RAM); diff --git a/target/linux/ramips/patches-5.4/110-mt7621-perfctr-fix.patch b/target/linux/ramips/patches-5.4/110-mt7621-perfctr-fix.patch deleted file mode 100644 index dfeac7eb99..0000000000 --- a/target/linux/ramips/patches-5.4/110-mt7621-perfctr-fix.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/mips/ralink/irq-gic.c -+++ b/arch/mips/ralink/irq-gic.c -@@ -13,6 +13,12 @@ - - int get_c0_perfcount_int(void) - { -+ /* -+ * Performance counter events are routed through GIC. -+ * Prevent them from firing on CPU IRQ7 as well -+ */ -+ clear_c0_status(IE_SW0 << 7); -+ - return gic_get_c0_perfcount_int(); - } - EXPORT_SYMBOL_GPL(get_c0_perfcount_int); diff --git a/target/linux/ramips/patches-5.4/111-gpio-mmio-introduce-BGPIOF_NO_SET_ON_INPUT.patch b/target/linux/ramips/patches-5.4/111-gpio-mmio-introduce-BGPIOF_NO_SET_ON_INPUT.patch deleted file mode 100644 index fdb89d0902..0000000000 --- a/target/linux/ramips/patches-5.4/111-gpio-mmio-introduce-BGPIOF_NO_SET_ON_INPUT.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 5d7b644aad721ecca20bd8976b38fb243fdc84f9 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 15 Mar 2020 20:13:37 +0800 -Subject: [PATCH] gpio: mmio: introduce BGPIOF_NO_SET_ON_INPUT -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Some gpio controllers ignores pin value writing when that pin is -configured as input mode. As a result, bgpio_dir_out should set -pin to output before configuring pin values or gpio pin values -can't be set up properly. -Introduce two variants of bgpio_dir_out: bgpio_dir_out_val_first -and bgpio_dir_out_dir_first, and assign direction_output according -to a new flag: BGPIOF_NO_SET_ON_INPUT. - -Signed-off-by: Chuanhong Guo -Tested-by: René van Dorst -Reviewed-by: Sergio Paracuellos -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/gpio-mmio.c | 23 +++++++++++++++++++---- - include/linux/gpio/driver.h | 1 + - 2 files changed, 20 insertions(+), 4 deletions(-) - ---- a/drivers/gpio/gpio-mmio.c -+++ b/drivers/gpio/gpio-mmio.c -@@ -381,12 +381,10 @@ static int bgpio_get_dir(struct gpio_chi - return 1; - } - --static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) -+static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) - { - unsigned long flags; - -- gc->set(gc, gpio, val); -- - spin_lock_irqsave(&gc->bgpio_lock, flags); - - gc->bgpio_dir |= bgpio_line2mask(gc, gpio); -@@ -397,7 +395,21 @@ static int bgpio_dir_out(struct gpio_chi - gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); - - spin_unlock_irqrestore(&gc->bgpio_lock, flags); -+} - -+static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, -+ int val) -+{ -+ bgpio_dir_out(gc, gpio, val); -+ gc->set(gc, gpio, val); -+ return 0; -+} -+ -+static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, -+ int val) -+{ -+ gc->set(gc, gpio, val); -+ bgpio_dir_out(gc, gpio, val); - return 0; - } - -@@ -530,7 +542,10 @@ static int bgpio_setup_direction(struct - if (dirout || dirin) { - gc->reg_dir_out = dirout; - gc->reg_dir_in = dirin; -- gc->direction_output = bgpio_dir_out; -+ if (flags & BGPIOF_NO_SET_ON_INPUT) -+ gc->direction_output = bgpio_dir_out_dir_first; -+ else -+ gc->direction_output = bgpio_dir_out_val_first; - gc->direction_input = bgpio_dir_in; - gc->get_direction = bgpio_get_dir; - } else { ---- a/include/linux/gpio/driver.h -+++ b/include/linux/gpio/driver.h -@@ -567,6 +567,7 @@ int bgpio_init(struct gpio_chip *gc, str - #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) - #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ - #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ -+#define BGPIOF_NO_SET_ON_INPUT BIT(6) - - int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq); diff --git a/target/linux/ramips/patches-5.4/112-gpio-mt7621-add-BGPIOF_NO_SET_ON_INPUT-flag.patch b/target/linux/ramips/patches-5.4/112-gpio-mt7621-add-BGPIOF_NO_SET_ON_INPUT-flag.patch deleted file mode 100644 index 862f9adb47..0000000000 --- a/target/linux/ramips/patches-5.4/112-gpio-mt7621-add-BGPIOF_NO_SET_ON_INPUT-flag.patch +++ /dev/null @@ -1,33 +0,0 @@ -From ad65f02fd73e9a700f1693a4513ae923ca07beb0 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 15 Mar 2020 20:13:38 +0800 -Subject: [PATCH] gpio: mt7621: add BGPIOF_NO_SET_ON_INPUT flag -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -DSET/DCLR registers only works on output pins. Add corresponding -BGPIOF_NO_SET_ON_INPUT flag to bgpio_init call to fix direction_out -behavior. - -Signed-off-by: Chuanhong Guo -Tested-by: René van Dorst -Reviewed-by: Sergio Paracuellos -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/gpio-mt7621.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/gpio/gpio-mt7621.c -+++ b/drivers/gpio/gpio-mt7621.c -@@ -227,8 +227,8 @@ mediatek_gpio_bank_probe(struct device * - ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); - diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); - -- ret = bgpio_init(&rg->chip, dev, 4, -- dat, set, ctrl, diro, NULL, 0); -+ ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL, -+ BGPIOF_NO_SET_ON_INPUT); - if (ret) { - dev_err(dev, "bgpio_init() failed\n"); - return ret; diff --git a/target/linux/ramips/patches-5.4/200-add-ralink-eth.patch b/target/linux/ramips/patches-5.4/200-add-ralink-eth.patch deleted file mode 100644 index 79e7c2309b..0000000000 --- a/target/linux/ramips/patches-5.4/200-add-ralink-eth.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -160,6 +160,7 @@ source "drivers/net/ethernet/pasemi/Kcon - source "drivers/net/ethernet/pensando/Kconfig" - source "drivers/net/ethernet/qlogic/Kconfig" - source "drivers/net/ethernet/qualcomm/Kconfig" -+source "drivers/net/ethernet/ralink/Kconfig" - source "drivers/net/ethernet/rdc/Kconfig" - source "drivers/net/ethernet/realtek/Kconfig" - source "drivers/net/ethernet/renesas/Kconfig" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -72,6 +72,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES) - obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/ - obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/ - obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/ -+obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/ - obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/ - obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ - obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ diff --git a/target/linux/ramips/patches-5.4/300-mt7620-export-chip-version-and-pkg.patch b/target/linux/ramips/patches-5.4/300-mt7620-export-chip-version-and-pkg.patch deleted file mode 100644 index 8b4335eb03..0000000000 --- a/target/linux/ramips/patches-5.4/300-mt7620-export-chip-version-and-pkg.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -135,4 +135,16 @@ static inline int mt7620_get_eco(void) - return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; - } - -+static inline int mt7620_get_chipver(void) -+{ -+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) & -+ CHIP_REV_VER_MASK; -+} -+ -+static inline int mt7620_get_pkg(void) -+{ -+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) & -+ CHIP_REV_PKG_MASK; -+} -+ - #endif diff --git a/target/linux/ramips/patches-5.4/301-MIPS-ralink-mt7621-introduce-soc_device-initializati.patch b/target/linux/ramips/patches-5.4/301-MIPS-ralink-mt7621-introduce-soc_device-initializati.patch deleted file mode 100644 index dc3dd0d1ec..0000000000 --- a/target/linux/ramips/patches-5.4/301-MIPS-ralink-mt7621-introduce-soc_device-initializati.patch +++ /dev/null @@ -1,89 +0,0 @@ -From f798b7588bd7397bbab958281ca6c88d08714941 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Thu, 12 Mar 2020 12:29:15 +0100 -Subject: [PATCH] MIPS: ralink: mt7621: introduce 'soc_device' initialization - -mt7621 SoC has its own 'ralink_soc_info' structure with some -information about the soc itself. Pcie controller and pcie phy -drivers for this soc which are still in staging git tree make uses -of 'soc_device_attribute' looking for revision 'E2' in order to -know if reset lines are or not inverted. This way of doing things -seems to be necessary in order to make things clean and properly. -Hence, introduce this 'soc_device' to be able to properly use those -attributes in drivers. Also set 'data' pointer points to the struct -'ralink_soc_info' to be able to export also current soc information -using this mechanism. - -Cc: Paul Burton -Cc: ralf@linux-mips.org -Cc: jhogan@kernel.org -Cc: john@phrozen.org -Cc: NeilBrown -Cc: Greg Kroah-Hartman -Cc: linux-mips@vger.kernel.org - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ralink/mt7621.c | 32 +++++++++++++++++++++++++++++++- - 1 file changed, 31 insertions(+), 1 deletion(-) - ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -7,6 +7,8 @@ - - #include - #include -+#include -+#include - #include - #include - #include -@@ -294,6 +296,33 @@ static int udelay_recal(void) - } - device_initcall(udelay_recal); - -+static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev) -+{ -+ struct soc_device *soc_dev; -+ struct soc_device_attribute *soc_dev_attr; -+ -+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); -+ if (!soc_dev_attr) -+ return; -+ -+ soc_dev_attr->soc_id = "mt7621"; -+ soc_dev_attr->family = "Ralink"; -+ -+ if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 && -+ (rev & CHIP_REV_ECO_MASK) == 1) -+ soc_dev_attr->revision = "E2"; -+ else -+ soc_dev_attr->revision = "E1"; -+ -+ soc_dev_attr->data = soc_info; -+ -+ soc_dev = soc_device_register(soc_dev_attr); -+ if (IS_ERR(soc_dev)) { -+ kfree(soc_dev_attr); -+ return; -+ } -+} -+ - void prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); -@@ -345,11 +374,12 @@ void prom_soc_init(struct ralink_soc_inf - soc_info->mem_detect = mt7621_memory_detect; - rt2880_pinmux_data = mt7621_pinmux_data; - -- - if (!register_cps_smp_ops()) - return; - if (!register_cmp_smp_ops()) - return; - if (!register_vsmp_smp_ops()) - return; -+ -+ soc_dev_init(soc_info, rev); - } diff --git a/target/linux/ramips/patches-5.4/302-spi-nor-add-gd25q512.patch b/target/linux/ramips/patches-5.4/302-spi-nor-add-gd25q512.patch deleted file mode 100644 index d5de4e45bc..0000000000 --- a/target/linux/ramips/patches-5.4/302-spi-nor-add-gd25q512.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -2306,6 +2306,11 @@ static const struct flash_info spi_nor_i - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - .fixups = &gd25q256_fixups, - }, -+ { -+ "gd25q512", INFO(0xc84020, 0, 64 * 1024, 1024, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES) -+ }, - - /* Intel/Numonyx -- xxxs33b */ - { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, diff --git a/target/linux/ramips/patches-5.4/401-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.4/401-net-ethernet-mediatek-support-net-labels.patch deleted file mode 100644 index be453a6d7a..0000000000 --- a/target/linux/ramips/patches-5.4/401-net-ethernet-mediatek-support-net-labels.patch +++ /dev/null @@ -1,34 +0,0 @@ -From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= -Date: Fri, 21 Jun 2019 10:04:05 +0200 -Subject: [PATCH] net: ethernet: mediatek: support net-labels - -With this patch, device name can be set within dts file in the same way as dsa -port can. -Add: label = "wan"; to GMAC node. - -Signed-off-by: René van Dorst ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2940,6 +2940,7 @@ static const struct net_device_ops mtk_n - - static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) - { -+ const char *name = of_get_property(np, "label", NULL); - const __be32 *_id = of_get_property(np, "reg", NULL); - struct phylink *phylink; - int phy_mode, id, err; -@@ -3032,6 +3033,9 @@ static int mtk_add_mac(struct mtk_eth *e - - eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; - -+ if (name) -+ strlcpy(eth->netdev[id]->name, name, IFNAMSIZ); -+ - return 0; - - free_netdev: diff --git a/target/linux/ramips/patches-5.4/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch b/target/linux/ramips/patches-5.4/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch deleted file mode 100644 index 728876322c..0000000000 --- a/target/linux/ramips/patches-5.4/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Thu, 6 May 2021 17:49:55 +0200 -Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as - -Add MTD support for the BoHong bh25q128as SPI NOR chip. -The chip has 16MB of total capacity, divided into a total of 256 -sectors, each 64KB sized. The chip also supports 4KB sectors. -Additionally, it supports dual and quad read modes. - -Functionality was verified on an Tenbay WR1800K / MTK MT7621 board. - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/Makefile | 1 + - drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++ - drivers/mtd/spi-nor/core.c | 1 + - drivers/mtd/spi-nor/core.h | 1 + - 4 files changed, 24 insertions(+) - create mode 100644 drivers/mtd/spi-nor/bohong.c - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -2233,6 +2233,10 @@ static const struct flash_info spi_nor_i - - { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, - -+ /* BoHong Microelectronics */ -+ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ - /* EON -- en25xxx */ - { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, - { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, diff --git a/target/linux/ramips/patches-5.4/804-staging-mt7621-pinctrl-use-ngpios-not-num-gpios.patch b/target/linux/ramips/patches-5.4/804-staging-mt7621-pinctrl-use-ngpios-not-num-gpios.patch deleted file mode 100644 index 0d62bd8b03..0000000000 --- a/target/linux/ramips/patches-5.4/804-staging-mt7621-pinctrl-use-ngpios-not-num-gpios.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c -+++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c -@@ -354,7 +354,7 @@ static int rt2880_pinmux_probe(struct pl - if (!of_device_is_available(np)) - continue; - -- ngpio = of_get_property(np, "ralink,num-gpios", NULL); -+ ngpio = of_get_property(np, "ngpios", NULL); - gpiobase = of_get_property(np, "ralink,gpio-base", NULL); - if (!ngpio || !gpiobase) { - dev_err(&pdev->dev, "failed to load chip info\n"); diff --git a/target/linux/ramips/patches-5.4/805-pinctrl-AW9523.patch b/target/linux/ramips/patches-5.4/805-pinctrl-AW9523.patch deleted file mode 100644 index d8e17a671a..0000000000 --- a/target/linux/ramips/patches-5.4/805-pinctrl-AW9523.patch +++ /dev/null @@ -1,72 +0,0 @@ -From: AngeloGioacchino Del Regno - -To: linus.walleij@linaro.org -Cc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, - marijn.suijten@somainline.org, martin.botka@somainline.org, - phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org, - devicetree@vger.kernel.org, robh+dt@kernel.org, - AngeloGioacchino Del Regno - -Subject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO - Expander -Date: Mon, 25 Jan 2021 19:22:18 +0100 - -The Awinic AW9523(B) is a multi-function I2C gpio expander in a -TQFN-24L package, featuring PWM (max 37mA per pin, or total max -power 3.2Watts) for LED driving capability. - -It has two ports with 8 pins per port (for a total of 16 pins), -configurable as either PWM with 1/256 stepping or GPIO input/output, -1.8V logic input; each GPIO can be configured as input or output -independently from each other. - -This IC also has an internal interrupt controller, which is capable -of generating an interrupt for each GPIO, depending on the -configuration, and will raise an interrupt on the INTN pin to -advertise this to an external interrupt controller. - -Signed-off-by: AngeloGioacchino Del Regno ---- - drivers/pinctrl/Kconfig | 17 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++ - 3 files changed, 1140 insertions(+) - create mode 100644 drivers/pinctrl/pinctrl-aw9523.c - ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -109,6 +109,24 @@ config PINCTRL_AMD - Requires ACPI/FDT device enumeration code to set up a platform - device. - -+config PINCTRL_AW9523 -+ bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver" -+ depends on OF && I2C -+ select PINMUX -+ select PINCONF -+ select GENERIC_PINCONF -+ select GPIOLIB -+ select GPIOLIB_IRQCHIP -+ select REGMAP -+ select REGMAP_I2C -+ help -+ The Awinic AW9523/AW9523B is a multi-function I2C GPIO -+ expander with PWM functionality. This driver bundles a -+ pinctrl driver to select the function muxing and a GPIO -+ driver to handle GPIO, when the GPIO function is selected. -+ -+ Say yes to enable pinctrl and GPIO support for the AW9523(B). -+ - config PINCTRL_BM1880 - bool "Bitmain BM1880 Pinctrl driver" - depends on OF && (ARCH_BITMAIN || COMPILE_TEST) ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl- - obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o - obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o - obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o -+obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o - obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o - obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o - obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o diff --git a/target/linux/ramips/patches-5.4/990-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-5.4/990-NET-no-auto-carrier-off-support.patch deleted file mode 100644 index 8b95eacab1..0000000000 --- a/target/linux/ramips/patches-5.4/990-NET-no-auto-carrier-off-support.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:38:50 +0100 -Subject: [PATCH 34/53] NET: multi phy support - -Signed-off-by: John Crispin ---- - drivers/net/phy/phy.c | 9 ++++++--- - include/linux/phy.h | 1 + - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/phy.c -+++ b/drivers/net/phy/phy.c -@@ -549,7 +549,10 @@ static int phy_check_link_status(struct - phy_link_up(phydev); - } else if (!phydev->link && phydev->state != PHY_NOLINK) { - phydev->state = PHY_NOLINK; -- phy_link_down(phydev, true); -+ if (!phydev->no_auto_carrier_off) -+ phy_link_down(phydev, true); -+ else -+ phy_link_down(phydev, false); - } - - return 0; -@@ -947,7 +950,10 @@ void phy_state_machine(struct work_struc - case PHY_HALTED: - if (phydev->link) { - phydev->link = 0; -- phy_link_down(phydev, true); -+ if (!phydev->no_auto_carrier_off) -+ phy_link_down(phydev, true); -+ else -+ phy_link_down(phydev, false); - } - do_suspend = true; - break; ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -381,6 +381,7 @@ struct phy_device { - unsigned suspended_by_mdio_bus:1; - unsigned sysfs_links:1; - unsigned loopback_enabled:1; -+ unsigned no_auto_carrier_off:1; - - unsigned autoneg:1; - /* The most recently read link state */ diff --git a/target/linux/ramips/patches-5.4/991-at803x.patch b/target/linux/ramips/patches-5.4/991-at803x.patch deleted file mode 100644 index a0d9a03fcf..0000000000 --- a/target/linux/ramips/patches-5.4/991-at803x.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 924453aa9d2324e5611f8e2b71df746d8f0c79f1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= -Date: Fri, 13 Nov 2020 16:11:32 +0100 -Subject: [PATCH] net: phy: at803x: add support for SFP module in - RGMII-to-x-base mode -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: René van Dorst ---- - drivers/net/phy/at803x.c | 91 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 91 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -14,6 +14,8 @@ - #include - #include - #include -+#include -+#include - - #define AT803X_SPECIFIC_STATUS 0x11 - #define AT803X_SS_SPEED_MASK (3 << 14) -@@ -52,9 +54,18 @@ - - #define AT803X_MODE_CFG_MASK 0x0F - #define AT803X_MODE_CFG_SGMII 0x01 -+#define AT803X_MODE_CFG_BX1000_RGMII_50 0x02 -+#define AT803X_MODE_CFG_BX1000_RGMII_75 0x03 -+#define AT803X_MODE_FIBER 0x01 -+#define AT803X_MODE_COPPER 0x00 - - #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ - #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 -+#define PSSR_LINK BIT(10) -+#define PSSR_SYNC_STATUS BIT(8) -+#define PSSR_DUPLEX BIT(13) -+#define PSSR_SPEED_1000 BIT(15) -+#define PSSR_SPEED_100 BIT(14) - - #define AT803X_DEBUG_REG_0 0x00 - #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) -@@ -274,18 +285,80 @@ static int at803x_resume(struct phy_devi - return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); - } - -+static int at803x_mode(struct phy_device *phydev) -+{ -+ int mode; -+ -+ mode = phy_read(phydev, AT803X_REG_CHIP_CONFIG) & AT803X_MODE_CFG_MASK; -+ -+ if (mode == AT803X_MODE_CFG_BX1000_RGMII_50 || -+ mode == AT803X_MODE_CFG_BX1000_RGMII_75) -+ return AT803X_MODE_FIBER; -+ return AT803X_MODE_COPPER; -+} -+ -+static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) -+{ -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(at803x_support) = { 0, }; -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; -+ struct phy_device *phydev = upstream; -+ phy_interface_t iface; -+ -+ phylink_set(at803x_support, 1000baseX_Full); -+ /* AT803x only support 1000baseX but SGMII works fine when module runs -+ * at 1Gbit. -+ */ -+ phylink_set(at803x_support, 1000baseT_Full); -+ -+ sfp_parse_support(phydev->sfp_bus, id, support); -+ -+ // Limit to interfaces that both sides support -+ linkmode_and(support, support, at803x_support); -+ -+ if (linkmode_empty(support)) -+ goto unsupported_mode; -+ -+ iface = sfp_select_interface(phydev->sfp_bus, support); -+ -+ if (iface != PHY_INTERFACE_MODE_SGMII && -+ iface != PHY_INTERFACE_MODE_1000BASEX) -+ goto unsupported_mode; -+ -+ dev_info(&phydev->mdio.dev, "SFP interface %s", phy_modes(iface)); -+ -+ return 0; -+ -+unsupported_mode: -+ dev_info(&phydev->mdio.dev, "incompatible SFP module inserted;" -+ "Only SGMII at 1Gbit/1000BASEX are supported!\n"); -+ return -EINVAL; -+} -+ -+static const struct sfp_upstream_ops at803x_sfp_ops = { -+ .attach = phy_sfp_attach, -+ .detach = phy_sfp_detach, -+ .module_insert = at803x_sfp_insert, -+}; -+ - static int at803x_probe(struct phy_device *phydev) - { - struct device *dev = &phydev->mdio.dev; - struct at803x_priv *priv; - int ret = 0; - -+ if (at803x_mode(phydev) == AT803X_MODE_FIBER) { -+ ret = phy_sfp_probe(phydev, &at803x_sfp_ops); -+ if (ret < 0) -+ return ret; -+ } -+ - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - phydev->priv = priv; - -+#if 0 - /* Some bootloaders leave the fiber page selected. - * Switch to the copper page, as otherwise we read - * the PHY capabilities from the fiber side. -@@ -295,6 +368,7 @@ static int at803x_probe(struct phy_devic - ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); - mutex_unlock(&phydev->mdio.bus->mdio_lock); - } -+#endif - - return ret; - } -@@ -419,6 +493,7 @@ static int at803x_get_features(struct ph - if (err) - return err; - -+#if 0 - if (!(phydev->phy_id & phydev->drv->phy_id_mask) == (ATH8031_PHY_ID & phydev->drv->phy_id_mask)) - return 0; - -@@ -436,6 +511,7 @@ static int at803x_get_features(struct ph - */ - linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, - phydev->supported); -+#endif - return 0; - } - -@@ -443,6 +519,10 @@ static int at803x_read_status(struct phy - { - int ss, err, old_link = phydev->link; - -+ /* Handle (Fiber) SGMII to RGMII mode */ -+ if (at803x_mode(phydev) == AT803X_MODE_FIBER) -+ return genphy_c37_read_status(phydev); -+ - /* Update the link, but return if there was an error */ - err = genphy_update_link(phydev); - if (err) -@@ -497,6 +577,19 @@ static int at803x_read_status(struct phy - return 0; - } - -+static int at803x_config_aneg(struct phy_device *phydev) -+{ -+ /* Handle (Fiber) SerDes to RGMII mode */ -+ if (at803x_mode(phydev) == AT803X_MODE_FIBER) { -+ pr_warn("%s: fiber\n", __func__); -+ return genphy_c37_config_aneg(phydev); -+ } -+ -+ pr_warn("%s: enter\n", __func__); -+ -+ return genphy_config_aneg(phydev); -+} -+ - static struct phy_driver at803x_driver[] = { - { - /* ATHEROS 8035 */ -@@ -532,6 +625,7 @@ static struct phy_driver at803x_driver[] - /* ATHEROS 8031 */ - .phy_id = ATH8031_PHY_ID, - .name = "Atheros 8031 ethernet", -+ .config_aneg = at803x_config_aneg, - .phy_id_mask = AT803X_PHY_ID_MASK, - .probe = at803x_probe, - .config_init = at803x_config_init, diff --git a/target/linux/ramips/rt288x/config-5.4 b/target/linux/ramips/rt288x/config-5.4 deleted file mode 100644 index 2ddcb15741..0000000000 --- a/target/linux/ramips/rt288x/config-5.4 +++ /dev/null @@ -1,177 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -# CONFIG_DTB_RT2880_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_RALINK=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IP17XX_PHY=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=4 -CONFIG_MIPS_L1_CACHE_SHIFT_4=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_LZMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_RT2880=y -CONFIG_NET_RALINK_RT2880=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NLS=m -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -# CONFIG_PHY_RALINK_USB is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -CONFIG_SOC_RT288X=y -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB=m -CONFIG_USB_COMMON=m -CONFIG_USB_EHCI_HCD=m -CONFIG_USB_EHCI_HCD_PLATFORM=m -CONFIG_USB_OHCI_HCD=m -CONFIG_USB_OHCI_HCD_PLATFORM=m -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/rt305x/config-5.4 b/target/linux/ramips/rt305x/config-5.4 deleted file mode 100644 index 8ba86b501c..0000000000 --- a/target/linux/ramips/rt305x/config-5.4 +++ /dev/null @@ -1,176 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -# CONFIG_DTB_RT305X_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_RALINK=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384 -CONFIG_MTD_SPLIT_JIMAGE_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_ESW_RT3050=y -CONFIG_NET_RALINK_RT3050=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -# CONFIG_RALINK_ILL_ACC is not set -CONFIG_RALINK_WDT=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -CONFIG_SOC_RT305X=y -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/rt3883/config-5.4 b/target/linux/ramips/rt3883/config-5.4 deleted file mode 100644 index 49e449f8b9..0000000000 --- a/target/linux/ramips/rt3883/config-5.4 +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -# CONFIG_DTB_RT3883_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_RALINK=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384 -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_RT2880=y -CONFIG_NET_RALINK_RT3883=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL8366_SMI=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -CONFIG_SOC_RT3883=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y