From 4646aa169986036772b9f75393c08508d20ddf8b Mon Sep 17 00:00:00 2001 From: Ivan Romanov Date: Mon, 26 Aug 2024 12:45:38 +0500 Subject: [PATCH 01/23] build: fix CMake generator for non-Ninja builds OpenWRT by default uses the Ninja generator, but some packages disable Ninja and use the default Unix Makefiles generator. This generator can be overridden in the user environment with `CMAKE_GENERATOR`. This patch explicitly sets the correct generator when `PKG_USE_NINJA:=0`. In particular, the `mt76` package uses the Makefiles generator. Signed-off-by: Ivan Romanov Link: https://github.com/openwrt/openwrt/pull/16263 Signed-off-by: Hauke Mehrtens --- include/cmake.mk | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/cmake.mk b/include/cmake.mk index c82ba5f809..00ade7fd7d 100644 --- a/include/cmake.mk +++ b/include/cmake.mk @@ -68,6 +68,8 @@ ifeq ($(HOST_USE_NINJA),1) define Host/Uninstall/Default +$(NINJA) -C $(HOST_CMAKE_BINARY_DIR) uninstall endef +else + CMAKE_HOST_OPTIONS += -DCMAKE_GENERATOR="Unix Makefiles" endif ifeq ($(PKG_USE_NINJA),1) @@ -80,6 +82,8 @@ ifeq ($(PKG_USE_NINJA),1) define Build/Install/Default +DESTDIR="$(PKG_INSTALL_DIR)" $(NINJA) -C $(CMAKE_BINARY_DIR) install endef +else + CMAKE_OPTIONS += -DCMAKE_GENERATOR="Unix Makefiles" endif define Build/Configure/Default From c364cb8e469f9a7de1ed8960163c90e26b2df1ad Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 29 Aug 2024 20:04:02 +0200 Subject: [PATCH 02/23] include: autotools: do not symlink files in autoreconf In Gluon's Github Actions CI, we were occasionally seeing bizarre build errors that looked like a config.sub file had been corrupted, or changed while it was being executed. The cause turned out to be an interaction of the symlinks created by autoreconf (pointing from individual tools' build dirs into `staging_dir/host/share/automake-1.16`) and OpenWrt's host-build.mk, which replaced config.guess and config.sub *after* autoreconf. The result was that the replacement of these files ended up following the symlinks and writing the files in `staging_dir/host/share/automake-1.16` instead of a package's build dir. This could cause other packages' builds to fail if they were currently executing the scripts while they were being written. To fix this, disable autoreconf's symlinking feature, so that modifying these files in a package's build directory can't accidentally affect the staged versions. Link: https://github.com/openwrt/openwrt/pull/15825 Signed-off-by: Matthias Schiffer --- include/autotools.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/autotools.mk b/include/autotools.mk index d0e4b3642f..7fc6f37175 100644 --- a/include/autotools.mk +++ b/include/autotools.mk @@ -44,7 +44,7 @@ define autoreconf touch NEWS AUTHORS COPYING ABOUT-NLS ChangeLog; \ $(AM_TOOL_PATHS) \ LIBTOOLIZE='$(STAGING_DIR_HOST)/bin/libtoolize --install' \ - $(STAGING_DIR_HOST)/bin/autoreconf -v -f -i -s \ + $(STAGING_DIR_HOST)/bin/autoreconf -v -f -i \ $(if $(word 2,$(3)),--no-recursive) \ -B $(STAGING_DIR_HOST)/share/aclocal \ $(patsubst %,-I %,$(5)) \ From d6e54593198851235906c6ab77c20c6209ab19f5 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 29 Aug 2024 20:04:02 +0200 Subject: [PATCH 03/23] tools: libtool: do not symlink files in bootstrap Another instance of files in build_dir symlinking to staging_dir. While the symlinks do not currently cause any bugs in the libtool package, such symlinks were found to make the build more fragile, as writing to the symlink may accidentally modify the shared file in staging_dir. Pass --copy to bootstrap to disable the symlinking. Link: https://github.com/openwrt/openwrt/pull/15825 Signed-off-by: Matthias Schiffer --- tools/libtool/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/libtool/Makefile b/tools/libtool/Makefile index dd9afc05bd..533360d199 100644 --- a/tools/libtool/Makefile +++ b/tools/libtool/Makefile @@ -28,6 +28,7 @@ define Host/Bootstrap cd $(HOST_BUILD_DIR); \ $(AM_TOOL_PATHS) \ ./bootstrap \ + --copy \ --force \ --skip-git \ --skip-po \ From e231cdd0c65829b0169608fa55a2b3adb501c201 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Wed, 14 Aug 2024 11:24:43 +0900 Subject: [PATCH 04/23] uboot-rockchip: renumber patches renumber patches for upcoming new device support Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/16185 Signed-off-by: Hauke Mehrtens --- ...stream-dts-sync.patch => 000-backport-upstream-dts-sync.patch} | 0 ...ch => 001-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename package/boot/uboot-rockchip/patches/{001-backport-upstream-dts-sync.patch => 000-backport-upstream-dts-sync.patch} (100%) rename package/boot/uboot-rockchip/patches/{000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch => 001-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch} (100%) diff --git a/package/boot/uboot-rockchip/patches/001-backport-upstream-dts-sync.patch b/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch similarity index 100% rename from package/boot/uboot-rockchip/patches/001-backport-upstream-dts-sync.patch rename to package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch diff --git a/package/boot/uboot-rockchip/patches/000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch b/package/boot/uboot-rockchip/patches/001-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch similarity index 100% rename from package/boot/uboot-rockchip/patches/000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch rename to package/boot/uboot-rockchip/patches/001-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch From 8384c6d796d0daa4cbb7d1b208577c2c95e8c3e7 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Wed, 14 Aug 2024 11:26:48 +0900 Subject: [PATCH 05/23] rockchip: add support for Radxa ROCK 3C Radxa ROCK 3C is a high-performance, low-cost SBC[1] using the Rockchip RK3566. Hardware -------- - Rockchip RK3566 SoC - Quad A55 CPU - Mali-G52-2EE GPU - 1 TOPS @ INT8 NPU - 1GB/2GB/4GB LPDDR4 RAM - eMMC connector - Micro SD Card slot - NVMe SSD through the M.2 M Key connector(2230) or M.2 Extension board(2232/2260/2280) - SATA through the Radxa Penta SATA HAT - 1x Gigabit ethernet port(supports PoE with add-on PoE HAT) - WiFi6/BT5.4 (not supported yet on OpenWrt) - 1x USB 3.0 Type-A HOST port - 2x USB 2.0 Type-A HOST ports - 1x USB 2.0 Type-A OTG port - 40 Pin GPIO header [1] https://radxa.com/products/rock3/3c Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/16185 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-rockchip/Makefile | 8 + .../000-backport-upstream-dts-sync.patch | 729 +++++++++++++++++ ...rd-rockchip-add-Radxa-ROCK-3-Model-C.patch | 178 ++++ target/linux/rockchip/image/armv8.mk | 8 + ...arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch | 769 ++++++++++++++++++ ...ip-change-spi-max-frequency-for-Radx.patch | 26 + ...-rockchip-Add-support-for-NanoPi-R6S.patch | 2 +- ...c-add-led-aliases-and-stop-heartbeat.patch | 29 + 8 files changed, 1748 insertions(+), 1 deletion(-) create mode 100644 package/boot/uboot-rockchip/patches/002-board-rockchip-add-Radxa-ROCK-3-Model-C.patch create mode 100644 target/linux/rockchip/patches-6.6/009-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch create mode 100644 target/linux/rockchip/patches-6.6/010-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch create mode 100644 target/linux/rockchip/patches-6.6/122-rock-3c-add-led-aliases-and-stop-heartbeat.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 79c3b71148..b61cb78dbf 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -167,6 +167,13 @@ define U-Boot/radxa-cm3-io-rk3566 radxa_cm3-io endef +define U-Boot/rock-3c-rk3566 + $(U-Boot/rk3566/Default) + NAME:=ROCK 3C + BUILD_DEVICES:= \ + radxa_rock-3c +endef + # RK3568 boards define U-Boot/rk3568/Default @@ -270,6 +277,7 @@ UBOOT_TARGETS := \ rock-pi-e-rk3328 \ rock-pi-e-v3-rk3328 \ radxa-cm3-io-rk3566 \ + rock-3c-rk3566 \ bpi-r2-pro-rk3568 \ nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 \ diff --git a/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch b/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch index b6984ec3e5..bcc22bb510 100644 --- a/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch +++ b/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch @@ -765,3 +765,732 @@ +&usb_host0_ohci { + status = "okay"; +}; +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts +@@ -0,0 +1,726 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ model = "Radxa ROCK 3C"; ++ compatible = "radxa,rock-3c", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ mmc2 = &sdmmc1; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac1_clkin: external-gmac1-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac1_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ function = LED_FUNCTION_HEARTBEAT; ++ color = ; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led2>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ post-power-on-delay-ms = <100>; ++ power-off-delay-us = <5000000>; ++ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ vcc5v_dcin: vcc5v-dcin-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pwr_en>; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v_dcin>; ++ }; ++ ++ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb30_host_en>; ++ regulator-name = "vcc5v0_usb30_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_cam: vcc-cam-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_cam_en>; ++ regulator-name = "vcc_cam"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_mipi: vcc-mipi-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_mipi_en>; ++ regulator-name = "vcc_mipi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; ++ system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ #clock-cells = <1>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ eeprom: eeprom@50 { ++ compatible = "belling,bl24c16a", "atmel,24c16"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bluetooth { ++ bt_reg_on_h: bt-reg-on-h { ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_host_h: bt-wake-host-h { ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_h: bt-host-wake-h { ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ cam { ++ vcc_cam_en: vcc_cam_en { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ display { ++ vcc_mipi_en: vcc_mipi_en { ++ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ user_led2: user-led2 { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pwr_en: pcie-pwr-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { ++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_host_wake_h: wifi-host-wake-h { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_reg_on_h: wifi-reg-on-h { ++ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcca1v8_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcca1v8_pmu>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr50; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vcca1v8_pmu>; ++ status = "okay"; ++}; ++ ++&sfc { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb30_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb30_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_usb30_host>; ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/package/boot/uboot-rockchip/patches/002-board-rockchip-add-Radxa-ROCK-3-Model-C.patch b/package/boot/uboot-rockchip/patches/002-board-rockchip-add-Radxa-ROCK-3-Model-C.patch new file mode 100644 index 0000000000..22ced545fe --- /dev/null +++ b/package/boot/uboot-rockchip/patches/002-board-rockchip-add-Radxa-ROCK-3-Model-C.patch @@ -0,0 +1,178 @@ +From e6e82ce24d4e9d20c232db2a95b2d10faf8f2bcf Mon Sep 17 00:00:00 2001 +From: Maxim Moskalets +Date: Thu, 8 Aug 2024 22:37:10 +0300 +Subject: [PATCH] board: rockchip: add Radxa ROCK 3 Model C + +Based on rock-3a-rk3568_defconfig. +Tested on v1.31 revision. + +Board Specifications: +- Rockchip RK3566 +- 1/2/4GB LPDDR4 2112MT/s +- eMMC socket +- uSD card slot +- M.2 2230 Connector +- GbE LAN with POE +- 3.5mm jack with mic +- HDMI 2.0, MIPI DSI/CSI +- USB 3.0 Host, USB 2.0 Host/OTG +- 40-pin GPIO expansion ports + +Signed-off-by: Maxim Moskalets +Suggested-by: Jonas Karlman +Reviewed-by: Jonas Karlman +Tested-by: FUKAUMI Naoki +Reviewed-by: Kever Yang +--- + arch/arm/dts/rk3566-rock-3c-u-boot.dtsi | 18 +++++ + board/rockchip/evb_rk3568/MAINTAINERS | 7 ++ + configs/rock-3c-rk3566_defconfig | 97 +++++++++++++++++++++++++ + doc/board/rockchip/rockchip.rst | 1 + + 4 files changed, 123 insertions(+) + create mode 100644 arch/arm/dts/rk3566-rock-3c-u-boot.dtsi + create mode 100644 configs/rock-3c-rk3566_defconfig + +--- /dev/null ++++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x-u-boot.dtsi" ++ ++&sfc { ++ flash@0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++ }; ++}; ++ ++/ { ++ leds { ++ led-0 { ++ default-state = "on"; ++ }; ++ }; ++}; +--- a/board/rockchip/evb_rk3568/MAINTAINERS ++++ b/board/rockchip/evb_rk3568/MAINTAINERS +@@ -69,3 +69,10 @@ S: Maintained + F: configs/rock-3a-rk3568_defconfig + F: arch/arm/dts/rk3568-rock-3a.dts + F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi ++ ++ROCK-3C ++M: Jonas Karlman ++M: Maxim Moskalets ++S: Maintained ++F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi ++F: configs/rock-3c-rk3566_defconfig +--- /dev/null ++++ b/configs/rock-3c-rk3566_defconfig +@@ -0,0 +1,97 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=24000000 ++CONFIG_SF_DEFAULT_MODE=0x2000 ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-rock-3c" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SPL_SERIAL=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SF_DEFAULT_BUS=4 ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_SPL_RAM=y ++CONFIG_SCSI=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_ERRNO_STR=y +--- a/doc/board/rockchip/rockchip.rst ++++ b/doc/board/rockchip/rockchip.rst +@@ -106,6 +106,7 @@ List of mainline supported Rockchip boar + - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566) + - Powkiddy X55 (powkiddy-x55-rk3566) + - Radxa CM3 IO Board (radxa-cm3-io-rk3566) ++ - Radxa ROCK 3C (rock-3c-rk3566) + + * rk3568 + - Rockchip Evb-RK3568 (evb-rk3568) diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index e7e33079fb..92e53fab3b 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -140,6 +140,14 @@ define Device/radxa_rock-3a endef TARGET_DEVICES += radxa_rock-3a +define Device/radxa_rock-3c + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ROCK 3C + SOC := rk3566 + DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis +endef +TARGET_DEVICES += radxa_rock-3c + define Device/radxa_rock-5a DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK 5A diff --git a/target/linux/rockchip/patches-6.6/009-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch b/target/linux/rockchip/patches-6.6/009-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch new file mode 100644 index 0000000000..9901d9fff0 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/009-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch @@ -0,0 +1,769 @@ +From ee219017ddb50be14c60d3cbe3e51ac0b2008d40 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sun, 28 Apr 2024 20:36:18 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3C + +The Radxa ROCK 3C is a development board with the +Rockchip RK3566 SoC. It has the following features: + +- 1/2/4GB LPDDR4 +- 1x HDMI Type A +- 1x PCIE 2.0 slot +- 1x FAN connector +- 3.5mm jack with mic +- 1GbE RTL8211F Ethernet +- 1x USB 3.0, 3x USB 2.0 +- 40-pin expansion header +- MicroSD card/eMMC socket +- 16MB SPI NOR (gd25lq128d) +- AP6256 or AIC8800 WiFi/BT + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20240428123618.72170-3-amadeus@jmu.edu.cn +[dropped rk809-sound and not specified pmic sound properties] +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3566-rock-3c.dts | 726 ++++++++++++++++++ + 2 files changed, 727 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +@@ -0,0 +1,726 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ model = "Radxa ROCK 3C"; ++ compatible = "radxa,rock-3c", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ mmc2 = &sdmmc1; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac1_clkin: external-gmac1-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac1_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ function = LED_FUNCTION_HEARTBEAT; ++ color = ; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led2>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ post-power-on-delay-ms = <100>; ++ power-off-delay-us = <5000000>; ++ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ vcc5v_dcin: vcc5v-dcin-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pwr_en>; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v_dcin>; ++ }; ++ ++ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb30_host_en>; ++ regulator-name = "vcc5v0_usb30_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_cam: vcc-cam-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_cam_en>; ++ regulator-name = "vcc_cam"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_mipi: vcc-mipi-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_mipi_en>; ++ regulator-name = "vcc_mipi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; ++ system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ #clock-cells = <1>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ eeprom: eeprom@50 { ++ compatible = "belling,bl24c16a", "atmel,24c16"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bluetooth { ++ bt_reg_on_h: bt-reg-on-h { ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_host_h: bt-wake-host-h { ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_h: bt-host-wake-h { ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ cam { ++ vcc_cam_en: vcc_cam_en { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ display { ++ vcc_mipi_en: vcc_mipi_en { ++ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ user_led2: user-led2 { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pwr_en: pcie-pwr-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { ++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_host_wake_h: wifi-host-wake-h { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_reg_on_h: wifi-reg-on-h { ++ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcca1v8_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcca1v8_pmu>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr50; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vcca1v8_pmu>; ++ status = "okay"; ++}; ++ ++&sfc { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <120000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb30_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb30_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_usb30_host>; ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.6/010-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch b/target/linux/rockchip/patches-6.6/010-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch new file mode 100644 index 0000000000..936fe91c5d --- /dev/null +++ b/target/linux/rockchip/patches-6.6/010-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch @@ -0,0 +1,26 @@ +From 06f6dd4d607766a527e37529f2f3f90dd1464293 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Sun, 23 Jun 2024 11:33:29 +0900 +Subject: [PATCH] arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK + 3C + +SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20240623023329.1044-3-naoki@radxa.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +@@ -633,7 +633,7 @@ + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; +- spi-max-frequency = <120000000>; ++ spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; diff --git a/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch index e5afbb4f40..0da3272ed7 100644 --- a/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch +++ b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch @@ -17,7 +17,7 @@ Signed-off-by: Heiko Stuebner --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -104,4 +104,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na +@@ -105,4 +105,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb diff --git a/target/linux/rockchip/patches-6.6/122-rock-3c-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.6/122-rock-3c-add-led-aliases-and-stop-heartbeat.patch new file mode 100644 index 0000000000..ee5a297887 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/122-rock-3c-add-led-aliases-and-stop-heartbeat.patch @@ -0,0 +1,29 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +@@ -16,6 +16,10 @@ + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; ++ led-boot = &led_blue; ++ led-failsafe = &led_blue; ++ led-running = &led_blue; ++ led-upgrade = &led_blue; + }; + + chosen: chosen { +@@ -43,11 +47,11 @@ + leds { + compatible = "gpio-leds"; + +- led-0 { +- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; +- function = LED_FUNCTION_HEARTBEAT; ++ led_blue: led-0 { + color = ; +- linux,default-trigger = "heartbeat"; ++ default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + }; From 59fc334ed02ccf96721f3628660490f5d328a2b8 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Thu, 22 Aug 2024 10:09:21 +0900 Subject: [PATCH 06/23] rockchip: add support for Radxa ZERO 3E and 3W Radxa ZERO 3E and 3W are light, compact and tiny SBC[1][2] using the Rockchip RK3566. Hardware -------- - Rockchip RK3566 SoC - Quad A55 CPU - Mali-G52-2EE GPU - 1 TOPS @ INT8 NPU - 1GB/2GB/4GB/8G LPDDR4 RAM - Optional 8GB/16GB/32GB/64GB eMMC (3E) - Micro SD Card slot - 1x Gigabit ethernet port (supports PoE with add-on PoE HAT) (3E) - WiFi6/BT5.4 (3W) (not supported yet on OpenWrt) - 1x USB 3.0 Type-C HOST port - 1x USB 2.0 Type-C OTG port - Optional 40 Pin GPIO header [1] https://radxa.com/products/zeros/zero3e [2] https://radxa.com/products/zeros/zero3w Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/16185 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-rockchip/Makefile | 9 + .../000-backport-upstream-dts-sync.patch | 684 ++++++++++++++++++ ...DC-Kconfig-symbol-for-use-of-ADC-in-.patch | 67 ++ ...-board-rockchip-Add-Radxa-ZERO-3W-3E.patch | 295 ++++++++ target/linux/rockchip/image/armv8.mk | 20 + ...64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch | 657 +++++++++++++++++ ...ip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch | 64 ++ ...ip-add-gpio-line-names-to-radxa-zero.patch | 101 +++ ...-rockchip-Add-support-for-NanoPi-R6S.patch | 2 +- ...3-add-led-aliases-and-stop-heartbeat.patch | 30 + 10 files changed, 1928 insertions(+), 1 deletion(-) create mode 100644 package/boot/uboot-rockchip/patches/003-dm-adc-Add-SPL_ADC-Kconfig-symbol-for-use-of-ADC-in-.patch create mode 100644 package/boot/uboot-rockchip/patches/004-board-rockchip-Add-Radxa-ZERO-3W-3E.patch create mode 100644 target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch create mode 100644 target/linux/rockchip/patches-6.6/012-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch create mode 100644 target/linux/rockchip/patches-6.6/013-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch create mode 100644 target/linux/rockchip/patches-6.6/123-radxa-zero-3-add-led-aliases-and-stop-heartbeat.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index b61cb78dbf..cc834fb3ed 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -167,6 +167,14 @@ define U-Boot/radxa-cm3-io-rk3566 radxa_cm3-io endef +define U-Boot/radxa-zero-3-rk3566 + $(U-Boot/rk3566/Default) + NAME:=ZERO 3E/3W + BUILD_DEVICES:= \ + radxa_zero-3e \ + radxa_zero-3w +endef + define U-Boot/rock-3c-rk3566 $(U-Boot/rk3566/Default) NAME:=ROCK 3C @@ -277,6 +285,7 @@ UBOOT_TARGETS := \ rock-pi-e-rk3328 \ rock-pi-e-v3-rk3328 \ radxa-cm3-io-rk3566 \ + radxa-zero-3-rk3566 \ rock-3c-rk3566 \ bpi-r2-pro-rk3568 \ nanopi-r5c-rk3568 \ diff --git a/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch b/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch index bcc22bb510..4996271c59 100644 --- a/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch +++ b/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch @@ -1494,3 +1494,687 @@ + remote-endpoint = <&hdmi_in_vp0>; + }; +}; +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3.dtsi +@@ -0,0 +1,531 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "d"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led2>; ++ ++ led-green { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ vcc_1v8: regulator-1v8-vcc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8_p>; ++ }; ++ ++ vcca_1v8: regulator-1v8-vcca { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8_p>; ++ }; ++ ++ vcca1v8_image: regulator-1v8-vcca-image { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca1v8_image"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8_p>; ++ }; ++ ++ vcc_3v3: regulator-3v3-vcc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc_sys: regulator-5v0-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpio0 { ++ gpio-line-names = ++ /* GPIO0_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_D0 - D7 */ ++ "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "", ++ "", "", "", "", ""; ++}; ++ ++&gpio1 { ++ gpio-line-names = ++ /* GPIO1_A0 - A7 */ ++ "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "", ++ "", "pin-37 [GPIO1_A4]", "", ++ "", "", ++ /* GPIO1_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio2 { ++ gpio-line-names = ++ /* GPIO2_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO2_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO2_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO2_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = ++ /* GPIO3_A0 - A7 */ ++ "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]", ++ "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", ++ "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]", ++ /* GPIO3_B0 - B7 */ ++ "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]", ++ "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "", ++ "", "", ++ /* GPIO3_C0 - C7 */ ++ "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]", ++ "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "", ++ "", "", ++ /* GPIO3_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio4 { ++ gpio-line-names = ++ /* GPIO4_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO4_B0 - B7 */ ++ "", "", "pin-27 [GPIO4_B2]", ++ "pin-28 [GPIO4_B3]", "", "", "", "", ++ /* GPIO4_C0 - C7 */ ++ "", "", "pin-23 [GPIO4_C2]", ++ "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", ++ "pin-24 [GPIO4_C6]", "", ++ /* GPIO4_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_npu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda_0v9>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ rk817: pmic@20 { ++ compatible = "rockchip,rk817"; ++ reg = <0x20>; ++ #clock-cells = <1>; ++ clock-output-names = "rk817-clkout1", "rk817-clkout2"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc_sys>; ++ vcc9-supply = <&vcc5v_midu>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_gpu_npu: DCDC_REG2 { ++ regulator-name = "vdd_gpu_npu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sys: DCDC_REG4 { ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG1 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_1v8_p: LDO_REG7 { ++ regulator-name = "vcc_1v8_p"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG8 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc2v8_dvp: LDO_REG9 { ++ regulator-name = "vcc2v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc5v_midu: BOOST { ++ regulator-name = "vcc5v_midu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vbus: OTG_SWITCH { ++ regulator-name = "vbus"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu: regulator@40 { ++ compatible = "rockchip,rk8600"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ leds { ++ user_led2: user-led2 { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcca1v8_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3e.dts +@@ -0,0 +1,52 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3566-radxa-zero-3.dtsi" ++ ++/ { ++ model = "Radxa ZERO 3E"; ++ compatible = "radxa,zero-3e", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdmmc0; ++ }; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ status = "okay"; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1_rstn>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ gmac1 { ++ gmac1_rstn: gmac1-rstn { ++ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3w.dts +@@ -0,0 +1,92 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3566-radxa-zero-3.dtsi" ++ ++/ { ++ model = "Radxa ZERO 3W"; ++ compatible = "radxa,zero-3w", "rockchip,rk3566"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ mmc2 = &sdmmc1; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk817 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ post-power-on-delay-ms = <100>; ++ power-off-delay-us = <5000000>; ++ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ bluetooth { ++ bt_reg_on_h: bt-reg-on-h { ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_host_h: bt-wake-host-h { ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ host_wake_bt_h: host-wake-bt-h { ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_reg_on_h: wifi-reg-on-h { ++ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_wake_host_h: wifi-wake-host-h { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ mmc-hs200-1_8v; ++ no-sd; ++ no-sdio; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ no-mmc; ++ no-sd; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; ++ uart-has-rtscts; ++ status = "okay"; ++}; diff --git a/package/boot/uboot-rockchip/patches/003-dm-adc-Add-SPL_ADC-Kconfig-symbol-for-use-of-ADC-in-.patch b/package/boot/uboot-rockchip/patches/003-dm-adc-Add-SPL_ADC-Kconfig-symbol-for-use-of-ADC-in-.patch new file mode 100644 index 0000000000..c62c378980 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/003-dm-adc-Add-SPL_ADC-Kconfig-symbol-for-use-of-ADC-in-.patch @@ -0,0 +1,67 @@ +From 232af1e58a977f3857074d3aba3709c860bd8058 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 2 Aug 2024 22:12:22 +0000 +Subject: [PATCH] dm: adc: Add SPL_ADC Kconfig symbol for use of ADC in SPL + +What model of Radxa ZERO 3W/3E board can be identified using ADC at +runtime, add a Kconfig symbol to allow use of ADC in SPL. + +This will be used to identify board model in SPL to allow loading +correct FIT configuration and FDT for U-Boot proper at SPL phase. + +Signed-off-by: Jonas Karlman +Reviewed-by: Kever Yang +--- + drivers/Makefile | 2 +- + drivers/adc/Kconfig | 5 +++++ + drivers/adc/Makefile | 2 +- + 3 files changed, 7 insertions(+), 2 deletions(-) + +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0+ + ++obj-$(CONFIG_$(SPL_TPL_)ADC) += adc/ + obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/ + obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ + obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ +@@ -81,7 +82,6 @@ endif + + ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) + +-obj-y += adc/ + obj-y += ata/ + obj-$(CONFIG_DM_DEMO) += demo/ + obj-y += block/ +--- a/drivers/adc/Kconfig ++++ b/drivers/adc/Kconfig +@@ -1,5 +1,6 @@ + config ADC + bool "Enable ADC drivers using Driver Model" ++ depends on DM + help + This enables ADC API for drivers, which allows driving ADC features + by single and multi-channel methods for: +@@ -11,6 +12,10 @@ config ADC + - support supply's phandle with auto-enable + - supply polarity setting in fdt + ++config SPL_ADC ++ bool "Enable ADC drivers using Driver Model in SPL" ++ depends on SPL_DM ++ + config ADC_EXYNOS + bool "Enable Exynos 54xx ADC driver" + depends on ADC +--- a/drivers/adc/Makefile ++++ b/drivers/adc/Makefile +@@ -4,7 +4,7 @@ + # Przemyslaw Marczak + # + +-obj-$(CONFIG_ADC) += adc-uclass.o ++obj-$(CONFIG_$(SPL_TPL_)ADC) += adc-uclass.o + obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o + obj-$(CONFIG_ADC_SANDBOX) += sandbox.o + obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o diff --git a/package/boot/uboot-rockchip/patches/004-board-rockchip-Add-Radxa-ZERO-3W-3E.patch b/package/boot/uboot-rockchip/patches/004-board-rockchip-Add-Radxa-ZERO-3W-3E.patch new file mode 100644 index 0000000000..cbd6995874 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/004-board-rockchip-Add-Radxa-ZERO-3W-3E.patch @@ -0,0 +1,295 @@ +From 5d199ad9a6bb43dbf43efe45ec37002c4ae305a0 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 2 Aug 2024 22:12:23 +0000 +Subject: [PATCH] board: rockchip: Add Radxa ZERO 3W/3E + +The Radxa ZERO 3W/3E is an ultra-small, high-performance single board +computer based on the Rockchip RK3566, with a compact form factor and +rich interfaces. + +Implement rk_board_late_init() to set correct fdtfile env var and +board_fit_config_name_match() to load correct FIT config based on what +board is detected at runtime so a single board target can be used for +both board models. + +Features tested on a ZERO 3W 8GB v1.11: +- SD-card boot +- eMMC boot +- USB gadget +- USB host + +Features tested on a ZERO 3E 4GB v1.2: +- SD-card boot +- Ethernet +- USB gadget +- USB host + +Signed-off-by: Jonas Karlman +Tested-by: FUKAUMI Naoki +Reviewed-by: Kever Yang +--- + arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi | 15 ++++ + arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi | 15 ++++ + arch/arm/mach-rockchip/rk3568/Kconfig | 6 ++ + board/radxa/zero3-rk3566/Kconfig | 12 +++ + board/radxa/zero3-rk3566/MAINTAINERS | 6 ++ + board/radxa/zero3-rk3566/Makefile | 3 + + board/radxa/zero3-rk3566/zero3-rk3566.c | 59 +++++++++++++ + configs/radxa-zero-3-rk3566_defconfig | 85 +++++++++++++++++++ + doc/board/rockchip/rockchip.rst | 1 + + 9 files changed, 202 insertions(+) + create mode 100644 arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi + create mode 100644 board/radxa/zero3-rk3566/Kconfig + create mode 100644 board/radxa/zero3-rk3566/MAINTAINERS + create mode 100644 board/radxa/zero3-rk3566/Makefile + create mode 100644 board/radxa/zero3-rk3566/zero3-rk3566.c + create mode 100644 configs/radxa-zero-3-rk3566_defconfig + +--- /dev/null ++++ b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi +@@ -0,0 +1,15 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x-u-boot.dtsi" ++ ++&saradc { ++ bootph-pre-ram; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "otg"; ++}; ++ ++&vcca_1v8 { ++ bootph-pre-ram; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi +@@ -0,0 +1,15 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x-u-boot.dtsi" ++ ++&saradc { ++ bootph-pre-ram; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "otg"; ++}; ++ ++&vcca_1v8 { ++ bootph-pre-ram; ++}; +--- a/arch/arm/mach-rockchip/rk3568/Kconfig ++++ b/arch/arm/mach-rockchip/rk3568/Kconfig +@@ -32,6 +32,11 @@ config TARGET_QUARTZ64_RK3566 + help + Pine64 Quartz64 single board computer with a RK3566 SoC. + ++config TARGET_RADXA_ZERO_3_RK3566 ++ bool "Radxa ZERO 3W/3E" ++ help ++ Radxa ZERO 3W/3E single board computers with a RK3566 SoC. ++ + endchoice + + config ROCKCHIP_BOOT_MODE_REG +@@ -54,5 +59,6 @@ source "board/anbernic/rgxx3_rk3566/Kcon + source "board/hardkernel/odroid_m1/Kconfig" + source "board/pine64/quartz64_rk3566/Kconfig" + source "board/powkiddy/x55/Kconfig" ++source "board/radxa/zero3-rk3566/Kconfig" + + endif +--- /dev/null ++++ b/board/radxa/zero3-rk3566/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_RADXA_ZERO_3_RK3566 ++ ++config SYS_BOARD ++ default "zero3-rk3566" ++ ++config SYS_VENDOR ++ default "radxa" ++ ++config SYS_CONFIG_NAME ++ default "evb_rk3568" ++ ++endif +--- /dev/null ++++ b/board/radxa/zero3-rk3566/MAINTAINERS +@@ -0,0 +1,6 @@ ++RADXA-ZERO-3-RK3566 ++M: Jonas Karlman ++S: Maintained ++F: board/radxa/zero3-rk3566 ++F: configs/radxa-zero-3-rk3566_defconfig ++F: arch/arm/dts/rk3566-radxa-zero-3* +--- /dev/null ++++ b/board/radxa/zero3-rk3566/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y += zero3-rk3566.o +--- /dev/null ++++ b/board/radxa/zero3-rk3566/zero3-rk3566.c +@@ -0,0 +1,59 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++#include ++#include ++ ++#define HW_ID_CHANNEL 1 ++ ++struct board_model { ++ unsigned int low; ++ unsigned int high; ++ const char *fdtfile; ++}; ++ ++static const struct board_model board_models[] = { ++ { 230, 270, "rockchip/rk3566-radxa-zero-3w.dtb" }, ++ { 400, 450, "rockchip/rk3566-radxa-zero-3e.dtb" }, ++}; ++ ++static const struct board_model *get_board_model(void) ++{ ++ unsigned int val; ++ int i, ret; ++ ++ ret = adc_channel_single_shot("saradc@fe720000", HW_ID_CHANNEL, &val); ++ if (ret) ++ return NULL; ++ ++ for (i = 0; i < ARRAY_SIZE(board_models); i++) { ++ unsigned int min = board_models[i].low; ++ unsigned int max = board_models[i].high; ++ ++ if (min <= val && val <= max) ++ return &board_models[i]; ++ } ++ ++ return NULL; ++} ++ ++int rk_board_late_init(void) ++{ ++ const struct board_model *model = get_board_model(); ++ ++ if (model) ++ env_set("fdtfile", model->fdtfile); ++ ++ return 0; ++} ++ ++int board_fit_config_name_match(const char *name) ++{ ++ const struct board_model *model = get_board_model(); ++ ++ if (model && !strcmp(name, model->fdtfile)) ++ return 0; ++ ++ return -EINVAL; ++} +--- /dev/null ++++ b/configs/radxa-zero-3-rk3566_defconfig +@@ -0,0 +1,85 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SPL_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-radxa-zero-3w" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_SERIAL=y ++CONFIG_TARGET_RADXA_ZERO_3_RK3566=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-zero-3w.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_POWER=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_ROCKUSB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_LIST="rockchip/rk3566-radxa-zero-3w rockchip/rk3566-radxa-zero-3e" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_ADC=y ++CONFIG_SPL_CLK=y ++# CONFIG_USB_FUNCTION_FASTBOOT is not set ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_DM_PMIC_FAN53555=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_ERRNO_STR=y +--- a/doc/board/rockchip/rockchip.rst ++++ b/doc/board/rockchip/rockchip.rst +@@ -107,6 +107,7 @@ List of mainline supported Rockchip boar + - Powkiddy X55 (powkiddy-x55-rk3566) + - Radxa CM3 IO Board (radxa-cm3-io-rk3566) + - Radxa ROCK 3C (rock-3c-rk3566) ++ - Radxa ZERO 3W/3E (radxa-zero-3-rk3566) + + * rk3568 + - Rockchip Evb-RK3568 (evb-rk3568) diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 92e53fab3b..6924ceaa0a 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -201,6 +201,26 @@ define Device/radxa_rock-pi-s endef TARGET_DEVICES += radxa_rock-pi-s +define Device/radxa_zero-3e + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ZERO 3E + SOC := rk3566 + DEVICE_DTS := rockchip/rk3566-radxa-zero-3e + UBOOT_DEVICE_NAME := radxa-zero-3-rk3566 + DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis +endef +TARGET_DEVICES += radxa_zero-3e + +define Device/radxa_zero-3w + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ZERO 3W + SOC := rk3566 + DEVICE_DTS := rockchip/rk3566-radxa-zero-3w + UBOOT_DEVICE_NAME := radxa-zero-3-rk3566 + DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis +endef +TARGET_DEVICES += radxa_zero-3w + define Device/sinovoip_bpi-r2-pro DEVICE_VENDOR := Sinovoip DEVICE_MODEL := Bananapi-R2 Pro diff --git a/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch b/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch new file mode 100644 index 0000000000..746078cf9e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/011-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch @@ -0,0 +1,657 @@ +From 1a5c8d307c83c808a32686ed51afb4bac2092d39 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 21 May 2024 20:28:05 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add Radxa ZERO 3W/3E + +The Radxa ZERO 3W/3E is an ultra-small, high-performance single board +computer based on the Rockchip RK3566, with a compact form factor and +rich interfaces. + +The ZERO 3W and ZERO 3E are basically the same size and model, but +differ only in storage and network interfaces. + +- eMMC (3W) +- SD-card (both) +- Ethernet (3E) +- WiFi/BT (3W) + +Add initial support for eMMC, SD-card, Ethernet, HDMI and USB. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521202810.1225636-3-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 2 + + .../dts/rockchip/rk3566-radxa-zero-3.dtsi | 463 ++++++++++++++++++ + .../dts/rockchip/rk3566-radxa-zero-3e.dts | 51 ++ + .../dts/rockchip/rk3566-radxa-zero-3w.dts | 91 ++++ + 4 files changed, 607 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -80,6 +80,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3e.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3w.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi +@@ -0,0 +1,463 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdmmc0; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "d"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led2>; ++ ++ led-green { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ vcc_1v8: regulator-1v8-vcc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8_p>; ++ }; ++ ++ vcca_1v8: regulator-1v8-vcca { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8_p>; ++ }; ++ ++ vcca1v8_image: regulator-1v8-vcca-image { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca1v8_image"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8_p>; ++ }; ++ ++ vcc_3v3: regulator-3v3-vcc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc_sys: regulator-5v0-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_npu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda_0v9>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ rk817: pmic@20 { ++ compatible = "rockchip,rk817"; ++ reg = <0x20>; ++ #clock-cells = <1>; ++ clock-output-names = "rk817-clkout1", "rk817-clkout2"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc_sys>; ++ vcc9-supply = <&vcc5v_midu>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_gpu_npu: DCDC_REG2 { ++ regulator-name = "vdd_gpu_npu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sys: DCDC_REG4 { ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG1 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_1v8_p: LDO_REG7 { ++ regulator-name = "vcc_1v8_p"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG8 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc2v8_dvp: LDO_REG9 { ++ regulator-name = "vcc2v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc5v_midu: BOOST { ++ regulator-name = "vcc5v_midu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vbus: OTG_SWITCH { ++ regulator-name = "vbus"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu: regulator@40 { ++ compatible = "rockchip,rk8600"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ leds { ++ user_led2: user-led2 { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcca1v8_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3566-radxa-zero-3.dtsi" ++ ++/ { ++ model = "Radxa ZERO 3E"; ++ compatible = "radxa,zero-3e", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ }; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ status = "okay"; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1_rstn>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ gmac1 { ++ gmac1_rstn: gmac1-rstn { ++ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts +@@ -0,0 +1,91 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3566-radxa-zero-3.dtsi" ++ ++/ { ++ model = "Radxa ZERO 3W"; ++ compatible = "radxa,zero-3w", "rockchip,rk3566"; ++ ++ aliases { ++ mmc1 = &sdhci; ++ mmc2 = &sdmmc1; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk817 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ post-power-on-delay-ms = <100>; ++ power-off-delay-us = <5000000>; ++ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ bluetooth { ++ bt_reg_on_h: bt-reg-on-h { ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_host_h: bt-wake-host-h { ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ host_wake_bt_h: host-wake-bt-h { ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_reg_on_h: wifi-reg-on-h { ++ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_wake_host_h: wifi-wake-host-h { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ mmc-hs200-1_8v; ++ no-sd; ++ no-sdio; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ no-mmc; ++ no-sd; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; ++ uart-has-rtscts; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/012-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch b/target/linux/rockchip/patches-6.6/012-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch new file mode 100644 index 0000000000..b96e8e1774 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/012-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch @@ -0,0 +1,64 @@ +From 060c1950037e4c54ca4d8186a8f46269e35db901 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Fri, 21 Jun 2024 07:44:35 +0900 +Subject: [PATCH] arm64: dts: rockchip: fix mmc aliases for Radxa ZERO 3E/3W + +align with other Radxa products. + +- mmc0 is eMMC +- mmc1 is microSD + +for ZERO 3E, there is no eMMC, but aliases should start at 0, so mmc0 +is microSD as exception. + +Fixes: 1a5c8d307c83 ("arm64: dts: rockchip: Add Radxa ZERO 3W/3E") +Signed-off-by: FUKAUMI Naoki + +Changes in v3: +- fix syntax error in rk3566-radxa-zero-3e.dts +Changes in v2: +- microSD is mmc0 instead of mmc1 for ZERO 3E + +Link: https://lore.kernel.org/r/20240620224435.2752-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 4 ---- + arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts | 1 + + arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts | 3 ++- + 3 files changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi +@@ -6,10 +6,6 @@ + #include "rk3566.dtsi" + + / { +- aliases { +- mmc0 = &sdmmc0; +- }; +- + chosen { + stdout-path = "serial2:1500000n8"; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts +@@ -10,6 +10,7 @@ + + aliases { + ethernet0 = &gmac1; ++ mmc0 = &sdmmc0; + }; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts +@@ -9,7 +9,8 @@ + compatible = "radxa,zero-3w", "rockchip,rk3566"; + + aliases { +- mmc1 = &sdhci; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + diff --git a/target/linux/rockchip/patches-6.6/013-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch b/target/linux/rockchip/patches-6.6/013-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch new file mode 100644 index 0000000000..4c5107ab35 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/013-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch @@ -0,0 +1,101 @@ +From f7c742cbe664ebdedc075945e75443683d1175f7 Mon Sep 17 00:00:00 2001 +From: Trevor Woerner +Date: Wed, 19 Jun 2024 21:32:49 -0400 +Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to radxa-zero-3 + +Add names to the pins of the general-purpose expansion header as given +in the Radxa documentation[1] following the conventions in the kernel[2] +to make it easier for users to correlate pins with functions when using +utilities such as 'gpioinfo'. + +[1] https://docs.radxa.com/en/zero/zero3/hardware-design/hardware-interface +[2] https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/gpio.txt + +Signed-off-by: Trevor Woerner +Link: https://lore.kernel.org/r/20240620013301.33653-1-twoerner@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../dts/rockchip/rk3566-radxa-zero-3.dtsi | 72 +++++++++++++++++++ + 1 file changed, 72 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi +@@ -105,6 +105,78 @@ + cpu-supply = <&vdd_cpu>; + }; + ++&gpio0 { ++ gpio-line-names = ++ /* GPIO0_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO0_D0 - D7 */ ++ "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "", ++ "", "", "", "", ""; ++}; ++ ++&gpio1 { ++ gpio-line-names = ++ /* GPIO1_A0 - A7 */ ++ "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "", ++ "", "pin-37 [GPIO1_A4]", "", ++ "", "", ++ /* GPIO1_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO1_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio2 { ++ gpio-line-names = ++ /* GPIO2_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO2_B0 - B7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO2_C0 - C7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO2_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = ++ /* GPIO3_A0 - A7 */ ++ "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]", ++ "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", ++ "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]", ++ /* GPIO3_B0 - B7 */ ++ "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]", ++ "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "", ++ "", "", ++ /* GPIO3_C0 - C7 */ ++ "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]", ++ "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "", ++ "", "", ++ /* GPIO3_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ ++&gpio4 { ++ gpio-line-names = ++ /* GPIO4_A0 - A7 */ ++ "", "", "", "", "", "", "", "", ++ /* GPIO4_B0 - B7 */ ++ "", "", "pin-27 [GPIO4_B2]", ++ "pin-28 [GPIO4_B3]", "", "", "", "", ++ /* GPIO4_C0 - C7 */ ++ "", "", "pin-23 [GPIO4_C2]", ++ "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", ++ "pin-24 [GPIO4_C6]", "", ++ /* GPIO4_D0 - D7 */ ++ "", "", "", "", "", "", "", ""; ++}; ++ + &gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; diff --git a/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch index 0da3272ed7..0f7cd388fe 100644 --- a/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch +++ b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch @@ -17,7 +17,7 @@ Signed-off-by: Heiko Stuebner --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -105,4 +105,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na +@@ -107,4 +107,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb diff --git a/target/linux/rockchip/patches-6.6/123-radxa-zero-3-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.6/123-radxa-zero-3-add-led-aliases-and-stop-heartbeat.patch new file mode 100644 index 0000000000..81a86e5edb --- /dev/null +++ b/target/linux/rockchip/patches-6.6/123-radxa-zero-3-add-led-aliases-and-stop-heartbeat.patch @@ -0,0 +1,30 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi +@@ -6,6 +6,13 @@ + #include "rk3566.dtsi" + + / { ++ aliases { ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; ++ }; ++ + chosen { + stdout-path = "serial2:1500000n8"; + }; +@@ -26,12 +33,11 @@ + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + +- led-green { ++ led_green: led-green { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + From 61878706f9ca334ffa57be3cc28b7bf9aea6eaa6 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Thu, 15 Aug 2024 06:49:13 +0900 Subject: [PATCH 07/23] rockchip: add support for Radxa ROCK 3B Radxa ROCK 3B is a Pico-ITX form factor SBC[1] using the Rockchip RK3568(J). Hardware -------- - Rockchip RK3568(J) SoC - Quad A55 CPU - Mali-G52 GPU - 1 TOPS @ INT8 NPU - 2GB/4GB/8GB LPDDR4 RAM - eMMC connector - Micro SD Card slot - NVMe SSD through the M.2 M Key (2-lane PCIe 3.0) - SPI Flash for bootloader - 2x Gigabit ethernet port (one supports PoE with add-on PoE HAT) - 1x M.2 E Key socket with SDIO, UART and USB interfaces - 1x M.2 B Key socket with PCIe, SATA, and USB interfaces - 1x SIM card socket - 1x USB 3.0 Type-A HOST port - 1x USB 3.0 Type-A OTG port - 2x USB 2.0 Type-A HOST ports - 40 Pin GPIO header [1] https://radxa.com/products/rock3/3b Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: FUKAUMI Naoki Link: https://github.com/openwrt/openwrt/pull/16185 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-rockchip/Makefile | 8 + .../000-backport-upstream-dts-sync.patch | 784 +++++++++++++++++ ...005-board-rockchip-Add-Radxa-ROCK-3B.patch | 179 ++++ .../armv8/base-files/etc/board.d/02_network | 3 +- target/linux/rockchip/image/armv8.mk | 8 + ...arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch | 815 ++++++++++++++++++ ...-rockchip-Add-support-for-NanoPi-R6S.patch | 2 +- ...b-add-led-aliases-and-stop-heartbeat.patch | 27 + 8 files changed, 1824 insertions(+), 2 deletions(-) create mode 100644 package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-3B.patch create mode 100644 target/linux/rockchip/patches-6.6/014-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch create mode 100644 target/linux/rockchip/patches-6.6/124-rock-3b-add-led-aliases-and-stop-heartbeat.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index cc834fb3ed..626b058ea5 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -228,6 +228,13 @@ define U-Boot/rock-3a-rk3568 radxa_rock-3a endef +define U-Boot/rock-3b-rk3568 + $(U-Boot/rk3568/Default) + NAME:=ROCK 3B + BUILD_DEVICES:= \ + radxa_rock-3b +endef + # RK3588 boards @@ -292,6 +299,7 @@ UBOOT_TARGETS := \ nanopi-r5s-rk3568 \ radxa-e25-rk3568 \ rock-3a-rk3568 \ + rock-3b-rk3568 \ rock5b-rk3588 \ nanopc-t6-rk3588 \ nanopi-r6s-rk3588s \ diff --git a/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch b/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch index 4996271c59..bd639a683d 100644 --- a/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch +++ b/package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch @@ -2178,3 +2178,787 @@ + uart-has-rtscts; + status = "okay"; +}; +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3568-rock-3b.dts +@@ -0,0 +1,781 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ model = "Radxa ROCK 3B"; ++ compatible = "radxa,rock-3b", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ mmc2 = &sdmmc2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm3_ir>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led>; ++ ++ led-0 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ /* pi6c pcie clock generator */ ++ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pwren_h>; ++ regulator-name = "vcc3v3_pi6c_03"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <10000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_sys: regulator-3v3-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_sys2: regulator-3v3-vcc-sys2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys2"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-5v0-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc5v0_usb_host: regulator-5v0-vcc-usb-host { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_host_pwren_h>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_otg_pwren_h>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ post-power-on-delay-ms = <100>; ++ power-off-delay-us = <5000000>; ++ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus ++ &gmac0_clkinout>; ++ status = "okay"; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ #clock-cells = <1>; ++ clocks = <&cru I2S1_MCLKOUT_TX>; ++ clock-names = "mclk"; ++ clock-output-names = "rk809-clkout1", "rk809-clkout2"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; ++ #sound-dai-cells = <0>; ++ system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtcic_int_l>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20m1_pins>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_sys2>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie30x2m1_pins>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bluetooth { ++ bt_reg_on_h: bt-reg-on-h { ++ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_host_h: bt-wake-host-h { ++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ host_wake_bt_h: host-wake-bt-h { ++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ ir-receiver { ++ pwm3_ir: pwm3-ir { ++ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led: led { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pwren_h: pcie-pwren-h { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie20 { ++ pcie20m1_pins: pcie20m1-pins { ++ rockchip,pins = ++ <2 RK_PD0 4 &pcfg_pull_none>, ++ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x2 { ++ pcie30x2m1_pins: pcie30x2m1-pins { ++ rockchip,pins = ++ <2 RK_PD4 4 &pcfg_pull_none>, ++ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PD5 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rtc { ++ rtcic_int_l: rtcic-int-l { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ usb_host_pwren_h: usb-host-pwren-h { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usb_otg_pwren_h: usb-otg-pwren-h { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_reg_on_h: wifi-reg-on-h { ++ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_wake_host_h: wifi-wake-host-h { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sys2>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "disabled"; ++}; ++ ++&sfc { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; ++ uart-has-rtscts; ++ status = "disabled"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-3B.patch b/package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-3B.patch new file mode 100644 index 0000000000..0fe8bfd52d --- /dev/null +++ b/package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-3B.patch @@ -0,0 +1,179 @@ +From e20d57ae7e0c28f2d770a7d18c1501d332e8766a Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 31 Jul 2024 07:28:54 +0000 +Subject: [PATCH] board: rockchip: Add Radxa ROCK 3B + +The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form +factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community +version based on the RK3568 SoC and an industrial version based on the +RK3568J SoC. + +Features tested on ROCK 3B 8GB v1.51 (both variants): +- SD-card boot +- eMMC boot +- SPI Flash boot +- Ethernet +- PCIe/NVMe +- USB gadget +- USB host + +Signed-off-by: Jonas Karlman +Tested-by: FUKAUMI Naoki +Reviewed-by: Kever Yang +--- + arch/arm/dts/rk3568-rock-3b-u-boot.dtsi | 15 ++++ + board/rockchip/evb_rk3568/MAINTAINERS | 6 ++ + configs/rock-3b-rk3568_defconfig | 100 ++++++++++++++++++++++++ + doc/board/rockchip/rockchip.rst | 3 +- + 4 files changed, 123 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/rk3568-rock-3b-u-boot.dtsi + create mode 100644 configs/rock-3b-rk3568_defconfig + +--- /dev/null ++++ b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi +@@ -0,0 +1,15 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x-u-boot.dtsi" ++ ++&sdhci { ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++}; ++ ++&sfc { ++ flash@0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++ }; ++}; +--- a/board/rockchip/evb_rk3568/MAINTAINERS ++++ b/board/rockchip/evb_rk3568/MAINTAINERS +@@ -70,6 +70,12 @@ F: configs/rock-3a-rk3568_defconfig + F: arch/arm/dts/rk3568-rock-3a.dts + F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi + ++ROCK-3B ++M: Jonas Karlman ++S: Maintained ++F: configs/rock-3b-rk3568_defconfig ++F: arch/arm/dts/rk3568-rock-3b* ++ + ROCK-3C + M: Jonas Karlman + M: Maxim Moskalets +--- /dev/null ++++ b/configs/rock-3b-rk3568_defconfig +@@ -0,0 +1,100 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=24000000 ++CONFIG_SF_DEFAULT_MODE=0x2000 ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-rock-3b" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SPL_SERIAL=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3b.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_ROCKUSB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SPL_CLK=y ++# CONFIG_USB_FUNCTION_FASTBOOT is not set ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SF_DEFAULT_BUS=4 ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_DM_PMIC_FAN53555=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_SPL_RAM=y ++CONFIG_SCSI=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_ERRNO_STR=y +--- a/doc/board/rockchip/rockchip.rst ++++ b/doc/board/rockchip/rockchip.rst +@@ -118,7 +118,8 @@ List of mainline supported Rockchip boar + - Generic RK3566/RK3568 (generic-rk3568) + - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - Radxa E25 Carrier Board (radxa-e25-rk3568) +- - Radxa ROCK 3 Model A (rock-3a-rk3568) ++ - Radxa ROCK 3A (rock-3a-rk3568) ++ - Radxa ROCK 3B (rock-3b-rk3568) + + * rk3588 + - Rockchip EVB (evb-rk3588) diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 0e3bb8deaf..078ecfaabe 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -9,7 +9,8 @@ rockchip_setup_interfaces() case "$board" in friendlyarm,nanopc-t6|\ friendlyarm,nanopi-r5c|\ - radxa,e25) + radxa,e25|\ + radxa,rock-3b) ucidef_set_interfaces_lan_wan 'eth0' 'eth1' ;; friendlyarm,nanopi-r2c|\ diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 6924ceaa0a..99dde6aef1 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -140,6 +140,14 @@ define Device/radxa_rock-3a endef TARGET_DEVICES += radxa_rock-3a +define Device/radxa_rock-3b + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ROCK 3B + SOC := rk3568 + DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis +endef +TARGET_DEVICES += radxa_rock-3b + define Device/radxa_rock-3c DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK 3C diff --git a/target/linux/rockchip/patches-6.6/014-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch b/target/linux/rockchip/patches-6.6/014-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch new file mode 100644 index 0000000000..e93a055c3e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/014-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch @@ -0,0 +1,815 @@ +From 846ef7748fa9124c8eea76e2d5e833fa69b3ef7c Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Thu, 27 Jun 2024 21:17:31 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3B + +The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form +factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community +version based on the RK3568 SoC and an industrial version based on the +RK3568J SoC. + +Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB. + +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240627211737.1985549-3-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3568-rock-3b.dts | 781 ++++++++++++++++++ + 2 files changed, 782 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +@@ -0,0 +1,781 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ model = "Radxa ROCK 3B"; ++ compatible = "radxa,rock-3b", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ mmc2 = &sdmmc2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm3_ir>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led>; ++ ++ led-0 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ /* pi6c pcie clock generator */ ++ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pwren_h>; ++ regulator-name = "vcc3v3_pi6c_03"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <10000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_sys: regulator-3v3-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_sys2: regulator-3v3-vcc-sys2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys2"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-5v0-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc5v0_usb_host: regulator-5v0-vcc-usb-host { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_host_pwren_h>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_otg_pwren_h>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ post-power-on-delay-ms = <100>; ++ power-off-delay-us = <5000000>; ++ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus ++ &gmac0_clkinout>; ++ status = "okay"; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; ++ clock_in_out = "input"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-id"; ++ phy-supply = <&vcc_3v3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ #clock-cells = <1>; ++ clocks = <&cru I2S1_MCLKOUT_TX>; ++ clock-names = "mclk"; ++ clock-output-names = "rk809-clkout1", "rk809-clkout2"; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; ++ #sound-dai-cells = <0>; ++ system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtcic_int_l>; ++ wakeup-source; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20m1_pins>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_sys2>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie30x2m1_pins>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bluetooth { ++ bt_reg_on_h: bt-reg-on-h { ++ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_host_h: bt-wake-host-h { ++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ host_wake_bt_h: host-wake-bt-h { ++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ ir-receiver { ++ pwm3_ir: pwm3-ir { ++ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led: led { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pwren_h: pcie-pwren-h { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie20 { ++ pcie20m1_pins: pcie20m1-pins { ++ rockchip,pins = ++ <2 RK_PD0 4 &pcfg_pull_none>, ++ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x2 { ++ pcie30x2m1_pins: pcie30x2m1-pins { ++ rockchip,pins = ++ <2 RK_PD4 4 &pcfg_pull_none>, ++ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 RK_PD5 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rtc { ++ rtcic_int_l: rtcic-int-l { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ usb_host_pwren_h: usb-host-pwren-h { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usb_otg_pwren_h: usb-otg-pwren-h { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_reg_on_h: wifi-reg-on-h { ++ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_wake_host_h: wifi-wake-host-h { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <200000000>; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sys2>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "disabled"; ++}; ++ ++&sfc { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; ++ uart-has-rtscts; ++ status = "disabled"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch index 0f7cd388fe..d0243023fc 100644 --- a/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch +++ b/target/linux/rockchip/patches-6.6/053-v6.9-arm64-dts-rockchip-Add-support-for-NanoPi-R6S.patch @@ -17,7 +17,7 @@ Signed-off-by: Heiko Stuebner --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -107,4 +107,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na +@@ -108,4 +108,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb diff --git a/target/linux/rockchip/patches-6.6/124-rock-3b-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.6/124-rock-3b-add-led-aliases-and-stop-heartbeat.patch new file mode 100644 index 0000000000..420f3ccc4c --- /dev/null +++ b/target/linux/rockchip/patches-6.6/124-rock-3b-add-led-aliases-and-stop-heartbeat.patch @@ -0,0 +1,27 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +@@ -18,6 +18,10 @@ + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc2; ++ led-boot = &led_green; ++ led-failsafe = &led_green; ++ led-running = &led_green; ++ led-upgrade = &led_green; + }; + + chosen { +@@ -47,12 +51,11 @@ + pinctrl-names = "default"; + pinctrl-0 = <&led>; + +- led-0 { ++ led_green: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + From ad3a7fc129590ce67f4a9057748c83df7e6a5ed2 Mon Sep 17 00:00:00 2001 From: Til Kaiser Date: Sun, 28 Apr 2024 14:25:23 +0200 Subject: [PATCH 08/23] kernel: modules: add x86 dependency for leds-mlxcpld This commit adds the missing x86 dependency for the Mellanox mlxcpld LED driver. Signed-off-by: Til Kaiser Link: https://github.com/openwrt/openwrt/pull/15362 Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/leds.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/leds.mk b/package/kernel/linux/modules/leds.mk index 60465a8ad5..8b24cb0ef8 100644 --- a/package/kernel/linux/modules/leds.mk +++ b/package/kernel/linux/modules/leds.mk @@ -150,8 +150,9 @@ $(eval $(call KernelPackage,leds-apu)) define KernelPackage/leds-mlxcpld SUBMENU:=$(LEDS_MENU) TITLE:=LED support for the Mellanox boards - FILES:=$(LINUX_DIR)/drivers/leds/leds-mlxcpld.ko + DEPENDS:=@TARGET_x86 KCONFIG:=CONFIG_LEDS_MLXCPLD + FILES:=$(LINUX_DIR)/drivers/leds/leds-mlxcpld.ko AUTOLOAD:=$(call AutoProbe,leds-mlxcpld) endef From ababc2d0a7a4c6b07f096f3e9f1d5546e4a64a26 Mon Sep 17 00:00:00 2001 From: Til Kaiser Date: Sun, 28 Apr 2024 14:24:11 +0200 Subject: [PATCH 09/23] linux-firmware: add firmware for all Mellanox Spectrum Switches This commit adds the currently missing Mellanox Spectrum-2, Spectrum-3, and Spectrum-4 firmware files. Signed-off-by: Til Kaiser Link: https://github.com/openwrt/openwrt/pull/15362 Signed-off-by: Hauke Mehrtens --- package/firmware/linux-firmware/mellanox.mk | 30 +++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/package/firmware/linux-firmware/mellanox.mk b/package/firmware/linux-firmware/mellanox.mk index 039c7deb10..949085f2a8 100644 --- a/package/firmware/linux-firmware/mellanox.mk +++ b/package/firmware/linux-firmware/mellanox.mk @@ -7,3 +7,33 @@ define Package/mlxsw_spectrum-firmware/install endef $(eval $(call BuildPackage,mlxsw_spectrum-firmware)) + +Package/mlxsw_spectrum2-firmware = $(call Package/firmware-default,Mellanox Spectrum-2 firmware) +define Package/mlxsw_spectrum2-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/mellanox + $(CP) \ + $(PKG_BUILD_DIR)/mellanox/mlxsw_spectrum2-*.mfa2 \ + $(1)/lib/firmware/mellanox +endef + +$(eval $(call BuildPackage,mlxsw_spectrum2-firmware)) + +Package/mlxsw_spectrum3-firmware = $(call Package/firmware-default,Mellanox Spectrum-3 firmware) +define Package/mlxsw_spectrum3-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/mellanox + $(CP) \ + $(PKG_BUILD_DIR)/mellanox/mlxsw_spectrum3-*.mfa2 \ + $(1)/lib/firmware/mellanox +endef + +$(eval $(call BuildPackage,mlxsw_spectrum3-firmware)) + +Package/mlxsw_spectrum4-firmware = $(call Package/firmware-default,Mellanox Spectrum-4 firmware) +define Package/mlxsw_spectrum4-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/mellanox + $(CP) \ + $(PKG_BUILD_DIR)/mellanox/mlxsw_spectrum4-*.mfa2 \ + $(1)/lib/firmware/mellanox +endef + +$(eval $(call BuildPackage,mlxsw_spectrum4-firmware)) From 55bbd5f5c01955d1da885824f0b984e242cdbc4c Mon Sep 17 00:00:00 2001 From: Til Kaiser Date: Sat, 3 Aug 2024 10:29:25 +0200 Subject: [PATCH 10/23] generic: 6.6: add missing DCB symbols Disables Data Center Bridging support for some network drivers by default to avoid compilation errors when CONFIG_DCB is enabled. Signed-off-by: Til Kaiser Link: https://github.com/openwrt/openwrt/pull/15362 Signed-off-by: Hauke Mehrtens --- target/linux/generic/config-6.6 | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/linux/generic/config-6.6 b/target/linux/generic/config-6.6 index e0e1bd5280..733b8b4dbb 100644 --- a/target/linux/generic/config-6.6 +++ b/target/linux/generic/config-6.6 @@ -179,6 +179,7 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_AMD_MEM_ENCRYPT is not set # CONFIG_AMD_PHY is not set # CONFIG_AMD_XGBE is not set +# CONFIG_AMD_XGBE_DCB is not set # CONFIG_AMD_XGBE_HAVE_ECC is not set # CONFIG_AMIGA_PARTITION is not set # CONFIG_AMILO_RFKILL is not set @@ -2526,6 +2527,7 @@ CONFIG_HZ_100=y # CONFIG_I3C is not set # CONFIG_I40E is not set # CONFIG_I40EVF is not set +# CONFIG_I40E_DCB is not set # CONFIG_I6300ESB_WDT is not set # CONFIG_I82092 is not set # CONFIG_I82365 is not set @@ -2874,6 +2876,7 @@ CONFIG_ISDN=y # CONFIG_IWLWIFI is not set # CONFIG_IXGBE is not set # CONFIG_IXGBEVF is not set +# CONFIG_IXGBE_DCB is not set # CONFIG_JAILHOUSE_GUEST is not set # CONFIG_JBD2_DEBUG is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set @@ -4803,6 +4806,7 @@ CONFIG_PWRSEQ_SIMPLE=y # CONFIG_QFMT_V1 is not set # CONFIG_QLA3XXX is not set # CONFIG_QLCNIC is not set +# CONFIG_QLCNIC_DCB is not set # CONFIG_QLGE is not set # CONFIG_QNX4FS_FS is not set # CONFIG_QNX6FS_FS is not set From f1812d5901e5450034fba24e7c8234841799c747 Mon Sep 17 00:00:00 2001 From: Til Kaiser Date: Sat, 3 Aug 2024 10:48:34 +0200 Subject: [PATCH 11/23] kernel: netdevices: adjust mlxsw network drivers * Adds the x86_64 dependency for mlxsw_core * Removes the redundant mlxsw_core dependency from mlxsw-minimal and mlxsw-spectrum * Removes the DCB configuration symbols because they were moved into the generic configuration Signed-off-by: Til Kaiser Link: https://github.com/openwrt/openwrt/pull/15362 Signed-off-by: Hauke Mehrtens --- package/kernel/linux/modules/netdevices.mk | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk index c1188351dc..312f310485 100644 --- a/package/kernel/linux/modules/netdevices.mk +++ b/package/kernel/linux/modules/netdevices.mk @@ -1441,7 +1441,7 @@ $(eval $(call KernelPackage,mlxfw)) define KernelPackage/mlxsw-core SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Mellanox Technologies Switch ASICs support - DEPENDS:=+kmod-mlxfw +kmod-hwmon-core + DEPENDS:=@TARGET_x86_64 +kmod-mlxfw +kmod-hwmon-core FILES:=$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlxsw/mlxsw_core.ko KCONFIG:= \ CONFIG_MLXSW_CORE \ @@ -1476,7 +1476,7 @@ $(eval $(call KernelPackage,mlxsw-i2c)) define KernelPackage/mlxsw-minimal SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Mellanox Technologies minimal I2C support - DEPENDS:=+kmod-mlxsw-core +kmod-mlxsw-i2c + DEPENDS:=+kmod-mlxsw-i2c FILES:=$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlxsw/mlxsw_minimal.ko KCONFIG:=CONFIG_MLXSW_MINIMAL AUTOLOAD:=$(call AutoProbe,mlxsw_minimal) @@ -1510,20 +1510,14 @@ define KernelPackage/mlxsw-spectrum SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Mellanox Technologies Spectrum family support DEPENDS:= \ - +kmod-mlxsw-core +kmod-mlxsw-pci +kmod-lib-objagg +kmod-lib-parman \ + +kmod-mlxsw-pci +kmod-lib-objagg +kmod-lib-parman \ +kmod-ip6-tunnel +kmod-ptp +kmod-sched-act-sample +kmod-vxlan FILES:=$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlxsw/mlxsw_spectrum.ko KCONFIG:= \ CONFIG_MLXSW_SPECTRUM \ - CONFIG_NET_SWITCHDEV=y \ CONFIG_MLXSW_SPECTRUM_DCB=y \ - CONFIG_DCB=y \ - CONFIG_AMD_XGBE_DCB=n \ - CONFIG_IXGBE_DCB=n \ - CONFIG_I40E_DCB=n \ - CONFIG_QLCNIC_DCB=n \ - CONFIG_FSL_DPAA2_ETH_DCB=n \ - CONFIG_FSL_DPAA2_SWITCH=n + CONFIG_NET_SWITCHDEV=y \ + CONFIG_DCB=y AUTOLOAD:=$(call AutoProbe,mlxsw_spectrum) endef From 5c8862a649a09480abc7f46ca5257653597b398d Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Sat, 27 Jul 2024 15:41:14 +0200 Subject: [PATCH 12/23] kernel: rtl8367b: detect rtl8367d chip family Detect the RTL8367D chip family and set the appropriate extif Co-authored-by: Serge Vasilugin Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/14804 Signed-off-by: Hauke Mehrtens --- .../generic/files/drivers/net/phy/rtl8366_smi.h | 4 +++- .../generic/files/drivers/net/phy/rtl8367b.c | 16 ++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h index 4b3b3fe98c..c81d168ee4 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h +++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h @@ -30,7 +30,9 @@ typedef enum rtl8367b_chip_e { RTL8367B_CHIP_RTL8367R_VB, /* chip with exception in extif assignment */ /* Family C */ RTL8367B_CHIP_RTL8367RB_VB, - RTL8367B_CHIP_RTL8367S + RTL8367B_CHIP_RTL8367S, +/* Family D */ + RTL8367B_CHIP_RTL8367S_VB /* chip with exception in extif assignment */ } rtl8367b_chip_t; struct rtl8366_mib_counter { diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index 69deaec20c..a80e1c2f80 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -1,6 +1,7 @@ /* * Platform driver for Realtek RTL8367B family chips, i.e. RTL8367RB and RTL8367R-VB * extended with support for RTL8367C family chips, i.e. RTL8367RB-VB and RTL8367S + * extended with support for RTL8367D family chips, i.e. RTL8367S-VB * * Copyright (C) 2012 Gabor Juhos * @@ -528,6 +529,7 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi) break; case RTL8367B_CHIP_RTL8367RB_VB: case RTL8367B_CHIP_RTL8367S: + case RTL8367B_CHIP_RTL8367S_VB: initvals = rtl8367c_initvals; count = ARRAY_SIZE(rtl8367c_initvals); break; @@ -741,6 +743,14 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, err = -EINVAL; goto err_init; } + } else if (smi->rtl8367b_chip == RTL8367B_CHIP_RTL8367S_VB) { /* for the RTL8367S-VB chip, cpu_port 7 corresponds to extif1, cpu_port 6 corresponds to extif0 */ + if (cpu_port != RTL8367B_CPU_PORT_NUM) { + id = cpu_port - RTL8367B_CPU_PORT_NUM - 1; + } else { + dev_err(smi->parent, "wrong cpu_port %u in %s property\n", cpu_port, name); + err = -EINVAL; + goto err_init; + } } else { id = cpu_port - RTL8367B_CPU_PORT_NUM; } @@ -1348,6 +1358,12 @@ static int rtl8367b_detect(struct rtl8366_smi *smi) } switch (chip_ver) { + case 0x0010: + if (chip_num == 0x6642) { + chip_name = "8367S-VB"; + smi->rtl8367b_chip = RTL8367B_CHIP_RTL8367S_VB; + } + break; case 0x0020: if (chip_num == 0x6367) { chip_name = "8367RB-VB"; From 2283e746d809ec260f6d50991f7df67aa538913b Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Fri, 23 Aug 2024 21:24:03 +0200 Subject: [PATCH 13/23] kernel: set and get ports speed for rtl8367d family chips Set and get ports speed for rtl8367d family chips Co-authored-by: Serge Vasilugin Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/14804 Signed-off-by: Hauke Mehrtens --- .../generic/files/drivers/net/phy/rtl8367b.c | 54 +++++++++++++------ 1 file changed, 38 insertions(+), 16 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index a80e1c2f80..a1efd8fe5b 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -268,6 +268,14 @@ struct rtl8367b_initval { #define RTL8367B_MIB_RXB_ID 0 /* IfInOctets */ #define RTL8367B_MIB_TXB_ID 28 /* IfOutOctets */ +#define RTL8367D_PORT_STATUS_REG(_p) (0x12d0 + (_p)) + +#define RTL8367D_PORT_STATUS_SPEED1_MASK 0x3000 +#define RTL8367D_PORT_STATUS_SPEED1_SHIFT 10 /*12-2*/ + +#define RTL8367D_REG_MAC0_FORCE_SELECT 0x12c0 +#define RTL8367D_REG_MAC0_FORCE_SELECT_EN 0x12c8 + static struct rtl8366_mib_counter rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = { {0, 0, 4, "ifInOctets" }, @@ -646,23 +654,31 @@ static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id, u32 val; int err; - mask = (RTL8367B_DI_FORCE_MODE | - RTL8367B_DI_FORCE_NWAY | - RTL8367B_DI_FORCE_TXPAUSE | - RTL8367B_DI_FORCE_RXPAUSE | - RTL8367B_DI_FORCE_LINK | - RTL8367B_DI_FORCE_DUPLEX | - RTL8367B_DI_FORCE_SPEED_MASK); - - val = pa->speed; - val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0; + val = pa->speed & RTL8367B_DI_FORCE_SPEED_MASK; val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0; val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0; val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0; val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0; val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0; - REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val); + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) { /* Family D */ + val |= (pa->speed << RTL8367D_PORT_STATUS_SPEED1_SHIFT) & RTL8367D_PORT_STATUS_SPEED1_MASK; + if (smi->cpu_port != UINT_MAX) { + REG_WR(smi, RTL8367D_REG_MAC0_FORCE_SELECT + smi->cpu_port, val); + REG_WR(smi, RTL8367D_REG_MAC0_FORCE_SELECT_EN + smi->cpu_port, pa->force_mode ? 0xffff : 0x0000); + } + } else { + val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0; + mask = (RTL8367B_DI_FORCE_MODE | + RTL8367B_DI_FORCE_NWAY | + RTL8367B_DI_FORCE_TXPAUSE | + RTL8367B_DI_FORCE_RXPAUSE | + RTL8367B_DI_FORCE_LINK | + RTL8367B_DI_FORCE_DUPLEX | + RTL8367B_DI_FORCE_SPEED_MASK); + + REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val); + } return 0; } @@ -1100,7 +1116,10 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev, if (port >= RTL8367B_NUM_PORTS) return -EINVAL; - rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data); + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */ + rtl8366_smi_read_reg(smi, RTL8367D_PORT_STATUS_REG(port), &data); + else + rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data); link->link = !!(data & RTL8367B_PORT_STATUS_LINK); if (!link->link) @@ -1111,15 +1130,18 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev, link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE); link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY); - speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK); + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */ + speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK) | ((data & RTL8367D_PORT_STATUS_SPEED1_MASK) >> RTL8367D_PORT_STATUS_SPEED1_SHIFT); + else + speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK); switch (speed) { - case 0: + case RTL8367B_PORT_STATUS_SPEED_10: link->speed = SWITCH_PORT_SPEED_10; break; - case 1: + case RTL8367B_PORT_STATUS_SPEED_100: link->speed = SWITCH_PORT_SPEED_100; break; - case 2: + case RTL8367B_PORT_STATUS_SPEED_1000: link->speed = SWITCH_PORT_SPEED_1000; break; default: From dd2af4711ae3d36ddf262472e561cd0e30a23ca6 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Sun, 21 Jul 2024 22:55:17 +0200 Subject: [PATCH 14/23] kernel: set and get mc index for rtl8367d family chips Set and get mc index for rtl8367d family chips Co-authored-by: Serge Vasilugin Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/14804 Signed-off-by: Hauke Mehrtens --- .../generic/files/drivers/net/phy/rtl8367b.c | 26 ++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index a1efd8fe5b..75912c4454 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -276,6 +276,10 @@ struct rtl8367b_initval { #define RTL8367D_REG_MAC0_FORCE_SELECT 0x12c0 #define RTL8367D_REG_MAC0_FORCE_SELECT_EN 0x12c8 +#define RTL8367D_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p)) +#define RTL8367D_VLAN_PVID_CTRL_MASK 0xfff +#define RTL8367D_VLAN_PVID_CTRL_SHIFT(_p) 0 + static struct rtl8366_mib_counter rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = { {0, 0, 4, "ifInOctets" }, @@ -1040,10 +1044,17 @@ static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val) if (port >= RTL8367B_NUM_PORTS) return -EINVAL; - REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data); + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) { /* Family D */ + REG_RD(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), &data); - *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) & - RTL8367B_VLAN_PVID_CTRL_MASK; + *val = (data >> RTL8367D_VLAN_PVID_CTRL_SHIFT(port)) & + RTL8367D_VLAN_PVID_CTRL_MASK; + } else { + REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data); + + *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) & + RTL8367B_VLAN_PVID_CTRL_MASK; + } return 0; } @@ -1053,7 +1064,14 @@ static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index) if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS) return -EINVAL; - return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */ + return rtl8366_smi_rmwr(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), + RTL8367D_VLAN_PVID_CTRL_MASK << + RTL8367D_VLAN_PVID_CTRL_SHIFT(port), + (index & RTL8367D_VLAN_PVID_CTRL_MASK) << + RTL8367D_VLAN_PVID_CTRL_SHIFT(port)); + else + return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), RTL8367B_VLAN_PVID_CTRL_MASK << RTL8367B_VLAN_PVID_CTRL_SHIFT(port), (index & RTL8367B_VLAN_PVID_CTRL_MASK) << From fe71f37bc1f208d4f1c28a0695d78511c8e1a917 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Tue, 20 Aug 2024 21:19:41 +0200 Subject: [PATCH 15/23] kernel: set and get vlan 4k for rtl8367d family chips Set and get vlan 4k for rtl8367d family chips Co-authored-by: Serge Vasilugin Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/14804 Signed-off-by: Hauke Mehrtens --- .../generic/files/drivers/net/phy/rtl8367b.c | 35 +++++++++++++++---- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index 75912c4454..0f93e95a6f 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -280,6 +280,14 @@ struct rtl8367b_initval { #define RTL8367D_VLAN_PVID_CTRL_MASK 0xfff #define RTL8367D_VLAN_PVID_CTRL_SHIFT(_p) 0 +#define RTL8367D_FIDMAX 3 +#define RTL8367D_FID_MASK 3 +#define RTL8367D_TA_VLAN1_FID_SHIFT 0 +#define RTL8367D_TA_VLAN1_FID_MASK RTL8367D_FID_MASK + +#define RTL8367D_VID_MASK 0xfff +#define RTL8367D_TA_VLAN_VID_MASK RTL8367D_VID_MASK + static struct rtl8366_mib_counter rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = { {0, 0, 4, "ifInOctets" }, @@ -941,8 +949,12 @@ static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, RTL8367B_TA_VLAN0_MEMBER_MASK; vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) & RTL8367B_TA_VLAN0_UNTAG_MASK; - vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) & - RTL8367B_TA_VLAN1_FID_MASK; + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */ + vlan4k->fid = (data[1] >> RTL8367D_TA_VLAN1_FID_SHIFT) & + RTL8367D_TA_VLAN1_FID_MASK; + else + vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) & + RTL8367B_TA_VLAN1_FID_MASK; return 0; } @@ -957,7 +969,7 @@ static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi, if (vlan4k->vid >= RTL8367B_NUM_VIDS || vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK || vlan4k->untag > RTL8367B_UNTAG_MASK || - vlan4k->fid > RTL8367B_FIDMAX) + vlan4k->fid > ((smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) ? RTL8367D_FIDMAX : RTL8367B_FIDMAX)) return -EINVAL; memset(data, 0, sizeof(data)); @@ -966,15 +978,24 @@ static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi, RTL8367B_TA_VLAN0_MEMBER_SHIFT; data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) << RTL8367B_TA_VLAN0_UNTAG_SHIFT; - data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) << - RTL8367B_TA_VLAN1_FID_SHIFT; + + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */ + data[1] = ((vlan4k->fid & RTL8367D_TA_VLAN1_FID_MASK) << + RTL8367D_TA_VLAN1_FID_SHIFT) | 12; /* ivl_svl - BIT(3), svlan_chek_ivl_svl - BIT(2) */ + else + data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) << + RTL8367B_TA_VLAN1_FID_SHIFT; for (i = 0; i < ARRAY_SIZE(data); i++) REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]); /* write VID */ - REG_WR(smi, RTL8367B_TA_ADDR_REG, - vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK); + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */ + REG_WR(smi, RTL8367B_TA_ADDR_REG, + vlan4k->vid & RTL8367D_TA_VLAN_VID_MASK); + else + REG_WR(smi, RTL8367B_TA_ADDR_REG, + vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK); /* write table access control word */ REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE); From 035bb34f2629a0e80ec4bc3ccca8119ce83b1a4c Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Sun, 21 Jul 2024 23:00:59 +0200 Subject: [PATCH 16/23] kernel: set vlan mc for rtl8367d family chips Set vlan mc for rtl8367d family chips Co-authored-by: Serge Vasilugin Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/14804 Signed-off-by: Hauke Mehrtens --- target/linux/generic/files/drivers/net/phy/rtl8367b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index 0f93e95a6f..33a40f5929 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -1040,7 +1040,7 @@ static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index, vlanmc->priority > RTL8367B_PRIORITYMAX || vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK || vlanmc->untag > RTL8367B_UNTAG_MASK || - vlanmc->fid > RTL8367B_FIDMAX) + vlanmc->fid > ((smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) ? RTL8367D_FIDMAX : RTL8367B_FIDMAX)) return -EINVAL; data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) << From c288f2034d19e9503001c02f6200ba4436d18063 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Wed, 21 Aug 2024 11:46:14 +0200 Subject: [PATCH 17/23] kernel: set RGMII mode for rtl8367d family chips Set RGMII mode for rtl8367d family chips Co-authored-by: Serge Vasilugin Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/14804 Signed-off-by: Hauke Mehrtens --- .../generic/files/drivers/net/phy/rtl8367b.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index 33a40f5929..296d013619 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -288,6 +288,17 @@ struct rtl8367b_initval { #define RTL8367D_VID_MASK 0xfff #define RTL8367D_TA_VLAN_VID_MASK RTL8367D_VID_MASK +#define RTL8367D_REG_EXT_TXC_DLY 0x13f9 +#define RTL8367D_EXT1_RGMII_TX_DLY_MASK 0x38 + +#define RTL8367D_REG_TOP_CON0 0x1d70 +#define RTL8367D_MAC7_SEL_EXT1_MASK 0x2000 +#define RTL8367D_MAC4_SEL_EXT1_MASK 0x1000 + +#define RTL8367D_REG_SDS1_MISC0 0x1d78 +#define RTL8367D_SDS1_MODE_MASK 0x1f +#define RTL8367D_PORT_SDS_MODE_DISABLE 0x1f + static struct rtl8366_mib_counter rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = { {0, 0, 4, "ifInOctets" }, @@ -589,6 +600,7 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id, enum rtl8367_extif_mode mode) { int err; + u32 data; /* set port mode */ switch (mode) { @@ -608,6 +620,15 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id, RTL8367B_DEBUG1_DP_MASK(id), (7 << RTL8367B_DEBUG1_DN_SHIFT(id)) | (7 << RTL8367B_DEBUG1_DP_SHIFT(id))); + if ((smi->rtl8367b_chip == RTL8367B_CHIP_RTL8367S_VB) && (id == 1)) { + REG_RMW(smi, RTL8367D_REG_EXT_TXC_DLY, RTL8367D_EXT1_RGMII_TX_DLY_MASK, 0); + /* Configure RGMII/MII mux to port 7 if UTP_PORT4 is not RGMII mode */ + REG_RD(smi, RTL8367D_REG_TOP_CON0, &data); + data &= RTL8367D_MAC4_SEL_EXT1_MASK; + if (data == 0) + REG_RMW(smi, RTL8367D_REG_TOP_CON0, RTL8367D_MAC7_SEL_EXT1_MASK, RTL8367D_MAC7_SEL_EXT1_MASK); + REG_RMW(smi, RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_DISABLE); + } } else { REG_RMW(smi, RTL8367B_CHIP_DEBUG2_REG, RTL8367B_DEBUG2_DRI_EXT2 | From 9232fdeb8687c3ff0f4caeb94a3615ea4fdfca00 Mon Sep 17 00:00:00 2001 From: Mieczyslaw Nalewaj Date: Thu, 22 Aug 2024 13:30:28 +0200 Subject: [PATCH 18/23] kernel: set vlan mc emulation for rtl8367d family chips Set vlan mc emulation for rtl8367d family chips Co-authored-by: Serge Vasilugin Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/14804 Signed-off-by: Hauke Mehrtens --- .../files/drivers/net/phy/rtl8366_smi.h | 1 + .../generic/files/drivers/net/phy/rtl8367b.c | 81 ++++++++++++++++--- 2 files changed, 72 insertions(+), 10 deletions(-) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h index c81d168ee4..2608240bb0 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h +++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h @@ -78,6 +78,7 @@ struct rtl8366_smi { u32 phy_id; rtl8367b_chip_t rtl8367b_chip; struct mii_bus *ext_mbus; + struct rtl8366_vlan_mc *emu_vlanmc; }; struct rtl8366_vlan_mc { diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index 296d013619..4236912dd5 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -563,6 +563,10 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi) case RTL8367B_CHIP_RTL8367S_VB: initvals = rtl8367c_initvals; count = ARRAY_SIZE(rtl8367c_initvals); + if ((smi->rtl8367b_chip == RTL8367B_CHIP_RTL8367S_VB) && (smi->emu_vlanmc == NULL)) { + smi->emu_vlanmc = kzalloc(sizeof(struct rtl8366_vlan_mc) * smi->num_vlan_mc, GFP_KERNEL); + dev_info(smi->parent, "alloc vlan mc emulator"); + } break; default: return -ENODEV; @@ -1036,6 +1040,14 @@ static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index, if (index >= RTL8367B_NUM_VLANS) return -EINVAL; + if (smi->emu_vlanmc) { /* use vlan mc emulation */ + vlanmc->vid = smi->emu_vlanmc[index].vid; + vlanmc->member = smi->emu_vlanmc[index].member; + vlanmc->fid = smi->emu_vlanmc[index].fid; + vlanmc->untag = smi->emu_vlanmc[index].untag; + return 0; + } + for (i = 0; i < ARRAY_SIZE(data); i++) REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]); @@ -1064,6 +1076,14 @@ static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index, vlanmc->fid > ((smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) ? RTL8367D_FIDMAX : RTL8367B_FIDMAX)) return -EINVAL; + if (smi->emu_vlanmc) { /* use vlanmc emulation */ + smi->emu_vlanmc[index].vid = vlanmc->vid; + smi->emu_vlanmc[index].member = vlanmc->member; + smi->emu_vlanmc[index].fid = vlanmc->fid; + smi->emu_vlanmc[index].untag = vlanmc->untag; + return 0; + } + data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) << RTL8367B_VLAN_MC0_MEMBER_SHIFT; data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) << @@ -1087,10 +1107,34 @@ static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val) return -EINVAL; if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) { /* Family D */ - REG_RD(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), &data); + int i; + struct rtl8366_vlan_mc vlanmc; - *val = (data >> RTL8367D_VLAN_PVID_CTRL_SHIFT(port)) & - RTL8367D_VLAN_PVID_CTRL_MASK; + err = rtl8366_smi_read_reg(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), &data); + + if (err) { + dev_err(smi->parent, "read pvid register 0x%04x fail", RTL8367D_VLAN_PVID_CTRL_REG(port)); + return err; + } + + data &= RTL8367D_VLAN_PVID_CTRL_MASK; + for (i = 0; i < smi->num_vlan_mc; i++) { + err = rtl8367b_get_vlan_mc(smi, i, &vlanmc); + + if (err) { + dev_err(smi->parent, "get vlan mc index %d fail", i); + return err; + } + + if (data == vlanmc.vid) break; + } + + if (i < smi->num_vlan_mc) { + *val = i; + } else { + dev_err(smi->parent, "vlan mc index for pvid %d not found", data); + return -EINVAL; + } } else { REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data); @@ -1106,13 +1150,27 @@ static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index) if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS) return -EINVAL; - if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */ - return rtl8366_smi_rmwr(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), - RTL8367D_VLAN_PVID_CTRL_MASK << - RTL8367D_VLAN_PVID_CTRL_SHIFT(port), - (index & RTL8367D_VLAN_PVID_CTRL_MASK) << - RTL8367D_VLAN_PVID_CTRL_SHIFT(port)); - else + if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) { /* Family D */ + int pvid, err; + struct rtl8366_vlan_mc vlanmc; + + err = rtl8367b_get_vlan_mc(smi, index, &vlanmc); + + if (err) { + dev_err(smi->parent, "get vlan mc index %d fail", index); + return err; + } + + pvid = vlanmc.vid & RTL8367D_VLAN_PVID_CTRL_MASK; + err = rtl8366_smi_write_reg(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), pvid); + + if (err) { + dev_err(smi->parent, "set port %d pvid %d fail", port, pvid); + return err; + } + + return 0; + } else return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), RTL8367B_VLAN_PVID_CTRL_MASK << RTL8367B_VLAN_PVID_CTRL_SHIFT(port), @@ -1420,6 +1478,7 @@ static int rtl8367b_detect(struct rtl8366_smi *smi) u32 chip_ver; int ret; + smi->emu_vlanmc = NULL; smi->rtl8367b_chip = RTL8367B_CHIP_UNKNOWN; rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG, @@ -1535,6 +1594,8 @@ static int rtl8367b_probe(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); rtl8366_smi_cleanup(smi); err_free_smi: + if (smi->emu_vlanmc) + kfree(smi->emu_vlanmc); kfree(smi); return err; } From 51f96278ed121546fa5788d717fd8a9635a56158 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Fri, 14 Jun 2024 12:19:15 -0700 Subject: [PATCH 19/23] ath79: nec,wX1200cr: use nvmem Userspace handling is deprecated. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/16245 Signed-off-by: Hauke Mehrtens --- target/linux/ath79/dts/qca9561_nec_wf1200cr.dts | 7 ++++++- target/linux/ath79/dts/qca9563_nec_wg1200cr.dts | 7 ++++++- .../base-files/etc/hotplug.d/firmware/10-ath9k-eeprom | 2 -- .../base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac | 9 +++++++-- 4 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts b/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts index c4671bf57f..4e66f45ebe 100644 --- a/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts +++ b/target/linux/ath79/dts/qca9561_nec_wf1200cr.dts @@ -114,6 +114,10 @@ #address-cells = <1>; #size-cells = <1>; + cal_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + precal_art_5000: pre-calibration@5000 { reg = <0x5000 0x2f20>; }; @@ -177,5 +181,6 @@ &wmac { status = "okay"; - qca,no-eeprom; + nvmem-cells = <&cal_art_1000>; + nvmem-cell-names = "calibration"; }; diff --git a/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts b/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts index 7f8866bd36..c9e47938d3 100644 --- a/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts +++ b/target/linux/ath79/dts/qca9563_nec_wg1200cr.dts @@ -129,6 +129,10 @@ #address-cells = <1>; #size-cells = <1>; + cal_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + precal_art_5000: pre-calibration@5000 { reg = <0x5000 0x2f20>; }; @@ -178,5 +182,6 @@ &wmac { status = "okay"; - qca,no-eeprom; + nvmem-cells = <&cal_art_1000>; + nvmem-cell-names = "calibration"; }; diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom index ddcef7b685..1f20250a2b 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -30,8 +30,6 @@ case "$FIRMWARE" in dlink,dir-842-c1|\ dlink,dir-842-c2|\ dlink,dir-842-c3|\ - nec,wf1200cr|\ - nec,wg1200cr|\ wd,mynet-n600|\ wd,mynet-n750) caldata_extract "art" 0x1000 0x440 diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac index 2a1f230eb4..15cd2adda3 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -88,12 +88,17 @@ case "$board" in [ "$PHYNBR" -eq 1 ] && \ macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress ;; - nec,wf1200cr|\ - nec,wg1200cr|\ qihoo,c301) [ "$PHYNBR" -eq 0 ] && \ mtd_get_mac_ascii devdata wlan5mac > /sys${DEVPATH}/macaddress ;; + nec,wf1200cr|\ + nec,wg1200cr|\ + [ "$PHYNBR" -eq 0 ] && \ + mtd_get_mac_ascii devdata wlan5mac > /sys${DEVPATH}/macaddress + [ "$PHYNBR" -eq 1 ] && \ + mtd_get_mac_ascii devdata wlan24mac > /sys${DEVPATH}/macaddress + ;; phicomm,k2t) [ "$PHYNBR" -eq 0 ] && \ k2t_get_mac "5g_mac" > /sys${DEVPATH}/macaddress From 9bbaa6f2c0419739fb85d48d0f527cb1622946ee Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 29 Aug 2024 20:24:02 +0200 Subject: [PATCH 20/23] base-files: fix merge of passwd/shadow/group lines with trailing colons Empty trailing fields get lost when the lines are split and merged again at colons, resulting in unparsable entries. Only use the split fields for matching against the other file, but emit the original line unchanged to fix the issue. Fixes: de7ca7dafadf ("base-files: merge /etc/passwd et al at sysupgrade config restore") Signed-off-by: Matthias Schiffer --- package/base-files/files/lib/preinit/80_mount_root | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/base-files/files/lib/preinit/80_mount_root b/package/base-files/files/lib/preinit/80_mount_root index fa6abcde57..940c56c925 100644 --- a/package/base-files/files/lib/preinit/80_mount_root +++ b/package/base-files/files/lib/preinit/80_mount_root @@ -9,7 +9,7 @@ missing_lines() { IFS=":" while read line; do set -- $line - grep -q "^$1:" "$file2" || echo "$*" + grep -q "^$1:" "$file2" || echo "$line" done < "$file1" IFS="$oIFS" } From 70e41d0205d95386881fa1cdf6ee00f6cca1b3f6 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 15 Jun 2024 13:42:25 -0700 Subject: [PATCH 21/23] ath79: elecom,wab: use nvmem Userspace handling is deprecated. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/16247 Signed-off-by: Hauke Mehrtens --- target/linux/ath79/dts/qca955x_elecom_wab.dtsi | 17 +++++++++++++---- .../generic/base-files/etc/board.d/02_network | 3 --- .../etc/hotplug.d/ieee80211/10_fix_wifi_mac | 10 ---------- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/target/linux/ath79/dts/qca955x_elecom_wab.dtsi b/target/linux/ath79/dts/qca955x_elecom_wab.dtsi index 43e34c6029..53bb5b0141 100644 --- a/target/linux/ath79/dts/qca955x_elecom_wab.dtsi +++ b/target/linux/ath79/dts/qca955x_elecom_wab.dtsi @@ -8,6 +8,7 @@ / { aliases { + label-mac-device = ð0; led-boot = &led_status; led-failsafe = &led_status; led-upgrade = &led_status; @@ -107,6 +108,9 @@ phy-mode = "rgmii-rxid"; pll-data = <0xae000000 0x80000101 0x80001313>; + nvmem-cells = <&macaddr_uboot_ethaddr 0>; + nvmem-cell-names = "mac-address"; + gmac-config { device = <&gmac>; @@ -144,8 +148,8 @@ wifi@0,0 { compatible = "qcom,ath10k"; reg = <0x0000 0 0 0 0>; - nvmem-cells = <&cal_art_5000>; - nvmem-cell-names = "calibration"; + nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_ethaddr 1>; + nvmem-cell-names = "calibration", "mac-address"; }; }; @@ -169,9 +173,14 @@ }; partition@40000 { + compatible = "u-boot,env"; label = "u-boot-env"; reg = <0x40000 0x10000>; read-only; + + macaddr_uboot_ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; }; partition@50000 { @@ -252,6 +261,6 @@ &wmac { status = "okay"; - nvmem-cells = <&cal_art_1000>; - nvmem-cell-names = "calibration"; + nvmem-cells = <&cal_art_1000>, <&macaddr_uboot_ethaddr 0>; + nvmem-cell-names = "calibration", "mac-address"; }; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index ccb296a62a..bc251d0484 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -712,9 +712,6 @@ ath79_setup_macs() lan_mac=$(mtd_get_mac_ascii devdata "lanmac") wan_mac=$(mtd_get_mac_ascii devdata "wanmac") ;; - elecom,wab-i1750-ps|\ - elecom,wab-s1167-ps|\ - elecom,wab-s600-ps|\ engenius,ecb1200|\ engenius,ecb1750) lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac index 15cd2adda3..0a49c0b5aa 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -42,16 +42,6 @@ case "$board" in [ "$PHYNBR" -eq 1 ] && \ mtd_get_mac_ascii bdcfg "wlanmac" > /sys${DEVPATH}/macaddress ;; - elecom,wab-i1750-ps|\ - elecom,wab-s1167-ps|\ - elecom,wab-s600-ps) - # set the 5G MAC address (= ethaddr + 1) - [ "$PHYNBR" -eq 0 ] && \ - macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress - # set the 2.4G MAC address (= ethaddr) - [ "$PHYNBR" -eq 1 ] && \ - mtd_get_mac_ascii u-boot-env "ethaddr" > /sys${DEVPATH}/macaddress - ;; engenius,ecb1200|\ engenius,ecb1750) [ "$PHYNBR" -eq 0 ] && \ From 8918d842508a5f2fb021452cd55704c38a0734f4 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sat, 15 Jun 2024 15:19:04 -0700 Subject: [PATCH 22/23] ath79: nec,wg800hp: convert to nvmem Userspace handling is deprecated. Unused wan mac added to dts. Requires DSA to implement. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/16246 Signed-off-by: Hauke Mehrtens --- .../linux/ath79/dts/qca9563_nec_wg800hp.dts | 29 ++++++++++++++++++- .../generic/base-files/etc/board.d/02_network | 1 - .../etc/hotplug.d/firmware/10-ath9k-eeprom | 4 --- 3 files changed, 28 insertions(+), 6 deletions(-) diff --git a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts index d2621fa304..d8ecf46201 100644 --- a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts +++ b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts @@ -142,6 +142,24 @@ #address-cells = <1>; #size-cells = <1>; + macaddr_board_data_280: macaddr@280 { + compatible = "mac-base"; + reg = <0x280 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_board_data_480: macaddr@480 { + compatible = "mac-base"; + reg = <0x480 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_board_data_680: macaddr@680 { + compatible = "mac-base"; + reg = <0x680 0x11>; + #nvmem-cell-cells = <1>; + }; + macaddr_board_data_880: macaddr@880 { compatible = "mac-base"; reg = <0x880 0x11>; @@ -160,6 +178,10 @@ #address-cells = <1>; #size-cells = <1>; + cal_art_1000: calibration@1000 { + reg = <0x1000 0x440>; + }; + cal_art_5000: calibration@5000 { reg = <0x5000 0x844>; }; @@ -191,6 +213,9 @@ phy-mode = "sgmii"; phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_board_data_280 0>; + nvmem-cell-names = "mac-address"; }; &pcie { @@ -206,5 +231,7 @@ &wmac { status = "okay"; - qca,no-eeprom; + + nvmem-cells = <&macaddr_board_data_680 0>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; }; diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network index bc251d0484..742892a2f3 100644 --- a/target/linux/ath79/generic/base-files/etc/board.d/02_network +++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network @@ -781,7 +781,6 @@ ath79_setup_macs() label_mac=$wan_mac ;; nec,wg800hp) - lan_mac=$(mtd_get_mac_text board_data 0x280) wan_mac=$(mtd_get_mac_text board_data 0x480) label_mac=$wan_mac ;; diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom index 1f20250a2b..8cbb0e10bd 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -61,10 +61,6 @@ case "$FIRMWARE" in caldata_extract "art" 0x1000 0x440 ath9k_patch_mac $(mtd_get_mac_ascii u-boot-env mac_addr) ;; - nec,wg800hp) - caldata_extract "art" 0x1000 0x440 - ath9k_patch_mac $(mtd_get_mac_text board_data 0x680) - ;; qihoo,c301) caldata_extract "radiocfg" 0x1000 0x440 ath9k_patch_mac $(mtd_get_mac_ascii devdata "wlan24mac") From 2c48cda28b86c2ea0b3b0cd0ba12be62b8b0563a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Owoc?= Date: Tue, 30 Jul 2024 12:44:21 +0200 Subject: [PATCH 23/23] uboot-envtools: ath79: add Belkin F9K1115v2/F9J1108v2 u-boot env support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Belkin F9K1115v2/F9J1108v2 u-boot env Signed-off-by: PaweÅ‚ Owoc Link: https://github.com/openwrt/openwrt/pull/16033 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-envtools/files/ath79 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79 index 55fcec2661..4f3bc2de6c 100644 --- a/package/boot/uboot-envtools/files/ath79 +++ b/package/boot/uboot-envtools/files/ath79 @@ -89,6 +89,8 @@ zyxel,nbg6616) aruba,ap-105|\ aruba,ap-115|\ aruba,ap-175|\ +belkin,f9j1108-v2|\ +belkin,f9k1115-v2|\ dongwon,dw02-412h-64m|\ dongwon,dw02-412h-128m|\ glinet,gl-ar300m-lite|\