From 9b53a29a58d8cc271a22a207b050e788a6a5573e Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Tue, 29 Mar 2022 19:29:34 +0900 Subject: [PATCH 01/43] realtek: separate lock of RTL8231 from phy driver RTL8231 and ethernet phys are not on the same bus, so separate the lock to each own to cut off the unnecessary dependency. Signed-off-by: INAGAKI Hiroshi --- .../files-5.10/drivers/gpio/gpio-rtl8231.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c b/target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c index 7a1d6aa136..368c4fa60f 100644 --- a/target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c +++ b/target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c @@ -29,9 +29,10 @@ struct rtl8231_gpios { int ext_gpio_indrt_access; }; -extern struct mutex smi_lock; extern struct rtl83xx_soc_info soc_info; +DEFINE_MUTEX(miim_lock); + static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg) { u32 t = 0, n = 0; @@ -187,9 +188,9 @@ static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset) struct rtl8231_gpios *gpios = gpiochip_get_data(gc); pr_debug("%s: %d\n", __func__, offset); - mutex_lock(&smi_lock); + mutex_lock(&miim_lock); err = rtl8231_pin_dir(gpios, offset, 1); - mutex_unlock(&smi_lock); + mutex_unlock(&miim_lock); return err; } @@ -199,9 +200,9 @@ static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, i struct rtl8231_gpios *gpios = gpiochip_get_data(gc); pr_debug("%s: %d\n", __func__, offset); - mutex_lock(&smi_lock); + mutex_lock(&miim_lock); err = rtl8231_pin_dir(gpios, offset, 0); - mutex_unlock(&smi_lock); + mutex_unlock(&miim_lock); if (!err) err = rtl8231_pin_set(gpios, offset, value); return err; @@ -213,9 +214,9 @@ static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset) struct rtl8231_gpios *gpios = gpiochip_get_data(gc); pr_debug("%s: %d\n", __func__, offset); - mutex_lock(&smi_lock); + mutex_lock(&miim_lock); rtl8231_pin_dir_get(gpios, offset, &v); - mutex_unlock(&smi_lock); + mutex_unlock(&miim_lock); return v; } @@ -224,9 +225,9 @@ static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset) u16 state = 0; struct rtl8231_gpios *gpios = gpiochip_get_data(gc); - mutex_lock(&smi_lock); + mutex_lock(&miim_lock); rtl8231_pin_get(gpios, offset, &state); - mutex_unlock(&smi_lock); + mutex_unlock(&miim_lock); if (state & (1 << (offset % 16))) return 1; return 0; From 5b37e3245d02f414c4883e78ffe9e157225958e7 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 7 Aug 2022 15:12:46 +0900 Subject: [PATCH 02/43] realtek: update SMP-related calls in prom_init() The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects this symbol, so the family check is redudant. Furthermore, mips_cm_probe() is already called from setup_arch() in mips/kernel/setup.c before prom_init(), and as such is not required. Also move mips_cpc_probe() to run just before registering SMP ops. Signed-off-by: INAGAKI Hiroshi [squash SMP change commits, reword commit message] Signed-off-by: Sander Vanheule --- This patch only really has an impact on the rtl931x subtarget, which has no devices. Noboby is currently set up to test these patches either, but the end result is closer to MIPS_GENERIC, so I do not expect it to cause issues. --- target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c index 1428c01a33..d04d77e438 100644 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c +++ b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c @@ -214,14 +214,10 @@ void __init prom_init(void) pr_info("SoC Type: %s\n", get_system_type()); - /* Early detection of CMP support */ - if(soc_info.family == RTL9310_FAMILY_ID) { - mips_cm_probe(); - mips_cpc_probe(); - } - prom_init_cmdline(); + mips_cpc_probe(); + if (!register_cps_smp_ops()) return; From 27a580df4a560ccecc0f8d6dd0b0229a4c9192ce Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 7 Aug 2022 14:43:35 +0900 Subject: [PATCH 03/43] realtek: use MIPS fw_init_cmdline() Use the generic function of MIPS in Linux Kernel instead of open coding our own initialisation. Signed-off-by: INAGAKI Hiroshi [amend commit message] Signed-off-by: Sander Vanheule --- .../files-5.10/arch/mips/rtl838x/prom.c | 22 ++----------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c index d04d77e438..dd1b2b170d 100644 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c +++ b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -78,25 +79,6 @@ void __init device_tree_init(void) unflatten_and_copy_device_tree(); } -static void __init prom_init_cmdline(void) -{ - int argc = fw_arg0; - char **argv = (char **) KSEG1ADDR(fw_arg1); - int i; - - arcs_cmdline[0] = '\0'; - - for (i = 0; i < argc; i++) { - char *p = (char *) KSEG1ADDR(argv[i]); - - if (CPHYSADDR(p) && *p) { - strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); - } - } - pr_info("Kernel command line: %s\n", arcs_cmdline); -} - void __init identify_rtl9302(void) { switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) { @@ -214,7 +196,7 @@ void __init prom_init(void) pr_info("SoC Type: %s\n", get_system_type()); - prom_init_cmdline(); + fw_init_cmdline(); mips_cpc_probe(); From 04cca345dfc8d0debbdad0bb1907003d3433cd8c Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Wed, 30 Mar 2022 12:00:42 +0900 Subject: [PATCH 04/43] realtek: fix use of uninitialized sds_mode The initial state of sds_mode in rtl9300_force_sds_mode() is null and it will be configured in switch-case. So print message after it. Signed-off-by: INAGAKI Hiroshi [amend commit message] Signed-off-by: Sander Vanheule --- target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c index 4175b95043..259458b1be 100644 --- a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c @@ -1697,7 +1697,6 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) u32 v, cr_0, cr_1, cr_2; u32 m_bit, l_bit; - pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode); pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if); switch (phy_if) { case PHY_INTERFACE_MODE_SGMII: @@ -1740,7 +1739,7 @@ void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) return; } - pr_info("%s: SDS mode %x\n", __func__, sds_mode); + pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode); // Power down SerDes rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3); if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0)); From 3834e72fa3b632f819227bd2c564dc87ed0575fe Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Wed, 30 Mar 2022 12:04:23 +0900 Subject: [PATCH 05/43] realtek: add missing of.h include in phy driver of.h is required for of_property_read_u32(). Signed-off-by: INAGAKI Hiroshi [amend commit message] Signed-off-by: Sander Vanheule --- target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c index 259458b1be..491ceb48b6 100644 --- a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include From ff307f52f54e643ff72b50012a012f3e4ab2f0bc Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Mon, 4 Apr 2022 21:57:43 +0900 Subject: [PATCH 06/43] realtek: fix place of fdb/mdb info messages Those messages should be printed when entry was found (idx >= 0). Move them to the right place to not print invalid entry indices. Signed-off-by: INAGAKI Hiroshi [amden commit message] Signed-off-by: Sander Vanheule --- target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index f54fdd298a..f08ede730b 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -1689,8 +1689,8 @@ static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e); - pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); if (idx >= 0) { + pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); e.valid = false; dump_l2_entry(&e); priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); @@ -1870,8 +1870,8 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e); - pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); if (idx >= 0) { + pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port); if (!portmask) { e.valid = false; From b11b56e8a840471ed0cca97f43f30316468acc35 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sun, 10 Apr 2022 16:45:57 +0900 Subject: [PATCH 07/43] realtek: swap *_phylink_mac_link_down() contents Fix the (accidentally?) swapped contents of rtl83xx_phylink_mac_link_down() and rtl93xx_phylink_mac_link_down(). Signed-off-by: INAGAKI Hiroshi [amend commit message] Signed-off-by: Sander Vanheule --- .../files-5.10/drivers/net/dsa/rtl83xx/dsa.c | 29 ++++++++++--------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index f08ede730b..3ff1a96ed6 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -864,7 +864,20 @@ static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port, phy_interface_t interface) { struct rtl838x_switch_priv *priv = ds->priv; - u32 v; + + /* Stop TX/RX to port */ + sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); + + // No longer force link + sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u32 v = 0; /* Stop TX/RX to port */ sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); @@ -874,19 +887,7 @@ static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port, v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN; else if (priv->family_id == RTL9310_FAMILY_ID) v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN; - sw_w32_mask(v, 0, priv->r->mac_port_ctrl(port)); -} - -static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port, - unsigned int mode, - phy_interface_t interface) -{ - struct rtl838x_switch_priv *priv = ds->priv; - /* Stop TX/RX to port */ - sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); - - // No longer force link - sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port)); + sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port)); } static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port, From 629f2de1a772bbfc6bbc37a3aacb67805dc9fb39 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Sat, 17 Sep 2022 13:30:05 +0900 Subject: [PATCH 08/43] realtek: cleanup rtl83{8x,9x}_enable_learning/flood In *_enable_learning() only address learning should be configured, so remove enabling forwarding. Forwarding is configured by the respective *_enable_flood() functions. Clean up both functions for RTL838x and RTL839x, and fix the comment on the number of entries. Signed-off-by: INAGAKI Hiroshi [squash RTL838x, RTL839x changes] Signed-off-by: Sander Vanheule --- .../drivers/net/dsa/rtl83xx/rtl838x.c | 32 ++++++----------- .../drivers/net/dsa/rtl83xx/rtl839x.c | 34 ++++++------------- 2 files changed, 22 insertions(+), 44 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c index 76b6cde7be..93fab7e6e3 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c @@ -515,32 +515,22 @@ static void rtl838x_l2_learning_setup(void) static void rtl838x_enable_learning(int port, bool enable) { - // Limit learning to maximum: 32k entries, after that just flood (bits 0-1) + // Limit learning to maximum: 16k entries - if (enable) { - // flood after 32k entries - sw_w32((0x3fff << 2) | 0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); - } else { - // just forward - sw_w32(0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); - } + sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0, + RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); } static void rtl838x_enable_flood(int port, bool enable) { - u32 flood_mask = sw_r32(RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); - - if (enable) { - // flood - flood_mask &= ~3; - flood_mask |= 0; - sw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); - } else { - // drop (bit 1) - flood_mask &= ~3; - flood_mask |= 1; - sw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); - } + /* + * 0: Forward + * 1: Disable + * 2: to CPU + * 3: Copy to CPU + */ + sw_w32_mask(0x3, enable ? 0 : 1, + RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); } static void rtl838x_enable_mcast_flood(int port, bool enable) diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c index 7b838cb76b..199ba347da 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c @@ -560,34 +560,22 @@ static void rtl839x_l2_learning_setup(void) static void rtl839x_enable_learning(int port, bool enable) { - // Limit learning to maximum: 32k entries, after that just flood (bits 0-1) - - if (enable) { - // flood after 32k entries - sw_w32((0x7fff << 2) | 0, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); - } else { - // just forward - sw_w32(0, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); - } + // Limit learning to maximum: 32k entries + sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0, + RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); } static void rtl839x_enable_flood(int port, bool enable) { - u32 flood_mask = sw_r32(RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); - - if (enable) { - // flood - flood_mask &= ~3; - flood_mask |= 0; - sw_w32(flood_mask, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); - } else { - // drop (bit 1) - flood_mask &= ~3; - flood_mask |= 1; - sw_w32(flood_mask, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); - } - + /* + * 0: Forward + * 1: Disable + * 2: to CPU + * 3: Copy to CPU + */ + sw_w32_mask(0x3, enable ? 0 : 1, + RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); } static void rtl839x_enable_mcast_flood(int port, bool enable) From 88eae0f0366d483dad77e5e4e9cdb02c99523e69 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 9 Oct 2022 16:34:35 +0100 Subject: [PATCH 09/43] mediatek: filogic: set correct PWM clock and clean thermal zone * set correct clocks for PWM to work. * MT7986 PWM does have the 26MHz-clock-select, set that in patch * drop useless 'passive' trip point in thermal zone * extend pwm-fan to have 3 active operating points * set reasonable trip points in thermal zone * invert pwm-fan operating points and set shorter period to allow less noisy operation of the PWM fan of the BPi-R3. Signed-off-by: Daniel Golle --- .../mediatek/dts/mt7986a-bananapi-bpi-r3.dts | 3 +- .../arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 33 +++++++++---------- .../804-pwm-add-mt7986-support.patch | 2 +- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts index 37588e2ac4..8e47cb8579 100644 --- a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts +++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts @@ -447,7 +447,8 @@ }; &fan { - pwms = <&pwm 0 500000 0>; + pwms = <&pwm 0 10000 0>; + cooling-levels = <255 96 52 0>; status = "okay"; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index ade4cebbd5..be82acd204 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -206,8 +206,8 @@ #clock-cells = <1>; #pwm-cells = <2>; interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&infracfg CLK_INFRA_PWM_BSEL>, + clocks = <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM_STA>, <&infracfg CLK_INFRA_PWM1_CK>, <&infracfg CLK_INFRA_PWM2_CK>; clock-names = "top", "main", "pwm1", "pwm2"; @@ -664,8 +664,8 @@ fan: pwm-fan { compatible = "pwm-fan"; - /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ - cooling-levels = <0 128 255>; + /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */ + cooling-levels = <0 86 172 255>; #cooling-cells = <2>; status = "disabled"; }; @@ -694,14 +694,14 @@ type = "active"; }; - cpu_trip_active_low: active-low { + cpu_trip_active_med: active-med { temperature = <85000>; hysteresis = <2000>; type = "active"; }; - cpu_trip_passive: passive { - temperature = <40000>; + cpu_trip_active_low: active-low { + temperature = <60000>; hysteresis = <2000>; type = "passive"; }; @@ -709,24 +709,23 @@ cooling-maps { cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; trip = <&cpu_trip_active_high>; }; + cpu-active-med { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + cpu-active-low { - /* active: set fan to cooling level 1 */ + /* passive: set fan to cooling level 1 */ cooling-device = <&fan 1 1>; trip = <&cpu_trip_active_low>; }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; }; - }; }; }; diff --git a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch index fe095c5633..7a10dac051 100644 --- a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch +++ b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch @@ -7,7 +7,7 @@ +static const struct pwm_mediatek_of_data mt7986_pwm_data = { + .num_pwms = 2, + .pwm45_fixup = false, -+ .has_ck_26m_sel = false, ++ .has_ck_26m_sel = true, +}; + static const struct pwm_mediatek_of_data mt8516_pwm_data = { From df08849c00a0ba81d7e24f8635900bdc8e66adb2 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Tue, 10 Aug 2021 21:37:17 +0200 Subject: [PATCH 10/43] odhcp6c: respect 'delegate' option for 464XLAT sub-interface dhcpv6.script contained support for disabling prefix delegation of 464XLAT sub-interface, but netifd protocol handler was missing the required export to disable this. Add missing export, akin to DS-Lite and MAP. Signed-off-by: Lech Perczak Signed-off-by: Hans Dedecker [PKG_RELEASE increase] --- package/network/ipv6/odhcp6c/Makefile | 2 +- package/network/ipv6/odhcp6c/files/dhcpv6.sh | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/package/network/ipv6/odhcp6c/Makefile b/package/network/ipv6/odhcp6c/Makefile index 82bc719139..505aa56e41 100644 --- a/package/network/ipv6/odhcp6c/Makefile +++ b/package/network/ipv6/odhcp6c/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=odhcp6c -PKG_RELEASE:=18 +PKG_RELEASE:=19 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcp6c.git diff --git a/package/network/ipv6/odhcp6c/files/dhcpv6.sh b/package/network/ipv6/odhcp6c/files/dhcpv6.sh index cf6847f29e..ac8c7797fb 100755 --- a/package/network/ipv6/odhcp6c/files/dhcpv6.sh +++ b/package/network/ipv6/odhcp6c/files/dhcpv6.sh @@ -105,6 +105,7 @@ proto_dhcpv6_setup() { [ -n "$iface_464xlat" ] && proto_export "IFACE_464XLAT=$iface_464xlat" [ "$delegate" = "0" ] && proto_export "IFACE_DSLITE_DELEGATE=0" [ "$delegate" = "0" ] && proto_export "IFACE_MAP_DELEGATE=0" + [ "$delegate" = "0" ] && proto_export "IFACE_464XLAT_DELEGATE=0" [ -n "$zone_dslite" ] && proto_export "ZONE_DSLITE=$zone_dslite" [ -n "$zone_map" ] && proto_export "ZONE_MAP=$zone_map" [ -n "$zone_464xlat" ] && proto_export "ZONE_464XLAT=$zone_464xlat" From e2da6a0a59a81a4fc0fdffde31abf22ee121e9f5 Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 5 Oct 2022 07:58:32 -0400 Subject: [PATCH 11/43] kernel: bump 5.10 to 5.10.147 Removed upstreamed: bcm53xx/patches-5.10/083-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch[1] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.147&id=a8e6cde5062fb2aff81f86cc0770591714bee545 Signed-off-by: John Audia --- include/kernel-5.10 | 4 +- ...or-support-mtd-name-from-device-tree.patch | 2 +- ...-rely-on-node-name-for-correct-PLL-s.patch | 72 ------------------- ...-mt7530-MT7530-optional-GPIO-support.patch | 4 +- ...-mt7530-Add-support-for-EEE-features.patch | 6 +- ...the-dst-buffer-to-of_get_mac_address.patch | 2 +- ...1-net-dsa-mt7530-support-setting-MTU.patch | 4 +- ...-dsa-mt7530-enable-MTU-normalization.patch | 4 +- ...a-mt7530-support-setting-ageing-time.patch | 4 +- ...et-dsa-mt7530-support-MDB-operations.patch | 8 +-- ...net-dsa-mt7530-add-interrupt-support.patch | 16 ++--- .../generic/hack-5.10/253-ksmbd-config.patch | 1 + ...e_mem_map-with-ARCH_PFN_OFFSET-calcu.patch | 2 +- .../pending-5.10/834-ledtrig-libata.patch | 8 +-- ...c-explicitly-deassert-gmac-ahb-reset.patch | 4 +- .../lantiq/patches-5.10/0152-lantiq-VPE.patch | 2 +- .../oxnas/patches-5.10/999-libata-hacks.patch | 4 +- ...or-support-mtd-name-from-device-tree.patch | 2 +- 18 files changed, 39 insertions(+), 110 deletions(-) delete mode 100644 target/linux/bcm53xx/patches-5.10/083-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch diff --git a/include/kernel-5.10 b/include/kernel-5.10 index 60b71eea92..58ba0d5b30 100644 --- a/include/kernel-5.10 +++ b/include/kernel-5.10 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.10 = .146 -LINUX_KERNEL_HASH-5.10.146 = 7bbd97f3278eadb73c19a1ca8c1a655c60afcee9f487b910063cdd15e9ee6dc1 +LINUX_VERSION-5.10 = .147 +LINUX_KERNEL_HASH-5.10.147 = 85253abf097eb5013b988a400eb022eed0e0626e7e0a7daa3ab4b6bcabbced9a diff --git a/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch index 63c05e84bd..62f610492f 100644 --- a/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ b/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -34,7 +34,7 @@ Signed-off-by: Abhimanyu Vishwakarma mtd->type = MTD_NORFLASH; --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c -@@ -849,6 +849,17 @@ out_error: +@@ -851,6 +851,17 @@ out_error: */ static void mtd_set_dev_defaults(struct mtd_info *mtd) { diff --git a/target/linux/bcm53xx/patches-5.10/083-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch b/target/linux/bcm53xx/patches-5.10/083-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch deleted file mode 100644 index 12c60ce297..0000000000 --- a/target/linux/bcm53xx/patches-5.10/083-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 1b24a132eba7a1c19475ba2510ec1c00af3ff914 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 5 Sep 2022 09:15:03 -0700 -Subject: [PATCH] clk: iproc: Do not rely on node name for correct PLL setup -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -After commit 31fd9b79dc58 ("ARM: dts: BCM5301X: update CRU block -description") a warning from clk-iproc-pll.c was generated due to a -duplicate PLL name as well as the console stopped working. Upon closer -inspection it became clear that iproc_pll_clk_setup() used the Device -Tree node unit name as an unique identifier as well as a parent name to -parent all clocks under the PLL. - -BCM5301X was the first platform on which that got noticed because of the -DT node unit name renaming but the same assumptions hold true for any -user of the iproc_pll_clk_setup() function. - -The first 'clock-output-names' property is always guaranteed to be -unique as well as providing the actual desired PLL clock name, so we -utilize that to register the PLL and as a parent name of all children -clock. - -Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") -Signed-off-by: Florian Fainelli -Acked-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20220905161504.1526-1-f.fainelli@gmail.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/bcm/clk-iproc-pll.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/clk/bcm/clk-iproc-pll.c -+++ b/drivers/clk/bcm/clk-iproc-pll.c -@@ -736,6 +736,7 @@ void iproc_pll_clk_setup(struct device_n - const char *parent_name; - struct iproc_clk *iclk_array; - struct clk_hw_onecell_data *clk_data; -+ const char *clk_name; - - if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) - return; -@@ -783,7 +784,12 @@ void iproc_pll_clk_setup(struct device_n - iclk = &iclk_array[0]; - iclk->pll = pll; - -- init.name = node->name; -+ ret = of_property_read_string_index(node, "clock-output-names", -+ 0, &clk_name); -+ if (WARN_ON(ret)) -+ goto err_pll_register; -+ -+ init.name = clk_name; - init.ops = &iproc_pll_ops; - init.flags = 0; - parent_name = of_clk_get_parent_name(node, 0); -@@ -803,13 +809,11 @@ void iproc_pll_clk_setup(struct device_n - goto err_pll_register; - - clk_data->hws[0] = &iclk->hw; -+ parent_name = clk_name; - - /* now initialize and register all leaf clocks */ - for (i = 1; i < num_clks; i++) { -- const char *clk_name; -- - memset(&init, 0, sizeof(init)); -- parent_name = node->name; - - ret = of_property_read_string_index(node, "clock-output-names", - i, &clk_name); diff --git a/target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch b/target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch index cf3ccae5bf..bd60df37e3 100644 --- a/target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch +++ b/target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch @@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski #include #include "mt7530.h" -@@ -1534,6 +1535,109 @@ mtk_get_tag_protocol(struct dsa_switch * +@@ -1537,6 +1538,109 @@ mtk_get_tag_protocol(struct dsa_switch * } } @@ -137,7 +137,7 @@ Signed-off-by: Jakub Kicinski static int mt7530_setup(struct dsa_switch *ds) { -@@ -1676,6 +1780,12 @@ mt7530_setup(struct dsa_switch *ds) +@@ -1679,6 +1783,12 @@ mt7530_setup(struct dsa_switch *ds) } } diff --git a/target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch b/target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch index 84f8db54aa..2ba6c604a8 100644 --- a/target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch +++ b/target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2366,6 +2366,17 @@ static void mt753x_phylink_mac_link_up(s +@@ -2371,6 +2371,17 @@ static void mt753x_phylink_mac_link_up(s mcr |= PMCR_RX_FC_EN; } @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller mt7530_set(priv, MT7530_PMCR_P(port), mcr); } -@@ -2596,6 +2607,36 @@ mt753x_phy_write(struct dsa_switch *ds, +@@ -2599,6 +2610,36 @@ mt753x_phy_write(struct dsa_switch *ds, return priv->info->phy_write(ds, port, regnum, val); } @@ -72,7 +72,7 @@ Signed-off-by: David S. Miller static const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, -@@ -2624,6 +2665,8 @@ static const struct dsa_switch_ops mt753 +@@ -2627,6 +2668,8 @@ static const struct dsa_switch_ops mt753 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, .phylink_mac_link_down = mt753x_phylink_mac_link_down, .phylink_mac_link_up = mt753x_phylink_mac_link_up, diff --git a/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch b/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch index 77b85a232c..1c1884e571 100644 --- a/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch +++ b/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch @@ -1360,7 +1360,7 @@ Signed-off-by: David S. Miller int irq; --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -4987,7 +4987,7 @@ int stmmac_dvr_probe(struct device *devi +@@ -5000,7 +5000,7 @@ int stmmac_dvr_probe(struct device *devi priv->wol_irq = res->wol_irq; priv->lpi_irq = res->lpi_irq; diff --git a/target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch b/target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch index 52476b926a..f1fa461aec 100644 --- a/target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch +++ b/target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch @@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1015,6 +1015,53 @@ mt7530_port_disable(struct dsa_switch *d +@@ -1018,6 +1018,53 @@ mt7530_port_disable(struct dsa_switch *d mutex_unlock(&priv->reg_mutex); } @@ -73,7 +73,7 @@ Signed-off-by: Jakub Kicinski static void mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) { -@@ -2647,6 +2694,8 @@ static const struct dsa_switch_ops mt753 +@@ -2650,6 +2697,8 @@ static const struct dsa_switch_ops mt753 .get_sset_count = mt7530_get_sset_count, .port_enable = mt7530_port_enable, .port_disable = mt7530_port_disable, diff --git a/target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch b/target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch index 1c0a80aa78..a239549758 100644 --- a/target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch +++ b/target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch @@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1703,6 +1703,7 @@ mt7530_setup(struct dsa_switch *ds) +@@ -1706,6 +1706,7 @@ mt7530_setup(struct dsa_switch *ds) */ dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; ds->configure_vlan_while_not_filtering = true; @@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski if (priv->id == ID_MT7530) { regulator_set_voltage(priv->core_pwr, 1000000, 1000000); -@@ -1948,6 +1949,7 @@ mt7531_setup(struct dsa_switch *ds) +@@ -1953,6 +1954,7 @@ mt7531_setup(struct dsa_switch *ds) } ds->configure_vlan_while_not_filtering = true; diff --git a/target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch b/target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch index d5a3eb8dc3..0b28a4626e 100644 --- a/target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch +++ b/target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch @@ -20,7 +20,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -870,6 +870,46 @@ mt7530_get_sset_count(struct dsa_switch +@@ -873,6 +873,46 @@ mt7530_get_sset_count(struct dsa_switch return ARRAY_SIZE(mt7530_mib); } @@ -67,7 +67,7 @@ Signed-off-by: David S. Miller static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; -@@ -2694,6 +2734,7 @@ static const struct dsa_switch_ops mt753 +@@ -2697,6 +2737,7 @@ static const struct dsa_switch_ops mt753 .phy_write = mt753x_phy_write, .get_ethtool_stats = mt7530_get_ethtool_stats, .get_sset_count = mt7530_get_sset_count, diff --git a/target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch b/target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch index 8208670a38..99f49972ff 100644 --- a/target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch +++ b/target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch @@ -14,7 +14,7 @@ Signed-off-by: DENG Qingfang --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -998,9 +998,6 @@ mt753x_cpu_port_enable(struct dsa_switch +@@ -1001,9 +1001,6 @@ mt753x_cpu_port_enable(struct dsa_switch mt7530_write(priv, MT7530_PVC_P(port), PORT_SPEC_TAG); @@ -24,7 +24,7 @@ Signed-off-by: DENG Qingfang /* Set CPU port number */ if (priv->id == ID_MT7621) mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); -@@ -1131,6 +1128,20 @@ mt7530_stp_state_set(struct dsa_switch * +@@ -1134,6 +1131,20 @@ mt7530_stp_state_set(struct dsa_switch * } static int @@ -45,7 +45,7 @@ Signed-off-by: DENG Qingfang mt7530_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *bridge) { -@@ -1331,6 +1342,63 @@ err: +@@ -1334,6 +1345,63 @@ err: } static int @@ -109,7 +109,7 @@ Signed-off-by: DENG Qingfang mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) { struct mt7530_dummy_poll p; -@@ -2740,11 +2808,15 @@ static const struct dsa_switch_ops mt753 +@@ -2743,11 +2811,15 @@ static const struct dsa_switch_ops mt753 .port_change_mtu = mt7530_port_change_mtu, .port_max_mtu = mt7530_port_max_mtu, .port_stp_state_set = mt7530_stp_state_set, diff --git a/target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch b/target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch index 1831670f06..c7e3a4ceb4 100644 --- a/target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch +++ b/target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch @@ -27,7 +27,7 @@ Signed-off-by: David S. Miller #include #include #include -@@ -600,18 +601,14 @@ mt7530_mib_reset(struct dsa_switch *ds) +@@ -603,18 +604,14 @@ mt7530_mib_reset(struct dsa_switch *ds) mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); } @@ -48,7 +48,7 @@ Signed-off-by: David S. Miller return mdiobus_write_nested(priv->bus, port, regnum, val); } -@@ -789,9 +786,8 @@ out: +@@ -792,9 +789,8 @@ out: } static int @@ -59,7 +59,7 @@ Signed-off-by: David S. Miller int devad; int ret; -@@ -807,10 +803,9 @@ mt7531_ind_phy_read(struct dsa_switch *d +@@ -810,10 +806,9 @@ mt7531_ind_phy_read(struct dsa_switch *d } static int @@ -71,7 +71,7 @@ Signed-off-by: David S. Miller int devad; int ret; -@@ -826,6 +821,22 @@ mt7531_ind_phy_write(struct dsa_switch * +@@ -829,6 +824,22 @@ mt7531_ind_phy_write(struct dsa_switch * return ret; } @@ -94,7 +94,7 @@ Signed-off-by: David S. Miller static void mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) -@@ -1793,6 +1804,210 @@ mt7530_setup_gpio(struct mt7530_priv *pr +@@ -1796,6 +1807,210 @@ mt7530_setup_gpio(struct mt7530_priv *pr return devm_gpiochip_add_data(dev, gc, priv); } @@ -305,7 +305,7 @@ Signed-off-by: David S. Miller static int mt7530_setup(struct dsa_switch *ds) { -@@ -2744,24 +2959,20 @@ static int +@@ -2747,24 +2962,20 @@ static int mt753x_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; @@ -340,7 +340,7 @@ Signed-off-by: David S. Miller } static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, -@@ -2798,8 +3009,6 @@ static const struct dsa_switch_ops mt753 +@@ -2801,8 +3012,6 @@ static const struct dsa_switch_ops mt753 .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, .get_strings = mt7530_get_strings, @@ -349,7 +349,7 @@ Signed-off-by: David S. Miller .get_ethtool_stats = mt7530_get_ethtool_stats, .get_sset_count = mt7530_get_sset_count, .set_ageing_time = mt7530_set_ageing_time, -@@ -2982,6 +3191,9 @@ mt7530_remove(struct mdio_device *mdiode +@@ -2985,6 +3194,9 @@ mt7530_remove(struct mdio_device *mdiode dev_err(priv->dev, "Failed to disable io pwr: %d\n", ret); diff --git a/target/linux/generic/hack-5.10/253-ksmbd-config.patch b/target/linux/generic/hack-5.10/253-ksmbd-config.patch index 2992dbeda0..81da6d8f52 100644 --- a/target/linux/generic/hack-5.10/253-ksmbd-config.patch +++ b/target/linux/generic/hack-5.10/253-ksmbd-config.patch @@ -31,3 +31,4 @@ Submitted-by: Rosen Penev + tristate "OID" help Enable fast lookup object identifier registry. + diff --git a/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch index f788deabac..e00382149a 100644 --- a/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch +++ b/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch @@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf --- a/mm/page_alloc.c +++ b/mm/page_alloc.c -@@ -7059,7 +7059,7 @@ static void __ref alloc_node_mem_map(str +@@ -7104,7 +7104,7 @@ static void __ref alloc_node_mem_map(str if (pgdat == NODE_DATA(0)) { mem_map = NODE_DATA(0)->node_mem_map; if (page_to_pfn(mem_map) != pgdat->node_start_pfn) diff --git a/target/linux/generic/pending-5.10/834-ledtrig-libata.patch b/target/linux/generic/pending-5.10/834-ledtrig-libata.patch index 5b10f1257e..636fe24aea 100644 --- a/target/linux/generic/pending-5.10/834-ledtrig-libata.patch +++ b/target/linux/generic/pending-5.10/834-ledtrig-libata.patch @@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle /** * ata_build_rw_tf - Build ATA taskfile for given read/write request * @tf: Target ATA taskfile -@@ -4551,6 +4564,9 @@ struct ata_queued_cmd *ata_qc_new_init(s +@@ -4555,6 +4568,9 @@ struct ata_queued_cmd *ata_qc_new_init(s if (tag < 0) return NULL; } @@ -75,7 +75,7 @@ Signed-off-by: Daniel Golle qc = __ata_qc_from_tag(ap, tag); qc->tag = qc->hw_tag = tag; -@@ -5329,6 +5345,9 @@ struct ata_port *ata_port_alloc(struct a +@@ -5333,6 +5349,9 @@ struct ata_port *ata_port_alloc(struct a ap->stats.unhandled_irq = 1; ap->stats.idle_irq = 1; #endif @@ -85,7 +85,7 @@ Signed-off-by: Daniel Golle ata_sff_port_init(ap); return ap; -@@ -5364,6 +5383,12 @@ static void ata_host_release(struct kref +@@ -5368,6 +5387,12 @@ static void ata_host_release(struct kref kfree(ap->pmp_link); kfree(ap->slave_link); @@ -98,7 +98,7 @@ Signed-off-by: Daniel Golle kfree(ap); host->ports[i] = NULL; } -@@ -5770,7 +5795,23 @@ int ata_host_register(struct ata_host *h +@@ -5774,7 +5799,23 @@ int ata_host_register(struct ata_host *h host->ports[i]->print_id = atomic_inc_return(&ata_print_id); host->ports[i]->local_port_no = i + 1; } diff --git a/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch b/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch index 84f5f95841..324d42770d 100644 --- a/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch +++ b/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch @@ -29,7 +29,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5020,6 +5020,10 @@ int stmmac_dvr_probe(struct device *devi +@@ -5033,6 +5033,10 @@ int stmmac_dvr_probe(struct device *devi reset_control_reset(priv->plat->stmmac_rst); } @@ -40,7 +40,7 @@ Signed-off-by: David S. Miller /* Init MAC and get the capabilities */ ret = stmmac_hw_init(priv); if (ret) -@@ -5244,6 +5248,7 @@ int stmmac_dvr_remove(struct device *dev +@@ -5247,6 +5251,7 @@ int stmmac_dvr_remove(struct device *dev phylink_destroy(priv->phylink); if (priv->plat->stmmac_rst) reset_control_assert(priv->plat->stmmac_rst); diff --git a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch index c3b63188a7..71e9886d2e 100644 --- a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch +++ b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch @@ -1,6 +1,6 @@ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -2438,6 +2438,12 @@ config MIPS_VPE_LOADER +@@ -2434,6 +2434,12 @@ config MIPS_VPE_LOADER Includes a loader for loading an elf relocatable object onto another VPE and running it. diff --git a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch index 5af87b4a86..461a1b87f4 100644 --- a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch +++ b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch @@ -15,7 +15,7 @@ /* initialize internal qc */ qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL); -@@ -4558,6 +4566,9 @@ struct ata_queued_cmd *ata_qc_new_init(s +@@ -4562,6 +4570,9 @@ struct ata_queued_cmd *ata_qc_new_init(s if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) return NULL; @@ -25,7 +25,7 @@ /* libsas case */ if (ap->flags & ATA_FLAG_SAS_HOST) { tag = ata_sas_allocate_tag(ap); -@@ -4603,6 +4614,8 @@ void ata_qc_free(struct ata_queued_cmd * +@@ -4607,6 +4618,8 @@ void ata_qc_free(struct ata_queued_cmd * qc->tag = ATA_TAG_POISON; if (ap->flags & ATA_FLAG_SAS_HOST) ata_sas_free_tag(tag, ap); diff --git a/target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch index 63c05e84bd..62f610492f 100644 --- a/target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ b/target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -34,7 +34,7 @@ Signed-off-by: Abhimanyu Vishwakarma mtd->type = MTD_NORFLASH; --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c -@@ -849,6 +849,17 @@ out_error: +@@ -851,6 +851,17 @@ out_error: */ static void mtd_set_dev_defaults(struct mtd_info *mtd) { From 911012662047ec133bdf4f5e490e0891cb782f3c Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 5 Oct 2022 06:04:11 -0400 Subject: [PATCH 12/43] kernel: bump 5.15 to 5.15.72 Removed upstreamed: generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch[1] bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch[2] All other patches automatically rebased Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 Run-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 (RB5009UG+S+IN) 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=5de02ab84aeca765da0e4d8e999af35325ac67c2 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=ab5c5787ab5ecdc4a7ea20b4ef542579e1beb49d Signed-off-by: John Audia --- include/kernel-5.15 | 4 +- ...or-support-mtd-name-from-device-tree.patch | 2 +- .../patches-5.15/920-mikrotik-rb4xx.patch | 2 +- .../patches-5.15/939-mikrotik-rb91x.patch | 4 +- ...oup-Disable-cgroup-memory-by-default.patch | 4 +- ...-rely-on-node-name-for-correct-PLL-s.patch | 72 --------------- ...terate-using-dsa_switch_for_each_use.patch | 4 +- ...opulate-supported_interfaces-and-mac.patch | 16 ++-- ...t-dsa-mt7530-remove-interface-checks.patch | 16 ++-- ...rop-use-of-phylink_helper_basex_spee.patch | 2 +- ...nly-indicate-linkmodes-that-can-be-s.patch | 6 +- ...-switch-to-use-phylink_get_linkmodes.patch | 12 +-- ...530-partially-convert-to-phylink_pcs.patch | 30 +++--- ...ove-autoneg-handling-to-PCS-validati.patch | 6 +- ...19-net-dsa-mt7530-mark-as-non-legacy.patch | 2 +- ...mt753x-fix-pcs-conversion-regression.patch | 4 +- ...t7530-rework-mt7530_hw_vlan_-add-del.patch | 6 +- ...et-dsa-mt7530-rework-mt753-01-_setup.patch | 8 +- ...et-cpu-port-via-dp-cpu_dp-instead-of.patch | 16 ++-- ...icro-stmmac-move-queue-reset-to-dedi.patch | 12 +-- ...icro-stmmac-first-disable-all-queues.patch | 4 +- ...icro-stmmac-move-dma-conf-to-dedicat.patch | 92 +++++++++---------- ...icro-stmmac-generate-stmmac-dma-conf.patch | 24 ++--- ...icro-stmmac-permit-MTU-change-with-i.patch | 4 +- ...-mm-multigenerational-lru-groundwork.patch | 2 +- ...e_mem_map-with-ARCH_PFN_OFFSET-calcu.patch | 2 +- ...detach-callback-to-struct-phy_driver.patch | 2 +- ...531-only-do-PLL-once-after-the-reset.patch | 67 -------------- .../pending-5.15/834-ledtrig-libata.patch | 8 +- ...pecific-data-to-struct-skb_shared_in.patch | 2 +- ...phy-define-PSGMII-PHY-interface-mode.patch | 4 +- .../oxnas/patches-5.15/999-libata-hacks.patch | 4 +- ...y-simplify-phy_link_change-arguments.patch | 2 +- 33 files changed, 153 insertions(+), 292 deletions(-) delete mode 100644 target/linux/bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch delete mode 100644 target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch diff --git a/include/kernel-5.15 b/include/kernel-5.15 index 3085a029d2..f971683bdd 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .71 -LINUX_KERNEL_HASH-5.15.71 = 5f5408138e016c0e029e015d98ceab86f4e6366c65cd611259dac808ab1d1e53 +LINUX_VERSION-5.15 = .72 +LINUX_KERNEL_HASH-5.15.72 = 6090323b5b471ae9d3bbc0058966113609f5bbd22fa19a76df32a8abc52f07ab diff --git a/target/linux/ath79/patches-5.15/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/ath79/patches-5.15/401-mtd-nor-support-mtd-name-from-device-tree.patch index afedf0be88..92f5116a8e 100644 --- a/target/linux/ath79/patches-5.15/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ b/target/linux/ath79/patches-5.15/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -34,7 +34,7 @@ Signed-off-by: Abhimanyu Vishwakarma mtd->type = MTD_NORFLASH; --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c -@@ -849,6 +849,17 @@ out_error: +@@ -851,6 +851,17 @@ out_error: */ static void mtd_set_dev_defaults(struct mtd_info *mtd) { diff --git a/target/linux/ath79/patches-5.15/920-mikrotik-rb4xx.patch b/target/linux/ath79/patches-5.15/920-mikrotik-rb4xx.patch index 5492687251..a425f8639d 100644 --- a/target/linux/ath79/patches-5.15/920-mikrotik-rb4xx.patch +++ b/target/linux/ath79/patches-5.15/920-mikrotik-rb4xx.patch @@ -58,7 +58,7 @@ Submitted-by: Christopher Hill + Routerboard RB4xx series. + config SGI_MFD_IOC3 - bool "SGI IOC3 core driver" + bool "SGI IOC3 core driver" depends on PCI && MIPS && 64BIT --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile diff --git a/target/linux/ath79/patches-5.15/939-mikrotik-rb91x.patch b/target/linux/ath79/patches-5.15/939-mikrotik-rb91x.patch index 459b6ff9b1..94967bf674 100644 --- a/target/linux/ath79/patches-5.15/939-mikrotik-rb91x.patch +++ b/target/linux/ath79/patches-5.15/939-mikrotik-rb91x.patch @@ -44,8 +44,8 @@ Tested-by: Koen Vandeputte tristate "Xylon LogiCVC GPIO support" depends on MFD_SYSCON && OF @@ -529,6 +536,10 @@ config GPIO_ROCKCHIP - help - Say yes here to support GPIO on Rockchip SoCs. + help + Say yes here to support GPIO on Rockchip SoCs. +config GPIO_RB91X_KEY + tristate "MikroTik RB91x board series reset key support" diff --git a/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch b/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch index a836952eeb..087d28300d 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch @@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell for_each_subsys(ss, ssid) { if (ss->early_init) { struct cgroup_subsys_state *css = -@@ -6497,6 +6506,10 @@ static int __init cgroup_disable(char *s +@@ -6503,6 +6512,10 @@ static int __init cgroup_disable(char *s strcmp(token, ss->legacy_name)) continue; @@ -51,7 +51,7 @@ Signed-off-by: Phil Elwell static_branch_disable(cgroup_subsys_enabled_key[i]); pr_info("Disabling %s control group subsystem\n", ss->name); -@@ -6515,6 +6528,31 @@ static int __init cgroup_disable(char *s +@@ -6521,6 +6534,31 @@ static int __init cgroup_disable(char *s } __setup("cgroup_disable=", cgroup_disable); diff --git a/target/linux/bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch b/target/linux/bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch deleted file mode 100644 index 12c60ce297..0000000000 --- a/target/linux/bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 1b24a132eba7a1c19475ba2510ec1c00af3ff914 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 5 Sep 2022 09:15:03 -0700 -Subject: [PATCH] clk: iproc: Do not rely on node name for correct PLL setup -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -After commit 31fd9b79dc58 ("ARM: dts: BCM5301X: update CRU block -description") a warning from clk-iproc-pll.c was generated due to a -duplicate PLL name as well as the console stopped working. Upon closer -inspection it became clear that iproc_pll_clk_setup() used the Device -Tree node unit name as an unique identifier as well as a parent name to -parent all clocks under the PLL. - -BCM5301X was the first platform on which that got noticed because of the -DT node unit name renaming but the same assumptions hold true for any -user of the iproc_pll_clk_setup() function. - -The first 'clock-output-names' property is always guaranteed to be -unique as well as providing the actual desired PLL clock name, so we -utilize that to register the PLL and as a parent name of all children -clock. - -Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") -Signed-off-by: Florian Fainelli -Acked-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20220905161504.1526-1-f.fainelli@gmail.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/bcm/clk-iproc-pll.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/clk/bcm/clk-iproc-pll.c -+++ b/drivers/clk/bcm/clk-iproc-pll.c -@@ -736,6 +736,7 @@ void iproc_pll_clk_setup(struct device_n - const char *parent_name; - struct iproc_clk *iclk_array; - struct clk_hw_onecell_data *clk_data; -+ const char *clk_name; - - if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) - return; -@@ -783,7 +784,12 @@ void iproc_pll_clk_setup(struct device_n - iclk = &iclk_array[0]; - iclk->pll = pll; - -- init.name = node->name; -+ ret = of_property_read_string_index(node, "clock-output-names", -+ 0, &clk_name); -+ if (WARN_ON(ret)) -+ goto err_pll_register; -+ -+ init.name = clk_name; - init.ops = &iproc_pll_ops; - init.flags = 0; - parent_name = of_clk_get_parent_name(node, 0); -@@ -803,13 +809,11 @@ void iproc_pll_clk_setup(struct device_n - goto err_pll_register; - - clk_data->hws[0] = &iclk->hw; -+ parent_name = clk_name; - - /* now initialize and register all leaf clocks */ - for (i = 1; i < num_clks; i++) { -- const char *clk_name; -- - memset(&init, 0, sizeof(init)); -- parent_name = node->name; - - ret = of_property_read_string_index(node, "clock-output-names", - i, &clk_name); diff --git a/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch index 74567109c5..e3f01ada6d 100644 --- a/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch +++ b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch @@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1188,27 +1188,31 @@ static int +@@ -1191,27 +1191,31 @@ static int mt7530_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *bridge) { @@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski } /* Add the all other ports to this port matrix. */ -@@ -1301,24 +1305,28 @@ static void +@@ -1304,24 +1308,28 @@ static void mt7530_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *bridge) { diff --git a/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch index 690cc78fb5..94b8cb053d 100644 --- a/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch +++ b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch @@ -23,7 +23,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2385,6 +2385,32 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2390,6 +2390,32 @@ mt7531_setup(struct dsa_switch *ds) return 0; } @@ -56,7 +56,7 @@ Signed-off-by: Paolo Abeni static bool mt7530_phy_mode_supported(struct dsa_switch *ds, int port, const struct phylink_link_state *state) -@@ -2421,6 +2447,37 @@ static bool mt7531_is_rgmii_port(struct +@@ -2426,6 +2452,37 @@ static bool mt7531_is_rgmii_port(struct return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); } @@ -94,7 +94,7 @@ Signed-off-by: Paolo Abeni static bool mt7531_phy_mode_supported(struct dsa_switch *ds, int port, const struct phylink_link_state *state) -@@ -2899,6 +2956,18 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -2902,6 +2959,18 @@ mt7531_cpu_port_config(struct dsa_switch return 0; } @@ -113,7 +113,7 @@ Signed-off-by: Paolo Abeni static void mt7530_mac_port_validate(struct dsa_switch *ds, int port, unsigned long *supported) -@@ -3134,6 +3203,7 @@ static const struct dsa_switch_ops mt753 +@@ -3137,6 +3206,7 @@ static const struct dsa_switch_ops mt753 .port_vlan_del = mt7530_port_vlan_del, .port_mirror_add = mt753x_port_mirror_add, .port_mirror_del = mt753x_port_mirror_del, @@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni .phylink_validate = mt753x_phylink_validate, .phylink_mac_link_state = mt753x_phylink_mac_link_state, .phylink_mac_config = mt753x_phylink_mac_config, -@@ -3151,6 +3221,7 @@ static const struct mt753x_info mt753x_t +@@ -3154,6 +3224,7 @@ static const struct mt753x_info mt753x_t .phy_read = mt7530_phy_read, .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, @@ -129,7 +129,7 @@ Signed-off-by: Paolo Abeni .phy_mode_supported = mt7530_phy_mode_supported, .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, -@@ -3162,6 +3233,7 @@ static const struct mt753x_info mt753x_t +@@ -3165,6 +3236,7 @@ static const struct mt753x_info mt753x_t .phy_read = mt7530_phy_read, .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, @@ -137,7 +137,7 @@ Signed-off-by: Paolo Abeni .phy_mode_supported = mt7530_phy_mode_supported, .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, -@@ -3174,6 +3246,7 @@ static const struct mt753x_info mt753x_t +@@ -3177,6 +3249,7 @@ static const struct mt753x_info mt753x_t .phy_write = mt7531_ind_phy_write, .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, @@ -145,7 +145,7 @@ Signed-off-by: Paolo Abeni .phy_mode_supported = mt7531_phy_mode_supported, .mac_port_validate = mt7531_mac_port_validate, .mac_port_get_state = mt7531_phylink_mac_link_state, -@@ -3236,6 +3309,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3239,6 +3312,7 @@ mt7530_probe(struct mdio_device *mdiodev */ if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || diff --git a/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch index 60eee013d1..322dc6f6ef 100644 --- a/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch +++ b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch @@ -21,7 +21,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2411,37 +2411,6 @@ static void mt7530_mac_port_get_caps(str +@@ -2416,37 +2416,6 @@ static void mt7530_mac_port_get_caps(str } } @@ -59,7 +59,7 @@ Signed-off-by: Paolo Abeni static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) { return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); -@@ -2478,44 +2447,6 @@ static void mt7531_mac_port_get_caps(str +@@ -2483,44 +2452,6 @@ static void mt7531_mac_port_get_caps(str } } @@ -104,7 +104,7 @@ Signed-off-by: Paolo Abeni static int mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) { -@@ -2770,9 +2701,6 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2775,9 +2706,6 @@ mt753x_phylink_mac_config(struct dsa_swi struct mt7530_priv *priv = ds->priv; u32 mcr_cur, mcr_new; @@ -114,7 +114,7 @@ Signed-off-by: Paolo Abeni switch (port) { case 0 ... 4: /* Internal phy */ if (state->interface != PHY_INTERFACE_MODE_GMII) -@@ -2990,12 +2918,6 @@ mt753x_phylink_validate(struct dsa_switc +@@ -2993,12 +2921,6 @@ mt753x_phylink_validate(struct dsa_switc __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; struct mt7530_priv *priv = ds->priv; @@ -127,7 +127,7 @@ Signed-off-by: Paolo Abeni phylink_set_port_modes(mask); if (state->interface != PHY_INTERFACE_MODE_TRGMII && -@@ -3222,7 +3144,6 @@ static const struct mt753x_info mt753x_t +@@ -3225,7 +3147,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -135,7 +135,7 @@ Signed-off-by: Paolo Abeni .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, -@@ -3234,7 +3155,6 @@ static const struct mt753x_info mt753x_t +@@ -3237,7 +3158,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -143,7 +143,7 @@ Signed-off-by: Paolo Abeni .mac_port_validate = mt7530_mac_port_validate, .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, -@@ -3247,7 +3167,6 @@ static const struct mt753x_info mt753x_t +@@ -3250,7 +3170,6 @@ static const struct mt753x_info mt753x_t .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, .mac_port_get_caps = mt7531_mac_port_get_caps, @@ -151,7 +151,7 @@ Signed-off-by: Paolo Abeni .mac_port_validate = mt7531_mac_port_validate, .mac_port_get_state = mt7531_phylink_mac_link_state, .mac_port_config = mt7531_mac_config, -@@ -3310,7 +3229,6 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3313,7 +3232,6 @@ mt7530_probe(struct mdio_device *mdiodev if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || !priv->info->mac_port_get_caps || diff --git a/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch index 22bb2068de..36b3aab33b 100644 --- a/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch +++ b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2942,11 +2942,6 @@ mt753x_phylink_validate(struct dsa_switc +@@ -2945,11 +2945,6 @@ mt753x_phylink_validate(struct dsa_switc linkmode_and(supported, supported, mask); linkmode_and(state->advertising, state->advertising, mask); diff --git a/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch index d5d7c54974..831f509341 100644 --- a/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch +++ b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch @@ -23,7 +23,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2518,12 +2518,13 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2523,12 +2523,13 @@ static int mt7531_rgmii_setup(struct mt7 } static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, @@ -38,7 +38,7 @@ Signed-off-by: Paolo Abeni phylink_set(supported, 2500baseX_Full); phylink_set(supported, 2500baseT_Full); } -@@ -2898,16 +2899,18 @@ static void mt753x_phylink_get_caps(stru +@@ -2901,16 +2902,18 @@ static void mt753x_phylink_get_caps(stru static void mt7530_mac_port_validate(struct dsa_switch *ds, int port, @@ -58,7 +58,7 @@ Signed-off-by: Paolo Abeni } static void -@@ -2930,12 +2933,13 @@ mt753x_phylink_validate(struct dsa_switc +@@ -2933,12 +2936,13 @@ mt753x_phylink_validate(struct dsa_switc } /* This switch only supports 1G full-duplex. */ diff --git a/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch index 4a2c2f151d..9f54f2789b 100644 --- a/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch +++ b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2517,19 +2517,6 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2522,19 +2522,6 @@ static int mt7531_rgmii_setup(struct mt7 return 0; } @@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni static void mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, -@@ -2898,51 +2885,21 @@ static void mt753x_phylink_get_caps(stru +@@ -2901,51 +2888,21 @@ static void mt753x_phylink_get_caps(stru } static void @@ -97,7 +97,7 @@ Signed-off-by: Paolo Abeni linkmode_and(supported, supported, mask); linkmode_and(state->advertising, state->advertising, mask); -@@ -3143,7 +3100,6 @@ static const struct mt753x_info mt753x_t +@@ -3146,7 +3103,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -105,7 +105,7 @@ Signed-off-by: Paolo Abeni .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, }, -@@ -3154,7 +3110,6 @@ static const struct mt753x_info mt753x_t +@@ -3157,7 +3113,6 @@ static const struct mt753x_info mt753x_t .phy_write = mt7530_phy_write, .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, @@ -113,7 +113,7 @@ Signed-off-by: Paolo Abeni .mac_port_get_state = mt7530_phylink_mac_link_state, .mac_port_config = mt7530_mac_config, }, -@@ -3166,7 +3121,6 @@ static const struct mt753x_info mt753x_t +@@ -3169,7 +3124,6 @@ static const struct mt753x_info mt753x_t .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, .mac_port_get_caps = mt7531_mac_port_get_caps, @@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni .mac_port_get_state = mt7531_phylink_mac_link_state, .mac_port_config = mt7531_mac_config, .mac_pcs_an_restart = mt7531_sgmii_restart_an, -@@ -3228,7 +3182,6 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3231,7 +3185,6 @@ mt7530_probe(struct mdio_device *mdiodev if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || !priv->info->mac_port_get_caps || diff --git a/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch index 8a66b7fb0b..c07e627c77 100644 --- a/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch +++ b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch @@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni /* String, offset, and register size in bytes if different from 4 bytes */ static const struct mt7530_mib_desc mt7530_mib[] = { MIB_DESC(1, 0x00, "TxDrop"), -@@ -2517,12 +2522,11 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2522,12 +2527,11 @@ static int mt7531_rgmii_setup(struct mt7 return 0; } @@ -50,7 +50,7 @@ Signed-off-by: Paolo Abeni unsigned int val; /* For adjusting speed and duplex of SGMII force mode. */ -@@ -2548,6 +2552,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw +@@ -2553,6 +2557,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw /* MT7531 SGMII 1G force mode can only work in full duplex mode, * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. @@ -60,7 +60,7 @@ Signed-off-by: Paolo Abeni */ if ((speed == SPEED_10 || speed == SPEED_100) && duplex != DUPLEX_FULL) -@@ -2623,9 +2630,10 @@ static int mt7531_sgmii_setup_mode_an(st +@@ -2628,9 +2635,10 @@ static int mt7531_sgmii_setup_mode_an(st return 0; } @@ -73,7 +73,7 @@ Signed-off-by: Paolo Abeni u32 val; /* Only restart AN when AN is enabled */ -@@ -2682,6 +2690,24 @@ mt753x_mac_config(struct dsa_switch *ds, +@@ -2687,6 +2695,24 @@ mt753x_mac_config(struct dsa_switch *ds, return priv->info->mac_port_config(ds, port, mode, state->interface); } @@ -98,7 +98,7 @@ Signed-off-by: Paolo Abeni static void mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) -@@ -2743,17 +2769,6 @@ unsupported: +@@ -2748,17 +2774,6 @@ unsupported: mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); } @@ -116,7 +116,7 @@ Signed-off-by: Paolo Abeni static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) -@@ -2763,16 +2778,13 @@ static void mt753x_phylink_mac_link_down +@@ -2768,16 +2783,13 @@ static void mt753x_phylink_mac_link_down mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); } @@ -139,7 +139,7 @@ Signed-off-by: Paolo Abeni } static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, -@@ -2785,8 +2797,6 @@ static void mt753x_phylink_mac_link_up(s +@@ -2790,8 +2802,6 @@ static void mt753x_phylink_mac_link_up(s struct mt7530_priv *priv = ds->priv; u32 mcr; @@ -148,7 +148,7 @@ Signed-off-by: Paolo Abeni mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; /* MT753x MAC works in 1G full duplex mode for all up-clocked -@@ -2866,6 +2876,8 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -2869,6 +2879,8 @@ mt7531_cpu_port_config(struct dsa_switch return ret; mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPU_PORT_SETTING(priv->id)); @@ -157,7 +157,7 @@ Signed-off-by: Paolo Abeni mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, speed, DUPLEX_FULL, true, true); -@@ -2905,16 +2917,13 @@ mt753x_phylink_validate(struct dsa_switc +@@ -2908,16 +2920,13 @@ mt753x_phylink_validate(struct dsa_switc linkmode_and(state->advertising, state->advertising, mask); } @@ -178,7 +178,7 @@ Signed-off-by: Paolo Abeni pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); state->link = (pmsr & PMSR_LINK); -@@ -2941,8 +2950,6 @@ mt7530_phylink_mac_link_state(struct dsa +@@ -2944,8 +2953,6 @@ mt7530_phylink_mac_link_state(struct dsa state->pause |= MLO_PAUSE_RX; if (pmsr & PMSR_TX_FC) state->pause |= MLO_PAUSE_TX; @@ -187,7 +187,7 @@ Signed-off-by: Paolo Abeni } static int -@@ -2984,32 +2991,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 +@@ -2987,32 +2994,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 return 0; } @@ -249,7 +249,7 @@ Signed-off-by: Paolo Abeni if (ret) return ret; -@@ -3022,6 +3046,13 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3025,6 +3049,13 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -263,7 +263,7 @@ Signed-off-by: Paolo Abeni return ret; } -@@ -3083,9 +3114,8 @@ static const struct dsa_switch_ops mt753 +@@ -3086,9 +3117,8 @@ static const struct dsa_switch_ops mt753 .port_mirror_del = mt753x_port_mirror_del, .phylink_get_caps = mt753x_phylink_get_caps, .phylink_validate = mt753x_phylink_validate, @@ -274,7 +274,7 @@ Signed-off-by: Paolo Abeni .phylink_mac_link_down = mt753x_phylink_mac_link_down, .phylink_mac_link_up = mt753x_phylink_mac_link_up, .get_mac_eee = mt753x_get_mac_eee, -@@ -3095,36 +3125,34 @@ static const struct dsa_switch_ops mt753 +@@ -3098,36 +3128,34 @@ static const struct dsa_switch_ops mt753 static const struct mt753x_info mt753x_table[] = { [ID_MT7621] = { .id = ID_MT7621, @@ -314,7 +314,7 @@ Signed-off-by: Paolo Abeni }, }; -@@ -3182,7 +3210,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3185,7 +3213,7 @@ mt7530_probe(struct mdio_device *mdiodev if (!priv->info->sw_setup || !priv->info->pad_setup || !priv->info->phy_read || !priv->info->phy_write || !priv->info->mac_port_get_caps || diff --git a/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch index 2d8b4d5d57..2d57bc7a03 100644 --- a/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch +++ b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2896,25 +2896,16 @@ static void mt753x_phylink_get_caps(stru +@@ -2899,25 +2899,16 @@ static void mt753x_phylink_get_caps(stru priv->info->mac_port_get_caps(ds, port, config); } @@ -55,7 +55,7 @@ Signed-off-by: Paolo Abeni } static void mt7530_pcs_get_state(struct phylink_pcs *pcs, -@@ -3016,12 +3007,14 @@ static void mt7530_pcs_an_restart(struct +@@ -3019,12 +3010,14 @@ static void mt7530_pcs_an_restart(struct } static const struct phylink_pcs_ops mt7530_pcs_ops = { @@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni .pcs_get_state = mt7531_pcs_get_state, .pcs_config = mt753x_pcs_config, .pcs_an_restart = mt7531_pcs_an_restart, -@@ -3113,7 +3106,6 @@ static const struct dsa_switch_ops mt753 +@@ -3116,7 +3109,6 @@ static const struct dsa_switch_ops mt753 .port_mirror_add = mt753x_port_mirror_add, .port_mirror_del = mt753x_port_mirror_del, .phylink_get_caps = mt753x_phylink_get_caps, diff --git a/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch index 849a9925a1..bddc984a1f 100644 --- a/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch +++ b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch @@ -19,7 +19,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2893,6 +2893,12 @@ static void mt753x_phylink_get_caps(stru +@@ -2896,6 +2896,12 @@ static void mt753x_phylink_get_caps(stru config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; diff --git a/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch index 89f6e7509b..dcf946120e 100644 --- a/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch +++ b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch @@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3031,9 +3031,16 @@ static int +@@ -3034,9 +3034,16 @@ static int mt753x_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski if (ret) return ret; -@@ -3045,13 +3052,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3048,13 +3055,6 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch index 77b4fa1102..5fd109329c 100644 --- a/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch +++ b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch @@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1522,11 +1522,11 @@ static void +@@ -1525,11 +1525,11 @@ static void mt7530_hw_vlan_add(struct mt7530_priv *priv, struct mt7530_hw_vlan_entry *entry) { @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski /* Validate the entry with independent learning, create egress tag per * VLAN and joining the port as one of the port members. -@@ -1537,22 +1537,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p +@@ -1540,22 +1540,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p /* Decide whether adding tag or not for those outgoing packets from the * port inside the VLAN. @@ -72,7 +72,7 @@ Signed-off-by: Jakub Kicinski } static void -@@ -1571,11 +1569,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p +@@ -1574,11 +1572,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p return; } diff --git a/target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch b/target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch index 2324336ed8..165d1d035f 100644 --- a/target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch +++ b/target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch @@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2087,11 +2087,12 @@ static int +@@ -2090,11 +2090,12 @@ static int mt7530_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; @@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski u32 id, val; int ret, i; -@@ -2099,7 +2100,19 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2102,7 +2103,19 @@ mt7530_setup(struct dsa_switch *ds) * controller also is the container for two GMACs nodes representing * as two netdev instances. */ @@ -51,7 +51,7 @@ Signed-off-by: Jakub Kicinski ds->assisted_learning_on_cpu_port = true; ds->mtu_enforcement_ingress = true; -@@ -2261,6 +2274,7 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2264,6 +2277,7 @@ mt7531_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; struct mt7530_dummy_poll p; @@ -59,7 +59,7 @@ Signed-off-by: Jakub Kicinski u32 val, id; int ret, i; -@@ -2333,8 +2347,11 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2338,8 +2352,11 @@ mt7531_setup(struct dsa_switch *ds) CORE_PLL_GROUP4, val); /* BPDU to CPU port */ diff --git a/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch index 3b5ce7363f..5af91a0f7f 100644 --- a/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch +++ b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch @@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1038,6 +1038,7 @@ static int +@@ -1041,6 +1041,7 @@ static int mt7530_port_enable(struct dsa_switch *ds, int port, struct phy_device *phy) { @@ -29,7 +29,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_priv *priv = ds->priv; mutex_lock(&priv->reg_mutex); -@@ -1046,7 +1047,11 @@ mt7530_port_enable(struct dsa_switch *ds +@@ -1049,7 +1050,11 @@ mt7530_port_enable(struct dsa_switch *ds * restore the port matrix if the port is the member of a certain * bridge. */ @@ -42,7 +42,7 @@ Signed-off-by: Jakub Kicinski priv->ports[port].enable = true; mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, priv->ports[port].pm); -@@ -1194,7 +1199,8 @@ mt7530_port_bridge_join(struct dsa_switc +@@ -1197,7 +1202,8 @@ mt7530_port_bridge_join(struct dsa_switc struct net_device *bridge) { struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; @@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_priv *priv = ds->priv; mutex_lock(&priv->reg_mutex); -@@ -1271,9 +1277,12 @@ mt7530_port_set_vlan_unaware(struct dsa_ +@@ -1274,9 +1280,12 @@ mt7530_port_set_vlan_unaware(struct dsa_ * the CPU port get out of VLAN filtering mode. */ if (all_user_ports_removed) { @@ -67,7 +67,7 @@ Signed-off-by: Jakub Kicinski | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); } } -@@ -1311,6 +1320,7 @@ mt7530_port_bridge_leave(struct dsa_swit +@@ -1314,6 +1323,7 @@ mt7530_port_bridge_leave(struct dsa_swit struct net_device *bridge) { struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; @@ -75,7 +75,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_priv *priv = ds->priv; mutex_lock(&priv->reg_mutex); -@@ -1339,8 +1349,8 @@ mt7530_port_bridge_leave(struct dsa_swit +@@ -1342,8 +1352,8 @@ mt7530_port_bridge_leave(struct dsa_swit */ if (priv->ports[port].enable) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, @@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski /* When a port is removed from the bridge, the port would be set up * back to the default as is at initial boot which is a VLAN-unaware -@@ -1503,6 +1513,9 @@ static int +@@ -1506,6 +1516,9 @@ static int mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { @@ -96,7 +96,7 @@ Signed-off-by: Jakub Kicinski if (vlan_filtering) { /* The port is being kept as VLAN-unaware port when bridge is * set up with vlan_filtering not being set, Otherwise, the -@@ -1510,7 +1523,7 @@ mt7530_port_vlan_filtering(struct dsa_sw +@@ -1513,7 +1526,7 @@ mt7530_port_vlan_filtering(struct dsa_sw * for becoming a VLAN-aware port. */ mt7530_port_set_vlan_aware(ds, port); diff --git a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch index d6b7dcfbeb..b6b94ba6c2 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch @@ -62,8 +62,8 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); stmmac_start_tx_dma(priv, chan); -@@ -3757,6 +3748,8 @@ static int stmmac_open(struct net_device - goto init_error; +@@ -3766,6 +3757,8 @@ static int stmmac_open(struct net_device + } } + stmmac_reset_queues_param(priv); @@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski ret = stmmac_hw_setup(dev, true); if (ret < 0) { netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); -@@ -6396,6 +6389,7 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6409,6 +6402,7 @@ void stmmac_enable_rx_queue(struct stmma return; } @@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski stmmac_clear_rx_descriptors(priv, queue); stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, -@@ -6457,6 +6451,7 @@ void stmmac_enable_tx_queue(struct stmma +@@ -6470,6 +6464,7 @@ void stmmac_enable_tx_queue(struct stmma return; } @@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski stmmac_clear_tx_descriptors(priv, queue); stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, -@@ -7384,6 +7379,25 @@ int stmmac_suspend(struct device *dev) +@@ -7387,6 +7382,25 @@ int stmmac_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(stmmac_suspend); @@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski /** * stmmac_reset_queues_param - reset queue parameters * @priv: device pointer -@@ -7394,22 +7408,11 @@ static void stmmac_reset_queues_param(st +@@ -7397,22 +7411,11 @@ static void stmmac_reset_queues_param(st u32 tx_cnt = priv->plat->tx_queues_to_use; u32 queue; diff --git a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch index 2b148ff290..0bb28c79e7 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch @@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -3809,8 +3809,6 @@ static int stmmac_release(struct net_dev +@@ -3818,8 +3818,6 @@ static int stmmac_release(struct net_dev struct stmmac_priv *priv = netdev_priv(dev); u32 chan; @@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski if (device_may_wakeup(priv->device)) phylink_speed_down(priv->phylink, false); /* Stop and disconnect the PHY */ -@@ -3822,6 +3820,8 @@ static int stmmac_release(struct net_dev +@@ -3831,6 +3829,8 @@ static int stmmac_release(struct net_dev for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) hrtimer_cancel(&priv->tx_queue[chan].txtimer); diff --git a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch index 980d821cf5..ec3607feeb 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch @@ -766,7 +766,7 @@ Signed-off-by: Jakub Kicinski int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; /* Setup per-TXQ tbs flag before TX descriptor alloc */ -@@ -3776,7 +3776,7 @@ irq_error: +@@ -3785,7 +3785,7 @@ irq_error: phylink_stop(priv->phylink); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -775,7 +775,7 @@ Signed-off-by: Jakub Kicinski stmmac_hw_teardown(dev); init_error: -@@ -3818,7 +3818,7 @@ static int stmmac_release(struct net_dev +@@ -3827,7 +3827,7 @@ static int stmmac_release(struct net_dev stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski netif_tx_disable(dev); -@@ -3878,7 +3878,7 @@ static bool stmmac_vlan_insert(struct st +@@ -3891,7 +3891,7 @@ static bool stmmac_vlan_insert(struct st return false; stmmac_set_tx_owner(priv, p); @@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski return true; } -@@ -3896,7 +3896,7 @@ static bool stmmac_vlan_insert(struct st +@@ -3909,7 +3909,7 @@ static bool stmmac_vlan_insert(struct st static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, int total_len, bool last_segment, u32 queue) { @@ -802,7 +802,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *desc; u32 buff_size; int tmp_len; -@@ -3907,7 +3907,7 @@ static void stmmac_tso_allocator(struct +@@ -3920,7 +3920,7 @@ static void stmmac_tso_allocator(struct dma_addr_t curr_addr; tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, @@ -811,7 +811,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); if (tx_q->tbs & STMMAC_TBS_AVAIL) -@@ -3935,7 +3935,7 @@ static void stmmac_tso_allocator(struct +@@ -3948,7 +3948,7 @@ static void stmmac_tso_allocator(struct static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) { @@ -820,7 +820,7 @@ Signed-off-by: Jakub Kicinski int desc_size; if (likely(priv->extend_desc)) -@@ -3997,7 +3997,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4010,7 +4010,7 @@ static netdev_tx_t stmmac_tso_xmit(struc dma_addr_t des; int i; @@ -829,7 +829,7 @@ Signed-off-by: Jakub Kicinski first_tx = tx_q->cur_tx; /* Compute header lengths */ -@@ -4037,7 +4037,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4050,7 +4050,7 @@ static netdev_tx_t stmmac_tso_xmit(struc stmmac_set_mss(priv, mss_desc, mss); tx_q->mss = mss; tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, @@ -838,7 +838,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); } -@@ -4149,7 +4149,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4162,7 +4162,7 @@ static netdev_tx_t stmmac_tso_xmit(struc * ndo_start_xmit will fill this descriptor the next time it's * called and stmmac_tx_clean may clean up to this descriptor. */ @@ -847,7 +847,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", -@@ -4237,7 +4237,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4250,7 +4250,7 @@ static netdev_tx_t stmmac_xmit(struct sk int entry, first_tx; dma_addr_t des; @@ -856,7 +856,7 @@ Signed-off-by: Jakub Kicinski first_tx = tx_q->cur_tx; if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) -@@ -4300,7 +4300,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4313,7 +4313,7 @@ static netdev_tx_t stmmac_xmit(struct sk int len = skb_frag_size(frag); bool last_segment = (i == (nfrags - 1)); @@ -865,7 +865,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[entry]); if (likely(priv->extend_desc)) -@@ -4371,7 +4371,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4384,7 +4384,7 @@ static netdev_tx_t stmmac_xmit(struct sk * ndo_start_xmit will fill this descriptor the next time it's * called and stmmac_tx_clean may clean up to this descriptor. */ @@ -874,7 +874,7 @@ Signed-off-by: Jakub Kicinski tx_q->cur_tx = entry; if (netif_msg_pktdata(priv)) { -@@ -4486,7 +4486,7 @@ static void stmmac_rx_vlan(struct net_de +@@ -4499,7 +4499,7 @@ static void stmmac_rx_vlan(struct net_de */ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) { @@ -883,7 +883,7 @@ Signed-off-by: Jakub Kicinski int dirty = stmmac_rx_dirty(priv, queue); unsigned int entry = rx_q->dirty_rx; -@@ -4536,7 +4536,7 @@ static inline void stmmac_rx_refill(stru +@@ -4549,7 +4549,7 @@ static inline void stmmac_rx_refill(stru dma_wmb(); stmmac_set_rx_owner(priv, p, use_rx_wd); @@ -892,7 +892,7 @@ Signed-off-by: Jakub Kicinski } rx_q->dirty_rx = entry; rx_q->rx_tail_addr = rx_q->dma_rx_phy + -@@ -4564,12 +4564,12 @@ static unsigned int stmmac_rx_buf1_len(s +@@ -4577,12 +4577,12 @@ static unsigned int stmmac_rx_buf1_len(s /* First descriptor, not last descriptor and not split header */ if (status & rx_not_ls) @@ -907,7 +907,7 @@ Signed-off-by: Jakub Kicinski } static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, -@@ -4585,7 +4585,7 @@ static unsigned int stmmac_rx_buf2_len(s +@@ -4598,7 +4598,7 @@ static unsigned int stmmac_rx_buf2_len(s /* Not last descriptor */ if (status & rx_not_ls) @@ -916,7 +916,7 @@ Signed-off-by: Jakub Kicinski plen = stmmac_get_rx_frame_len(priv, p, coe); -@@ -4596,7 +4596,7 @@ static unsigned int stmmac_rx_buf2_len(s +@@ -4609,7 +4609,7 @@ static unsigned int stmmac_rx_buf2_len(s static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, struct xdp_frame *xdpf, bool dma_map) { @@ -925,7 +925,7 @@ Signed-off-by: Jakub Kicinski unsigned int entry = tx_q->cur_tx; struct dma_desc *tx_desc; dma_addr_t dma_addr; -@@ -4659,7 +4659,7 @@ static int stmmac_xdp_xmit_xdpf(struct s +@@ -4672,7 +4672,7 @@ static int stmmac_xdp_xmit_xdpf(struct s stmmac_enable_dma_transmission(priv, priv->ioaddr); @@ -934,7 +934,7 @@ Signed-off-by: Jakub Kicinski tx_q->cur_tx = entry; return STMMAC_XDP_TX; -@@ -4833,7 +4833,7 @@ static void stmmac_dispatch_skb_zc(struc +@@ -4846,7 +4846,7 @@ static void stmmac_dispatch_skb_zc(struc static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) { @@ -943,7 +943,7 @@ Signed-off-by: Jakub Kicinski unsigned int entry = rx_q->dirty_rx; struct dma_desc *rx_desc = NULL; bool ret = true; -@@ -4876,7 +4876,7 @@ static bool stmmac_rx_refill_zc(struct s +@@ -4889,7 +4889,7 @@ static bool stmmac_rx_refill_zc(struct s dma_wmb(); stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); @@ -952,7 +952,7 @@ Signed-off-by: Jakub Kicinski } if (rx_desc) { -@@ -4891,7 +4891,7 @@ static bool stmmac_rx_refill_zc(struct s +@@ -4904,7 +4904,7 @@ static bool stmmac_rx_refill_zc(struct s static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) { @@ -961,7 +961,7 @@ Signed-off-by: Jakub Kicinski unsigned int count = 0, error = 0, len = 0; int dirty = stmmac_rx_dirty(priv, queue); unsigned int next_entry = rx_q->cur_rx; -@@ -4913,7 +4913,7 @@ static int stmmac_rx_zc(struct stmmac_pr +@@ -4926,7 +4926,7 @@ static int stmmac_rx_zc(struct stmmac_pr desc_size = sizeof(struct dma_desc); } @@ -970,7 +970,7 @@ Signed-off-by: Jakub Kicinski rx_q->dma_rx_phy, desc_size); } while (count < limit) { -@@ -4960,7 +4960,7 @@ read_again: +@@ -4973,7 +4973,7 @@ read_again: /* Prefetch the next RX descriptor */ rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, @@ -979,7 +979,7 @@ Signed-off-by: Jakub Kicinski next_entry = rx_q->cur_rx; if (priv->extend_desc) -@@ -5081,7 +5081,7 @@ read_again: +@@ -5094,7 +5094,7 @@ read_again: */ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) { @@ -988,7 +988,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned int count = 0, error = 0, len = 0; int status = 0, coe = priv->hw->rx_csum; -@@ -5094,7 +5094,7 @@ static int stmmac_rx(struct stmmac_priv +@@ -5107,7 +5107,7 @@ static int stmmac_rx(struct stmmac_priv int buf_sz; dma_dir = page_pool_get_dma_dir(rx_q->page_pool); @@ -997,7 +997,7 @@ Signed-off-by: Jakub Kicinski if (netif_msg_rx_status(priv)) { void *rx_head; -@@ -5108,7 +5108,7 @@ static int stmmac_rx(struct stmmac_priv +@@ -5121,7 +5121,7 @@ static int stmmac_rx(struct stmmac_priv desc_size = sizeof(struct dma_desc); } @@ -1006,7 +1006,7 @@ Signed-off-by: Jakub Kicinski rx_q->dma_rx_phy, desc_size); } while (count < limit) { -@@ -5152,7 +5152,7 @@ read_again: +@@ -5165,7 +5165,7 @@ read_again: break; rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, @@ -1015,7 +1015,7 @@ Signed-off-by: Jakub Kicinski next_entry = rx_q->cur_rx; if (priv->extend_desc) -@@ -5286,7 +5286,7 @@ read_again: +@@ -5299,7 +5299,7 @@ read_again: buf1_len, dma_dir); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, buf->page, buf->page_offset, buf1_len, @@ -1024,7 +1024,7 @@ Signed-off-by: Jakub Kicinski /* Data payload appended into SKB */ page_pool_release_page(rx_q->page_pool, buf->page); -@@ -5298,7 +5298,7 @@ read_again: +@@ -5311,7 +5311,7 @@ read_again: buf2_len, dma_dir); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, buf->sec_page, 0, buf2_len, @@ -1033,7 +1033,7 @@ Signed-off-by: Jakub Kicinski /* Data payload appended into SKB */ page_pool_release_page(rx_q->page_pool, buf->sec_page); -@@ -5740,11 +5740,13 @@ static irqreturn_t stmmac_safety_interru +@@ -5753,11 +5753,13 @@ static irqreturn_t stmmac_safety_interru static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) { struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; @@ -1048,7 +1048,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(!data)) { netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); -@@ -5784,10 +5786,12 @@ static irqreturn_t stmmac_msi_intr_tx(in +@@ -5797,10 +5799,12 @@ static irqreturn_t stmmac_msi_intr_tx(in static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) { struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; @@ -1062,7 +1062,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(!data)) { netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); -@@ -5818,10 +5822,10 @@ static void stmmac_poll_controller(struc +@@ -5831,10 +5835,10 @@ static void stmmac_poll_controller(struc if (priv->plat->multi_msi_en) { for (i = 0; i < priv->plat->rx_queues_to_use; i++) @@ -1075,7 +1075,7 @@ Signed-off-by: Jakub Kicinski } else { disable_irq(dev->irq); stmmac_interrupt(dev->irq, dev); -@@ -6002,34 +6006,34 @@ static int stmmac_rings_status_show(stru +@@ -6015,34 +6019,34 @@ static int stmmac_rings_status_show(stru return 0; for (queue = 0; queue < rx_count; queue++) { @@ -1116,7 +1116,7 @@ Signed-off-by: Jakub Kicinski } } -@@ -6370,7 +6374,7 @@ void stmmac_disable_rx_queue(struct stmm +@@ -6383,7 +6387,7 @@ void stmmac_disable_rx_queue(struct stmm void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1125,7 +1125,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned long flags; u32 buf_size; -@@ -6407,7 +6411,7 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6420,7 +6424,7 @@ void stmmac_enable_rx_queue(struct stmma rx_q->queue_index); } else { stmmac_set_dma_bfsize(priv, priv->ioaddr, @@ -1134,7 +1134,7 @@ Signed-off-by: Jakub Kicinski rx_q->queue_index); } -@@ -6433,7 +6437,7 @@ void stmmac_disable_tx_queue(struct stmm +@@ -6446,7 +6450,7 @@ void stmmac_disable_tx_queue(struct stmm void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1143,7 +1143,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned long flags; int ret; -@@ -6480,7 +6484,7 @@ void stmmac_xdp_release(struct net_devic +@@ -6493,7 +6497,7 @@ void stmmac_xdp_release(struct net_devic stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1152,7 +1152,7 @@ Signed-off-by: Jakub Kicinski /* Free the IRQ lines */ stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); -@@ -6539,7 +6543,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6552,7 +6556,7 @@ int stmmac_xdp_open(struct net_device *d /* DMA RX Channel Configuration */ for (chan = 0; chan < rx_cnt; chan++) { @@ -1161,7 +1161,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, rx_q->dma_rx_phy, chan); -@@ -6557,7 +6561,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6570,7 +6574,7 @@ int stmmac_xdp_open(struct net_device *d rx_q->queue_index); } else { stmmac_set_dma_bfsize(priv, priv->ioaddr, @@ -1170,7 +1170,7 @@ Signed-off-by: Jakub Kicinski rx_q->queue_index); } -@@ -6566,7 +6570,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6579,7 +6583,7 @@ int stmmac_xdp_open(struct net_device *d /* DMA TX Channel Configuration */ for (chan = 0; chan < tx_cnt; chan++) { @@ -1179,7 +1179,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); -@@ -6599,7 +6603,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6612,7 +6616,7 @@ int stmmac_xdp_open(struct net_device *d irq_error: for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1188,7 +1188,7 @@ Signed-off-by: Jakub Kicinski stmmac_hw_teardown(dev); init_error: -@@ -6626,8 +6630,8 @@ int stmmac_xsk_wakeup(struct net_device +@@ -6639,8 +6643,8 @@ int stmmac_xsk_wakeup(struct net_device queue >= priv->plat->tx_queues_to_use) return -EINVAL; @@ -1199,7 +1199,7 @@ Signed-off-by: Jakub Kicinski ch = &priv->channel[queue]; if (!rx_q->xsk_pool && !tx_q->xsk_pool) -@@ -6883,8 +6887,8 @@ int stmmac_reinit_ringparam(struct net_d +@@ -6896,8 +6900,8 @@ int stmmac_reinit_ringparam(struct net_d if (netif_running(dev)) stmmac_release(dev); @@ -1210,7 +1210,7 @@ Signed-off-by: Jakub Kicinski if (netif_running(dev)) ret = stmmac_open(dev); -@@ -7330,7 +7334,7 @@ int stmmac_suspend(struct device *dev) +@@ -7333,7 +7337,7 @@ int stmmac_suspend(struct device *dev) stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1219,7 +1219,7 @@ Signed-off-by: Jakub Kicinski if (priv->eee_enabled) { priv->tx_path_in_lpi_mode = false; -@@ -7381,7 +7385,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend); +@@ -7384,7 +7388,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend); static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1228,7 +1228,7 @@ Signed-off-by: Jakub Kicinski rx_q->cur_rx = 0; rx_q->dirty_rx = 0; -@@ -7389,7 +7393,7 @@ static void stmmac_reset_rx_queue(struct +@@ -7392,7 +7396,7 @@ static void stmmac_reset_rx_queue(struct static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) { diff --git a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch index be5643df7f..0635693d55 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch @@ -1003,9 +1003,9 @@ Signed-off-by: Jakub Kicinski + buf_sz = dma_conf->dma_buf_sz; + memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); - stmmac_reset_queues_param(priv); - -@@ -3780,14 +3882,28 @@ irq_error: + if (priv->plat->serdes_powerup) { + ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); +@@ -3789,14 +3891,28 @@ irq_error: stmmac_hw_teardown(dev); init_error: @@ -1036,7 +1036,7 @@ Signed-off-by: Jakub Kicinski static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) { set_bit(__FPE_REMOVING, &priv->fpe_task_state); -@@ -3834,7 +3950,7 @@ static int stmmac_release(struct net_dev +@@ -3843,7 +3959,7 @@ static int stmmac_release(struct net_dev stmmac_stop_all_dma(priv); /* Release and free the Rx/Tx resources */ @@ -1045,7 +1045,7 @@ Signed-off-by: Jakub Kicinski /* Disable the MAC Rx/Tx */ stmmac_mac_set(priv, priv->ioaddr, false); -@@ -6369,7 +6485,7 @@ void stmmac_disable_rx_queue(struct stmm +@@ -6382,7 +6498,7 @@ void stmmac_disable_rx_queue(struct stmm spin_unlock_irqrestore(&ch->lock, flags); stmmac_stop_rx_dma(priv, queue); @@ -1054,7 +1054,7 @@ Signed-off-by: Jakub Kicinski } void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) -@@ -6380,21 +6496,21 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6393,21 +6509,21 @@ void stmmac_enable_rx_queue(struct stmma u32 buf_size; int ret; @@ -1080,7 +1080,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, rx_q->dma_rx_phy, rx_q->queue_index); -@@ -6432,7 +6548,7 @@ void stmmac_disable_tx_queue(struct stmm +@@ -6445,7 +6561,7 @@ void stmmac_disable_tx_queue(struct stmm spin_unlock_irqrestore(&ch->lock, flags); stmmac_stop_tx_dma(priv, queue); @@ -1089,7 +1089,7 @@ Signed-off-by: Jakub Kicinski } void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) -@@ -6442,21 +6558,21 @@ void stmmac_enable_tx_queue(struct stmma +@@ -6455,21 +6571,21 @@ void stmmac_enable_tx_queue(struct stmma unsigned long flags; int ret; @@ -1115,7 +1115,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, tx_q->queue_index); -@@ -6493,7 +6609,7 @@ void stmmac_xdp_release(struct net_devic +@@ -6506,7 +6622,7 @@ void stmmac_xdp_release(struct net_devic stmmac_stop_all_dma(priv); /* Release and free the Rx/Tx resources */ @@ -1124,7 +1124,7 @@ Signed-off-by: Jakub Kicinski /* Disable the MAC Rx/Tx */ stmmac_mac_set(priv, priv->ioaddr, false); -@@ -6518,14 +6634,14 @@ int stmmac_xdp_open(struct net_device *d +@@ -6531,14 +6647,14 @@ int stmmac_xdp_open(struct net_device *d u32 chan; int ret; @@ -1141,7 +1141,7 @@ Signed-off-by: Jakub Kicinski if (ret < 0) { netdev_err(dev, "%s: DMA descriptors initialization failed\n", __func__); -@@ -6607,7 +6723,7 @@ irq_error: +@@ -6620,7 +6736,7 @@ irq_error: stmmac_hw_teardown(dev); init_error: @@ -1150,7 +1150,7 @@ Signed-off-by: Jakub Kicinski dma_desc_error: return ret; } -@@ -7476,7 +7592,7 @@ int stmmac_resume(struct device *dev) +@@ -7479,7 +7595,7 @@ int stmmac_resume(struct device *dev) stmmac_reset_queues_param(priv); stmmac_free_tx_skbufs(priv); diff --git a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch index 536c7334ec..996c28119e 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch @@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5598,18 +5598,15 @@ static int stmmac_change_mtu(struct net_ +@@ -5611,18 +5611,15 @@ static int stmmac_change_mtu(struct net_ { struct stmmac_priv *priv = netdev_priv(dev); int txfifosz = priv->plat->tx_fifo_size; @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); return -EINVAL; -@@ -5621,8 +5618,29 @@ static int stmmac_change_mtu(struct net_ +@@ -5634,8 +5631,29 @@ static int stmmac_change_mtu(struct net_ if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) return -EINVAL; diff --git a/target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch b/target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch index 146f510d28..fbc15d8c91 100644 --- a/target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch +++ b/target/linux/generic/pending-5.15/020-03-mm-multigenerational-lru-groundwork.patch @@ -652,7 +652,7 @@ Change-Id: I71de7cd15b8dfa6f9fdd838023474693c4fee0a7 "Section %d Node %d Zone %d Lastcpupid %d Kasantag %d\n", --- a/mm/page_alloc.c +++ b/mm/page_alloc.c -@@ -7411,6 +7411,7 @@ static void __meminit pgdat_init_interna +@@ -7456,6 +7456,7 @@ static void __meminit pgdat_init_interna pgdat_page_ext_init(pgdat); lruvec_init(&pgdat->__lruvec); diff --git a/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch index b0b399a2dd..1ba95d3ffa 100644 --- a/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch +++ b/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch @@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf --- a/mm/page_alloc.c +++ b/mm/page_alloc.c -@@ -7557,7 +7557,7 @@ static void __init alloc_node_mem_map(st +@@ -7602,7 +7602,7 @@ static void __init alloc_node_mem_map(st if (pgdat == NODE_DATA(0)) { mem_map = NODE_DATA(0)->node_mem_map; if (page_to_pfn(mem_map) != pgdat->node_start_pfn) diff --git a/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch index d6e7f40f3b..976239c128 100644 --- a/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch +++ b/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -11,7 +11,7 @@ Signed-off-by: Gabor Juhos --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -1744,6 +1744,9 @@ void phy_detach(struct phy_device *phyde +@@ -1746,6 +1746,9 @@ void phy_detach(struct phy_device *phyde struct module *ndev_owner = NULL; struct mii_bus *bus; diff --git a/target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch b/target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch deleted file mode 100644 index 6fd450d7f9..0000000000 --- a/target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 9fec662b54fc956b776df15c704e996c61292850 Mon Sep 17 00:00:00 2001 -From: Alexander Couzens -Date: Sat, 13 Aug 2022 13:05:09 +0200 -Subject: [PATCH 02/10] net: mt7531: only do PLL once after the reset - -Move the PLL init of the switch out of the pad configuration of the port -6 (usally cpu port). - -Fix a unidirectional 100 mbit limitation on 1 gbit or 2.5 gbit links for -outbound traffic on port 5 or port 6. - -Signed-off-by: Alexander Couzens ---- - drivers/net/dsa/mt7530.c | 15 +++++++++------ - 1 file changed, 9 insertions(+), 6 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -506,14 +506,19 @@ static bool mt7531_dual_sgmii_supported( - static int - mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) - { -- struct mt7530_priv *priv = ds->priv; -+ return 0; -+} -+ -+static void -+mt7531_pll_setup(struct mt7530_priv *priv) -+{ - u32 top_sig; - u32 hwstrap; - u32 xtal; - u32 val; - - if (mt7531_dual_sgmii_supported(priv)) -- return 0; -+ return; - - val = mt7530_read(priv, MT7531_CREV); - top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); -@@ -592,8 +597,6 @@ mt7531_pad_setup(struct dsa_switch *ds, - val |= EN_COREPLL; - mt7530_write(priv, MT7531_PLLGP_EN, val); - usleep_range(25, 35); -- -- return 0; - } - - static void -@@ -2326,6 +2329,8 @@ mt7531_setup(struct dsa_switch *ds) - SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | - SYS_CTRL_REG_RST); - -+ mt7531_pll_setup(priv); -+ - if (mt7531_dual_sgmii_supported(priv)) { - priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; - -@@ -2882,8 +2887,6 @@ mt7531_cpu_port_config(struct dsa_switch - case 6: - interface = PHY_INTERFACE_MODE_2500BASEX; - -- mt7531_pad_setup(ds, interface); -- - priv->p6_interface = interface; - break; - default: diff --git a/target/linux/generic/pending-5.15/834-ledtrig-libata.patch b/target/linux/generic/pending-5.15/834-ledtrig-libata.patch index 3977b57d9f..58b837c084 100644 --- a/target/linux/generic/pending-5.15/834-ledtrig-libata.patch +++ b/target/linux/generic/pending-5.15/834-ledtrig-libata.patch @@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle /** * ata_build_rw_tf - Build ATA taskfile for given read/write request * @tf: Target ATA taskfile -@@ -4576,6 +4589,9 @@ struct ata_queued_cmd *ata_qc_new_init(s +@@ -4580,6 +4593,9 @@ struct ata_queued_cmd *ata_qc_new_init(s if (tag < 0) return NULL; } @@ -75,7 +75,7 @@ Signed-off-by: Daniel Golle qc = __ata_qc_from_tag(ap, tag); qc->tag = qc->hw_tag = tag; -@@ -5354,6 +5370,9 @@ struct ata_port *ata_port_alloc(struct a +@@ -5358,6 +5374,9 @@ struct ata_port *ata_port_alloc(struct a ap->stats.unhandled_irq = 1; ap->stats.idle_irq = 1; #endif @@ -85,7 +85,7 @@ Signed-off-by: Daniel Golle ata_sff_port_init(ap); return ap; -@@ -5389,6 +5408,12 @@ static void ata_host_release(struct kref +@@ -5393,6 +5412,12 @@ static void ata_host_release(struct kref kfree(ap->pmp_link); kfree(ap->slave_link); @@ -98,7 +98,7 @@ Signed-off-by: Daniel Golle kfree(ap); host->ports[i] = NULL; } -@@ -5795,7 +5820,23 @@ int ata_host_register(struct ata_host *h +@@ -5799,7 +5824,23 @@ int ata_host_register(struct ata_host *h host->ports[i]->print_id = atomic_inc_return(&ata_print_id); host->ports[i]->local_port_no = i + 1; } diff --git a/target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch b/target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch index e13c1ec223..582b98cc7d 100644 --- a/target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch +++ b/target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch @@ -31,7 +31,7 @@ Signed-off-by: Gabor Juhos --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h -@@ -528,6 +528,9 @@ struct skb_shared_info { +@@ -563,6 +563,9 @@ struct skb_shared_info { unsigned int gso_type; u32 tskey; diff --git a/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch b/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch index 9791652fd3..36d3e2738f 100644 --- a/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch +++ b/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch @@ -32,7 +32,7 @@ Signed-off-by: Gabor Juhos - rev-mii --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -293,6 +293,7 @@ static int phylink_parse_mode(struct phy +@@ -629,6 +629,7 @@ static int phylink_parse_mode(struct phy switch (pl->link_config.interface) { case PHY_INTERFACE_MODE_SGMII: @@ -50,7 +50,7 @@ Signed-off-by: Gabor Juhos PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TRGMII, PHY_INTERFACE_MODE_100BASEX, -@@ -209,6 +210,8 @@ static inline const char *phy_modes(phy_ +@@ -243,6 +244,8 @@ static inline const char *phy_modes(phy_ return "xlgmii"; case PHY_INTERFACE_MODE_MOCA: return "moca"; diff --git a/target/linux/oxnas/patches-5.15/999-libata-hacks.patch b/target/linux/oxnas/patches-5.15/999-libata-hacks.patch index 73700f5c61..3f0d5bb261 100644 --- a/target/linux/oxnas/patches-5.15/999-libata-hacks.patch +++ b/target/linux/oxnas/patches-5.15/999-libata-hacks.patch @@ -15,7 +15,7 @@ /* initialize internal qc */ qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL); -@@ -4583,6 +4591,9 @@ struct ata_queued_cmd *ata_qc_new_init(s +@@ -4587,6 +4595,9 @@ struct ata_queued_cmd *ata_qc_new_init(s if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) return NULL; @@ -25,7 +25,7 @@ /* libsas case */ if (ap->flags & ATA_FLAG_SAS_HOST) { tag = ata_sas_allocate_tag(ap); -@@ -4628,6 +4639,8 @@ void ata_qc_free(struct ata_queued_cmd * +@@ -4632,6 +4643,8 @@ void ata_qc_free(struct ata_queued_cmd * qc->tag = ATA_TAG_POISON; if (ap->flags & ATA_FLAG_SAS_HOST) ata_sas_free_tag(tag, ap); diff --git a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch index 94e99da015..192f5b48da 100644 --- a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch @@ -71,7 +71,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c break; --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c -@@ -1029,14 +1029,16 @@ struct phy_device *phy_find_first(struct +@@ -1031,14 +1031,16 @@ struct phy_device *phy_find_first(struct } EXPORT_SYMBOL(phy_find_first); From 579ea6b97079cf57949892969064dbee3203d1f4 Mon Sep 17 00:00:00 2001 From: Dirk Buchwalder Date: Thu, 6 Oct 2022 18:25:12 +0200 Subject: [PATCH 13/43] ipq40xx: ZTE MF289F: convert to DSA Convert ZTE MF289F device to DSA, re-order network ports to match the labels on the case and re-enable the device. Signed-off-by: Dirk Buchwalder Reviewed-by: Robert Marko Reviewed-by: Lech Perczak --- .../ipq40xx/base-files/etc/board.d/02_network | 8 ++--- .../arch/arm/boot/dts/qcom-ipq4019-mf289f.dts | 30 ++++++++++--------- target/linux/ipq40xx/image/generic.mk | 3 +- 3 files changed, 19 insertions(+), 22 deletions(-) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 163dcdcbc6..583b5c8fbd 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -33,7 +33,8 @@ ipq40xx_setup_interfaces() glinet,gl-b2200|\ luma,wrtq-329acn|\ mikrotik,cap-ac|\ - netgear,wac510) + netgear,wac510|\ + zte,mf289f) ucidef_set_interfaces_lan_wan "lan" "wan" ;; aruba,ap-303|\ @@ -59,11 +60,6 @@ ipq40xx_setup_interfaces() zte,mf286d) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" "wan" ;; - zte,mf289f) - ucidef_set_interfaces_lan_wan "eth0" "eth1" - ucidef_add_switch "switch0" \ - "0u@eth0" "0u@eth1" "2:lan:1" "5:lan:2" - ;; *) echo "Unsupported hardware. Network interfaces not initialized" ;; diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts index 2dac307990..ccb70dce87 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts @@ -71,10 +71,6 @@ }; soc { - ess-psgmii@98000 { - status = "okay"; - }; - tcsr@1949000 { compatible = "qcom,tcsr"; reg = <0x1949000 0x100>; @@ -100,14 +96,6 @@ reg = <0x1957000 0x100>; qcom,wifi_noc_memtype_m0_m2 = ; }; - - ess-switch@c000000 { - status = "okay"; - }; - - edma@c080000 { - status = "okay"; - }; }; }; @@ -319,17 +307,31 @@ status = "okay"; }; -&gmac0 { +&gmac { + status = "okay"; nvmem-cell-names = "mac-address"; nvmem-cells = <&macaddr_mac_0>; }; -&gmac1 { +&switch { + status = "okay"; +}; + +&swport2 { + status = "okay"; + + label = "wan"; + nvmem-cell-names = "mac-address"; nvmem-cells = <&macaddr_mac_0>; mac-address-increment = <1>; }; +&swport5 { + status = "okay"; + + label = "lan"; +}; &qpic_bam { status = "okay"; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 3c1cf67448..82c7464b87 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -1119,8 +1119,7 @@ define Device/zte_mf289f DEVICE_MODEL := MF289F DEVICE_PACKAGES += ipq-wifi-zte_mf289f ath10k-firmware-qca9984-ct endef -# Missing DSA Setup -#TARGET_DEVICES += zte_mf289f +TARGET_DEVICES += zte_mf289f define Device/zyxel_nbg6617 $(call Device/FitImageLzma) From 32e41ba18a41eac8cc782de78fd988b18fc44527 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Wed, 5 Oct 2022 23:35:21 +0900 Subject: [PATCH 14/43] ipq40xx: convert to DSA and enable Sony NCP-HG100/Cellular This patch converts networking on Sony NCP-HG100/Cellular to DSA and re-enables support for the device. Signed-off-by: INAGAKI Hiroshi --- .../ipq40xx/base-files/etc/board.d/01_leds | 4 +-- .../ipq40xx/base-files/etc/board.d/02_network | 1 + .../dts/qcom-ipq4019-ncp-hg100-cellular.dts | 34 +++++++++++-------- target/linux/ipq40xx/image/generic.mk | 3 +- 4 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/01_leds b/target/linux/ipq40xx/base-files/etc/board.d/01_leds index 74f31e778f..cd68ed32c0 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/01_leds +++ b/target/linux/ipq40xx/base-files/etc/board.d/01_leds @@ -95,8 +95,8 @@ qxwlan,e2600ac-c2) ucidef_set_led_wlan "wlan5g" "WLAN1" "green:wlan1" "phy1tpt" ;; sony,ncp-hg100-cellular) - ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" - ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" + ucidef_set_led_netdev "lan" "LAN" "green:lan" "lan" + ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan" ucidef_set_led_netdev "wwan" "WWAN" "green:wan-4" "wwan0" ;; zyxel,nbg6617 |\ diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 583b5c8fbd..1089a7f3f8 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -34,6 +34,7 @@ ipq40xx_setup_interfaces() luma,wrtq-329acn|\ mikrotik,cap-ac|\ netgear,wac510|\ + sony,ncp-hg100-cellular|\ zte,mf289f) ucidef_set_interfaces_lan_wan "lan" "wan" ;; diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ncp-hg100-cellular.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ncp-hg100-cellular.dts index f1ac5fd52f..ea27defea3 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ncp-hg100-cellular.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ncp-hg100-cellular.dts @@ -16,7 +16,7 @@ led-failsafe = &led_cloud_red; led-running = &led_cloud_green; led-upgrade = &led_cloud_green; - label-mac-device = &gmac0; + label-mac-device = &gmac; }; chosen { @@ -57,23 +57,9 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - ess-psgmii@98000 { - status = "okay"; - }; - dma@7984000 { status = "okay"; }; - - ess-switch@c000000 { - status = "okay"; - switch_mac_mode = <0x0>; /* mac mode for RGMII RMII */ - switch_initvlas = <0x0007c 0x54>; /* PORT0_STATUS */ - }; - - edma@c080000 { - status = "okay"; - }; }; keys-repeat { @@ -616,6 +602,24 @@ status = "okay"; }; +&gmac { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&swport4 { + status = "okay"; + label = "lan"; +}; + +&swport5 { + status = "okay"; + label = "wan"; +}; + &wifi0 { status = "okay"; qcom,ath10k-calibration-variant = "Sony-NCP-HG100-Cellular"; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 82c7464b87..68ce31c205 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -1048,8 +1048,7 @@ define Device/sony_ncp-hg100-cellular DEVICE_PACKAGES := e2fsprogs ipq-wifi-sony_ncp-hg100-cellular \ kmod-fs-ext4 uqmi endef -# Missing DSA Setup -#TARGET_DEVICES += sony_ncp-hg100-cellular +TARGET_DEVICES += sony_ncp-hg100-cellular define Device/teltonika_rutx10 $(call Device/FitImage) From 8ac69159f20ff65ba4e755f403fd5f82ecb02f76 Mon Sep 17 00:00:00 2001 From: Du Cai Date: Fri, 7 Oct 2022 23:08:56 +0800 Subject: [PATCH 15/43] ramips: use lzma-loader on JCG Q20 Fixes the LZMA uncompression issue on JCG Q20. Signed-off-by: Du Cai --- target/linux/ramips/image/mt7621.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 10add92a23..c4a033b8dc 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -1133,6 +1133,7 @@ TARGET_DEVICES += jcg_jhr-ac876m define Device/jcg_q20 $(Device/dsa-migration) + $(Device/uimage-lzma-loader) BLOCKSIZE := 128k PAGESIZE := 2048 UBINIZE_OPTS := -E 5 From ffd29a55c31697a69f4ebc59305cd95bda82aae3 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 26 Sep 2022 23:09:28 +0800 Subject: [PATCH 16/43] libnl-tiny: update to the latest version c42d890 build static library 28c44ca genl_family: explicitly null terminate strncpy destination buffer This fixes the compilation with gcc 12. Signed-off-by: Chukun Pan --- package/libs/libnl-tiny/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/libs/libnl-tiny/Makefile b/package/libs/libnl-tiny/Makefile index 48df6a4c8c..eee17d22bb 100644 --- a/package/libs/libnl-tiny/Makefile +++ b/package/libs/libnl-tiny/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/libnl-tiny.git -PKG_SOURCE_DATE:=2022-05-17 -PKG_SOURCE_VERSION:=b5b2ba09c4f1c8b3c21580aea7223edc2f5e92be -PKG_MIRROR_HASH:=b957d56aa8c2e7b55184111be69eb8dea734f1feba19e670a91f302459a48a78 +PKG_SOURCE_DATE:=2022-05-23 +PKG_SOURCE_VERSION:=28c44ca97cd546ef8168e7476472a0da022b3421 +PKG_MIRROR_HASH:=66151ac44d70510d9320b6c0e002a3c43c787c2d756d1eaaa3b84b12edd34af5 CMAKE_INSTALL:=1 PKG_LICENSE:=LGPL-2.1 From 2683cca5927844594f7835aa983e2690d1e343c6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 10 Oct 2022 17:48:49 +0200 Subject: [PATCH 17/43] lantiq: dts: vr9: Add missing properties to the CPU port on the switch The CPU port should define the phy-mode and and a PHY phandle or fixed-link to indicate how the CPU port is connected to the SoC's Ethernet controller. On xRX200 this is all internal connection, so use phy-mode = "internal" along with a fixed-link that matches the definition inside ð0. Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports"). when these properties are missing. Adding the properties before OpenWrt is updated to Linux 6.0 is harmless. Suggested-by: Martin Schiller Signed-off-by: Martin Blumenstingl --- .../linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi index 1089cdc80c..7fa2fac1ef 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi @@ -448,7 +448,13 @@ port@6 { reg = <0x6>; label = "cpu"; + phy-mode = "internal"; ethernet = <ð0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; }; From b3c81c9f21ea402e13de5580303178d7f32551a2 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 2 Oct 2022 23:16:08 +0800 Subject: [PATCH 18/43] uboot-mediatek: fixes defconfig typo for Linksys E8450 CONFIG_CMD_MTDPART does not exist, fix it. Fixes: ed50004 ("uboot-mediatek: add support for Linksys E8450") Signed-off-by: Chukun Pan --- package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch index cbcd098c3b..fb53bffff1 100644 --- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch +++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch @@ -58,7 +58,7 @@ +CONFIG_CMD_LINK_LOCAL=y +# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPART=y ++CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y From bb212092dfef41ace28f599324d45062a52746ab Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 3 Oct 2022 23:26:19 +0800 Subject: [PATCH 19/43] uboot-mediatek: fixes defconfig typo for UniFi 6 LR CONFIG_CMD_MTDPART does not exist, fix it. Fixes: e9ad412 ("uboot-mediatek: add build for Ubiquiti Networks UniFi 6 LR") Signed-off-by: Chukun Pan --- .../boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index 8279d250f3..cd6aaf8faa 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -64,7 +64,7 @@ +CONFIG_CMD_LINK_LOCAL=y +# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPART=y ++CONFIG_CMD_MTDPARTS=y +# CONFIG_CMD_PCI is not set +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y From 23e946d1aded1fc21125704c0819146d5772d72b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 8 Oct 2022 19:25:54 +0200 Subject: [PATCH 20/43] CI: kernel: generate ccache cache on kernel push To actually use ccache cache on kernel test from pr, the kernel workflow has to be run first from a push action. This will permit as a side effect to test merged commits and catch commit that may cause regression in kernel compilation even outside the github system. Signed-off-by: Christian Marangi --- .github/workflows/kernel.yml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernel.yml index 0ba8c27e2e..25d6d265eb 100644 --- a/.github/workflows/kernel.yml +++ b/.github/workflows/kernel.yml @@ -7,6 +7,12 @@ on: - 'include/kernel-*' - 'package/kernel/**' - 'target/linux/generic/**' + push: + paths: + - '.github/workflows/kernel.yml' + - 'include/kernel-*' + - 'package/kernel/**' + - 'target/linux/generic/**' permissions: contents: read From faa79f97b6040fca7f5a72b7b86c6f10d03b51f8 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:01:39 +0200 Subject: [PATCH 21/43] ipq806x: split files dir to 5.10 and 5.15 In preparation for a cleanup of 5.15 patches copy the files dir to 5.10 and 5.15 kernel version. Signed-off-by: Christian Marangi --- .../arm/boot/dts/qcom-ipq8062-wg2600hp3.dts | 0 .../arch/arm/boot/dts/qcom-ipq8062.dtsi | 0 .../boot/dts/qcom-ipq8064-ad7200-c2600.dtsi | 0 .../arch/arm/boot/dts/qcom-ipq8064-ad7200.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-c2600.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-db149.dts | 0 .../arm/boot/dts/qcom-ipq8064-ea7500-v1.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-ea8500.dts | 0 .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 0 .../arch/arm/boot/dts/qcom-ipq8064-g10.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 0 .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 0 .../arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 0 .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 0 .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 0 .../arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 0 .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 0 .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 0 .../arm/boot/dts/qcom-ipq8065-nighthawk.dtsi | 0 .../arch/arm/boot/dts/qcom-ipq8065-r7800.dts | 0 .../boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 0 .../arm/boot/dts/qcom-ipq8065-tr4400-v2.dts | 0 .../arch/arm/boot/dts/qcom-ipq8065-xr500.dts | 0 .../arch/arm/boot/dts/qcom-ipq8065.dtsi | 0 .../boot/dts/qcom-ipq8068-cryptid-common.dtsi | 0 .../arm/boot/dts/qcom-ipq8068-ecw5410.dts | 0 .../arch/arm/boot/dts/qcom-ipq8068-mr42.dts | 0 .../arch/arm/boot/dts/qcom-ipq8068-mr52.dts | 0 .../arm/boot/dts/qcom-ipq8062-wg2600hp3.dts | 479 ++++++++++++++++ .../arch/arm/boot/dts/qcom-ipq8062.dtsi | 98 ++++ .../boot/dts/qcom-ipq8064-ad7200-c2600.dtsi | 375 +++++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-ad7200.dts | 135 +++++ .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 121 ++++ .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 159 ++++++ .../arch/arm/boot/dts/qcom-ipq8064-c2600.dts | 119 ++++ .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 384 +++++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-db149.dts | 163 ++++++ .../arm/boot/dts/qcom-ipq8064-ea7500-v1.dts | 91 +++ .../arch/arm/boot/dts/qcom-ipq8064-ea8500.dts | 128 +++++ .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 207 +++++++ .../arch/arm/boot/dts/qcom-ipq8064-g10.dts | 279 ++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 314 +++++++++++ .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 374 +++++++++++++ .../arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts | 317 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++ .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 408 ++++++++++++++ .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 447 +++++++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 465 ++++++++++++++++ .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 526 ++++++++++++++++++ .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 316 +++++++++++ .../arm/boot/dts/qcom-ipq8065-nighthawk.dtsi | 453 +++++++++++++++ .../arch/arm/boot/dts/qcom-ipq8065-r7800.dts | 48 ++ .../boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 403 ++++++++++++++ .../arm/boot/dts/qcom-ipq8065-tr4400-v2.dts | 425 ++++++++++++++ .../arch/arm/boot/dts/qcom-ipq8065-xr500.dts | 50 ++ .../arch/arm/boot/dts/qcom-ipq8065.dtsi | 167 ++++++ .../boot/dts/qcom-ipq8068-cryptid-common.dtsi | 239 ++++++++ .../arm/boot/dts/qcom-ipq8068-ecw5410.dts | 332 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8068-mr42.dts | 204 +++++++ .../arch/arm/boot/dts/qcom-ipq8068-mr52.dts | 230 ++++++++ 64 files changed, 8525 insertions(+) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8062.dtsi (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-ap148.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-ap161.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-c2600.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-d7800.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-db149.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-g10.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-r7500.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8065-r7800.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8065-xr500.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8065.dtsi (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8068-mr42.dts (100%) rename target/linux/ipq806x/{files => files-5.10}/arch/arm/boot/dts/qcom-ipq8068-mr52.dts (100%) create mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts create mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi create mode 100644 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a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts similarity index 100% rename from target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts rename to target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-xr500.dts similarity index 100% rename from target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts rename to target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-xr500.dts diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065.dtsi similarity index 100% rename from target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi rename to 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target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts rename to target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr42.dts diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr52.dts similarity index 100% rename from target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts rename to target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr52.dts diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts new file mode 100644 index 0000000000..c1c21856ca --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8062.dtsi" +#include + +/delete-node/ &nand_pins; + +/ { + model = "NEC Platforms Aterm WG2600HP3"; + compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064"; + + memory { + device_type = "memory"; + reg = <0x42000000 0x1e000000>; + }; + + aliases { + label-mac-device = &gmac2; + + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_red; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + mode0 { + label = "mode0"; + gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + mode1 { + label = "mode1"; + gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + label = "green:power"; + gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; + }; + + led_power_red: power_red { + label = "red:power"; + gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>; + }; + + active_green { + label = "green:active"; + gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>; + }; + + active_red { + label = "red:active"; + gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + + wlan2g_red { + label = "red:wlan2g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + wlan5g_red { + label = "red:wlan5g"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; + }; + + tv_green { + label = "green:tv"; + gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>; + }; + + tv_red { + label = "red:tv"; + gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>; + }; + + converter_green { + label = "green:converter"; + gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>; + }; + + converter_red { + label = "red:converter"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + pinctrl-0 = <&akro_pins>; + pinctrl-names = "default"; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + buttons_pins: buttons_pins { + mux { + pins = "gpio22", "gpio24", "gpio40", + "gpio41"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio14", "gpio15", "gpio35", + "gpio36", "gpio38", "gpio42", + "gpio43", "gpio46", "gpio55", + "gpio56", "gpio57", "gpio58"; + function = "gpio"; + bias-pull-down; + }; + + akro2 { + pins = "gpio15", "gpio35", "gpio38", + "gpio42", "gpio43", "gpio46", + "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <2>; + }; + + akro4 { + pins = "gpio14", "gpio36"; + drive-strength = <4>; + }; + }; + + /* + * Stock firmware has the following settings, so let's do the same. + * I don't sure why these are required. + */ + akro_pins: akro_pinmux { + akro { + pins = "gpio17", "gpio26", "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset { + pins = "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + gmac0_rgmii { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0000000 0x0020000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x0020000 0x0020000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x0040000 0x0040000>; + read-only; + }; + + partition@80000 { + label = "SBL3"; + reg = <0x0080000 0x0080000>; + read-only; + }; + + partition@100000 { + label = "DDRCONFIG"; + reg = <0x0100000 0x0010000>; + read-only; + }; + + partition@110000 { + label = "SSD"; + reg = <0x0110000 0x0010000>; + read-only; + }; + + partition@120000 { + label = "TZ"; + reg = <0x0120000 0x0080000>; + read-only; + }; + + partition@1a0000 { + label = "RPM"; + reg = <0x01a0000 0x0080000>; + read-only; + }; + + partition@220000 { + label = "APPSBL"; + reg = <0x0220000 0x0080000>; + read-only; + }; + + partition@2a0000 { + label = "APPSBLENV"; + reg = <0x02a0000 0x0010000>; + read-only; + }; + + factory: partition@2b0000 { + label = "PRODUCTDATA"; + reg = <0x02b0000 0x0030000>; + read-only; + }; + + partition@2e0000 { + label = "ART"; + reg = <0x02e0000 0x0040000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + partition@320000 { + label = "TP"; + reg = <0x0320000 0x0040000>; + read-only; + }; + + partition@360000 { + label = "TINY"; + reg = <0x0360000 0x0500000>; + read-only; + }; + + partition@860000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x0860000 0x17a0000>; + }; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; + + nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + force_gen1 = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + ieee80211-freq-limit = <2400000 2483000>; + qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; + + nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x04 0x80080080 /* PAD0_MODE */ + 0x0c 0x06000000 /* PAD6_MODE */ + 0x10 0x002613a0 /* PWS_REG */ + 0x50 0xcc36cc36 /* LED_CTRL0 */ + 0x54 0xca36ca36 /* LED_CTRL1 */ + 0x58 0xc936c936 /* LED_CTRL2 */ + 0x5c 0x03ffff00 /* LED_CTRL3 */ + 0x7c 0x0000004e /* PORT0_STATUS */ + 0x94 0x0000004e /* PORT6_STATUS */ + 0xe0 0xc74164de /* SGMII_CTRL */ + 0xe4 0x0006a545 /* MAC_PWR_SEL */ + >; + }; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + mdiobus = <&mdio0>; + nvmem-cells = <&macaddr_factory_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + mdiobus = <&mdio0>; + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_factory_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_PRODUCTDATA_c: macaddr@c { + reg = <0xc 0x6>; + }; + + macaddr_PRODUCTDATA_12: macaddr@12 { + reg = <0x12 0x6>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi new file mode 100644 index 0000000000..29226ca275 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm IPQ8062"; + compatible = "qcom,ipq8062", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&opp_table0 { + /delete-node/opp-1200000000; + /delete-node/opp-1400000000; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>; + opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>; + opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>; + opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>; + opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>; + opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>; + }; +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&smb208_s2a { + regulator-max-microvolt = <1150000>; +}; + +&smb208_s2b { + regulator-max-microvolt = <1150000>; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi new file mode 100644 index 0000000000..115c6d43d2 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + label-mac-device = &gmac2; + }; +}; + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb0_pwr_en_pin: usb0_pwr_en_pin { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + output-high; + }; + }; + + usb1_pwr_en_pin: usb1_pwr_en_pin { + mux { + pins = "gpio23"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + output-high; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "SBL3"; + reg = <0x60000 0x30000>; + read-only; + }; + + partition@90000 { + label = "DDRCONFIG"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "SSD"; + reg = <0xa0000 0x10000>; + read-only; + }; + + partition@b0000 { + label = "TZ"; + reg = <0xb0000 0x30000>; + read-only; + }; + + partition@e0000 { + label = "RPM"; + reg = <0xe0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "fs-uboot"; + reg = <0x100000 0x70000>; + read-only; + }; + + partition@170000 { + label = "uboot-env"; + reg = <0x170000 0x40000>; + read-only; + }; + + partition@1b0000 { + label = "radio"; + reg = <0x1b0000 0x40000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_radio_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_radio_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + partition@1f0000 { + label = "os-image"; + reg = <0x1f0000 0x400000>; + }; + + partition@5f0000 { + label = "rootfs"; + reg = <0x5f0000 0x1900000>; + }; + + defaultmac: partition@1ef0000 { + label = "default-mac"; + reg = <0x1ef0000 0x00200>; + read-only; + }; + + partition@1ef0200 { + label = "pin"; + reg = <0x1ef0200 0x00200>; + read-only; + }; + + partition@1ef0400 { + label = "product-info"; + reg = <0x1ef0400 0x0fc00>; + read-only; + }; + + partition@1f00000 { + label = "partition-table"; + reg = <0x1f00000 0x10000>; + read-only; + }; + + partition@1f10000 { + label = "soft-version"; + reg = <0x1f10000 0x10000>; + read-only; + }; + + partition@1f20000 { + label = "support-list"; + reg = <0x1f20000 0x10000>; + read-only; + }; + + partition@1f30000 { + label = "profile"; + reg = <0x1f30000 0x10000>; + read-only; + }; + + partition@1f40000 { + label = "default-config"; + reg = <0x1f40000 0x10000>; + read-only; + }; + + partition@1f50000 { + label = "user-config"; + reg = <0x1f50000 0x40000>; + read-only; + }; + + partition@1f90000 { + label = "qos-db"; + reg = <0x1f90000 0x40000>; + read-only; + }; + + partition@1fd0000 { + label = "usb-config"; + reg = <0x1fd0000 0x10000>; + read-only; + }; + + partition@1fe0000 { + label = "log"; + reg = <0x1fe0000 0x20000>; + read-only; + }; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pin>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pin>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(-1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_defaultmac_8>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_defaultmac_8>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&defaultmac { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_defaultmac_8: macaddr@8 { + reg = <0x8 0x6>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts new file mode 100644 index 0000000000..6cb21fc4f3 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-ad7200-c2600.dtsi" + +/ { + model = "TP-Link Talon AD7200"; + compatible = "tplink,ad7200", "qcom,ipq8064"; + + aliases { + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + led_enable { + label = "led-enable"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + lan { + label = "blue:lan"; + gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>; + }; + + usb1 { + label = "blue:usb1"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + wlan5g { + label = "blue:wlan5g"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + + usb3 { + label = "blue:usb3"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan2g { + label = "blue:wlan2g"; + gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; + }; + + wan_orange { + label = "orange:wan"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + wan_blue { + label = "blue:wan"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "blue:wps"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; + + wlan60g { + label = "blue:wlan60g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + led_status: status { + label = "blue:status"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio53", "gpio54", "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26", + "gpio33", "gpio55", "gpio56", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie2 { + status = "okay"; + max-link-speed = <1>; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts new file mode 100644 index 0000000000..70034a50e3 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -0,0 +1,121 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&flash { + partitions { + compatible = "qcom,smem-part"; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts new file mode 100644 index 0000000000..c771a627ca --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts @@ -0,0 +1,159 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/AP161"; + compatible = "qcom,ipq8064-ap161", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; +}; + +&qcom_pinmux { + rgmii2_pins: rgmii2_pins { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62", + "gpio2", "gpio66"; + }; + }; +}; + +&flash { + partitions { + compatible = "qcom,smem-part"; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&pcie2 { + status = "okay"; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x20080 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + qca,phy-rgmii-en; + qca,txclk-delay-en; + qca,rxclk-delay-en; + }; + + phy3: ethernet-phy@3 { + device_type = "ethernet-phy"; + reg = <3>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts new file mode 100644 index 0000000000..cef1aba344 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-c2600.dts @@ -0,0 +1,119 @@ +#include "qcom-ipq8064-ad7200-c2600.dtsi" + +/ { + model = "TP-Link Archer C2600"; + compatible = "tplink,c2600", "qcom,ipq8064"; + + aliases { + led-boot = &power; + led-failsafe = &general; + led-running = &power; + led-upgrade = &general; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ledswitch { + label = "ledswitch"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + lan { + label = "white:lan"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; + }; + + usb4 { + label = "white:usb_4"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb_2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + general: general { + label = "white:general"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio16", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33", + "gpio53", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts new file mode 100644 index 0000000000..23487c9ca0 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts @@ -0,0 +1,384 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "Netgear Nighthawk X4 D7800"; + compatible = "netgear,d7800", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + power_amber: power_amber { + label = "amber:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power_white: power_white { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(2)>; + }; + }; +}; + +&pcie2 { + status = "okay"; + reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + artbak: art@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + kernel@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + + ubi@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + reserve@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts new file mode 100644 index 0000000000..8e8d942fbd --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts @@ -0,0 +1,163 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/DB149"; + compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi2_serial; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&qcom_pinmux { + rgmii0_pins: rgmii0_pins { + mux { + pins = "gpio2", "gpio66"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&gsbi2 { + qcom,mode = ; + status = "okay"; + + gsbi2_serial: serial@12490000 { + status = "okay"; + }; +}; + +&gsbi4 { + status = "disabled"; +}; + +&gsbi4_serial { + status = "disabled"; +}; + +&flash { + m25p,fast-read; + + partition@0 { + label = "lowlevel_init"; + reg = <0x0 0x1b0000>; + }; + + partition@1 { + label = "u-boot"; + reg = <0x1b0000 0x80000>; + }; + + partition@2 { + label = "u-boot-env"; + reg = <0x230000 0x40000>; + }; + + partition@3 { + label = "caldata"; + reg = <0x270000 0x40000>; + }; + + partition@4 { + label = "firmware"; + reg = <0x2b0000 0x1d50000>; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + }; + + phy7: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + phy-handle = <&phy4>; + + pinctrl-0 = <&rgmii0_pins>; + pinctrl-names = "default"; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + phy-handle = <&phy6>; +}; + +&gmac3 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <3>; + phy-handle = <&phy7>; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts new file mode 100644 index 0000000000..9d82d52d27 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-eax500.dtsi" + +/ { + model = "Linksys EA7500 V1 WiFi Router"; + compatible = "linksys,ea7500-v1", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0xe000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + chosen { + /* look for root deviceblock nbr in this bootarg */ + find-rootblock = "ubi.mtd="; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "white:power"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio65", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&partitions { + partition@5f80000 { + label = "sysdiag"; + reg = <0x5f80000 0x100000>; + }; + + partition@6080000 { + label = "syscfg"; + reg = <0x6080000 0x1f80000>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts new file mode 100644 index 0000000000..1c6a4bdacd --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts @@ -0,0 +1,128 @@ +#include "qcom-ipq8064-eax500.dtsi" + +/ { + model = "Linksys EA8500 WiFi Router"; + compatible = "linksys,ea8500", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + wps { + label = "green:wps"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + led_power: power { + label = "white:power"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + wifi { + label = "green:wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio65", "gpio67", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio53", "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&partitions { + partition@5f80000 { + label = "syscfg"; + reg = <0x5f80000 0x2080000>; + }; +}; + +&mdio0 { + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <1>; + qcom,rgmii_delay = <0>; + qcom,emulation = <0>; +}; + +/* LAN */ +&gmac2 { + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,emulation = <0>; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi new file mode 100644 index 0000000000..e74d2dcdbd --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + chosen { + bootargs = "console=ttyMSM0,115200n8"; + /* append to bootargs adding the root deviceblock nbr from bootloader */ + append-rootblock = "ubi.mtd="; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + max-link-speed = <1>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x0c80000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + partition@180000 { + label = "SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + partition@2c0000 { + label = "SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + partition@540000 { + label = "DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + partition@660000 { + label = "SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + partition@780000 { + label = "TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + partition@a00000 { + label = "RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + art: partition@c80000 { + label = "art"; + reg = <0x0c80000 0x0140000>; + read-only; + }; + + partition@dc0000 { + label = "APPSBL"; + reg = <0x0dc0000 0x0100000>; + read-only; + }; + + partition@ec0000 { + label = "u_env"; + reg = <0x0ec0000 0x0040000>; + }; + + partition@f00000 { + label = "s_env"; + reg = <0x0f00000 0x0040000>; + }; + + partition@f40000 { + label = "devinfo"; + reg = <0x0f40000 0x0040000>; + }; + + partition@f80000 { + label = "kernel1"; + reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */ + }; + + partition@1380000 { + label = "rootfs1"; + reg = <0x1380000 0x2400000>; + }; + + partition@3780000 { + label = "kernel2"; + reg = <0x3780000 0x2800000>; + }; + + partition@3b80000 { + label = "rootfs2"; + reg = <0x3b80000 0x2400000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x00010 0x2613a0 /* PWS_REG */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts new file mode 100644 index 0000000000..735ccb2d53 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064-v2.0.dtsi" + +#include +#include + +/ { + compatible = "asrock,g10", "qcom,ipq8064"; + model = "ASRock G10"; + + aliases { + ethernet0 = &gmac1; + ethernet1 = &gmac0; + + led-boot = &led_status_blue; + led-failsafe = &led_status_amber; + led-running = &led_status_blue; + led-upgrade = &led_status_amber; + }; + + chosen { + bootargs-override = "console=ttyMSM0,115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + /* + * this is a bit misleading. Because there are about seven + * multicolor LEDs connected all wired together in parallel. + */ + + status_yellow { + label = "yellow:status"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + led_status_amber: status_amber { + label = "amber:status"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: status_blue { + label = "blue:status"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + /* + * LED is declared in vendors boardfile but it's not + * working and the manual doesn't mention anything + * about the LED being white. + + status_white { + label = "white:status"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + */ + }; + + i2c-gpio { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */ + <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <5>; + i2c-gpio,scl-output-only; + + mcu@50 { + reg = <0x50>; + compatible = "sonix,sn8f25e21"; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + ir-remote { + label = "ir-remote"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps5g { + label = "wps5g"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps2g { + label = "wps2g"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1200000>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi5g: wifi@1,0 { + reg = <0x00010000 0 0 0 0>; + compatible = "qcom,ath10k"; + qcom,ath10k-calibration-variant = "ASRock-G10"; + }; + }; +}; + +&pcie1 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi2g: wifi@1,0 { + reg = <0x00010000 0 0 0 0>; + compatible = "qcom,ath10k"; + qcom,ath10k-calibration-variant = "ASRock-G10"; + }; + }; +}; + +&qcom_pinmux { + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio15", "gpio16", "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; +}; + +&rpm { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&tcsr { + qcom,usb-ctrl-select = ; +}; + +/delete-node/ &pcie2_pins; +/delete-node/ &pcie2; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts new file mode 100644 index 0000000000..0970eaf0ec --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts @@ -0,0 +1,314 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +#include +#include + +/ { + model = "Netgear Nighthawk X4 R7500"; + compatible = "netgear,r7500", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0xe000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + power_amber: power_amber { + label = "amber:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power_white: power_white { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + status = "disabled"; + + spi@1a280000 { + status = "disabled"; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + }; + + kernel@1340000 { + label = "kernel"; + reg = <0x1340000 0x0400000>; + }; + + ubi@1740000 { + label = "ubi"; + reg = <0x1740000 0x1600000>; + }; + + netgear@2d40000 { + label = "netgear"; + reg = <0x2d40000 0x0c00000>; + read-only; + }; + + reserve@3940000 { + label = "reserve"; + reg = <0x3940000 0x46c0000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&tcsr { + qcom,usb-ctrl-select = ; + compatible = "qcom,tcsr"; +}; + +&adm_dma { + status = "okay"; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts new file mode 100644 index 0000000000..30b56bb9d6 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts @@ -0,0 +1,374 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "Netgear Nighthawk X4 R7500v2"; + compatible = "netgear,r7500v2", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "amber:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb3 { + label = "amber:usb3"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + status { + label = "amber:status"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + internet { + label = "white:internet"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan { + label = "white:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(2)>; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + artbak: art@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + kernel@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + + ubi@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + reserve@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts new file mode 100644 index 0000000000..b3e06db86d --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include +#include + +/ { + model = "Ubiquiti UniFi AC HD"; + compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064"; + + aliases { + label-mac-device = &gmac2; + led-boot = &led_dome_white; + led-failsafe = &led_dome_white; + led-running = &led_dome_blue; + led-upgrade = &led_dome_blue; + mdio-gpio0 = &mdio0; + ethernet0 = &gmac2; + ethernet1 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_dome_blue: dome_blue { + label = "blue:dome"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + led_dome_white: dome_white { + label = "white:dome"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio9", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; +}; + +&CPU_SPC { + status = "disabled"; +}; + +&gsbi5 { + status = "okay"; + + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + cs-gpios = <&qcom_pinmux 20 0>; + + flash@0 { + compatible = "mx25u25635f", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "SBL2"; + reg = <0x30000 0x20000>; + read-only; + }; + + partition@50000 { + label = "SBL3"; + reg = <0x50000 0x30000>; + read-only; + }; + + partition@80000 { + label = "DDRCONFIG"; + reg = <0x80000 0x10000>; + read-only; + }; + + partition@90000 { + label = "SSD"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "TZ"; + reg = <0xa0000 0x30000>; + read-only; + }; + + partition@d0000 { + label = "RPM"; + reg = <0xd0000 0x20000>; + read-only; + }; + + partition@f0000 { + label = "APPSBL"; + reg = <0xf0000 0xc0000>; + read-only; + }; + + partition@1b0000 { + label = "APPSBLENV"; + reg = <0x1b0000 0x10000>; + read-only; + }; + + eeprom: partition@1c0000 { + label = "EEPROM"; + reg = <0x1c0000 0x10000>; + read-only; + }; + + partition@1d0000 { + label = "bootselect"; + reg = <0x1d0000 0x10000>; + }; + + partition@1e0000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x1e0000 0xe70000>; + }; + + partition@1050000 { + label = "kernel1"; + reg = <0x1050000 0xe70000>; + read-only; + }; + + partition@1ec0000 { + label = "debug"; + reg = <0x1ec0000 0x100000>; + read-only; + }; + + partition@1fc0000 { + label = "cfg"; + reg = <0x1fc0000 0x40000>; + read-only; + }; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + nand-ecc-strength = <4>; + nand-bus-width = <8>; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + }; +}; + +&gmac1 { + status = "okay"; + + mdiobus = <&mdio0>; + phy-handle = <&phy5>; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + status = "okay"; + + mdiobus = <&mdio0>; + phy-handle = <&phy4>; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&tcsr { + status = "okay"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi new file mode 100644 index 0000000000..b9ee86a891 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi @@ -0,0 +1,69 @@ +#include "qcom-ipq8064.dtsi" + +/ { + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&CPU_SPC { + status = "okay"; +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&sata { + ports-implemented = <0x1>; +}; + +&ss_phy_0 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&ss_phy_1 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts new file mode 100644 index 0000000000..27d9fc84b3 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts @@ -0,0 +1,408 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "TP-Link Archer VR2600v"; + compatible = "tplink,vr2600v", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power; + led-failsafe = &general; + led-running = &power; + led-upgrade = &general; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + dect { + label = "dect"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ledswitch { + label = "ledswitch"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + dsl { + label = "white:dsl"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb { + label = "white:usb"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + lan { + label = "white:lan"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wlan2g { + label = "white:wlan2g"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan5g { + label = "white:wlan5g"; + gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + phone { + label = "white:phone"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + wan { + label = "white:wan"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + general: general { + label = "white:general"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", + "gpio26", "gpio53", "gpio56", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x40000 0x40000>; + read-only; + }; + + partition@80000 { + label = "SBL3"; + reg = <0x80000 0x80000>; + read-only; + }; + + partition@100000 { + label = "DDRCONFIG"; + reg = <0x100000 0x10000>; + read-only; + }; + + partition@110000 { + label = "SSD"; + reg = <0x110000 0x10000>; + read-only; + }; + + partition@120000 { + label = "TZ"; + reg = <0x120000 0x80000>; + read-only; + }; + + partition@1a0000 { + label = "RPM"; + reg = <0x1a0000 0x80000>; + read-only; + }; + + partition@220000 { + label = "APPSBL"; + reg = <0x220000 0x80000>; + read-only; + }; + + partition@2a0000 { + label = "APPSBLENV"; + reg = <0x2a0000 0x40000>; + read-only; + }; + + partition@2e0000 { + label = "OLDART"; + reg = <0x2e0000 0x40000>; + read-only; + }; + + partition@320000 { + label = "firmware"; + reg = <0x320000 0xc60000>; + compatible = "openwrt,uimage"; + openwrt,offset = <512>; /* account for pad-extra 512 */ + }; + + /* hole 0xf80000 - 0xfaf100 */ + + partition@faf100 { + label = "default-mac"; + reg = <0xfaf100 0x00200>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_defaultmac_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; + + partition@fc0000 { + label = "ART"; + reg = <0xfc0000 0x40000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(-1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_defaultmac_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_defaultmac_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts new file mode 100644 index 0000000000..998dad55c5 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts @@ -0,0 +1,447 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "NEC Aterm WG2600HP"; + compatible = "nec,wg2600hp", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + bridge { + label = "bridge"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + converter { + label = "converter"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + converter_green { + label = "green:converter"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; + }; + + power_red: power_red { + label = "red:power"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + active_green { + label = "green:active"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + active_red { + label = "red:active"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + power_green: power_green { + label = "green:power"; + gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; + }; + + converter_red { + label = "red:converter"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_red { + label = "red:wlan2g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_red { + label = "red:wlan5g"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; + }; + + tv_green { + label = "green:tv"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + tv_red { + label = "red:tv"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&CPU_SPC { + status = "disabled"; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x06000000 /* PAD0_MODE */ + 0x0000c 0x00080080 /* PAD6_MODE */ + 0x000e4 0x0006a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x0000004e /* PORT0_STATUS */ + 0x00094 0x0000004e /* PORT6_STATUS */ + >; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_PRODUCTDATA_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_PRODUCTDATA_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi5 { + status = "okay"; + + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + MIBIB@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + SBL2@40000 { + label = "SBL2"; + reg = <0x40000 0x40000>; + read-only; + }; + + SBL3@80000 { + label = "SBL3"; + reg = <0x80000 0x80000>; + read-only; + }; + + DDRCONFIG@100000 { + label = "DDRCONFIG"; + reg = <0x100000 0x10000>; + read-only; + }; + + SSD@110000 { + label = "SSD"; + reg = <0x110000 0x10000>; + read-only; + }; + + TZ@120000 { + label = "TZ"; + reg = <0x120000 0x80000>; + read-only; + }; + + RPM@1a0000 { + label = "RPM"; + reg = <0x1a0000 0x80000>; + read-only; + }; + + APPSBL@220000 { + label = "APPSBL"; + reg = <0x220000 0x80000>; + read-only; + }; + + APPSBLENV@2a0000 { + label = "APPSBLENV"; + reg = <0x2a0000 0x10000>; + }; + + PRODUCTDATA: PRODUCTDATA@2b0000 { + label = "PRODUCTDATA"; + reg = <0x2b0000 0x30000>; + read-only; + }; + + ART@2e0000 { + label = "ART"; + reg = <0x2e0000 0x40000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + TP@320000 { + label = "TP"; + reg = <0x320000 0x40000>; + read-only; + }; + + TINY@360000 { + label = "TINY"; + reg = <0x360000 0x500000>; + read-only; + }; + + firmware@860000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x860000 0x17a0000>; + }; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio16", "gpio54", "gpio24", "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", + "gpio15", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb_pwr_en_pins: usb_pwr_en_pins { + mux { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-high; + }; + }; +}; + +&PRODUCTDATA { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_PRODUCTDATA_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_PRODUCTDATA_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_PRODUCTDATA_c: macaddr@c { + reg = <0xc 0x6>; + }; + + macaddr_PRODUCTDATA_12: macaddr@12 { + reg = <0x12 0x6>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts new file mode 100644 index 0000000000..d7f3a7f881 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2017 Christian Mehlis + * Copyright (C) 2018 Mathias Kresin + * All rights reserved. + */ + +#include "qcom-ipq8064-v1.0.dtsi" + +#include +#include + +/ { + compatible = "compex,wpq864", "qcom,ipq8064"; + model = "Compex WPQ864"; + + aliases { + mdio-gpio0 = &mdio0; + ethernet0 = &gmac1; + ethernet1 = &gmac0; + + led-boot = &led_pass; + led-failsafe = &led_fail; + led-running = &led_pass; + led-upgrade = &led_pass; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + rss4 { + label = "green:rss4"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + rss3 { + label = "green:rss3"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rss2 { + label = "orange:rss2"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; + }; + + rss1 { + label = "red:rss1"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + led_pass: pass { + label = "green:pass"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + led_fail: fail { + label = "green:fail"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + usb { + label = "green:usb"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb-pcie { + label = "green:usb-pcie"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + beeper { + compatible = "gpio-beeper"; + + pinctrl-0 = <&beeper_pins>; + pinctrl-names = "default"; + + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; +}; + +&rpm { + pinctrl-0 = <&rpm_pins>; + pinctrl-names = "default"; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + mt29f2g08abbeah4@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + MIBIB@40000 { + label = "MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + SBL2@180000 { + label = "SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + SBL3@2c0000 { + label = "SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + DDRCONFIG@540000 { + label = "DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + SSD@660000 { + label = "SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + TZ@780000 { + label = "TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + RPM@a00000 { + label = "RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + + ART@1200000 { + label = "ART"; + reg = <0x1200000 0x0140000>; + }; + + ubi@1340000 { + label = "ubi"; + reg = <0x1340000 0x4000000>; + }; + + BOOTCONFIG@5340000 { + label = "BOOTCONFIG"; + reg = <0x5340000 0x0060000>; + }; + + SBL2-1@53a0000- { + label = "SBL2_1"; + reg = <0x53a0000 0x0140000>; + read-only; + }; + + SBL3-1@54e0000 { + label = "SBL3_1"; + reg = <0x54e0000 0x0280000>; + read-only; + }; + + DDRCONFIG-1@5760000 { + label = "DDRCONFIG_1"; + reg = <0x5760000 0x0120000>; + read-only; + }; + + SSD-1@5880000 { + label = "SSD_1"; + reg = <0x5880000 0x0120000>; + read-only; + }; + + TZ-1@59a0000 { + label = "TZ_1"; + reg = <0x59a0000 0x0280000>; + read-only; + }; + + RPM-1@5c20000 { + label = "RPM_1"; + reg = <0x5c20000 0x0280000>; + read-only; + }; + + BOOTCONFIG1@5ea0000 { + label = "BOOTCONFIG1"; + reg = <0x5ea0000 0x0060000>; + }; + + APPSBL-1@5f00000 { + label = "APPSBL_1"; + reg = <0x5f00000 0x0500000>; + read-only; + }; + + ubi-1@6400000 { + label = "ubi_1"; + reg = <0x6400000 0x4000000>; + }; + + unused@a400000 { + label = "unused"; + reg = <0xa400000 0x5c00000>; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&flash { + compatible = "jedec,spi-nor"; +}; + +&sata_phy { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +&ss_phy_0 { /* USB3 port 0 SS phy */ + status = "okay"; + + rx_eq = <2>; + tx_deamp_3_5db = <32>; + mpll = <160>; +}; + +&ss_phy_1 { /* USB3 port 1 SS phy */ + status = "okay"; + + rx_eq = <2>; + tx_deamp_3_5db = <32>; + mpll = <160>; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; +}; + +&qcom_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinctrl0 { + pcie0_pcie2_perst { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + beeper_pins: beeper_pins { + mux { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rpm_pins: rpm_pins { + mux { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&tcsr { + qcom,usb-ctrl-select = ; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts new file mode 100644 index 0000000000..04a2261929 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "Buffalo WXR-2533DHP"; + compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064"; + + memory@42000000 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &power; + led-failsafe = &diag; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + /* use "ubi_rootfs" volume in "ubi" partition as rootfs */ + bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb { + label = "green:usb"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port0 &hub_port1>; + }; + + guestport { + label = "green:guestport"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + diag: diag { + label = "orange:diag"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + internet_orange { + label = "orange:internet"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + internet_white { + label = "white:internet"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wireless_orange { + label = "orange:wireless"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wireless_white { + label = "white:wireless"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + router_orange { + label = "orange:router"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; + }; + + router_white { + label = "white:router"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + power { + label = "power"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + eject { + label = "eject"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + guest { + label = "guest"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ap { + label = "ap"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + router { + label = "router"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + auto { + label = "auto"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + cs@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubi@0 { + label = "ubi"; + reg = <0x0000000 0x4000000>; + }; + + rootfs_1@4000000 { + label = "rootfs_1"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x07600000 /* PAD0_MODE */ + 0x00008 0x01000000 /* PAD5_MODE */ + 0x0000c 0x00000080 /* PAD6_MODE */ + 0x00050 0xcc35cc35 /* LED_CTRL0 */ + 0x00054 0xca35ca35 /* LED_CTRL1 */ + 0x00058 0xc935c935 /* LED_CTRL2 */ + 0x0005c 0x03ffff00 /* LED_CTRL3 */ + 0x000e4 0x0006a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x0000007e /* PORT0_STATUS */ + 0x00094 0x0000007e /* PORT6_STATUS */ + >; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_ART_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_ART_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0 0x10000>; + read-only; + }; + + MIBIB@10000 { + label = "MIBIB"; + reg = <0x10000 0x20000>; + read-only; + }; + + SBL2@30000 { + label = "SBL2"; + reg = <0x30000 0x30000>; + read-only; + }; + + SBL3@60000 { + label = "SBL3"; + reg = <0x60000 0x30000>; + read-only; + }; + + DDRCONFIG@90000 { + label = "DDRCONFIG"; + reg = <0x90000 0x10000>; + read-only; + }; + + SSD@a0000 { + label = "SSD"; + reg = <0xa0000 0x10000>; + read-only; + }; + + TZ@b0000 { + label = "TZ"; + reg = <0xb0000 0x30000>; + read-only; + }; + + RPM@e0000 { + label = "RPM"; + reg = <0xe0000 0x20000>; + read-only; + }; + + APPSBL@100000 { + label = "APPSBL"; + reg = <0x100000 0x70000>; + read-only; + }; + + APPSBLENV@170000 { + label = "APPSBLENV"; + reg = <0x170000 0x10000>; + read-only; + }; + + ART@180000 { + label = "ART"; + reg = <0x180000 0x40000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ART_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_ART_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_ART_18: macaddr@18 { + reg = <0x18 0x6>; + }; + + macaddr_ART_1e: macaddr@1e { + reg = <0x1e 0x6>; + }; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + BOOTCONFIG@1c0000 { + label = "BOOTCONFIG"; + reg = <0x1c0000 0x10000>; + read-only; + }; + + APPSBL_1@1d0000 { + label = "APPSBL_1"; + reg = <0x1d0000 0x70000>; + read-only; + }; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; +}; + +&dwc3_0 { + #address-cells = <1>; + #size-cells = <0>; + + hub_port0: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio58", "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs{ + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb_pwr_en_pins: usb_pwr_en_pins { + mux{ + pins = "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts new file mode 100644 index 0000000000..969ca724e3 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts @@ -0,0 +1,316 @@ +#include "qcom-ipq8065.dtsi" + +#include + +/ { + model = "ZyXEL NBG6817"; + compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + sdcc1 = &sdcc1; + + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1"; + append-rootblock = "root=/dev/mmcblk0p"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + internet { + label = "white:internet"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi2g { + label = "amber:wifi2g"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; + }; + + /* wifi2g amber from the manual is missing */ + + wifi5g { + label = "amber:wifi5g"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + /* wifi5g amber from the manual is missing */ + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio53", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio9", "gpio26", "gpio33", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + mdio0_pins: mdio0_pins { + clk { + pins = "gpio1"; + input-disable; + }; + }; + + rgmii2_pins: rgmii2_pins { + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; + input-disable; + }; + }; + + spi_pins: spi_pins { + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <12>; + }; + + pwr { + pins = "gpio17"; + bias-pull-down; + output-high; + }; + + ovc { + pins = "gpio16"; + bias-pull-up; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <12>; + }; + + pwr { + pins = "gpio14"; + bias-pull-down; + output-high; + }; + + ovc { + pins = "gpio15"; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <51200000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ + 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ + 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ + 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ + 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ + 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ + 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ + 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ + 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ + 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ + 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ + 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ + 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ + 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + qca,ar8327-initvals = < + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x0000c 0x80 /* PAD6_MODE */ + >; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <0>; + qcom,rgmii_delay = <1>; + qcom,phy_mii_type = <0>; + qcom,emulation = <0>; + qcom,irq = <255>; + mdiobus = <&mdio0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,phy_mii_type = <1>; + qcom,emulation = <0>; + qcom,irq = <258>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&amba { + sdcc1: sdcc@12400000 { + status = "okay"; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi new file mode 100644 index 0000000000..c899fa7c75 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi @@ -0,0 +1,453 @@ +#include "qcom-ipq8065.dtsi" + +#include + +/ { + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + + ramoops@42100000 { + compatible = "ramoops"; + reg = <0x42100000 0x40000>; + record-size = <0x4000>; + console-size = <0x4000>; + ftrace-size = <0x4000>; + pmsg-size = <0x4000>; + }; + }; + + aliases { + label-mac-device = &gmac2; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + + mdio-gpio0 = &mdio0; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + power_white: power_white { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + power_amber: power_amber { + label = "amber:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", + "gpio22", "gpio23", "gpio24", + "gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + mdio0_pins: mdio0_pins { + clk { + pins = "gpio1"; + input-disable; + }; + }; + + rgmii2_pins: rgmii2_pins { + tx { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + spi6_pins: spi6_pins { + mux { + pins = "gpio55", "gpio56", "gpio58"; + function = "gsbi6"; + bias-pull-down; + }; + + mosi { + pins = "gpio55"; + drive-strength = <12>; + }; + + miso { + pins = "gpio56"; + drive-strength = <14>; + }; + + cs { + pins = "gpio57"; + drive-strength = <12>; + bias-pull-up; + }; + + clk { + pins = "gpio58"; + drive-strength = <12>; + }; + + reset { + pins = "gpio33"; + drive-strength = <10>; + bias-pull-down; + output-high; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + partition@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + partition@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: partition@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + partition@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + partition@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ + 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ + 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ + 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ + 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ + 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ + 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ + 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ + 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ + 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ + 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ + 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ + 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ + 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ + >; + qca,ar8327-vlans = < + 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */ + 0x2 0x21 /* VLAN2 Ports 0/5 */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + qca,ar8327-initvals = < + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x0000c 0x80 /* PAD6_MODE */ + >; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <0>; + qcom,rgmii_delay = <1>; + qcom,phy_mii_type = <0>; + qcom,emulation = <0>; + qcom,irq = <255>; + mdiobus = <&mdio0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,phy_mii_type = <1>; + qcom,emulation = <0>; + qcom,irq = <258>; + mdiobus = <&mdio0>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts new file mode 100644 index 0000000000..bf7c963944 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-r7800.dts @@ -0,0 +1,48 @@ +#include "qcom-ipq8065-nighthawk.dtsi" + +/ { + model = "Netgear Nighthawk X4S R7800"; + compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064"; +}; + +&leds { + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&partitions { + partition@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + partition@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; +}; + +&wifi0 { + nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(1)>; +}; + +&wifi1 { + nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <(2)>; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts new file mode 100644 index 0000000000..96163331f3 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "qcom-ipq8065.dtsi" +#include + +/ { + model = "Askey RT4230W REV6"; + compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x3e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &ledctrl3; + led-failsafe = &ledctrl1; + led-running = &ledctrl2; + led-upgrade = &ledctrl3; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + ledctrl1: ledctrl1 { + label = "ledctrl1"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + ledctrl2: ledctrl2 { + label = "ledctrl2"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + ledctrl3: ledctrl3 { + label = "ledctrl3"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio54", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio22", "gpio23", "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + rgmii2_pins: rgmii2_pins { + mux { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; + }; + + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; + + spi_pins: spi_pins { + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "everspin,mr25h256"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "0:MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + partition@180000 { + label = "0:SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + partition@2c0000 { + label = "0:SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + partition@540000 { + label = "0:DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + partition@660000 { + label = "0:SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + partition@780000 { + label = "0:TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + partition@a00000 { + label = "0:RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + partition@c80000 { + label = "0:APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + partition@1180000 { + label = "0:APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + + partition@1200000 { + label = "0:ART"; + reg = <0x1200000 0x0140000>; + read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ART_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_ART_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + partition@1340000 { + label = "0:BOOTCONFIG"; + reg = <0x1340000 0x0060000>; + read-only; + }; + + partition@13a0000 { + label = "0:SBL2_1"; + reg = <0x13a0000 0x0140000>; + read-only; + }; + + partition@14e0000 { + label = "0:SBL3_1"; + reg = <0x14e0000 0x0280000>; + read-only; + }; + + partition@1760000 { + label = "0:DDRCONFIG_1"; + reg = <0x1760000 0x0120000>; + read-only; + }; + + partition@1880000 { + label = "0:SSD_1"; + reg = <0x1880000 0x0120000>; + read-only; + }; + + partition@19a0000 { + label = "0:TZ_1"; + reg = <0x19a0000 0x0280000>; + read-only; + }; + + partition@1c20000 { + label = "0:RPM_1"; + reg = <0x1c20000 0x0280000>; + read-only; + }; + + partition@1ea0000 { + label = "0:BOOTCONFIG1"; + reg = <0x1ea0000 0x0060000>; + read-only; + }; + + partition@1f00000 { + label = "0:APPSBL_1"; + reg = <0x1f00000 0x0500000>; + read-only; + }; + + partition@2400000 { + label = "ubi"; + reg = <0x2400000 0x1a000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + 0x00050 0xcf02cf02 /* LED_CTRL_0 */ + 0x00054 0xc832c832 /* LED_CTRL_1 */ + >; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + nvmem-cells = <&macaddr_ART_0>; + nvmem-cell-names = "mac-address"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_ART_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_1000>; + nvmem-cell-names = "pre-calibration"; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_5000>; + nvmem-cell-names = "pre-calibration"; + }; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts new file mode 100644 index 0000000000..871cc09502 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "qcom-ipq8065.dtsi" +#include + +/ { + model = "Arris TR4400 v2"; + compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &led_status_blue; + led-failsafe = &led_status_red; + led-running = &led_status_blue; + led-upgrade = &led_status_red; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_status_red: status_red { + label = "red:status"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: status_blue { + label = "blue:status"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + rgmii2_pins: rgmii2_pins { + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; + + spi_pins: spi_pins { + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "everspin,mr25h256"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + partition@40000 { + label = "0:MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + partition@180000 { + label = "0:SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + partition@2c0000 { + label = "0:SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + partition@540000 { + label = "0:DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + partition@660000 { + label = "0:SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + partition@780000 { + label = "0:TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + partition@a00000 { + label = "0:RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + partition@c80000 { + label = "0:APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + partition@1180000 { + label = "0:APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + partition@1200000 { + label = "0:ART"; + reg = <0x1200000 0x0140000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_ART_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + precal_ART_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + stock_partition@1340000 { + label = "stock_rootfs"; + reg = <0x1340000 0x4000000>; + }; + partition@5340000 { + label = "0:BOOTCONFIG"; + reg = <0x5340000 0x0060000>; + read-only; + }; + partition@53a0000 { + label = "0:SBL2_1"; + reg = <0x53a0000 0x0140000>; + read-only; + }; + partition@54e0000 { + label = "0:SBL3_1"; + reg = <0x54e0000 0x0280000>; + read-only; + }; + partition@5760000 { + label = "0:DDRCONFIG_1"; + reg = <0x5760000 0x0120000>; + read-only; + }; + partition@5880000 { + label = "0:SSD_1"; + reg = <0x5880000 0x0120000>; + read-only; + }; + partition@59a0000 { + label = "0:TZ_1"; + reg = <0x59a0000 0x0280000>; + read-only; + }; + partition@5c20000 { + label = "0:RPM_1"; + reg = <0x5c20000 0x0280000>; + read-only; + }; + partition@5ea0000 { + label = "0:BOOTCONFIG1"; + reg = <0x5ea0000 0x0060000>; + read-only; + }; + partition@5f00000 { + label = "0:APPSBL_1"; + reg = <0x5f00000 0x0500000>; + read-only; + }; + stock_partition@6400000 { + label = "stock_rootfs_1"; + reg = <0x6400000 0x4000000>; + }; + stock_partition@a400000 { + label = "stock_fw_env"; + reg = <0xa400000 0x0100000>; + }; + stock_partition@a500000 { + label = "stock_config"; + reg = <0xa500000 0x0800000>; + }; + stock_partition@ad00000 { + label = "stock_PKI"; + reg = <0xad00000 0x0200000>; + }; + stock_partition@af00000 { + label = "stock_scfgmgr"; + reg = <0xaf00000 0x0100000>; + }; + + partition@6400000 { + label = "fw_env"; + reg = <0x6400000 0x0100000>; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_fw_env_0: macaddr@0 { + reg = <0x00 0x6>; + }; + macaddr_fw_env_6: macaddr@6 { + reg = <0x06 0x6>; + }; + macaddr_fw_env_c: macaddr@c { + reg = <0x0c 0x6>; + }; + macaddr_fw_env_12: macaddr@12 { + reg = <0x12 0x6>; + }; + macaddr_fw_env_18: macaddr@18 { + reg = <0x18 0x6>; + }; + }; + partition@6500000 { + label = "ubi"; + reg = <0x6500000 0x9b00000>; + }; + partition@1340000 { + label = "extra"; + reg = <0x1340000 0x4000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0x0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy7: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + nvmem-cells = <&macaddr_fw_env_18>; + nvmem-cell-names = "mac-address"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_fw_env_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac3 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <3>; + phy-handle = <&phy7>; + + nvmem-cells = <&macaddr_fw_env_6>; + nvmem-cell-names = "mac-address"; +}; + +&adm_dma { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>; + nvmem-cell-names = "pre-calibration", "mac-address"; + }; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts new file mode 100644 index 0000000000..f584735e15 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-xr500.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8065-nighthawk.dtsi" + +/ { + model = "Netgear Nighthawk XR500"; + compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064"; + +}; + +&leds { + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&partitions { + partition@1880000 { + label = "ubi"; + reg = <0x1880000 0xce00000>; + }; + + partition@e680000 { + label = "reserve"; + reg = <0xe680000 0x0780000>; + read-only; + }; +}; + +&wifi0 { + nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; + +&wifi1 { + nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; +}; + +&art { + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi new file mode 100644 index 0000000000..c70a5cbaed --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi @@ -0,0 +1,167 @@ +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm IPQ8065"; + compatible = "qcom,ipq8065", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&sata { + ports-implemented = <0x1>; +}; + +&smb208_s2a { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; +}; + +&smb208_s2b { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; +}; + +&ss_phy_0 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&ss_phy_1 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&opp_table_l2 { + /delete-node/opp-1200000000; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1150000>; + clock-latency-ns = <100000>; + opp-level = <2>; + }; +}; + +&opp_table0 { + /* + * On ipq8065 1.2 ghz freq is not present + * Remove it to make cpufreq work and not + * complain for missing definition + */ + + /delete-node/opp-1200000000; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; + opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; + opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; + opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; + opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; + opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; + opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; + opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; + }; + + opp-1400000000 { + opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; + opp-level = <1>; + }; + + opp-1725000000 { + opp-hz = /bits/ 64 <1725000000>; + opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; + opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; + opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; + opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <2>; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi new file mode 100644 index 0000000000..141c71a8aa --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + memory { + device_type = "memory"; + linux,usable-memory = <0x41500000 0x1ea00000>; + reg = <0x40000000 0x20000000>; + }; + + cpus { + idle-states { + CPU_SPC: spc { + status = "disabled"; + }; + }; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art"; + }; +}; + +&qcom_pinmux { + mdio0_pins_active: mdio0_pins_active { + mux { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + + clk { + pins = "gpio1"; + input-disable; + }; + }; + + phy_active: phy_active { + phy { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-high; + }; + }; + + uart1_pins: uart1_pins { + mux { + pins = "gpio51", "gpio52"; + function = "gsbi1"; + drive-strength = <4>; + bias-disable; + }; + }; +}; + +&gsbi1 { + status = "okay"; + qcom,mode = ; + + serial@12450000 { + status = "okay"; + + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + }; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi2: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x2140000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "sbl1"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "mibib"; + reg = <0x40000 0x140000>; + read-only; + }; + + partition@180000 { + label = "sbl2"; + reg = <0x180000 0x140000>; + read-only; + }; + + partition@2c0000 { + label = "sbl3"; + reg = <0x2c0000 0x280000>; + read-only; + }; + + partition@540000 { + label = "ddrconfig"; + reg = <0x540000 0x120000>; + read-only; + }; + + partition@660000 { + label = "ssd"; + reg = <0x660000 0x120000>; + read-only; + }; + + partition@780000 { + label = "tz"; + reg = <0x780000 0x280000>; + read-only; + }; + + partition@a00000 { + label = "rpm"; + reg = <0xa00000 0x280000>; + read-only; + }; + + partition@1fc0000 { + label = "u-boot"; + reg = <0x1fc0000 0x180000>; + read-only; + }; + + partition@21c0000 { + label = "bootkernel1"; + reg = <0x21c0000 0xa80000>; + }; + + partition@2c40000 { + label = "bootkernel2"; + reg = <0x2c40000 0xa80000>; + }; + + partition@36c0000 { + label = "ubi"; + reg = <0x36c0000 0x46c0000>; + }; + + partition@7d80000 { + label = "art"; + reg = <0x7d80000 0x200000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts new file mode 100644 index 0000000000..85b0dc3b8c --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts @@ -0,0 +1,332 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include +#include + +/ { + model = "Edgecore ECW5410"; + compatible = "edgecore,ecw5410", "qcom,ipq8064"; + + reserved-memory { + nss@40000000 { + reg = <0x40000000 0x1000000>; + no-map; + }; + + smem: smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; + + wifi_dump@44000000 { + reg = <0x44000000 0x600000>; + no-map; + }; + }; + + cpus { + idle-states { + CPU_SPC: spc { + status = "disabled"; + }; + }; + }; + + aliases { + serial1 = &gsbi1_serial; + ethernet0 = &gmac2; + ethernet1 = &gmac3; + + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_green; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + label = "green:power"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; + }; + + wlan2g_yellow { + label = "yellow:wlan2g"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + led_power_red: power_red { + label = "red:power"; + gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; + }; + + wlan5g_yellow { + label = "yellow:wlan5g"; + gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>; + }; + }; +}; + + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio16", "gpio23", "gpio24", "gpio26", + "gpio28", "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart1_pins: uart1_pins { + mux { + pins = "gpio51", "gpio52", "gpio53", "gpio54"; + function = "gsbi1"; + drive-strength = <12>; + bias-none; + }; + }; +}; + +&gsbi1 { + qcom,mode = ; + status = "okay"; + + serial@12450000 { + status = "okay"; + + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; + }; +}; + +&hs_phy_0 { /* USB3 port 0 HS phy */ + status = "okay"; +}; + +&hs_phy_1 { /* USB3 port 1 HS phy */ + status = "okay"; +}; + +&ss_phy_0 { /* USB3 port 0 SS phy */ + status = "okay"; +}; + +&ss_phy_1 { /* USB3 port 1 SS phy */ + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; + }; + }; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + rootfs1@0 { + label = "rootfs1"; + reg = <0x0000000 0x4000000>; + }; + + rootfs2@4000000 { + label = "rootfs2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy1>; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts new file mode 100644 index 0000000000..ccf2554ca3 --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8068-cryptid-common.dtsi" + +#include + +/ { + model = "Meraki MR42"; + compatible = "meraki,mr42", "qcom,ipq8064"; + + aliases { + serial1 = &gsbi1_serial; + ethernet0 = &gmac3; + + led-boot = &led_active; + led-failsafe = &led_power; + led-running = &led_active; + led-upgrade = &led_active; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "orange:power"; + gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>; + }; + + led_active: active { + label = "white:active"; + gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy2>; + + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; +}; + +&gsbi2 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi2_i2c { + status = "okay"; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + ina2xx@40 { + compatible = "ina219"; + shunt-resistor = <40000>; + reg = <0x40>; + }; + + eeprom@56 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x56>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; + +&gsbi6 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi6_i2c { + status = "okay"; + + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + tlc591xx@40 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x40>; + + red@0 { + label = "red:user"; + reg = <0x0>; + }; + + green@1 { + label = "green:user"; + reg = <0x1>; + }; + + blue@2 { + label = "blue:user"; + reg = <0x2>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; + pinctrl-names = "default"; + + phy2: ethernet-phy2 { + reg = <2>; + + reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&qcom_pinmux { + i2c0_pins: i2c0_pins { + mux { + pins = "gpio24", "gpio25"; + function = "gsbi2"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1_pins { + mux { + pins = "gpio29", "gpio30"; + function = "gsbi6"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio31", "gpio32"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-low; + }; + }; +}; + +&wifi0 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; +}; + +&wifi1 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <2>; +}; + +&wifi2 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <3>; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts new file mode 100644 index 0000000000..e1c233254d --- /dev/null +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8068-cryptid-common.dtsi" + +#include + +/ { + model = "Meraki MR52"; + compatible = "meraki,mr52", "qcom,ipq8064"; + + aliases { + serial1 = &gsbi1_serial; + mdio-gpio0 = &mdio_gpio0; + ethernet0 = &gmac2; + ethernet1 = &gmac3; + + led-boot = &led_active; + led-failsafe = &led_power; + led-running = &led_active; + led-upgrade = &led_active; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "orange:power"; + gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>; + }; + + lan2_green { + label = "green:lan2"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + lan1_green { + label = "green:lan1"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + led_active: active { + label = "white:active"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + lan2_orange { + label = "orange:lan2"; + gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>; + }; + + lan1_orange { + label = "orange:lan1"; + gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio_gpio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy4>; + + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; +}; + +&gsbi7 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi7_i2c { + status = "okay"; + + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + + ina2xx@45 { + compatible = "ina219"; + shunt-resistor = <80000>; + reg = <0x45>; + }; + + tlc591xx@49 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x49>; + + red@0 { + label = "red:user"; + reg = <0x0>; + }; + + green@1 { + label = "green:user"; + reg = <0x1>; + }; + + blue@2 { + label = "blue:user"; + reg = <0x2>; + }; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; + +&qcom_pinmux { + i2c_pins: i2c_pins { + mux { + pins = "gpio8", "gpio9"; + function = "gsbi7"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio19", "gpio26"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-low; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; +}; + +&soc { + mdio_gpio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; + pinctrl-names = "default"; + + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH + &qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + + phy0: ethernet-phy0 { + reg = <0>; + reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + }; + + phy4: ethernet-phy4 { + reg = <4>; + reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + }; + }; +}; + +&wifi0 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <4>; +}; + +&wifi1 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <3>; +}; + +&wifi2 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <2>; +}; From f2dc0024951202874dfaf7a81c58afa4c5d9369c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:07:47 +0200 Subject: [PATCH 22/43] ipq806x: 5.15: remove qcom adm Documentation patch Remove qcom adm Documentation patch that is not needed for the target. Probably a leftover when the adm bus was added, now merged upstream. Signed-off-by: Christian Marangi --- ...ings-qcom_adm-Fix-channel-specifiers.patch | 71 ------------------- 1 file changed, 71 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch diff --git a/target/linux/ipq806x/patches-5.15/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch b/target/linux/ipq806x/patches-5.15/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch deleted file mode 100644 index 83d7bbc6f4..0000000000 --- a/target/linux/ipq806x/patches-5.15/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 28d0ed88f536dd639adf1b0c7c08e04be3c8f294 Mon Sep 17 00:00:00 2001 -From: Thomas Pedersen -Date: Mon, 16 May 2016 17:58:50 -0700 -Subject: [PATCH 01/69] dtbindings: qcom_adm: Fix channel specifiers - -Original patch from Andy Gross. - -This patch removes the crci information from the dma -channel property. At least one client device requires -using more than one CRCI value for a channel. This does -not match the current binding and the crci information -needs to be removed. - -Instead, the client device will provide this information -via other means. - -Signed-off-by: Andy Gross -Signed-off-by: Thomas Pedersen ---- - Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++---------- - 1 file changed, 6 insertions(+), 10 deletions(-) - ---- a/Documentation/devicetree/bindings/dma/qcom_adm.txt -+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt -@@ -4,8 +4,7 @@ Required properties: - - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 - - reg: Address range for DMA registers - - interrupts: Should contain one interrupt shared by all channels --- #dma-cells: must be <2>. First cell denotes the channel number. Second cell -- denotes CRCI (client rate control interface) flow control assignment. -+- #dma-cells: must be <1>. First cell denotes the channel number. - - clocks: Should contain the core clock and interface clock. - - clock-names: Must contain "core" for the core clock and "iface" for the - interface clock. -@@ -22,7 +21,7 @@ Example: - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <0 170 0>; -- #dma-cells = <2>; -+ #dma-cells = <1>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; -@@ -35,15 +34,12 @@ Example: - qcom,ee = <0>; - }; - --DMA clients must use the format descripted in the dma.txt file, using a three -+DMA clients must use the format descripted in the dma.txt file, using a two - cell specifier for each channel. - --Each dmas request consists of 3 cells: -+Each dmas request consists of two cells: - 1. phandle pointing to the DMA controller - 2. channel number -- 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. -- The CRCI is used for flow control. It identifies the peripheral device that -- is the source/destination for the transferred data. - - Example: - -@@ -55,7 +51,7 @@ Example: - - cs-gpios = <&qcom_pinmux 20 0>; - -- dmas = <&adm_dma 6 9>, -- <&adm_dma 5 10>; -+ dmas = <&adm_dma 6>, -+ <&adm_dma 5>; - dma-names = "rx", "tx"; - }; From bd02eb75020a5cb73e1ddda91e38f98668cddb4f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:08:39 +0200 Subject: [PATCH 23/43] ipq806x: 5.15: remove PCI_DOMAINS patch not needed anymore This doesn't cause any panic anymore and no regression are observed with ath10k. Remove this additional patch. Signed-off-by: Christian Marangi --- ...ically-select-PCI_DOMAINS-if-PCI-is-.patch | 29 ------------------- 1 file changed, 29 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch diff --git a/target/linux/ipq806x/patches-5.15/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch b/target/linux/ipq806x/patches-5.15/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch deleted file mode 100644 index a12aa721e2..0000000000 --- a/target/linux/ipq806x/patches-5.15/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 48051ece78136e4235a2415a52797db56f8a4478 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Tue, 21 Apr 2015 19:09:07 -0700 -Subject: [PATCH 33/69] ARM: qcom: automatically select PCI_DOMAINS if PCI is - enabled - -If multiple PCIe devices are present in the system, the kernel will -panic at boot time when trying to scan the PCI buses. This happens on -IPQ806x based platforms, which has 3 PCIe ports. - -Enabling this option allows the kernel to assign the pci-domains -according to the device-tree content. This allows multiple PCIe -controllers to coexist in the system. - -Signed-off-by: Mathieu Olivari ---- - arch/arm/mach-qcom/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-qcom/Kconfig -+++ b/arch/arm/mach-qcom/Kconfig -@@ -7,6 +7,7 @@ menuconfig ARCH_QCOM - select ARM_AMBA - select PINCTRL - select QCOM_SCM if SMP -+ select PCI_DOMAINS if PCI - help - Support for Qualcomm's devicetree based systems. - From 88bf6525251f7ef3d4f0b63e2cf77b42078101a4 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:12:01 +0200 Subject: [PATCH 24/43] ipq806x: 5.15: replace dtsi patches with upstream version Reorganize dtsi patches with upstream version and drop dtsi in 5.15 files. Also add an additional upstream patch for hwspinlock support. Refresh all the dts with needed changes. Signed-off-by: Christian Marangi --- .../arm/boot/dts/qcom-ipq8062-wg2600hp3.dts | 11 +- .../arch/arm/boot/dts/qcom-ipq8062.dtsi | 98 ----- .../boot/dts/qcom-ipq8064-ad7200-c2600.dtsi | 2 +- .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 3 - .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 5 +- .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 8 +- .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 5 +- .../arch/arm/boot/dts/qcom-ipq8064-g10.dts | 81 +++- .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 3 - .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 5 +- .../arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts | 4 +- .../arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 ---- .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 2 +- .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 2 +- .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 5 +- .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 6 +- .../arm/boot/dts/qcom-ipq8065-nighthawk.dtsi | 9 +- .../boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 7 +- .../arm/boot/dts/qcom-ipq8065-tr4400-v2.dts | 7 +- .../arch/arm/boot/dts/qcom-ipq8065.dtsi | 167 -------- .../boot/dts/qcom-ipq8068-cryptid-common.dtsi | 5 +- .../arm/boot/dts/qcom-ipq8068-ecw5410.dts | 5 +- .../082-ipq8064-dtsi-tweaks.patch | 240 ----------- .../083-ipq8064-dtsi-additions.patch | 371 ------------------ .../084-ipq8064-v1.0-dtsi-cleanup.patch | 89 ----- .../085-ipq8064-v1.0-dtsi-additions.patch | 14 - ...replace-gcc-PXO-with-pxo_board-fixed.patch | 36 ++ ...add-syscon-and-cxo-pxo-clock-to-gcc-.patch | 39 ++ ...8064-add-multiple-missing-pin-defini.patch | 101 +++++ ...ipq8064-add-gsbi6-missing-definition.patch | 67 ++++ ...8064-add-specific-dtsi-with-smb208-r.patch | 66 ++++ ...8064-add-missing-snps-dwmac-compatib.patch | 56 +++ ...m-ipq8064-disable-usb-phy-by-default.patch | 37 ++ ...m-ipq8064-reduce-pci-IO-size-to-64K.patch} | 21 +- ...8064-fix-and-add-some-missing-gsbi-n.patch | 94 +++++ ...pq8064-add-speedbin-efuse-nvmem-node.patch | 28 ++ ...Add-support-for-mmio-usage-to-sfpb-m.patch | 71 ++++ ...-dts-qcom-ipq8064-add-missing-hwlock.patch | 31 ++ ...-ipq8064-add-missing-smem-compatible.patch | 30 ++ ...dts-qcom-ipq8064-add-v2-dtsi-variant.patch | 129 ++++++ ...dts-qcom-ipq8064-add-ipq8062-variant.patch | 67 ++++ ...dts-qcom-ipq8064-add-ipq8065-variant.patch | 67 ++++ ...add-saw-for-l2-cache-and-kraitcc-for.patch | 95 +++++ ...add-opp-table-for-cpu-and-l2-for-ipq.patch | 268 +++++++++++++ ...add-multiple-missing-binding-for-cpu.patch | 153 ++++++++ ...-wrong-nad_pins-definition-for-ipq80.patch | 29 ++ ...MDIO-dedicated-controller-node-for-.patch} | 45 ++- .../patches-5.15/851-add-gsbi1-dts.patch | 44 --- 48 files changed, 1618 insertions(+), 1179 deletions(-) delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi delete mode 100644 target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi delete mode 100644 target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch delete mode 100644 target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch delete mode 100644 target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch delete mode 100644 target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch create mode 100644 target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch create mode 100644 target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch create mode 100644 target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch create mode 100644 target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch create mode 100644 target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch create mode 100644 target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch create mode 100644 target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch rename target/linux/ipq806x/patches-5.15/{103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch => 104-v6.0-06-ARM-dts-qcom-ipq8064-reduce-pci-IO-size-to-64K.patch} (72%) create mode 100644 target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch create mode 100644 target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch create mode 100644 target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch create mode 100644 target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch create mode 100644 target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch create mode 100644 target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch create mode 100644 target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch create mode 100644 target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch create mode 100644 target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch create mode 100644 target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch create mode 100644 target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch create mode 100644 target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch rename target/linux/ipq806x/patches-5.15/{086-ipq8064-fix-duplicate-node.patch => 108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch} (63%) delete mode 100644 target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts index c1c21856ca..11ae3f81c3 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8062.dtsi" +#include "qcom-ipq8062-smb208.dtsi" #include /delete-node/ &nand_pins; @@ -134,6 +134,15 @@ }; }; +/* nand_pins are used for leds_pins, empty the node + * from ipq8064.dtsi + */ +&nand_pins { + /delete-property/ disable; + /delete-property/ pullups; + /delete-property/ hold; +}; + &qcom_pinmux { pinctrl-0 = <&akro_pins>; pinctrl-names = "default"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi deleted file mode 100644 index 29226ca275..0000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "qcom-ipq8064.dtsi" - -/ { - model = "Qualcomm IPQ8062"; - compatible = "qcom,ipq8062", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&opp_table0 { - /delete-node/opp-1200000000; - /delete-node/opp-1400000000; - - /* - * Voltage thresholds are - */ - opp-384000000 { - opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>; - opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>; - opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>; - }; - - opp-600000000 { - opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; - opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>; - opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>; - opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>; - }; - - opp-800000000 { - opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>; - opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>; - }; - - opp-1000000000 { - opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; - opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; - opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>; - }; -}; - -&pcie0 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie1 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie2 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&smb208_s2a { - regulator-max-microvolt = <1150000>; -}; - -&smb208_s2b { - regulator-max-microvolt = <1150000>; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi index 115c6d43d2..c6a78f7fd8 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index 70034a50e3..cf73ed6a0a 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -54,9 +54,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts index c771a627ca..926d9286a7 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts @@ -25,7 +25,7 @@ }; &qcom_pinmux { - rgmii2_pins: rgmii2_pins { + rgmii2_pins: rgmii2-pins { mux { pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", @@ -66,9 +66,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts index 23487c9ca0..f9f9c035d3 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts @@ -1,4 +1,4 @@ -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include @@ -234,12 +234,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi index e74d2dcdbd..68e5b24704 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include @@ -37,9 +37,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts index 735ccb2d53..ba27d89c05 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include #include @@ -158,26 +158,77 @@ pinctrl-0 = <&mdio0_pins>; pinctrl-names = "default"; - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + + qca8k,rgmii56_1_8v; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "wan"; + }; + + /* + port@6 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + asym-pause; + }; + }; + */ + }; }; }; &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts index 0970eaf0ec..1505e23f38 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts @@ -167,9 +167,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts index 30b56bb9d6..b43ee90034 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts @@ -1,4 +1,4 @@ -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include @@ -231,9 +231,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts index b3e06db86d..90927ddb85 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include #include @@ -221,8 +221,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; nand-ecc-strength = <4>; nand-bus-width = <8>; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi deleted file mode 100644 index b9ee86a891..0000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -#include "qcom-ipq8064.dtsi" - -/ { - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&CPU_SPC { - status = "okay"; -}; - -&pcie0 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie1 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie2 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&sata { - ports-implemented = <0x1>; -}; - -&ss_phy_0 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; - -&ss_phy_1 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts index 27d9fc84b3..5ae1a3ec08 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts @@ -1,4 +1,4 @@ -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts index 998dad55c5..b33183d1a2 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts @@ -1,4 +1,4 @@ -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts index 04a2261929..c617064250 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include @@ -159,9 +159,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - cs@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts index 969ca724e3..c00f95f225 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts @@ -1,4 +1,4 @@ -#include "qcom-ipq8065.dtsi" +#include "qcom-ipq8065-smb208.dtsi" #include @@ -108,14 +108,14 @@ }; }; - mdio0_pins: mdio0_pins { + mdio0_pins: mdio0-pins { clk { pins = "gpio1"; input-disable; }; }; - rgmii2_pins: rgmii2_pins { + rgmii2_pins: rgmii2-pins { tx { pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; input-disable; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi index c899fa7c75..6c007e2c16 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi @@ -1,4 +1,4 @@ -#include "qcom-ipq8065.dtsi" +#include "qcom-ipq8065-smb208.dtsi" #include @@ -124,14 +124,14 @@ }; }; - mdio0_pins: mdio0_pins { + mdio0_pins: mdio0-pins { clk { pins = "gpio1"; input-disable; }; }; - rgmii2_pins: rgmii2_pins { + rgmii2_pins: rgmii2-pins { tx { pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; @@ -223,9 +223,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts index 96163331f3..51ef2c3321 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later -#include "qcom-ipq8065.dtsi" +#include "qcom-ipq8065-smb208.dtsi" #include / { @@ -82,7 +82,7 @@ }; }; - rgmii2_pins: rgmii2_pins { + rgmii2_pins: rgmii2-pins { mux { pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62"; @@ -130,9 +130,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts index 871cc09502..9244639137 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later -#include "qcom-ipq8065.dtsi" +#include "qcom-ipq8065-smb208.dtsi" #include / { @@ -81,7 +81,7 @@ }; }; - rgmii2_pins: rgmii2_pins { + rgmii2_pins: rgmii2-pins { tx { pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; input-disable; @@ -119,9 +119,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { reg = <0>; compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi deleted file mode 100644 index c70a5cbaed..0000000000 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065.dtsi +++ /dev/null @@ -1,167 +0,0 @@ -#include "qcom-ipq8064.dtsi" - -/ { - model = "Qualcomm IPQ8065"; - compatible = "qcom,ipq8065", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&pcie0 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie1 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie2 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&sata { - ports-implemented = <0x1>; -}; - -&smb208_s2a { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; -}; - -&smb208_s2b { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; -}; - -&ss_phy_0 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; - -&ss_phy_1 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; - -&opp_table_l2 { - /delete-node/opp-1200000000; - - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1150000>; - clock-latency-ns = <100000>; - opp-level = <2>; - }; -}; - -&opp_table0 { - /* - * On ipq8065 1.2 ghz freq is not present - * Remove it to make cpufreq work and not - * complain for missing definition - */ - - /delete-node/opp-1200000000; - - /* - * Voltage thresholds are - */ - opp-384000000 { - opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; - opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; - opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; - opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; - opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; - opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; - }; - - opp-600000000 { - opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; - opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; - opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; - opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; - opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; - }; - - opp-800000000 { - opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; - opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; - opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; - opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; - }; - - opp-1000000000 { - opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; - opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; - opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; - }; - - opp-1400000000 { - opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; - opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; - opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; - opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; - opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; - opp-level = <1>; - }; - - opp-1725000000 { - opp-hz = /bits/ 64 <1725000000>; - opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; - opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; - opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; - opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; - opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; - opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - opp-level = <2>; - }; -}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi index 141c71a8aa..93b9aa86f7 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 OR MIT -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" / { memory { @@ -140,9 +140,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts index 85b0dc3b8c..574536cf55 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts @@ -1,4 +1,4 @@ -#include "qcom-ipq8064-v2.0.dtsi" +#include "qcom-ipq8064-v2.0-smb208.dtsi" #include #include @@ -262,9 +262,6 @@ &nand { status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand@0 { compatible = "qcom,nandcs"; diff --git a/target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch b/target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch deleted file mode 100644 index 36be35fce1..0000000000 --- a/target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch +++ /dev/null @@ -1,240 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -352,6 +352,7 @@ - gpio-ranges = <&qcom_pinmux 0 0 69>; - #gpio-cells = <2>; - interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <2>; - interrupts = ; - -@@ -379,6 +380,7 @@ - function = "pcie3_rst"; - drive-strength = <12>; - bias-disable; -+ output-low; - }; - }; - -@@ -411,12 +413,9 @@ - }; - - nand_pins: nand_pins { -- mux { -+ disable { - pins = "gpio34", "gpio35", "gpio36", -- "gpio37", "gpio38", "gpio39", -- "gpio40", "gpio41", "gpio42", -- "gpio43", "gpio44", "gpio45", -- "gpio46", "gpio47"; -+ "gpio37", "gpio38"; - function = "nand"; - drive-strength = <10>; - bias-disable; -@@ -424,6 +423,8 @@ - - pullups { - pins = "gpio39"; -+ function = "nand"; -+ drive-strength = <10>; - bias-pull-up; - }; - -@@ -431,6 +432,8 @@ - pins = "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47"; -+ function = "nand"; -+ drive-strength = <10>; - bias-bus-hold; - }; - }; -@@ -439,6 +442,7 @@ - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; -@@ -468,11 +472,13 @@ - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu0_aux"; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu1_aux"; - }; - - adm_dma: dma-controller@18300000 { -@@ -496,13 +502,13 @@ - }; - - saw0: regulator@2089000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; -@@ -530,7 +536,7 @@ - status = "disabled"; - }; - -- i2c@124a0000 { -+ gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = ; -@@ -676,9 +682,6 @@ - compatible = "qcom,ipq806x-nand"; - reg = <0x1ac00000 0x800>; - -- pinctrl-0 = <&nand_pins>; -- pinctrl-names = "default"; -- - clocks = <&gcc EBI2_CLK>, - <&gcc EBI2_AON_CLK>; - clock-names = "core", "aon"; -@@ -733,10 +736,13 @@ - tsens_calib_backup: calib_backup@410 { - reg = <0x410 0xb>; - }; -+ speedbin_efuse: speedbin@0c0 { -+ reg = <0x0c0 0x4>; -+ }; - }; - - gcc: clock-controller@900000 { -- compatible = "qcom,gcc-ipq8064"; -+ compatible = "qcom,gcc-ipq8064", "syscon"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; -@@ -768,10 +774,45 @@ - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - -+ #address-cells = <1>; -+ #size-cells = <0>; -+ - rpmcc: clock-controller { - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; - }; -+ -+ regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; - }; - - tcsr: syscon@1a400000 { -@@ -965,7 +1006,7 @@ - - gmac0: ethernet@37000000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -989,7 +1030,7 @@ - - gmac1: ethernet@37200000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37200000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1013,7 +1054,7 @@ - - gmac2: ethernet@37400000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37400000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1037,7 +1078,7 @@ - - gmac3: ethernet@37600000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37600000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -1065,8 +1106,6 @@ - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; -- -- status = "disabled"; - }; - - ss_phy_0: phy@100f8830 { -@@ -1075,8 +1114,6 @@ - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; -- -- status = "disabled"; - }; - - usb3_0: usb3@100f8800 { -@@ -1176,7 +1213,7 @@ - }; - - amba: amba { -- compatible = "simple-bus"; -+ compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -1195,7 +1232,6 @@ - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; -- mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; diff --git a/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch b/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch deleted file mode 100644 index adc784fcfc..0000000000 --- a/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch +++ /dev/null @@ -1,371 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -10,6 +10,8 @@ - #include - #include - #include -+#include -+#include - - / { - #address-cells = <1>; -@@ -30,6 +32,16 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; -+ clocks = <&kraitcc 0>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2a>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; - }; - - cpu1: cpu@1 { -@@ -40,11 +52,125 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; -+ clocks = <&kraitcc 1>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2b>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; -+ }; -+ -+ idle-states { -+ CPU_SPC: spc { -+ compatible = "qcom,idle-state-spc"; -+ status = "disabled"; -+ entry-latency-us = <400>; -+ exit-latency-us = <900>; -+ min-residency-us = <3000>; -+ }; - }; -+ }; - -- L2: l2-cache { -- compatible = "cache"; -- cache-level = <2>; -+ opp_table_l2: opp_table_l2 { -+ compatible = "operating-points-v2"; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ opp_table0: opp_table0 { -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&speedbin_efuse>; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; -+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; -+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; -+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; -+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; - }; - }; - -@@ -317,6 +443,15 @@ - }; - }; - -+ fab-scaling { -+ compatible = "qcom,fab-scaling"; -+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; -+ clock-names = "apps-fab-clk", "ddr-fab-clk"; -+ fab_freq_high = <533000000>; -+ fab_freq_nominal = <400000000>; -+ cpu_freq_threshold = <1000000000>; -+ }; -+ - firmware { - scm { - compatible = "qcom,scm-ipq806x", "qcom,scm"; -@@ -384,6 +519,15 @@ - }; - }; - -+ i2c4_pins: i2c4_pinmux { -+ mux { -+ pins = "gpio12", "gpio13"; -+ function = "gsbi4"; -+ drive-strength = <12>; -+ bias-disable; -+ }; -+ }; -+ - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; -@@ -437,6 +581,27 @@ - bias-bus-hold; - }; - }; -+ -+ mdio0_pins: mdio0_pins { -+ mux { -+ pins = "gpio0", "gpio1"; -+ function = "mdio"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; -+ -+ rgmii2_pins: rgmii2_pins { -+ mux { -+ pins = "gpio27", "gpio28", "gpio29", -+ "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", -+ "gpio60", "gpio61", "gpio62"; -+ function = "rgmii2"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; - }; - - intc: interrupt-controller@2000000 { -@@ -513,6 +678,17 @@ - regulator; - }; - -+ saw_l2: regulator@02012000 { -+ compatible = "qcom,saw2", "syscon"; -+ reg = <0x02012000 0x1000>; -+ regulator; -+ }; -+ -+ sic_non_secure: sic-non-secure@12100000 { -+ compatible = "syscon"; -+ reg = <0x12100000 0x10000>; -+ }; -+ - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; -@@ -637,6 +813,33 @@ - }; - }; - -+ gsbi6: gsbi@16500000 { -+ status = "disabled"; -+ compatible = "qcom,gsbi-v1.0.0"; -+ cell-index = <6>; -+ reg = <0x16500000 0x100>; -+ clocks = <&gcc GSBI6_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ gsbi6_i2c: i2c@16580000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16580000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; -@@ -658,6 +861,19 @@ - clock-names = "core", "iface"; - status = "disabled"; - }; -+ -+ gsbi7_i2c: i2c@16680000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16680000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; - }; - - rng@1a500000 { -@@ -761,6 +977,17 @@ - }; - }; - -+ L2: l2-cache { -+ compatible = "qcom,krait-cache", "cache"; -+ cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ l2-supply = <&smb208_s1a>; -+ operating-points-v2 = <&opp_table_l2>; -+ }; -+ - rpm: rpm@108000 { - compatible = "qcom,rpm-ipq8064"; - reg = <0x108000 0x1000>; -@@ -828,6 +1055,11 @@ - clock-output-names = "acpu_l2_aux"; - }; - -+ kraitcc: clock-controller { -+ compatible = "qcom,krait-cc-v1"; -+ #clock-cells = <1>; -+ }; -+ - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; -@@ -835,6 +1067,11 @@ - #reset-cells = <1>; - }; - -+ sfpb_mutex_block: syscon@1200600 { -+ compatible = "syscon"; -+ reg = <0x01200600 0x100>; -+ }; -+ - pcie0: pci@1b500000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b500000 0x1000 -@@ -1184,6 +1421,21 @@ - }; - }; - -+ -+ mdio0: mdio@37000000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "qcom,ipq8064-mdio", "syscon"; -+ reg = <0x37000000 0x200000>; -+ resets = <&gcc GMAC_CORE1_RESET>; -+ reset-names = "stmmaceth"; -+ clocks = <&gcc GMAC_CORE1_CLK>; -+ clock-names = "stmmaceth"; -+ -+ status = "disabled"; -+ }; -+ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; -@@ -1258,4 +1510,17 @@ - }; - }; - }; -+ -+ sfpb_mutex: sfpb-mutex { -+ compatible = "qcom,sfpb-mutex"; -+ syscon = <&sfpb_mutex_block 4 4>; -+ -+ #hwlock-cells = <1>; -+ }; -+ -+ smem { -+ compatible = "qcom,smem"; -+ memory-region = <&smem>; -+ hwlocks = <&sfpb_mutex 3>; -+ }; - }; diff --git a/target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch b/target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch deleted file mode 100644 index 44323a1561..0000000000 --- a/target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch +++ /dev/null @@ -1,89 +0,0 @@ -This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches -instead of keeping a local version. -We drop partitions, LEDs and keys from the file as we will implement -them differently anyway. - ---- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -@@ -42,16 +42,6 @@ - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; -- -- partition@0 { -- label = "rootfs"; -- reg = <0x0 0x1000000>; -- }; -- -- partition@1 { -- label = "scratch"; -- reg = <0x1000000 0x1000000>; -- }; - }; - }; - }; -@@ -64,64 +54,5 @@ - ports-implemented = <0x1>; - status = "okay"; - }; -- -- gpio_keys { -- compatible = "gpio-keys"; -- pinctrl-0 = <&buttons_pins>; -- pinctrl-names = "default"; -- -- button@1 { -- label = "reset"; -- linux,code = ; -- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; -- linux,input-type = <1>; -- debounce-interval = <60>; -- }; -- button@2 { -- label = "wps"; -- linux,code = ; -- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; -- linux,input-type = <1>; -- debounce-interval = <60>; -- }; -- }; -- -- leds { -- compatible = "gpio-leds"; -- pinctrl-0 = <&leds_pins>; -- pinctrl-names = "default"; -- -- led@7 { -- label = "led_usb1"; -- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "usbdev"; -- default-state = "off"; -- }; -- -- led@8 { -- label = "led_usb3"; -- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "usbdev"; -- default-state = "off"; -- }; -- -- led@9 { -- label = "status_led_fail"; -- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- -- led@26 { -- label = "sata_led"; -- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- -- led@53 { -- label = "status_led_pass"; -- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- }; - }; - }; diff --git a/target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch b/target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch deleted file mode 100644 index 58f6a46e4f..0000000000 --- a/target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch +++ /dev/null @@ -1,14 +0,0 @@ -This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches -instead of keeping a local version. This patch adds our local adjustments -for the (local) additional contents of qcom-ipq8064.dtsi - ---- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -@@ -56,3 +56,7 @@ - }; - }; - }; -+ -+&CPU_SPC { -+ status = "okay"; -+}; diff --git a/target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch b/target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch new file mode 100644 index 0000000000..0c25062214 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/103-01-ARM-dts-qcom-replace-gcc-PXO-with-pxo_board-fixed.patch @@ -0,0 +1,36 @@ +From 5a8aa766cedac0ceaa4beabc30e9fa62dd9f1ac1 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Fri, 29 Apr 2022 14:23:16 +0200 +Subject: [PATCH v2 1/2] ARM: dts: qcom: replace gcc PXO with pxo_board fixed + clock + +Replace gcc PXO phandle to pxo_board fixed clock declared in the dts. +gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a +kernel panic if any driver actually try to use it. + +Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064") +Signed-off-by: Ansuel Smith +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -304,7 +304,7 @@ + clock-frequency = <25000000>; + }; + +- pxo_board { ++ pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +@@ -782,7 +782,7 @@ + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; +- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; ++ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + }; diff --git a/target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch b/target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch new file mode 100644 index 0000000000..db23af128f --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/103-v5.19-02-ARM-dts-qcom-add-syscon-and-cxo-pxo-clock-to-gcc-.patch @@ -0,0 +1,39 @@ +From 9fa82f98cb85e5432060f469253adcf14fa38082 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Mon, 17 Jan 2022 21:59:39 +0100 +Subject: [PATCH v2 2/2] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc + node for ipq8064 + +Add syscon compatible required for tsens driver to correctly probe driver +and access the reg. Also add cxo and pxo tag and declare them as gcc clock +now requires them for the ipq8064 gcc driver that has now been modernized. + +Signed-off-by: Ansuel Smith +Reviewed-by: Bjorn Andersson +Reviewed-by: Stephen Boyd +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -298,7 +298,7 @@ + }; + + clocks { +- cxo_board { ++ cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +@@ -736,7 +736,9 @@ + }; + + gcc: clock-controller@900000 { +- compatible = "qcom,gcc-ipq8064"; ++ compatible = "qcom,gcc-ipq8064", "syscon"; ++ clocks = <&pxo_board>, <&cxo_board>; ++ clock-names = "pxo", "cxo"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch new file mode 100644 index 0000000000..5dad164e3c --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-01-ARM-dts-qcom-ipq8064-add-multiple-missing-pin-defini.patch @@ -0,0 +1,101 @@ +From 4af1defb305798d1a064a5ea0d0c9b30e5eee185 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:35 +0200 +Subject: [PATCH 1/8] ARM: dts: qcom: ipq8064: add multiple missing pin + definition + +Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4 +pins and rgmii2 pins for ipq8064. + +Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064 +dtsi. + +Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to +ipq8064 dtsi. + +Signed-off-by: Christian Marangi +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-2-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 ----- + arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 ------- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++ + 3 files changed, 32 insertions(+), 15 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +@@ -305,15 +305,6 @@ + }; + }; + +- mdio0_pins: mdio0_pins { +- mux { +- pins = "gpio0", "gpio1"; +- function = "gpio"; +- drive-strength = <8>; +- bias-disable; +- }; +- }; +- + mdio1_pins: mdio1_pins { + mux { + pins = "gpio10", "gpio11"; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -382,6 +382,13 @@ + }; + }; + ++ i2c4_pins: i2c4-default { ++ pins = "gpio12", "gpio13"; ++ function = "gsbi4"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; +@@ -424,6 +431,8 @@ + + pullups { + pins = "gpio39"; ++ function = "nand"; ++ drive-strength = <10>; + bias-pull-up; + }; + +@@ -431,9 +440,32 @@ + pins = "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; ++ function = "nand"; ++ drive-strength = <10>; + bias-bus-hold; + }; + }; ++ ++ mdio0_pins: mdio0-pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "mdio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ rgmii2_pins: rgmii2-pins { ++ mux { ++ pins = "gpio27", "gpio28", "gpio29", ++ "gpio30", "gpio31", "gpio32", ++ "gpio51", "gpio52", "gpio59", ++ "gpio60", "gpio61", "gpio62"; ++ function = "rgmii2"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + intc: interrupt-controller@2000000 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch new file mode 100644 index 0000000000..1f4e288fb8 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-02-ARM-dts-qcom-ipq8064-add-gsbi6-missing-definition.patch @@ -0,0 +1,67 @@ +From d883a12a547b6d42e795ff3b5ac87cfd013b5423 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:36 +0200 +Subject: [PATCH 2/8] ARM: dts: qcom: ipq8064: add gsbi6 missing definition + +Add gsbi6 missing definition for ipq8064. + +Signed-off-by: Christian Marangi +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-3-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 43 +++++++++++++++++++++++++++++ + 1 file changed, 43 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -663,6 +663,49 @@ + }; + }; + ++ gsbi6: gsbi@16500000 { ++ compatible = "qcom,gsbi-v1.0.0"; ++ reg = <0x16500000 0x100>; ++ cell-index = <6>; ++ clocks = <&gcc GSBI6_H_CLK>; ++ clock-names = "iface"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ syscon-tcsr = <&tcsr>; ++ ++ status = "disabled"; ++ ++ gsbi6_i2c: i2c@16580000 { ++ compatible = "qcom,i2c-qup-v1.1.1"; ++ reg = <0x16580000 0x1000>; ++ interrupts = ; ++ ++ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; ++ clock-names = "core", "iface"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ gsbi6_spi: spi@16580000 { ++ compatible = "qcom,spi-qup-v1.1.1"; ++ reg = <0x16580000 0x1000>; ++ interrupts = ; ++ ++ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; ++ clock-names = "core", "iface"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ }; ++ + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch new file mode 100644 index 0000000000..dbba722caa --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-03-ARM-dts-qcom-ipq8064-add-specific-dtsi-with-smb208-r.patch @@ -0,0 +1,66 @@ +From 5c47a46d5e942ea6b041c8b7727b201817c1ff76 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:37 +0200 +Subject: [PATCH 3/8] ARM: dts: qcom: ipq8064: add specific dtsi with smb208 + rpm regulators + +Add specific ipq8064 dtsi with smb208 rpm regulators. + +Qcom advise to use this configuration but it's not mandatory and OEM +can decide to implement their own regulators. +smb208 regulators are used to scale CPU voltage, L2 cache voltage and +Ubi32 cores. + +There regulators are controlled by rpm and to correctly works gsbi4-i2c +require to be NEVER disabled or rpm will reject any regulator change +request. + +Signed-off-by: Christian Marangi +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-4-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 ++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8064.dtsi" ++ ++&rpm { ++ smb208_regulators: regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++}; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch new file mode 100644 index 0000000000..1a3185f500 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-04-ARM-dts-qcom-ipq8064-add-missing-snps-dwmac-compatib.patch @@ -0,0 +1,56 @@ +From 0ce34e0c13e99c239cce6099f64b0e95697f36b1 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:38 +0200 +Subject: [PATCH 4/8] ARM: dts: qcom: ipq8064: add missing snps,dwmac + compatible for gmac + +Add missing snps,dwmac compatible for gmac ipq8064 dtsi. + +Signed-off-by: Christian Marangi +Tested-by: Jonathan McDowell +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-5-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1042,7 +1042,7 @@ + + gmac0: ethernet@37000000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; +@@ -1066,7 +1066,7 @@ + + gmac1: ethernet@37200000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37200000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; +@@ -1090,7 +1090,7 @@ + + gmac2: ethernet@37400000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37400000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; +@@ -1114,7 +1114,7 @@ + + gmac3: ethernet@37600000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37600000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch new file mode 100644 index 0000000000..43dac4b7fa --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-05-ARM-dts-qcom-ipq8064-disable-usb-phy-by-default.patch @@ -0,0 +1,37 @@ +From d63d3124c0a5cdbe8b91d81b922fe56b2462e1b9 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:39 +0200 +Subject: [PATCH 5/8] ARM: dts: qcom: ipq8064: disable usb phy by default + +Disable usb phy by default. When the usb phy were pushed, half of them +were flagged as disabled by mistake. +Correctly disable all usb phy and enable them only if a device actually +use them. + +Signed-off-by: Christian Marangi +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-6-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1188,6 +1188,8 @@ + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; ++ ++ status = "disabled"; + }; + + ss_phy_1: phy@110f8830 { +@@ -1196,6 +1198,8 @@ + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; ++ ++ status = "disabled"; + }; + + usb3_1: usb3@110f8800 { diff --git a/target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-06-ARM-dts-qcom-ipq8064-reduce-pci-IO-size-to-64K.patch similarity index 72% rename from target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch rename to target/linux/ipq806x/patches-5.15/104-v6.0-06-ARM-dts-qcom-ipq8064-reduce-pci-IO-size-to-64K.patch index 1f61fdf886..b1fca01c5e 100644 --- a/target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-06-ARM-dts-qcom-ipq8064-reduce-pci-IO-size-to-64K.patch @@ -1,8 +1,10 @@ -From 84909e85881d67244240c9f40974ce12a51e3886 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 11 May 2021 23:09:45 +0200 -Subject: [PATCH] ARM: dts: qcom: reduce pci IO size to 64K +From 8fafb7e5c041814876266259e5e439f93571dcef Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:40 +0200 +Subject: [PATCH 6/8] ARM: dts: qcom: ipq8064: reduce pci IO size to 64K +The current value for pci IO is problematic for ath10k wifi card +commonly connected to ipq8064 SoC. The current value is probably a typo and is actually uncommon to find 1MB IO space even on a x86 arch. Also with recent changes to the pci driver, pci1 and pci2 now fails to function as any connected device @@ -10,14 +12,17 @@ fails any reg read/write. Reduce this to 64K as it should be more than enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT hardcoded for the ARM arch. -Signed-off-by: Ansuel Smith +Signed-off-by: Christian Marangi +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-7-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1086,7 +1086,7 @@ +@@ -885,7 +885,7 @@ #address-cells = <3>; #size-cells = <2>; @@ -26,7 +31,7 @@ Signed-off-by: Ansuel Smith 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ interrupts = ; -@@ -1137,7 +1137,7 @@ +@@ -936,7 +936,7 @@ #address-cells = <3>; #size-cells = <2>; @@ -35,7 +40,7 @@ Signed-off-by: Ansuel Smith 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = ; -@@ -1188,7 +1188,7 @@ +@@ -987,7 +987,7 @@ #address-cells = <3>; #size-cells = <2>; diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch new file mode 100644 index 0000000000..ca5e5aa3c4 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-07-ARM-dts-qcom-ipq8064-fix-and-add-some-missing-gsbi-n.patch @@ -0,0 +1,94 @@ +From 6c421a9c08286389bb331fe783e2625c9efcc187 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:41 +0200 +Subject: [PATCH 7/8] ARM: dts: qcom: ipq8064: fix and add some missing gsbi + node + +Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing +gsbi7 i2c node and gsbi1 node. + +Signed-off-by: Christian Marangi +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++- + 1 file changed, 53 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -539,6 +539,44 @@ + regulator; + }; + ++ gsbi1: gsbi@12440000 { ++ compatible = "qcom,gsbi-v1.0.0"; ++ reg = <0x12440000 0x100>; ++ cell-index = <1>; ++ clocks = <&gcc GSBI1_H_CLK>; ++ clock-names = "iface"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ syscon-tcsr = <&tcsr>; ++ ++ status = "disabled"; ++ ++ gsbi1_serial: serial@12450000 { ++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; ++ reg = <0x12450000 0x100>, ++ <0x12400000 0x03>; ++ interrupts = ; ++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; ++ clock-names = "core", "iface"; ++ ++ status = "disabled"; ++ }; ++ ++ gsbi1_i2c: i2c@12460000 { ++ compatible = "qcom,i2c-qup-v1.1.1"; ++ reg = <0x12460000 0x1000>; ++ interrupts = ; ++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; ++ clock-names = "core", "iface"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ }; ++ + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; +@@ -562,7 +600,7 @@ + status = "disabled"; + }; + +- i2c@124a0000 { ++ gsbi2_i2c: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + interrupts = ; +@@ -727,6 +765,20 @@ + clock-names = "core", "iface"; + status = "disabled"; + }; ++ ++ gsbi7_i2c: i2c@16680000 { ++ compatible = "qcom,i2c-qup-v1.1.1"; ++ reg = <0x16680000 0x1000>; ++ interrupts = ; ++ ++ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; ++ clock-names = "core", "iface"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "disabled"; ++ }; + }; + + rng@1a500000 { diff --git a/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch b/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch new file mode 100644 index 0000000000..463c3d4a65 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/104-v6.0-08-ARM-dts-qcom-ipq8064-add-speedbin-efuse-nvmem-node.patch @@ -0,0 +1,28 @@ +From 7f5aecdd4ffcc018f73171bc0e028cd4e3361acd Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 03:09:43 +0200 +Subject: [PATCH 8/8] ARM: dts: qcom: ipq8064: add speedbin efuse nvmem node + +Add speedbin efuse nvmem cell needed for the opp table for the CPU +freqs. + +Signed-off-by: Christian Marangi +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707010943.20857-10-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -854,6 +854,9 @@ + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ speedbin_efuse: speedbin@c0 { ++ reg = <0xc0 0x4>; ++ }; + tsens_calib: calib@400 { + reg = <0x400 0xb>; + }; diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch new file mode 100644 index 0000000000..2c6f6b10c4 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/105-v6.0-01-hwspinlock-qcom-Add-support-for-mmio-usage-to-sfpb-m.patch @@ -0,0 +1,71 @@ +From cdab30b44518513003607ecfc8a22de3dbbb78ed Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 12:20:38 +0200 +Subject: [PATCH 1/1] hwspinlock: qcom: Add support for mmio usage to + sfpb-mutex + +Allow sfpb-mutex to use mmio in addition to syscon. + +Signed-off-by: Christian Marangi +Reviewed-by: Bjorn Andersson +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707102040.1859-1-ansuelsmth@gmail.com +--- + drivers/hwspinlock/qcom_hwspinlock.c | 28 +++++++++++++++++++++++----- + 1 file changed, 23 insertions(+), 5 deletions(-) + +--- a/drivers/hwspinlock/qcom_hwspinlock.c ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -19,6 +19,11 @@ + #define QCOM_MUTEX_APPS_PROC_ID 1 + #define QCOM_MUTEX_NUM_LOCKS 32 + ++struct qcom_hwspinlock_of_data { ++ u32 offset; ++ u32 stride; ++}; ++ + static int qcom_hwspinlock_trylock(struct hwspinlock *lock) + { + struct regmap_field *field = lock->priv; +@@ -63,9 +68,20 @@ static const struct hwspinlock_ops qcom_ + .unlock = qcom_hwspinlock_unlock, + }; + ++static const struct qcom_hwspinlock_of_data of_sfpb_mutex = { ++ .offset = 0x4, ++ .stride = 0x4, ++}; ++ ++/* All modern platform has offset 0 and stride of 4k */ ++static const struct qcom_hwspinlock_of_data of_tcsr_mutex = { ++ .offset = 0, ++ .stride = 0x1000, ++}; ++ + static const struct of_device_id qcom_hwspinlock_of_match[] = { +- { .compatible = "qcom,sfpb-mutex" }, +- { .compatible = "qcom,tcsr-mutex" }, ++ { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, ++ { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, + { } + }; + MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); +@@ -112,12 +128,14 @@ static const struct regmap_config tcsr_m + static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev, + u32 *offset, u32 *stride) + { ++ const struct qcom_hwspinlock_of_data *data; + struct device *dev = &pdev->dev; + void __iomem *base; + +- /* All modern platform has offset 0 and stride of 4k */ +- *offset = 0; +- *stride = 0x1000; ++ data = of_device_get_match_data(dev); ++ ++ *offset = data->offset; ++ *stride = data->stride; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch new file mode 100644 index 0000000000..d8303442f7 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/105-v6.0-02-ARM-dts-qcom-ipq8064-add-missing-hwlock.patch @@ -0,0 +1,31 @@ +From fbe4be367b2169602f6a5949a20d2917b25714d4 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 12:20:39 +0200 +Subject: [PATCH 1/2] ARM: dts: qcom: ipq8064: add missing hwlock + +Add missing hwlock for ipq8064 dtsi provided by qcom,sfpb-mutex. + +Signed-off-by: Christian Marangi +Acked-by: Krzysztof Kozlowski +[bjorn: Moved the node inside /soc] +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707102040.1859-2-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1357,5 +1357,12 @@ + dma-names = "tx", "rx"; + }; + }; ++ ++ sfpb_mutex: hwlock@1200600 { ++ compatible = "qcom,sfpb-mutex"; ++ reg = <0x01200600 0x100>; ++ ++ #hwlock-cells = <1>; ++ }; + }; + }; diff --git a/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch b/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch new file mode 100644 index 0000000000..8b91eeb511 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/105-v6.0-03-ARM-dts-qcom-ipq8064-add-missing-smem-compatible.patch @@ -0,0 +1,30 @@ +From 4fefb5434c4b735daf913abaef12431405368031 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 7 Jul 2022 12:20:40 +0200 +Subject: [PATCH 2/2] ARM: dts: qcom: ipq8064: add missing smem compatible + +Add missing smem compatible and hwlocks phandle for ipq8064 dtsi +smem node. + +Signed-off-by: Christian Marangi +Acked-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220707102040.1859-3-ansuelsmth@gmail.com +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -292,8 +292,11 @@ + }; + + smem: smem@41000000 { ++ compatible = "qcom,smem"; + reg = <0x41000000 0x200000>; + no-map; ++ ++ hwlocks = <&sfpb_mutex 3>; + }; + }; + diff --git a/target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch b/target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch new file mode 100644 index 0000000000..8b20a550f6 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/106-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch @@ -0,0 +1,129 @@ +From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 18 Jul 2022 18:05:16 +0200 +Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant + +Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for +some additional pcie, sata and usb configuration values, additional +reserved memory and serial output. + +Signed-off-by: Christian Marangi +--- + .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++ + arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++ + 2 files changed, 106 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8064-v2.0.dtsi" ++ ++&rpm { ++ smb208_regulators: regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi +@@ -0,0 +1,69 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8064.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; ++ ++ aliases { ++ serial0 = &gsbi4_serial; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ rsvd@41200000 { ++ reg = <0x41200000 0x300000>; ++ no-map; ++ }; ++ }; ++}; ++ ++&gsbi4 { ++ qcom,mode = ; ++ status = "okay"; ++ ++ serial@16340000 { ++ status = "okay"; ++ }; ++ /* ++ * The i2c device on gsbi4 should not be enabled. ++ * On ipq806x designs gsbi4 i2c is meant for exclusive ++ * RPM usage. Turning this on in kernel manifests as ++ * i2c failure for the RPM. ++ */ ++}; ++ ++&pcie0 { ++ compatible = "qcom,pcie-ipq8064-v2"; ++}; ++ ++&pcie1 { ++ compatible = "qcom,pcie-ipq8064-v2"; ++}; ++ ++&pcie2 { ++ compatible = "qcom,pcie-ipq8064-v2"; ++}; ++ ++&sata { ++ ports-implemented = <0x1>; ++}; ++ ++&ss_phy_0 { ++ qcom,rx-eq = <2>; ++ qcom,tx-deamp_3_5db = <32>; ++ qcom,mpll = <5>; ++}; ++ ++&ss_phy_1 { ++ qcom,rx-eq = <2>; ++ qcom,tx-deamp_3_5db = <32>; ++ qcom,mpll = <5>; ++}; diff --git a/target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch b/target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch new file mode 100644 index 0000000000..fdff292480 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/106-02-ARM-dts-qcom-ipq8064-add-ipq8062-variant.patch @@ -0,0 +1,67 @@ +From 41d9fa8de7845bd92d9c963196fdfd7ea9232bb2 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 18 Jul 2022 18:07:26 +0200 +Subject: [PATCH 2/3] ARM: dts: qcom: ipq8064: add ipq8062 variant + +ipq8062 SoC is based on ipq8064-v2.0 with lower supported freq, lack of +usb port and a reduced voltage output with the smb208 regulators. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 ++++++++++++++++++++++ + arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 +++++ + 2 files changed, 45 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi + create mode 100644 arch/arm/boot/dts/qcom-ipq8062.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include "qcom-ipq8062.dtsi" ++ ++&rpm { ++ smb208_regulators: regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include "qcom-ipq8064-v2.0.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ8062"; ++ compatible = "qcom,ipq8062", "qcom,ipq8064"; ++}; diff --git a/target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch b/target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch new file mode 100644 index 0000000000..bccc577b91 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/106-03-ARM-dts-qcom-ipq8064-add-ipq8065-variant.patch @@ -0,0 +1,67 @@ +From 01e7aa3fe6f76f7960f2382038136235eee9c6cd Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 18 Jul 2022 18:09:35 +0200 +Subject: [PATCH 3/3] ARM: dts: qcom: ipq8064: add ipq8065 variant + +ipq8065 SoC is based on ipq8064-v2.0 with a more clocked CPU and +an increased voltage output with the smb208 regulators. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 ++++++++++++++++++++++ + arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 +++++ + 2 files changed, 45 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi + create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8065.dtsi" ++ ++&rpm { ++ smb208_regulators: regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = <775000>; ++ regulator-max-microvolt = <1275000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = <775000>; ++ regulator-max-microvolt = <1275000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "qcom-ipq8064-v2.0.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ8065"; ++ compatible = "qcom,ipq8065", "qcom,ipq8064"; ++}; diff --git a/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch new file mode 100644 index 0000000000..12e4874f6b --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch @@ -0,0 +1,95 @@ +From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Mon, 17 Jan 2022 23:39:34 +0100 +Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for + ipq8064 + +Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi. +Also declare clock-output-names for acc0 and acc1 and qsb fixed clock +for the secondary mux. + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++-- + 1 file changed, 32 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -301,6 +301,12 @@ + }; + + clocks { ++// qsb: qsb { ++// compatible = "fixed-clock"; ++// clock-frequency = <384000000>; ++// #clock-cells = <0>; ++// }; ++ + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -503,11 +509,19 @@ + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu0_aux"; ++ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; ++ clock-names = "pll8_vote", "pxo"; ++ #clock-cells = <0>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu1_aux"; ++ clocks = <&gcc PLL8_VOTE>, <&pxo_board>; ++ clock-names = "pll8_vote", "pxo"; ++ #clock-cells = <0>; + }; + + adm_dma: dma-controller@18300000 { +@@ -531,17 +545,23 @@ + }; + + saw0: regulator@2089000 { +- compatible = "qcom,saw2"; ++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { +- compatible = "qcom,saw2"; ++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + ++ saw_l2: regulator@02012000 { ++ compatible = "qcom,saw2", "syscon"; ++ reg = <0x02012000 0x1000>; ++ regulator; ++ }; ++ + gsbi1: gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; +@@ -920,6 +940,17 @@ + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; ++ #clock-cells = <0>; ++ }; ++ ++ kraitcc: clock-controller { ++ compatible = "qcom,krait-cc-v1"; ++ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, ++ <&acc0>, <&acc1>, <&l2cc>; // <&qsb> ++ clock-names = "hfpll0", "hfpll1", "hfpll_l2", ++ "acpu0_aux", "acpu1_aux", "acpu_l2_aux"; ++// "qsb"; ++ #clock-cells = <1>; + }; + + lcc: clock-controller@28000000 { diff --git a/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch b/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch new file mode 100644 index 0000000000..f3c8f18f1d --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch @@ -0,0 +1,268 @@ +From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 18 Jan 2022 00:03:47 +0100 +Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for + ipq8064 + +Add opp table for cpu and l2 cache. While the current cpufreq is +the generic one that doesn't scale the L2 cache, we add the l2 +cache opp anyway for the sake of completeness. This will be handy in the +future when a dedicated cpufreq driver is introduced for krait cores +that will correctly scale l2 cache with the core freq. + +Opp-level is set based on the logic of +0: idle level +1: normal level +2: turbo level + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++ + 1 file changed, 99 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -48,6 +48,105 @@ + }; + }; + ++ opp_table_l2: opp_table_l2 { ++ compatible = "operating-points-v2"; ++ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <100000>; ++ opp-level = <0>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1150000>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ }; ++ ++ opp_table0: opp_table0 { ++ compatible = "operating-points-v2-kryo-cpu"; ++ nvmem-cells = <&speedbin_efuse>; ++ ++ /* ++ * Voltage thresholds are ++ */ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; ++ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <0>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; ++ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; ++ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ ++ opp-1400000000 { ++ opp-hz = /bits/ 64 <1400000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; ++ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; ++ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ }; ++ + thermal-zones { + tsens_tz_sensor0 { + polling-delay-passive = <0>; +--- a/arch/arm/boot/dts/qcom-ipq8065.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi +@@ -6,3 +6,92 @@ + model = "Qualcomm Technologies, Inc. IPQ8065"; + compatible = "qcom,ipq8065", "qcom,ipq8064"; + }; ++ ++&opp_table_l2 { ++ /delete-node/opp-1200000000; ++ ++ opp-1400000000 { ++ opp-hz = /bits/ 64 <1400000000>; ++ opp-microvolt = <1150000>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++}; ++ ++&opp_table0 { ++ /* ++ * On ipq8065 1.2 ghz freq is not present ++ * Remove it to make cpufreq work and not ++ * complain for missing definition ++ */ ++ ++ /delete-node/opp-1200000000; ++ ++ /* ++ * Voltage thresholds are ++ */ ++ opp-384000000 { ++ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; ++ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; ++ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; ++ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; ++ }; ++ ++ opp-600000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; ++ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; ++ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; ++ }; ++ ++ opp-800000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; ++ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; ++ }; ++ ++ opp-1000000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; ++ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; ++ }; ++ ++ opp-1400000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; ++ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; ++ opp-level = <1>; ++ }; ++ ++ opp-1725000000 { ++ opp-hz = /bits/ 64 <1725000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; ++ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; ++ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; ++ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; ++ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++}; +--- a/arch/arm/boot/dts/qcom-ipq8062.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi +@@ -6,3 +6,39 @@ + model = "Qualcomm Technologies, Inc. IPQ8062"; + compatible = "qcom,ipq8062", "qcom,ipq8064"; + }; ++ ++&opp_table0 { ++ /delete-node/opp-1200000000; ++ /delete-node/opp-1400000000; ++ ++ /* ++ * Voltage thresholds are ++ */ ++ opp-384000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>; ++ opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>; ++ opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>; ++ }; ++ ++ opp-600000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>; ++ opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>; ++ opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>; ++ }; ++ ++ opp-800000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>; ++ opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>; ++ }; ++ ++ opp-1000000000 { ++ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>; ++ }; ++}; diff --git a/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch b/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch new file mode 100644 index 0000000000..cf27aaa08b --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch @@ -0,0 +1,153 @@ +From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 18 Jan 2022 00:07:57 +0100 +Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu + and l2 for ipq8064 + +Add multiple binding for cpu node, l2 node and add idle-states +definition for ipq8064 dtsi. + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -30,6 +30,15 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; ++ clocks = <&kraitcc 0>, <&kraitcc 4>; ++ clock-names = "cpu", "l2"; ++ clock-latency = <100000>; ++ operating-points-v2 = <&opp_table0>; ++ voltage-tolerance = <5>; ++ cooling-min-state = <0>; ++ cooling-max-state = <10>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SPC>; + }; + + cpu1: cpu@1 { +@@ -40,11 +49,35 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; ++ clocks = <&kraitcc 1>, <&kraitcc 4>; ++ clock-names = "cpu", "l2"; ++ clock-latency = <100000>; ++ operating-points-v2 = <&opp_table0>; ++ voltage-tolerance = <5>; ++ cooling-min-state = <0>; ++ cooling-max-state = <10>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SPC>; ++ }; ++ ++ idle-states { ++ CPU_SPC: spc { ++ compatible = "qcom,idle-state-spc"; ++ status = "disabled"; ++ entry-latency-us = <400>; ++ exit-latency-us = <900>; ++ min-residency-us = <3000>; ++ }; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; ++ qcom,saw = <&saw_l2>; ++ ++ clocks = <&kraitcc 4>; ++ clock-names = "l2"; ++ operating-points-v2 = <&opp_table_l2>; + }; + }; + +--- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8064.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; +--- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8064-v2.0.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; +--- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8062.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; +--- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi +@@ -2,6 +2,18 @@ + + #include "qcom-ipq8065.dtsi" + ++&cpu0 { ++ cpu-supply = <&smb208_s2a>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&smb208_s2b>; ++}; ++ ++&L2 { ++ l2-supply = <&smb208_s1a>; ++}; ++ + &rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; diff --git a/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch b/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch new file mode 100644 index 0000000000..d3f821a6a0 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch @@ -0,0 +1,29 @@ +From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Wed, 15 Jun 2022 16:47:09 +0200 +Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x + +Fix wrong nand_pings definition for bias-disable pins. + +Signed-off-by: Christian 'Ansuel' Marangi +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -559,12 +559,9 @@ + }; + + nand_pins: nand_pins { +- mux { ++ disable { + pins = "gpio34", "gpio35", "gpio36", +- "gpio37", "gpio38", "gpio39", +- "gpio40", "gpio41", "gpio42", +- "gpio43", "gpio44", "gpio45", +- "gpio46", "gpio47"; ++ "gpio37", "gpio38"; + function = "nand"; + drive-strength = <10>; + bias-disable; diff --git a/target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch b/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch similarity index 63% rename from target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch rename to target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch index e4aefe171a..4a57fc0330 100644 --- a/target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch +++ b/target/linux/ipq806x/patches-5.15/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch @@ -1,3 +1,18 @@ +From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Wed, 15 Jun 2022 16:59:30 +0200 +Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for + ipq806x + +Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to +correctly use the new tag. + +Signed-off-by: Christian 'Ansuel' Marangi +--- + arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++----------- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++ + 2 files changed, 81 insertions(+), 67 deletions(-) + --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -24,73 +24,6 @@ @@ -74,12 +89,17 @@ mdio1: mdio-1 { status = "okay"; compatible = "virtual,mdio-gpio"; -@@ -220,6 +153,68 @@ +@@ -220,6 +153,73 @@ status = "okay"; }; +&mdio0 { + status = "okay"; ++ compatible = "virtual,mdio-gpio"; ++ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, ++ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; ++ #address-cells = <1>; ++ #size-cells = <0>; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; @@ -143,3 +163,26 @@ &gmac0 { status = "okay"; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1446,6 +1446,20 @@ + }; + }; + ++ mdio0: mdio@37000000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ compatible = "qcom,ipq8064-mdio", "syscon"; ++ reg = <0x37000000 0x200000>; ++ resets = <&gcc GMAC_CORE1_RESET>; ++ reset-names = "stmmaceth"; ++ clocks = <&gcc GMAC_CORE1_CLK>; ++ clock-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; diff --git a/target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch b/target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch deleted file mode 100644 index b7c198c126..0000000000 --- a/target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -689,6 +689,41 @@ - reg = <0x12100000 0x10000>; - }; - -+ gsbi1: gsbi@12440000 { -+ compatible = "qcom,gsbi-v1.0.0"; -+ cell-index = <1>; -+ reg = <0x12440000 0x100>; -+ clocks = <&gcc GSBI1_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ gsbi1_serial: serial@12450000 { -+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; -+ reg = <0x12450000 0x100>, -+ <0x12400000 0x03>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ gsbi1_i2c: i2c@12460000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x12460000 0x1000>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; From 61a2bedf7902c64a47a42a3d8df3350f1b67ee2f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:13:02 +0200 Subject: [PATCH 25/43] ipq806x: 5.15: replace lcc patch with upstream version Replace lcc patch with proposed upstream version. Signed-off-by: Christian Marangi --- .../097-2-ipq806x-lcc-add-missing-reset.patch | 59 ----- ...-clock-add-pcm-reset-for-ipq806x-lcc.patch | 29 +++ ...com-lcc-ipq806x-add-reset-definition.patch | 48 ++++ ...m-lcc-ipq806x-convert-to-parent-data.patch | 217 ++++++++++++++++++ 4 files changed, 294 insertions(+), 59 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch create mode 100644 target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch create mode 100644 target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch create mode 100644 target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch diff --git a/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch b/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch deleted file mode 100644 index cd2cb33356..0000000000 --- a/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 17:00:07 +0100 -Subject: [PATCH 2/4] ipq806x: lcc: add missing reset - -Add missing reset for ipq806x lcc clk - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/lcc-ipq806x.c | 8 ++++++++ - include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 + - 2 files changed, 9 insertions(+) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #include - -@@ -22,6 +23,7 @@ - #include "clk-branch.h" - #include "clk-regmap-divider.h" - #include "clk-regmap-mux.h" -+#include "reset.h" - - static struct clk_pll pll4 = { - .l_reg = 0x4, -@@ -39,6 +41,10 @@ static struct clk_pll pll4 = { - }, - }; - -+static const struct qcom_reset_map lcc_ipq806x_resets[] = { -+ [LCC_PCM_RESET] = { 0x54, 13 }, -+}; -+ - static const struct pll_config pll4_config = { - .l = 0xf, - .m = 0x91, -@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq - .config = &lcc_ipq806x_regmap_config, - .clks = lcc_ipq806x_clks, - .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), -+ .resets = lcc_ipq806x_resets, -+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), - }; - - static const struct of_device_id lcc_ipq806x_match_table[] = { ---- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h -@@ -19,4 +19,5 @@ - #define SPDIF_CLK 10 - #define AHBIX_CLK 11 - -+#define LCC_PCM_RESET 0 - #endif diff --git a/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch b/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch new file mode 100644 index 0000000000..72e70b613c --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch @@ -0,0 +1,29 @@ +From fc7dc1d0c10e8e3d72b68ddae8a61c8aa02a62c1 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:13:32 +0200 +Subject: [PATCH v4 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc + +Add pcm reset define for ipq806x lcc. + +Signed-off-by: Christian Marangi +Reviewed-by: Dmitry Baryshkov +Acked-by: Rob Herring +--- +v3: + - Added review tag + - Added ack tag +v2: + - Fix Sob tag + + include/dt-bindings/clock/qcom,lcc-ipq806x.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h +@@ -19,4 +19,6 @@ + #define SPDIF_CLK 10 + #define AHBIX_CLK 11 + ++#define LCC_PCM_RESET 0 ++ + #endif diff --git a/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch b/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch new file mode 100644 index 0000000000..2393651306 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch @@ -0,0 +1,48 @@ +From 3587d768bdf4683a53244be1acca5d095044671f Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:19:55 +0200 +Subject: [PATCH v4 2/3] clk: qcom: lcc-ipq806x: add reset definition + +Add reset definition for lcc-ipq806x. + +Signed-off-by: Christian Marangi +Reviewed-by: Dmitry Baryshkov +--- +v3: + - Added review tag +v2: + - Fix Sob tag + + drivers/clk/qcom/lcc-ipq806x.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/clk/qcom/lcc-ipq806x.c ++++ b/drivers/clk/qcom/lcc-ipq806x.c +@@ -22,6 +22,7 @@ + #include "clk-branch.h" + #include "clk-regmap-divider.h" + #include "clk-regmap-mux.h" ++#include "reset.h" + + static struct clk_pll pll4 = { + .l_reg = 0x4, +@@ -405,6 +406,10 @@ static struct clk_regmap *lcc_ipq806x_cl + [AHBIX_CLK] = &ahbix_clk.clkr, + }; + ++static const struct qcom_reset_map lcc_ipq806x_resets[] = { ++ [LCC_PCM_RESET] = { 0x54, 13 }, ++}; ++ + static const struct regmap_config lcc_ipq806x_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -417,6 +422,8 @@ static const struct qcom_cc_desc lcc_ipq + .config = &lcc_ipq806x_regmap_config, + .clks = lcc_ipq806x_clks, + .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), ++ .resets = lcc_ipq806x_resets, ++ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), + }; + + static const struct of_device_id lcc_ipq806x_match_table[] = { diff --git a/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch b/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch new file mode 100644 index 0000000000..905dc5bf40 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch @@ -0,0 +1,217 @@ +From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:35:13 +0200 +Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data + +Convert lcc-ipq806x driver to parent_data API. + +Signed-off-by: Christian Marangi +--- +v5: +- Fix the same compilation error (don't know what the hell happen + to my buildroot) +v4: +- Fix compilation error +v3: + - Inline pxo pll4 parent + - Change .name from pxo to pxo_board + + drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++---------------- + 1 file changed, 42 insertions(+), 35 deletions(-) + +--- a/drivers/clk/qcom/lcc-ipq806x.c ++++ b/drivers/clk/qcom/lcc-ipq806x.c +@@ -34,7 +34,9 @@ static struct clk_pll pll4 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll4", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = &(const struct clk_parent_data) { ++ .fw_name = "pxo", .name = "pxo_board", ++ }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p + { P_PLL4, 2 } + }; + +-static const char * const lcc_pxo_pll4[] = { +- "pxo", +- "pll4_vote", ++static const struct clk_parent_data lcc_pxo_pll4[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .fw_name = "pll4_vote", .name = "pll4_vote" }, + }; + + static struct freq_tbl clk_tbl_aif_mi2s[] = { +@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_osr_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, + }, + }; + +-static const char * const lcc_mi2s_parents[] = { +- "mi2s_osr_src", +-}; +- + static struct clk_branch mi2s_osr_clk = { + .halt_reg = 0x50, + .halt_bit = 1, +@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_osr_clk", +- .parent_names = lcc_mi2s_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_osr_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mi2s_div_clk", +- .parent_names = lcc_mi2s_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_osr_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_bit_div_clk", +- .parent_names = (const char *[]){ "mi2s_div_clk" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_div_clk.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl + }, + }; + ++static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { ++ { .hw = &mi2s_bit_div_clk.clkr.hw, }, ++ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, ++}; + + static struct clk_regmap_mux mi2s_bit_clk = { + .reg = 0x48, +@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mi2s_bit_clk", +- .parent_names = (const char *[]){ +- "mi2s_bit_div_clk", +- "mi2s_codec_clk", +- }, +- .num_parents = 2, ++ .parent_data = lcc_mi2s_bit_div_codec_clk, ++ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, +@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcm_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcm_clk_out", +- .parent_names = (const char *[]){ "pcm_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcm_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { + }, + }; + ++static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { ++ { .hw = &pcm_clk_out.clkr.hw, }, ++ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, ++}; ++ + static struct clk_regmap_mux pcm_clk = { + .reg = 0x54, + .shift = 10, +@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "pcm_clk", +- .parent_names = (const char *[]){ +- "pcm_clk_out", +- "pcm_codec_clk", +- }, +- .num_parents = 2, ++ .parent_data = lcc_pcm_clk_out_codec_clk, ++ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, +@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "spdif_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, + }, + }; + +-static const char * const lcc_spdif_parents[] = { +- "spdif_src", +-}; +- + static struct clk_branch spdif_clk = { + .halt_reg = 0xd4, + .halt_bit = 1, +@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { + .enable_mask = BIT(12), + .hw.init = &(struct clk_init_data){ + .name = "spdif_clk", +- .parent_names = lcc_spdif_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &spdif_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "ahbix", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_lcc_ops, + }, + }, From cd619eeff2cb18907b69c26ca496f558575de9ba Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:14:23 +0200 Subject: [PATCH 26/43] ipq806x: 5.15: replace gcc fixes with upstream version Replace gcc patch fixes with upstream version. Signed-off-by: Christian Marangi --- ...7-1-ipq806x-gcc-add-missing-clk-flag.patch | 99 -- ...com-krait-add-missing-enable-disable.patch | 57 -- ...806x-fix-wrong-naming-for-gcc_pxo_pl.patch | 109 +++ ...806x-convert-parent_names-to-parent_.patch | 921 ++++++++++++++++++ ...q806x-use-ARRAY_SIZE-for-num_parents.patch | 325 ++++++ ...pq806x-add-additional-freq-nss-cores.patch | 88 ++ ...806x-add-unusued-flag-for-critical-c.patch | 65 ++ ...om-clk-rcg-add-clk_rcg_floor_ops-ops.patch | 69 ++ ...806x-add-additional-freq-for-sdc-tab.patch | 38 + ...ngs-clock-add-ipq8064-ce5-clk-define.patch | 39 + ...gcc-ipq806x-add-CryptoEngine-clocks.patch} | 164 +--- ...indings-reset-add-ipq8064-ce5-resets.patch | 29 + ...-gcc-ipq806x-add-CryptoEngine-resets.patch | 30 + 13 files changed, 1761 insertions(+), 272 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch delete mode 100644 target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch rename target/linux/ipq806x/patches-5.15/{097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch => 100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch} (57%) create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch create mode 100644 target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch diff --git a/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch b/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch deleted file mode 100644 index 3b4900fafb..0000000000 --- a/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 16:52:56 +0100 -Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag - -Some flag are missing from the original code. -These clk can't be set using the protected-clock proprities as they -cause the malfunction of the serial interface. -These clks are needed for the rpm interface to work proprely or the -cpu regulators starts to fail as soon as they are disabled by the -kernel. - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -65,6 +65,7 @@ static struct clk_pll pll3 = { - .parent_names = (const char *[]){ "pxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, -+ .flags = CLK_IS_CRITICAL, - }, - }; - -@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk = - .parent_names = (const char *[]){ "gsbi4_qup_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk = - .parent_names = (const char *[]){ "gsbi7_qup_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_h_clk", - .ops = &clk_branch_ops, -+ .flags = CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -+ .flags = CLK_SET_RATE_GATE, - }, - } - }; -@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, -- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | -+ CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, -- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | -+ CLK_IGNORE_UNUSED, - }, - }, - }; diff --git a/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch b/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch deleted file mode 100644 index 78068f359c..0000000000 --- a/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 17:08:16 +0100 -Subject: [PATCH 3/4] clk: qcom: krait: add missing enable disable - -Add missing enable disable mux function. Add extra check to -div2_round_rate. - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++-- - 1 file changed, 25 insertions(+), 2 deletions(-) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -73,7 +73,25 @@ static u8 krait_mux_get_parent(struct cl - return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); - } - -+static int krait_mux_enable(struct clk_hw *hw) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ -+ __krait_mux_set_sel(mux, mux->en_mask); -+ -+ return 0; -+} -+ -+static void krait_mux_disable(struct clk_hw *hw) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ -+ __krait_mux_set_sel(mux, mux->safe_sel); -+} -+ - const struct clk_ops krait_mux_clk_ops = { -+ .enable = krait_mux_enable, -+ .disable = krait_mux_disable, - .set_parent = krait_mux_set_parent, - .get_parent = krait_mux_get_parent, - .determine_rate = __clk_mux_determine_rate_closest, -@@ -84,8 +102,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops); - static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) - { -- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); -- return DIV_ROUND_UP(*parent_rate, 2); -+ struct clk_hw *hw_parent = clk_hw_get_parent(hw); -+ -+ if (hw_parent) { -+ *parent_rate = clk_hw_round_rate(hw_parent, rate * 2); -+ return DIV_ROUND_UP(*parent_rate, 2); -+ } else -+ return -1; - } - - static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch new file mode 100644 index 0000000000..f3f3ea30da --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch @@ -0,0 +1,109 @@ +From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:24 +0100 +Subject: [PATCH 04/14] clk: qcom: gcc-ipq806x: fix wrong naming for + gcc_pxo_pll8_pll0 + +Parent gcc_pxo_pll8_pll0 had the parent definition and parent map +swapped. Fix this naming error. + +Signed-off-by: Ansuel Smith +Reviewed-by: Bjorn Andersson +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] + "pll3", + }; + +-static const struct parent_map gcc_pxo_pll8_pll0[] = { ++static const struct parent_map gcc_pxo_pll8_pll0_map[] = { + { P_PXO, 0 }, + { P_PLL8, 3 }, + { P_PLL0, 2 } + }; + +-static const char * const gcc_pxo_pll8_pll0_map[] = { ++static const char * const gcc_pxo_pll8_pll0[] = { + "pxo", + "pll8_vote", + "pll0_vote", +@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_s + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb30_master, + .clkr = { +@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_master_ref_src", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb30_utmi, + .clkr = { +@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_utmi_clk", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb, + .clkr = { +@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb, + .clkr = { +@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch new file mode 100644 index 0000000000..d99ac9992f --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch @@ -0,0 +1,921 @@ +From cb02866f9a740fb9fb8ff19698a69290da4057e5 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:25 +0100 +Subject: [PATCH 05/14] clk: qcom: gcc-ipq806x: convert parent_names to + parent_data + +Convert parent_names to parent_data to modernize the driver. +Where possible use parent_hws directly. + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++------------- + 1 file changed, 173 insertions(+), 113 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -25,6 +25,10 @@ + #include "clk-hfpll.h" + #include "reset.h" + ++static const struct clk_parent_data gcc_pxo[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++}; ++ + static struct clk_pll pll0 = { + .l_reg = 0x30c4, + .m_reg = 0x30c8, +@@ -35,7 +39,7 @@ static struct clk_pll pll0 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll0", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "pll0_vote", +- .parent_names = (const char *[]){ "pll0" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pll0.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +@@ -62,7 +68,7 @@ static struct clk_pll pll3 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll3", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -89,7 +95,7 @@ static struct clk_pll pll8 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll8", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "pll8_vote", +- .parent_names = (const char *[]){ "pll8" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pll8.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +@@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = { + static struct clk_hfpll hfpll0 = { + .d = &hfpll0_data, + .clkr.hw.init = &(struct clk_init_data){ +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .name = "hfpll0", + .ops = &clk_ops_hfpll, +@@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = { + static struct clk_hfpll hfpll1 = { + .d = &hfpll1_data, + .clkr.hw.init = &(struct clk_init_data){ +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .name = "hfpll1", + .ops = &clk_ops_hfpll, +@@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = + static struct clk_hfpll hfpll_l2 = { + .d = &hfpll_l2_data, + .clkr.hw.init = &(struct clk_init_data){ +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .name = "hfpll_l2", + .ops = &clk_ops_hfpll, +@@ -194,7 +202,7 @@ static struct clk_pll pll14 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll14", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "pll14_vote", +- .parent_names = (const char *[]){ "pll14" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pll14.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +@@ -238,7 +248,7 @@ static struct clk_pll pll18 = { + .freq_tbl = pll18_freq_tbl, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll18", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_p + { P_PLL8, 3 } + }; + +-static const char * const gcc_pxo_pll8[] = { +- "pxo", +- "pll8_vote", ++static const struct clk_parent_data gcc_pxo_pll8[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, + }; + + static const struct parent_map gcc_pxo_pll8_cxo_map[] = { +@@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_p + { P_CXO, 5 } + }; + +-static const char * const gcc_pxo_pll8_cxo[] = { +- "pxo", +- "pll8_vote", +- "cxo", ++static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .fw_name = "cxo", .name = "cxo" }, + }; + + static const struct parent_map gcc_pxo_pll3_map[] = { +@@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_p + { P_PLL3, 6 } + }; + +-static const char * const gcc_pxo_pll3[] = { +- "pxo", +- "pll3", ++static const struct clk_parent_data gcc_pxo_pll3[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll3.clkr.hw }, + }; + + static const struct parent_map gcc_pxo_pll8_pll0_map[] = { +@@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_p + { P_PLL0, 2 } + }; + +-static const char * const gcc_pxo_pll8_pll0[] = { +- "pxo", +- "pll8_vote", +- "pll0_vote", ++static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .hw = &pll0_vote.hw }, + }; + + static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { +@@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_p + { P_PLL18, 1 } + }; + +-static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { +- "pxo", +- "pll8_vote", +- "pll0_vote", +- "pll14", +- "pll18", ++static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .hw = &pll0_vote.hw }, ++ { .hw = &pll14.clkr.hw }, ++ { .hw = &pll18.clkr.hw }, + }; + + static struct freq_tbl clk_tbl_gsbi_uart[] = { +@@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi1_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi1_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi2_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi2_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi4_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi4_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi5_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi5_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi6_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi6_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi7_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi7_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_qup_clk", +- .parent_names = (const char *[]){ "gsbi1_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi1_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_qup_clk", +- .parent_names = (const char *[]){ "gsbi2_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi2_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_qup_clk", +- .parent_names = (const char *[]){ "gsbi4_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi4_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_qup_clk", +- .parent_names = (const char *[]){ "gsbi5_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi5_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_qup_clk", +- .parent_names = (const char *[]){ "gsbi6_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi6_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_qup_clk", +- .parent_names = (const char *[]){ "gsbi7_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi7_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gp0_src", +- .parent_names = gcc_pxo_pll8_cxo, ++ .parent_data = gcc_pxo_pll8_cxo, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gp0_clk", +- .parent_names = (const char *[]){ "gp0_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp0_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gp1_src", +- .parent_names = gcc_pxo_pll8_cxo, ++ .parent_data = gcc_pxo_pll8_cxo, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gp1_clk", +- .parent_names = (const char *[]){ "gp1_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp1_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gp2_src", +- .parent_names = gcc_pxo_pll8_cxo, ++ .parent_data = gcc_pxo_pll8_cxo, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gp2_clk", +- .parent_names = (const char *[]){ "gp2_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp2_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "prng_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "prng_clk", +- .parent_names = (const char *[]){ "prng_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &prng_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + }, +@@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "sdc1_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "sdc1_clk", +- .parent_names = (const char *[]){ "sdc1_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdc1_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "sdc3_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "sdc3_clk", +- .parent_names = (const char *[]){ "sdc3_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdc3_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "tsif_ref_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "tsif_ref_clk", +- .parent_names = (const char *[]){ "tsif_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &tsif_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcie_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_cl + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcie_ref_src_clk", +- .parent_names = (const char *[]){ "pcie_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcie1_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_c + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcie1_ref_src_clk", +- .parent_names = (const char *[]){ "pcie1_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie1_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcie2_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_c + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcie2_ref_src_clk", +- .parent_names = (const char *[]){ "pcie2_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie2_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "sata_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "sata_rxoob_clk", +- .parent_names = (const char *[]){ "sata_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sata_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "sata_pmalive_clk", +- .parent_names = (const char *[]){ "sata_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sata_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "sata_phy_ref_clk", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_branch_ops, + }, +@@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_master_ref_src", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_ + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_0_branch_clk", +- .parent_names = (const char *[]){ "usb30_master_ref_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_ + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_1_branch_clk", +- .parent_names = (const char *[]){ "usb30_master_ref_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_utmi_clk", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_0_utmi_clk_ctl", +- .parent_names = (const char *[]){ "usb30_utmi_clk", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_utmi_clk.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_1_utmi_clk_ctl", +- .parent_names = (const char *[]){ "usb30_utmi_clk", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_utmi_clk.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_cl + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_clk", +- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb_hs1_xcvr_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_cl + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_clk", +- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb_fs1_xcvr_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_sys_clk", +- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb_fs1_xcvr_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_clk", +- .parent_names = (const char *[]){ +- "gmac_core1_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core1_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_clk", +- .parent_names = (const char *[]){ +- "gmac_core2_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core2_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_clk", +- .parent_names = (const char *[]){ +- "gmac_core3_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core3_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_clk", +- .parent_names = (const char *[]){ +- "gmac_core4_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core4_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { + .enable_mask = BIT(6) | BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_clk", +- .parent_names = (const char *[]){ +- "nss_tcm_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &nss_tcm_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_sr + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core1_src_clk", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, +@@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_sr + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core2_src_clk", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch new file mode 100644 index 0000000000..6e6cec7db5 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch @@ -0,0 +1,325 @@ +From a6aedd6532131bc81d47bbf63385dfcf2a0e9faa Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:26 +0100 +Subject: [PATCH 06/14] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents + +Use ARRAY_SIZE for num_parents instead of hardcoding the value. + +Signed-off-by: Ansuel Smith +Reviewed-by: Bjorn Andersson +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- + 1 file changed, 34 insertions(+), 34 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { + .hw.init = &(struct clk_init_data){ + .name = "gp0_src", + .parent_data = gcc_pxo_pll8_cxo, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { + .hw.init = &(struct clk_init_data){ + .name = "gp1_src", + .parent_data = gcc_pxo_pll8_cxo, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { + .hw.init = &(struct clk_init_data){ + .name = "gp2_src", + .parent_data = gcc_pxo_pll8_cxo, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { + .hw.init = &(struct clk_init_data){ + .name = "prng_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + }, +@@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { + .hw.init = &(struct clk_init_data){ + .name = "sdc1_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + } +@@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { + .hw.init = &(struct clk_init_data){ + .name = "sdc3_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + } +@@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "tsif_ref_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + } +@@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "pcie_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "pcie1_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "pcie2_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "sata_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_s + .hw.init = &(struct clk_init_data){ + .name = "usb30_master_ref_src", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { + .hw.init = &(struct clk_init_data){ + .name = "usb30_utmi_clk", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_src", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_src", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_sr + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core1_src_clk", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, +@@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_sr + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core2_src_clk", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch new file mode 100644 index 0000000000..b0f09ec34d --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch @@ -0,0 +1,88 @@ +From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:27 +0100 +Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores + +Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be +clocked to 800MHz. Add these missing freq to the gcc driver. +Set the freq_tbl for the ubi32_cores to the correct values based on the +machine compatible. + +Signed-off-by: Ansuel Smith +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++--- + 1 file changed, 21 insertions(+), 3 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { + + static struct pll_freq_tbl pll18_freq_tbl[] = { + NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), ++ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), + NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), ++ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), + }; + + static struct clk_pll pll18 = { +@@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = { + }, + }; + +-static const struct freq_tbl clk_tbl_nss[] = { ++static const struct freq_tbl clk_tbl_nss_ipq8064[] = { + { 110000000, P_PLL18, 1, 1, 5 }, + { 275000000, P_PLL18, 2, 0, 0 }, + { 550000000, P_PLL18, 1, 0, 0 }, +@@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss + { } + }; + ++static const struct freq_tbl clk_tbl_nss_ipq8065[] = { ++ { 110000000, P_PLL18, 1, 1, 5 }, ++ { 275000000, P_PLL18, 2, 0, 0 }, ++ { 600000000, P_PLL18, 1, 0, 0 }, ++ { 800000000, P_PLL18, 1, 0, 0 }, ++ { } ++}; ++ + static struct clk_dyn_rcg ubi32_core1_src_clk = { + .ns_reg[0] = 0x3d2c, + .ns_reg[1] = 0x3d30, +@@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr + .pre_div_width = 2, + }, + .mux_sel_bit = 0, +- .freq_tbl = clk_tbl_nss, ++ /* nss freq table is selected based on the SoC compatible */ + .clkr = { + .enable_reg = 0x3d20, + .enable_mask = BIT(1), +@@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr + .pre_div_width = 2, + }, + .mux_sel_bit = 0, +- .freq_tbl = clk_tbl_nss, ++ /* nss freq table is selected based on the SoC compatible */ + .clkr = { + .enable_reg = 0x3d40, + .enable_mask = BIT(1), +@@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat + if (ret) + return ret; + ++ if (of_machine_is_compatible("qcom,ipq8065")) { ++ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; ++ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; ++ } else { ++ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064; ++ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064; ++ } ++ + ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); + if (ret) + return ret; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch new file mode 100644 index 0000000000..3d55cb421a --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch @@ -0,0 +1,65 @@ +From 28aa450d38e521de45be951df052d2c49a17fae2 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:28 +0100 +Subject: [PATCH 08/14] clk: qcom: gcc-ipq806x: add unusued flag for critical + clock + +Some clocks are used by other devices present on the SoC. For example +the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to +reject any regulator change command. These clock should never be +disabled. + +Signed-off-by: Ansuel Smith +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, +- .flags = CLK_SET_PARENT_GATE, ++ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = + }, + .num_parents = 1, + .ops = &clk_branch_ops, +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, +- .flags = CLK_SET_PARENT_GATE, ++ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = + }, + .num_parents = 1, + .ops = &clk_branch_ops, +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_h_clk", + .ops = &clk_branch_ops, ++ .flags = CLK_IGNORE_UNUSED, + }, + }, + }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch new file mode 100644 index 0000000000..22bd040d1b --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch @@ -0,0 +1,69 @@ +From 33958ad3fc02aeb06a4634e59689a9559d968e1f Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:29 +0100 +Subject: [PATCH 09/14] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops + +Add clk_rcg_floor_ops for clock that can't provide a stable freq and +require to use a floor freq to provide the requested frequency. + +Signed-off-by: Ansuel Smith +Reviewed-by: Bjorn Andersson +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com +--- + drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++ + drivers/clk/qcom/clk-rcg.h | 1 + + 2 files changed, 25 insertions(+) + +--- a/drivers/clk/qcom/clk-rcg.c ++++ b/drivers/clk/qcom/clk-rcg.c +@@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_h + return __clk_rcg_set_rate(rcg, f); + } + ++static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_rcg *rcg = to_clk_rcg(hw); ++ const struct freq_tbl *f; ++ ++ f = qcom_find_freq_floor(rcg->freq_tbl, rate); ++ if (!f) ++ return -EINVAL; ++ ++ return __clk_rcg_set_rate(rcg, f); ++} ++ + static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { +@@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = { + }; + EXPORT_SYMBOL_GPL(clk_rcg_ops); + ++const struct clk_ops clk_rcg_floor_ops = { ++ .enable = clk_enable_regmap, ++ .disable = clk_disable_regmap, ++ .get_parent = clk_rcg_get_parent, ++ .set_parent = clk_rcg_set_parent, ++ .recalc_rate = clk_rcg_recalc_rate, ++ .determine_rate = clk_rcg_determine_rate, ++ .set_rate = clk_rcg_set_floor_rate, ++}; ++EXPORT_SYMBOL_GPL(clk_rcg_floor_ops); ++ + const struct clk_ops clk_rcg_bypass_ops = { + .enable = clk_enable_regmap, + .disable = clk_disable_regmap, +--- a/drivers/clk/qcom/clk-rcg.h ++++ b/drivers/clk/qcom/clk-rcg.h +@@ -86,6 +86,7 @@ struct clk_rcg { + }; + + extern const struct clk_ops clk_rcg_ops; ++extern const struct clk_ops clk_rcg_floor_ops; + extern const struct clk_ops clk_rcg_bypass_ops; + extern const struct clk_ops clk_rcg_bypass2_ops; + extern const struct clk_ops clk_rcg_pixel_ops; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch new file mode 100644 index 0000000000..3bb5e57c87 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch @@ -0,0 +1,38 @@ +From 7e726f34c782b2ca28a29ca9870e34e4319d65bc Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:30 +0100 +Subject: [PATCH 10/14] clk: qcom: gcc-ipq806x: add additional freq for sdc + table + +Add additional freq supported for the sdc table. The ops are changed to +the floor_ops to handle a freq request of 52kHz where we need to provide +a freq of 51.2kHz instead for stability reason. + +Signed-off-by: Ansuel Smith +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc + { 20210000, P_PLL8, 1, 1, 19 }, + { 24000000, P_PLL8, 4, 1, 4 }, + { 48000000, P_PLL8, 4, 1, 2 }, ++ { 51200000, P_PLL8, 1, 2, 15 }, + { 64000000, P_PLL8, 3, 1, 2 }, + { 96000000, P_PLL8, 4, 0, 0 }, + { 192000000, P_PLL8, 2, 0, 0 }, +@@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = { + .name = "sdc1_src", + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), +- .ops = &clk_rcg_ops, ++ .ops = &clk_rcg_floor_ops, + }, + } + }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch new file mode 100644 index 0000000000..858c6f78a5 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch @@ -0,0 +1,39 @@ +From b565d66403e3df303a058c0d8d00d0fc6aeb2ddc Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:31 +0100 +Subject: [PATCH 11/14] dt-bindings: clock: add ipq8064 ce5 clk define + +Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. +Define CE5_SRC is not used so it's OK to change and we align it to +the QSDK naming. + +Signed-off-by: Ansuel Smith +Acked-by: Rob Herring +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-12-ansuelsmth@gmail.com +--- + include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h +@@ -240,7 +240,7 @@ + #define PLL14 232 + #define PLL14_VOTE 233 + #define PLL18 234 +-#define CE5_SRC 235 ++#define CE5_A_CLK 235 + #define CE5_H_CLK 236 + #define CE5_CORE_CLK 237 + #define CE3_SLEEP_CLK 238 +@@ -283,5 +283,8 @@ + #define EBI2_AON_CLK 281 + #define NSSTCM_CLK_SRC 282 + #define NSSTCM_CLK 283 ++#define CE5_A_CLK_SRC 285 ++#define CE5_H_CLK_SRC 286 ++#define CE5_CORE_CLK_SRC 287 + + #endif diff --git a/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch similarity index 57% rename from target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch rename to target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch index d1e047cabf..3ded707bf0 100644 --- a/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch @@ -1,31 +1,22 @@ -From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001 +From b293510f3961b90dcab59965f57779be93ceda7c Mon Sep 17 00:00:00 2001 From: Ansuel Smith -Date: Sun, 7 Feb 2021 17:23:38 +0100 -Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine +Date: Sat, 26 Feb 2022 14:52:32 +0100 +Subject: [PATCH 12/14] clk: qcom: gcc-ipq806x: add CryptoEngine clocks -Add missing clk and reset needed for nss additional core and crypto -engine. +Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com --- - drivers/clk/qcom/gcc-ipq806x.c | 250 +++++++++++++++++++ - include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +- - include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 + - 3 files changed, 259 insertions(+), 1 deletion(-) + drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ + 1 file changed, 244 insertions(+) --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = { - - static struct pll_freq_tbl pll18_freq_tbl[] = { - NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), -+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), - NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), -+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), - }; - - static struct clk_pll pll18 = { -@@ -245,6 +247,22 @@ static struct clk_pll pll18 = { +@@ -256,6 +256,24 @@ static struct clk_pll pll18 = { }, }; @@ -39,7 +30,9 @@ Signed-off-by: Ansuel Smith + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll11", -+ .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "pxo", ++ }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, @@ -48,7 +41,7 @@ Signed-off-by: Ansuel Smith enum { P_PXO, P_PLL8, -@@ -253,6 +271,7 @@ enum { +@@ -264,6 +282,7 @@ enum { P_CXO, P_PLL14, P_PLL18, @@ -56,8 +49,8 @@ Signed-off-by: Ansuel Smith }; static const struct parent_map gcc_pxo_pll8_map[] = { -@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p - "pll18", +@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_ + { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { @@ -69,13 +62,14 @@ Signed-off-by: Ansuel Smith + { P_PLL11, 3 }, +}; + -+static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { -+ "pxo", -+ "pll8_vote", -+ "pll0_vote", -+ "pll14", -+ "pll18", -+ "pll11" ++static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { ++ { .fw_name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .hw = &pll0_vote.hw }, ++ { .hw = &pll14.clkr.hw }, ++ { .hw = &pll18.clkr.hw }, ++ { .hw = &pll11.clkr.hw }, ++ +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { @@ -87,37 +81,20 @@ Signed-off-by: Ansuel Smith + { P_PLL11, 3 }, +}; + -+static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { -+ "pxo", -+ "pll3", -+ "pll0_vote", -+ "pll14", -+ "pll18", -+ "pll11" ++static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { ++ { .fw_name = "pxo" }, ++ { .hw = &pll3.clkr.hw }, ++ { .hw = &pll0_vote.hw }, ++ { .hw = &pll14.clkr.hw }, ++ { .hw = &pll18.clkr.hw }, ++ { .hw = &pll11.clkr.hw }, ++ +}; + static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, -@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc - { 20210000, P_PLL8, 1, 1, 19 }, - { 24000000, P_PLL8, 4, 1, 4 }, - { 48000000, P_PLL8, 4, 1, 2 }, -+ { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ - { 64000000, P_PLL8, 3, 1, 2 }, - { 96000000, P_PLL8, 4, 0, 0 }, - { 192000000, P_PLL8, 2, 0, 0 }, -@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss - { 110000000, P_PLL18, 1, 1, 5 }, - { 275000000, P_PLL18, 2, 0, 0 }, - { 550000000, P_PLL18, 1, 0, 0 }, -+ { 600000000, P_PLL18, 1, 0, 0 }, - { 733000000, P_PLL18, 1, 0, 0 }, -+ { 800000000, P_PLL18, 1, 0, 0 }, - { } - }; - -@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr +@@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_sr }, }; @@ -154,8 +131,8 @@ Signed-off-by: Ansuel Smith + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_src", -+ .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11, -+ .num_parents = 6, ++ .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, @@ -171,8 +148,8 @@ Signed-off-by: Ansuel Smith + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_clk", -+ .parent_names = (const char *[]){ -+ "ce5_core_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &ce5_core_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, @@ -214,8 +191,8 @@ Signed-off-by: Ansuel Smith + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk_src", -+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = 6, ++ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, @@ -231,8 +208,8 @@ Signed-off-by: Ansuel Smith + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk", -+ .parent_names = (const char *[]){ -+ "ce5_a_clk_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &ce5_a_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, @@ -274,8 +251,8 @@ Signed-off-by: Ansuel Smith + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk_src", -+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = 6, ++ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, @@ -291,8 +268,8 @@ Signed-off-by: Ansuel Smith + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk", -+ .parent_names = (const char *[]){ -+ "ce5_h_clk_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &ce5_h_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, @@ -304,7 +281,7 @@ Signed-off-by: Ansuel Smith static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, -@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, @@ -312,7 +289,7 @@ Signed-off-by: Ansuel Smith [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, -@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, @@ -325,48 +302,3 @@ Signed-off-by: Ansuel Smith }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i - [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, - [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, - [GMAC_AHB_RESET] = { 0x3e24, 0 }, -+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, -+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, -+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, -+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, -+ [CRYPTO_AHB_RESET] = { 0x3e10, 0}, - [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, - [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, - [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, ---- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h -@@ -240,7 +240,7 @@ - #define PLL14 232 - #define PLL14_VOTE 233 - #define PLL18 234 --#define CE5_SRC 235 -+#define CE5_A_CLK 235 - #define CE5_H_CLK 236 - #define CE5_CORE_CLK 237 - #define CE3_SLEEP_CLK 238 -@@ -283,5 +283,8 @@ - #define EBI2_AON_CLK 281 - #define NSSTCM_CLK_SRC 282 - #define NSSTCM_CLK 283 -+#define CE5_A_CLK_SRC 285 -+#define CE5_H_CLK_SRC 286 -+#define CE5_CORE_CLK_SRC 287 - - #endif ---- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h -@@ -163,5 +163,10 @@ - #define NSS_CAL_PRBS_RST_N_RESET 154 - #define NSS_LCKDT_RST_N_RESET 155 - #define NSS_SRDS_N_RESET 156 -+#define CRYPTO_ENG1_RESET 157 -+#define CRYPTO_ENG2_RESET 158 -+#define CRYPTO_ENG3_RESET 159 -+#define CRYPTO_ENG4_RESET 160 -+#define CRYPTO_AHB_RESET 161 - - #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch new file mode 100644 index 0000000000..5d05c2b3af --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch @@ -0,0 +1,29 @@ +From f4a7e56f4956f0450b9f671ed93d45ffcc15aa62 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 18 Jan 2022 01:22:05 +0100 +Subject: [PATCH v6 13/15] dt-bindings: reset: add ipq8064 ce5 resets + +Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. + +Signed-off-by: Ansuel Smith +Reviewed-by: Bjorn Andersson +Acked-by: Philipp Zabel +Acked-by: Rob Herring +Reviewed-by: Stephen Boyd +--- + include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h +@@ -163,5 +163,10 @@ + #define NSS_CAL_PRBS_RST_N_RESET 154 + #define NSS_LCKDT_RST_N_RESET 155 + #define NSS_SRDS_N_RESET 156 ++#define CRYPTO_ENG1_RESET 157 ++#define CRYPTO_ENG2_RESET 158 ++#define CRYPTO_ENG3_RESET 159 ++#define CRYPTO_ENG4_RESET 160 ++#define CRYPTO_AHB_RESET 161 + + #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch new file mode 100644 index 0000000000..a26f67e36e --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch @@ -0,0 +1,30 @@ +From 4f865bdcb44fb18951de94be5c2ec37a891a8d03 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 26 Feb 2022 14:52:34 +0100 +Subject: [PATCH 14/14] clk: qcom: gcc-ipq806x: add CryptoEngine resets + +Add missing CryptoEngine resets. + +Signed-off-by: Ansuel Smith +Reviewed-by: Stephen Boyd +Tested-by: Jonathan McDowell +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220226135235.10051-15-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -3320,6 +3320,11 @@ static const struct qcom_reset_map gcc_i + [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, + [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, + [GMAC_AHB_RESET] = { 0x3e24, 0 }, ++ [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, ++ [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, ++ [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, ++ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, ++ [CRYPTO_AHB_RESET] = { 0x3e10, 0}, + [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, + [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, + [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, From 5ad826f48a4f3c3e08bd1da8c1504a53edd281a0 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:15:13 +0200 Subject: [PATCH 27/43] ipq806x: 5.15: replace stmmac pcs fix with upstream version Replace stmmac pcs fix with upstream version. Signed-off-by: Christian Marangi --- ...-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch | 83 ---------- ...mac-add-missing-sgmii-configure-for-.patch | 151 ++++++++++++++++++ ...mac-reset-force-speed-bit-for-ipq806.patch | 110 +++++++++++++ 3 files changed, 261 insertions(+), 83 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch create mode 100644 target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch create mode 100644 target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch diff --git a/target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch b/target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch deleted file mode 100644 index 2210f4e249..0000000000 --- a/target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch +++ /dev/null @@ -1,83 +0,0 @@ ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -@@ -64,6 +64,17 @@ - #define NSS_COMMON_CLK_DIV_SGMII_100 4 - #define NSS_COMMON_CLK_DIV_SGMII_10 49 - -+#define QSGMII_PCS_ALL_CH_CTL 0x80 -+#define QSGMII_PCS_CH_SPEED_FORCE 0x2 -+#define QSGMII_PCS_CH_SPEED_10 0x0 -+#define QSGMII_PCS_CH_SPEED_100 0x4 -+#define QSGMII_PCS_CH_SPEED_1000 0x8 -+#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \ -+ QSGMII_PCS_CH_SPEED_10 | \ -+ QSGMII_PCS_CH_SPEED_100 | \ -+ QSGMII_PCS_CH_SPEED_1000) -+#define QSGMII_PCS_CH_SPEED_SHIFT(x) (x * 4) -+ - #define QSGMII_PCS_CAL_LCKDT_CTL 0x120 - #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) - -@@ -242,6 +253,36 @@ static void ipq806x_gmac_fix_mac_speed(v - ipq806x_gmac_set_speed(gmac, speed); - } - -+static int -+ipq806x_gmac_get_qsgmii_pcs_speed_val(struct platform_device *pdev) { -+ struct device_node *fixed_link_node; -+ int rv; -+ int fixed_link_speed; -+ -+ if (!of_phy_is_fixed_link(pdev->dev.of_node)) -+ return 0; -+ -+ fixed_link_node = of_get_child_by_name(pdev->dev.of_node, "fixed-link"); -+ if (!fixed_link_node) -+ return -1; -+ -+ rv = of_property_read_u32(fixed_link_node, "speed", &fixed_link_speed); -+ of_node_put(fixed_link_node); -+ if (rv) -+ return -1; -+ -+ switch (fixed_link_speed) { -+ case SPEED_1000: -+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_1000; -+ case SPEED_100: -+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_100; -+ case SPEED_10: -+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_10; -+ } -+ -+ return -1; -+} -+ - static int ipq806x_gmac_probe(struct platform_device *pdev) - { - struct plat_stmmacenet_data *plat_dat; -@@ -250,6 +291,7 @@ static int ipq806x_gmac_probe(struct pla - struct ipq806x_gmac *gmac; - int val; - int err; -+ int qsgmii_pcs_speed; - - val = stmmac_get_platform_resources(pdev, &stmmac_res); - if (val) -@@ -339,6 +381,17 @@ static int ipq806x_gmac_probe(struct pla - 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET | - 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET | - 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET); -+ -+ qsgmii_pcs_speed = ipq806x_gmac_get_qsgmii_pcs_speed_val(pdev); -+ if (qsgmii_pcs_speed != -1) { -+ regmap_update_bits( -+ gmac->qsgmii_csr, -+ QSGMII_PCS_ALL_CH_CTL, -+ QSGMII_PCS_CH_SPEED_MASK << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id), -+ qsgmii_pcs_speed << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id)); -+ } - } - - plat_dat->has_gmac = true; diff --git a/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch b/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch new file mode 100644 index 0000000000..bd492ca1ec --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/101-v6.0-01-net-ethernet-stmmac-add-missing-sgmii-configure-for-.patch @@ -0,0 +1,151 @@ +From 9ec092d2feb69045dd289845024301fb91c064ee Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Tue, 14 Jun 2022 13:22:27 +0200 +Subject: [PATCH 1/2] net: ethernet: stmmac: add missing sgmii configure for + ipq806x + +The different gmacid require different configuration based on the soc +and on the gmac id. Add these missing configuration taken from the +original driver. + +Signed-off-by: Christian 'Ansuel' Marangi +Link: https://lore.kernel.org/r/20220614112228.1998-1-ansuelsmth@gmail.com +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + + .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 93 +++++++++++++++---- + 2 files changed, 78 insertions(+), 16 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -83,6 +83,7 @@ config DWMAC_IPQ806X + default ARCH_QCOM + depends on OF && (ARCH_QCOM || COMPILE_TEST) + select MFD_SYSCON ++ select QCOM_SOCINFO + help + Support for QCA IPQ806X DWMAC Ethernet. + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c +@@ -27,6 +27,8 @@ + #include + #include + #include ++#include ++#include + + #include "stmmac_platform.h" + +@@ -75,11 +77,20 @@ + #define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2) + #define QSGMII_PHY_TX_DRIVER_EN BIT(3) + #define QSGMII_PHY_QSGMII_EN BIT(7) +-#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12 +-#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18 +-#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20 +-#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22 +-#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28 ++#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10) ++#define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x)) ++#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12) ++#define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x)) ++#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18) ++#define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x)) ++#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20) ++#define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x)) ++#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22) ++#define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x)) ++#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26) ++#define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x)) ++#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28) ++#define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x)) + + struct ipq806x_gmac { + struct platform_device *pdev; +@@ -242,6 +253,64 @@ static void ipq806x_gmac_fix_mac_speed(v + ipq806x_gmac_set_speed(gmac, speed); + } + ++static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = { ++ { ++ .revision = "1.*", ++ }, ++ { ++ /* sentinel */ ++ } ++}; ++ ++static int ++ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac) ++{ ++ struct platform_device *pdev = gmac->pdev; ++ const struct soc_device_attribute *soc; ++ struct device *dev = &pdev->dev; ++ u32 qsgmii_param; ++ ++ switch (gmac->id) { ++ case 1: ++ soc = soc_device_match(ipq806x_gmac_soc_v1); ++ ++ if (soc) ++ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) | ++ QSGMII_PHY_TX_SLEW(0x2) | ++ QSGMII_PHY_DEEMPHASIS_LVL(0x2); ++ else ++ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) | ++ QSGMII_PHY_TX_SLEW(0x0) | ++ QSGMII_PHY_DEEMPHASIS_LVL(0x0); ++ ++ qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2); ++ break; ++ case 2: ++ case 3: ++ qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) | ++ QSGMII_PHY_TX_DRV_AMP(0xc); ++ break; ++ default: /* gmac 0 can't be set in SGMII mode */ ++ dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id); ++ return -EINVAL; ++ } ++ ++ /* Common params across all gmac id */ ++ qsgmii_param |= QSGMII_PHY_CDR_EN | ++ QSGMII_PHY_RX_FRONT_EN | ++ QSGMII_PHY_RX_SIGNAL_DETECT_EN | ++ QSGMII_PHY_TX_DRIVER_EN | ++ QSGMII_PHY_QSGMII_EN | ++ QSGMII_PHY_PHASE_LOOP_GAIN(0x4) | ++ QSGMII_PHY_RX_INPUT_EQU(0x1) | ++ QSGMII_PHY_CDR_PI_SLEW(0x2); ++ ++ regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), ++ qsgmii_param); ++ ++ return 0; ++} ++ + static int ipq806x_gmac_probe(struct platform_device *pdev) + { + struct plat_stmmacenet_data *plat_dat; +@@ -328,17 +397,9 @@ static int ipq806x_gmac_probe(struct pla + regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); + + if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) { +- regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), +- QSGMII_PHY_CDR_EN | +- QSGMII_PHY_RX_FRONT_EN | +- QSGMII_PHY_RX_SIGNAL_DETECT_EN | +- QSGMII_PHY_TX_DRIVER_EN | +- QSGMII_PHY_QSGMII_EN | +- 0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET | +- 0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET | +- 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET | +- 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET | +- 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET); ++ err = ipq806x_gmac_configure_qsgmii_params(gmac); ++ if (err) ++ goto err_remove_config_dt; + } + + plat_dat->has_gmac = true; diff --git a/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch b/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch new file mode 100644 index 0000000000..d444553452 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/101-v6.0-02-net-ethernet-stmmac-reset-force-speed-bit-for-ipq806.patch @@ -0,0 +1,110 @@ +From 8bca458990dd8c6d001b2fb52063aa18e8ca7444 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Tue, 14 Jun 2022 13:22:28 +0200 +Subject: [PATCH 2/2] net: ethernet: stmmac: reset force speed bit for ipq806x + +Some bootloader may set the force speed regs even if the actual +interface should use autonegotiation between PCS and PHY. +This cause the complete malfuction of the interface. + +To fix this correctly reset the force speed regs if a fixed-link is not +defined in the DTS. With a fixed-link node correctly configure the +forced speed regs to handle any misconfiguration by the bootloader. + +Reported-by: Mark Mentovai +Co-developed-by: Mark Mentovai +Signed-off-by: Mark Mentovai +Signed-off-by: Christian 'Ansuel' Marangi +Link: https://lore.kernel.org/r/20220614112228.1998-2-ansuelsmth@gmail.com +Signed-off-by: Paolo Abeni +--- + .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 64 +++++++++++++++++++ + 1 file changed, 64 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c +@@ -66,6 +66,17 @@ + #define NSS_COMMON_CLK_DIV_SGMII_100 4 + #define NSS_COMMON_CLK_DIV_SGMII_10 49 + ++#define QSGMII_PCS_ALL_CH_CTL 0x80 ++#define QSGMII_PCS_CH_SPEED_FORCE BIT(1) ++#define QSGMII_PCS_CH_SPEED_10 0x0 ++#define QSGMII_PCS_CH_SPEED_100 BIT(2) ++#define QSGMII_PCS_CH_SPEED_1000 BIT(3) ++#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \ ++ QSGMII_PCS_CH_SPEED_10 | \ ++ QSGMII_PCS_CH_SPEED_100 | \ ++ QSGMII_PCS_CH_SPEED_1000) ++#define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4) ++ + #define QSGMII_PCS_CAL_LCKDT_CTL 0x120 + #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) + +@@ -253,6 +264,55 @@ static void ipq806x_gmac_fix_mac_speed(v + ipq806x_gmac_set_speed(gmac, speed); + } + ++static int ++ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac) ++{ ++ struct platform_device *pdev = gmac->pdev; ++ struct device *dev = &pdev->dev; ++ struct device_node *dn; ++ int link_speed; ++ int val = 0; ++ int ret; ++ ++ /* Some bootloader may apply wrong configuration and cause ++ * not functioning port. If fixed link is not set, ++ * reset the force speed bit. ++ */ ++ if (!of_phy_is_fixed_link(pdev->dev.of_node)) ++ goto write; ++ ++ dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link"); ++ ret = of_property_read_u32(dn, "speed", &link_speed); ++ of_node_put(dn); ++ if (ret) { ++ dev_err(dev, "found fixed-link node with no speed"); ++ return ret; ++ } ++ ++ val = QSGMII_PCS_CH_SPEED_FORCE; ++ ++ switch (link_speed) { ++ case SPEED_1000: ++ val |= QSGMII_PCS_CH_SPEED_1000; ++ break; ++ case SPEED_100: ++ val |= QSGMII_PCS_CH_SPEED_100; ++ break; ++ case SPEED_10: ++ val |= QSGMII_PCS_CH_SPEED_10; ++ break; ++ } ++ ++write: ++ regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL, ++ QSGMII_PCS_CH_SPEED_MASK << ++ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id), ++ val << ++ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id)); ++ ++ return 0; ++} ++ + static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = { + { + .revision = "1.*", +@@ -400,6 +460,10 @@ static int ipq806x_gmac_probe(struct pla + err = ipq806x_gmac_configure_qsgmii_params(gmac); + if (err) + goto err_remove_config_dt; ++ ++ err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac); ++ if (err) ++ goto err_remove_config_dt; + } + + plat_dat->has_gmac = true; From 3a911b8c2d97293f04288775599843ab5cb77045 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:16:04 +0200 Subject: [PATCH 28/43] ipq806x: 5.15: backport devfreq new cpufreq based PASSIVE governor Backport devfreq new cpufreq based PASSIVE governor needed for devfreq based fab and cache scaling. Signed-off-by: Christian Marangi --- ...t-devfreq_get_freq_range-symbol-with.patch | 113 +++++ ...pu-based-scaling-support-to-passive-.patch | 461 ++++++++++++++++++ ...ve-Reduce-duplicate-code-when-passiv.patch | 110 +++++ ...ve-Keep-cpufreq_policy-for-possible-.patch | 232 +++++++++ ...ve-Return-non-error-when-not-support.patch | 31 ++ ...ernel-warning-with-cpufreq-passive-r.patch | 31 ++ ...x-cpufreq-passive-unregister-errorin.patch | 85 ++++ ...ernel-panic-with-cpu-based-scaling-t.patch | 39 ++ ...work-freq_table-to-be-local-to-devfr.patch | 269 ++++++++++ ...Mute-warning-on-governor-PROBE_DEFER.patch | 28 ++ 10 files changed, 1399 insertions(+) create mode 100644 target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch create mode 100644 target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch create mode 100644 target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch create mode 100644 target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch create mode 100644 target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch create mode 100644 target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch create mode 100644 target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch create mode 100644 target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch create mode 100644 target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch create mode 100644 target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch new file mode 100644 index 0000000000..0442105d87 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/111-v5.19-01-PM-devfreq-Export-devfreq_get_freq_range-symbol-with.patch @@ -0,0 +1,113 @@ +From 713472e53e6e53c985e283782b0fd76b8ecfd47e Mon Sep 17 00:00:00 2001 +From: Chanwoo Choi +Date: Mon, 1 Mar 2021 02:07:29 +0900 +Subject: [PATCH 1/5] PM / devfreq: Export devfreq_get_freq_range symbol within + devfreq + +In order to get frequency range within devfreq governors, +export devfreq_get_freq_range symbol within devfreq. + +Reviewed-by: Matthias Kaehlcke +Tested-by: Chen-Yu Tsai +Tested-by: Johnson Wang +Signed-off-by: Chanwoo Choi +--- + drivers/devfreq/devfreq.c | 20 ++++++++++++-------- + drivers/devfreq/governor.h | 2 ++ + 2 files changed, 14 insertions(+), 8 deletions(-) + +--- a/drivers/devfreq/devfreq.c ++++ b/drivers/devfreq/devfreq.c +@@ -112,16 +112,16 @@ static unsigned long find_available_max_ + } + + /** +- * get_freq_range() - Get the current freq range ++ * devfreq_get_freq_range() - Get the current freq range + * @devfreq: the devfreq instance + * @min_freq: the min frequency + * @max_freq: the max frequency + * + * This takes into consideration all constraints. + */ +-static void get_freq_range(struct devfreq *devfreq, +- unsigned long *min_freq, +- unsigned long *max_freq) ++void devfreq_get_freq_range(struct devfreq *devfreq, ++ unsigned long *min_freq, ++ unsigned long *max_freq) + { + unsigned long *freq_table = devfreq->profile->freq_table; + s32 qos_min_freq, qos_max_freq; +@@ -158,6 +158,7 @@ static void get_freq_range(struct devfre + if (*min_freq > *max_freq) + *min_freq = *max_freq; + } ++EXPORT_SYMBOL(devfreq_get_freq_range); + + /** + * devfreq_get_freq_level() - Lookup freq_table for the frequency +@@ -418,7 +419,7 @@ int devfreq_update_target(struct devfreq + err = devfreq->governor->get_target_freq(devfreq, &freq); + if (err) + return err; +- get_freq_range(devfreq, &min_freq, &max_freq); ++ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); + + if (freq < min_freq) { + freq = min_freq; +@@ -785,6 +786,7 @@ struct devfreq *devfreq_add_device(struc + { + struct devfreq *devfreq; + struct devfreq_governor *governor; ++ unsigned long min_freq, max_freq; + int err = 0; + + if (!dev || !profile || !governor_name) { +@@ -849,6 +851,8 @@ struct devfreq *devfreq_add_device(struc + goto err_dev; + } + ++ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); ++ + devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev); + devfreq->opp_table = dev_pm_opp_get_opp_table(dev); + if (IS_ERR(devfreq->opp_table)) +@@ -1561,7 +1565,7 @@ static ssize_t min_freq_show(struct devi + unsigned long min_freq, max_freq; + + mutex_lock(&df->lock); +- get_freq_range(df, &min_freq, &max_freq); ++ devfreq_get_freq_range(df, &min_freq, &max_freq); + mutex_unlock(&df->lock); + + return sprintf(buf, "%lu\n", min_freq); +@@ -1615,7 +1619,7 @@ static ssize_t max_freq_show(struct devi + unsigned long min_freq, max_freq; + + mutex_lock(&df->lock); +- get_freq_range(df, &min_freq, &max_freq); ++ devfreq_get_freq_range(df, &min_freq, &max_freq); + mutex_unlock(&df->lock); + + return sprintf(buf, "%lu\n", max_freq); +@@ -1929,7 +1933,7 @@ static int devfreq_summary_show(struct s + + mutex_lock(&devfreq->lock); + cur_freq = devfreq->previous_freq; +- get_freq_range(devfreq, &min_freq, &max_freq); ++ devfreq_get_freq_range(devfreq, &min_freq, &max_freq); + timer = devfreq->profile->timer; + + if (IS_SUPPORTED_ATTR(devfreq->governor->attrs, POLLING_INTERVAL)) +--- a/drivers/devfreq/governor.h ++++ b/drivers/devfreq/governor.h +@@ -86,6 +86,8 @@ int devfreq_remove_governor(struct devfr + + int devfreq_update_status(struct devfreq *devfreq, unsigned long freq); + int devfreq_update_target(struct devfreq *devfreq, unsigned long freq); ++void devfreq_get_freq_range(struct devfreq *devfreq, unsigned long *min_freq, ++ unsigned long *max_freq); + + static inline int devfreq_update_stats(struct devfreq *df) + { diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch new file mode 100644 index 0000000000..52f1200c31 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/111-v5.19-02-PM-devfreq-Add-cpu-based-scaling-support-to-passive-.patch @@ -0,0 +1,461 @@ +From a03dacb0316f74400846aaf144d6c73f4217ca08 Mon Sep 17 00:00:00 2001 +From: Saravana Kannan +Date: Tue, 2 Mar 2021 15:58:21 +0900 +Subject: [PATCH 2/5] PM / devfreq: Add cpu based scaling support to passive + governor + +Many CPU architectures have caches that can scale independent of the +CPUs. Frequency scaling of the caches is necessary to make sure that the +cache is not a performance bottleneck that leads to poor performance and +power. The same idea applies for RAM/DDR. + +To achieve this, this patch adds support for cpu based scaling to the +passive governor. This is accomplished by taking the current frequency +of each CPU frequency domain and then adjust the frequency of the cache +(or any devfreq device) based on the frequency of the CPUs. It listens +to CPU frequency transition notifiers to keep itself up to date on the +current CPU frequency. + +To decide the frequency of the device, the governor does one of the +following: +* Derives the optimal devfreq device opp from required-opps property of + the parent cpu opp_table. + +* Scales the device frequency in proportion to the CPU frequency. So, if + the CPUs are running at their max frequency, the device runs at its + max frequency. If the CPUs are running at their min frequency, the + device runs at its min frequency. It is interpolated for frequencies + in between. + +Tested-by: Chen-Yu Tsai +Tested-by: Johnson Wang +Signed-off-by: Saravana Kannan +[Sibi: Integrated cpu-freqmap governor into passive_governor] +Signed-off-by: Sibi Sankar +[Chanwoo: Fix conflict with latest code and cleanup code] +Signed-off-by: Chanwoo Choi +--- + drivers/devfreq/governor.h | 22 +++ + drivers/devfreq/governor_passive.c | 298 +++++++++++++++++++++++++++-- + include/linux/devfreq.h | 17 +- + 3 files changed, 323 insertions(+), 14 deletions(-) + +--- a/drivers/devfreq/governor.h ++++ b/drivers/devfreq/governor.h +@@ -48,6 +48,28 @@ + #define DEVFREQ_GOV_ATTR_TIMER BIT(1) + + /** ++ * struct devfreq_cpu_data - Hold the per-cpu data ++ * @dev: reference to cpu device. ++ * @first_cpu: the cpumask of the first cpu of a policy. ++ * @opp_table: reference to cpu opp table. ++ * @cur_freq: the current frequency of the cpu. ++ * @min_freq: the min frequency of the cpu. ++ * @max_freq: the max frequency of the cpu. ++ * ++ * This structure stores the required cpu_data of a cpu. ++ * This is auto-populated by the governor. ++ */ ++struct devfreq_cpu_data { ++ struct device *dev; ++ unsigned int first_cpu; ++ ++ struct opp_table *opp_table; ++ unsigned int cur_freq; ++ unsigned int min_freq; ++ unsigned int max_freq; ++}; ++ ++/** + * struct devfreq_governor - Devfreq policy governor + * @node: list node - contains registered devfreq governors + * @name: Governor's name +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -8,11 +8,85 @@ + */ + + #include ++#include ++#include ++#include ++#include + #include + #include + #include "governor.h" + +-static int devfreq_passive_get_target_freq(struct devfreq *devfreq, ++#define HZ_PER_KHZ 1000 ++ ++static unsigned long get_target_freq_by_required_opp(struct device *p_dev, ++ struct opp_table *p_opp_table, ++ struct opp_table *opp_table, ++ unsigned long *freq) ++{ ++ struct dev_pm_opp *opp = NULL, *p_opp = NULL; ++ unsigned long target_freq; ++ ++ if (!p_dev || !p_opp_table || !opp_table || !freq) ++ return 0; ++ ++ p_opp = devfreq_recommended_opp(p_dev, freq, 0); ++ if (IS_ERR(p_opp)) ++ return 0; ++ ++ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp); ++ dev_pm_opp_put(p_opp); ++ ++ if (IS_ERR(opp)) ++ return 0; ++ ++ target_freq = dev_pm_opp_get_freq(opp); ++ dev_pm_opp_put(opp); ++ ++ return target_freq; ++} ++ ++static int get_target_freq_with_cpufreq(struct devfreq *devfreq, ++ unsigned long *target_freq) ++{ ++ struct devfreq_passive_data *p_data = ++ (struct devfreq_passive_data *)devfreq->data; ++ struct devfreq_cpu_data *parent_cpu_data; ++ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent; ++ unsigned long dev_min, dev_max; ++ unsigned long freq = 0; ++ ++ for_each_online_cpu(cpu) { ++ parent_cpu_data = p_data->parent_cpu_data[cpu]; ++ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu) ++ continue; ++ ++ /* Get target freq via required opps */ ++ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ; ++ freq = get_target_freq_by_required_opp(parent_cpu_data->dev, ++ parent_cpu_data->opp_table, ++ devfreq->opp_table, &cpu_cur); ++ if (freq) { ++ *target_freq = max(freq, *target_freq); ++ continue; ++ } ++ ++ /* Use interpolation if required opps is not available */ ++ devfreq_get_freq_range(devfreq, &dev_min, &dev_max); ++ ++ cpu_min = parent_cpu_data->min_freq; ++ cpu_max = parent_cpu_data->max_freq; ++ cpu_cur = parent_cpu_data->cur_freq; ++ ++ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min); ++ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100); ++ ++ *target_freq = max(freq, *target_freq); ++ } ++ ++ return 0; ++} ++ ++static int get_target_freq_with_devfreq(struct devfreq *devfreq, + unsigned long *freq) + { + struct devfreq_passive_data *p_data +@@ -99,6 +173,181 @@ no_required_opp: + return 0; + } + ++static int devfreq_passive_get_target_freq(struct devfreq *devfreq, ++ unsigned long *freq) ++{ ++ struct devfreq_passive_data *p_data = ++ (struct devfreq_passive_data *)devfreq->data; ++ int ret; ++ ++ if (!p_data) ++ return -EINVAL; ++ ++ /* ++ * If the devfreq device with passive governor has the specific method ++ * to determine the next frequency, should use the get_target_freq() ++ * of struct devfreq_passive_data. ++ */ ++ if (p_data->get_target_freq) ++ return p_data->get_target_freq(devfreq, freq); ++ ++ switch (p_data->parent_type) { ++ case DEVFREQ_PARENT_DEV: ++ ret = get_target_freq_with_devfreq(devfreq, freq); ++ break; ++ case CPUFREQ_PARENT_DEV: ++ ret = get_target_freq_with_cpufreq(devfreq, freq); ++ break; ++ default: ++ ret = -EINVAL; ++ dev_err(&devfreq->dev, "Invalid parent type\n"); ++ break; ++ } ++ ++ return ret; ++} ++ ++static int cpufreq_passive_notifier_call(struct notifier_block *nb, ++ unsigned long event, void *ptr) ++{ ++ struct devfreq_passive_data *p_data = ++ container_of(nb, struct devfreq_passive_data, nb); ++ struct devfreq *devfreq = (struct devfreq *)p_data->this; ++ struct devfreq_cpu_data *parent_cpu_data; ++ struct cpufreq_freqs *freqs = ptr; ++ unsigned int cur_freq; ++ int ret; ++ ++ if (event != CPUFREQ_POSTCHANGE || !freqs || ++ !p_data->parent_cpu_data[freqs->policy->cpu]) ++ return 0; ++ ++ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu]; ++ if (parent_cpu_data->cur_freq == freqs->new) ++ return 0; ++ ++ cur_freq = parent_cpu_data->cur_freq; ++ parent_cpu_data->cur_freq = freqs->new; ++ ++ mutex_lock(&devfreq->lock); ++ ret = devfreq_update_target(devfreq, freqs->new); ++ mutex_unlock(&devfreq->lock); ++ if (ret) { ++ parent_cpu_data->cur_freq = cur_freq; ++ dev_err(&devfreq->dev, "failed to update the frequency.\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq) ++{ ++ struct devfreq_passive_data *p_data ++ = (struct devfreq_passive_data *)devfreq->data; ++ struct devfreq_cpu_data *parent_cpu_data; ++ int cpu, ret; ++ ++ if (p_data->nb.notifier_call) { ++ ret = cpufreq_unregister_notifier(&p_data->nb, ++ CPUFREQ_TRANSITION_NOTIFIER); ++ if (ret < 0) ++ return ret; ++ } ++ ++ for_each_possible_cpu(cpu) { ++ parent_cpu_data = p_data->parent_cpu_data[cpu]; ++ if (!parent_cpu_data) ++ continue; ++ ++ if (parent_cpu_data->opp_table) ++ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); ++ kfree(parent_cpu_data); ++ } ++ ++ return 0; ++} ++ ++static int cpufreq_passive_register_notifier(struct devfreq *devfreq) ++{ ++ struct devfreq_passive_data *p_data ++ = (struct devfreq_passive_data *)devfreq->data; ++ struct device *dev = devfreq->dev.parent; ++ struct opp_table *opp_table = NULL; ++ struct devfreq_cpu_data *parent_cpu_data; ++ struct cpufreq_policy *policy; ++ struct device *cpu_dev; ++ unsigned int cpu; ++ int ret; ++ ++ p_data->nb.notifier_call = cpufreq_passive_notifier_call; ++ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER); ++ if (ret) { ++ dev_err(dev, "failed to register cpufreq notifier\n"); ++ p_data->nb.notifier_call = NULL; ++ goto err; ++ } ++ ++ for_each_possible_cpu(cpu) { ++ if (p_data->parent_cpu_data[cpu]) ++ continue; ++ ++ policy = cpufreq_cpu_get(cpu); ++ if (!policy) { ++ ret = -EPROBE_DEFER; ++ goto err; ++ } ++ ++ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data), ++ GFP_KERNEL); ++ if (!parent_cpu_data) { ++ ret = -ENOMEM; ++ goto err_put_policy; ++ } ++ ++ cpu_dev = get_cpu_device(cpu); ++ if (!cpu_dev) { ++ dev_err(dev, "failed to get cpu device\n"); ++ ret = -ENODEV; ++ goto err_free_cpu_data; ++ } ++ ++ opp_table = dev_pm_opp_get_opp_table(cpu_dev); ++ if (IS_ERR(opp_table)) { ++ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu); ++ ret = PTR_ERR(opp_table); ++ goto err_free_cpu_data; ++ } ++ ++ parent_cpu_data->dev = cpu_dev; ++ parent_cpu_data->opp_table = opp_table; ++ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus); ++ parent_cpu_data->cur_freq = policy->cur; ++ parent_cpu_data->min_freq = policy->cpuinfo.min_freq; ++ parent_cpu_data->max_freq = policy->cpuinfo.max_freq; ++ ++ p_data->parent_cpu_data[cpu] = parent_cpu_data; ++ cpufreq_cpu_put(policy); ++ } ++ ++ mutex_lock(&devfreq->lock); ++ ret = devfreq_update_target(devfreq, 0L); ++ mutex_unlock(&devfreq->lock); ++ if (ret) ++ dev_err(dev, "failed to update the frequency\n"); ++ ++ return ret; ++ ++err_free_cpu_data: ++ kfree(parent_cpu_data); ++err_put_policy: ++ cpufreq_cpu_put(policy); ++err: ++ WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); ++ ++ return ret; ++} ++ + static int devfreq_passive_notifier_call(struct notifier_block *nb, + unsigned long event, void *ptr) + { +@@ -131,30 +380,55 @@ static int devfreq_passive_notifier_call + return NOTIFY_DONE; + } + +-static int devfreq_passive_event_handler(struct devfreq *devfreq, +- unsigned int event, void *data) ++static int devfreq_passive_unregister_notifier(struct devfreq *devfreq) ++{ ++ struct devfreq_passive_data *p_data ++ = (struct devfreq_passive_data *)devfreq->data; ++ struct devfreq *parent = (struct devfreq *)p_data->parent; ++ struct notifier_block *nb = &p_data->nb; ++ ++ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER); ++} ++ ++static int devfreq_passive_register_notifier(struct devfreq *devfreq) + { + struct devfreq_passive_data *p_data + = (struct devfreq_passive_data *)devfreq->data; + struct devfreq *parent = (struct devfreq *)p_data->parent; + struct notifier_block *nb = &p_data->nb; +- int ret = 0; + + if (!parent) + return -EPROBE_DEFER; + ++ nb->notifier_call = devfreq_passive_notifier_call; ++ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER); ++} ++ ++static int devfreq_passive_event_handler(struct devfreq *devfreq, ++ unsigned int event, void *data) ++{ ++ struct devfreq_passive_data *p_data ++ = (struct devfreq_passive_data *)devfreq->data; ++ int ret = -EINVAL; ++ ++ if (!p_data) ++ return -EINVAL; ++ ++ if (!p_data->this) ++ p_data->this = devfreq; ++ + switch (event) { + case DEVFREQ_GOV_START: +- if (!p_data->this) +- p_data->this = devfreq; +- +- nb->notifier_call = devfreq_passive_notifier_call; +- ret = devfreq_register_notifier(parent, nb, +- DEVFREQ_TRANSITION_NOTIFIER); ++ if (p_data->parent_type == DEVFREQ_PARENT_DEV) ++ ret = devfreq_passive_register_notifier(devfreq); ++ else if (p_data->parent_type == CPUFREQ_PARENT_DEV) ++ ret = cpufreq_passive_register_notifier(devfreq); + break; + case DEVFREQ_GOV_STOP: +- WARN_ON(devfreq_unregister_notifier(parent, nb, +- DEVFREQ_TRANSITION_NOTIFIER)); ++ if (p_data->parent_type == DEVFREQ_PARENT_DEV) ++ WARN_ON(devfreq_passive_unregister_notifier(devfreq)); ++ else if (p_data->parent_type == CPUFREQ_PARENT_DEV) ++ WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); + break; + default: + break; +--- a/include/linux/devfreq.h ++++ b/include/linux/devfreq.h +@@ -38,6 +38,7 @@ enum devfreq_timer { + + struct devfreq; + struct devfreq_governor; ++struct devfreq_cpu_data; + struct thermal_cooling_device; + + /** +@@ -288,6 +289,11 @@ struct devfreq_simple_ondemand_data { + #endif + + #if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE) ++enum devfreq_parent_dev_type { ++ DEVFREQ_PARENT_DEV, ++ CPUFREQ_PARENT_DEV, ++}; ++ + /** + * struct devfreq_passive_data - ``void *data`` fed to struct devfreq + * and devfreq_add_device +@@ -299,8 +305,11 @@ struct devfreq_simple_ondemand_data { + * using governors except for passive governor. + * If the devfreq device has the specific method to decide + * the next frequency, should use this callback. +- * @this: the devfreq instance of own device. +- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list ++ * @parent_type: the parent type of the device. ++ * @this: the devfreq instance of own device. ++ * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or ++ * CPUFREQ_TRANSITION_NOTIFIER list. ++ * @parent_cpu_data: the state min/max/current frequency of all online cpu's. + * + * The devfreq_passive_data have to set the devfreq instance of parent + * device with governors except for the passive governor. But, don't need to +@@ -314,9 +323,13 @@ struct devfreq_passive_data { + /* Optional callback to decide the next frequency of passvice device */ + int (*get_target_freq)(struct devfreq *this, unsigned long *freq); + ++ /* Should set the type of parent device */ ++ enum devfreq_parent_dev_type parent_type; ++ + /* For passive governor's internal use. Don't need to set them */ + struct devfreq *this; + struct notifier_block nb; ++ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS]; + }; + #endif + diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch new file mode 100644 index 0000000000..cb10bd1b62 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/111-v5.19-03-PM-devfreq-passive-Reduce-duplicate-code-when-passiv.patch @@ -0,0 +1,110 @@ +From 05723e71234b60a1a47313ea1a889797ec648f1c Mon Sep 17 00:00:00 2001 +From: Chanwoo Choi +Date: Tue, 2 Mar 2021 17:22:50 +0900 +Subject: [PATCH 3/5] PM / devfreq: passive: Reduce duplicate code when + passive_devfreq case + +In order to keep the consistent coding style between passive_devfreq +and passive_cpufreq, use common code for handling required opp property. +Also remove the unneed conditional statement and unify the comment +of both passive_devfreq and passive_cpufreq when getting the target frequency. + +Tested-by: Chen-Yu Tsai +Tested-by: Johnson Wang +Signed-off-by: Chanwoo Choi +--- + drivers/devfreq/governor_passive.c | 66 ++++-------------------------- + 1 file changed, 8 insertions(+), 58 deletions(-) + +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -93,65 +93,16 @@ static int get_target_freq_with_devfreq( + = (struct devfreq_passive_data *)devfreq->data; + struct devfreq *parent_devfreq = (struct devfreq *)p_data->parent; + unsigned long child_freq = ULONG_MAX; +- struct dev_pm_opp *opp, *p_opp; + int i, count; + +- /* +- * If the devfreq device with passive governor has the specific method +- * to determine the next frequency, should use the get_target_freq() +- * of struct devfreq_passive_data. +- */ +- if (p_data->get_target_freq) +- return p_data->get_target_freq(devfreq, freq); +- +- /* +- * If the parent and passive devfreq device uses the OPP table, +- * get the next frequency by using the OPP table. +- */ +- +- /* +- * - parent devfreq device uses the governors except for passive. +- * - passive devfreq device uses the passive governor. +- * +- * Each devfreq has the OPP table. After deciding the new frequency +- * from the governor of parent devfreq device, the passive governor +- * need to get the index of new frequency on OPP table of parent +- * device. And then the index is used for getting the suitable +- * new frequency for passive devfreq device. +- */ +- if (!devfreq->profile || !devfreq->profile->freq_table +- || devfreq->profile->max_state <= 0) +- return -EINVAL; +- +- /* +- * The passive governor have to get the correct frequency from OPP +- * list of parent device. Because in this case, *freq is temporary +- * value which is decided by ondemand governor. +- */ +- if (devfreq->opp_table && parent_devfreq->opp_table) { +- p_opp = devfreq_recommended_opp(parent_devfreq->dev.parent, +- freq, 0); +- if (IS_ERR(p_opp)) +- return PTR_ERR(p_opp); +- +- opp = dev_pm_opp_xlate_required_opp(parent_devfreq->opp_table, +- devfreq->opp_table, p_opp); +- dev_pm_opp_put(p_opp); +- +- if (IS_ERR(opp)) +- goto no_required_opp; +- +- *freq = dev_pm_opp_get_freq(opp); +- dev_pm_opp_put(opp); +- +- return 0; +- } ++ /* Get target freq via required opps */ ++ child_freq = get_target_freq_by_required_opp(parent_devfreq->dev.parent, ++ parent_devfreq->opp_table, ++ devfreq->opp_table, freq); ++ if (child_freq) ++ goto out; + +-no_required_opp: +- /* +- * Get the OPP table's index of decided frequency by governor +- * of parent device. +- */ ++ /* Use interpolation if required opps is not available */ + for (i = 0; i < parent_devfreq->profile->max_state; i++) + if (parent_devfreq->profile->freq_table[i] == *freq) + break; +@@ -159,7 +110,6 @@ no_required_opp: + if (i == parent_devfreq->profile->max_state) + return -EINVAL; + +- /* Get the suitable frequency by using index of parent device. */ + if (i < devfreq->profile->max_state) { + child_freq = devfreq->profile->freq_table[i]; + } else { +@@ -167,7 +117,7 @@ no_required_opp: + child_freq = devfreq->profile->freq_table[count - 1]; + } + +- /* Return the suitable frequency for passive device. */ ++out: + *freq = child_freq; + + return 0; diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch new file mode 100644 index 0000000000..12de8af22e --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/111-v5.19-04-PM-devfreq-passive-Keep-cpufreq_policy-for-possible-.patch @@ -0,0 +1,232 @@ +From 26984d9d581e5049bd75091d2e789b9cc3ea12e0 Mon Sep 17 00:00:00 2001 +From: Chanwoo Choi +Date: Wed, 27 Apr 2022 03:49:19 +0900 +Subject: [PATCH 4/5] PM / devfreq: passive: Keep cpufreq_policy for possible + cpus + +The passive governor requires the cpu data to get the next target frequency +of devfreq device if depending on cpu. In order to reduce the unnecessary +memory data, keep cpufreq_policy data for possible cpus instead of NR_CPU. + +Tested-by: Chen-Yu Tsai +Tested-by: Johnson Wang +Signed-off-by: Chanwoo Choi +--- + drivers/devfreq/governor.h | 3 ++ + drivers/devfreq/governor_passive.c | 75 +++++++++++++++++++++++------- + include/linux/devfreq.h | 4 +- + 3 files changed, 64 insertions(+), 18 deletions(-) + +--- a/drivers/devfreq/governor.h ++++ b/drivers/devfreq/governor.h +@@ -49,6 +49,7 @@ + + /** + * struct devfreq_cpu_data - Hold the per-cpu data ++ * @node: list node + * @dev: reference to cpu device. + * @first_cpu: the cpumask of the first cpu of a policy. + * @opp_table: reference to cpu opp table. +@@ -60,6 +61,8 @@ + * This is auto-populated by the governor. + */ + struct devfreq_cpu_data { ++ struct list_head node; ++ + struct device *dev; + unsigned int first_cpu; + +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -1,4 +1,4 @@ +-// SPDX-License-Identifier: GPL-2.0-only ++ // SPDX-License-Identifier: GPL-2.0-only + /* + * linux/drivers/devfreq/governor_passive.c + * +@@ -18,6 +18,22 @@ + + #define HZ_PER_KHZ 1000 + ++static struct devfreq_cpu_data * ++get_parent_cpu_data(struct devfreq_passive_data *p_data, ++ struct cpufreq_policy *policy) ++{ ++ struct devfreq_cpu_data *parent_cpu_data; ++ ++ if (!p_data || !policy) ++ return NULL; ++ ++ list_for_each_entry(parent_cpu_data, &p_data->cpu_data_list, node) ++ if (parent_cpu_data->first_cpu == cpumask_first(policy->related_cpus)) ++ return parent_cpu_data; ++ ++ return NULL; ++} ++ + static unsigned long get_target_freq_by_required_opp(struct device *p_dev, + struct opp_table *p_opp_table, + struct opp_table *opp_table, +@@ -51,14 +67,24 @@ static int get_target_freq_with_cpufreq( + struct devfreq_passive_data *p_data = + (struct devfreq_passive_data *)devfreq->data; + struct devfreq_cpu_data *parent_cpu_data; ++ struct cpufreq_policy *policy; + unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent; + unsigned long dev_min, dev_max; + unsigned long freq = 0; ++ int ret = 0; + + for_each_online_cpu(cpu) { +- parent_cpu_data = p_data->parent_cpu_data[cpu]; +- if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu) ++ policy = cpufreq_cpu_get(cpu); ++ if (!policy) { ++ ret = -EINVAL; ++ continue; ++ } ++ ++ parent_cpu_data = get_parent_cpu_data(p_data, policy); ++ if (!parent_cpu_data) { ++ cpufreq_cpu_put(policy); + continue; ++ } + + /* Get target freq via required opps */ + cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ; +@@ -67,6 +93,7 @@ static int get_target_freq_with_cpufreq( + devfreq->opp_table, &cpu_cur); + if (freq) { + *target_freq = max(freq, *target_freq); ++ cpufreq_cpu_put(policy); + continue; + } + +@@ -81,9 +108,10 @@ static int get_target_freq_with_cpufreq( + freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100); + + *target_freq = max(freq, *target_freq); ++ cpufreq_cpu_put(policy); + } + +- return 0; ++ return ret; + } + + static int get_target_freq_with_devfreq(struct devfreq *devfreq, +@@ -168,12 +196,11 @@ static int cpufreq_passive_notifier_call + unsigned int cur_freq; + int ret; + +- if (event != CPUFREQ_POSTCHANGE || !freqs || +- !p_data->parent_cpu_data[freqs->policy->cpu]) ++ if (event != CPUFREQ_POSTCHANGE || !freqs) + return 0; + +- parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu]; +- if (parent_cpu_data->cur_freq == freqs->new) ++ parent_cpu_data = get_parent_cpu_data(p_data, freqs->policy); ++ if (!parent_cpu_data || parent_cpu_data->cur_freq == freqs->new) + return 0; + + cur_freq = parent_cpu_data->cur_freq; +@@ -196,7 +223,7 @@ static int cpufreq_passive_unregister_no + struct devfreq_passive_data *p_data + = (struct devfreq_passive_data *)devfreq->data; + struct devfreq_cpu_data *parent_cpu_data; +- int cpu, ret; ++ int cpu, ret = 0; + + if (p_data->nb.notifier_call) { + ret = cpufreq_unregister_notifier(&p_data->nb, +@@ -206,16 +233,26 @@ static int cpufreq_passive_unregister_no + } + + for_each_possible_cpu(cpu) { +- parent_cpu_data = p_data->parent_cpu_data[cpu]; +- if (!parent_cpu_data) ++ struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); ++ if (!policy) { ++ ret = -EINVAL; ++ continue; ++ } ++ ++ parent_cpu_data = get_parent_cpu_data(p_data, policy); ++ if (!parent_cpu_data) { ++ cpufreq_cpu_put(policy); + continue; ++ } + ++ list_del(&parent_cpu_data->node); + if (parent_cpu_data->opp_table) + dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); + kfree(parent_cpu_data); ++ cpufreq_cpu_put(policy); + } + +- return 0; ++ return ret; + } + + static int cpufreq_passive_register_notifier(struct devfreq *devfreq) +@@ -230,6 +267,9 @@ static int cpufreq_passive_register_noti + unsigned int cpu; + int ret; + ++ p_data->cpu_data_list ++ = (struct list_head)LIST_HEAD_INIT(p_data->cpu_data_list); ++ + p_data->nb.notifier_call = cpufreq_passive_notifier_call; + ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER); + if (ret) { +@@ -239,15 +279,18 @@ static int cpufreq_passive_register_noti + } + + for_each_possible_cpu(cpu) { +- if (p_data->parent_cpu_data[cpu]) +- continue; +- + policy = cpufreq_cpu_get(cpu); + if (!policy) { + ret = -EPROBE_DEFER; + goto err; + } + ++ parent_cpu_data = get_parent_cpu_data(p_data, policy); ++ if (parent_cpu_data) { ++ cpufreq_cpu_put(policy); ++ continue; ++ } ++ + parent_cpu_data = kzalloc(sizeof(*parent_cpu_data), + GFP_KERNEL); + if (!parent_cpu_data) { +@@ -276,7 +319,7 @@ static int cpufreq_passive_register_noti + parent_cpu_data->min_freq = policy->cpuinfo.min_freq; + parent_cpu_data->max_freq = policy->cpuinfo.max_freq; + +- p_data->parent_cpu_data[cpu] = parent_cpu_data; ++ list_add_tail(&parent_cpu_data->node, &p_data->cpu_data_list); + cpufreq_cpu_put(policy); + } + +--- a/include/linux/devfreq.h ++++ b/include/linux/devfreq.h +@@ -309,7 +309,7 @@ enum devfreq_parent_dev_type { + * @this: the devfreq instance of own device. + * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or + * CPUFREQ_TRANSITION_NOTIFIER list. +- * @parent_cpu_data: the state min/max/current frequency of all online cpu's. ++ * @cpu_data_list: the list of cpu frequency data for all cpufreq_policy. + * + * The devfreq_passive_data have to set the devfreq instance of parent + * device with governors except for the passive governor. But, don't need to +@@ -329,7 +329,7 @@ struct devfreq_passive_data { + /* For passive governor's internal use. Don't need to set them */ + struct devfreq *this; + struct notifier_block nb; +- struct devfreq_cpu_data *parent_cpu_data[NR_CPUS]; ++ struct list_head cpu_data_list; + }; + #endif + diff --git a/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch b/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch new file mode 100644 index 0000000000..69160fd77a --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/111-v5.19-05-PM-devfreq-passive-Return-non-error-when-not-support.patch @@ -0,0 +1,31 @@ +From 42d2607d91c4ec37ea1970899c2d614824f3014b Mon Sep 17 00:00:00 2001 +From: Chanwoo Choi +Date: Thu, 19 May 2022 10:07:53 +0900 +Subject: [PATCH 5/5] PM / devfreq: passive: Return non-error when + not-supported event is required + +Each devfreq governor specifies the supported governor event +such as GOV_START and GOV_STOP. When not-supported event is required, +just return non-error. But, commit ce9a0d88d97a ("PM / devfreq: Add +cpu based scaling support to passive governor") returned the error +value. So that return non-error value when not-supported event is required. + +Fixes: ce9a0d88d97a ("PM / devfreq: Add cpu based scaling support to passive governor") +Reported-by: Marek Szyprowski +Signed-off-by: Chanwoo Choi +Signed-off-by: Rafael J. Wysocki +--- + drivers/devfreq/governor_passive.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -402,7 +402,7 @@ static int devfreq_passive_event_handler + { + struct devfreq_passive_data *p_data + = (struct devfreq_passive_data *)devfreq->data; +- int ret = -EINVAL; ++ int ret = 0; + + if (!p_data) + return -EINVAL; diff --git a/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch b/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch new file mode 100644 index 0000000000..3d2bb2de05 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/112-v5.19-PM-devfreq-Fix-kernel-warning-with-cpufreq-passive-r.patch @@ -0,0 +1,31 @@ +From 82c66d2bbbeda9e493487e7413769087a0b46250 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Mon, 20 Jun 2022 00:29:39 +0200 +Subject: [PATCH 1/1] PM / devfreq: Fix kernel warning with cpufreq passive + register fail + +Remove cpufreq_passive_unregister_notifier from +cpufreq_passive_register_notifier in case of error as devfreq core +already call unregister on GOV_START fail. + +This fix the kernel always printing a WARN on governor PROBE_DEFER as +cpufreq_passive_unregister_notifier is called two times and return +error on the second call as the cpufreq is already unregistered. + +Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") +Signed-off-by: Christian Marangi +Signed-off-by: Chanwoo Choi +--- + drivers/devfreq/governor_passive.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -336,7 +336,6 @@ err_free_cpu_data: + err_put_policy: + cpufreq_cpu_put(policy); + err: +- WARN_ON(cpufreq_passive_unregister_notifier(devfreq)); + + return ret; + } diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch new file mode 100644 index 0000000000..0883424548 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/113-v5.19-01-PM-devfreq-Fix-cpufreq-passive-unregister-errorin.patch @@ -0,0 +1,85 @@ +From 8953603eb5447be52f6fc3d8fcae1b3ce9899189 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Mon, 6 Jun 2022 11:58:49 +0200 +Subject: [PATCH v4 1/4] PM / devfreq: Fix cpufreq passive unregister erroring + on PROBE_DEFER + +With the passive governor, the cpu based scaling can PROBE_DEFER due to +the fact that CPU policy are not ready. +The cpufreq passive unregister notifier is called both from the +GOV_START errors and for the GOV_STOP and assume the notifier is +successfully registred every time. With GOV_START failing it's wrong to +loop over each possible CPU since the register path has failed for +some CPU policy not ready. Change the logic and unregister the notifer +based on the current allocated parent_cpu_data list to correctly handle +errors and the governor unregister path. + +Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") +Signed-off-by: Christian 'Ansuel' Marangi +--- + drivers/devfreq/governor_passive.c | 39 +++++++++++++----------------- + 1 file changed, 17 insertions(+), 22 deletions(-) + +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -34,6 +34,20 @@ get_parent_cpu_data(struct devfreq_passi + return NULL; + } + ++static void delete_parent_cpu_data(struct devfreq_passive_data *p_data) ++{ ++ struct devfreq_cpu_data *parent_cpu_data, *tmp; ++ ++ list_for_each_entry_safe(parent_cpu_data, tmp, &p_data->cpu_data_list, node) { ++ list_del(&parent_cpu_data->node); ++ ++ if (parent_cpu_data->opp_table) ++ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); ++ ++ kfree(parent_cpu_data); ++ } ++} ++ + static unsigned long get_target_freq_by_required_opp(struct device *p_dev, + struct opp_table *p_opp_table, + struct opp_table *opp_table, +@@ -222,8 +236,7 @@ static int cpufreq_passive_unregister_no + { + struct devfreq_passive_data *p_data + = (struct devfreq_passive_data *)devfreq->data; +- struct devfreq_cpu_data *parent_cpu_data; +- int cpu, ret = 0; ++ int ret; + + if (p_data->nb.notifier_call) { + ret = cpufreq_unregister_notifier(&p_data->nb, +@@ -232,27 +245,9 @@ static int cpufreq_passive_unregister_no + return ret; + } + +- for_each_possible_cpu(cpu) { +- struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); +- if (!policy) { +- ret = -EINVAL; +- continue; +- } +- +- parent_cpu_data = get_parent_cpu_data(p_data, policy); +- if (!parent_cpu_data) { +- cpufreq_cpu_put(policy); +- continue; +- } +- +- list_del(&parent_cpu_data->node); +- if (parent_cpu_data->opp_table) +- dev_pm_opp_put_opp_table(parent_cpu_data->opp_table); +- kfree(parent_cpu_data); +- cpufreq_cpu_put(policy); +- } ++ delete_parent_cpu_data(p_data); + +- return ret; ++ return 0; + } + + static int cpufreq_passive_register_notifier(struct devfreq *devfreq) diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch new file mode 100644 index 0000000000..84cb67bc99 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/113-v5.19-02-PM-devfreq-Fix-kernel-panic-with-cpu-based-scaling-t.patch @@ -0,0 +1,39 @@ +From 57e00b40033a376de3f3cf0bb9bf7590d2dd679d Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Tue, 14 Jun 2022 13:06:59 +0200 +Subject: [PATCH 1/1] PM / devfreq: Fix kernel panic with cpu based scaling to + passive gov + +The cpufreq passive register notifier can PROBE_DEFER and the devfreq +struct is freed and then reallocaed on probe retry. +The current logic assume that the code can't PROBE_DEFER so the devfreq +struct in the this variable in devfreq_passive_data is assumed to be +(if already set) always correct. +This cause kernel panic as the code try to access the wrong address. +To correctly handle this, update the this variable in +devfreq_passive_data to the devfreq reallocated struct. + +Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") +Signed-off-by: Christian 'Ansuel' Marangi +Signed-off-by: Chanwoo Choi +--- + drivers/devfreq/governor_passive.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c +index 72c67979ebe1..091a69e1f487 100644 +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -407,8 +407,7 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq, + if (!p_data) + return -EINVAL; + +- if (!p_data->this) +- p_data->this = devfreq; ++ p_data->this = devfreq; + + switch (event) { + case DEVFREQ_GOV_START: +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch new file mode 100644 index 0000000000..0813140eca --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/113-v5.19-03-PM-devfreq-Rework-freq_table-to-be-local-to-devfr.patch @@ -0,0 +1,269 @@ +From 46d05776a1a5dd8eb479e868f5ff4f4b97d68238 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Mon, 6 Jun 2022 12:39:19 +0200 +Subject: [PATCH v4 3/4] PM / devfreq: Rework freq_table to be local to devfreq + struct + +Currently we reference the freq_table to the profile defined one and we +make changes on it. Devfreq never supported PROBE_DEFER before the cpu +based scaling support to the passive governor and assumed that a devfreq +device could only had error and be done with it. +Now that a device can PROBE_DEFER a rework to the freq_table logic is +required. + +If a device PROBE_DEFER on the GOV_START, the freq_table is already set +in the device profile struct and its init is skipped. This is due to the +fact that it's common for devs to declare this kind of struct static. +This cause the devfreq logic to find a freq table declared (freq_table +not NULL) with random data and poiting to the old addrs freed by devm. + +This problem CAN be solved by devs by clearing the freq_table in their +profile struct on driver exit path but it should not be trusted and it +looks to use a flawed logic. + +A better solution is to move the freq_table and max_state to the +devfreq struct and never change the profile struct. +This permit to correctly handle PROBE_DEFER since the devfreq struct is +reallocated and contains new values. +Also the profile struct should only be used to init the driver and should +not be used by the devfreq to write the freq_table if it's not provided +by the driver. + +Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") +Signed-off-by: Christian 'Ansuel' Marangi +--- + drivers/devfreq/devfreq.c | 71 ++++++++++++++---------------- + drivers/devfreq/governor_passive.c | 14 +++--- + include/linux/devfreq.h | 4 ++ + 3 files changed, 45 insertions(+), 44 deletions(-) + +--- a/drivers/devfreq/devfreq.c ++++ b/drivers/devfreq/devfreq.c +@@ -123,7 +123,7 @@ void devfreq_get_freq_range(struct devfr + unsigned long *min_freq, + unsigned long *max_freq) + { +- unsigned long *freq_table = devfreq->profile->freq_table; ++ unsigned long *freq_table = devfreq->freq_table; + s32 qos_min_freq, qos_max_freq; + + lockdep_assert_held(&devfreq->lock); +@@ -133,11 +133,11 @@ void devfreq_get_freq_range(struct devfr + * The devfreq drivers can initialize this in either ascending or + * descending order and devfreq core supports both. + */ +- if (freq_table[0] < freq_table[devfreq->profile->max_state - 1]) { ++ if (freq_table[0] < freq_table[devfreq->max_state - 1]) { + *min_freq = freq_table[0]; +- *max_freq = freq_table[devfreq->profile->max_state - 1]; ++ *max_freq = freq_table[devfreq->max_state - 1]; + } else { +- *min_freq = freq_table[devfreq->profile->max_state - 1]; ++ *min_freq = freq_table[devfreq->max_state - 1]; + *max_freq = freq_table[0]; + } + +@@ -169,8 +169,8 @@ static int devfreq_get_freq_level(struct + { + int lev; + +- for (lev = 0; lev < devfreq->profile->max_state; lev++) +- if (freq == devfreq->profile->freq_table[lev]) ++ for (lev = 0; lev < devfreq->max_state; lev++) ++ if (freq == devfreq->freq_table[lev]) + return lev; + + return -EINVAL; +@@ -178,7 +178,6 @@ static int devfreq_get_freq_level(struct + + static int set_freq_table(struct devfreq *devfreq) + { +- struct devfreq_dev_profile *profile = devfreq->profile; + struct dev_pm_opp *opp; + unsigned long freq; + int i, count; +@@ -188,25 +187,22 @@ static int set_freq_table(struct devfreq + if (count <= 0) + return -EINVAL; + +- profile->max_state = count; +- profile->freq_table = devm_kcalloc(devfreq->dev.parent, +- profile->max_state, +- sizeof(*profile->freq_table), +- GFP_KERNEL); +- if (!profile->freq_table) { +- profile->max_state = 0; ++ devfreq->max_state = count; ++ devfreq->freq_table = devm_kcalloc(devfreq->dev.parent, ++ devfreq->max_state, ++ sizeof(*devfreq->freq_table), ++ GFP_KERNEL); ++ if (!devfreq->freq_table) + return -ENOMEM; +- } + +- for (i = 0, freq = 0; i < profile->max_state; i++, freq++) { ++ for (i = 0, freq = 0; i < devfreq->max_state; i++, freq++) { + opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &freq); + if (IS_ERR(opp)) { +- devm_kfree(devfreq->dev.parent, profile->freq_table); +- profile->max_state = 0; ++ devm_kfree(devfreq->dev.parent, devfreq->freq_table); + return PTR_ERR(opp); + } + dev_pm_opp_put(opp); +- profile->freq_table[i] = freq; ++ devfreq->freq_table[i] = freq; + } + + return 0; +@@ -246,7 +242,7 @@ int devfreq_update_status(struct devfreq + + if (lev != prev_lev) { + devfreq->stats.trans_table[ +- (prev_lev * devfreq->profile->max_state) + lev]++; ++ (prev_lev * devfreq->max_state) + lev]++; + devfreq->stats.total_trans++; + } + +@@ -835,6 +831,9 @@ struct devfreq *devfreq_add_device(struc + if (err < 0) + goto err_dev; + mutex_lock(&devfreq->lock); ++ } else { ++ devfreq->freq_table = devfreq->profile->freq_table; ++ devfreq->max_state = devfreq->profile->max_state; + } + + devfreq->scaling_min_freq = find_available_min_freq(devfreq); +@@ -870,8 +869,8 @@ struct devfreq *devfreq_add_device(struc + + devfreq->stats.trans_table = devm_kzalloc(&devfreq->dev, + array3_size(sizeof(unsigned int), +- devfreq->profile->max_state, +- devfreq->profile->max_state), ++ devfreq->max_state, ++ devfreq->max_state), + GFP_KERNEL); + if (!devfreq->stats.trans_table) { + mutex_unlock(&devfreq->lock); +@@ -880,7 +879,7 @@ struct devfreq *devfreq_add_device(struc + } + + devfreq->stats.time_in_state = devm_kcalloc(&devfreq->dev, +- devfreq->profile->max_state, ++ devfreq->max_state, + sizeof(*devfreq->stats.time_in_state), + GFP_KERNEL); + if (!devfreq->stats.time_in_state) { +@@ -1639,9 +1638,9 @@ static ssize_t available_frequencies_sho + + mutex_lock(&df->lock); + +- for (i = 0; i < df->profile->max_state; i++) ++ for (i = 0; i < df->max_state; i++) + count += scnprintf(&buf[count], (PAGE_SIZE - count - 2), +- "%lu ", df->profile->freq_table[i]); ++ "%lu ", df->freq_table[i]); + + mutex_unlock(&df->lock); + /* Truncate the trailing space */ +@@ -1664,7 +1663,7 @@ static ssize_t trans_stat_show(struct de + + if (!df->profile) + return -EINVAL; +- max_state = df->profile->max_state; ++ max_state = df->max_state; + + if (max_state == 0) + return sprintf(buf, "Not Supported.\n"); +@@ -1681,19 +1680,17 @@ static ssize_t trans_stat_show(struct de + len += sprintf(buf + len, " :"); + for (i = 0; i < max_state; i++) + len += sprintf(buf + len, "%10lu", +- df->profile->freq_table[i]); ++ df->freq_table[i]); + + len += sprintf(buf + len, " time(ms)\n"); + + for (i = 0; i < max_state; i++) { +- if (df->profile->freq_table[i] +- == df->previous_freq) { ++ if (df->freq_table[i] == df->previous_freq) + len += sprintf(buf + len, "*"); +- } else { ++ else + len += sprintf(buf + len, " "); +- } +- len += sprintf(buf + len, "%10lu:", +- df->profile->freq_table[i]); ++ ++ len += sprintf(buf + len, "%10lu:", df->freq_table[i]); + for (j = 0; j < max_state; j++) + len += sprintf(buf + len, "%10u", + df->stats.trans_table[(i * max_state) + j]); +@@ -1717,7 +1714,7 @@ static ssize_t trans_stat_store(struct d + if (!df->profile) + return -EINVAL; + +- if (df->profile->max_state == 0) ++ if (df->max_state == 0) + return count; + + err = kstrtoint(buf, 10, &value); +@@ -1725,11 +1722,11 @@ static ssize_t trans_stat_store(struct d + return -EINVAL; + + mutex_lock(&df->lock); +- memset(df->stats.time_in_state, 0, (df->profile->max_state * ++ memset(df->stats.time_in_state, 0, (df->max_state * + sizeof(*df->stats.time_in_state))); + memset(df->stats.trans_table, 0, array3_size(sizeof(unsigned int), +- df->profile->max_state, +- df->profile->max_state)); ++ df->max_state, ++ df->max_state)); + df->stats.total_trans = 0; + df->stats.last_update = get_jiffies_64(); + mutex_unlock(&df->lock); +--- a/drivers/devfreq/governor_passive.c ++++ b/drivers/devfreq/governor_passive.c +@@ -145,18 +145,18 @@ static int get_target_freq_with_devfreq( + goto out; + + /* Use interpolation if required opps is not available */ +- for (i = 0; i < parent_devfreq->profile->max_state; i++) +- if (parent_devfreq->profile->freq_table[i] == *freq) ++ for (i = 0; i < parent_devfreq->max_state; i++) ++ if (parent_devfreq->freq_table[i] == *freq) + break; + +- if (i == parent_devfreq->profile->max_state) ++ if (i == parent_devfreq->max_state) + return -EINVAL; + +- if (i < devfreq->profile->max_state) { +- child_freq = devfreq->profile->freq_table[i]; ++ if (i < devfreq->max_state) { ++ child_freq = devfreq->freq_table[i]; + } else { +- count = devfreq->profile->max_state; +- child_freq = devfreq->profile->freq_table[count - 1]; ++ count = devfreq->max_state; ++ child_freq = devfreq->freq_table[count - 1]; + } + + out: +--- a/include/linux/devfreq.h ++++ b/include/linux/devfreq.h +@@ -185,6 +185,10 @@ struct devfreq { + struct notifier_block nb; + struct delayed_work work; + ++ /* devfreq local freq_table */ ++ unsigned long *freq_table; ++ unsigned int max_state; ++ + unsigned long previous_freq; + struct devfreq_dev_status last_status; + diff --git a/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch b/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch new file mode 100644 index 0000000000..cfdef8d6c5 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/113-v5.19-04-PM-devfreq-Mute-warning-on-governor-PROBE_DEFER.patch @@ -0,0 +1,28 @@ +From eee9f767c41b03a2744d4b0f0c1a144e4ff41e78 Mon Sep 17 00:00:00 2001 +From: Christian 'Ansuel' Marangi +Date: Mon, 6 Jun 2022 13:01:02 +0200 +Subject: [PATCH v4 4/4] PM / devfreq: Mute warning on governor PROBE_DEFER + +Don't print warning when a governor PROBE_DEFER as it's not a real +GOV_START fail. + +Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor") +Signed-off-by: Christian 'Ansuel' Marangi +--- + drivers/devfreq/devfreq.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/devfreq/devfreq.c ++++ b/drivers/devfreq/devfreq.c +@@ -931,8 +931,9 @@ struct devfreq *devfreq_add_device(struc + err = devfreq->governor->event_handler(devfreq, DEVFREQ_GOV_START, + NULL); + if (err) { +- dev_err(dev, "%s: Unable to start governor for the device\n", +- __func__); ++ dev_err_probe(dev, err, ++ "%s: Unable to start governor for the device\n", ++ __func__); + goto err_init; + } + create_sysfs_files(devfreq, devfreq->governor); From 25aa65304c43de8327b20342d7eb13e5532c8e88 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:17:19 +0200 Subject: [PATCH 29/43] ipq806x: 5.15: add new version of cache cpu scaling driver Use a new implementation by using a devfreq driver to scale the shared cache of the krait cpu cores. Signed-off-by: Christian Marangi --- ...qcom-cpufreq-nvmem-support-specific-.patch | 51 -- ...q-add-Krait-dedicated-scaling-driver.patch | 713 ------------------ ...ufreq-add-qcom-krait-cpufreq-binding.patch | 237 ------ ...-L2-Krait-Cache-devfreq-scaling-driv.patch | 242 ++++++ ...-krait-cache-compatible-for-ipq806x-.patch | 50 ++ 5 files changed, 292 insertions(+), 1001 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch delete mode 100644 target/linux/ipq806x/patches-5.15/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch delete mode 100644 target/linux/ipq806x/patches-5.15/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch create mode 100644 target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch create mode 100644 target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch diff --git a/target/linux/ipq806x/patches-5.15/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch b/target/linux/ipq806x/patches-5.15/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch deleted file mode 100644 index 19c3d096c4..0000000000 --- a/target/linux/ipq806x/patches-5.15/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch +++ /dev/null @@ -1,51 +0,0 @@ -From a206d4061f1cc2c5cd17ee45c53a0ba711e48e6d Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 16:42:52 +0100 -Subject: [PATCH 3/3] drivers: cpufreq: qcom-cpufreq-nvmem: support specific - cpufreq driver - -Add support for specific cpufreq driver for qcom-cpufreq-nvmem driver. - -Signed-off-by: Ansuel Smith ---- - drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -52,6 +52,7 @@ struct qcom_cpufreq_match_data { - char **pvs_name, - struct qcom_cpufreq_drv *drv); - const char **genpd_names; -+ const char *cpufreq_driver; - }; - - struct qcom_cpufreq_drv { -@@ -250,6 +251,7 @@ static const struct qcom_cpufreq_match_d - - static const struct qcom_cpufreq_match_data match_data_krait = { - .get_version = qcom_cpufreq_krait_name_version, -+ .cpufreq_driver = "krait-cpufreq", - }; - - static const char *qcs404_genpd_names[] = { "cpr", NULL }; -@@ -385,6 +387,19 @@ static int qcom_cpufreq_probe(struct pla - } - } - -+ if (drv->data->cpufreq_driver) { -+ cpufreq_dt_pdev = platform_device_register_simple( -+ drv->data->cpufreq_driver, -1, NULL, 0); -+ if (!IS_ERR(cpufreq_dt_pdev)) { -+ platform_set_drvdata(pdev, drv); -+ return 0; -+ } else { -+ dev_err(cpu_dev, -+ "Failed to register dedicated %s cpufreq\n", -+ drv->data->cpufreq_driver); -+ } -+ } -+ - cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, - NULL, 0); - if (!IS_ERR(cpufreq_dt_pdev)) { diff --git a/target/linux/ipq806x/patches-5.15/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch b/target/linux/ipq806x/patches-5.15/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch deleted file mode 100644 index a3896f2fc2..0000000000 --- a/target/linux/ipq806x/patches-5.15/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch +++ /dev/null @@ -1,713 +0,0 @@ -From cc41a266280cad0b55319e614167c88dff344248 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 22 Feb 2020 16:33:10 +0100 -Subject: [PATCH 1/8] cpufreq: add Krait dedicated scaling driver - -This new driver is based on generic cpufreq-dt driver. -Krait SoCs have 2-4 cpu and one shared L2 cache that can -operate at different frequency based on the maximum cpu clk -across all core. -L2 frequency and voltage are scaled on every frequency change -if needed. On Krait SoCs is present a bug that can cause -transition problem between frequency bin, to workaround this -on more than one transition, the L2 frequency is first set to the -base rate and then to the target rate. -The L2 frequency use the OPP framework and use the opp-level -bindings to link the l2 freq to different cpu freq. This is needed -as the Krait l2 clk are note mapped 1:1 to the core clks and some -of the l2 clk is set based on a range of the cpu clks. If the driver -find a broken config (for example no opp-level set) the l2 scaling is -skipped. - -Signed-off-by: Ansuel Smith ---- - drivers/cpufreq/Kconfig.arm | 14 +- - drivers/cpufreq/Makefile | 2 + - drivers/cpufreq/qcom-cpufreq-krait.c | 589 +++++++++++++++++++++++++++ - 3 files changed, 604 insertions(+), 1 deletion(-) - create mode 100644 drivers/cpufreq/qcom-cpufreq-krait.c - ---- a/drivers/cpufreq/Kconfig.arm -+++ b/drivers/cpufreq/Kconfig.arm -@@ -172,6 +172,18 @@ config ARM_QCOM_CPUFREQ_HW - The driver implements the cpufreq interface for this HW engine. - Say Y if you want to support CPUFreq HW. - -+config ARM_QCOM_CPUFREQ_KRAIT -+ tristate "CPU Frequency scaling support for Krait SoCs" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select PM_OPP -+ select ARM_QCOM_CPUFREQ_NVMEM -+ help -+ This adds the CPUFreq driver for Qualcomm Krait SoC based boards. -+ This scale the cache clk and regulator based on the different cpu -+ clks when scaling the different cores clk. -+ -+ If in doubt, say N. -+ - config ARM_RASPBERRYPI_CPUFREQ - tristate "Raspberry Pi cpufreq support" - depends on CLK_RASPBERRYPI || COMPILE_TEST -@@ -356,4 +368,4 @@ config ARM_PXA2xx_CPUFREQ - help - This add the CPUFreq driver support for Intel PXA2xx SOCs. - -- If in doubt, say N. -+ If in doubt, say N. -\ No newline at end of file ---- a/drivers/cpufreq/Makefile -+++ b/drivers/cpufreq/Makefile -@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2 - obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o - obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o - obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o -+obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRAIT) += qcom-cpufreq-krait.o - obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o - obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o - obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o -@@ -85,6 +86,7 @@ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += te - obj-$(CONFIG_ARM_TEGRA194_CPUFREQ) += tegra194-cpufreq.o - obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o - obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o -+obj-$(CONFIG_ARM_KRAIT_CPUFREQ) += krait-cpufreq.o - - - ################################################################################## ---- /dev/null -+++ b/drivers/cpufreq/qcom-cpufreq-krait.c -@@ -0,0 +1,635 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "cpufreq-dt.h" -+ -+static struct device *l2_dev; -+static struct mutex lock; -+ -+struct private_data { -+ struct opp_table *opp_table; -+ struct device *cpu_dev; -+ struct device *l2_dev; -+ const char *reg_name; -+ bool have_static_opps; -+}; -+ -+static int set_target(struct cpufreq_policy *policy, unsigned int index) -+{ -+ struct private_data *priv = policy->driver_data; -+ unsigned long freq = policy->freq_table[index].frequency; -+ unsigned long target_freq = freq * 1000; -+ struct dev_pm_opp *opp; -+ unsigned int level; -+ int cpu, ret; -+ -+ if (l2_dev) { -+ int policy_cpu = policy->cpu; -+ -+ mutex_lock(&lock); -+ -+ /* find the max freq across all core */ -+ for_each_present_cpu(cpu) -+ if (cpu != policy_cpu) -+ target_freq = max( -+ target_freq, -+ (unsigned long)cpufreq_quick_get(cpu)); -+ -+ opp = dev_pm_opp_find_freq_exact(priv->cpu_dev, target_freq, -+ true); -+ if (IS_ERR(opp)) { -+ dev_err(l2_dev, "failed to find OPP for %ld\n", -+ target_freq); -+ ret = PTR_ERR(opp); -+ goto l2_scale_fail; -+ } -+ level = dev_pm_opp_get_level(opp); -+ dev_pm_opp_put(opp); -+ -+ /* -+ * Hardware constraint: -+ * Krait CPU cannot operate at 384MHz with L2 at 1Ghz. -+ * Assume index 0 with the idle freq and level > 0 as -+ * any L2 freq > 384MHz. -+ * Skip CPU freq change in this corner case. -+ */ -+ if (unlikely(index == 0 && level != 0)) { -+ dev_err(priv->cpu_dev, "Krait CPU can't operate at idle freq with L2 at 1GHz"); -+ ret = -EINVAL; -+ goto l2_scale_fail; -+ } -+ -+ opp = dev_pm_opp_find_level_exact(l2_dev, level); -+ if (IS_ERR(opp)) { -+ dev_err(l2_dev, -+ "failed to find level OPP for %d\n", level); -+ ret = PTR_ERR(opp); -+ goto l2_scale_fail; -+ } -+ target_freq = dev_pm_opp_get_freq(opp); -+ dev_pm_opp_put(opp); -+ -+ ret = dev_pm_opp_set_rate(l2_dev, target_freq); -+ if (ret) -+ goto l2_scale_fail; -+ -+ mutex_unlock(&lock); -+ } -+ -+ ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); -+ if (ret) -+ return ret; -+ -+ arch_set_freq_scale(policy->related_cpus, freq, -+ policy->cpuinfo.max_freq); -+ -+ return 0; -+l2_scale_fail: -+ mutex_unlock(&lock); -+ -+ return ret; -+} -+ -+/* -+ * An earlier version of opp-v1 bindings used to name the regulator -+ * "cpu0-supply", we still need to handle that for backwards compatibility. -+ */ -+static const char *find_supply_name(struct device *dev) -+{ -+ struct device_node *np; -+ struct property *pp; -+ int cpu = dev->id; -+ const char *name = NULL; -+ -+ np = of_node_get(dev->of_node); -+ -+ /* This must be valid for sure */ -+ if (WARN_ON(!np)) -+ return NULL; -+ -+ /* Try "cpu0" for older DTs */ -+ if (!cpu) { -+ pp = of_find_property(np, "cpu0-supply", NULL); -+ if (pp) { -+ name = "cpu0"; -+ goto node_put; -+ } -+ } -+ -+ pp = of_find_property(np, "cpu-supply", NULL); -+ if (pp) { -+ name = "cpu"; -+ goto node_put; -+ } -+ -+ dev_dbg(dev, "no regulator for cpu%d\n", cpu); -+node_put: -+ of_node_put(np); -+ return name; -+} -+ -+static int resources_available(void) -+{ -+ struct device *cpu_dev; -+ struct regulator *cpu_reg; -+ struct clk *cpu_clk; -+ int ret = 0; -+ const char *name; -+ -+ cpu_dev = get_cpu_device(0); -+ if (!cpu_dev) { -+ pr_err("failed to get cpu0 device\n"); -+ return -ENODEV; -+ } -+ -+ cpu_clk = clk_get(cpu_dev, NULL); -+ ret = PTR_ERR_OR_ZERO(cpu_clk); -+ if (ret) { -+ /* -+ * If cpu's clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret == -EPROBE_DEFER) -+ dev_dbg(cpu_dev, "clock not ready, retry\n"); -+ else -+ dev_err(cpu_dev, "failed to get clock: %d\n", ret); -+ -+ return ret; -+ } -+ -+ clk_put(cpu_clk); -+ -+ name = find_supply_name(cpu_dev); -+ /* Platform doesn't require regulator */ -+ if (!name) -+ return 0; -+ -+ cpu_reg = regulator_get_optional(cpu_dev, name); -+ ret = PTR_ERR_OR_ZERO(cpu_reg); -+ if (ret) { -+ /* -+ * If cpu's regulator supply node is present, but regulator is -+ * not yet registered, we should try defering probe. -+ */ -+ if (ret == -EPROBE_DEFER) -+ dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n"); -+ else -+ dev_dbg(cpu_dev, "no regulator for cpu0: %d\n", ret); -+ -+ return ret; -+ } -+ -+ regulator_put(cpu_reg); -+ return 0; -+} -+ -+static int cpufreq_init(struct cpufreq_policy *policy) -+{ -+ struct cpufreq_frequency_table *freq_table; -+ struct opp_table *opp_table = NULL; -+ unsigned int transition_latency; -+ struct private_data *priv; -+ struct device *cpu_dev; -+ bool fallback = false; -+ struct clk *cpu_clk; -+ const char *name; -+ int ret; -+ -+ cpu_dev = get_cpu_device(policy->cpu); -+ if (!cpu_dev) { -+ pr_err("failed to get cpu%d device\n", policy->cpu); -+ return -ENODEV; -+ } -+ -+ cpu_clk = clk_get(cpu_dev, NULL); -+ if (IS_ERR(cpu_clk)) { -+ ret = PTR_ERR(cpu_clk); -+ dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret); -+ return ret; -+ } -+ -+ /* Get OPP-sharing information from "operating-points-v2" bindings */ -+ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus); -+ if (ret) { -+ if (ret != -ENOENT) -+ goto out_put_clk; -+ -+ /* -+ * operating-points-v2 not supported, fallback to old method of -+ * finding shared-OPPs for backward compatibility if the -+ * platform hasn't set sharing CPUs. -+ */ -+ if (dev_pm_opp_get_sharing_cpus(cpu_dev, policy->cpus)) -+ fallback = true; -+ } -+ -+ /* -+ * OPP layer will be taking care of regulators now, but it needs to know -+ * the name of the regulator first. -+ */ -+ name = find_supply_name(cpu_dev); -+ if (name) { -+ opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1); -+ if (IS_ERR(opp_table)) { -+ ret = PTR_ERR(opp_table); -+ dev_err(cpu_dev, -+ "Failed to set regulator for cpu%d: %d\n", -+ policy->cpu, ret); -+ goto out_put_clk; -+ } -+ } -+ -+ priv = kzalloc(sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ ret = -ENOMEM; -+ goto out_put_regulator; -+ } -+ -+ priv->reg_name = name; -+ priv->opp_table = opp_table; -+ -+ /* -+ * Initialize OPP tables for all policy->cpus. They will be shared by -+ * all CPUs which have marked their CPUs shared with OPP bindings. -+ * -+ * For platforms not using operating-points-v2 bindings, we do this -+ * before updating policy->cpus. Otherwise, we will end up creating -+ * duplicate OPPs for policy->cpus. -+ * -+ * OPPs might be populated at runtime, don't check for error here -+ */ -+ if (!dev_pm_opp_of_cpumask_add_table(policy->cpus)) -+ priv->have_static_opps = true; -+ -+ /* -+ * But we need OPP table to function so if it is not there let's -+ * give platform code chance to provide it for us. -+ */ -+ ret = dev_pm_opp_get_opp_count(cpu_dev); -+ if (ret < 0) { -+ dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n"); -+ ret = -EPROBE_DEFER; -+ goto out_free_opp; -+ } -+ -+ if (fallback) { -+ cpumask_setall(policy->cpus); -+ -+ /* -+ * OPP tables are initialized only for policy->cpu, do it for -+ * others as well. -+ */ -+ ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); -+ if (ret) -+ dev_err(cpu_dev, -+ "%s: failed to mark OPPs as shared: %d\n", -+ __func__, ret); -+ } -+ -+ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); -+ if (ret) { -+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); -+ goto out_free_opp; -+ } -+ -+ priv->cpu_dev = cpu_dev; -+ -+ policy->driver_data = priv; -+ policy->clk = cpu_clk; -+ policy->freq_table = freq_table; -+ -+ policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000; -+ -+ transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev); -+ if (!transition_latency) -+ transition_latency = CPUFREQ_ETERNAL; -+ -+ policy->cpuinfo.transition_latency = transition_latency; -+ policy->dvfs_possible_from_any_cpu = true; -+ -+ dev_pm_opp_of_register_em(cpu_dev, policy->cpus); -+ -+ return 0; -+ -+out_free_opp: -+ if (priv->have_static_opps) -+ dev_pm_opp_of_cpumask_remove_table(policy->cpus); -+ kfree(priv); -+out_put_regulator: -+ if (name) -+ dev_pm_opp_put_regulators(opp_table); -+out_put_clk: -+ clk_put(cpu_clk); -+ -+ return ret; -+} -+ -+static int cpufreq_online(struct cpufreq_policy *policy) -+{ -+ /* We did light-weight tear down earlier, nothing to do here */ -+ return 0; -+} -+ -+static int cpufreq_offline(struct cpufreq_policy *policy) -+{ -+ /* -+ * Preserve policy->driver_data and don't free resources on light-weight -+ * tear down. -+ */ -+ return 0; -+} -+ -+static int cpufreq_exit(struct cpufreq_policy *policy) -+{ -+ struct private_data *priv = policy->driver_data; -+ -+ dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); -+ if (priv->have_static_opps) -+ dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); -+ if (priv->reg_name) -+ dev_pm_opp_put_regulators(priv->opp_table); -+ -+ clk_put(policy->clk); -+ kfree(priv); -+ -+ return 0; -+} -+ -+static struct freq_attr *krait_cpufreq_attr[] = { -+ &cpufreq_freq_attr_scaling_available_freqs, -+ NULL, -+}; -+ -+static struct cpufreq_driver krait_cpufreq_driver = { -+ .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | -+ CPUFREQ_IS_COOLING_DEV, -+ .verify = cpufreq_generic_frequency_table_verify, -+ .target_index = set_target, -+ .get = cpufreq_generic_get, -+ .init = cpufreq_init, -+ .exit = cpufreq_exit, -+ .online = cpufreq_online, -+ .offline = cpufreq_offline, -+ .name = "krait-cpufreq", -+ .attr = krait_cpufreq_attr, -+ .suspend = cpufreq_generic_suspend, -+}; -+ -+struct krait_data { -+ unsigned long idle_freq; -+ bool regulator_enabled; -+}; -+ -+static int krait_cache_set_opp(struct dev_pm_set_opp_data *data) -+{ -+ unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate; -+ struct dev_pm_opp_supply *supply = &data->new_opp.supplies[0]; -+ struct regulator *reg = data->regulators[0]; -+ struct clk *clk = data->clk; -+ struct krait_data *kdata; -+ unsigned long idle_freq; -+ int ret; -+ -+ kdata = (struct krait_data *)dev_get_drvdata(data->dev); -+ idle_freq = kdata->idle_freq; -+ -+ /* Scaling up? Scale voltage before frequency */ -+ if (freq >= old_freq) { -+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, -+ supply->u_volt, -+ supply->u_volt_max); -+ if (ret) -+ goto exit; -+ } -+ -+ /* -+ * Set to idle bin if switching from normal to high bin -+ * or vice versa. It has been notice that a bug is triggered -+ * in cache scaling when more than one bin is scaled, to fix -+ * this we first need to transition to the base rate and then -+ * to target rate -+ */ -+ if (likely(freq != idle_freq && old_freq != idle_freq)) { -+ ret = clk_set_rate(clk, idle_freq); -+ if (ret) -+ goto exit; -+ } -+ -+ ret = clk_set_rate(clk, freq); -+ if (ret) -+ goto exit; -+ -+ /* Scaling down? Scale voltage after frequency */ -+ if (freq < old_freq) { -+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, -+ supply->u_volt, -+ supply->u_volt_max); -+ } -+ -+ if (unlikely(!kdata->regulator_enabled)) { -+ ret = regulator_enable(reg); -+ if (ret < 0) -+ dev_warn(data->dev, "Failed to enable regulator: %d", ret); -+ else -+ kdata->regulator_enabled = true; -+ } -+ -+exit: -+ return ret; -+}; -+ -+static int krait_cache_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct krait_data *data; -+ struct opp_table *table; -+ struct dev_pm_opp *opp; -+ struct device *cpu_dev; -+ int ret; -+ -+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ table = dev_pm_opp_set_regulators(dev, (const char *[]){ "l2" }, 1); -+ if (IS_ERR(table)) { -+ ret = PTR_ERR(table); -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, "failed to set regulators %d\n", ret); -+ -+ return ret; -+ } -+ -+ ret = PTR_ERR_OR_ZERO( -+ dev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp)); -+ if (ret) -+ return ret; -+ -+ ret = dev_pm_opp_of_add_table(dev); -+ if (ret) { -+ dev_err(dev, "failed to parse L2 freq thresholds\n"); -+ return ret; -+ } -+ -+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq); -+ dev_pm_opp_put(opp); -+ -+ /* -+ * Check if we have at least opp-level 1, 0 should always be set to -+ * the idle freq -+ */ -+ opp = dev_pm_opp_find_level_exact(dev, 1); -+ if (IS_ERR(opp)) { -+ ret = PTR_ERR(opp); -+ dev_err(dev, -+ "Invalid configuration found of l2 opp. Can't find opp-level 1"); -+ goto invalid_conf; -+ } -+ dev_pm_opp_put(opp); -+ -+ /* -+ * Check opp-level configuration -+ * At least 2 level must be set or the cache will always be scaled -+ * the idle freq causing some performance problem -+ * -+ * In case of invalid configuration, the l2 scaling is skipped -+ */ -+ cpu_dev = get_cpu_device(0); -+ if (!cpu_dev) { -+ pr_err("failed to get cpu0 device\n"); -+ return -ENODEV; -+ } -+ -+ /* With opp error assume cpufreq still has to be registred. Defer probe. */ -+ ret = dev_pm_opp_get_opp_count(cpu_dev); -+ if (ret < 0) { -+ ret = -EPROBE_DEFER; -+ goto invalid_conf; -+ } -+ -+ /* -+ * Check if we have at least opp-level 1 in the cpu opp, 0 should always -+ * be set to the idle freq -+ */ -+ opp = dev_pm_opp_find_level_exact(cpu_dev, 1); -+ if (IS_ERR(opp)) { -+ ret = PTR_ERR(opp); -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, -+ "Invalid configuration found of cpu opp. Can't find opp-level 1"); -+ goto invalid_conf; -+ } -+ dev_pm_opp_put(opp); -+ -+ platform_set_drvdata(pdev, data); -+ -+ mutex_init(&lock); -+ -+ /* The l2 scaling is enabled by linking the cpufreq driver */ -+ l2_dev = dev; -+ -+ return 0; -+ -+invalid_conf: -+ dev_pm_opp_remove_table(dev); -+ dev_pm_opp_put_regulators(table); -+ dev_pm_opp_unregister_set_opp_helper(table); -+ -+ return ret; -+}; -+ -+static int krait_cache_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct opp_table *table = dev_pm_opp_get_opp_table(dev); -+ -+ dev_pm_opp_remove_table(dev); -+ dev_pm_opp_put_regulators(table); -+ dev_pm_opp_unregister_set_opp_helper(table); -+ -+ return 0; -+}; -+ -+static const struct of_device_id krait_cache_match_table[] = { -+ { .compatible = "qcom,krait-cache" }, -+ {} -+}; -+ -+static struct platform_driver krait_cache_driver = { -+ .driver = { -+ .name = "krait-cache", -+ .of_match_table = krait_cache_match_table, -+ }, -+ .probe = krait_cache_probe, -+ .remove = krait_cache_remove, -+}; -+module_platform_driver(krait_cache_driver); -+ -+static int krait_cpufreq_probe(struct platform_device *pdev) -+{ -+ struct cpufreq_dt_platform_data *data = dev_get_platdata(&pdev->dev); -+ int ret; -+ -+ /* -+ * All per-cluster (CPUs sharing clock/voltages) initialization is done -+ * from ->init(). In probe(), we just need to make sure that clk and -+ * regulators are available. Else defer probe and retry. -+ * -+ * FIXME: Is checking this only for CPU0 sufficient ? -+ */ -+ ret = resources_available(); -+ if (ret) -+ return ret; -+ -+ if (data) { -+ if (data->have_governor_per_policy) -+ krait_cpufreq_driver.flags |= -+ CPUFREQ_HAVE_GOVERNOR_PER_POLICY; -+ -+ krait_cpufreq_driver.resume = data->resume; -+ if (data->suspend) -+ krait_cpufreq_driver.suspend = data->suspend; -+ } -+ -+ ret = cpufreq_register_driver(&krait_cpufreq_driver); -+ if (ret) -+ dev_err(&pdev->dev, "failed register driver: %d\n", ret); -+ -+ return ret; -+} -+ -+static int krait_cpufreq_remove(struct platform_device *pdev) -+{ -+ cpufreq_unregister_driver(&krait_cpufreq_driver); -+ return 0; -+} -+ -+static struct platform_driver krait_cpufreq_platdrv = { -+ .driver = { -+ .name = "krait-cpufreq", -+ }, -+ .probe = krait_cpufreq_probe, -+ .remove = krait_cpufreq_remove, -+}; -+ -+module_platform_driver(krait_cpufreq_platdrv); -+ -+MODULE_ALIAS("platform:krait-cpufreq"); -+MODULE_AUTHOR("Ansuel Smith "); -+MODULE_DESCRIPTION("Dedicated Krait SoC cpufreq driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ipq806x/patches-5.15/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch b/target/linux/ipq806x/patches-5.15/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch deleted file mode 100644 index 316e18b790..0000000000 --- a/target/linux/ipq806x/patches-5.15/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch +++ /dev/null @@ -1,237 +0,0 @@ -From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 22 Feb 2020 18:02:17 +0100 -Subject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings - -Document dedicated cpufreq for Krait CPUs. - -Signed-off-by: Ansuel Smith ---- - .../bindings/cpufreq/qcom-cpufreq-krait.yaml | 221 ++++++++++++++++++ - 1 file changed, 221 insertions(+) - create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml -@@ -0,0 +1,221 @@ -+# SPDX-License-Identifier: GPL-2.0 -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: CPU Frequency scaling driver for Krait SoCs -+ -+maintainers: -+ - Ansuel Smith -+ -+description: | -+ The krait cpufreq driver is a dedicated frequency scaling driver -+ based on cpufreq-dt generic driver that scale L2 cache and the -+ cores. TEST -+ -+ The L2 cache is scaled based on the max clk across all cores and -+ the clock is decided based on the opp-level set in the device tree. -+ -+ Different core freq can be linked to a specific l2 freq and the driver -+ on frequency change will scale the core and the l2 clk based of the -+ linked freq. -+ -+ On Krait SoC is present a bug and on every L2 clk change the driver -+ needs to set the clk to the idle freq before changing it to the new value. -+ -+ This requires the qcom cpufreq nvmem driver to parse the different opp -+ core clk and an additional opp table for the l2 scaling. -+ -+ If the driver detect broken config (for example missing opp-level) the -+ cpufreq driver skips the l2 scaling -+ -+ Referring to this example opp-level can be used to link a range of cpu freq -+ to a specific l2 freq: -+ cpu opp freq 384000000 has opp-level 0 -+ l2 opp freq 384000000 has opp-level 0 -+ The driver will scale l2 to 384000000 -+ -+ cpu opp freq 600000000-1000000000 has opp-level 1 -+ l2 opp freq 1000000000 has opp-level 1 -+ The driver will scale l2 to 1000000000 -+ -+allOf: -+ - $ref: /schemas/cache-controller.yaml# -+ -+select: -+ properties: -+ compatible: -+ items: -+ - enum: -+ - qcom,krait-cache -+ -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ items: -+ - const: qcom,krait-cache -+ - const: cache -+ -+ cache-level: -+ const: 2 -+ -+ clocks: -+ maxItems: 1 -+ -+ clock-names: -+ const: l2 -+ -+ l2-supply: true -+ -+ operating-points-v2: true -+ -+required: -+ - compatible -+ - cache-level -+ - clocks -+ - clock-names -+ - l2-supply -+ - operating-points-v2 -+ -+additionalProperties: false -+ -+examples: -+ - | -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ compatible = "qcom,krait"; -+ enable-method = "qcom,kpss-acc-v1"; -+ device_type = "cpu"; -+ reg = <0>; -+ next-level-cache = <&L2>; -+ qcom,acc = <&acc0>; -+ qcom,saw = <&saw0>; -+ clocks = <&kraitcc 0>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2a>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; -+ }; -+ -+ /* ... */ -+ -+ }; -+ -+ opp_table0: opp_table0 { -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&speedbin_efuse>; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1000000>; -+ opp-microvolt-speed0-pvs1-v0 = <925000>; -+ opp-microvolt-speed0-pvs2-v0 = <875000>; -+ opp-microvolt-speed0-pvs3-v0 = <800000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <975000>; -+ opp-microvolt-speed0-pvs2-v0 = <925000>; -+ opp-microvolt-speed0-pvs3-v0 = <850000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1100000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000>; -+ opp-microvolt-speed0-pvs2-v0 = <995000>; -+ opp-microvolt-speed0-pvs3-v0 = <900000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1150000>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000>; -+ opp-microvolt-speed0-pvs3-v0 = <950000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1200000>; -+ opp-microvolt-speed0-pvs1-v0 = <1125000>; -+ opp-microvolt-speed0-pvs2-v0 = <1075000>; -+ opp-microvolt-speed0-pvs3-v0 = <1000000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1250000>; -+ opp-microvolt-speed0-pvs1-v0 = <1175000>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000>; -+ opp-microvolt-speed0-pvs3-v0 = <1050000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ opp_table_l2: opp_table_l2 { -+ compatible = "operating-points-v2"; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ soc { -+ L2: l2-cache { -+ compatible = "qcom,krait-cache", "cache"; -+ cache-level = <2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ l2-supply = <&smb208_s1a>; -+ operating-points-v2 = <&opp_table_l2>; -+ }; -+ }; -+ -+... diff --git a/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch b/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch new file mode 100644 index 0000000000..85feb89148 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch @@ -0,0 +1,242 @@ +From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 5 Aug 2020 14:19:23 +0200 +Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver + +Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually +scale the Cache frequency when the CPU frequency is changed. This +devfreq driver register with the cpu notifier and scale the Cache +based on the max Freq across all core as the CPU cache is shared across +all of them. If provided this also scale the voltage of the regulator +attached to the CPU cache. The scaling logic is based on the CPU freq +and the 3 scaling interval are set by the device dts. + +Signed-off-by: Christian Marangi +--- + drivers/devfreq/Kconfig | 11 ++ + drivers/devfreq/Makefile | 1 + + drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++ + 3 files changed, 200 insertions(+) + create mode 100644 drivers/devfreq/krait-cache-devfreq.c + +--- a/drivers/devfreq/Kconfig ++++ b/drivers/devfreq/Kconfig +@@ -132,6 +132,17 @@ config ARM_RK3399_DMC_DEVFREQ + It sets the frequency for the memory controller and reads the usage counts + from hardware. + ++config ARM_KRAIT_CACHE_DEVFREQ ++ tristate "Scaling support for Krait CPU Cache Devfreq" ++ depends on ARCH_QCOM || COMPILE_TEST ++ select DEVFREQ_GOV_PASSIVE ++ help ++ This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores. ++ ++ The driver register with the cpufreq notifier and find the right frequency ++ based on the max frequency across all core and the range set in the device ++ dts. If provided this scale also the regulator attached to the l2 cache. ++ + source "drivers/devfreq/event/Kconfig" + + endif # PM_DEVFREQ +--- a/drivers/devfreq/Makefile ++++ b/drivers/devfreq/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx + obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o + obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o + obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o ++obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o + + # DEVFREQ Event Drivers + obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ +--- /dev/null ++++ b/drivers/devfreq/krait-cache-devfreq.c +@@ -0,0 +1,188 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "governor.h" ++ ++struct krait_cache_data { ++ struct clk *clk; ++ unsigned long idle_freq; ++}; ++ ++static int krait_cache_set_opp(struct dev_pm_set_opp_data *data) ++{ ++ unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate; ++ struct dev_pm_opp_supply *supply = &data->new_opp.supplies[0]; ++ struct regulator *reg = data->regulators[0]; ++ struct krait_cache_data *kdata; ++ struct clk *clk = data->clk; ++ unsigned long idle_freq; ++ int ret; ++ ++ kdata = dev_get_drvdata(data->dev); ++ idle_freq = kdata->idle_freq; ++ ++ if (reg) { ++ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, ++ supply->u_volt, ++ supply->u_volt_max); ++ if (ret) ++ goto exit; ++ } ++ ++ /* ++ * Set to idle bin if switching from normal to high bin ++ * or vice versa. It has been notice that a bug is triggered ++ * in cache scaling when more than one bin is scaled, to fix ++ * this we first need to transition to the base rate and then ++ * to target rate ++ */ ++ if (likely(freq != idle_freq && old_freq != idle_freq)) { ++ ret = clk_set_rate(clk, idle_freq); ++ if (ret) ++ goto exit; ++ } ++ ++ ret = clk_set_rate(clk, freq); ++ if (ret) ++ goto exit; ++ ++exit: ++ return ret; ++}; ++ ++static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq) ++{ ++ struct krait_cache_data *data = dev_get_drvdata(dev); ++ ++ *freq = clk_get_rate(data->clk); ++ ++ return 0; ++}; ++ ++static int krait_cache_target(struct device *dev, unsigned long *freq, ++ u32 flags) ++{ ++ struct dev_pm_opp *opp; ++ ++ opp = dev_pm_opp_find_freq_ceil(dev, freq); ++ if (unlikely(IS_ERR(opp))) ++ return PTR_ERR(opp); ++ ++ dev_pm_opp_put(opp); ++ ++ return dev_pm_opp_set_rate(dev, *freq); ++}; ++ ++static int krait_cache_get_dev_status(struct device *dev, ++ struct devfreq_dev_status *stat) ++{ ++ struct krait_cache_data *data = dev_get_drvdata(dev); ++ ++ stat->busy_time = 0; ++ stat->total_time = 0; ++ stat->current_frequency = clk_get_rate(data->clk); ++ ++ return 0; ++}; ++ ++static struct devfreq_dev_profile krait_cache_devfreq_profile = { ++ .target = krait_cache_target, ++ .get_dev_status = krait_cache_get_dev_status, ++ .get_cur_freq = krait_cache_get_cur_freq ++}; ++ ++static struct devfreq_passive_data devfreq_gov_data = { ++ .parent_type = CPUFREQ_PARENT_DEV, ++}; ++ ++static int krait_cache_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct krait_cache_data *data; ++ struct opp_table *table; ++ struct devfreq *devfreq; ++ struct dev_pm_opp *opp; ++ struct clk *clk; ++ int ret; ++ ++ krait_cache_devfreq_profile.freq_table = NULL; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ clk = devm_clk_get(dev, "l2"); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ table = dev_pm_opp_set_regulators(dev, (const char *[]){ "l2" }, 1); ++ if (IS_ERR(table)) { ++ ret = PTR_ERR(table); ++ dev_err_probe(dev, -EPROBE_DEFER, "failed to set regulators %d\n", ret); ++ return ret; ++ } ++ ++ ret = PTR_ERR_OR_ZERO( ++ dev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp)); ++ if (ret) ++ return ret; ++ ++ ret = dev_pm_opp_of_add_table(dev); ++ if (ret) { ++ dev_err(dev, "failed to parse L2 freq thresholds\n"); ++ return ret; ++ } ++ ++ data->clk = clk; ++ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq); ++ dev_pm_opp_put(opp); ++ ++ dev_set_drvdata(dev, data); ++ ++ devfreq = devm_devfreq_add_device(&pdev->dev, &krait_cache_devfreq_profile, ++ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); ++ if (IS_ERR(devfreq)) { ++ dev_pm_opp_remove_table(dev); ++ dev_pm_opp_put_regulators(table); ++ dev_pm_opp_unregister_set_opp_helper(table); ++ } ++ ++ return PTR_ERR_OR_ZERO(devfreq); ++}; ++ ++static int krait_cache_remove(struct platform_device *pdev) ++{ ++ dev_pm_opp_remove_table(&pdev->dev); ++ ++ return 0; ++}; ++ ++static const struct of_device_id krait_cache_match_table[] = { ++ { .compatible = "qcom,krait-cache" }, ++ {} ++}; ++ ++static struct platform_driver krait_cache_driver = { ++ .probe = krait_cache_probe, ++ .remove = krait_cache_remove, ++ .driver = { ++ .name = "krait-cache-scaling", ++ .of_match_table = krait_cache_match_table, ++ }, ++}; ++module_platform_driver(krait_cache_driver); ++ ++MODULE_DESCRIPTION("Krait CPU Cache Scaling driver"); ++MODULE_AUTHOR("Christian 'Ansuel' Marangi "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch b/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch new file mode 100644 index 0000000000..f42729fd50 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch @@ -0,0 +1,50 @@ +From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 18:39:21 +0200 +Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi + +Add qcom,krait-cache compatible to enable cache devfreq driver for +ipq806x SoC and move the L2 node to the soc node to make the devfreq +driver correctly probe. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -69,16 +69,6 @@ + min-residency-us = <3000>; + }; + }; +- +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; +- qcom,saw = <&saw_l2>; +- +- clocks = <&kraitcc 4>; +- clock-names = "l2"; +- operating-points-v2 = <&opp_table_l2>; +- }; + }; + + opp_table_l2: opp_table_l2 { +@@ -470,6 +460,16 @@ + ranges; + compatible = "simple-bus"; + ++ L2: l2-cache { ++ compatible = "cache", "qcom,krait-cache"; ++ cache-level = <2>; ++ qcom,saw = <&saw_l2>; ++ ++ clocks = <&kraitcc 4>; ++ clock-names = "l2"; ++ operating-points-v2 = <&opp_table_l2>; ++ }; ++ + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; From a8d7aed033cfe03fadf3c18459cf8b9302e7eefb Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:18:49 +0200 Subject: [PATCH 30/43] ipq806x: 5.15: replace fab scaling patch with devfreq driver Replace fab scaling patch with devfreq driver. Signed-off-by: Christian Marangi --- ...add-fab-scaling-support-with-cpufreq.patch | 243 ------------------ ...eq-add-ipq806x-fabric-scaling-driver.patch | 203 +++++++++++++++ ...com-add-fab-scaling-node-for-ipq806x.patch | 48 ++++ 3 files changed, 251 insertions(+), 243 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/098-3-add-fab-scaling-support-with-cpufreq.patch create mode 100644 target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch create mode 100644 target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch diff --git a/target/linux/ipq806x/patches-5.15/098-3-add-fab-scaling-support-with-cpufreq.patch b/target/linux/ipq806x/patches-5.15/098-3-add-fab-scaling-support-with-cpufreq.patch deleted file mode 100644 index 805979df8c..0000000000 --- a/target/linux/ipq806x/patches-5.15/098-3-add-fab-scaling-support-with-cpufreq.patch +++ /dev/null @@ -1,243 +0,0 @@ ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-k - clk-qcom-y += clk-hfpll.o - clk-qcom-y += reset.o - clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o -+clk-qcom-y += fab_scaling.o - - # Keep alphabetically sorted by config - obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o ---- /dev/null -+++ b/drivers/clk/qcom/fab_scaling.c -@@ -0,0 +1,172 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct qcom_fab_scaling_data { -+ u32 fab_freq_high; -+ u32 fab_freq_nominal; -+ u32 cpu_freq_threshold; -+ struct clk *apps_fab_clk; -+ struct clk *ddr_fab_clk; -+}; -+ -+static struct qcom_fab_scaling_data *drv_data; -+ -+int scale_fabrics(unsigned long max_cpu_freq) -+{ -+ struct clk *apps_fab_clk = drv_data->apps_fab_clk, -+ *ddr_fab_clk = drv_data->ddr_fab_clk; -+ unsigned long target_freq, cur_freq; -+ int ret; -+ -+ /* Skip fab scaling if the driver is not ready */ -+ if (!apps_fab_clk || !ddr_fab_clk) -+ return 0; -+ -+ if (max_cpu_freq > drv_data->cpu_freq_threshold) -+ target_freq = drv_data->fab_freq_high; -+ else -+ target_freq = drv_data->fab_freq_nominal; -+ -+ cur_freq = clk_get_rate(ddr_fab_clk); -+ -+ if (target_freq != cur_freq) { -+ ret = clk_set_rate(apps_fab_clk, target_freq); -+ if (ret) -+ return ret; -+ ret = clk_set_rate(ddr_fab_clk, target_freq); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(scale_fabrics); -+ -+static int ipq806x_fab_scaling_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct clk *apps_fab_clk, *ddr_fab_clk; -+ int ret; -+ -+ if (!np) -+ return -ENODEV; -+ -+ drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL); -+ if (!drv_data) -+ return -ENOMEM; -+ -+ if (of_property_read_u32(np, "fab_freq_high", &drv_data->fab_freq_high)) { -+ pr_err("FABRICS turbo freq not found. Using defaults...\n"); -+ drv_data->fab_freq_high = 533000000; -+ } -+ -+ if (of_property_read_u32(np, "fab_freq_nominal", &drv_data->fab_freq_nominal)) { -+ pr_err("FABRICS nominal freq not found. Using defaults...\n"); -+ drv_data->fab_freq_nominal = 400000000; -+ } -+ -+ if (of_property_read_u32(np, "cpu_freq_threshold", &drv_data->cpu_freq_threshold)) { -+ pr_err("FABRICS cpu freq threshold not found. Using defaults...\n"); -+ drv_data->cpu_freq_threshold = 1000000000; -+ } -+ -+ apps_fab_clk = devm_clk_get(&pdev->dev, "apps-fab-clk"); -+ ret = PTR_ERR_OR_ZERO(apps_fab_clk); -+ if (ret) { -+ /* -+ * If apps fab clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret != -EPROBE_DEFER) { -+ pr_err("Failed to get APPS FABRIC clock: %d\n", ret); -+ ret = -ENODEV; -+ } -+ goto err; -+ } -+ -+ clk_prepare_enable(apps_fab_clk); -+ clk_set_rate(apps_fab_clk, drv_data->fab_freq_high); -+ drv_data->apps_fab_clk = apps_fab_clk; -+ -+ ddr_fab_clk = devm_clk_get(&pdev->dev, "ddr-fab-clk"); -+ ret = PTR_ERR_OR_ZERO(ddr_fab_clk); -+ if (ret) { -+ /* -+ * If ddr fab clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret != -EPROBE_DEFER) { -+ pr_err("Failed to get DDR FABRIC clock: %d\n", ret); -+ ddr_fab_clk = NULL; -+ ret = -ENODEV; -+ } -+ goto err; -+ } -+ -+ clk_prepare_enable(ddr_fab_clk); -+ clk_set_rate(ddr_fab_clk, drv_data->fab_freq_high); -+ drv_data->ddr_fab_clk = ddr_fab_clk; -+ -+ return 0; -+err: -+ kfree(drv_data); -+ return ret; -+} -+ -+static int ipq806x_fab_scaling_remove(struct platform_device *pdev) -+{ -+ kfree(drv_data); -+ return 0; -+} -+ -+static const struct of_device_id fab_scaling_ipq806x_match_table[] = { -+ { .compatible = "qcom,fab-scaling" }, -+ { } -+}; -+ -+static struct platform_driver fab_scaling_ipq806x_driver = { -+ .probe = ipq806x_fab_scaling_probe, -+ .remove = ipq806x_fab_scaling_remove, -+ .driver = { -+ .name = "fab-scaling", -+ .of_match_table = fab_scaling_ipq806x_match_table, -+ }, -+}; -+ -+static int __init fab_scaling_ipq806x_init(void) -+{ -+ return platform_driver_register(&fab_scaling_ipq806x_driver); -+} -+late_initcall(fab_scaling_ipq806x_init); -+ -+static void __exit fab_scaling_ipq806x_exit(void) -+{ -+ platform_driver_unregister(&fab_scaling_ipq806x_driver); -+} -+module_exit(fab_scaling_ipq806x_exit); ---- /dev/null -+++ b/include/linux/fab_scaling.h -@@ -0,0 +1,31 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+ -+#ifndef __FAB_SCALING_H -+#define __FAB_SCALING_H -+ -+/** -+ * scale_fabrics - Scale DDR and APPS FABRICS -+ * -+ * This function monitors all the registered clocks and does APPS -+ * and DDR FABRIC scaling based on the idle frequencies with which -+ * it was registered. -+ * -+ */ -+int scale_fabrics(unsigned long max_cpu_freq); -+ -+#endif ---- a/drivers/cpufreq/qcom-cpufreq-krait.c -+++ b/drivers/cpufreq/qcom-cpufreq-krait.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - - #include "cpufreq-dt.h" - -@@ -74,6 +75,13 @@ static int set_target(struct cpufreq_pol - goto l2_scale_fail; - } - -+ /* -+ * Scale fabrics with max freq across all cores -+ */ -+ ret = scale_fabrics(target_freq); -+ if (ret) -+ goto l2_scale_fail; -+ - opp = dev_pm_opp_find_level_exact(l2_dev, level); - if (IS_ERR(opp)) { - dev_err(l2_dev, diff --git a/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch b/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch new file mode 100644 index 0000000000..340c58a0c1 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch @@ -0,0 +1,203 @@ +From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 19:56:08 +0200 +Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver + +Add ipq806x fabric scaling driver using the devfreq passive governor. + +Signed-off-by: Christian Marangi +--- + drivers/devfreq/Kconfig | 11 ++ + drivers/devfreq/Makefile | 1 + + drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++ + 3 files changed, 167 insertions(+) + create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c + +--- a/drivers/devfreq/Kconfig ++++ b/drivers/devfreq/Kconfig +@@ -143,6 +143,17 @@ config ARM_KRAIT_CACHE_DEVFREQ + based on the max frequency across all core and the range set in the device + dts. If provided this scale also the regulator attached to the l2 cache. + ++config ARM_IPQ806X_FAB_DEVFREQ ++ tristate "Scaling support for ipq806x Soc Fabric" ++ depends on ARCH_QCOM || COMPILE_TEST ++ select DEVFREQ_GOV_PASSIVE ++ help ++ This adds the DEVFREQ driver for the ipq806x Soc Fabric. ++ ++ The driver register with the cpufreq notifier and find the right frequency ++ based on the max frequency across all core and the range set in the device ++ dts. ++ + source "drivers/devfreq/event/Kconfig" + + endif # PM_DEVFREQ +--- a/drivers/devfreq/Makefile ++++ b/drivers/devfreq/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += + obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o + obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o + obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o ++obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o + + # DEVFREQ Event Drivers + obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ +--- /dev/null ++++ b/drivers/devfreq/ipq806x-fab-devfreq.c +@@ -0,0 +1,155 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "governor.h" ++ ++struct ipq806x_fab_data { ++ struct clk *fab_clk; ++ struct clk *ddr_clk; ++}; ++ ++static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(dev); ++ ++ *freq = clk_get_rate(data->fab_clk); ++ ++ return 0; ++}; ++ ++static int ipq806x_fab_target(struct device *dev, unsigned long *freq, ++ u32 flags) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(dev); ++ struct dev_pm_opp *opp; ++ int ret; ++ ++ opp = dev_pm_opp_find_freq_ceil(dev, freq); ++ if (unlikely(IS_ERR(opp))) ++ return PTR_ERR(opp); ++ ++ dev_pm_opp_put(opp); ++ ++ ret = clk_set_rate(data->fab_clk, *freq); ++ if (ret) ++ return ret; ++ ++ return clk_set_rate(data->ddr_clk, *freq); ++}; ++ ++static int ipq806x_fab_get_dev_status(struct device *dev, ++ struct devfreq_dev_status *stat) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(dev); ++ ++ stat->busy_time = 0; ++ stat->total_time = 0; ++ stat->current_frequency = clk_get_rate(data->fab_clk); ++ ++ return 0; ++}; ++ ++static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = { ++ .target = ipq806x_fab_target, ++ .get_dev_status = ipq806x_fab_get_dev_status, ++ .get_cur_freq = ipq806x_fab_get_cur_freq ++}; ++ ++static struct devfreq_passive_data devfreq_gov_data = { ++ .parent_type = CPUFREQ_PARENT_DEV, ++}; ++ ++static int ipq806x_fab_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ipq806x_fab_data *data; ++ struct devfreq *devfreq; ++ struct clk *clk; ++ int ret; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ clk = devm_clk_get(dev, "apps-fab-clk"); ++ if (IS_ERR(clk)) { ++ dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n"); ++ return PTR_ERR(clk); ++ } ++ ++ clk_prepare_enable(clk); ++ data->fab_clk = clk; ++ ++ clk = devm_clk_get(dev, "ddr-fab-clk"); ++ if (IS_ERR(clk)) { ++ dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n"); ++ goto err_ddr; ++ } ++ ++ clk_prepare_enable(clk); ++ data->ddr_clk = clk; ++ ++ ret = dev_pm_opp_of_add_table(dev); ++ if (ret) { ++ dev_err(dev, "failed to parse fab freq thresholds\n"); ++ return ret; ++ } ++ ++ dev_set_drvdata(dev, data); ++ ++ devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile, ++ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data); ++ if (IS_ERR(devfreq)) ++ dev_pm_opp_remove_table(dev); ++ ++ return PTR_ERR_OR_ZERO(devfreq); ++ ++err_ddr: ++ clk_unprepare(data->fab_clk); ++ clk_put(data->fab_clk); ++ return PTR_ERR(clk); ++}; ++ ++static int ipq806x_fab_remove(struct platform_device *pdev) ++{ ++ struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev); ++ ++ clk_unprepare(data->fab_clk); ++ clk_put(data->fab_clk); ++ ++ clk_unprepare(data->ddr_clk); ++ clk_put(data->ddr_clk); ++ ++ dev_pm_opp_remove_table(&pdev->dev); ++ ++ return 0; ++}; ++ ++static const struct of_device_id ipq806x_fab_match_table[] = { ++ { .compatible = "qcom,fab-scaling" }, ++ {} ++}; ++ ++static struct platform_driver ipq806x_fab_driver = { ++ .probe = ipq806x_fab_probe, ++ .remove = ipq806x_fab_remove, ++ .driver = { ++ .name = "ipq806x-fab-scaling", ++ .of_match_table = ipq806x_fab_match_table, ++ }, ++}; ++module_platform_driver(ipq806x_fab_driver); ++ ++MODULE_DESCRIPTION("ipq806x Fab Scaling driver"); ++MODULE_AUTHOR("Christian Marangi "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch b/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch new file mode 100644 index 0000000000..f4de1dbb52 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch @@ -0,0 +1,48 @@ +From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 20:03:05 +0200 +Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x + +Add fabric scaling node for ipq806x to correctly scale apps and ddr +fabric clk. + +Signed-off-by: Christian Marangi +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -170,6 +170,18 @@ + }; + }; + ++ opp_table_fab: opp_table_fab { ++ compatible = "operating-points-v2"; ++ ++ opp-533000000 { ++ opp-hz = /bits/ 64 <533000000>; ++ }; ++ ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ }; ++ }; ++ + thermal-zones { + tsens_tz_sensor0 { + polling-delay-passive = <0>; +@@ -470,6 +482,13 @@ + operating-points-v2 = <&opp_table_l2>; + }; + ++ fab-scaling { ++ compatible = "qcom,fab-scaling"; ++ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; ++ clock-names = "apps-fab-clk", "ddr-fab-clk"; ++ operating-points-v2 = <&opp_table_fab>; ++ }; ++ + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; From ae6a63bc97cf30287ac6076534ac7efa089cbc82 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:19:44 +0200 Subject: [PATCH 31/43] ipq806x: 5.15: replace nandc patch with upstream version Replace nandc fix patch with upstream version. Signed-off-by: Christian Marangi --- ...m_nandc-add-boot_layout_mode-support.patch | 240 ----------- ...vicetree-mtd-qcom_nandc-document-qco.patch | 41 -- ...m_nandc-reorder-qcom_nand_host-struc.patch | 268 ++++++++++++ ...m_nandc-add-support-for-unprotected-.patch | 406 ++++++++++++++++++ 4 files changed, 674 insertions(+), 281 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch delete mode 100644 target/linux/ipq806x/patches-5.15/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch create mode 100644 target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch create mode 100644 target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch diff --git a/target/linux/ipq806x/patches-5.15/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch b/target/linux/ipq806x/patches-5.15/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch deleted file mode 100644 index 08c067255e..0000000000 --- a/target/linux/ipq806x/patches-5.15/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch +++ /dev/null @@ -1,240 +0,0 @@ -From 6949d651e3be3ebbfedb6bbd5b541cfda6ee58a9 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 10 Feb 2021 10:40:17 +0100 -Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: add boot_layout_mode support - -ipq806x nand have a special ecc configuration for the boot pages. The -use of the non-boot pages configuration on boot pages cause I/O error -and can cause broken data written to the nand. Add support for this -special configuration if the page to be read/write is in the size of the -boot pages set by the dts. - -Signed-off-by: Ansuel Smith ---- - drivers/mtd/nand/raw/qcom_nandc.c | 82 +++++++++++++++++++++++++++++-- - 1 file changed, 77 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -163,6 +163,11 @@ - /* NAND_CTRL bits */ - #define BAM_MODE_EN BIT(0) - -+ -+#define UD_SIZE_BYTES_MASK (0x3ff << UD_SIZE_BYTES) -+#define SPARE_SIZE_BYTES_MASK (0xf << SPARE_SIZE_BYTES) -+#define ECC_NUM_DATA_BYTES_MASK (0x3ff << ECC_NUM_DATA_BYTES) -+ - /* - * the NAND controller performs reads/writes with ECC in 516 byte chunks. - * the driver calls the chunks 'step' or 'codeword' interchangeably -@@ -443,6 +448,13 @@ struct qcom_nand_controller { - * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for - * ecc/non-ecc mode for the current nand flash - * device -+ * -+ * @boot_pages_conf: keep track of the current ecc configuration used by -+ * the driver for read/write operation. (boot pages -+ * have different configuration than normal page) -+ * @boot_pages: number of pages starting from 0 used as boot pages -+ * where the driver will use the boot pages ecc -+ * configuration for read/write operation - */ - struct qcom_nand_host { - struct nand_chip chip; -@@ -465,6 +477,9 @@ struct qcom_nand_host { - u32 ecc_bch_cfg; - u32 clrflashstatus; - u32 clrreadstatus; -+ -+ bool boot_pages_conf; -+ u32 boot_pages; - }; - - /* -@@ -474,6 +489,7 @@ struct qcom_nand_host { - * @is_bam - whether NAND controller is using BAM - * @is_qpic - whether NAND CTRL is part of qpic IP - * @qpic_v2 - flag to indicate QPIC IP version 2 -+ * @has_boot_pages - whether NAND has different ecc settings for boot pages - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - */ - struct qcom_nandc_props { -@@ -481,6 +497,7 @@ struct qcom_nandc_props { - bool is_bam; - bool is_qpic; - bool qpic_v2; -+ bool has_boot_pages; - u32 dev_cmd_reg_start; - }; - -@@ -1691,7 +1708,7 @@ qcom_nandc_read_cw_raw(struct mtd_info * - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (qcom_nandc_is_last_cw(ecc, cw)) { -+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->boot_pages_conf) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) * 4); - oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + -@@ -1772,7 +1789,7 @@ check_for_erased_page(struct qcom_nand_h - } - - for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { -- if (qcom_nandc_is_last_cw(ecc, cw)) { -+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->boot_pages_conf) { - data_size = ecc->size - ((ecc->steps - 1) * 4); - oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; - } else { -@@ -1930,7 +1947,7 @@ static int read_page_ecc(struct qcom_nan - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -2027,6 +2044,30 @@ static int copy_last_cw(struct qcom_nand - return ret; - } - -+static void -+check_boot_pages_conf(struct qcom_nand_host *host, int page) -+{ -+ bool boot_pages_conf = page < host->boot_pages; -+ -+ /* Skip conf write if we are already in the correct mode */ -+ if (boot_pages_conf != host->boot_pages_conf) { -+ host->boot_pages_conf = boot_pages_conf; -+ -+ host->cw_data = boot_pages_conf ? 512 : 516; -+ host->spare_bytes = host->cw_size - host->ecc_bytes_hw - -+ host->bbm_size - host->cw_data; -+ -+ host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); -+ host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | -+ host->cw_data << UD_SIZE_BYTES; -+ -+ host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; -+ host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; -+ host->ecc_buf_cfg = (boot_pages_conf ? 0x1ff : 0x203) << -+ NUM_STEPS; -+ } -+} -+ - /* implements ecc->read_page() */ - static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, - int oob_required, int page) -@@ -2035,6 +2076,9 @@ static int qcom_nandc_read_page(struct n - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - u8 *data_buf, *oob_buf = NULL; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - nand_read_page_op(chip, page, 0, NULL, 0); - data_buf = buf; - oob_buf = oob_required ? chip->oob_poi : NULL; -@@ -2054,6 +2098,9 @@ static int qcom_nandc_read_page_raw(stru - int cw, ret; - u8 *data_buf = buf, *oob_buf = chip->oob_poi; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - for (cw = 0; cw < ecc->steps; cw++) { - ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, - page, cw); -@@ -2074,6 +2121,9 @@ static int qcom_nandc_read_oob(struct na - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct nand_ecc_ctrl *ecc = &chip->ecc; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - clear_read_regs(nandc); - clear_bam_transaction(nandc); - -@@ -2094,6 +2144,9 @@ static int qcom_nandc_write_page(struct - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - - clear_read_regs(nandc); -@@ -2109,7 +2162,7 @@ static int qcom_nandc_write_page(struct - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -2166,6 +2219,9 @@ static int qcom_nandc_write_page_raw(str - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - clear_read_regs(nandc); - clear_bam_transaction(nandc); -@@ -2184,7 +2240,7 @@ static int qcom_nandc_write_page_raw(str - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (qcom_nandc_is_last_cw(ecc, i)) { -+ if (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) << 2); - oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + -@@ -2244,6 +2300,9 @@ static int qcom_nandc_write_oob(struct n - int data_size, oob_size; - int ret; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - host->use_ecc = true; - clear_bam_transaction(nandc); - -@@ -2912,6 +2971,7 @@ static int qcom_nand_host_init_and_regis - struct nand_chip *chip = &host->chip; - struct mtd_info *mtd = nand_to_mtd(chip); - struct device *dev = nandc->dev; -+ u32 boot_pages_size; - int ret; - - ret = of_property_read_u32(dn, "reg", &host->cs); -@@ -2962,6 +3022,17 @@ static int qcom_nand_host_init_and_regis - if (ret) - nand_cleanup(chip); - -+ if (nandc->props->has_boot_pages && -+ of_property_read_bool(dn, "nand-is-boot-medium")) { -+ ret = of_property_read_u32(dn, "qcom,boot_pages_size", -+ &boot_pages_size); -+ if (ret) -+ dev_warn(dev, "can't get boot pages size"); -+ else -+ /* Convert size to nand pages */ -+ host->boot_pages = boot_pages_size / mtd->writesize; -+ } -+ - return ret; - } - -@@ -3127,6 +3198,7 @@ static int qcom_nandc_remove(struct plat - static const struct qcom_nandc_props ipq806x_nandc_props = { - .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), - .is_bam = false, -+ .has_boot_pages = true, - .dev_cmd_reg_start = 0x0, - }; - diff --git a/target/linux/ipq806x/patches-5.15/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch b/target/linux/ipq806x/patches-5.15/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch deleted file mode 100644 index 91d304479a..0000000000 --- a/target/linux/ipq806x/patches-5.15/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 6fb003a7a117f97a35b078ba726c84adeae29c4c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 10 Feb 2021 10:54:19 +0100 -Subject: [PATCH 2/2] Documentation: devicetree: mtd: qcom_nandc: document - qcom,boot_layout_size binding - -Document new qcom,boot_layout_size binding used to apply special -read/write confituation to boots partitions. - -Signed-off-by: Ansuel Smith ---- - Documentation/devicetree/bindings/mtd/qcom,nandc.yaml | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml -+++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml -@@ -78,6 +78,14 @@ allOf: - Must contain the ADM data type CRCI block instance number - specified for the NAND controller on the given platform - -+ qcom,boot_pages_size: -+ description: -+ Should contain the size of the total boot partitions -+ where the boot layout read/write specific configuration -+ should be used. The boot layout is considered from the -+ start of the nand to the value set in this binding. -+ Only used in combination with 'nand-is-boot-medium'. -+ - - if: - properties: - compatible: -@@ -135,6 +143,9 @@ examples: - nand-ecc-strength = <4>; - nand-bus-width = <8>; - -+ nand-is-boot-medium; -+ qcom,boot_pages_size: <0x58a0000>; -+ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; diff --git a/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch b/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch new file mode 100644 index 0000000000..c595b10dd7 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch @@ -0,0 +1,268 @@ +From b360514edb4743cbf86fc377699c75e98b1264c7 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 02:18:33 +0200 +Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct + +Reorder structs in nandc driver to save holes. + +Signed-off-by: Christian Marangi +Reviewed-by: Manivannan Sadhasivam +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-2-ansuelsmth@gmail.com +--- + drivers/mtd/nand/raw/qcom_nandc.c | 107 +++++++++++++++++------------- + 1 file changed, 62 insertions(+), 45 deletions(-) + +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -237,6 +237,9 @@ nandc_set_reg(chip, reg, \ + * @bam_ce - the array of BAM command elements + * @cmd_sgl - sgl for NAND BAM command pipe + * @data_sgl - sgl for NAND BAM consumer/producer pipe ++ * @last_data_desc - last DMA desc in data channel (tx/rx). ++ * @last_cmd_desc - last DMA desc in command channel. ++ * @txn_done - completion for NAND transfer. + * @bam_ce_pos - the index in bam_ce which is available for next sgl + * @bam_ce_start - the index in bam_ce which marks the start position ce + * for current sgl. It will be used for size calculation +@@ -249,14 +252,14 @@ nandc_set_reg(chip, reg, \ + * @rx_sgl_start - start index in data sgl for rx. + * @wait_second_completion - wait for second DMA desc completion before making + * the NAND transfer completion. +- * @txn_done - completion for NAND transfer. +- * @last_data_desc - last DMA desc in data channel (tx/rx). +- * @last_cmd_desc - last DMA desc in command channel. + */ + struct bam_transaction { + struct bam_cmd_element *bam_ce; + struct scatterlist *cmd_sgl; + struct scatterlist *data_sgl; ++ struct dma_async_tx_descriptor *last_data_desc; ++ struct dma_async_tx_descriptor *last_cmd_desc; ++ struct completion txn_done; + u32 bam_ce_pos; + u32 bam_ce_start; + u32 cmd_sgl_pos; +@@ -266,25 +269,23 @@ struct bam_transaction { + u32 rx_sgl_pos; + u32 rx_sgl_start; + bool wait_second_completion; +- struct completion txn_done; +- struct dma_async_tx_descriptor *last_data_desc; +- struct dma_async_tx_descriptor *last_cmd_desc; + }; + + /* + * This data type corresponds to the nand dma descriptor ++ * @dma_desc - low level DMA engine descriptor + * @list - list for desc_info +- * @dir - DMA transfer direction ++ * + * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by + * ADM + * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM +- * @dma_desc - low level DMA engine descriptor ++ * @dir - DMA transfer direction + */ + struct desc_info { ++ struct dma_async_tx_descriptor *dma_desc; + struct list_head node; + +- enum dma_data_direction dir; + union { + struct scatterlist adm_sgl; + struct { +@@ -292,7 +293,7 @@ struct desc_info { + int sgl_cnt; + }; + }; +- struct dma_async_tx_descriptor *dma_desc; ++ enum dma_data_direction dir; + }; + + /* +@@ -336,52 +337,64 @@ struct nandc_regs { + /* + * NAND controller data struct + * +- * @controller: base controller structure +- * @host_list: list containing all the chips attached to the +- * controller + * @dev: parent device ++ * + * @base: MMIO base +- * @base_phys: physical base address of controller registers +- * @base_dma: dma base address of controller registers ++ * + * @core_clk: controller clock + * @aon_clk: another controller clock + * ++ * @regs: a contiguous chunk of memory for DMA register ++ * writes. contains the register values to be ++ * written to controller ++ * ++ * @props: properties of current NAND controller, ++ * initialized via DT match data ++ * ++ * @controller: base controller structure ++ * @host_list: list containing all the chips attached to the ++ * controller ++ * + * @chan: dma channel + * @cmd_crci: ADM DMA CRCI for command flow control + * @data_crci: ADM DMA CRCI for data flow control ++ * + * @desc_list: DMA descriptor list (list of desc_infos) + * + * @data_buffer: our local DMA buffer for page read/writes, + * used when we can't use the buffer provided + * by upper layers directly +- * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf +- * functions + * @reg_read_buf: local buffer for reading back registers via DMA ++ * ++ * @base_phys: physical base address of controller registers ++ * @base_dma: dma base address of controller registers + * @reg_read_dma: contains dma address for register read buffer +- * @reg_read_pos: marker for data read in reg_read_buf + * +- * @regs: a contiguous chunk of memory for DMA register +- * writes. contains the register values to be +- * written to controller +- * @cmd1/vld: some fixed controller register values +- * @props: properties of current NAND controller, +- * initialized via DT match data ++ * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf ++ * functions + * @max_cwperpage: maximum QPIC codewords required. calculated + * from all connected NAND devices pagesize ++ * ++ * @reg_read_pos: marker for data read in reg_read_buf ++ * ++ * @cmd1/vld: some fixed controller register values + */ + struct qcom_nand_controller { +- struct nand_controller controller; +- struct list_head host_list; +- + struct device *dev; + + void __iomem *base; +- phys_addr_t base_phys; +- dma_addr_t base_dma; + + struct clk *core_clk; + struct clk *aon_clk; + ++ struct nandc_regs *regs; ++ struct bam_transaction *bam_txn; ++ ++ const struct qcom_nandc_props *props; ++ ++ struct nand_controller controller; ++ struct list_head host_list; ++ + union { + /* will be used only by QPIC for BAM DMA */ + struct { +@@ -399,22 +412,22 @@ struct qcom_nand_controller { + }; + + struct list_head desc_list; +- struct bam_transaction *bam_txn; + + u8 *data_buffer; ++ __le32 *reg_read_buf; ++ ++ phys_addr_t base_phys; ++ dma_addr_t base_dma; ++ dma_addr_t reg_read_dma; ++ + int buf_size; + int buf_count; + int buf_start; + unsigned int max_cwperpage; + +- __le32 *reg_read_buf; +- dma_addr_t reg_read_dma; + int reg_read_pos; + +- struct nandc_regs *regs; +- + u32 cmd1, vld; +- const struct qcom_nandc_props *props; + }; + + /* +@@ -430,19 +443,21 @@ struct qcom_nand_controller { + * and reserved bytes + * @cw_data: the number of bytes within a codeword protected + * by ECC +- * @use_ecc: request the controller to use ECC for the +- * upcoming read/write +- * @bch_enabled: flag to tell whether BCH ECC mode is used + * @ecc_bytes_hw: ECC bytes used by controller hardware for this + * chip +- * @status: value to be returned if NAND_CMD_STATUS command +- * is executed ++ * + * @last_command: keeps track of last command on this chip. used + * for reading correct status + * + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for + * ecc/non-ecc mode for the current nand flash + * device ++ * ++ * @status: value to be returned if NAND_CMD_STATUS command ++ * is executed ++ * @use_ecc: request the controller to use ECC for the ++ * upcoming read/write ++ * @bch_enabled: flag to tell whether BCH ECC mode is used + */ + struct qcom_nand_host { + struct nand_chip chip; +@@ -451,12 +466,10 @@ struct qcom_nand_host { + int cs; + int cw_size; + int cw_data; +- bool use_ecc; +- bool bch_enabled; + int ecc_bytes_hw; + int spare_bytes; + int bbm_size; +- u8 status; ++ + int last_command; + + u32 cfg0, cfg1; +@@ -465,23 +478,27 @@ struct qcom_nand_host { + u32 ecc_bch_cfg; + u32 clrflashstatus; + u32 clrreadstatus; ++ ++ u8 status; ++ bool use_ecc; ++ bool bch_enabled; + }; + + /* + * This data type corresponds to the NAND controller properties which varies + * among different NAND controllers. + * @ecc_modes - ecc mode for NAND ++ * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset + * @is_bam - whether NAND controller is using BAM + * @is_qpic - whether NAND CTRL is part of qpic IP + * @qpic_v2 - flag to indicate QPIC IP version 2 +- * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset + */ + struct qcom_nandc_props { + u32 ecc_modes; ++ u32 dev_cmd_reg_start; + bool is_bam; + bool is_qpic; + bool qpic_v2; +- u32 dev_cmd_reg_start; + }; + + /* Frees the BAM transaction memory */ diff --git a/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch b/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch new file mode 100644 index 0000000000..2a66195304 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/116-v6.0-02-mtd-nand-raw-qcom_nandc-add-support-for-unprotected-.patch @@ -0,0 +1,406 @@ +From 862bdedd7f4b8aebf00fdb422062e64896e97809 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 16 Jun 2022 02:18:34 +0200 +Subject: [PATCH 2/2] mtd: nand: raw: qcom_nandc: add support for unprotected + spare data pages + +IPQ8064 nand have special pages where a different layout scheme is used. +These special page are used by boot partition and on reading them +lots of warning are reported about wrong ECC data and if written to +results in broken data and not bootable device. + +The layout scheme used by these special page consist in using 512 bytes +as the codeword size (even for the last codeword) while writing to CFG0 +register. This forces the NAND controller to unprotect the 4 bytes of +spare data. + +Since the kernel is unaware of this different layout for these special +page, it does try to protect the spare data too during read/write and +warn about CRC errors. + +Add support for this by permitting the user to declare these special +pages in dts by declaring offset and size of the partition. The driver +internally will convert these value to nand pages. + +On user read/write the page is checked and if it's a boot page the +correct layout is used. + +Signed-off-by: Christian Marangi +Reviewed-by: Manivannan Sadhasivam +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-3-ansuelsmth@gmail.com +--- + drivers/mtd/nand/raw/qcom_nandc.c | 199 +++++++++++++++++++++++++++++- + 1 file changed, 194 insertions(+), 5 deletions(-) + +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -79,8 +79,10 @@ + #define DISABLE_STATUS_AFTER_WRITE 4 + #define CW_PER_PAGE 6 + #define UD_SIZE_BYTES 9 ++#define UD_SIZE_BYTES_MASK GENMASK(18, 9) + #define ECC_PARITY_SIZE_BYTES_RS 19 + #define SPARE_SIZE_BYTES 23 ++#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) + #define NUM_ADDR_CYCLES 27 + #define STATUS_BFR_READ 30 + #define SET_RD_MODE_AFTER_STATUS 31 +@@ -101,6 +103,7 @@ + #define ECC_MODE 4 + #define ECC_PARITY_SIZE_BYTES_BCH 8 + #define ECC_NUM_DATA_BYTES 16 ++#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) + #define ECC_FORCE_CLK_OPEN 30 + + /* NAND_DEV_CMD1 bits */ +@@ -431,12 +434,31 @@ struct qcom_nand_controller { + }; + + /* ++ * NAND special boot partitions ++ * ++ * @page_offset: offset of the partition where spare data is not protected ++ * by ECC (value in pages) ++ * @page_offset: size of the partition where spare data is not protected ++ * by ECC (value in pages) ++ */ ++struct qcom_nand_boot_partition { ++ u32 page_offset; ++ u32 page_size; ++}; ++ ++/* + * NAND chip structure + * ++ * @boot_partitions: array of boot partitions where offset and size of the ++ * boot partitions are stored ++ * + * @chip: base NAND chip structure + * @node: list node to add itself to host_list in + * qcom_nand_controller + * ++ * @nr_boot_partitions: count of the boot partitions where spare data is not ++ * protected by ECC ++ * + * @cs: chip select value for this chip + * @cw_size: the number of bytes in a single step/codeword + * of a page, consisting of all data, ecc, spare +@@ -455,14 +477,20 @@ struct qcom_nand_controller { + * + * @status: value to be returned if NAND_CMD_STATUS command + * is executed ++ * @codeword_fixup: keep track of the current layout used by ++ * the driver for read/write operation. + * @use_ecc: request the controller to use ECC for the + * upcoming read/write + * @bch_enabled: flag to tell whether BCH ECC mode is used + */ + struct qcom_nand_host { ++ struct qcom_nand_boot_partition *boot_partitions; ++ + struct nand_chip chip; + struct list_head node; + ++ int nr_boot_partitions; ++ + int cs; + int cw_size; + int cw_data; +@@ -480,6 +508,7 @@ struct qcom_nand_host { + u32 clrreadstatus; + + u8 status; ++ bool codeword_fixup; + bool use_ecc; + bool bch_enabled; + }; +@@ -492,6 +521,7 @@ struct qcom_nand_host { + * @is_bam - whether NAND controller is using BAM + * @is_qpic - whether NAND CTRL is part of qpic IP + * @qpic_v2 - flag to indicate QPIC IP version 2 ++ * @use_codeword_fixup - whether NAND has different layout for boot partitions + */ + struct qcom_nandc_props { + u32 ecc_modes; +@@ -499,6 +529,7 @@ struct qcom_nandc_props { + bool is_bam; + bool is_qpic; + bool qpic_v2; ++ bool use_codeword_fixup; + }; + + /* Frees the BAM transaction memory */ +@@ -1708,7 +1739,7 @@ qcom_nandc_read_cw_raw(struct mtd_info * + data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); + oob_size1 = host->bbm_size; + +- if (qcom_nandc_is_last_cw(ecc, cw)) { ++ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { + data_size2 = ecc->size - data_size1 - + ((ecc->steps - 1) * 4); + oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + +@@ -1789,7 +1820,7 @@ check_for_erased_page(struct qcom_nand_h + } + + for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { +- if (qcom_nandc_is_last_cw(ecc, cw)) { ++ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { + data_size = ecc->size - ((ecc->steps - 1) * 4); + oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; + } else { +@@ -1947,7 +1978,7 @@ static int read_page_ecc(struct qcom_nan + for (i = 0; i < ecc->steps; i++) { + int data_size, oob_size; + +- if (qcom_nandc_is_last_cw(ecc, i)) { ++ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { + data_size = ecc->size - ((ecc->steps - 1) << 2); + oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + + host->spare_bytes; +@@ -2044,6 +2075,69 @@ static int copy_last_cw(struct qcom_nand + return ret; + } + ++static bool qcom_nandc_is_boot_partition(struct qcom_nand_host *host, int page) ++{ ++ struct qcom_nand_boot_partition *boot_partition; ++ u32 start, end; ++ int i; ++ ++ /* ++ * Since the frequent access will be to the non-boot partitions like rootfs, ++ * optimize the page check by: ++ * ++ * 1. Checking if the page lies after the last boot partition. ++ * 2. Checking from the boot partition end. ++ */ ++ ++ /* First check the last boot partition */ ++ boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1]; ++ start = boot_partition->page_offset; ++ end = start + boot_partition->page_size; ++ ++ /* Page is after the last boot partition end. This is NOT a boot partition */ ++ if (page > end) ++ return false; ++ ++ /* Actually check if it's a boot partition */ ++ if (page < end && page >= start) ++ return true; ++ ++ /* Check the other boot partitions starting from the second-last partition */ ++ for (i = host->nr_boot_partitions - 2; i >= 0; i--) { ++ boot_partition = &host->boot_partitions[i]; ++ start = boot_partition->page_offset; ++ end = start + boot_partition->page_size; ++ ++ if (page < end && page >= start) ++ return true; ++ } ++ ++ return false; ++} ++ ++static void qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page) ++{ ++ bool codeword_fixup = qcom_nandc_is_boot_partition(host, page); ++ ++ /* Skip conf write if we are already in the correct mode */ ++ if (codeword_fixup == host->codeword_fixup) ++ return; ++ ++ host->codeword_fixup = codeword_fixup; ++ ++ host->cw_data = codeword_fixup ? 512 : 516; ++ host->spare_bytes = host->cw_size - host->ecc_bytes_hw - ++ host->bbm_size - host->cw_data; ++ ++ host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); ++ host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | ++ host->cw_data << UD_SIZE_BYTES; ++ ++ host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; ++ host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; ++ host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS; ++} ++ + /* implements ecc->read_page() */ + static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +@@ -2052,6 +2146,9 @@ static int qcom_nandc_read_page(struct n + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + u8 *data_buf, *oob_buf = NULL; + ++ if (host->nr_boot_partitions) ++ qcom_nandc_codeword_fixup(host, page); ++ + nand_read_page_op(chip, page, 0, NULL, 0); + data_buf = buf; + oob_buf = oob_required ? chip->oob_poi : NULL; +@@ -2071,6 +2168,9 @@ static int qcom_nandc_read_page_raw(stru + int cw, ret; + u8 *data_buf = buf, *oob_buf = chip->oob_poi; + ++ if (host->nr_boot_partitions) ++ qcom_nandc_codeword_fixup(host, page); ++ + for (cw = 0; cw < ecc->steps; cw++) { + ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, + page, cw); +@@ -2091,6 +2191,9 @@ static int qcom_nandc_read_oob(struct na + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + ++ if (host->nr_boot_partitions) ++ qcom_nandc_codeword_fixup(host, page); ++ + clear_read_regs(nandc); + clear_bam_transaction(nandc); + +@@ -2111,6 +2214,9 @@ static int qcom_nandc_write_page(struct + u8 *data_buf, *oob_buf; + int i, ret; + ++ if (host->nr_boot_partitions) ++ qcom_nandc_codeword_fixup(host, page); ++ + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + + clear_read_regs(nandc); +@@ -2126,7 +2232,7 @@ static int qcom_nandc_write_page(struct + for (i = 0; i < ecc->steps; i++) { + int data_size, oob_size; + +- if (qcom_nandc_is_last_cw(ecc, i)) { ++ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { + data_size = ecc->size - ((ecc->steps - 1) << 2); + oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + + host->spare_bytes; +@@ -2183,6 +2289,9 @@ static int qcom_nandc_write_page_raw(str + u8 *data_buf, *oob_buf; + int i, ret; + ++ if (host->nr_boot_partitions) ++ qcom_nandc_codeword_fixup(host, page); ++ + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + clear_read_regs(nandc); + clear_bam_transaction(nandc); +@@ -2201,7 +2310,7 @@ static int qcom_nandc_write_page_raw(str + data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); + oob_size1 = host->bbm_size; + +- if (qcom_nandc_is_last_cw(ecc, i)) { ++ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { + data_size2 = ecc->size - data_size1 - + ((ecc->steps - 1) << 2); + oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + +@@ -2261,6 +2370,9 @@ static int qcom_nandc_write_oob(struct n + int data_size, oob_size; + int ret; + ++ if (host->nr_boot_partitions) ++ qcom_nandc_codeword_fixup(host, page); ++ + host->use_ecc = true; + clear_bam_transaction(nandc); + +@@ -2922,6 +3034,74 @@ static int qcom_nandc_setup(struct qcom_ + + static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL }; + ++static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc, ++ struct qcom_nand_host *host, ++ struct device_node *dn) ++{ ++ struct nand_chip *chip = &host->chip; ++ struct mtd_info *mtd = nand_to_mtd(chip); ++ struct qcom_nand_boot_partition *boot_partition; ++ struct device *dev = nandc->dev; ++ int partitions_count, i, j, ret; ++ ++ if (!of_find_property(dn, "qcom,boot-partitions", NULL)) ++ return 0; ++ ++ partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); ++ if (partitions_count <= 0) { ++ dev_err(dev, "Error parsing boot partition\n"); ++ return partitions_count ? partitions_count : -EINVAL; ++ } ++ ++ host->nr_boot_partitions = partitions_count / 2; ++ host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, ++ sizeof(*host->boot_partitions), GFP_KERNEL); ++ if (!host->boot_partitions) { ++ host->nr_boot_partitions = 0; ++ return -ENOMEM; ++ } ++ ++ for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { ++ boot_partition = &host->boot_partitions[i]; ++ ++ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, ++ &boot_partition->page_offset); ++ if (ret) { ++ dev_err(dev, "Error parsing boot partition offset at index %d\n", i); ++ host->nr_boot_partitions = 0; ++ return ret; ++ } ++ ++ if (boot_partition->page_offset % mtd->writesize) { ++ dev_err(dev, "Boot partition offset not multiple of writesize at index %i\n", ++ i); ++ host->nr_boot_partitions = 0; ++ return -EINVAL; ++ } ++ /* Convert offset to nand pages */ ++ boot_partition->page_offset /= mtd->writesize; ++ ++ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, ++ &boot_partition->page_size); ++ if (ret) { ++ dev_err(dev, "Error parsing boot partition size at index %d\n", i); ++ host->nr_boot_partitions = 0; ++ return ret; ++ } ++ ++ if (boot_partition->page_size % mtd->writesize) { ++ dev_err(dev, "Boot partition size not multiple of writesize at index %i\n", ++ i); ++ host->nr_boot_partitions = 0; ++ return -EINVAL; ++ } ++ /* Convert size to nand pages */ ++ boot_partition->page_size /= mtd->writesize; ++ } ++ ++ return 0; ++} ++ + static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, + struct qcom_nand_host *host, + struct device_node *dn) +@@ -2979,6 +3159,14 @@ static int qcom_nand_host_init_and_regis + if (ret) + nand_cleanup(chip); + ++ if (nandc->props->use_codeword_fixup) { ++ ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); ++ if (ret) { ++ nand_cleanup(chip); ++ return ret; ++ } ++ } ++ + return ret; + } + +@@ -3144,6 +3332,7 @@ static int qcom_nandc_remove(struct plat + static const struct qcom_nandc_props ipq806x_nandc_props = { + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), + .is_bam = false, ++ .use_codeword_fixup = true, + .dev_cmd_reg_start = 0x0, + }; + From 900542698c34ec70669bd524c410733771087fee Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:20:30 +0200 Subject: [PATCH 32/43] ipq806x: 5.15: remove useless spm patch Remove useless spm patch as using the normal qcom,spm compatible is enough to register it with no clks. Signed-off-by: Christian Marangi --- .../patches-5.15/0072-add-ipq806x-with-no-clocks.patch | 10 ---------- 1 file changed, 10 deletions(-) delete mode 100644 target/linux/ipq806x/patches-5.15/0072-add-ipq806x-with-no-clocks.patch diff --git a/target/linux/ipq806x/patches-5.15/0072-add-ipq806x-with-no-clocks.patch b/target/linux/ipq806x/patches-5.15/0072-add-ipq806x-with-no-clocks.patch deleted file mode 100644 index 47394f5bbc..0000000000 --- a/target/linux/ipq806x/patches-5.15/0072-add-ipq806x-with-no-clocks.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -1333,6 +1333,7 @@ static const struct of_device_id qcom_sc - SCM_HAS_BUS_CLK) - }, - { .compatible = "qcom,scm-ipq4019" }, -+ { .compatible = "qcom,scm-ipq806x" }, - { .compatible = "qcom,scm-mdm9607", .data = (void *)(SCM_HAS_CORE_CLK | - SCM_HAS_IFACE_CLK | - SCM_HAS_BUS_CLK) }, From 6134ba4a34db8768cea0df487cb1e2a1400b90b2 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 16 Jun 2022 22:32:35 +0200 Subject: [PATCH 33/43] ipq806x: 5.15: add boot-partitions binding to fix block warning The patch has changed implementation and now the binding has changed. Replace the old binding with boot-partitions and reimplement the definition with the new definition. The new definition is: and now supports sparsed patch. Also add missing binding in some dts and add the backup boot partition to the boot-partitions list. Signed-off-by: Christian Marangi --- .../ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 2 +- .../files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi | 2 +- .../ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts | 2 +- .../ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 2 +- .../files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts | 2 +- .../files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 2 +- .../files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi | 2 +- .../files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 2 ++ .../files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts | 2 ++ .../arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi | 2 +- 10 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts index f9f9c035d3..719b9c86c5 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts @@ -243,7 +243,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; + qcom,boot-partitions = <0x0 0x1180000>; partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi index 68e5b24704..b9b296094b 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi @@ -46,7 +46,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x0c80000>; + qcom,boot-partitions = <0x0 0x0c80000>; partitions: partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts index ba27d89c05..75b02a00d0 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts @@ -238,7 +238,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x1200000>; + qcom,boot-partitions = <0x0 0x1200000>; partitions { compatible = "qcom,smem-part"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts index 1505e23f38..aa783e7ee6 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts @@ -176,7 +176,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; + qcom,boot-partitions = <0x0 0x1180000>; partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts index b43ee90034..23a32697e1 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts @@ -240,7 +240,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; + qcom,boot-partitions = <0x0 0x1180000>; partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts index d7f3a7f881..983a4243db 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts @@ -119,7 +119,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; + qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x6400000>; partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi index 6c007e2c16..420b540132 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi @@ -232,7 +232,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; + qcom,boot-partitions = <0x0 0x1180000>; partitions: partitions { compatible = "fixed-partitions"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts index 51ef2c3321..902f7d6098 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts @@ -138,6 +138,8 @@ nand-bus-width = <8>; nand-ecc-step-size = <512>; + qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x2400000>; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts index 9244639137..db9bab18dd 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts @@ -127,6 +127,8 @@ nand-bus-width = <8>; nand-ecc-step-size = <512>; + qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x6400000>; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi index 93b9aa86f7..a8f43591f9 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi @@ -150,7 +150,7 @@ nand-ecc-step-size = <512>; nand-is-boot-medium; - qcom,boot_pages_size = <0x2140000>; + qcom,boot-partitions = <0x0 0x2140000>; partitions { compatible = "fixed-partitions"; From 9254ed0f3b02bc9cfcc69d78c8fe69e0097818f7 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 18 Jun 2022 04:05:08 +0200 Subject: [PATCH 34/43] ipq806x: 5.15: rework nand_pins for wg2600hp3 dts nand_pins definition is now shipped in ipq8064 dtsi. Rework the nand_pins definition for wg2600hp3 5.15 files. Signed-off-by: Christian Marangi --- .../files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts index 11ae3f81c3..c3b3f6feda 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts @@ -3,8 +3,6 @@ #include "qcom-ipq8062-smb208.dtsi" #include -/delete-node/ &nand_pins; - / { model = "NEC Platforms Aterm WG2600HP3"; compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064"; From 8392a6b395c036cfc82a181cb1d814ba2249481c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 18 Jun 2022 04:08:38 +0200 Subject: [PATCH 35/43] ipq806x: 5.15: enable new devfreq scaling driver in config Enable new devfreq scaling driver in kernel config. Signed-off-by: Christian Marangi --- target/linux/ipq806x/config-5.15 | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/linux/ipq806x/config-5.15 b/target/linux/ipq806x/config-5.15 index 967abbfb08..b2b3e601be 100644 --- a/target/linux/ipq806x/config-5.15 +++ b/target/linux/ipq806x/config-5.15 @@ -121,12 +121,14 @@ CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_GPIO=y CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEVFREQ_GOV_PASSIVE is not set +CONFIG_DEVFREQ_GOV_PASSIVE=y # CONFIG_DEVFREQ_GOV_PERFORMANCE is not set # CONFIG_DEVFREQ_GOV_POWERSAVE is not set # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set # CONFIG_DEVFREQ_GOV_USERSPACE is not set # CONFIG_DEVFREQ_THERMAL is not set +CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y +CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y From 78fef3cc6f466ed54ee8fa97931e55eb5b41e1f0 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 13 Sep 2022 18:42:21 +0200 Subject: [PATCH 36/43] ipq806x: 5.15: renumber tsens patch with new order Renumber tsens patch with new order for consistency. Signed-off-by: Christian Marangi --- ...01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch} | 0 ...10-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename target/linux/ipq806x/patches-5.15/{107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch => 110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch} (100%) rename target/linux/ipq806x/patches-5.15/{107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch => 110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch} (100%) diff --git a/target/linux/ipq806x/patches-5.15/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch b/target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch similarity index 100% rename from target/linux/ipq806x/patches-5.15/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch rename to target/linux/ipq806x/patches-5.15/110-01-thermal-qcom-tsens-init-debugfs-only-with-successful.patch diff --git a/target/linux/ipq806x/patches-5.15/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch b/target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch similarity index 100% rename from target/linux/ipq806x/patches-5.15/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch rename to target/linux/ipq806x/patches-5.15/110-02-thermal-qcom-tsens-simplify-debugfs-init-function.patch From a7c7a3c009eb1b0590b55f2614521e9bc62d2468 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 13 Sep 2022 18:43:47 +0200 Subject: [PATCH 37/43] ipq806x: 5.15: backport qcom clk fixes for krait and hfpll Backport some qcom clock fixes for krait and hfpll driver. Signed-off-by: Christian Marangi --- ...com-clk-hfpll-use-poll_timeout-macro.patch | 41 +++++++++ ...it-add-apq-ipq8064-errata-workaround.patch | 86 +++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch create mode 100644 target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch new file mode 100644 index 0000000000..3008fff9b7 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch @@ -0,0 +1,41 @@ +From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 30 Apr 2022 07:44:56 +0200 +Subject: [PATCH 1/3] clk: qcom: clk-hfpll: use poll_timeout macro + +Use regmap_read_poll_timeout macro instead of do-while structure to tidy +things up. Also set a timeout to prevent any sort of system stall. + +Signed-off-by: Ansuel Smith +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com +--- + drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +--- a/drivers/clk/qcom/clk-hfpll.c ++++ b/drivers/clk/qcom/clk-hfpll.c +@@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct cl + regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); + + /* Wait for PLL to lock. */ +- if (hd->status_reg) { +- do { +- regmap_read(regmap, hd->status_reg, &val); +- } while (!(val & BIT(hd->lock_bit))); +- } else { ++ if (hd->status_reg) ++ /* ++ * Busy wait. Should never timeout, we add a timeout to ++ * prevent any sort of stall. ++ */ ++ regmap_read_poll_timeout(regmap, hd->status_reg, val, ++ !(val & BIT(hd->lock_bit)), 0, ++ 100 * USEC_PER_MSEC); ++ else + udelay(60); +- } + + /* Enable PLL output. */ + regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch new file mode 100644 index 0000000000..4012e16f9b --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/117-v6.0-03-clk-qcom-clk-krait-add-apq-ipq8064-errata-workaround.patch @@ -0,0 +1,86 @@ +From 898d0d6483a9360f1968e0a900465c1fa152a4a9 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 30 Apr 2022 07:44:58 +0200 +Subject: [PATCH 3/3] clk: qcom: clk-krait: add apq/ipq8064 errata workaround + +Add apq/ipq8064 errata workaround where the sec_src clock gating needs to +be disabled during switching. krait-cc compatible is not enough to +handle this and limit this workaround to apq/ipq8064. We check machine +compatible to handle this. + +Signed-off-by: Ansuel Smith +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com +--- + drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ + drivers/clk/qcom/clk-krait.h | 1 + + drivers/clk/qcom/krait-cc.c | 8 ++++++++ + 3 files changed, 25 insertions(+) + +--- a/drivers/clk/qcom/clk-krait.c ++++ b/drivers/clk/qcom/clk-krait.c +@@ -18,13 +18,23 @@ + static DEFINE_SPINLOCK(krait_clock_reg_lock); + + #define LPL_SHIFT 8 ++#define SECCLKAGD BIT(4) ++ + static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) + { + unsigned long flags; + u32 regval; + + spin_lock_irqsave(&krait_clock_reg_lock, flags); ++ + regval = krait_get_l2_indirect_reg(mux->offset); ++ ++ /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ ++ if (mux->disable_sec_src_gating) { ++ regval |= SECCLKAGD; ++ krait_set_l2_indirect_reg(mux->offset, regval); ++ } ++ + regval &= ~(mux->mask << mux->shift); + regval |= (sel & mux->mask) << mux->shift; + if (mux->lpl) { +@@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct k + } + krait_set_l2_indirect_reg(mux->offset, regval); + ++ /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ ++ if (mux->disable_sec_src_gating) { ++ regval &= ~SECCLKAGD; ++ krait_set_l2_indirect_reg(mux->offset, regval); ++ } ++ + /* Wait for switch to complete. */ + mb(); + udelay(1); +--- a/drivers/clk/qcom/clk-krait.h ++++ b/drivers/clk/qcom/clk-krait.h +@@ -15,6 +15,7 @@ struct krait_mux_clk { + u8 safe_sel; + u8 old_index; + bool reparent; ++ bool disable_sec_src_gating; + + struct clk_hw hw; + struct notifier_block clk_nb; +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -139,6 +139,14 @@ krait_add_sec_mux(struct device *dev, in + mux->hw.init = &init; + mux->safe_sel = 0; + ++ /* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not ++ * enough to limit this to apq/ipq8064. Directly check machine ++ * compatible to correctly handle this errata. ++ */ ++ if (of_machine_is_compatible("qcom,ipq8064") || ++ of_machine_is_compatible("qcom,apq8064")) ++ mux->disable_sec_src_gating = true; ++ + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); + if (!init.name) + return -ENOMEM; From e5a3720a56c277c7e083dac335b6aa442aa58d98 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 13 Sep 2022 18:45:10 +0200 Subject: [PATCH 38/43] ipq806x: 5.15: add krait clock modernization patch Backport krait clock modernization patch. Signed-off-by: Christian Marangi --- ...vm_-hw_register_mux_parent_data_tabl.patch | 46 +++++++++++ ...-kpss-xcc-convert-to-parent-data-API.patch | 70 +++++++++++++++++ ...add-rpmcc-missing-clocks-for-apq-ipq.patch | 59 ++++++++++++++ ...m-clk-rpm-convert-to-parent_data-API.patch | 76 +++++++++++++++++++ ...ipq806x-remove-cc_register_board-for.patch | 31 ++++++++ 5 files changed, 282 insertions(+) create mode 100644 target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch create mode 100644 target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch create mode 100644 target/linux/ipq806x/patches-5.15/119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch create mode 100644 target/linux/ipq806x/patches-5.15/119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch create mode 100644 target/linux/ipq806x/patches-5.15/119-04-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch diff --git a/target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch b/target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch new file mode 100644 index 0000000000..a15a723029 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/118-03-clk-introduce-devm_-hw_register_mux_parent_data_tabl.patch @@ -0,0 +1,46 @@ +From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 12 Apr 2022 16:48:39 +0200 +Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table + API + +Introduce (devm_)hw_register_mux_parent_data_table new API. We have +basic support for clk_register_mux using parent_data but we lack any API +to provide a custom parent_map. Add these 2 new API to correctly handle +these special configuration instead of using the generic +__(devm_)clk_hw_register_mux API. + +Signed-off-by: Christian Marangi +--- + include/linux/clk-provider.h | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -932,12 +932,26 @@ struct clk *clk_register_mux_table(struc + __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ + (parent_data), (flags), (reg), (shift), \ + BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) ++#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ ++ num_parents, flags, reg, shift, \ ++ width, clk_mux_flags, table, \ ++ lock) \ ++ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ ++ (parent_data), (flags), (reg), (shift), \ ++ BIT((width)) - 1, (clk_mux_flags), table, (lock)) + #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ + shift, width, clk_mux_flags, lock) \ + __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ + (parent_names), NULL, NULL, (flags), (reg), \ + (shift), BIT((width)) - 1, (clk_mux_flags), \ + NULL, (lock)) ++#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ ++ num_parents, flags, reg, shift, \ ++ width, clk_mux_flags, table, \ ++ lock) \ ++ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ ++ NULL, (parent_data), (flags), (reg), (shift), \ ++ BIT((width)) - 1, (clk_mux_flags), table, (lock)) + + int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, + unsigned int val); diff --git a/target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch b/target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch new file mode 100644 index 0000000000..6c5f5ea96b --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/118-04-clk-qcom-kpss-xcc-convert-to-parent-data-API.patch @@ -0,0 +1,70 @@ +From d08c79b818767f24c3c9cbba585d8a3ec896c1a1 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 17 Feb 2022 22:43:34 +0100 +Subject: [PATCH 4/4] clk: qcom: kpss-xcc: convert to parent data API + +Convert the driver to parent data API. From the Documentation pll8_vote +and pxo should be declared in the DTS so fw_name can be used instead of +parent_names. Name is still used to save regression on old definition. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/kpss-xcc.c | 26 +++++++++----------------- + 1 file changed, 9 insertions(+), 17 deletions(-) + +--- a/drivers/clk/qcom/kpss-xcc.c ++++ b/drivers/clk/qcom/kpss-xcc.c +@@ -12,9 +12,9 @@ + #include + #include + +-static const char *aux_parents[] = { +- "pll8_vote", +- "pxo", ++static const struct clk_parent_data aux_parents[] = { ++ { .name = "pll8_vote", .fw_name = "pll8_vote" }, ++ { .name = "pxo", .fw_name = "pxo" }, + }; + + static unsigned int aux_parent_map[] = { +@@ -32,9 +32,9 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t + static int kpss_xcc_driver_probe(struct platform_device *pdev) + { + const struct of_device_id *id; +- struct clk *clk; + struct resource *res; + void __iomem *base; ++ struct clk_hw *hw; + const char *name; + + id = of_match_device(kpss_xcc_match_table, &pdev->dev); +@@ -57,24 +57,16 @@ static int kpss_xcc_driver_probe(struct + base += 0x28; + } + +- clk = clk_register_mux_table(&pdev->dev, name, aux_parents, +- ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, +- 0, aux_parent_map, NULL); ++ hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, ++ ARRAY_SIZE(aux_parents), 0, ++ base, 0, 0x3, ++ 0, aux_parent_map, NULL); + +- platform_set_drvdata(pdev, clk); +- +- return PTR_ERR_OR_ZERO(clk); +-} +- +-static int kpss_xcc_driver_remove(struct platform_device *pdev) +-{ +- clk_unregister_mux(platform_get_drvdata(pdev)); +- return 0; ++ return PTR_ERR_OR_ZERO(hw); + } + + static struct platform_driver kpss_xcc_driver = { + .probe = kpss_xcc_driver_probe, +- .remove = kpss_xcc_driver_remove, + .driver = { + .name = "kpss-xcc", + .of_match_table = kpss_xcc_match_table, diff --git a/target/linux/ipq806x/patches-5.15/119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch b/target/linux/ipq806x/patches-5.15/119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch new file mode 100644 index 0000000000..b82239f135 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/119-02-ARM-DTS-qcom-add-rpmcc-missing-clocks-for-apq-ipq.patch @@ -0,0 +1,59 @@ +From 3a0cf0a2b99fb3d193d72e3804292697d73d3aab Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 5 Jul 2022 21:29:01 +0200 +Subject: [PATCH v2 2/4] ARM: DTS: qcom: add rpmcc missing clocks for + apq/ipq8064 and msm8660 + +Add missing rpmcc pxo and cxo clock for apq8064, ipq8064 and +msm8660 dtsi. + +Signed-off-by: Christian Marangi +Reviewed-by: Dmitry Baryshkov +--- + arch/arm/boot/dts/qcom-apq8064.dtsi | 2 ++ + arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++ + arch/arm/boot/dts/qcom-msm8660.dtsi | 4 +++- + 3 files changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/qcom-apq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-apq8064.dtsi +@@ -862,6 +862,8 @@ + rpmcc: clock-controller { + compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; + #clock-cells = <1>; ++ clocks = <&pxo_board>, <&cxo_board>; ++ clock-names = "pxo", "cxo"; + }; + + regulators { +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1074,6 +1074,8 @@ + rpmcc: clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; ++ clocks = <&pxo_board>; ++ clock-names = "pxo"; + }; + }; + +--- a/arch/arm/boot/dts/qcom-msm8660.dtsi ++++ b/arch/arm/boot/dts/qcom-msm8660.dtsi +@@ -56,7 +56,7 @@ + clock-frequency = <19200000>; + }; + +- pxo_board { ++ pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; +@@ -420,6 +420,8 @@ + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; + #clock-cells = <1>; ++ clocks = <&pxo_board>; ++ clock-names = "pxo"; + }; + + pm8901-regulators { diff --git a/target/linux/ipq806x/patches-5.15/119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch new file mode 100644 index 0000000000..8398fb4ae3 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/119-03-clk-qcom-clk-rpm-convert-to-parent_data-API.patch @@ -0,0 +1,76 @@ +From 3d8c0e94a792ae62fa0495ac940c9850a059afc2 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 5 Jul 2022 21:39:18 +0200 +Subject: [PATCH v2 3/4] clk: qcom: clk-rpm: convert to parent_data API + +Convert clk-rpm driver to parent_data API. +We keep the old pxo/cxo_board parent naming to keep compatibility with +old DT and we use the new pxo/cxo for new implementation where these +clock are defined in DTS. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/clk-rpm.c | 24 ++++++++++++++++-------- + 1 file changed, 16 insertions(+), 8 deletions(-) + +--- a/drivers/clk/qcom/clk-rpm.c ++++ b/drivers/clk/qcom/clk-rpm.c +@@ -23,6 +23,14 @@ + #define QCOM_RPM_SCALING_ENABLE_ID 0x2 + #define QCOM_RPM_XO_MODE_ON 0x2 + ++static const struct clk_parent_data gcc_pxo[] = { ++ { .fw_name = "pxo", .name = "pxo_board" }, ++}; ++ ++static const struct clk_parent_data gcc_cxo[] = { ++ { .fw_name = "cxo", .name = "cxo_board" }, ++}; ++ + #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \ + static struct clk_rpm _platform##_##_active; \ + static struct clk_rpm _platform##_##_name = { \ +@@ -32,8 +40,8 @@ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_rpm_ops, \ + .name = #_name, \ +- .parent_names = (const char *[]){ "pxo_board" }, \ +- .num_parents = 1, \ ++ .parent_data = gcc_pxo, \ ++ .num_parents = ARRAY_SIZE(gcc_pxo), \ + }, \ + }; \ + static struct clk_rpm _platform##_##_active = { \ +@@ -44,8 +52,8 @@ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_rpm_ops, \ + .name = #_active, \ +- .parent_names = (const char *[]){ "pxo_board" }, \ +- .num_parents = 1, \ ++ .parent_data = gcc_pxo, \ ++ .num_parents = ARRAY_SIZE(gcc_pxo), \ + }, \ + } + +@@ -56,8 +64,8 @@ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_rpm_xo_ops, \ + .name = #_name, \ +- .parent_names = (const char *[]){ "cxo_board" }, \ +- .num_parents = 1, \ ++ .parent_data = gcc_cxo, \ ++ .num_parents = ARRAY_SIZE(gcc_cxo), \ + }, \ + } + +@@ -68,8 +76,8 @@ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_rpm_fixed_ops, \ + .name = #_name, \ +- .parent_names = (const char *[]){ "pxo" }, \ +- .num_parents = 1, \ ++ .parent_data = gcc_pxo, \ ++ .num_parents = ARRAY_SIZE(gcc_pxo), \ + }, \ + } + diff --git a/target/linux/ipq806x/patches-5.15/119-04-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-5.15/119-04-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch new file mode 100644 index 0000000000..20e7440ace --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/119-04-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch @@ -0,0 +1,31 @@ +From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Tue, 5 Jul 2022 18:30:18 +0200 +Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for + pxo and cxo + +Now that these clock are defined as fixed clk in dts, we can drop the +register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/gcc-ipq806x.c | 8 -------- + 1 file changed, 8 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -3384,14 +3384,6 @@ static int gcc_ipq806x_probe(struct plat + struct regmap *regmap; + int ret; + +- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); +- if (ret) +- return ret; +- +- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); +- if (ret) +- return ret; +- + if (of_machine_is_compatible("qcom,ipq8065")) { + ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; + ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; From 6f1b89babaa519afbbd8ea7f7d1cbcc855dbb31c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 15 Sep 2022 04:01:22 +0200 Subject: [PATCH 39/43] ipq806x: 5.15: add krait-cc modernization patch and fixup Add multiple patch for krait-cc modernization and multiple fixup for the driver. Also modify a patch to enable the qsb fixed clock and add pxo to krait-cc node. Signed-off-by: Christian Marangi --- ...add-saw-for-l2-cache-and-kraitcc-for.patch | 16 +- ...kpss-xcc-register-it-as-clk-provider.patch | 64 +++++ ...-krait-cc-convert-to-parent_data-API.patch | 269 ++++++++++++++++++ ...t-cc-handle-qsb-clock-defined-in-DTS.patch | 52 ++++ ...ait-cc-register-REAL-qsb-fixed-clock.patch | 59 ++++ ...c-use-devm-variant-for-clk-notifier-.patch | 30 ++ ...t-cc-fix-never-enabled-secondary-mux.patch | 52 ++++ ...ait-cc-drop-pr_info-and-use-dev_info.patch | 49 ++++ ...c-handle-secondary-mux-sourcing-out-.patch | 75 +++++ ...c-rework-mux-reset-logic-and-reset-h.patch | 102 +++++++ 10 files changed, 760 insertions(+), 8 deletions(-) create mode 100644 target/linux/ipq806x/patches-5.15/121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch create mode 100644 target/linux/ipq806x/patches-5.15/121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch diff --git a/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch index 12e4874f6b..418d6b26ce 100644 --- a/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch +++ b/target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch @@ -20,11 +20,11 @@ Tested-by: Jonathan McDowell }; clocks { -+// qsb: qsb { -+// compatible = "fixed-clock"; -+// clock-frequency = <384000000>; -+// #clock-cells = <0>; -+// }; ++ qsb: qsb { ++ compatible = "fixed-clock"; ++ clock-frequency = <225000000>; ++ #clock-cells = <0>; ++ }; + cxo_board: cxo_board { compatible = "fixed-clock"; @@ -85,10 +85,10 @@ Tested-by: Jonathan McDowell + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, -+ <&acc0>, <&acc1>, <&l2cc>; // <&qsb> ++ <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>; + clock-names = "hfpll0", "hfpll1", "hfpll_l2", -+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux"; -+// "qsb"; ++ "acpu0_aux", "acpu1_aux", "acpu_l2_aux", ++ "qsb", "pxo"; + #clock-cells = <1>; }; diff --git a/target/linux/ipq806x/patches-5.15/121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch b/target/linux/ipq806x/patches-5.15/121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch new file mode 100644 index 0000000000..36716591f0 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-01-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch @@ -0,0 +1,64 @@ +From 09930efb4f4fb81019ca33bf64827ce258eca66f Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 01:58:12 +0200 +Subject: [PATCH 1/9] clk: qcom: kpss-xcc: register it as clk provider + +krait-cc use this driver for the secondary mux. Register it as a clk +provider to correctly use this clk in other drivers. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/kpss-xcc.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c +index b1b370274ec4..97358c98c6c9 100644 +--- a/drivers/clk/qcom/kpss-xcc.c ++++ b/drivers/clk/qcom/kpss-xcc.c +@@ -31,13 +31,14 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); + + static int kpss_xcc_driver_probe(struct platform_device *pdev) + { ++ struct device *dev = &pdev->dev; + const struct of_device_id *id; + struct resource *res; + void __iomem *base; + struct clk_hw *hw; + const char *name; + +- id = of_match_device(kpss_xcc_match_table, &pdev->dev); ++ id = of_match_device(kpss_xcc_match_table, dev); + if (!id) + return -ENODEV; + +@@ -45,7 +46,7 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev) + return PTR_ERR(base); + + if (id->data) { +- if (of_property_read_string_index(pdev->dev.of_node, ++ if (of_property_read_string_index(dev->of_node, + "clock-output-names", + 0, &name)) + return -ENODEV; +@@ -55,12 +56,16 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev) + base += 0x28; + } + +- hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents, ++ hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents, + ARRAY_SIZE(aux_parents), 0, + base, 0, 0x3, + 0, aux_parent_map, NULL); ++ if (IS_ERR(hw)) ++ return PTR_ERR(hw); + +- return PTR_ERR_OR_ZERO(hw); ++ of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw); ++ ++ return 0; + } + + static struct platform_driver kpss_xcc_driver = { +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch new file mode 100644 index 0000000000..26f8333990 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-02-clk-qcom-krait-cc-convert-to-parent_data-API.patch @@ -0,0 +1,269 @@ +From 334c1540d5753a3c83a4cb84d935d606cb47a03b Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 17 Feb 2022 23:02:59 +0100 +Subject: [PATCH 2/9] clk: qcom: krait-cc: convert to parent_data API + +Modernize the krait-cc driver to parent-data API and refactor to drop +any use of clk_names. From Documentation all the required clocks should +be declared in DTS so fw_name can be correctly used to get the parents +for all the muxes. .name is also declared to save compatibility with old +implementation. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 126 +++++++++++++++++++----------------- + 1 file changed, 66 insertions(+), 60 deletions(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index cfd961d5cc45..84f0048961f5 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -69,21 +69,22 @@ static int krait_notifier_register(struct device *dev, struct clk *clk, + return ret; + } + +-static int ++static struct clk * + krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) + { + struct krait_div2_clk *div; ++ static struct clk_parent_data p_data[1]; + struct clk_init_data init = { +- .num_parents = 1, ++ .num_parents = ARRAY_SIZE(p_data), + .ops = &krait_div2_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; +- const char *p_names[1]; + struct clk *clk; ++ char *parent_name; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + + div->width = 2; + div->shift = 6; +@@ -93,43 +94,49 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) + + init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); + if (!init.name) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + +- init.parent_names = p_names; +- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); +- if (!p_names[0]) { +- kfree(init.name); +- return -ENOMEM; ++ init.parent_data = p_data; ++ parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!parent_name) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_parent_name; + } + ++ p_data[0].fw_name = parent_name; ++ p_data[0].name = parent_name; ++ + clk = devm_clk_register(dev, &div->hw); +- kfree(p_names[0]); ++ ++ kfree(parent_name); ++err_parent_name: + kfree(init.name); + +- return PTR_ERR_OR_ZERO(clk); ++ return clk; + } + +-static int ++static struct clk * + krait_add_sec_mux(struct device *dev, int id, const char *s, + unsigned int offset, bool unique_aux) + { + int ret; + struct krait_mux_clk *mux; +- static const char *sec_mux_list[] = { +- "acpu_aux", +- "qsb", ++ static struct clk_parent_data sec_mux_list[2] = { ++ { .name = "qsb", .fw_name = "qsb" }, ++ {}, + }; + struct clk_init_data init = { +- .parent_names = sec_mux_list, ++ .parent_data = sec_mux_list, + .num_parents = ARRAY_SIZE(sec_mux_list), + .ops = &krait_mux_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; + struct clk *clk; ++ char *parent_name; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + + mux->offset = offset; + mux->lpl = id >= 0; +@@ -149,44 +156,51 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, + + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); + if (!init.name) +- return -ENOMEM; ++ return ERR_PTR(-ENOMEM); + + if (unique_aux) { +- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); +- if (!sec_mux_list[0]) { ++ parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); ++ if (!parent_name) { + clk = ERR_PTR(-ENOMEM); + goto err_aux; + } ++ sec_mux_list[1].fw_name = parent_name; ++ sec_mux_list[1].name = parent_name; ++ } else { ++ sec_mux_list[1].name = "apu_aux"; + } + + clk = devm_clk_register(dev, &mux->hw); ++ if (IS_ERR(clk)) ++ goto err_clk; + + ret = krait_notifier_register(dev, clk, mux); + if (ret) +- goto unique_aux; ++ clk = ERR_PTR(ret); + +-unique_aux: ++err_clk: + if (unique_aux) +- kfree(sec_mux_list[0]); ++ kfree(parent_name); + err_aux: + kfree(init.name); +- return PTR_ERR_OR_ZERO(clk); ++ return clk; + } + + static struct clk * +-krait_add_pri_mux(struct device *dev, int id, const char *s, +- unsigned int offset) ++krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux, ++ int id, const char *s, unsigned int offset) + { + int ret; + struct krait_mux_clk *mux; +- const char *p_names[3]; ++ static struct clk_parent_data p_data[3]; + struct clk_init_data init = { +- .parent_names = p_names, +- .num_parents = ARRAY_SIZE(p_names), ++ .parent_data = p_data, ++ .num_parents = ARRAY_SIZE(p_data), + .ops = &krait_mux_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; + struct clk *clk; ++ char *hfpll_name; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) +@@ -204,36 +218,29 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, + if (!init.name) + return ERR_PTR(-ENOMEM); + +- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); +- if (!p_names[0]) { ++ hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!hfpll_name) { + clk = ERR_PTR(-ENOMEM); +- goto err_p0; ++ goto err_hfpll; + } + +- p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); +- if (!p_names[1]) { +- clk = ERR_PTR(-ENOMEM); +- goto err_p1; +- } ++ p_data[0].fw_name = hfpll_name; ++ p_data[0].name = hfpll_name; + +- p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); +- if (!p_names[2]) { +- clk = ERR_PTR(-ENOMEM); +- goto err_p2; +- } ++ p_data[1].hw = __clk_get_hw(hfpll_div); ++ p_data[2].hw = __clk_get_hw(sec_mux); + + clk = devm_clk_register(dev, &mux->hw); ++ if (IS_ERR(clk)) ++ goto err_clk; + + ret = krait_notifier_register(dev, clk, mux); + if (ret) +- goto err_p3; +-err_p3: +- kfree(p_names[2]); +-err_p2: +- kfree(p_names[1]); +-err_p1: +- kfree(p_names[0]); +-err_p0: ++ clk = ERR_PTR(ret); ++ ++err_clk: ++ kfree(hfpll_name); ++err_hfpll: + kfree(init.name); + return clk; + } +@@ -241,11 +248,10 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, + /* id < 0 for L2, otherwise id == physical CPU number */ + static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) + { +- int ret; + unsigned int offset; + void *p = NULL; + const char *s; +- struct clk *clk; ++ struct clk *hfpll_div, *sec_mux, *clk; + + if (id >= 0) { + offset = 0x4501 + (0x1000 * id); +@@ -257,19 +263,19 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) + s = "_l2"; + } + +- ret = krait_add_div(dev, id, s, offset); +- if (ret) { +- clk = ERR_PTR(ret); ++ hfpll_div = krait_add_div(dev, id, s, offset); ++ if (IS_ERR(hfpll_div)) { ++ clk = hfpll_div; + goto err; + } + +- ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); +- if (ret) { +- clk = ERR_PTR(ret); ++ sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); ++ if (IS_ERR(sec_mux)) { ++ clk = sec_mux; + goto err; + } + +- clk = krait_add_pri_mux(dev, id, s, offset); ++ clk = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); + err: + kfree(p); + return clk; +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-5.15/121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch new file mode 100644 index 0000000000..a8bf748258 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-03-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch @@ -0,0 +1,52 @@ +From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 02:19:28 +0200 +Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS + +qsb fixed clk may be defined in DTS and correctly passed in the clocks +list. Add related code to handle this and modify the logic to +dynamically read qsb clock frequency. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index 84f0048961f5..f1d64b16cac3 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -305,7 +305,7 @@ static int krait_cc_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; + const struct of_device_id *id; +- unsigned long cur_rate, aux_rate; ++ unsigned long cur_rate, aux_rate, qsb_rate; + int cpu; + struct clk *clk; + struct clk **clks; +@@ -315,11 +315,19 @@ static int krait_cc_probe(struct platform_device *pdev) + if (!id) + return -ENODEV; + +- /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ +- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); ++ /* ++ * Per Documentation qsb should be provided from DTS. ++ * To address old implementation, register the fixed clock anyway. ++ * Rate is 1 because 0 causes problems for __clk_mux_determine_rate ++ */ ++ clk = clk_get(dev, "qsb"); ++ if (IS_ERR(clk)) ++ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ++ qsb_rate = clk_get_rate(clk); ++ + if (!id->data) { + clk = clk_register_fixed_factor(dev, "acpu_aux", + "gpll0_vote", 0, 1, 2); +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-5.15/121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch new file mode 100644 index 0000000000..cf0c7e5071 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-04-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch @@ -0,0 +1,59 @@ +From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 02:24:33 +0200 +Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock + +With some tools it was discovered the real frequency of the qsb fixed +clock. While not 100% correct it's still better than using 1 as a dummy +frequency. +Correctly register the qsb fixed clock with the frequency of 225 MHz +instead of 1. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index f1d64b16cac3..e91275663973 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -15,6 +15,8 @@ + + #include "clk-krait.h" + ++#define QSB_RATE 2250000000 ++ + static unsigned int sec_mux_map[] = { + 2, + 0, +@@ -322,7 +324,7 @@ static int krait_cc_probe(struct platform_device *pdev) + */ + clk = clk_get(dev, "qsb"); + if (IS_ERR(clk)) +- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); ++ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE); + if (IS_ERR(clk)) + return PTR_ERR(clk); + +@@ -378,7 +380,7 @@ static int krait_cc_probe(struct platform_device *pdev) + */ + cur_rate = clk_get_rate(l2_pri_mux_clk); + aux_rate = 384000000; +- if (cur_rate == 1) { ++ if (cur_rate == qsb_rate) { + pr_info("L2 @ QSB rate. Forcing new rate.\n"); + cur_rate = aux_rate; + } +@@ -389,7 +391,7 @@ static int krait_cc_probe(struct platform_device *pdev) + for_each_possible_cpu(cpu) { + clk = clks[cpu]; + cur_rate = clk_get_rate(clk); +- if (cur_rate == 1) { ++ if (cur_rate == qsb_rate) { + pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); + cur_rate = aux_rate; + } +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch b/target/linux/ipq806x/patches-5.15/121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch new file mode 100644 index 0000000000..a624443fbb --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-05-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch @@ -0,0 +1,30 @@ +From ff65b60fa89be06ba68e3e22702dd71700afb6a5 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 02:34:58 +0200 +Subject: [PATCH 5/9] clk: qcom: krait-cc: use devm variant for clk notifier + register + +Use devm variant for clk notifier register and correctly handle free +resource on driver remove. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index e91275663973..33a78b7de0bd 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -64,7 +64,7 @@ static int krait_notifier_register(struct device *dev, struct clk *clk, + int ret = 0; + + mux->clk_nb.notifier_call = krait_notifier_cb; +- ret = clk_notifier_register(clk, &mux->clk_nb); ++ ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb); + if (ret) + dev_err(dev, "failed to register clock notifier: %d\n", ret); + +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch b/target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch new file mode 100644 index 0000000000..bac7db9d54 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-06-clk-qcom-krait-cc-fix-never-enabled-secondary-mux.patch @@ -0,0 +1,52 @@ +From a0f6d7abe7f5da1a9b435eed89acace7cde4add6 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 02:39:11 +0200 +Subject: [PATCH 6/9] clk: qcom: krait-cc: fix never enabled secondary mux + +While never actually used as a pure mux, the secondary mux is used as a +safe selection for the primary mux to switch while the hfpll are +reprogrammed. +The secondary muxes were never enabled and this cause the krait-clk +drivers to silently ignore any set parent request without any error. +Enable the secondary mux to actually apply the parent and apply the +requested frequency. + +Fixes: bb5c4a85051e ("clk: qcom: Add Krait clock controller driver") +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index 33a78b7de0bd..b71067a49ee7 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -121,7 +121,7 @@ static struct clk * + krait_add_sec_mux(struct device *dev, int id, const char *s, + unsigned int offset, bool unique_aux) + { +- int ret; ++ int ret, cpu; + struct krait_mux_clk *mux; + static struct clk_parent_data sec_mux_list[2] = { + { .name = "qsb", .fw_name = "qsb" }, +@@ -180,6 +180,16 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, + if (ret) + clk = ERR_PTR(ret); + ++ /* The secondary mux MUST be enabled or clk-krait silently ++ * ignore any request. ++ * Increase refcount for every CPU if it's the L2 secondary mux. ++ */ ++ if (id < 0) ++ for_each_possible_cpu(cpu) ++ clk_prepare_enable(clk); ++ else ++ clk_prepare_enable(clk); ++ + err_clk: + if (unique_aux) + kfree(parent_name); +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-5.15/121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch new file mode 100644 index 0000000000..cd2b2d771f --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-07-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch @@ -0,0 +1,49 @@ +From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 18 Mar 2022 16:12:14 +0100 +Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info + +Replace pr_info() with dev_info() to provide better diagnostics. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index b71067a49ee7..e4fb3ff2b5b5 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -391,25 +391,25 @@ static int krait_cc_probe(struct platform_device *pdev) + cur_rate = clk_get_rate(l2_pri_mux_clk); + aux_rate = 384000000; + if (cur_rate == qsb_rate) { +- pr_info("L2 @ QSB rate. Forcing new rate.\n"); ++ dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); + cur_rate = aux_rate; + } + clk_set_rate(l2_pri_mux_clk, aux_rate); + clk_set_rate(l2_pri_mux_clk, 2); + clk_set_rate(l2_pri_mux_clk, cur_rate); +- pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); ++ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); + for_each_possible_cpu(cpu) { + clk = clks[cpu]; + cur_rate = clk_get_rate(clk); + if (cur_rate == qsb_rate) { +- pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); ++ dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); + cur_rate = aux_rate; + } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); + clk_set_rate(clk, cur_rate); +- pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); ++ dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); + } + + of_clk_add_provider(dev->of_node, krait_of_get, clks); +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch new file mode 100644 index 0000000000..9e7081b40e --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-08-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch @@ -0,0 +1,75 @@ +From b6655ca513b3f1b40417287ab7f706409455fe48 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 02:56:47 +0200 +Subject: [PATCH 8/9] clk: qcom: krait-cc: handle secondary mux sourcing out of + PXO + +The secondary mux can sourc out of PXO as the secondary MUX is attached +to QSB and to another mux that can source out of PXO or PLL8_VOTE. + +Many device may run with uncorrect configuration with the mux sourcing +out of PXO instead of PLL8_VOTE. + +To handle this case we add also PXO as required clocks and we check if +the frequency is currently set to PXO and force a correct rate if it's +the case. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 19 ++++++++++++++++++- + 1 file changed, 18 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index e4fb3ff2b5b5..717eff44b6a4 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -317,7 +317,7 @@ static int krait_cc_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; + const struct of_device_id *id; +- unsigned long cur_rate, aux_rate, qsb_rate; ++ unsigned long cur_rate, aux_rate, qsb_rate, pxo_rate; + int cpu; + struct clk *clk; + struct clk **clks; +@@ -327,6 +327,15 @@ static int krait_cc_probe(struct platform_device *pdev) + if (!id) + return -ENODEV; + ++ clk = clk_get(dev, "pxo"); ++ if (IS_ERR(clk)) ++ clk = __clk_lookup("pxo_board"); ++ ++ if (IS_ERR_OR_NULL(clk)) ++ return clk == NULL ? -ENODEV : PTR_ERR(clk); ++ ++ pxo_rate = clk_get_rate(clk); ++ + /* + * Per Documentation qsb should be provided from DTS. + * To address old implementation, register the fixed clock anyway. +@@ -394,6 +403,10 @@ static int krait_cc_probe(struct platform_device *pdev) + dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); + cur_rate = aux_rate; + } ++ if (cur_rate == pxo_rate) { ++ dev_info(dev, "L2 @ PXO rate. Forcing new rate.\n"); ++ cur_rate = aux_rate; ++ } + clk_set_rate(l2_pri_mux_clk, aux_rate); + clk_set_rate(l2_pri_mux_clk, 2); + clk_set_rate(l2_pri_mux_clk, cur_rate); +@@ -405,6 +418,10 @@ static int krait_cc_probe(struct platform_device *pdev) + dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); + cur_rate = aux_rate; + } ++ if (cur_rate ==pxo_rate) { ++ dev_info(dev, "CPU%d @ PXO rate. Forcing new rate.\n", cpu); ++ cur_rate = aux_rate; ++ } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-5.15/121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch new file mode 100644 index 0000000000..fb5cb14a79 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/121-09-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch @@ -0,0 +1,102 @@ +From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 15 Sep 2022 03:33:13 +0200 +Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset + hfpll + +Rework and clean mux reset logic. +Compact it to a for loop to handle both CPU and L2 in one place. +Move hardcoded aux_rate to define and add a new hfpll_rate value to +reset hfpll settings. +Change logic to now reset the hfpll to the lowest value of 600 Mhz and +then restoring the previous frequency. This permits to reset the hfpll if +the primary mux was set to source out of the secondary mux. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++-------------------- + 1 file changed, 23 insertions(+), 27 deletions(-) + +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index 717eff44b6a4..90dee71e7c38 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -15,7 +15,9 @@ + + #include "clk-krait.h" + +-#define QSB_RATE 2250000000 ++#define QSB_RATE 225000000 ++#define AUX_RATE 384000000 ++#define HFPLL_RATE 600000000 + + static unsigned int sec_mux_map[] = { + 2, +@@ -317,7 +319,7 @@ static int krait_cc_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; + const struct of_device_id *id; +- unsigned long cur_rate, aux_rate, qsb_rate, pxo_rate; ++ unsigned long cur_rate, qsb_rate, pxo_rate; + int cpu; + struct clk *clk; + struct clk **clks; +@@ -397,36 +399,30 @@ static int krait_cc_probe(struct platform_device *pdev) + * two different rates to force a HFPLL reinit under all + * circumstances. + */ +- cur_rate = clk_get_rate(l2_pri_mux_clk); +- aux_rate = 384000000; +- if (cur_rate == qsb_rate) { +- dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); +- cur_rate = aux_rate; +- } +- if (cur_rate == pxo_rate) { +- dev_info(dev, "L2 @ PXO rate. Forcing new rate.\n"); +- cur_rate = aux_rate; +- } +- clk_set_rate(l2_pri_mux_clk, aux_rate); +- clk_set_rate(l2_pri_mux_clk, 2); +- clk_set_rate(l2_pri_mux_clk, cur_rate); +- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); +- for_each_possible_cpu(cpu) { ++ for (cpu = 0; cpu < 5; cpu++) { ++ const char *l2_s = "L2"; ++ char cpu_s[5]; ++ + clk = clks[cpu]; ++ if (!clk) ++ continue; ++ ++ if (cpu < 4) ++ snprintf(cpu_s, 5, "CPU%d", cpu); ++ + cur_rate = clk_get_rate(clk); +- if (cur_rate == qsb_rate) { +- dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); +- cur_rate = aux_rate; +- } +- if (cur_rate ==pxo_rate) { +- dev_info(dev, "CPU%d @ PXO rate. Forcing new rate.\n", cpu); +- cur_rate = aux_rate; ++ if (cur_rate == qsb_rate || cur_rate == pxo_rate) { ++ dev_info(dev, "%s @ %s rate. Forcing new rate.\n", ++ cpu < 4 ? cpu_s : l2_s, ++ cur_rate == qsb_rate ? "QSB" : "PXO"); ++ cur_rate = AUX_RATE; + } + +- clk_set_rate(clk, aux_rate); +- clk_set_rate(clk, 2); ++ clk_set_rate(clk, AUX_RATE); ++ clk_set_rate(clk, HFPLL_RATE); + clk_set_rate(clk, cur_rate); +- dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); ++ dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s, ++ clk_get_rate(clk) / 1000); + } + + of_clk_add_provider(dev->of_node, krait_of_get, clks); +-- +2.37.2 + From ecf1abe5bf0b86c0c2b6d52948f113049b9a7413 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Sep 2022 13:06:46 +0200 Subject: [PATCH 40/43] ipq806x: 5.15: enable again usb node for each device Usb node now are disabled by default in dtsi. Enable again them in each device dts. Signed-off-by: Christian Marangi --- .../arm/boot/dts/qcom-ipq8062-wg2600hp3.dts | 24 ++++++++++++++++ .../boot/dts/qcom-ipq8064-ad7200-c2600.dtsi | 16 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 16 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 16 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 16 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-db149.dts | 16 +++++++++++ .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 16 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-g10.dts | 16 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 16 +++++++++++ .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 16 +++++++++++ .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 16 +++++++++++ .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 16 +++++++++++ .../arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 28 ++++++++++++------- .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 16 +++++++++++ .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 16 +++++++++++ .../arm/boot/dts/qcom-ipq8065-nighthawk.dtsi | 16 +++++++++++ .../boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 16 +++++++++++ .../arm/boot/dts/qcom-ipq8065-tr4400-v2.dts | 8 ++++++ .../arm/boot/dts/qcom-ipq8068-ecw5410.dts | 20 ++++++------- .../arch/arm/boot/dts/qcom-ipq8068-mr42.dts | 24 ++++++++++++++++ .../arch/arm/boot/dts/qcom-ipq8068-mr52.dts | 24 ++++++++++++++++ 21 files changed, 348 insertions(+), 20 deletions(-) diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts index c3b3f6feda..c55287a4f1 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts @@ -484,3 +484,27 @@ reg = <0x12 0x6>; }; }; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi index c6a78f7fd8..dd57fc02b4 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi @@ -250,6 +250,14 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; @@ -257,6 +265,14 @@ pinctrl-names = "default"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index cf73ed6a0a..d3b7c44877 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -34,10 +34,26 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts index 926d9286a7..02ddbf3118 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-ap161.dts @@ -42,10 +42,26 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts index 719b9c86c5..b8273c614a 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-d7800.dts @@ -163,6 +163,14 @@ status = "okay"; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; @@ -170,6 +178,14 @@ pinctrl-names = "default"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts index 8e8d942fbd..f628df919b 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-db149.dts @@ -75,10 +75,26 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi index b9b296094b..adf5192ac8 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi @@ -12,10 +12,26 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts index 75b02a00d0..59d5d3ec3d 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-g10.dts @@ -314,10 +314,26 @@ pinctrl-names = "default"; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts index aa783e7ee6..7bea5b6bce 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500.dts @@ -147,10 +147,26 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts index 23a32697e1..6f0ba09c87 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts @@ -167,6 +167,14 @@ status = "okay"; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; @@ -174,6 +182,14 @@ pinctrl-names = "default"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts index 5ae1a3ec08..b0db8c8863 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts @@ -299,10 +299,26 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts index b33183d1a2..431c9cd9af 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts @@ -318,6 +318,14 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; @@ -325,6 +333,14 @@ pinctrl-names = "default"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts index 983a4243db..ee257f9d40 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts @@ -332,7 +332,11 @@ status = "disabled"; }; -&ss_phy_0 { /* USB3 port 0 SS phy */ +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { status = "okay"; rx_eq = <2>; @@ -340,7 +344,15 @@ mpll = <160>; }; -&ss_phy_1 { /* USB3 port 1 SS phy */ +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { status = "okay"; rx_eq = <2>; @@ -348,6 +360,10 @@ mpll = <160>; }; +&usb3_1 { + status = "okay"; +}; + &pcie0 { status = "okay"; @@ -452,14 +468,6 @@ }; }; -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - &tcsr { qcom,usb-ctrl-select = ; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts index c617064250..39fd81fe55 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts @@ -387,6 +387,14 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; @@ -394,6 +402,14 @@ pinctrl-names = "default"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts index c00f95f225..162b28d27f 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts @@ -194,6 +194,14 @@ }; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; @@ -201,6 +209,14 @@ pinctrl-names = "default"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi index 420b540132..2328c497ea 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi @@ -401,6 +401,14 @@ status = "okay"; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; @@ -408,6 +416,14 @@ pinctrl-names = "default"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts index 902f7d6098..10844ecca7 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts @@ -348,10 +348,26 @@ status = "okay"; }; +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + &usb3_0 { status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts index db9bab18dd..075c1f7eee 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts @@ -374,6 +374,14 @@ status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts index 574536cf55..50c1d37c29 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts @@ -191,19 +191,11 @@ }; }; -&hs_phy_0 { /* USB3 port 0 HS phy */ +&hs_phy_0 { status = "okay"; }; -&hs_phy_1 { /* USB3 port 1 HS phy */ - status = "okay"; -}; - -&ss_phy_0 { /* USB3 port 0 SS phy */ - status = "okay"; -}; - -&ss_phy_1 { /* USB3 port 1 SS phy */ +&ss_phy_0 { status = "okay"; }; @@ -211,6 +203,14 @@ status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + &usb3_1 { status = "okay"; }; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts index ccf2554ca3..cfbfafb179 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr42.dts @@ -202,3 +202,27 @@ nvmem-cell-names = "mac-address"; mac-address-increment = <3>; }; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; diff --git a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts index e1c233254d..f81e3ef690 100644 --- a/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts +++ b/target/linux/ipq806x/files-5.15/arch/arm/boot/dts/qcom-ipq8068-mr52.dts @@ -228,3 +228,27 @@ nvmem-cell-names = "mac-address"; mac-address-increment = <2>; }; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; From 8d9dfac2bd2cdee042cdeb03c9cf3f8f54b99c91 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 23 Sep 2022 19:35:35 +0200 Subject: [PATCH 41/43] ipq806x: 5.15: add clk krait fixes/improvement patch Add various krait fixes patch that correctly bringup mux and cpu clocks. Signed-off-by: Christian Marangi --- ...m-clk-krait-fix-wrong-div2-functions.patch | 33 ++++ ...m-clk-krait-generilize-div-functions.patch | 165 ++++++++++++++++++ 2 files changed, 198 insertions(+) create mode 100644 target/linux/ipq806x/patches-5.15/122-01-clk-qcom-clk-krait-fix-wrong-div2-functions.patch create mode 100644 target/linux/ipq806x/patches-5.15/122-02-clk-qcom-clk-krait-generilize-div-functions.patch diff --git a/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-clk-krait-fix-wrong-div2-functions.patch b/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-clk-krait-fix-wrong-div2-functions.patch new file mode 100644 index 0000000000..e299e49f3c --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/122-01-clk-qcom-clk-krait-fix-wrong-div2-functions.patch @@ -0,0 +1,33 @@ +From 2acc3260050cf17d72ec5fb7a00cd91cf53ef5b6 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 23 Sep 2022 18:42:29 +0200 +Subject: [PATCH 1/4] clk: qcom: clk-krait: fix wrong div2 functions + +Currently div2 value is applied to the wrong bits. This is caused by a +bug in the code where the shift is done only for lpl, for anything +else the mask is not shifted to the correct bits. + +Fix this by correctly shift if lpl is not supported. + +Fixes: 4d7dc77babfe ("clk: qcom: Add support for Krait clocks") +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/clk-krait.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c +index 45da736bd5f4..293a9dfa7151 100644 +--- a/drivers/clk/qcom/clk-krait.c ++++ b/drivers/clk/qcom/clk-krait.c +@@ -114,6 +114,8 @@ static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, + + if (d->lpl) + mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; ++ else ++ mask <<= d->shift; + + spin_lock_irqsave(&krait_clock_reg_lock, flags); + val = krait_get_l2_indirect_reg(d->offset); +-- +2.37.2 + diff --git a/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-clk-krait-generilize-div-functions.patch new file mode 100644 index 0000000000..def0dfe126 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/122-02-clk-qcom-clk-krait-generilize-div-functions.patch @@ -0,0 +1,165 @@ +From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Fri, 23 Sep 2022 19:05:39 +0200 +Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions + +Generilize div functions and remove hardcode to a divisor of 2. +This is just a cleanup and permit to make it more clear the settings of +the devisor when used by the krait-cc driver. + +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++---------------- + drivers/clk/qcom/clk-krait.h | 11 ++++--- + drivers/clk/qcom/krait-cc.c | 7 +++-- + 3 files changed, 42 insertions(+), 33 deletions(-) + +diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c +index 293a9dfa7151..1d40dd1acb0f 100644 +--- a/drivers/clk/qcom/clk-krait.c ++++ b/drivers/clk/qcom/clk-krait.c +@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops = { + EXPORT_SYMBOL_GPL(krait_mux_clk_ops); + + /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ +-static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, ++static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) + { +- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); +- return DIV_ROUND_UP(*parent_rate, 2); ++ struct krait_div_clk *d = to_krait_div_clk(hw); ++ ++ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), ++ rate * d->divisor); ++ ++ return DIV_ROUND_UP(*parent_rate, d->divisor); + } + +-static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, ++static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { +- struct krait_div2_clk *d = to_krait_div2_clk(hw); ++ struct krait_div_clk *d = to_krait_div_clk(hw); ++ u8 div_val = krait_div_to_val(d->divisor); + unsigned long flags; +- u32 val; +- u32 mask = BIT(d->width) - 1; +- +- if (d->lpl) +- mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; +- else +- mask <<= d->shift; ++ u32 regval; + + spin_lock_irqsave(&krait_clock_reg_lock, flags); +- val = krait_get_l2_indirect_reg(d->offset); +- val &= ~mask; +- krait_set_l2_indirect_reg(d->offset, val); ++ regval = krait_get_l2_indirect_reg(d->offset); ++ ++ regval &= ~(d->mask << d->shift); ++ regval |= (div_val & d->mask) << d->shift; ++ ++ if (d->lpl) { ++ regval &= ~(d->mask << (d->shift + LPL_SHIFT)); ++ regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT); ++ } ++ ++ krait_set_l2_indirect_reg(d->offset, regval); + spin_unlock_irqrestore(&krait_clock_reg_lock, flags); + + return 0; + } + + static unsigned long +-krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) + { +- struct krait_div2_clk *d = to_krait_div2_clk(hw); +- u32 mask = BIT(d->width) - 1; ++ struct krait_div_clk *d = to_krait_div_clk(hw); + u32 div; + + div = krait_get_l2_indirect_reg(d->offset); + div >>= d->shift; +- div &= mask; +- div = (div + 1) * 2; ++ div &= d->mask; + +- return DIV_ROUND_UP(parent_rate, div); ++ return DIV_ROUND_UP(parent_rate, krait_val_to_div(div)); + } + +-const struct clk_ops krait_div2_clk_ops = { +- .round_rate = krait_div2_round_rate, +- .set_rate = krait_div2_set_rate, +- .recalc_rate = krait_div2_recalc_rate, ++const struct clk_ops krait_div_clk_ops = { ++ .round_rate = krait_div_round_rate, ++ .set_rate = krait_div_set_rate, ++ .recalc_rate = krait_div_recalc_rate, + }; +-EXPORT_SYMBOL_GPL(krait_div2_clk_ops); ++EXPORT_SYMBOL_GPL(krait_div_clk_ops); +diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h +index f930538c539e..94c798f8e834 100644 +--- a/drivers/clk/qcom/clk-krait.h ++++ b/drivers/clk/qcom/clk-krait.h +@@ -25,17 +25,20 @@ struct krait_mux_clk { + + extern const struct clk_ops krait_mux_clk_ops; + +-struct krait_div2_clk { ++struct krait_div_clk { + u32 offset; +- u8 width; ++ u32 mask; ++ u8 divisor; + u32 shift; + bool lpl; + + struct clk_hw hw; + }; + +-#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) ++#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw) ++#define krait_div_to_val(_div) ((_div) / 2) - 1 ++#define krait_val_to_div(_val) ((_val) + 1) * 2 + +-extern const struct clk_ops krait_div2_clk_ops; ++extern const struct clk_ops krait_div_clk_ops; + + #endif +diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c +index 90dee71e7c38..949657186fdb 100644 +--- a/drivers/clk/qcom/krait-cc.c ++++ b/drivers/clk/qcom/krait-cc.c +@@ -76,11 +76,11 @@ static int krait_notifier_register(struct device *dev, struct clk *clk, + static struct clk * + krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) + { +- struct krait_div2_clk *div; ++ struct krait_div_clk *div; + static struct clk_parent_data p_data[1]; + struct clk_init_data init = { + .num_parents = ARRAY_SIZE(p_data), +- .ops = &krait_div2_clk_ops, ++ .ops = &krait_div_clk_ops, + .flags = CLK_SET_RATE_PARENT, + }; + struct clk *clk; +@@ -90,7 +90,8 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) + if (!div) + return ERR_PTR(-ENOMEM); + +- div->width = 2; ++ div->mask = 0x3; ++ div->divisor = 2; + div->shift = 6; + div->lpl = id >= 0; + div->offset = offset; +-- +2.37.2 + From bb451eccaa51bb7d57fd837ef586a8a0d1ab91b1 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 19 Sep 2022 13:25:34 +0200 Subject: [PATCH 42/43] ipq806x: switch to 5.15 kernel by default Switch to 5.15 kernel by default to promote more wider testing and use better upstream patch. Signed-off-by: Christian Marangi --- target/linux/ipq806x/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/ipq806x/Makefile b/target/linux/ipq806x/Makefile index 665a830e34..862ad7da00 100644 --- a/target/linux/ipq806x/Makefile +++ b/target/linux/ipq806x/Makefile @@ -10,8 +10,7 @@ CPU_TYPE:=cortex-a15 CPU_SUBTYPE:=neon-vfpv4 SUBTARGETS:=generic -KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.15 +KERNEL_PATCHVER:=5.15 KERNELNAME:=zImage Image dtbs From cd93980abb0c6452fd3e9c1213caaf26d221fcd4 Mon Sep 17 00:00:00 2001 From: Giammarco Marzano Date: Mon, 10 Oct 2022 12:15:19 +0200 Subject: [PATCH 43/43] ipq40xx: Fix wrong GPIO for internal status LED on ZTE MF289F Change GPIO from 10 to 35 to make it works as expected Fixes: 0de6a3339f1a ("ipq40xx: Add ZTE MF289F") Signed-off-by: Giammarco Marzano Reviewed-by: Robert Marko --- .../ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts index ccb70dce87..0d9f24ad70 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts @@ -43,7 +43,7 @@ label = "blue:power"; function = LED_FUNCTION_POWER; color = ; - gpios = <&tlmm 10 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; }; led-1 {