ipq40xx: 5.10: apply our own patches

This commit is contained in:
AmadeusGhost 2022-02-06 12:20:06 +08:00
parent f4d0d04a72
commit b8fde8c7b8
3 changed files with 107 additions and 1 deletions

View File

@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -902,11 +902,61 @@ dtb-$(CONFIG_ARCH_QCOM) += \
@@ -902,11 +902,68 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
@ -27,6 +27,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
+ qcom-ipq4018-ens620ext.dtb \
+ qcom-ipq4018-ex6100v2.dtb \
+ qcom-ipq4018-ex6150v2.dtb \
+ qcom-ipq4018-ex6200v2.dtb \
+ qcom-ipq4018-fritzbox-4040.dtb \
+ qcom-ipq4018-gl-ap1300.dtb \
+ qcom-ipq4018-jalapeno.dtb \
@ -46,6 +47,8 @@ Signed-off-by: John Crispin <john@phrozen.org>
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
+ qcom-ipq4019-a62.dtb \
+ qcom-ipq4019-c526a.dtb \
+ qcom-ipq4019-c526a-128m.dtb \
+ qcom-ipq4019-cm520-79f.dtb \
+ qcom-ipq4019-ea8300.dtb \
+ qcom-ipq4019-eap2200.dtb \
@ -58,9 +61,13 @@ Signed-off-by: John Crispin <john@phrozen.org>
+ qcom-ipq4019-e2600ac-c2.dtb \
+ qcom-ipq4019-habanero-dvk.dtb \
+ qcom-ipq4019-pa2200.dtb \
+ qcom-ipq4019-r619ac.dtb \
+ qcom-ipq4019-rtl30vw.dtb \
+ qcom-ipq4019-rt-acrh17.dtb \
+ qcom-ipq4019-u4019-32m.dtb \
+ qcom-ipq4019-wpj419.dtb \
+ qcom-ipq4019-wr142ac.dtb \
+ qcom-ipq4019-wr142ac-nand.dtb \
+ qcom-ipq4019-wtr-m2133hp.dtb \
+ qcom-ipq4028-wpj428.dtb \
+ qcom-ipq4029-ap-303.dtb \

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@ -0,0 +1,45 @@
From 42b508d91b7f51b054f383e3aa42089ccab9300d Mon Sep 17 00:00:00 2001
From: Chen Minqiang <ptpt52@gmail.com>
Date: Thu, 15 Mar 2018 05:33:46 +0800
Subject: [PATCH] essedma: disable default vlan tagging
The essedma driver has its own unique take on VLAN management
and its configuration. In the original SDK, each VLAN is
assigned one virtual ethernet netdev.
However, this is non-standard. So, this patch does away
with the default_vlan_tag property the driver is using
and therefore forces the user to use the kernel's vlan
feature.
This patch also removes the "qcom,poll_required = <1>;" from
the essedma node.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 ++---
drivers/net/ethernet/qualcomm/essedma/edma.c | 14 +++++---------
2 files changed, 7 insertions(+), 12 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -665,8 +665,7 @@
qcom,page-mode = <0>;
qcom,rx_head_buf_size = <1540>;
qcom,mdio_supported;
- qcom,poll_required = <1>;
- qcom,num_gmac = <2>;
+ qcom,num_gmac = <1>;
interrupts = <0 65 IRQ_TYPE_EDGE_RISING
0 66 IRQ_TYPE_EDGE_RISING
0 67 IRQ_TYPE_EDGE_RISING
@@ -704,7 +703,7 @@
gmac0: gmac0 {
local-mac-address = [00 00 00 00 00 00];
- vlan_tag = <1 0x1f>;
+ vlan_tag = <1 0x3f>;
};
gmac1: gmac1 {

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@ -0,0 +1,54 @@
From: William <gw826943555@qq.com>
Subject: [PATCH] ipq40xx: improve CPU clock
Date: Tue, 15 Dec 2020 15:26:35 +0800
This patch will match the clock-latency-ns values in the device tree
for those found inside the OEM device tree and kernel source code and
unlock 896Mhz CPU operating points.
Signed-off-by: William <gw826943555@qq.com>
---
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -115,20 +115,24 @@
opp-48000000 {
opp-hz = /bits/ 64 <48000000>;
- clock-latency-ns = <256000>;
+ clock-latency-ns = <100000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
- clock-latency-ns = <256000>;
+ clock-latency-ns = <100000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- clock-latency-ns = <256000>;
+ clock-latency-ns = <100000>;
};
opp-716000000 {
opp-hz = /bits/ 64 <716000000>;
- clock-latency-ns = <256000>;
+ clock-latency-ns = <100000>;
};
+ opp-896000000 {
+ opp-hz = /bits/ 64 <896000000>;
+ clock-latency-ns = <100000>;
+ };
};
memory {
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -579,6 +579,9 @@ static const struct freq_tbl ftbl_gcc_ap
F(632000000, P_DDRPLLAPSS, 1, 0, 0),
F(672000000, P_DDRPLLAPSS, 1, 0, 0),
F(716000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(768000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(823000000, P_DDRPLLAPSS, 1, 0, 0),
+ F(896000000, P_DDRPLLAPSS, 1, 0, 0),
{ }
};