From bb19c0e1d8410920347836d90c24a4a545266a27 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Tue, 4 Apr 2023 01:51:27 +0800 Subject: [PATCH] rockchip: add Firefly ROC-RK3328-CC support Hardware -------- RockChip RK3328 ARM64 (4 cores) 4GB DDR4 RAM 1x 1000 Base-T 2 LEDs (POWER / USER) HDMI 2.0 3.5mm TRRS AV jack Micro-SD slot eMMC slot 1x USB 3.0 Port 2x USB 2.0 Port Signed-off-by: Tianling Shen (cherry picked from commit f05de856379977e0f48f9fcd27ec199c1bf5aa74) --- target/linux/rockchip/armv8/config-5.4 | 6 +- .../rockchip/rk3328-dram-renegade-timing.dtsi | 311 ++++++++++++++++++ target/linux/rockchip/image/armv8.mk | 9 + ...kchip-fix-sdmmc-detection-on-boot-on.patch | 28 ++ ...Enable-USB3-for-rk3328-ROC-RK3328-CC.patch | 36 ++ ...-rockchip-use-system-LED-for-OpenWrt.patch | 29 ++ .../107-nanopi-r4s-sd-signalling.patch | 10 + ...anopi-r2s-add-rk3328-dmc-relate-node.patch | 110 +++++++ 8 files changed, 537 insertions(+), 2 deletions(-) create mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi create mode 100644 target/linux/rockchip/patches-5.4/011-v5.5-arm64-dts-rockchip-fix-sdmmc-detection-on-boot-on.patch create mode 100644 target/linux/rockchip/patches-5.4/012-v5.14-arm64-dts-rockchip-Enable-USB3-for-rk3328-ROC-RK3328-CC.patch diff --git a/target/linux/rockchip/armv8/config-5.4 b/target/linux/rockchip/armv8/config-5.4 index 9053164809..41d4025fbe 100644 --- a/target/linux/rockchip/armv8/config-5.4 +++ b/target/linux/rockchip/armv8/config-5.4 @@ -175,6 +175,7 @@ CONFIG_GPIOLIB=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_SYSCON=y # CONFIG_HARDENED_USERCOPY is not set CONFIG_HAS_IOPORT_MAP=y CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y @@ -214,7 +215,7 @@ CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_MATRIXKMAP=y # CONFIG_INPUT_MISC is not set -# CONFIG_INPUT_RK805_PWRKEY is not set +CONFIG_INPUT_RK805_PWRKEY=y CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set @@ -242,6 +243,7 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 @@ -338,7 +340,7 @@ CONFIG_PHY_ROCKCHIP_PCIE=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y CONFIG_PINCTRL=y -# CONFIG_PINCTRL_RK805 is not set +CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_ROCKCHIP=y # CONFIG_PINCTRL_SINGLE is not set CONFIG_PL330_DMA=y diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi new file mode 100644 index 0000000000..3034281530 --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr3_speed_bin = ; + ddr4_speed_bin = ; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + + auto_pd_dis_freq = <1066>; + auto_sr_dis_freq = <800>; + ddr3_dll_dis_freq = <300>; + ddr4_dll_dis_freq = <625>; + phy_dll_dis_freq = <400>; + + ddr3_odt_dis_freq = <100>; + phy_ddr3_odt_dis_freq = <100>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + lpddr3_odt_dis_freq = <666>; + phy_lpddr3_odt_dis_freq = <666>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + phy_lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + + ddr4_odt_dis_freq = <666>; + phy_ddr4_odt_dis_freq = <666>; + ddr4_drv = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; + + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <0>; + ddr3a0_ddr4a10_de-skew = <0>; + ddr3a3_ddr4a6_de-skew = <1>; + ddr3a2_ddr4a4_de-skew = <1>; + ddr3a5_ddr4a8_de-skew = <0>; + ddr3a4_ddr4a5_de-skew = <2>; + ddr3a7_ddr4a11_de-skew = <0>; + ddr3a6_ddr4a7_de-skew = <2>; + ddr3a9_ddr4a0_de-skew = <1>; + ddr3a8_ddr4a13_de-skew = <0>; + ddr3a11_ddr4a3_de-skew = <2>; + ddr3a10_ddr4cs0_de-skew = <0>; + ddr3a13_ddr4a2_de-skew = <1>; + ddr3a12_ddr4ba1_de-skew = <0>; + ddr3a15_ddr4odt0_de-skew = <0>; + ddr3a14_ddr4a1_de-skew = <1>; + ddr3ba1_ddr4a15_de-skew = <0>; + ddr3ba0_ddr4bg0_de-skew = <0>; + ddr3ras_ddr4cke_de-skew = <0>; + ddr3ba2_ddr4ba0_de-skew = <1>; + ddr3we_ddr4bg1_de-skew = <1>; + ddr3cas_ddr4a12_de-skew = <0>; + ddr3ckn_ddr4ckn_de-skew = <5>; + ddr3ckp_ddr4ckp_de-skew = <5>; + ddr3cke_ddr4a16_de-skew = <1>; + ddr3odt0_ddr4a14_de-skew = <0>; + ddr3cs0_ddr4act_de-skew = <1>; + ddr3reset_ddr4reset_de-skew = <0>; + ddr3cs1_ddr4cs1_de-skew = <0>; + ddr3odt1_ddr4odt1_de-skew = <0>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <8>; + cs0_dq0_rx_de-skew = <7>; + cs0_dq0_tx_de-skew = <8>; + cs0_dq1_rx_de-skew = <7>; + cs0_dq1_tx_de-skew = <8>; + cs0_dq2_rx_de-skew = <7>; + cs0_dq2_tx_de-skew = <8>; + cs0_dq3_rx_de-skew = <7>; + cs0_dq3_tx_de-skew = <8>; + cs0_dq4_rx_de-skew = <7>; + cs0_dq4_tx_de-skew = <8>; + cs0_dq5_rx_de-skew = <7>; + cs0_dq5_tx_de-skew = <8>; + cs0_dq6_rx_de-skew = <7>; + cs0_dq6_tx_de-skew = <8>; + cs0_dq7_rx_de-skew = <7>; + cs0_dq7_tx_de-skew = <8>; + cs0_dqs0_rx_de-skew = <6>; + cs0_dqs0p_tx_de-skew = <9>; + cs0_dqs0n_tx_de-skew = <9>; + + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <7>; + cs0_dq8_rx_de-skew = <7>; + cs0_dq8_tx_de-skew = <8>; + cs0_dq9_rx_de-skew = <7>; + cs0_dq9_tx_de-skew = <7>; + cs0_dq10_rx_de-skew = <7>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <7>; + cs0_dq11_tx_de-skew = <7>; + cs0_dq12_rx_de-skew = <7>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <7>; + cs0_dq13_tx_de-skew = <7>; + cs0_dq14_rx_de-skew = <7>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <7>; + cs0_dq15_tx_de-skew = <7>; + cs0_dqs1_rx_de-skew = <7>; + cs0_dqs1p_tx_de-skew = <9>; + cs0_dqs1n_tx_de-skew = <9>; + + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <8>; + cs0_dq16_rx_de-skew = <7>; + cs0_dq16_tx_de-skew = <8>; + cs0_dq17_rx_de-skew = <7>; + cs0_dq17_tx_de-skew = <8>; + cs0_dq18_rx_de-skew = <7>; + cs0_dq18_tx_de-skew = <8>; + cs0_dq19_rx_de-skew = <7>; + cs0_dq19_tx_de-skew = <8>; + cs0_dq20_rx_de-skew = <7>; + cs0_dq20_tx_de-skew = <8>; + cs0_dq21_rx_de-skew = <7>; + cs0_dq21_tx_de-skew = <8>; + cs0_dq22_rx_de-skew = <7>; + cs0_dq22_tx_de-skew = <8>; + cs0_dq23_rx_de-skew = <7>; + cs0_dq23_tx_de-skew = <8>; + cs0_dqs2_rx_de-skew = <6>; + cs0_dqs2p_tx_de-skew = <9>; + cs0_dqs2n_tx_de-skew = <9>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <7>; + cs0_dq24_tx_de-skew = <8>; + cs0_dq25_rx_de-skew = <7>; + cs0_dq25_tx_de-skew = <7>; + cs0_dq26_rx_de-skew = <7>; + cs0_dq26_tx_de-skew = <7>; + cs0_dq27_rx_de-skew = <7>; + cs0_dq27_tx_de-skew = <7>; + cs0_dq28_rx_de-skew = <7>; + cs0_dq28_tx_de-skew = <7>; + cs0_dq29_rx_de-skew = <7>; + cs0_dq29_tx_de-skew = <7>; + cs0_dq30_rx_de-skew = <7>; + cs0_dq30_tx_de-skew = <7>; + cs0_dq31_rx_de-skew = <7>; + cs0_dq31_tx_de-skew = <7>; + cs0_dqs3_rx_de-skew = <7>; + cs0_dqs3p_tx_de-skew = <9>; + cs0_dqs3n_tx_de-skew = <9>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <8>; + cs1_dq0_rx_de-skew = <7>; + cs1_dq0_tx_de-skew = <8>; + cs1_dq1_rx_de-skew = <7>; + cs1_dq1_tx_de-skew = <8>; + cs1_dq2_rx_de-skew = <7>; + cs1_dq2_tx_de-skew = <8>; + cs1_dq3_rx_de-skew = <7>; + cs1_dq3_tx_de-skew = <8>; + cs1_dq4_rx_de-skew = <7>; + cs1_dq4_tx_de-skew = <8>; + cs1_dq5_rx_de-skew = <7>; + cs1_dq5_tx_de-skew = <8>; + cs1_dq6_rx_de-skew = <7>; + cs1_dq6_tx_de-skew = <8>; + cs1_dq7_rx_de-skew = <7>; + cs1_dq7_tx_de-skew = <8>; + cs1_dqs0_rx_de-skew = <6>; + cs1_dqs0p_tx_de-skew = <9>; + cs1_dqs0n_tx_de-skew = <9>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <7>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <7>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <7>; + cs1_dq11_tx_de-skew = <7>; + cs1_dq12_rx_de-skew = <7>; + cs1_dq12_tx_de-skew = <8>; + cs1_dq13_rx_de-skew = <7>; + cs1_dq13_tx_de-skew = <7>; + cs1_dq14_rx_de-skew = <7>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <7>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1_rx_de-skew = <7>; + cs1_dqs1p_tx_de-skew = <9>; + cs1_dqs1n_tx_de-skew = <9>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <8>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq16_tx_de-skew = <8>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq17_tx_de-skew = <8>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <7>; + cs1_dq19_tx_de-skew = <8>; + cs1_dq20_rx_de-skew = <7>; + cs1_dq20_tx_de-skew = <8>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq21_tx_de-skew = <8>; + cs1_dq22_rx_de-skew = <7>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <7>; + cs1_dq23_tx_de-skew = <8>; + cs1_dqs2_rx_de-skew = <6>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <7>; + cs1_dq24_tx_de-skew = <8>; + cs1_dq25_rx_de-skew = <7>; + cs1_dq25_tx_de-skew = <7>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_rx_de-skew = <7>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_rx_de-skew = <7>; + cs1_dq28_tx_de-skew = <7>; + cs1_dq29_rx_de-skew = <7>; + cs1_dq29_tx_de-skew = <7>; + cs1_dq30_rx_de-skew = <7>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_rx_de-skew = <7>; + cs1_dq31_tx_de-skew = <7>; + cs1_dqs3_rx_de-skew = <7>; + cs1_dqs3p_tx_de-skew = <9>; + cs1_dqs3n_tx_de-skew = <9>; + }; +}; diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 133e41479a..29be80b4d6 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -2,6 +2,15 @@ # # Copyright (C) 2020 Tobias Maedel +define Device/firefly_roc-cc + DEVICE_VENDOR := Firefly + DEVICE_MODEL := ROC-RK3328-CC + SOC := rk3328 + UBOOT_DEVICE_NAME := roc-cc-rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata +endef +TARGET_DEVICES += firefly_roc-cc + define Device/friendlyarm_nanopi-r2c DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R2C diff --git a/target/linux/rockchip/patches-5.4/011-v5.5-arm64-dts-rockchip-fix-sdmmc-detection-on-boot-on.patch b/target/linux/rockchip/patches-5.4/011-v5.5-arm64-dts-rockchip-fix-sdmmc-detection-on-boot-on.patch new file mode 100644 index 0000000000..f1c9f640e1 --- /dev/null +++ b/target/linux/rockchip/patches-5.4/011-v5.5-arm64-dts-rockchip-fix-sdmmc-detection-on-boot-on.patch @@ -0,0 +1,28 @@ +From 75aa567803b15e679432655badf95cd30b66b930 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 16 Oct 2019 18:59:46 +0000 +Subject: [PATCH] arm64: dts: rockchip: fix sdmmc detection on boot on + rk3328-roc-cc + +With working GPIO, during init the GPIO state s reset. +This causes the sdmmc regulator to shut down, preventing detection. +Removing and replacing the card will allow it to be detected, but that should not be necessary. +Fix this by setting the regulator on at boot. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20191016185945.1962-1-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -35,6 +35,7 @@ + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; ++ regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; diff --git a/target/linux/rockchip/patches-5.4/012-v5.14-arm64-dts-rockchip-Enable-USB3-for-rk3328-ROC-RK3328-CC.patch b/target/linux/rockchip/patches-5.4/012-v5.14-arm64-dts-rockchip-Enable-USB3-for-rk3328-ROC-RK3328-CC.patch new file mode 100644 index 0000000000..65c9cd48ba --- /dev/null +++ b/target/linux/rockchip/patches-5.4/012-v5.14-arm64-dts-rockchip-Enable-USB3-for-rk3328-ROC-RK3328-CC.patch @@ -0,0 +1,36 @@ +From 75f95927334dea863f16f4ecd29cc709edc3c6ad Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Tue, 4 May 2021 16:36:14 +0800 +Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 ROC-RK3328-CC + +Enable USB3 nodes for the ROC-RK3328-CC board. + +The separate power regulator is not added as it is controlled by the +same GPIO line as the existing VBUS regulators, so it is already +enabled. Also there is no port representation to tie the regulator to. + +Signed-off-by: Chen-Yu Tsai +Link: https://lore.kernel.org/r/20210504083616.9654-3-wens@kernel.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -336,6 +336,15 @@ + status = "okay"; + }; + ++&usbdrd3 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; diff --git a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch index d0860de8c9..1021f1fd9d 100644 --- a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch +++ b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -45,3 +45,32 @@ Signed-off-by: David Bauer /delete-node/ display-subsystem; gpio-leds { +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -10,6 +10,13 @@ + model = "Firefly roc-rk3328-cc"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + ++ aliases { ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; ++ }; ++ + chosen { + stdout-path = "serial2:1500000n8"; + }; +@@ -86,11 +93,9 @@ + leds { + compatible = "gpio-leds"; + +- power { ++ power_led: power { + label = "firefly:blue:power"; +- linux,default-trigger = "heartbeat"; + gpios = <&rk805 1 GPIO_ACTIVE_LOW>; +- default-state = "on"; + }; + + user { diff --git a/target/linux/rockchip/patches-5.4/107-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-5.4/107-nanopi-r4s-sd-signalling.patch index 6bebe5f258..76da575450 100644 --- a/target/linux/rockchip/patches-5.4/107-nanopi-r4s-sd-signalling.patch +++ b/target/linux/rockchip/patches-5.4/107-nanopi-r4s-sd-signalling.patch @@ -10,6 +10,16 @@ userspace or following a kernel panic is always working. Signed-off-by: David Bauer +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -310,7 +310,6 @@ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; +- sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts @@ -141,6 +141,11 @@ diff --git a/target/linux/rockchip/patches-5.4/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.4/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch index 091e295978..f2079d6513 100644 --- a/target/linux/rockchip/patches-5.4/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch +++ b/target/linux/rockchip/patches-5.4/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch @@ -124,3 +124,113 @@ Signed-off-by: hmz007 regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-ramp-delay = <12500>; +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -4,6 +4,7 @@ + */ + + /dts-v1/; ++#include "rk3328-dram-renegade-timing.dtsi" + #include "rk3328.dtsi" + + / { +@@ -105,6 +106,72 @@ + default-state = "off"; + }; + }; ++ ++ dmc: dmc { ++ compatible = "rockchip,rk3328-dmc"; ++ devfreq-events = <&dfi>; ++ center-supply = <&vdd_logic>; ++ clocks = <&cru SCLK_DDRCLK>; ++ clock-names = "dmc_clk"; ++ operating-points-v2 = <&dmc_opp_table>; ++ ddr_timing = <&ddr_timing>; ++ upthreshold = <40>; ++ downdifferential = <20>; ++ auto-min-freq = <786000>; ++ auto-freq-en = <0>; ++ #cooling-cells = <2>; ++ status = "okay"; ++ ++ ddr_power_model: ddr_power_model { ++ compatible = "ddr_power_model"; ++ dynamic-power-coefficient = <120>; ++ static-power-coefficient = <200>; ++ ts = <32000 4700 (-80) 2>; ++ thermal-zone = "soc-thermal"; ++ }; ++ }; ++ ++ dmc_opp_table: dmc-opp-table { ++ compatible = "operating-points-v2"; ++ ++ rockchip,leakage-voltage-sel = < ++ 1 10 0 ++ 11 254 1 ++ >; ++ nvmem-cells = <&logic_leakage>; ++ nvmem-cell-names = "ddr_leakage"; ++ ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <12000000>; ++ }; ++ opp-798000000 { ++ opp-hz = /bits/ 64 <798000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <12000000>; ++ }; ++ opp-840000000 { ++ opp-hz = /bits/ 64 <840000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <12000000>; ++ }; ++ opp-924000000 { ++ opp-hz = /bits/ 64 <924000000>; ++ opp-microvolt = <1100000>; ++ opp-microvolt-L0 = <1100000>; ++ opp-microvolt-L1 = <12000000>; ++ }; ++ opp-1068000000 { ++ opp-hz = /bits/ 64 <1068000000>; ++ opp-microvolt = <1175000>; ++ opp-microvolt-L0 = <1175000>; ++ opp-microvolt-L1 = <12000000>; ++ }; ++ }; + }; + + &cpu0 { +@@ -123,6 +190,10 @@ + cpu-supply = <&vdd_arm>; + }; + ++&dfi { ++ status = "okay"; ++}; ++ + &emmc { + bus-width = <8>; + cap-mmc-highspeed; +@@ -191,6 +262,7 @@ + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; ++ regulator-init-microvolt = <1075000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; +@@ -203,6 +275,7 @@ + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; ++ regulator-init-microvolt = <1225000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on;