From bb521879e1b78b8f061587aec055d7a2315d1311 Mon Sep 17 00:00:00 2001 From: Jayantajit Gogoi Date: Mon, 4 May 2020 13:21:44 +0000 Subject: [PATCH] sunxi: add support for NanoPi R1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specification: -CPU: Allwinner H3, Quad-core Cortex-A7 Up to 1.2GHz -DDR3 RAM: 512MB/1GB -Network: 10/100/1000M Ethernet x 1， 10/100M Ethernet x 1 -WiFi: 802.11b/g/n, with SMA antenna interface -Bluetooth：4.0 dual mode -USB Host: Type-A x2 -MicroSD Slot x 1 -MicroUSB: for OTG and power input -Debug Serial Port: 3Pin 2.54mm pitch pin-header -UART: 4Pin 2.54mm pitch pin-header -LED: nanopi:red:pwr nanopi:green:wan nanopi:green:lan -KEY: reset -Power Supply: DC 5V/2A Installation: -Burn the image to and SD Card -Boot NanoPi from the SD Card Signed-off-by: Jayantajit Gogoi --- package/boot/uboot-sunxi/Makefile | 7 + ...-sun8i-h3-Nano-Pi-R1-add-device-tree.patch | 78 +++++++ .../251-sun8i-h3-Nano-Pi-R1-defconfig.patch | 25 +++ .../sunxi/base-files/etc/board.d/02_network | 3 + target/linux/sunxi/image/cortexa7.mk | 10 + ...dts-sun8i-add-support-for-Nano-Pi-R1.patch | 195 ++++++++++++++++++ 6 files changed, 318 insertions(+) create mode 100644 package/boot/uboot-sunxi/patches/250-sun8i-h3-Nano-Pi-R1-add-device-tree.patch create mode 100644 package/boot/uboot-sunxi/patches/251-sun8i-h3-Nano-Pi-R1-defconfig.patch create mode 100644 target/linux/sunxi/patches-5.4/062-ARM-dts-sun8i-add-support-for-Nano-Pi-R1.patch diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index ac2f9de888..9b29e42a5b 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -166,6 +166,12 @@ define U-Boot/nanopi_neo BUILD_DEVICES:=friendlyarm_nanopi-neo endef +define U-Boot/nanopi_r1 + BUILD_SUBTARGET:=cortexa7 + NAME:=U-Boot for NanoPi R1 (H3) + BUILD_DEVICES:=friendlyarm_nanopi-r1 +endef + define U-Boot/orangepi_r1 BUILD_SUBTARGET:=cortexa7 NAME:=Orange Pi R1 (H2+) @@ -303,6 +309,7 @@ UBOOT_TARGETS := \ nanopi_neo_air \ nanopi_neo_plus2 \ nanopi_neo2 \ + nanopi_r1 \ orangepi_zero \ orangepi_r1 \ orangepi_one \ diff --git a/package/boot/uboot-sunxi/patches/250-sun8i-h3-Nano-Pi-R1-add-device-tree.patch b/package/boot/uboot-sunxi/patches/250-sun8i-h3-Nano-Pi-R1-add-device-tree.patch new file mode 100644 index 0000000000..7c80ce910c --- /dev/null +++ b/package/boot/uboot-sunxi/patches/250-sun8i-h3-Nano-Pi-R1-add-device-tree.patch @@ -0,0 +1,78 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -531,6 +531,7 @@ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ ++ sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 Igor Pecovnik ++ */ ++ ++#include "sun8i-h3-nanopi.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R1"; ++ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&pio { ++ gmac_power_pin_nanopi: gmac_power_pin@0 { ++ pins = "PD6"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; diff --git a/package/boot/uboot-sunxi/patches/251-sun8i-h3-Nano-Pi-R1-defconfig.patch b/package/boot/uboot-sunxi/patches/251-sun8i-h3-Nano-Pi-R1-defconfig.patch new file mode 100644 index 0000000000..726262c79d --- /dev/null +++ b/package/boot/uboot-sunxi/patches/251-sun8i-h3-Nano-Pi-R1-defconfig.patch @@ -0,0 +1,25 @@ +--- /dev/null ++++ b/configs/nanopi_r1_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MACPWR="PD6" ++# CONFIG_VIDEO_DE2 is not set ++CONFIG_NR_DRAM_BANKS=1 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1" ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/target/linux/sunxi/base-files/etc/board.d/02_network b/target/linux/sunxi/base-files/etc/board.d/02_network index 5cf000cccf..08d31caadc 100755 --- a/target/linux/sunxi/base-files/etc/board.d/02_network +++ b/target/linux/sunxi/base-files/etc/board.d/02_network @@ -8,6 +8,9 @@ board_config_update case $(board_name) in +friendlyarm,nanopi-r1) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; lamobo,lamobo-r1) ucidef_add_switch "switch0" \ "4:lan:1" "0:lan:2" "1:lan:3" "2:lan:4" "3:wan" "8@eth0" diff --git a/target/linux/sunxi/image/cortexa7.mk b/target/linux/sunxi/image/cortexa7.mk index 083010ad8c..bfdf59bc9c 100644 --- a/target/linux/sunxi/image/cortexa7.mk +++ b/target/linux/sunxi/image/cortexa7.mk @@ -47,6 +47,16 @@ define Device/friendlyarm_nanopi-neo-air endef TARGET_DEVICES += friendlyarm_nanopi-neo-air +define Device/friendlyarm_nanopi-r1 + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R1 + DEVICE_PACKAGES := kmod-rtc-sunxi kmod-usb2 kmod-usb-net-rtl8152 \ + kmod-brcmfmac kmod-leds-gpio kmod-ledtrig-heartbeat wpad-basic \ + brcmfmac-firmware-43430-sdio + SOC := sun8i-h3 +endef +TARGET_DEVICES += friendlyarm_nanopi-r1 + define Device/lamobo_lamobo-r1 DEVICE_VENDOR := Lamobo DEVICE_MODEL := Lamobo R1 diff --git a/target/linux/sunxi/patches-5.4/062-ARM-dts-sun8i-add-support-for-Nano-Pi-R1.patch b/target/linux/sunxi/patches-5.4/062-ARM-dts-sun8i-add-support-for-Nano-Pi-R1.patch new file mode 100644 index 0000000000..ee265375aa --- /dev/null +++ b/target/linux/sunxi/patches-5.4/062-ARM-dts-sun8i-add-support-for-Nano-Pi-R1.patch @@ -0,0 +1,195 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -923,6 +923,7 @@ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ ++ sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts +@@ -0,0 +1,149 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 Igor Pecovnik ++ */ ++ ++#include "sun8i-h3-nanopi.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R1"; ++ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial1 = &uart3; ++ ethernet0 = &emac; ++ ethernet1 = &emac; ++ ethernet2 = &sdio_wifi; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vdd_cpux: gpio-regulator { ++ compatible = "regulator-gpio"; ++ pinctrl-names = "default"; ++ regulator-name = "vdd-cpux"; ++ regulator-type = "voltage"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-ramp-delay = <50>; /* 4ms */ ++ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ gpios-states = <0x1>; ++ states = <1100000 0x0 ++ 1300000 0x1>; ++ }; ++ ++ leds { ++ /delete-node/ status; ++ pwr { ++ label = "nanopi:red:pwr"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ wan { ++ label = "nanopi:green:wan"; ++ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ lan { ++ label = "nanopi:green:lan"; ++ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ r_gpio_keys { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sw_r_npi>; ++ ++ /delete-node/ k1; ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpux>; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ sdio_wifi: sdio_wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&r_pio { ++ sw_r_npi: key_pins { ++ pins = "PL3"; ++ function = "gpio_in"; ++ }; ++}; +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -78,6 +78,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; ++ clock-frequency = <1296000000>; + }; + + cpu1: cpu@1 { +@@ -88,6 +89,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; ++ clock-frequency = <1296000000>; + }; + + cpu2: cpu@2 { +@@ -98,6 +100,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; ++ clock-frequency = <1296000000>; + }; + + cpu3: cpu@3 { +@@ -108,6 +111,7 @@ + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; ++ clock-frequency = <1296000000>; + }; + };