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rockchip: force enable rk3568 msi interrupt

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Since the interrupt of RK3568 has hardware bug,
we need a workaround to enable msi interrupt.
Without this, the r8125 will not be stable.
This commit is contained in:
AmadeusGhost 2022-12-29 17:38:47 +08:00 committed by Tianling Shen
parent 9665cb08ba
commit bba53dd541
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
6 changed files with 390 additions and 0 deletions
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105
target/linux/rockchip/patches-5.15/701-01-irqchip-gic-v3-its-add-GFP_DMA32-flag-for-memory-allocate.patch Normal file
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@ -0,0 +1,105 @@
From a9d1129997cf016b24a33a822659abd13b686323 Mon Sep 17 00:00:00 2001
From: XiaoDong Huang <derrick.huang@rock-chips.com>
Date: Wed, 2 Dec 2020 17:30:47 +0800
Subject: [PATCH] irqchip/gic-v3-its: add GFP_DMA32 flag for memory allocated
for ITS in rk356x
Change-Id: Ic1d866733b348b86bbfdf2df4c0416a68eb422b7
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
---
drivers/irqchip/irq-gic-v3-its.c | 28 ++++++++++++++++++++++++----
1 file changed, 24 insertions(+), 4 deletions(-)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2172,6 +2172,8 @@ static struct page *its_allocate_prop_ta
{
struct page *prop_page;
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
+ gfp_flags |= GFP_DMA32;
prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
if (!prop_page)
return NULL;
@@ -2295,6 +2297,7 @@ static int its_setup_baser(struct its_no
u32 alloc_pages, psz;
struct page *page;
void *base;
+ gfp_t gfp_flags;
psz = baser->psz;
alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
@@ -2306,7 +2309,10 @@ static int its_setup_baser(struct its_no
order = get_order(GITS_BASER_PAGES_MAX * psz);
}
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
+ gfp_flags = GFP_KERNEL | __GFP_ZERO;
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
+ gfp_flags |= GFP_DMA32;
+ page = alloc_pages_node(its->numa_node, gfp_flags, order);
if (!page)
return -ENOMEM;
@@ -2935,6 +2941,8 @@ static struct page *its_allocate_pending
{
struct page *pend_page;
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
+ gfp_flags |= GFP_DMA32;
pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
get_order(LPI_PENDBASE_SZ));
if (!pend_page)
@@ -3278,7 +3286,11 @@ static bool its_alloc_table_entry(struct
/* Allocate memory for 2nd level table */
if (!table[idx]) {
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
+
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
+ gfp_flags |= GFP_DMA32;
+ page = alloc_pages_node(its->numa_node, gfp_flags,
get_order(baser->psz));
if (!page)
return false;
@@ -3367,6 +3379,7 @@ static struct its_device *its_create_dev
int nr_lpis;
int nr_ites;
int sz;
+ gfp_t gfp_flags;
if (!its_alloc_device_table(its, dev_id))
return NULL;
@@ -3382,7 +3395,10 @@ static struct its_device *its_create_dev
nr_ites = max(2, nvecs);
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
+ gfp_flags = GFP_KERNEL;
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
+ gfp_flags |= GFP_DMA32;
+ itt = kzalloc_node(sz, gfp_flags, its->numa_node);
if (alloc_lpis) {
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
if (lpi_map)
@@ -4974,6 +4990,7 @@ static int __init its_probe_one(struct r
u64 baser, tmp, typer;
struct page *page;
int err;
+ gfp_t gfp_flags;
its_base = ioremap(res->start, SZ_64K);
if (!its_base) {
@@ -5042,7 +5059,10 @@ static int __init its_probe_one(struct r
its->numa_node = numa_node;
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+ gfp_flags = GFP_KERNEL | __GFP_ZERO;
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
+ gfp_flags |= GFP_DMA32;
+ page = alloc_pages_node(its->numa_node, gfp_flags,
get_order(ITS_CMD_QUEUE_SZ));
if (!page) {
err = -ENOMEM;

58
target/linux/rockchip/patches-5.15/701-02-irqchip-gic-v3-its-force-to-config-its-tables-as.patch Normal file
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From 44cbfbc637028698b73628a2a635b5466eb341d5 Mon Sep 17 00:00:00 2001
From: XiaoDong Huang <derrick.huang@rock-chips.com>
Date: Wed, 2 Dec 2020 18:03:43 +0800
Subject: [PATCH] irqchip/gic-v3-its: force to config its tables as
no-inner-cache in rk356x
Change-Id: Idebfe94622cbb8169f4d464a3152c7828683c72c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
---
drivers/irqchip/irq-gic-v3-its.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2359,6 +2359,10 @@ retry_baser:
its_write_baser(its, baser, val);
tmp = baser->val;
+ if (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566"))
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
/*
* Shareability didn't stick. Just use
@@ -3100,6 +3104,10 @@ static void its_cpu_init_lpis(void)
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
+ if (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566"))
+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
/*
@@ -3124,6 +3132,10 @@ static void its_cpu_init_lpis(void)
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+ if (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566"))
+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
+
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
* The HW reports non-shareable, we must remove the
@@ -5093,6 +5105,10 @@ static int __init its_probe_one(struct r
gits_write_cbaser(baser, its->base + GITS_CBASER);
tmp = gits_read_cbaser(its->base + GITS_CBASER);
+ if (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566"))
+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
/*

28
target/linux/rockchip/patches-5.15/701-03-irqchip-gic-v3-its-flush-base-table-if-rk356x.patch Normal file
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From bc0263dea7e284d67e4bbe97db3f226d353f4d39 Mon Sep 17 00:00:00 2001
From: XiaoDong Huang <derrick.huang@rock-chips.com>
Date: Mon, 11 Jan 2021 19:51:18 +0800
Subject: [PATCH] irqchip/gic-v3-its: flush base table if rk356x
Change-Id: Ia2b0dd3d47742c43939eb99d3f8adac8e1107603
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
---
drivers/irqchip/irq-gic-v3-its.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2360,8 +2360,12 @@ retry_baser:
tmp = baser->val;
if (of_machine_is_compatible("rockchip,rk3568") ||
- of_machine_is_compatible("rockchip,rk3566"))
- tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+ of_machine_is_compatible("rockchip,rk3566")) {
+ if (tmp & GITS_BASER_SHAREABILITY_MASK)
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+ else
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
+ }
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
/*

66
target/linux/rockchip/patches-5.15/701-04-irqchip-gic-v3-its-force-to-config-its-tables-as.patch Normal file
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@ -0,0 +1,66 @@
From 0b985f29304dcb9d644174edacb67298e8049d4f Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Thu, 18 Mar 2021 20:15:23 +0800
Subject: [PATCH] irqchip/gic-v3-its: force to config its tables as
no-inner-cache in rk3588
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I7275cbf011061f11968505a7570230d2d789e9fc
---
drivers/irqchip/irq-gic-v3-its.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2359,8 +2359,10 @@ retry_baser:
its_write_baser(its, baser, val);
tmp = baser->val;
- if (of_machine_is_compatible("rockchip,rk3568") ||
- of_machine_is_compatible("rockchip,rk3566")) {
+ if (IS_ENABLED(CONFIG_NO_GKI) &&
+ (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566") ||
+ of_machine_is_compatible("rockchip,rk3588"))) {
if (tmp & GITS_BASER_SHAREABILITY_MASK)
tmp &= ~GITS_BASER_SHAREABILITY_MASK;
else
@@ -3108,8 +3110,10 @@ static void its_cpu_init_lpis(void)
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
- if (of_machine_is_compatible("rockchip,rk3568") ||
- of_machine_is_compatible("rockchip,rk3566"))
+ if (IS_ENABLED(CONFIG_NO_GKI) &&
+ (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566") ||
+ of_machine_is_compatible("rockchip,rk3588")))
tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
@@ -3136,8 +3140,10 @@ static void its_cpu_init_lpis(void)
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
- if (of_machine_is_compatible("rockchip,rk3568") ||
- of_machine_is_compatible("rockchip,rk3566"))
+ if (IS_ENABLED(CONFIG_NO_GKI) &&
+ (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566") ||
+ of_machine_is_compatible("rockchip,rk3588")))
tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
@@ -5109,8 +5115,10 @@ static int __init its_probe_one(struct r
gits_write_cbaser(baser, its->base + GITS_CBASER);
tmp = gits_read_cbaser(its->base + GITS_CBASER);
- if (of_machine_is_compatible("rockchip,rk3568") ||
- of_machine_is_compatible("rockchip,rk3566"))
+ if (IS_ENABLED(CONFIG_NO_GKI) &&
+ (of_machine_is_compatible("rockchip,rk3568") ||
+ of_machine_is_compatible("rockchip,rk3566") ||
+ of_machine_is_compatible("rockchip,rk3588")))
tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {

56
target/linux/rockchip/patches-5.15/702-arm64-dts-rockchip-rk356x-Fix-PCIe-register-and-range-map.patch Normal file
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@ -0,0 +1,56 @@
From: Andrew Powers-Holmes <aholmes@omnom.net>
To: linux-rockchip@lists.infradead.org
Cc: "Ondřej Jirman" <megi@xff.cz>, "Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Peter Geis" <pgwipeout@gmail.com>,
"Frank Wunderlich" <frank-w@public-files.de>,
"Michael Riesch" <michael.riesch@wolfvision.net>,
"Yifeng Zhao" <yifeng.zhao@rock-chips.com>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Nicolas Frattaroli" <frattaroli.nicolas@gmail.com>,
"Chris Morgan" <macromorgan@hotmail.com>,
"Ezequiel Garcia" <ezequiel@vanguardiasur.com.ar>,
"Robin Murphy" <robin.murphy@arm.com>,
"Mark Kettenis" <mark.kettenis@xs4all.nl>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/1] arm64: dts: rockchip: rk356x: Fix PCIe register and range mappings
Date: Sat, 12 Nov 2022 22:41:26 +1100 [thread overview]
Message-ID: <20221112114125.1637543-2-aholmes@omnom.net> (raw)
In-Reply-To: <20221112114125.1637543-1-aholmes@omnom.net>
The register and range mappings for the PCIe controller in Rockchip's
RK356x SoCs are incorrect. Replace them with corrected values from the
vendor BSP sources, updated to match current DT schema.
Tested-by: Ondrej Jirman <megi@xff.cz>
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
2 files changed, 12 insertions(+), 9 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -855,7 +855,7 @@
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc0000000 0x0 0x00400000>,
<0x0 0xfe260000 0x0 0x00010000>,
- <0x3 0x3f000000 0x0 0x01000000>;
+ <0x0 0xf4000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -884,8 +884,9 @@
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;

77
target/linux/rockchip/patches-5.15/703-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch Normal file
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@ -0,0 +1,77 @@
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -64,7 +64,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
@@ -87,7 +87,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
- msi-map = <0x0 &gic 0x1000 0x1000>;
+ msi-map = <0x1000 &its 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
@@ -116,7 +116,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
@@ -139,7 +139,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
- msi-map = <0x0 &gic 0x2000 0x1000>;
+ msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -315,14 +315,21 @@
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
- <0x0 0xfd460000 0 0x80000>; /* GICR */
+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- mbi-alias = <0x0 0xfd410000>;
- mbi-ranges = <296 24>;
- msi-controller;
+ its: interrupt-controller@fd440000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0xfd440000 0x0 0x20000>;
+ };
};
usb_host0_ehci: usb@fd800000 {
@@ -879,7 +886,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <2>;
- msi-map = <0x0 &gic 0x0 0x1000>;
+ msi-map = <0x0 &its 0x0 0x1000>;
num-lanes = <1>;
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";