fish/immortalwrt
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge Official Source

Browse Source 
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2021-06-27 02:15:25 +08:00
commit bff4fbaa91
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
79 changed files with 1047 additions and 8992 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
include/kernel-version.mk
View File

@ -6,11 +6,11 @@ ifdef CONFIG_TESTING_KERNEL
KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
endif
LINUX_VERSION-5.4 = .124
LINUX_VERSION-5.10 = .44
LINUX_VERSION-5.4 = .128
LINUX_VERSION-5.10 = .46
LINUX_KERNEL_HASH-5.4.124 = f7f29dda2b042d7b5986d18274413131cf70e17288c05e9a683df1f46c507d82
LINUX_KERNEL_HASH-5.10.44 = 77beefa59c854ce1e8353db947a71a8a91f2a907aed45c1335ac1f209983c767
LINUX_KERNEL_HASH-5.4.128 = 3b54aebb816b9e628cb9ba3055a6aca58ce0ddeec49366c0da86ced9a7be39ab
LINUX_KERNEL_HASH-5.10.46 = 569122a39c6b325befb9ac1c07da0c53e6363b3baacd82081d131b06c1dc1415
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

6
package/network/services/dnsmasq/Makefile
View File

@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=dnsmasq
PKG_UPSTREAM_VERSION:=2.85
PKG_UPSTREAM_VERSION:=2.86test3
PKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION)))
PKG_RELEASE:=$(AUTORELEASE)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz
PKG_SOURCE_URL:=http://thekelleys.org.uk/dnsmasq
PKG_HASH:=ad98d3803df687e5b938080f3d25c628fe41c878752d03fbc6199787fee312fa
PKG_SOURCE_URL:=http://thekelleys.org.uk/dnsmasq/test-releases
PKG_HASH:=0d0b465db89390e9f518f1239dec88b458c84489e7fd38586af6a5781f85e7db
PKG_LICENSE:=GPL-2.0
PKG_LICENSE_FILES:=COPYING

12
package/network/services/dnsmasq/files/dnsmasq.init
View File

@ -172,6 +172,10 @@ append_ipset() {
xappend "--ipset=$1"
}
append_connmark_allowlist() {
xappend "--connmark-allowlist=$1"
}
append_interface() {
network_get_device ifname "$1" || ifname="$1"
xappend "--interface=$ifname"
@ -917,6 +921,14 @@ dnsmasq_start()
config_list_foreach "$cfg" "rev_server" append_rev_server
config_list_foreach "$cfg" "address" append_address
config_list_foreach "$cfg" "ipset" append_ipset
local connmark_allowlist_enable
config_get connmark_allowlist_enable "$cfg" connmark_allowlist_enable 0
[ "$connmark_allowlist_enable" -gt 0 ] && {
append_parm "$cfg" "connmark_allowlist_enable" "--connmark-allowlist-enable"
config_list_foreach "$cfg" "connmark_allowlist" append_connmark_allowlist
}
[ -n "$BOOT" ] || {
config_list_foreach "$cfg" "interface" append_interface
config_list_foreach "$cfg" "notinterface" append_notinterface

4
package/network/services/dnsmasq/patches/100-remove-old-runtime-kernel-support.patch
View File

@ -26,7 +26,7 @@ Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
--- a/src/dnsmasq.h
+++ b/src/dnsmasq.h
@@ -1144,7 +1144,7 @@ extern struct daemon {
@@ -1185,7 +1185,7 @@ extern struct daemon {
int inotifyfd;
#endif
#if defined(HAVE_LINUX_NETWORK)
@ -35,7 +35,7 @@ Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
#elif defined(HAVE_BSD_NETWORK)
int dhcp_raw_fd, dhcp_icmp_fd, routefd;
#endif
@@ -1326,9 +1326,6 @@ int read_write(int fd, unsigned char *pa
@@ -1368,9 +1368,6 @@ int read_write(int fd, unsigned char *pa
void close_fds(long max_fd, int spare1, int spare2, int spare3);
int wildcard_match(const char* wildcard, const char* match);
int wildcard_matchn(const char* wildcard, const char* match, int num);

2
target/linux/bcm27xx/patches-5.4/950-0012-dmaengine-bcm2835-Load-driver-early-and-support-lega.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -133,7 +133,7 @@ config COH901318
@@ -134,7 +134,7 @@ config COH901318
config DMA_BCM2835
tristate "BCM2835 DMA engine support"

2
target/linux/bcm27xx/patches-5.4/950-0037-Add-dwc_otg-driver.patch
View File

@ -1040,7 +1040,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
}
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -5319,7 +5319,7 @@ static void port_event(struct usb_hub *h
@@ -5321,7 +5321,7 @@ static void port_event(struct usb_hub *h
port_dev->over_current_count++;
port_over_current_notify(port_dev);

4
target/linux/bcm27xx/patches-5.4/950-0042-dmaengine-Add-support-for-BCM2708.patch
View File

@ -178,7 +178,7 @@ Signed-off-by: Andrei Gherzan <andrei@gherzan.com>
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -133,7 +133,7 @@ config COH901318
@@ -134,7 +134,7 @@ config COH901318
config DMA_BCM2835
tristate "BCM2835 DMA engine support"
@ -187,7 +187,7 @@ Signed-off-by: Andrei Gherzan <andrei@gherzan.com>
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
@@ -608,6 +608,10 @@ config UNIPHIER_MDMAC
@@ -609,6 +609,10 @@ config UNIPHIER_MDMAC
UniPhier platform. This DMA controller is used as the external
DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.

39
target/linux/bcm27xx/patches-5.4/950-0089-cgroup-Disable-cgroup-memory-by-default.patch
View File

@ -1,4 +1,4 @@
From 0f95a2f2688ff44dc7080beaa2076741a0bdf510 Mon Sep 17 00:00:00 2001
From 2b13c54592135b6fab269517ed687fa9f80bf8e5 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 27 Nov 2017 17:14:54 +0000
Subject: [PATCH] cgroup: Disable cgroup "memory" by default
@ -12,34 +12,46 @@ See: https://github.com/raspberrypi/linux/issues/1950
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
kernel/cgroup/cgroup.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
kernel/cgroup/cgroup.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
--- a/kernel/cgroup/cgroup.c
+++ b/kernel/cgroup/cgroup.c
@@ -5722,6 +5722,8 @@ int __init cgroup_init_early(void)
@@ -5721,6 +5721,9 @@ int __init cgroup_init_early(void)
return 0;
}
static u16 cgroup_disable_mask __initdata;
+static u16 cgroup_enable_mask __initdata;
+static int __init cgroup_disable(char *str);
+
/**
* cgroup_init - cgroup initialization
@@ -5761,6 +5763,12 @@ int __init cgroup_init(void)
*
@@ -5759,6 +5762,12 @@ int __init cgroup_init(void)
mutex_unlock(&cgroup_mutex);
+ /* Apply an implicit disable... */
+ /*
+ * Apply an implicit disable, knowing that an explicit enable will
+ * prevent if from doing anything.
+ */
+ cgroup_disable("memory");
+
+ /* ...knowing that an explicit enable will override it. */
+ cgroup_disable_mask &= ~cgroup_enable_mask;
+
for_each_subsys(ss, ssid) {
if (ss->early_init) {
struct cgroup_subsys_state *css =
@@ -6180,6 +6188,28 @@ static int __init cgroup_disable(char *s
@@ -6168,6 +6177,10 @@ static int __init cgroup_disable(char *s
strcmp(token, ss->legacy_name))
continue;
+ /* An explicit cgroup_enable overrides a disable */
+ if (cgroup_enable_mask & (1 << i))
+ continue;
+
static_branch_disable(cgroup_subsys_enabled_key[i]);
pr_info("Disabling %s control group subsystem\n",
ss->name);
@@ -6177,6 +6190,31 @@ static int __init cgroup_disable(char *s
}
__setup("cgroup_disable=", cgroup_disable);
@ -59,6 +71,9 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+ continue;
+
+ cgroup_enable_mask |= 1 << i;
+ static_branch_enable(cgroup_subsys_enabled_key[i]);
+ pr_info("Enabling %s control group subsystem\n",
+ ss->name);
+ }
+ }
+ return 1;

2
target/linux/bcm27xx/patches-5.4/950-0134-spi-spi-bcm2835-Disable-forced-software-CS.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -1230,31 +1230,6 @@ static int bcm2835_spi_setup(struct spi_
@@ -1236,31 +1236,6 @@ static int bcm2835_spi_setup(struct spi_
return -EINVAL;
}

2
target/linux/bcm27xx/patches-5.4/950-0212-spi-bcm2835-enable-shared-interrupt-support.patch
View File

@ -23,7 +23,7 @@ Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
/* Read as many bytes as possible from FIFO */
bcm2835_rd_fifo(bs);
/* Write as many bytes as possible to FIFO */
@@ -1281,7 +1285,8 @@ static int bcm2835_spi_probe(struct plat
@@ -1287,7 +1291,8 @@ static int bcm2835_spi_probe(struct plat
bcm2835_wr(bs, BCM2835_SPI_CS,
BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

4
target/linux/bcm27xx/patches-5.4/950-0280-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch
View File

@ -33,7 +33,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
#define USB_VENDOR_ID_BELKIN 0x050d
#define USB_DEVICE_ID_FLIP_KVM 0x3201
@@ -1259,6 +1262,9 @@
@@ -1261,6 +1264,9 @@
#define USB_VENDOR_ID_XAT 0x2505
#define USB_DEVICE_ID_XAT_CSR 0x0220
@ -53,7 +53,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_MULTI_TOUCH), HID_QUIRK_MULTI_INPUT },
{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL },
{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE2), HID_QUIRK_ALWAYS_POLL },
@@ -190,6 +191,7 @@ static const struct hid_device_id hid_qu
@@ -192,6 +193,7 @@ static const struct hid_device_id hid_qu
{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP_LTD2, USB_DEVICE_ID_SMARTJOY_DUAL_PLUS), HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT },
{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_QUAD_USB_JOYPAD), HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT },
{ HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_XIN_MO_DUAL_ARCADE), HID_QUIRK_MULTI_INPUT },

2
target/linux/bcm27xx/patches-5.4/950-0409-SQUASH-Fix-spi-driver-compiler-warnings.patch
View File

@ -19,4 +19,4 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
- struct gpio_chip *chip;
u32 cs;
/*
if (spi->chip_select >= BCM2835_SPI_NUM_CS) {

2
target/linux/bcm27xx/patches-5.4/950-0441-PCI-of-Add-inbound-resource-parsing-to-helpers.patch
View File

@ -82,7 +82,7 @@ Cc: linux-rockchip@lists.infradead.org
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1018,7 +1018,8 @@ static int advk_pcie_probe(struct platfo
@@ -1049,7 +1049,8 @@ static int advk_pcie_probe(struct platfo
return ret;
}

4
target/linux/bcm27xx/patches-5.4/950-0646-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
View File

@ -23,7 +23,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -3110,6 +3110,7 @@ static int __spi_validate_bits_per_word(
@@ -3116,6 +3116,7 @@ static int __spi_validate_bits_per_word(
*/
int spi_setup(struct spi_device *spi)
{
@ -31,7 +31,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
unsigned bad_bits, ugly_bits;
int status;
@@ -3127,6 +3128,14 @@ int spi_setup(struct spi_device *spi)
@@ -3133,6 +3134,14 @@ int spi_setup(struct spi_device *spi)
(SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
return -EINVAL;

2
target/linux/bcm27xx/patches-5.4/950-0665-spi-use_gpio_descriptor-fixup-moved-to-spi_setup.patch
View File

@ -37,7 +37,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1793,15 +1793,6 @@ static int of_spi_parse_dt(struct spi_co
@@ -1799,15 +1799,6 @@ static int of_spi_parse_dt(struct spi_co
}
spi->chip_select = value;

2
target/linux/bcm27xx/patches-5.4/950-0690-SQUASH-spi-Demote-SPI_CS_HIGH-warning-to-KERN_DEBUG.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -3122,8 +3122,8 @@ int spi_setup(struct spi_device *spi)
@@ -3128,8 +3128,8 @@ int spi_setup(struct spi_device *spi)
if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
ctlr->cs_gpiods[spi->chip_select] && !(spi->mode & SPI_CS_HIGH)) {

2
target/linux/bcm27xx/patches-5.4/950-0788-Revert-SQUASH-Fix-spi-driver-compiler-warnings.patch
View File

@ -20,4 +20,4 @@ See: https://github.com/raspberrypi/linux/pull/3687
+ enum gpio_lookup_flags lflags;
u32 cs;
/*
if (spi->chip_select >= BCM2835_SPI_NUM_CS) {

2
target/linux/bcm27xx/patches-5.4/950-0789-Revert-spi-spi-bcm2835-Disable-forced-software-CS.patch
View File

@ -13,7 +13,7 @@ See: https://github.com/raspberrypi/linux/pull/3687
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -1235,6 +1235,43 @@ static int bcm2835_spi_setup(struct spi_
@@ -1241,6 +1241,43 @@ static int bcm2835_spi_setup(struct spi_
return -EINVAL;
}

16
target/linux/generic/backport-5.4/393-v5.5-sch_cake-drop-unused-variable-tin_quantum_prio.patch
View File

@ -32,7 +32,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
s32 tin_deficit;
u32 tin_backlog;
u32 tin_dropped;
@@ -1943,7 +1942,7 @@ begin:
@@ -1947,7 +1946,7 @@ begin:
while (b->tin_deficit < 0 ||
!(b->sparse_flow_count + b->bulk_flow_count)) {
if (b->tin_deficit <= 0)
@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
if (b->sparse_flow_count + b->bulk_flow_count)
empty = false;
@@ -2265,8 +2264,7 @@ static int cake_config_besteffort(struct
@@ -2269,8 +2268,7 @@ static int cake_config_besteffort(struct
cake_set_rate(b, rate, mtu,
us_to_ns(q->target), us_to_ns(q->interval));
@ -51,7 +51,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
return 0;
}
@@ -2277,8 +2275,7 @@ static int cake_config_precedence(struct
@@ -2281,8 +2279,7 @@ static int cake_config_precedence(struct
struct cake_sched_data *q = qdisc_priv(sch);
u32 mtu = psched_mtu(qdisc_dev(sch));
u64 rate = q->rate_bps;
@ -61,7 +61,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
u32 i;
q->tin_cnt = 8;
@@ -2291,18 +2288,14 @@ static int cake_config_precedence(struct
@@ -2295,18 +2292,14 @@ static int cake_config_precedence(struct
cake_set_rate(b, rate, mtu, us_to_ns(q->target),
us_to_ns(q->interval));
@ -83,7 +83,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
}
return 0;
@@ -2371,8 +2364,7 @@ static int cake_config_diffserv8(struct
@@ -2375,8 +2368,7 @@ static int cake_config_diffserv8(struct
struct cake_sched_data *q = qdisc_priv(sch);
u32 mtu = psched_mtu(qdisc_dev(sch));
u64 rate = q->rate_bps;
@ -93,7 +93,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
u32 i;
q->tin_cnt = 8;
@@ -2388,18 +2380,14 @@ static int cake_config_diffserv8(struct
@@ -2392,18 +2384,14 @@ static int cake_config_diffserv8(struct
cake_set_rate(b, rate, mtu, us_to_ns(q->target),
us_to_ns(q->interval));
@ -115,7 +115,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
}
return 0;
@@ -2438,17 +2426,11 @@ static int cake_config_diffserv4(struct
@@ -2442,17 +2430,11 @@ static int cake_config_diffserv4(struct
cake_set_rate(&q->tins[3], rate >> 2, mtu,
us_to_ns(q->target), us_to_ns(q->interval));
@ -137,7 +137,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
return 0;
}
@@ -2479,15 +2461,10 @@ static int cake_config_diffserv3(struct
@@ -2483,15 +2465,10 @@ static int cake_config_diffserv3(struct
cake_set_rate(&q->tins[2], rate >> 2, mtu,
us_to_ns(q->target), us_to_ns(q->interval));

1
target/linux/generic/config-5.10
View File

@ -3560,6 +3560,7 @@ CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_NAND_PXA3xx is not set
# CONFIG_MTD_NAND_RB4XX is not set
# CONFIG_MTD_NAND_RB91X is not set
# CONFIG_MTD_NAND_RB750 is not set
# CONFIG_MTD_NAND_RICOH is not set
# CONFIG_MTD_NAND_S3C2410 is not set

1
target/linux/generic/config-5.4
View File

@ -3834,6 +3834,7 @@ CONFIG_NMI_LOG_BUF_SHIFT=13
# CONFIG_NVMEM_SYSFS is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TARGET is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVRAM is not set
# CONFIG_NV_TCO is not set
# CONFIG_NXP_STB220 is not set

2
target/linux/generic/hack-5.4/221-module_exports.patch
View File

@ -56,7 +56,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
} \
\
/* __*init sections */ \
@@ -903,6 +913,8 @@
@@ -904,6 +914,8 @@
EXIT_TEXT \
EXIT_DATA \
EXIT_CALL \

18
target/linux/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
View File

@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
case RTN_THROW:
case RTN_UNREACHABLE:
default:
@@ -4419,6 +4438,17 @@ static int ip6_pkt_prohibit_out(struct n
@@ -4423,6 +4442,17 @@ static int ip6_pkt_prohibit_out(struct n
return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
}
@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
/*
* Allocate a dst for local (unicast / anycast) address.
*/
@@ -4899,7 +4929,8 @@ static int rtm_to_fib6_config(struct sk_
@@ -4903,7 +4933,8 @@ static int rtm_to_fib6_config(struct sk_
if (rtm->rtm_type == RTN_UNREACHABLE ||
rtm->rtm_type == RTN_BLACKHOLE ||
rtm->rtm_type == RTN_PROHIBIT ||
@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
cfg->fc_flags |= RTF_REJECT;
if (rtm->rtm_type == RTN_LOCAL)
@@ -6021,6 +6052,8 @@ static int ip6_route_dev_notify(struct n
@@ -6025,6 +6056,8 @@ static int ip6_route_dev_notify(struct n
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.ip6_prohibit_entry->dst.dev = dev;
net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
#endif
@@ -6032,6 +6065,7 @@ static int ip6_route_dev_notify(struct n
@@ -6036,6 +6069,7 @@ static int ip6_route_dev_notify(struct n
in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
#endif
}
@@ -6224,6 +6258,8 @@ static int __net_init ip6_route_net_init
@@ -6228,6 +6262,8 @@ static int __net_init ip6_route_net_init
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.fib6_has_custom_rules = false;
@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
sizeof(*net->ipv6.ip6_prohibit_entry),
GFP_KERNEL);
@@ -6234,11 +6270,21 @@ static int __net_init ip6_route_net_init
@@ -6238,11 +6274,21 @@ static int __net_init ip6_route_net_init
ip6_template_metrics, true);
INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
ip6_template_metrics, true);
@@ -6262,6 +6308,8 @@ out:
@@ -6266,6 +6312,8 @@ out:
return ret;
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
out_ip6_prohibit_entry:
kfree(net->ipv6.ip6_prohibit_entry);
out_ip6_null_entry:
@@ -6281,6 +6329,7 @@ static void __net_exit ip6_route_net_exi
@@ -6285,6 +6333,7 @@ static void __net_exit ip6_route_net_exi
kfree(net->ipv6.ip6_null_entry);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
kfree(net->ipv6.ip6_prohibit_entry);
@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
kfree(net->ipv6.ip6_blk_hole_entry);
#endif
dst_entries_destroy(&net->ipv6.ip6_dst_ops);
@@ -6358,6 +6407,9 @@ void __init ip6_route_init_special_entri
@@ -6362,6 +6411,9 @@ void __init ip6_route_init_special_entri
init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);

0
target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq → target/linux/lantiq/ase/base-files/lib/preinit/05_set_preinit_iface_lantiq
View File

1
target/linux/lantiq/ase/config-5.10
View File

@ -16,6 +16,7 @@ CONFIG_NLS=y
CONFIG_SGL_ALLOC=y
CONFIG_SOC_AMAZON_SE=y
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SWCONFIG=y
CONFIG_TARGET_ISA_REV=1
CONFIG_USB=y
CONFIG_USB_COMMON=y

1
target/linux/lantiq/ase/config-5.4
View File

@ -16,6 +16,7 @@ CONFIG_NLS=y
CONFIG_SGL_ALLOC=y
CONFIG_SOC_AMAZON_SE=y
# CONFIG_SOC_XWAY is not set
CONFIG_SWCONFIG=y
CONFIG_TARGET_ISA_REV=1
CONFIG_USB=y
CONFIG_USB_COMMON=y

3
target/linux/lantiq/config-5.10
View File

@ -129,7 +129,6 @@ CONFIG_LANTIQ_DT_NONE=y
# CONFIG_LANTIQ_ETOP is not set
CONFIG_LANTIQ_WDT=y
# CONFIG_LANTIQ_XRX200 is not set
# CONFIG_LANTIQ_XRX200_LEGACY is not set
CONFIG_LEDS_GPIO=y
CONFIG_LIBFDT=y
CONFIG_LLD_VERSION=0
@ -211,7 +210,6 @@ CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SRCU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SWCONFIG=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
@ -228,4 +226,3 @@ CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_XRX200_PHY_FW is not set

3
target/linux/lantiq/config-5.4
View File

@ -130,7 +130,6 @@ CONFIG_LANTIQ_DT_NONE=y
# CONFIG_LANTIQ_ETOP is not set
CONFIG_LANTIQ_WDT=y
# CONFIG_LANTIQ_XRX200 is not set
# CONFIG_LANTIQ_XRX200_LEGACY is not set
CONFIG_LEDS_GPIO=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
@ -207,7 +206,6 @@ CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SRCU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SWCONFIG=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
@ -224,4 +222,3 @@ CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_XRX200_PHY_FW is not set

89
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
View File

@ -120,22 +120,6 @@
ranges = <0x0 0x203000 0x100>;
big-endian;
gphy0: gphy@20 {
compatible = "lantiq,xrx200-gphy";
reg = <0x20 0x4>;
resets = <&reset0 31 30>, <&reset1 7 7>;
reset-names = "gphy", "gphy2";
};
gphy1: gphy@68 {
compatible = "lantiq,xrx200-gphy";
reg = <0x68 0x4>;
resets = <&reset0 29 28>, <&reset1 6 6>;
reset-names = "gphy", "gphy2";
};
reset0: reset-controller@10 {
compatible = "lantiq,xrx200-reset";
reg = <0x10 4>, <0x14 4>;
@ -446,22 +430,71 @@
};
};
eth0: eth@e108000 {
gswip: switch@e108000 {
compatible = "lantiq,xrx200-gswip";
#address-cells = <1>;
#size-cells = <0>;
reg = < 0xe108000 0x3000 /* switch */
0xe10b100 0x70 /* mdio */
0xe10b1d8 0x30 /* mii */
>;
dsa,member = <0 0>;
gswip_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <0x6>;
label = "cpu";
ethernet = <&eth0>;
};
};
gswip_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
};
gphy-fw {
compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
lantiq,rcu = <&rcu0>;
#address-cells = <1>;
#size-cells = <0>;
gphy0: gphy@20 {
reg = <0x20>;
resets = <&reset0 31 30>;
reset-names = "gphy";
};
gphy1: gphy@68 {
reg = <0x68>;
resets = <&reset0 29 28>;
reset-names = "gphy";
};
};
};
eth0: eth@e10b308 {
compatible = "lantiq,xrx200-net";
reg = < 0xe108000 0x3000 /* switch */
0xe10b100 0x70 /* mdio */
0xe10b1d8 0x30 /* mii */
0xe10b308 0x30 /* pmac */
>;
reg = <0xe10b308 0x30>; /* pmac */
interrupt-parent = <&icu0>;
interrupts = <75 73 72>;
resets = <&reset0 21 16>, <&reset0 8 8>;
reset-names = "switch", "ppe";
lantiq,phys = <&gphy0>, <&gphy1>;
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
interrupts = <73>, <72>;
interrupt-names = "tx", "rx";
resets = <&reset0 21 16>, <&reset0 8 8>, <&reset0 3 3>;
reset-names = "switch", "ppe", "ppe_dsp";
#address-cells = <1>;
#size-cells = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
mei@e116000 {

66
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts
View File

@ -69,46 +69,6 @@
};
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <3>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy14: ethernet-phy@14 {
reg = <0x14>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
@ -117,6 +77,32 @@
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
&gswip_mdio {
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy14: ethernet-phy@14 {
reg = <0x14>;
};
};
&gswip_ports {
port@2 {
reg = <2>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy14>;
};
};
&localbus {
flash@0 {
compatible = "lantiq,nor";

123
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
View File

@ -94,72 +94,7 @@
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mtd-mac-address = <&boardconfig 0x16>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <3>;
phy-mode = "mii";
phy-handle = <&phy12>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy12: ethernet-phy@12 {
reg = <0x12>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy14: ethernet-phy@14 {
reg = <0x14>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
};
mtd-mac-address = <&boardconfig 0x16>;
};
&gphy0 {
@ -183,6 +118,62 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy12: ethernet-phy@12 {
reg = <0x12>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
phy14: ethernet-phy@14 {
reg = <0x14>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan5";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy12>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy14>;
};
};
&localbus {
flash@0 {
compatible = "lantiq,nor";

88
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
View File

@ -54,56 +54,6 @@
};
};
&eth0 {
pinctrl-0 = <&mdio_pins>,
<&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>,
<&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>;
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
lantiq,led1h = <0x70>;
lantiq,led1l = <0x00>;
lantiq,led2h = <0x00>;
lantiq,led2l = <0x03>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
lantiq,led1h = <0x70>;
lantiq,led1l = <0x00>;
lantiq,led2h = <0x00>;
lantiq,led2l = <0x03>;
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
@ -112,6 +62,44 @@
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
&gswip {
pinctrl-0 = <&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>,
<&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy11: ethernet-phy@11 {
reg = <0x11>;
lantiq,led1h = <0x70>;
lantiq,led1l = <0x00>;
lantiq,led2h = <0x00>;
lantiq,led2l = <0x03>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
lantiq,led1h = <0x70>;
lantiq,led1l = <0x00>;
lantiq,led2h = <0x00>;
lantiq,led2l = <0x03>;
};
};
&gswip_ports {
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
};
&localbus {
flash@0 {
compatible = "lantiq,nor";

131
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi
View File

@ -107,78 +107,7 @@
};
&eth0 {
pinctrl-0 = <&mdio_pins>,
<&gphy0_led0_pins>,
<&gphy1_led0_pins>, <&gphy1_led1_pins>;
pinctrl-names = "default";
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mtd-mac-address = <&boardconfig 0x16>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "mii";
phy-handle = <&phy1>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <3>;
phy-mode = "mii";
phy-handle = <&phy12>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy12: ethernet-phy@12 {
reg = <0x12>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy14: ethernet-phy@14 {
reg = <0x14>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
};
mtd-mac-address = <&boardconfig 0x16>;
};
&gphy0 {
@ -203,6 +132,64 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>,
<&gphy0_led0_pins>,
<&gphy1_led0_pins>, <&gphy1_led1_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy1: ethernet-phy@1 {
reg = <0x1>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy12: ethernet-phy@12 {
reg = <0x12>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
phy14: ethernet-phy@14 {
reg = <0x14>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "wan";
phy-mode = "mii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@3 {
reg = <3>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy12>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy14>;
};
};
&localbus {
flash@0 {
compatible = "lantiq,nor";

128
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi
View File

@ -127,76 +127,8 @@
};
&eth0 {
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>;
pinctrl-names = "default";
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mtd-mac-address = <&boardconfig 0x16>;
mtd-mac-address-increment = <1>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
mtd-mac-address = <&boardconfig 0x16>;
mtd-mac-address-increment = <1>;
};
&gphy0 {
@ -221,6 +153,62 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan4";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan3";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
&localbus {
flash@0 {
compatible = "lantiq,nor";

121
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi
View File

@ -114,72 +114,6 @@
};
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
@ -208,6 +142,61 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan3";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
};
&pcie0 {
gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;

121
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts
View File

@ -106,72 +106,6 @@
};
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
@ -207,6 +141,61 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan3";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
};
&spi {
status = "okay";

122
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
View File

@ -81,71 +81,8 @@
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mtd-mac-address = <&urlader 0xa91>;
mtd-mac-address-increment = <(-2)>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rmii";
phy-handle = <&phy1>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x00>;
compatible = "ethernet-phy-ieee802.3-c22";
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@1 {
reg = <0x01>;
compatible = "ethernet-phy-ieee802.3-c22";
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
mtd-mac-address = <&urlader 0xa91>;
mtd-mac-address-increment = <(-2)>;
};
&gphy0 {
@ -171,6 +108,61 @@
};
&gswip {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x00>;
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@1 {
reg = <0x01>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan3";
phy-mode = "rmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "rmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
};
&pcie0 {
status = "okay";

40
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts
View File

@ -181,33 +181,17 @@
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
&eth0 {
lantiq,phys = <&gphy0>;
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mac-address = [ 00 11 22 33 44 55 ];
lantiq,switch;
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
&gswip_mdio {
phy11: ethernet-phy@11 {
reg = <0x11>;
};
};
&gswip_ports {
port@2 {
reg = <2>;
label = "lan";
phy-mode = "internal";
phy-handle = <&phy11>;
};
};

106
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts
View File

@ -185,70 +185,6 @@
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <3>;
phy-mode = "mii";
phy-handle = <&phy12>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy12: ethernet-phy@12 {
reg = <0x12>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy14: ethernet-phy@14 {
reg = <0x14>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
};
};
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@ -262,6 +198,48 @@
};
};
&gswip_mdio {
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy12: ethernet-phy@12 {
reg = <0x12>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
phy14: ethernet-phy@14 {
reg = <0x14>;
};
};
&gswip_ports {
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy12>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy14>;
};
};
&usb_phy0 {
status = "okay";
};

124
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
View File

@ -114,74 +114,6 @@
};
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
@ -215,6 +147,62 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan3";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
&localbus {
flash@1 {
compatible = "lantiq,nand-xway";

100
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
View File

@ -152,64 +152,6 @@
};
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <3>;
phy-mode = "mii";
phy-handle = <&phy12>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy12: ethernet-phy@12 {
reg = <0x12>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
phy14: ethernet-phy@14 {
reg = <0x14>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
@ -237,6 +179,48 @@
};
};
&gswip_mdio {
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy12: ethernet-phy@12 {
reg = <0x12>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
phy14: ethernet-phy@14 {
reg = <0x14>;
};
};
&gswip_ports {
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy12>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy14>;
};
};
&spi {
status = "okay";

133
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
View File

@ -97,83 +97,6 @@
};
};
&eth0 {
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
};
interface@1 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
lantiq,wan;
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
@ -210,6 +133,62 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan4";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan3";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
&spi {
status = "okay";

40
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts
View File

@ -83,37 +83,23 @@
};
};
&eth0 {
lantiq,phys = <&gphy1>;
&gphy1 {
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
};
&gswip_mdio {
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gphy1 {
lantiq,gphy-mode = <GPHY_MODE_FE>;
&gswip_ports {
port@4 {
reg = <4>;
label = "lan";
phy-mode = "internal";
phy-handle = <&phy13>;
};
};
&pcie0 {

109
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
View File

@ -110,66 +110,7 @@
};
&eth0 {
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
pinctrl-names = "default";
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mtd-mac-address = <&ath9k_cal 0xf100>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
// gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
mtd-mac-address = <&ath9k_cal 0xf100>;
};
&gphy0 {
@ -199,6 +140,54 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
// reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan2";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "lan1";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
&pcie0 {
pcie@0 {
reg = <0 0 0 0 0>;

109
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
View File

@ -100,66 +100,7 @@
};
&eth0 {
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
pinctrl-names = "default";
lan: interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mtd-mac-address = <&romfile 0xf100>;
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
// gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
mtd-mac-address = <&romfile 0xf100>;
};
&gphy0 {
@ -189,6 +130,54 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
// reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan3";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "lan4";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
&pcie0 {
pcie@0 {
reg = <0 0 0 0 0>;

132
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi
View File

@ -110,80 +110,6 @@
};
};
&eth0 {
pinctrl-0 = <&mdio_pins>,
<&gphy0_led1_pins>, <&gphy0_led2_pins>,
<&gphy1_led1_pins>, <&gphy1_led2_pins>;
pinctrl-names = "default";
interface@0 {
compatible = "lantiq,xrx200-pdi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mac-address = [ 00 11 22 33 44 55 ];
lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "lantiq,xrx200-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
@ -221,6 +147,64 @@
};
};
&gswip {
pinctrl-0 = <&mdio_pins>,
<&gphy0_led1_pins>, <&gphy0_led2_pins>,
<&gphy1_led1_pins>, <&gphy1_led2_pins>;
pinctrl-names = "default";
};
&gswip_mdio {
phy0: ethernet-phy@0 {
reg = <0x0>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
};
&gswip_ports {
port@0 {
reg = <0>;
label = "lan1";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan2";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
&pci0 {
status = "okay";

9
target/linux/lantiq/image/tp-link.mk
View File

@ -1,5 +1,10 @@
DEVICE_VARS += TPLINK_FLASHLAYOUT TPLINK_HWID TPLINK_HWREV TPLINK_HWREVADD TPLINK_HVERSION
define Device/dsa-migration
DEVICE_COMPAT_VERSION := 1.1
DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA
endef
define Device/lantiqTpLink
DEVICE_VENDOR := TP-Link
TPLINK_HWREVADD := 0
@ -13,6 +18,7 @@ define Device/lantiqTpLink
endef
define Device/tplink_tdw8970
$(Device/dsa-migration)
$(Device/lantiqTpLink)
DEVICE_MODEL := TD-W8970
DEVICE_VARIANT := v1
@ -26,6 +32,7 @@ endef
TARGET_DEVICES += tplink_tdw8970
define Device/tplink_tdw8980
$(Device/dsa-migration)
$(Device/lantiqTpLink)
DEVICE_MODEL := TD-W8980
DEVICE_VARIANT := v1
@ -39,6 +46,7 @@ endef
TARGET_DEVICES += tplink_tdw8980
define Device/tplink_vr200
$(Device/dsa-migration)
$(Device/lantiqTpLink)
DEVICE_MODEL := Archer VR200
DEVICE_VARIANT := v1
@ -52,6 +60,7 @@ endef
TARGET_DEVICES += tplink_vr200
define Device/tplink_vr200v
$(Device/dsa-migration)
$(Device/lantiqTpLink)
DEVICE_MODEL := Archer VR200v
DEVICE_VARIANT := v1

28
target/linux/lantiq/image/vr9.mk
View File

@ -1,6 +1,12 @@
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
define Device/dsa-migration
DEVICE_COMPAT_VERSION := 1.1
DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA
endef
define Device/alphanetworks_asl56026
$(Device/dsa-migration)
DEVICE_VENDOR := Alpha
DEVICE_MODEL := ASL56026
DEVICE_ALT0_VENDOR := BT Openreach
@ -10,6 +16,7 @@ endef
TARGET_DEVICES += alphanetworks_asl56026
define Device/arcadyan_arv7519rw22
$(Device/dsa-migration)
DEVICE_VENDOR := Arcadyan
DEVICE_MODEL := ARV7519RW22
DEVICE_ALT0_VENDOR := Orange
@ -26,6 +33,7 @@ endef
TARGET_DEVICES += arcadyan_arv7519rw22
define Device/arcadyan_vg3503j
$(Device/dsa-migration)
DEVICE_VENDOR := BT Openreach
DEVICE_MODEL := ECI VDSL Modem V-2FUb/R
IMAGE_SIZE := 8000k
@ -34,6 +42,7 @@ endef
TARGET_DEVICES += arcadyan_vg3503j
define Device/arcadyan_vgv7510kw22-brn
$(Device/dsa-migration)
$(Device/lantiqBrnImage)
DEVICE_VENDOR := Arcadyan
DEVICE_MODEL := VGV7510KW22
@ -51,6 +60,7 @@ endef
TARGET_DEVICES += arcadyan_vgv7510kw22-brn
define Device/arcadyan_vgv7510kw22-nor
$(Device/dsa-migration)
DEVICE_VENDOR := Arcadyan
DEVICE_MODEL := VGV7510KW22
DEVICE_VARIANT := NOR
@ -64,6 +74,7 @@ endef
TARGET_DEVICES += arcadyan_vgv7510kw22-nor
define Device/arcadyan_vgv7519-brn
$(Device/dsa-migration)
$(Device/lantiqBrnImage)
DEVICE_VENDOR := Arcadyan
DEVICE_MODEL := VGV7519
@ -81,6 +92,7 @@ endef
TARGET_DEVICES += arcadyan_vgv7519-brn
define Device/arcadyan_vgv7519-nor
$(Device/dsa-migration)
DEVICE_VENDOR := Arcadyan
DEVICE_MODEL := VGV7519
DEVICE_VARIANT := NOR
@ -94,6 +106,7 @@ endef
TARGET_DEVICES += arcadyan_vgv7519-nor
define Device/avm_fritz3370
$(Device/dsa-migration)
$(Device/AVM)
$(Device/NAND)
DEVICE_MODEL := FRITZ!Box 3370
@ -107,6 +120,7 @@ define Device/avm_fritz3370
endef
define Device/avm_fritz3370-rev2-hynix
$(Device/dsa-migration)
$(Device/avm_fritz3370)
DEVICE_MODEL := FRITZ!Box 3370
DEVICE_VARIANT := Rev. 2 (Hynix NAND)
@ -114,6 +128,7 @@ endef
TARGET_DEVICES += avm_fritz3370-rev2-hynix
define Device/avm_fritz3370-rev2-micron
$(Device/dsa-migration)
$(Device/avm_fritz3370)
DEVICE_MODEL := FRITZ!Box 3370
DEVICE_VARIANT := Rev. 2 (Micron NAND)
@ -121,6 +136,7 @@ endef
TARGET_DEVICES += avm_fritz3370-rev2-micron
define Device/avm_fritz3390
$(Device/dsa-migration)
$(Device/AVM)
$(Device/NAND)
DEVICE_MODEL := FRITZ!Box 3390
@ -132,6 +148,7 @@ endef
TARGET_DEVICES += avm_fritz3390
define Device/avm_fritz7360sl
$(Device/dsa-migration)
$(Device/AVM)
DEVICE_MODEL := FRITZ!Box 7360 SL
IMAGE_SIZE := 15744k
@ -141,6 +158,7 @@ endef
TARGET_DEVICES += avm_fritz7360sl
define Device/avm_fritz7360-v2
$(Device/dsa-migration)
$(Device/AVM)
DEVICE_MODEL := FRITZ!Box 7360
DEVICE_VARIANT := v2
@ -150,6 +168,7 @@ endef
TARGET_DEVICES += avm_fritz7360-v2
define Device/avm_fritz7362sl
$(Device/dsa-migration)
$(Device/AVM)
$(Device/NAND)
DEVICE_MODEL := FRITZ!Box 7362 SL
@ -160,6 +179,7 @@ endef
TARGET_DEVICES += avm_fritz7362sl
define Device/avm_fritz7412
$(Device/dsa-migration)
$(Device/AVM)
$(Device/NAND)
DEVICE_MODEL := FRITZ!Box 7412
@ -171,6 +191,7 @@ endef
TARGET_DEVICES += avm_fritz7412
define Device/avm_fritz7430
$(Device/dsa-migration)
$(Device/AVM)
$(Device/NAND)
DEVICE_MODEL := FRITZ!Box 7430
@ -181,6 +202,7 @@ endef
TARGET_DEVICES += avm_fritz7430
define Device/bt_homehub-v5a
$(Device/dsa-migration)
$(Device/NAND)
DEVICE_VENDOR := British Telecom
DEVICE_MODEL := Home Hub 5
@ -193,6 +215,7 @@ endef
TARGET_DEVICES += bt_homehub-v5a
define Device/buffalo_wbmr-300hpd
$(Device/dsa-migration)
DEVICE_VENDOR := Buffalo
DEVICE_MODEL := WBMR-300HPD
IMAGE_SIZE := 15616k
@ -202,6 +225,7 @@ endef
TARGET_DEVICES += buffalo_wbmr-300hpd
define Device/lantiq_easy80920-nand
$(Device/dsa-migration)
$(Device/lantiqFullImage)
DEVICE_VENDOR := Lantiq
DEVICE_MODEL := VR9 EASY80920
@ -212,6 +236,7 @@ endef
TARGET_DEVICES += lantiq_easy80920-nand
define Device/lantiq_easy80920-nor
$(Device/dsa-migration)
DEVICE_VENDOR := Lantiq
DEVICE_MODEL := VR9 EASY80920
DEVICE_VARIANT := NOR
@ -221,6 +246,7 @@ endef
TARGET_DEVICES += lantiq_easy80920-nor
define Device/netgear_dm200
$(Device/dsa-migration)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := DM200
IMAGES := sysupgrade.bin factory.img
@ -236,6 +262,7 @@ endef
TARGET_DEVICES += netgear_dm200
define Device/zyxel_p-2812hnu-f1
$(Device/dsa-migration)
$(Device/NAND)
DEVICE_VENDOR := ZyXEL
DEVICE_MODEL := P-2812HNU
@ -248,6 +275,7 @@ endef
TARGET_DEVICES += zyxel_p-2812hnu-f1
define Device/zyxel_p-2812hnu-f3
$(Device/dsa-migration)
$(Device/NAND)
DEVICE_VENDOR := ZyXEL
DEVICE_MODEL := P-2812HNU

71
target/linux/lantiq/patches-5.10/0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
View File

@ -1,71 +0,0 @@
From d0ee51bbb7ce9880749a3d4794ec1fbbcda0f381 Mon Sep 17 00:00:00 2001
From: Mathias Kresin <dev@kresin.me>
Date: Sun, 7 Jul 2019 21:45:51 +0200
Subject: [PATCH] MIPS: lantiq revert DSA switch driver PMU/clock changes
Switch back to the former used names, to make the legacy switch driver
happy.
Signed-off-by: Mathias Kresin <dev@kresin.me>
---
arch/mips/lantiq/xway/sysctrl.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -469,9 +469,9 @@ void __init ltq_soc_init(void)
if (of_machine_is_compatible("lantiq,grx390") ||
of_machine_is_compatible("lantiq,ar10")) {
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
- clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
+ clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY0);
+ clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY1);
+ clkdev_add_pmu("1f2030ac.gphy", NULL, 1, 0, PMU_GPHY2);
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
/* rc 0 */
@@ -503,7 +503,7 @@ void __init ltq_soc_init(void)
} else if (of_machine_is_compatible("lantiq,grx390")) {
clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
- clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
+ clkdev_add_pmu("1f203264.gphy", NULL, 1, 0, PMU_GPHY3);
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
/* rc 2 */
@@ -511,7 +511,7 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
} else if (of_machine_is_compatible("lantiq,ar10")) {
@@ -519,7 +519,7 @@ void __init ltq_soc_init(void)
ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
PMU_PPE_DP | PMU_PPE_TC);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
@@ -540,12 +540,12 @@ void __init ltq_soc_init(void)
clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_PPE_TOP);
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);

3473
target/linux/lantiq/patches-5.10/0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch
View File

File diff suppressed because it is too large Load Diff

352
target/linux/lantiq/patches-5.10/0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
View File

@ -1,352 +0,0 @@
From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
From: Mathias Kresin <dev@kresin.me>
Date: Sun, 7 Jul 2019 21:48:56 +0200
Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
Upstream, the GPHY Firmware loader has been merged into the DSA switch
driver. But we don't use the driver yet, so bring it back.
Signed-off-by: Mathias Kresin <dev@kresin.me>
---
.../bindings/mips/lantiq/rcu-gphy.txt | 36 +++
.../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++
arch/mips/configs/xway_defconfig | 1 +
arch/mips/lantiq/Kconfig | 4 +
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++
6 files changed, 284 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
create mode 100644 drivers/soc/lantiq/gphy.c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,37 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200-gphy"
+ "lantiq,xrx200a1x-gphy"
+ "lantiq,xrx200a2x-gphy"
+ "lantiq,xrx300-gphy"
+ "lantiq,xrx330-gphy"
+- reg : Addrress of the GPHY FW load address register
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+- clocks : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
@@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
ranges = <0x0 0x203000 0x100>;
big-endian;
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ gphy1: gphy@68 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x68 0x4>;
+
+ resets = <&reset0 29 28>, <&reset1 6 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
reset0: reset-controller@10 {
compatible = "lantiq,xrx200-reset";
reg = <0x10 4>, <0x14 4>;
--- a/arch/mips/configs/xway_defconfig
+++ b/arch/mips/configs/xway_defconfig
@@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_LANTIQ=y
CONFIG_PCI_LANTIQ=y
+CONFIG_XRX200_PHY_FW=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_MIPS_VPE_LOADER=y
CONFIG_NR_CPUS=2
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
depends on PCIE_LANTIQ && PCI_MSI
default y
+config XRX200_PHY_FW
+ bool "XRX200 PHY firmware loader"
+ depends on SOC_XWAY
+
endif
--- a/drivers/soc/lantiq/Makefile
+++ b/drivers/soc/lantiq/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += fpi-bus.o
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,235 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+struct xway_gphy_priv {
+ struct clk *gphy_clk_gate;
+ struct reset_control *gphy_reset;
+ struct reset_control *gphy_reset2;
+ void __iomem *membase;
+ char *fw_name;
+};
+
+struct xway_gphy_match_data {
+ char *fe_firmware_name;
+ char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+ { .compatible = "lantiq,xrx200-gphy", .data = NULL },
+ { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
+ { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
+ { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
+ { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
+ dma_addr_t *dev_addr)
+{
+ const struct firmware *fw;
+ void *fw_addr;
+ dma_addr_t dma_addr;
+ size_t size;
+ int ret;
+
+ ret = request_firmware(&fw, priv->fw_name, dev);
+ if (ret) {
+ dev_err(dev, "failed to load firmware: %s, error: %i\n",
+ priv->fw_name, ret);
+ return ret;
+ }
+
+ /*
+ * GPHY cores need the firmware code in a persistent and contiguous
+ * memory area with a 16 kB boundary aligned start address.
+ */
+ size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+ fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
+ if (fw_addr) {
+ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
+ *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+ memcpy(fw_addr, fw->data, fw->size);
+ } else {
+ dev_err(dev, "failed to alloc firmware memory\n");
+ ret = -ENOMEM;
+ }
+
+ release_firmware(fw);
+
+ return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+ struct xway_gphy_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
+ u32 gphy_mode;
+ int ret;
+ struct resource *res_gphy;
+
+ gphy_fw_name_cfg = of_device_get_match_data(dev);
+
+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
+ switch (ltq_soc_type()) {
+ case SOC_TYPE_VR9:
+ gphy_fw_name_cfg = &xrx200a1x_gphy_data;
+ break;
+ case SOC_TYPE_VR9_2:
+ gphy_fw_name_cfg = &xrx200a2x_gphy_data;
+ break;
+ }
+
+ priv->gphy_clk_gate = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->gphy_clk_gate)) {
+ dev_err(dev, "Failed to lookup gate clock\n");
+ return PTR_ERR(priv->gphy_clk_gate);
+ }
+
+ res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->membase = devm_ioremap_resource(dev, res_gphy);
+ if (IS_ERR(priv->membase))
+ return PTR_ERR(priv->membase);
+
+ priv->gphy_reset = devm_reset_control_get(dev, "gphy");
+ if (IS_ERR(priv->gphy_reset)) {
+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
+ dev_err(dev, "Failed to lookup gphy reset\n");
+ return PTR_ERR(priv->gphy_reset);
+ }
+
+ priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
+ if (IS_ERR(priv->gphy_reset2))
+ return PTR_ERR(priv->gphy_reset2);
+
+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
+ /* Default to GE mode */
+ if (ret)
+ gphy_mode = GPHY_MODE_GE;
+
+ switch (gphy_mode) {
+ case GPHY_MODE_FE:
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+ break;
+ case GPHY_MODE_GE:
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+ break;
+ default:
+ dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct xway_gphy_priv *priv;
+ dma_addr_t fw_addr = 0;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = xway_gphy_of_probe(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->gphy_clk_gate);
+ if (ret)
+ return ret;
+
+ ret = xway_gphy_load(dev, priv, &fw_addr);
+ if (ret) {
+ clk_disable_unprepare(priv->gphy_clk_gate);
+ return ret;
+ }
+
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+
+ iowrite32be(fw_addr, priv->membase);
+
+ reset_control_deassert(priv->gphy_reset);
+ reset_control_deassert(priv->gphy_reset2);
+
+ platform_set_drvdata(pdev, priv);
+
+ return ret;
+}
+
+static int xway_gphy_remove(struct platform_device *pdev)
+{
+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
+
+ iowrite32be(0, priv->membase);
+
+ clk_disable_unprepare(priv->gphy_clk_gate);
+
+ return 0;
+}
+
+static struct platform_driver xway_gphy_driver = {
+ .probe = xway_gphy_probe,
+ .remove = xway_gphy_remove,
+ .driver = {
+ .name = "xway-rcu-gphy",
+ .of_match_table = xway_gphy_match,
+ },
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");

55
target/linux/lantiq/patches-5.4/0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
View File

@ -1,55 +0,0 @@
From d0ee51bbb7ce9880749a3d4794ec1fbbcda0f381 Mon Sep 17 00:00:00 2001
From: Mathias Kresin <dev@kresin.me>
Date: Sun, 7 Jul 2019 21:45:51 +0200
Subject: [PATCH] MIPS: lantiq revert DSA switch driver PMU/clock changes
Switch back to the former used names, to make the legacy switch driver
happy.
Signed-off-by: Mathias Kresin <dev@kresin.me>
---
arch/mips/lantiq/xway/sysctrl.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -503,7 +503,7 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
} else if (of_machine_is_compatible("lantiq,ar10")) {
@@ -511,11 +511,11 @@ void __init ltq_soc_init(void)
ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
PMU_PPE_DP | PMU_PPE_TC);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
@@ -534,12 +534,12 @@ void __init ltq_soc_init(void)
clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_PPE_TOP);
- clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
- clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
+ clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);

3470
target/linux/lantiq/patches-5.4/0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch
View File

File diff suppressed because it is too large Load Diff

352
target/linux/lantiq/patches-5.4/0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
View File

@ -1,352 +0,0 @@
From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
From: Mathias Kresin <dev@kresin.me>
Date: Sun, 7 Jul 2019 21:48:56 +0200
Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
Upstream, the GPHY Firmware loader has been merged into the DSA switch
driver. But we don't use the driver yet, so bring it back.
Signed-off-by: Mathias Kresin <dev@kresin.me>
---
.../bindings/mips/lantiq/rcu-gphy.txt | 36 +++
.../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++
arch/mips/configs/xway_defconfig | 1 +
arch/mips/lantiq/Kconfig | 4 +
drivers/soc/lantiq/Makefile | 1 +
drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++
6 files changed, 284 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
create mode 100644 drivers/soc/lantiq/gphy.c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,37 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200-gphy"
+ "lantiq,xrx200a1x-gphy"
+ "lantiq,xrx200a2x-gphy"
+ "lantiq,xrx300-gphy"
+ "lantiq,xrx330-gphy"
+- reg : Addrress of the GPHY FW load address register
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+- clocks : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
@@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
ranges = <0x0 0x203000 0x100>;
big-endian;
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ gphy1: gphy@68 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x68 0x4>;
+
+ resets = <&reset0 29 28>, <&reset1 6 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
reset0: reset-controller@10 {
compatible = "lantiq,xrx200-reset";
reg = <0x10 4>, <0x14 4>;
--- a/arch/mips/configs/xway_defconfig
+++ b/arch/mips/configs/xway_defconfig
@@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_LANTIQ=y
CONFIG_PCI_LANTIQ=y
+CONFIG_XRX200_PHY_FW=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_MIPS_VPE_LOADER=y
CONFIG_NR_CPUS=2
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
depends on PCIE_LANTIQ && PCI_MSI
default y
+config XRX200_PHY_FW
+ bool "XRX200 PHY firmware loader"
+ depends on SOC_XWAY
+
endif
--- a/drivers/soc/lantiq/Makefile
+++ b/drivers/soc/lantiq/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += fpi-bus.o
+obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,235 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+struct xway_gphy_priv {
+ struct clk *gphy_clk_gate;
+ struct reset_control *gphy_reset;
+ struct reset_control *gphy_reset2;
+ void __iomem *membase;
+ char *fw_name;
+};
+
+struct xway_gphy_match_data {
+ char *fe_firmware_name;
+ char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+ { .compatible = "lantiq,xrx200-gphy", .data = NULL },
+ { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
+ { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
+ { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
+ { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
+ dma_addr_t *dev_addr)
+{
+ const struct firmware *fw;
+ void *fw_addr;
+ dma_addr_t dma_addr;
+ size_t size;
+ int ret;
+
+ ret = request_firmware(&fw, priv->fw_name, dev);
+ if (ret) {
+ dev_err(dev, "failed to load firmware: %s, error: %i\n",
+ priv->fw_name, ret);
+ return ret;
+ }
+
+ /*
+ * GPHY cores need the firmware code in a persistent and contiguous
+ * memory area with a 16 kB boundary aligned start address.
+ */
+ size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+ fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
+ if (fw_addr) {
+ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
+ *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+ memcpy(fw_addr, fw->data, fw->size);
+ } else {
+ dev_err(dev, "failed to alloc firmware memory\n");
+ ret = -ENOMEM;
+ }
+
+ release_firmware(fw);
+
+ return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+ struct xway_gphy_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+ const struct xway_gphy_match_data *gphy_fw_name_cfg;
+ u32 gphy_mode;
+ int ret;
+ struct resource *res_gphy;
+
+ gphy_fw_name_cfg = of_device_get_match_data(dev);
+
+ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
+ switch (ltq_soc_type()) {
+ case SOC_TYPE_VR9:
+ gphy_fw_name_cfg = &xrx200a1x_gphy_data;
+ break;
+ case SOC_TYPE_VR9_2:
+ gphy_fw_name_cfg = &xrx200a2x_gphy_data;
+ break;
+ }
+
+ priv->gphy_clk_gate = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->gphy_clk_gate)) {
+ dev_err(dev, "Failed to lookup gate clock\n");
+ return PTR_ERR(priv->gphy_clk_gate);
+ }
+
+ res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->membase = devm_ioremap_resource(dev, res_gphy);
+ if (IS_ERR(priv->membase))
+ return PTR_ERR(priv->membase);
+
+ priv->gphy_reset = devm_reset_control_get(dev, "gphy");
+ if (IS_ERR(priv->gphy_reset)) {
+ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
+ dev_err(dev, "Failed to lookup gphy reset\n");
+ return PTR_ERR(priv->gphy_reset);
+ }
+
+ priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
+ if (IS_ERR(priv->gphy_reset2))
+ return PTR_ERR(priv->gphy_reset2);
+
+ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
+ /* Default to GE mode */
+ if (ret)
+ gphy_mode = GPHY_MODE_GE;
+
+ switch (gphy_mode) {
+ case GPHY_MODE_FE:
+ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+ break;
+ case GPHY_MODE_GE:
+ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+ break;
+ default:
+ dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct xway_gphy_priv *priv;
+ dma_addr_t fw_addr = 0;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = xway_gphy_of_probe(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->gphy_clk_gate);
+ if (ret)
+ return ret;
+
+ ret = xway_gphy_load(dev, priv, &fw_addr);
+ if (ret) {
+ clk_disable_unprepare(priv->gphy_clk_gate);
+ return ret;
+ }
+
+ reset_control_assert(priv->gphy_reset);
+ reset_control_assert(priv->gphy_reset2);
+
+ iowrite32be(fw_addr, priv->membase);
+
+ reset_control_deassert(priv->gphy_reset);
+ reset_control_deassert(priv->gphy_reset2);
+
+ platform_set_drvdata(pdev, priv);
+
+ return ret;
+}
+
+static int xway_gphy_remove(struct platform_device *pdev)
+{
+ struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
+
+ iowrite32be(0, priv->membase);
+
+ clk_disable_unprepare(priv->gphy_clk_gate);
+
+ return 0;
+}
+
+static struct platform_driver xway_gphy_driver = {
+ .probe = xway_gphy_probe,
+ .remove = xway_gphy_remove,
+ .driver = {
+ .name = "xway-rcu-gphy",
+ .of_match_table = xway_gphy_match,
+ },
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");

60
target/linux/lantiq/xrx200/base-files/etc/board.d/02_network
View File

@ -11,65 +11,41 @@ lantiq_setup_interfaces()
local board="$1"
case "$board" in
alphanetworks,asl56026)
ucidef_add_switch "switch0" \
"2:lan" "3:lan" "6t@eth0"
alphanetworks,asl56026|\
arcadyan,vg3503j)
ucidef_set_interface_lan "lan1 lan2"
;;
arcadyan,arv7519rw22)
ucidef_add_switch "switch0" \
"0:lan:5" "2:lan:3" "3:lan:4" "4:lan:1" "5:lan:2" "6t@eth0"
;;
arcadyan,vg3503j)
ucidef_add_switch "switch0" \
"2:lan:2" "4:lan:1" "6t@eth0"
ucidef_set_interface_lan "lan1 lan2 lan3 lan4 lan5"
;;
arcadyan,vgv7510kw22-brn|\
arcadyan,vgv7510kw22-nor)
ucidef_add_switch "switch0" \
"2:lan:2" "3:lan:1" "4:lan:4" "5:lan:3" "0:wan:5" "6t@eth0"
;;
arcadyan,vgv7510kw22-nor|\
arcadyan,vgv7519-brn|\
arcadyan,vgv7519-nor|\
bt,homehub-v5a|\
lantiq,easy80920-nand|\
lantiq,easy80920-nor)
ucidef_add_switch "switch0" \
"0:lan:4" "1:lan:3" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0"
lantiq,easy80920-nor|\
zyxel,p-2812hnu-f1|\
zyxel,p-2812hnu-f3)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
avm,fritz3370-rev2-hynix|\
avm,fritz3370-rev2-micron|\
avm,fritz3390|\
avm,fritz7360sl|\
avm,fritz7360-v2|\
avm,fritz7362sl)
ucidef_add_switch "switch0" \
"0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "6t@eth0"
;;
avm,fritz7430)
ucidef_add_switch "switch0" \
"2:lan:3" "3:lan:4" "4:lan:1" "5:lan:2" "6t@eth0"
;;
bt,homehub-v5a)
ucidef_add_switch "switch0" \
"0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0"
;;
buffalo,wbmr-300hpd)
ucidef_add_switch "switch0" \
"5:lan:2" "2:lan:3" "3:lan:4" "4:wan:1" "6t@eth0"
;;
avm,fritz7362sl|\
avm,fritz7430|\
buffalo,wbmr-300hpd|\
tplink,tdw8970|\
tplink,tdw8980)
ucidef_add_switch "switch0" \
"0:lan:2" "2:lan:3" "4:lan:4" "5:lan:1" "6t@eth0"
;;
tplink,tdw8980|\
tplink,vr200|\
tplink,vr200v)
ucidef_add_switch "switch0" \
"0:lan" "2:lan" "4:lan" "5:lan" "6t@eth0"
ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
;;
zyxel,p-2812hnu-f1|\
zyxel,p-2812hnu-f3)
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "4:lan" "5:wan" "6t@eth0"
avm,fritz7412|\
netgear,dm200)
ucidef_set_interface_lan "lan"
;;
*)
ucidef_set_interface_lan 'eth0'

18
target/linux/lantiq/xrx200/base-files/etc/board.d/05_compat-version Normal file
View File

@ -0,0 +1,18 @@
#
# Copyright (C) 2020 OpenWrt.org
#
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
*)
ucidef_set_compat_version "1.1"
;;
esac
board_config_flush
exit 0

10
target/linux/lantiq/xrx200/config-5.10
View File

@ -18,6 +18,7 @@ CONFIG_CRYPTO_ZSTD=y
CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
CONFIG_EXTRA_FIRMWARE_DIR="firmware"
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GRO_CELLS=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_ICPLUS_PHY=y
@ -27,7 +28,7 @@ CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_POLLDEV=y
CONFIG_INTEL_XWAY_PHY=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_XRX200_LEGACY=y
CONFIG_LANTIQ_XRX200=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MIPS_MT=y
@ -50,7 +51,12 @@ CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_LANTIQ_GSWIP=y
CONFIG_NET_DSA_TAG_GSWIP=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NR_CPUS=2
CONFIG_PADATA=y
@ -77,7 +83,6 @@ CONFIG_SMP=y
CONFIG_SMP_UP=y
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SOC_XWAY=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SYNC_R4K=y
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
CONFIG_SYS_SUPPORTS_SMP=y
@ -88,7 +93,6 @@ CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_XPS=y
CONFIG_XRX200_PHY_FW=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

11
target/linux/lantiq/xrx200/config-5.4
View File

@ -17,6 +17,7 @@ CONFIG_CRYPTO_ZSTD=y
CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
CONFIG_EXTRA_FIRMWARE_DIR="firmware"
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GRO_CELLS=y
CONFIG_HWMON=y
CONFIG_ICPLUS_PHY=y
CONFIG_IFX_VPE_EXT=y
@ -25,7 +26,7 @@ CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_POLLDEV=y
CONFIG_INTEL_XWAY_PHY=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_XRX200_LEGACY=y
CONFIG_LANTIQ_XRX200=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MIPS_MT=y
@ -47,7 +48,12 @@ CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_LANTIQ_GSWIP=y
CONFIG_NET_DSA_TAG_GSWIP=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NR_CPUS=2
CONFIG_PADATA=y
@ -56,6 +62,7 @@ CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_LANTIQ=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_PHYLINK=y
CONFIG_PHY_LANTIQ_VRX200_PCIE=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_SUPPLY=y
@ -72,7 +79,6 @@ CONFIG_SENSORS_LTQ_CPUTEMP=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_UP=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SYNC_R4K=y
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
CONFIG_SYS_SUPPORTS_SMP=y
@ -83,7 +89,6 @@ CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_XPS=y
CONFIG_XRX200_PHY_FW=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

3
target/linux/lantiq/xrx200/target.mk
View File

@ -15,8 +15,7 @@ DEFAULT_PACKAGES+=kmod-leds-gpio \
ltq-vdsl-app \
dsl-vrx200-firmware-xdsl-a \
dsl-vrx200-firmware-xdsl-b-patch \
ppp-mod-pppoa \
swconfig
ppp-mod-pppoa
define Target/Description
Lantiq XRX200

5
target/linux/lantiq/xway/base-files/lib/preinit/05_set_preinit_iface_lantiq Normal file
View File

@ -0,0 +1,5 @@
set_preinit_iface() {
ifname=eth0
}
boot_hook_add preinit_main set_preinit_iface

1
target/linux/lantiq/xway/config-5.10
View File

@ -41,6 +41,7 @@ CONFIG_RTL8367_PHY=y
CONFIG_SGL_ALLOC=y
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SOC_XWAY=y
CONFIG_SWCONFIG=y
CONFIG_UBIFS_FS=y
CONFIG_USB=y
CONFIG_USB_COMMON=y

1
target/linux/lantiq/xway/config-5.4
View File

@ -37,6 +37,7 @@ CONFIG_RTL8366_SMI=y
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SGL_ALLOC=y
CONFIG_SWCONFIG=y
CONFIG_UBIFS_FS=y
CONFIG_USB=y
CONFIG_USB_COMMON=y

5
target/linux/lantiq/xway_legacy/base-files/lib/preinit/05_set_preinit_iface_lantiq Normal file
View File

@ -0,0 +1,5 @@
set_preinit_iface() {
ifname=eth0
}
boot_hook_add preinit_main set_preinit_iface

1
target/linux/lantiq/xway_legacy/config-5.10
View File

@ -32,6 +32,7 @@ CONFIG_RTL8367_PHY=y
CONFIG_SGL_ALLOC=y
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SOC_XWAY=y
CONFIG_SWCONFIG=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y

1
target/linux/lantiq/xway_legacy/config-5.4
View File

@ -30,6 +30,7 @@ CONFIG_RTL8366_SMI=y
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SGL_ALLOC=y
CONFIG_SWCONFIG=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y

2
target/linux/layerscape/patches-5.4/806-dma-0002-dmaengine-fsl-dpaa2-qdma-Add-NXP-dpaa2-qDMA-controll.patch
View File

@ -38,7 +38,7 @@ Signed-off-by: Peng Ma <peng.ma@nxp.com>
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -669,6 +669,8 @@ source "drivers/dma/sh/Kconfig"
@@ -670,6 +670,8 @@ source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"

2
target/linux/layerscape/patches-5.4/806-dma-0003-MLK-14610-DMA-fsl-edma-v3-add-fsl-edma-v3-support.patch
View File

@ -85,7 +85,7 @@ Signed-off-by: Robin Gong <yibin.gong@nxp.com>
+};
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -227,6 +227,17 @@ config FSL_QDMA
@@ -228,6 +228,17 @@ config FSL_QDMA
or dequeuing DMA jobs from, different work queues.
This module can be found on NXP Layerscape SoCs.
The qdma driver only work on SoCs with a DPAA hardware block.

4
target/linux/layerscape/patches-5.4/806-dma-0026-dma-caam-add-dma-memcpy-driver.patch
View File

@ -28,7 +28,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -131,6 +131,24 @@ config COH901318
@@ -132,6 +132,24 @@ config COH901318
help
Enable support for ST-Ericsson COH 901 318 DMA.
@ -53,7 +53,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
config DMA_BCM2835
tristate "BCM2835 DMA engine support"
depends on ARCH_BCM2835
@@ -662,7 +680,6 @@ config ZX_DMA
@@ -663,7 +681,6 @@ config ZX_DMA
help
Support the DMA engine for ZTE ZX family platform devices.

2
target/linux/layerscape/patches-5.4/820-usb-0005-usb-dwc3-add-otg-properties-update.patch
View File

@ -54,7 +54,7 @@ Signed-off-by: Peter Chen <peter.chen@nxp.com>
* All 3.1 IP version constants are greater than the 3.0 IP
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -3575,6 +3575,10 @@ int dwc3_gadget_init(struct dwc3 *dwc)
@@ -3578,6 +3578,10 @@ int dwc3_gadget_init(struct dwc3 *dwc)
dwc->gadget.sg_supported = true;
dwc->gadget.name = "dwc3-gadget";
dwc->gadget.lpm_capable = true;

2
target/linux/layerscape/patches-5.4/820-usb-0019-MLK-9829-usb-core-print-suggested-message-if-failed-.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Li Jun <jun.li@freescale.com>
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -4729,7 +4729,8 @@ hub_port_init(struct usb_hub *hub, struc
@@ -4731,7 +4731,8 @@ hub_port_init(struct usb_hub *hub, struc
}
if (r) {
if (r != -ENODEV)

2
target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
View File

@ -47,7 +47,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
@@ -1134,6 +1144,16 @@ static int mtk_tphy_probe(struct platfor
@@ -1136,6 +1146,16 @@ static int mtk_tphy_probe(struct platfor
&tphy->src_ref_clk);
device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);

2
target/linux/mediatek/patches-5.4/0001-v5.7-spi-make-spi-max-frequency-optional.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1803,13 +1803,8 @@ static int of_spi_parse_dt(struct spi_co
@@ -1809,13 +1809,8 @@ static int of_spi_parse_dt(struct spi_co
spi->mode |= SPI_CS_HIGH;
/* Device speed */

2
target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch
View File

@ -33,7 +33,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -337,6 +337,14 @@ static void advk_pcie_setup_hw(struct ad
@@ -338,6 +338,14 @@ static void advk_pcie_setup_hw(struct ad
reg |= PIO_CTRL_ADDR_WIN_DISABLE;
advk_writel(pcie, reg, PIO_CTRL);

54
target/linux/mvebu/patches-5.4/002-PCI-aardvark-Don-t-rely-on-jiffies-while-holding-spi.patch
View File

@ -1,54 +0,0 @@
From 7fbcb5da811be7d47468417c7795405058abb3da Mon Sep 17 00:00:00 2001
From: Remi Pommarel <repk@triplefau.lt>
Date: Fri, 27 Sep 2019 10:55:02 +0200
Subject: [PATCH] PCI: aardvark: Don't rely on jiffies while holding spinlock
advk_pcie_wait_pio() can be called while holding a spinlock (from
pci_bus_read_config_dword()), then depends on jiffies in order to
timeout while polling on PIO state registers. In the case the PIO
transaction failed, the timeout will never happen and will also cause
the cpu to stall.
This decrements a variable and wait instead of using jiffies.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
drivers/pci/controller/pci-aardvark.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -175,7 +175,8 @@
(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
-#define PIO_TIMEOUT_MS 1
+#define PIO_RETRY_CNT 500
+#define PIO_RETRY_DELAY 2 /* 2 us*/
#define LINK_WAIT_MAX_RETRIES 10
#define LINK_WAIT_USLEEP_MIN 90000
@@ -400,17 +401,16 @@ static void advk_pcie_check_pio_status(s
static int advk_pcie_wait_pio(struct advk_pcie *pcie)
{
struct device *dev = &pcie->pdev->dev;
- unsigned long timeout;
+ int i;
- timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
-
- while (time_before(jiffies, timeout)) {
+ for (i = 0; i < PIO_RETRY_CNT; i++) {
u32 start, isr;
start = advk_readl(pcie, PIO_START);
isr = advk_readl(pcie, PIO_ISR);
if (!start && isr)
return 0;
+ udelay(PIO_RETRY_DELAY);
}
dev_err(dev, "config read/write timed out\n");

2
target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch
View File

@ -193,7 +193,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
@@ -1035,6 +1093,12 @@ static int advk_pcie_probe(struct platfo
@@ -1066,6 +1124,12 @@ static int advk_pcie_probe(struct platfo
return ret;
}

2
target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch
View File

@ -98,7 +98,7 @@ Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* fundamental reset. As required by PCI Express spec a delay for at
* least 100ms after such a reset before link training is needed.
*/
@@ -1093,6 +1118,22 @@ static int advk_pcie_probe(struct platfo
@@ -1124,6 +1149,22 @@ static int advk_pcie_probe(struct platfo
return ret;
}

4
target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch
View File

@ -76,7 +76,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com>
/* Set to Direct mode */
reg = advk_readl(pcie, CTRL_CONFIG_REG);
reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
@@ -1083,6 +1092,62 @@ out_release_res:
@@ -1114,6 +1123,62 @@ out_release_res:
return err;
}
@ -139,7 +139,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com>
static int advk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1140,6 +1205,10 @@ static int advk_pcie_probe(struct platfo
@@ -1171,6 +1236,10 @@ static int advk_pcie_probe(struct platfo
else
pcie->link_gen = ret;

2
target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch
View File

@ -31,7 +31,7 @@ Cc: <stable@vger.kernel.org> # 5.8+: ea17a0f153af: phy: marvell: comphy: Convert
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1123,7 +1123,9 @@ static int advk_pcie_enable_phy(struct a
@@ -1154,7 +1154,9 @@ static int advk_pcie_enable_phy(struct a
}
ret = phy_power_on(pcie->phy);

2
target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
View File

@ -22,7 +22,7 @@ Signed-off-by: Tim Harvey <tharvey@gateworks.com>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/switchtec.h>
@@ -5625,3 +5626,34 @@ static void apex_pci_fixup_class(struct
@@ -5714,3 +5715,34 @@ static void apex_pci_fixup_class(struct
}
DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);