From d9d7286279157dfc3cfe010423566f7d2ce5d238 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 4 May 2024 03:01:39 +0100 Subject: [PATCH 1/6] rockchip: add driver for hardware RNG Rockchip SoCs used to have a random number generator as part of their crypto device, and support for it has to be added to the corresponding driver. Newer Rockchip SoCs like the RK3568 have an independent True Random Number Generator device. Import pending patchset which adds a driver for it, include it in Kconfig and enable it in the device tree. Doing so significantly reduces the time needed to boot devices based on those SoCs, from about 27 seconds until Ethernet is up and running to less than 13 seconds with a minimal snapshot image. Signed-off-by: Daniel Golle --- target/linux/rockchip/armv8/config-6.1 | 2 + ...-hwrng-add-Rockchip-SoC-hwrng-driver.patch | 339 ++++++++++++++++++ ...kchip-add-DT-entry-for-RNG-to-RK356x.patch | 56 +++ 3 files changed, 397 insertions(+) create mode 100644 target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch create mode 100644 target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1 index 1830a89c93..a1f79510d7 100644 --- a/target/linux/rockchip/armv8/config-6.1 +++ b/target/linux/rockchip/armv8/config-6.1 @@ -295,6 +295,8 @@ CONFIG_HUGETLB_PAGE=y CONFIG_HWMON=y CONFIG_HWSPINLOCK=y CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y diff --git a/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch b/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch new file mode 100644 index 0000000000..6a2d35889b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch @@ -0,0 +1,339 @@ +From patchwork Sat Nov 12 14:10:58 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Aurelien Jarno +X-Patchwork-Id: 13041222 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +From: Aurelien Jarno +To: Olivia Mackall , + Herbert Xu , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Lin Jinhan +Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR + CORE), + devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE + BINDINGS), + linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC + support), + linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), + linux-kernel@vger.kernel.org (open list), + Aurelien Jarno +Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver +Date: Sat, 12 Nov 2022 15:10:58 +0100 +Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net> +In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> +References: <20221112141059.3802506-1-aurelien@aurel32.net> +MIME-Version: 1.0 +List-Id: + +Rockchip SoCs used to have a random number generator as part of their +crypto device, and support for it has to be added to the corresponding +driver. However newer Rockchip SoCs like the RK356x have an independent +True Random Number Generator device. This patch adds a driver for it, +greatly inspired from the downstream driver. + +The TRNG device does not seem to have a signal conditionner and the FIPS +140-2 test returns a lot of failures. They can be reduced by increasing +RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value +has been adjusted to get ~90% of successes and the quality value has +been set accordingly. + +Signed-off-by: Aurelien Jarno +--- + drivers/char/hw_random/Kconfig | 14 ++ + drivers/char/hw_random/Makefile | 1 + + drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++ + 3 files changed, 266 insertions(+) + create mode 100644 drivers/char/hw_random/rockchip-rng.c + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -549,6 +549,20 @@ config HW_RANDOM_CN10K + To compile this driver as a module, choose M here. + The module will be called cn10k_rng. If unsure, say Y. + ++config HW_RANDOM_ROCKCHIP ++ tristate "Rockchip True Random Number Generator" ++ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST) ++ depends on HAS_IOMEM ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the True Random Number ++ Generator hardware found on some Rockchip SoC like RK3566 or RK3568. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. ++ ++ If unsure, say Y. ++ + endif # HW_RANDOM + + config UML_RANDOM +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -47,3 +47,4 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe + obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o + obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o + obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o ++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o +--- /dev/null ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -0,0 +1,251 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2022, Aurelien Jarno ++ * Authors: ++ * Lin Jinhan ++ * Aurelien Jarno ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RK_RNG_AUTOSUSPEND_DELAY 100 ++#define RK_RNG_MAX_BYTE 32 ++#define RK_RNG_POLL_PERIOD_US 100 ++#define RK_RNG_POLL_TIMEOUT_US 10000 ++ ++/* ++ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is ++ * a tradeoff between speed and quality and has been adjusted to get a quality ++ * of ~900 (~90% of FIPS 140-2 successes). ++ */ ++#define RK_RNG_SAMPLE_CNT 1000 ++ ++/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ ++#define TRNG_RST_CTL 0x0004 ++#define TRNG_RNG_CTL 0x0400 ++#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4) ++#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4) ++#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4) ++#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2) ++#define TRNG_RNG_CTL_ENABLE BIT(1) ++#define TRNG_RNG_CTL_START BIT(0) ++#define TRNG_RNG_SAMPLE_CNT 0x0404 ++#define TRNG_RNG_DOUT_0 0x0410 ++#define TRNG_RNG_DOUT_1 0x0414 ++#define TRNG_RNG_DOUT_2 0x0418 ++#define TRNG_RNG_DOUT_3 0x041c ++#define TRNG_RNG_DOUT_4 0x0420 ++#define TRNG_RNG_DOUT_5 0x0424 ++#define TRNG_RNG_DOUT_6 0x0428 ++#define TRNG_RNG_DOUT_7 0x042c ++ ++struct rk_rng { ++ struct hwrng rng; ++ void __iomem *base; ++ struct reset_control *rst; ++ int clk_num; ++ struct clk_bulk_data *clk_bulks; ++}; ++ ++/* The mask determine the bits that are updated */ ++static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) ++{ ++ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL); ++} ++ ++static int rk_rng_init(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ int ret; ++ ++ /* start clocks */ ++ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); ++ if (ret < 0) { ++ dev_err((struct device *) rk_rng->rng.priv, ++ "Failed to enable clks %d\n", ret); ++ return ret; ++ } ++ ++ /* set the sample period */ ++ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); ++ ++ /* set osc ring speed and enable it */ ++ reg = TRNG_RNG_CTL_LEN_256_BIT | ++ TRNG_RNG_CTL_OSC_RING_SPEED_0 | ++ TRNG_RNG_CTL_ENABLE; ++ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ ++ return 0; ++} ++ ++static void rk_rng_cleanup(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ ++ /* stop TRNG */ ++ reg = 0; ++ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ ++ /* stop clocks */ ++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); ++} ++ ++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ int ret = 0; ++ int i; ++ ++ pm_runtime_get_sync((struct device *) rk_rng->rng.priv); ++ ++ /* Start collecting random data */ ++ reg = TRNG_RNG_CTL_START; ++ rk_rng_write_ctl(rk_rng, reg, reg); ++ ++ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg, ++ !(reg & TRNG_RNG_CTL_START), ++ RK_RNG_POLL_PERIOD_US, ++ RK_RNG_POLL_TIMEOUT_US); ++ if (ret < 0) ++ goto out; ++ ++ /* Read random data stored in big endian in the registers */ ++ ret = min_t(size_t, max, RK_RNG_MAX_BYTE); ++ for (i = 0; i < ret; i += 4) { ++ reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i); ++ *(u32 *)(buf + i) = be32_to_cpu(reg); ++ } ++ ++out: ++ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); ++ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); ++ ++ return ret; ++} ++ ++static int rk_rng_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rk_rng *rk_rng; ++ int ret; ++ ++ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL); ++ if (!rk_rng) ++ return -ENOMEM; ++ ++ rk_rng->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rk_rng->base)) ++ return PTR_ERR(rk_rng->base); ++ ++ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks); ++ if (rk_rng->clk_num < 0) ++ return dev_err_probe(dev, rk_rng->clk_num, ++ "Failed to get clks property\n"); ++ ++ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false); ++ if (IS_ERR(rk_rng->rst)) ++ return dev_err_probe(dev, PTR_ERR(rk_rng->rst), ++ "Failed to get reset property\n"); ++ ++ reset_control_assert(rk_rng->rst); ++ udelay(2); ++ reset_control_deassert(rk_rng->rst); ++ ++ platform_set_drvdata(pdev, rk_rng); ++ ++ rk_rng->rng.name = dev_driver_string(dev); ++#ifndef CONFIG_PM ++ rk_rng->rng.init = rk_rng_init; ++ rk_rng->rng.cleanup = rk_rng_cleanup; ++#endif ++ rk_rng->rng.read = rk_rng_read; ++ rk_rng->rng.priv = (unsigned long) dev; ++ rk_rng->rng.quality = 900; ++ ++ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); ++ pm_runtime_use_autosuspend(dev); ++ pm_runtime_enable(dev); ++ ++ ret = devm_hwrng_register(dev, &rk_rng->rng); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); ++ ++ dev_info(&pdev->dev, "Registered Rockchip hwrng\n"); ++ ++ return 0; ++} ++ ++static int rk_rng_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int rk_rng_runtime_suspend(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ rk_rng_cleanup(&rk_rng->rng); ++ ++ return 0; ++} ++ ++static int rk_rng_runtime_resume(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ return rk_rng_init(&rk_rng->rng); ++} ++#endif ++ ++static const struct dev_pm_ops rk_rng_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, ++ rk_rng_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++}; ++ ++static const struct of_device_id rk_rng_dt_match[] = { ++ { ++ .compatible = "rockchip,rk3568-rng", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, rk_rng_dt_match); ++ ++static struct platform_driver rk_rng_driver = { ++ .driver = { ++ .name = "rockchip-rng", ++ .pm = &rk_rng_pm_ops, ++ .of_match_table = rk_rng_dt_match, ++ }, ++ .probe = rk_rng_probe, ++ .remove = rk_rng_remove, ++}; ++ ++module_platform_driver(rk_rng_driver); ++ ++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver"); ++MODULE_AUTHOR("Lin Jinhan , Aurelien Jarno "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch b/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch new file mode 100644 index 0000000000..bb34ba76e0 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch @@ -0,0 +1,56 @@ +From patchwork Sat Nov 12 14:10:59 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Aurelien Jarno +X-Patchwork-Id: 13041221 +From: Aurelien Jarno +To: Olivia Mackall , + Herbert Xu , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Lin Jinhan +Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR + CORE), + devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE + BINDINGS), + linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC + support), + linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), + linux-kernel@vger.kernel.org (open list), + Aurelien Jarno +Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x +Date: Sat, 12 Nov 2022 15:10:59 +0100 +Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net> +In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> +References: <20221112141059.3802506-1-aurelien@aurel32.net> +MIME-Version: 1.0 +List-Id: + +Enable the just added Rockchip RNG driver for RK356x SoCs. + +Signed-off-by: Aurelien Jarno +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1773,6 +1773,15 @@ + }; + }; + ++ rng: rng@fe388000 { ++ compatible = "rockchip,rk3568-rng"; ++ reg = <0x0 0xfe388000 0x0 0x4000>; ++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; ++ clock-names = "trng_clk", "trng_hclk"; ++ resets = <&cru SRST_TRNG_NS>; ++ reset-names = "reset"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; From 6b3195ae62091fc224500e50661ccdc9651376fc Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 28 Apr 2024 22:05:23 +0200 Subject: [PATCH 2/6] toolchain: glibc: Update glibc 2.38 to recent HEAD 23514c72b7 syslog: Fix heap buffer overflow in __vsyslog_internal (CVE-2023-6246) d0338312aa syslog: Fix heap buffer overflow in __vsyslog_internal (CVE-2023-6779) d37c2b20a4 syslog: Fix integer overflow in __vsyslog_internal (CVE-2023-6780) 30e546d76e x86_64: Optimize ffsll function code size. 18876c9ff5 S390: Fix building with --disable-mutli-arch [BZ #31196] 6f68075869 sparc: Fix broken memset for sparc32 [BZ #31068] 0e383d2d4e sparc64: Remove unwind information from signal return stubs [BZ#31244] aac57faf54 sparc: Fix sparc64 memmove length comparison (BZ 31266) 0c5e5bace5 sparc: Remove unwind information from signal return stubs [BZ #31244] b09073e631 arm: Remove wrong ldr from _dl_start_user (BZ 31339) 506e47da1d malloc: Use __get_nprocs on arena_get2 (BZ 30945) ee4806e978 S390: Do not clobber r7 in clone [BZ #31402] 5753cda1ca linux: Use rseq area unconditionally in sched_getcpu (bug 31479) 0518bb0c16 LoongArch: Correct {__ieee754, _}_scalb -> {__ieee754, _}_scalbf 5456ff5d80 Add HWCAP2_MOPS from Linux 6.5 to AArch64 bits/hwcap.h d8a2b56b4f AArch64: Add support for MOPS memcpy/memmove/memset 25b66e8c4a AArch64: Cleanup ifuncs 1521237c32 AArch64: Cleanup emag memset 156e44845f AArch64: Add memset_zva64 a08ff92294 AArch64: Remove Falkor memcpy 168ae58e6e aarch64: correct CFI in rawmemchr (bug 31113) 1bf17ce978 aarch64: fix check for SVE support in assembler 92da7c2cfe AArch64: Check kernel version for SVE ifuncs 20534f8176 powerpc: Fix ld.so address determination for PCREL mode (bug 31640) e1135387de iconv: ISO-2022-CN-EXT: fix out-of-bound writes when writing escape sequence (CVE-2024-2961) 61484011e7 sparc: Remove 64 bit check on sparc32 wordsize (BZ 27574) 78d9f91da6 login: Check default sizes of structs utmp, utmpx, lastlog 68bff88592 login: structs utmp, utmpx, lastlog _TIME_BITS independence (bug 30701) decc9f504a nptl: Fix tst-cancel30 on kernels without ppoll_time64 support 29e20bd122 i386: ulp update for SSE2 --disable-multi-arch configurations 5968aebb86 CVE-2024-33599: nscd: Stack-based buffer overflow in netgroup cache (bug 31677) 541ea5172a CVE-2024-33600: nscd: Do not send missing not-found response in addgetnetgrentX (bug 31678) 2ae9446c1b CVE-2024-33600: nscd: Avoid null pointer crashes after notfound response (bug 31678) 71af8ca864 CVE-2024-33601, CVE-2024-33602: nscd: netgroup: Use two buffers in addgetnetgrentX (bug 31680) e9f05fa1c6 elf: Also compile dl-misc.os with $(rtld-early-cflags) Signed-off-by: Hauke Mehrtens --- toolchain/glibc/common.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/toolchain/glibc/common.mk b/toolchain/glibc/common.mk index 79a7a0131d..28beda04eb 100644 --- a/toolchain/glibc/common.mk +++ b/toolchain/glibc/common.mk @@ -12,8 +12,8 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE_VERSION:=cfe121910013a46e2477562282c56ae8062089aa -PKG_MIRROR_HASH:=99b9beb283d644caacea12fe87dd7f0a0141ff26349ee500a78047aba3f5be5c +PKG_SOURCE_VERSION:=e9f05fa1c62c8044ff025963498063f73eb51c5f +PKG_MIRROR_HASH:=fd61eb2caea0d4100638b8aa8285b0f1bc23af921c376516307c9ab8ac307739 PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.zst PKG_CPE_ID:=cpe:/a:gnu:glibc From 4a6e3e1bc85111b787472148322c51329256be1e Mon Sep 17 00:00:00 2001 From: Antonio Flores Date: Thu, 11 Apr 2024 11:10:40 -0400 Subject: [PATCH 3/6] uboot-rockchip: add Bananapi-R2 Pro support add uboot support for Bananapi-R2 Pro Signed-off-by: Antonio Flores --- package/boot/uboot-rockchip/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 863d0157f4..844f59e9f6 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -151,6 +151,13 @@ define U-Boot/rk3568/Default TPL:=rk3568_ddr_1560MHz_v1.21.bin endef +define U-Boot/bpi-r2-pro-rk3568 + $(U-Boot/rk3568/Default) + NAME:=Bananapi-R2 Pro + BUILD_DEVICES:= \ + sinovoip_bpi-r2-pro +endef + define U-Boot/nanopi-r5c-rk3568 $(U-Boot/rk3568/Default) NAME:=NanoPi R5C @@ -186,6 +193,7 @@ UBOOT_TARGETS := \ rock64-rk3328 \ rock-pi-e-rk3328 \ radxa-cm3-io-rk3566 \ + bpi-r2-pro-rk3568 \ nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 \ radxa-e25-rk3568 From 298e11e43ddaff226cf381560aec253f9790e395 Mon Sep 17 00:00:00 2001 From: Antonio Flores Date: Thu, 11 Apr 2024 14:51:37 -0400 Subject: [PATCH 4/6] rockchip: enable MT7531 and RTC drivers This patch enable MT7531 switch and RTC drivers for BPI-R2 Pro. Signed-off-by: Antonio Flores --- target/linux/rockchip/armv8/config-6.1 | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1 index a1f79510d7..6337245ff8 100644 --- a/target/linux/rockchip/armv8/config-6.1 +++ b/target/linux/rockchip/armv8/config-6.1 @@ -365,6 +365,7 @@ CONFIG_MDIO_BUS_MUX_GPIO=y CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y +CONFIG_MEDIATEK_GE_PHY=y CONFIG_MEMFD_CREATE=y CONFIG_MEMORY_ISOLATION=y CONFIG_MFD_CORE=y @@ -401,9 +402,16 @@ CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +CONFIG_NET_DSA_MT7530_MMIO=y +CONFIG_NET_DSA_TAG_MTK=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y CONFIG_NLS=y CONFIG_NLS_ISO8859_1=y CONFIG_NOP_USB_XCEIV=y @@ -458,6 +466,7 @@ CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_STUB=y +CONFIG_PCS_MTK_LYNXI=y CONFIG_PCS_XPCS=y CONFIG_PGTABLE_LEVELS=4 CONFIG_PHYLIB=y @@ -550,6 +559,7 @@ CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_HYM8563=y CONFIG_RTC_DRV_RK808=y CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_NVMEM=y From cfb7df2991d9b9580d9c14b482813214bddbe125 Mon Sep 17 00:00:00 2001 From: Antonio Flores Date: Thu, 11 Apr 2024 14:43:06 -0400 Subject: [PATCH 5/6] kernel: add kmod-ata-ahci-dwc Add kmod-ata-ahci-dwc for the rockchip target. https://github.com/torvalds/linux/commit/33629d35090f5ce2b1b4ce78aa39954c603536d5 Signed-off-by: Antonio Flores --- package/kernel/linux/modules/block.mk | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/package/kernel/linux/modules/block.mk b/package/kernel/linux/modules/block.mk index 4f3a6e085f..3dbeca9f9f 100644 --- a/package/kernel/linux/modules/block.mk +++ b/package/kernel/linux/modules/block.mk @@ -89,6 +89,18 @@ endef $(eval $(call KernelPackage,ata-artop)) +define KernelPackage/ata-ahci-dwc + TITLE:=Synopsys DWC AHCI SATA + KCONFIG:= \ + CONFIG_AHCI_DWC \ + CONFIG_SATA_HOST=y + FILES:=$(LINUX_DIR)/drivers/ata/ahci_dwc.ko + DEPENDS:=+kmod-ata-ahci-platform + AUTOLOAD:=$(call AutoLoad,41,ahci_dwc,1) + $(call AddDepends/ata,@TARGET_rockchip) +endef + +$(eval $(call KernelPackage,ata-ahci-dwc)) define KernelPackage/ata-nvidia-sata TITLE:=Nvidia Serial ATA support From 4ebcc5375a5f3610164a3b605437b4392f021454 Mon Sep 17 00:00:00 2001 From: Antonio Flores Date: Thu, 11 Apr 2024 12:35:00 -0400 Subject: [PATCH 6/6] rockchip: add Bananapi-R2 Pro board support Hardware spec: - Rockchip RK3568 Quad-core ARM Cortex-A55 CPU 2GHz - GPU Mali-G52 1-Core-2EE OpenGL ES3.2 Vu1kn 1.1 OpenCL 2.0 - Memory2G DDR3 SDRAM (option 4G) - Storage Onboard 16GB eMMC Flash, Micro SD-Card slot, SATA 3.0 Port,SPI flash - Network 5 x 10/100/1000 Mbit/s Ethernet MT7531 - Display 1 HDMI port, 2 DSI interface(1 DSI can change to LVDS by software) - Camera 1 CSI camera interface - Audio Output HDMI & I2S & Speaker & Headphone - USB port USB 3.0 PORT (x2), micro USB OTG (x1) - PCIE 1 mini pcie interface & 1 M.2 key-e interface - Remote IR Receiver (x1) - GPIO 40 Pin Header : GPIO (x28) and Power (+5V, +3.3V and GND). - Switches Reset button, Power button, U-boot button - LED Power Status - Power Source 12 volt 2A via DC Power Installation: Uncompress the OpenWrt sysupgrade and write image to the SD card using dd (dd if=*.img of=/*) Boot from the SD card 1-hold down the MaskRom button 2-Connect DC power 3-Wait 5 seconds, release the button. eMMC Installation: 1-Uncompress the OpenWrt sysupgrade image 2-fash to eMMC dd if=openwrt-rockchip-armv8-sinovoip_bpi-r2-pro-squashfs-sysupgrade.img of=/dev/mmcblk1 sync 3-remove SD card reboot Signed-off-by: Antonio Flores --- .../armv8/base-files/etc/board.d/02_network | 6 ++- .../etc/hotplug.d/net/40-net-smp-affinity | 3 +- target/linux/rockchip/image/armv8.mk | 9 +++++ ...ip-adjust-vendor-on-Banana-Pi-R2-Pro.patch | 27 +++++++++++++ ...ip-set-PHY-address-of-MT7531-switch-.patch | 40 +++++++++++++++++++ ...ip-regulator-for-sd-needs-to-be-alwa.patch | 33 +++++++++++++++ 6 files changed, 116 insertions(+), 2 deletions(-) create mode 100644 target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch create mode 100644 target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch create mode 100644 target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index d6e97b91fa..8729bd52f2 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -23,6 +23,9 @@ rockchip_setup_interfaces() friendlyarm,nanopi-r5s) ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' ;; + sinovoip,rk3568-bpi-r2pro) + ucidef_set_interfaces_lan_wan 'lan0 lan1 lan2 lan3' 'eth0' + ;; *) ucidef_set_interface_lan 'eth0' ;; @@ -44,7 +47,8 @@ rockchip_setup_macs() ;; friendlyarm,nanopi-r2c-plus|\ friendlyarm,nanopi-r4s|\ - friendlyarm,nanopi-r5s) + friendlyarm,nanopi-r5s|\ + sinovoip,rk3568-bpi-r2pro) wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1) lan_mac=$(macaddr_add "$wan_mac" 1) ;; diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 5753d1e856..8bbce1c328 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -44,7 +44,8 @@ friendlyarm,nanopi-r4s-enterprise) set_interface_core 20 "eth1" ;; friendlyarm,nanopi-r5c|\ -radxa,e25) +radxa,e25|\ +sinovoip,rk3568-bpi-r2pro) set_interface_core 2 "eth0" set_interface_core 4 "eth1" ;; diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index d457058282..df0ca6ffb5 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -130,6 +130,15 @@ define Device/radxa_rock-pi-e endef TARGET_DEVICES += radxa_rock-pi-e +define Device/sinovoip_bpi-r2-pro + DEVICE_VENDOR := Sinovoip + DEVICE_MODEL := Bananapi-R2 Pro + SOC := rk3568 + SUPPORTED_DEVICES := sinovoip,rk3568-bpi-r2pro + DEVICE_PACKAGES := kmod-ata-ahci-dwc +endef +TARGET_DEVICES += sinovoip_bpi-r2-pro + define Device/xunlong_orangepi-r1-plus DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi R1 Plus diff --git a/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch new file mode 100644 index 0000000000..9be609f661 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch @@ -0,0 +1,27 @@ +From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Wed, 14 Feb 2024 15:07:30 +1100 +Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board + +Adjust compatible string to match the board vendor of Sinovoip + +Signed-off-by: Tim Lunn +Reviewed-by: Dragan Simic +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -13,7 +13,7 @@ + + / { + model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; +- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; ++ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; diff --git a/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch b/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch new file mode 100644 index 0000000000..6a5622b813 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch @@ -0,0 +1,40 @@ +From a2ac2a1b02590a22a236c43c455f421cdede45f5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Thu, 14 Mar 2024 15:24:35 +0300 +Subject: [PATCH] arm64: dts: rockchip: set PHY address of MT7531 switch to + 0x1f +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7531 switch listens on PHY address 0x1f on an MDIO bus. I've got two +findings that support this. There's no bootstrapping option to change the +PHY address of the switch. The Linux driver hardcodes 0x1f as the PHY +address of the switch. So the reg property on the device tree is currently +ignored by the Linux driver. + +Therefore, describe the correct PHY address on Banana Pi BPI-R2 Pro that +has this switch. + +Signed-off-by: Arınç ÜNAL +Fixes: c1804463e5c6 ("arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro board") +Link: https://lore.kernel.org/r/20240314-for-rockchip-mt7531-phy-address-v1-1-743b5873358f@arinc9.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -521,9 +521,9 @@ + #address-cells = <1>; + #size-cells = <0>; + +- switch@0 { ++ switch@1f { + compatible = "mediatek,mt7531"; +- reg = <0>; ++ reg = <0x1f>; + + ports { + #address-cells = <1>; diff --git a/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch b/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch new file mode 100644 index 0000000000..dca18f5c58 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch @@ -0,0 +1,33 @@ +From 433d54818f64a2fe0562f8c04c7a81f562368515 Mon Sep 17 00:00:00 2001 +From: Jose Ignacio Tornos Martinez +Date: Tue, 5 Mar 2024 15:32:18 +0100 +Subject: [PATCH] arm64: dts: rockchip: regulator for sd needs to be always on + for BPI-R2Pro + +With default dts configuration for BPI-R2Pro, the regulator for sd card is +powered off when reboot is commanded, and the only solution to detect the +sd card again, and therefore, allow rebooting from there, is to do a +hardware reset. + +Configure the regulator for sd to be always on for BPI-R2Pro in order to +avoid this issue. + +Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro") +Signed-off-by: Jose Ignacio Tornos Martinez +Link: https://lore.kernel.org/r/20240305143222.189413-1-jtornosm@redhat.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -412,6 +412,8 @@ + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; +