From caf22aa4ce3c1298f4e82d7d3f145545716e49ac Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Thu, 16 Apr 2020 18:09:15 +0800 Subject: [PATCH] apm821xx/archs38/armvirt/gemini/imx6/kirkwood/lantiq/malta: add kernel 5.4 support --- .../files/lib/functions/migrations.sh | 39 + target/linux/apm821xx/Makefile | 1 + .../base-files/lib/preinit/79_move_config | 3 +- target/linux/apm821xx/config-4.19 | 3 - target/linux/apm821xx/config-5.4 | 345 ++ .../linux/apm821xx/dts/netgear-wndr4700.dts | 33 +- target/linux/apm821xx/dts/wd-mybooklive.dts | 10 + target/linux/apm821xx/image/Makefile | 26 +- .../linux/apm821xx/image/mbl_gen_hdd_img.sh | 4 +- target/linux/apm821xx/nand/config-default | 3 + ...rypto4xx-reduce-memory-fragmentation.patch | 99 + ...x-use-GFP_KERNEL-for-big-allocations.patch | 72 + .../201-add-amcc-apollo3g-support.patch | 30 + .../202-add-netgear-wndr4700-support.patch | 32 + .../300-fix-atheros-nics-on-apm82181.patch | 51 + .../301-fix-memory-map-wndr4700.patch | 14 + ...mware-loader-for-uPD720201-and-uPD72.patch | 1026 +++ .../802-usb-xhci-force-msi-renesas-xhci.patch | 53 + ...03-hwmon-tc654-add-detection-routine.patch | 65 + ...mon-tc654-add-thermal_cooling-device.patch | 174 + ...per-force-gzip-as-mkimage-s-compress.patch | 29 + target/linux/apm821xx/sata/target.mk | 2 +- target/linux/archs38/Makefile | 1 + target/linux/archs38/config-5.4 | 285 + .../archs38/image/gen_axs10x_sdcard_img.sh | 4 +- ...h-arc-Add-compiler-option-for-gcc8.4.patch | 21 + .../32/{config-default => config-4.19} | 28 +- target/linux/armvirt/32/config-5.4 | 95 + .../64/{config-default => config-4.19} | 152 +- target/linux/armvirt/64/config-5.4 | 261 + target/linux/armvirt/Makefile | 5 +- target/linux/armvirt/config-4.19 | 222 + target/linux/armvirt/config-5.4 | 240 + target/linux/armvirt/image/Makefile | 10 +- target/linux/gemini/Makefile | 1 + target/linux/gemini/config-4.19 | 1 - target/linux/gemini/config-5.4 | 466 ++ target/linux/gemini/image/Makefile | 7 +- .../linux/gemini/image/dns313_gen_hdd_img.sh | 2 +- ...t-fotg2-add-Gemini-specific-handling.patch | 131 + ...-DIR-685-partition-table-for-OpenWrt.patch | 37 + ...0003-ARM-dts-gemini-Rename-IDE-nodes.patch | 117 + ...s-gemini-Add-thermal-zone-to-DIR-685.patch | 101 + target/linux/imx6/Makefile | 3 +- .../imx6/base-files/etc/board.d/02_network | 18 +- target/linux/imx6/base-files/lib/imx6.sh | 20 + .../base-files/lib/preinit/79_move_config | 1 + .../imx6/base-files/lib/upgrade/platform.sh | 22 +- target/linux/imx6/config-4.19 | 4 - target/linux/imx6/config-5.4 | 720 +++ .../files/firmware/imx/sdma/sdma-imx6q.bin | Bin 2718 -> 2746 bytes target/linux/imx6/image/Makefile | 37 +- target/linux/imx6/image/bootscript-apalis | 7 +- target/linux/imx6/image/bootscript-ventana | 34 +- target/linux/imx6/image/recovery-apalis | 1 + ...ARM-dts-imx-Add-GW5907-board-support.patch | 18 +- ...ARM-dts-imx-Add-GW5910-board-support.patch | 18 +- ...ARM-dts-imx-Add-GW5913-board-support.patch | 18 +- ...ARM-dts-imx-Add-GW5912-board-support.patch | 18 +- ...ARM-dts-imx-Add-GW5907-board-support.patch | 482 ++ ...ARM-dts-imx-Add-GW5910-board-support.patch | 583 ++ ...ARM-dts-imx-Add-GW5913-board-support.patch | 435 ++ ...ARM-dts-imx-Add-GW5912-board-support.patch | 551 ++ ...gw553x-add-lsm9ds1-iio-imu-magn-supp.patch | 68 + .../linux/imx6/patches-5.4/100-bootargs.patch | 11 + .../301-apalis-ixora-dts-leds.patch | 86 + .../302-apalis-ixora-dts-reset-button.patch | 76 + target/linux/kirkwood/Makefile | 3 +- .../base-files/etc/init.d/hwmon_fancontrol | 33 +- target/linux/kirkwood/config-4.14 | 3 +- target/linux/kirkwood/config-4.19 | 3 +- target/linux/kirkwood/config-5.4 | 359 ++ .../arch/arm/boot/dts/kirkwood-goflexhome.dts | 124 + .../arm/boot/dts/kirkwood-linksys-audi.dts | 250 + .../arch/arm/boot/dts/kirkwood-nsa310b.dts | 132 + .../arch/arm/boot/dts/kirkwood-on100.dts | 165 + .../arch/arm/boot/dts/kirkwood-goflexhome.dts | 135 + .../arm/boot/dts/kirkwood-linksys-audi.dts | 207 + .../arch/arm/boot/dts/kirkwood-nsa310b.dts | 141 + .../arch/arm/boot/dts/kirkwood-on100.dts | 165 + .../arch/arm/boot/dts/kirkwood-goflexhome.dts | 135 + .../arm/boot/dts/kirkwood-linksys-audi.dts | 207 + .../arch/arm/boot/dts/kirkwood-nsa310b.dts | 141 + .../arch/arm/boot/dts/kirkwood-on100.dts | 165 + target/linux/kirkwood/image/Makefile | 89 +- .../kirkwood/patches-4.14/100-ib62x0.patch | 27 +- .../kirkwood/patches-4.14/101-iconnect.patch | 34 +- .../kirkwood/patches-4.14/102-dockstar.patch | 32 +- .../patches-4.14/103-iomega-ix2-200.patch | 38 +- .../kirkwood/patches-4.14/104-ea3500.patch | 258 - .../kirkwood/patches-4.14/105-ea4500.patch | 31 +- .../patches-4.14/105-goflexhome.patch | 130 - .../kirkwood/patches-4.14/106-goflexnet.patch | 32 +- .../patches-4.14/107-02-nsa310b.patch | 147 - .../kirkwood/patches-4.14/107-03-nsa325.patch | 31 + .../kirkwood/patches-4.14/108-on100.patch | 173 - .../patches-4.14/109-pogoplug_v4.patch | 34 +- .../kirkwood/patches-4.14/110-pogo_e02.patch | 68 + .../kirkwood/patches-4.19/100-ib62x0.patch | 27 +- .../kirkwood/patches-4.19/101-iconnect.patch | 34 +- .../kirkwood/patches-4.19/102-dockstar.patch | 32 +- .../patches-4.19/103-iomega-ix2-200.patch | 38 +- .../kirkwood/patches-4.19/104-ea3500.patch | 259 - .../kirkwood/patches-4.19/105-ea4500.patch | 48 +- .../patches-4.19/105-goflexhome.patch | 130 - .../kirkwood/patches-4.19/106-goflexnet.patch | 32 +- .../patches-4.19/107-02-nsa310b.patch | 147 - .../kirkwood/patches-4.19/107-03-nsa325.patch | 31 + .../kirkwood/patches-4.19/108-on100.patch | 171 - .../patches-4.19/109-pogoplug_v4.patch | 34 +- .../kirkwood/patches-4.19/110-pogo_e02.patch | 70 + .../kirkwood/patches-5.4/100-ib62x0.patch | 53 + .../kirkwood/patches-5.4/101-iconnect.patch | 80 + .../kirkwood/patches-5.4/102-dockstar.patch | 62 + .../patches-5.4/103-iomega-ix2-200.patch | 67 + .../kirkwood/patches-5.4/105-ea4500.patch | 95 + .../kirkwood/patches-5.4/106-goflexnet.patch | 53 + ...-zyxel-nsa3x0-common-nand-partitions.patch | 48 + .../kirkwood/patches-5.4/107-03-nsa325.patch | 31 + .../patches-5.4/109-pogoplug_v4.patch | 87 + .../kirkwood/patches-5.4/110-pogo_e02.patch | 68 + ...able-sata-port-specific-led-triggers.patch | 10 + .../202-linksys-find-active-root.patch | 62 + target/linux/lantiq/Makefile | 1 + .../lantiq/ase/base-files/etc/board.d/01_leds | 32 + .../ase/base-files/etc/board.d/02_network | 56 + .../ase/base-files/lib/upgrade/platform.sh | 10 + target/linux/lantiq/ase/config-4.19 | 1 - target/linux/lantiq/ase/config-5.4 | 28 + .../lantiq/base-files/etc/board.d/02_network | 268 - .../base-files/etc/hotplug.d/dsl/pppoa.sh | 2 +- .../etc/uci-defaults/01_led_migration | 51 +- .../etc/uci-defaults/02_migrate_xdsl_iface | 1 - .../lantiq/base-files/lib/functions/lantiq.sh | 17 +- .../base-files/lib/functions/lantiq_dsl.sh | 32 +- .../lib/preinit/05_set_preinit_iface_lantiq | 2 - target/linux/lantiq/config-5.4 | 234 + .../falcon/base-files/etc/board.d/02_network | 52 + .../falcon/base-files/lib/upgrade/platform.sh | 10 + target/linux/lantiq/falcon/config-5.4 | 11 + .../arch/mips/boot/dts/lantiq}/amazonse.dtsi | 40 + .../dts/lantiq/amazonse_allnet_all0333cj.dts} | 4 - .../dts/lantiq/amazonse_netgear_dgn1000b.dts} | 18 - .../arch/mips/boot/dts/lantiq}/ar9.dtsi | 151 + .../boot/dts/lantiq/ar9_avm_fritz7312.dts} | 25 +- .../boot/dts/lantiq/ar9_avm_fritz7320.dts} | 32 +- .../boot/dts/lantiq/ar9_bt_homehub-v3a.dts} | 36 +- .../dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts} | 0 .../boot/dts/lantiq/ar9_netgear_dgn3500.dts} | 2 +- .../boot/dts/lantiq/ar9_netgear_dgn3500.dtsi} | 34 +- .../boot/dts/lantiq/ar9_netgear_dgn3500b.dts} | 2 +- .../mips/boot/dts/lantiq/ar9_zte_h201l.dts} | 0 .../boot/dts/lantiq/ar9_zyxel_p-2601hn.dts} | 25 +- .../arch/mips/boot/dts/lantiq}/danube.dtsi | 80 + .../dts/lantiq/danube_arcadyan_arv4510pw.dts} | 23 +- .../lantiq/danube_arcadyan_arv4518pwr01.dts} | 2 +- .../lantiq/danube_arcadyan_arv4518pwr01.dtsi} | 18 +- .../lantiq/danube_arcadyan_arv4518pwr01a.dts} | 2 +- .../dts/lantiq/danube_arcadyan_arv4519pw.dts} | 0 .../dts/lantiq/danube_arcadyan_arv4520pw.dts} | 16 +- .../dts/lantiq/danube_arcadyan_arv4525pw.dts} | 16 +- .../dts/lantiq/danube_arcadyan_arv452cqw.dts} | 16 +- .../lantiq/danube_arcadyan_arv7506pw11.dts} | 9 +- .../lantiq/danube_arcadyan_arv7510pw22.dts} | 16 +- .../dts/lantiq/danube_arcadyan_arv7518pw.dts} | 17 +- .../dts/lantiq/danube_arcadyan_arv7519pw.dts} | 17 +- .../dts/lantiq/danube_arcadyan_arv7525pw.dts} | 8 +- .../dts/lantiq/danube_arcadyan_arv752dpw.dts} | 16 +- .../lantiq/danube_arcadyan_arv752dpw22.dts} | 16 +- .../lantiq/danube_arcadyan_arv8539pw22.dts} | 16 +- .../dts/lantiq/danube_audiocodes_mp-252.dts} | 7 +- .../dts/lantiq/danube_bt_homehub-v2b.dts} | 34 +- .../dts/lantiq/danube_lantiq_easy50712.dts} | 18 +- .../lantiq/danube_siemens_gigaset-sx76x.dts} | 12 - .../arch/mips/boot/dts/lantiq}/falcon.dtsi | 0 .../dts/lantiq/falcon_lantiq_easy88388.dts} | 2 +- .../dts/lantiq/falcon_lantiq_easy88444.dts} | 2 +- .../lantiq/falcon_lantiq_easy98000-nand.dts} | 3 +- .../lantiq/falcon_lantiq_easy98000-nor.dts} | 3 +- .../falcon_lantiq_easy98000-sflash.dts} | 6 +- .../dts/lantiq/falcon_lantiq_easy98000.dtsi} | 4 +- .../lantiq/falcon_lantiq_easy98020-v18.dts} | 2 +- .../dts/lantiq/falcon_lantiq_easy98020.dts} | 2 +- .../dts/lantiq/falcon_lantiq_easy98021.dts} | 2 +- .../lantiq/falcon_lantiq_easy98035synce.dts} | 2 +- .../falcon_lantiq_easy98035synce1588.dts} | 2 +- .../dts/lantiq/falcon_lantiq_falcon-mdu.dts} | 2 +- .../dts/lantiq/falcon_lantiq_falcon-sfp.dts} | 2 +- .../boot/dts/lantiq/falcon_sflash-16m.dtsi} | 0 .../arch/mips/boot/dts/lantiq}/vr9.dtsi | 150 + .../lantiq/vr9_alphanetworks_asl56026.dts} | 12 - .../dts/lantiq/vr9_arcadyan_arv7519rw22.dts} | 4 - .../boot/dts/lantiq/vr9_arcadyan_vg3503j.dts} | 25 +- .../lantiq/vr9_arcadyan_vgv7510kw22-brn.dts} | 2 +- .../lantiq/vr9_arcadyan_vgv7510kw22-nor.dts} | 2 +- .../dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi} | 19 +- .../dts/lantiq/vr9_arcadyan_vgv7519-brn.dts} | 2 +- .../dts/lantiq/vr9_arcadyan_vgv7519-nor.dts} | 2 +- .../dts/lantiq/vr9_arcadyan_vgv7519.dtsi} | 21 +- .../lantiq/vr9_avm_fritz3370-rev2-hynix.dts} | 5 +- .../lantiq/vr9_avm_fritz3370-rev2-micron.dts} | 5 +- .../dts/lantiq/vr9_avm_fritz3370-rev2.dtsi} | 31 +- .../boot/dts/lantiq/vr9_avm_fritz7360sl.dts} | 2 +- .../boot/dts/lantiq/vr9_avm_fritz7362sl.dts} | 30 +- .../boot/dts/lantiq/vr9_avm_fritz736x.dtsi} | 9 +- .../boot/dts/lantiq/vr9_avm_fritz7412.dts} | 24 +- .../boot/dts/lantiq/vr9_bt_homehub-v5a.dts} | 21 +- .../dts/lantiq/vr9_buffalo_wbmr-300hpd.dts} | 19 - .../dts/lantiq/vr9_lantiq_easy80920-nand.dts} | 5 +- .../dts/lantiq/vr9_lantiq_easy80920-nor.dts} | 2 +- .../dts/lantiq/vr9_lantiq_easy80920.dtsi} | 44 +- .../boot/dts/lantiq/vr9_netgear_dm200.dts} | 27 - .../boot/dts/lantiq/vr9_tplink_tdw8970.dts} | 2 +- .../boot/dts/lantiq/vr9_tplink_tdw8980.dts} | 2 +- .../boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi} | 29 +- .../boot/dts/lantiq/vr9_tplink_vr200.dts} | 2 +- .../boot/dts/lantiq/vr9_tplink_vr200.dtsi} | 46 +- .../boot/dts/lantiq/vr9_tplink_vr200v.dts} | 2 +- .../dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts} | 5 +- .../dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts} | 5 +- .../dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi} | 55 +- .../arch/mips/boot/dts/lantiq/amazonse.dtsi | 243 + .../dts/lantiq/amazonse_allnet_all0333cj.dts | 111 + .../dts/lantiq/amazonse_netgear_dgn1000b.dts | 153 + .../arch/mips/boot/dts/lantiq/ar9.dtsi | 419 ++ .../boot/dts/lantiq/ar9_avm_fritz7312.dts | 169 + .../boot/dts/lantiq/ar9_avm_fritz7320.dts | 151 + .../boot/dts/lantiq/ar9_bt_homehub-v3a.dts | 191 + .../dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts | 197 + .../boot/dts/lantiq/ar9_netgear_dgn3500.dts | 8 + .../boot/dts/lantiq/ar9_netgear_dgn3500.dtsi | 185 + .../boot/dts/lantiq/ar9_netgear_dgn3500b.dts | 8 + .../mips/boot/dts/lantiq/ar9_zte_h201l.dts | 172 + .../boot/dts/lantiq/ar9_zyxel_p-2601hn.dts | 178 + .../arch/mips/boot/dts/lantiq/danube.dtsi | 325 + .../dts/lantiq/danube_arcadyan_arv4510pw.dts | 214 + .../lantiq/danube_arcadyan_arv4518pwr01.dts | 8 + .../lantiq/danube_arcadyan_arv4518pwr01.dtsi | 200 + .../lantiq/danube_arcadyan_arv4518pwr01a.dts | 12 + .../dts/lantiq/danube_arcadyan_arv4519pw.dts | 205 + .../dts/lantiq/danube_arcadyan_arv4520pw.dts | 222 + .../dts/lantiq/danube_arcadyan_arv4525pw.dts | 151 + .../dts/lantiq/danube_arcadyan_arv452cqw.dts | 240 + .../lantiq/danube_arcadyan_arv7506pw11.dts | 162 + .../lantiq/danube_arcadyan_arv7510pw22.dts | 198 + .../dts/lantiq/danube_arcadyan_arv7518pw.dts | 233 + .../dts/lantiq/danube_arcadyan_arv7519pw.dts | 217 + .../dts/lantiq/danube_arcadyan_arv7525pw.dts | 149 + .../dts/lantiq/danube_arcadyan_arv752dpw.dts | 240 + .../lantiq/danube_arcadyan_arv752dpw22.dts | 261 + .../lantiq/danube_arcadyan_arv8539pw22.dts | 181 + .../dts/lantiq/danube_audiocodes_mp-252.dts | 112 + .../boot/dts/lantiq/danube_bt_homehub-v2b.dts | 238 + .../dts/lantiq/danube_lantiq_easy50712.dts} | 26 +- .../lantiq/danube_siemens_gigaset-sx76x.dts | 119 + .../arch/mips/boot/dts/lantiq/falcon.dtsi | 363 ++ .../dts/lantiq/falcon_lantiq_easy88388.dts | 93 + .../dts/lantiq/falcon_lantiq_easy88444.dts | 72 + .../lantiq/falcon_lantiq_easy98000-nand.dts | 38 + .../lantiq/falcon_lantiq_easy98000-nor.dts | 41 + .../lantiq/falcon_lantiq_easy98000-sflash.dts | 14 + .../dts/lantiq/falcon_lantiq_easy98000.dtsi | 110 + .../lantiq/falcon_lantiq_easy98020-v18.dts | 68 + .../dts/lantiq/falcon_lantiq_easy98020.dts | 85 + .../dts/lantiq/falcon_lantiq_easy98021.dts | 81 + .../lantiq/falcon_lantiq_easy98035synce.dts | 76 + .../falcon_lantiq_easy98035synce1588.dts | 76 + .../dts/lantiq/falcon_lantiq_falcon-mdu.dts | 53 + .../dts/lantiq/falcon_lantiq_falcon-sfp.dts | 76 + .../boot/dts/lantiq/falcon_sflash-16m.dtsi | 40 + .../arch/mips/boot/dts/lantiq/vr9.dtsi | 512 ++ .../dts/lantiq/vr9_alphanetworks_asl56026.dts | 155 + .../dts/lantiq/vr9_arcadyan_arv7519rw22.dts | 246 + .../boot/dts/lantiq/vr9_arcadyan_vg3503j.dts | 144 + .../lantiq/vr9_arcadyan_vgv7510kw22-brn.dts | 65 + .../lantiq/vr9_arcadyan_vgv7510kw22-nor.dts | 31 + .../dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi | 258 + .../dts/lantiq/vr9_arcadyan_vgv7519-brn.dts | 70 + .../dts/lantiq/vr9_arcadyan_vgv7519-nor.dts | 29 + .../boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi | 295 + .../lantiq/vr9_avm_fritz3370-rev2-hynix.dts | 39 + .../lantiq/vr9_avm_fritz3370-rev2-micron.dts | 37 + .../dts/lantiq/vr9_avm_fritz3370-rev2.dtsi | 279 + .../boot/dts/lantiq/vr9_avm_fritz7360sl.dts | 81 + .../boot/dts/lantiq/vr9_avm_fritz7362sl.dts | 113 + .../boot/dts/lantiq/vr9_avm_fritz736x.dtsi | 200 + .../boot/dts/lantiq/vr9_avm_fritz7412.dts | 218 + .../boot/dts/lantiq/vr9_bt_homehub-v5a.dts | 283 + .../dts/lantiq/vr9_buffalo_wbmr-300hpd.dts | 312 + .../dts/lantiq/vr9_lantiq_easy80920-nand.dts | 66 + .../dts/lantiq/vr9_lantiq_easy80920-nor.dts | 37 + .../boot/dts/lantiq/vr9_lantiq_easy80920.dtsi | 279 + .../boot/dts/lantiq/vr9_netgear_dm200.dts | 186 + .../boot/dts/lantiq/vr9_tplink_tdw8970.dts | 8 + .../boot/dts/lantiq/vr9_tplink_tdw8980.dts | 33 + .../boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi | 272 + .../mips/boot/dts/lantiq/vr9_tplink_vr200.dts | 92 + .../boot/dts/lantiq/vr9_tplink_vr200.dtsi | 213 + .../boot/dts/lantiq/vr9_tplink_vr200v.dts | 99 + .../dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts | 71 + .../dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts | 65 + .../dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi | 259 + target/linux/lantiq/image/Makefile | 760 +-- target/linux/lantiq/image/amazonse.mk | 20 + target/linux/lantiq/image/ar9.mk | 165 + target/linux/lantiq/image/danube.mk | 219 + target/linux/lantiq/image/falcon.mk | 93 + target/linux/lantiq/image/tp-link.mk | 23 +- target/linux/lantiq/image/vr9.mk | 227 + target/linux/lantiq/image/xway_legacy.mk | 72 + ...T-PHY-add-led-support-for-intel-xway.patch | 4 +- ...0025-NET-MIPS-lantiq-adds-xrx200-net.patch | 37 +- .../0001-MIPS-lantiq-add-pcie-driver.patch | 5518 +++++++++++++++++ .../0004-MIPS-lantiq-add-atm-hack.patch | 482 ++ ...-MIPS-lantiq-backport-old-timer-code.patch | 1035 ++++ .../0018-MTD-nand-lots-of-xrx200-fixes.patch | 121 + ...antiq-handle-NO_XIP-on-cfi0001-flash.patch | 25 + ...T-PHY-add-led-support-for-intel-xway.patch | 294 + ...rt-DSA-switch-driver-PMU-clock-chang.patch | 55 + ...5-NET-MIPS-lantiq-adds-xrx200-legacy.patch | 3470 +++++++++++ ...MIPS-lantiq-Add-GPHY-Firmware-loader.patch | 352 ++ .../0028-NET-lantiq-various-etop-fixes.patch | 866 +++ .../0030-GPIO-add-named-gpio-exports.patch | 169 + ...PS-lantiq-add-FALC-ON-i2c-bus-master.patch | 1034 +++ ...iq-wifi-and-ethernet-eeprom-handling.patch | 218 + ...42-arch-mips-increase-io_space_limit.patch | 23 + ...e-lantiq-settings-match-vendor-drive.patch | 78 + ...PS-lantiq-improve-USB-initialization.patch | 49 + .../patches-5.4/0101-find_active_root.patch | 93 + .../0151-lantiq-ifxmips_pcie-use-of.patch | 387 ++ .../lantiq/patches-5.4/0152-lantiq-VPE.patch | 180 + .../0154-lantiq-pci-bar11mask-fix.patch | 22 + .../patches-5.4/0155-lantiq-VPE-nosmp.patch | 14 + .../0160-owrt-lantiq-multiple-flash.patch | 220 + ...-cmdset-0001-disable-buffered-writes.patch | 11 + ...add-gphy-clk-src-device-tree-binding.patch | 30 + .../0701-NET-lantiq-etop-of-mido.patch | 37 + .../base-files/etc/board.d/01_leds | 44 +- .../xrx200/base-files/etc/board.d/02_network | 175 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 0 .../etc/hotplug.d/firmware/12-ath9k-eeprom | 161 + .../base-files/lib/upgrade/platform.sh | 2 - target/linux/lantiq/xrx200/config-5.4 | 106 + .../xway/base-files/etc/board.d/01_leds | 44 + .../xway/base-files/etc/board.d/02_network | 118 + .../etc/hotplug.d/firmware/12-ath9k-eeprom | 17 +- .../xway/base-files/lib/upgrade/platform.sh | 20 + target/linux/lantiq/xway/config-4.19 | 4 - target/linux/lantiq/xway/config-5.4 | 47 + .../base-files/etc/board.d/01_leds | 41 + .../base-files/etc/board.d/02_network | 61 + .../base-files/lib/upgrade/platform.sh | 10 + target/linux/lantiq/xway_legacy/config-4.19 | 4 - target/linux/lantiq/xway_legacy/config-5.4 | 37 + target/linux/malta/Makefile | 8 +- target/linux/malta/be/config-default | 1 + target/linux/malta/be64/config-default | 18 +- target/linux/malta/config-4.19 | 336 + target/linux/malta/config-5.4 | 345 ++ target/linux/malta/image/Makefile | 13 +- target/linux/malta/le/config-default | 1 + target/linux/malta/le64/config-default | 18 +- target/linux/sunxi/Makefile | 1 + target/linux/sunxi/config-5.4 | 589 ++ target/linux/sunxi/cortexa53/config-5.4 | 155 + target/linux/sunxi/cortexa7/config-5.4 | 15 + target/linux/sunxi/cortexa8/config-5.4 | 18 + target/linux/sunxi/image/Makefile | 2 +- target/linux/sunxi/image/cortex-a53.mk | 70 +- ...angepi_pc2_usb_otg_to_host_key_power.patch | 20 + ...un7i-Add-BCM53125-switch-nodes-to-th.patch | 86 + ...a64-sopine-Add-Sopine-flash-partitio.patch | 46 + ...ner-a64-olinuxino-Add-bank-supply-re.patch | 58 + ...inner-a64-olinuxino-add-user-red-LED.patch | 32 + ...ner-a64-olinuxino-add-status-LED-ali.patch | 32 + 375 files changed, 42730 insertions(+), 3633 deletions(-) create mode 100644 package/base-files/files/lib/functions/migrations.sh create mode 100644 target/linux/apm821xx/config-5.4 create mode 100644 target/linux/apm821xx/patches-5.4/111-crypto-crypto4xx-reduce-memory-fragmentation.patch create mode 100644 target/linux/apm821xx/patches-5.4/112-crypto-crypto4xx-use-GFP_KERNEL-for-big-allocations.patch create mode 100644 target/linux/apm821xx/patches-5.4/201-add-amcc-apollo3g-support.patch create mode 100644 target/linux/apm821xx/patches-5.4/202-add-netgear-wndr4700-support.patch create mode 100644 target/linux/apm821xx/patches-5.4/300-fix-atheros-nics-on-apm82181.patch create mode 100644 target/linux/apm821xx/patches-5.4/301-fix-memory-map-wndr4700.patch create mode 100644 target/linux/apm821xx/patches-5.4/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch create mode 100644 target/linux/apm821xx/patches-5.4/802-usb-xhci-force-msi-renesas-xhci.patch create mode 100644 target/linux/apm821xx/patches-5.4/803-hwmon-tc654-add-detection-routine.patch create mode 100644 target/linux/apm821xx/patches-5.4/804-hwmon-tc654-add-thermal_cooling-device.patch create mode 100644 target/linux/apm821xx/patches-5.4/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch create mode 100644 target/linux/archs38/config-5.4 create mode 100644 target/linux/archs38/patches-5.4/0001-arch-arc-Add-compiler-option-for-gcc8.4.patch rename target/linux/armvirt/32/{config-default => config-4.19} (81%) create mode 100644 target/linux/armvirt/32/config-5.4 rename target/linux/armvirt/64/{config-default => config-4.19} (54%) create mode 100644 target/linux/armvirt/64/config-5.4 create mode 100644 target/linux/armvirt/config-4.19 create mode 100644 target/linux/armvirt/config-5.4 create mode 100644 target/linux/gemini/config-5.4 create mode 100644 target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch create mode 100644 target/linux/gemini/patches-5.4/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch create mode 100644 target/linux/gemini/patches-5.4/0003-ARM-dts-gemini-Rename-IDE-nodes.patch create mode 100644 target/linux/gemini/patches-5.4/0004-ARM-dts-gemini-Add-thermal-zone-to-DIR-685.patch create mode 100644 target/linux/imx6/config-5.4 create mode 100644 target/linux/imx6/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch create mode 100644 target/linux/imx6/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch create mode 100644 target/linux/imx6/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch create mode 100644 target/linux/imx6/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch create mode 100644 target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch create mode 100644 target/linux/imx6/patches-5.4/100-bootargs.patch create mode 100644 target/linux/imx6/patches-5.4/301-apalis-ixora-dts-leds.patch create mode 100644 target/linux/imx6/patches-5.4/302-apalis-ixora-dts-reset-button.patch create mode 100644 target/linux/kirkwood/config-5.4 create mode 100644 target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-goflexhome.dts create mode 100644 target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-linksys-audi.dts create mode 100644 target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-nsa310b.dts create mode 100644 target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-on100.dts create mode 100644 target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-goflexhome.dts create mode 100644 target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-linksys-audi.dts create mode 100644 target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-nsa310b.dts create mode 100644 target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-on100.dts create mode 100644 target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-goflexhome.dts create mode 100644 target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-linksys-audi.dts create mode 100644 target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-nsa310b.dts create mode 100644 target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-on100.dts delete mode 100644 target/linux/kirkwood/patches-4.14/104-ea3500.patch delete mode 100644 target/linux/kirkwood/patches-4.14/105-goflexhome.patch delete mode 100644 target/linux/kirkwood/patches-4.14/107-02-nsa310b.patch create mode 100644 target/linux/kirkwood/patches-4.14/107-03-nsa325.patch delete mode 100644 target/linux/kirkwood/patches-4.14/108-on100.patch create mode 100644 target/linux/kirkwood/patches-4.14/110-pogo_e02.patch delete mode 100644 target/linux/kirkwood/patches-4.19/104-ea3500.patch delete mode 100644 target/linux/kirkwood/patches-4.19/105-goflexhome.patch delete mode 100644 target/linux/kirkwood/patches-4.19/107-02-nsa310b.patch create mode 100644 target/linux/kirkwood/patches-4.19/107-03-nsa325.patch delete mode 100644 target/linux/kirkwood/patches-4.19/108-on100.patch create mode 100644 target/linux/kirkwood/patches-4.19/110-pogo_e02.patch create mode 100644 target/linux/kirkwood/patches-5.4/100-ib62x0.patch create mode 100644 target/linux/kirkwood/patches-5.4/101-iconnect.patch create mode 100644 target/linux/kirkwood/patches-5.4/102-dockstar.patch create mode 100644 target/linux/kirkwood/patches-5.4/103-iomega-ix2-200.patch create mode 100644 target/linux/kirkwood/patches-5.4/105-ea4500.patch create mode 100644 target/linux/kirkwood/patches-5.4/106-goflexnet.patch create mode 100644 target/linux/kirkwood/patches-5.4/107-01-zyxel-nsa3x0-common-nand-partitions.patch create mode 100644 target/linux/kirkwood/patches-5.4/107-03-nsa325.patch create mode 100644 target/linux/kirkwood/patches-5.4/109-pogoplug_v4.patch create mode 100644 target/linux/kirkwood/patches-5.4/110-pogo_e02.patch create mode 100644 target/linux/kirkwood/patches-5.4/201-enable-sata-port-specific-led-triggers.patch create mode 100644 target/linux/kirkwood/patches-5.4/202-linksys-find-active-root.patch create mode 100755 target/linux/lantiq/ase/base-files/etc/board.d/01_leds create mode 100755 target/linux/lantiq/ase/base-files/etc/board.d/02_network create mode 100755 target/linux/lantiq/ase/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/lantiq/ase/config-5.4 delete mode 100755 target/linux/lantiq/base-files/etc/board.d/02_network create mode 100644 target/linux/lantiq/config-5.4 create mode 100755 target/linux/lantiq/falcon/base-files/etc/board.d/02_network create mode 100755 target/linux/lantiq/falcon/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/lantiq/falcon/config-5.4 rename target/linux/lantiq/{files/arch/mips/boot/dts => files-4.19/arch/mips/boot/dts/lantiq}/amazonse.dtsi (84%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ALL0333CJ.dts => files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts} (96%) rename target/linux/lantiq/{files/arch/mips/boot/dts/DGN1000B.dts => files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts} (87%) rename target/linux/lantiq/{files/arch/mips/boot/dts => files-4.19/arch/mips/boot/dts/lantiq}/ar9.dtsi (66%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ7312.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts} (87%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ7320.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts} (81%) rename target/linux/lantiq/{files/arch/mips/boot/dts/BTHOMEHUBV3A.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts} (86%) rename target/linux/lantiq/{files/arch/mips/boot/dts/WBMR.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts} (100%) rename target/linux/lantiq/{files/arch/mips/boot/dts/DGN3500.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts} (75%) rename target/linux/lantiq/{files/arch/mips/boot/dts/DGN3500.dtsi => files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi} (85%) rename target/linux/lantiq/{files/arch/mips/boot/dts/DGN3500B.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts} (75%) rename target/linux/lantiq/{files/arch/mips/boot/dts/H201L.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts} (100%) rename target/linux/lantiq/{files/arch/mips/boot/dts/P2601HNFX.dts => files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts} (88%) rename target/linux/lantiq/{files/arch/mips/boot/dts => files-4.19/arch/mips/boot/dts/lantiq}/danube.dtsi (76%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV4510PW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts} (90%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV4518PWR01.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts} (71%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV4518PWR01.dtsi => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi} (92%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV4518PWR01A.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts} (78%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV4519PW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts} (100%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV4520PW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts} (94%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV4525PW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts} (91%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV452CQW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts} (94%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV7506PW11.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts} (96%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV7510PW22.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts} (93%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV7518PW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts} (94%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV7519PW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts} (93%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV7525PW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts} (96%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV752DPW.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts} (94%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV752DPW22.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts} (95%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV8539PW22.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts} (92%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ACMP252.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts} (95%) rename target/linux/lantiq/{files/arch/mips/boot/dts/BTHOMEHUBV2B.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts} (88%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY50712.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts} (80%) rename target/linux/lantiq/{files/arch/mips/boot/dts/GIGASX76X.dts => files-4.19/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts} (91%) rename target/linux/lantiq/{files/arch/mips/boot/dts => files-4.19/arch/mips/boot/dts/lantiq}/falcon.dtsi (100%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY88388.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts} (98%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY88444.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98000NAND.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts} (91%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98000NOR.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts} (91%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98000SFLASH.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts} (67%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98000-base.dtsi => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi} (98%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98020V18.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98020.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98021.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98035SYNCE.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY98035SYNCE1588.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FALCON-MDU.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts} (96%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FALCON-SFP.dts => files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/falcon-sflash-16M.dtsi => files-4.19/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi} (100%) rename target/linux/lantiq/{files/arch/mips/boot/dts => files-4.19/arch/mips/boot/dts/lantiq}/vr9.dtsi (71%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ASL56026.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts} (93%) rename target/linux/lantiq/{files/arch/mips/boot/dts/ARV7519RW22.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts} (98%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VG3503J.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts} (86%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VGV7510KW22BRN.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts} (96%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VGV7510KW22NOR.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts} (92%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VGV7510KW22.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi} (93%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VGV7519BRN.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts} (96%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VGV7519NOR.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts} (92%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VGV7519.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi} (93%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ3370-REV2-HYNIX.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts} (84%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ3370-REV2-MICRON.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts} (83%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ3370-REV2.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi} (89%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ7360SL.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts} (97%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ7362SL.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts} (78%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ736X.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi} (96%) rename target/linux/lantiq/{files/arch/mips/boot/dts/FRITZ7412.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts} (88%) rename target/linux/lantiq/{files/arch/mips/boot/dts/BTHOMEHUBV5A.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts} (93%) rename target/linux/lantiq/{files/arch/mips/boot/dts/WBMR300.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts} (93%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY80920NAND.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts} (92%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY80920NOR.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts} (94%) rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY80920.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi} (86%) rename target/linux/lantiq/{files/arch/mips/boot/dts/DM200.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts} (86%) rename target/linux/lantiq/{files/arch/mips/boot/dts/TDW8970.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts} (78%) rename target/linux/lantiq/{files/arch/mips/boot/dts/TDW8980.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts} (94%) rename target/linux/lantiq/{files/arch/mips/boot/dts/TDW89X0.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi} (90%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VR200.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts} (98%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VR200.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi} (86%) rename target/linux/lantiq/{files/arch/mips/boot/dts/VR200v.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts} (98%) rename target/linux/lantiq/{files/arch/mips/boot/dts/P2812HNUF1.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts} (90%) rename target/linux/lantiq/{files/arch/mips/boot/dts/P2812HNUF3.dts => files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts} (89%) rename target/linux/lantiq/{files/arch/mips/boot/dts/P2812HNUFX.dtsi => files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi} (82%) create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts rename target/linux/lantiq/{files/arch/mips/boot/dts/EASY50810.dts => files-5.4/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts} (67%) create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts create mode 100644 target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi create mode 100644 target/linux/lantiq/image/amazonse.mk create mode 100644 target/linux/lantiq/image/ar9.mk create mode 100644 target/linux/lantiq/image/danube.mk create mode 100644 target/linux/lantiq/image/falcon.mk create mode 100644 target/linux/lantiq/image/vr9.mk create mode 100644 target/linux/lantiq/image/xway_legacy.mk create mode 100644 target/linux/lantiq/patches-5.4/0001-MIPS-lantiq-add-pcie-driver.patch create mode 100644 target/linux/lantiq/patches-5.4/0004-MIPS-lantiq-add-atm-hack.patch create mode 100644 target/linux/lantiq/patches-5.4/0008-MIPS-lantiq-backport-old-timer-code.patch create mode 100644 target/linux/lantiq/patches-5.4/0018-MTD-nand-lots-of-xrx200-fixes.patch create mode 100644 target/linux/lantiq/patches-5.4/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch create mode 100644 target/linux/lantiq/patches-5.4/0023-NET-PHY-add-led-support-for-intel-xway.patch create mode 100644 target/linux/lantiq/patches-5.4/0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch create mode 100644 target/linux/lantiq/patches-5.4/0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch create mode 100644 target/linux/lantiq/patches-5.4/0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch create mode 100644 target/linux/lantiq/patches-5.4/0028-NET-lantiq-various-etop-fixes.patch create mode 100644 target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch create mode 100644 target/linux/lantiq/patches-5.4/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch create mode 100644 target/linux/lantiq/patches-5.4/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch create mode 100644 target/linux/lantiq/patches-5.4/0042-arch-mips-increase-io_space_limit.patch create mode 100644 target/linux/lantiq/patches-5.4/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch create mode 100644 target/linux/lantiq/patches-5.4/0051-MIPS-lantiq-improve-USB-initialization.patch create mode 100644 target/linux/lantiq/patches-5.4/0101-find_active_root.patch create mode 100644 target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch create mode 100644 target/linux/lantiq/patches-5.4/0152-lantiq-VPE.patch create mode 100644 target/linux/lantiq/patches-5.4/0154-lantiq-pci-bar11mask-fix.patch create mode 100644 target/linux/lantiq/patches-5.4/0155-lantiq-VPE-nosmp.patch create mode 100644 target/linux/lantiq/patches-5.4/0160-owrt-lantiq-multiple-flash.patch create mode 100644 target/linux/lantiq/patches-5.4/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch create mode 100644 target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch create mode 100644 target/linux/lantiq/patches-5.4/0701-NET-lantiq-etop-of-mido.patch rename target/linux/lantiq/{ => xrx200}/base-files/etc/board.d/01_leds (80%) create mode 100755 target/linux/lantiq/xrx200/base-files/etc/board.d/02_network rename target/linux/lantiq/{ => xrx200}/base-files/etc/hotplug.d/firmware/11-ath10k-caldata (100%) create mode 100644 target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom rename target/linux/lantiq/{ => xrx200}/base-files/lib/upgrade/platform.sh (91%) create mode 100644 target/linux/lantiq/xrx200/config-5.4 create mode 100755 target/linux/lantiq/xway/base-files/etc/board.d/01_leds create mode 100755 target/linux/lantiq/xway/base-files/etc/board.d/02_network rename target/linux/lantiq/{ => xway}/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom (86%) create mode 100755 target/linux/lantiq/xway/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/lantiq/xway/config-5.4 create mode 100755 target/linux/lantiq/xway_legacy/base-files/etc/board.d/01_leds create mode 100755 target/linux/lantiq/xway_legacy/base-files/etc/board.d/02_network create mode 100755 target/linux/lantiq/xway_legacy/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/lantiq/xway_legacy/config-5.4 create mode 100644 target/linux/malta/config-4.19 create mode 100644 target/linux/malta/config-5.4 create mode 100644 target/linux/sunxi/config-5.4 create mode 100644 target/linux/sunxi/cortexa53/config-5.4 create mode 100644 target/linux/sunxi/cortexa7/config-5.4 create mode 100644 target/linux/sunxi/cortexa8/config-5.4 create mode 100644 target/linux/sunxi/patches-5.4/301-orangepi_pc2_usb_otg_to_host_key_power.patch create mode 100644 target/linux/sunxi/patches-5.4/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch create mode 100644 target/linux/sunxi/patches-5.4/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch create mode 100644 target/linux/sunxi/patches-5.4/410-v5.6-arm64-dts-allwinner-a64-olinuxino-Add-bank-supply-re.patch create mode 100644 target/linux/sunxi/patches-5.4/420-v5.7-arm64-dts-allwinner-a64-olinuxino-add-user-red-LED.patch create mode 100644 target/linux/sunxi/patches-5.4/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch diff --git a/package/base-files/files/lib/functions/migrations.sh b/package/base-files/files/lib/functions/migrations.sh new file mode 100644 index 0000000000..b180a0242f --- /dev/null +++ b/package/base-files/files/lib/functions/migrations.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +. /lib/functions.sh + +migrate_led_sysfs() { + local cfg="$1"; shift + local tuples="$@" + local sysfs + local name + + config_get sysfs ${cfg} sysfs + config_get name ${cfg} name + + [ -z "${sysfs}" ] && return + + for tuple in ${tuples}; do + local old=${tuple%=*} + local new=${tuple#*=} + local new_sysfs + + new_sysfs=$(echo ${sysfs} | sed "s/${old}/${new}/") + + [ "${new_sysfs}" = "${sysfs}" ] && continue + + uci set system.${cfg}.sysfs="${new_sysfs}" + + logger -t led-migration "sysfs option of LED \"${name}\" updated to ${new_sysfs}" + done; +} + +migrate_leds() { + config_load system + config_foreach migrate_led_sysfs led "$@" +} + +migrations_apply() { + local realm="$1" + [ -n "$(uci changes ${realm})" ] && uci -q commit ${realm} +} diff --git a/target/linux/apm821xx/Makefile b/target/linux/apm821xx/Makefile index b74dc177a8..9ba623535e 100644 --- a/target/linux/apm821xx/Makefile +++ b/target/linux/apm821xx/Makefile @@ -14,6 +14,7 @@ MAINTAINER:=Chris Blake , \ SUBTARGETS:=nand sata KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 define Target/Description Build images for AppliedMicro APM821xx based boards. diff --git a/target/linux/apm821xx/base-files/lib/preinit/79_move_config b/target/linux/apm821xx/base-files/lib/preinit/79_move_config index cb5e5c759d..37d35b663b 100644 --- a/target/linux/apm821xx/base-files/lib/preinit/79_move_config +++ b/target/linux/apm821xx/base-files/lib/preinit/79_move_config @@ -4,13 +4,14 @@ BOOTPART=/dev/sda1 move_config() { . /lib/functions.sh + . /lib/upgrade/common.sh case "$(board_name)" in wd,mybooklive) if [ -b $BOOTPART ]; then mkdir -p /boot mount -t ext4 -o rw,noatime $BOOTPART /boot - [ -f /boot/sysupgrade.tgz ] && mv -f /boot/sysupgrade.tgz / + [ -f "/boot/$BACKUP_FILE" ] && mv -f "/boot/$BACKUP_FILE" / fi ;; *) diff --git a/target/linux/apm821xx/config-4.19 b/target/linux/apm821xx/config-4.19 index 358eb3c716..27385ef1fd 100644 --- a/target/linux/apm821xx/config-4.19 +++ b/target/linux/apm821xx/config-4.19 @@ -51,7 +51,6 @@ CONFIG_BUILD_SALT="" # CONFIG_CANYONLANDS is not set CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_CC_HAS_STACKPROTECTOR_NONE=y -CONFIG_CC_IS_GCC=y CONFIG_CLANG_VERSION=0 CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="rootfstype=squashfs noinitrd" @@ -109,7 +108,6 @@ CONFIG_EXTRA_TARGETS="uImage" CONFIG_FIXED_PHY=y CONFIG_FREEZER=y # CONFIG_FSL_LBC is not set -CONFIG_GCC_VERSION=70300 CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y @@ -171,7 +169,6 @@ CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_PPC4XX=y CONFIG_HZ=1000 -# CONFIG_HZ_100 is not set CONFIG_HZ_1000=y CONFIG_HZ_PERIODIC=y CONFIG_I2C=y diff --git a/target/linux/apm821xx/config-5.4 b/target/linux/apm821xx/config-5.4 new file mode 100644 index 0000000000..f2caef0e26 --- /dev/null +++ b/target/linux/apm821xx/config-5.4 @@ -0,0 +1,345 @@ +# CONFIG_40x is not set +CONFIG_44x=y +CONFIG_460EX=y +CONFIG_4xx=y +CONFIG_4xx_SOC=y +# CONFIG_ADVANCED_OPTIONS is not set +CONFIG_APM821xx=y +CONFIG_APOLLO3G=y +# CONFIG_ARCHES is not set +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS=11 +CONFIG_ARCH_MMAP_RND_BITS_MAX=17 +CONFIG_ARCH_MMAP_RND_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y +CONFIG_AUDIT_ARCH=y +# CONFIG_BAMBOO is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLUESTONE=y +CONFIG_BOOKE=y +CONFIG_BOOKE_WDT=y +# CONFIG_CANYONLANDS is not set +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs noinitrd" +CONFIG_CMDLINE_BOOL=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_CFB=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEV_PPC4XX=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ESSIV=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD5_PPC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_OFB=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1_PPC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_DATA_SHIFT=12 +CONFIG_DEBUG_MISC=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +# CONFIG_E200 is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_EBONY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EIGER is not set +CONFIG_ETEXT_SHIFT=12 +CONFIG_EXTRA_TARGETS="uImage" +CONFIG_FIXED_PHY=y +CONFIG_FORCE_PCI=y +CONFIG_FREEZER=y +# CONFIG_FSL_LBC is not set +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +# CONFIG_GEN_RTC is not set +# CONFIG_GLACIER is not set +CONFIG_GPIOLIB=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_SYSFS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_NVRAM_OPS=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CBPF_JIT=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MMU_GATHER_PAGE_SIZE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_PPC4XX=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_IBM_IIC=y +CONFIG_IBM_EMAC=y +CONFIG_IBM_EMAC_EMAC4=y +CONFIG_IBM_EMAC_POLL_WEIGHT=32 +CONFIG_IBM_EMAC_RGMII=y +CONFIG_IBM_EMAC_RXB=128 +CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256 +CONFIG_IBM_EMAC_TAH=y +CONFIG_IBM_EMAC_TXB=128 +# CONFIG_ICON is not set +CONFIG_ILLEGAL_POINTER_VALUE=0 +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_ISA_DMA_API=y +# CONFIG_JFFS2_FS is not set +# CONFIG_KATMAI is not set +CONFIG_KERNEL_START=0xc0000000 +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_PATTERN=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_MATH_EMULATION is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NOT_COHERENT_CACHE=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_IRQS=512 +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND=y +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PACKING=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_MSI=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYSICAL_START=0x00000000 +CONFIG_PHYS_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PLUGIN_HOSTCC="g++" +CONFIG_PM=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PPC=y +CONFIG_PPC32=y +CONFIG_PPC44x_SIMPLE=y +CONFIG_PPC4xx_CPM=y +CONFIG_PPC4xx_GPIO=y +CONFIG_PPC4xx_MSI=y +CONFIG_PPC4xx_PCI_EXPRESS=y +# CONFIG_PPC64 is not set +# CONFIG_PPC_47x is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_REGS=y +# CONFIG_PPC_BOOK3S_601 is not set +# CONFIG_PPC_BOOK3S_6xx is not set +CONFIG_PPC_DCR=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_EARLY_DEBUG is not set +CONFIG_PPC_FPU=y +CONFIG_PPC_INDIRECT_PCI=y +# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +CONFIG_PPC_MSI_BITMAP=y +CONFIG_PPC_PAGE_SHIFT=12 +# CONFIG_PPC_PTDUMP is not set +CONFIG_PPC_UDBG_16550=y +CONFIG_PPC_WERROR=y +CONFIG_PTE_64BIT=y +# CONFIG_RAINIER is not set +CONFIG_RAS=y +CONFIG_RSEQ=y +# CONFIG_SAM440EP is not set +# CONFIG_SCOM_DEBUGFS is not set +# CONFIG_SEQUOIA is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SIMPLE_GPIO=y +CONFIG_SPARSE_IRQ=y +CONFIG_SRCU=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_TAISHAN is not set +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THREAD_SHIFT=13 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_USB_SUPPORT=y +CONFIG_VDSO32=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set +# CONFIG_WARP is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WNDR4700 is not set +# CONFIG_XILINX_SYSACE is not set +# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_POWERPC=y +# CONFIG_YOSEMITE is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/apm821xx/dts/netgear-wndr4700.dts b/target/linux/apm821xx/dts/netgear-wndr4700.dts index a9ec36adad..8972d2b030 100644 --- a/target/linux/apm821xx/dts/netgear-wndr4700.dts +++ b/target/linux/apm821xx/dts/netgear-wndr4700.dts @@ -36,13 +36,25 @@ thermal-sensors = <&temp0 1>; + /* + * REVISIT: + * + * Add the <&drive_temp>; sensor there and wire up + * the coefficients = <1 1>; property. + * + * Note: The kernel does not yet support more than + * one sensor (see of_thermal.c's function: + * thermal_of_build_thermal_zon()). Once this is + * implemented. + */ + trips { /* * Once the thermal governers are a bit smarter * and do hysteresis properly, we can disable * the fan when the HDD and CPU has < 39 C. */ - cpu_alert0: cpu-alert0 { + cpu_alert0: board-alert0 { temperature = <25000>; hysteresis = <2000>; type = "active"; @@ -79,7 +91,7 @@ }; cpu_alert6: cpu-alert6 { - temperature = <850000>; /* millicelsius */ + temperature = <85000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "active"; }; @@ -145,6 +157,17 @@ &SATA1 { status = "okay"; + + /* + * This drive may have a temperature sensor with a + * thermal zone we can use for thermal control of the + * chassis temperature using the fan. + */ + + drive_temp: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; }; &USBOTG0 { @@ -244,12 +267,6 @@ &GPIO0 { status = "okay"; - #interrupt-cells = <2>; - interrupt-controller; - interrupts-extended = <&UIC1 0x14>, - <&UIC1 0x1e>, - <&UIC1 0x1f>, - <&UIC2 0x19>; }; &IIC0 { diff --git a/target/linux/apm821xx/dts/wd-mybooklive.dts b/target/linux/apm821xx/dts/wd-mybooklive.dts index 6cba7d2f26..82e9497ecd 100644 --- a/target/linux/apm821xx/dts/wd-mybooklive.dts +++ b/target/linux/apm821xx/dts/wd-mybooklive.dts @@ -179,10 +179,20 @@ &SATA0 { status = "okay"; + + drive0: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; }; &SATA1 { status = "okay"; + + drive1: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; }; &UART0 { diff --git a/target/linux/apm821xx/image/Makefile b/target/linux/apm821xx/image/Makefile index 277b2a1fcc..e78bf046a7 100644 --- a/target/linux/apm821xx/image/Makefile +++ b/target/linux/apm821xx/image/Makefile @@ -58,7 +58,7 @@ define Build/MerakiAdd-dtb $(call Image/BuildDTB,../dts/$(DEVICE_DTS).dts,$@.dtb) ( \ dd if=$@.dtb bs=$(DTB_SIZE) conv=sync; \ - dd if=$@ bs=$(BLOCKSIZE) conv=sync; \ + cat $@ ; \ ) > $@.new @mv $@.new $@ endef @@ -122,11 +122,11 @@ endef ifeq ($(SUBTARGET),nand) define Device/meraki_mr24 - DEVICE_TITLE := Cisco Meraki MR24 + DEVICE_VENDOR := Cisco Meraki + DEVICE_MODEL := MR24 DEVICE_PACKAGES := kmod-spi-gpio -swconfig BOARD_NAME := mr24 DEVICE_DTS := meraki-mr24 - BLOCKSIZE := 63k IMAGES := sysupgrade.bin DTB_SIZE := 64512 IMAGE_SIZE := 8191k @@ -139,7 +139,8 @@ endef TARGET_DEVICES += meraki_mr24 define Device/meraki_mx60 - DEVICE_TITLE := Cisco Meraki MX60/MX60W + DEVICE_VENDOR := Cisco Meraki + DEVICE_MODEL := MX60/MX60W DEVICE_PACKAGES := kmod-spi-gpio kmod-usb-ledtrig-usbport kmod-usb-dwc2 \ kmod-usb-storage block-mount BOARD_NAME := mx60 @@ -158,6 +159,7 @@ endef TARGET_DEVICES += meraki_mx60 define Device/netgear_wndap6x0 + DEVICE_VENDOR := NETGEAR DEVICE_PACKAGES := kmod-eeprom-at24 SUBPAGESIZE := 256 PAGESIZE := 512 @@ -174,21 +176,22 @@ endef define Device/netgear_wndap620 $(Device/netgear_wndap6x0) - DEVICE_TITLE := Netgear WNDAP620 - Premium Wireless-N + DEVICE_MODEL := WNDAP620 (Premium Wireless-N) DEVICE_DTS := netgear-wndap620 endef TARGET_DEVICES += netgear_wndap620 define Device/netgear_wndap660 $(Device/netgear_wndap6x0) - DEVICE_TITLE := Netgear WNDAP660 - Dual Radio Dual Band Wireless-N + DEVICE_MODEL := WNDAP660 (Dual Radio Dual Band Wireless-N) DEVICE_DTS := netgear-wndap660 endef TARGET_DEVICES += netgear_wndap660 define Device/netgear_wndr4700 - DEVICE_TITLE := Netgear Centria N900 WNDR4700/WNDR4720 - DEVICE_PACKAGES := badblocks block-mount e2fsprogs \ + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := Centria N900 WNDR4700/WNDR4720 + DEVICE_PACKAGES := badblocks block-mount e2fsprogs kmod-hwmon-drivetemp \ kmod-dm kmod-fs-ext4 kmod-fs-vfat kmod-usb-ledtrig-usbport \ kmod-md-mod kmod-nls-cp437 kmod-nls-iso8859-1 kmod-nls-iso8859-15 \ kmod-nls-utf8 kmod-usb3 kmod-usb-dwc2 kmod-usb-storage \ @@ -209,7 +212,7 @@ define Device/netgear_wndr4700 append-uImage-fakehdr filesystem | dtb | create-uImage-dtb | prepend-dtb KERNEL_INITRAMFS := kernel-bin | gzip | dtb | MuImage-initramfs gzip IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \ - netgear-dni | check-size $$$$(IMAGE_SIZE) + netgear-dni | check-size IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata ARTIFACT/device-tree.dtb := export-dtb | uImage none NETGEAR_BOARD_ID := WNDR4700 @@ -224,7 +227,8 @@ endif ifeq ($(SUBTARGET),sata) define Device/wd_mybooklive - DEVICE_TITLE := Western Digital My Book Live Series (Single + Duo) + DEVICE_VENDOR := Western Digital + DEVICE_MODEL := My Book Live Series (Single + Duo) DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport kmod-usb-storage kmod-fs-vfat wpad-basic DEVICE_TYPE := nas DEVICE_DTS := wd-mybooklive @@ -233,7 +237,7 @@ define Device/wd_mybooklive DTB_SIZE := 16384 KERNEL := kernel-bin | dtb | gzip | uImage gzip KERNEL_INITRAMFS := kernel-bin | gzip | dtb | MuImage-initramfs gzip - IMAGES := factory.img.gz kernel.dtb sysupgrade.img.gz + IMAGES := factory.img.gz sysupgrade.img.gz ARTIFACTS := apollo3g.dtb DEVICE_DTB := apollo3g.dtb FILESYSTEMS := ext4 squashfs diff --git a/target/linux/apm821xx/image/mbl_gen_hdd_img.sh b/target/linux/apm821xx/image/mbl_gen_hdd_img.sh index 6536ce9872..0e11e10226 100755 --- a/target/linux/apm821xx/image/mbl_gen_hdd_img.sh +++ b/target/linux/apm821xx/image/mbl_gen_hdd_img.sh @@ -1,4 +1,4 @@ -#!/usr/bin/env bash +#!/bin/sh set -x [ $# -eq 5 ] || { @@ -15,7 +15,7 @@ ROOTFSSIZE="$5" head=4 sect=63 -set `ptgen -o $OUTPUT -h $head -s $sect -l 4096 -t 83 -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M` +set $(ptgen -o $OUTPUT -h $head -s $sect -l 4096 -t 83 -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M) BOOTOFFSET="$(($1 / 512))" BOOTSIZE="$(($2 / 512))" diff --git a/target/linux/apm821xx/nand/config-default b/target/linux/apm821xx/nand/config-default index 1c05a83fb1..f53167f75b 100644 --- a/target/linux/apm821xx/nand/config-default +++ b/target/linux/apm821xx/nand/config-default @@ -31,6 +31,9 @@ CONFIG_THERMAL_HWMON=y CONFIG_HWMON=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_CMDLINE="rootfstype=squashfs noinitrd" +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_NDFC=y +CONFIG_MTD_RAW_NAND=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y diff --git a/target/linux/apm821xx/patches-5.4/111-crypto-crypto4xx-reduce-memory-fragmentation.patch b/target/linux/apm821xx/patches-5.4/111-crypto-crypto4xx-reduce-memory-fragmentation.patch new file mode 100644 index 0000000000..4d23b8816a --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/111-crypto-crypto4xx-reduce-memory-fragmentation.patch @@ -0,0 +1,99 @@ +From 3913dbe4b3256ead342572f7aba726a60ab5fd43 Mon Sep 17 00:00:00 2001 +Message-Id: <3913dbe4b3256ead342572f7aba726a60ab5fd43.1577917078.git.chunkeey@gmail.com> +From: Christian Lamparter +Date: Wed, 1 Jan 2020 22:28:28 +0100 +Subject: [PATCH 1/2] crypto: crypto4xx - reduce memory fragmentation +To: linux-crypto@vger.kernel.org +Cc: Herbert Xu + +With recent kernels (>5.2), the driver fails to probe, as the +allocation of the driver's scatter buffer fails with -ENOMEM. + +This happens in crypto4xx_build_sdr(). Where the driver tries +to get 512KiB (=PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD) of +continuous memory. This big chunk is by design, since the driver +uses this circumstance in the crypto4xx_copy_pkt_to_dst() to +its advantage: +"all scatter-buffers are all neatly organized in one big +continuous ringbuffer; So scatterwalk_map_and_copy() can be +instructed to copy a range of buffers in one go." + +The PowerPC arch does not have support for DMA_CMA. Hence, +this patch reorganizes the order in which the memory +allocations are done. Since the driver itself is responsible +for some of the issues. + +Signed-off-by: Christian Lamparter +--- + drivers/crypto/amcc/crypto4xx_core.c | 27 +++++++++++++-------------- + 1 file changed, 13 insertions(+), 14 deletions(-) + +--- a/drivers/crypto/amcc/crypto4xx_core.c ++++ b/drivers/crypto/amcc/crypto4xx_core.c +@@ -286,7 +286,8 @@ static u32 crypto4xx_build_gdr(struct cr + + static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev) + { +- dma_free_coherent(dev->core_dev->device, ++ if (dev->gdr) ++ dma_free_coherent(dev->core_dev->device, + sizeof(struct ce_gd) * PPC4XX_NUM_GD, + dev->gdr, dev->gdr_pa); + } +@@ -354,13 +355,6 @@ static u32 crypto4xx_build_sdr(struct cr + { + int i; + +- /* alloc memory for scatter descriptor ring */ +- dev->sdr = dma_alloc_coherent(dev->core_dev->device, +- sizeof(struct ce_sd) * PPC4XX_NUM_SD, +- &dev->sdr_pa, GFP_ATOMIC); +- if (!dev->sdr) +- return -ENOMEM; +- + dev->scatter_buffer_va = + dma_alloc_coherent(dev->core_dev->device, + PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD, +@@ -368,6 +362,13 @@ static u32 crypto4xx_build_sdr(struct cr + if (!dev->scatter_buffer_va) + return -ENOMEM; + ++ /* alloc memory for scatter descriptor ring */ ++ dev->sdr = dma_alloc_coherent(dev->core_dev->device, ++ sizeof(struct ce_sd) * PPC4XX_NUM_SD, ++ &dev->sdr_pa, GFP_ATOMIC); ++ if (!dev->sdr) ++ return -ENOMEM; ++ + for (i = 0; i < PPC4XX_NUM_SD; i++) { + dev->sdr[i].ptr = dev->scatter_buffer_pa + + PPC4XX_SD_BUFFER_SIZE * i; +@@ -1439,16 +1440,15 @@ static int crypto4xx_probe(struct platfo + spin_lock_init(&core_dev->lock); + INIT_LIST_HEAD(&core_dev->dev->alg_list); + ratelimit_default_init(&core_dev->dev->aead_ratelimit); ++ rc = crypto4xx_build_sdr(core_dev->dev); ++ if (rc) ++ goto err_build_sdr; + rc = crypto4xx_build_pdr(core_dev->dev); + if (rc) +- goto err_build_pdr; ++ goto err_build_sdr; + + rc = crypto4xx_build_gdr(core_dev->dev); + if (rc) +- goto err_build_pdr; +- +- rc = crypto4xx_build_sdr(core_dev->dev); +- if (rc) + goto err_build_sdr; + + /* Init tasklet for bottom half processing */ +@@ -1493,7 +1493,6 @@ err_iomap: + err_build_sdr: + crypto4xx_destroy_sdr(core_dev->dev); + crypto4xx_destroy_gdr(core_dev->dev); +-err_build_pdr: + crypto4xx_destroy_pdr(core_dev->dev); + kfree(core_dev->dev); + err_alloc_dev: diff --git a/target/linux/apm821xx/patches-5.4/112-crypto-crypto4xx-use-GFP_KERNEL-for-big-allocations.patch b/target/linux/apm821xx/patches-5.4/112-crypto-crypto4xx-use-GFP_KERNEL-for-big-allocations.patch new file mode 100644 index 0000000000..6668c3a91d --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/112-crypto-crypto4xx-use-GFP_KERNEL-for-big-allocations.patch @@ -0,0 +1,72 @@ +From 5bacaaea8a228bc46f402595b1694ef9128f3599 Mon Sep 17 00:00:00 2001 +Message-Id: <5bacaaea8a228bc46f402595b1694ef9128f3599.1577917078.git.chunkeey@gmail.com> +In-Reply-To: <3913dbe4b3256ead342572f7aba726a60ab5fd43.1577917078.git.chunkeey@gmail.com> +References: <3913dbe4b3256ead342572f7aba726a60ab5fd43.1577917078.git.chunkeey@gmail.com> +From: Christian Lamparter +Date: Wed, 1 Jan 2020 22:54:54 +0100 +Subject: [PATCH 2/2] crypto: crypto4xx - use GFP_KERNEL for big allocations +To: linux-crypto@vger.kernel.org +Cc: Herbert Xu + +The driver should use GFP_KERNEL for the bigger allocation +during the driver's crypto4xx_probe() and not GFP_ATOMIC in +my opinion. + +Signed-off-by: Christian Lamparter +--- + drivers/crypto/amcc/crypto4xx_core.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/crypto/amcc/crypto4xx_core.c ++++ b/drivers/crypto/amcc/crypto4xx_core.c +@@ -169,7 +169,7 @@ static u32 crypto4xx_build_pdr(struct cr + int i; + dev->pdr = dma_alloc_coherent(dev->core_dev->device, + sizeof(struct ce_pd) * PPC4XX_NUM_PD, +- &dev->pdr_pa, GFP_ATOMIC); ++ &dev->pdr_pa, GFP_KERNEL); + if (!dev->pdr) + return -ENOMEM; + +@@ -185,13 +185,13 @@ static u32 crypto4xx_build_pdr(struct cr + dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device, + sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD, + &dev->shadow_sa_pool_pa, +- GFP_ATOMIC); ++ GFP_KERNEL); + if (!dev->shadow_sa_pool) + return -ENOMEM; + + dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device, + sizeof(struct sa_state_record) * PPC4XX_NUM_PD, +- &dev->shadow_sr_pool_pa, GFP_ATOMIC); ++ &dev->shadow_sr_pool_pa, GFP_KERNEL); + if (!dev->shadow_sr_pool) + return -ENOMEM; + for (i = 0; i < PPC4XX_NUM_PD; i++) { +@@ -277,7 +277,7 @@ static u32 crypto4xx_build_gdr(struct cr + { + dev->gdr = dma_alloc_coherent(dev->core_dev->device, + sizeof(struct ce_gd) * PPC4XX_NUM_GD, +- &dev->gdr_pa, GFP_ATOMIC); ++ &dev->gdr_pa, GFP_KERNEL); + if (!dev->gdr) + return -ENOMEM; + +@@ -358,14 +358,14 @@ static u32 crypto4xx_build_sdr(struct cr + dev->scatter_buffer_va = + dma_alloc_coherent(dev->core_dev->device, + PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD, +- &dev->scatter_buffer_pa, GFP_ATOMIC); ++ &dev->scatter_buffer_pa, GFP_KERNEL); + if (!dev->scatter_buffer_va) + return -ENOMEM; + + /* alloc memory for scatter descriptor ring */ + dev->sdr = dma_alloc_coherent(dev->core_dev->device, + sizeof(struct ce_sd) * PPC4XX_NUM_SD, +- &dev->sdr_pa, GFP_ATOMIC); ++ &dev->sdr_pa, GFP_KERNEL); + if (!dev->sdr) + return -ENOMEM; + diff --git a/target/linux/apm821xx/patches-5.4/201-add-amcc-apollo3g-support.patch b/target/linux/apm821xx/patches-5.4/201-add-amcc-apollo3g-support.patch new file mode 100644 index 0000000000..e188954094 --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/201-add-amcc-apollo3g-support.patch @@ -0,0 +1,30 @@ +--- a/arch/powerpc/platforms/44x/Kconfig ++++ b/arch/powerpc/platforms/44x/Kconfig +@@ -121,6 +121,17 @@ config CANYONLANDS + help + This option enables support for the AMCC PPC460EX evaluation board. + ++config APOLLO3G ++ bool "Apollo3G" ++ depends on 44x ++ default n ++ select PPC44x_SIMPLE ++ select APM821xx ++ select IBM_EMAC_RGMII ++ select 460EX ++ help ++ This option enables support for the AMCC Apollo 3G board. ++ + config GLACIER + bool "Glacier" + depends on 44x +--- a/arch/powerpc/platforms/44x/ppc44x_simple.c ++++ b/arch/powerpc/platforms/44x/ppc44x_simple.c +@@ -47,6 +47,7 @@ machine_device_initcall(ppc44x_simple, p + * board.c file for it rather than adding it to this list. + */ + static char *board[] __initdata = { ++ "amcc,apollo3g", + "amcc,arches", + "amcc,bamboo", + "apm,bluestone", diff --git a/target/linux/apm821xx/patches-5.4/202-add-netgear-wndr4700-support.patch b/target/linux/apm821xx/patches-5.4/202-add-netgear-wndr4700-support.patch new file mode 100644 index 0000000000..b0619852b9 --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/202-add-netgear-wndr4700-support.patch @@ -0,0 +1,32 @@ +--- a/arch/powerpc/platforms/44x/Makefile ++++ b/arch/powerpc/platforms/44x/Makefile +@@ -4,6 +4,7 @@ ifneq ($(CONFIG_PPC4xx_CPM),y) + obj-y += idle.o + endif + obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o ++obj-$(CONFIG_WNDR4700) += wndr4700.o + obj-$(CONFIG_EBONY) += ebony.o + obj-$(CONFIG_SAM440EP) += sam440ep.o + obj-$(CONFIG_WARP) += warp.o +--- a/arch/powerpc/platforms/44x/Kconfig ++++ b/arch/powerpc/platforms/44x/Kconfig +@@ -243,6 +243,19 @@ config ICON + help + This option enables support for the AMCC PPC440SPe evaluation board. + ++config WNDR4700 ++ bool "WNDR4700" ++ depends on 44x ++ default n ++ select APM821xx ++ select PCI_MSI ++ select PPC4xx_MSI ++ select PPC4xx_PCI_EXPRESS ++ select IBM_EMAC_RGMII ++ select 460EX ++ help ++ This option enables support for the Netgear WNDR4700/WNDR4720 board. ++ + config XILINX_VIRTEX440_GENERIC_BOARD + bool "Generic Xilinx Virtex 5 FXT board support" + depends on 44x diff --git a/target/linux/apm821xx/patches-5.4/300-fix-atheros-nics-on-apm82181.patch b/target/linux/apm821xx/patches-5.4/300-fix-atheros-nics-on-apm82181.patch new file mode 100644 index 0000000000..110726d258 --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/300-fix-atheros-nics-on-apm82181.patch @@ -0,0 +1,51 @@ +--- a/arch/powerpc/platforms/4xx/pci.c ++++ b/arch/powerpc/platforms/4xx/pci.c +@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po + u32 val; + + /* +- * Do a software reset on PCIe ports. +- * This code is to fix the issue that pci drivers doesn't re-assign +- * bus number for PCIE devices after Uboot +- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 +- * PT quad port, SAS LSI 1064E) ++ * Only reset the PHY when no link is currently established. ++ * This is for the Atheros PCIe board which has problems to establish ++ * the link (again) after this PHY reset. All other currently tested ++ * PCIe boards don't show this problem. + */ +- +- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); +- mdelay(10); ++ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); ++ if (!(val & 0x00001000)) { ++ /* ++ * Do a software reset on PCIe ports. ++ * This code is to fix the issue that pci drivers doesn't re-assign ++ * bus number for PCIE devices after Uboot ++ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 ++ * PT quad port, SAS LSI 1064E) ++ */ ++ ++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); ++ mdelay(10); ++ } + + if (port->endpoint) + val = PTYPE_LEGACY_ENDPOINT << 20; +@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po + mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); + mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); + +- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); +- mdelay(50); +- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); ++ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); ++ if (!(val & 0x00001000)) { ++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); ++ mdelay(50); ++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); ++ } + + mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, + mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | diff --git a/target/linux/apm821xx/patches-5.4/301-fix-memory-map-wndr4700.patch b/target/linux/apm821xx/patches-5.4/301-fix-memory-map-wndr4700.patch new file mode 100644 index 0000000000..9c0ed35cf1 --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/301-fix-memory-map-wndr4700.patch @@ -0,0 +1,14 @@ +--- a/arch/powerpc/platforms/4xx/pci.c ++++ b/arch/powerpc/platforms/4xx/pci.c +@@ -1904,9 +1904,9 @@ static void __init ppc4xx_configure_pcie + * if it works + */ + out_le32(mbase + PECFG_PIM0LAL, 0x00000000); +- out_le32(mbase + PECFG_PIM0LAH, 0x00000000); ++ out_le32(mbase + PECFG_PIM0LAH, 0x00000008); + out_le32(mbase + PECFG_PIM1LAL, 0x00000000); +- out_le32(mbase + PECFG_PIM1LAH, 0x00000000); ++ out_le32(mbase + PECFG_PIM1LAH, 0x0000000c); + out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); + out_le32(mbase + PECFG_PIM01SAL, 0x00000000); + diff --git a/target/linux/apm821xx/patches-5.4/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch b/target/linux/apm821xx/patches-5.4/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch new file mode 100644 index 0000000000..36eab9349b --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch @@ -0,0 +1,1026 @@ +Subject: [PATCH v2 1/5] usb: xhci: add firmware loader for uPD720201 and uPD720202 w/o ROM +Date: Fri, 21 Jun 2019 14:29:09 +0530 +Message-Id: <20190621085913.8722-2-vkoul@kernel.org> +From: Christian Lamparter + +This patch adds a firmware loader for the uPD720201K8-711-BAC-A +and uPD720202K8-711-BAA-A variant. Both of these chips are listed +in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as +devices which need the firmware loader on page 2 in order to +work as they "do not support the External ROM". + +The "Firmware Download Sequence" is describe in chapter +"7.1 FW Download Interface" R19UH0078EJ0500 Rev.5.00 page 131. + +The firmware "K2013080.mem" is available from a USB3.0 Host to +PCIe Adapter (PP2U-E card) "Firmware download" archive. An +alternative version can be sourced from Netgear's WNDR4700 GPL +archives. + +The release notes of the PP2U-E's "Firmware Download" ver 2.0.1.3 +(2012-06-15) state that the firmware is for the following devices: + - uPD720201 ES 2.0 sample whose revision ID is 2. + - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3. + - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2. + +Cc: Yoshihiro Shimoda +Signed-off-by: Christian Lamparter +Signed-off-by: Bjorn Andersson +[vkoul: fixed comments: + used macros for timeout count and delay + removed renesas_fw_alive_check + cleaned renesas_fw_callback + removed recurion for renesas_fw_download + added MODULE_FIRMWARE] +Signed-off-by: Vinod Koul +--- + drivers/usb/host/xhci-pci.c | 458 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 458 insertions(+) + +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -12,6 +12,8 @@ + #include + #include + #include ++#include ++#include + + #include "xhci.h" + #include "xhci-trace.h" +@@ -57,6 +59,44 @@ + #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc + #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 + ++#define RENESAS_FW_VERSION 0x6C ++#define RENESAS_ROM_CONFIG 0xF0 ++#define RENESAS_FW_STATUS 0xF4 ++#define RENESAS_FW_STATUS_MSB 0xF5 ++#define RENESAS_ROM_STATUS 0xF6 ++#define RENESAS_ROM_STATUS_MSB 0xF7 ++#define RENESAS_DATA0 0xF8 ++#define RENESAS_DATA1 0xFC ++ ++#define RENESAS_FW_VERSION_FIELD GENMASK(23, 7) ++#define RENESAS_FW_VERSION_OFFSET 8 ++ ++#define RENESAS_FW_STATUS_DOWNLOAD_ENABLE BIT(0) ++#define RENESAS_FW_STATUS_LOCK BIT(1) ++#define RENESAS_FW_STATUS_RESULT GENMASK(6, 4) ++ #define RENESAS_FW_STATUS_INVALID 0 ++ #define RENESAS_FW_STATUS_SUCCESS BIT(4) ++ #define RENESAS_FW_STATUS_ERROR BIT(5) ++#define RENESAS_FW_STATUS_SET_DATA0 BIT(8) ++#define RENESAS_FW_STATUS_SET_DATA1 BIT(9) ++ ++#define RENESAS_ROM_STATUS_ACCESS BIT(0) ++#define RENESAS_ROM_STATUS_ERASE BIT(1) ++#define RENESAS_ROM_STATUS_RELOAD BIT(2) ++#define RENESAS_ROM_STATUS_RESULT GENMASK(6, 4) ++ #define RENESAS_ROM_STATUS_INVALID 0 ++ #define RENESAS_ROM_STATUS_SUCCESS BIT(4) ++ #define RENESAS_ROM_STATUS_ERROR BIT(5) ++#define RENESAS_ROM_STATUS_SET_DATA0 BIT(8) ++#define RENESAS_ROM_STATUS_SET_DATA1 BIT(9) ++#define RENESAS_ROM_STATUS_ROM_EXISTS BIT(15) ++ ++#define RENESAS_ROM_ERASE_MAGIC 0x5A65726F ++#define RENESAS_ROM_WRITE_MAGIC 0x53524F4D ++ ++#define RENESAS_RETRY 1000 ++#define RENESAS_DELAY 10 ++ + static const char hcd_name[] = "xhci_hcd"; + + static struct hc_driver __read_mostly xhci_pci_hc_driver; +@@ -284,6 +324,873 @@ static void xhci_pme_acpi_rtd3_enable(st + static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } + #endif /* CONFIG_ACPI */ + ++static const struct renesas_fw_entry { ++ const char *firmware_name; ++ u16 device; ++ u8 revision; ++ u16 expected_version; ++} renesas_fw_table[] = { ++ /* ++ * Only the uPD720201K8-711-BAC-A or uPD720202K8-711-BAA-A ++ * are listed in R19UH0078EJ0500 Rev.5.00 as devices which ++ * need the software loader. ++ * ++ * PP2U/ReleaseNote_USB3-201-202-FW.txt: ++ * ++ * Note: This firmware is for the following devices. ++ * - uPD720201 ES 2.0 sample whose revision ID is 2. ++ * - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3. ++ * - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2. ++ * ++ * Entry expected_version should be kept in increasing order for a ++ * chip, so that driver will pick first version and if that fails ++ * then next one will be picked ++ */ ++ { "K2013080.mem", 0x0014, 0x02, 0x2013 }, ++ { "K2013080.mem", 0x0014, 0x03, 0x2013 }, ++ { "K2026090.mem", 0x0014, 0x03, 0x2026 }, ++ { "K2013080.mem", 0x0015, 0x02, 0x2013 }, ++ { "K2026090.mem", 0x0015, 0x02, 0x2026 }, ++}; ++ ++MODULE_FIRMWARE("K2013080.mem"); ++MODULE_FIRMWARE("K2026090.mem"); ++ ++static const struct renesas_fw_entry *renesas_needs_fw_dl(struct pci_dev *dev) ++{ ++ const struct renesas_fw_entry *entry; ++ size_t i; ++ ++ /* This loader will only work with a RENESAS device. */ ++ if (!(dev->vendor == PCI_VENDOR_ID_RENESAS)) ++ return NULL; ++ ++ for (i = 0; i < ARRAY_SIZE(renesas_fw_table); i++) { ++ entry = &renesas_fw_table[i]; ++ if (entry->device == dev->device && ++ entry->revision == dev->revision) ++ return entry; ++ } ++ ++ return NULL; ++} ++ ++static const struct ++renesas_fw_entry *renesas_get_next_entry(struct pci_dev *dev, ++ const struct renesas_fw_entry *entry) ++{ ++ const struct renesas_fw_entry *next_entry; ++ size_t i; ++ ++ for (i = 0; i < ARRAY_SIZE(renesas_fw_table); i++) { ++ next_entry = &renesas_fw_table[i]; ++ if (next_entry->device == dev->device && ++ next_entry->revision == dev->revision && ++ next_entry->expected_version > entry->expected_version) ++ return next_entry; ++ } ++ ++ return NULL; ++} ++ ++static int renesas_fw_download_image(struct pci_dev *dev, ++ const u32 *fw, ++ size_t step) ++{ ++ size_t i; ++ int err; ++ u8 fw_status; ++ bool data0_or_data1; ++ ++ /* ++ * The hardware does alternate between two 32-bit pages. ++ * (This is because each row of the firmware is 8 bytes). ++ * ++ * for even steps we use DATA0, for odd steps DATA1. ++ */ ++ data0_or_data1 = (step & 1) == 1; ++ ++ /* step+1. Read "Set DATAX" and confirm it is cleared. */ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ err = pci_read_config_byte(dev, RENESAS_FW_STATUS_MSB, ++ &fw_status); ++ if (err) ++ return pcibios_err_to_errno(err); ++ if (!(fw_status & BIT(data0_or_data1))) ++ break; ++ ++ udelay(RENESAS_DELAY); ++ } ++ if (i == RENESAS_RETRY) ++ return -ETIMEDOUT; ++ ++ /* ++ * step+2. Write FW data to "DATAX". ++ * "LSB is left" => force little endian ++ */ ++ err = pci_write_config_dword(dev, data0_or_data1 ? ++ RENESAS_DATA1 : RENESAS_DATA0, ++ (__force u32)cpu_to_le32(fw[step])); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ udelay(100); ++ ++ /* step+3. Set "Set DATAX". */ ++ err = pci_write_config_byte(dev, RENESAS_FW_STATUS_MSB, ++ BIT(data0_or_data1)); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ return 0; ++} ++ ++static int renesas_fw_verify(struct pci_dev *dev, ++ const void *fw_data, ++ size_t length) ++{ ++ const struct renesas_fw_entry *entry = renesas_needs_fw_dl(dev); ++ u16 fw_version_pointer; ++ u16 fw_version; ++ ++ if (!entry) ++ return -EINVAL; ++ ++ /* ++ * The Firmware's Data Format is describe in ++ * "6.3 Data Format" R19UH0078EJ0500 Rev.5.00 page 124 ++ */ ++ ++ /* "Each row is 8 bytes". => firmware size must be a multiple of 8. */ ++ if (length % 8 != 0) ++ dev_warn(&dev->dev, "firmware size is not a multiple of 8."); ++ ++ /* ++ * The bootrom chips of the big brother have sizes up to 64k, let's ++ * assume that's the biggest the firmware can get. ++ */ ++ if (length < 0x1000 || length >= 0x10000) { ++ dev_err(&dev->dev, "firmware is size %zd is not (4k - 64k).", ++ length); ++ return -EINVAL; ++ } ++ ++ /* The First 2 bytes are fixed value (55aa). "LSB on Left" */ ++ if (get_unaligned_le16(fw_data) != 0x55aa) { ++ dev_err(&dev->dev, "no valid firmware header found."); ++ return -EINVAL; ++ } ++ ++ /* verify the firmware version position and print it. */ ++ fw_version_pointer = get_unaligned_le16(fw_data + 4); ++ if (fw_version_pointer + 2 >= length) { ++ dev_err(&dev->dev, ++ "firmware version pointer is outside of the firmware image."); ++ return -EINVAL; ++ } ++ ++ fw_version = get_unaligned_le16(fw_data + fw_version_pointer); ++ dev_dbg(&dev->dev, "got firmware version: %02x.", fw_version); ++ ++ if (fw_version != entry->expected_version) { ++ dev_err(&dev->dev, ++ "firmware version mismatch, expected version: %02x.", ++ entry->expected_version); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int renesas_check_rom_state(struct pci_dev *pdev) ++{ ++ const struct renesas_fw_entry *entry; ++ u16 rom_state; ++ u32 version; ++ bool valid_version = false; ++ int err, i; ++ ++ /* check FW version */ ++ err = pci_read_config_dword(pdev, RENESAS_FW_VERSION, &version); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ version &= RENESAS_FW_VERSION_FIELD; ++ version = version >> RENESAS_FW_VERSION_OFFSET; ++ dev_dbg(&pdev->dev, "Found FW version loaded is %x\n", version); ++ ++ /* treat version in renesas_fw_table as correct ones */ ++ for (i = 0; i < ARRAY_SIZE(renesas_fw_table); i++) { ++ entry = &renesas_fw_table[i]; ++ if (version == entry->expected_version) { ++ dev_dbg(&pdev->dev, "Detected valid ROM version..\n"); ++ valid_version = true; ++ } ++ } ++ ++ /* ++ * Test if ROM is present and loaded, if so we can skip everything ++ */ ++ err = pci_read_config_word(pdev, RENESAS_ROM_STATUS, &rom_state); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ if (rom_state & BIT(15)) { ++ /* ROM exists */ ++ dev_dbg(&pdev->dev, "ROM exists\n"); ++ ++ /* Check the "Result Code" Bits (6:4) and act accordingly */ ++ switch (rom_state & RENESAS_ROM_STATUS_RESULT) { ++ case RENESAS_ROM_STATUS_SUCCESS: ++ dev_dbg(&pdev->dev, "Success ROM load..."); ++ /* we have valid version and status so success */ ++ if (valid_version) ++ return 0; ++ break; ++ ++ case RENESAS_ROM_STATUS_INVALID: /* No result yet */ ++ dev_dbg(&pdev->dev, "No result as it is ROM..."); ++ /* we have valid version and status so success */ ++ if (valid_version) ++ return 0; ++ break; ++ ++ case RENESAS_ROM_STATUS_ERROR: /* Error State */ ++ default: /* All other states are marked as "Reserved states" */ ++ dev_err(&pdev->dev, "Invalid ROM.."); ++ break; ++ } ++ } ++ ++ return -EIO; ++} ++ ++static int renesas_fw_check_running(struct pci_dev *pdev) ++{ ++ int err; ++ u8 fw_state; ++ ++ /* Check if device has ROM and loaded, if so skip everything */ ++ err = renesas_check_rom_state(pdev); ++ if (!err) ++ return err; ++ ++ /* ++ * Test if the device is actually needing the firmware. As most ++ * BIOSes will initialize the device for us. If the device is ++ * initialized. ++ */ ++ err = pci_read_config_byte(pdev, RENESAS_FW_STATUS, &fw_state); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ /* ++ * Check if "FW Download Lock" is locked. If it is and the FW is ++ * ready we can simply continue. If the FW is not ready, we have ++ * to give up. ++ */ ++ if (fw_state & RENESAS_FW_STATUS_LOCK) { ++ dev_dbg(&pdev->dev, "FW Download Lock is engaged."); ++ ++ if (fw_state & RENESAS_FW_STATUS_SUCCESS) ++ return 0; ++ ++ dev_err(&pdev->dev, ++ "FW Download Lock is set and FW is not ready. Giving Up."); ++ return -EIO; ++ } ++ ++ /* ++ * Check if "FW Download Enable" is set. If someone (us?) tampered ++ * with it and it can't be resetted, we have to give up too... and ++ * ask for a forgiveness and a reboot. ++ */ ++ if (fw_state & RENESAS_FW_STATUS_DOWNLOAD_ENABLE) { ++ dev_err(&pdev->dev, ++ "FW Download Enable is stale. Giving Up (poweroff/reboot needed)."); ++ return -EIO; ++ } ++ ++ /* Otherwise, Check the "Result Code" Bits (6:4) and act accordingly */ ++ switch (fw_state & RENESAS_FW_STATUS_RESULT) { ++ case 0: /* No result yet */ ++ dev_dbg(&pdev->dev, "FW is not ready/loaded yet."); ++ ++ /* tell the caller, that this device needs the firmware. */ ++ return 1; ++ ++ case RENESAS_FW_STATUS_SUCCESS: /* Success, device should be working. */ ++ dev_dbg(&pdev->dev, "FW is ready."); ++ return 0; ++ ++ case RENESAS_FW_STATUS_ERROR: /* Error State */ ++ dev_err(&pdev->dev, ++ "hardware is in an error state. Giving up (poweroff/reboot needed)."); ++ return -ENODEV; ++ ++ default: /* All other states are marked as "Reserved states" */ ++ dev_err(&pdev->dev, ++ "hardware is in an invalid state %lx. Giving up (poweroff/reboot needed).", ++ (fw_state & RENESAS_FW_STATUS_RESULT) >> 4); ++ return -EINVAL; ++ } ++} ++ ++static int renesas_fw_download(struct pci_dev *pdev, ++ const struct firmware *fw) ++{ ++ const u32 *fw_data = (const u32 *)fw->data; ++ size_t i; ++ int err; ++ u8 fw_status; ++ ++ /* ++ * For more information and the big picture: please look at the ++ * "Firmware Download Sequence" in "7.1 FW Download Interface" ++ * of R19UH0078EJ0500 Rev.5.00 page 131 ++ */ ++ ++ /* ++ * 0. Set "FW Download Enable" bit in the ++ * "FW Download Control & Status Register" at 0xF4 ++ */ ++ err = pci_write_config_byte(pdev, RENESAS_FW_STATUS, ++ RENESAS_FW_STATUS_DOWNLOAD_ENABLE); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ /* 1 - 10 follow one step after the other. */ ++ for (i = 0; i < fw->size / 4; i++) { ++ err = renesas_fw_download_image(pdev, fw_data, i); ++ if (err) { ++ dev_err(&pdev->dev, ++ "Firmware Download Step %zd failed at position %zd bytes with (%d).", ++ i, i * 4, err); ++ return err; ++ } ++ } ++ ++ /* ++ * This sequence continues until the last data is written to ++ * "DATA0" or "DATA1". Naturally, we wait until "SET DATA0/1" ++ * is cleared by the hardware beforehand. ++ */ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ err = pci_read_config_byte(pdev, RENESAS_FW_STATUS_MSB, ++ &fw_status); ++ if (err) ++ return pcibios_err_to_errno(err); ++ if (!(fw_status & (BIT(0) | BIT(1)))) ++ break; ++ ++ udelay(RENESAS_DELAY); ++ } ++ if (i == RENESAS_RETRY) ++ dev_warn(&pdev->dev, "Final Firmware Download step timed out."); ++ ++ /* ++ * 11. After finishing writing the last data of FW, the ++ * System Software must clear "FW Download Enable" ++ */ ++ err = pci_write_config_byte(pdev, RENESAS_FW_STATUS, 0); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ /* 12. Read "Result Code" and confirm it is good. */ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ err = pci_read_config_byte(pdev, RENESAS_FW_STATUS, &fw_status); ++ if (err) ++ return pcibios_err_to_errno(err); ++ if (fw_status & RENESAS_FW_STATUS_SUCCESS) ++ break; ++ ++ udelay(RENESAS_DELAY); ++ } ++ if (i == RENESAS_RETRY) { ++ /* Timed out / Error - let's see if we can fix this */ ++ err = renesas_fw_check_running(pdev); ++ switch (err) { ++ case 0: /* ++ * we shouldn't end up here. ++ * maybe it took a little bit longer. ++ * But all should be well? ++ */ ++ break; ++ ++ case 1: /* (No result yet! */ ++ return -ETIMEDOUT; ++ ++ default: ++ return err; ++ } ++ } ++ /* ++ * Optional last step: Engage Firmware Lock ++ * ++ * err = pci_write_config_byte(pdev, 0xF4, BIT(2)); ++ * if (err) ++ * return pcibios_err_to_errno(err); ++ */ ++ ++ return 0; ++} ++ ++struct renesas_fw_ctx { ++ struct pci_dev *pdev; ++ const struct pci_device_id *id; ++ bool resume; ++ const struct renesas_fw_entry *entry; ++}; ++ ++static int xhci_pci_probe(struct pci_dev *pdev, ++ const struct pci_device_id *id); ++ ++static bool renesas_check_rom(struct pci_dev *pdev) ++{ ++ u16 rom_status; ++ int retval; ++ ++ /* 1. Check if external ROM exists */ ++ retval = pci_read_config_word(pdev, RENESAS_ROM_STATUS, &rom_status); ++ if (retval) ++ return false; ++ ++ rom_status &= RENESAS_ROM_STATUS_ROM_EXISTS; ++ if (rom_status) { ++ dev_dbg(&pdev->dev, "External ROM exists\n"); ++ return true; /* External ROM exists */ ++ } ++ ++ return false; ++} ++ ++static void renesas_rom_erase(struct pci_dev *pdev) ++{ ++ int retval, i; ++ u8 status; ++ ++ dev_dbg(&pdev->dev, "Performing ROM Erase...\n"); ++ retval = pci_write_config_dword(pdev, RENESAS_DATA0, ++ RENESAS_ROM_ERASE_MAGIC); ++ if (retval) { ++ dev_err(&pdev->dev, "ROM erase, magic word write failed: %d\n", ++ pcibios_err_to_errno(retval)); ++ return; ++ } ++ ++ retval = pci_read_config_byte(pdev, RENESAS_ROM_STATUS, &status); ++ if (retval) { ++ dev_err(&pdev->dev, "ROM status read failed: %d\n", ++ pcibios_err_to_errno(retval)); ++ return; ++ } ++ status |= RENESAS_ROM_STATUS_ERASE; ++ retval = pci_write_config_byte(pdev, RENESAS_ROM_STATUS, status); ++ if (retval) { ++ dev_err(&pdev->dev, "ROM erase set word write failed\n"); ++ return; ++ } ++ ++ /* sleep a bit while ROM is erased */ ++ msleep(20); ++ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ retval = pci_read_config_byte(pdev, RENESAS_ROM_STATUS, ++ &status); ++ status &= RENESAS_ROM_STATUS_ERASE; ++ if (!status) ++ break; ++ ++ mdelay(RENESAS_DELAY); ++ } ++ ++ if (i == RENESAS_RETRY) ++ dev_dbg(&pdev->dev, "Chip erase timedout: %x\n", status); ++ ++ dev_dbg(&pdev->dev, "ROM Erase... Done success\n"); ++} ++ ++static bool renesas_download_rom(struct pci_dev *pdev, ++ const u32 *fw, size_t step) ++{ ++ bool data0_or_data1; ++ u8 fw_status; ++ size_t i; ++ int err; ++ ++ /* ++ * The hardware does alternate between two 32-bit pages. ++ * (This is because each row of the firmware is 8 bytes). ++ * ++ * for even steps we use DATA0, for odd steps DATA1. ++ */ ++ data0_or_data1 = (step & 1) == 1; ++ ++ /* Read "Set DATAX" and confirm it is cleared. */ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ err = pci_read_config_byte(pdev, RENESAS_ROM_STATUS_MSB, ++ &fw_status); ++ if (err) { ++ dev_err(&pdev->dev, "Read ROM Status failed: %d\n", ++ pcibios_err_to_errno(err)); ++ return false; ++ } ++ if (!(fw_status & BIT(data0_or_data1))) ++ break; ++ ++ udelay(RENESAS_DELAY); ++ } ++ if (i == RENESAS_RETRY) { ++ dev_err(&pdev->dev, "Timeout for Set DATAX step: %zd\n", step); ++ return false; ++ } ++ ++ /* ++ * Write FW data to "DATAX". ++ * "LSB is left" => force little endian ++ */ ++ err = pci_write_config_dword(pdev, data0_or_data1 ? ++ RENESAS_DATA1 : RENESAS_DATA0, ++ (__force u32)cpu_to_le32(fw[step])); ++ if (err) { ++ dev_err(&pdev->dev, "Write to DATAX failed: %d\n", ++ pcibios_err_to_errno(err)); ++ return false; ++ } ++ ++ udelay(100); ++ ++ /* Set "Set DATAX". */ ++ err = pci_write_config_byte(pdev, RENESAS_ROM_STATUS_MSB, ++ BIT(data0_or_data1)); ++ if (err) { ++ dev_err(&pdev->dev, "Write config for DATAX failed: %d\n", ++ pcibios_err_to_errno(err)); ++ return false; ++ } ++ ++ return true; ++} ++ ++static bool renesas_setup_rom(struct pci_dev *pdev, const struct firmware *fw) ++{ ++ const u32 *fw_data = (const u32 *)fw->data; ++ int err, i; ++ u8 status; ++ ++ /* 2. Write magic word to Data0 */ ++ err = pci_write_config_dword(pdev, RENESAS_DATA0, ++ RENESAS_ROM_WRITE_MAGIC); ++ if (err) ++ return false; ++ ++ /* 3. Set External ROM access */ ++ err = pci_write_config_byte(pdev, RENESAS_ROM_STATUS, ++ RENESAS_ROM_STATUS_ACCESS); ++ if (err) ++ goto remove_bypass; ++ ++ /* 4. Check the result */ ++ err = pci_read_config_byte(pdev, RENESAS_ROM_STATUS, &status); ++ if (err) ++ goto remove_bypass; ++ status &= GENMASK(6, 4); ++ if (status) { ++ dev_err(&pdev->dev, ++ "setting external rom failed: %x\n", status); ++ goto remove_bypass; ++ } ++ ++ /* 5 to 16 Write FW to DATA0/1 while checking SetData0/1 */ ++ for (i = 0; i < fw->size / 4; i++) { ++ err = renesas_download_rom(pdev, fw_data, i); ++ if (!err) { ++ dev_err(&pdev->dev, ++ "ROM Download Step %d failed at position %d bytes\n", ++ i, i * 4); ++ goto remove_bypass; ++ } ++ } ++ ++ /* ++ * wait till DATA0/1 is cleared ++ */ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ err = pci_read_config_byte(pdev, RENESAS_ROM_STATUS_MSB, ++ &status); ++ if (err) ++ goto remove_bypass; ++ if (!(status & (BIT(0) | BIT(1)))) ++ break; ++ ++ udelay(RENESAS_DELAY); ++ } ++ if (i == RENESAS_RETRY) { ++ dev_err(&pdev->dev, "Final Firmware ROM Download step timed out\n"); ++ goto remove_bypass; ++ } ++ ++ /* 17. Remove bypass */ ++ err = pci_write_config_byte(pdev, RENESAS_ROM_STATUS, 0); ++ if (err) ++ return false; ++ ++ udelay(10); ++ ++ /* 18. check result */ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ err = pci_read_config_byte(pdev, RENESAS_ROM_STATUS, &status); ++ if (err) { ++ dev_err(&pdev->dev, "Read ROM status failed:%d\n", ++ pcibios_err_to_errno(err)); ++ return false; ++ } ++ status &= RENESAS_ROM_STATUS_RESULT; ++ if (status == RENESAS_ROM_STATUS_SUCCESS) { ++ dev_dbg(&pdev->dev, "Download ROM success\n"); ++ break; ++ } ++ udelay(RENESAS_DELAY); ++ } ++ if (i == RENESAS_RETRY) { /* Timed out */ ++ dev_err(&pdev->dev, ++ "Download to external ROM TO: %x\n", status); ++ return false; ++ } ++ ++ dev_dbg(&pdev->dev, "Download to external ROM scuceeded\n"); ++ ++ /* Last step set Reload */ ++ err = pci_write_config_byte(pdev, RENESAS_ROM_STATUS, ++ RENESAS_ROM_STATUS_RELOAD); ++ if (err) { ++ dev_err(&pdev->dev, "Set ROM execute failed: %d\n", ++ pcibios_err_to_errno(err)); ++ return false; ++ } ++ ++ /* ++ * wait till Reload is cleared ++ */ ++ for (i = 0; i < RENESAS_RETRY; i++) { ++ err = pci_read_config_byte(pdev, RENESAS_ROM_STATUS, &status); ++ if (err) ++ return false; ++ if (!(status & RENESAS_ROM_STATUS_RELOAD)) ++ break; ++ ++ udelay(RENESAS_DELAY); ++ } ++ if (i == RENESAS_RETRY) { ++ dev_err(&pdev->dev, "ROM Exec timed out: %x\n", status); ++ return false; ++ } ++ ++ return true; ++ ++remove_bypass: ++ pci_write_config_byte(pdev, RENESAS_ROM_STATUS, 0); ++ return false; ++} ++ ++static void renesas_fw_callback(const struct firmware *fw, ++ void *context) ++{ ++ struct renesas_fw_ctx *ctx = context; ++ struct pci_dev *pdev = ctx->pdev; ++ struct device *parent = pdev->dev.parent; ++ const struct renesas_fw_entry *next_entry; ++ bool rom; ++ int err; ++ ++ if (!fw) { ++ dev_err(&pdev->dev, "firmware failed to load\n"); ++ /* ++ * we didn't find firmware, check if we have another ++ * entry for this device ++ */ ++ next_entry = renesas_get_next_entry(ctx->pdev, ctx->entry); ++ if (next_entry) { ++ ctx->entry = next_entry; ++ dev_dbg(&pdev->dev, "Found next entry, requesting: %s\n", ++ next_entry->firmware_name); ++ request_firmware_nowait(THIS_MODULE, 1, ++ next_entry->firmware_name, ++ &pdev->dev, GFP_KERNEL, ++ ctx, renesas_fw_callback); ++ return; ++ } else { ++ goto cleanup; ++ } ++ } ++ ++ err = renesas_fw_verify(pdev, fw->data, fw->size); ++ if (err) ++ goto cleanup; ++ ++ /* Check if the device has external ROM */ ++ rom = renesas_check_rom(pdev); ++ if (rom) { ++ /* perfrom chip erase first */ ++ renesas_rom_erase(pdev); ++ ++ /* lets try loading fw on ROM first */ ++ rom = renesas_setup_rom(pdev, fw); ++ if (!rom) { ++ dev_err(&pdev->dev, ++ "ROM load failed, falling back on FW load\n"); ++ } else { ++ dev_dbg(&pdev->dev, "ROM load done..\n"); ++ ++ release_firmware(fw); ++ goto do_probe; ++ } ++ } ++ ++ err = renesas_fw_download(pdev, fw); ++ release_firmware(fw); ++ if (err) { ++ dev_err(&pdev->dev, "firmware failed to download (%d).", err); ++ goto cleanup; ++ } ++ ++do_probe: ++ if (ctx->resume) ++ return; ++ ++ err = xhci_pci_probe(pdev, ctx->id); ++ if (!err) { ++ /* everything worked */ ++ devm_kfree(&pdev->dev, ctx); ++ return; ++ } ++ ++cleanup: ++ /* in case of an error - fall through */ ++ dev_info(&pdev->dev, "Unloading driver"); ++ ++ if (parent) ++ device_lock(parent); ++ ++ device_release_driver(&pdev->dev); ++ ++ if (parent) ++ device_unlock(parent); ++ ++ pci_dev_put(pdev); ++} ++ ++static int renesas_fw_alive_check(struct pci_dev *pdev) ++{ ++ const struct renesas_fw_entry *entry; ++ ++ /* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */ ++ entry = renesas_needs_fw_dl(pdev); ++ if (!entry) ++ return 0; ++ ++ return renesas_fw_check_running(pdev); ++} ++ ++static int renesas_fw_download_to_hw(struct pci_dev *pdev, ++ const struct pci_device_id *id, ++ bool do_resume) ++{ ++ const struct renesas_fw_entry *entry; ++ struct renesas_fw_ctx *ctx; ++ int err; ++ ++ /* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */ ++ entry = renesas_needs_fw_dl(pdev); ++ if (!entry) ++ return 0; ++ ++ err = renesas_fw_check_running(pdev); ++ /* Continue ahead, if the firmware is already running. */ ++ if (err == 0) ++ return 0; ++ ++ if (err != 1) ++ return err; ++ ++ ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) ++ return -ENOMEM; ++ ctx->pdev = pdev; ++ ctx->resume = do_resume; ++ ctx->id = id; ++ ctx->entry = entry; ++ ++ pci_dev_get(pdev); ++ err = request_firmware_nowait(THIS_MODULE, 1, entry->firmware_name, ++ &pdev->dev, GFP_KERNEL, ++ ctx, renesas_fw_callback); ++ if (err) { ++ pci_dev_put(pdev); ++ return err; ++ } ++ ++ /* ++ * The renesas_fw_callback() callback will continue the probe ++ * process, once it aquires the firmware. ++ */ ++ return 1; ++} ++ ++static int renesas_check_if_fw_dl_is_needed(struct pci_dev *pdev) ++{ ++ int err; ++ u8 fw_state; ++ ++ /* ++ * Only the uPD720201K8-711-BAC-A or uPD720202K8-711-BAA-A ++ * are listed in R19UH0078EJ0500 Rev.5.00 as devices which ++ * need a firmware in order to work. ++ * ++ * - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2. ++ * - uPD720201 ES 2.0 sample whose revision ID is 2. ++ * - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3. ++ */ ++ if (!((pdev->vendor == PCI_VENDOR_ID_RENESAS) && ++ ((pdev->device == 0x0015 && pdev->revision == 0x02) || ++ (pdev->device == 0x0014 && ++ (pdev->revision == 0x02 || pdev->revision == 0x03))))) ++ return 0; ++ ++ /* Check if device has ROM and loaded, if so skip everything */ ++ err = renesas_check_rom_state(pdev); ++ if (!err) ++ return err; ++ ++ /* ++ * Test if the firmware was uploaded and is running. ++ * As most BIOSes will initialize the device for us. ++ */ ++ err = pci_read_config_byte(pdev, RENESAS_FW_STATUS, &fw_state); ++ if (err) ++ return pcibios_err_to_errno(err); ++ ++ /* Check the "Result Code" Bits (6:4) and act accordingly */ ++ switch (fw_state & RENESAS_FW_STATUS_RESULT) { ++ case 0: /* No result yet */ ++ dev_err(&pdev->dev, "FW is not ready/loaded yet."); ++ return -ENODEV; ++ ++ case RENESAS_FW_STATUS_SUCCESS: ++ dev_dbg(&pdev->dev, "FW is ready."); ++ return 0; ++ ++ case RENESAS_FW_STATUS_ERROR: ++ dev_err(&pdev->dev, "HW is in an error state."); ++ return -ENODEV; ++ ++ default: /* All other states are marked as "Reserved states" */ ++ dev_err(&pdev->dev, "HW is in an invalid state (%x).", ++ (fw_state & 0x70) >> 4); ++ return -EINVAL; ++ } ++} ++ + /* called during probe() after chip reset completes */ + static int xhci_pci_setup(struct usb_hcd *hcd) + { +@@ -325,6 +1232,27 @@ static int xhci_pci_probe(struct pci_dev + struct hc_driver *driver; + struct usb_hcd *hcd; + ++ /* ++ * Check if this device is a RENESAS uPD720201/2 device. ++ * Otherwise, we can continue with xhci_pci_probe as usual. ++ */ ++ retval = renesas_fw_download_to_hw(dev, id, false); ++ switch (retval) { ++ case 0: ++ break; ++ ++ case 1: /* let it load the firmware and recontinue the probe. */ ++ return 0; ++ ++ default: ++ return retval; ++ }; ++ ++ /* Check if this device is a RENESAS uPD720201/2 device. */ ++ retval = renesas_check_if_fw_dl_is_needed(dev); ++ if (retval) ++ return retval; ++ + driver = (struct hc_driver *)id->driver_data; + + /* Prevent runtime suspending between USB-2 and USB-3 initialization */ +@@ -386,6 +1314,16 @@ static void xhci_pci_remove(struct pci_d + { + struct xhci_hcd *xhci; + ++ if (renesas_fw_alive_check(dev)) { ++ /* ++ * bail out early, if this was a renesas device w/o FW. ++ * Else we might hit the NMI watchdog in xhci_handsake ++ * during xhci_reset as part of the driver's unloading. ++ * which we forced in the renesas_fw_callback(). ++ */ ++ return; ++ } ++ + xhci = hcd_to_xhci(pci_get_drvdata(dev)); + xhci->xhc_state |= XHCI_STATE_REMOVING; + +@@ -513,6 +1451,11 @@ static int xhci_pci_resume(struct usb_hc + if (pdev->vendor == PCI_VENDOR_ID_INTEL) + usb_enable_intel_xhci_ports(pdev); + ++ /* Check if this device is a RENESAS uPD720201/2 device. */ ++ retval = renesas_check_if_fw_dl_is_needed(pdev); ++ if (retval) ++ return retval; ++ + if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) + xhci_ssic_port_unused_quirk(hcd, false); + diff --git a/target/linux/apm821xx/patches-5.4/802-usb-xhci-force-msi-renesas-xhci.patch b/target/linux/apm821xx/patches-5.4/802-usb-xhci-force-msi-renesas-xhci.patch new file mode 100644 index 0000000000..55686a2fd8 --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/802-usb-xhci-force-msi-renesas-xhci.patch @@ -0,0 +1,53 @@ +From a0dc613140bab907a3d5787a7ae7b0638bf674d0 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Thu, 23 Jun 2016 20:28:20 +0200 +Subject: [PATCH] usb: xhci: force MSI for uPD720201 and + uPD720202 + +The APM82181 does not support MSI-X. When probed, it will +produce a noisy warning. + +--- + drivers/usb/host/pci-quirks.c | 362 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 362 insertions(+) + +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -275,6 +275,7 @@ static void xhci_pci_quirks(struct devic + pdev->device == 0x0015) { + xhci->quirks |= XHCI_RESET_ON_RESUME; + xhci->quirks |= XHCI_ZERO_64B_REGS; ++ xhci->quirks |= XHCI_FORCE_MSI; + } + if (pdev->vendor == PCI_VENDOR_ID_VIA) + xhci->quirks |= XHCI_RESET_ON_RESUME; +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -423,10 +423,14 @@ static int xhci_try_enable_msi(struct us + free_irq(hcd->irq, hcd); + hcd->irq = 0; + +- ret = xhci_setup_msix(xhci); +- if (ret) +- /* fall back to msi*/ ++ if (xhci->quirks & XHCI_FORCE_MSI) { + ret = xhci_setup_msi(xhci); ++ } else { ++ ret = xhci_setup_msix(xhci); ++ if (ret) ++ /* fall back to msi*/ ++ ret = xhci_setup_msi(xhci); ++ } + + if (!ret) { + hcd->msi_enabled = 1; +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1879,6 +1879,7 @@ struct xhci_hcd { + struct xhci_hub usb2_rhub; + struct xhci_hub usb3_rhub; + /* support xHCI 1.0 spec USB2 hardware LPM */ ++#define XHCI_FORCE_MSI (1 << 24) + unsigned hw_lpm_support:1; + /* Broken Suspend flag for SNPS Suspend resume issue */ + unsigned broken_suspend:1; diff --git a/target/linux/apm821xx/patches-5.4/803-hwmon-tc654-add-detection-routine.patch b/target/linux/apm821xx/patches-5.4/803-hwmon-tc654-add-detection-routine.patch new file mode 100644 index 0000000000..f0ed5a7cff --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/803-hwmon-tc654-add-detection-routine.patch @@ -0,0 +1,65 @@ +From 694f9bfb8efaef8a33e8992015ff9d0866faf4a2 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Sun, 17 Dec 2017 17:27:15 +0100 +Subject: [PATCH 1/2] hwmon: tc654 add detection routine + +This patch adds a detection routine for the TC654/TC655 +chips. Both IDs are listed in the Datasheet. + +Signed-off-by: Christian Lamparter +--- + drivers/hwmon/tc654.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/drivers/hwmon/tc654.c ++++ b/drivers/hwmon/tc654.c +@@ -55,6 +55,11 @@ enum tc654_regs { + /* Register data is read (and cached) at most once per second. */ + #define TC654_UPDATE_INTERVAL HZ + ++/* Manufacturer and Version Identification Register Values */ ++#define TC654_MFR_ID_MICROCHIP 0x84 ++#define TC654_VER_ID 0x00 ++#define TC655_VER_ID 0x01 ++ + struct tc654_data { + struct i2c_client *client; + +@@ -482,6 +487,29 @@ static const struct i2c_device_id tc654_ + {} + }; + ++static int ++tc654_detect(struct i2c_client *new_client, struct i2c_board_info *info) ++{ ++ struct i2c_adapter *adapter = new_client->adapter; ++ int manufacturer, product; ++ ++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) ++ return -ENODEV; ++ ++ manufacturer = i2c_smbus_read_byte_data(new_client, TC654_REG_MFR_ID); ++ if (manufacturer != TC654_MFR_ID_MICROCHIP) ++ return -ENODEV; ++ ++ product = i2c_smbus_read_byte_data(new_client, TC654_REG_VER_ID); ++ if (!((product == TC654_VER_ID) || (product == TC655_VER_ID))) ++ return -ENODEV; ++ ++ strlcpy(info->type, product == TC654_VER_ID ? "tc654" : "tc655", ++ I2C_NAME_SIZE); ++ return 0; ++} ++ ++ + MODULE_DEVICE_TABLE(i2c, tc654_id); + + static struct i2c_driver tc654_driver = { +@@ -490,6 +518,7 @@ static struct i2c_driver tc654_driver = + }, + .probe = tc654_probe, + .id_table = tc654_id, ++ .detect = tc654_detect, + }; + + module_i2c_driver(tc654_driver); diff --git a/target/linux/apm821xx/patches-5.4/804-hwmon-tc654-add-thermal_cooling-device.patch b/target/linux/apm821xx/patches-5.4/804-hwmon-tc654-add-thermal_cooling-device.patch new file mode 100644 index 0000000000..a7b0a58f7c --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/804-hwmon-tc654-add-thermal_cooling-device.patch @@ -0,0 +1,174 @@ +From 9cb27801b5cbad2e1aaf45aac428cb2fac5e1372 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Sun, 17 Dec 2017 17:29:13 +0100 +Subject: [PATCH] hwmon: tc654: add thermal_cooling device + +This patch adds a thermaL_cooling device to the tc654 driver. +This allows the chip to be used for DT-based cooling. + +Signed-off-by: Christian Lamparter +--- + drivers/hwmon/tc654.c | 103 +++++++++++++++++++++++++++++++++++------- + 1 file changed, 86 insertions(+), 17 deletions(-) + +--- a/drivers/hwmon/tc654.c ++++ b/drivers/hwmon/tc654.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + + enum tc654_regs { +@@ -132,6 +133,9 @@ struct tc654_data { + * writable register used to control the duty + * cycle of the V OUT output. + */ ++ ++ /* optional cooling device */ ++ struct thermal_cooling_device *cdev; + }; + + /* helper to grab and cache data, at most one time per second */ +@@ -367,36 +371,30 @@ static ssize_t pwm_mode_store(struct dev + static const int tc654_pwm_map[16] = { 77, 88, 102, 112, 124, 136, 148, 160, + 172, 184, 196, 207, 219, 231, 243, 255}; + ++static int get_pwm(struct tc654_data *data) ++{ ++ if (data->config & TC654_REG_CONFIG_SDM) ++ return 0; ++ else ++ return tc654_pwm_map[data->duty_cycle]; ++} ++ + static ssize_t pwm_show(struct device *dev, struct device_attribute *da, + char *buf) + { + struct tc654_data *data = tc654_update_client(dev); +- int pwm; + + if (IS_ERR(data)) + return PTR_ERR(data); + +- if (data->config & TC654_REG_CONFIG_SDM) +- pwm = 0; +- else +- pwm = tc654_pwm_map[data->duty_cycle]; +- +- return sprintf(buf, "%d\n", pwm); ++ return sprintf(buf, "%d\n", get_pwm(data)); + } + +-static ssize_t pwm_store(struct device *dev, struct device_attribute *da, +- const char *buf, size_t count) ++static int _set_pwm(struct tc654_data *data, unsigned long val) + { +- struct tc654_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; +- unsigned long val; + int ret; + +- if (kstrtoul(buf, 10, &val)) +- return -EINVAL; +- if (val > 255) +- return -EINVAL; +- + mutex_lock(&data->update_lock); + + if (val == 0) +@@ -416,6 +414,22 @@ static ssize_t pwm_store(struct device * + + out: + mutex_unlock(&data->update_lock); ++ return ret; ++} ++ ++static ssize_t pwm_store(struct device *dev, struct device_attribute *da, ++ const char *buf, size_t count) ++{ ++ struct tc654_data *data = dev_get_drvdata(dev); ++ unsigned long val; ++ int ret; ++ ++ if (kstrtoul(buf, 10, &val)) ++ return -EINVAL; ++ if (val > 255) ++ return -EINVAL; ++ ++ ret = _set_pwm(data, val); + return ret < 0 ? ret : count; + } + +@@ -447,6 +461,47 @@ static struct attribute *tc654_attrs[] = + + ATTRIBUTE_GROUPS(tc654); + ++/* cooling device */ ++ ++static int tc654_get_max_state(struct thermal_cooling_device *cdev, ++ unsigned long *state) ++{ ++ *state = 255; ++ return 0; ++} ++ ++static int tc654_get_cur_state(struct thermal_cooling_device *cdev, ++ unsigned long *state) ++{ ++ struct tc654_data *data = tc654_update_client(cdev->devdata); ++ ++ if (IS_ERR(data)) ++ return PTR_ERR(data); ++ ++ *state = get_pwm(data); ++ return 0; ++} ++ ++static int tc654_set_cur_state(struct thermal_cooling_device *cdev, ++ unsigned long state) ++{ ++ struct tc654_data *data = tc654_update_client(cdev->devdata); ++ ++ if (IS_ERR(data)) ++ return PTR_ERR(data); ++ ++ if (state > 255) ++ return -EINVAL; ++ ++ return _set_pwm(data, state); ++} ++ ++static const struct thermal_cooling_device_ops tc654_fan_cool_ops = { ++ .get_max_state = tc654_get_max_state, ++ .get_cur_state = tc654_get_cur_state, ++ .set_cur_state = tc654_set_cur_state, ++}; ++ + /* + * device probe and removal + */ +@@ -478,7 +533,21 @@ static int tc654_probe(struct i2c_client + hwmon_dev = + devm_hwmon_device_register_with_groups(dev, client->name, data, + tc654_groups); +- return PTR_ERR_OR_ZERO(hwmon_dev); ++ if (IS_ERR(hwmon_dev)) ++ return PTR_ERR(hwmon_dev); ++ ++#if IS_ENABLED(CONFIG_OF) ++ /* Optional cooling device register for Device tree platforms */ ++ data->cdev = thermal_of_cooling_device_register(client->dev.of_node, ++ "tc654", hwmon_dev, ++ &tc654_fan_cool_ops); ++#else /* CONFIG_OF */ ++ /* Optional cooling device register for non Device tree platforms */ ++ data->cdev = thermal_cooling_device_register("tc654", hwmon_dev, ++ &tc654_fan_cool_ops); ++#endif /* CONFIG_OF */ ++ ++ return PTR_ERR_OR_ZERO(data->cdev); + } + + static const struct i2c_device_id tc654_id[] = { diff --git a/target/linux/apm821xx/patches-5.4/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch b/target/linux/apm821xx/patches-5.4/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch new file mode 100644 index 0000000000..c2cc632693 --- /dev/null +++ b/target/linux/apm821xx/patches-5.4/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch @@ -0,0 +1,29 @@ +From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Sun, 1 Dec 2019 02:08:23 +0100 +Subject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression + method + +Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to +instruct the mkimage to use the xz compression, which isn't +supported. This patch forces the gzip compression, which is +supported and doesn't matter because the generated uImage for +the apm821xx target gets ignored as the OpenWrt toolchain will +do separate U-Boot kernel images for each device individually. + +Signed-off-by: Christian Lamparter +--- + arch/powerpc/boot/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -254,7 +254,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo + + # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd + quiet_cmd_wrap = WRAP $@ +- cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \ ++ cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \ + $(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \ + vmlinux + diff --git a/target/linux/apm821xx/sata/target.mk b/target/linux/apm821xx/sata/target.mk index 790746c480..d3af6ef821 100644 --- a/target/linux/apm821xx/sata/target.mk +++ b/target/linux/apm821xx/sata/target.mk @@ -1,6 +1,6 @@ BOARDNAME := Devices which boot from SATA (NAS) FEATURES += ext4 usb ramdisk squashfs rootfs-part boot-part -DEFAULT_PACKAGES += badblocks block-mount e2fsprogs \ +DEFAULT_PACKAGES += badblocks block-mount e2fsprogs kmod-hwmon-drivetemp \ kmod-dm kmod-md-mod partx-utils mkf2fs f2fsck define Target/Description diff --git a/target/linux/archs38/Makefile b/target/linux/archs38/Makefile index be6be0472b..47791119e2 100644 --- a/target/linux/archs38/Makefile +++ b/target/linux/archs38/Makefile @@ -14,6 +14,7 @@ MAINTAINER:=Alexey Brodkin SUBTARGETS:=generic KERNEL_PATCHVER:=4.14 +KERNEL_TESTING_PATCHVER:=5.4 DEVICE_TYPE:=developerboard diff --git a/target/linux/archs38/config-5.4 b/target/linux/archs38/config-5.4 new file mode 100644 index 0000000000..ab03472cd7 --- /dev/null +++ b/target/linux/archs38/config-5.4 @@ -0,0 +1,285 @@ +# CONFIG_16KSTACKS is not set +CONFIG_ARC=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARC_BUILTIN_DTB_NAME="" +CONFIG_ARC_CACHE=y +CONFIG_ARC_CACHE_LINE_SHIFT=6 +CONFIG_ARC_CACHE_PAGES=y +CONFIG_ARC_CPU_HS=y +CONFIG_ARC_CURR_IN_REG=y +CONFIG_ARC_DBG=y +# CONFIG_ARC_DBG_TLB_PARANOIA is not set +CONFIG_ARC_DW2_UNWIND=y +CONFIG_ARC_HAS_ACCL_REGS=y +CONFIG_ARC_HAS_DCACHE=y +# CONFIG_ARC_HAS_DCCM is not set +CONFIG_ARC_HAS_DIV_REM=y +CONFIG_ARC_HAS_ICACHE=y +# CONFIG_ARC_HAS_ICCM is not set +CONFIG_ARC_HAS_LL64=y +CONFIG_ARC_HAS_LLSC=y +# CONFIG_ARC_HAS_PAE40 is not set +CONFIG_ARC_HAS_SWAPE=y +CONFIG_ARC_IRQ_NO_AUTOSAVE=y +CONFIG_ARC_KVADDR_SIZE=256 +CONFIG_ARC_MCIP=y +# CONFIG_ARC_METAWARE_HLINK is not set +CONFIG_ARC_MMU_V4=y +# CONFIG_ARC_PAGE_SIZE_16K is not set +# CONFIG_ARC_PAGE_SIZE_4K is not set +CONFIG_ARC_PAGE_SIZE_8K=y +CONFIG_ARC_PLAT_AXS10X=y +# CONFIG_ARC_PLAT_EZNPS is not set +# CONFIG_ARC_PLAT_TB10X is not set +# CONFIG_ARC_SMP_HALT_ON_RESET is not set +CONFIG_ARC_SOC_HSDK=y +CONFIG_ARC_TIMERS=y +CONFIG_ARC_TIMERS_64BIT=y +CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y +CONFIG_AXS103=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_SCSI_REQUEST=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y +CONFIG_CC_HAS_KASAN_GENERIC=y +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLK_HSDK=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_DEVTMPFS=y +CONFIG_DMADEVICES=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DWMAC_ANARION=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DW_APB_ICTL=y +CONFIG_DW_AXI_DMAC=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EZNPS_GIC is not set +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_CMDLINE=y +CONFIG_FIXED_PHY=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_SNPS_CREG=y +CONFIG_GPIO_SYSFS=y +CONFIG_GRACE_PERIOD=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_ST_PRESS=y +CONFIG_IIO_ST_PRESS_I2C=y +CONFIG_IIO_ST_PRESS_SPI=y +CONFIG_IIO_ST_SENSORS_CORE=y +CONFIG_IIO_ST_SENSORS_I2C=y +CONFIG_IIO_ST_SENSORS_SPI=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_WORK=y +# CONFIG_ISA_ARCOMPACT is not set +CONFIG_ISA_ARCV2=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KERNEL_GZIP=y +CONFIG_LIBFDT=y +CONFIG_LINUX_LINK_BASE=0x90000000 +CONFIG_LINUX_RAM_BASE=0x80000000 +CONFIG_LOCKD=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_NS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PERF_EVENTS=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_PTP_1588_CLOCK=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_RESET_AXS10X=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_HSDK=y +CONFIG_RESET_SIMPLE=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_ARC=y +CONFIG_SERIAL_ARC_CONSOLE=y +CONFIG_SERIAL_ARC_NR_PORTS=1 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SPI=y +CONFIG_SPI_DESIGNWARE=y +CONFIG_SPI_DW_MMIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +# CONFIG_STANDALONE is not set +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_SUNRPC=y +CONFIG_SWPHY=y +CONFIG_TASKS_RCU=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TI_ADC108S102=y +CONFIG_TREE_SRCU=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_USB_SUPPORT=y +# CONFIG_USER_NS is not set +CONFIG_VFAT_FS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y diff --git a/target/linux/archs38/image/gen_axs10x_sdcard_img.sh b/target/linux/archs38/image/gen_axs10x_sdcard_img.sh index 9a6f93d0d9..87c2bba92c 100755 --- a/target/linux/archs38/image/gen_axs10x_sdcard_img.sh +++ b/target/linux/archs38/image/gen_axs10x_sdcard_img.sh @@ -1,4 +1,4 @@ -#!/usr/bin/env bash +#!/bin/sh # # Copyright (C) 2016 OpenWrt.org @@ -22,7 +22,7 @@ ROOTFSSIZE="$5" head=4 sect=63 -set `ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M` +set $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M) BOOTOFFSET="$(($1 / 512))" BOOTSIZE="$(($2 / 512))" diff --git a/target/linux/archs38/patches-5.4/0001-arch-arc-Add-compiler-option-for-gcc8.4.patch b/target/linux/archs38/patches-5.4/0001-arch-arc-Add-compiler-option-for-gcc8.4.patch new file mode 100644 index 0000000000..4489a5169c --- /dev/null +++ b/target/linux/archs38/patches-5.4/0001-arch-arc-Add-compiler-option-for-gcc8.4.patch @@ -0,0 +1,21 @@ +From 2e2b3aeda9af9c029bf347c974911fe96cd79c43 Mon Sep 17 00:00:00 2001 +From: Evgeniy Didin +Date: Mon, 23 Mar 2020 15:57:18 +0300 +Subject: [PATCH] arch/arc: Add compiler option for gcc8.4 + +Signed-off-by: Evgeniy Didin +--- + arch/arc/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arc/Makefile ++++ b/arch/arc/Makefile +@@ -11,7 +11,7 @@ endif + + cflags-y += -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__ + cflags-$(CONFIG_ISA_ARCOMPACT) += -mA7 +-cflags-$(CONFIG_ISA_ARCV2) += -mcpu=hs38 ++cflags-$(CONFIG_ISA_ARCV2) += -mcpu=hs38 -mmpy-option=2 + + ifdef CONFIG_ARC_CURR_IN_REG + # For a global register defintion, make sure it gets passed to every file diff --git a/target/linux/armvirt/32/config-default b/target/linux/armvirt/32/config-4.19 similarity index 81% rename from target/linux/armvirt/32/config-default rename to target/linux/armvirt/32/config-4.19 index a3530b0e77..735839cc40 100644 --- a/target/linux/armvirt/32/config-default +++ b/target/linux/armvirt/32/config-4.19 @@ -1,25 +1,27 @@ CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ARCH_AXXIA is not set +CONFIG_ARCH_HAS_PHYS_TO_DMA=y CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set CONFIG_ARCH_MULTI_V6_V7=y CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_NR_GPIO=0 -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_ARCH_VIRT=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_ARM=y CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_HAS_SG_CHAIN=y CONFIG_ARM_HEAVY_MB=y CONFIG_ARM_L1_CACHE_SHIFT=6 CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_LPAE is not set +CONFIG_ARM_LPAE=y CONFIG_ARM_PATCH_IDIV=y CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_ARM_PSCI=y @@ -27,7 +29,6 @@ CONFIG_ARM_THUMB=y # CONFIG_ARM_THUMBEE is not set CONFIG_ARM_VIRT_EXT=y CONFIG_AUTO_ZRELADDR=y -# CONFIG_BINFMT_FLAT is not set CONFIG_CACHE_L2X0=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y @@ -41,35 +42,35 @@ CONFIG_CPU_CP15_MMU=y CONFIG_CPU_HAS_ASID=y # CONFIG_CPU_ICACHE_DISABLE is not set CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y CONFIG_CPU_TLB_V7=y CONFIG_CPU_V7=y -CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_UART_8250 is not set # CONFIG_DEBUG_USER is not set CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_CBPF_JIT=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_IDE=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_PROC_CPU=y CONFIG_HAVE_SMP=y +# CONFIG_HUGETLBFS is not set CONFIG_HZ_FIXED=0 CONFIG_HZ_PERIODIC=y CONFIG_MIGHT_HAVE_CACHE_L2X0=y CONFIG_MIGHT_HAVE_PCI=y CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MULTI_IRQ_HANDLER=y CONFIG_NEON=y +CONFIG_NR_CPUS=4 CONFIG_OLD_SIGACTION=y CONFIG_OUTER_CACHE=y CONFIG_OUTER_CACHE_SYNC=y CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PCI_V3_SEMI is not set CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 # CONFIG_PL310_ERRATA_588369 is not set # CONFIG_PL310_ERRATA_727915 is not set # CONFIG_PL310_ERRATA_753970 is not set @@ -82,7 +83,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y # CONFIG_THUMB2_KERNEL is not set CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" CONFIG_USE_OF=y -CONFIG_VECTORS_BASE=0xffff0000 CONFIG_VFP=y CONFIG_VFPv3=y CONFIG_XZ_DEC_ARM=y diff --git a/target/linux/armvirt/32/config-5.4 b/target/linux/armvirt/32/config-5.4 new file mode 100644 index 0000000000..33f02e8bb3 --- /dev/null +++ b/target/linux/armvirt/32/config-5.4 @@ -0,0 +1,95 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +# CONFIG_ARCH_AXXIA is not set +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_VIRT=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_LPAE=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_CACHE_L2X0=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_USER is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_SMP=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_NEON=y +CONFIG_NR_CPUS=4 +CONFIG_OLD_SIGACTION=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SMP_ON_UP=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/armvirt/64/config-default b/target/linux/armvirt/64/config-4.19 similarity index 54% rename from target/linux/armvirt/64/config-default rename to target/linux/armvirt/64/config-4.19 index a38a9162b6..8bcef5bed6 100644 --- a/target/linux/armvirt/64/config-default +++ b/target/linux/armvirt/64/config-4.19 @@ -1,21 +1,49 @@ CONFIG_64BIT=y -# CONFIG_ACPI is not set -CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=24 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y CONFIG_ARCH_WANT_FRAME_POINTERS=y @@ -32,66 +60,75 @@ CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y CONFIG_ARM64_ERRATUM_832075=y CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_HW_AFDBM=y # CONFIG_ARM64_LSE_ATOMICS is not set -CONFIG_ARM64_MODULE_CMODEL_LARGE=y +CONFIG_ARM64_MODULE_PLTS=y CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y # CONFIG_ARM64_PMEM is not set -# CONFIG_ARM64_PTDUMP is not set # CONFIG_ARM64_PTDUMP_DEBUGFS is not set # CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set CONFIG_ARM64_SSBD=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_SVE=y CONFIG_ARM64_UAO=y CONFIG_ARM64_VA_BITS=39 CONFIG_ARM64_VA_BITS_39=y # CONFIG_ARM64_VA_BITS_48 is not set CONFIG_ARM64_VHE=y -# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_PMU=y -# CONFIG_ARM_SBSA_WATCHDOG is not set +CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ATOMIC64_SELFTEST=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BOUNCE=y CONFIG_CLKSRC_MMIO=y CONFIG_CLKSRC_VERSATILE=y CONFIG_CLK_SP810=y CONFIG_CLK_VEXPRESS_OSC=y CONFIG_COMMON_CLK_VERSATILE=y -# CONFIG_COMMON_CLK_XGENE is not set -CONFIG_COMPAT=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_IDLE=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_PM=y -CONFIG_CRYPTO_ABLK_HELPER=y +CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_BS=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CRC32_ARM64=y CONFIG_CRYPTO_CRC32_ARM64_CE=y CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set +CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA256_ARM64=y CONFIG_CRYPTO_SHA2_ARM64_CE=y +# CONFIG_CRYPTO_SHA3_ARM64 is not set CONFIG_CRYPTO_SHA512_ARM64=y -# CONFIG_DEBUG_ALIGN_RODATA is not set -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_RODATA=y +# CONFIG_CRYPTO_SHA512_ARM64_CE is not set +CONFIG_CRYPTO_SIMD=y +# CONFIG_CRYPTO_SM3_ARM64_CE is not set +# CONFIG_CRYPTO_SM4_ARM64_CE is not set +CONFIG_DMA_DIRECT_OPS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DRM=y +CONFIG_DRM_BOCHS=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_SIMPLE is not set +CONFIG_DRM_QXL=y +CONFIG_DRM_TTM=y +CONFIG_DRM_VIRTIO_GPU=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FB_CFB_COPYAREA=y @@ -99,44 +136,59 @@ CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_CMDLINE=y CONFIG_FB_MODE_HELPERS=y +# CONFIG_FLATMEM_MANUAL is not set CONFIG_FSL_ERRATUM_A008585=y -# CONFIG_FSL_MC_BUS is not set CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_HAVE_GENERIC_RCU_GUP=y CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_HAVE_PATA_PLATFORM=y -CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HDMI=y +CONFIG_HOLES_IN_ZONE=y # CONFIG_HUGETLBFS is not set CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_CAVIUM is not set CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INLINE_READ_LOCK=y +CONFIG_INLINE_READ_LOCK_BH=y +CONFIG_INLINE_READ_LOCK_IRQ=y +CONFIG_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_INLINE_READ_UNLOCK_BH=y +CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_SPIN_LOCK=y +CONFIG_INLINE_SPIN_LOCK_BH=y +CONFIG_INLINE_SPIN_LOCK_IRQ=y +CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_INLINE_SPIN_TRYLOCK=y +CONFIG_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_WRITE_LOCK=y +CONFIG_INLINE_WRITE_LOCK_BH=y +CONFIG_INLINE_WRITE_LOCK_IRQ=y +CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_INLINE_WRITE_UNLOCK_BH=y +CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_PLATFORM is not set -# CONFIG_LIQUIDIO is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y CONFIG_MFD_CORE=y CONFIG_MFD_SYSCON=y CONFIG_MFD_VEXPRESS_SYSREG=y CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y -# CONFIG_MMC_CAVIUM_THUNDERX is not set # CONFIG_MMC_TIFM_SD is not set CONFIG_MODULES_USE_ELF_RELA=y # CONFIG_MTD_PHYSMAP_OF is not set @@ -146,15 +198,6 @@ CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y CONFIG_NR_CPUS=64 # CONFIG_NUMA is not set -# CONFIG_PCIE_KIRIN is not set -CONFIG_PCI_BUS_ADDR_T_64BIT=y -# CONFIG_PCI_HISI is not set -# CONFIG_PCI_HOST_THUNDER_ECAM is not set -# CONFIG_PCI_HOST_THUNDER_PEM is not set -# CONFIG_PCI_XGENE is not set -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_XGENE is not set CONFIG_PM=y CONFIG_PM_CLK=y # CONFIG_PM_DEBUG is not set @@ -163,24 +206,25 @@ CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_SUPPLY=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y # CONFIG_RANDOMIZE_BASE is not set CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y CONFIG_REGMAP_MMIO=y +CONFIG_RTC_I2C_AND_SPI=y CONFIG_SMC91X=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SYNC_FILE=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_RGX is not set -# CONFIG_THUNDER_NIC_VF is not set +CONFIG_THREAD_INFO_IN_TASK=y CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_VEXPRESS_CONFIG=y CONFIG_VEXPRESS_SYSCFG=y CONFIG_VIDEOMODE_HELPERS=y CONFIG_VMAP_STACK=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/armvirt/64/config-5.4 b/target/linux/armvirt/64/config-5.4 new file mode 100644 index 0000000000..c69ad8943f --- /dev/null +++ b/target/linux/armvirt/64/config-5.4 @@ -0,0 +1,261 @@ +CONFIG_64BIT=y +# CONFIG_ARCH_AGILEX is not set +# CONFIG_ARCH_BITMAIN is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARM64=y +# CONFIG_ARM64_16K_PAGES is not set +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_CNP=y +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARM64_CRYPTO=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_MODULE_PLTS=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +# CONFIG_ARM64_PMEM is not set +# CONFIG_ARM64_PSEUDO_NMI is not set +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set +CONFIG_ARM64_PTR_AUTH=y +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +CONFIG_ARM64_SSBD=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_UAO=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VHE=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BLK_PM=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_VERSATILE=y +CONFIG_CLK_SP810=y +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_COMMON_CLK_VERSATILE=y +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PM=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_CHACHA20=y +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +# CONFIG_CRYPTO_SHA3_ARM64 is not set +CONFIG_CRYPTO_SHA512_ARM64=y +# CONFIG_CRYPTO_SHA512_ARM64_CE is not set +CONFIG_CRYPTO_SIMD=y +# CONFIG_CRYPTO_SM3_ARM64_CE is not set +# CONFIG_CRYPTO_SM4_ARM64_CE is not set +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DRM=y +CONFIG_DRM_BOCHS=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_SIMPLE is not set +CONFIG_DRM_QXL=y +CONFIG_DRM_RCAR_WRITEBACK=y +CONFIG_DRM_TTM=y +CONFIG_DRM_VIRTIO_GPU=y +CONFIG_DRM_VRAM_HELPER=y +CONFIG_EFI_EARLYCON=y +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_HDMI=y +CONFIG_HOLES_IN_ZONE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INLINE_READ_LOCK=y +CONFIG_INLINE_READ_LOCK_BH=y +CONFIG_INLINE_READ_LOCK_IRQ=y +CONFIG_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_INLINE_READ_UNLOCK_BH=y +CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_SPIN_LOCK=y +CONFIG_INLINE_SPIN_LOCK_BH=y +CONFIG_INLINE_SPIN_LOCK_IRQ=y +CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_INLINE_SPIN_TRYLOCK=y +CONFIG_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_WRITE_LOCK=y +CONFIG_INLINE_WRITE_LOCK_BH=y +CONFIG_INLINE_WRITE_LOCK_IRQ=y +CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_INLINE_WRITE_UNLOCK_BH=y +CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y +# CONFIG_IONIC is not set +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_PLATFORM is not set +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_VEXPRESS_SYSREG=y +CONFIG_MMC=y +CONFIG_MMC_ARMMMCI=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=64 +# CONFIG_NUMA is not set +# CONFIG_OCTEONTX2_AF is not set +# CONFIG_PCIE_AL is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_SUPPLY=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +# CONFIG_RANDOMIZE_BASE is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_SMC91X=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_VEXPRESS_SYSCFG=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VMAP_STACK=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/armvirt/Makefile b/target/linux/armvirt/Makefile index 107f8607c3..2d1815a12b 100644 --- a/target/linux/armvirt/Makefile +++ b/target/linux/armvirt/Makefile @@ -13,8 +13,11 @@ FEATURES+=cpiogz ext4 ramdisk squashfs targz MAINTAINER:=Florian Fainelli , \ Yousong Zhou -KERNEL_PATCHVER:=4.14 +KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += mkf2fs e2fsprogs + $(eval $(call BuildTarget)) diff --git a/target/linux/armvirt/config-4.19 b/target/linux/armvirt/config-4.19 new file mode 100644 index 0000000000..2ef1786af5 --- /dev/null +++ b/target/linux/armvirt/config-4.19 @@ -0,0 +1,222 @@ +CONFIG_9P_FS=y +# CONFIG_9P_FS_POSIX_ACL is not set +# CONFIG_9P_FS_SECURITY is not set +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_BALLOON_COMPACTION=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXT4_FS=y +# CONFIG_F2FS_CHECK_FS is not set +CONFIG_F2FS_FS=y +# CONFIG_F2FS_FS_SECURITY is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_STAT_FS=y +CONFIG_FAILOVER=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_PL061=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_GUP=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HVC_DRIVER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMFD_CREATE=y +CONFIG_MIGRATION=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NO_BOOTMEM=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_RATIONAL=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_REFCOUNT_FULL=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +# CONFIG_SCHED_INFO is not set +CONFIG_SCSI=y +CONFIG_SCSI_VIRTIO=y +CONFIG_SERIAL_8250_FSL=y +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SPARSE_IRQ=y +CONFIG_SRCU=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USB_SUPPORT=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_MMIO=y +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_XPS=y diff --git a/target/linux/armvirt/config-5.4 b/target/linux/armvirt/config-5.4 new file mode 100644 index 0000000000..5d62dcd276 --- /dev/null +++ b/target/linux/armvirt/config-5.4 @@ -0,0 +1,240 @@ +CONFIG_9P_FS=y +# CONFIG_9P_FS_POSIX_ACL is not set +# CONFIG_9P_FS_SECURITY is not set +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_BALLOON_COMPACTION=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXT4_FS=y +# CONFIG_F2FS_CHECK_FS is not set +CONFIG_F2FS_FS=y +# CONFIG_F2FS_FS_SECURITY is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_STAT_FS=y +CONFIG_FAILOVER=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_PL061=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_GUP=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HOTPLUG_CPU=y +# CONFIG_HUGETLBFS is not set +CONFIG_HVC_DRIVER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY_BALLOON=y +CONFIG_MIGRATION=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REFCOUNT_FULL=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +# CONFIG_SCHED_INFO is not set +CONFIG_SCSI=y +CONFIG_SCSI_VIRTIO=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SPARSE_IRQ=y +CONFIG_SRCU=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USB_SUPPORT=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_MMIO=y +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y diff --git a/target/linux/armvirt/image/Makefile b/target/linux/armvirt/image/Makefile index 73d9145e0e..0292dbab42 100644 --- a/target/linux/armvirt/image/Makefile +++ b/target/linux/armvirt/image/Makefile @@ -19,10 +19,16 @@ define Image/Build/Initramfs ) endef +define Image/Build/gzip + gzip -f9n $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img +endef + +$(eval $(call Image/gzip-ext4-padded-squashfs)) + define Image/Build $(call Image/Build/$(1)) - dd if=$(KDIR)/root.$(1) bs=128k conv=sync | \ - gzip -9n >$(BIN_DIR)/$(IMG_PREFIX)-root.$(1).gz + $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img + $(call Image/Build/gzip/$(1)) endef $(eval $(call BuildImage)) diff --git a/target/linux/gemini/Makefile b/target/linux/gemini/Makefile index 1efa2ae10f..cab67cf76d 100644 --- a/target/linux/gemini/Makefile +++ b/target/linux/gemini/Makefile @@ -14,6 +14,7 @@ CPU_TYPE:=fa526 MAINTAINER:=Roman Yeryomin KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 define Target/Description Build firmware images for the StorLink/Cortina Gemini CS351x ARM FA526 CPU diff --git a/target/linux/gemini/config-4.19 b/target/linux/gemini/config-4.19 index ac295f0857..b23e6a56d4 100644 --- a/target/linux/gemini/config-4.19 +++ b/target/linux/gemini/config-4.19 @@ -431,7 +431,6 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIO=y CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_SERPORT=y -# CONFIG_SFP is not set CONFIG_SG_POOL=y CONFIG_SLUB_DEBUG=y CONFIG_SPARSE_IRQ=y diff --git a/target/linux/gemini/config-5.4 b/target/linux/gemini/config-5.4 new file mode 100644 index 0000000000..7cfdb3ccdb --- /dev/null +++ b/target/linux/gemini/config-5.4 @@ -0,0 +1,466 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_AMBA_PL08X=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_GEMINI=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_ARCH_MOXART is not set +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V4=y +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +# CONFIG_ARCH_MULTI_V5 is not set +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_UNWIND=y +CONFIG_ATA=y +CONFIG_ATAGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BOUNCE=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_GEMINI=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_32v4=y +CONFIG_CPU_ABRT_EV4=y +CONFIG_CPU_CACHE_FA=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FA=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_CPU_FA526=y +CONFIG_CPU_NO_EFFICIENT_FFS=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_TLB_FA=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRASH_CORE=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DRM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ILITEK_IL9322=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_TVE200=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_93CX6=y +CONFIG_ELF_CORE=y +# CONFIG_EMBEDDED is not set +# CONFIG_EXPERT is not set +CONFIG_EXT4_FS=y +CONFIG_FARADAY_FTINTC010=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FPE_FASTFPE is not set +# CONFIG_FPE_NWFPE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FTTMR010_TIMER=y +CONFIG_FTWDT010_WATCHDOG=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_GEMINI_ETHERNET=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GENERIC=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HDMI=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_KEYBOARD=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IOSCHED_CFQ=y +CONFIG_IPC_NS=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KERNEL_LZMA=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEYBOARD_DLINK_DIR685=y +# CONFIG_LDM_DEBUG is not set +CONFIG_LDM_PARTITION=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MANDATORY_FILE_LOCKING=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_GPIO=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_GEMINI=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_WRGG_FW=y +CONFIG_NAMESPACES=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_REALTEK_SMI=y +CONFIG_NET_DSA_VITESSE_VSC73XX=y +CONFIG_NET_NS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NVMEM=y +CONFIG_OABI_COMPAT=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PATA_FTIDE010=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_FTPCI100=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PID_NS=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_GEMINI=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GEMINI_POWEROFF=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_RATIONAL=y +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_REALTEK_PHY=y +CONFIG_REFCOUNT_FULL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RELAY=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RSEQ=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_FTRTC010=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_NVMEM=y +CONFIG_SATA_GEMINI=y +CONFIG_SATA_PMP=y +CONFIG_SCSI=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +CONFIG_SENSORS_DRIVETEMP=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_LM75=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SLUB_DEBUG=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRCU=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SWPHY=y +CONFIG_SYNC_FILE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TASKS_RCU=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TREE_SRCU=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNWINDER_ARM=y +CONFIG_USB_SUPPORT=y +# CONFIG_USERIO is not set +CONFIG_USER_NS=y +CONFIG_USE_OF=y +CONFIG_UTS_NS=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VITESSE_PHY=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/gemini/image/Makefile b/target/linux/gemini/image/Makefile index b4daa92670..80a698927c 100644 --- a/target/linux/gemini/image/Makefile +++ b/target/linux/gemini/image/Makefile @@ -135,12 +135,13 @@ endef # A reasonable set of default packages handling the NAS type # of devices out of the box (former NAS42x0 IcyBox defaults) -GEMINI_NAS_PACKAGES:=kmod-md-mod kmod-md-linear kmod-md-multipath \ +GEMINI_NAS_PACKAGES := $(DEFAULT_PACKAGES.nas) \ + kmod-md-mod kmod-md-linear kmod-md-multipath \ kmod-md-raid0 kmod-md-raid1 kmod-md-raid10 kmod-md-raid456 \ kmod-fs-btrfs kmod-fs-cifs kmod-fs-nfs \ kmod-fs-nfsd kmod-fs-ntfs kmod-fs-reiserfs kmod-fs-vfat \ - kmod-nls-utf8 kmod-usb-storage-extras \ - samba36-server mdadm cfdisk fdisk e2fsprogs badblocks \ + kmod-nls-utf8 kmod-usb-storage-extras kmod-hwmon-drivetemp \ + samba36-server cfdisk e2fsprogs badblocks \ partx-utils # The DIR-685 flash layout is kernel in WRGG format, padded and followed diff --git a/target/linux/gemini/image/dns313_gen_hdd_img.sh b/target/linux/gemini/image/dns313_gen_hdd_img.sh index 6e899ec840..813852232f 100755 --- a/target/linux/gemini/image/dns313_gen_hdd_img.sh +++ b/target/linux/gemini/image/dns313_gen_hdd_img.sh @@ -1,4 +1,4 @@ -#!/usr/bin/env bash +#!/bin/sh set -x [ $# -eq 5 ] || { diff --git a/target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch b/target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch new file mode 100644 index 0000000000..4a6a804ca4 --- /dev/null +++ b/target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch @@ -0,0 +1,131 @@ +From 3aaff88a0f5e154aa5a489d59fd4015a2a937c23 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Fri, 21 Apr 2017 22:19:00 +0200 +Subject: [PATCH 1/7] usb: host: fotg2: add Gemini-specific handling + +The Cortina Systems Gemini has bolted on a PHY inside the +silicon that can be handled by six bits in a MISC register in +the system controller. + +If we are running on Gemini, look up a syscon regmap through +a phandle and enable VBUS and optionally the Mini-B connector. + +If the device is flagged as "wakeup-source" using the standard +DT bindings, we also enable this in the global controller for +respective port. + +Signed-off-by: Linus Walleij +--- + drivers/usb/host/Kconfig | 1 + + drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++ + 2 files changed, 77 insertions(+) + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -363,6 +363,7 @@ config USB_ISP1362_HCD + config USB_FOTG210_HCD + tristate "FOTG210 HCD support" + depends on USB && HAS_DMA && HAS_IOMEM ++ select MFD_SYSCON + ---help--- + Faraday FOTG210 is an OTG controller which can be configured as + an USB2.0 host. It is designed to meet USB2.0 EHCI specification +--- a/drivers/usb/host/fotg210-hcd.c ++++ b/drivers/usb/host/fotg210-hcd.c +@@ -33,6 +33,10 @@ + #include + #include + #include ++#include ++/* For Cortina Gemini */ ++#include ++#include + + #include + #include +@@ -5558,6 +5562,72 @@ static void fotg210_init(struct fotg210_ + iowrite32(value, &fotg210->regs->otgcsr); + } + ++/* ++ * Gemini-specific initialization function, only executed on the ++ * Gemini SoC using the global misc control register. ++ */ ++#define GEMINI_GLOBAL_MISC_CTRL 0x30 ++#define GEMINI_MISC_USB0_WAKEUP BIT(14) ++#define GEMINI_MISC_USB1_WAKEUP BIT(15) ++#define GEMINI_MISC_USB0_VBUS_ON BIT(22) ++#define GEMINI_MISC_USB1_VBUS_ON BIT(23) ++#define GEMINI_MISC_USB0_MINI_B BIT(29) ++#define GEMINI_MISC_USB1_MINI_B BIT(30) ++ ++static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd) ++{ ++ struct device_node *np = dev->of_node; ++ struct regmap *map; ++ bool mini_b; ++ bool wakeup; ++ u32 mask, val; ++ int ret; ++ ++ map = syscon_regmap_lookup_by_phandle(np, "syscon"); ++ if (IS_ERR(map)) { ++ dev_err(dev, "no syscon\n"); ++ return PTR_ERR(map); ++ } ++ mini_b = of_property_read_bool(np, "cortina,gemini-mini-b"); ++ wakeup = of_property_read_bool(np, "wakeup-source"); ++ ++ /* ++ * Figure out if this is USB0 or USB1 by simply checking the ++ * physical base address. ++ */ ++ mask = 0; ++ if (hcd->rsrc_start == 0x69000000) { ++ val = GEMINI_MISC_USB1_VBUS_ON; ++ if (mini_b) ++ val |= GEMINI_MISC_USB1_MINI_B; ++ else ++ mask |= GEMINI_MISC_USB1_MINI_B; ++ if (wakeup) ++ val |= GEMINI_MISC_USB1_WAKEUP; ++ else ++ mask |= GEMINI_MISC_USB1_WAKEUP; ++ } else { ++ val = GEMINI_MISC_USB0_VBUS_ON; ++ if (mini_b) ++ val |= GEMINI_MISC_USB0_MINI_B; ++ else ++ mask |= GEMINI_MISC_USB0_MINI_B; ++ if (wakeup) ++ val |= GEMINI_MISC_USB0_WAKEUP; ++ else ++ mask |= GEMINI_MISC_USB0_WAKEUP; ++ } ++ ++ ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val); ++ if (ret) { ++ dev_err(dev, "failed to initialize Gemini PHY\n"); ++ return ret; ++ } ++ ++ dev_info(dev, "initialized Gemini PHY\n"); ++ return 0; ++} ++ + /** + * fotg210_hcd_probe - initialize faraday FOTG210 HCDs + * +@@ -5635,6 +5705,12 @@ static int fotg210_hcd_probe(struct plat + + fotg210_init(fotg210); + ++ if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) { ++ retval = fotg210_gemini_init(dev, hcd); ++ if (retval) ++ goto failed_dis_clk; ++ } ++ + retval = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (retval) { + dev_err(dev, "failed to add hcd with err %d\n", retval); diff --git a/target/linux/gemini/patches-5.4/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch b/target/linux/gemini/patches-5.4/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch new file mode 100644 index 0000000000..39dfd3d535 --- /dev/null +++ b/target/linux/gemini/patches-5.4/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch @@ -0,0 +1,37 @@ +From a2de8560885469f3d76c80207a669029e4fc8a45 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Mon, 11 Mar 2019 15:44:29 +0100 +Subject: [PATCH 2/7] ARM: dts: Augment DIR-685 partition table for OpenWrt + +Rename the firmware partition so that the firmware MTD +splitter will do its job, drop the rootfs arguments as +the MTD splitter will set this up automatically. + +Signed-off-by: Linus Walleij +--- + arch/arm/boot/dts/gemini-dlink-dir-685.dts | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts ++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts +@@ -20,7 +20,7 @@ + }; + + chosen { +- bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300"; ++ bootargs = "console=ttyS0,19200n8 consoleblank=300"; + stdout-path = "uart0:19200n8"; + }; + +@@ -285,9 +285,9 @@ + * this is called "upgrade" on the vendor system. + */ + partition@40000 { +- label = "upgrade"; ++ compatible = "wrg"; ++ label = "firmware"; + reg = <0x00040000 0x01f40000>; +- read-only; + }; + /* RGDB, Residental Gateway Database? */ + partition@1f80000 { diff --git a/target/linux/gemini/patches-5.4/0003-ARM-dts-gemini-Rename-IDE-nodes.patch b/target/linux/gemini/patches-5.4/0003-ARM-dts-gemini-Rename-IDE-nodes.patch new file mode 100644 index 0000000000..6477b2d2a4 --- /dev/null +++ b/target/linux/gemini/patches-5.4/0003-ARM-dts-gemini-Rename-IDE-nodes.patch @@ -0,0 +1,117 @@ +From 9b95b301b219df19c20f4a563f1da6338b09b0d0 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Tue, 31 Dec 2019 18:14:28 +0100 +Subject: [PATCH 3/7] ARM: dts: gemini: Rename IDE nodes + +By renaming the ATA drive nodes to "ide@" we activate the +semantic checks to the DT schema for the controller and use +the correct notation for PATA drives. + +Signed-off-by: Linus Walleij +--- + arch/arm/boot/dts/gemini-dlink-dir-685.dts | 2 +- + arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +- + arch/arm/boot/dts/gemini-nas4220b.dts | 4 ++-- + arch/arm/boot/dts/gemini-sl93512r.dts | 4 ++-- + arch/arm/boot/dts/gemini-sq201.dts | 2 +- + arch/arm/boot/dts/gemini.dtsi | 8 ++++++-- + 6 files changed, 13 insertions(+), 9 deletions(-) + +--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts ++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts +@@ -443,7 +443,7 @@ + }; + }; + +- ata@63000000 { ++ ide@63000000 { + status = "okay"; + }; + +--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts ++++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts +@@ -297,7 +297,7 @@ + }; + }; + +- ata@63000000 { ++ ide@63000000 { + status = "okay"; + }; + }; +--- a/arch/arm/boot/dts/gemini-nas4220b.dts ++++ b/arch/arm/boot/dts/gemini-nas4220b.dts +@@ -170,11 +170,11 @@ + }; + }; + +- ata@63000000 { ++ ide@63000000 { + status = "okay"; + }; + +- ata@63400000 { ++ ide@63400000 { + status = "okay"; + }; + +--- a/arch/arm/boot/dts/gemini-sl93512r.dts ++++ b/arch/arm/boot/dts/gemini-sl93512r.dts +@@ -293,11 +293,11 @@ + }; + }; + +- ata@63000000 { ++ ide@63000000 { + status = "okay"; + }; + +- ata@63400000 { ++ ide@63400000 { + status = "okay"; + }; + +--- a/arch/arm/boot/dts/gemini-sq201.dts ++++ b/arch/arm/boot/dts/gemini-sq201.dts +@@ -289,7 +289,7 @@ + }; + }; + +- ata@63000000 { ++ ide@63000000 { + status = "okay"; + }; + +--- a/arch/arm/boot/dts/gemini.dtsi ++++ b/arch/arm/boot/dts/gemini.dtsi +@@ -356,7 +356,7 @@ + }; + }; + +- ata@63000000 { ++ ide@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x1000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; +@@ -365,9 +365,11 @@ + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; + }; + +- ata@63400000 { ++ ide@63400000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63400000 0x1000>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; +@@ -376,6 +378,8 @@ + clock-names = "PCLK"; + sata = <&sata>; + status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; + }; + + dma-controller@67000000 { diff --git a/target/linux/gemini/patches-5.4/0004-ARM-dts-gemini-Add-thermal-zone-to-DIR-685.patch b/target/linux/gemini/patches-5.4/0004-ARM-dts-gemini-Add-thermal-zone-to-DIR-685.patch new file mode 100644 index 0000000000..5949b92be1 --- /dev/null +++ b/target/linux/gemini/patches-5.4/0004-ARM-dts-gemini-Add-thermal-zone-to-DIR-685.patch @@ -0,0 +1,101 @@ +From 2b2e9d0e1ee4765b21c648235489028c6dc7e336 Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Tue, 31 Dec 2019 18:18:08 +0100 +Subject: [PATCH 4/7] ARM: dts: gemini: Add thermal zone to DIR-685 + +The DIR-685 can now exploit the thermal zone added by the +drive temperature sensor inside the hard drive. We have +patched the libata subsystem to assign the device nodes +properly to the SCSI devices and this is what the drivetemp +driver will use to populate the sensor and the thermal +zone, so pick that up into the thermal zone and let this +control the fan. + +The hardware lacks an embedded temperature sensor so the +D-Link vendor firmware uses this method to control the +temperature of the NAS enclosure using the thermal sensor +inside the hard drive. + +The drive temperature trigger points to be used comes from +the vendor firmware. + +Signed-off-by: Linus Walleij +--- + arch/arm/boot/dts/gemini-dlink-dir-685.dts | 48 ++++++++++++++++++++-- + 1 file changed, 45 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts ++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts +@@ -119,13 +119,11 @@ + + /* + * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. +- * Since the platform has no temperature sensor, this is controlled +- * from userspace by using the hard disks S.M.A.R.T. temperature + * sensor. It is turned on when the temperature exceeds 46 degrees + * and turned off when the temperatures goes below 41 degrees + * (celsius). + */ +- gpio-fan { ++ fan0: gpio-fan { + compatible = "gpio-fan"; + /* Collides with IDE */ + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; +@@ -133,6 +131,40 @@ + #cooling-cells = <2>; + }; + ++ thermal-zones { ++ chassis-thermal { ++ /* Poll every 20 seconds */ ++ polling-delay = <20000>; ++ /* Poll every 2nd second when cooling */ ++ polling-delay-passive = <2000>; ++ /* Use the thermal sensor in the hard drive */ ++ thermal-sensors = <&drive0>; ++ ++ /* Tripping points from the fan.script in the rootfs */ ++ trips { ++ alert: chassis-alert { ++ /* At 43 degrees turn on the fan */ ++ temperature = <43000>; ++ hysteresis = <3000>; ++ type = "active"; ++ }; ++ crit: chassis-crit { ++ /* Just shut down at 60 degrees */ ++ temperature = <60000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&alert>; ++ cooling-device = <&fan0 1 1>; ++ }; ++ }; ++ }; ++ }; ++ + /* + * The touchpad input is connected to a GPIO bit-banged + * I2C bus. +@@ -445,6 +477,16 @@ + + ide@63000000 { + status = "okay"; ++ ++ /* ++ * This drive may have a temperature sensor with a ++ * thermal zone we can use for thermal control of the ++ * chassis temperature using the fan. ++ */ ++ drive0: ide-port@0 { ++ reg = <0>; ++ #thermal-sensor-cells = <0>; ++ }; + }; + + display-controller@6a000000 { diff --git a/target/linux/imx6/Makefile b/target/linux/imx6/Makefile index 49e4487026..8c0770d041 100644 --- a/target/linux/imx6/Makefile +++ b/target/linux/imx6/Makefile @@ -14,7 +14,8 @@ CPU_TYPE:=cortex-a9 CPU_SUBTYPE:=neon MAINTAINER:=Luka Perkov -KERNEL_PATCHVER:=4.14 +KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/imx6/base-files/etc/board.d/02_network b/target/linux/imx6/base-files/etc/board.d/02_network index 6ec667346d..bc0531352e 100755 --- a/target/linux/imx6/base-files/etc/board.d/02_network +++ b/target/linux/imx6/base-files/etc/board.d/02_network @@ -11,17 +11,21 @@ board_config_update case "$board" in cubox-i |\ -*gw51xx |\ -*gw52xx |\ -*gw5904) +gw51xx |\ +gw52xx |\ +gw5904 |\ +gw5907 |\ +gw5910 |\ +gw5912 |\ +gw5913) ucidef_set_interface_lan 'eth0' ;; -*gw53xx |\ -*gw54xx |\ -*gw552x) +gw53xx |\ +gw54xx |\ +gw552x) ucidef_set_interfaces_lan_wan 'eth0' 'eth1' ;; -*wandboard) +wandboard) ucidef_set_interface_wan 'eth0' ;; esac diff --git a/target/linux/imx6/base-files/lib/imx6.sh b/target/linux/imx6/base-files/lib/imx6.sh index 68caaff15f..63fff0f3c4 100755 --- a/target/linux/imx6/base-files/lib/imx6.sh +++ b/target/linux/imx6/base-files/lib/imx6.sh @@ -81,6 +81,26 @@ imx6_board_detect() { name="gw5904" ;; + "Gateworks Ventana i.MX6 DualLite/Solo GW5907" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW5907") + name="gw5907" + ;; + + "Gateworks Ventana i.MX6 DualLite/Solo GW5910" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW5910") + name="gw5910" + ;; + + "Gateworks Ventana i.MX6 DualLite/Solo GW5912" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW5912") + name="gw5912" + ;; + + "Gateworks Ventana i.MX6 DualLite/Solo GW5913" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW5913") + name="gw5913" + ;; + "SolidRun Cubox-i Solo/DualLite" |\ "SolidRun Cubox-i Dual/Quad") name="cubox-i" diff --git a/target/linux/imx6/base-files/lib/preinit/79_move_config b/target/linux/imx6/base-files/lib/preinit/79_move_config index 6b66fbd42d..8f5253e02a 100644 --- a/target/linux/imx6/base-files/lib/preinit/79_move_config +++ b/target/linux/imx6/base-files/lib/preinit/79_move_config @@ -2,6 +2,7 @@ . /lib/imx6.sh . /lib/functions.sh +. /lib/upgrade/common.sh move_config() { local board=$(board_name) diff --git a/target/linux/imx6/base-files/lib/upgrade/platform.sh b/target/linux/imx6/base-files/lib/upgrade/platform.sh index 2d76b6b4af..c687a03ac5 100755 --- a/target/linux/imx6/base-files/lib/upgrade/platform.sh +++ b/target/linux/imx6/base-files/lib/upgrade/platform.sh @@ -4,7 +4,7 @@ . /lib/imx6.sh -RAMFS_COPY_BIN='blkid' +RAMFS_COPY_BIN='blkid jffs2reset' enable_image_metadata_check() { case "$(board_name)" in @@ -23,12 +23,9 @@ apalis_copy_config() { } apalis_do_upgrade() { - local board_name=$(board_name) - board_name=${board_name/,/_} - apalis_mount_boot - get_image "$1" | tar Oxf - sysupgrade-${board_name}/kernel > /boot/uImage - get_image "$1" | tar Oxf - sysupgrade-${board_name}/root > $(rootpart_from_uuid) + get_image "$1" | tar Oxf - sysupgrade-apalis/kernel > /boot/uImage + get_image "$1" | tar Oxf - sysupgrade-apalis/root > $(rootpart_from_uuid) sync umount /boot } @@ -72,3 +69,16 @@ platform_copy_config() { ;; esac } + +platform_pre_upgrade() { + local board=$(board_name) + + case "$board" in + apalis*) + [ -z "$UPGRADE_BACKUP" ] && { + jffs2reset -y + umount /overlay + } + ;; + esac +} diff --git a/target/linux/imx6/config-4.19 b/target/linux/imx6/config-4.19 index 9fada9a01a..9ba1d02b93 100644 --- a/target/linux/imx6/config-4.19 +++ b/target/linux/imx6/config-4.19 @@ -338,7 +338,6 @@ CONFIG_MMC_SDHCI_PLTFM=y # CONFIG_MMC_TIFM_SD is not set CONFIG_MODULES_USE_ELF_REL=y CONFIG_MPILIB=y -# CONFIG_MSCC_OCELOT_SWITCH is not set CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_GPMI_NAND=y @@ -354,11 +353,9 @@ CONFIG_MXS_DMA=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEON=y CONFIG_NET_DSA=y -CONFIG_NET_DSA_LEGACY=y CONFIG_NET_DSA_MV88E6XXX=y CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y # CONFIG_NET_DSA_MV88E6XXX_PTP is not set -# CONFIG_NET_DSA_REALTEK_SMI is not set CONFIG_NET_DSA_TAG_DSA=y CONFIG_NET_DSA_TAG_EDSA=y # CONFIG_NET_DSA_VITESSE_VSC73XX is not set @@ -465,7 +462,6 @@ CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_MCTRL_GPIO=y -# CONFIG_SFP is not set CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y CONFIG_SMP=y diff --git a/target/linux/imx6/config-5.4 b/target/linux/imx6/config-5.4 new file mode 100644 index 0000000000..bd7d95bd9c --- /dev/null +++ b/target/linux/imx6/config-5.4 @@ -0,0 +1,720 @@ +# CONFIG_ADIN_PHY is not set +CONFIG_AHCI_IMX=y +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_AL_FIC is not set +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_ARCH_MILBEAUT is not set +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +# CONFIG_ARCH_RDA is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_814220 is not set +# CONFIG_ARM_ERRATA_857271 is not set +# CONFIG_ARM_ERRATA_857272 is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +# CONFIG_ARM_IMX_CPUFREQ_DT is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ATA=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_IMX_GPT=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMDLINE="pci=nomsi" +CONFIG_CMDLINE_EXTEND=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_SI5341 is not set +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_COUNTER is not set +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_AES_ARM=y +CONFIG_CRYPTO_AES_ARM_BS=y +# CONFIG_CRYPTO_AES_ARM_CE is not set +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CHACHA20=y +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32_ARM_CE=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_ESSIV is not set +# CONFIG_CRYPTO_GHASH_ARM_CE is not set +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_OFB is not set +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_ARM=y +# CONFIG_CRYPTO_SHA1_ARM_CE is not set +CONFIG_CRYPTO_SHA1_ARM_NEON=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM=y +# CONFIG_CRYPTO_SHA2_ARM_CE is not set +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_SIMD=y +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_XTS=y +# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MISC=y +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +CONFIG_E1000E=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EEPROM_EE1004 is not set +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENERGY_MODEL is not set +# CONFIG_EXFAT_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXTCON=y +# CONFIG_EXTCON_PTN5150 is not set +CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +# CONFIG_F2FS_CHECK_FS is not set +CONFIG_F2FS_FS=y +# CONFIG_F2FS_FS_SECURITY is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_STAT_FS=y +CONFIG_FEC=y +# CONFIG_FIELDBUS_DEV is not set +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FSL_GUTS=y +# CONFIG_FSL_QDMA is not set +CONFIG_FS_ENCRYPTION=y +# CONFIG_FSL_IMX8_DDR_PMU is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +# CONFIG_FS_VERITY is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +# CONFIG_GIANFAR is not set +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_CADENCE is not set +CONFIG_GPIO_GENERIC=y +# CONFIG_GPIO_GW_PLD is not set +CONFIG_GPIO_MXC=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +CONFIG_GPIO_SYSFS=y +# CONFIG_HABANA_AI is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IMX_ANATOP=y +CONFIG_HAVE_IMX_GPC=y +CONFIG_HAVE_IMX_MMDC=y +CONFIG_HAVE_IMX_SRC=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_HEADER_TEST is not set +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_IMX_RNGC=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_IMX=y +# CONFIG_I2C_IMX_LPI2C is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I3C is not set +# CONFIG_IGC is not set +# CONFIG_IKHEADERS is not set +CONFIG_IMX2_WDT=y +# CONFIG_IMX7ULP_WDT is not set +CONFIG_IMX_DMA=y +# CONFIG_IMX_GPCV2_PM_DOMAINS is not set +CONFIG_IMX_IRQSTEER=y +CONFIG_IMX_SDMA=y +CONFIG_IMX_THERMAL=y +# CONFIG_IMX_WEIM is not set +# CONFIG_INITRAMFS_FORCE is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_INIT_STACK_NONE=y +# CONFIG_INTERCONNECT is not set +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +# CONFIG_JFFS2_FS is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STPMIC1 is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TQMX86 is not set +CONFIG_MICREL_PHY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +# CONFIG_MISC_ALCOR_PCI is not set +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_MXC is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_AM654 is not set +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +CONFIG_MMC_SDHCI_OF_ESDHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_MOXTET is not set +CONFIG_MPILIB=y +# CONFIG_MTD_HYPERBUS is not set +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_GPMI_NAND=y +# CONFIG_MTD_NAND_MXIC is not set +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MX3_IPU is not set +CONFIG_MXC_CLK=y +CONFIG_MXS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_LANTIQ_GSWIP is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set +CONFIG_NET_DSA_MV88E6XXX=y +CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y +# CONFIG_NET_DSA_MV88E6XXX_PTP is not set +# CONFIG_NET_DSA_SJA1105 is not set +# CONFIG_NET_DSA_TAG_8021Q is not set +# CONFIG_NET_DSA_TAG_BRCM is not set +# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set +CONFIG_NET_DSA_TAG_DSA=y +CONFIG_NET_DSA_TAG_EDSA=y +# CONFIG_NET_DSA_TAG_GSWIP is not set +# CONFIG_NET_DSA_TAG_KSZ is not set +# CONFIG_NET_DSA_TAG_LAN9303 is not set +# CONFIG_NET_DSA_TAG_MTK is not set +# CONFIG_NET_DSA_TAG_QCA is not set +# CONFIG_NET_DSA_TAG_SJA1105 is not set +# CONFIG_NET_DSA_TAG_TRAILER is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NR_CPUS=4 +# CONFIG_NULL_TTY is not set +CONFIG_NVMEM=y +# CONFIG_NVMEM_IMX_IIM is not set +CONFIG_NVMEM_IMX_OCOTP=y +# CONFIG_NVMEM_SNVS_LPGPR is not set +CONFIG_NVMEM_SYSFS=y +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +# CONFIG_PACKING is not set +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_IMX6=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +# CONFIG_PCI_V3_SEMI is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX=y +CONFIG_PINCTRL_IMX6Q=y +CONFIG_PINCTRL_IMX6SL=y +CONFIG_PINCTRL_IMX6SX=y +CONFIG_PINCTRL_IMX6UL=y +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +CONFIG_PL310_ERRATA_769419=y +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_PPS=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_PSI is not set +CONFIG_PTP_1588_CLOCK=y +# CONFIG_PVPANIC is not set +CONFIG_PWM=y +# CONFIG_PWM_IMX1 is not set +# CONFIG_PWM_IMX27 is not set +# CONFIG_PWM_IMX_TPM is not set +CONFIG_PWM_SYSFS=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +# CONFIG_REED_SOLOMON_TEST is not set +CONFIG_REFCOUNT_FULL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_LTC3676=y +# CONFIG_REGULATOR_MCP16502 is not set +CONFIG_REGULATOR_PFUZE100=y +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8824X is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1672=y +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_SD3078 is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_SENSORS_AD7418=y +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +CONFIG_SERIAL_8250_FSL=y +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SFP is not set +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_IMX50 is not set +# CONFIG_SOC_IMX51 is not set +# CONFIG_SOC_IMX53 is not set +CONFIG_SOC_IMX6=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +# CONFIG_SOC_IMX6SLL is not set +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y +# CONFIG_SOC_IMX7D is not set +# CONFIG_SOC_IMX7ULP is not set +# CONFIG_SOC_LS1021A is not set +# CONFIG_SOC_VF610 is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_FSL_LPSPI is not set +# CONFIG_SPI_FSL_QUADSPI is not set +CONFIG_SPI_IMX=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_SIFIVE is not set +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +CONFIG_STMP_DEVICE=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_XARRAY is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_MMIO is not set +CONFIG_THERMAL_OF=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TRUSTED_FOUNDATIONS is not set +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +# CONFIG_UBIFS_FS_AUTHENTICATION is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y +# CONFIG_UCLAMP_TASK is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_UNICODE is not set +CONFIG_UNWINDER_ARM=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_USB=y +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_CDNS3 is not set +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_OF=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_COMMON=y +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_EHCI_MXC is not set +CONFIG_USB_GADGET=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_OTG=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USE_OF=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_XILINX_SDFEC is not set +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/imx6/files/firmware/imx/sdma/sdma-imx6q.bin b/target/linux/imx6/files/firmware/imx/sdma/sdma-imx6q.bin index 73c588655df47bd00e6d9d79b68de8cbfbabe6ae..4d0593cec7dfdae1a8bf28a2d83bdd1e95839b82 100644 GIT binary patch delta 1124 zcmZuvU1%It7`^w-ow+-+Y13q#CfizO)0*A9Y(puULa9+|Y(TcD`=c?*q;Zo-9Mhkd z(6!9$qHofIhKsN>vx*P;P)ZfSzKDq3KwL-zg%v4DRIEmR;-S)N_evC4`U+cpMN1Tm$@}BJ?&vXtpD^y`I>KP#vxs5C_BS^@UmU zh3JiTgzoP^Xb_}#VCY?80o*WP2Kaqo9iX%GKOTuY2kbYgVJ}`k9c+3lUn0uT%Y~AHV^RbS)NC;yN}>K6_T}Ot{~3pjFN!)^ysl-H zAu)wv>b{No|Fi`UCp<(hVTE5I`u?qMbSPH91~~Qq{?Mu0)e+69pjNZdp}o+FUbtzZ z=c;4`Zx$J9nhKS*@^5^jJy z2ayE7EbZy>+>gl*gg8$#&m9HSGAKdpqFgiYBp;+LcEFit*tzMx!5sT_Mx80}#aln; z&D3a~Z|q1i)Z7i2=ZEOd!`EDDK2~@~;m1%vb}qOho{p59m>FOs^Mu*Wus!0np;Pe0 z5uW(~F*Lq3<8FH2<38PF8G%DWC7^QgIL5%osA^(E@lVhx0TNsCW_?HSi}MP1igNPS0v z5&I+gG=E?2IUaWm2+33S>e6~hl;lKyOd`%U(n?fov>@)ojr-t6KyGaWX}?*>0e)3nRF zThPiE{T}WI`r4u;u`B$KY|!e2T2z|V$@gjDmV3U~u$sgHGKlHG%3a=}#`UA609!t; zv2$oHxd2gJgQ)iMadmvlM2VsLRMQk96Q%EXRXx%+_lSFW!@b;a=cPy8*H+%+!&-cM K?SI@?O8){~*k$4X delta 1167 zcmZuvU2GIp82#qX-MKrn1!>FDb{E_&V7FBXqFL|-lBR8_A!~JaOY4}0I;ODxQ*TIiW*3p92`~8bU?LhH*zE%oYkaT?Arv$qCQ5A@f8tMgSiienDJqkk zneRLI-gCa0IiH2!4aYORscsnnC}K0>A%u^(qykJ6fSLBhrfN?Vpo-TL61&@0>(ev2 z1NUER1z3pyJc&nt#7%Ds3FMwdOh#tD`o`(BAG2Pg5oq_BLleD)^UGL(xl$l#t>u@RtSszgr&`!r))l?#YXl z(7#uBlAL-%ay8>obb6%jG{T6j=&IYHCmbmzJb$QrKIn#lP6=1l=+L{c6TNWLM9-sg zEOfKLpkb`JqE)W*J~^}VIrq=>V)k?LB~dL4l{?cWG7GDW4RqK&0Tt2LWiflwbNZ5|A4l( z&6#A%AEmi&ln6{+G(}zOc`C4F?*WhI)+E}!A#Zh%>bMvM;Jd8&43ahJ4!feRYK^2C zaTu}Q3moNV1A8z`5e(C=dYF{-NPa{n_6E{KR8x1veW-TN)`GNB|EU$6CJc*Llyu0% zFvX?BKVd54ir}^X@q$(V!*=l(lwHy*+*K0N%e<^4r4au^No?C)6#614!l46^tTCe3 zu-D8a?`AReH}BO-mTHxs`4QF=n=Wp^_gk3o%|gfA#5+abm?)}dt0O%CshE9`&$EQO zzsP_Z4d&bYHfviqUFMg!k-4X6B1=-?Zjh%qG^gIUl zCk$?qJL>c6^b&*WSi=|)z4QfNQTMledYAh7JL>0!deiaJ-Rd{4zE$G;)Q2}+zlZ$S GrN04F;%`g< diff --git a/target/linux/imx6/image/Makefile b/target/linux/imx6/image/Makefile index 85d6823021..232dc4225f 100644 --- a/target/linux/imx6/image/Makefile +++ b/target/linux/imx6/image/Makefile @@ -131,7 +131,9 @@ define Device/Default endef define Device/ventana - DEVICE_TITLE := Gateworks Ventana family (normal NAND flash) + DEVICE_VENDOR := Gateworks + DEVICE_MODEL := Ventana family + DEVICE_VARIANT := normal NAND flash DEVICE_DTS:= \ imx6dl-gw51xx \ imx6dl-gw52xx \ @@ -141,6 +143,10 @@ define Device/ventana imx6dl-gw552x \ imx6dl-gw553x \ imx6dl-gw5904 \ + imx6dl-gw5907 \ + imx6dl-gw5910 \ + imx6dl-gw5912 \ + imx6dl-gw5913 \ imx6q-gw51xx \ imx6q-gw52xx \ imx6q-gw53xx \ @@ -149,19 +155,24 @@ define Device/ventana imx6q-gw551x \ imx6q-gw552x \ imx6q-gw553x \ - imx6q-gw5904 + imx6q-gw5904 \ + imx6q-gw5907 \ + imx6q-gw5910 \ + imx6q-gw5912 \ + imx6q-gw5913 DEVICE_PACKAGES := kmod-sky2 kmod-sound-core kmod-sound-soc-imx kmod-sound-soc-imx-sgtl5000 \ kmod-can kmod-can-flexcan kmod-can-raw \ kmod-hwmon-gsc \ kmod-leds-gpio kmod-pps-gpio \ kobs-ng KERNEL += | boot-overlay - IMAGES := nand.ubi bootfs.tar.gz + IMAGES := nand.ubi bootfs.tar.gz dtb IMAGE_NAME = $$(IMAGE_PREFIX)-$$(1).$$(2) UBINIZE_PARTS = boot=$$(KDIR_KERNEL_IMAGE).boot.ubifs=15 BOOT_SCRIPT := bootscript-ventana IMAGE/nand.ubi := append-ubi - IMAGE/bootfs.tar.gz := bootfs.tar.gz | install-dtb + IMAGE/bootfs.tar.gz := bootfs.tar.gz + IMAGE/dtb := install-dtb IMAGE_NAME = $$(IMAGE_PREFIX)-$$(1)-$$(2) PAGESIZE := 2048 BLOCKSIZE := 128k @@ -171,8 +182,10 @@ TARGET_DEVICES += ventana define Device/ventana-large $(Device/ventana) + DEVICE_VENDOR := Gateworks + DEVICE_MODEL := Ventana family + DEVICE_VARIANT := large NAND flash DEVICE_NAME := ventana - DEVICE_TITLE := Gateworks Ventana family (large NAND flash) IMAGES := nand.ubi PAGESIZE := 4096 BLOCKSIZE := 256k @@ -181,27 +194,31 @@ endef TARGET_DEVICES += ventana-large define Device/wandboard - DEVICE_TITLE := Wandboard Dual + DEVICE_VENDOR := Wandboard + DEVICE_MODEL := Dual DEVICE_DTS := imx6dl-wandboard endef TARGET_DEVICES += wandboard define Device/cubox-i - KERNEL := kernel-bin | install-dtb + DEVICE_VENDOR := SolidRun + DEVICE_MODEL := CuBox-i + KERNEL := kernel-bin UBOOT := mx6cuboxi BOOT_SCRIPT = bootscript-cubox DEVICE_NAME := cubox - DEVICE_TITLE := SolidRun CuBox-i DEVICE_PACKAGES := kmod-drm-imx kmod-drm-imx-hdmi kmod-usb-hid DEVICE_DTS := imx6q-cubox-i imx6dl-cubox-i imx6q-hummingboard imx6dl-hummingboard - IMAGES := combined.bin + IMAGES := combined.bin dtb FILESYSTEMS := squashfs IMAGE/combined.bin := append-rootfs | pad-extra 128k | imx6-sdcard + IMAGE/dtb := install-dtb endef TARGET_DEVICES += cubox-i define Device/apalis - DEVICE_TITLE := Toradex Apalis family + DEVICE_VENDOR := Toradex + DEVICE_MODEL := Apalis family SUPPORTED_DEVICES := apalis,ixora apalis,eval DEVICE_DTS := \ imx6q-apalis-eval \ diff --git a/target/linux/imx6/image/bootscript-apalis b/target/linux/imx6/image/bootscript-apalis index 81a501cc63..3a3a6dadb1 100644 --- a/target/linux/imx6/image/bootscript-apalis +++ b/target/linux/imx6/image/bootscript-apalis @@ -1,12 +1,13 @@ -echo "Toradex Apalis OpenWrt Boot script v1.0" +echo "Toradex Apalis OpenWrt Boot script v1.1" -run finduuid +run emmcfinduuid setenv nextcon 0 +setenv boot_file uImage setenv fdt_file imx6q-apalis-ixora.dtb setenv root root=PARTUUID=${uuid} rootfstype=squashfs rootwait setenv bootargs earlyprintk console=${console},${baudrate}n8 ${root} -setenv fsload ext4load mmc ${mmcbootdev}:${bootpart} +setenv fsload ext4load mmc ${emmcdev}:${emmcbootpart} if ${fsload} ${kernel_addr_r} ${boot_file}; then if ${fsload} ${fdt_addr_r} ${fdt_file}; then diff --git a/target/linux/imx6/image/bootscript-ventana b/target/linux/imx6/image/bootscript-ventana index 941afb519a..734f74a30c 100644 --- a/target/linux/imx6/image/bootscript-ventana +++ b/target/linux/imx6/image/bootscript-ventana @@ -1,4 +1,4 @@ -echo "Gateworks Ventana OpenWrt Boot script v1.01" +echo "Gateworks Ventana OpenWrt Boot script v1.02" # set some defaults # set some defaults @@ -9,7 +9,7 @@ setenv bootargs console=${console},${baudrate} setenv loadaddr 10800000 setenv fdt_addr 18000000 -# detect dtype and bootdev by looking for kernel on media the bootloader +# detect dtype by looking for kernel on media the bootloader # has mounted (in order of preference: usb/mmc/sata) # # This assumes the bootloader has already started the respective subsystem @@ -31,18 +31,9 @@ else fi echo "detected dtype:$dtype" fi -if test -n "$bootdev" ; then - echo "Using bootdev from env: $bootdev" -else - if itest.s "x${dtype}" == "xmmc" ; then - bootdev=mmcblk0p1 - else - bootdev=sda1 - fi -fi +echo "Booting from ${dtype}..." if itest.s "x${dtype}" == "xnand" ; then - echo "Booting from NAND..." # fix partition name # OpenWrt kernel bug prevents partition name of 'rootfs' from booting # instead name the partition ubi which is what is looked for by @@ -52,9 +43,24 @@ if itest.s "x${dtype}" == "xnand" ; then setenv fsload ubifsload setenv root "ubi0:ubi ubi.mtd=2 rootfstype=squashfs,ubifs" else - echo "Booting from block device ${bootdev}..." setenv fsload "${fs}load ${dtype} ${disk}:1" - setenv root "root=/dev/${bootdev} rootfstype=${fs} rootwait rw" + part uuid ${dtype} ${disk}:1 uuid + if test -z "${uuid}"; then + # fallback to bootdev + if test -n "$bootdev" ; then + echo "Using bootdev from env: $bootdev" + else + if itest.s "x${dtype}" == "xmmc" ; then + bootdev=mmcblk0p1 + else + bootdev=sda1 + fi + fi + setenv root "root=/dev/${bootdev}" + else + setenv root "root=PARTUUID=${uuid}" + fi + setenv root "$root rootfstype=${fs} rootwait rw" fi setenv bootargs "${bootargs}" "${root}" "${video}" "${extra}" diff --git a/target/linux/imx6/image/recovery-apalis b/target/linux/imx6/image/recovery-apalis index c1c5a3f5d6..d75b954345 100644 --- a/target/linux/imx6/image/recovery-apalis +++ b/target/linux/imx6/image/recovery-apalis @@ -4,6 +4,7 @@ mmc dev 0 1 mmc write 0x12100000 0x2 0x800 # flash openwrt-imx6-apalis-squashfs.combined.bin +setenv set_blkcnt 'setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200' run set_blkcnt mmc dev 0 0 mmc write 0x12500000 0 ${blkcnt} diff --git a/target/linux/imx6/patches-4.19/001-ARM-dts-imx-Add-GW5907-board-support.patch b/target/linux/imx6/patches-4.19/001-ARM-dts-imx-Add-GW5907-board-support.patch index 99d11692fa..a4e9604ffa 100644 --- a/target/linux/imx6/patches-4.19/001-ARM-dts-imx-Add-GW5907-board-support.patch +++ b/target/linux/imx6/patches-4.19/001-ARM-dts-imx-Add-GW5907-board-support.patch @@ -26,9 +26,11 @@ Signed-off-by: Shawn Guo create mode 100644 arch/arm/boot/dts/imx6q-gw5907.dts create mode 100644 arch/arm/boot/dts/imx6qdl-gw5907.dtsi +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 1e9e1af..9ee80e2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -404,6 +404,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -422,6 +422,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw560x.dtb \ imx6dl-gw5903.dtb \ imx6dl-gw5904.dtb \ @@ -36,7 +38,7 @@ Signed-off-by: Shawn Guo imx6dl-hummingboard.dtb \ imx6dl-hummingboard-emmc-som-v15.dtb \ imx6dl-hummingboard-som-v15.dtb \ -@@ -471,6 +472,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -493,6 +494,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw560x.dtb \ imx6q-gw5903.dtb \ imx6q-gw5904.dtb \ @@ -44,6 +46,9 @@ Signed-off-by: Shawn Guo imx6q-h100.dtb \ imx6q-hummingboard.dtb \ imx6q-hummingboard-emmc-som-v15.dtb \ +diff --git a/arch/arm/boot/dts/imx6dl-gw5907.dts b/arch/arm/boot/dts/imx6dl-gw5907.dts +new file mode 100644 +index 00000000..3fa2822 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw5907.dts @@ -0,0 +1,14 @@ @@ -61,6 +66,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907"; + compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl"; +}; +diff --git a/arch/arm/boot/dts/imx6q-gw5907.dts b/arch/arm/boot/dts/imx6q-gw5907.dts +new file mode 100644 +index 00000000..b25526e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw5907.dts @@ -0,0 +1,14 @@ @@ -78,6 +86,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 Dual/Quad GW5907"; + compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q"; +}; +diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi +new file mode 100644 +index 00000000..0bdebdd --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi @@ -0,0 +1,399 @@ @@ -480,3 +491,6 @@ Signed-off-by: Shawn Guo + >; + }; +}; +-- +2.7.4 + diff --git a/target/linux/imx6/patches-4.19/002-ARM-dts-imx-Add-GW5910-board-support.patch b/target/linux/imx6/patches-4.19/002-ARM-dts-imx-Add-GW5910-board-support.patch index ec982e96ad..aade7650f9 100644 --- a/target/linux/imx6/patches-4.19/002-ARM-dts-imx-Add-GW5910-board-support.patch +++ b/target/linux/imx6/patches-4.19/002-ARM-dts-imx-Add-GW5910-board-support.patch @@ -35,9 +35,11 @@ Signed-off-by: Shawn Guo create mode 100644 arch/arm/boot/dts/imx6q-gw5910.dts create mode 100644 arch/arm/boot/dts/imx6qdl-gw5910.dtsi +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 9ee80e2..85e53cc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -405,6 +405,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -423,6 +423,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw5903.dtb \ imx6dl-gw5904.dtb \ imx6dl-gw5907.dtb \ @@ -45,7 +47,7 @@ Signed-off-by: Shawn Guo imx6dl-hummingboard.dtb \ imx6dl-hummingboard-emmc-som-v15.dtb \ imx6dl-hummingboard-som-v15.dtb \ -@@ -473,6 +474,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -495,6 +496,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw5903.dtb \ imx6q-gw5904.dtb \ imx6q-gw5907.dtb \ @@ -53,6 +55,9 @@ Signed-off-by: Shawn Guo imx6q-h100.dtb \ imx6q-hummingboard.dtb \ imx6q-hummingboard-emmc-som-v15.dtb \ +diff --git a/arch/arm/boot/dts/imx6dl-gw5910.dts b/arch/arm/boot/dts/imx6dl-gw5910.dts +new file mode 100644 +index 00000000..0d5e7e5 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw5910.dts @@ -0,0 +1,14 @@ @@ -70,6 +75,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910"; + compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl"; +}; +diff --git a/arch/arm/boot/dts/imx6q-gw5910.dts b/arch/arm/boot/dts/imx6q-gw5910.dts +new file mode 100644 +index 00000000..6aafa2f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw5910.dts @@ -0,0 +1,14 @@ @@ -87,6 +95,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 Dual/Quad GW5910"; + compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q"; +}; +diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +new file mode 100644 +index 00000000..be1af74 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -0,0 +1,491 @@ @@ -581,3 +592,6 @@ Signed-off-by: Shawn Guo + >; + }; +}; +-- +2.7.4 + diff --git a/target/linux/imx6/patches-4.19/003-ARM-dts-imx-Add-GW5913-board-support.patch b/target/linux/imx6/patches-4.19/003-ARM-dts-imx-Add-GW5913-board-support.patch index 9c46401201..2d242fb890 100644 --- a/target/linux/imx6/patches-4.19/003-ARM-dts-imx-Add-GW5913-board-support.patch +++ b/target/linux/imx6/patches-4.19/003-ARM-dts-imx-Add-GW5913-board-support.patch @@ -30,9 +30,11 @@ Signed-off-by: Shawn Guo create mode 100644 arch/arm/boot/dts/imx6q-gw5913.dts create mode 100644 arch/arm/boot/dts/imx6qdl-gw5913.dtsi +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 85e53cc..5b059fc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -406,6 +406,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -424,6 +424,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw5904.dtb \ imx6dl-gw5907.dtb \ imx6dl-gw5910.dtb \ @@ -40,7 +42,7 @@ Signed-off-by: Shawn Guo imx6dl-hummingboard.dtb \ imx6dl-hummingboard-emmc-som-v15.dtb \ imx6dl-hummingboard-som-v15.dtb \ -@@ -475,6 +476,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -497,6 +498,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw5904.dtb \ imx6q-gw5907.dtb \ imx6q-gw5910.dtb \ @@ -48,6 +50,9 @@ Signed-off-by: Shawn Guo imx6q-h100.dtb \ imx6q-hummingboard.dtb \ imx6q-hummingboard-emmc-som-v15.dtb \ +diff --git a/arch/arm/boot/dts/imx6dl-gw5913.dts b/arch/arm/boot/dts/imx6dl-gw5913.dts +new file mode 100644 +index 00000000..b74e533 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw5913.dts @@ -0,0 +1,14 @@ @@ -65,6 +70,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913"; + compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl"; +}; +diff --git a/arch/arm/boot/dts/imx6q-gw5913.dts b/arch/arm/boot/dts/imx6q-gw5913.dts +new file mode 100644 +index 00000000..6f511f1 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw5913.dts @@ -0,0 +1,14 @@ @@ -82,6 +90,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 Dual/Quad GW5913"; + compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q"; +}; +diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +new file mode 100644 +index 00000000..635c203 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi @@ -0,0 +1,348 @@ @@ -433,3 +444,6 @@ Signed-off-by: Shawn Guo + >; + }; +}; +-- +2.7.4 + diff --git a/target/linux/imx6/patches-4.19/004-ARM-dts-imx-Add-GW5912-board-support.patch b/target/linux/imx6/patches-4.19/004-ARM-dts-imx-Add-GW5912-board-support.patch index cd03a95d8e..a47cb279cb 100644 --- a/target/linux/imx6/patches-4.19/004-ARM-dts-imx-Add-GW5912-board-support.patch +++ b/target/linux/imx6/patches-4.19/004-ARM-dts-imx-Add-GW5912-board-support.patch @@ -35,9 +35,11 @@ Signed-off-by: Shawn Guo create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 5b059fc..1a32a7d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -406,6 +406,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -424,6 +424,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw5904.dtb \ imx6dl-gw5907.dtb \ imx6dl-gw5910.dtb \ @@ -45,7 +47,7 @@ Signed-off-by: Shawn Guo imx6dl-gw5913.dtb \ imx6dl-hummingboard.dtb \ imx6dl-hummingboard-emmc-som-v15.dtb \ -@@ -476,6 +477,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ +@@ -498,6 +499,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw5904.dtb \ imx6q-gw5907.dtb \ imx6q-gw5910.dtb \ @@ -53,6 +55,9 @@ Signed-off-by: Shawn Guo imx6q-gw5913.dtb \ imx6q-h100.dtb \ imx6q-hummingboard.dtb \ +diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/imx6dl-gw5912.dts +new file mode 100644 +index 00000000..5260e01 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw5912.dts @@ -0,0 +1,13 @@ @@ -69,6 +74,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912"; + compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl"; +}; +diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/imx6q-gw5912.dts +new file mode 100644 +index 00000000..4dcbd94 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw5912.dts @@ -0,0 +1,13 @@ @@ -85,6 +93,9 @@ Signed-off-by: Shawn Guo + model = "Gateworks Ventana i.MX6 Dual/Quad GW5912"; + compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q"; +}; +diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +new file mode 100644 +index 00000000..8c57fd2 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi @@ -0,0 +1,461 @@ @@ -549,3 +560,6 @@ Signed-off-by: Shawn Guo + >; + }; +}; +-- +2.7.4 + diff --git a/target/linux/imx6/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch b/target/linux/imx6/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch new file mode 100644 index 0000000000..133c3b9566 --- /dev/null +++ b/target/linux/imx6/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch @@ -0,0 +1,482 @@ +From 125120298dc05bb55a8874f07aa3f4bb6056bfb3 Mon Sep 17 00:00:00 2001 +From: Robert Jones +Date: Wed, 8 Jan 2020 07:44:21 -0800 +Subject: [PATCH 1/4] ARM: dts: imx: Add GW5907 board support + +The Gateworks GW5907 is an IMX6 SoC based single board computer with: + - IMX6Q or IMX6DL + - 32bit DDR3 DRAM + - FEC GbE Phy + - bi-color front-panel LED + - 256MB NAND boot device + - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) + - Digital IO expander (pca9555) + - Joystick 12bit adc (ads1015) + +Signed-off-by: Robert Jones +Reviewed-by: Tim Harvey +Signed-off-by: Shawn Guo +--- + arch/arm/boot/dts/Makefile | 2 + + arch/arm/boot/dts/imx6dl-gw5907.dts | 14 ++ + arch/arm/boot/dts/imx6q-gw5907.dts | 14 ++ + arch/arm/boot/dts/imx6qdl-gw5907.dtsi | 399 ++++++++++++++++++++++++++++++++++ + 4 files changed, 429 insertions(+) + create mode 100644 arch/arm/boot/dts/imx6dl-gw5907.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw5907.dts + create mode 100644 arch/arm/boot/dts/imx6qdl-gw5907.dtsi + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -418,6 +418,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-gw560x.dtb \ + imx6dl-gw5903.dtb \ + imx6dl-gw5904.dtb \ ++ imx6dl-gw5907.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ +@@ -489,6 +490,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6q-gw560x.dtb \ + imx6q-gw5903.dtb \ + imx6q-gw5904.dtb \ ++ imx6q-gw5907.dtb \ + imx6q-h100.dtb \ + imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw5907.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++ ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw5907.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907"; ++ compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw5907.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++ ++#include "imx6q.dtsi" ++#include "imx6qdl-gw5907.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5907"; ++ compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi +@@ -0,0 +1,399 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++#include ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ led0 = &led0; ++ led1 = &led1; ++ nand = &gpmi; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ }; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_leds>; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory@10000000 { ++ device_type = "memory"; ++ reg = <0x10000000 0x20000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pps>; ++ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_5p0v: regulator-5p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "5P0V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_otg_vbus: regulator-usb-otg-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet>; ++ phy-mode = "rgmii-id"; ++ phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ gpio@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ rtc@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++ ++ gpio@20 { ++ compatible = "nxp,pca9555"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ adc@48 { ++ compatible = "ti,ads1015"; ++ reg = <0x48>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ channel@4 { ++ reg = <4>; ++ ti,gain = <0>; ++ ti,datarate = <5>; ++ }; ++ ++ channel@5 { ++ reg = <5>; ++ ti,gain = <0>; ++ ti,datarate = <5>; ++ }; ++ ++ channel@6 { ++ reg = <6>; ++ ti,gain = <0>; ++ ti,datarate = <5>; ++ }; ++ }; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie>; ++ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ ++ status = "disabled"; ++}; ++ ++&pwm3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ ++ status = "disabled"; ++}; ++ ++&pwm4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ ++ status = "disabled"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ status = "okay"; ++}; ++ ++&wdog1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wdog>; ++ fsl,ext-reset-output; ++}; ++ ++&iomuxc { ++ pinctrl_enet: enetgrp { ++ fsl,pins = < ++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 ++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 ++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 ++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 ++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 ++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 ++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 ++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 ++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 ++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 ++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 ++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_gpio_leds: gpioledsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_gpmi_nand: gpminandgrp { ++ fsl,pins = < ++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 ++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 ++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 ++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 ++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 ++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 ++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 ++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 ++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 ++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 ++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 ++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 ++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 ++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 ++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 ++ >; ++ }; ++ ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 ++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 ++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 ++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 ++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 ++ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_pcie: pciegrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_pps: ppsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm2: pwm2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm3: pwm3grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm4: pwm4grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart3: uart3grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart5: uart5grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_usbotg: usbotggrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 ++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_wdog: wdoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 ++ >; ++ }; ++}; diff --git a/target/linux/imx6/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch b/target/linux/imx6/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch new file mode 100644 index 0000000000..707577edc1 --- /dev/null +++ b/target/linux/imx6/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch @@ -0,0 +1,583 @@ +From a1fb69366bb16753f0fba6a891fbef5cdd97cfbe Mon Sep 17 00:00:00 2001 +From: Tim Harvey +Date: Wed, 8 Jan 2020 07:44:22 -0800 +Subject: [PATCH 2/4] ARM: dts: imx: Add GW5910 board support + +The Gateworks GW5910 is an IMX6 SoC based single board computer with: + - IMX6Q or IMX6DL + - 32bit DDR3 DRAM + - FEC GbE RJ45 front-panel + - 1x miniPCIe socket with PCI Gen2, USB2 + - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM + - 5V to 60V DC input barrel jack + - 3axis accelerometer (lis2de12) + - GPS (ublox ZOE-M8Q) + - bi-color front-panel LED + - 256MB NAND boot device + - microSD socket (with UHS-I support) + - user pushbutton + - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) + - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6) + - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6) + - RS232 transceiver (1x UART with flow-control or 2x UART (build option) + - off-board SPI connector (1x chip-select) + +Signed-off-by: Tim Harvey +Signed-off-by: Robert Jones +Signed-off-by: Shawn Guo +--- + arch/arm/boot/dts/Makefile | 2 + + arch/arm/boot/dts/imx6dl-gw5910.dts | 14 + + arch/arm/boot/dts/imx6q-gw5910.dts | 14 + + arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 491 ++++++++++++++++++++++++++++++++++ + 4 files changed, 521 insertions(+) + create mode 100644 arch/arm/boot/dts/imx6dl-gw5910.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw5910.dts + create mode 100644 arch/arm/boot/dts/imx6qdl-gw5910.dtsi + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -419,6 +419,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-gw5903.dtb \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ ++ imx6dl-gw5910.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ +@@ -491,6 +492,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6q-gw5903.dtb \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ ++ imx6q-gw5910.dtb \ + imx6q-h100.dtb \ + imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw5910.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++ ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw5910.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910"; ++ compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw5910.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++ ++#include "imx6q.dtsi" ++#include "imx6qdl-gw5910.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5910"; ++ compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +@@ -0,0 +1,491 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++#include ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ led0 = &led0; ++ led1 = &led1; ++ led2 = &led2; ++ }; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ memory@10000000 { ++ device_type = "memory"; ++ reg = <0x10000000 0x20000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_leds>; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ ++ led2: user3 { ++ label = "user3"; ++ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ ++ default-state = "off"; ++ }; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pps>; ++ gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_5p0v: regulator-5p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "5P0V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_wl: regulator-wl { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_reg_wl>; ++ compatible = "regulator-fixed"; ++ regulator-name = "wl"; ++ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <100>; ++ enable-active-high; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_bt: regulator-bt { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_reg_bt>; ++ compatible = "regulator-fixed"; ++ regulator-name = "bt"; ++ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <100>; ++ enable-active-high; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++}; ++ ++ ++&ecspi3 { ++ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi3>; ++ status = "okay"; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ gpio@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ rtc@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++ ++ accel@19 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_accel>; ++ compatible = "st,lis2de12"; ++ reg = <0x19>; ++ st,drdy-int-pin = <1>; ++ interrupt-parent = <&gpio7>; ++ interrupts = <13 0>; ++ interrupt-names = "INT1"; ++ }; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie>; ++ reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ ++ status = "disabled"; ++}; ++ ++&pwm3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ ++ status = "disabled"; ++}; ++ ++/* off-board RS232 */ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ status = "okay"; ++}; ++ ++/* serial console */ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ status = "okay"; ++}; ++ ++/* Sterling-LWB Bluetooth */ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart4>; ++ uart-has-rtscts; ++ status = "okay"; ++}; ++ ++/* GPS */ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_5p0v>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ status = "okay"; ++}; ++ ++/* Sterling-LWB SDIO WiFi */ ++&usdhc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc2>; ++ vmmc-supply = <®_3p3v>; ++ non-removable; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc3>; ++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; ++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; ++ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; ++ ++&wdog1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wdog>; ++ fsl,ext-reset-output; ++}; ++ ++&iomuxc { ++ pinctrl_accel: accelmuxgrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_ecspi3: escpi3grp { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 ++ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 ++ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 ++ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 ++ >; ++ }; ++ ++ pinctrl_enet: enetgrp { ++ fsl,pins = < ++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 ++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 ++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 ++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 ++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 ++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 ++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 ++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 ++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 ++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 ++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 ++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 ++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 ++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 ++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 ++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_gpio_leds: gpioledsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 ++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_gpmi_nand: gpminandgrp { ++ fsl,pins = < ++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 ++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 ++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 ++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 ++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 ++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 ++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 ++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 ++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 ++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 ++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 ++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 ++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 ++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 ++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 ++ >; ++ }; ++ ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 ++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 ++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 ++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 ++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_pcie: pciegrp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_pps: ppsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm2: pwm2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm3: pwm3grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_reg_bt: regbtgrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_reg_wl: regwlgrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart4: uart4grp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 ++ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 ++ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart5: uart5grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_usbotg: usbotggrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 ++ >; ++ }; ++ ++ pinctrl_usdhc2: usdhc2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 ++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 ++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 ++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 ++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 ++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 ++ >; ++ }; ++ ++ pinctrl_usdhc3: usdhc3grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ ++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 ++ >; ++ }; ++ ++ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ ++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 ++ >; ++ }; ++ ++ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ ++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 ++ >; ++ }; ++ ++ pinctrl_wdog: wdoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 ++ >; ++ }; ++}; diff --git a/target/linux/imx6/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch b/target/linux/imx6/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch new file mode 100644 index 0000000000..07a7cbfc88 --- /dev/null +++ b/target/linux/imx6/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch @@ -0,0 +1,435 @@ +From 169e12f99cf9d5fce752564f32fd8df96461de43 Mon Sep 17 00:00:00 2001 +From: Robert Jones +Date: Wed, 8 Jan 2020 07:44:23 -0800 +Subject: [PATCH 3/4] ARM: dts: imx: Add GW5913 board support + +The Gateworks GW5913 is an IMX6 SoC based single board computer with: + - IMX6Q or IMX6DL + - 32bit DDR3 DRAM + - FEC GbE RJ45 front-panel + - 1x miniPCIe socket with PCI Gen2, USB2 + - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM + - 6V to 60V DC input connector + - GPS (ublox ZOE-M8Q) + - bi-color front-panel LED + - 256MB NAND boot device + - nanoSIM socket + - user pushbutton + - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) + +Signed-off-by: Robert Jones +Reviewed-by: Tim Harvey +Signed-off-by: Shawn Guo +--- + arch/arm/boot/dts/Makefile | 2 + + arch/arm/boot/dts/imx6dl-gw5913.dts | 14 ++ + arch/arm/boot/dts/imx6q-gw5913.dts | 14 ++ + arch/arm/boot/dts/imx6qdl-gw5913.dtsi | 348 ++++++++++++++++++++++++++++++++++ + 4 files changed, 378 insertions(+) + create mode 100644 arch/arm/boot/dts/imx6dl-gw5913.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw5913.dts + create mode 100644 arch/arm/boot/dts/imx6qdl-gw5913.dtsi + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ + imx6dl-gw5910.dtb \ ++ imx6dl-gw5913.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ +@@ -493,6 +494,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ + imx6q-gw5910.dtb \ ++ imx6q-gw5913.dtb \ + imx6q-h100.dtb \ + imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw5913.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++ ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw5913.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913"; ++ compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw5913.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++ ++#include "imx6q.dtsi" ++#include "imx6qdl-gw5913.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5913"; ++ compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +@@ -0,0 +1,348 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++#include ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ led0 = &led0; ++ led1 = &led1; ++ nand = &gpmi; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ }; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_leds>; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory@10000000 { ++ device_type = "memory"; ++ reg = <0x10000000 0x20000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pps>; ++ gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_5p0v: regulator-5p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "5P0V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ gpio@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ rtc@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie>; ++ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ ++ status = "disabled"; ++}; ++ ++&pwm3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ ++ status = "disabled"; ++}; ++ ++&pwm4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ ++ status = "disabled"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ status = "okay"; ++}; ++ ++&wdog1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wdog>; ++ fsl,ext-reset-output; ++}; ++ ++&iomuxc { ++ pinctrl_enet: enetgrp { ++ fsl,pins = < ++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 ++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 ++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 ++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 ++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 ++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 ++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 ++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 ++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 ++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 ++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 ++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 ++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 ++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 ++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 ++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 ++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_gpio_leds: gpioledsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_gpmi_nand: gpminandgrp { ++ fsl,pins = < ++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 ++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 ++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 ++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 ++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 ++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 ++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 ++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 ++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 ++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 ++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 ++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 ++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 ++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 ++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 ++ >; ++ }; ++ ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 ++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 ++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 ++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 ++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_pcie: pciegrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_pps: ppsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm2: pwm2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm3: pwm3grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm4: pwm4grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart3: uart3grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart5: uart5grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_usbotg: usbotggrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 ++ >; ++ }; ++ ++ pinctrl_wdog: wdoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 ++ >; ++ }; ++}; diff --git a/target/linux/imx6/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch b/target/linux/imx6/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch new file mode 100644 index 0000000000..cf0ff9dbb2 --- /dev/null +++ b/target/linux/imx6/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch @@ -0,0 +1,551 @@ +From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001 +From: Robert Jones +Date: Wed, 8 Jan 2020 07:44:24 -0800 +Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support + +The Gateworks GW5912 is an IMX6 SoC based single board computer with: + - IMX6Q or IMX6DL + - 32bit DDR3 DRAM + - GbE RJ45 front-panel + - 4x miniPCIe socket with PCI Gen2, USB2 + - 1x miniPCIe socket with PCI Gen2, USB2, mSATA + - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine + - 10V to 60V DC input barrel jack + - 3axis accelerometer (lis2de12) + - GPS (ublox ZOE-M8Q) + - bi-color front-panel LED + - 256MB NAND boot device + - nanoSIM/microSD socket (with UHS-I support) + - user pushbutton + - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) + - CAN Bus transceiver (mcp2562) + - RS232 transceiver (1x UART with flow-control or 2x UART (build option) + - off-board SPI connector (1x chip-select) + +Signed-off-by: Robert Jones +Reviewed-by: Tim Harvey +Signed-off-by: Shawn Guo +--- + arch/arm/boot/dts/Makefile | 2 + + arch/arm/boot/dts/imx6dl-gw5912.dts | 13 + + arch/arm/boot/dts/imx6q-gw5912.dts | 13 + + arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++ + 4 files changed, 489 insertions(+) + create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts + create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ + imx6dl-gw5910.dtb \ ++ imx6dl-gw5912.dtb \ + imx6dl-gw5913.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ +@@ -494,6 +495,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ + imx6q-gw5910.dtb \ ++ imx6q-gw5912.dtb \ + imx6q-gw5913.dtb \ + imx6q-h100.dtb \ + imx6q-hummingboard.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw5912.dts +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw5912.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912"; ++ compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw5912.dts +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++/dts-v1/; ++#include "imx6q.dtsi" ++#include "imx6qdl-gw5912.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5912"; ++ compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +@@ -0,0 +1,461 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2019 Gateworks Corporation ++ */ ++ ++#include ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ led0 = &led0; ++ led1 = &led1; ++ led2 = &led2; ++ nand = &gpmi; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ }; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_leds>; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ ++ led2: user3 { ++ label = "user3"; ++ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory@10000000 { ++ device_type = "memory"; ++ reg = <0x10000000 0x40000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pps>; ++ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_vbus: regulator-5p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&can1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan1>; ++ status = "okay"; ++}; ++ ++&ecspi2 { ++ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi2>; ++ status = "okay"; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ gpio@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ rtc@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++ ++ accel@19 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_accel>; ++ compatible = "st,lis2de12"; ++ reg = <0x19>; ++ st,drdy-int-pin = <1>; ++ interrupt-parent = <&gpio7>; ++ interrupts = <13 0>; ++ interrupt-names = "INT1"; ++ }; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie>; ++ reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pwm1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ ++ status = "disabled"; ++}; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ ++ status = "disabled"; ++}; ++ ++&pwm3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ ++ status = "disabled"; ++}; ++ ++&pwm4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ ++ status = "disabled"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg>; ++ disable-over-current; ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_vbus>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc3>; ++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; ++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; ++ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <®_3p3v>; ++ no-1-8-v; /* firmware will remove if board revision supports */ ++ status = "okay"; ++}; ++ ++&wdog1 { ++ status = "disabled"; ++}; ++ ++&wdog2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wdog>; ++ fsl,ext-reset-output; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl_accel: accelmuxgrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_enet: enetgrp { ++ fsl,pins = < ++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 ++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 ++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 ++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 ++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 ++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 ++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 ++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 ++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 ++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 ++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 ++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 ++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 ++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 ++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_ecspi2: escpi2grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 ++ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 ++ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 ++ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 ++ >; ++ }; ++ ++ pinctrl_flexcan1: flexcan1grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 ++ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 ++ >; ++ }; ++ ++ pinctrl_gpio_leds: gpioledsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 ++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_gpmi_nand: gpminandgrp { ++ fsl,pins = < ++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 ++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 ++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 ++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 ++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 ++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 ++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 ++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 ++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 ++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 ++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 ++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 ++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 ++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 ++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 ++ >; ++ }; ++ ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 ++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 ++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 ++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 ++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ++ >; ++ }; ++ ++ pinctrl_pcie: pciegrp { ++ fsl,pins = < ++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 ++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 ++ >; ++ }; ++ ++ pinctrl_pps: ppsgrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm1: pwm1grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm2: pwm2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm3: pwm3grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_pwm4: pwm4grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1 ++ >; ++ }; ++ ++ pinctrl_uart5: uart5grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ++ >; ++ }; ++ ++ pinctrl_usbotg: usbotggrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 ++ >; ++ }; ++ ++ pinctrl_usdhc3: usdhc3grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ ++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 ++ >; ++ }; ++ ++ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ ++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 ++ >; ++ }; ++ ++ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ ++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 ++ >; ++ }; ++ ++ pinctrl_wdog: wdoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 ++ >; ++ }; ++}; diff --git a/target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch b/target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch new file mode 100644 index 0000000000..f05c1f1ec1 --- /dev/null +++ b/target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch @@ -0,0 +1,68 @@ +From 62e7f0b553038e3a1a1b2b067dd1fbdacd634e37 Mon Sep 17 00:00:00 2001 +From: Robert Jones +Date: Fri, 14 Feb 2020 13:02:41 -0800 +Subject: [PATCH] ARM: dts: imx6qdl-gw553x: add lsm9ds1 iio imu/magn support + +Add one node for the accel/gyro i2c device and another for the separate +magnetometer device in the lsm9ds1. + +Signed-off-by: Robert Jones +Signed-off-by: Shawn Guo +--- + arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +@@ -173,6 +173,25 @@ + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + ++ magn@1c { ++ compatible = "st,lsm9ds1-magn"; ++ reg = <0x1c>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_mag>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <2 IRQ_TYPE_EDGE_RISING>; ++ }; ++ ++ imu@6a { ++ compatible = "st,lsm9ds1-imu"; ++ reg = <0x6a>; ++ st,drdy-int-pin = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_imu>; ++ interrupt-parent = <&gpio7>; ++ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; +@@ -426,6 +445,12 @@ + >; + }; + ++ pinctrl_imu: imugrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 ++ >; ++ }; ++ + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 +@@ -449,6 +474,12 @@ + >; + }; + ++ pinctrl_mag: maggrp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 ++ >; ++ }; ++ + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 diff --git a/target/linux/imx6/patches-5.4/100-bootargs.patch b/target/linux/imx6/patches-5.4/100-bootargs.patch new file mode 100644 index 0000000000..cf63a3bdb1 --- /dev/null +++ b/target/linux/imx6/patches-5.4/100-bootargs.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/imx6dl-wandboard.dts ++++ b/arch/arm/boot/dts/imx6dl-wandboard.dts +@@ -16,4 +16,8 @@ + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; ++ ++ chosen { ++ bootargs = "console=ttymxc0,115200"; ++ }; + }; diff --git a/target/linux/imx6/patches-5.4/301-apalis-ixora-dts-leds.patch b/target/linux/imx6/patches-5.4/301-apalis-ixora-dts-leds.patch new file mode 100644 index 0000000000..bae9df1734 --- /dev/null +++ b/target/linux/imx6/patches-5.4/301-apalis-ixora-dts-leds.patch @@ -0,0 +1,86 @@ +arm: dts: apalis-ixora: Add status LEDs aliases + +Signed-off-by: Petr Štetiar + +--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts ++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts +@@ -60,6 +60,10 @@ + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; ++ led-boot = &led_boot; ++ led-failsafe = &led_failsafe; ++ led-running = &led_running; ++ led-upgrade = &led_upgrade; + }; + + chosen { +@@ -127,22 +131,22 @@ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + +- led4-green { ++ led_running: led4-green { + label = "LED_4_GREEN"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + +- led4-red { ++ led_upgrade: led4-red { + label = "LED_4_RED"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + +- led5-green { ++ led_boot: led5-green { + label = "LED_5_GREEN"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + +- led5-red { ++ led_failsafe: led5-red { + label = "LED_5_RED"; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + }; +--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts ++++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +@@ -61,6 +61,10 @@ + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; ++ led-boot = &led_boot; ++ led-failsafe = &led_failsafe; ++ led-running = &led_running; ++ led-upgrade = &led_upgrade; + }; + + chosen { +@@ -128,22 +132,22 @@ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + +- led4-green { ++ led_running: led4-green { + label = "LED_4_GREEN"; +- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + +- led4-red { ++ led_upgrade: led4-red { + label = "LED_4_RED"; +- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + +- led5-green { ++ led_boot: led5-green { + label = "LED_5_GREEN"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + +- led5-red { ++ led_failsafe: led5-red { + label = "LED_5_RED"; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + }; diff --git a/target/linux/imx6/patches-5.4/302-apalis-ixora-dts-reset-button.patch b/target/linux/imx6/patches-5.4/302-apalis-ixora-dts-reset-button.patch new file mode 100644 index 0000000000..f5afb66371 --- /dev/null +++ b/target/linux/imx6/patches-5.4/302-apalis-ixora-dts-reset-button.patch @@ -0,0 +1,76 @@ +arm: dts: apalis-ixora: Add switch3 as reset button + +Signed-off-by: Petr Štetiar + +--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts ++++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +@@ -74,7 +74,7 @@ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; ++ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; + + wakeup { + label = "Wake-Up"; +@@ -83,6 +83,13 @@ + debounce-interval = <10>; + wakeup-source; + }; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <10>; ++ }; + }; + + lcd_display: disp0 { +@@ -298,4 +305,10 @@ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; ++ ++ pinctrl_switch3_ixora: switch3ixora { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 ++ >; ++ }; + }; +--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts ++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts +@@ -73,7 +73,7 @@ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gpio_keys>; ++ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>; + + wakeup { + label = "Wake-Up"; +@@ -82,6 +82,13 @@ + debounce-interval = <10>; + wakeup-source; + }; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <10>; ++ }; + }; + + lcd_display: disp0 { +@@ -299,4 +306,10 @@ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; ++ ++ pinctrl_switch3_ixora: switch3ixora { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 ++ >; ++ }; + }; diff --git a/target/linux/kirkwood/Makefile b/target/linux/kirkwood/Makefile index 3eac246a42..a834549208 100644 --- a/target/linux/kirkwood/Makefile +++ b/target/linux/kirkwood/Makefile @@ -13,7 +13,8 @@ FEATURES:=usb nand squashfs ramdisk CPU_TYPE:=xscale MAINTAINER:=Luka Perkov -KERNEL_PATCHVER:=4.14 +KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/kirkwood/base-files/etc/init.d/hwmon_fancontrol b/target/linux/kirkwood/base-files/etc/init.d/hwmon_fancontrol index 0adc5d0726..a0e3de062b 100755 --- a/target/linux/kirkwood/base-files/etc/init.d/hwmon_fancontrol +++ b/target/linux/kirkwood/base-files/etc/init.d/hwmon_fancontrol @@ -1,23 +1,22 @@ #!/bin/sh /etc/rc.common START=98 + boot() { -. /lib/functions.sh + # configuring (lm85/lm63) onboard temp/fan controller to run the fan on its own + # for more information, please read https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface -#configuring (lm85/lm63) onboard temp/fan controller to run the fan on its own -#for more information, please read https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface - -case $(board_name) in -zyxel,nsa310b) - path_to_hwmon='/sys/devices/platform/ocp@f1000000/f1011000.i2c/i2c-0/0-002e/hwmon/hwmon0' - echo 2 > "$path_to_hwmon/pwm1_enable" # fan is on pwm1 - echo 1 > "$path_to_hwmon/pwm1_auto_channels" # temp1 is the only one that changes - echo 23000 > "$path_to_hwmon/temp1_auto_temp_min" - echo 43000 > "$path_to_hwmon/temp1_auto_temp_max" # next step is 49600 millicelsius, or 50 celsius, 43 celsius is better - ;; -iom,ix2-200) - path_to_hwmon='/sys/class/hwmon/hwmon0' - echo 2 > "$path_to_hwmon/pwm1_enable" # fan is on pwm1 - ;; -esac + case $(board_name) in + iom,ix2-200) + path_to_hwmon='/sys/class/hwmon/hwmon0' + echo 2 > "$path_to_hwmon/pwm1_enable" # fan is on pwm1 + ;; + zyxel,nsa310b) + path_to_hwmon='/sys/devices/platform/ocp@f1000000/f1011000.i2c/i2c-0/0-002e/hwmon/hwmon0' + echo 2 > "$path_to_hwmon/pwm1_enable" # fan is on pwm1 + echo 1 > "$path_to_hwmon/pwm1_auto_channels" # temp1 is the only one that changes + echo 23000 > "$path_to_hwmon/temp1_auto_temp_min" + echo 43000 > "$path_to_hwmon/temp1_auto_temp_max" # next step is 49600 millicelsius, or 50 celsius, 43 celsius is better + ;; + esac } diff --git a/target/linux/kirkwood/config-4.14 b/target/linux/kirkwood/config-4.14 index 95c01d7500..9481d0a3cf 100644 --- a/target/linux/kirkwood/config-4.14 +++ b/target/linux/kirkwood/config-4.14 @@ -199,8 +199,6 @@ CONFIG_KIRKWOOD_THERMAL=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_NETXBIG=y CONFIG_LEDS_NS2=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LIBFDT=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y @@ -291,6 +289,7 @@ CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_MC146818_LIB=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_SATA_MV=y +CONFIG_SATA_PMP=y # CONFIG_SCHED_INFO is not set CONFIG_SCSI=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y diff --git a/target/linux/kirkwood/config-4.19 b/target/linux/kirkwood/config-4.19 index 2cc45afb2c..d7ea9e9eef 100644 --- a/target/linux/kirkwood/config-4.19 +++ b/target/linux/kirkwood/config-4.19 @@ -195,8 +195,6 @@ CONFIG_KIRKWOOD_THERMAL=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_NETXBIG=y CONFIG_LEDS_NS2=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LZO_COMPRESS=y @@ -289,6 +287,7 @@ CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_MC146818_LIB=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_SATA_MV=y +CONFIG_SATA_PMP=y CONFIG_SCSI=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_FSL=y diff --git a/target/linux/kirkwood/config-5.4 b/target/linux/kirkwood/config-5.4 new file mode 100644 index 0000000000..e149631f0e --- /dev/null +++ b/target/linux/kirkwood/config-5.4 @@ -0,0 +1,359 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_LIBATA_LEDS=y +CONFIG_ARM=y +# CONFIG_ARMADA_37XX_WATCHDOG is not set +# CONFIG_ARMADA_THERMAL is not set +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_THUMB is not set +CONFIG_ARM_UNWIND=y +CONFIG_ATA=y +CONFIG_ATAGS=y +CONFIG_ATA_LEDS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FEROCEON=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEV_MARVELL_CESA=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART0_ALTERNATE=y +# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xf1012000 +CONFIG_DEBUG_UART_VIRT=0xfed12000 +CONFIG_DEBUG_UNCOMPRESS=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DLCI is not set +CONFIG_DMA_REMAP=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +# CONFIG_EARLY_PRINTK is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXT4_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FORCE_PCI=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OMAP=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_PXA is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KIRKWOOD_CLK=y +CONFIG_KIRKWOOD_THERMAL=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_NETXBIG=y +CONFIG_LEDS_NS2=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_KIRKWOOD=y +CONFIG_MACH_MVEBU_ANY=y +CONFIG_MANGLE_BOOTARGS=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_MVSDIO=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_MARVELL is not set +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MV643XX_ETH=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +# CONFIG_MVNETA is not set +# CONFIG_MVPP2 is not set +CONFIG_MVSW61XX_PHY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NLS=y +CONFIG_NVMEM=y +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_ORION_IRQCHIP=y +CONFIG_ORION_TIMER=y +CONFIG_ORION_WATCHDOG=y +CONFIG_OUTER_CACHE=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_BRIDGE_EMUL=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_PHY_MVEBU_A3700_UTMI is not set +# CONFIG_PHY_MVEBU_A38X_COMPHY is not set +CONFIG_PHY_MVEBU_SATA=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_KIRKWOOD=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PLAT_ORION=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +# CONFIG_POWER_RESET_QNAP is not set +CONFIG_POWER_SUPPLY=y +CONFIG_RATIONAL=y +CONFIG_REFCOUNT_FULL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_SATA_MV=y +CONFIG_SATA_PMP=y +CONFIG_SCSI=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_MVEBU_UART is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_ARMADA_3700 is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRAM=y +CONFIG_SRAM_EXEC=y +CONFIG_SRCU=y +CONFIG_SWCONFIG=y +CONFIG_SWPHY=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_ZSTD is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_ORION=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_LED_TRIG=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-goflexhome.dts b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-goflexhome.dts new file mode 100644 index 0000000000..af20cf9e2c --- /dev/null +++ b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-goflexhome.dts @@ -0,0 +1,124 @@ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Seagate GoFlex Home"; + compatible = "seagate,goflexhome", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + aliases { + led-boot = &led_health; + led-failsafe = &led_fault; + led-running = &led_health; + led-upgrade = &led_fault; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_white: pmx-led-white { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_led_green: pmx-led_green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_orange: pmx-led-orange { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "ok"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + }; + gpio-leds { + compatible = "gpio-leds"; + + led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + misc { + label = "status:white:misc"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + chip-delay = <40>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "ubi"; + reg = <0x100000 0x0ff00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-linksys-audi.dts b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-linksys-audi.dts new file mode 100644 index 0000000000..004ce10219 --- /dev/null +++ b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-linksys-audi.dts @@ -0,0 +1,250 @@ +/* + * kirkwood-linksys-audi.dts - Device Tree file for Linksys EA3500 + * + * (c) 2013 Jonas Gorski + * (c) 2013 Deutsche Telekom Innovation Laboratories + * (c) 2014 Luka Perkov + * (c) 2014 Dan Walters + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Linksys Audi (EA3500)"; + compatible = "linksys,audi", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; + pinctrl-names = "default"; + + wps { + label = "WPS Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_green_power >; + pinctrl-names = "default"; + + led_power: power { + label = "audi:green:power"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mvsw61xx { + compatible = "marvell,88e6171"; + status = "okay"; + reg = <0x10>; + + mii-bus = <&mdio>; + cpu-port-0 = <5>; + cpu-port-1 = <6>; + is-indirect; + }; + + dsa { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; + + switch@16,0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <16 0>; /* MDIO address 16, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "ethernet1"; + }; + + port@1 { + reg = <1>; + label = "ethernet2"; + }; + + port@2 { + reg = <2>; + label = "ethernet3"; + }; + + port@3 { + reg = <3>; + label = "ethernet4"; + }; + + port@4 { + reg = <4>; + label = "internet"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&pinctrl { + pmx_led_green_power: pmx-led-green-power { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u_env"; + reg = <0x80000 0x4000>; + }; + + partition@84000 { + label = "s_env"; + reg = <0x84000 0x4000>; + }; + + partition@200000 { + label = "kernel1"; + reg = <0x200000 0x290000>; + }; + + partition@490000 { + label = "rootfs1"; + reg = <0x490000 0x1170000>; + }; + + partition@1600000 { + label = "kernel2"; + reg = <0x1600000 0x290000>; + }; + + partition@1890000 { + label = "rootfs2"; + reg = <0x1890000 0x1170000>; + }; + + partition@2a00000 { + label = "syscfg"; + reg = <0x2a00000 0x1600000>; + }; + + partition@88000 { + label = "unused"; + reg = <0x88000 0x178000>; + }; + + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. + */ +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* eth1 is connected to the switch at port 6. However DSA only supports a + * single CPU port. Upstream uses DSA so they disable this port to avoid confusion. + */ +ð1 { + status = "okay"; + ethernet1-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* There is no battery on the board, so the RTC does not keep + * time when there is no power, making it useless. + */ +&rtc { + status = "disabled"; +}; diff --git a/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-nsa310b.dts b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-nsa310b.dts new file mode 100644 index 0000000000..a83a55af07 --- /dev/null +++ b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-nsa310b.dts @@ -0,0 +1,132 @@ +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/* + * There are at least two different NSA310 designs. This variant has + * a red/green USB Led (same as nsa310) and a lm85 temp/fan controller. + */ + +/ { + model = "ZyXEL NSA310b"; + compatible = "zyxel,nsa310b", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + aliases { + led-boot = &led_green_sys; + led-failsafe = &led_red_sys; + led-running = &led_green_sys; + led-upgrade = &led_red_sys; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_led_esata_green: pmx-led-esata-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_esata_red: pmx-led-esata-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_led_usb_red: pmx-led-usb-red { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_red: pmx-led-sys-red { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_green: pmx-led-hdd-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_red: pmx-led-hdd-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + }; + + i2c@11000 { + status = "okay"; + + lm85: lm85@2e { + compatible = "national,lm85"; + reg = <0x2e>; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_green_sys: green-sys { + label = "nsa310:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + led_red_sys: red-sys { + label = "nsa310:red:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd { + label = "nsa310:green:hdd"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd { + label = "nsa310:red:hdd"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-esata { + label = "nsa310:green:esata"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-esata { + label = "nsa310:red:esata"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa310:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + red-usb { + label = "nsa310:red:usb"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa310:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa310:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-on100.dts b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-on100.dts new file mode 100644 index 0000000000..9296c3fc71 --- /dev/null +++ b/target/linux/kirkwood/files-4.14/arch/arm/boot/dts/kirkwood-on100.dts @@ -0,0 +1,165 @@ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Cisco Systems ON100"; + compatible = "cisco,on100", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + aliases { + led-boot = &led_health_green; + led-failsafe = &led_health_red; + led-running = &led_health_green; + led-upgrade = &led_health_red; + serial0 = &uart0; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset>; + pinctrl-names = "default"; + + button@1 { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g >; + pinctrl-names = "default"; + + led_health_green: health_green { + label = "on100:green:health"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_health_red: health_red { + label = "on100:red:health"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + health2_green { + label = "on100:green:health2"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + + health2_red { + label = "on100:red:health2"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + phy-connection-type = "rgmii-id"; + }; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + phy-connection-type = "rgmii-id"; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000a0000>; + read-only; + }; + + partition@a0000 { + label = "u-boot environment"; + reg = <0x000a0000 0x00020000>; + read-only; + }; + + partition@c0000 { + label = "kernel"; + reg = <0x000c0000 0x00540000>; + }; + + partition@600000 { + label = "ubi"; + reg = <0x00600000 0x1fa00000>; + }; +}; + +&pinctrl { + pmx_led_health_r: pmx-led-health-r { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_led_health_g: pmx-led-health-g { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_led_health2_r: pmx-led-health2-r { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_led_health2_g: pmx-led-health2-g { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-led-reset { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; +}; + +&sdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-goflexhome.dts b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-goflexhome.dts new file mode 100644 index 0000000000..b0b69b46cd --- /dev/null +++ b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-goflexhome.dts @@ -0,0 +1,135 @@ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Seagate GoFlex Home"; + compatible = "seagate,goflexhome", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + aliases { + led-boot = &led_health; + led-failsafe = &led_fault; + led-running = &led_health; + led-upgrade = &led_fault; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_white: pmx-led-white { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_led_green: pmx-led_green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_orange: pmx-led-orange { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + misc { + label = "status:white:misc"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + + chip-delay = <40>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "ubi"; + reg = <0x0100000 0xff00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-linksys-audi.dts b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-linksys-audi.dts new file mode 100644 index 0000000000..eff9102d33 --- /dev/null +++ b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-linksys-audi.dts @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-linksys-audi.dts - Device Tree file for Linksys EA3500 + * + * (c) 2013 Jonas Gorski + * (c) 2013 Deutsche Telekom Innovation Laboratories + * (c) 2014 Luka Perkov + * (c) 2014 Dan Walters + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Linksys Audi (EA3500)"; + compatible = "linksys,audi", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&pmx_btn_wps &pmx_btn_reset>; + pinctrl-names = "default"; + + wps { + label = "WPS Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&pmx_led_green_power>; + pinctrl-names = "default"; + + led_power: power { + label = "audi:green:power"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mvsw61xx { + compatible = "marvell,88e6171"; + status = "okay"; + reg = <0x10>; + + mii-bus = <&mdio>; + cpu-port-0 = <5>; + cpu-port-1 = <6>; + is-indirect; + }; +}; + +&pinctrl { + pmx_led_green_power: pmx-led-green-power { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u_env"; + reg = <0x80000 0x4000>; + }; + + partition@84000 { + label = "s_env"; + reg = <0x84000 0x4000>; + }; + + partition@200000 { + label = "kernel1"; + reg = <0x200000 0x290000>; + }; + + partition@490000 { + label = "rootfs1"; + reg = <0x490000 0x1170000>; + }; + + partition@1600000 { + label = "kernel2"; + reg = <0x1600000 0x290000>; + }; + + partition@1890000 { + label = "rootfs2"; + reg = <0x1890000 0x1170000>; + }; + + partition@2a00000 { + label = "syscfg"; + reg = <0x2a00000 0x1600000>; + }; + + partition@88000 { + label = "unused"; + reg = <0x88000 0x178000>; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. + */ +ð0 { + status = "okay"; + + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* eth1 is connected to the switch at port 6. However DSA only supports a + * single CPU port. Upstream uses DSA so they disable this port to avoid confusion. + */ +ð1 { + status = "okay"; + + ethernet1-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* There is no battery on the board, so the RTC does not keep + * time when there is no power, making it useless. + */ +&rtc { + status = "disabled"; +}; diff --git a/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-nsa310b.dts b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-nsa310b.dts new file mode 100644 index 0000000000..10b119eb01 --- /dev/null +++ b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-nsa310b.dts @@ -0,0 +1,141 @@ +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/* + * There are at least two different NSA310 designs. This variant has + * a red/green USB Led (same as nsa310) and a lm85 temp/fan controller. + */ + +/ { + model = "ZyXEL NSA310b"; + compatible = "zyxel,nsa310b", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + aliases { + led-boot = &led_green_sys; + led-failsafe = &led_red_sys; + led-running = &led_green_sys; + led-upgrade = &led_red_sys; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_led_esata_green: pmx-led-esata-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_esata_red: pmx-led-esata-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_led_usb_red: pmx-led-usb-red { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_red: pmx-led-sys-red { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_green: pmx-led-hdd-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_red: pmx-led-hdd-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + }; + + i2c@11000 { + status = "okay"; + + lm85: lm85@2e { + compatible = "national,lm85"; + reg = <0x2e>; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_green_sys: green-sys { + label = "nsa310:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red_sys: red-sys { + label = "nsa310:red:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + green-hdd { + label = "nsa310:green:hdd"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + red-hdd { + label = "nsa310:red:hdd"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + green-esata { + label = "nsa310:green:esata"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + + red-esata { + label = "nsa310:red:esata"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + + green-usb { + label = "nsa310:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + + red-usb { + label = "nsa310:red:usb"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + + green-copy { + label = "nsa310:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + red-copy { + label = "nsa310:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-on100.dts b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-on100.dts new file mode 100644 index 0000000000..5ae66ede2f --- /dev/null +++ b/target/linux/kirkwood/files-4.19/arch/arm/boot/dts/kirkwood-on100.dts @@ -0,0 +1,165 @@ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Cisco Systems ON100"; + compatible = "cisco,on100", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + aliases { + led-boot = &led_health_green; + led-failsafe = &led_health_red; + led-running = &led_health_green; + led-upgrade = &led_health_red; + serial0 = &uart0; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&pmx_btn_reset>; + pinctrl-names = "default"; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&pmx_led_health_red &pmx_led_health_green>; + pinctrl-names = "default"; + + led_health_green: health-green { + label = "on100:green:health"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_health_red: health-red { + label = "on100:red:health"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + health2-green { + label = "on100:green:health2"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + + health2-red { + label = "on100:red:health2"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + phy-connection-type = "rgmii-id"; + }; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + phy-connection-type = "rgmii-id"; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000a0000>; + read-only; + }; + + partition@a0000 { + label = "u-boot environment"; + reg = <0x000a0000 0x00020000>; + read-only; + }; + + partition@c0000 { + label = "kernel"; + reg = <0x000c0000 0x00540000>; + }; + + partition@600000 { + label = "ubi"; + reg = <0x00600000 0x1fa00000>; + }; +}; + +&pinctrl { + pmx_led_health_red: pmx-led-health-red { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_led_health_green: pmx-led-health-green { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_led_health2_red: pmx-led-health2-red { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_led_health2_green: pmx-led-health2-green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; +}; + +&sdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-goflexhome.dts b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-goflexhome.dts new file mode 100644 index 0000000000..b0b69b46cd --- /dev/null +++ b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-goflexhome.dts @@ -0,0 +1,135 @@ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Seagate GoFlex Home"; + compatible = "seagate,goflexhome", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + aliases { + led-boot = &led_health; + led-failsafe = &led_fault; + led-running = &led_health; + led-upgrade = &led_fault; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_white: pmx-led-white { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_led_green: pmx-led_green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_orange: pmx-led-orange { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + misc { + label = "status:white:misc"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + + chip-delay = <40>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "ubi"; + reg = <0x0100000 0xff00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-linksys-audi.dts b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-linksys-audi.dts new file mode 100644 index 0000000000..eff9102d33 --- /dev/null +++ b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-linksys-audi.dts @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * kirkwood-linksys-audi.dts - Device Tree file for Linksys EA3500 + * + * (c) 2013 Jonas Gorski + * (c) 2013 Deutsche Telekom Innovation Laboratories + * (c) 2014 Luka Perkov + * (c) 2014 Dan Walters + * + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Linksys Audi (EA3500)"; + compatible = "linksys,audi", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&pmx_btn_wps &pmx_btn_reset>; + pinctrl-names = "default"; + + wps { + label = "WPS Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&pmx_led_green_power>; + pinctrl-names = "default"; + + led_power: power { + label = "audi:green:power"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mvsw61xx { + compatible = "marvell,88e6171"; + status = "okay"; + reg = <0x10>; + + mii-bus = <&mdio>; + cpu-port-0 = <5>; + cpu-port-1 = <6>; + is-indirect; + }; +}; + +&pinctrl { + pmx_led_green_power: pmx-led-green-power { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u_env"; + reg = <0x80000 0x4000>; + }; + + partition@84000 { + label = "s_env"; + reg = <0x84000 0x4000>; + }; + + partition@200000 { + label = "kernel1"; + reg = <0x200000 0x290000>; + }; + + partition@490000 { + label = "rootfs1"; + reg = <0x490000 0x1170000>; + }; + + partition@1600000 { + label = "kernel2"; + reg = <0x1600000 0x290000>; + }; + + partition@1890000 { + label = "rootfs2"; + reg = <0x1890000 0x1170000>; + }; + + partition@2a00000 { + label = "syscfg"; + reg = <0x2a00000 0x1600000>; + }; + + partition@88000 { + label = "unused"; + reg = <0x88000 0x178000>; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. + */ +ð0 { + status = "okay"; + + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* eth1 is connected to the switch at port 6. However DSA only supports a + * single CPU port. Upstream uses DSA so they disable this port to avoid confusion. + */ +ð1 { + status = "okay"; + + ethernet1-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* There is no battery on the board, so the RTC does not keep + * time when there is no power, making it useless. + */ +&rtc { + status = "disabled"; +}; diff --git a/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-nsa310b.dts b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-nsa310b.dts new file mode 100644 index 0000000000..10b119eb01 --- /dev/null +++ b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-nsa310b.dts @@ -0,0 +1,141 @@ +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/* + * There are at least two different NSA310 designs. This variant has + * a red/green USB Led (same as nsa310) and a lm85 temp/fan controller. + */ + +/ { + model = "ZyXEL NSA310b"; + compatible = "zyxel,nsa310b", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + aliases { + led-boot = &led_green_sys; + led-failsafe = &led_red_sys; + led-running = &led_green_sys; + led-upgrade = &led_red_sys; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_led_esata_green: pmx-led-esata-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_esata_red: pmx-led-esata-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_led_usb_red: pmx-led-usb-red { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_red: pmx-led-sys-red { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_green: pmx-led-hdd-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_red: pmx-led-hdd-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + }; + + i2c@11000 { + status = "okay"; + + lm85: lm85@2e { + compatible = "national,lm85"; + reg = <0x2e>; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_green_sys: green-sys { + label = "nsa310:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red_sys: red-sys { + label = "nsa310:red:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + green-hdd { + label = "nsa310:green:hdd"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + red-hdd { + label = "nsa310:red:hdd"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + green-esata { + label = "nsa310:green:esata"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + + red-esata { + label = "nsa310:red:esata"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + + green-usb { + label = "nsa310:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + + red-usb { + label = "nsa310:red:usb"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + + green-copy { + label = "nsa310:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + red-copy { + label = "nsa310:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-on100.dts b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-on100.dts new file mode 100644 index 0000000000..5ae66ede2f --- /dev/null +++ b/target/linux/kirkwood/files-5.4/arch/arm/boot/dts/kirkwood-on100.dts @@ -0,0 +1,165 @@ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Cisco Systems ON100"; + compatible = "cisco,on100", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + aliases { + led-boot = &led_health_green; + led-failsafe = &led_health_red; + led-running = &led_health_green; + led-upgrade = &led_health_red; + serial0 = &uart0; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&pmx_btn_reset>; + pinctrl-names = "default"; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&pmx_led_health_red &pmx_led_health_green>; + pinctrl-names = "default"; + + led_health_green: health-green { + label = "on100:green:health"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_health_red: health-red { + label = "on100:red:health"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + health2-green { + label = "on100:green:health2"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + + health2-red { + label = "on100:red:health2"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + phy-connection-type = "rgmii-id"; + }; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + phy-connection-type = "rgmii-id"; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000a0000>; + read-only; + }; + + partition@a0000 { + label = "u-boot environment"; + reg = <0x000a0000 0x00020000>; + read-only; + }; + + partition@c0000 { + label = "kernel"; + reg = <0x000c0000 0x00540000>; + }; + + partition@600000 { + label = "ubi"; + reg = <0x00600000 0x1fa00000>; + }; +}; + +&pinctrl { + pmx_led_health_red: pmx-led-health-red { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_led_health_green: pmx-led-health-green { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_led_health2_red: pmx-led-health2-red { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_led_health2_green: pmx-led-health2-green { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; +}; + +&sdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/target/linux/kirkwood/image/Makefile b/target/linux/kirkwood/image/Makefile index 0672ba0374..865122ae19 100644 --- a/target/linux/kirkwood/image/Makefile +++ b/target/linux/kirkwood/image/Makefile @@ -12,6 +12,7 @@ KERNEL_LOADADDR:=0x8000 define Device/Default PROFILES := Default + DEVICE_DTS = $$(if $$(BOARD_NAME),kirkwood-$$(BOARD_NAME),) KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts) KERNEL := kernel-bin | append-dtb | uImage none KERNEL_NAME := zImage @@ -24,15 +25,14 @@ define Device/Default IMAGES := sysupgrade.bin factory.bin IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata IMAGE/factory.bin := append-ubi - SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) + SUPPORTED_DEVICES = $(subst _,$(comma),$(1)) $$(BOARD_NAME) endef define Device/cisco_on100 - DEVICE_TITLE := Cisco Systems ON100 - DEVICE_DTS := kirkwood-on100 - DEVICE_PACKAGES := kmod-i2c-mv64xxx + DEVICE_VENDOR := Cisco Systems + DEVICE_MODEL := ON100 KERNEL_SIZE := 5376k - KERNEL_IN_UBI := 0 + KERNEL_IN_UBI := UBINIZE_OPTS := -E 5 IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi BOARD_NAME := on100 @@ -40,113 +40,112 @@ endef TARGET_DEVICES += cisco_on100 define Device/cloudengines_pogoe02 - DEVICE_TITLE := Cloud Engines Pogoplug E02 - DEVICE_DTS := kirkwood-pogo_e02 + DEVICE_VENDOR := Cloud Engines + DEVICE_MODEL := Pogoplug E02 BOARD_NAME := pogo_e02 - SUPPORTED_DEVICES += pogo_e02 endef TARGET_DEVICES += cloudengines_pogoe02 define Device/cloudengines_pogoplugv4 - DEVICE_TITLE := Cloud Engines Pogoplug V4 + DEVICE_VENDOR := Cloud Engines + DEVICE_MODEL := Pogoplug V4 DEVICE_DTS := kirkwood-pogoplug-series-4 DEVICE_PACKAGES := kmod-usb3 endef TARGET_DEVICES += cloudengines_pogoplugv4 define Device/iom_iconnect-1.1 - DEVICE_TITLE := Iomega Iconnect - DEVICE_DTS := kirkwood-iconnect + DEVICE_VENDOR := Iomega + DEVICE_MODEL := Iconnect BOARD_NAME := iconnect - SUPPORTED_DEVICES += iconnect endef TARGET_DEVICES += iom_iconnect-1.1 -define Device/iom_ix2_200 - DEVICE_TITLE := Iomega StorCenter ix2-200 +define Device/iom_ix2-200 + DEVICE_VENDOR := Iomega + DEVICE_MODEL := StorCenter ix2-200 DEVICE_DTS := kirkwood-iomega_ix2_200 - DEVICE_PACKAGES += kmod-gpio-button-hotplug kmod-i2c-mv64xxx kmod-hwmon-lm63 + DEVICE_PACKAGES := kmod-gpio-button-hotplug kmod-hwmon-lm63 DEVICE_TYPE:=nas PAGESIZE := 512 SUBPAGESIZE := 256 - BLOCKSIZE := 16KiB + BLOCKSIZE := 16k KERNEL_SIZE := 3072k - KERNEL_IN_UBI := 0 - UBINIZE_OPTS := -E 5 - IMAGE_SIZE := 32505856 - IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | check-size $$$$(IMAGE_SIZE) + KERNEL_IN_UBI := + UBINIZE_OPTS := -E 5 + IMAGE_SIZE := 31744k + IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \ + check-size endef -TARGET_DEVICES += iom_ix2_200 +TARGET_DEVICES += iom_ix2-200 define Device/linksys_audi - DEVICE_TITLE := Linksys EA3500 (Audi) + DEVICE_VENDOR := Linksys + DEVICE_MODEL := EA3500 (Audi) DEVICE_PACKAGES := kmod-mwl8k swconfig wpad-basic kmod-gpio-button-hotplug - DEVICE_DTS := kirkwood-linksys-audi + PAGESIZE := 512 + SUBPAGESIZE := 256 + BLOCKSIZE := 16k KERNEL_SIZE := 2624k - KERNEL_IN_UBI := 0 + KERNEL_IN_UBI := UBINIZE_OPTS := -E 5 IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi BOARD_NAME := linksys-audi - SUPPORTED_DEVICES += linksys-audi endef TARGET_DEVICES += linksys_audi define Device/linksys_viper - DEVICE_TITLE := Linksys E4200v2 / EA4500 (Viper) + DEVICE_VENDOR := Linksys + DEVICE_MODEL := E4200v2 / EA4500 (Viper) DEVICE_PACKAGES := kmod-mwl8k swconfig wpad-basic kmod-gpio-button-hotplug - DEVICE_DTS := kirkwood-linksys-viper KERNEL_SIZE := 2688k - KERNEL_IN_UBI := 0 + KERNEL_IN_UBI := UBINIZE_OPTS := -E 5 IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi BOARD_NAME := linksys-viper - SUPPORTED_DEVICES += linksys-viper endef TARGET_DEVICES += linksys_viper define Device/raidsonic_ib-nas62x0 - DEVICE_TITLE := RaidSonic ICY BOX IB-NAS62x0 - DEVICE_DTS := kirkwood-ib62x0 + DEVICE_VENDOR := RaidSonic + DEVICE_MODEL := ICY BOX IB-NAS62x0 BOARD_NAME := ib62x0 - SUPPORTED_DEVICES += ib62x0 endef TARGET_DEVICES += raidsonic_ib-nas62x0 define Device/seagate_dockstar - DEVICE_DTS := kirkwood-dockstar - DEVICE_TITLE := Seagate FreeAgent Dockstar + DEVICE_VENDOR := Seagate + DEVICE_MODEL := FreeAgent Dockstar BOARD_NAME := dockstar - SUPPORTED_DEVICES += dockstar endef TARGET_DEVICES += seagate_dockstar define Device/seagate_goflexnet - DEVICE_TITLE := Seagate GoFlexNet - DEVICE_DTS := kirkwood-goflexnet + DEVICE_VENDOR := Seagate + DEVICE_MODEL := GoFlexNet BOARD_NAME := goflexnet - SUPPORTED_DEVICES += goflexnet endef TARGET_DEVICES += seagate_goflexnet define Device/seagate_goflexhome - DEVICE_TITLE := Seagate GoFlexHome - DEVICE_DTS := kirkwood-goflexhome + DEVICE_VENDOR := Seagate + DEVICE_MODEL := GoFlexHome BOARD_NAME := goflexhome - SUPPORTED_DEVICES += goflexhome endef TARGET_DEVICES += seagate_goflexhome define Device/zyxel_nsa310b - DEVICE_TITLE := ZyXEL NSA310b - DEVICE_DTS := kirkwood-nsa310b + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := NSA310b DEVICE_PACKAGES := kmod-r8169 kmod-gpio-button-hotplug kmod-hwmon-lm85 BOARD_NAME := nsa310b endef TARGET_DEVICES += zyxel_nsa310b define Device/zyxel_nsa325 - DEVICE_TITLE := ZyXEL NSA325 (v1 and v2) - DEVICE_DTS := kirkwood-nsa325 + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := NSA325 + DEVICE_VARIANT := v1/v2 DEVICE_PACKAGES := kmod-gpio-button-hotplug kmod-rtc-pcf8563 kmod-usb3 BOARD_NAME := nsa325 endef diff --git a/target/linux/kirkwood/patches-4.14/100-ib62x0.patch b/target/linux/kirkwood/patches-4.14/100-ib62x0.patch index d1a5aa7d3e..0637c24b63 100644 --- a/target/linux/kirkwood/patches-4.14/100-ib62x0.patch +++ b/target/linux/kirkwood/patches-4.14/100-ib62x0.patch @@ -1,15 +1,38 @@ --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts -@@ -6,7 +6,7 @@ +@@ -6,7 +6,14 @@ / { model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + compatible = "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ ++ aliases { ++ led-boot = &led_green_os; ++ led-failsafe = &led_red_os; ++ led-running = &led_green_os; ++ led-upgrade = &led_red_os; ++ }; memory { device_type = "memory"; -@@ -118,13 +118,13 @@ +@@ -81,12 +88,12 @@ + &pmx_led_usb_transfer>; + pinctrl-names = "default"; + +- green-os { ++ led_green_os: green-os { + label = "ib62x0:green:os"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- red-os { ++ led_red_os: red-os { + label = "ib62x0:red:os"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; +@@ -118,13 +125,13 @@ }; partition@100000 { diff --git a/target/linux/kirkwood/patches-4.14/101-iconnect.patch b/target/linux/kirkwood/patches-4.14/101-iconnect.patch index d2310b80ab..935e2dfcf5 100644 --- a/target/linux/kirkwood/patches-4.14/101-iconnect.patch +++ b/target/linux/kirkwood/patches-4.14/101-iconnect.patch @@ -1,6 +1,20 @@ --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts -@@ -16,8 +16,6 @@ +@@ -8,6 +8,13 @@ + model = "Iomega Iconnect"; + compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power_blue; ++ led-failsafe = &led_power_red; ++ led-running = &led_power_blue; ++ led-upgrade = &led_power_red; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -16,8 +23,6 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; stdout-path = &uart0; @@ -9,7 +23,23 @@ }; ocp@f1000000 { -@@ -146,28 +144,23 @@ +@@ -89,12 +94,12 @@ + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; +- power-blue { ++ led_power_blue: power-blue { + label = "power:blue"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- power-red { ++ led_power_red: power-red { + label = "power:red"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; +@@ -146,28 +151,23 @@ status = "okay"; partition@0 { diff --git a/target/linux/kirkwood/patches-4.14/102-dockstar.patch b/target/linux/kirkwood/patches-4.14/102-dockstar.patch index 7462b93e0c..127f84962c 100644 --- a/target/linux/kirkwood/patches-4.14/102-dockstar.patch +++ b/target/linux/kirkwood/patches-4.14/102-dockstar.patch @@ -1,6 +1,36 @@ --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts -@@ -78,18 +78,22 @@ +@@ -8,6 +8,13 @@ + model = "Seagate FreeAgent Dockstar"; + compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -42,12 +49,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_orange>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -78,18 +85,22 @@ partition@0 { label = "u-boot"; diff --git a/target/linux/kirkwood/patches-4.14/103-iomega-ix2-200.patch b/target/linux/kirkwood/patches-4.14/103-iomega-ix2-200.patch index 9036ead951..9313b4bc3e 100644 --- a/target/linux/kirkwood/patches-4.14/103-iomega-ix2-200.patch +++ b/target/linux/kirkwood/patches-4.14/103-iomega-ix2-200.patch @@ -1,6 +1,40 @@ --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts -@@ -186,18 +186,18 @@ +@@ -8,6 +8,13 @@ + model = "Iomega StorCenter ix2-200"; + compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power; ++ led-failsafe = &led_health; ++ led-running = &led_power; ++ led-upgrade = &led_health; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -127,16 +134,16 @@ + &pmx_led_rebuild &pmx_led_health >; + pinctrl-names = "default"; + +- power_led { ++ led_power: power_led { + label = "status:white:power_led"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; + rebuild_led { + label = "status:white:rebuild_led"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; +- health_led { ++ led_health: health_led { + label = "status:red:health_led"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; +@@ -186,18 +193,18 @@ }; partition@a0000 { @@ -22,7 +56,7 @@ reg = <0x400000 0x1C00000>; }; }; -@@ -211,7 +211,7 @@ +@@ -211,7 +218,7 @@ }; ð0 { diff --git a/target/linux/kirkwood/patches-4.14/104-ea3500.patch b/target/linux/kirkwood/patches-4.14/104-ea3500.patch deleted file mode 100644 index 73bb252a79..0000000000 --- a/target/linux/kirkwood/patches-4.14/104-ea3500.patch +++ /dev/null @@ -1,258 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -250,6 +250,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-linkstation-lswsxl.dtb \ - kirkwood-linkstation-lswvl.dtb \ - kirkwood-linkstation-lswxl.dtb \ -+ kirkwood-linksys-audi.dtb \ - kirkwood-linksys-viper.dtb \ - kirkwood-lschlv2.dtb \ - kirkwood-lsxhl.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-linksys-audi.dts -@@ -0,0 +1,245 @@ -+/* -+ * kirkwood-linksys-audi.dts - Device Tree file for Linksys EA3500 -+ * -+ * (c) 2013 Jonas Gorski -+ * (c) 2013 Deutsche Telekom Innovation Laboratories -+ * (c) 2014 Luka Perkov -+ * (c) 2014 Dan Walters -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+#include "kirkwood.dtsi" -+#include "kirkwood-6282.dtsi" -+ -+/ { -+ model = "Linksys Audi (EA3500)"; -+ compatible = "linksys,audi", "marvell,kirkwood-88f6282", "marvell,kirkwood"; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x4000000>; -+ }; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; -+ pinctrl-names = "default"; -+ -+ wps { -+ label = "WPS Button"; -+ linux,code = ; -+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -+ }; -+ -+ reset { -+ label = "Reset Button"; -+ linux,code = ; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = < &pmx_led_green_power >; -+ pinctrl-names = "default"; -+ -+ green-power { -+ label = "audi:green:power"; -+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ mvsw61xx { -+ compatible = "marvell,88e6171"; -+ status = "okay"; -+ reg = <0x10>; -+ -+ mii-bus = <&mdio>; -+ cpu-port-0 = <5>; -+ cpu-port-1 = <6>; -+ is-indirect; -+ }; -+ -+ dsa { -+ compatible = "marvell,dsa"; -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ dsa,ethernet = <ð0port>; -+ dsa,mii-bus = <&mdio>; -+ -+ switch@16,0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <16 0>; /* MDIO address 16, switch 0 in tree */ -+ -+ port@0 { -+ reg = <0>; -+ label = "ethernet1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "ethernet2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "ethernet3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "ethernet4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "internet"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ }; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmx_led_green_power: pmx-led-green-power { -+ marvell,pins = "mpp7"; -+ marvell,function = "gpo"; -+ }; -+ pmx_btn_wps: pmx-btn-wps { -+ marvell,pins = "mpp47"; -+ marvell,function = "gpio"; -+ }; -+ pmx_btn_reset: pmx-btn-reset { -+ marvell,pins = "mpp48"; -+ marvell,function = "gpio"; -+ }; -+}; -+ -+&nand { -+ status = "okay"; -+ pinctrl-0 = <&pmx_nand>; -+ pinctrl-names = "default"; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "u_env"; -+ reg = <0x80000 0x4000>; -+ }; -+ -+ partition@84000 { -+ label = "s_env"; -+ reg = <0x84000 0x4000>; -+ }; -+ -+ partition@200000 { -+ label = "kernel1"; -+ reg = <0x200000 0x290000>; -+ }; -+ -+ partition@490000 { -+ label = "rootfs1"; -+ reg = <0x490000 0x1170000>; -+ }; -+ -+ partition@1600000 { -+ label = "kernel2"; -+ reg = <0x1600000 0x290000>; -+ }; -+ -+ partition@1890000 { -+ label = "rootfs2"; -+ reg = <0x1890000 0x1170000>; -+ }; -+ -+ partition@2a00000 { -+ label = "syscfg"; -+ reg = <0x2a00000 0x1600000>; -+ }; -+ -+ partition@88000 { -+ label = "unused"; -+ reg = <0x88000 0x178000>; -+ }; -+ -+ }; -+}; -+ -+&pciec { -+ status = "okay"; -+}; -+ -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&mdio { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set -+ * fixed speed and duplex. -+ */ -+ð0 { -+ status = "okay"; -+ ethernet0-port@0 { -+ speed = <1000>; -+ duplex = <1>; -+ }; -+}; -+ -+/* eth1 is connected to the switch at port 6. However DSA only supports a -+ * single CPU port. Upstream uses DSA so they disable this port to avoid confusion. -+ */ -+ð1 { -+ status = "okay"; -+ ethernet1-port@0 { -+ speed = <1000>; -+ duplex = <1>; -+ }; -+}; -+ -+/* There is no battery on the board, so the RTC does not keep -+ * time when there is no power, making it useless. -+ */ -+&rtc { -+ status = "disabled"; -+}; diff --git a/target/linux/kirkwood/patches-4.14/105-ea4500.patch b/target/linux/kirkwood/patches-4.14/105-ea4500.patch index 6cc3de221b..cfa499c911 100644 --- a/target/linux/kirkwood/patches-4.14/105-ea4500.patch +++ b/target/linux/kirkwood/patches-4.14/105-ea4500.patch @@ -1,6 +1,29 @@ --- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts -@@ -69,9 +69,18 @@ +@@ -26,6 +26,10 @@ + }; + + aliases { ++ led-boot = &led_white_health; ++ led-failsafe = &led_white_health; ++ led-running = &led_white_health; ++ led-upgrade = &led_white_health; + serial0 = &uart0; + }; + +@@ -58,9 +62,10 @@ + pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; + pinctrl-names = "default"; + +- white-health { ++ led_white_health: white-health { + label = "viper:white:health"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; + + white-pulse { +@@ -69,9 +74,18 @@ }; }; @@ -21,7 +44,7 @@ compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; -@@ -163,22 +172,22 @@ +@@ -163,22 +177,22 @@ }; partition@200000 { @@ -48,7 +71,7 @@ reg = <0x1EA0000 0x1760000>; }; -@@ -209,53 +218,6 @@ +@@ -209,53 +223,6 @@ &mdio { status = "okay"; @@ -102,7 +125,7 @@ }; &uart0 { -@@ -274,10 +236,14 @@ +@@ -274,10 +241,14 @@ }; /* eth1 is connected to the switch at port 6. However DSA only supports a diff --git a/target/linux/kirkwood/patches-4.14/105-goflexhome.patch b/target/linux/kirkwood/patches-4.14/105-goflexhome.patch deleted file mode 100644 index 8270613ea0..0000000000 --- a/target/linux/kirkwood/patches-4.14/105-goflexhome.patch +++ /dev/null @@ -1,130 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -237,6 +237,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-ds411.dtb \ - kirkwood-ds411j.dtb \ - kirkwood-ds411slim.dtb \ -+ kirkwood-goflexhome.dtb \ - kirkwood-goflexnet.dtb \ - kirkwood-guruplug-server-plus.dtb \ - kirkwood-ib62x0.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-goflexhome.dts -@@ -0,0 +1,117 @@ -+/dts-v1/; -+ -+#include "kirkwood.dtsi" -+#include "kirkwood-6281.dtsi" -+ -+/ { -+ model = "Seagate GoFlex Home"; -+ compatible = "seagate,goflexhome", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x8000000>; -+ }; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; -+ stdout-path = &uart0; -+ }; -+ -+ ocp@f1000000 { -+ pinctrl: pin-controller@10000 { -+ pmx_usb_power_enable: pmx-usb-power-enable { -+ marvell,pins = "mpp29"; -+ marvell,function = "gpio"; -+ }; -+ pmx_led_white: pmx-led-white { -+ marvell,pins = "mpp40"; -+ marvell,function = "gpio"; -+ }; -+ pmx_led_green: pmx-led_green { -+ marvell,pins = "mpp46"; -+ marvell,function = "gpio"; -+ }; -+ pmx_led_orange: pmx-led-orange { -+ marvell,pins = "mpp47"; -+ marvell,function = "gpio"; -+ }; -+ }; -+ serial@12000 { -+ status = "ok"; -+ }; -+ -+ sata@80000 { -+ status = "okay"; -+ nr-ports = <2>; -+ }; -+ -+ }; -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ health { -+ label = "status:green:health"; -+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-on"; -+ }; -+ fault { -+ label = "status:orange:fault"; -+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -+ }; -+ misc { -+ label = "status:white:misc"; -+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "disk-activity"; -+ }; -+ }; -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-0 = <&pmx_usb_power_enable>; -+ pinctrl-names = "default"; -+ -+ usb_power: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "USB Power"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ regulator-always-on; -+ regulator-boot-on; -+ gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; -+ -+&nand { -+ chip-delay = <40>; -+ status = "okay"; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x0000000 0x100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "ubi"; -+ reg = <0x100000 0x0ff00000>; -+ }; -+}; -+ -+&mdio { -+ status = "okay"; -+ -+ ethphy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+}; -+ -+ð0 { -+ status = "okay"; -+ ethernet0-port@0 { -+ phy-handle = <ðphy0>; -+ }; -+}; diff --git a/target/linux/kirkwood/patches-4.14/106-goflexnet.patch b/target/linux/kirkwood/patches-4.14/106-goflexnet.patch index b22176880b..82cf90841e 100644 --- a/target/linux/kirkwood/patches-4.14/106-goflexnet.patch +++ b/target/linux/kirkwood/patches-4.14/106-goflexnet.patch @@ -1,6 +1,36 @@ --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts -@@ -159,18 +159,8 @@ +@@ -8,6 +8,13 @@ + model = "Seagate GoFlex Net"; + compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -85,12 +92,12 @@ + >; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -159,18 +166,8 @@ }; partition@100000 { diff --git a/target/linux/kirkwood/patches-4.14/107-02-nsa310b.patch b/target/linux/kirkwood/patches-4.14/107-02-nsa310b.patch deleted file mode 100644 index eefd78abdb..0000000000 --- a/target/linux/kirkwood/patches-4.14/107-02-nsa310b.patch +++ /dev/null @@ -1,147 +0,0 @@ -kirkwood: add nsa310b dtb, a zyxel nsa310 variant - -add support to a nsa310 variant with red/green usb led -and lm85 temp/fan controller - -Signed-off-by: Alberto Bursi - -NOTE: this patch can be upstreamed as-is, LEDE-specific - nand partitions are set in another patch - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -268,6 +268,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-ns2mini.dtb \ - kirkwood-nsa310.dtb \ - kirkwood-nsa310a.dtb \ -+ kirkwood-nsa310b.dtb \ - kirkwood-nsa320.dtb \ - kirkwood-nsa325.dtb \ - kirkwood-openblocks_a6.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-nsa310b.dts -@@ -0,0 +1,124 @@ -+/dts-v1/; -+ -+#include "kirkwood-nsa3x0-common.dtsi" -+ -+/* -+ * There are at least two different NSA310 designs. This variant has -+ * a red/green USB Led (same as nsa310) and a lm85 temp/fan controller. -+ */ -+ -+/ { -+ model = "ZyXEL NSA310b"; -+ compatible = "zyxel,nsa310b", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x10000000>; -+ }; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+ -+ ocp@f1000000 { -+ pinctrl: pin-controller@10000 { -+ pinctrl-names = "default"; -+ -+ pmx_led_esata_green: pmx-led-esata-green { -+ marvell,pins = "mpp12"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_esata_red: pmx-led-esata-red { -+ marvell,pins = "mpp13"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_usb_green: pmx-led-usb-green { -+ marvell,pins = "mpp15"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_usb_red: pmx-led-usb-red { -+ marvell,pins = "mpp16"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_sys_green: pmx-led-sys-green { -+ marvell,pins = "mpp28"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_sys_red: pmx-led-sys-red { -+ marvell,pins = "mpp29"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_hdd_green: pmx-led-hdd-green { -+ marvell,pins = "mpp41"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_hdd_red: pmx-led-hdd-red { -+ marvell,pins = "mpp42"; -+ marvell,function = "gpio"; -+ }; -+ -+ }; -+ -+ i2c@11000 { -+ status = "okay"; -+ -+ lm85: lm85@2e { -+ compatible = "national,lm85"; -+ reg = <0x2e>; -+ }; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ green-sys { -+ label = "nsa310:green:sys"; -+ gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -+ }; -+ red-sys { -+ label = "nsa310:red:sys"; -+ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; -+ }; -+ green-hdd { -+ label = "nsa310:green:hdd"; -+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ }; -+ red-hdd { -+ label = "nsa310:red:hdd"; -+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; -+ }; -+ green-esata { -+ label = "nsa310:green:esata"; -+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; -+ }; -+ red-esata { -+ label = "nsa310:red:esata"; -+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; -+ }; -+ green-usb { -+ label = "nsa310:green:usb"; -+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; -+ }; -+ red-usb { -+ label = "nsa310:red:usb"; -+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; -+ }; -+ green-copy { -+ label = "nsa310:green:copy"; -+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ }; -+ red-copy { -+ label = "nsa310:red:copy"; -+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/kirkwood/patches-4.14/107-03-nsa325.patch b/target/linux/kirkwood/patches-4.14/107-03-nsa325.patch new file mode 100644 index 0000000000..e6935613e3 --- /dev/null +++ b/target/linux/kirkwood/patches-4.14/107-03-nsa325.patch @@ -0,0 +1,31 @@ +--- a/arch/arm/boot/dts/kirkwood-nsa325.dts ++++ b/arch/arm/boot/dts/kirkwood-nsa325.dts +@@ -18,6 +18,13 @@ + model = "ZyXEL NSA325"; + compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_green_sys; ++ led-failsafe = &led_orange_sys; ++ led-running = &led_green_sys; ++ led-upgrade = &led_orange_sys; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; +@@ -165,11 +172,12 @@ + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + +- green-sys { ++ led_green_sys: green-sys { + label = "nsa325:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; +- orange-sys { ++ led_orange_sys: orange-sys { + label = "nsa325:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; diff --git a/target/linux/kirkwood/patches-4.14/108-on100.patch b/target/linux/kirkwood/patches-4.14/108-on100.patch deleted file mode 100644 index 7856277e40..0000000000 --- a/target/linux/kirkwood/patches-4.14/108-on100.patch +++ /dev/null @@ -1,173 +0,0 @@ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-on100.dts -@@ -0,0 +1,160 @@ -+/dts-v1/; -+ -+#include "kirkwood.dtsi" -+#include "kirkwood-6282.dtsi" -+ -+/ { -+ model = "Cisco Systems ON100"; -+ compatible = "cisco,on100", "marvell,kirkwood-88f6282", "marvell,kirkwood"; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x00000000 0x20000000>; -+ }; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200n8 earlyprintk"; -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-0 = <&pmx_btn_reset>; -+ pinctrl-names = "default"; -+ -+ button@1 { -+ label = "Reset Button"; -+ linux,code = ; -+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g >; -+ pinctrl-names = "default"; -+ -+ health-g { -+ label = "on100:green:health"; -+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; -+ }; -+ -+ health-r { -+ label = "on100:red:health"; -+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ }; -+ -+ health2-g { -+ label = "on100:green:health2"; -+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ health2-r { -+ label = "on100:red:health2"; -+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+ð0 { -+ status = "okay"; -+ -+ ethernet0-port@0 { -+ phy-handle = <ðphy0>; -+ phy-connection-type = "rgmii-id"; -+ }; -+}; -+ -+ð1 { -+ status = "okay"; -+ -+ ethernet1-port@0 { -+ phy-handle = <ðphy1>; -+ phy-connection-type = "rgmii-id"; -+ }; -+}; -+ -+&mdio { -+ status = "okay"; -+ -+ ethphy0: ethernet-phy@0 { -+ /* Marvell 88E1121R */ -+ compatible = "ethernet-phy-id0141.0cb0", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ /* Marvell 88E1121R */ -+ compatible = "ethernet-phy-id0141.0cb0", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ -+&nand { -+ status = "okay"; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x00000000 0x000a0000>; -+ read-only; -+ }; -+ -+ partition@a0000 { -+ label = "u-boot environment"; -+ reg = <0x000a0000 0x00020000>; -+ read-only; -+ }; -+ -+ partition@c0000 { -+ label = "kernel"; -+ reg = <0x000c0000 0x00540000>; -+ }; -+ -+ partition@600000 { -+ label = "ubi"; -+ reg = <0x00600000 0x1fa00000>; -+ }; -+}; -+ -+&pinctrl { -+ pmx_led_health_r: pmx-led-health-r { -+ marvell,pins = "mpp45"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_health_g: pmx-led-health-g { -+ marvell,pins = "mpp44"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_health2_r: pmx-led-health2-r { -+ marvell,pins = "mpp47"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_health2_g: pmx-led-health2-g { -+ marvell,pins = "mpp46"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_btn_reset: pmx-led-reset { -+ marvell,pins = "mpp31"; -+ marvell,function = "gpio"; -+ }; -+}; -+ -+&sdio { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -271,6 +271,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-nsa310b.dtb \ - kirkwood-nsa320.dtb \ - kirkwood-nsa325.dtb \ -+ kirkwood-on100.dtb \ - kirkwood-openblocks_a6.dtb \ - kirkwood-openblocks_a7.dtb \ - kirkwood-openrd-base.dtb \ diff --git a/target/linux/kirkwood/patches-4.14/109-pogoplug_v4.patch b/target/linux/kirkwood/patches-4.14/109-pogoplug_v4.patch index cc72ffb234..60c07b8c76 100644 --- a/target/linux/kirkwood/patches-4.14/109-pogoplug_v4.patch +++ b/target/linux/kirkwood/patches-4.14/109-pogoplug_v4.patch @@ -1,6 +1,19 @@ --- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts +++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts -@@ -24,6 +24,7 @@ +@@ -18,12 +18,20 @@ + compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; }; chosen { @@ -8,7 +21,7 @@ stdout-path = "uart0:115200n8"; }; -@@ -37,8 +38,8 @@ +@@ -37,8 +45,8 @@ eject { debounce_interval = <50>; wakeup-source; @@ -19,7 +32,22 @@ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; }; -@@ -137,29 +138,19 @@ +@@ -48,12 +56,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_red>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "pogoplugv4:green:health"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogoplugv4:red:fault"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; +@@ -137,29 +145,19 @@ #size-cells = <1>; partition@0 { diff --git a/target/linux/kirkwood/patches-4.14/110-pogo_e02.patch b/target/linux/kirkwood/patches-4.14/110-pogo_e02.patch new file mode 100644 index 0000000000..26dbf8a734 --- /dev/null +++ b/target/linux/kirkwood/patches-4.14/110-pogo_e02.patch @@ -0,0 +1,68 @@ +--- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts ++++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts +@@ -22,6 +22,13 @@ + compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -35,12 +42,12 @@ + gpio-leds { + compatible = "gpio-leds"; + +- health { ++ led_health: health { + label = "pogo_e02:green:health"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogo_e02:orange:fault"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; +@@ -97,24 +104,24 @@ + status = "okay"; + + partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; ++ label = "uboot"; ++ reg = <0x0 0xe0000>; + read-only; + }; + +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; ++ partition@e0000 { ++ label = "uboot_env"; ++ reg = <0xe0000 0x20000>; + }; + +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; ++ partition@100000 { ++ label = "second_stage_uboot"; ++ reg = <0x100000 0x100000>; + }; + +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0x5b00000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-4.19/100-ib62x0.patch b/target/linux/kirkwood/patches-4.19/100-ib62x0.patch index d1a5aa7d3e..0637c24b63 100644 --- a/target/linux/kirkwood/patches-4.19/100-ib62x0.patch +++ b/target/linux/kirkwood/patches-4.19/100-ib62x0.patch @@ -1,15 +1,38 @@ --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts -@@ -6,7 +6,7 @@ +@@ -6,7 +6,14 @@ / { model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + compatible = "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ ++ aliases { ++ led-boot = &led_green_os; ++ led-failsafe = &led_red_os; ++ led-running = &led_green_os; ++ led-upgrade = &led_red_os; ++ }; memory { device_type = "memory"; -@@ -118,13 +118,13 @@ +@@ -81,12 +88,12 @@ + &pmx_led_usb_transfer>; + pinctrl-names = "default"; + +- green-os { ++ led_green_os: green-os { + label = "ib62x0:green:os"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- red-os { ++ led_red_os: red-os { + label = "ib62x0:red:os"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; +@@ -118,13 +125,13 @@ }; partition@100000 { diff --git a/target/linux/kirkwood/patches-4.19/101-iconnect.patch b/target/linux/kirkwood/patches-4.19/101-iconnect.patch index d2310b80ab..935e2dfcf5 100644 --- a/target/linux/kirkwood/patches-4.19/101-iconnect.patch +++ b/target/linux/kirkwood/patches-4.19/101-iconnect.patch @@ -1,6 +1,20 @@ --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts -@@ -16,8 +16,6 @@ +@@ -8,6 +8,13 @@ + model = "Iomega Iconnect"; + compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power_blue; ++ led-failsafe = &led_power_red; ++ led-running = &led_power_blue; ++ led-upgrade = &led_power_red; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -16,8 +23,6 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; stdout-path = &uart0; @@ -9,7 +23,23 @@ }; ocp@f1000000 { -@@ -146,28 +144,23 @@ +@@ -89,12 +94,12 @@ + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; +- power-blue { ++ led_power_blue: power-blue { + label = "power:blue"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- power-red { ++ led_power_red: power-red { + label = "power:red"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; +@@ -146,28 +151,23 @@ status = "okay"; partition@0 { diff --git a/target/linux/kirkwood/patches-4.19/102-dockstar.patch b/target/linux/kirkwood/patches-4.19/102-dockstar.patch index 7462b93e0c..127f84962c 100644 --- a/target/linux/kirkwood/patches-4.19/102-dockstar.patch +++ b/target/linux/kirkwood/patches-4.19/102-dockstar.patch @@ -1,6 +1,36 @@ --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts -@@ -78,18 +78,22 @@ +@@ -8,6 +8,13 @@ + model = "Seagate FreeAgent Dockstar"; + compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -42,12 +49,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_orange>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -78,18 +85,22 @@ partition@0 { label = "u-boot"; diff --git a/target/linux/kirkwood/patches-4.19/103-iomega-ix2-200.patch b/target/linux/kirkwood/patches-4.19/103-iomega-ix2-200.patch index 9036ead951..9313b4bc3e 100644 --- a/target/linux/kirkwood/patches-4.19/103-iomega-ix2-200.patch +++ b/target/linux/kirkwood/patches-4.19/103-iomega-ix2-200.patch @@ -1,6 +1,40 @@ --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts -@@ -186,18 +186,18 @@ +@@ -8,6 +8,13 @@ + model = "Iomega StorCenter ix2-200"; + compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power; ++ led-failsafe = &led_health; ++ led-running = &led_power; ++ led-upgrade = &led_health; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -127,16 +134,16 @@ + &pmx_led_rebuild &pmx_led_health >; + pinctrl-names = "default"; + +- power_led { ++ led_power: power_led { + label = "status:white:power_led"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; + rebuild_led { + label = "status:white:rebuild_led"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; +- health_led { ++ led_health: health_led { + label = "status:red:health_led"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; +@@ -186,18 +193,18 @@ }; partition@a0000 { @@ -22,7 +56,7 @@ reg = <0x400000 0x1C00000>; }; }; -@@ -211,7 +211,7 @@ +@@ -211,7 +218,7 @@ }; ð0 { diff --git a/target/linux/kirkwood/patches-4.19/104-ea3500.patch b/target/linux/kirkwood/patches-4.19/104-ea3500.patch deleted file mode 100644 index 45dc670ebc..0000000000 --- a/target/linux/kirkwood/patches-4.19/104-ea3500.patch +++ /dev/null @@ -1,259 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -269,6 +269,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-linkstation-lswsxl.dtb \ - kirkwood-linkstation-lswvl.dtb \ - kirkwood-linkstation-lswxl.dtb \ -+ kirkwood-linksys-audi.dtb \ - kirkwood-linksys-viper.dtb \ - kirkwood-lschlv2.dtb \ - kirkwood-lsxhl.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-linksys-audi.dts -@@ -0,0 +1,246 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * kirkwood-linksys-audi.dts - Device Tree file for Linksys EA3500 -+ * -+ * (c) 2013 Jonas Gorski -+ * (c) 2013 Deutsche Telekom Innovation Laboratories -+ * (c) 2014 Luka Perkov -+ * (c) 2014 Dan Walters -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "kirkwood.dtsi" -+#include "kirkwood-6282.dtsi" -+ -+/ { -+ model = "Linksys Audi (EA3500)"; -+ compatible = "linksys,audi", "marvell,kirkwood-88f6282", "marvell,kirkwood"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x4000000>; -+ }; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; -+ pinctrl-names = "default"; -+ -+ wps { -+ label = "WPS Button"; -+ linux,code = ; -+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -+ }; -+ -+ reset { -+ label = "Reset Button"; -+ linux,code = ; -+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = < &pmx_led_green_power >; -+ pinctrl-names = "default"; -+ -+ green-power { -+ label = "audi:green:power"; -+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ switches { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mvsw61xx@10 { -+ compatible = "marvell,88e6171"; -+ status = "okay"; -+ reg = <0x10>; -+ -+ mii-bus = <&mdio>; -+ cpu-port-0 = <5>; -+ cpu-port-1 = <6>; -+ is-indirect; -+ }; -+ }; -+ -+ dsa { -+ compatible = "marvell,dsa"; -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ dsa,ethernet = <ð0port>; -+ dsa,mii-bus = <&mdio>; -+ -+ switch@16,0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <16 0>; /* MDIO address 16, switch 0 in tree */ -+ -+ port@0 { -+ reg = <0>; -+ label = "ethernet1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "ethernet2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "ethernet3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "ethernet4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "internet"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ }; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmx_led_green_power: pmx-led-green-power { -+ marvell,pins = "mpp7"; -+ marvell,function = "gpo"; -+ }; -+ pmx_btn_wps: pmx-btn-wps { -+ marvell,pins = "mpp47"; -+ marvell,function = "gpio"; -+ }; -+ pmx_btn_reset: pmx-btn-reset { -+ marvell,pins = "mpp48"; -+ marvell,function = "gpio"; -+ }; -+}; -+ -+&nand { -+ status = "okay"; -+ pinctrl-0 = <&pmx_nand>; -+ pinctrl-names = "default"; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "u_env"; -+ reg = <0x80000 0x4000>; -+ }; -+ -+ partition@84000 { -+ label = "s_env"; -+ reg = <0x84000 0x4000>; -+ }; -+ -+ partition@200000 { -+ label = "kernel1"; -+ reg = <0x200000 0x290000>; -+ }; -+ -+ partition@490000 { -+ label = "rootfs1"; -+ reg = <0x490000 0x1170000>; -+ }; -+ -+ partition@1600000 { -+ label = "kernel2"; -+ reg = <0x1600000 0x290000>; -+ }; -+ -+ partition@1890000 { -+ label = "rootfs2"; -+ reg = <0x1890000 0x1170000>; -+ }; -+ -+ partition@2a00000 { -+ label = "syscfg"; -+ reg = <0x2a00000 0x1600000>; -+ }; -+ -+ partition@88000 { -+ label = "unused"; -+ reg = <0x88000 0x178000>; -+ }; -+ -+ }; -+}; -+ -+&pciec { -+ status = "okay"; -+}; -+ -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&mdio { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set -+ * fixed speed and duplex. -+ */ -+ð0 { -+ status = "okay"; -+ ethernet0-port@0 { -+ speed = <1000>; -+ duplex = <1>; -+ }; -+}; -+ -+/* eth1 is connected to the switch at port 6. However DSA only supports a -+ * single CPU port. Upstream uses DSA so they disable this port to avoid confusion. -+ */ -+ð1 { -+ status = "okay"; -+ ethernet1-port@0 { -+ speed = <1000>; -+ duplex = <1>; -+ }; -+}; -+ -+/* There is no battery on the board, so the RTC does not keep -+ * time when there is no power, making it useless. -+ */ -+&rtc { -+ status = "disabled"; -+}; diff --git a/target/linux/kirkwood/patches-4.19/105-ea4500.patch b/target/linux/kirkwood/patches-4.19/105-ea4500.patch index c7c8b38f95..4c3c82bdfd 100644 --- a/target/linux/kirkwood/patches-4.19/105-ea4500.patch +++ b/target/linux/kirkwood/patches-4.19/105-ea4500.patch @@ -1,27 +1,45 @@ --- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts -@@ -67,9 +67,23 @@ +@@ -24,6 +24,10 @@ + }; + + aliases { ++ led-boot = &led_white_health; ++ led-failsafe = &led_white_health; ++ led-running = &led_white_health; ++ led-upgrade = &led_white_health; + serial0 = &uart0; + }; + +@@ -56,9 +60,10 @@ + pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; + pinctrl-names = "default"; + +- white-health { ++ led_white_health: white-health { + label = "viper:white:health"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; + + white-pulse { +@@ -67,9 +72,18 @@ }; }; - dsa { - status = "disabled"; -+ switches { -+ #address-cells = <1>; -+ #size-cells = <0>; - -+ mvsw61xx@10 { -+ compatible = "marvell,88e6171"; -+ status = "okay"; -+ reg = <0x10>; ++ mvsw61xx { ++ compatible = "marvell,88e6171"; ++ status = "okay"; ++ reg = <0x10>; + -+ mii-bus = <&mdio>; -+ cpu-port-0 = <5>; -+ cpu-port-1 = <6>; -+ is-indirect; -+ }; ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ is-indirect; + }; -+ + + dsa { compatible = "marvell,dsa"; #address-cells = <2>; diff --git a/target/linux/kirkwood/patches-4.19/105-goflexhome.patch b/target/linux/kirkwood/patches-4.19/105-goflexhome.patch deleted file mode 100644 index 9ac30b6d30..0000000000 --- a/target/linux/kirkwood/patches-4.19/105-goflexhome.patch +++ /dev/null @@ -1,130 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -256,6 +256,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-ds411.dtb \ - kirkwood-ds411j.dtb \ - kirkwood-ds411slim.dtb \ -+ kirkwood-goflexhome.dtb \ - kirkwood-goflexnet.dtb \ - kirkwood-guruplug-server-plus.dtb \ - kirkwood-ib62x0.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-goflexhome.dts -@@ -0,0 +1,117 @@ -+/dts-v1/; -+ -+#include "kirkwood.dtsi" -+#include "kirkwood-6281.dtsi" -+ -+/ { -+ model = "Seagate GoFlex Home"; -+ compatible = "seagate,goflexhome", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x8000000>; -+ }; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; -+ stdout-path = &uart0; -+ }; -+ -+ ocp@f1000000 { -+ pinctrl: pin-controller@10000 { -+ pmx_usb_power_enable: pmx-usb-power-enable { -+ marvell,pins = "mpp29"; -+ marvell,function = "gpio"; -+ }; -+ pmx_led_white: pmx-led-white { -+ marvell,pins = "mpp40"; -+ marvell,function = "gpio"; -+ }; -+ pmx_led_green: pmx-led_green { -+ marvell,pins = "mpp46"; -+ marvell,function = "gpio"; -+ }; -+ pmx_led_orange: pmx-led-orange { -+ marvell,pins = "mpp47"; -+ marvell,function = "gpio"; -+ }; -+ }; -+ serial@12000 { -+ status = "ok"; -+ }; -+ -+ sata@80000 { -+ status = "okay"; -+ nr-ports = <2>; -+ }; -+ -+ }; -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ health { -+ label = "status:green:health"; -+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-on"; -+ }; -+ fault { -+ label = "status:orange:fault"; -+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -+ }; -+ misc { -+ label = "status:white:misc"; -+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "disk-activity"; -+ }; -+ }; -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-0 = <&pmx_usb_power_enable>; -+ pinctrl-names = "default"; -+ -+ usb_power: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "USB Power"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ regulator-always-on; -+ regulator-boot-on; -+ gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; -+ -+&nand { -+ chip-delay = <40>; -+ status = "okay"; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x0000000 0x100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "ubi"; -+ reg = <0x100000 0x0ff00000>; -+ }; -+}; -+ -+&mdio { -+ status = "okay"; -+ -+ ethphy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+}; -+ -+ð0 { -+ status = "okay"; -+ ethernet0-port@0 { -+ phy-handle = <ðphy0>; -+ }; -+}; diff --git a/target/linux/kirkwood/patches-4.19/106-goflexnet.patch b/target/linux/kirkwood/patches-4.19/106-goflexnet.patch index b22176880b..82cf90841e 100644 --- a/target/linux/kirkwood/patches-4.19/106-goflexnet.patch +++ b/target/linux/kirkwood/patches-4.19/106-goflexnet.patch @@ -1,6 +1,36 @@ --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts -@@ -159,18 +159,8 @@ +@@ -8,6 +8,13 @@ + model = "Seagate GoFlex Net"; + compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -85,12 +92,12 @@ + >; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -159,18 +166,8 @@ }; partition@100000 { diff --git a/target/linux/kirkwood/patches-4.19/107-02-nsa310b.patch b/target/linux/kirkwood/patches-4.19/107-02-nsa310b.patch deleted file mode 100644 index f8b963e03f..0000000000 --- a/target/linux/kirkwood/patches-4.19/107-02-nsa310b.patch +++ /dev/null @@ -1,147 +0,0 @@ -kirkwood: add nsa310b dtb, a zyxel nsa310 variant - -add support to a nsa310 variant with red/green usb led -and lm85 temp/fan controller - -Signed-off-by: Alberto Bursi - -NOTE: this patch can be upstreamed as-is, LEDE-specific - nand partitions are set in another patch - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -287,6 +287,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-ns2mini.dtb \ - kirkwood-nsa310.dtb \ - kirkwood-nsa310a.dtb \ -+ kirkwood-nsa310b.dtb \ - kirkwood-nsa320.dtb \ - kirkwood-nsa325.dtb \ - kirkwood-openblocks_a6.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-nsa310b.dts -@@ -0,0 +1,124 @@ -+/dts-v1/; -+ -+#include "kirkwood-nsa3x0-common.dtsi" -+ -+/* -+ * There are at least two different NSA310 designs. This variant has -+ * a red/green USB Led (same as nsa310) and a lm85 temp/fan controller. -+ */ -+ -+/ { -+ model = "ZyXEL NSA310b"; -+ compatible = "zyxel,nsa310b", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x10000000>; -+ }; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+ -+ ocp@f1000000 { -+ pinctrl: pin-controller@10000 { -+ pinctrl-names = "default"; -+ -+ pmx_led_esata_green: pmx-led-esata-green { -+ marvell,pins = "mpp12"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_esata_red: pmx-led-esata-red { -+ marvell,pins = "mpp13"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_usb_green: pmx-led-usb-green { -+ marvell,pins = "mpp15"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_usb_red: pmx-led-usb-red { -+ marvell,pins = "mpp16"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_sys_green: pmx-led-sys-green { -+ marvell,pins = "mpp28"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_sys_red: pmx-led-sys-red { -+ marvell,pins = "mpp29"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_hdd_green: pmx-led-hdd-green { -+ marvell,pins = "mpp41"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_hdd_red: pmx-led-hdd-red { -+ marvell,pins = "mpp42"; -+ marvell,function = "gpio"; -+ }; -+ -+ }; -+ -+ i2c@11000 { -+ status = "okay"; -+ -+ lm85: lm85@2e { -+ compatible = "national,lm85"; -+ reg = <0x2e>; -+ }; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ green-sys { -+ label = "nsa310:green:sys"; -+ gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -+ }; -+ red-sys { -+ label = "nsa310:red:sys"; -+ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; -+ }; -+ green-hdd { -+ label = "nsa310:green:hdd"; -+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ }; -+ red-hdd { -+ label = "nsa310:red:hdd"; -+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; -+ }; -+ green-esata { -+ label = "nsa310:green:esata"; -+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; -+ }; -+ red-esata { -+ label = "nsa310:red:esata"; -+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; -+ }; -+ green-usb { -+ label = "nsa310:green:usb"; -+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; -+ }; -+ red-usb { -+ label = "nsa310:red:usb"; -+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; -+ }; -+ green-copy { -+ label = "nsa310:green:copy"; -+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; -+ }; -+ red-copy { -+ label = "nsa310:red:copy"; -+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/kirkwood/patches-4.19/107-03-nsa325.patch b/target/linux/kirkwood/patches-4.19/107-03-nsa325.patch new file mode 100644 index 0000000000..36c77cd44a --- /dev/null +++ b/target/linux/kirkwood/patches-4.19/107-03-nsa325.patch @@ -0,0 +1,31 @@ +--- a/arch/arm/boot/dts/kirkwood-nsa325.dts ++++ b/arch/arm/boot/dts/kirkwood-nsa325.dts +@@ -15,6 +15,13 @@ + model = "ZyXEL NSA325"; + compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_green_sys; ++ led-failsafe = &led_orange_sys; ++ led-running = &led_green_sys; ++ led-upgrade = &led_orange_sys; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; +@@ -162,11 +169,12 @@ + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + +- green-sys { ++ led_green_sys: green-sys { + label = "nsa325:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; +- orange-sys { ++ led_orange_sys: orange-sys { + label = "nsa325:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; diff --git a/target/linux/kirkwood/patches-4.19/108-on100.patch b/target/linux/kirkwood/patches-4.19/108-on100.patch deleted file mode 100644 index 2f535955dd..0000000000 --- a/target/linux/kirkwood/patches-4.19/108-on100.patch +++ /dev/null @@ -1,171 +0,0 @@ ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-on100.dts -@@ -0,0 +1,158 @@ -+/dts-v1/; -+ -+#include "kirkwood.dtsi" -+#include "kirkwood-6282.dtsi" -+ -+/ { -+ model = "Cisco Systems ON100"; -+ compatible = "cisco,on100", "marvell,kirkwood-88f6282", "marvell,kirkwood"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x20000000>; -+ }; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200n8 earlyprintk"; -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&pmx_btn_reset>; -+ pinctrl-names = "default"; -+ -+ reset { -+ label = "Reset Button"; -+ linux,code = ; -+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g >; -+ pinctrl-names = "default"; -+ -+ health-g { -+ label = "on100:green:health"; -+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; -+ }; -+ -+ health-r { -+ label = "on100:red:health"; -+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; -+ }; -+ -+ health2-g { -+ label = "on100:green:health2"; -+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ health2-r { -+ label = "on100:red:health2"; -+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+ð0 { -+ status = "okay"; -+ -+ ethernet0-port@0 { -+ phy-handle = <ðphy0>; -+ phy-connection-type = "rgmii-id"; -+ }; -+}; -+ -+ð1 { -+ status = "okay"; -+ -+ ethernet1-port@0 { -+ phy-handle = <ðphy1>; -+ phy-connection-type = "rgmii-id"; -+ }; -+}; -+ -+&mdio { -+ status = "okay"; -+ -+ ethphy0: ethernet-phy@0 { -+ /* Marvell 88E1121R */ -+ compatible = "ethernet-phy-id0141.0cb0", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ /* Marvell 88E1121R */ -+ compatible = "ethernet-phy-id0141.0cb0", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ -+&nand { -+ status = "okay"; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x00000000 0x000a0000>; -+ read-only; -+ }; -+ -+ partition@a0000 { -+ label = "u-boot environment"; -+ reg = <0x000a0000 0x00020000>; -+ read-only; -+ }; -+ -+ partition@c0000 { -+ label = "kernel"; -+ reg = <0x000c0000 0x00540000>; -+ }; -+ -+ partition@600000 { -+ label = "ubi"; -+ reg = <0x00600000 0x1fa00000>; -+ }; -+}; -+ -+&pinctrl { -+ pmx_led_health_r: pmx-led-health-r { -+ marvell,pins = "mpp45"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_health_g: pmx-led-health-g { -+ marvell,pins = "mpp44"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_health2_r: pmx-led-health2-r { -+ marvell,pins = "mpp47"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_led_health2_g: pmx-led-health2-g { -+ marvell,pins = "mpp46"; -+ marvell,function = "gpio"; -+ }; -+ -+ pmx_btn_reset: pmx-led-reset { -+ marvell,pins = "mpp31"; -+ marvell,function = "gpio"; -+ }; -+}; -+ -+&sdio { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -290,6 +290,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-nsa310b.dtb \ - kirkwood-nsa320.dtb \ - kirkwood-nsa325.dtb \ -+ kirkwood-on100.dtb \ - kirkwood-openblocks_a6.dtb \ - kirkwood-openblocks_a7.dtb \ - kirkwood-openrd-base.dtb \ diff --git a/target/linux/kirkwood/patches-4.19/109-pogoplug_v4.patch b/target/linux/kirkwood/patches-4.19/109-pogoplug_v4.patch index 26b6314277..4273eb9af1 100644 --- a/target/linux/kirkwood/patches-4.19/109-pogoplug_v4.patch +++ b/target/linux/kirkwood/patches-4.19/109-pogoplug_v4.patch @@ -1,6 +1,19 @@ --- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts +++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts -@@ -24,6 +24,7 @@ +@@ -18,12 +18,20 @@ + compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; }; chosen { @@ -8,7 +21,7 @@ stdout-path = "uart0:115200n8"; }; -@@ -37,8 +38,8 @@ +@@ -37,8 +45,8 @@ eject { debounce-interval = <50>; wakeup-source; @@ -19,7 +32,22 @@ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; }; -@@ -137,29 +138,19 @@ +@@ -48,12 +56,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_red>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "pogoplugv4:green:health"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogoplugv4:red:fault"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; +@@ -137,29 +145,19 @@ #size-cells = <1>; partition@0 { diff --git a/target/linux/kirkwood/patches-4.19/110-pogo_e02.patch b/target/linux/kirkwood/patches-4.19/110-pogo_e02.patch new file mode 100644 index 0000000000..4b64337c9c --- /dev/null +++ b/target/linux/kirkwood/patches-4.19/110-pogo_e02.patch @@ -0,0 +1,70 @@ +--- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts ++++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts +@@ -20,6 +20,13 @@ + compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -33,12 +40,12 @@ + gpio-leds { + compatible = "gpio-leds"; + +- health { ++ led_health: health { + label = "pogo_e02:green:health"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogo_e02:orange:fault"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; +@@ -95,25 +102,26 @@ + status = "okay"; + + partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; ++ label = "uboot"; ++ reg = <0x0 0xe0000>; + read-only; + }; + +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; ++ partition@e0000 { ++ label = "uboot_env"; ++ reg = <0xe0000 0x20000>; + }; + +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; ++ partition@100000 { ++ label = "second_stage_uboot"; ++ reg = <0x100000 0x100000>; + }; + +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0x5b00000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; + }; ++ + }; + + &mdio { diff --git a/target/linux/kirkwood/patches-5.4/100-ib62x0.patch b/target/linux/kirkwood/patches-5.4/100-ib62x0.patch new file mode 100644 index 0000000000..0637c24b63 --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/100-ib62x0.patch @@ -0,0 +1,53 @@ +--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts ++++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts +@@ -6,7 +6,14 @@ + + / { + model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; +- compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ compatible = "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ ++ aliases { ++ led-boot = &led_green_os; ++ led-failsafe = &led_red_os; ++ led-running = &led_green_os; ++ led-upgrade = &led_red_os; ++ }; + + memory { + device_type = "memory"; +@@ -81,12 +88,12 @@ + &pmx_led_usb_transfer>; + pinctrl-names = "default"; + +- green-os { ++ led_green_os: green-os { + label = "ib62x0:green:os"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- red-os { ++ led_red_os: red-os { + label = "ib62x0:red:os"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; +@@ -118,13 +125,13 @@ + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x600000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@700000 { +- label = "root"; +- reg = <0x0700000 0xf900000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0xfe00000>; + }; + + }; diff --git a/target/linux/kirkwood/patches-5.4/101-iconnect.patch b/target/linux/kirkwood/patches-5.4/101-iconnect.patch new file mode 100644 index 0000000000..935e2dfcf5 --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/101-iconnect.patch @@ -0,0 +1,80 @@ +--- a/arch/arm/boot/dts/kirkwood-iconnect.dts ++++ b/arch/arm/boot/dts/kirkwood-iconnect.dts +@@ -8,6 +8,13 @@ + model = "Iomega Iconnect"; + compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power_blue; ++ led-failsafe = &led_power_red; ++ led-running = &led_power_blue; ++ led-upgrade = &led_power_red; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -16,8 +23,6 @@ + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; +- linux,initrd-start = <0x4500040>; +- linux,initrd-end = <0x4800000>; + }; + + ocp@f1000000 { +@@ -89,12 +94,12 @@ + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; +- power-blue { ++ led_power_blue: power-blue { + label = "power:blue"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; +- power-red { ++ led_power_red: power-red { + label = "power:red"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; +@@ -146,28 +151,23 @@ + status = "okay"; + + partition@0 { +- label = "uboot"; +- reg = <0x0000000 0xc0000>; ++ label = "u-boot"; ++ reg = <0x0000000 0xe0000>; + }; + +- partition@a0000 { +- label = "env"; +- reg = <0xa0000 0x20000>; ++ partition@e0000 { ++ label = "u-boot environment"; ++ reg = <0xe0000 0x100000>; + }; + + partition@100000 { +- label = "zImage"; +- reg = <0x100000 0x300000>; +- }; +- +- partition@540000 { +- label = "initrd"; +- reg = <0x540000 0x300000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@980000 { +- label = "boot"; +- reg = <0x980000 0x1f400000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x1fe00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.4/102-dockstar.patch b/target/linux/kirkwood/patches-5.4/102-dockstar.patch new file mode 100644 index 0000000000..127f84962c --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/102-dockstar.patch @@ -0,0 +1,62 @@ +--- a/arch/arm/boot/dts/kirkwood-dockstar.dts ++++ b/arch/arm/boot/dts/kirkwood-dockstar.dts +@@ -8,6 +8,13 @@ + model = "Seagate FreeAgent Dockstar"; + compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -42,12 +49,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_orange>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -78,18 +85,22 @@ + + partition@0 { + label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; ++ reg = <0x0000000 0xe0000>; ++ }; ++ ++ partition@e0000 { ++ label = "u-boot environment"; ++ reg = <0xe0000 0x100000>; + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@500000 { +- label = "data"; +- reg = <0x0500000 0xfb00000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0xfe00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.4/103-iomega-ix2-200.patch b/target/linux/kirkwood/patches-5.4/103-iomega-ix2-200.patch new file mode 100644 index 0000000000..9313b4bc3e --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/103-iomega-ix2-200.patch @@ -0,0 +1,67 @@ +--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts ++++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +@@ -8,6 +8,13 @@ + model = "Iomega StorCenter ix2-200"; + compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_power; ++ led-failsafe = &led_health; ++ led-running = &led_power; ++ led-upgrade = &led_health; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -127,16 +134,16 @@ + &pmx_led_rebuild &pmx_led_health >; + pinctrl-names = "default"; + +- power_led { ++ led_power: power_led { + label = "status:white:power_led"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; ++ default-state = "on"; + }; + rebuild_led { + label = "status:white:rebuild_led"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; +- health_led { ++ led_health: health_led { + label = "status:red:health_led"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; +@@ -186,18 +193,18 @@ + }; + + partition@a0000 { +- label = "env"; ++ label = "u-boot environment"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@100000 { +- label = "uImage"; ++ label = "kernel"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { +- label = "rootfs"; ++ label = "ubi"; + reg = <0x400000 0x1C00000>; + }; + }; +@@ -211,7 +218,7 @@ + }; + + ð0 { +- status = "okay"; ++ status = "disabled"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; diff --git a/target/linux/kirkwood/patches-5.4/105-ea4500.patch b/target/linux/kirkwood/patches-5.4/105-ea4500.patch new file mode 100644 index 0000000000..7302723029 --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/105-ea4500.patch @@ -0,0 +1,95 @@ +--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts ++++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts +@@ -24,6 +24,10 @@ + }; + + aliases { ++ led-boot = &led_white_health; ++ led-failsafe = &led_white_health; ++ led-running = &led_white_health; ++ led-upgrade = &led_white_health; + serial0 = &uart0; + }; + +@@ -56,9 +60,10 @@ + pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; + pinctrl-names = "default"; + +- white-health { ++ led_white_health: white-health { + label = "viper:white:health"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; + + white-pulse { +@@ -66,6 +71,17 @@ + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; ++ ++ mvsw61xx@10 { ++ compatible = "marvell,88e6171"; ++ status = "okay"; ++ reg = <0x10>; ++ ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ is-indirect; ++ }; + }; + + &pinctrl { +@@ -114,22 +130,22 @@ + }; + + partition@200000 { +- label = "kernel"; ++ label = "kernel1"; + reg = <0x200000 0x2A0000>; + }; + + partition@4a0000 { +- label = "rootfs"; ++ label = "rootfs1"; + reg = <0x4A0000 0x1760000>; + }; + + partition@1c00000 { +- label = "alt_kernel"; ++ label = "kernel2"; + reg = <0x1C00000 0x2A0000>; + }; + + partition@1ea0000 { +- label = "alt_rootfs"; ++ label = "rootfs2"; + reg = <0x1EA0000 0x1760000>; + }; + +@@ -162,6 +178,7 @@ + status = "okay"; + + switch@10 { ++ status = "disabled"; + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; +@@ -225,10 +242,14 @@ + }; + + /* eth1 is connected to the switch at port 6. However DSA only supports a +- * single CPU port. So leave this port disabled to avoid confusion. ++ * single CPU port. Upstream uses DSA so they disable this port to avoid confusion. + */ + ð1 { +- status = "disabled"; ++ status = "okay"; ++ ethernet1-port@0 { ++ speed = <1000>; ++ duplex = <1>; ++ }; + }; + + /* There is no battery on the board, so the RTC does not keep diff --git a/target/linux/kirkwood/patches-5.4/106-goflexnet.patch b/target/linux/kirkwood/patches-5.4/106-goflexnet.patch new file mode 100644 index 0000000000..82cf90841e --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/106-goflexnet.patch @@ -0,0 +1,53 @@ +--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts ++++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts +@@ -8,6 +8,13 @@ + model = "Seagate GoFlex Net"; + compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; +@@ -85,12 +92,12 @@ + >; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "status:green:health"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; +@@ -159,18 +166,8 @@ + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; +- }; +- +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; +- }; +- +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0xd800000>; ++ label = "ubi"; ++ reg = <0x0100000 0x0ff00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.4/107-01-zyxel-nsa3x0-common-nand-partitions.patch b/target/linux/kirkwood/patches-5.4/107-01-zyxel-nsa3x0-common-nand-partitions.patch new file mode 100644 index 0000000000..df654033fd --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/107-01-zyxel-nsa3x0-common-nand-partitions.patch @@ -0,0 +1,48 @@ +--- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi ++++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +@@ -112,40 +112,16 @@ + + partition@0 { + label = "uboot"; +- reg = <0x0000000 0x0100000>; ++ reg = <0x0000000 0x00c0000>; + read-only; + }; + partition@100000 { + label = "uboot_env"; +- reg = <0x0100000 0x0080000>; ++ reg = <0x00c0000 0x0080000>; + }; +- partition@180000 { +- label = "key_store"; +- reg = <0x0180000 0x0080000>; +- }; +- partition@200000 { +- label = "info"; +- reg = <0x0200000 0x0080000>; +- }; +- partition@280000 { +- label = "etc"; +- reg = <0x0280000 0x0a00000>; +- }; +- partition@c80000 { +- label = "kernel_1"; +- reg = <0x0c80000 0x0a00000>; +- }; +- partition@1680000 { +- label = "rootfs1"; +- reg = <0x1680000 0x2fc0000>; +- }; +- partition@4640000 { +- label = "kernel_2"; +- reg = <0x4640000 0x0a00000>; +- }; +- partition@5040000 { +- label = "rootfs2"; +- reg = <0x5040000 0x2fc0000>; ++ partition@140000 { ++ label = "ubi"; ++ reg = <0x0140000 0x7ec0000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.4/107-03-nsa325.patch b/target/linux/kirkwood/patches-5.4/107-03-nsa325.patch new file mode 100644 index 0000000000..36c77cd44a --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/107-03-nsa325.patch @@ -0,0 +1,31 @@ +--- a/arch/arm/boot/dts/kirkwood-nsa325.dts ++++ b/arch/arm/boot/dts/kirkwood-nsa325.dts +@@ -15,6 +15,13 @@ + model = "ZyXEL NSA325"; + compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_green_sys; ++ led-failsafe = &led_orange_sys; ++ led-running = &led_green_sys; ++ led-upgrade = &led_orange_sys; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; +@@ -162,11 +169,12 @@ + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + +- green-sys { ++ led_green_sys: green-sys { + label = "nsa325:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; + }; +- orange-sys { ++ led_orange_sys: orange-sys { + label = "nsa325:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; diff --git a/target/linux/kirkwood/patches-5.4/109-pogoplug_v4.patch b/target/linux/kirkwood/patches-5.4/109-pogoplug_v4.patch new file mode 100644 index 0000000000..4273eb9af1 --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/109-pogoplug_v4.patch @@ -0,0 +1,87 @@ +--- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts ++++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts +@@ -18,12 +18,20 @@ + compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { ++ bootargs = "console=ttyS0,115200"; + stdout-path = "uart0:115200n8"; + }; + +@@ -37,8 +45,8 @@ + eject { + debounce-interval = <50>; + wakeup-source; +- linux,code = ; +- label = "Eject Button"; ++ linux,code = ; ++ label = "Reset"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; +@@ -48,12 +56,12 @@ + pinctrl-0 = <&pmx_led_green &pmx_led_red>; + pinctrl-names = "default"; + +- health { ++ led_health: health { + label = "pogoplugv4:green:health"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogoplugv4:red:fault"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; +@@ -137,29 +145,19 @@ + #size-cells = <1>; + + partition@0 { +- label = "u-boot"; +- reg = <0x00000000 0x200000>; ++ label = "uboot"; ++ reg = <0x00000000 0x1c0000>; + read-only; + }; + +- partition@200000 { +- label = "uImage"; +- reg = <0x00200000 0x300000>; +- }; +- +- partition@500000 { +- label = "uImage2"; +- reg = <0x00500000 0x300000>; +- }; +- +- partition@800000 { +- label = "failsafe"; +- reg = <0x00800000 0x800000>; ++ partition@1c0000 { ++ label = "uboot_env"; ++ reg = <0x001c0000 0x40000>; + }; + +- partition@1000000 { +- label = "root"; +- reg = <0x01000000 0x7000000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x00200000 0x7e00000>; + }; + }; + }; diff --git a/target/linux/kirkwood/patches-5.4/110-pogo_e02.patch b/target/linux/kirkwood/patches-5.4/110-pogo_e02.patch new file mode 100644 index 0000000000..fc384d3521 --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/110-pogo_e02.patch @@ -0,0 +1,68 @@ +--- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts ++++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts +@@ -20,6 +20,13 @@ + compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", + "marvell,kirkwood"; + ++ aliases { ++ led-boot = &led_health; ++ led-failsafe = &led_fault; ++ led-running = &led_health; ++ led-upgrade = &led_fault; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; +@@ -33,12 +40,12 @@ + gpio-leds { + compatible = "gpio-leds"; + +- health { ++ led_health: health { + label = "pogo_e02:green:health"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +- default-state = "keep"; ++ default-state = "on"; + }; +- fault { ++ led_fault: fault { + label = "pogo_e02:orange:fault"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; +@@ -95,24 +102,24 @@ + status = "okay"; + + partition@0 { +- label = "u-boot"; +- reg = <0x0000000 0x100000>; ++ label = "uboot"; ++ reg = <0x0 0xe0000>; + read-only; + }; + +- partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; ++ partition@e0000 { ++ label = "uboot_env"; ++ reg = <0xe0000 0x20000>; + }; + +- partition@500000 { +- label = "pogoplug"; +- reg = <0x0500000 0x2000000>; ++ partition@100000 { ++ label = "second_stage_uboot"; ++ reg = <0x100000 0x100000>; + }; + +- partition@2500000 { +- label = "root"; +- reg = <0x02500000 0x5b00000>; ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-5.4/201-enable-sata-port-specific-led-triggers.patch b/target/linux/kirkwood/patches-5.4/201-enable-sata-port-specific-led-triggers.patch new file mode 100644 index 0000000000..c1645367a4 --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/201-enable-sata-port-specific-led-triggers.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/mach-mvebu/Kconfig ++++ b/arch/arm/mach-mvebu/Kconfig +@@ -119,6 +119,7 @@ config MACH_DOVE + config MACH_KIRKWOOD + bool "Marvell Kirkwood boards" + depends on ARCH_MULTI_V5 ++ select ARCH_WANT_LIBATA_LEDS + select CPU_FEROCEON + select GPIOLIB + select KIRKWOOD_CLK diff --git a/target/linux/kirkwood/patches-5.4/202-linksys-find-active-root.patch b/target/linux/kirkwood/patches-5.4/202-linksys-find-active-root.patch new file mode 100644 index 0000000000..b7e7f50271 --- /dev/null +++ b/target/linux/kirkwood/patches-5.4/202-linksys-find-active-root.patch @@ -0,0 +1,62 @@ +The WRT1900AC among other Linksys routers uses a dual-firmware layout. +Dynamically rename the active partition to "ubi". + +Signed-off-by: Imre Kaloz +--- +--- a/drivers/mtd/parsers/ofpart.c ++++ b/drivers/mtd/parsers/ofpart.c +@@ -21,6 +21,8 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static int mangled_rootblock; ++ + static int parse_fixed_partitions(struct mtd_info *master, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -28,6 +30,7 @@ static int parse_fixed_partitions(struct + struct mtd_partition *parts; + struct device_node *mtd_node; + struct device_node *ofpart_node; ++ const char *owrtpart = "ubi"; + const char *partname; + struct device_node *pp; + int nr_parts, i, ret = 0; +@@ -106,9 +109,15 @@ static int parse_fixed_partitions(struct + parts[i].size = of_read_number(reg + a_cells, s_cells); + parts[i].of_node = pp; + +- partname = of_get_property(pp, "label", &len); +- if (!partname) +- partname = of_get_property(pp, "name", &len); ++ if (mangled_rootblock && (i == mangled_rootblock)) { ++ partname = owrtpart; ++ } else { ++ partname = of_get_property(pp, "label", &len); ++ ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ } ++ + parts[i].name = partname; + + if (of_get_property(pp, "read-only", &len)) +@@ -215,6 +224,18 @@ static int __init ofpart_parser_init(voi + return 0; + } + ++static int __init active_root(char *str) ++{ ++ get_option(&str, &mangled_rootblock); ++ ++ if (!mangled_rootblock) ++ return 1; ++ ++ return 1; ++} ++ ++__setup("mangled_rootblock=", active_root); ++ + static void __exit ofpart_parser_exit(void) + { + deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile index ee3e42bcb0..217280c42f 100644 --- a/target/linux/lantiq/Makefile +++ b/target/linux/lantiq/Makefile @@ -13,6 +13,7 @@ SUBTARGETS:=xrx200 xway xway_legacy falcon ase MAINTAINER:=John Crispin KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 define Target/Description Build firmware images for Lantiq SoC diff --git a/target/linux/lantiq/ase/base-files/etc/board.d/01_leds b/target/linux/lantiq/ase/base-files/etc/board.d/01_leds new file mode 100755 index 0000000000..6a8de7d7a5 --- /dev/null +++ b/target/linux/lantiq/ase/base-files/etc/board.d/01_leds @@ -0,0 +1,32 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/leds.sh +. /lib/functions/uci-defaults.sh + +board_config_update + +led_dsl="$(get_dt_led dsl)" +[ -n "$led_dsl" ] && { + led_internet="$(get_dt_led internet)" + if [ -n "$led_internet" ]; then + ucidef_set_led_default "dsl" "dsl" "$led_dsl" "0" + ucidef_set_led_netdev "internet" "internet" "$led_internet" "pppoe-wan" + else + ucidef_set_led_netdev "dsl" "dsl" "$led_dsl" "dsl0" + fi +} + +board=$(board_name) + +case "$board" in +allnet,all0333cj) + ucidef_set_led_netdev "lan" "lan" "all0333cj:green:lan" "eth0.1" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/ase/base-files/etc/board.d/02_network b/target/linux/lantiq/ase/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..0bda3e4763 --- /dev/null +++ b/target/linux/lantiq/ase/base-files/etc/board.d/02_network @@ -0,0 +1,56 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh +. /lib/functions/lantiq.sh + +lantiq_setup_interfaces() +{ + local board="$1" + + case "$board" in + *) + ucidef_set_interface_lan 'eth0' + ;; + esac +} + +lantiq_setup_dsl() +{ + local board="$1" + local annex="b" + + case "$board" in + esac + + lantiq_setup_dsl_helper "$annex" +} + +lantiq_setup_macs() +{ + local board="$1" + local lan_mac="" + local wan_mac="" + + case "$board" in + allnet,all0333cj) + lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) + wan_mac=$(macaddr_add "$lan_mac" 1) + ;; + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" "$lan_mac" + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" +} + +board_config_update +board=$(board_name) +lantiq_setup_interfaces $board +lantiq_setup_dsl $board +lantiq_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/ase/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/ase/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000000..d088601bb0 --- /dev/null +++ b/target/linux/lantiq/ase/base-files/lib/upgrade/platform.sh @@ -0,0 +1,10 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +platform_check_image() { + return 0 +} + +platform_do_upgrade() { + default_do_upgrade "$1" +} diff --git a/target/linux/lantiq/ase/config-4.19 b/target/linux/lantiq/ase/config-4.19 index cf27a148b7..0c211847d2 100644 --- a/target/linux/lantiq/ase/config-4.19 +++ b/target/linux/lantiq/ase/config-4.19 @@ -5,7 +5,6 @@ CONFIG_CPU_MIPSR1=y CONFIG_CRC16=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_DEFLATE=y -CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_GENERIC_PLATFORM=y diff --git a/target/linux/lantiq/ase/config-5.4 b/target/linux/lantiq/ase/config-5.4 new file mode 100644 index 0000000000..455cd54d10 --- /dev/null +++ b/target/linux/lantiq/ase/config-5.4 @@ -0,0 +1,28 @@ +CONFIG_ADM6996_PHY=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_NLS=y +# CONFIG_PSB6970_PHY is not set +# CONFIG_RTL8366_SMI is not set +CONFIG_SGL_ALLOC=y +CONFIG_SOC_AMAZON_SE=y +# CONFIG_SOC_XWAY is not set +CONFIG_TARGET_ISA_REV=1 +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/base-files/etc/board.d/02_network b/target/linux/lantiq/base-files/etc/board.d/02_network deleted file mode 100755 index a6a9e4d29d..0000000000 --- a/target/linux/lantiq/base-files/etc/board.d/02_network +++ /dev/null @@ -1,268 +0,0 @@ -#!/bin/sh -# -# Copyright (C) 2011-2015 OpenWrt.org -# - -. /lib/functions/uci-defaults.sh -. /lib/functions/system.sh -. /lib/functions/lantiq.sh - -board_config_update - -vpi=1 -vci=32 -annex="a" -tone="av" -xfer_mode="" -encaps="llc" -payload="bridged" -lan_mac="" -wan_mac="" -interface_wan="dsl0" - -board=$(board_name) - -case "$board" in -audiocodes,mp-252) - ucidef_add_switch "switch0" \ - "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5t@eth0" - ;; - -allnet,all0333cj) - annex="b" - lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_set_interface_lan 'eth0' - ;; - -arcadyan,arv4510pw) - lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_add_switch "switch0" \ - "0:lan:4" "2:lan:2" "1:lan:3" "3:lan:1" "5t@eth0" - ;; - -arcadyan,arv4519pw|arcadyan,arv7510pw22|arcadyan,arv7518pw) - ucidef_add_switch "switch0" \ - "0t@eth0" "2:lan" "3:lan" "4:lan" "5:lan" - ;; - -arcadyan,arv4520pw) - annex="b" - ucidef_add_switch "switch0" \ - "0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5t@eth0" - ;; - -arcadyan,arv4525pw|arcadyan,arv452cqw|arcadyan,arv7525pw|arcadyan,arv752dpw) - annex="b" - ucidef_set_interface_lan 'eth0' - ;; - -arcadyan,arv7506pw11) - annex="b" - wan_mac=$(macaddr_add "$(mtd_get_mac_binary board_config 22)" 2) - ucidef_add_switch "switch0" \ - "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5t@eth0" - ;; - -arcadyan,arv7519pw) - wan_mac=$(macaddr_add "$(mtd_get_mac_binary board_config 22)" 1) - ucidef_add_switch "switch0" \ - "0:lan" "1:lan" "2:lan" "3:lan" "4t@eth0" - ;; - -arcadyan,arv7519rw22) - wan_mac=$(macaddr_add "$(mtd_get_mac_binary boardconfig 22)" 1) - ucidef_add_switch "switch0" \ - "0:lan:5" "2:lan:3" "3:lan:4" "4:lan:1" "5:lan:2" "6t@eth0" - ;; - -arcadyan,arv752dpw22|arcadyan,arv8539pw22) - annex="b" - ucidef_add_switch "switch0" \ - "0t@eth0" "2:lan" "3:lan" "4:lan" "5:lan" - ;; - -alphanetworks,asl56026) - lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) - wan_mac=$(mtd_get_mac_ascii uboot_env wanmac) - ucidef_add_switch "switch0"\ - "2:lan" "3:lan" "6t@eth0" - ;; - -bt,homehub-v2b) - lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_add_switch "switch0" \ - "1:lan" "2:lan" "3:lan" "4:lan" "5t@eth0" - ;; - -bt,homehub-v3a) - lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_set_interface_lan 'eth0' - ;; - -bt,homehub-v5a) - lan_mac=$(mtd_get_mac_binary_ubi caldata 4364) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_add_switch "switch0" \ - "0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0" - ;; - -netgear,dgn1000b) - annex="b" - ucidef_set_interface_lan 'eth0' - ;; - -netgear,dgn3500|netgear,dgn3500b) - lan_mac=$(mtd_get_mac_ascii uboot-env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_add_switch "switch0" \ - "0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5t@eth0" - ;; - -netgear,dm200) - lan_mac=$(mtd_get_mac_binary ART 0) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_set_interface_lan 'eth0' - ;; - -lantiq,easy80920-nand|lantiq,easy80920-nor) - lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_add_switch "switch0" \ - "0:lan:4" "1:lan:3" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0" - ;; - -avm,fritz3370-rev2-hynix|\ -avm,fritz3370-rev2-micron) - annex="b" - lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) - wan_mac=$(macaddr_add "$lan_mac" 3) - ucidef_add_switch "switch0" \ - "0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "6t@eth0" - ;; - -avm,fritz7312|\ -avm,fritz7320) - annex="b" - wan_mac=$(macaddr_add "$(mtd_get_mac_binary urlader 2705)" 1) - ucidef_set_interface_lan 'eth0' - ;; - -avm,fritz7360sl) - annex="b" - wan_mac=$(macaddr_add "$(mtd_get_mac_binary urlader 2705)" 1) - ucidef_add_switch "switch0" \ - "0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "6t@eth0" - ;; - -avm,fritz7362sl) - annex="b" - lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) - wan_mac=$(fritz_tffs -n macdsl -i $(find_mtd_part "tffs (1)")) - ucidef_add_switch "switch0" \ - "0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "6t@eth0" - ;; - -avm,fritz7412) - tffsdev=$(find_mtd_chardev "nand-tffs") - annex="b" - lan_mac=$(/usr/bin/fritz_tffs_nand -d $tffsdev -n maca -o) - wan_mac=$(/usr/bin/fritz_tffs_nand -d $tffsdev -n macdsl -o) - ucidef_set_interface_lan 'eth0' - ;; - -siemens,gigaset-sx76x) - annex="b" - ucidef_add_switch "switch0" \ - "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5t@eth0" - ;; - -zte,h201l) - annex="b" - ucidef_add_switch "switch0" \ - "0:lan" "1:lan" "2:lan" "3:lan" "4t@eth0" - ;; - -zyxel,p-2601hn) - ucidef_add_switch "switch0" \ - "0:lan" "1:lan" "2:lan" "3:lan" "5t@eth0" - ;; - -zyxel,p-2812hnu-f1|zyxel,p-2812hnu-f3) - lan_mac=$(mtd_get_mac_ascii uboot-env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_add_switch "switch0" \ - "0:lan" "1:lan" "2:lan" "4:lan" "5:wan" "6t@eth0" - ;; - -tplink,tdw8970|tplink,tdw8980) - wan_mac=$(macaddr_add "$(mtd_get_mac_binary boardconfig 61696)" 1) - ucidef_add_switch "switch0" \ - "0:lan:2" "2:lan:3" "4:lan:4" "5:lan:1" "6t@eth0" - ;; - -arcadyan,vg3503j) - lan_mac=$(mtd_get_mac_ascii uboot-env ethaddr) - wan_mac=$(macaddr_add "$lan_mac" 1) - ucidef_add_switch "switch0" \ - "2:lan:2" "4:lan:1" "6t@eth0" - ;; - -tplink,vr200|tplink,vr200v) - wan_mac=$(macaddr_add "$(mtd_get_mac_binary romfile 61696)" 1) - ucidef_add_switch "switch0" \ - "0:lan" "2:lan" "4:lan" "5:lan" "6t@eth0" - ;; - -arcadyan,vgv7510kw22-nor|arcadyan,vgv7510kw22-brn) - annex="b" - wan_mac=$(macaddr_add "$(mtd_get_mac_binary board_config 22)" 2) - ucidef_add_switch "switch0" \ - "2:lan:2" "3:lan:1" "4:lan:4" "5:lan:3" "0:wan:5" "6t@eth0" - ;; - -arcadyan,vgv7519-nor|arcadyan,vgv7519-brn) - wan_mac=$(mtd_get_mac_binary board_config 22) - ucidef_add_switch "switch0" \ - "0:lan:4" "1:lan:3" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0" - ;; - -buffalo,wbmr-hp-g300h) - ucidef_add_switch "switch0" \ - "0t@eth0" "2:lan" "3:lan" "4:lan" "5:lan" - ;; - -buffalo,wbmr-300hpd) - lan_mac=$(mtd_get_mac_ascii ubootconfig ethaddr) - wan_mac="$lan_mac" - ucidef_add_switch "switch0" \ - "5:lan:2" "2:lan:3" "3:lan:4" "4:wan:1" "6t@eth0" - ;; - -*) - ucidef_set_interface_lan 'eth0' - ;; - -esac - -ls /lib/modules/$(uname -r)/ltq_atm* 1> /dev/null 2>&1 && \ - ucidef_add_atm_bridge "$vpi" "$vci" "$encaps" "$payload" "dsl" - -if lantiq_is_vdsl_system; then - ucidef_add_vdsl_modem "$annex" "$tone" "$xfer_mode" -else - ucidef_add_adsl_modem "$annex" "/lib/firmware/adsl.bin" -fi - -ucidef_set_interface_wan "$interface_wan" "pppoe" - -[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" "$lan_mac" -[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" - -board_config_flush - -exit 0 - diff --git a/target/linux/lantiq/base-files/etc/hotplug.d/dsl/pppoa.sh b/target/linux/lantiq/base-files/etc/hotplug.d/dsl/pppoa.sh index b9a3313c83..4506737672 100755 --- a/target/linux/lantiq/base-files/etc/hotplug.d/dsl/pppoa.sh +++ b/target/linux/lantiq/base-files/etc/hotplug.d/dsl/pppoa.sh @@ -8,7 +8,7 @@ include /lib/network scan_interfaces -interfaces=`ubus list network.interface.\* | cut -d"." -f3` +interfaces=$(ubus list network.interface.\* | cut -d"." -f3) for ifc in $interfaces; do json_load "$(ifstatus $ifc)" diff --git a/target/linux/lantiq/base-files/etc/uci-defaults/01_led_migration b/target/linux/lantiq/base-files/etc/uci-defaults/01_led_migration index dc594e35e9..b1e7be6bd2 100644 --- a/target/linux/lantiq/base-files/etc/uci-defaults/01_led_migration +++ b/target/linux/lantiq/base-files/etc/uci-defaults/01_led_migration @@ -3,37 +3,7 @@ # Copyright (C) 2013 OpenWrt.org # -LED_OPTIONS_CHANGED=0 - -. /lib/functions.sh - -do_led_update_sysfs() -{ - local cfg=$1; shift - local tuples="$@" - local sysfs - local name - - config_get sysfs $cfg sysfs - config_get name $cfg name - - [ -z "$sysfs" ] && return - - for tuple in $tuples; do - local old=${tuple%=*} - local new=${tuple#*=} - local new_sysfs - - new_sysfs=$(echo ${sysfs} | sed "s/${old}/${new}/") - - [ "$new_sysfs" = "$sysfs" ] && continue - - uci set system.${cfg}.sysfs="${new_sysfs}" - LED_OPTIONS_CHANGED=1 - - logger -t led-migration "sysfs option of LED \"${name}\" updated to ${new_sysfs}" - done; -} +. /lib/functions/migrations.sh do_internet_led_rename() { @@ -45,38 +15,29 @@ do_internet_led_rename() uci rename system.led_internet=led_dsl uci set system.led_dsl.name=dsl - LED_OPTIONS_CHANGED=1 logger -t led-migration "internet led renamed to dsl" } -migrate_leds() -{ - config_load system - config_foreach do_led_update_sysfs led "$@" -} - case "$(board_name)" in +alphanetworks,asl56026|\ arcadyan,arv452cqw|\ arcadyan,arv7510pw22|\ arcadyan,arv7519rw22|\ arcadyan,arv752dpw|\ arcadyan,arv752dpw22|\ -alphanetworks,asl56026|\ +arcadyan,vg3503j|\ +avm,fritz7360sl|\ bt,homehub-v2b|\ bt,homehub-v3a|\ -bt,homehub-v5a|\ -avm,fritz7360sl|\ -arcadyan,vg3503j) +bt,homehub-v5a) do_internet_led_rename ;; netgear,dgn3500|\ netgear,dgn3500b) migrate_leds "dgn3500:blue:wireless=dgn3500:green:wireless" ;; -*) - ;; esac -[ "$LED_OPTIONS_CHANGED" = "1" ] && uci commit system +migrations_apply system exit 0 diff --git a/target/linux/lantiq/base-files/etc/uci-defaults/02_migrate_xdsl_iface b/target/linux/lantiq/base-files/etc/uci-defaults/02_migrate_xdsl_iface index 3b0313d1aa..dd57ca6d39 100644 --- a/target/linux/lantiq/base-files/etc/uci-defaults/02_migrate_xdsl_iface +++ b/target/linux/lantiq/base-files/etc/uci-defaults/02_migrate_xdsl_iface @@ -1,7 +1,6 @@ #!/bin/sh . /lib/functions.sh -. /lib/functions/lantiq.sh IFNAME_CHANGED=0 diff --git a/target/linux/lantiq/base-files/lib/functions/lantiq.sh b/target/linux/lantiq/base-files/lib/functions/lantiq.sh index 62c7a6b662..e88e638285 100644 --- a/target/linux/lantiq/base-files/lib/functions/lantiq.sh +++ b/target/linux/lantiq/base-files/lib/functions/lantiq.sh @@ -1,5 +1,18 @@ -#!/bin/sh - lantiq_is_vdsl_system() { grep -qE "system type.*: (VR9|xRX200)" /proc/cpuinfo } + +lantiq_setup_dsl_helper() { + local annex="$1" + + ls /lib/modules/$(uname -r)/ltq_atm* 1> /dev/null 2>&1 && \ + ucidef_add_atm_bridge "1" "32" "llc" "bridged" "dsl" + + if lantiq_is_vdsl_system; then + ucidef_add_vdsl_modem "$annex" "av" + else + ucidef_add_adsl_modem "$annex" "/lib/firmware/adsl.bin" + fi + + ucidef_set_interface_wan "dsl0" "pppoe" +} diff --git a/target/linux/lantiq/base-files/lib/functions/lantiq_dsl.sh b/target/linux/lantiq/base-files/lib/functions/lantiq_dsl.sh index 8665240da4..11b02fc4aa 100755 --- a/target/linux/lantiq/base-files/lib/functions/lantiq_dsl.sh +++ b/target/linux/lantiq/base-files/lib/functions/lantiq_dsl.sh @@ -290,8 +290,8 @@ xtse() { annex_s="$annex_s M," fi - annex_s=`echo ${annex_s:1}` - annex_s=`echo ${annex_s%?}` + annex_s=${annex_s:1} + annex_s=${annex_s%?} # Evaluate Line Mode (according to G.997.1, 7.3.1.1.1) @@ -346,8 +346,8 @@ xtse() { line_mode_s="$line_mode_s G.993.1 (VDSL)," fi - line_mode_s=`echo ${line_mode_s:1}` - line_mode_s=`echo ${line_mode_s%?}` + line_mode_s=${line_mode_s:1} + line_mode_s=${line_mode_s%?} xtse_s="${xtse1}, ${xtse2}, ${xtse3}, ${xtse4}, ${xtse5}, ${xtse6}, ${xtse7}, ${xtse8}" @@ -451,7 +451,8 @@ latency_delay() { errors() { local lsctg local dpctg - local ccsg + local fecsf + local fecsn local esf local esn local sesf @@ -468,16 +469,15 @@ errors() { local hecf local hecn - local fecn - local fecf - lsctg=$(dsl_cmd pmlsctg 1) + fecsf=$(dsl_val "$lsctg" nFECS) esf=$(dsl_val "$lsctg" nES) sesf=$(dsl_val "$lsctg" nSES) lossf=$(dsl_val "$lsctg" nLOSS) uasf=$(dsl_val "$lsctg" nUAS) lsctg=$(dsl_cmd pmlsctg 0) + fecsn=$(dsl_val "$lsctg" nFECS) esn=$(dsl_val "$lsctg" nES) sesn=$(dsl_val "$lsctg" nSES) lossn=$(dsl_val "$lsctg" nLOSS) @@ -493,15 +493,9 @@ errors() { crc_pn=$(dsl_val "$dpctg" nCRC_P) crcp_pn=$(dsl_val "$dpctg" nCRCP_P) - ccsg=$(dsl_cmd pmccsg 0 1 0) - fecf=$(dsl_val "$ccsg" nFEC) - - ccsg=$(dsl_cmd pmccsg 0 0 0) - fecn=$(dsl_val "$ccsg" nFEC) - if [ "$action" = "lucistat" ]; then - echo "dsl.errors_fec_near=${fecn:-nil}" - echo "dsl.errors_fec_far=${fecf:-nil}" + echo "dsl.errors_fecs_near=${fecsn:-nil}" + echo "dsl.errors_fecs_far=${fecsf:-nil}" echo "dsl.errors_es_near=${esn:-nil}" echo "dsl.errors_es_far=${esf:-nil}" echo "dsl.errors_ses_near=${sesn:-nil}" @@ -517,7 +511,7 @@ errors() { echo "dsl.errors_crcp_p_near=${crcp_pn:-nil}" echo "dsl.errors_crcp_p_far=${crcp_pf:-nil}" else - echo "Forward Error Correction Seconds (FECS): Near: ${fecn} / Far: ${fecf}" + echo "Forward Error Correction Seconds (FECS): Near: ${fecsn} / Far: ${fecsf}" echo "Errored seconds (ES): Near: ${esn} / Far: ${esf}" echo "Severely Errored Seconds (SES): Near: ${sesn} / Far: ${sesf}" echo "Loss of Signal Seconds (LOSS): Near: ${lossn} / Far: ${lossf}" @@ -734,7 +728,7 @@ profile() { fi } -status() { +dslstat() { vendor chipset xtse @@ -750,6 +744,6 @@ status() { lucistat() { echo "local dsl={}" - status + dslstat echo "return dsl" } diff --git a/target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq b/target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq index 7ed0fabcf7..4f7dc6673c 100644 --- a/target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq +++ b/target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq @@ -1,7 +1,5 @@ #!/bin/sh -. /lib/functions/lantiq.sh - set_preinit_iface() { ifname=eth0 } diff --git a/target/linux/lantiq/config-5.4 b/target/linux/lantiq/config-5.4 new file mode 100644 index 0000000000..8d84f1cdac --- /dev/null +++ b/target/linux/lantiq/config-5.4 @@ -0,0 +1,234 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_LOAD_STORE_LR=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y +CONFIG_DTC=y +# CONFIG_DT_EASY50712 is not set +CONFIG_EARLY_PRINTK=y +CONFIG_EFI_EARLYCON=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_FIXED_PHY=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_MM_LANTIQ=y +CONFIG_GPIO_STP_XWAY=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_RANDOM=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_LANTIQ=y +CONFIG_LANTIQ_DT_NONE=y +# CONFIG_LANTIQ_ETOP is not set +CONFIG_LANTIQ_WDT=y +# CONFIG_LANTIQ_XRX200 is not set +# CONFIG_LANTIQ_XRX200_LEGACY is not set +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHY_LANTIQ_RCU_USB2=y +# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_LANTIQ=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_XWAY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PSB6970_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_LANTIQ=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366_SMI=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_LANTIQ=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SPI=y +CONFIG_SPI_LANTIQ_SSC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_USE_OF=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_XRX200_PHY_FW is not set diff --git a/target/linux/lantiq/falcon/base-files/etc/board.d/02_network b/target/linux/lantiq/falcon/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..7998efc2a0 --- /dev/null +++ b/target/linux/lantiq/falcon/base-files/etc/board.d/02_network @@ -0,0 +1,52 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh +. /lib/functions/lantiq.sh + +lantiq_setup_interfaces() +{ + local board="$1" + + case "$board" in + *) + ucidef_set_interface_lan 'eth0' + ;; + esac +} + +lantiq_setup_dsl() +{ + local board="$1" + local annex="a" + + case "$board" in + esac + + lantiq_setup_dsl_helper "$annex" +} + +lantiq_setup_macs() +{ + local board="$1" + local lan_mac="" + local wan_mac="" + + case "$board" in + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" "$lan_mac" + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" +} + +board_config_update +board=$(board_name) +lantiq_setup_interfaces $board +lantiq_setup_dsl $board +lantiq_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/falcon/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/falcon/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000000..d088601bb0 --- /dev/null +++ b/target/linux/lantiq/falcon/base-files/lib/upgrade/platform.sh @@ -0,0 +1,10 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +platform_check_image() { + return 0 +} + +platform_do_upgrade() { + default_do_upgrade "$1" +} diff --git a/target/linux/lantiq/falcon/config-5.4 b/target/linux/lantiq/falcon/config-5.4 new file mode 100644 index 0000000000..a6d9e944f0 --- /dev/null +++ b/target/linux/lantiq/falcon/config-5.4 @@ -0,0 +1,11 @@ +CONFIG_LANTIQ_ETOP=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" +CONFIG_PINCTRL_FALCON=y +# CONFIG_PSB6970_PHY is not set +# CONFIG_RTL8366_SMI is not set +CONFIG_SOC_FALCON=y +# CONFIG_SOC_XWAY is not set +CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/amazonse.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse.dtsi similarity index 84% rename from target/linux/lantiq/files/arch/mips/boot/dts/amazonse.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse.dtsi index feb4cd529a..496150b7a7 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/amazonse.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse.dtsi @@ -133,6 +133,8 @@ "spi_frm"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; status = "disabled"; }; @@ -148,6 +150,40 @@ #gpio-cells = <2>; gpio-controller; reg = <0xe100b10 0xa0>; + + asc_pins: asc-pins { + mux { + lantiq,groups = "asc"; + lantiq,function = "asc"; + }; + }; + + mdio_pins: mdio { + mux { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + + spi_pins: spi { + mux-0 { + lantiq,groups = "spi_di"; + lantiq,function = "spi"; + }; + mux-1 { + lantiq,groups = "spi_do", "spi_clk"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + spi_cs4_pins: spi-cs4 { + mux { + lantiq,groups = "spi_cs4"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; }; asc1: serial@e100c00 { @@ -155,6 +191,8 @@ reg = <0xe100c00 0x400>; interrupt-parent = <&icu0>; interrupts = <72 74 75>; + pinctrl-0 = <&asc_pins>; + pinctrl-names = "default"; }; mei@e116000 { @@ -198,6 +236,8 @@ reg = <0xe180000 0x40000>; interrupt-parent = <&icu0>; interrupts = <105 109>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; }; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ALL0333CJ.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts similarity index 96% rename from target/linux/lantiq/files/arch/mips/boot/dts/ALL0333CJ.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts index ef57b2f06b..c5dd1600f4 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ALL0333CJ.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts @@ -61,10 +61,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - asc { - lantiq,groups = "asc"; - lantiq,function = "asc"; - }; keys_in { lantiq,pins = "io0",/* "io25", */"io29"; lantiq,pull = <2>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/DGN1000B.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts similarity index 87% rename from target/linux/lantiq/files/arch/mips/boot/dts/DGN1000B.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts index b4eee73b73..943b00f898 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/DGN1000B.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts @@ -86,28 +86,12 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - asc { - lantiq,groups = "asc"; - lantiq,function = "asc"; - }; keys_in { lantiq,pins = "io0",/* "io25", */"io29"; lantiq,pull = <2>; lantiq,open-drain = <1>; }; }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs1"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; }; &gsw { @@ -117,8 +101,6 @@ &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; flash@1 { compatible = "jedec,spi-nor"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ar9.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9.dtsi similarity index 66% rename from target/linux/lantiq/files/arch/mips/boot/dts/ar9.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9.dtsi index 37b44aecdd..12af82b8ce 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ar9.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9.dtsi @@ -160,6 +160,8 @@ "spi_frm"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; status = "disabled"; }; @@ -168,6 +170,149 @@ #gpio-cells = <2>; gpio-controller; reg = <0xe100b10 0xa0>; + + mdio_pins: mdio { + mux { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + + nand_pins: nand { + mux-0 { + lantiq,groups = "nand cle", "nand ale", + "nand rd"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + mux-1 { + lantiq,groups = "nand rdy"; + lantiq,function = "ebu"; + lantiq,output = <0>; + lantiq,pull = <2>; + }; + }; + + nand_cs1_pins: nand-cs1 { + mux { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt1_pins: pci-gnt1 { + mux { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt2_pins: pci-gnt2 { + mux { + lantiq,groups = "gnt2"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt3_pins: pci-gnt3 { + mux { + lantiq,groups = "gnt3"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt4_pins: pci-gnt4 { + mux { + lantiq,groups = "gnt4"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_req1_pins: pci-req1 { + mux { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req2_pins: pci-req2 { + mux { + lantiq,groups = "req2"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req3_pins: pci-req3 { + mux { + lantiq,groups = "req3"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req4_pins: pci-req4 { + mux { + lantiq,groups = "req4"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + spi_pins: spi { + mux-0 { + lantiq,groups = "spi_di"; + lantiq,function = "spi"; + }; + mux-1 { + lantiq,groups = "spi_do", "spi_clk"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + spi_cs4_pins: spi-cs4 { + mux { + lantiq,groups = "spi_cs4"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + stp_pins: stp { + mux { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; }; stp: stp@e100bb0 { @@ -175,6 +320,10 @@ compatible = "lantiq,gpio-stp-xway"; gpio-controller; reg = <0xe100bb0 0x40>; + + pinctrl-0 = <&stp_pins>; + pinctrl-names = "default"; + status = "disabled"; }; @@ -238,6 +387,8 @@ interrupt-parent = <&icu0>; interrupts = <73 72>; mac-address = [ 00 11 22 33 44 55 ]; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; }; ppe@e234000 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7312.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts similarity index 87% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7312.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts index 811f78f934..aa825abd9f 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7312.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts @@ -18,8 +18,7 @@ led-running = &power; led-upgrade = &power; - led-internet = &info_green; - led-dsl = &power; + led-dsl = &info_green; led-wifi = &wlan; }; @@ -76,21 +75,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - pci { - lantiq,groups = "gnt1", "req1", "req2", "req4", "gnt2", "gnt3", "gnt4"; - lantiq,function = "pci"; - }; - pci-in { - lantiq,groups = "req1", "req2", "req4"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1", "gnt2", "gnt3", "gnt4"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; ar8030-intr { lantiq,groups = "exin3"; lantiq,function = "exin"; @@ -167,6 +151,13 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_gnt3_pins>, <&pci_gnt4_pins>, + <&pci_req1_pins>, <&pci_req2_pins>, + <&pci_req4_pins>; + pinctrl-names = "default"; + req-mask = <0xf>; gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7320.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts similarity index 81% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7320.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts index 40348b1d59..424b778bb4 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7320.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts @@ -18,8 +18,7 @@ led-running = &power; led-upgrade = &power; - led-internet = &info_green; - led-dsl = &power; + led-dsl = &info_green; led-wifi = &wlan; }; @@ -74,29 +73,6 @@ }; }; -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci { - lantiq,groups = "gnt1", "req1", "req2", "req3", "req4", "gnt2", "gnt3", "gnt4"; - lantiq,function = "pci"; - }; - pci-in { - lantiq,groups = "req1", "req2", "req3", "req4"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1", "gnt2", "gnt3", "gnt4"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - }; -}; - &gsw { phy-mode = "mii"; mtd-mac-address = <&ath9k_cal 0xa91>; @@ -142,6 +118,12 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_gnt3_pins>, <&pci_gnt4_pins>, + <&pci_req1_pins>, <&pci_req2_pins>, + <&pci_req3_pins>, <&pci_req4_pins>; + req-mask = <0xf>; gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV3A.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts similarity index 86% rename from target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV3A.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts index 823a158fbf..044ae2b417 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV3A.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts @@ -109,35 +109,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - pci_rst { lantiq,pins = "io21"; lantiq,output = <1>; @@ -158,6 +129,9 @@ reg = <1 0x0 0x2000000 >; req-mask = <0x1>; /* PCI request lines to mask during NAND access */ + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -195,6 +169,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; wifi@7000 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/WBMR.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts similarity index 100% rename from target/linux/lantiq/files/arch/mips/boot/dts/WBMR.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/DGN3500.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts similarity index 75% rename from target/linux/lantiq/files/arch/mips/boot/dts/DGN3500.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts index 98a2ebd98e..cbc99fe620 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/DGN3500.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "DGN3500.dtsi" +#include "ar9_netgear_dgn3500.dtsi" / { compatible = "netgear,dgn3500", "lantiq,xway", "lantiq,ar9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/DGN3500.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi similarity index 85% rename from target/linux/lantiq/files/arch/mips/boot/dts/DGN3500.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi index 4a20dcefd3..a3dbbbdfad 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/DGN3500.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi @@ -115,33 +115,6 @@ lantiq,groups = "exin1"; lantiq,function = "exin"; }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; - pci-in { - lantiq,groups = "req1"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; }; }; @@ -151,6 +124,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; wifi@168c,0029 { @@ -163,9 +140,6 @@ &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - flash@4 { compatible = "jedec,spi-nor"; reg = <4>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/DGN3500B.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts similarity index 75% rename from target/linux/lantiq/files/arch/mips/boot/dts/DGN3500B.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts index d1d788cc7d..b69613e48f 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/DGN3500B.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "DGN3500.dtsi" +#include "ar9_netgear_dgn3500.dtsi" / { compatible = "netgear,dgn3500b", "lantiq,xway", "lantiq,ar9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/H201L.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts similarity index 100% rename from target/linux/lantiq/files/arch/mips/boot/dts/H201L.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/P2601HNFX.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts similarity index 88% rename from target/linux/lantiq/files/arch/mips/boot/dts/P2601HNFX.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts index 62e5e70169..79896c6478 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/P2601HNFX.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts @@ -103,30 +103,10 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; exin { lantiq,groups = "exin1"; lantiq,function = "exin"; }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; - lantiq,open-drain; - lantiq,pull = <0>; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; }; usb_vbus: regulator-usb-vbus { @@ -177,6 +157,11 @@ }; }; +&pci0 { + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; +}; + &stp { status = "okay"; lantiq,shadow = <0xfff>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/danube.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube.dtsi similarity index 76% rename from target/linux/lantiq/files/arch/mips/boot/dts/danube.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube.dtsi index cadfb80750..ae8c1c045a 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/danube.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube.dtsi @@ -144,6 +144,10 @@ compatible = "lantiq,gpio-stp-xway"; gpio-controller; reg = <0xe100bb0 0x40>; + + pinctrl-0 = <&stp_pins>; + pinctrl-names = "default"; + lantiq,shadow = <0xfff>; lantiq,groups = <0x3>; status = "disabled"; @@ -162,6 +166,82 @@ #gpio-cells = <2>; gpio-controller; reg = <0xe100b10 0xa0>; + + nand_pins: nand { + mux-0 { + lantiq,groups = "nand cle", "nand ale", + "nand rd"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + mux-1 { + lantiq,groups = "nand rdy"; + lantiq,function = "ebu"; + lantiq,output = <0>; + lantiq,pull = <2>; + }; + }; + + nand_cs1_pins: nand-cs1 { + mux { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt1_pins: pci-gnt1 { + mux { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt2_pins: pci-gnt2 { + mux { + lantiq,groups = "gnt2"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_req1_pins: pci-req1 { + mux { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req2_pins: pci-req2 { + mux { + lantiq,groups = "req2"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + stp_pins: stp { + mux { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; }; asc1: serial@e100c00 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4510PW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts similarity index 90% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV4510PW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts index e15eb66b04..19a44d5f6d 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4510PW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts @@ -131,29 +131,11 @@ lantiq,open-drain = <0>; lantiq,output = <1>; }; - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; exin { lantiq,groups = "exin1", "exin2"; lantiq,function = "exin"; lantiq,output = <0>; }; - pci_in { - lantiq,groups = "req1", "req2"; - lantiq,function = "pci"; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1", "gnt2"; - lantiq,function = "pci"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,open-drain = <0>; @@ -211,6 +193,11 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + lantiq,external-clock; interrupt-map = < 0x6000 0 0 1 &icu0 135 diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts similarity index 71% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts index 34f868f484..ff34068005 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "ARV4518PWR01.dtsi" +#include "danube_arcadyan_arv4518pwr01.dtsi" / { compatible = "arcadyan,arv4518pwr01", "lantiq,xway", "lantiq,danube"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi similarity index 92% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi index f5dec312f8..dcae06d894 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi @@ -119,19 +119,6 @@ lantiq,groups = "ebu cs1"; lantiq,function = "ebu"; }; - pci_in { - lantiq,groups = "req1", "req2"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1", "gnt2"; - lantiq,function = "pci"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; }; }; @@ -189,6 +176,11 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; req-mask = <0xf>; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01A.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts similarity index 78% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01A.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts index 9617398bbc..b261a2fa91 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4518PWR01A.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "ARV4518PWR01.dtsi" +#include "danube_arcadyan_arv4518pwr01.dtsi" / { compatible = "arcadyan,arv4518pwr01a", "lantiq,xway", "lantiq,danube"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4519PW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts similarity index 100% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV4519PW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4520PW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts similarity index 94% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV4520PW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts index 95944d9cfc..b59477cb19 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4520PW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts @@ -135,18 +135,6 @@ lantiq,groups = "ebu cs1"; lantiq,function = "ebu"; }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,open-drain = <0>; @@ -210,6 +198,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + lantiq,external-clock; gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4525PW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts similarity index 91% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV4525PW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts index d55613a02b..cceb42164e 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV4525PW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts @@ -80,18 +80,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <2>; @@ -149,6 +137,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV452CQW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts similarity index 94% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV452CQW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts index 4ff0f67ca3..eecff4bb0b 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV452CQW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts @@ -147,18 +147,6 @@ lantiq,groups = "ebu cs1"; lantiq,function = "ebu"; }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <0>; @@ -228,6 +216,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + lantiq,external-clock; gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7506PW11.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts similarity index 96% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV7506PW11.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts index c0bca84031..9e4216033b 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7506PW11.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts @@ -91,11 +91,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <2>; @@ -149,6 +144,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + lantiq,external-clock; gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7510PW22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts similarity index 93% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV7510PW22.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts index 5c4a41e957..e5fd05fe40 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7510PW22.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts @@ -86,18 +86,6 @@ lantiq,pull = <2>; lantiq,output = <0>; }; - pci_in { - lantiq,groups = "req1", "req2"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <2>; @@ -173,6 +161,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + lantiq,external-clock; interrupt-map = < 0x7000 0 0 1 &icu0 30 diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7518PW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts similarity index 94% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV7518PW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts index 458fd65495..ae0d27a042 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7518PW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts @@ -116,19 +116,6 @@ lantiq,groups = "ebu cs1"; lantiq,function = "ebu"; }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <2>; @@ -215,6 +202,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; lantiq,external-clock; req-mask = <0xf>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7519PW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts similarity index 93% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV7519PW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts index e9c418e482..34b541af92 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7519PW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts @@ -131,19 +131,6 @@ lantiq,groups = "ebu cs1"; lantiq,function = "ebu"; }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <2>; @@ -200,6 +187,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + lantiq,external-clock; gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; req-mask = <0xf>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7525PW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts similarity index 96% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV7525PW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts index bcdc2249fd..d673c9b204 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7525PW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts @@ -83,10 +83,6 @@ lantiq,groups = "exin1"; lantiq,function = "exin"; }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; }; }; @@ -134,6 +130,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + interrupt-map = <0x7000 0 0 1 &icu0 135 1>; wifi@0,0 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts similarity index 94% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts index dbec1eb6a1..069b1b1ed6 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts @@ -123,18 +123,6 @@ lantiq,pull = <2>; lantiq,output = <0>; }; - pci_in { - lantiq,groups = "req2", "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <2>; @@ -220,6 +208,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + lantiq,external-clock; gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; interrupt-map = <0x7000 0 0 1 &icu0 135>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts similarity index 95% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW22.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts index de996d10cc..ec90a2bef9 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW22.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts @@ -151,18 +151,6 @@ lantiq,pull = <2>; lantiq,output = <0>; }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,open-drain = <1>; @@ -235,6 +223,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + lantiq,external-clock; interrupt-map = < 0x7000 0 0 1 &icu0 30 diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV8539PW22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts similarity index 92% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV8539PW22.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts index 00131f929c..4bf44a10e1 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV8539PW22.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts @@ -95,18 +95,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; pci_rst { lantiq,pins = "io21"; lantiq,pull = <2>; @@ -163,6 +151,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; wifi@168c,0029 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ACMP252.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts similarity index 95% rename from target/linux/lantiq/files/arch/mips/boot/dts/ACMP252.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts index 7942535943..67b0f9631f 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ACMP252.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts @@ -37,10 +37,6 @@ lantiq,groups = "exin1"; lantiq,function = "exin"; }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; }; }; @@ -96,6 +92,9 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; }; &usb_phy { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV2B.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts similarity index 88% rename from target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV2B.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts index 2b3afb2295..40886feec4 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV2B.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts @@ -108,37 +108,10 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; exin { lantiq,groups = "exin1"; lantiq,function = "exin"; }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; pci_rst { lantiq,pins = "io21"; @@ -209,6 +182,9 @@ reg = <1 0x0 0x2000000 >; req-mask = <0x1>; /* PCI request lines to mask during NAND access */ + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -235,6 +211,10 @@ &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; wifi@168c,0027 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY50712.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts similarity index 80% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY50712.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts index ba7f302c2e..1afc74900e 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY50712.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts @@ -21,23 +21,10 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; exin { lantiq,groups = "exin1"; lantiq,function = "exin"; }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; }; }; @@ -78,3 +65,8 @@ }; }; }; + +&pci0 { + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; +}; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/GIGASX76X.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts similarity index 91% rename from target/linux/lantiq/files/arch/mips/boot/dts/GIGASX76X.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts index a9a5cbae2f..0072f7e2b1 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/GIGASX76X.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts @@ -52,18 +52,6 @@ }; }; -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - }; -}; - &gpios { status = "okay"; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/falcon.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon.dtsi similarity index 100% rename from target/linux/lantiq/files/arch/mips/boot/dts/falcon.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon.dtsi diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY88388.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts similarity index 98% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY88388.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts index 12c448c2e6..22ce8caced 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY88388.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts @@ -2,7 +2,7 @@ #include #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon FTTDP8 Reference Board"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY88444.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY88444.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts index 3f29d319cd..fa331450bf 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY88444.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts @@ -2,7 +2,7 @@ #include #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon FTTdp G.FAST Reference Board"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000NAND.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts similarity index 91% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98000NAND.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts index 2155f0cb1d..2107da5435 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000NAND.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts @@ -1,7 +1,6 @@ /dts-v1/; -#include "falcon.dtsi" -#include "EASY98000-base.dtsi" +#include "falcon_lantiq_easy98000.dtsi" / { model = "Lantiq Falcon (NAND)"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000NOR.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts similarity index 91% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98000NOR.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts index 3cb00343f5..56d0fe0bc3 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000NOR.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts @@ -1,7 +1,6 @@ /dts-v1/; -#include "falcon.dtsi" -#include "EASY98000-base.dtsi" +#include "falcon_lantiq_easy98000.dtsi" / { model = "Lantiq Falcon (NOR)"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000SFLASH.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts similarity index 67% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98000SFLASH.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts index bbe524e94e..8c931746ed 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000SFLASH.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts @@ -1,8 +1,7 @@ /dts-v1/; -#include "falcon.dtsi" -#include "EASY98000-base.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_lantiq_easy98000.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon (SFLASH)"; @@ -13,4 +12,3 @@ spi1 = &spi; }; }; - diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000-base.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi similarity index 98% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98000-base.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi index fa8c0b4b06..5821c51def 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98000-base.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi @@ -1,7 +1,8 @@ - #include #include +#include "falcon.dtsi" + / { compatible = "lantiq,easy98000", "lantiq,falcon"; @@ -107,4 +108,3 @@ reg = <0x51>; }; }; - diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98020V18.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98020V18.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts index 571e23454a..773a490019 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98020V18.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts @@ -3,7 +3,7 @@ #include #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon Reference Board V1.8"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98020.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98020.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts index 7a3ef418d0..397764aac4 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98020.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts @@ -3,7 +3,7 @@ #include #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon Reference Board"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98021.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98021.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts index 7eb40bde24..aa63268149 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98021.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts @@ -3,7 +3,7 @@ #include #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon HGU Reference Board"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98035SYNCE.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98035SYNCE.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts index df941cdb67..f1ecebec3b 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98035SYNCE.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts @@ -1,7 +1,7 @@ /dts-v1/; #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon SFP Stick with SyncE"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98035SYNCE1588.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY98035SYNCE1588.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts index a3abc6e707..98421174d3 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY98035SYNCE1588.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts @@ -1,7 +1,7 @@ /dts-v1/; #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon SFP Stick with SyncE/1588"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FALCON-MDU.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts similarity index 96% rename from target/linux/lantiq/files/arch/mips/boot/dts/FALCON-MDU.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts index c5da8b564f..130d49ebd7 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FALCON-MDU.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts @@ -3,7 +3,7 @@ #include #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon / Vinax MDU Board"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FALCON-SFP.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/FALCON-SFP.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts index 8d45de4ebe..880c4edca8 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FALCON-SFP.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts @@ -1,7 +1,7 @@ /dts-v1/; #include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" +#include "falcon_sflash-16m.dtsi" / { model = "Lantiq Falcon SFP Stick"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/falcon-sflash-16M.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi similarity index 100% rename from target/linux/lantiq/files/arch/mips/boot/dts/falcon-sflash-16M.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/vr9.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9.dtsi similarity index 71% rename from target/linux/lantiq/files/arch/mips/boot/dts/vr9.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9.dtsi index e8b87dbcc7..35b1f180a5 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/vr9.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9.dtsi @@ -202,6 +202,8 @@ "spi_frm"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; status = "disabled"; }; @@ -210,6 +212,149 @@ #gpio-cells = <2>; gpio-controller; reg = <0xe100b10 0xa0>; + + gphy0_led0_pins: gphy0-led0 { + mux { + lantiq,groups = "gphy0 led0"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy0_led1_pins: gphy0-led1 { + mux { + lantiq,groups = "gphy0 led1"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy0_led2_pins: gphy0-led2 { + mux { + lantiq,groups = "gphy0 led2"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy1_led0_pins: gphy1-led0 { + mux { + lantiq,groups = "gphy1 led0"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy1_led1_pins: gphy1-led1 { + mux { + lantiq,groups = "gphy1 led1"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy1_led2_pins: gphy1-led2 { + mux { + lantiq,groups = "gphy1 led2"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + mdio_pins: mdio { + mux { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + + nand_pins: nand { + mux-0 { + lantiq,groups = "nand cle", "nand ale", + "nand rd"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + mux-1 { + lantiq,groups = "nand rdy"; + lantiq,function = "ebu"; + lantiq,output = <0>; + lantiq,pull = <2>; + }; + }; + + nand_cs1_pins: nand-cs1 { + mux { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt1_pins: pci-gnt1 { + mux { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_req1_pins: pci-req1 { + mux { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + spi_pins: spi { + mux-0 { + lantiq,groups = "spi_di"; + lantiq,function = "spi"; + }; + mux-1 { + lantiq,groups = "spi_do", "spi_clk"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + spi_cs4_pins: spi-cs4 { + mux { + lantiq,groups = "spi_cs4"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + stp_pins: stp { + mux { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; }; stp: stp@e100bb0 { @@ -219,6 +364,9 @@ #gpio-cells = <2>; gpio-controller; + pinctrl-0 = <&stp_pins>; + pinctrl-names = "default"; + lantiq,shadow = <0xffffff>; lantiq,groups = <0x7>; lantiq,dsl = <0x0>; @@ -285,6 +433,8 @@ resets = <&reset0 21 16>, <&reset0 8 8>; reset-names = "switch", "ppe"; lantiq,phys = <&gphy0>, <&gphy1>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; }; mei@e116000 { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ASL56026.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts similarity index 93% rename from target/linux/lantiq/files/arch/mips/boot/dts/ASL56026.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts index 1c7f03c355..3d10f582b0 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ASL56026.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts @@ -119,18 +119,6 @@ lantiq,gphy-mode = ; }; -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; -}; - &localbus { flash@0 { compatible = "lantiq,nor"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7519RW22.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts similarity index 98% rename from target/linux/lantiq/files/arch/mips/boot/dts/ARV7519RW22.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts index f245fe370b..d6c521cfe7 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/ARV7519RW22.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts @@ -177,10 +177,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; pcie-rst { lantiq,pins = "io21"; lantiq,pull = <0>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VG3503J.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts similarity index 86% rename from target/linux/lantiq/files/arch/mips/boot/dts/VG3503J.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts index 2d52176430..e074147d66 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VG3503J.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts @@ -57,6 +57,10 @@ }; ð0 { + pinctrl-0 = <&mdio_pins>, + <&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>, + <&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>; + interface@0 { compatible = "lantiq,xrx200-pdi"; #address-cells = <1>; @@ -110,27 +114,6 @@ lantiq,gphy-mode = ; }; -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led0", "gphy0 led1", - "gphy0 led2", "gphy1 led0", - "gphy1 led1", "gphy1 led2"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - }; -}; - &localbus { flash@0 { compatible = "lantiq,nor"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22BRN.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts similarity index 96% rename from target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22BRN.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts index 5a33121d72..9f6f405a09 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22BRN.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "VGV7510KW22.dtsi" +#include "vr9_arcadyan_vgv7510kw22.dtsi" / { compatible = "arcadyan,vgv7510kw22-brn", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22NOR.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts similarity index 92% rename from target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22NOR.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts index 2accffaed7..613ff3782c 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22NOR.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "VGV7510KW22.dtsi" +#include "vr9_arcadyan_vgv7510kw22.dtsi" / { compatible = "arcadyan,vgv7510kw22-nor", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi similarity index 93% rename from target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi index f10a9dd8e6..017e473a04 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi @@ -107,6 +107,11 @@ }; ð0 { + pinctrl-0 = <&mdio_pins>, + <&gphy0_led0_pins>, + <&gphy1_led0_pins>, <&gphy1_led1_pins>; + pinctrl-names = "default"; + lan: interface@0 { compatible = "lantiq,xrx200-pdi"; #address-cells = <1>; @@ -186,21 +191,9 @@ &gpio { pinctrl-names = "default"; - pinctrl-0 = <&state_default>; + pinctrl-0 = <&state_default>, <&gphy0_led1_pins>; state_default: pinmux { - gphy-leds { - lantiq,groups = "gphy0 led0", "gphy0 led1", - "gphy1 led0", "gphy1 led1"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; pci-rst { lantiq,pins = "io21"; lantiq,open-drain = <0>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7519BRN.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts similarity index 96% rename from target/linux/lantiq/files/arch/mips/boot/dts/VGV7519BRN.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts index c51a44bb3d..051de0c23e 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7519BRN.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "VGV7519.dtsi" +#include "vr9_arcadyan_vgv7519.dtsi" / { compatible = "arcadyan,vgv7519-brn", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7519NOR.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts similarity index 92% rename from target/linux/lantiq/files/arch/mips/boot/dts/VGV7519NOR.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts index aa6a96156f..2121fbf41d 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7519NOR.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "VGV7519.dtsi" +#include "vr9_arcadyan_vgv7519.dtsi" / { compatible = "arcadyan,vgv7519-nor", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7519.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi similarity index 93% rename from target/linux/lantiq/files/arch/mips/boot/dts/VGV7519.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi index 0b3e72d3ab..e82407d7c3 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VGV7519.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi @@ -127,6 +127,9 @@ }; ð0 { + pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>; + pinctrl-names = "default"; + lan: interface@0 { compatible = "lantiq,xrx200-pdi"; #address-cells = <1>; @@ -209,30 +212,12 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; pci-rst { lantiq,pins = "io21"; lantiq,open-drain = <0>; lantiq,pull = <0>; lantiq,output = <1>; }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led0"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; }; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2-HYNIX.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts similarity index 84% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2-HYNIX.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts index c70f124db5..1aea98260a 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2-HYNIX.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "FRITZ3370-REV2.dtsi" +#include "vr9_avm_fritz3370-rev2.dtsi" / { compatible = "avm,fritz3370-rev2-hynix", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; @@ -13,6 +13,9 @@ bank-width = <2>; reg = <1 0x0 0x2000000>; + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + nand-ecc-mode = "soft"; nand-ecc-strength = <3>; nand-ecc-step-size = <256>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2-MICRON.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts similarity index 83% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2-MICRON.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts index 3aaea4cb6d..a19d168159 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2-MICRON.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "FRITZ3370-REV2.dtsi" +#include "vr9_avm_fritz3370-rev2.dtsi" / { compatible = "avm,fritz3370-rev2-micron", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; @@ -13,6 +13,9 @@ bank-width = <2>; reg = <1 0x0 0x2000000>; + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + nand-ecc-mode = "on-die"; partitions { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi similarity index 89% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi index f23d2d2cf5..bac27c3649 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi @@ -15,7 +15,7 @@ led-boot = &power_green; led-failsafe = &power_red; led-running = &power_green; - led-upgrade = &power_green; + led-upgrade = &power_red; led-dsl = &dsl; led-internet = &info_green; @@ -193,18 +193,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - - nand { - lantiq,groups = "nand cle", "nand ale", - "nand rd", "nand cs1", "nand rdy"; - lantiq,function = "ebu"; - lantiq,pull = <1>; - }; - phy-rst { lantiq,pins = "io37", "io44"; lantiq,pull = <0>; @@ -218,20 +206,6 @@ lantiq,output = <1>; }; }; - - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; }; &pcie0 { @@ -255,9 +229,6 @@ &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - flash@4 { compatible = "jedec,spi-nor"; reg = <4>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7360SL.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts similarity index 97% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7360SL.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts index 0fbe6396a8..012300ec57 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7360SL.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "FRITZ736X.dtsi" +#include "vr9_avm_fritz736x.dtsi" #include #include diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7362SL.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts similarity index 78% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7362SL.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts index cca79c926e..a061a482da 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7362SL.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include "FRITZ736X.dtsi" +#include "vr9_avm_fritz736x.dtsi" #include #include @@ -35,29 +35,7 @@ label = "fritz7362sl:green:dect"; }; -&gpio { - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; -}; - &state_default { - nand { - lantiq,groups = "nand ale", "nand cle", - "nand cs1", "nand rd", "nand rdy"; - lantiq,function = "ebu"; - }; - pcie-rst { lantiq,pins = "io21"; lantiq,open-drain = <1>; @@ -67,8 +45,6 @@ &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; flash@4 { #address-cells = <1>; @@ -103,6 +79,10 @@ lantiq,cs1 = <1>; bank-width = <1>; reg = <1 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + nand-ecc-mode = "on-die"; partitions { diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ736X.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi similarity index 96% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ736X.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi index 82546a3572..1553d2f7f4 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ736X.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/dts-v1/; #include "vr9.dtsi" @@ -17,7 +16,8 @@ led-boot = &power_green; led-failsafe = &power_red; led-running = &power_green; - led-upgrade = &power_green; + led-upgrade = &power_red; + led-dsl = &info_green; led-wifi = &wifi; }; @@ -155,11 +155,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - phy-rst { lantiq,pins = "io37", "io44"; lantiq,pull = <0>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7412.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts similarity index 88% rename from target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7412.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts index baf3d69fb5..43216d66be 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7412.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts @@ -11,13 +11,14 @@ model = "AVM FRITZ!Box 7412"; chosen { - bootargs = "console=ttyLTQ0,115200 mem=126M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; + bootargs = "console=ttyLTQ0,115200"; }; aliases { led-boot = &power_green; led-failsafe = &power_red; led-running = &power_green; + led-upgrade = &power_red; led-dsl = &info; led-wifi = &wifi; @@ -34,13 +35,13 @@ wps { label = "wps"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; linux,code = ; }; dect { label = "dect"; - gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -88,6 +89,9 @@ reg = <0 0x0 0x2000000>; lantiq,cs = <1>; + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -166,25 +170,11 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; pcie-rst { lantiq,pins = "io11"; lantiq,open-drain = <1>; lantiq,output = <1>; }; - nand-mux { - lantiq,groups = "nand cle", "nand ale", - "nand rd", "nand cs1", - "nand rdy"; - lantiq,function = "ebu"; - }; - nand-pins { - lantiq,pins = "io13", "io24", "io49"; - lantiq,pull = <1>; - }; }; }; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV5A.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts similarity index 93% rename from target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV5A.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts index c105f0a9ae..f6a2d9f6a7 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV5A.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts @@ -197,10 +197,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; pci_rst { lantiq,pins = "io21"; lantiq,output = <1>; @@ -218,19 +214,6 @@ lantiq,open-drain = <0>; lantiq,output = <1>; }; - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; }; }; @@ -240,6 +223,10 @@ lantiq,cs = <1>; bank-width = <2>; reg = <0x1 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + nand-on-flash-bbt; nand-ecc-strength = <3>; nand-ecc-step-size = <256>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/WBMR300.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts similarity index 93% rename from target/linux/lantiq/files/arch/mips/boot/dts/WBMR300.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts index 48f6dc71a1..4631ad4ffe 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/WBMR300.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts @@ -225,10 +225,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; phy-rst { lantiq,pins = "io42"; lantiq,pull = <0>; @@ -241,26 +237,11 @@ lantiq,output = <1>; }; }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; }; &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - flash@4 { compatible = "jedec,spi-nor"; reg = <4>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY80920NAND.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts similarity index 92% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY80920NAND.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts index f687edf54d..585521459b 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY80920NAND.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts @@ -1,7 +1,7 @@ /dts-v1/; -#include "EASY80920.dtsi" +#include "vr9_lantiq_easy80920.dtsi" / { compatible = "lantiq,easy80920-nand", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; @@ -19,6 +19,9 @@ bank-width = <2>; reg = <0 0x0 0x2000000>; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY80920NOR.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts similarity index 94% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY80920NOR.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts index 6ed6c5d427..c204c5e093 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY80920NOR.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "EASY80920.dtsi" +#include "vr9_lantiq_easy80920.dtsi" / { compatible = "lantiq,easy80920-nor", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY80920.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi similarity index 86% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY80920.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi index b7ccb4ed57..4fbc1ac496 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY80920.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi @@ -189,27 +189,8 @@ lantiq,groups = "exin3"; lantiq,function = "exin"; }; - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - nand { - lantiq,groups = "nand cle", "nand ale", - "nand rd", "nand rdy"; - lantiq,function = "ebu"; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; conf_out { - lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */ - "io4", "io5", "io6", /* stp */ - "io21", + lantiq,pins = "io21", "io33"; lantiq,open-drain; lantiq,pull = <0>; @@ -221,29 +202,13 @@ lantiq,output = <1>; }; conf_in { - lantiq,pins = "io39", /* exin3 */ - "io48"; /* nand rdy */ + lantiq,pins = "io39"; /* exin3 */ lantiq,pull = <2>; }; }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; }; &spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - status = "okay"; flash@4 { @@ -288,6 +253,11 @@ }; }; +&pci0 { + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; +}; + &stp { status = "okay"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/DM200.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts similarity index 86% rename from target/linux/lantiq/files/arch/mips/boot/dts/DM200.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts index 4796123c20..cdba656e49 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/DM200.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts @@ -118,30 +118,6 @@ lantiq,gphy-mode = ; }; -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; - - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; -}; - &pcie0 { status = "disabled"; }; @@ -149,9 +125,6 @@ &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - flash@4 { compatible = "jedec,spi-nor"; reg = <4>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/TDW8970.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts similarity index 78% rename from target/linux/lantiq/files/arch/mips/boot/dts/TDW8970.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts index 25eb3dac67..9b3055983a 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/TDW8970.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "TDW89X0.dtsi" +#include "vr9_tplink_tdw89x0.dtsi" / { compatible = "tplink,tdw8970", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/TDW8980.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts similarity index 94% rename from target/linux/lantiq/files/arch/mips/boot/dts/TDW8980.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts index 76875e735d..725aa759d2 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/TDW8980.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "TDW89X0.dtsi" +#include "vr9_tplink_tdw89x0.dtsi" / { compatible = "tplink,tdw8980", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/TDW89X0.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi similarity index 90% rename from target/linux/lantiq/files/arch/mips/boot/dts/TDW89X0.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi index 1a7d90a5bf..eabbc0257f 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/TDW89X0.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi @@ -103,6 +103,9 @@ }; ð0 { + pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>; + pinctrl-names = "default"; + lan: interface@0 { compatible = "lantiq,xrx200-pdi"; #address-cells = <1>; @@ -175,17 +178,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led1"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; phy-rst { lantiq,pins = "io42"; lantiq,pull = <0>; @@ -198,18 +190,6 @@ lantiq,output = <1>; }; }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; }; &pcie0 { @@ -236,9 +216,6 @@ &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - flash@4 { compatible = "jedec,spi-nor"; reg = <4>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VR200.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts similarity index 98% rename from target/linux/lantiq/files/arch/mips/boot/dts/VR200.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts index 8724e37b47..98f2282579 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VR200.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "VR200.dtsi" +#include "vr9_tplink_vr200.dtsi" / { compatible = "tplink,vr200", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VR200.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi similarity index 86% rename from target/linux/lantiq/files/arch/mips/boot/dts/VR200.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi index 3c04785314..77b4f0defb 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VR200.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi @@ -23,6 +23,9 @@ }; ð0 { + pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>; + pinctrl-names = "default"; + lan: interface@0 { compatible = "lantiq,xrx200-pdi"; #address-cells = <1>; @@ -95,17 +98,6 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led1"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; phy-rst { lantiq,pins = "io42"; lantiq,pull = <0>; @@ -118,16 +110,23 @@ lantiq,output = <1>; }; }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; +}; + +&pcie0 { + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + + wifi@0,0 { + reg = <0 0 0 0 0>; + mediatek,mtd-eeprom = <&radio 0x0000>; + big-endian; + ieee80211-freq-limit = <5000000 6000000>; + mtd-mac-address = <&romfile 0xf100>; + mtd-mac-address-increment = <2>; }; }; }; @@ -140,9 +139,6 @@ &spi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - flash@4 { compatible = "jedec,spi-nor"; reg = <4>; @@ -189,7 +185,7 @@ read-only; }; - partition@ff0000 { + radio: partition@ff0000 { reg = <0xff0000 0x10000>; label = "radio"; read-only; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/VR200v.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts similarity index 98% rename from target/linux/lantiq/files/arch/mips/boot/dts/VR200v.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts index 34805bb9f0..2e25a72a83 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/VR200v.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "VR200.dtsi" +#include "vr9_tplink_vr200.dtsi" / { compatible = "tplink,vr200v", "lantiq,xway", "lantiq,vr9"; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF1.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts similarity index 90% rename from target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF1.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts index 3159a5a244..4d7aac325b 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF1.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "P2812HNUFX.dtsi" +#include "vr9_zyxel_p-2812hnu-fx.dtsi" / { compatible = "zyxel,p-2812hnu-f1", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; @@ -30,6 +30,9 @@ bank-width = <2>; reg = <0 0x0 0x2000000>; + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF3.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts similarity index 89% rename from target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF3.dts rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts index f6e8fd8c83..7da1533809 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF3.dts +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "P2812HNUFX.dtsi" +#include "vr9_zyxel_p-2812hnu-fx.dtsi" / { compatible = "zyxel,p-2812hnu-f3", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; @@ -21,6 +21,9 @@ bank-width = <2>; reg = <0 0x0 0x800000>; + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUFX.dtsi b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi similarity index 82% rename from target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUFX.dtsi rename to target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi index 9956a5b89f..5f8392ca44 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUFX.dtsi +++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi @@ -111,6 +111,11 @@ }; ð0 { + pinctrl-0 = <&mdio_pins>, + <&gphy0_led0_pins>, <&gphy0_led2_pins>, + <&gphy1_led1_pins>, <&gphy1_led2_pins>; + pinctrl-names = "default"; + lan: interface@0 { compatible = "lantiq,xrx200-pdi"; #address-cells = <1>; @@ -196,39 +201,6 @@ lantiq,groups = "exin3"; lantiq,function = "exin"; }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led1", - "gphy0 led2", "gphy1 led2"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pci-in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; pci_rst { lantiq,pins = "io21"; lantiq,output = <1>; @@ -246,24 +218,15 @@ lantiq,open-drain = <0>; lantiq,output = <1>; }; - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; }; }; &pci0 { status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; }; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse.dtsi new file mode 100644 index 0000000000..f2845ee4ac --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse.dtsi @@ -0,0 +1,243 @@ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,ase"; + + aliases { + serial0 = &asc1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips4Kc"; + reg = <0>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + + regmap = <&rcu0>; + offset = <0x10>; + mask = <0x40000000>; + }; + + biu@1f800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1f800000 0x800000>; + ranges = <0x0 0x1f800000 0x7fffff>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0xc8>; + }; + + watchdog@803f0 { + compatible = "lantiq,wdt"; + reg = <0x803f0 0x10>; + }; + }; + + sram@1f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram", "simple-bus"; + reg = <0x1f000000 0x800000>; + ranges = <0x0 0x1f000000 0x7fffff>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + lantiq,eiu-irqs = <29 30 31>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + rcu0: rcu@203000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,ase-rcu", "simple-mfd", "syscon"; + reg = <0x203000 0x1000>; + ranges = <0x0 0x203000 0x100>; + big-endian; + + reset: reset-controller@10 { + compatible = "lantiq,danube-reset"; + reg = <0x10 4>, <0x14 4>; + + #reset-cells = <2>; + }; + + usb_phy: usb2-phy@18 { + compatible = "lantiq,ase-usb2-phy"; + reg = <0x18 4>; + status = "disabled"; + + resets = <&reset 4 4>; + reset-names = "ctrl"; + #phy-cells = <0>; + }; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xeefffff>; + reg = <0x10000000 0xef00000>; + + localbus: localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + spi: spi@e100800 { + compatible = "lantiq,ase-spi"; + reg = <0xe100800 0x100>; + interrupt-parent = <&icu0>; + interrupts = <24 25 26>; + interrupt-names = "spi_rx", "spi_tx", "spi_err", + "spi_frm"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; + status = "disabled"; + }; + + gptu@e100a00 { + compatible = "lantiq,gptu-xway"; + reg = <0xe100a00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <33 34 35 36 37 38>; + }; + + gpio: pinmux@e100b10 { + compatible = "lantiq,ase-pinctrl"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe100b10 0xa0>; + + asc_pins: asc-pins { + mux { + lantiq,groups = "asc"; + lantiq,function = "asc"; + }; + }; + + mdio_pins: mdio { + mux { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + + spi_pins: spi { + mux-0 { + lantiq,groups = "spi_di"; + lantiq,function = "spi"; + }; + mux-1 { + lantiq,groups = "spi_do", "spi_clk"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + spi_cs4_pins: spi-cs4 { + mux { + lantiq,groups = "spi_cs4"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + }; + + asc1: serial@e100c00 { + compatible = "lantiq,asc"; + reg = <0xe100c00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <72 74 75>; + pinctrl-0 = <&asc_pins>; + pinctrl-names = "default"; + }; + + mei@e116000 { + compatible = "lantiq,mei-xway"; + reg = <0xe116000 0x400>; + interrupt-parent = <&icu0>; + interrupts = <81>; + }; + + usb: usb@e101000 { + compatible = "lantiq,ase-usb"; + reg = <0xe101000 0x1000 + 0xe120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <39>; + dr_mode = "host"; + phys = <&usb_phy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + dma0: dma@e104100 { + compatible = "lantiq,dma-xway"; + reg = <0xe104100 0x800>; + }; + + ebu0: ebu@e105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xe105300 0x100>; + }; + + ppe@e234000 { + compatible = "lantiq,ppe-ase"; + reg = <0xe234000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <85>; + }; + + gsw: etop@e180000 { + compatible = "lantiq,etop-xway"; + reg = <0xe180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <105 109>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + }; + }; + + adsl { + compatible = "lantiq,adsl-ase"; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts new file mode 100644 index 0000000000..c5dd1600f4 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts @@ -0,0 +1,111 @@ +/dts-v1/; + +#include "amazonse.dtsi" + +/ { + compatible = "allnet,all0333cj", "lantiq,xway", "lantiq,ase"; + model = "Allnet ALL0333CJ DSL Modem"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &dsl; + led-internet = &online_green; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x1000000>; + }; + + leds { + compatible = "gpio-leds"; + + /* power led: red=off, green=on */ + power: power { + label = "all0333cj:green:power"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + lan: lan { + label = "all0333cj:green:lan"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + + dsl: dsl { + label = "all0333cj:green:dsl"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + online_green: online { + label = "all0333cj:green:online"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + online_red { + label = "all0333cj:red:online"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + keys_in { + lantiq,pins = "io0",/* "io25", */"io29"; + lantiq,pull = <2>; + lantiq,open-drain = <1>; + }; + }; +}; + +&gsw { + phy-mode = "mii"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x400000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "firmware"; + reg = <0x10000 0x3ef200>; + }; + + partition@3ff200 { + label = "uboot_env"; + reg = <0x3ff200 0xc00>; + read-only; + }; + + partition@3ffe00 { + label = "dummy_bits"; + reg = <0x3ffe00 0x200>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts new file mode 100644 index 0000000000..943b00f898 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts @@ -0,0 +1,153 @@ +/dts-v1/; + +#include "amazonse.dtsi" + +#include + +/ { + compatible = "netgear,dgn1000b", "lantiq,xway", "lantiq,ase"; + model = "Netgear DGN1000B"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &dsl; + led-internet = &online_green; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x1000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + dsl: dsl { + label = "dgn1000b:green:dsl"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + online_green: online { + label = "dgn1000b:green:online"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + online2 { + label = "dgn1000b:red:online"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + wps { + label = "dgn1000b:green:wps"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + power: power { + label = "dgn1000b:green:power"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + /* + power red is missing + */ + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + keys_in { + lantiq,pins = "io0",/* "io25", */"io29"; + lantiq,pull = <2>; + lantiq,open-drain = <1>; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mac-address = [ 00 11 22 33 44 55 ]; +}; + +&spi { + status = "okay"; + + flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <5000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x20000>; + label = "SPI (RO) U-Boot Image"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "ENV_MAC"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x10000>; + label = "DPF"; + read-only; + }; + + partition@40000 { + reg = <0x40000 0x10000>; + label = "NVRAM"; + read-only; + }; + + partition@500000 { + reg = <0x50000 0x003a0000>; + label = "kernel"; + }; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9.dtsi new file mode 100644 index 0000000000..d4afd23f7b --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9.dtsi @@ -0,0 +1,419 @@ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,ar9"; + + aliases { + serial0 = &asc1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips34K"; + reg = <0>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + + regmap = <&rcu0>; + offset = <0x10>; + mask = <0x40000000>; + }; + + biu@1f800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1f800000 0x800000>; + ranges = <0x0 0x1f800000 0x7fffff>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + /* TODO: AR9 should have ICU1 (like VR9) too */ + reg = <0x80200 0xc8>; + }; + + watchdog@803f0 { + compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt"; + reg = <0x803f0 0x10>; + + regmap = <&rcu0>; + }; + }; + + sram@1f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram", "simple-bus"; + reg = <0x1f000000 0x800000>; + ranges = <0x0 0x1f000000 0x7fffff>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + lantiq,eiu-irqs = <166 135 66 40 41 42>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + rcu0: rcu@203000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xrx100-rcu", "simple-mfd", "syscon"; + reg = <0x203000 0x1000>; + ranges = <0x0 0x203000 0x100>; + big-endian; + + reset: reset-controller@10 { + compatible = "lantiq,xrx100-reset", "lantiq,danube-reset"; + reg = <0x10 4>, <0x14 4>; + + #reset-cells = <2>; + }; + + usb_phy0: usb2-phy@18 { + compatible = "lantiq,xrx100-usb2-phy"; + reg = <0x18 4>; + status = "disabled"; + + resets = <&reset 4 4>; + reset-names = "ctrl"; + #phy-cells = <0>; + }; + + usb_phy1: usb2-phy@34 { + compatible = "lantiq,xrx100-usb2-phy"; + reg = <0x34 4>; + status = "disabled"; + + resets = <&reset 28 28>; + reset-names = "ctrl"; + #phy-cells = <0>; + }; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xeefffff>; + reg = <0x10000000 0xef00000>; + + localbus: localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + gptu@e100a00 { + compatible = "lantiq,gptu-xway"; + reg = <0xe100a00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <126 127 128 129 130 131>; + }; + + asc0: serial@e100400 { + compatible = "lantiq,asc"; + reg = <0xe100400 0x400>; + interrupt-parent = <&icu0>; + interrupts = <104 105 106>; + status = "disabled"; + }; + + spi: spi@e100800 { + compatible = "lantiq,xrx100-spi"; + reg = <0xe100800 0x100>; + interrupt-parent = <&icu0>; + interrupts = <22 23 24>; + interrupt-names = "spi_rx", "spi_tx", "spi_err", + "spi_frm"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; + status = "disabled"; + }; + + gpio: pinmux@e100b10 { + compatible = "lantiq,xrx100-pinctrl"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe100b10 0xa0>; + + mdio_pins: mdio { + mux { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + + nand_pins: nand { + mux-0 { + lantiq,groups = "nand cle", "nand ale", + "nand rd"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + mux-1 { + lantiq,groups = "nand rdy"; + lantiq,function = "ebu"; + lantiq,output = <0>; + lantiq,pull = <2>; + }; + }; + + nand_cs1_pins: nand-cs1 { + mux { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt1_pins: pci-gnt1 { + mux { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt2_pins: pci-gnt2 { + mux { + lantiq,groups = "gnt2"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt3_pins: pci-gnt3 { + mux { + lantiq,groups = "gnt3"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt4_pins: pci-gnt4 { + mux { + lantiq,groups = "gnt4"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_req1_pins: pci-req1 { + mux { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req2_pins: pci-req2 { + mux { + lantiq,groups = "req2"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req3_pins: pci-req3 { + mux { + lantiq,groups = "req3"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req4_pins: pci-req4 { + mux { + lantiq,groups = "req4"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + spi_pins: spi { + mux-0 { + lantiq,groups = "spi_di"; + lantiq,function = "spi"; + }; + mux-1 { + lantiq,groups = "spi_do", "spi_clk"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + spi_cs4_pins: spi-cs4 { + mux { + lantiq,groups = "spi_cs4"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + stp_pins: stp { + mux { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; + }; + + stp: stp@e100bb0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xe100bb0 0x40>; + + pinctrl-0 = <&stp_pins>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + asc1: serial@e100c00 { + compatible = "lantiq,asc"; + reg = <0xe100c00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + usb0: usb@e101000 { + compatible = "lantiq,arx100-usb"; + reg = <0xe101000 0x1000 + 0xe120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <62 91>; + dr_mode = "host"; + phys = <&usb_phy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@e106000 { + compatible = "lantiq,arx100-usb"; + reg = <0xe106000 0x1000 + 0xe1e0000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <91>; + dr_mode = "host"; + phys = <&usb_phy1>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + deu@e103100 { + compatible = "lantiq,deu-arx100"; + reg = <0xe103100 0xf00>; + }; + + dma0: dma@e104100 { + compatible = "lantiq,dma-xway"; + reg = <0xe104100 0x800>; + }; + + ebu0: ebu@e105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xe105300 0x100>; + }; + + mei@e116000 { + compatible = "lantiq,mei-xway"; + reg = <0xe116000 0x9c>; + interrupt-parent = <&icu0>; + interrupts = <63>; + }; + + gsw: etop@e180000 { + compatible = "lantiq,etop-xway"; + reg = <0xe180000 0x40000 + 0xe108000 0x200>; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + mac-address = [ 00 11 22 33 44 55 ]; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + }; + + ppe@e234000 { + compatible = "lantiq,ppe-arx100"; + reg = <0xe234000 0x3ffd>; + interrupt-parent = <&icu0>; + interrupts = <96>; + }; + + pci0: pci@e105400 { + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xe105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + req-mask = <0x1>; + }; + }; + + adsl { + compatible = "lantiq,adsl-arx100"; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts new file mode 100644 index 0000000000..aa825abd9f --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts @@ -0,0 +1,169 @@ +/dts-v1/; + +#include "ar9.dtsi" + +#include + +/ { + compatible = "avm,fritz7312", "lantiq,xway", "lantiq,ar9"; + model = "AVM FRITZ!Box 7312"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &info_green; + led-wifi = &wlan; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wlan { + label = "wlan"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + dect { + label = "dect"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power: power { + label = "fritz7312:green:power"; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + voice { + label = "fritz7312:green:fon"; + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + dect { + label = "fritz7312:green:dect"; + gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + }; + wlan: wlan { + label = "fritz7312:green:wlan"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; + info_green: info_green { + label = "fritz7312:green:info"; + gpios = <&gpio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ar8030-intr { + lantiq,groups = "exin3"; + lantiq,function = "exin"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + ar8030-clk { + lantiq,groups = "clkout2"; + lantiq,output = <1>; + lantiq,open-drain; + }; + ar8030-rst { + lantiq,pins = "io34"; + lantiq,output = <1>; + lantiq,pull = <2>; + lantiq,open-drain; + }; + }; +}; + +&gsw { + phy-mode = "rmii"; + phy-handle = <&phy0>; + mtd-mac-address = <&ath9k_cal 0xa91>; + mtd-mac-address-increment = <(-2)>; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ath9k_cal: partition@0 { + label = "urlader"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0xf60000>; + }; + + partition@f80000 { + label = "tffs (1)"; + reg = <0xf80000 0x40000>; + read-only; + }; + + partition@fc0000 { + label = "tffs (2)"; + reg = <0xfc0000 0x40000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_gnt3_pins>, <&pci_gnt4_pins>, + <&pci_req1_pins>, <&pci_req2_pins>, + <&pci_req4_pins>; + pinctrl-names = "default"; + + req-mask = <0xf>; + gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>; + + wifi@0,0 { + compatible = "pci0,0"; + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts new file mode 100644 index 0000000000..424b778bb4 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts @@ -0,0 +1,151 @@ +/dts-v1/; + +#include "ar9.dtsi" + +#include + +/ { + compatible = "avm,fritz7320", "lantiq,xway", "lantiq,ar9"; + model = "AVM FRITZ!Box 7320"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &info_green; + led-wifi = &wlan; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + dect { + label = "dect"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power: power { + label = "fritz7320:green:power"; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + voice { + label = "fritz7320:green:fon"; + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + dect { + label = "fritz7320:green:dect"; + gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + }; + wlan: wlan { + label = "fritz7320:green:wlan"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; + info_green: info_green { + label = "fritz7320:green:info"; + gpios = <&gpio 35 GPIO_ACTIVE_LOW>; + }; + info_red { + label = "fritz7320:red:info"; + gpios = <&gpio 45 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&ath9k_cal 0xa91>; + mtd-mac-address-increment = <(-2)>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ath9k_cal: partition@0 { + label = "urlader"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0xf60000>; + }; + + partition@f80000 { + label = "tffs (1)"; + reg = <0xf80000 0x40000>; + read-only; + }; + + partition@fc0000 { + label = "tffs (2)"; + reg = <0xfc0000 0x40000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_gnt3_pins>, <&pci_gnt4_pins>, + <&pci_req1_pins>, <&pci_req2_pins>, + <&pci_req3_pins>, <&pci_req4_pins>; + + req-mask = <0xf>; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@0,0 { + compatible = "pci0,0"; + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts new file mode 100644 index 0000000000..044ae2b417 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts @@ -0,0 +1,191 @@ +/dts-v1/; + +#include "ar9.dtsi" + +#include + +/ { + compatible = "bt,homehub-v3a", "lantiq,xway", "lantiq,ar9"; + model = "BT Home Hub 3A"; /* SoC: Lantiq ar9 @ 333MHz */ + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_orange; + led-failsafe = &power_red; + led-running = &power_blue; + led-upgrade = &power_blue; + + led-dsl = &broadband_blue; + led-wifi = &wireless_blue; + }; + + memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + restart { + label = "restart"; + gpios = <&gpio 52 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 53 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + wireless-red { + label = "bthomehubv3a:red:wireless"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + wireless-orange { + label = "bthomehubv3a:orange:wireless"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + wireless_blue: wireless-blue { + label = "bthomehubv3a:blue:wireless"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + + broadband-red { + label = "bthomehubv3a:red:broadband"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + broadband-orange { + label = "bthomehubv3a:orange:broadband"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + broadband_blue: broadband-blue { + label = "bthomehubv3a:blue:broadband"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + + power_red: power-red { + label = "bthomehubv3a:red:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + power_orange: power-orange { + label = "bthomehubv3a:orange:power"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_blue: power-blue { + label = "bthomehubv3a:blue:power"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + }; + }; +}; + +&gsw { + phy-mode = "rgmii"; +}; + +&localbus { + flash@1 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ + compatible = "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <1 0x0 0x2000000 >; + req-mask = <0x1>; /* PCI request lines to mask during NAND access */ + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "preboot"; + reg = <0x00000 0x8000>; + read-only; + }; + partition@8000 { + label = "u-boot"; + reg = <0x8000 0x05c000>; + read-only; + }; + partition@64000 { + label = "uboot_env"; + reg = <0x64000 0x004000>; + }; + ath9k_cal: partition@68000 { + label = "art-copy"; + reg = <0x68000 0x004000>; + }; + partition@6c000 { + label = "kernel"; + reg = <0x6c000 0x200000>; + }; + partition@26c000 { + label = "ubi"; + reg = <0x26c000 0x1d94000>; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@7000 { + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts new file mode 100644 index 0000000000..5419215dc6 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts @@ -0,0 +1,197 @@ +/dts-v1/; + +#include "ar9.dtsi" + +#include + +/ { + compatible = "buffalo,wbmr-hp-g300h", "lantiq,xway", "lantiq,ar9"; + model = "Buffalo WBMR-HP-G300H"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + led-internet = &online_green; + led-usb = &led_usb; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + eject { + label = "eject"; + gpios = <&gpio 34 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + movie { + label = "movie"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_green: power { + label = "wbmr:green:power"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_red: power2 { + label = "wbmr:red:power"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + security { + label = "wbmr:yellow:security"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "wbmr:green:wireless"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "wbmr:green:dsl"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + online_green: online { + label = "wbmr:green:internet"; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + online2 { + label = "wbmr:red:internet"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + }; + movie { + label = "wbmr:blue:movie"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "wbmr:green:usb"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 36 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci-in { + lantiq,groups = "req1"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci-out { + lantiq,groups = "gnt1"; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&gsw { + phy-mode = "rgmii"; + mtd-mac-address = <&boardconfig 0x10024>; +}; + +&pci0 { + status = "okay"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x60000 0x1f20000>; + }; + + boardconfig: partition@1fc0000 { + label = "board"; + reg = <0x1fc0000 0x20000>; + read-only; + }; + + partition@1fe0000 { + label = "calibration"; + reg = <0x1fe0000 0x20000>; + read-only; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts new file mode 100644 index 0000000000..cbc99fe620 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "ar9_netgear_dgn3500.dtsi" + +/ { + compatible = "netgear,dgn3500", "lantiq,xway", "lantiq,ar9"; + model = "Netgear DGN3500"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi new file mode 100644 index 0000000000..a3dbbbdfad --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi @@ -0,0 +1,185 @@ +#include "ar9.dtsi" + +#include + +/ { + chosen { + bootargs = "root= console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + led-internet = &internet; + led-usb = &led_usb; + led-wifi = &wifi_green; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + rtl8366rb { + compatible = "realtek,rtl8366rb"; + gpio-sda = <&gpio 35 GPIO_ACTIVE_HIGH>; + gpio-sck = <&gpio 37 GPIO_ACTIVE_HIGH>; + + realtek,initvals = < + 0x0000 0x0830 + 0x0400 0x8130 + 0x000a 0x83ed + 0x0f51 0x0017 + 0x02f5 0x0048 + 0x02fa 0xffdf + 0x02fb 0xffe0 + 0x0450 0x0000 + 0x0401 0x0000 + 0x0431 0x0960 + >; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 36 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 53 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + internet: internet { + label = "dgn3500:green:internet"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + internet2 { + label = "dgn3500:red:internet"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "dgn3500:green:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "dgn3500:green:usb"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + power_green: power { + label = "dgn3500:green:power"; + gpios = <&gpio 34 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_red: power2 { + label = "dgn3500:red:power"; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + }; + wifi_green: wifi { + label = "dgn3500:green:wireless"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + wifi2 { + label = "dgn3500:amber:wireless"; + gpios = <&gpio 51 GPIO_ACTIVE_LOW>; + }; + wps { + label = "dgn3500:green:wps"; + gpios = <&gpio 52 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + }; +}; + +&gsw { + phy-mode = "mii"; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@168c,0029 { + compatible = "pci168c,0029"; + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + }; +}; + +&spi { + status = "okay"; + + flash@4 { + compatible = "jedec,spi-nor"; + reg = <4>; + spi-max-frequency = <20000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x10000>; + label = "uboot"; + read-only; + }; + + partition@10000 { + reg = <0x10000 0x10000>; + label = "uboot-env"; + read-only; + }; + + ath9k_cal: partition@20000 { + reg = <0x20000 0x10000>; + label = "calibration"; + read-only; + }; + + partition@50000 { + reg = <0x50000 0xfa0000>; + label = "firmware"; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts new file mode 100644 index 0000000000..b69613e48f --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "ar9_netgear_dgn3500.dtsi" + +/ { + compatible = "netgear,dgn3500b", "lantiq,xway", "lantiq,ar9"; + model = "Netgear DGN3500B"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts new file mode 100644 index 0000000000..9b640e0327 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts @@ -0,0 +1,172 @@ +/dts-v1/; + +#include "ar9.dtsi" + +#include + +/ { + compatible = "zte,h201l", "lantiq,xway", "lantiq,ar9"; + model = "ZTE H210L"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_green; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + led-internet = &online; + led-usb = &led_usb; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 53 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 55 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_green: power { + label = "h201l:green:power"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + online: online { + label = "h201l:green:internet"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "h201l:green:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + phone { + label = "h201l:green:phone"; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + }; + wps { + label = "h201l:green:wps"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "h201l:green:wlan"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "h201l:green:usb"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; + }; + usb { + gpio-export,name = "usb"; + gpio-export,output = <1>; + gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; + }; + wifi { + gpio-export,name = "wifi"; + gpio-export,output = <1>; + gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 36 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + }; +}; + +&gsw { + phy-mode = "rgmii"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "uboot_env"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "firmware"; + reg = <0x30000 0x7d0000>; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts new file mode 100644 index 0000000000..79896c6478 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts @@ -0,0 +1,178 @@ +/dts-v1/; + +#include "ar9.dtsi" + +#include + +/ { + compatible = "zyxel,p-2601hn", "lantiq,xway", "lantiq,ar9"; + model = "ZyXEL P-2601HN-Fx"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + led-internet = &online; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 53 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_green: power { + label = "p2601hnfx:green:power"; + gpios = <&stp 11 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_red: power2 { + label = "p2601hnfx:red:power"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; + online: online { + label = "p2601hnfx:green:internet"; + gpios = <&stp 13 GPIO_ACTIVE_LOW>; + }; + online2 { + label = "p2601hnfx:red:internet"; + gpios = <&stp 12 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "p2601hnfx:green:dsl"; + gpios = <&stp 14 GPIO_ACTIVE_LOW>; + }; + phone { + label = "p2601hnfx:green:phone"; + gpios = <&stp 9 GPIO_ACTIVE_LOW>; + }; + phone2 { + label = "p2601hnfx:orange:phone"; + gpios = <&stp 8 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "p2601hnfx:green:wireless"; + gpios = <&stp 15 GPIO_ACTIVE_LOW>; + }; + wifi2 { + label = "p2601hnfx:orange:wireless"; + gpios = <&stp 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 50 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gsw { + phy-mode = "rmii"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xfa0000>; + }; + }; + }; +}; + +&pci0 { + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; +}; + +&stp { + status = "okay"; + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube.dtsi new file mode 100644 index 0000000000..eae613e008 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube.dtsi @@ -0,0 +1,325 @@ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,danube"; + + aliases { + serial0 = &asc1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + + regmap = <&rcu0>; + offset = <0x10>; + mask = <0x40000000>; + }; + + biu@1f800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1f800000 0x800000>; + ranges = <0x0 0x1f800000 0x7fffff>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + /* + * There is a second ICU, but the SoC is not SMP + * capable. + */ + reg = <0x80200 0xc8>; + }; + + watchdog@803f0 { + compatible = "lantiq,wdt"; + reg = <0x803f0 0x10>; + }; + }; + + sram@1f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram", "simple-bus"; + reg = <0x1f000000 0x800000>; + ranges = <0x0 0x1f000000 0x7fffff>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + lantiq,eiu-irqs = <166 135 66>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + vmmc: vmmc@107000 { + status = "disabled"; + compatible = "lantiq,vmmc-xway"; + reg = <0x107000 0x400>; + interrupt-parent = <&icu0>; + interrupts = <150 151 152 153 154 155>; + }; + + rcu0: rcu@203000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,danube-rcu", "simple-mfd", "syscon"; + reg = <0x203000 0x1000>; + ranges = <0x0 0x203000 0x100>; + big-endian; + + reset: reset-controller@10 { + compatible = "lantiq,danube-reset"; + reg = <0x10 4>, <0x14 4>; + + #reset-cells = <2>; + }; + + usb_phy: usb2-phy@18 { + compatible = "lantiq,danube-usb2-phy"; + reg = <0x18 4>; + status = "disabled"; + + resets = <&reset 4 4>; + reset-names = "ctrl"; + #phy-cells = <0>; + }; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xeefffff>; + reg = <0x10000000 0xef00000>; + + localbus: localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + gptu@e100a00 { + compatible = "lantiq,gptu-xway"; + reg = <0xe100a00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <126 127 128 129 130 131>; + }; + + gpios: stp@e100bb0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xe100bb0 0x40>; + + pinctrl-0 = <&stp_pins>; + pinctrl-names = "default"; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + status = "disabled"; + }; + + asc0: serial@e100400 { + compatible = "lantiq,asc"; + reg = <0xe100400 0x400>; + interrupt-parent = <&icu0>; + interrupts = <104 105 106>; + status = "disabled"; + }; + + gpio: pinmux@e100b10 { + compatible = "lantiq,danube-pinctrl"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe100b10 0xa0>; + + nand_pins: nand { + mux-0 { + lantiq,groups = "nand cle", "nand ale", + "nand rd"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + mux-1 { + lantiq,groups = "nand rdy"; + lantiq,function = "ebu"; + lantiq,output = <0>; + lantiq,pull = <2>; + }; + }; + + nand_cs1_pins: nand-cs1 { + mux { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt1_pins: pci-gnt1 { + mux { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt2_pins: pci-gnt2 { + mux { + lantiq,groups = "gnt2"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_req1_pins: pci-req1 { + mux { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + pci_req2_pins: pci-req2 { + mux { + lantiq,groups = "req2"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + stp_pins: stp { + mux { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; + }; + + asc1: serial@e100c00 { + compatible = "lantiq,asc"; + reg = <0xe100c00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + usb: usb@e101000 { + compatible = "lantiq,danube-usb"; + reg = <0xe101000 0x1000 + 0xe120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <62>; + dr_mode = "host"; + phys = <&usb_phy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + deu@e103100 { + compatible = "lantiq,deu-danube"; + reg = <0xe103100 0xf00>; + }; + + dma0: dma@e104100 { + compatible = "lantiq,dma-xway"; + reg = <0xe104100 0x800>; + }; + + ebu0: ebu@e105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xe105300 0x100>; + }; + + mei@e116000 { + compatible = "lantiq,mei-xway"; + reg = <0xe116000 0x400>; + interrupt-parent = <&icu0>; + interrupts = <63>; + }; + + gsw: etop@e180000 { + compatible = "lantiq,etop-xway"; + reg = <0xe180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <73 78>; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + ppe@e234000 { + compatible = "lantiq,ppe-danube"; + reg = <0xe234000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <96>; + }; + + pci0: pci@e105400 { + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xe105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */ + req-mask = <0x1>; /* GNT1 */ + }; + }; + + adsl { + compatible = "lantiq,adsl-danube"; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts new file mode 100644 index 0000000000..19a44d5f6d --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts @@ -0,0 +1,214 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv4510pw", "lantiq,xway", "lantiq,danube"; + model = "Wippies, Elisa"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power2; + led-running = &power; + led-upgrade = &power; + + led-dsl = &adsl; + led-internet = &internet; + led-usb = &led_usb; + led-usb2 = &led_usb2; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power: power { + label = "power"; + gpios = <&gpios 21 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + power2: power2 { + label = "power2"; + gpios = <&gpios 20 GPIO_ACTIVE_HIGH>; + }; + lan1 { + label = "lan1"; + gpios = <&gpios 19 GPIO_ACTIVE_HIGH>; + }; + lan2 { + label = "lan2"; + gpios = <&gpios 18 GPIO_ACTIVE_HIGH>; + }; + lan3 { + label = "lan3"; + gpios = <&gpios 17 GPIO_ACTIVE_HIGH>; + }; + lan4 { + label = "lan4"; + gpios = <&gpios 16 GPIO_ACTIVE_HIGH>; + }; + wifi: wifi { + label = "wifi"; + gpios = <&gpios 15 GPIO_ACTIVE_HIGH>; + }; + adsl: adsl { + label = "adsl"; + gpios = <&gpios 14 GPIO_ACTIVE_HIGH>; + }; + internet: internet { + label = "internet"; + gpios = <&gpios 13 GPIO_ACTIVE_HIGH>; + }; + internet2 { + label = "internet2"; + gpios = <&gpios 12 GPIO_ACTIVE_HIGH>; + }; + voip { + label = "voip"; + gpios = <&gpios 11 GPIO_ACTIVE_HIGH>; + }; + phone { + label = "phone"; + gpios = <&gpios 10 GPIO_ACTIVE_HIGH>; + }; + phone2 { + label = "phone2"; + gpios = <&gpios 9 GPIO_ACTIVE_HIGH>; + }; + led_usb: usb { + label = "usb"; + gpios = <&gpios 8 GPIO_ACTIVE_HIGH>; + }; + led_usb2: usb2 { + label = "usb2"; + gpios = <&gpios 7 GPIO_ACTIVE_HIGH>; + }; + usb3 { + label = "usb3"; + gpios = <&gpios 6 GPIO_ACTIVE_HIGH>; + }; + unlabeled { + label = "unlabeled"; + gpios = <&gpios 5 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu a23"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + exin { + lantiq,groups = "exin1", "exin2"; + lantiq,function = "exin"; + lantiq,output = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + buttons { + lantiq,pins = "io3", "io14"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + }; +}; + +&gpios { + status = "okay"; + lantiq,groups = <0x7>; +}; + +&gsw { + phy-mode = "rmii"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + + lantiq,noxip; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xfa0000>; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + interrupt-map = < + 0x6000 0 0 1 &icu0 135 + 0x7800 0 0 1 &icu0 66 + 0x7800 0 0 2 &icu0 66 + 0x7800 0 0 3 &icu0 66 + >; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + req-mask = <0x7>; +}; + +&vmmc { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts new file mode 100644 index 0000000000..ff34068005 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "danube_arcadyan_arv4518pwr01.dtsi" + +/ { + compatible = "arcadyan,arv4518pwr01", "lantiq,xway", "lantiq,danube"; + model = "SMC7908A-ISP"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi new file mode 100644 index 0000000000..dcae06d894 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi @@ -0,0 +1,200 @@ +#include "danube.dtsi" + +#include + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &dsl; + led-internet = &online; + led-usb = &led_usb; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + ath5k_eep { + compatible = "ath5k,eeprom"; + ath,eep-flash = <&boardconfig 0x400>; + ath,mac-offset = <0x16>; + ath,mac-increment = <1>; + ath,eep-swap; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power: power { + label = "power"; + gpios = <&gpio 3 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + dsl: dsl { + label = "dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + online: online { + label = "online"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "wifi"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + wps { + label = "wps"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; + dsl2 { + label = "dsl2"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "usb"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; + voice { + label = "voice"; + gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; /* 64 KB */ + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; /* 64 KB */ + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + boardconfig: partition@400000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x0>; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>, + <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + req-mask = <0xf>; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts new file mode 100644 index 0000000000..b261a2fa91 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "danube_arcadyan_arv4518pwr01.dtsi" + +/ { + compatible = "arcadyan,arv4518pwr01a", "lantiq,xway", "lantiq,danube"; + model = "SMC7908A-ISP, Airties WAV-221"; +}; + +&pci0 { + lantiq,external-clock; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts new file mode 100644 index 0000000000..8e5301ddc9 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts @@ -0,0 +1,205 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv4519pw", "lantiq,xway", "lantiq,danube"; + model = "Vodafone Netfaster IAD 2, Pirelli P.RG A4201G"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + led-internet = &internet_green; + led-usb = &led_usb; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_green: power { + label = "arv4519pw:green:power"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_red: power2 { + label = "arv4519pw:red:power"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv4519pw:green:wlan"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "arv4519pw:green:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + internet_green: online { + label = "arv4519pw:green:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + online2 { + label = "arv4519pw:red:internet"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "arv4519pw:green:usb"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; + voip { + label = "arv4519pw:green:voip"; + gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; + }; + fxs1 { + label = "arv4519pw:green:phone1"; + gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; + }; + fxs2 { + label = "arv4519pw:green:phone2"; + gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; + }; + fxo { + label = "arv4519pw:green:line"; + gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + }; + wps2 { + label = "arv4519pw:green:wps"; + gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; + }; + wps { + label = "arv4519pw:orange:wps"; + gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; + }; + wps3 { + label = "arv4519pw:red:wps"; + gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + boardconfig: partition@3f0000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x400>; + }; +}; + +&pci0 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + req-mask = <0xf>; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts new file mode 100644 index 0000000000..b59477cb19 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts @@ -0,0 +1,222 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv4520pw", "lantiq,xway", "lantiq,danube"; + model = "Easybox 800, WAV-281"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_blue; + led-failsafe = &power_red; + led-running = &power_blue; + led-upgrade = &power_blue; + + led-dsl = &dsl; + led-internet = &internet_blue; + led-usb = &led_usb; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "wps"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_blue: power { + label = "arv4520pw:blue:power"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + dsl: dsl { + label = "arv4520pw:blue:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + internet_blue: internet { + label = "arv4520pw:blue:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + power_red: power2 { + label = "arv4520pw:red:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + wps { + label = "arv4520pw:yellow:wps"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; + wps2 { + label = "arv4520pw:red:wps"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + /* + wps green is missing + */ + fxs1 { + label = "arv4520pw:blue:telefon1"; + gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; + }; + fxs2 { + label = "arv4520pw:blue:telefon2"; + gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; + }; + isdn { + label = "arv4520pw:blue:isdn"; + gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; + }; + fxo { + label = "arv4520pw:blue:line"; + gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + }; + voice { + label = "arv4520pw:blue:sprache"; + gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "arv4520pw:blue:usb"; + gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv4520pw:blue:wifi"; + gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; + }; + internet2 { + label = "arv4520pw:red:internet"; + gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; + }; + /* + info is missing + */ + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; +}; + +&gsw { + /* gpiomm 10 - switch */ + phy-mode = "rmii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "uboot_env"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "firmware"; + reg = <0x30000 0x3c0000>; + }; + + boardconfig: partition@7f0000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x400>; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH + &gpiomm 7 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts new file mode 100644 index 0000000000..cceb42164e --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts @@ -0,0 +1,151 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv4525pw", "lantiq,xway", "lantiq,danube"; + model = "Speedport W501V Typ A"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + /* we dont have a power led, lets use the online led */ + led-boot = &online; + led-failsafe = &online; + + led-dsl = &dsl; + led-internet = &online; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + ath5k_eep { + compatible = "ath5k,eeprom"; + ath,eep-flash = <&boardconfig 0x400>; + ath,mac-offset = <0x0>; + ath,eep-swap; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + fxo { + label = "arv4525pw:green:festnetz"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + fxs { + label = "arv4525pw:green:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "arv4525pw:green:t-dsl"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv4525pw:green:wlan"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + online: online { + label = "arv4525pw:green:online"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + relay { + lantiq,pins = "io31"; + lantiq,output = <1>; + }; + }; +}; + +/* #define ARV4525PW_PHYRESET 13 */ +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + boardconfig: partition@400000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +/* #define ARV4525PW_RELAY 31 */ +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts new file mode 100644 index 0000000000..eecff4bb0b --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts @@ -0,0 +1,240 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv452cqw", "lantiq,xway", "lantiq,danube"; + model = "Arcor 801"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_blue; + led-failsafe = &power_red; + led-running = &power_blue; + led-upgrade = &power_blue; + + led-dsl = &dsl_blue; + led-usb = &led_usb; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + ath5k_eep { + compatible = "ath5k,eeprom"; + ath,eep-flash = <&boardconfig 0x400>; + ath,mac-offset = <0x0>; + ath,eep-swap; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power_blue: power0 { + label = "arv452cqw:blue:power"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + dsl_blue: dsl { + label = "arv452cqw:blue:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + isdn { + label = "arv452cqw:blue:isdn"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + power_red: power1 { + label = "arv452cqw:red:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + wps { + label = "arv452cqw:blue:wps"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; + wps1 { + label = "arv452cqw:yellow:wps"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + fxs1 { + label = "arv452cqw:blue:telefon1"; + gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; + }; + fxs2 { + label = "arv452cqw:blue:telefon2"; + gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; + }; + wps2 { + label = "arv452cqw:red:wps"; + gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; + }; + fxo { + label = "arv452cqw:blue:line"; + gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + }; + voice { + label = "arv452cqw:blue:sprache"; + gpios = <&gpiomm 4 1>; + }; + led_usb: usb { + label = "arv452cqw:blue:usb"; + gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv452cqw:blue:wlan"; + gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; + }; + /* + internet blue and internet red are missing + dsl2 and dsl3 are not referenced in manual + */ + dsl2 { + label = "arv452cqw:yellow:dsl"; + gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; + }; + dsl3 { + label = "arv452cqw:red:dsl"; + gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io3", "io5", "io6", "io7", "io9"; + lantiq,output = <1>; + }; + }; +}; + +/* +#define ARV452CPW_SWITCH_RESET 110 +*/ +&gsw { + phy-mode = "rmii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x400000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + boardconfig: partition@3f0000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x77f>; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH + &gpiomm 7 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts new file mode 100644 index 0000000000..9e4216033b --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts @@ -0,0 +1,162 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv7506pw11", "lantiq,xway", "lantiq,danube"; + model = "Alice/O2 IAD 4421"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power_red; + led-running = &power; + led-upgrade = &power; + + led-dsl = &dsl; + led-internet = &internet; + led-wifi = &wlan; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + wlan: wlan { + label = "arv7506pw11:green:wlan"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + power: power { + label = "arv7506pw11:green:power"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + dsl: dsl { + label = "arv7506pw11:green:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + internet: internet { + label = "arv7506pw11:green:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + power_red: power_red { + label = "arv7506pw11:red:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + internet_red { + label = "arv7506pw11:red:internet"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; + info { + label = "arv7506pw11:green:info"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + telefon { + label = "arv7506pw11:green:telefon"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + info_red { + label = "arv7506pw11:red:info"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; +}; + +/* GPIO 19: switch reset */ +&gsw { + phy-mode = "rmii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7a0000>; + }; + + boardconfig: partition@7f0000 { + label = "board_config"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@1814,3592 { + compatible = "pci1814,3592"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + ralink,mtd-eeprom-swap; + mtd-mac-address = <&boardconfig 0x16>; + mtd-mac-address-increment = <1>; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts new file mode 100644 index 0000000000..e5fd05fe40 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts @@ -0,0 +1,198 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv7510pw22", "lantiq,xway", "lantiq,danube"; + model = "Astoria Networks ARV7510PW22"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &internet; + led-usb = &umts; + led-wifi = &wlan; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + restart { + label = "restart"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power: power { + label = "power"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + internet: internet { + label = "internet"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + wlan: wlan { + label = "wlan"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + umts: 3g { + label = "3g"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + message { + label = "message"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + pins_out { + lantiq,pins = "io2", "io4", "io8", "io9", "io10", "io15", "io20"; + lantiq,output = <1>; + }; + pins_in { + lantiq,pins = "io11", "io12", "io28"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gsw { + /* Switch reset 19 */ + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xf80000>; + }; + + boardconfig: partition@fe0000 { + label = "board_config"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + interrupt-map = < + 0x7000 0 0 1 &icu0 30 + 0x7800 0 0 1 &icu0 135 + 0x7800 0 0 2 &icu0 135 + 0x7800 0 0 3 &icu0 135 + >; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + req-mask = <0x3>; + + wifi@1814,3592 { + compatible = "pci1814,3592"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + ralink,mtd-eeprom-swap; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts new file mode 100644 index 0000000000..ae0d27a042 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts @@ -0,0 +1,233 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv7518pw", "lantiq,xway", "lantiq,danube"; + model = "Astoria Networks ARV7518PW"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + led-internet = &online_green; + led-usb = &led_usb; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power_green: power { + label = "arv7518pw:green:power"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + dsl: dsl { + label = "arv7518pw:green:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + online_green: online { + label = "arv7518pw:green:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv7518pw:green:wlan"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + power_red: power2 { + label = "arv7518pw:red:power"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; + online2 { + label = "arv7518pw:red:internet"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "arv7518pw:green:usb"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; + voice { + label = "arv7518pw:green:voip"; + gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; + }; + fxs1 { + label = "arv7518pw:green:phone1"; + gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; + }; + fxs2 { + label = "arv7518pw:green:phone2"; + gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; + }; + unlabeled { + label = "arv7518pw:amber:unlabeled"; + gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + }; + wps { + label = "arv7518pw:amber:wps"; + gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; + }; + wps2 { + label = "arv7518pw:green:wps"; + gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; + }; + wps3 { + label = "arv7518pw:red:wps"; + gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io2", "io4", "io5", "io6", "io7", "io8", "io19"; + lantiq,output = <1>; + }; + keys { + lantiq,pins = "io28", "io30"; + lantiq,output = <0>; + lantiq,pull = <2>; + lantiq,open-drain = <1>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* +#define SWITCH_RESET 13 +*/ +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7d0000>; + }; + + boardconfig: partition@400000 { + label = "boardconfig"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x0>; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + lantiq,external-clock; + req-mask = <0xf>; + + wifi@168c,0029 { + compatible = "pci168c,0029"; + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + mtd-mac-address = <&boardconfig 0x16>; + mtd-mac-address-increment = <1>; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts new file mode 100644 index 0000000000..34b541af92 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts @@ -0,0 +1,217 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv7519pw", "lantiq,xway", "lantiq,danube"; + model = "Astoria Networks ARV7519PW"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power2; + led-running = &power; + led-upgrade = &power; + + led-dsl = &dsl; + led-internet = &online; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power: power { + label = "power"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power2: power2 { + label = "power2"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + online: online { + label = "online"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + online2 { + label = "online2"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "wifi"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + wifi2 { + label = "wifi2"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + wifi3 { + label = "wifi3"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + voice { + label = "voice"; + gpios = <&gpio 31 GPIO_ACTIVE_LOW>; + }; + wps { + label = "wps"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + wps2 { + label = "wps2"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + }; + wps3 { + label = "wps3"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + lan { + label = "lan"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + tv { + label = "tv"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + upgrade { + label = "upgrade"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; + }; + + /* is there another way to "reserve" the GPIO? */ + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + switch_rst { + lantiq,pins = "io19"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xf80000>; + }; + + boardconfig: partition@fe0000 { + label = "board_config"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + req-mask = <0xf>; + + wifi@0,0 { + compatible = "pci0,0"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + ralink,mtd-eeprom-swap; + }; +}; + +&usb_phy { + status = "okay"; +}; + +/* warning: passive port only works with active devices */ +&usb { + status = "okay"; +}; + +&vmmc { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts new file mode 100644 index 0000000000..d673c9b204 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts @@ -0,0 +1,149 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv7525pw", "lantiq,xway", "lantiq,danube"; + model = "Speedport W303V Typ A"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &power_green; + led-internet = &online; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power_green: power { + label = "arv7525pw:green:power"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_red: power1 { + label = "arv7525pw:red:power"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + online: online { + label = "arv7525pw:green:online"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + voice { + label = "arv7525pw:green:telefonie"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + voice2 { + label = "arv7525pw:red:telefonie"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv7525pw:green:wlan"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + boardconfig: partition@400000 { + label = "board_config"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + interrupt-map = <0x7000 0 0 1 &icu0 135 1>; + + wifi@0,0 { + compatible = "pci0,0"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + }; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts new file mode 100644 index 0000000000..069b1b1ed6 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts @@ -0,0 +1,240 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv752dpw", "lantiq,xway", "lantiq,danube"; + model = "Arcor 802"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_red; + led-failsafe = &power_blue; + led-running = &power_red; + led-upgrade = &power_red; + + led-dsl = &internet_red; + led-usb = &umts; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + restart { + label = "restart"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + dsl { + label = "dsl"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power_blue: power1 { + label = "arv752dpw:blue:power"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + internet_red: internet { + label = "arv752dpw:red:internet"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + message { + label = "arv752dpw:red:message"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + power_red: power { + label = "arv752dpw:red:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + voice1 { + label = "arv752dpw:red:voice"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + umts: umts { + label = "arv752dpw:red:umts"; + gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv752dpw:red:wifi"; + gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; + }; + fxs1 { + label = "arv752dpw:green:tae-n"; + gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; + }; + fxs2 { + label = "arv752dpw:green:tae-u"; + gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; + }; + fxo { + label = "arv752dpw:green:isdn"; + gpios = <&gpiomm 7 GPIO_ACTIVE_LOW>; + }; + internet2 { + label = "arv752dpw:blue:internet"; + gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; + }; + voice2 { + label = "arv752dpw:blue:voice"; + gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io3", "io5", "io6", "io8"; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + keys { + lantiq,pins = "io11", "io12", "io13", "io28"; + lantiq,output = <0>; + lantiq,pull = <2>; + lantiq,open-drain = <1>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpiomm 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gsw { + phy-mode = "rmii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7d0000>; + }; + + boardconfig: partition@7f0000 { + label = "board_config"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x3>; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + interrupt-map = <0x7000 0 0 1 &icu0 135>; + req-mask = <0x3>; + + wifi@1814,0601 { + compatible = "pci1814,0601"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + ralink,mtd-eeprom-swap; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts new file mode 100644 index 0000000000..ec90a2bef9 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts @@ -0,0 +1,261 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv752dpw22", "lantiq,xway", "lantiq,danube"; + model = "Arcor 803"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_red; + led-failsafe = &power_blue; + led-running = &power_red; + led-upgrade = &power_red; + + led-dsl = &internet_red; + led-usb = &umts; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + restart { + label = "restart"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + dsl { + label = "dsl"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power_blue: power1 { + label = "arv752dpw22:blue:power"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + internet_red: internet { + label = "arv752dpw22:red:internet"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + message { + label = "arv752dpw22:red:message"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + power_red: power { + label = "arv752dpw22:red:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + voice1 { + label = "arv752dpw22:red:voice"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + umts: umts { + label = "arv752dpw22:red:umts"; + gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; + }; + wifi: wifi { + label = "arv752dpw22:red:wifi"; + gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; + }; + fxs1 { + label = "arv752dpw22:green:tae-n"; + gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; + }; + fxs2 { + label = "arv752dpw22:green:tae-u"; + gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; + }; + fxo { + label = "arv752dpw22:green:isdn"; + gpios = <&gpiomm 7 GPIO_ACTIVE_LOW>; + }; + internet2 { + label = "arv752dpw22:blue:internet"; + gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; + }; + voice2 { + label = "arv752dpw22:blue:voice"; + gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; + }; + eth1 { + label = "arv752dpw22:green:lan1"; + gpios = <&gpiomm 11 GPIO_ACTIVE_LOW>; + }; + eth2 { + label = "arv752dpw22:green:lan2"; + gpios = <&gpiomm 12 GPIO_ACTIVE_LOW>; + }; + eth3 { + label = "arv752dpw22:green:lan3"; + gpios = <&gpiomm 13 GPIO_ACTIVE_LOW>; + }; + eth4 { + label = "arv752dpw22:green:lan4"; + gpios = <&gpiomm 14 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpiomm 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,open-drain = <1>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io3", "io5", "io6", "io8"; + lantiq,open-drain = <1>; + lantiq,output = <1>; + }; + buttons { + lantiq,pins = "io11", "io12", "io13", "io28"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&boardconfig 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x30000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x40000 0x7b0000>; + }; + + boardconfig: partition@7f0000 { + label = "board_config"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <3>; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + lantiq,external-clock; + interrupt-map = < + 0x7000 0 0 1 &icu0 30 + 0x7800 0 0 1 &icu0 135 + 0x7800 0 0 2 &icu0 135 + 0x7800 0 0 3 &icu0 135 + >; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + req-mask = <0x3>; + + wifi@1814,3592 { + compatible = "pci1814,3592"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + ralink,mtd-eeprom-swap; + mtd-mac-address = <&boardconfig 0x16>; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts new file mode 100644 index 0000000000..4bf44a10e1 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts @@ -0,0 +1,181 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "arcadyan,arv8539pw22", "lantiq,xway", "lantiq,danube"; + model = "Speedport W 504V Typ A"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl_green; + led-internet = &online_green; + led-wifi = &wireless_green; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wlan { + label = "wlan"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio 30 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + /* key DECT is missing */ + }; + + leds { + compatible = "gpio-leds"; + + power_green: power-green { + label = "arv8539pw22:green:power"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_red: power-red { + label = "arv8539pw22:red:power"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + + dsl_green: dsl-green { + label = "arv8539pw22:green:dsl"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + + online_green: online-green { + label = "arv8539pw22:green:online"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + + wireless_green: wireless-green { + label = "arv8539pw22:green:wlan"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + /* + telefonie green is missing + */ + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + relay { + lantiq,pins = "io31"; + lantiq,output = <1>; + }; + }; +}; + +&gsw { + phy-mode = "mii"; + mtd-mac-address = <&art 0x16>; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x30000>; /* 192 KiB */ + read-only; + }; + + partition@30000 { + label = "uboot"; + reg = <0x30000 0x10000>; /* 64 KiB */ + read-only; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0x7b0000>; /* 7872 KiB */ + }; + + art: partition@7f0000 { + label = "art"; + reg = <0x7f0000 0x10000>; /* 64 KiB*/ + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@168c,0029 { + compatible = "pci168c,0029"; + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + mtd-mac-address = <&art 0x16>; + mtd-mac-address-increment = <1>; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts new file mode 100644 index 0000000000..67b0f9631f --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts @@ -0,0 +1,112 @@ +/dts-v1/; + +#include "danube.dtsi" + +/ { + compatible = "audiocodes,mp-252", "lantiq,xway", "lantiq,danube"; + model = "AudioCodes MediaPack MP-252"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + }; +}; + +&gsw { + phy-mode = "rmii"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "uboot_env"; + reg = <0x20000 0x20000>; + }; + + partition@40000 { + label = "boardconfig"; + reg = <0x40000 0x60000>; + read-only; + }; + + partition@a0000 { + label = "firmware"; + reg = <0xa0000 0xf20000>; + }; + + partition@fc0000 { + label = "sysconfig"; + reg = <0xfc0000 0x40000>; + }; + + partition@1000000 { + label = "rootfs_data"; + reg = <0x1000000 0x1000000>; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts new file mode 100644 index 0000000000..40886feec4 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts @@ -0,0 +1,238 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "bt,homehub-v2b", "lantiq,xway", "lantiq,danube"; + model = "BT Home Hub 2B"; /* SoC: Lantiq Danube-S PSB 50712 @ 333MHz V1.3/1.5 */ + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_orange; + led-failsafe = &power_red; + led-running = &power_blue; + led-upgrade = &power_blue; + + led-dsl = &broadband_blue; + led-wifi = &wireless_blue; + }; + + memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + findhandset { + label = "findhandset"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + upgrading-orange { + label = "bthomehubv2b:orange:upgrading"; + gpios = <&gpios 5 GPIO_ACTIVE_HIGH>; + }; + + phone-orange { + label = "bthomehubv2b:orange:phone"; + gpios = <&gpios 6 GPIO_ACTIVE_HIGH>; + }; + phone-blue { + label = "bthomehubv2b:blue:phone"; + gpios = <&gpios 7 GPIO_ACTIVE_HIGH>; + }; + + wireless-orange { + label = "bthomehubv2b:orange:wireless"; + gpios = <&gpios 8 GPIO_ACTIVE_HIGH>; + }; + wireless_blue: wireless-blue { + label = "bthomehubv2b:blue:wireless"; + gpios = <&gpios 9 GPIO_ACTIVE_HIGH>; + }; + + broadband-red { + label = "bthomehubv2b:red:broadband"; + gpios = <&gpios 10 GPIO_ACTIVE_HIGH>; + }; + broadband-orange { + label = "bthomehubv2b:orange:broadband"; + gpios = <&gpios 11 GPIO_ACTIVE_HIGH>; + }; + broadband_blue: broadband-blue { + label = "bthomehubv2b:blue:broadband"; + gpios = <&gpios 12 GPIO_ACTIVE_HIGH>; + }; + + power_red: power-red { + label = "bthomehubv2b:red:power"; + gpios = <&gpios 13 GPIO_ACTIVE_HIGH>; + }; + power_orange: power-orange { + label = "bthomehubv2b:orange:power"; + gpios = <&gpios 14 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + power_blue: power-blue { + label = "bthomehubv2b:blue:power"; + gpios = <&gpios 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + }; + + btn_in { + lantiq,pins = "io2", "io15", "io22"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; +}; + +&gpios { + status = "okay"; +}; + +&gsw { + phy-mode = "rmii"; +}; + +&localbus { + flash@0 { /* NOR Flash: Spansion S29AL004D 512KB */ + compatible = "lantiq,nor"; /* "AMD AM29LV400BB" compatible on 3.3.8 */ + lantiq,cs = <0>; + bank-width = <2>; + reg = <0 0x0 0x80000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; /* 256KB */ + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x10000>; /* 64KB */ + }; + + partition@50000 { + label = "rg_conf_1"; + reg = <0x50000 0x10000>; + }; + + partition@60000 { + label = "rg_conf_2"; + reg = <0x60000 0x10000>; + }; + + partition@70000 { + label = "rg_conf_factory"; + reg = <0x70000 0x10000>; + }; + }; + }; + + flash@1 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ + compatible = "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <1 0x0 0x2000000 >; + req-mask = <0x1>; /* PCI request lines to mask during NAND access */ + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ath9k_cal: partition@0 { + label = "art"; /* Atheros 9160 wifi b/g/n radio EEPROM */ + reg = <0x00000 0x4000>; + read-only; + }; + + partition@4000 { + label = "kernel"; + reg = <0x4000 0x200000>; + }; + + partition@164000 { + label = "ubi"; + reg = <0x204000 0x1dfc000>; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@168c,0027 { + compatible = "pci168c,0027"; + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/EASY50810.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts similarity index 67% rename from target/linux/lantiq/files/arch/mips/boot/dts/EASY50810.dts rename to target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts index 4f101151d1..1afc74900e 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/EASY50810.dts +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts @@ -1,10 +1,10 @@ /dts-v1/; -#include "ar9.dtsi" +#include "danube.dtsi" / { - compatible = "lantiq,easy50810", "lantiq,xway", "lantiq,ar9"; - model = "Lantiq EASY50810"; + compatible = "lantiq,easy50712", "lantiq,xway", "lantiq,danube"; + model = "Intel EASY50712 Nand"; chosen { bootargs = "console=ttyLTQ0,115200"; @@ -21,23 +21,10 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; exin { lantiq,groups = "exin1"; lantiq,function = "exin"; }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; }; }; @@ -79,8 +66,7 @@ }; }; -&stp { - status = "okay"; - lantiq,shadow = <0xfff>; - lantiq,groups = <0x3>; +&pci0 { + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; }; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts new file mode 100644 index 0000000000..0072f7e2b1 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts @@ -0,0 +1,119 @@ +/dts-v1/; + +#include "danube.dtsi" + +#include + +/ { + compatible = "siemens,gigaset-sx76x", "lantiq,xway", "lantiq,danube"; + model = "Gigaset SX761,SX762,SX763"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpios { + status = "okay"; +}; + +&gsw { + phy-mode = "rmii"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x30000 0x10000>; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0x7c0000>; + }; + }; + }; + + gpiomm: gpio@1 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x3>; + }; +}; + +&pci0 { + status = "okay"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon.dtsi new file mode 100644 index 0000000000..cf9b33ea93 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon.dtsi @@ -0,0 +1,363 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,falcon"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips34kc"; + reg = <0>; + }; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ebu_cs0: localbus@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,localbus", "simple-bus"; + reg = <0x10000000 0x4000000>; + ranges = <0x0 0x10000000 0x4000000>; + }; + ebu_cs1: localbus@14000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,localbus", "simple-bus"; + reg = <0x14000000 0x4000000>; + ranges = <0x0 0x14000000 0x4000000>; + }; + + ebu@18000000 { + compatible = "lantiq,ebu-falcon"; + reg = <0x18000000 0x100>; + }; + + sbs2@1d000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sysb2", "simple-bus"; + reg = <0x1d000000 0x1000000>; + ranges = <0x0 0x1d000000 0x1000000>; + + clock_sysgpe: clock-controller@700000 { + compatible = "lantiq,sysgpe-falcon"; + reg = <0x700000 0x100>; + #clock-cells = <1>; + }; + + mps@4000 { + compatible = "lantiq,mps-falcon", "lantiq,mps-xrx100"; + reg = <0x4000 0x1000>; + interrupt-parent = <&icu0>; + interrupts = <154 155>; + lantiq,mbx = <&mpsmbx>; + }; + + gpio0: gpio@810000 { + compatible = "lantiq,falcon-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu0>; + interrupts = <44>; + reg = <0x810000 0x80>; + clocks = <&clock_syseth 16>; + }; + + gpio2: gpio@810100 { + compatible = "lantiq,falcon-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu0>; + interrupts = <46>; + reg = <0x810100 0x80>; + clocks = <&clock_syseth 17>; + }; + + clock_syseth: clock-controller@b00000 { + compatible = "lantiq,syseth-falcon"; + reg = <0xb00000 0x100>; + #clock-cells = <1>; + }; + + pad@b01000 { + compatible = "lantiq,pad-falcon"; + reg = <0xb01000 0x100>; + lantiq,bank = <0>; + clocks = <&clock_syseth 20>; + }; + + pad@b02000 { + compatible = "lantiq,pad-falcon"; + reg = <0xb02000 0x100>; + lantiq,bank = <2>; + clocks = <&clock_syseth 21>; + }; + }; + + fpi@1e000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + reg = <0x1e000000 0x1000000>; + ranges = <0x0 0x1e000000 0x1000000>; + + serial1: serial@100b00 { + status = "disabled"; + compatible = "lantiq,asc"; + reg = <0x100b00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + line = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&asc1_pins>; + clocks = <&clock_sys1 11>; + }; + + serial0: serial@100c00 { + compatible = "lantiq,asc"; + reg = <0x100c00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <104 105 106>; + line = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&asc0_pins>; + clocks = <&clock_sys1 12>; + }; + + spi: spi@100d00 { + status = "disabled"; + compatible = "lantiq,falcon-spi", "lantiq,xrx100-spi", "lantiq,spi-lantiq-ssc"; + interrupts = <22 23 24 25>; + interrupt-names = "spi_tx", "spi_rx", "spi_err", "spi_frm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100d00 0x100>; + interrupt-parent = <&icu0>; + clocks = <&clock_sys1 13>; + base_cs = <1>; + num_cs = <2>; + }; + + gptc@100e00 { + compatible = "lantiq,gptc-falcon"; + reg = <0x100e00 0x100>; + }; + + i2c: i2c@200000 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,lantiq-i2c"; + reg = <0x200000 0x10000>; + interrupt-parent = <&icu0>; + interrupts = <18 19 20 21>; + gpios = <&gpio1 7 0 &gpio1 8 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + clocks = <&clock_sys1 14>; + }; + + gpio1: gpio@800100 { + compatible = "lantiq,falcon-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu0>; + interrupts = <45>; + reg = <0x800100 0x100>; + clocks = <&clock_sys1 16>; + }; + + gpio3: gpio@800200 { + compatible = "lantiq,falcon-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu0>; + interrupts = <47>; + reg = <0x800200 0x100>; + clocks = <&clock_sys1 17>; + }; + + gpio4: gpio@800300 { + compatible = "lantiq,falcon-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu0>; + interrupts = <48>; + reg = <0x800300 0x100>; + clocks = <&clock_sys1 18>; + }; + + pad@800400 { + compatible = "lantiq,pad-falcon"; + reg = <0x800400 0x100>; + lantiq,bank = <1>; + clocks = <&clock_sys1 20>; + }; + + pad@800500 { + compatible = "lantiq,pad-falcon"; + reg = <0x800500 0x100>; + lantiq,bank = <3>; + clocks = <&clock_sys1 21>; + }; + + pad@800600 { + compatible = "lantiq,pad-falcon"; + reg = <0x800600 0x100>; + lantiq,bank = <4>; + clocks = <&clock_sys1 22>; + }; + + status@802000 { + compatible = "lantiq,status-falcon"; + reg = <0x802000 0x80>; + }; + + clock_sys1: clock-controller@f00000 { + compatible = "lantiq,sys1-falcon"; + reg = <0xf00000 0x100>; + #clock-cells = <1>; + }; + }; + + sbs0@1f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x1f000000 0x400000>; + ranges = <0x0 0x1f000000 0x400000>; + + mpsmbx: mpsmbx@200000 { + reg = <0x200000 0x200>; + }; + }; + + biu@1f800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1f800000 0x800000>; + ranges = <0x0 0x1f800000 0x800000>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + /* TODO: Number of ICUs isn't known */ + reg = <0x80200 0xc8>; + }; + + watchdog@803f0 { + compatible = "lantiq,wdt"; + reg = <0x803f0 0x10>; + }; + }; + + pinctrl { + compatible = "lantiq,pinctrl-falcon"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinctrl0 { + /*ntr { + lantiq,groups = "ntr8k"; + lantiq,function = "ntr"; + };*/ + hrst { + lantiq,groups = "hrst"; + lantiq,function = "rst"; + }; + }; + + asc0_pins: asc0 { + asc0 { + lantiq,groups = "asc0"; + lantiq,function = "asc"; + }; + }; + asc1_pins: asc1 { + asc1 { + lantiq,groups = "asc1"; + lantiq,function = "asc"; + }; + }; + i2c_pins: i2c_pins { + i2c_pins { + lantiq,groups = "i2c"; + lantiq,function = "i2c"; + }; + }; + bootled_pins: bootled { + bootled { + lantiq,groups = "bootled"; + lantiq,function = "led"; + }; + }; + ntr_ntr8k: ntr8k { + ntr8k { + lantiq,groups = "ntr8k"; + lantiq,function = "ntr"; + }; + }; + ntr_pps: pps { + pps { + lantiq,groups = "pps"; + lantiq,function = "ntr"; + }; + }; + ntr_gpio: gpio { + gpio { + lantiq,pins = "io5"; + lantiq,mux = <1>; + lantiq,output = <0>; + }; + }; + slic_pins: slic { + slic { + lantiq,groups = "slic"; + lantiq,function = "slic"; + }; + }; + }; + + pinselect-ntr { + compatible = "lantiq,onu-ntr","lantiq,pinselect-ntr"; + pinctrl-names = "ntr8k", "pps", "gpio"; + pinctrl-0 = <&ntr_ntr8k>; + pinctrl-1 = <&ntr_pps>; + pinctrl-2 = <&ntr_gpio>; + }; + + pinselect-asc1 { + compatible = "lantiq,onu-asc1","lantiq,pinselect-asc1"; + pinctrl-names = "default", "asc1"; + pinctrl-0 = <&slic_pins>; + pinctrl-1 = <&asc1_pins>; + }; + +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts new file mode 100644 index 0000000000..22ce8caced --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts @@ -0,0 +1,93 @@ +/dts-v1/; + +#include +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon FTTDP8 Reference Board"; + compatible = "lantiq,easy88388", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + linux,code = <0x198>; + }; + }; + + pinctrl { + led_pins: led-pins { + lantiq,pins = "io34", "io35", "io36", "io37", "io38", + "io39", "io40", "io41"; + lantiq,function = "gpio"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins &bootled_pins>; + + GPON { + label = "easy88388:green:gpon"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + }; + TEST { + label = "easy88388:green:test"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + STATUS { + label = "easy88388:green:status"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + ERROR { + label = "easy88388:red:error"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + + DSL1 { + label = "easy88388:dsl:1"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + DSL2 { + label = "easy88388:dsl:2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + DSL3 { + label = "easy88388:dsl:3"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + DSL4 { + label = "easy88388:dsl:4"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + DSL5 { + label = "easy88388:dsl:5"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; + DSL6 { + label = "easy88388:dsl:6"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + DSL7 { + label = "easy88388:dsl:7"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + DSL8 { + label = "easy88388:dsl:8"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + }; +}; + diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts new file mode 100644 index 0000000000..fa331450bf --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon FTTdp G.FAST Reference Board"; + compatible = "lantiq,easy88444", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + linux,code = <0x198>; + }; + }; + + pinctrl { + led_pins: led-pins { + lantiq,pins = "io34", "io35", "io37"; + lantiq,function = "gpio"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins &bootled_pins>; + + GPON { + label = "easy88444:green:gpon"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + }; + TEST { + label = "easy88444:green:test"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + STATUS { + label = "easy88444:green:status"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + GFAST1 { + label = "easy88444:gfast:1"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + GFAST2 { + label = "easy88444:gfast:2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + GFAST3 { + label = "easy88444:gfast:3"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + GFAST4 { + label = "easy88444:gfast:4"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts new file mode 100644 index 0000000000..13f9f82b1a --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +#include "falcon_lantiq_easy98000.dtsi" + +/ { + model = "Lantiq Falcon (NAND)"; + compatible = "lantiq,easy98000-nand", "lantiq,easy98000", "lantiq,falcon"; + + aliases { + spi0 = &spi; + }; +}; + +&ebu_cs0 { + flash@0 { + compatible = "gen_nand", "lantiq,nand-falcon"; + bank-width = <1>; + reg = <0x0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + bbt-use-flash; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x40000 0x40000>; + }; + + partition@20000 { + label = "linux"; + reg = <0x80000 0x3d0000>; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts new file mode 100644 index 0000000000..56d0fe0bc3 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts @@ -0,0 +1,41 @@ +/dts-v1/; + +#include "falcon_lantiq_easy98000.dtsi" + +/ { + model = "Lantiq Falcon (NOR)"; + compatible = "lantiq,easy98000-nor", "lantiq,easy98000", "lantiq,falcon"; + + aliases { + spi0 = &spi; + }; +}; + +&ebu_cs0 { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0x0 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x40000 0x40000>; + }; + + partition@20000 { + label = "linux"; + reg = <0x80000 0x3d0000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts new file mode 100644 index 0000000000..8c931746ed --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "falcon_lantiq_easy98000.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon (SFLASH)"; + compatible = "lantiq,easy98000-sflash", "lantiq,easy98000", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + spi1 = &spi; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi new file mode 100644 index 0000000000..5821c51def --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi @@ -0,0 +1,110 @@ +#include +#include + +#include "falcon.dtsi" + +/ { + compatible = "lantiq,easy98000", "lantiq,falcon"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&bootled_pins>; + + LED_0 { + label = "easy98000:green:gpon"; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_1 { + label = "easy98000:red:gpon"; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_2 { + label = "easy98000:green:gpon_tx"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_3 { + label = "easy98000:green:gpon_rx"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_4 { + label = "easy98000:green:voice"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_5 { + label = "easy98000:green:status"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + +&ebu_cs1 { + eth0: ethernet@3 { + compatible = "davicom,dm9000"; + device_type = "network"; + reg = <0x0000003 0x1>, <0x0000001 0x1>; + reg-names = "addr", "data"; + interrupt-parent = <&gpio1>; + #interrupt-cells = <2>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpld@3c00000 { + compatible = "lantiq,easy98000_addon"; + reg = <0x3c00000 0x2>; + }; + + cpld@3c0000c { + compatible = "lantiq,easy98000_cpld_led"; + reg = <0x3c0000c 0x2>, <0x3c00012 0x2>; + }; +}; + +/* // enable this for second uart: +&serial1 { + status = "okay"; +};*/ + +&spi { + status = "okay"; + + eeprom@2 { + compatible = "atmel,at25", "atmel,at25160n"; + reg = <2>; + spi-max-frequency = <1000000>; + spi-cpha; + spi-cpol; + + pagesize = <32>; + size = <2048>; + address-width = <16>; + }; +}; + +&i2c { + status = "okay"; + + clock-frequency = <100000>; + + /* eeprom-emulation by OMU */ + eeprom@50 { + compatible = "at,24c02"; + reg = <0x50>; + }; + eeprom@51 { + compatible = "at,24c02"; + reg = <0x51>; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts new file mode 100644 index 0000000000..773a490019 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts @@ -0,0 +1,68 @@ +/dts-v1/; + +#include + +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon Reference Board V1.8"; + compatible = "lantiq,easy98020-v18", "lantiq,easy98020", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + linux,code = <0x198>; + }; + }; + + pinctrl { + led_pins: led-pins { + lantiq,pins = "io11", "io14", "io36", "io37", "io38"; + lantiq,function = "gpio"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins &bootled_pins>; + + GPON { + label = "easy98020:green:gpon"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + TEST { + label = "easy98020:green:test"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + ETH { + label = "easy98020:green:status"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + VOICE { + label = "easy98020:green:voice"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + VIDEO { + label = "easy98020:green:video"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts new file mode 100644 index 0000000000..397764aac4 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts @@ -0,0 +1,85 @@ +/dts-v1/; + +#include + +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon Reference Board"; + compatible = "lantiq,easy98020", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + linux,code = <0x198>; + }; + }; + + pinctrl { + led_pins: phy-led-pins { + lantiq,pins = "io42", "io41", "io38", "io37"; + lantiq,function = "gpio"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&bootled_pins>, <&led_pins>; + + GPON { + label = "easy98020:green:gpon"; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + TEST { + label = "easy98020:green:test"; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + ETH { + label = "easy98020:green:status"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + VOICE { + label = "easy98020:green:voice"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + VIDEO { + label = "easy98020:green:video"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + GE0_ACT { + label = "easy98020:ge0_act"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + GE0_LINK { + label = "easy98020:ge0_link"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + GE1_ACT { + label = "easy98020:ge1_act"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + GE1_LINK { + label = "easy98020:ge1_link"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts new file mode 100644 index 0000000000..aa63268149 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts @@ -0,0 +1,81 @@ +/dts-v1/; + +#include + +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon HGU Reference Board"; + compatible = "lantiq,easy98021", "lantiq,easy98020", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + linux,code = <0x198>; + }; + }; + + gpio-mmc { + /* Place-holder for SIM-Card connector, + to list the used GPIOs, no official binding */ + compatible = "gpio-mmc"; + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>, + <&gpio0 3 GPIO_ACTIVE_HIGH>, + <&gpio0 2 GPIO_ACTIVE_HIGH>, + <0>; /* no CS */ + gpio-names = "di", "do", "clk", "cs"; + reset-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; + }; + + pinctrl { + led_pins: led-pins { + lantiq,pins = "io11", "io14", "io36", "io37", "io38"; + lantiq,function = "gpio"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins &bootled_pins>; + + GPON { + label = "easy98021:green:gpon"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + TEST { + label = "easy98021:red:test"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + ETH { + label = "easy98021:green:status"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + VOICE { + label = "easy98021:green:voice"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + SIMCARD { + label = "easy98021:green:simcard"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts new file mode 100644 index 0000000000..f1ecebec3b --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts @@ -0,0 +1,76 @@ +/dts-v1/; + +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon SFP Stick with SyncE"; + compatible = "lantiq,easy98035synce", "lantiq,falcon-sfp", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + pinctrl { + compatible = "lantiq,pinctrl-falcon"; + + asc0_func1: func1 { + func1_tx { + lantiq,pins = "io32"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + func1_rx { + lantiq,pins = "io33"; + lantiq,mux = <0>; + }; + }; + asc0_func2: func2 { + func2_tx { + lantiq,pins = "io32"; + lantiq,mux = <0>; + }; + func2_rx { + lantiq,pins = "io33"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + }; + asc0_func3: func3 { + func3_tx { + lantiq,pins = "io32"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + func3_rx { + lantiq,pins = "io33"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + }; + }; + + pinselect-asc0 { + compatible = "lantiq,pinselect-asc0"; + pinctrl-names = "asc0", "func1", "func2", "func3"; + pinctrl-0 = <&asc0_pins>; + pinctrl-1 = <&asc0_func1>; + pinctrl-2 = <&asc0_func2>; + pinctrl-3 = <&asc0_func3>; + }; +}; + +&serial0 { + pinctrl-names = "default"; + /* use "empty" pinctrl to leave setting from u-boot enabled */ + pinctrl-0 = < >; +}; + +&i2c { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts new file mode 100644 index 0000000000..98421174d3 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts @@ -0,0 +1,76 @@ +/dts-v1/; + +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon SFP Stick with SyncE/1588"; + compatible = "lantiq,easy98035synce1588", "lantiq,falcon-sfp", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + pinctrl { + compatible = "lantiq,pinctrl-falcon"; + + asc0_func1: func1 { + func1_tx { + lantiq,pins = "io32"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + func1_rx { + lantiq,pins = "io33"; + lantiq,mux = <0>; + }; + }; + asc0_func2: func2 { + func2_tx { + lantiq,pins = "io32"; + lantiq,mux = <0>; + }; + func2_rx { + lantiq,pins = "io33"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + }; + asc0_func3: func3 { + func3_tx { + lantiq,pins = "io32"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + func3_rx { + lantiq,pins = "io33"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + }; + }; + + pinselect-asc0 { + compatible = "lantiq,pinselect-asc0"; + pinctrl-names = "asc0", "func1", "func2", "func3"; + pinctrl-0 = <&asc0_pins>; + pinctrl-1 = <&asc0_func1>; + pinctrl-2 = <&asc0_func2>; + pinctrl-3 = <&asc0_func3>; + }; +}; + +&serial0 { + pinctrl-names = "default"; + /* use "empty" pinctrl to leave setting from u-boot enabled */ + pinctrl-0 = < >; +}; + +&i2c { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts new file mode 100644 index 0000000000..130d49ebd7 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +#include + +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon / Vinax MDU Board"; + compatible = "lantiq,falcon-mdu", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&bootled_pins>; + + LED_0 { + label = "mdu:green:gpon"; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_1 { + label = "mdu:green:status"; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_2 { + label = "mdu:green:2"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_3 { + label = "mdu:green:3"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + LED_4 { + label = "mdu:green:4"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts new file mode 100644 index 0000000000..880c4edca8 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts @@ -0,0 +1,76 @@ +/dts-v1/; + +#include "falcon.dtsi" +#include "falcon_sflash-16m.dtsi" + +/ { + model = "Lantiq Falcon SFP Stick"; + compatible = "lantiq,falcon-sfp", "lantiq,falcon"; + + aliases { + spi0 = &ebu_cs0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + pinctrl { + compatible = "lantiq,pinctrl-falcon"; + + asc0_func1: func1 { + func1_tx { + lantiq,pins = "io32"; + lantiq,mux = <1>; + lantiq,output = <0>; + }; + func1_rx { + lantiq,pins = "io33"; + lantiq,mux = <0>; + }; + }; + asc0_func2: func2 { + func2_tx { + lantiq,pins = "io32"; + lantiq,mux = <0>; + }; + func2_rx { + lantiq,pins = "io33"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + }; + asc0_func3: func3 { + func3_tx { + lantiq,pins = "io32"; + lantiq,mux = <1>; + lantiq,output = <0>; + }; + func3_rx { + lantiq,pins = "io33"; + lantiq,mux = <1>; + lantiq,input = <0>; + }; + }; + }; + + pinselect-asc0 { + compatible = "lantiq,pinselect-asc0"; + pinctrl-names = "asc0", "func1", "func2", "func3"; + pinctrl-0 = <&asc0_pins>; + pinctrl-1 = <&asc0_func1>; + pinctrl-2 = <&asc0_func2>; + pinctrl-3 = <&asc0_func3>; + }; +}; + +&serial0 { + pinctrl-names = "default"; + /* use "empty" pinctrl to leave setting from u-boot enabled */ + pinctrl-0 = < >; +}; + +&i2c { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi new file mode 100644 index 0000000000..688b7da44c --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi @@ -0,0 +1,40 @@ + +&ebu_cs0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sflash-falcon", "simple-bus"; + + flash@0 { + compatible = "spansion,s25fl129p0", "spansion,s25fl129p1"; + reg = <0 0>; + spi-max-frequency = <80000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x40000>; + label = "uboot"; + read-only; + }; + + partition@40000 { + reg = <0x40000 0x80000>; + label = "uboot_env"; + }; + + partition@c0000 { + reg = <0xc0000 0x740000>; + label = "image0"; + }; + + partition@800000 { + reg = <0x800000 0x800000>; + label = "image1"; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9.dtsi new file mode 100644 index 0000000000..19f42d8c84 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9.dtsi @@ -0,0 +1,512 @@ +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,vr9"; + + aliases { + serial0 = &asc1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips34Kc"; + reg = <0>; + }; + }; + + cputemp { + compatible = "lantiq,cputemp"; + }; + + reboot { + compatible = "syscon-reboot"; + + regmap = <&rcu0>; + offset = <0x10>; + mask = <0xe0000000>; + }; + + biu@1f800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1f800000 0x800000>; + ranges = <0x0 0x1f800000 0x7fffff>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0xc8 /* icu0 */ + 0x80300 0xc8>; /* icu1 */ + }; + + watchdog@803f0 { + compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt"; + reg = <0x803f0 0x10>; + + regmap = <&rcu0>; + }; + }; + + sram@1f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram", "simple-bus"; + reg = <0x1f000000 0x800000>; + ranges = <0x0 0x1f000000 0x7fffff>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + lantiq,eiu-irqs = <166 135 66 40 41 42>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + }; + + dcdc@106a00 { + compatible = "lantiq,dcdc-xrx200"; + reg = <0x106a00 0x200>; + }; + + vmmc: vmmc@107000 { + status = "disabled"; + compatible = "lantiq,vmmc-xway"; + reg = <0x107000 0x300>; + interrupt-parent = <&icu0>; + interrupts = <150 151 152 153 154 155>; + }; + + pcie0_phy: phy@106800 { + compatible = "lantiq,vrx200-pcie-phy"; + reg = <0x106800 0x100>; + lantiq,rcu = <&rcu0>; + lantiq,rcu-endian-offset = <0x4c>; + lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */ + big-endian; + resets = <&reset0 12 24>, <&reset0 22 22>; + reset-names = "phy", "pcie"; + #phy-cells = <1>; + }; + + rcu0: rcu@203000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon"; + reg = <0x203000 0x100>; + ranges = <0x0 0x203000 0x100>; + big-endian; + + gphy0: gphy@20 { + compatible = "lantiq,xrx200-gphy"; + reg = <0x20 0x4>; + + resets = <&reset0 31 30>, <&reset1 7 7>; + reset-names = "gphy", "gphy2"; + }; + + gphy1: gphy@68 { + compatible = "lantiq,xrx200-gphy"; + reg = <0x68 0x4>; + + resets = <&reset0 29 28>, <&reset1 6 6>; + reset-names = "gphy", "gphy2"; + }; + + reset0: reset-controller@10 { + compatible = "lantiq,xrx200-reset"; + reg = <0x10 4>, <0x14 4>; + + #reset-cells = <2>; + }; + + reset1: reset-controller@48 { + compatible = "lantiq,xrx200-reset"; + reg = <0x48 4>, <0x24 4>; + + #reset-cells = <2>; + }; + + usb_phy0: usb2-phy@18 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x18 4>, <0x38 4>; + status = "disabled"; + + resets = <&reset1 4 4>, <&reset0 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + + usb_phy1: usb2-phy@34 { + compatible = "lantiq,xrx200-usb2-phy"; + reg = <0x34 4>, <0x3c 4>; + status = "disabled"; + + resets = <&reset1 5 5>, <&reset0 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + }; + }; + + fpi@10000000 { + compatible = "lantiq,xrx200-fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xf000000>; + reg = <0x1f400000 0x1000>, + <0x10000000 0xf000000>; + regmap = <&rcu0>; + offset-endianness = <0x4c>; + #address-cells = <1>; + #size-cells = <1>; + + localbus: localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + gptu@e100a00 { + compatible = "lantiq,gptu-xway"; + reg = <0xe100a00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <126 127 128 129 130 131>; + }; + + usif: usif@da00000 { + compatible = "lantiq,usif"; + reg = <0xda00000 0x1000000>; + interrupt-parent = <&icu0>; + interrupts = <29 125 107 108 109 110>; + status = "disabled"; + }; + + spi: spi@e100800 { + compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi"; + reg = <0xe100800 0x100>; + interrupt-parent = <&icu0>; + interrupts = <22 23 24>; + interrupt-names = "spi_rx", "spi_tx", "spi_err", + "spi_frm"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>; + status = "disabled"; + }; + + gpio: pinmux@e100b10 { + compatible = "lantiq,xrx200-pinctrl"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe100b10 0xa0>; + + gphy0_led0_pins: gphy0-led0 { + mux { + lantiq,groups = "gphy0 led0"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy0_led1_pins: gphy0-led1 { + mux { + lantiq,groups = "gphy0 led1"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy0_led2_pins: gphy0-led2 { + mux { + lantiq,groups = "gphy0 led2"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy1_led0_pins: gphy1-led0 { + mux { + lantiq,groups = "gphy1 led0"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy1_led1_pins: gphy1-led1 { + mux { + lantiq,groups = "gphy1 led1"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + gphy1_led2_pins: gphy1-led2 { + mux { + lantiq,groups = "gphy1 led2"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + + mdio_pins: mdio { + mux { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + + nand_pins: nand { + mux-0 { + lantiq,groups = "nand cle", "nand ale", + "nand rd"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + mux-1 { + lantiq,groups = "nand rdy"; + lantiq,function = "ebu"; + lantiq,output = <0>; + lantiq,pull = <2>; + }; + }; + + nand_cs1_pins: nand-cs1 { + mux { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_gnt1_pins: pci-gnt1 { + mux { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + + pci_req1_pins: pci-req1 { + mux { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + + spi_pins: spi { + mux-0 { + lantiq,groups = "spi_di"; + lantiq,function = "spi"; + }; + mux-1 { + lantiq,groups = "spi_do", "spi_clk"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + spi_cs4_pins: spi-cs4 { + mux { + lantiq,groups = "spi_cs4"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + + stp_pins: stp { + mux { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; + }; + + stp: stp@e100bb0 { + status = "disabled"; + compatible = "lantiq,gpio-stp-xway"; + reg = <0xe100bb0 0x40>; + #gpio-cells = <2>; + gpio-controller; + + pinctrl-0 = <&stp_pins>; + pinctrl-names = "default"; + + lantiq,shadow = <0xffffff>; + lantiq,groups = <0x7>; + lantiq,dsl = <0x0>; + lantiq,phy1 = <0x0>; + lantiq,phy2 = <0x0>; + }; + + asc1: serial@e100c00 { + compatible = "lantiq,asc"; + reg = <0xe100c00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + deu@e103100 { + compatible = "lantiq,deu-xrx200"; + reg = <0xe103100 0xf00>; + }; + + dma0: dma@e104100 { + compatible = "lantiq,dma-xway"; + reg = <0xe104100 0x800>; + }; + + ebu0: ebu@e105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xe105300 0x100>; + }; + + usb0: usb@e101000 { + status = "disabled"; + compatible = "lantiq,xrx200-usb"; + reg = <0xe101000 0x1000 + 0xe120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <62 91>; + dr_mode = "host"; + phys = <&usb_phy0>; + phy-names = "usb2-phy"; + }; + + usb1: usb@e106000 { + status = "disabled"; + compatible = "lantiq,xrx200-usb"; + reg = <0xe106000 0x1000>; + interrupt-parent = <&icu0>; + interrupts = <91>; + dr_mode = "host"; + phys = <&usb_phy1>; + phy-names = "usb2-phy"; + }; + + eth0: eth@e108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xe108000 0x3000 /* switch */ + 0xe10b100 0x70 /* mdio */ + 0xe10b1d8 0x30 /* mii */ + 0xe10b308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <75 73 72>; + resets = <&reset0 21 16>, <&reset0 8 8>; + reset-names = "switch", "ppe"; + lantiq,phys = <&gphy0>, <&gphy1>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + }; + + mei@e116000 { + compatible = "lantiq,mei-xrx200"; + reg = <0xe116000 0x9c>; + interrupt-parent = <&icu0>; + interrupts = <63>; + }; + + ppe@e234000 { + compatible = "lantiq,ppe-xrx200"; + reg = <0xe234000 0x3ffd>; + interrupt-parent = <&icu0>; + interrupts = <96>; + resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>; + reset-names = "dsp", "dfe", "tc"; + }; + + pcie0: pcie@d900000 { + compatible = "lantiq,pcie-xrx200"; + + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + + reg = <0xd900000 0x1000>; + + interrupt-parent = <&icu0>; + interrupts = <161 144>; + + phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>; + phy-names = "pcie"; + + resets = <&reset0 22 22>; + + lantiq,rcu = <&rcu0>; + + device_type = "pci"; + + gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>; + }; + + pci0: pci@e105400 { + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xe105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */ + req-mask = <0x1>; /* GNT1 */ + }; + }; + + vdsl { + compatible = "lantiq,vdsl-vrx200"; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts new file mode 100644 index 0000000000..3d10f582b0 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts @@ -0,0 +1,155 @@ +/dts-v1/; + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "alphanetworks,asl56026", "lantiq,xway", "lantiq,vr9"; + model = "BT OpenReach VDSL Modem"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 40 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + dsl: dsl { + label = "asl56026:green:dsl"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + + /* power-* is a bicolour led */ + power_green: power_green { + label = "asl56026:green:power"; + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + power_red: power_red { + label = "asl56026:red:power"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + power_led_blink { + gpio-export,name = "power_led_blink"; + gpio-export,output = <0>; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + lantiq,switch; + + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <3>; + phy-mode = "mii"; + phy-handle = <&phy14>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + + phy14: ethernet-phy@14 { + reg = <0x14>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x0800000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + }; + + partition@30000 { + label = "uboot_env"; + reg = <0x30000 0x10000>; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0x750000>; + }; + + partition@790000 { + label = "ddrconfig"; + reg = <0x790000 0x70000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts new file mode 100644 index 0000000000..d6c521cfe7 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts @@ -0,0 +1,246 @@ +/dts-v1/; + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "arcadyan,arv7519rw22", "lantiq,xway", "lantiq,vr9"; + model = "Orange Livebox 2.1"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_green; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &internet_green; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 33 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + lan_green { + label = "arv7519rw22:green:lan"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + internet_red { + label = "arv7519rw22:red:internet"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + power_green: power_green { + label = "arv7519rw22:green:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + alarm_blue { + label = "arv7519rw22:blue:alarm"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + internet_orange { + label = "arv7519rw22:orange:internet"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; + internet_green: internet_green { + label = "arv7519rw22:green:internet"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + }; + voice_green { + label = "arv7519rw22:green:voice"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 32 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&boardconfig 0x16>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "mii"; + phy-handle = <&phy14>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <3>; + phy-mode = "mii"; + phy-handle = <&phy12>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy12: ethernet-phy@12 { + reg = <0x12>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy14: ethernet-phy@14 { + reg = <0x14>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pcie-rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x60000>; + read-only; + }; + + partition@60000 { + label = "uboot-env"; + reg = <0x60000 0x20000>; + read-only; + }; + + partition@80000 { + label = "firmware"; + reg = <0x80000 0x1f00000>; + }; + + boardconfig: partition@1f80000 { + label = "boardconfig"; + reg = <0x1f80000 0x80000>; + read-only; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts new file mode 100644 index 0000000000..e074147d66 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts @@ -0,0 +1,144 @@ +/dts-v1/; + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "arcadyan,vg3503j", "lantiq,xway", "lantiq,vr9"; + model = "BT OpenReach VDSL Modem"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_red: power2 { + label = "vg3503j:red:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + dsl: dsl { + label = "vg3503j:green:dsl"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; + power_green: power { + label = "vg3503j:green:power"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +ð0 { + pinctrl-0 = <&mdio_pins>, + <&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>, + <&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>; + + interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lantiq,switch; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + lantiq,led1h = <0x70>; + lantiq,led1l = <0x00>; + lantiq,led2h = <0x00>; + lantiq,led2l = <0x03>; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + lantiq,led1h = <0x70>; + lantiq,led1l = <0x00>; + lantiq,led2h = <0x00>; + lantiq,led2l = <0x03>; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x20000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7d0000>; + }; + + partition@7f0000 { + label = "uboot-env"; + reg = <0x7f0000 0x10000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts new file mode 100644 index 0000000000..9f6f405a09 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts @@ -0,0 +1,65 @@ +/dts-v1/; + +#include "vr9_arcadyan_vgv7510kw22.dtsi" + +/ { + compatible = "arcadyan,vgv7510kw22-brn", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; + model = "o2 Box 6431"; + + sram@1f000000 { + cgu@103000 { + lantiq,phy-clk-src = <0x2>; + }; + }; +}; + +&localbus { + flash@0 { + partitions { + partition@0 { + label = "Boot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "Configuration"; + reg = <0x40000 0x40000>; + read-only; + }; + + partition@80000 { + label = "Certificate"; + reg = <0x80000 0x20000>; + read-only; + }; + + partition@a0000 { + label = "Special_Area"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@c0000 { + compatible = "brnboot,root-selector"; + label = "Primary_Setting"; + reg = <0xc0000 0x20000>; + read-only; + }; + + partition@e0000 { + label = "Code_Image_0"; + reg = <0xe0000 0x780000>; + brnboot,root-id = <0x00>; + read-only; + }; + + partition@860000 { + label = "Code_Image_1"; + reg = <0x860000 0x780000>; + brnboot,root-id = <0x01>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts new file mode 100644 index 0000000000..613ff3782c --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts @@ -0,0 +1,31 @@ +/dts-v1/; + +#include "vr9_arcadyan_vgv7510kw22.dtsi" + +/ { + compatible = "arcadyan,vgv7510kw22-nor", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; + model = "o2 Box 6431"; +}; + +&localbus { + flash@0 { + partitions { + partition@0 { + label = "uboot"; + reg = <0x0 0x60000>; /* 384 KiB */ + read-only; + }; + + partition@60000 { + label = "uboot-env"; + reg = <0x60000 0x20000>; /* 128 KiB */ + read-only; + }; + + partition@80000 { + label = "firmware"; + reg = <0x80000 0xf60000>; /* 15744 KiB */ + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi new file mode 100644 index 0000000000..017e473a04 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi @@ -0,0 +1,258 @@ +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; + + chosen { + bootargs = "console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl; + led-internet = &internet_green; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + dsl: dsl { + label = "vgv7510kw22:green:dsl"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + + internet_red { + label = "vgv7510kw22:red:internet"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + + info_red { + label = "vgv7510kw22:red:info"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + + power_green: power { + label = "vgv7510kw22:green:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + info_green { + label = "vgv7510kw22:green:info"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + internet_green: internet_green { + label = "vgv7510kw22:green:internet"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + }; + + wifi: wifi { + label = "vgv7510kw22:green:wlan"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + + power_red: power2 { + label = "vgv7510kw22:red:power"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + }; + + phone { + label = "vgv7510kw22:green:telefon"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + pinctrl-0 = <&mdio_pins>, + <&gphy0_led0_pins>, + <&gphy1_led0_pins>, <&gphy1_led1_pins>; + pinctrl-names = "default"; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&boardconfig 0x16>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "mii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <3>; + phy-mode = "mii"; + phy-handle = <&phy12>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "mii"; + phy-handle = <&phy14>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy12: ethernet-phy@12 { + reg = <0x12>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy14: ethernet-phy@14 { + reg = <0x14>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>, <&gphy0_led1_pins>; + + state_default: pinmux { + pci-rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boardconfig: partition@fe0000 { + label = "board_config"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@1814,3592 { + compatible = "pci1814,3592"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + ralink,mtd-eeprom-swap; + mtd-mac-address = <&boardconfig 0x16>; + mtd-mac-address-increment = <1>; + }; +}; + +&pcie0 { + status = "disabled"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay + &gpio 31 GPIO_ACTIVE_HIGH //still unknown + &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts new file mode 100644 index 0000000000..051de0c23e --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts @@ -0,0 +1,70 @@ +/dts-v1/; + +#include "vr9_arcadyan_vgv7519.dtsi" + +/ { + compatible = "arcadyan,vgv7519-brn", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; + model = "KPN Experiabox V8"; +}; + +&localbus { + flash@0 { + partitions { + partition@0 { + label = "Boot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@50000 { + label = "Certificate"; + reg = <0x50000 0x10000>; + read-only; + }; + partition@60000 { + label = "Special_Area"; + reg = <0x60000 0x10000>; + read-only; + }; + + partition@70000 { + label = " Reserve_0"; + reg = <0x70000 0x10000>; + read-only; + }; + + partition@80000 { + label = "Code_Image_0"; + reg = <0x80000 0x780000>; + brnboot,root-id = <0x00>; + read-only; + }; + + partition@4000000 { + compatible = "brnboot,root-selector"; + label = "Primary_Setting"; + reg = <0x4000000 0x10000>; + read-only; + }; + + partition@4010000 { + label = "Configuration"; + reg = <0x4010000 0x60000>; + read-only; + }; + + partition@4070000 { + label = " Reserve_1"; + reg = <0x4070000 0x10000>; + read-only; + }; + + partition@4080000 { + label = "Code_Image_1"; + reg = <0x4080000 0x780000>; + brnboot,root-id = <0x01>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts new file mode 100644 index 0000000000..2121fbf41d --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts @@ -0,0 +1,29 @@ +/dts-v1/; + +#include "vr9_arcadyan_vgv7519.dtsi" + +/ { + compatible = "arcadyan,vgv7519-nor", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; + model = "KPN Experiabox V8"; +}; + +&localbus { + flash@0 { + partitions { + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + partition@60000 { + label = "uboot_env"; + reg = <0x60000 0x10000>; + read-only; + }; + partition@80000 { + label = "firmware"; + reg = <0x80000 0xf80000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi new file mode 100644 index 0000000000..e82407d7c3 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi @@ -0,0 +1,295 @@ +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; + + chosen { + bootargs = "console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &broadband_green; + led-internet = &internet_green; + led-wifi = &wireless_green; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + eco { + label = "eco"; + gpios = <&gpio 41 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 45 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + eco { + label = "vgv7519:blue:eco"; + gpios = <&stp 2 GPIO_ACTIVE_LOW>; + }; + wps_red { + label = "vgv7519:red:wps"; + gpios = <&stp 3 GPIO_ACTIVE_LOW>; + }; + wps_green { + label = "vgv7519:green:wps"; + gpios = <&stp 4 GPIO_ACTIVE_LOW>; + }; + upgrade { + label = "vgv7519:blue:upgrade"; + gpios = <&stp 5 GPIO_ACTIVE_LOW>; + }; + tv { + label = "vgv7519:green:tv"; + gpios = <&stp 6 GPIO_ACTIVE_LOW>; + }; + internet_green: internet_green { + label = "vgv7519:green:internet"; + gpios = <&stp 7 GPIO_ACTIVE_LOW>; + }; + internet_red { + label = "vgv7519:red:internet"; + gpios = <&stp 8 GPIO_ACTIVE_LOW>; + }; + broadband_red { + label = "vgv7519:red:broadband"; + gpios = <&stp 9 GPIO_ACTIVE_LOW>; + }; + broadband_green: broadband_green { + label = "vgv7519:green:broadband"; + gpios = <&stp 10 GPIO_ACTIVE_LOW>; + }; + voice { + label = "vgv7519:green:voice"; + gpios = <&stp 11 GPIO_ACTIVE_LOW>; + }; + wireless_red { + label = "vgv7519:red:wireless"; + gpios = <&stp 12 GPIO_ACTIVE_LOW>; + }; + wireless_green: wireless_green { + label = "vgv7519:green:wireless"; + gpios = <&stp 13 GPIO_ACTIVE_LOW>; + }; + power_green: power2 { + label = "vgv7519:green:power"; + gpios = <&stp 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_red: power { + label = "vgv7519:red:power"; + gpios = <&stp 15 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 32 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>; + pinctrl-names = "default"; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&boardconfig 0x16>; + mtd-mac-address-increment = <1>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci-rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>, <1 0x800000 0x800000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boardconfig: partition@40000 { + label = "board_config"; + reg = <0x40000 0x10000>; + read-only; + }; + }; + }; +}; + +&pci0 { + status = "okay"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@1814,3091 { + compatible = "pci1814,3091"; + reg = <0x7000 0 0 0 0>; + ralink,mtd-eeprom = <&boardconfig 0x410>; + ralink,mtd-eeprom-swap; + mtd-mac-address = <&boardconfig 0x16>; + mtd-mac-address-increment = <1>; + }; +}; + +&pcie0 { + status = "disabled"; +}; + +&stp { + status = "okay"; + lantiq,shadow = <0xffff>; + lantiq,groups = <0x3>; + lantiq,dsl = <0x0>; + lantiq,phy1 = <0x0>; + lantiq,phy2 = <0x0>; + /* lantiq,rising; */ +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay + &gpio 31 GPIO_ACTIVE_HIGH //still unknown + &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts new file mode 100644 index 0000000000..1aea98260a --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts @@ -0,0 +1,39 @@ +/dts-v1/; + +#include "vr9_avm_fritz3370-rev2.dtsi" + +/ { + compatible = "avm,fritz3370-rev2-hynix", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; + model = "AVM FRITZ!Box 3370 Rev. 2 (Hynix NAND)"; +}; + +&localbus { + flash@1 { + compatible = "lantiq,nand-xway"; + bank-width = <2>; + reg = <1 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + nand-ecc-mode = "soft"; + nand-ecc-strength = <3>; + nand-ecc-step-size = <256>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "ubi"; + reg = <0x400000 0x7c00000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts new file mode 100644 index 0000000000..a19d168159 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts @@ -0,0 +1,37 @@ +/dts-v1/; + +#include "vr9_avm_fritz3370-rev2.dtsi" + +/ { + compatible = "avm,fritz3370-rev2-micron", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; + model = "AVM FRITZ!Box 3370 Rev. 2 (Micron NAND)"; +}; + +&localbus { + flash@1 { + compatible = "lantiq,nand-xway"; + bank-width = <2>; + reg = <1 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + nand-ecc-mode = "on-die"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "ubi"; + reg = <0x400000 0x7c00000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi new file mode 100644 index 0000000000..bac27c3649 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi @@ -0,0 +1,279 @@ +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; + model = "AVM FRITZ!Box 3370 Rev. 2"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_red; + + led-dsl = &dsl; + led-internet = &info_green; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + power { + label = "power"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + wifi { + label = "wlan"; + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_green: power { + label = "fritz3370:green:power"; + gpios = <&gpio 32 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + power_red: power2 { + label = "fritz3370:red:power"; + gpios = <&gpio 33 GPIO_ACTIVE_LOW>; + }; + + info_red { + label = "fritz3370:red:info"; + gpios = <&gpio 34 GPIO_ACTIVE_LOW>; + }; + + wifi: wifi { + label = "fritz3370:green:wlan"; + gpios = <&gpio 35 GPIO_ACTIVE_LOW>; + }; + + dsl: dsl { + label = "fritz3370:green:dsl"; + gpios = <&gpio 36 GPIO_ACTIVE_LOW>; + }; + + lan { + label = "fritz3370:green:lan"; + gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + }; + + info_green: info_green { + label = "fritz3370:green:info"; + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + }; + + usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB0_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB1_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + }; + + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; + }; + + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + phy-rst { + lantiq,pins = "io37", "io44"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + + pcie-rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&pcie0 { + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + + wifi@0,0 { + compatible = "pci0,0"; + reg = <0 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ + }; + }; +}; + +&spi { + status = "okay"; + + flash@4 { + compatible = "jedec,spi-nor"; + reg = <4>; + spi-max-frequency = <1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + urlader: partition@0 { + reg = <0x0 0x20000>; + label = "urlader"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "tffs (1)"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x10000>; + label = "tffs (2)"; + read-only; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb0_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb1_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts new file mode 100644 index 0000000000..012300ec57 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "vr9_avm_fritz736x.dtsi" + +#include +#include + +/ { + compatible = "avm,fritz7360sl", "avm,fritz736x", "lantiq,xway", "lantiq,vr9"; + model = "AVM FRITZ!Box 7360 SL"; +}; + +&power_green { + label = "fritz7360sl:green:power"; +}; + +&power_red { + label = "fritz7360sl:red:power"; +}; + +&info_green { + label = "fritz7360sl:green:info"; +}; + +&wifi { + label = "fritz7360sl:green:wlan"; +}; + +&info_red { + label = "fritz7360sl:red:info"; +}; + +&dect { + label = "fritz7360sl:green:dect"; +}; + +&state_default { + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fixed-partitions"; + + urlader: partition@0 { + label = "urlader"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0xf60000>; + }; + + partition@f80000 { + label = "tffs (1)"; + reg = <0xf80000 0x40000>; + read-only; + }; + + partition@fc0000 { + label = "tffs (2)"; + reg = <0xfc0000 0x40000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts new file mode 100644 index 0000000000..a061a482da --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "vr9_avm_fritz736x.dtsi" + +#include +#include + +/ { + compatible = "avm,fritz7362sl", "avm,fritz736x", "lantiq,xway", "lantiq,vr9"; + model = "AVM FRITZ!Box 7362 SL"; +}; + +&power_green { + label = "fritz7362sl:green:power"; +}; + +&power_red { + label = "fritz7362sl:red:power"; +}; + +&info_green { + label = "fritz7362sl:green:info"; +}; + +&wifi { + label = "fritz7362sl:green:wlan"; +}; + +&info_red { + label = "fritz7362sl:red:info"; +}; + +&dect { + label = "fritz7362sl:green:dect"; +}; + +&state_default { + pcie-rst { + lantiq,pins = "io21"; + lantiq,open-drain = <1>; + lantiq,output = <1>; + }; +}; + +&spi { + status = "okay"; + + flash@4 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <4 0>; + spi-max-frequency = <1000000>; + + urlader: partition@0 { + reg = <0x0 0x40000>; + label = "urlader"; + read-only; + }; + + partition@40000 { + reg = <0x40000 0x60000>; + label = "tffs (1)"; + read-only; + }; + + partition@A0000 { + reg = <0xA0000 0x60000>; + label = "tffs (2)"; + read-only; + }; + }; +}; + +&localbus { + flash@1 { + compatible = "lantiq,nand-xway"; + lantiq,cs1 = <1>; + bank-width = <1>; + reg = <1 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + nand-ecc-mode = "on-die"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "ubi"; + reg = <0x400000 0x7c00000>; + }; + }; + }; +}; + +&pcie0 { + gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>; + + pcie@0 { + #size-cells = <1>; + #address-cells = <2>; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi new file mode 100644 index 0000000000..1553d2f7f4 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "avm,fritz736x", "lantiq,xway", "lantiq,vr9"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_red; + + led-dsl = &info_green; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + dect { + label = "dect"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + wifi { + label = "wifi"; + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + power_green: power { + gpios = <&gpio 32 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + power_red: power2 { + gpios = <&gpio 33 GPIO_ACTIVE_LOW>; + }; + + info_green: info_green { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + + wifi: wifi { + gpios = <&gpio 36 GPIO_ACTIVE_LOW>; + }; + + info_red: info_red { + gpios = <&gpio 34 GPIO_ACTIVE_LOW>; + }; + + dect: dect { + gpios = <&gpio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&urlader 0xa91>; + mtd-mac-address-increment = <(-2)>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + }; + + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rmii"; + phy-handle = <&phy1>; + }; + + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x00>; + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; + + phy1: ethernet-phy@1 { + reg = <0x01>; + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + phy-rst { + lantiq,pins = "io37", "io44"; + lantiq,pull = <0>; + lantiq,open-drain; + lantiq,output = <1>; + }; + }; + +}; + +&pcie0 { + status = "okay"; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <1>; + #address-cells = <2>; + device_type = "pci"; + + wifi@168c,002e { + compatible = "pci168c,002e"; + reg = <0 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts new file mode 100644 index 0000000000..43216d66be --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "avm,fritz7412", "lantiq,xway", "lantiq,vr9"; + model = "AVM FRITZ!Box 7412"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_red; + + led-dsl = &info; + led-wifi = &wifi; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + dect { + label = "dect"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_green: power_green { + label = "fritz7412:green:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + power_red: power_red { + label = "fritz7412:red:power"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + + fon { + label = "fritz7412:green:fon"; + gpios = <&gpio 34 GPIO_ACTIVE_LOW>; + }; + + dect { + label = "fritz7412:green:dect"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + wifi: wifi { + label = "fritz7412:green:wifi"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + + info: info { + label = "fritz7412:green:info"; + gpios = <&gpio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nand-xway"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + lantiq,cs = <1>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "urlader"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "nand-tffs"; + reg = <0x40000 0x400000>; + read-only; + }; + + partition@440000 { + label = "kernel"; + reg = <0x440000 0x400000>; + }; + + partition@840000 { + label = "ubi"; + reg = <0x840000 0x3000000>; + }; + + partition@3840000 { + label = "reserved-kernel"; + reg = <0x3840000 0x400000>; + read-only; + }; + + partition@3c40000 { + label = "reserved-filesystem"; + reg = <0x3c40000 0x3000000>; + read-only; + }; + + partition@6c40000 { + label = "config"; + reg = <0x6c40000 0x400000>; + read-only; + }; + + partition@6e40000 { + label = "nand-filesystem"; + reg = <0x6e40000 0x400000>; + read-only; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + gpio-reset = <&gpio 11 GPIO_ACTIVE_HIGH>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + + wifi@168c,002e { + compatible = "pci168c,002e"; + reg = <0 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pcie-rst { + lantiq,pins = "io11"; + lantiq,open-drain = <1>; + lantiq,output = <1>; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +ð0 { + lantiq,phys = <&gphy0>; + + interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mac-address = [ 00 11 22 33 44 55 ]; + lantiq,switch; + + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&vmmc { + status = "okay"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts new file mode 100644 index 0000000000..f6a2d9f6a7 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts @@ -0,0 +1,283 @@ +/dts-v1/; + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "bt,homehub-v5a", "lantiq,xway", "lantiq,vr9"; + model = "BT Home Hub 5A"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_blue; + led-upgrade = &power_blue; + + led-dsl = &broadband_blue; + led-wifi = &wireless_blue; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + restart { + label = "restart"; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* broadband-* is a single RGB led */ + broadband-red { + label = "bthomehubv5a:red:broadband"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + broadband-green { + label = "bthomehubv5a:green:broadband"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + }; + broadband_blue: broadband-blue { + label = "bthomehubv5a:blue:broadband"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + + /* wireless-* is a single RGB led */ + wireless-red { + label = "bthomehubv5a:red:wireless"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + wireless-green { + label = "bthomehubv5a:green:wireless"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + wireless_blue: wireless-blue { + label = "bthomehubv5a:blue:wireless"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + + /* power-* is a single RGB led */ + power_red: power-red { + label = "bthomehubv5a:red:power"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + power_green: power-green { + label = "bthomehubv5a:green:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + power_blue: power-blue { + label = "bthomehubv5a:blue:power"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + dimmed { + label = "dimmed"; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain; + }; + pcie_rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + lantiq,open-drain; + }; + usb_vbus { + lantiq,pins = "io33"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; +}; + +&localbus { + flash@1 { + compatible = "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <0x1 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + nand-on-flash-bbt; + nand-ecc-strength = <3>; + nand-ecc-step-size = <256>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0xa0000>; + read-only; + }; + partition@a0000 { + label = "uboot-env"; + reg = <0xa0000 0x20000>; + read-only; + }; + partition@c0000 { + label = "unused"; + reg = <0xc0000 0x40000>; + }; + partition@100000 { + label = "ubi"; + reg = <0x100000 0x7e80000>; + }; + /* + * last 512 KiB are for the bad block table, not writable + */ + }; + }; +}; + +&pci0 { + status = "okay"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + + wifi@168c,002d { + compatible = "pci168c,002d"; + reg = <0x7000 0 0 0 0>; + qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ + qca,disable-5ghz; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts new file mode 100644 index 0000000000..4631ad4ffe --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts @@ -0,0 +1,312 @@ +/dts-v1/; + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "buffalo,wbmr-300hpd", "lantiq,xway", "lantiq,vr9"; + model = "Buffalo WBMR-300HPD"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_g; + led-failsafe = &diag_r; + led-running = &power_g; + led-upgrade = &power_g; + + led-dsl = &dsl; + led-internet = &router_g; + led-wifi = &wifi_g; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + power { + label = "power"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + reset { + label = "reset"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&gpio 31 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + auto { + label = "auto"; + gpios = <&gpio 48 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,input-type = ; + }; + + router { + label = "router"; + gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,input-type = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + diag_r: diag_r { + label = "wbmr300:red:diag"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + default_state = "off"; + }; + + wifi_g: wifi_g { + label = "wbmr300:green:wifi"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; + + dsl: dsl { + label = "dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; + }; + + router_y: router_y { + label = "wbmr300:yellow:router"; + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + + wifi_y: wifi_y { + label = "wbmr300:yellow:wifi"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; + }; + + lan1: lan1 { + label = "wbmr300:green:lan1"; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + + wan: wan { + label = "wbmr300:green:wan"; + gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; + }; + + lan3: lan3 { + label = "wbmr300:green:lan3"; + gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + }; + + lan2: lan2 { + label = "wbmr300:green:lan2"; + gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; + }; + + internet_g: internet_g { + label = "wbmr300:green:internet"; + gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; + }; + + internet_y: internet_y { + label = "wbmr300:yellow:internet"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + }; + + router_g: router_g { + label = "wbmr300:green:router"; + gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; + }; + + power_g: power_g { + label = "wbmr300:green:power"; + gpios = <&gpio 49 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + lantiq,switch; + + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "mii"; + phy-handle = <&phy14>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <3>; + phy-mode = "mii"; + phy-handle = <&phy12>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy12: ethernet-phy@12 { + reg = <0x12>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy14: ethernet-phy@14 { + reg = <0x14>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + phy-rst { + lantiq,pins = "io42"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&spi { + status = "okay"; + + flash@4 { + compatible = "jedec,spi-nor"; + reg = <4>; + spi-max-frequency = <20000000>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x10000>; + label = "u-boot"; + read-only; + }; + + partition@10000 { + reg = <0x10000 0x10000>; + label = "gphyfirmware"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x80000>; + label = "dsl_fw"; + }; + + partition@de0000 { + reg = <0xa0000 0xf40000>; + label = "firmware"; + }; + + partition@fe0000 { + reg = <0xfe0000 0x10000>; + label = "sysconfig"; + read-only; + }; + + partition@ff0000 { + reg = <0xff0000 0x2000>; + label = "ubootconfig"; + }; + + partition@ff3000 { + reg = <0xff3000 0x2000>; + label = "board_config"; + read-only; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts new file mode 100644 index 0000000000..585521459b --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts @@ -0,0 +1,66 @@ +/dts-v1/; + + +#include "vr9_lantiq_easy80920.dtsi" + +/ { + compatible = "lantiq,easy80920-nand", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; + model = "Intel EASY80920 Nand"; + + chosen { + bootargs = "ubi.mtd=ubi ubi.block=0,rootfsA root=/dev/ubiblock0_1"; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x100000>; /* 1024 KB */ + }; + + partition@100000 { + label = "uboot_env"; + reg = <0x100000 0x40000>; /* 256 KB */ + }; + + partition@140000 { + label = "ubootconfigB"; + reg = <0x140000 0x40000>; /* 256 KB */ + }; + + partition@180000 { + label = "gphyfirmware"; + reg = <0x180000 0x40000>; /* 256 KB */ + }; + + partition@1c0000 { + label = "ubi"; + reg = <0x1c0000 0xc800000>; + }; + + partition@c9c0000 { + label = "calibration"; + reg = <0xc9c0000 0x100000>; + }; + + partition@cac0000 { + label = "res"; + reg = <0xcac0000 0x13540000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts new file mode 100644 index 0000000000..c204c5e093 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts @@ -0,0 +1,37 @@ +/dts-v1/; + +#include "vr9_lantiq_easy80920.dtsi" + +/ { + compatible = "lantiq,easy80920-nor", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; + model = "Intel EASY80920 Nor"; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7e0000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi new file mode 100644 index 0000000000..4fbc1ac496 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi @@ -0,0 +1,279 @@ +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-usb = &led_usb1; + led-usb2 = &led_usb2; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; +/* reset { + label = "reset"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + };*/ + paging { + label = "paging"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + power: power { + label = "easy80920:green:power"; + gpios = <&stp 9 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + warning { + label = "easy80920:green:warning"; + gpios = <&stp 22 GPIO_ACTIVE_HIGH>; + }; + fxs1 { + label = "easy80920:green:fxs1"; + gpios = <&stp 21 GPIO_ACTIVE_HIGH>; + }; + fxs2 { + label = "easy80920:green:fxs2"; + gpios = <&stp 20 GPIO_ACTIVE_HIGH>; + }; + fxo { + label = "easy80920:green:fxo"; + gpios = <&stp 19 GPIO_ACTIVE_HIGH>; + }; + led_usb1: usb1 { + label = "easy80920:green:usb1"; + gpios = <&stp 18 GPIO_ACTIVE_HIGH>; + }; + led_usb2: usb2 { + label = "easy80920:green:usb2"; + gpios = <&stp 15 GPIO_ACTIVE_HIGH>; + }; + sd { + label = "easy80920:green:sd"; + gpios = <&stp 14 GPIO_ACTIVE_HIGH>; + }; + wps { + label = "easy80920:green:wps"; + gpios = <&stp 12 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + lantiq,switch; + + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + }; + + wan: interface@1 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + lantiq,wan; + + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin3 { + lantiq,groups = "exin3"; + lantiq,function = "exin"; + }; + conf_out { + lantiq,pins = "io21", + "io33"; + lantiq,open-drain; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + conf_in { + lantiq,pins = "io39"; /* exin3 */ + lantiq,pull = <2>; + }; + }; +}; + +&spi { + status = "okay"; + + flash@4 { + compatible = "jedec,spi-nor"; + reg = <4>; + spi-max-frequency = <1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x20000>; + label = "SPI (RO) U-Boot Image"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "ENV_MAC"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x10000>; + label = "DPF"; + read-only; + }; + + partition@40000 { + reg = <0x40000 0x10000>; + label = "NVRAM"; + read-only; + }; + + partition@500000 { + reg = <0x50000 0x003a0000>; + label = "kernel"; + }; + }; + }; +}; + +&pci0 { + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; +}; + +&stp { + status = "okay"; + + lantiq,shadow = <0xffff>; + lantiq,groups = <0x7>; + lantiq,dsl = <0x3>; + lantiq,phy1 = <0x7>; + lantiq,phy2 = <0x7>; + /* lantiq,rising; */ +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts new file mode 100644 index 0000000000..cdba656e49 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts @@ -0,0 +1,186 @@ +/dts-v1/; + +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "netgear,dm200", "lantiq,xway", "lantiq,vr9"; + model = "Netgear DM200"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_amber; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl_green; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + annexa { + gpio-export,name = "annexa"; + gpio-export,output = <0>; + gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; + }; + annexb { + gpio-export,name = "annexb"; + gpio-export,output = <0>; + gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_amber: power_amber { + label = "dm200:amber:power"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + }; + power_green: power_green { + label = "dm200:green:power"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; + + lan_amber { + label = "dm200:amber:lan"; + gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; + }; + lan_green { + label = "dm200:green:lan"; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + + dsl_amber { + label = "dm200:amber:dsl"; + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + dsl_green: dsl_green { + label = "dm200:green:dsl"; + gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð0 { + lantiq,phys = <&gphy1>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&pcie0 { + status = "disabled"; +}; + +&spi { + status = "okay"; + + flash@4 { + compatible = "jedec,spi-nor"; + reg = <4>; + spi-max-frequency = <10000000>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fixed-partitions"; + + partition@0 { + reg = <0x0 0x20000>; + label = "uboot"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "gphyfirmware"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x7b0000>; + label = "firmware"; + }; + + partition@7e0000 { + reg = <0x7e0000 0x10000>; + label = "sysconfig"; + read-only; + }; + + partition@7f0000 { + reg = <0x7f0000 0x2000>; + label = "ubootconfig"; + read-only; + }; + + partition@7f2000 { + reg = <0x7f2000 0x1000>; + label = "ART"; + read-only; + }; + + partition@7f3000 { + reg = <0x7f3000 0x1000>; + label = "pot"; + read-only; + }; + + partition@7f4000 { + reg = <0x7f4000 0xc000>; + label = "ret"; + read-only; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts new file mode 100644 index 0000000000..9b3055983a --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "vr9_tplink_tdw89x0.dtsi" + +/ { + compatible = "tplink,tdw8970", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; + model = "TP-LINK TD-W8970"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts new file mode 100644 index 0000000000..725aa759d2 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts @@ -0,0 +1,33 @@ +/dts-v1/; + +#include "vr9_tplink_tdw89x0.dtsi" + +/ { + compatible = "tplink,tdw8980", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; + model = "TP-LINK TD-W8980"; + + gpio-leds { + wifi2 { + label = "tdw8980:green:wlan5ghz"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + state_default: pinmux { + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain; + }; + }; +}; + +&pci0 { + status = "okay"; + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi new file mode 100644 index 0000000000..eabbc0257f --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi @@ -0,0 +1,272 @@ +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + /* the power led can't be controlled, use the wps led instead */ + led-boot = &wps; + led-failsafe = &wps; + + led-dsl = &dsl; + led-internet = &internet; + led-wifi = &wifi; + led-usb = &led_usb0; + led-usb2 = &led_usb2; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wifi { + label = "wifi"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,input-type = ; + }; + + wps { + label = "wps"; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + /* + power is not controllable via gpio + */ + dsl: dsl { + label = "tdw89x0:green:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; + }; + internet: internet { + label = "tdw89x0:green:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + }; + + led_usb0: usb0 { + label = "tdw89x0:green:usb"; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + }; + led_usb2: usb2 { + label = "tdw89x0:green:usb2"; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + }; + wps: wps { + label = "tdw89x0:green:wps"; + gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + }; + }; + + wifi-leds { + compatible = "gpio-leds"; + + wifi: wifi { + label = "tdw89x0:green:wifi"; + gpios = <&ath9k 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + }; + + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>; + pinctrl-names = "default"; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&ath9k_cal 0xf100>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + // gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + phy-rst { + lantiq,pins = "io42"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&pcie0 { + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + + ath9k: wifi@168c,002e { + compatible = "pci168c,002e"; + reg = <0 0 0 0 0>; + #gpio-cells = <2>; + gpio-controller; + qca,no-eeprom; + qca,disable-5ghz; + mtd-mac-address = <&ath9k_cal 0xf100>; + mtd-mac-address-increment = <2>; + }; + }; +}; + +&spi { + status = "okay"; + + flash@4 { + compatible = "jedec,spi-nor"; + reg = <4>; + spi-max-frequency = <33250000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x20000>; + label = "u-boot"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x7a0000>; + label = "firmware"; + }; + + partition@7c0000 { + reg = <0x7c0000 0x10000>; + label = "config"; + read-only; + }; + + ath9k_cal: partition@7d0000 { + reg = <0x7d0000 0x30000>; + label = "boardconfig"; + read-only; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts new file mode 100644 index 0000000000..98f2282579 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts @@ -0,0 +1,92 @@ +/dts-v1/; + +#include "vr9_tplink_vr200.dtsi" + +/ { + compatible = "tplink,vr200", "lantiq,xway", "lantiq,vr9"; + model = "TP-LINK Archer VR200"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &dsl; + led-internet = &internet; + led-wifi = &wlan5g; + + led-usb = &led_usb; + led-usb2 = &led_usb; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wifi { + label = "wifi"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,input-type = ; + }; + + wps { + label = "wps"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + led { + label = "led"; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power: power { + label = "vr200:blue:power"; + gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + dsl: dsl { + label = "vr200:blue:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + internet: internet { + label = "vr200:blue:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "vr200:blue:usb"; + gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + }; + eth { + label = "vr200:blue:lan"; + gpios = <&gpio 40 GPIO_ACTIVE_LOW>; + }; + wlan { + label = "vr200:blue:wlan"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + }; + wlan5g: wifi { + label = "vr200:blue:wlan5g"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + led_wps { + label = "vr200:blue:wps"; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi new file mode 100644 index 0000000000..77b4f0defb --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi @@ -0,0 +1,213 @@ +#include "vr9.dtsi" + +#include +#include + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x7f00000>; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>; + pinctrl-names = "default"; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&romfile 0xf100>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + // gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + phy-rst { + lantiq,pins = "io42"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; +}; + +&pcie0 { + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + + wifi@0,0 { + reg = <0 0 0 0 0>; + mediatek,mtd-eeprom = <&radio 0x0000>; + big-endian; + ieee80211-freq-limit = <5000000 6000000>; + mtd-mac-address = <&romfile 0xf100>; + mtd-mac-address-increment = <2>; + }; + }; +}; + +&pci0 { + status = "okay"; + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +&spi { + status = "okay"; + + flash@4 { + compatible = "jedec,spi-nor"; + reg = <4>; + spi-max-frequency = <33250000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x20000>; + label = "u-boot"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0xf90000>; + label = "firmware"; + }; + + partition@fb0000 { + reg = <0xfb0000 0x10000>; + label = "radioDECT"; + read-only; + }; + + partition@fc0000 { + reg = <0xfc0000 0x10000>; + label = "config"; + read-only; + }; + + romfile: partition@fd0000 { + reg = <0xfd0000 0x10000>; + label = "romfile"; + read-only; + }; + + partition@fe0000 { + reg = <0xfe0000 0x10000>; + label = "rom"; + read-only; + }; + + radio: partition@ff0000 { + reg = <0xff0000 0x10000>; + label = "radio"; + read-only; + }; + }; + }; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts new file mode 100644 index 0000000000..2e25a72a83 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts @@ -0,0 +1,99 @@ +/dts-v1/; + +#include "vr9_tplink_vr200.dtsi" + +/ { + compatible = "tplink,vr200v", "lantiq,xway", "lantiq,vr9"; + model = "TP-LINK Archer VR200v"; + + chosen { + bootargs = "console=ttyLTQ0,115200 mem=126M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; + }; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + + led-dsl = &dsl; + led-internet = &internet; + led-wifi = &wlan5g; + + led-usb = &led_usb; + led-usb2 = &led_usb; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wifi { + label = "wifi"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,input-type = ; + }; + + wps { + label = "wps"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + dect_paging { + label = "dect_paging"; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + power: power { + label = "vr200v:blue:power"; + gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + dsl: dsl { + label = "vr200v:blue:dsl"; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + internet: internet { + label = "vr200v:blue:internet"; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + led_usb: usb { + label = "vr200v:blue:usb"; + gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + }; + eth { + label = "vr200v:blue:lan"; + gpios = <&gpio 40 GPIO_ACTIVE_LOW>; + }; + wlan { + label = "vr200v:blue:wlan"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + }; + wlan5g: wifi { + label = "vr200v:blue:wlan5g"; + gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + }; + phone { + label = "vr200v:blue:phone"; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&vmmc { + status = "okay"; + gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay + &gpio 31 GPIO_ACTIVE_HIGH //still unknown + &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts new file mode 100644 index 0000000000..4d7aac325b --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts @@ -0,0 +1,71 @@ +/dts-v1/; + +#include "vr9_zyxel_p-2812hnu-fx.dtsi" + +/ { + compatible = "zyxel,p-2812hnu-f1", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; + model = "ZyXEL P-2812HNU-F1"; + + aliases { + led-usb = &led_usb1; + led-usb2 = &led_usb2; + }; + + leds { + led_usb1: usb1 { + label = "p2812hnuf1:green:usb1"; + gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + }; + led_usb2: usb2 { + label = "p2812hnuf1:green:usb2"; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + }; + partition@40000 { + label = "uboot-env"; + reg = <0x40000 0x20000>; + }; + partition@60000 { + label = "kernel"; + reg = <0x60000 0x300000>; + }; + partition@360000 { + label = "ubi"; + reg = <0x360000 0x7ca0000>; + }; + }; + }; +}; + +&pci0 { + wifi@1814,3062 { + compatible = "pci1814,3062"; + reg = <0x7000 0 0 0 0>; + ralink,eeprom = "RT3062.eeprom"; + }; +}; + +&pcie0 { + status = "disabled"; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts new file mode 100644 index 0000000000..7da1533809 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts @@ -0,0 +1,65 @@ +/dts-v1/; + +#include "vr9_zyxel_p-2812hnu-fx.dtsi" + +/ { + compatible = "zyxel,p-2812hnu-f3", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; + model = "ZyXEL P-2812HNU-F3"; +}; + +&pci0 { + wifi@1814,3092 { + compatible = "pci1814,3092"; + reg = <0x7000 0 0 0 0>; + ralink,eeprom = "RT3092.eeprom"; + }; +}; + +&localbus { + flash@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + + pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x50000>; + read-only; + }; + partition@50000 { + label = "uboot-env"; + reg = <0x50000 0x10000>; + }; + partition@60000 { + label = "unused"; + reg = <0x60000 0x7a0000>; + }; + }; + }; + + flash@1 { + compatible = "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <1 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x200000>; + }; + partition@200000 { + label = "ubi"; + reg = <0x200000 0x7e00000>; + }; + }; +}; diff --git a/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi new file mode 100644 index 0000000000..5f8392ca44 --- /dev/null +++ b/target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi @@ -0,0 +1,259 @@ +#include "vr9.dtsi" + +#include +#include + +/ { + compatible = "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + + led-dsl = &dsl_green; + led-internet = &internet_green; + led-wifi = &wireless_green; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + rfkill { + label = "rfkill"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + internet_red { + label = "p2812hnufx:red:internet"; + gpios = <&stp 16 GPIO_ACTIVE_LOW>; + }; + internet_green: internet_green { + label = "p2812hnufx:green:internet"; + gpios = <&stp 17 GPIO_ACTIVE_LOW>; + }; + dsl_green: dsl_green { + label = "p2812hnufx:green:dsl"; + gpios = <&stp 18 GPIO_ACTIVE_LOW>; + }; + dsl_orange { + label = "p2812hnufx:orange:dsl"; + gpios = <&stp 19 GPIO_ACTIVE_LOW>; + }; + wireless_orange { + label = "p2812hnufx:orange:wlan"; + gpios = <&stp 20 GPIO_ACTIVE_LOW>; + }; + wireless_green: wireless_green { + label = "p2812hnufx:green:wlan"; + gpios = <&stp 21 GPIO_ACTIVE_LOW>; + }; + power_red: power { + label = "p2812hnufx:red:power"; + gpios = <&stp 22 GPIO_ACTIVE_LOW>; + }; + power_green: power2 { + label = "p2812hnufx:green:power"; + gpios = <&stp 23 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + phone1 { + label = "p2812hnufx:green:phone"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + phone1warn { + label = "p2812hnufx:orange:phone"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + phone2warn { + label = "p2812hnufx:orange:phone2"; + gpios = <&gpio 26 GPIO_ACTIVE_LOW>; + }; + phone2 { + label = "p2812hnufx:green:phone2"; + gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð0 { + pinctrl-0 = <&mdio_pins>, + <&gphy0_led0_pins>, <&gphy0_led2_pins>, + <&gphy1_led1_pins>, <&gphy1_led2_pins>; + pinctrl-names = "default"; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mac-address = [ 00 11 22 33 44 55 ]; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&gphy0 { + lantiq,gphy-mode = ; +}; + +&gphy1 { + lantiq,gphy-mode = ; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin3 { + lantiq,groups = "exin3"; + lantiq,function = "exin"; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + ifxhcd-rst { + lantiq,pins = "io33"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; +}; + +&pci0 { + status = "okay"; + + pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>; + pinctrl-names = "default"; + + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; +}; + +&stp { + status = "okay"; + + lantiq,shadow = <0xffffff>; + lantiq,groups = <0x7>; + lantiq,dsl = <0x0>; + lantiq,phy1 = <0x0>; + lantiq,phy2 = <0x0>; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; diff --git a/target/linux/lantiq/image/Makefile b/target/linux/lantiq/image/Makefile index 2352cb6b5e..b169d93859 100644 --- a/target/linux/lantiq/image/Makefile +++ b/target/linux/lantiq/image/Makefile @@ -15,9 +15,9 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk ifeq ($(SUBTARGET),xway) - UBIFS_OPTS := -m 512 -e 15872 -c 1959 + UBIFS_OPTS := -m 512 -e 15872 -c 1959 else - UBIFS_OPTS := -m 2048 -e 126KiB -c 4096 + UBIFS_OPTS := -m 2048 -e 126KiB -c 4096 endif define Build/append-avm-fakeroot @@ -29,12 +29,12 @@ define Build/dgn3500-sercom-footer endef define Build/mkbrncmdline - mkbrncmdline -i $@ -o $@.new BRN-BOOT - mv $@.new $@ + mkbrncmdline -i $@ -o $@.new BRN-BOOT + mv $@.new $@ endef define Build/mkbrnimg - mkbrnimg -s $(SIGNATURE) -m $(MAGIC) -p $(CRC32_POLY) -o $@ $(IMAGE_KERNEL) $(IMAGE_ROOTFS) + mkbrnimg -s $(SIGNATURE) -m $(MAGIC) -p $(CRC32_POLY) -o $@ $(IMAGE_KERNEL) $(IMAGE_ROOTFS) endef define Build/fullimage @@ -52,6 +52,9 @@ define Build/fullimage rm $@.tmp endef +DEVICE_VARS += SIGNATURE MAGIC CRC32_POLY +DTS_DIR := $(DTS_DIR)/lantiq + # Shared device definition: applies to every defined device define Device/Default PROFILES = Default @@ -60,12 +63,12 @@ define Device/Default KERNEL := kernel-bin | append-dtb | lzma | uImage lzma KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma FILESYSTEMS := squashfs - IMAGE_SIZE := + SOC := $(DEFAULT_SOC) + DEVICE_DTS = $$(SOC)_$(1) SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) IMAGES := sysupgrade.bin - IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata | check-size endef -DEVICE_VARS += IMAGE_SIZE define Device/NAND/xway BLOCKSIZE := 16k @@ -89,760 +92,47 @@ endef define Device/lantiqBrnImage KERNEL := kernel-bin | append-dtb | mkbrncmdline | lzma-no-dict IMAGES := factory.bin - IMAGE/factory.bin := mkbrnimg | check-size $$$$(IMAGE_SIZE) + IMAGE/factory.bin := mkbrnimg | check-size endef -DEVICE_VARS += SIGNATURE MAGIC CRC32_POLY define Device/lantiqFullImage KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | pad-offset 4 0 IMAGES := sysupgrade.bin fullimage.bin - IMAGE/fullimage.bin := fullimage | check-size $$$$(IMAGE_SIZE) + IMAGE/fullimage.bin := fullimage | check-size endef define Device/AVM + DEVICE_VENDOR := AVM KERNEL := kernel-bin | append-dtb | lzma | eva-image KERNEL_INITRAMFS := $$(KERNEL) IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-avm-fakeroot | \ - append-rootfs | pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE) + append-rootfs | pad-rootfs | append-metadata | check-size endef ifeq ($(SUBTARGET),ase) - -define Device/allnet_all0333cj - IMAGE_SIZE := 3700k - DEVICE_DTS := ALL0333CJ - DEVICE_TITLE := Allnet ALL0333CJ - DEVICE_PACKAGES := kmod-ltq-adsl-ase kmod-ltq-adsl-ase-mei \ - kmod-ltq-adsl-ase-fw-b kmod-ltq-atm-ase \ - ltq-adsl-app ppp-mod-pppoe -endef -TARGET_DEVICES += allnet_all0333cj - -define Device/netgear_dgn1000b - IMAGE_SIZE := 6000k - DEVICE_DTS := DGN1000B - DEVICE_TITLE := Netgear DGN1000B - DEVICE_PACKAGES := kmod-ltq-adsl-ase kmod-ltq-adsl-ase-mei \ - kmod-ltq-adsl-ase-fw-b kmod-ltq-atm-ase \ - ltq-adsl-app ppp-mod-pppoe - SUPPORTED_DEVICES += DGN1000B -endef -TARGET_DEVICES += netgear_dgn1000b - +DEFAULT_SOC := amazonse +include amazonse.mk endif ifeq ($(SUBTARGET),xway_legacy) - -define Device/arcadyan_arv4520pw - IMAGE_SIZE := 3648k - DEVICE_DTS := ARV4520PW - DEVICE_TITLE := Easybox 800, WAV-281 - ARV4520PW - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-rt61-pci wpad-mini - SUPPORTED_DEVICES += ARV4520PW -endef -TARGET_DEVICES += arcadyan_arv4520pw - -define Device/arcadyan_arv4525pw - IMAGE_SIZE := 3776k - DEVICE_DTS := ARV4525PW - DEVICE_TITLE := Speedport W502V Typ A - ARV4525PW - DEVICE_PACKAGES := kmod-ath5k wpad-mini \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa -swconfig - SUPPORTED_DEVICES += ARV4525PW -endef -TARGET_DEVICES += arcadyan_arv4525pw - -define Device/arcadyan_arv452cqw - IMAGE_SIZE := 3776k - DEVICE_DTS := ARV452CQW - DEVICE_TITLE := Easybox 801 - ARV452CQW - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ath5k wpad-mini \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa - SUPPORTED_DEVICES += ARV452CQW -endef -TARGET_DEVICES += arcadyan_arv452cqw - -define Device/arcadyan_arv4518pwr01 - IMAGE_SIZE := 3776k - DEVICE_DTS := ARV4518PWR01 - DEVICE_TITLE := ARV4518PWR01 - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath5k wpad-mini - SUPPORTED_DEVICES += ARV4518PWR01 -endef -TARGET_DEVICES += arcadyan_arv4518pwr01 - -define Device/arcadyan_arv4518pwr01a - IMAGE_SIZE := 3776k - DEVICE_DTS := ARV4518PWR01A - DEVICE_TITLE := ARV4518PWR01A - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath5k wpad-basic - SUPPORTED_DEVICES += ARV4518PWR01A -endef -TARGET_DEVICES += arcadyan_arv4518pwr01a - +DEFAULT_SOC := danube +include xway_legacy.mk endif ifeq ($(SUBTARGET),xway) - -# Danube - -define Device/bt_homehub-v2b - $(Device/NAND) - BOARD_NAME := BTHOMEHUBV2B - DEVICE_DTS := BTHOMEHUBV2B - DEVICE_TITLE := BT Home Hub 2B - DEVICE_PACKAGES := kmod-usb-dwc2 \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - kmod-ltq-deu-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath9k kmod-owl-loader wpad-basic - SUPPORTED_DEVICES += BTHOMEHUBV2B -endef -TARGET_DEVICES += bt_homehub-v2b - -define Device/lantiq_easy50712 - DEVICE_DTS := EASY50712 - IMAGE_SIZE := 3776k - DEVICE_TITLE := Lantiq Danube - EASY50712 -endef -TARGET_DEVICES += lantiq_easy50712 - -define Device/audiocodes_mp-252 - IMAGE_SIZE := 14848k - DEVICE_DTS := ACMP252 - DEVICE_TITLE := AudioCodes MediaPack MP-252 - DEVICE_PACKAGES := kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - kmod-ltq-tapi kmod-ltq-vmmc \ - kmod-usb-ledtrig-usbport kmod-usb-dwc2 \ - kmod-rt2800-pci \ - ltq-adsl-app ppp-mod-pppoa \ - wpad-basic - SUPPORTED_DEVICES += ACMP252 -endef -TARGET_DEVICES += audiocodes_mp-252 - -define Device/arcadyan_arv4510pw - IMAGE_SIZE := 15616k - DEVICE_DTS := ARV4510PW - DEVICE_TITLE := Wippies, Elisa - ARV4510PW - DEVICE_PACKAGES := kmod-usb-ledtrig-usbport kmod-usb2-pci kmod-usb-uhci \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-tapi kmod-ltq-vmmc \ - kmod-rt2800-pci kmod-ath5k wpad-basic - SUPPORTED_DEVICES += ARV4510PW -endef -TARGET_DEVICES += arcadyan_arv4510pw - -define Device/arcadyan_arv7525pw - IMAGE_SIZE := 3776k - DEVICE_DTS := ARV4510PW - DEVICE_TITLE := Speedport W303V Typ A - ARV7525PW - DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa -swconfig - SUPPORTED_DEVICES += ARV4510PW -endef -TARGET_DEVICES += arcadyan_arv7525pw - -define Device/arcadyan_arv4519pw - IMAGE_SIZE := 3776k - DEVICE_DTS := ARV4519PW - DEVICE_TITLE := Vodafone, Pirelli - ARV4519PW - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa - SUPPORTED_DEVICES += ARV4519PW -endef -TARGET_DEVICES += arcadyan_arv4519pw - -define Device/arcadyan_arv7506pw11 - IMAGE_SIZE := 7808k - DEVICE_DTS := ARV7506PW11 - DEVICE_TITLE := Alice/O2 IAD 4421 - ARV7506PW11 - DEVICE_PACKAGES := kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-rt2800-pci wpad-basic - SUPPORTED_DEVICES += ARV7506PW11 -endef -TARGET_DEVICES += arcadyan_arv7506pw11 - -define Device/arcadyan_arv7510pw22 - IMAGE_SIZE := 31232k - DEVICE_DTS := ARV7510PW22 - DEVICE_TITLE := Astoria - ARV7510PW22 - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-tapi kmod-ltq-vmmc \ - kmod-rt2800-pci wpad-basic \ - kmod-usb-uhci kmod-usb2 kmod-usb2-pci - SUPPORTED_DEVICES += ARV7510PW22 -endef -TARGET_DEVICES += arcadyan_arv7510pw22 - -define Device/arcadyan_arv7518pw - IMAGE_SIZE := 7872k - DEVICE_DTS := ARV7518PW - DEVICE_TITLE := Astoria - ARV7518PW - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath9k kmod-owl-loader wpad-basic - SUPPORTED_DEVICES += ARV7518PW -endef -TARGET_DEVICES += arcadyan_arv7518pw - -define Device/arcadyan_arv7519pw - IMAGE_SIZE := 15488k - DEVICE_DTS := ARV7519PW - DEVICE_TITLE := Astoria - ARV7519PW - DEVICE_PACKAGES := kmod-usb-dwc2 \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-rt2800-pci wpad-basic - SUPPORTED_DEVICES += ARV7519PW -endef -TARGET_DEVICES += arcadyan_arv7519pw - -define Device/arcadyan_arv752dpw - IMAGE_SIZE := 7872k - DEVICE_DTS := ARV752DPW - DEVICE_TITLE := Easybox 802 - ARV752DPW - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-tapi kmod-ltq-vmmc \ - kmod-rt2800-pci wpad-basic - SUPPORTED_DEVICES += ARV752DPW -endef -TARGET_DEVICES += arcadyan_arv752dpw - -define Device/arcadyan_arv752dpw22 - IMAGE_SIZE := 7616k - DEVICE_DTS := ARV752DPW22 - DEVICE_TITLE := Easybox 803 - ARV752DPW22 - DEVICE_PACKAGES := kmod-usb2-pci kmod-usb-uhci kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-tapi kmod-ltq-vmmc \ - kmod-rt2800-pci wpad-basic - SUPPORTED_DEVICES += ARV752DPW22 -endef -TARGET_DEVICES += arcadyan_arv752dpw22 - -define Device/arcadyan_arv8539pw22 - IMAGE_SIZE := 7616k - DEVICE_DTS := ARV8539PW22 - DEVICE_TITLE := Speedport W504V Typ A - ARV8539PW22 - DEVICE_PACKAGES := kmod-usb-dwc2 \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath9k kmod-owl-loader wpad-basic - SUPPORTED_DEVICES += ARV8539PW22 -endef -TARGET_DEVICES += arcadyan_arv8539pw22 - -define Device/siemens_gigaset-sx76x - IMAGE_SIZE := 7680k - DEVICE_DTS := GIGASX76X - DEVICE_TITLE := Gigaset sx76x - DEVICE_PACKAGES := kmod-usb-dwc2 \ - kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ - kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ - ltq-adsl-app ppp-mod-pppoe \ - kmod-ath5k wpad-basic - SUPPORTED_DEVICES += GIGASX76X -endef -TARGET_DEVICES += siemens_gigaset-sx76x - - -# AR9 - -define Device/bt_homehub-v3a - $(Device/NAND) - BOARD_NAME := BTHOMEHUBV3A - DEVICE_DTS := BTHOMEHUBV3A - DEVICE_TITLE := BT Home Hub 3A - DEVICE_PACKAGES := kmod-usb-dwc2 \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ - kmod-ltq-deu-ar9 \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath9k kmod-owl-loader wpad-basic \ - uboot-envtools - SUPPORTED_DEVICES += BTHOMEHUBV3A -endef -TARGET_DEVICES += bt_homehub-v3a - -DGN3500_KERNEL_OFFSET_HEX=0x50000 -DGN3500_KERNEL_OFFSET_DEC=327680 -define Device/netgear_dgn3500 - DEVICE_DTS := DGN3500 - IMAGE_SIZE := 16000k - IMAGES := \ - sysupgrade-na.bin sysupgrade.bin \ - factory-na.img factory.img - IMAGE/sysupgrade-na.bin := \ - append-kernel | append-rootfs | dgn3500-sercom-footer 0x0 "NA" | \ - pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := \ - append-kernel | append-rootfs | dgn3500-sercom-footer 0x0 "WW" | \ - pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE) - IMAGE/factory-na.img := \ - pad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \ - dgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) "NA" | pad-rootfs | \ - check-size 16320k | pad-to 16384k - IMAGE/factory.img := \ - pad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \ - dgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) "WW" | pad-rootfs | \ - check-size 16320k | pad-to 16384k - DEVICE_TITLE := Netgear DGN3500 - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ath9k kmod-owl-loader wpad-basic \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-deu-ar9 - SUPPORTED_DEVICES += DGN3500 -endef -TARGET_DEVICES += netgear_dgn3500 - -define Device/netgear_dgn3500b - DEVICE_DTS := DGN3500B - IMAGE_SIZE := 16000k - IMAGES += factory.img - IMAGE/sysupgrade.bin := \ - append-kernel | append-rootfs | dgn3500-sercom-footer 0x0 "DE" | \ - pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE) - IMAGE/factory.img := \ - pad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \ - dgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) "DE" | pad-rootfs | \ - check-size 16320k | pad-to 16384k - DEVICE_TITLE := Netgear DGN3500B - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ath9k kmod-owl-loader wpad-basic \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-deu-ar9 - SUPPORTED_DEVICES += DGN3500B -endef -TARGET_DEVICES += netgear_dgn3500b - -define Device/buffalo_wbmr-hp-g300h-a - IMAGE_SIZE := 31488k - DEVICE_DTS := WBMR - DEVICE_TITLE := Buffalo WBMR-HP-G300H (A) - WBMR - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath9k kmod-owl-loader wpad-basic - SUPPORTED_DEVICES := WBMR buffalo,wbmr-hp-g300h -endef -TARGET_DEVICES += buffalo_wbmr-hp-g300h-a - -define Device/buffalo_wbmr-hp-g300h-b - IMAGE_SIZE := 31488k - DEVICE_DTS := WBMR - DEVICE_TITLE := Buffalo WBMR-HP-G300H (B) - WBMR - DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ath9k kmod-owl-loader wpad-basic - SUPPORTED_DEVICES := WBMR buffalo,wbmr-hp-g300h -endef -TARGET_DEVICES += buffalo_wbmr-hp-g300h-b - -define Device/avm_fritz7312 - $(Device/AVM) - DEVICE_DTS := FRITZ7312 - IMAGE_SIZE := 15744k - DEVICE_TITLE := AVM FRITZ!Box 7312 - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-deu-ar9 -swconfig -endef -TARGET_DEVICES += avm_fritz7312 - -define Device/avm_fritz7320 - $(Device/AVM) - DEVICE_DTS := FRITZ7320 - IMAGE_SIZE := 15744k - DEVICE_TITLE := AVM FRITZ!Box 7320 - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoa \ - kmod-ltq-deu-ar9 kmod-usb-dwc2 -swconfig - SUPPORTED_DEVICES += FRITZ7320 -endef -TARGET_DEVICES += avm_fritz7320 - -define Device/zte_h201l - IMAGE_SIZE := 7808k - DEVICE_DTS := H201L - DEVICE_TITLE := ZTE H201L - H201L - DEVICE_PACKAGES := kmod-ath9k-htc wpad-basic \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoe \ - kmod-ltq-deu-ar9 kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ - kmod-ltq-tapi kmod-ltq-vmmc - SUPPORTED_DEVICES += H201L -endef -TARGET_DEVICES += zte_h201l - -define Device/zyxel_p-2601hn - IMAGE_SIZE := 15616k - DEVICE_DTS := P2601HNFX - DEVICE_TITLE := ZyXEL P-2601HN-Fx - DEVICE_PACKAGES := kmod-rt2800-usb wpad-basic \ - kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ - kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ - ltq-adsl-app ppp-mod-pppoe \ - kmod-ltq-deu-ar9 kmod-usb-dwc2 - SUPPORTED_DEVICES += P2601HNFX -endef -TARGET_DEVICES += zyxel_p-2601hn - - +include danube.mk +include ar9.mk endif - ifeq ($(SUBTARGET),xrx200) - -# VR9 - -define Device/zyxel_p-2812hnu-f1 - $(Device/NAND) - BOARD_NAME := P2812HNUF1 - DEVICE_DTS := P2812HNUF1 - DEVICE_TITLE := ZyXEL P-2812HNU-F1 - DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport - KERNEL_SIZE := 3072k - SUPPORTED_DEVICES += P2812HNUF1 -endef -TARGET_DEVICES += zyxel_p-2812hnu-f1 - -define Device/zyxel_p-2812hnu-f3 - $(Device/NAND) - BOARD_NAME := P2812HNUF3 - DEVICE_DTS := P2812HNUF3 - DEVICE_TITLE := ZyXEL P-2812HNU-F3 - DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 - SUPPORTED_DEVICES += P2812HNUF3 -endef -TARGET_DEVICES += zyxel_p-2812hnu-f3 - -define Device/arcadyan_arv7519rw22 - IMAGE_SIZE := 31232k - DEVICE_DTS := ARV7519RW22 - DEVICE_TITLE := Livebox Astoria ARV7519RW22 - DEVICE_PACKAGES := kmod-usb-dwc2 - SUPPORTED_DEVICES += ARV7519RW22 -endef -TARGET_DEVICES += arcadyan_arv7519rw22 - -define Device/alphanetworks_asl56026 - DEVICE_DTS := ASL56026 - IMAGE_SIZE := 7488k - DEVICE_TITLE := BT OpenReach - ECI VDSL Modem V-2FUb/I -endef -TARGET_DEVICES += alphanetworks_asl56026 - -define Device/bt_homehub-v5a - $(Device/NAND) - BOARD_NAME := BTHOMEHUBV5A - DEVICE_DTS := BTHOMEHUBV5A - DEVICE_TITLE := BT Home Hub 5A - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader \ - kmod-ath10k-ct ath10k-firmware-qca988x-ct wpad-basic kmod-usb-dwc2 - SUPPORTED_DEVICES += BTHOMEHUBV5A -endef -TARGET_DEVICES += bt_homehub-v5a - -define Device/netgear_dm200 - DEVICE_DTS := DM200 - IMAGES := sysupgrade.bin factory.img - IMAGE/sysupgrade.bin := append-kernel | \ - pad-offset 64k 64 | append-uImage-fakehdr filesystem | \ - pad-offset 64k 64 | append-uImage-fakehdr filesystem | \ - append-rootfs | pad-rootfs | append-metadata | check-size $$$$(IMAGE_SIZE) - IMAGE/factory.img := $$(IMAGE/sysupgrade.bin) | netgear-dni - IMAGE_SIZE := 7872k - DEVICE_TITLE := Netgear DM200 - NETGEAR_BOARD_ID := DM200 - NETGEAR_HW_ID := 29765233+8+0+64+0+0 -endef -DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID -TARGET_DEVICES += netgear_dm200 - -define Device/lantiq_easy80920-nand - $(Device/lantiqFullImage) - DEVICE_DTS := EASY80920NAND - IMAGE_SIZE := 64512k - DEVICE_TITLE := Lantiq VR9 - EASY80920NAND - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport -endef -TARGET_DEVICES += lantiq_easy80920-nand - -define Device/lantiq_easy80920-nor - DEVICE_DTS := EASY80920NOR - IMAGE_SIZE := 7936k - DEVICE_TITLE := Lantiq VR9 - EASY80920NOR - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport -endef -TARGET_DEVICES += lantiq_easy80920-nor - -define Device/avm_fritz3370 - $(Device/AVM) - $(Device/NAND) - DEVICE_DTS := FRITZ3370 - DEVICE_TITLE := AVM FRITZ!Box 3370 Rev. 2 - KERNEL_SIZE := 4096k - UBINIZE_OPTS := -E 5 - IMAGES += eva-kernel.bin eva-filesystem.bin - IMAGE/eva-kernel.bin := append-kernel - IMAGE/eva-filesystem.bin := append-ubi - DEVICE_PACKAGES := kmod-ath9k wpad-basic kmod-usb-dwc2 fritz-tffs -endef - -define Device/avm_fritz3370-rev2-hynix - $(Device/avm_fritz3370) - DEVICE_DTS := FRITZ3370-REV2-HYNIX - DEVICE_TITLE := AVM FRITZ!Box 3370 Rev. 2 (Hynix NAND) -endef -TARGET_DEVICES += avm_fritz3370-rev2-hynix - -define Device/avm_fritz3370-rev2-micron - $(Device/avm_fritz3370) - DEVICE_DTS := FRITZ3370-REV2-MICRON - DEVICE_TITLE := AVM FRITZ!Box 3370 Rev. 2 (Micron NAND) -endef -TARGET_DEVICES += avm_fritz3370-rev2-micron - -define Device/avm_fritz7360sl - $(Device/AVM) - IMAGE_SIZE := 15744k - DEVICE_DTS := FRITZ7360SL - DEVICE_TITLE := AVM FRITZ!Box 7360 SL - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 - SUPPORTED_DEVICES += FRITZ7360SL -endef -TARGET_DEVICES += avm_fritz7360sl - -define Device/avm_fritz7412 - $(Device/AVM) - $(Device/NAND) - BOARD_NAME := FRITZ7412 - DEVICE_DTS := FRITZ7412 - KERNEL_SIZE := 4096k - IMAGE_SIZE := 49152k - DEVICE_TITLE := AVM FRITZ!Box 7412 - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-ltq-tapi kmod-ltq-vmmc fritz-tffs-nand fritz-caldata -endef -TARGET_DEVICES += avm_fritz7412 - -define Device/avm_fritz7362sl - $(Device/AVM) - $(Device/NAND) - KERNEL_SIZE := 4096k - IMAGE_SIZE := 49152k - DEVICE_DTS := FRITZ7362SL - DEVICE_TITLE := AVM FRITZ!Box 7362 SL - DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 fritz-tffs -endef -TARGET_DEVICES += avm_fritz7362sl - -define Device/arcadyan_vg3503j - IMAGE_SIZE := 8000k - DEVICE_DTS := VG3503J - DEVICE_TITLE := BT OpenReach - ECI VDSL Modem V-2FUb/R - SUPPORTED_DEVICES += VG3503J -endef -TARGET_DEVICES += arcadyan_vg3503j - +DEFAULT_SOC := vr9 include tp-link.mk - -define Device/buffalo_wbmr-300hpd - IMAGE_SIZE := 15616k - DEVICE_DTS := WBMR300 - DEVICE_TITLE := Buffalo WBMR-300HPD - DEVICE_PACKAGES := kmod-mt7603 wpad-basic kmod-usb-dwc2 - SUPPORTED_DEVICES += WBMR300 -endef -TARGET_DEVICES += buffalo_wbmr-300hpd - -define Device/arcadyan_vgv7510kw22-nor - IMAGE_SIZE := 15232k - DEVICE_DTS := VGV7510KW22NOR - DEVICE_TITLE := o2 Box 6431 / Arcadyan VGV7510KW22 (NOR) - DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc - SUPPORTED_DEVICES += VGV7510KW22NOR -endef -TARGET_DEVICES += arcadyan_vgv7510kw22-nor - -define Device/arcadyan_vgv7510kw22-brn - $(Device/lantiqBrnImage) - IMAGE_SIZE := 7168k - DEVICE_DTS := VGV7510KW22BRN - SIGNATURE := BRNDA6431 - MAGIC := 0x12345678 - CRC32_POLY := 0x04c11db7 - DEVICE_TITLE := o2 Box 6431 / Arcadyan VGV7510KW22 (BRN) - DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc - SUPPORTED_DEVICES += VGV7510KW22BRN -endef -TARGET_DEVICES += arcadyan_vgv7510kw22-brn - -define Device/arcadyan_vgv7519-nor - IMAGE_SIZE := 15360k - DEVICE_DTS := VGV7519NOR - DEVICE_TITLE := Experiabox 8 VGV7519 - DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc - SUPPORTED_DEVICES += VGV7519NOR -endef -TARGET_DEVICES += arcadyan_vgv7519-nor - -define Device/arcadyan_vgv7519-brn - $(Device/lantiqBrnImage) - IMAGE_SIZE := 7168k - DEVICE_DTS := VGV7519BRN - SIGNATURE := 5D00008000 - MAGIC := 0x12345678 - CRC32_POLY := 0x2083b8ed - DEVICE_TITLE := Experiabox 8 VGV7519 (BRN) - DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc - SUPPORTED_DEVICES += VGV7519BRN -endef -TARGET_DEVICES += arcadyan_vgv7519-brn - +include vr9.mk endif - ifeq ($(SUBTARGET),falcon) - -define Device/lantiq_easy98000-nor - IMAGE_SIZE := 3904k - DEVICE_DTS := EASY98000NOR - DEVICE_TITLE := EASY98000 - Lantiq Falcon Eval Board NOR - DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24 -endef -TARGET_DEVICES += lantiq_easy98000-nor - -define Device/lantiq_easy98000-nand - IMAGE_SIZE := 3904k - DEVICE_DTS := EASY98000NAND - DEVICE_TITLE := EASY98000 - Lantiq Falcon Eval Board NAND - DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24 -endef -TARGET_DEVICES += lantiq_easy98000-nand - -define Device/lantiq_easy98000-sflash - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY98000SFLASH - DEVICE_TITLE := EASY98000 - Lantiq Falcon Eval Board SFLASH - DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24 -endef -TARGET_DEVICES += lantiq_easy98000-sflash - -define Device/lantiq_falcon-mdu - IMAGE_SIZE := 7424k - DEVICE_DTS := FALCON-MDU - DEVICE_TITLE := MDU - Lantiq Falcon / VINAXdp MDU Board -endef -TARGET_DEVICES += lantiq_falcon-mdu - -define Device/lantiq_easy88388 - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY88388 - DEVICE_TITLE := EASY88388 - Lantiq Falcon FTTDP8 Reference Board -endef -TARGET_DEVICES += lantiq_easy88388 - -define Device/lantiq_easy88444 - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY88444 - DEVICE_TITLE := EASY88444 - Lantiq Falcon FTTdp G.FAST Reference Board -endef -TARGET_DEVICES += lantiq_easy88444 - -define Device/lantiq_falcon-sfp - IMAGE_SIZE := 7424k - DEVICE_DTS := FALCON-SFP - DEVICE_TITLE := SFP - Lantiq Falcon SFP Stick -endef -TARGET_DEVICES += lantiq_falcon-sfp - -define Device/lantiq_easy98035synce - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY98035SYNCE - DEVICE_TITLE := EASY98035SYNCE - Lantiq Falcon SFP Stick with Synchronous Ethernet -endef -TARGET_DEVICES += lantiq_easy98035synce - -define Device/lantiq_easy98035synce1588 - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY98035SYNCE1588 - DEVICE_TITLE := EASY98035SYNCE1588 - Lantiq Falcon SFP Stick with SyncE and IEEE1588 -endef -TARGET_DEVICES += lantiq_easy98035synce1588 - -define Device/lantiq_easy98020 - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY98020 - DEVICE_TITLE := EASY98020 - Lantiq Falcon SFU Reference Board -endef -TARGET_DEVICES += lantiq_easy98020 - -define Device/lantiq_easy98020-v18 - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY98020V18 - DEVICE_TITLE := EASY98020V18 - Lantiq Falcon SFU Reference Board V1.8 -endef -TARGET_DEVICES += lantiq_easy98020-v18 - -define Device/lantiq_easy98021 - IMAGE_SIZE := 7424k - DEVICE_DTS := EASY98021 - DEVICE_TITLE := EASY98021 - Lantiq Falcon HGU Reference Board -endef -TARGET_DEVICES += lantiq_easy98021 - +DEFAULT_SOC := falcon +include falcon.mk endif $(eval $(call BuildImage)) diff --git a/target/linux/lantiq/image/amazonse.mk b/target/linux/lantiq/image/amazonse.mk new file mode 100644 index 0000000000..4a23a68e40 --- /dev/null +++ b/target/linux/lantiq/image/amazonse.mk @@ -0,0 +1,20 @@ +define Device/allnet_all0333cj + DEVICE_VENDOR := Allnet + DEVICE_MODEL := ALL0333CJ + IMAGE_SIZE := 3700k + DEVICE_PACKAGES := kmod-ltq-adsl-ase kmod-ltq-adsl-ase-mei \ + kmod-ltq-adsl-ase-fw-b kmod-ltq-atm-ase \ + ltq-adsl-app ppp-mod-pppoe +endef +TARGET_DEVICES += allnet_all0333cj + +define Device/netgear_dgn1000b + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := DGN1000B + IMAGE_SIZE := 6000k + DEVICE_PACKAGES := kmod-ltq-adsl-ase kmod-ltq-adsl-ase-mei \ + kmod-ltq-adsl-ase-fw-b kmod-ltq-atm-ase \ + ltq-adsl-app ppp-mod-pppoe + SUPPORTED_DEVICES += DGN1000B +endef +TARGET_DEVICES += netgear_dgn1000b diff --git a/target/linux/lantiq/image/ar9.mk b/target/linux/lantiq/image/ar9.mk new file mode 100644 index 0000000000..7a8f05ea58 --- /dev/null +++ b/target/linux/lantiq/image/ar9.mk @@ -0,0 +1,165 @@ +define Device/avm_fritz7312 + $(Device/AVM) + DEVICE_MODEL := FRITZ!Box 7312 + SOC := ar9 + IMAGE_SIZE := 15744k + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-deu-ar9 -swconfig +endef +TARGET_DEVICES += avm_fritz7312 + +define Device/avm_fritz7320 + $(Device/AVM) + DEVICE_MODEL := FRITZ!Box 7320 + DEVICE_ALT0_VENDOR := 1&1 + DEVICE_ALT0_MODEL := HomeServer + SOC := ar9 + IMAGE_SIZE := 15744k + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-deu-ar9 kmod-usb-dwc2 -swconfig + SUPPORTED_DEVICES += FRITZ7320 +endef +TARGET_DEVICES += avm_fritz7320 + +define Device/bt_homehub-v3a + $(Device/NAND) + DEVICE_VENDOR := British Telecom + DEVICE_MODEL := Home Hub 3 + DEVICE_VARIANT := Type A + BOARD_NAME := BTHOMEHUBV3A + SOC := ar9 + DEVICE_PACKAGES := kmod-usb-dwc2 \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ + kmod-ltq-deu-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k kmod-owl-loader wpad-basic \ + uboot-envtools + SUPPORTED_DEVICES += BTHOMEHUBV3A +endef +TARGET_DEVICES += bt_homehub-v3a + +define Device/buffalo_wbmr-hp-g300h-a + DEVICE_VENDOR := Buffalo + DEVICE_MODEL := WBMR-HP-G300H + DEVICE_VARIANT := A + IMAGE_SIZE := 31488k + SOC := ar9 + DEVICE_DTS := ar9_buffalo_wbmr-hp-g300h + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k kmod-owl-loader wpad-basic + SUPPORTED_DEVICES := WBMR buffalo,wbmr-hp-g300h +endef +TARGET_DEVICES += buffalo_wbmr-hp-g300h-a + +define Device/buffalo_wbmr-hp-g300h-b + DEVICE_VENDOR := Buffalo + DEVICE_MODEL := WBMR-HP-G300H + DEVICE_VARIANT := B + IMAGE_SIZE := 31488k + SOC := ar9 + DEVICE_DTS := ar9_buffalo_wbmr-hp-g300h + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k kmod-owl-loader wpad-basic + SUPPORTED_DEVICES := WBMR buffalo,wbmr-hp-g300h +endef +TARGET_DEVICES += buffalo_wbmr-hp-g300h-b + +DGN3500_KERNEL_OFFSET_HEX=0x50000 +DGN3500_KERNEL_OFFSET_DEC=327680 +define Device/netgear_dgn3500 + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := DGN3500 + SOC := ar9 + IMAGE_SIZE := 16000k + IMAGES := \ + sysupgrade-na.bin sysupgrade.bin \ + factory-na.img factory.img + IMAGE/sysupgrade-na.bin := \ + append-kernel | append-rootfs | dgn3500-sercom-footer 0x0 "NA" | \ + pad-rootfs | append-metadata | check-size + IMAGE/sysupgrade.bin := \ + append-kernel | append-rootfs | dgn3500-sercom-footer 0x0 "WW" | \ + pad-rootfs | append-metadata | check-size + IMAGE/factory-na.img := \ + pad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \ + dgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) "NA" | pad-rootfs | \ + check-size 16320k | pad-to 16384k + IMAGE/factory.img := \ + pad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \ + dgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) "WW" | pad-rootfs | \ + check-size 16320k | pad-to 16384k + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ath9k kmod-owl-loader wpad-basic \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-deu-ar9 + SUPPORTED_DEVICES += DGN3500 +endef +TARGET_DEVICES += netgear_dgn3500 + +define Device/netgear_dgn3500b + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := DGN3500B + SOC := ar9 + IMAGE_SIZE := 16000k + IMAGES += factory.img + IMAGE/sysupgrade.bin := \ + append-kernel | append-rootfs | dgn3500-sercom-footer 0x0 "DE" | \ + pad-rootfs | append-metadata | check-size + IMAGE/factory.img := \ + pad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \ + dgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) "DE" | pad-rootfs | \ + check-size 16320k | pad-to 16384k + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ath9k kmod-owl-loader wpad-basic \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-deu-ar9 + SUPPORTED_DEVICES += DGN3500B +endef +TARGET_DEVICES += netgear_dgn3500b + +define Device/zte_h201l + DEVICE_VENDOR := ZTE + DEVICE_MODEL := H201L + IMAGE_SIZE := 7808k + SOC := ar9 + DEVICE_PACKAGES := kmod-ath9k-htc wpad-basic \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoe \ + kmod-ltq-deu-ar9 kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-tapi kmod-ltq-vmmc + SUPPORTED_DEVICES += H201L +endef +TARGET_DEVICES += zte_h201l + +define Device/zyxel_p-2601hn + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := P-2601HN + DEVICE_VARIANT := F1/F3 + IMAGE_SIZE := 15616k + SOC := ar9 + DEVICE_PACKAGES := kmod-rt2800-usb wpad-basic \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoe \ + kmod-ltq-deu-ar9 kmod-usb-dwc2 + SUPPORTED_DEVICES += P2601HNFX +endef +TARGET_DEVICES += zyxel_p-2601hn diff --git a/target/linux/lantiq/image/danube.mk b/target/linux/lantiq/image/danube.mk new file mode 100644 index 0000000000..2fb5ea061f --- /dev/null +++ b/target/linux/lantiq/image/danube.mk @@ -0,0 +1,219 @@ +define Device/arcadyan_arv4510pw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV4510PW + DEVICE_ALT0_VENDOR := Wippies + DEVICE_ALT0_MODEL := BeWan iBox v1.0 + IMAGE_SIZE := 15616k + SOC := danube + DEVICE_PACKAGES := kmod-usb-ledtrig-usbport kmod-usb2-pci kmod-usb-uhci \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci kmod-ath5k wpad-basic + SUPPORTED_DEVICES += ARV4510PW +endef +TARGET_DEVICES += arcadyan_arv4510pw + +define Device/arcadyan_arv4519pw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV4519PW + DEVICE_ALT0_VENDOR := Vodafone + DEVICE_ALT0_MODEL := NetFasteR IAD 2 + DEVICE_ALT1_VENDOR := Pirelli + DEVICE_ALT1_MODEL := P.RG A4201G + IMAGE_SIZE := 3776k + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa + SUPPORTED_DEVICES += ARV4519PW +endef +TARGET_DEVICES += arcadyan_arv4519pw + +define Device/arcadyan_arv7506pw11 + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV7506PW11 + DEVICE_ALT0_VENDOR := Alice/O2 + DEVICE_ALT0_MODEL := IAD 4421 + IMAGE_SIZE := 7808k + SOC := danube + DEVICE_PACKAGES := kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-rt2800-pci wpad-basic + SUPPORTED_DEVICES += ARV7506PW11 +endef +TARGET_DEVICES += arcadyan_arv7506pw11 + +define Device/arcadyan_arv7510pw22 + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV7510PW22 + DEVICE_ALT0_VENDOR := Astoria Networks + DEVICE_ALT0_MODEL := ARV7510PW22 + IMAGE_SIZE := 31232k + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci wpad-basic \ + kmod-usb-uhci kmod-usb2 kmod-usb2-pci + SUPPORTED_DEVICES += ARV7510PW22 +endef +TARGET_DEVICES += arcadyan_arv7510pw22 + +define Device/arcadyan_arv7518pw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV7518PW + DEVICE_ALT0_VENDOR := Astoria Networks + DEVICE_ALT0_MODEL := ARV7518PW + IMAGE_SIZE := 7872k + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k kmod-owl-loader wpad-basic + SUPPORTED_DEVICES += ARV7518PW +endef +TARGET_DEVICES += arcadyan_arv7518pw + +define Device/arcadyan_arv7519pw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV7519PW + DEVICE_ALT0_VENDOR := Astoria Networks + DEVICE_ALT0_MODEL := ARV7519PW + IMAGE_SIZE := 15488k + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-rt2800-pci wpad-basic + SUPPORTED_DEVICES += ARV7519PW +endef +TARGET_DEVICES += arcadyan_arv7519pw + +define Device/arcadyan_arv7525pw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV7525PW + DEVICE_ALT0_VENDOR := Telekom + DEVICE_ALT0_MODEL := Speedport W303V + DEVICE_ALT0_VARIANT := Typ A + IMAGE_SIZE := 3776k + SOC := danube + DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa -swconfig + SUPPORTED_DEVICES += ARV4510PW +endef +TARGET_DEVICES += arcadyan_arv7525pw + +define Device/arcadyan_arv752dpw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV752DPW + DEVICE_ALT0_VENDOR := Vodafone + DEVICE_ALT0_MODEL := Easybox 802 + IMAGE_SIZE := 7872k + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci wpad-basic + SUPPORTED_DEVICES += ARV752DPW +endef +TARGET_DEVICES += arcadyan_arv752dpw + +define Device/arcadyan_arv752dpw22 + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV752DPW22 + DEVICE_ALT0_VENDOR := Vodafone + DEVICE_ALT0_MODEL := Easybox 803 + IMAGE_SIZE := 7616k + SOC := danube + DEVICE_PACKAGES := kmod-usb2-pci kmod-usb-uhci kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci wpad-basic + SUPPORTED_DEVICES += ARV752DPW22 +endef +TARGET_DEVICES += arcadyan_arv752dpw22 + +define Device/arcadyan_arv8539pw22 + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV8539PW22 + DEVICE_ALT0_VENDOR := Telekom + DEVICE_ALT0_MODEL := Speedport W504V Typ A + IMAGE_SIZE := 7616k + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k kmod-owl-loader wpad-basic + SUPPORTED_DEVICES += ARV8539PW22 +endef +TARGET_DEVICES += arcadyan_arv8539pw22 + +define Device/audiocodes_mp-252 + DEVICE_VENDOR := AudioCodes + DEVICE_MODEL := MediaPack MP-252 + IMAGE_SIZE := 14848k + SOC := danube + DEVICE_PACKAGES := kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-usb-ledtrig-usbport kmod-usb-dwc2 \ + kmod-rt2800-pci \ + ltq-adsl-app ppp-mod-pppoa \ + wpad-basic + SUPPORTED_DEVICES += ACMP252 +endef +TARGET_DEVICES += audiocodes_mp-252 + +define Device/bt_homehub-v2b + $(Device/NAND) + DEVICE_VENDOR := British Telecom + DEVICE_MODEL := Home Hub 2 + DEVICE_VARIANT := Type B + BOARD_NAME := BTHOMEHUBV2B + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + kmod-ltq-deu-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k kmod-owl-loader wpad-basic + SUPPORTED_DEVICES += BTHOMEHUBV2B +endef +TARGET_DEVICES += bt_homehub-v2b + +define Device/lantiq_easy50712 + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Danube (EASY50712) + SOC := danube + IMAGE_SIZE := 3776k +endef +TARGET_DEVICES += lantiq_easy50712 + +define Device/siemens_gigaset-sx76x + DEVICE_VENDOR := Siemens + DEVICE_MODEL := Gigaset sx76x + IMAGE_SIZE := 7680k + SOC := danube + DEVICE_PACKAGES := kmod-usb-dwc2 \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoe \ + kmod-ath5k wpad-basic + SUPPORTED_DEVICES += GIGASX76X +endef +TARGET_DEVICES += siemens_gigaset-sx76x diff --git a/target/linux/lantiq/image/falcon.mk b/target/linux/lantiq/image/falcon.mk new file mode 100644 index 0000000000..a5490f6e68 --- /dev/null +++ b/target/linux/lantiq/image/falcon.mk @@ -0,0 +1,93 @@ +define Device/lantiq_easy88388 + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := EASY88388 Falcon FTTDP8 Reference Board + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_easy88388 + +define Device/lantiq_easy88444 + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := EASY88444 Falcon FTTdp G.FAST Reference Board + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_easy88444 + +define Device/lantiq_easy98020 + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Falcon SFU Reference Board (EASY98020) + DEVICE_VARIANT := v1.0-v1.7 + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_easy98020 + +define Device/lantiq_easy98020-v18 + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Falcon SFU Reference Board (EASY98020) + DEVICE_VARIANT := v1.8 + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_easy98020-v18 + +define Device/lantiq_easy98021 + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Falcon HGU Reference Board (EASY98021) + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_easy98021 + +define Device/lantiq_easy98035synce + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Falcon SFP Stick (EASY98035SYNCE) + DEVICE_VARIANT := with Synchronous Ethernet + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_easy98035synce + +define Device/lantiq_easy98035synce1588 + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Falcon SFP Stick (EASY98035SYNCE1588) + DEVICE_VARIANT := with SyncE and IEEE1588 + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_easy98035synce1588 + +define Device/lantiq_easy98000-nand + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := EASY98000 Falcon Eval Board + DEVICE_VARIANT := NAND + IMAGE_SIZE := 3904k + DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24 +endef +TARGET_DEVICES += lantiq_easy98000-nand + +define Device/lantiq_easy98000-nor + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := EASY98000 Falcon Eval Board + DEVICE_VARIANT := NOR + IMAGE_SIZE := 3904k + DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24 +endef +TARGET_DEVICES += lantiq_easy98000-nor + +define Device/lantiq_easy98000-sflash + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := EASY98000 Falcon Eval Board + DEVICE_VARIANT := SFLASH + IMAGE_SIZE := 7424k + DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24 +endef +TARGET_DEVICES += lantiq_easy98000-sflash + +define Device/lantiq_falcon-mdu + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Falcon / VINAXdp MDU Board + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_falcon-mdu + +define Device/lantiq_falcon-sfp + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := Falcon SFP Stick + IMAGE_SIZE := 7424k +endef +TARGET_DEVICES += lantiq_falcon-sfp diff --git a/target/linux/lantiq/image/tp-link.mk b/target/linux/lantiq/image/tp-link.mk index bec9eafbd1..2f9fa7b97f 100644 --- a/target/linux/lantiq/image/tp-link.mk +++ b/target/linux/lantiq/image/tp-link.mk @@ -1,6 +1,7 @@ DEVICE_VARS += TPLINK_FLASHLAYOUT TPLINK_HWID TPLINK_HWREV TPLINK_HWREVADD TPLINK_HVERSION define Device/lantiqTpLink + DEVICE_VENDOR := TP-Link TPLINK_HWREVADD := 0 TPLINK_HVERSION := 2 KERNEL := kernel-bin | append-dtb | lzma @@ -8,17 +9,17 @@ define Device/lantiqTpLink tplink-v2-header -s -V "ver. 1.0" IMAGES := sysupgrade.bin IMAGE/sysupgrade.bin := tplink-v2-image -s -V "ver. 1.0" | \ - append-metadata | check-size $$$$(IMAGE_SIZE) + append-metadata | check-size endef define Device/tplink_tdw8970 $(Device/lantiqTpLink) - DEVICE_DTS := TDW8970 + DEVICE_MODEL := TD-W8970 + DEVICE_VARIANT := v1 TPLINK_FLASHLAYOUT := 8Mltq TPLINK_HWID := 0x89700001 TPLINK_HWREV := 1 IMAGE_SIZE := 7680k - DEVICE_TITLE := TP-LINK TD-W8970 DEVICE_PACKAGES:= kmod-ath9k wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport SUPPORTED_DEVICES += TDW8970 endef @@ -26,12 +27,12 @@ TARGET_DEVICES += tplink_tdw8970 define Device/tplink_tdw8980 $(Device/lantiqTpLink) - DEVICE_DTS := TDW8980 + DEVICE_MODEL := TD-W8980 + DEVICE_VARIANT := v1 TPLINK_FLASHLAYOUT := 8Mltq TPLINK_HWID := 0x89800001 TPLINK_HWREV := 14 IMAGE_SIZE := 7680k - DEVICE_TITLE := TP-LINK TD-W8980 DEVICE_PACKAGES:= kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport SUPPORTED_DEVICES += TDW8980 endef @@ -39,26 +40,26 @@ TARGET_DEVICES += tplink_tdw8980 define Device/tplink_vr200 $(Device/lantiqTpLink) - DEVICE_DTS := VR200 + DEVICE_MODEL := Archer VR200 + DEVICE_VARIANT := v1 TPLINK_FLASHLAYOUT := 16Mltq TPLINK_HWID := 0x63e64801 TPLINK_HWREV := 0x53 IMAGE_SIZE := 15808k - DEVICE_TITLE := TP-LINK Archer VR200 - DEVICE_PACKAGES:= kmod-usb-dwc2 kmod-usb-ledtrig-usbport + DEVICE_PACKAGES:= kmod-mt76x0e wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport SUPPORTED_DEVICES += VR200 endef TARGET_DEVICES += tplink_vr200 define Device/tplink_vr200v $(Device/lantiqTpLink) - DEVICE_DTS := VR200v + DEVICE_MODEL := Archer VR200v + DEVICE_VARIANT := v1 TPLINK_FLASHLAYOUT := 16Mltq TPLINK_HWID := 0x73b70801 TPLINK_HWREV := 0x2f IMAGE_SIZE := 15808k - DEVICE_TITLE := TP-LINK Archer VR200v - DEVICE_PACKAGES:= kmod-usb-dwc2 kmod-usb-ledtrig-usbport kmod-ltq-tapi kmod-ltq-vmmc + DEVICE_PACKAGES:= kmod-mt76x0e wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport kmod-ltq-tapi kmod-ltq-vmmc SUPPORTED_DEVICES += VR200v endef TARGET_DEVICES += tplink_vr200v diff --git a/target/linux/lantiq/image/vr9.mk b/target/linux/lantiq/image/vr9.mk new file mode 100644 index 0000000000..167c57c7c4 --- /dev/null +++ b/target/linux/lantiq/image/vr9.mk @@ -0,0 +1,227 @@ +DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID + +define Device/alphanetworks_asl56026 + DEVICE_VENDOR := Alpha + DEVICE_MODEL := ASL56026 + DEVICE_ALT0_VENDOR := BT Openreach + DEVICE_ALT0_MODEL := ECI VDSL Modem V-2FUb/I + IMAGE_SIZE := 7488k +endef +TARGET_DEVICES += alphanetworks_asl56026 + +define Device/arcadyan_arv7519rw22 + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV7519RW22 + DEVICE_ALT0_VENDOR := Orange + DEVICE_ALT0_MODEL := Livebox + DEVICE_ALT0_VARIANT := 2.1 + DEVICE_ALT1_VENDOR := Astoria Networks + DEVICE_ALT1_MODEL := ARV7519RW22 + IMAGE_SIZE := 31232k + DEVICE_PACKAGES := kmod-usb-dwc2 + SUPPORTED_DEVICES += ARV7519RW22 +endef +TARGET_DEVICES += arcadyan_arv7519rw22 + +define Device/arcadyan_vg3503j + DEVICE_VENDOR := BT Openreach + DEVICE_MODEL := ECI VDSL Modem V-2FUb/R + IMAGE_SIZE := 8000k + SUPPORTED_DEVICES += VG3503J +endef +TARGET_DEVICES += arcadyan_vg3503j + +define Device/arcadyan_vgv7510kw22-brn + $(Device/lantiqBrnImage) + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := VGV7510KW22 + DEVICE_VARIANT := BRN + DEVICE_ALT0_VENDOR := o2 + DEVICE_ALT0_MODEL := Box 6431 + DEVICE_ALT0_VARIANT := BRN + IMAGE_SIZE := 7168k + SIGNATURE := BRNDA6431 + MAGIC := 0x12345678 + CRC32_POLY := 0x04c11db7 + DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc + SUPPORTED_DEVICES += VGV7510KW22BRN +endef +TARGET_DEVICES += arcadyan_vgv7510kw22-brn + +define Device/arcadyan_vgv7510kw22-nor + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := VGV7510KW22 + DEVICE_VARIANT := NOR + DEVICE_ALT0_VENDOR := o2 + DEVICE_ALT0_MODEL := Box 6431 + DEVICE_ALT0_VARIANT := NOR + IMAGE_SIZE := 15232k + DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc + SUPPORTED_DEVICES += VGV7510KW22NOR +endef +TARGET_DEVICES += arcadyan_vgv7510kw22-nor + +define Device/arcadyan_vgv7519-brn + $(Device/lantiqBrnImage) + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := VGV7519 + DEVICE_VARIANT := BRN + DEVICE_ALT0_VENDOR := KPN + DEVICE_ALT0_MODEL := Experiabox 8 + DEVICE_ALT0_VARIANT := BRN + IMAGE_SIZE := 7168k + SIGNATURE := 5D00008000 + MAGIC := 0x12345678 + CRC32_POLY := 0x2083b8ed + DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc + SUPPORTED_DEVICES += VGV7519BRN +endef +TARGET_DEVICES += arcadyan_vgv7519-brn + +define Device/arcadyan_vgv7519-nor + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := VGV7519 + DEVICE_VARIANT := NOR + DEVICE_ALT0_VENDOR := KPN + DEVICE_ALT0_MODEL := Experiabox 8 + DEVICE_ALT0_VARIANT := NOR + IMAGE_SIZE := 15360k + DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc + SUPPORTED_DEVICES += VGV7519NOR +endef +TARGET_DEVICES += arcadyan_vgv7519-nor + +define Device/avm_fritz3370 + $(Device/AVM) + $(Device/NAND) + DEVICE_MODEL := FRITZ!Box 3370 + DEVICE_VARIANT := Rev. 2 + KERNEL_SIZE := 4096k + UBINIZE_OPTS := -E 5 + IMAGES += eva-kernel.bin eva-filesystem.bin + IMAGE/eva-kernel.bin := append-kernel + IMAGE/eva-filesystem.bin := append-ubi + DEVICE_PACKAGES := kmod-ath9k wpad-basic kmod-usb-dwc2 fritz-tffs +endef + +define Device/avm_fritz3370-rev2-hynix + $(Device/avm_fritz3370) + DEVICE_MODEL := FRITZ!Box 3370 + DEVICE_VARIANT := Rev. 2 (Hynix NAND) +endef +TARGET_DEVICES += avm_fritz3370-rev2-hynix + +define Device/avm_fritz3370-rev2-micron + $(Device/avm_fritz3370) + DEVICE_MODEL := FRITZ!Box 3370 + DEVICE_VARIANT := Rev. 2 (Micron NAND) +endef +TARGET_DEVICES += avm_fritz3370-rev2-micron + +define Device/avm_fritz7360sl + $(Device/AVM) + DEVICE_MODEL := FRITZ!Box 7360 SL + IMAGE_SIZE := 15744k + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 + SUPPORTED_DEVICES += FRITZ7360SL +endef +TARGET_DEVICES += avm_fritz7360sl + +define Device/avm_fritz7362sl + $(Device/AVM) + $(Device/NAND) + DEVICE_MODEL := FRITZ!Box 7362 SL + KERNEL_SIZE := 4096k + IMAGE_SIZE := 49152k + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 fritz-tffs +endef +TARGET_DEVICES += avm_fritz7362sl + +define Device/avm_fritz7412 + $(Device/AVM) + $(Device/NAND) + DEVICE_MODEL := FRITZ!Box 7412 + BOARD_NAME := FRITZ7412 + KERNEL_SIZE := 4096k + IMAGE_SIZE := 49152k + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic fritz-tffs-nand fritz-caldata +endef +TARGET_DEVICES += avm_fritz7412 + +define Device/bt_homehub-v5a + $(Device/NAND) + DEVICE_VENDOR := British Telecom + DEVICE_MODEL := Home Hub 5 + DEVICE_VARIANT := Type A + BOARD_NAME := BTHOMEHUBV5A + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader \ + kmod-ath10k-ct ath10k-firmware-qca988x-ct wpad-basic kmod-usb-dwc2 + SUPPORTED_DEVICES += BTHOMEHUBV5A +endef +TARGET_DEVICES += bt_homehub-v5a + +define Device/buffalo_wbmr-300hpd + DEVICE_VENDOR := Buffalo + DEVICE_MODEL := WBMR-300HPD + IMAGE_SIZE := 15616k + DEVICE_PACKAGES := kmod-mt7603 wpad-basic kmod-usb-dwc2 + SUPPORTED_DEVICES += WBMR300 +endef +TARGET_DEVICES += buffalo_wbmr-300hpd + +define Device/lantiq_easy80920-nand + $(Device/lantiqFullImage) + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := VR9 EASY80920 + DEVICE_VARIANT := NAND + IMAGE_SIZE := 64512k + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport +endef +TARGET_DEVICES += lantiq_easy80920-nand + +define Device/lantiq_easy80920-nor + DEVICE_VENDOR := Lantiq + DEVICE_MODEL := VR9 EASY80920 + DEVICE_VARIANT := NOR + IMAGE_SIZE := 7936k + DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport +endef +TARGET_DEVICES += lantiq_easy80920-nor + +define Device/netgear_dm200 + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := DM200 + IMAGES := sysupgrade.bin factory.img + IMAGE/sysupgrade.bin := append-kernel | \ + pad-offset 64k 64 | append-uImage-fakehdr filesystem | \ + pad-offset 64k 64 | append-uImage-fakehdr filesystem | \ + append-rootfs | pad-rootfs | append-metadata | check-size + IMAGE/factory.img := $$(IMAGE/sysupgrade.bin) | netgear-dni + IMAGE_SIZE := 7872k + NETGEAR_BOARD_ID := DM200 + NETGEAR_HW_ID := 29765233+8+0+64+0+0 +endef +TARGET_DEVICES += netgear_dm200 + +define Device/zyxel_p-2812hnu-f1 + $(Device/NAND) + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := P-2812HNU + DEVICE_VARIANT := F1 + BOARD_NAME := P2812HNUF1 + DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 kmod-usb-ledtrig-usbport + KERNEL_SIZE := 3072k + SUPPORTED_DEVICES += P2812HNUF1 +endef +TARGET_DEVICES += zyxel_p-2812hnu-f1 + +define Device/zyxel_p-2812hnu-f3 + $(Device/NAND) + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := P-2812HNU + DEVICE_VARIANT := F3 + BOARD_NAME := P2812HNUF3 + DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic kmod-usb-dwc2 + SUPPORTED_DEVICES += P2812HNUF3 +endef +TARGET_DEVICES += zyxel_p-2812hnu-f3 diff --git a/target/linux/lantiq/image/xway_legacy.mk b/target/linux/lantiq/image/xway_legacy.mk new file mode 100644 index 0000000000..52a29ab2f0 --- /dev/null +++ b/target/linux/lantiq/image/xway_legacy.mk @@ -0,0 +1,72 @@ +define Device/arcadyan_arv4518pwr01 + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV4518PWR01 + IMAGE_SIZE := 3776k + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath5k wpad-mini + SUPPORTED_DEVICES += ARV4518PWR01 +endef +TARGET_DEVICES += arcadyan_arv4518pwr01 + +define Device/arcadyan_arv4518pwr01a + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV4518PWR01A + IMAGE_SIZE := 3776k + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath5k wpad-basic + SUPPORTED_DEVICES += ARV4518PWR01A +endef +TARGET_DEVICES += arcadyan_arv4518pwr01a + +define Device/arcadyan_arv4520pw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV4520PW + DEVICE_ALT0_VENDOR := Vodafone + DEVICE_ALT0_MODEL := Easybox 800 + DEVICE_ALT1_VENDOR := Airties + DEVICE_ALT1_MODEL := WAV-281 + IMAGE_SIZE := 3648k + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-rt61-pci wpad-mini + SUPPORTED_DEVICES += ARV4520PW +endef +TARGET_DEVICES += arcadyan_arv4520pw + +define Device/arcadyan_arv4525pw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV4525PW + DEVICE_ALT0_VENDOR := Telekom + DEVICE_ALT0_MODEL := Speedport W502V + DEVICE_ALT0_VARIANT := Typ A + IMAGE_SIZE := 3776k + DEVICE_PACKAGES := kmod-ath5k wpad-mini \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa -swconfig + SUPPORTED_DEVICES += ARV4525PW +endef +TARGET_DEVICES += arcadyan_arv4525pw + +define Device/arcadyan_arv452cqw + DEVICE_VENDOR := Arcadyan + DEVICE_MODEL := ARV452CQW + DEVICE_ALT0_VENDOR := Vodafone + DEVICE_ALT0_MODEL := Easybox 801 + IMAGE_SIZE := 3776k + DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \ + kmod-ath5k wpad-mini \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa + SUPPORTED_DEVICES += ARV452CQW +endef +TARGET_DEVICES += arcadyan_arv452cqw diff --git a/target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch index 60a6dbafdd..e5ba24c3e7 100644 --- a/target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch +++ b/target/linux/lantiq/patches-4.19/0023-NET-PHY-add-led-support-for-intel-xway.patch @@ -42,10 +42,10 @@ Signed-off-by: John Crispin + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp); + + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp); + + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp); ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp); + + if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); diff --git a/target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch b/target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch index b2de5ac510..4e5b55eb3e 100644 --- a/target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch +++ b/target/linux/lantiq/patches-4.19/0025-NET-MIPS-lantiq-adds-xrx200-net.patch @@ -209,7 +209,7 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net +}; --- /dev/null +++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -0,0 +1,1889 @@ +@@ -0,0 +1,1924 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published @@ -433,6 +433,7 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net +struct xrx200_hw { + struct clk *clk; + struct mii_bus *mii_bus; ++ u8 phy_addr[XRX200_MAX_PORT]; + + struct xrx200_chan chan[XRX200_MAX_DMA]; + u16 vlan_vid[XRX200_MAX_VLAN]; @@ -947,6 +948,34 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net + return 0; +} + ++static int xrx200sw_set_port_link(struct switch_dev *dev, int port, ++ struct switch_port_link *link) ++{ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ return switch_generic_set_link(dev, port, link); ++} ++ ++static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val); ++static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg); ++ ++static int xrx200sw_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ ++ *value = xrx200_mdio_rd(hw->mii_bus, hw->phy_addr[addr], reg); ++ ++ return 0; ++} ++ ++static int xrx200sw_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ ++ return xrx200_mdio_wr(hw->mii_bus, hw->phy_addr[addr], reg, value); ++} ++ +static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + if (val->port_vlan >= XRX200_MAX_PORT) @@ -1043,7 +1072,10 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net + .get_port_pvid = xrx200sw_get_port_pvid, + .reset_switch = xrx200sw_reset_switch, + .get_port_link = xrx200sw_get_port_link, ++ .set_port_link = xrx200sw_set_port_link, +// .get_port_stats = xrx200sw_get_port_stats, //TODO ++ .phy_read16 = xrx200sw_phy_read16, ++ .phy_write16 = xrx200sw_phy_write16, +}; + +static int xrx200sw_init(struct xrx200_hw *hw) @@ -1897,6 +1929,9 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net + + /* store the port id in the hw struct so we can map ports -> devices */ + priv->hw->port_map[p->num] = priv->hw->num_devs; ++ ++ /* store the phy addr in the hw struct so we can map ports -> phys */ ++ priv->hw->phy_addr[p->num] = p->phy_addr; +} + +static const struct net_device_ops xrx200_netdev_ops = { diff --git a/target/linux/lantiq/patches-5.4/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.4/0001-MIPS-lantiq-add-pcie-driver.patch new file mode 100644 index 0000000000..bcd928aea9 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0001-MIPS-lantiq-add-pcie-driver.patch @@ -0,0 +1,5518 @@ +From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:12:28 +0200 +Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Kconfig | 10 + + arch/mips/lantiq/xway/sysctrl.c | 2 + + arch/mips/pci/Makefile | 2 + + arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ + arch/mips/pci/fixup-lantiq.c | 5 +- + arch/mips/pci/ifxmips_pci_common.h | 57 ++ + arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie.h | 135 ++++ + arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ + arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ + arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ + arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ + arch/mips/pci/ifxmips_pcie_pm.h | 36 + + arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ + arch/mips/pci/pci.c | 25 + + arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ + drivers/pci/pcie/aer/Kconfig | 2 +- + include/linux/pci.h | 2 + + include/linux/pci_ids.h | 6 + + 20 files changed, 5374 insertions(+), 2 deletions(-) + create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c + create mode 100644 arch/mips/pci/ifxmips_pci_common.h + create mode 100644 arch/mips/pci/ifxmips_pcie.c + create mode 100644 arch/mips/pci/ifxmips_pcie.h + create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h + create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c + create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h + create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h + create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h + create mode 100644 arch/mips/pci/pcie-lantiq.h + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -20,6 +20,7 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HAVE_PCI ++ select ARCH_SUPPORTS_MSI + select MFD_SYSCON + select MFD_CORE + +@@ -52,4 +53,13 @@ config PCI_LANTIQ + bool "PCI Support" + depends on SOC_XWAY && PCI + ++config PCIE_LANTIQ ++ bool "PCIE Support" ++ depends on SOC_XWAY && PCI ++ ++config PCIE_LANTIQ_MSI ++ bool ++ depends on PCIE_LANTIQ && PCI_MSI ++ default y ++ + endif +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -51,6 +51,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o + obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o +--- /dev/null ++++ b/arch/mips/pci/fixup-lantiq-pcie.c +@@ -0,0 +1,74 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_fixup_pcie.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_fixup_pcie.c ++ \ingroup IFX_PCIE ++ \brief PCIe Fixup functions source file ++*/ ++#include ++#include ++#include ++ ++#include ++ ++#include "pcie-lantiq.h" ++ ++static void ++ifx_pcie_fixup_resource(struct pci_dev *dev) ++{ ++ u32 reg; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ printk("%s: fixup host controller %s (%04x:%04x)\n", ++ __func__, pci_name(dev), dev->vendor, dev->device); ++ ++ /* Setup COMMAND register */ ++ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | ++ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; ++ pci_write_config_word(dev, PCI_COMMAND, reg); ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); ++ ++static void ++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ if (dev->devfn == PCI_DEVFN(0, 0) && ++ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { ++ ++ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); ++ ++ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); ++ } ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++ mdelay(10); ++} ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ++ ifx_pcie_rc_class_early_fixup); ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, ++ ifx_pcie_rc_class_early_fixup); +--- a/arch/mips/pci/fixup-lantiq.c ++++ b/arch/mips/pci/fixup-lantiq.c +@@ -6,12 +6,18 @@ + + #include + #include ++#include "ifxmips_pci_common.h" + + int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; + int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; + + int pcibios_plat_dev_init(struct pci_dev *dev) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ ifx_pcie_bios_plat_dev_init(dev); ++#endif ++ + if (ltq_pci_plat_arch_init) + return ltq_pci_plat_arch_init(dev); + +@@ -23,5 +29,10 @@ int pcibios_plat_dev_init(struct pci_dev + + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ return ifx_pcie_bios_map_irq(dev, slot, pin); ++#endif ++ + return of_irq_parse_and_map_pci(dev, slot, pin); + } +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pci_common.h +@@ -0,0 +1,57 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pci_common.h ++** PROJECT : IFX UEIP ++** MODULES : PCI subsystem ++** ++** DATE : 30 June 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 30 June,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++ ++#ifndef IFXMIPS_PCI_COMMON_H ++#define IFXMIPS_PCI_COMMON_H ++#include ++/*! ++ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration ++ \brief PCI/PCIe common parts ++*/ ++ ++/*! ++ \defgroup IFX_PCI_COM_OS OS APIs ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver OS interface functions ++*/ ++/*! ++ \file ifxmips_pci_common.h ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver common OS header file ++*/ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++#define IFX_PCI_CONST ++#else ++#define IFX_PCI_CONST const ++#endif ++#ifdef CONFIG_IFX_PCI ++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); ++#endif /* COFNIG_IFX_PCI */ ++ ++#ifdef CONFIG_PCIE_LANTIQ ++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); ++#endif ++ ++#endif /* IFXMIPS_PCI_COMMON_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -0,0 +1,1092 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2009 Lei Chuanhua ++ * Copyright (C) 2013 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie.h" ++#include "ifxmips_pcie_reg.h" ++ ++/* Enable 32bit io due to its mem mapped io nature */ ++#define IFX_PCIE_ERROR_INT ++#define IFX_PCIE_IO_32BIT ++ ++#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) ++#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) ++#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) ++#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) ++#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) ++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) ++#define SM(_v, _f) (((_v) << _f##_S) & (_f)) ++#define IFX_REG_SET_BIT(_f, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) ++ ++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 ++ ++static DEFINE_SPINLOCK(ifx_pcie_lock); ++ ++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++ ++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .ir_irq = { ++ .irq = IFX_PCIE_IR, ++ .name = "ifx_pcie_rc0", ++ }, ++ ++ .legacy_irq = { ++ { ++ .irq_bit = PCIE_IRN_INTA, ++ .irq = IFX_PCIE_INTA, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTB, ++ .irq = IFX_PCIE_INTB, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTC, ++ .irq = IFX_PCIE_INTC, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTD, ++ .irq = IFX_PCIE_INTD, ++ }, ++ }, ++ }, ++ ++}; ++ ++void ifx_pcie_debug(const char *fmt, ...) ++{ ++ static char buf[256] = {0}; /* XXX */ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ vsnprintf(buf, sizeof(buf), fmt, ap); ++ va_end(ap); ++ ++ printk("%s", buf); ++} ++ ++ ++static inline int pcie_ltssm_enable(int pcie_port) ++{ ++ int i; ++ ++ /* Enable LTSSM */ ++ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); ++ ++ /* Wait for the link to come up */ ++ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) ++ return 0; ++ udelay(10); ++ } ++ ++ printk("%s link timeout!!!!!\n", __func__); ++ return -1; ++} ++ ++static inline void pcie_status_register_clear(int pcie_port) ++{ ++ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); ++ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_UESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_RESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); ++ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_QSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); ++} ++ ++static inline int ifx_pcie_link_up(int pcie_port) ++{ ++ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; ++} ++ ++ ++static inline void pcie_mem_io_setup(int pcie_port) ++{ ++ u32 reg; ++ /* ++ * BAR[0:1] readonly register ++ * RC contains only minimal BARs for packets mapped to this device ++ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that ++ * reside on the downstream side fo the bridge. ++ */ ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); ++ ++ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); ++ ++ ++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) ++ | PCIE_PMBL_64BIT_ADDR; ++ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); ++ ++ /* Must configure upper 32bit */ ++ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); ++ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); ++#else ++ /* PCIe_PBML, same as MBML */ ++ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); ++#endif ++ ++ /* IO Address Range */ ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); ++#ifdef IFX_PCIE_IO_32BIT ++ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; ++#endif /* IFX_PCIE_IO_32BIT */ ++ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); ++ ++#ifdef IFX_PCIE_IO_32BIT ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); ++ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); ++ ++#endif /* IFX_PCIE_IO_32BIT */ ++} ++ ++static inline void ++pcie_device_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Device capability register, set up Maximum payload size */ ++ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); ++ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); ++ ++ /* Only available for EP */ ++ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); ++ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); ++ ++ /* Device control and status register */ ++ /* Set Maximum Read Request size for the device as a Requestor */ ++ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); ++ ++ /* ++ * Request size can be larger than the MPS used, but the completions returned ++ * for the read will be bounded by the MPS size. ++ * In our system, Max request size depends on AHB burst size. It is 64 bytes. ++ * but we set it as 128 as minimum one. ++ */ ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) ++ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); ++ ++ /* Enable relaxed ordering, no snoop, and all kinds of errors */ ++ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; ++ ++ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); ++} ++ ++static inline void ++pcie_link_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM ++ * L0s is reported during link training via TS1 order set by N_FTS ++ */ ++ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); ++ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; ++ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); ++ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); ++ ++ /* Link control and status register */ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ /* Link Enable, ASPM enabled */ ++ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; ++ ++#ifdef CONFIG_PCIEASPM ++ /* ++ * We use the same physical reference clock that the platform provides on the connector ++ * It paved the way for ASPM to calculate the new exit Latency ++ */ ++ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; ++ reg |= PCIE_LCTLSTS_COM_CLK_CFG; ++ /* ++ * We should disable ASPM by default except that we have dedicated power management support ++ * Enable ASPM will cause the system hangup/instability, performance degration ++ */ ++ reg |= PCIE_LCTLSTS_ASPM_ENABLE; ++#else ++ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; ++#endif /* CONFIG_PCIEASPM */ ++ ++ /* ++ * The maximum size of any completion with data packet is bounded by the MPS setting ++ * in device control register ++ */ ++ ++ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ ++ reg &= ~ PCIE_LCTLSTS_RCB128; ++ ++ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); ++} ++ ++static inline void pcie_error_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone ++ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE ++ */ ++ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); ++ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; ++ ++ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); ++ ++ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ ++ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); ++ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); ++ ++ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ ++ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); ++ ++ /* Correctable Error Mask Register, unmask all bits */ ++ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); ++ reg &= ~PCIE_CORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); ++ ++ /* Advanced Error Capabilities and Control Registr */ ++ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); ++ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; ++ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); ++ ++ /* Root Error Command Register, Report all types of errors */ ++ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); ++ reg |= PCIE_RECR_ERR_REPORT_EN; ++ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); ++ ++ /* Clear the Root status register */ ++ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); ++ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); ++} ++ ++static inline void pcie_port_logic_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ ++ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); ++ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); ++ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) ++ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); ++ /* L0s and L1 entry latency */ ++ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); ++ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) ++ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); ++ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); ++ ++ ++ /* Port Link Control Register */ ++ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); ++ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ ++ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); ++ ++ /* Lane Skew Register */ ++ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); ++ /* Enable ACK/NACK and FC */ ++ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); ++ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); ++ ++ /* Symbol Timer Register and Filter Mask Register 1 */ ++ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); ++ ++ /* Default SKP interval is very accurate already, 5us */ ++ /* Enable IO/CFG transaction */ ++ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; ++ /* Disable FC WDT */ ++ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; ++ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); ++ ++ /* Filter Masker Register 2 */ ++ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); ++ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; ++ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); ++ ++ /* VC0 Completion Receive Queue Control Register */ ++ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); ++ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; ++ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); ++ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); ++} ++ ++static inline void pcie_rc_cfg_reg_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Disable LTSSM */ ++ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ ++ ++ pcie_mem_io_setup(pcie_port); ++ ++ /* XXX, MSI stuff should only apply to EP */ ++ /* MSI Capability: Only enable 32-bit addresses */ ++ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); ++ reg &= ~PCIE_MCAPR_ADDR64_CAP; ++ ++ reg |= PCIE_MCAPR_MSI_ENABLE; ++ ++ /* Disable multiple message */ ++ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); ++ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); ++ ++ ++ /* Enable PME, Soft reset enabled */ ++ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); ++ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; ++ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); ++ ++ /* setup the bus */ ++ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); ++ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); ++ ++ ++ pcie_device_setup(pcie_port); ++ pcie_link_setup(pcie_port); ++ pcie_error_setup(pcie_port); ++ ++ /* Root control and capabilities register */ ++ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); ++ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; ++ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); ++ ++ /* Port VC Capability Register 2 */ ++ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); ++ reg &= ~PCIE_PVC2_VC_ARB_WRR; ++ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; ++ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); ++ ++ /* VC0 Resource Capability Register */ ++ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); ++ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; ++ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); ++ ++ pcie_port_logic_setup(pcie_port); ++} ++ ++static int ifx_pcie_wait_phy_link_up(int pcie_port) ++{ ++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ ++ int i; ++ ++ /* Wait for PHY link is up */ ++ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { ++ if (ifx_pcie_link_up(pcie_port)) { ++ break; ++ } ++ udelay(100); ++ } ++ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -1; ++ } ++ ++ /* Check data link up or not */ ++ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { ++ printk(KERN_ERR "%s DLL link is still down\n", __func__); ++ return -1; ++ } ++ ++ /* Check Data link active or not */ ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { ++ printk(KERN_ERR "%s DLL is not active\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static inline int pcie_app_loigc_setup(int pcie_port) ++{ ++ /* supress ahb bus errrors */ ++ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); ++ ++ /* Pull PCIe EP out of reset */ ++ pcie_device_rst_deassert(pcie_port); ++ ++ /* Start LTSSM training between RC and EP */ ++ pcie_ltssm_enable(pcie_port); ++ ++ /* Check PHY status after enabling LTSSM */ ++ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++/* ++ * The numbers below are directly from the PCIe spec table 3-4/5. ++ */ ++static inline void pcie_replay_time_update(int pcie_port) ++{ ++ u32 reg; ++ int nlw; ++ int rtl; ++ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); ++ switch (nlw) { ++ case PCIE_MAX_LENGTH_WIDTH_X1: ++ rtl = 1677; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X2: ++ rtl = 867; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X4: ++ rtl = 462; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X8: ++ rtl = 258; ++ break; ++ default: ++ rtl = 1677; ++ break; ++ } ++ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); ++ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; ++ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); ++ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); ++} ++ ++/* ++ * Table 359 Enhanced Configuration Address Mapping1) ++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 ++ * Memory Address PCI Express Configuration Space ++ * A[(20+n-1):20] Bus Number 1 < n < 8 ++ * A[19:15] Device Number ++ * A[14:12] Function Number ++ * A[11:8] Extended Register Number ++ * A[7:2] Register Number ++ * A[1:0] Along with size of the access, used to generate Byte Enables ++ * For VR9, only the address bits [22:0] are mapped to the configuration space: ++ * . Address bits [22:20] select the target bus (1-of-8)1) ++ * . Address bits [19:15] select the target device (1-of-32) on the bus ++ * . Address bits [14:12] select the target function (1-of-8) within the device. ++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space ++ * . Address bits [1:0] define the start byte location within the selected dword. ++ */ ++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) ++{ ++ u32 addr; ++ u8 bus; ++ ++ if (!bus_num) { ++ /* type 0 */ ++ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); ++ } else { ++ bus = bus_num; ++ /* type 1, only support 8 buses */ ++ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | ++ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); ++ } ++ return addr; ++} ++ ++static int pcie_valid_config(int pcie_port, int bus, int dev) ++{ ++ /* RC itself */ ++ if ((bus == 0) && (dev == 0)) { ++ return 1; ++ } ++ ++ /* No physical link */ ++ if (!ifx_pcie_link_up(pcie_port)) { ++ return 0; ++ } ++ ++ /* Bus zero only has RC itself ++ * XXX, check if EP will be integrated ++ */ ++ if ((bus == 0) && (dev != 0)) { ++ return 0; ++ } ++ ++ /* Maximum 8 buses supported for VRX */ ++ if (bus > 9) { ++ return 0; ++ } ++ ++ /* ++ * PCIe is PtP link, one bus only supports only one device ++ * except bus zero and PCIe switch which is virtual bus device ++ * The following two conditions really depends on the system design ++ * and attached the device. ++ * XXX, how about more new switch ++ */ ++ if ((bus == 1) && (dev != 0)) { ++ return 0; ++ } ++ ++ if ((bus >= 3) && (dev != 0)) { ++ return 0; ++ } ++ return 1; ++} ++ ++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ primary += pcibios_1st_host_bus_nr(); ++ secondary += pcibios_1st_host_bus_nr(); ++ subordinate += pcibios_1st_host_bus_nr(); ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ return tvalue; ++} ++ ++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ if (primary > 0 && primary != 0xFF) { ++ primary -= pcibios_1st_host_bus_nr(); ++ } ++ ++ if (secondary > 0 && secondary != 0xFF) { ++ secondary -= pcibios_1st_host_bus_nr(); ++ } ++ if (subordinate > 0 && subordinate != 0xFF) { ++ subordinate -= pcibios_1st_host_bus_nr(); ++ } ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ else if (where == PCI_SUBORDINATE_BUS) { ++ u8 subordinate = tvalue & 0xFF; ++ ++ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; ++ tvalue = subordinate; ++ } ++ return tvalue; ++} ++ ++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 *value) ++{ ++ u32 data = 0; ++ int bus_number = bus->number; ++ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ if (unlikely(size != 1 && size != 2 && size != 4)){ ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ /* ++ * PCIe only has a single device connected to it. It is ++ * always device ID 0. Don't bother doing reads for other ++ * device IDs on the first segment. ++ */ ++ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { ++ ret = PCIBIOS_FUNC_NOT_SUPPORTED; ++ goto out; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ *value = 0xffffffff; ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ } ++ /* To get a correct PCI topology, we have to restore the bus number to OS */ ++ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); ++ ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++ ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++out: ++ return ret; ++} ++ ++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) ++{ ++ u32 shift; ++ u32 tdata = data; ++ ++ switch (size) { ++ case 1: ++ shift = (where & 0x3) << 3; ++ tdata &= ~(0xffU << shift); ++ tdata |= ((value & 0xffU) << shift); ++ break; ++ case 2: ++ shift = (where & 3) << 3; ++ tdata &= ~(0xffffU << shift); ++ tdata |= ((value & 0xffffU) << shift); ++ break; ++ case 4: ++ tdata = value; ++ break; ++ } ++ return tdata; ++} ++ ++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 value) ++{ ++ int bus_number = bus->number; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ u32 tvalue = value; ++ u32 data; ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ /* XXX, some PCIe device may need some delay */ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ ++ /* ++ * To configure the correct bus topology using native way, we have to cheat Os so that ++ * it can configure the PCIe hardware correctly. ++ */ ++ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); ++ ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++ ++ ifx_pcie_rc_cfg_wr(pcie_port, t, data); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++#endif ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = cpu_to_le32(data); ++#endif ++ ifx_pcie_cfg_wr(pcie_port, addr, data); ++ } ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++out: ++ return ret; ++} ++ ++static struct resource ifx_pcie_io_resource = { ++ .name = "PCIe0 I/O space", ++ .start = PCIE_IO_PHY_BASE, ++ .end = PCIE_IO_PHY_END, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ifx_pcie_mem_resource = { ++ .name = "PCIe0 Memory space", ++ .start = PCIE_MEM_PHY_BASE, ++ .end = PCIE_MEM_PHY_END, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_ops ifx_pcie_ops = { ++ .read = ifx_pcie_read_config, ++ .write = ifx_pcie_write_config, ++}; ++ ++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { ++ { ++ .pcic = { ++ .pci_ops = &ifx_pcie_ops, ++ .mem_resource = &ifx_pcie_mem_resource, ++ .io_resource = &ifx_pcie_io_resource, ++ }, ++ .port = IFX_PCIE_PORT0, ++ }, ++}; ++ ++#ifdef IFX_PCIE_ERROR_INT ++ ++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) ++{ ++ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; ++ int pcie_port = ctrl->port; ++ u32 reg; ++ ++ pr_debug("PCIe RC error intr %d\n", irq); ++ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); ++ reg &= PCIE_RC_CORE_COMBINED_INT; ++ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++pcie_rc_core_int_init(int pcie_port) ++{ ++ int ret; ++ ++ /* Enable core interrupt */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); ++ ++ /* Clear it first */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); ++ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, ++ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); ++ if (ret) ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ ++ return ret; ++} ++#endif ++ ++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ u32 irq_bit = 0; ++ int irq = 0; ++ struct ifx_pci_controller *ctrl = dev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); ++ ++ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { ++ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); ++ return -1; ++ } ++ ++ /* Pin index so minus one */ ++ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; ++ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); ++ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); ++ return irq; ++} ++ ++int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) ++{ ++ u16 config; ++#ifdef IFX_PCIE_ERROR_INT ++ u32 dconfig; ++ int pos; ++#endif ++ ++ /* Enable reporting System errors and parity errors on all devices */ ++ /* Enable parity checking and error reporting */ ++ pci_read_config_word(dev, PCI_COMMAND, &config); ++ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_FAST_BACK*/; ++ pci_write_config_word(dev, PCI_COMMAND, config); ++ ++ if (dev->subordinate) { ++ /* Set latency timers on sub bridges */ ++ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ ++ /* More bridge error detection */ ++ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); ++ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; ++ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); ++ } ++#ifdef IFX_PCIE_ERROR_INT ++ /* Enable the PCIe normal error reporting */ ++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); ++ if (pos) { ++ ++ /* Disable system error generation in response to error messages */ ++ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); ++ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); ++ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); ++ ++ /* Clear PCIE Capability's Device Status */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); ++ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); ++ ++ /* Update Device Control */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); ++ /* Correctable Error Reporting */ ++ config |= PCI_EXP_DEVCTL_CERE; ++ /* Non-Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_NFERE; ++ /* Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_FERE; ++ /* Unsupported Request */ ++ config |= PCI_EXP_DEVCTL_URRE; ++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); ++ } ++ ++ /* Find the Advanced Error Reporting capability */ ++ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); ++ if (pos) { ++ /* Clear Uncorrectable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); ++ /* Enable reporting of all uncorrectable errors */ ++ /* Uncorrectable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); ++ /* ++ * Leave severity at HW default. This only controls if ++ * errors are reported as uncorrectable or ++ * correctable, not if the error is reported. ++ */ ++ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ ++ /* Clear Correctable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); ++ /* Enable reporting of all correctable errors */ ++ /* Correctable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); ++ /* Advanced Error Capabilities */ ++ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); ++ /* ECRC Generation Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { ++ dconfig |= PCI_ERR_CAP_ECRC_GENE; ++ } ++ /* ECRC Check Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { ++ dconfig |= PCI_ERR_CAP_ECRC_CHKE; ++ } ++ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); ++ ++ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ ++ /* Enable Root Port's interrupt in response to error messages */ ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ++ PCI_ERR_ROOT_CMD_COR_EN | ++ PCI_ERR_ROOT_CMD_NONFATAL_EN | ++ PCI_ERR_ROOT_CMD_FATAL_EN); ++ /* Clear the Root status register */ ++ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); ++ } ++#endif /* IFX_PCIE_ERROR_INT */ ++ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ ++ pcie_set_readrq(dev, 128); ++ return 0; ++} ++ ++static int ++pcie_rc_initialize(int pcie_port) ++{ ++ int i; ++#define IFX_PCIE_PHY_LOOP_CNT 5 ++ ++ pcie_rcu_endian_setup(pcie_port); ++ ++ pcie_ep_gpio_rst_init(pcie_port); ++ ++ /* ++ * XXX, PCIe elastic buffer bug will cause not to be detected. One more ++ * reset PCIe PHY will solve this issue ++ */ ++ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { ++ /* Disable PCIe PHY Analog part for sanity check */ ++ pcie_phy_pmu_disable(pcie_port); ++ ++ pcie_phy_rst_assert(pcie_port); ++ pcie_phy_rst_deassert(pcie_port); ++ ++ /* Make sure PHY PLL is stable */ ++ udelay(20); ++ ++ /* PCIe Core reset enabled, low active, sw programmed */ ++ pcie_core_rst_assert(pcie_port); ++ ++ /* Put PCIe EP in reset status */ ++ pcie_device_rst_assert(pcie_port); ++ ++ /* PCI PHY & Core reset disabled, high active, sw programmed */ ++ pcie_core_rst_deassert(pcie_port); ++ ++ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ ++ pcie_phy_clock_mode_setup(pcie_port); ++ ++ /* Enable PCIe PHY and Clock */ ++ pcie_core_pmu_setup(pcie_port); ++ ++ /* Clear status registers */ ++ pcie_status_register_clear(pcie_port); ++ ++#ifdef CONFIG_PCI_MSI ++ pcie_msi_init(pcie_port); ++#endif /* CONFIG_PCI_MSI */ ++ pcie_rc_cfg_reg_setup(pcie_port); ++ ++ /* Once link is up, break out */ ++ if (pcie_app_loigc_setup(pcie_port) == 0) ++ break; ++ } ++ if (i >= IFX_PCIE_PHY_LOOP_CNT) { ++ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); ++ return -EIO; ++ } ++ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ ++ pcie_replay_time_update(pcie_port); ++ return 0; ++} ++ ++static int __init ifx_pcie_bios_init(void) ++{ ++ void __iomem *io_map_base; ++ int pcie_port; ++ int startup_port; ++ ++ /* Enable AHB Master/ Slave */ ++ pcie_ahb_pmu_setup(); ++ ++ startup_port = IFX_PCIE_PORT0; ++ ++ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ ++ if (pcie_rc_initialize(pcie_port) == 0) { ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", ++ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); ++ /* Otherwise, warning will pop up */ ++ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); ++ if (io_map_base == NULL) { ++ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ ++ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); ++ /* XXX, clear error status */ ++ ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", ++ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, ++ &ifx_pcie_controller[pcie_port].pcic.io_resource); ++ ++ #ifdef IFX_PCIE_ERROR_INT ++ pcie_rc_core_int_init(pcie_port); ++ #endif /* IFX_PCIE_ERROR_INT */ ++ } ++ } ++ ++ return 0; ++} ++arch_initcall(ifx_pcie_bios_init); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); ++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -0,0 +1,135 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_H ++#define IFXMIPS_PCIE_H ++#include ++#include ++#include ++#include ++#include "ifxmips_pci_common.h" ++#include "ifxmips_pcie_reg.h" ++ ++/*! ++ \defgroup IFX_PCIE PCI Express bus driver module ++ \brief PCI Express IP module support VRX200 ++*/ ++ ++/*! ++ \defgroup IFX_PCIE_OS OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module common header file ++*/ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++#define CONFIG_VR9 ++ ++#ifdef CONFIG_VR9 ++#include "ifxmips_pcie_vr9.h" ++#elif defined (CONFIG_AR10) ++#include "ifxmips_pcie_ar10.h" ++#else ++#error "PCIE: platform not defined" ++#endif /* CONFIG_VR9 */ ++ ++#endif /* IFXMIPS_PCIE_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_ar10.h +@@ -0,0 +1,290 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_ar10.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver ar10 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_AR10_H ++#define IFXMIPS_PCIE_AR10_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++ ++/* Project header file */ ++#include ++#include ++#include ++#include ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ifx_ebu_led_enable(); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* XXX, moved to CGU to control AHBM */ ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Inbound, big endian */ ++ reg |= IFX_RCU_BE_AHB4S; ++ if (pcie_port == 0) { ++ reg |= IFX_RCU_BE_PCIE0M; ++ ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #endif ++ } ++ else { ++ reg |= IFX_RCU_BE_PCIE1M; ++ #ifdef CONFIG_IFX_PCIE1_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #endif ++ } ++ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ if (pcie_port == 0) { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE0_PDI; ++ } ++ else { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE1_PDI; ++ } ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ /* Enable PDI to access PCIe PHY register */ ++ PDI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PDI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset Core, bit 22 */ ++ if (pcie_port == 0) { ++ reg |= 0x00400000; ++ } ++ else { ++ reg |= 0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00400000; /* bit 22 */ ++ } ++ else { ++ reg &= ~0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg |= 0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg |= 0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg &= ~0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 0); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 0); ++ } ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++ ifx_ebu_led_disable(); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ pcie_msi_pic_init(pcie_port); ++ if (pcie_port == 0) { ++ MSI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ MSI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++ } ++#endif /* CONFIG_IFX_PCI */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ } ++ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_AR10_H */ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_msi.c +@@ -0,0 +1,392 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_msi.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCI MSI sub module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe MSI Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 02 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_MSI MSI OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_msi.c ++ \ingroup IFX_PCIE ++ \brief PCIe MSI OS interface file ++*/ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++#define IFX_MSI_IRQ_NUM 16 ++ ++enum { ++ IFX_PCIE_MSI_IDX0 = 0, ++ IFX_PCIE_MSI_IDX1, ++ IFX_PCIE_MSI_IDX2, ++ IFX_PCIE_MSI_IDX3, ++}; ++ ++typedef struct ifx_msi_irq_idx { ++ const int irq; ++ const int idx; ++}ifx_msi_irq_idx_t; ++ ++struct ifx_msi_pic { ++ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; ++ volatile u32 pic_endian; /* 0x40 */ ++}; ++typedef struct ifx_msi_pic *ifx_msi_pic_t; ++ ++typedef struct ifx_msi_irq { ++ const volatile ifx_msi_pic_t msi_pic_p; ++ const u32 msi_phy_base; ++ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; ++ /* ++ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is ++ * in use. ++ */ ++ u16 msi_free_irq_bitmask; ++ ++ /* ++ * Each bit in msi_multiple_irq_bitmask tells that the device using ++ * this bit in msi_free_irq_bitmask is also using the next bit. This ++ * is used so we can disable all of the MSI interrupts when a device ++ * uses multiple. ++ */ ++ u16 msi_multiple_irq_bitmask; ++}ifx_msi_irq_t; ++ ++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, ++ .msi_phy_base = PCIE_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ }, ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, ++ .msi_phy_base = PCIE1_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ ++ }, ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++}; ++ ++/* ++ * This lock controls updates to msi_free_irq_bitmask, ++ * msi_multiple_irq_bitmask and pic register settting ++ */ ++static DEFINE_SPINLOCK(ifx_pcie_msi_lock); ++ ++void pcie_msi_pic_init(int pcie_port) ++{ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; ++ spin_unlock(&ifx_pcie_msi_lock); ++} ++ ++/** ++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++ * \brief Called when a driver request MSI interrupts instead of the ++ * legacy INT A-D. This routine will allocate multiple interrupts ++ * for MSI devices that support them. A device can override this by ++ * programming the MSI control bits [6:4] before calling ++ * pci_enable_msi(). ++ * ++ * \param[in] pdev Device requesting MSI interrupts ++ * \param[in] desc MSI descriptor ++ * ++ * \return -EINVAL Invalid pcie root port or invalid msi bit ++ * \return 0 OK ++ * \ingroup IFX_PCIE_MSI ++ */ ++int ++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++{ ++ int irq, pos; ++ u16 control; ++ int irq_idx; ++ int irq_step; ++ int configured_private_bits; ++ int request_private_bits; ++ struct msi_msg msg; ++ u16 search_mask; ++ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); ++ ++ /* XXX, skip RC MSI itself */ ++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Read the MSI config to figure out how many IRQs this device ++ * wants. Most devices only want 1, which will give ++ * configured_private_bits and request_private_bits equal 0. ++ */ ++ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); ++ ++ /* ++ * If the number of private bits has been configured then use ++ * that value instead of the requested number. This gives the ++ * driver the chance to override the number of interrupts ++ * before calling pci_enable_msi(). ++ */ ++ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; ++ if (configured_private_bits == 0) { ++ /* Nothing is configured, so use the hardware requested size */ ++ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; ++ } ++ else { ++ /* ++ * Use the number of configured bits, assuming the ++ * driver wanted to override the hardware request ++ * value. ++ */ ++ request_private_bits = configured_private_bits; ++ } ++ ++ /* ++ * The PCI 2.3 spec mandates that there are at most 32 ++ * interrupts. If this device asks for more, only give it one. ++ */ ++ if (request_private_bits > 5) { ++ request_private_bits = 0; ++ } ++again: ++ /* ++ * The IRQs have to be aligned on a power of two based on the ++ * number being requested. ++ */ ++ irq_step = (1 << request_private_bits); ++ ++ /* Mask with one bit for each IRQ */ ++ search_mask = (1 << irq_step) - 1; ++ ++ /* ++ * We're going to search msi_free_irq_bitmask_lock for zero ++ * bits. This represents an MSI interrupt number that isn't in ++ * use. ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { ++ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; ++ break; ++ } ++ } ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ /* Make sure the search for available interrupts didn't fail */ ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ if (request_private_bits) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " ++ "interrupts, trying just one", __func__, 1 << request_private_bits); ++ request_private_bits = 0; ++ goto again; ++ } ++ else { ++ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ } ++ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; ++ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); ++ ++ /* ++ * Initialize MSI. This has to match the memory-write endianess from the device ++ * Address bits [23:12] ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | ++ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | ++ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ ++ /* Enable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", ++ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); ++ ++ /* Update the number of IRQs the device has available to it */ ++ control &= ~PCI_MSI_FLAGS_QSIZE; ++ control |= (request_private_bits << 4); ++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); ++ ++ set_irq_msi(irq, desc); ++ msg.address_hi = 0x0; ++ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; ++ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); ++ ++ write_msi_msg(irq, &msg); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++ return 0; ++} ++ ++static int ++pcie_msi_irq_to_port(unsigned int irq, int *port) ++{ ++ int ret = 0; ++ ++ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || ++ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { ++ *port = IFX_PCIE_PORT0; ++ } ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || ++ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { ++ *port = IFX_PCIE_PORT1; ++ } ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ else { ++ printk(KERN_ERR "%s: Attempted to teardown illegal " ++ "MSI interrupt (%d)\n", __func__, irq); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/** ++ * \fn void arch_teardown_msi_irq(unsigned int irq) ++ * \brief Called when a device no longer needs its MSI interrupts. All ++ * MSI interrupts for the device are freed. ++ * ++ * \param irq The devices first irq number. There may be multple in sequence. ++ * \return none ++ * \ingroup IFX_PCIE_MSI ++ */ ++void ++arch_teardown_msi_irq(unsigned int irq) ++{ ++ int pos; ++ int number_irqs; ++ u16 bitmask; ++ int pcie_port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); ++ ++ BUG_ON(irq > INT_NUM_IM4_IRL31); ++ ++ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { ++ return; ++ } ++ ++ /* Shift the mask to the correct bit location, not always correct ++ * Probally, the first match will be chosen. ++ */ ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { ++ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) ++ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { ++ break; ++ } ++ } ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); ++ return; ++ } ++ spin_lock(&ifx_pcie_msi_lock); ++ /* Disable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); ++ spin_unlock(&ifx_pcie_msi_lock); ++ /* ++ * Count the number of IRQs we need to free by looking at the ++ * msi_multiple_irq_bitmask. Each bit set means that the next ++ * IRQ is also owned by this device. ++ */ ++ number_irqs = 0; ++ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && ++ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { ++ number_irqs++; ++ } ++ number_irqs++; ++ ++ /* Mask with one bit for each IRQ */ ++ bitmask = (1 << number_irqs) - 1; ++ ++ bitmask <<= pos; ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { ++ printk(KERN_ERR "%s: Attempted to teardown MSI " ++ "interrupt (%d) not in use\n", __func__, irq); ++ return; ++ } ++ /* Checks are done, update the in use bitmask */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); ++ spin_unlock(&ifx_pcie_msi_lock); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); ++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_phy.c +@@ -0,0 +1,478 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_phy.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe PHY sub module ++** ++** DATE : 14 May 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 14 May,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_phy.c ++ \ingroup IFX_PCIE ++ \brief PCIe PHY PLL register programming source file ++*/ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++/* PCIe PDI only supports 16 bit operation */ ++ ++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ ++ ((*(volatile u16 *) (__addr)) = (__data)) ++ ++#define IFX_PCIE_PHY_REG_READ16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ ++ u16 read_data; \ ++ u16 write_data; \ ++ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ ++ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ ++ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ ++} while (0) ++ ++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ ++ ++//#define IFX_PCI_PHY_REG_DUMP ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++static void ++pcie_phy_reg_dump(int pcie_port) ++{ ++ printk("PLL REGFILE\n"); ++ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); ++ ++ printk("TX1 REGFILE\n"); ++ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); ++ ++ printk("TX2 REGFILE\n"); ++ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); ++ ++ printk("RX1 REGFILE\n"); ++ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); ++ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); ++ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); ++} ++#endif /* IFX_PCI_PHY_REG_DUMP */ ++ ++static void ++pcie_phy_comm_setup(int pcie_port) ++{ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* Improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* Reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++} ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++static void ++pcie_phy_36mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE ++static void ++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* Increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* Force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* Predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); ++ ++ /* improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE ++static void ++pcie_phy_25mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); ++ ++ /* en_ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE ++static void ++pcie_phy_100mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ ++ ++static int ++pcie_phy_wait_startup_ready(int pcie_port) ++{ ++ int i; ++ ++ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { ++ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { ++ break; ++ } ++ udelay(10); ++ } ++ if (i >= IFX_PCIE_PLL_TIMEOUT) { ++ printk(KERN_ERR "%s PLL Link timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static void ++pcie_phy_load_enable(int pcie_port, int slice) ++{ ++ /* Set the load_en of tx/rx slice to '1' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_disable(int pcie_port, int slice) ++{ ++ /* set the load_en of tx/rx slice to '0' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_war(int pcie_port) ++{ ++ int slice; ++ ++ for (slice = 1; slice < 4; slice++) { ++ pcie_phy_load_enable(pcie_port, slice); ++ udelay(1); ++ pcie_phy_load_disable(pcie_port, slice); ++ } ++} ++ ++static void ++pcie_phy_tx2_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx1_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx_modulation_war(int pcie_port) ++{ ++ int i; ++ ++#define PCIE_PHY_MODULATION_NUM 5 ++ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { ++ pcie_phy_tx2_modulation(pcie_port); ++ pcie_phy_tx1_modulation(pcie_port); ++ } ++#undef PCIE_PHY_MODULATION_NUM ++} ++ ++void ++pcie_phy_clock_mode_setup(int pcie_port) ++{ ++ pcie_pdi_big_endian(pcie_port); ++ ++ /* Enable PDI to access PCIe PHY register */ ++ pcie_pdi_pmu_enable(pcie_port); ++ ++ /* Configure PLL and PHY clock */ ++ pcie_phy_comm_setup(pcie_port); ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ pcie_phy_36mhz_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) ++ pcie_phy_36mhz_ssc_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) ++ pcie_phy_25mhz_mode_setup(pcie_port); ++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) ++ pcie_phy_100mhz_mode_setup(pcie_port); ++#else ++ #error "PCIE PHY Clock Mode must be chosen first!!!!" ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++ /* Enable PCIe PHY and make PLL setting take effect */ ++ pcie_phy_pmu_enable(pcie_port); ++ ++ /* Check if we are in startup_ready status */ ++ pcie_phy_wait_startup_ready(pcie_port); ++ ++ pcie_phy_load_war(pcie_port); ++ ++ /* Apply TX modulation workarounds */ ++ pcie_phy_tx_modulation_war(pcie_port); ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.c +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.c ++** PROJECT : IFX UEIP ++** MODULES : PCIE Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIE Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_PM Power Management functions ++ \ingroup IFX_PCIE ++ \brief IFX PCIE Root Complex Driver power management functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_pm.c ++ \ingroup IFX_PCIE ++ \brief source file for PCIE Root Complex Driver Power Management ++*/ ++ ++#ifndef EXPORT_SYMTAB ++#define EXPORT_SYMTAB ++#endif ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++ ++/* Project header */ ++#include ++#include ++#include ++#include ++#include "ifxmips_pcie_pm.h" ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++ * \brief the callback function to request pmcu state in the power management hardware-dependent module ++ * ++ * \param pmcuState This parameter is a PMCU state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++{ ++ switch(pmcuState) ++ { ++ case IFX_PMCU_STATE_D0: ++ return IFX_PMCU_RETURN_SUCCESS; ++ case IFX_PMCU_STATE_D1: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D2: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating ++ return IFX_PMCU_RETURN_SUCCESS; ++ default: ++ return IFX_PMCU_RETURN_DENIED; ++ } ++} ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++ * \brief the callback function to get pmcu state in the power management hardware-dependent module ++ ++ * \param pmcuState Pointer to return power state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_init(void) ++ * \brief Register with central PMCU module ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_init(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuRegister; ++ ++ /* XXX, hook driver context */ ++ ++ /* State function register */ ++ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); ++ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuRegister.pmcuModuleNr = 0; ++ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; ++ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; ++ pmcuRegister.pre = ifx_pcie_pmcu_prechange; ++ pmcuRegister.post= ifx_pcie_pmcu_postchange; ++ ifx_pmcu_register(&pmcuRegister); ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_exit(void) ++ * \brief Unregister with central PMCU module ++ * ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_exit(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuUnRegister; ++ ++ /* XXX, hook driver context */ ++ ++ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuUnRegister.pmcuModuleNr = 0; ++ ifx_pmcu_unregister(&pmcuUnRegister); ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.h ++** PROJECT : IFX UEIP ++** MODULES : PCIe Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_pm.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe Root Complex Driver Power Management ++*/ ++ ++#ifndef IFXMIPS_PCIE_PM_H ++#define IFXMIPS_PCIE_PM_H ++ ++void ifx_pcie_pmcu_init(void); ++void ifx_pcie_pmcu_exit(void); ++ ++#endif /* IFXMIPS_PCIE_PM_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_reg.h +@@ -0,0 +1,1001 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#endif /* IFXMIPS_PCIE_REG_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -0,0 +1,269 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_vr9.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver vr9 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_VR9_H ++#define IFXMIPS_PCIE_VR9_H ++ ++#include ++#include ++ ++#include ++#include ++ ++#define IFX_PCIE_GPIO_RESET 494 ++ ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) ++#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) ++#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) ++#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) ++#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ++ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ ++/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* Enable AHB bus master/slave */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ahb"); ++ clk_enable(clk); ++ ++ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); ++ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_enable(clk); ++ ++ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_disable(clk); ++ ++// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ /* SRAM2PDI endianness control. */ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ /* Enable PDI to access PCIe PHY register */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "pdi"); ++ clk_enable(clk); ++ //PDI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ ++ reg |= 0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ /* Reset PCIe PHY & Core, bit 22 */ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg |= 0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); ++// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ctl"); ++ clk_enable(clk); ++ clk = clk_get_sys("1d900000.pcie", "bus"); ++ clk_enable(clk); ++ ++ /* PCIe Core controller enabled */ ++// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ ++ /* Enable PCIe L0 Clock */ ++// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ struct clk *clk; ++ pcie_msi_pic_init(pcie_port); ++ clk = clk_get_sys("ltq_pcie", "msi"); ++ clk_enable(clk); ++// MSI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/arch/mips/pci/pci-legacy.c ++++ b/arch/mips/pci/pci-legacy.c +@@ -308,3 +308,30 @@ char *__init pcibios_setup(char *str) + return pcibios_plat_setup(str); + return str; + } ++ ++int pcibios_host_nr(void) ++{ ++ int count = 0; ++ struct pci_controller *hose; ++ list_for_each_entry(hose, &controllers, list) { ++ count++; ++ } ++ return count; ++} ++EXPORT_SYMBOL(pcibios_host_nr); ++ ++int pcibios_1st_host_bus_nr(void) ++{ ++ int bus_nr = 0; ++ struct pci_controller *hose; ++ ++ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); ++ ++ if (hose != NULL) { ++ if (hose->bus != NULL) { ++ bus_nr = hose->bus->number + 1; ++ } ++ } ++ return bus_nr; ++} ++EXPORT_SYMBOL(pcibios_1st_host_bus_nr); +--- /dev/null ++++ b/arch/mips/pci/pcie-lantiq.h +@@ -0,0 +1,1305 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++#include ++#include ++#include ++#include ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++//#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ if (g_pcie_debug_flag & (_m)) { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++ } \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define IFX_PCIE_GPIO_RESET 38 ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "ahb"); ++ clk_enable(clk); ++ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "phy"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1<PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "pdi"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1< 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/drivers/pci/pcie/Kconfig ++++ b/drivers/pci/pcie/Kconfig +@@ -52,6 +52,7 @@ config PCIEAER_INJECT + config PCIE_ECRC + bool "PCI Express ECRC settings control" + depends on PCIEAER ++ default n + help + Used to override firmware/bios settings for PCI Express ECRC + (transaction layer end-to-end CRC checking). +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -1390,6 +1390,8 @@ void pci_walk_bus(struct pci_bus *top, i + void *userdata); + int pci_cfg_space_size(struct pci_dev *dev); + unsigned char pci_bus_max_busnr(struct pci_bus *bus); ++int pcibios_host_nr(void); ++int pcibios_1st_host_bus_nr(void); + void pci_setup_bridge(struct pci_bus *bus); + resource_size_t pcibios_window_alignment(struct pci_bus *bus, + unsigned long type); +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1072,6 +1072,12 @@ + #define PCI_DEVICE_ID_SGI_IOC3 0x0003 + #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 + ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 ++ + #define PCI_VENDOR_ID_WINBOND 0x10ad + #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 + #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-5.4/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-5.4/0004-MIPS-lantiq-add-atm-hack.patch new file mode 100644 index 0000000000..1b1a0a1ca7 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0004-MIPS-lantiq-add-atm-hack.patch @@ -0,0 +1,482 @@ +From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:25 +0200 +Subject: [PATCH 04/36] MIPS: lantiq: add atm hack + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ + arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ + arch/mips/lantiq/irq.c | 2 + + arch/mips/mm/cache.c | 4 + + include/uapi/linux/atm.h | 6 + + net/atm/common.c | 6 + + net/atm/proc.c | 2 +- + 7 files changed, 416 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_atm.h ++** PROJECT : UEIP ++** MODULES : ATM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ATM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_ATM_H ++#define IFX_ATM_H ++ ++ ++ ++/*! ++ \defgroup IFX_ATM UEIP Project - ATM driver module ++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_IOCTL IOCTL Commands ++ \ingroup IFX_ATM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_STRUCT Structures ++ \ingroup IFX_ATM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_atm.h ++ \ingroup IFX_ATM ++ \brief ATM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ATM MIB ++ */ ++ ++/*! ++ \struct atm_cell_ifEntry_t ++ \brief Structure used for Cell Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifInErrors; /*!< counter of error ingress cells */ ++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ ++ __u32 ifOutErrors; /*!< counter of error egress cells */ ++} atm_cell_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_ifEntry_t ++ \brief Structure used for AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifInUcastPkts; /*!< counter of ingress packets */ ++ __u32 ifOutUcastPkts; /*!< counter of egress packets */ ++ __u32 ifInErrors; /*!< counter of error ingress packets */ ++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ ++ __u32 ifOutErros; /*!< counter of error egress packets */ ++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ ++} atm_aal5_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_vcc_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ This structure is a part of structure "atm_aal5_vcc_x_t". ++ */ ++typedef struct { ++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ ++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet ++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ ++} atm_aal5_vcc_t; ++ ++/*! ++ \struct atm_aal5_vcc_x_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". ++ */ ++typedef struct { ++ int vpi; /*!< VPI of the VCC to get MIB counters */ ++ int vci; /*!< VCI of the VCC to get MIB counters */ ++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ ++} atm_aal5_vcc_x_t; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief ATM IOCTL Magic Number ++ */ ++#define PPE_ATM_IOC_MAGIC 'o' ++/*! ++ \brief ATM IOCTL Command - Get Cell Level MIB Counters ++ ++ This command is obsolete. User can get cell level MIB from DSL API. ++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters ++ ++ Get AAL5 packet counters. ++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get Per PVC MIB Counters ++ ++ Get AAL5 packet counters for each PVC. ++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. ++ */ ++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) ++/*! ++ \brief Total Number of ATM IOCTL Commands ++ */ ++#define PPE_ATM_IOC_MAXNR 3 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_ATM_H ++ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h +@@ -0,0 +1,203 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ptm.h ++** PROJECT : UEIP ++** MODULES : PTM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global PTM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_PTM_H ++#define IFX_PTM_H ++ ++ ++ ++/*! ++ \defgroup IFX_PTM UEIP Project - PTM driver module ++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_IOCTL IOCTL Commands ++ \ingroup IFX_PTM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_STRUCT Structures ++ \ingroup IFX_PTM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ptm.h ++ \ingroup IFX_PTM ++ \brief PTM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_PTM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief PTM IOCTL Command - Get codeword MIB counters. ++ ++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. ++ */ ++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 ++/*! ++ \brief PTM IOCTL Command - Get packet MIB counters. ++ ++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. ++ */ ++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 ++/*! ++ \brief PTM IOCTL Command - Get firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 ++/*! ++ \brief PTM IOCTL Command - Set firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 ++/*! ++ \brief PTM IOCTL Command - Program priority value to TX queue mapping. ++ ++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. ++ */ ++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_PTM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Data Type ++ */ ++ ++/*! ++ \typedef PTM_CW_IF_ENTRY_T ++ \brief Wrapping of structure "ptm_cw_ifEntry_t". ++ */ ++/*! ++ \struct ptm_cw_ifEntry_t ++ \brief Structure used for CodeWord level MIB counters. ++ */ ++typedef struct ptm_cw_ifEntry_t { ++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ ++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ ++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ ++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ ++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ ++} PTM_CW_IF_ENTRY_T; ++ ++/*! ++ \typedef PTM_FRAME_MIB_T ++ \brief Wrapping of structure "ptm_frame_mib_t". ++ */ ++/*! ++ \struct ptm_frame_mib_t ++ \brief Structure used for packet level MIB counters. ++ */ ++typedef struct ptm_frame_mib_t { ++ uint32_t RxCorrect; /*!< output, number of ingress packet */ ++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ ++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ ++ uint32_t TxSend; /*!< output, number of egress packet */ ++} PTM_FRAME_MIB_T; ++ ++/*! ++ \typedef IFX_PTM_CFG_T ++ \brief Wrapping of structure "ptm_cfg_t". ++ */ ++/*! ++ \struct ptm_cfg_t ++ \brief Structure used for ETH/TC CRC configuration. ++ */ ++typedef struct ptm_cfg_t { ++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ ++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ ++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ ++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ ++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ ++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ ++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ ++} IFX_PTM_CFG_T; ++ ++/*! ++ \typedef IFX_PTM_PRIO_Q_MAP_T ++ \brief Wrapping of structure "ppe_prio_q_map". ++ */ ++/*! ++ \struct ppe_prio_q_map ++ \brief Structure used for Priority Value to TX Queue mapping. ++ */ ++typedef struct ppe_prio_q_map { ++ int pkt_prio; ++ int qid; ++ int vpi; // ignored in eth interface ++ int vci; // ignored in eth interface ++} IFX_PTM_PRIO_Q_MAP_T; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_PTM_H ++ +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -91,6 +92,7 @@ void ltq_disable_irq(struct irq_data *d) + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); + } ++EXPORT_SYMBOL(ltq_mask_and_ack_irq); + + void ltq_mask_and_ack_irq(struct irq_data *d) + { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -62,6 +62,10 @@ void (*_dma_cache_wback_inv)(unsigned lo + void (*_dma_cache_wback)(unsigned long start, unsigned long size); + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + ++EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); ++ + #endif /* CONFIG_DMA_NONCOHERENT */ + + /* +--- a/include/uapi/linux/atm.h ++++ b/include/uapi/linux/atm.h +@@ -131,8 +131,14 @@ + #define ATM_ABR 4 + #define ATM_ANYCLASS 5 /* compatible with everything */ + ++#define ATM_VBR_NRT ATM_VBR ++#define ATM_VBR_RT 6 ++#define ATM_UBR_PLUS 7 ++#define ATM_GFR 8 ++ + #define ATM_MAX_PCR -1 /* maximum available PCR */ + ++ + struct atm_trafprm { + unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ + int max_pcr; /* maximum PCR in cells per second */ +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -142,7 +142,7 @@ static void *vcc_seq_next(struct seq_fil + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-5.4/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-5.4/0008-MIPS-lantiq-backport-old-timer-code.patch new file mode 100644 index 0000000000..1d869afd9a --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -0,0 +1,1035 @@ +From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:30:56 +0200 +Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ + 3 files changed, 1001 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h + create mode 100644 arch/mips/lantiq/xway/timer.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +@@ -0,0 +1,155 @@ ++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++ ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++ ++/* ++ * ioctl Command ++ */ ++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ ++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ ++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ ++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ ++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ ++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ ++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ ++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ ++ ++/* ++ * Data Type Used to Call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field is ID of expected * ++ * timer/counter. If it's zero, a timer/counter would * ++ * be dynamically allocated and ID would be stored in * ++ * this field. * ++ * In command GPTU_GET_COUNT_VALUE, this field is * ++ * ignored. * ++ * In other command, this field is ID of timer/counter * ++ * allocated. */ ++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field contains flags to * ++ * specify how to configure timer/counter. * ++ * In command GPTU_START_TIMER, zero indicate start * ++ * and non-zero indicate resume timer/counter. * ++ * In other command, this field is ignored. */ ++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * ++ * init/reload value. * ++ * In command GPTU_SET_TIMER, this field contains * ++ * frequency (0.001Hz) of timer. * ++ * In command GPTU_GET_COUNT_VALUE, current count * ++ * value would be stored in this field. * ++ * In command GPTU_CALCULATE_DIVIDER, this field * ++ * contains frequency wanted, and after calculation, * ++ * divider would be stored in this field to overwrite * ++ * the frequency. * ++ * In other command, this field is ignored. */ ++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains process * ++ * ID to which signal would be sent. * ++ * In other command, this field is ignored. */ ++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains signal * ++ * number which would be sent. * ++ * In other command, this field is ignored. */ ++}; ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int lq_free_timer(unsigned int); ++extern int lq_start_timer(unsigned int, int); ++extern int lq_stop_timer(unsigned int); ++extern int lq_reset_counter_flags(u32 timer, u32 flags); ++extern int lq_get_count_value(unsigned int, unsigned long *); ++extern u32 lq_cal_divider(unsigned long); ++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int lq_set_counter(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,10 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o ++obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o ++ ++ifdef CONFIG_SOC_AMAZON_SE ++obj-y += gptu.o ++else ++obj-y += timer.o ++endif + + obj-y += vmmc.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/timer.c +@@ -0,0 +1,846 @@ ++#ifndef CONFIG_SOC_AMAZON_SE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "../clk.h" ++ ++#include ++#include ++#include ++ ++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 ++ ++#ifdef TIMER1A ++#define FIRST_TIMER TIMER1A ++#else ++#define FIRST_TIMER 2 ++#endif ++ ++/* ++ * GPTC divider is set or not. ++ */ ++#define GPTU_CLC_RMC_IS_SET 0 ++ ++/* ++ * Timer Interrupt (IRQ) ++ */ ++/* Must be adjusted when ICU driver is available */ ++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ ++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++/* ++ * GPTU Register Mapping ++ */ ++#define LQ_GPTU (KSEG1 + 0x1E100A00) ++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) ++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) ++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) ++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) ++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) ++ ++/* ++ * Clock Control Register ++ */ ++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) ++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) ++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) ++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) ++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) ++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) ++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) ++ ++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) ++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) ++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) ++ ++/* ++ * ID Register ++ */ ++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) ++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) ++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) ++ ++/* ++ * Control Register of Timer/Counter nX ++ * n is the index of block (1 based index) ++ * X is either A or B ++ */ ++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) ++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) ++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) ++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) ++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) ++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ ++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) ++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) ++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) ++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) ++ ++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) ++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) ++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) ++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) ++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) ++ ++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) ++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) ++ ++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++ ++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) ++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) ++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) ++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) ++#define TIMER_FLAG_NONE_EDGE 0x0000 ++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) ++#define TIMER_FLAG_REAL 0x0000 ++#define TIMER_FLAG_INVERT 0x0040 ++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) ++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) ++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) ++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 ++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) ++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) ++ ++struct timer_dev_timer { ++ unsigned int f_irq_on; ++ unsigned int irq; ++ unsigned int flag; ++ unsigned long arg1; ++ unsigned long arg2; ++}; ++ ++struct timer_dev { ++ struct mutex gptu_mutex; ++ unsigned int number_of_timers; ++ unsigned int occupation; ++ unsigned int f_gptu_on; ++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; ++}; ++ ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi) { ++ struct clk *clk = clk_get_fpi(); ++ return clk_get_rate(clk); ++} ++ ++ ++static long gptu_ioctl(struct file *, unsigned int, unsigned long); ++static int gptu_open(struct inode *, struct file *); ++static int gptu_release(struct inode *, struct file *); ++ ++static struct file_operations gptu_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gptu_ioctl, ++ .open = gptu_open, ++ .release = gptu_release ++}; ++ ++static struct miscdevice gptu_miscdev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "gptu", ++ .fops = &gptu_fops, ++}; ++ ++static struct timer_dev timer_dev; ++ ++static irqreturn_t timer_irq_handler(int irq, void *p) ++{ ++ unsigned int timer; ++ unsigned int flag; ++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; ++ ++ timer = irq - TIMER_INTERRUPT; ++ if (timer < timer_dev.number_of_timers ++ && dev_timer == &timer_dev.timer[timer]) { ++ /* Clear interrupt. */ ++ ltq_w32(1 << timer, LQ_GPTU_IRNCR); ++ ++ /* Call user hanler or signal. */ ++ flag = dev_timer->flag; ++ if (!(timer & 0x01) ++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ /* 16-bit timer or timer A of 32-bit timer */ ++ switch (TIMER_FLAG_MASK_HANDLE(flag)) { ++ case TIMER_FLAG_CALLBACK_IN_IRQ: ++ case TIMER_FLAG_CALLBACK_IN_HB: ++ if (dev_timer->arg1) ++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); ++ break; ++ case TIMER_FLAG_SIGNAL: ++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); ++ break; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static inline void lq_enable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ clk_enable(clk); ++ ++ //ltq_pmu_enable(PMU_GPT); ++ ++ /* Set divider as 1, disable write protection for SPEN, enable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x01) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(1) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(0); ++} ++ ++static inline void lq_disable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ ltq_w32(0x00, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ /* Set divider as 0, enable write protection for SPEN, disable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x00) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(0) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(1); ++ ++ clk_enable(clk); ++} ++ ++int lq_request_timer(unsigned int timer, unsigned int flag, ++ unsigned long value, unsigned long arg1, unsigned long arg2) ++{ ++ int ret = 0; ++ unsigned int con_reg, irnen_reg; ++ int n, X; ++ ++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", ++ timer, flag, value); ++ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) ++ value &= 0xFFFF; ++ else ++ timer &= ~0x01; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ /* ++ * Allocate timer. ++ */ ++ if (timer < FIRST_TIMER) { ++ unsigned int mask; ++ unsigned int shift; ++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ ++ unsigned int offset = TIMER2A; ++ ++ /* ++ * Pick up a free timer. ++ */ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ mask = 1 << offset; ++ shift = 1; ++ } else { ++ mask = 3 << offset; ++ shift = 2; ++ } ++ for (timer = offset; ++ timer < offset + timer_dev.number_of_timers; ++ timer += shift, mask <<= shift) ++ if (!(timer_dev.occupation & mask)) { ++ timer_dev.occupation |= mask; ++ break; ++ } ++ if (timer >= offset + timer_dev.number_of_timers) { ++ printk("failed![%d]\n", __LINE__); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } else ++ ret = timer; ++ } else { ++ register unsigned int mask; ++ ++ /* ++ * Check if the requested timer is free. ++ */ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if ((timer_dev.occupation & mask)) { ++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", ++ __LINE__, mask, timer_dev.occupation); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EBUSY; ++ } else { ++ timer_dev.occupation |= mask; ++ ret = 0; ++ } ++ } ++ ++ /* ++ * Prepare control register value. ++ */ ++ switch (TIMER_FLAG_MASK_EDGE(flag)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : ++ GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : ++ GPTU_CON_SRC_EG_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_SYNC(flag) == ++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : ++ GPTU_CON_SYNC_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_INVERT(flag) == ++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : ++ GPTU_CON_EXT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_STOP(flag) == ++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_TYPE(flag) == ++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : ++ GPTU_CON_CNT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_DIR(flag) == ++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ /* ++ * Fill up running data. ++ */ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flag; ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; ++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; ++ ++ /* ++ * Enable GPTU module. ++ */ ++ if (!timer_dev.f_gptu_on) { ++ lq_enable_gptu(); ++ timer_dev.f_gptu_on = 1; ++ } ++ ++ /* ++ * Enable IRQ. ++ */ ++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = ++ (unsigned long) find_task_by_vpid((int) arg1); ++ ++ irnen_reg = 1 << (timer - FIRST_TIMER); ++ ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL ++ || (TIMER_FLAG_MASK_HANDLE(flag) == ++ TIMER_FLAG_CALLBACK_IN_IRQ ++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { ++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; ++ } ++ } else ++ irnen_reg = 0; ++ ++ /* ++ * Write config register, reload value and enable interrupt. ++ */ ++ n = timer >> 1; ++ X = timer & 0x01; ++ *LQ_GPTU_CON(n, X) = con_reg; ++ *LQ_GPTU_RELOAD(n, X) = value; ++ /* printk("reload value = %d\n", (u32)value); */ ++ *LQ_GPTU_IRNEN |= irnen_reg; ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ printk("successful!\n"); ++ return ret; ++} ++EXPORT_SYMBOL(lq_request_timer); ++ ++int lq_free_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ if (GPTU_CON_EN(n, X)) ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); ++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); ++ ++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { ++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; ++ } ++ ++ timer_dev.occupation &= ~mask; ++ if (!timer_dev.occupation && timer_dev.f_gptu_on) { ++ lq_disable_gptu(); ++ timer_dev.f_gptu_on = 0; ++ } ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_free_timer); ++ ++int lq_start_timer(unsigned int timer, int is_resume) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_start_timer); ++ ++int lq_stop_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_stop_timer); ++ ++int lq_reset_counter_flags(u32 timer, u32 flags) ++{ ++ unsigned int oflag; ++ unsigned int mask, con_reg; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ switch (TIMER_FLAG_MASK_EDGE(flags)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); ++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); ++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flags; ++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_CON(n, X) = con_reg; ++ smp_wmb(); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(lq_reset_counter_flags); ++ ++int lq_get_count_value(unsigned int timer, unsigned long *value) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *value = *LQ_GPTU_COUNT(n, X); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_get_count_value); ++ ++u32 lq_cal_divider(unsigned long freq) ++{ ++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); ++ u32 clock_divider = 1; ++ module_freq = fpi * 1000; ++ do_div(module_freq, clock_divider * freq); ++ return module_freq; ++} ++EXPORT_SYMBOL(lq_cal_divider); ++ ++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, ++ int is_ext_src, unsigned int handle_flag, unsigned long arg1, ++ unsigned long arg2) ++{ ++ unsigned long divider; ++ unsigned int flag; ++ ++ divider = lq_cal_divider(freq); ++ if (divider == 0) ++ return -EINVAL; ++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) ++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) ++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) ++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN ++ | TIMER_FLAG_MASK_HANDLE(handle_flag); ++ ++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", ++ timer, freq, divider); ++ return lq_request_timer(timer, flag, divider, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_timer); ++ ++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, ++ unsigned long arg1, unsigned long arg2) ++{ ++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); ++ return lq_request_timer(timer, flag, reload, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_counter); ++ ++static long gptu_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret; ++ struct gptu_ioctl_param param; ++ ++ if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ copy_from_user(¶m, (void __user *)arg, sizeof(param)); ++ ++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER ++ || GPTU_SET_COUNTER) && param.timer < 2) ++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) ++ && !access_ok((void __user *)arg, ++ sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case GPTU_REQUEST_TIMER: ++ ret = lq_request_timer(param.timer, param.flag, param.value, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_FREE_TIMER: ++ ret = lq_free_timer(param.timer); ++ break; ++ case GPTU_START_TIMER: ++ ret = lq_start_timer(param.timer, param.flag); ++ break; ++ case GPTU_STOP_TIMER: ++ ret = lq_stop_timer(param.timer); ++ break; ++ case GPTU_GET_COUNT_VALUE: ++ ret = lq_get_count_value(param.timer, ¶m.value); ++ if (!ret) ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ break; ++ case GPTU_CALCULATE_DIVIDER: ++ param.value = lq_cal_divider(param.value); ++ if (param.value == 0) ++ ret = -EINVAL; ++ else { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_TIMER: ++ ret = lq_set_timer(param.timer, param.value, ++ TIMER_FLAG_MASK_STOP(param.flag) != ++ TIMER_FLAG_ONCE ? 1 : 0, ++ TIMER_FLAG_MASK_SRC(param.flag) == ++ TIMER_FLAG_EXT_SRC ? 1 : 0, ++ TIMER_FLAG_MASK_HANDLE(param.flag) == ++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : ++ TIMER_FLAG_NO_HANDLE, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_COUNTER: ++ lq_set_counter(param.timer, param.flag, param.value, 0, 0); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ default: ++ ret = -ENOTTY; ++ } ++ ++ return ret; ++} ++ ++static int gptu_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++int __init lq_gptu_init(void) ++{ ++ int ret; ++ unsigned int i; ++ ++ ltq_w32(0, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ memset(&timer_dev, 0, sizeof(timer_dev)); ++ mutex_init(&timer_dev.gptu_mutex); ++ ++ lq_enable_gptu(); ++ timer_dev.number_of_timers = GPTU_ID_CFG * 2; ++ lq_disable_gptu(); ++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) ++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; ++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); ++ ++ ret = misc_register(&gptu_miscdev); ++ if (ret) { ++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); ++ return ret; ++ } else { ++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); ++ } ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { ++ for (; i >= 0; i--) ++ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ return ret; ++ } else { ++ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; ++ disable_irq(timer_dev.timer[i].irq); ++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); ++ } ++ } ++ ++ return 0; ++} ++ ++void __exit lq_gptu_exit(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ if (timer_dev.timer[i].f_irq_on) ++ disable_irq(timer_dev.timer[i].irq); ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ } ++ lq_disable_gptu(); ++ misc_deregister(&gptu_miscdev); ++} ++ ++module_init(lq_gptu_init); ++module_exit(lq_gptu_exit); ++ ++#endif diff --git a/target/linux/lantiq/patches-5.4/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-5.4/0018-MTD-nand-lots-of-xrx200-fixes.patch new file mode 100644 index 0000000000..d68466c368 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0018-MTD-nand-lots-of-xrx200-fixes.patch @@ -0,0 +1,121 @@ +From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 23:12:15 +0200 +Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +--- a/drivers/mtd/nand/raw/xway_nand.c ++++ b/drivers/mtd/nand/raw/xway_nand.c +@@ -61,6 +61,24 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) ++#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) ++#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) ++ ++/* ++ * req_mask provides a mechanism to prevent interference between ++ * nand and pci (probably only relevant for the BT Home Hub 2B). ++ * Setting it causes the corresponding pci req pins to be masked ++ * during nand access, and also moves ebu locking from the read/write ++ * functions to the chip select function to ensure that the whole ++ * operation runs with interrupts disabled. ++ * In addition it switches on some extra waiting in xway_cmd_ctrl(). ++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, ++ * which in turn seems to be necessary for the nor chip to be recognised ++ * reliably, on a board (Home Hub 2B again) which has both nor and nand. ++ */ ++static __be32 req_mask = 0; ++ + struct xway_nand_data { + struct nand_chip chip; + unsigned long csflags; +@@ -91,10 +109,22 @@ static void xway_select_chip(struct nand + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ ++ if (req_mask) { ++ /* Unmask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); ++ } ++ + spin_unlock_irqrestore(&ebu_lock, data->csflags); + break; + case 0: + spin_lock_irqsave(&ebu_lock, data->csflags); ++ ++ if (req_mask) { ++ /* Mask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); ++ } ++ + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); + break; +@@ -107,6 +137,11 @@ static void xway_cmd_ctrl(struct nand_ch + { + struct mtd_info *mtd = nand_to_mtd(chip); + ++ if (req_mask) { ++ if (cmd != NAND_CMD_STATUS) ++ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ ++ } ++ + if (cmd == NAND_CMD_NONE) + return; + +@@ -117,6 +152,24 @@ static void xway_cmd_ctrl(struct nand_ch + + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; ++ ++ if (req_mask) { ++ /* ++ * program and erase have their own busy handlers ++ * status and sequential in needs no delay ++ */ ++ switch (cmd) { ++ case NAND_CMD_ERASE1: ++ case NAND_CMD_SEQIN: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_READID: ++ return; ++ } ++ ++ /* wait until command is processed */ ++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) ++ ; ++ } + } + + static int xway_dev_ready(struct nand_chip *chip) +@@ -156,6 +209,7 @@ static int xway_nand_probe(struct platfo + int err; + u32 cs; + u32 cs_flag = 0; ++ const __be32 *req_mask_ptr; + + /* Allocate memory for the device structure (and zero it) */ + data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), +@@ -191,6 +245,15 @@ static int xway_nand_probe(struct platfo + if (!err && cs == 1) + cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; + ++ req_mask_ptr = of_get_property(pdev->dev.of_node, ++ "req-mask", NULL); ++ ++ /* ++ * Load the PCI req lines to mask from the device tree. If the ++ * property is not present, setting req_mask to 0 disables masking. ++ */ ++ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); ++ + /* setup the EBU to run in NAND mode on our base addr */ + ltq_ebu_w32(CPHYSADDR(data->nandaddr) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-5.4/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-5.4/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch new file mode 100644 index 0000000000..c1fc59487a --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch @@ -0,0 +1,25 @@ +From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:18:00 +0200 +Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash + +Signed-off-by: John Crispin +--- + drivers/mtd/maps/lantiq-flash.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd + if (!ltq_mtd->map) + return -ENOMEM; + +- ltq_mtd->map->phys = ltq_mtd->res->start; ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map->phys = NO_XIP; ++ else ++ ltq_mtd->map->phys = ltq_mtd->res->start; ++ ltq_mtd->res->start; + ltq_mtd->map->size = resource_size(ltq_mtd->res); + ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); + if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-5.4/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-5.4/0023-NET-PHY-add-led-support-for-intel-xway.patch new file mode 100644 index 0000000000..5a668b6f56 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0023-NET-PHY-add-led-support-for-intel-xway.patch @@ -0,0 +1,294 @@ +From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:15:36 +0200 +Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G + +Signed-off-by: John Crispin +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 237 insertions(+) + create mode 100644 drivers/net/phy/lantiq.c + +--- a/drivers/net/phy/intel-xway.c ++++ b/drivers/net/phy/intel-xway.c +@@ -145,6 +145,51 @@ + #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 + #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 + ++#if IS_ENABLED(CONFIG_OF_MDIO) ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ u32 tmp; ++ ++ /* store the led values if one was passed by the devicetree */ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); ++ ++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) ++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp); ++ ++ return 0; ++} ++#else ++static int vr9_gphy_of_reg_init(struct phy_device *phydev) ++{ ++ return 0; ++} ++#endif /* CONFIG_OF_MDIO */ ++ + static int xway_gphy_config_init(struct phy_device *phydev) + { + int err; +@@ -183,6 +228,7 @@ static int xway_gphy_config_init(struct + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); + ++ vr9_gphy_of_reg_init(phydev); + return 0; + } + +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt +@@ -0,0 +1,216 @@ ++Lanitq PHY binding ++============================================ ++ ++This devicetree binding controls the lantiq ethernet phys led functionality. ++ ++Example: ++ mdio@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "lantiq,xrx200-mdio"; ++ phy5: ethernet-phy@5 { ++ reg = <0x1>; ++ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; ++ }; ++ phy11: ethernet-phy@11 { ++ reg = <0x11>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy12: ethernet-phy@12 { ++ reg = <0x12>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ phy13: ethernet-phy@13 { ++ reg = <0x13>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led2h = <0x00>; ++ lantiq,led2l = <0x03>; ++ }; ++ phy14: ethernet-phy@14 { ++ reg = <0x14>; ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; ++ lantiq,led1h = <0x00>; ++ lantiq,led1l = <0x03>; ++ }; ++ }; ++ ++Register Description ++============================================ ++ ++LEDCH: ++ ++Name Hardware Reset Value ++LEDCH 0x00C5 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| FBF | SBF |RES | NACS | ++========================================= ++ ++Field Bits Type Description ++FBF 7:6 RW Fast Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++SBF 5:4 RW Slow Blink Frequency ++ --- ++ 0x0 (00b) F02HZ 2 Hz blinking frequency ++ 0x1 (01b) F04HZ 4 Hz blinking frequency ++ 0x2 (10b) F08HZ 8 Hz blinking frequency ++ 0x3 (11b) F16HZ 16 Hz blinking frequency ++ ++NACS 2:0 RW Inverse of Scan Function ++ --- ++ 0x0 (000b) NONE No Function ++ 0x1 (001b) LINK Complex function enabled when link is up ++ 0x2 (010b) PDOWN Complex function enabled when device is powered-down ++ 0x3 (011b) EEE Complex function enabled when device is in EEE mode ++ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running ++ 0x5 (101b) ABIST Complex function enabled when analog self-test is running ++ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running ++ 0x7 (111b) TEST Complex function enabled when test mode is running ++ ++LEDCL: ++ ++Name Hardware Reset Value ++LEDCL 0x0067 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++|RES | SCAN |RES | CBLINK | ++========================================= ++ ++Field Bits Type Description ++SCAN 6:4 RW Complex Scan Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++CBLINK 2:0 RW Complex Blinking Configuration ++ --- ++ 000 B NONE No Function ++ 001 B LINK Complex function enabled when link is up ++ 010 B PDOWN Complex function enabled when device is powered-down ++ 011 B EEE Complex function enabled when device is in EEE mode ++ 100 B ANEG Complex function enabled when auto-negotiation is running ++ 101 B ABIST Complex function enabled when analog self-test is running ++ 110 B CDIAG Complex function enabled when cable diagnostics are running ++ 111 B TEST Complex function enabled when test mode is running ++ ++LEDxH: ++ ++Name Hardware Reset Value ++LED0H 0x0070 ++LED1H 0x0020 ++LED2H 0x0040 ++LED3H 0x0040 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| CON | BLINKF | ++========================================= ++ ++Field Bits Type Description ++CON 7:4 RW Constant On Configuration ++ --- ++ 0x0 (0000b) NONE LED does not light up constantly ++ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN LED is on when device is powered-down ++ 0x9 (1001b) EEE LED is on when device is in EEE mode ++ 0xA (1010b) ANEG LED is on when auto-negotiation is running ++ 0xB (1011b) ABIST LED is on when analog self-test is running ++ 0xC (1100b) CDIAG LED is on when cable diagnostics are running ++ ++BLINKF 3:0 RW Fast Blinking Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are running ++ ++LEDxL: ++ ++Name Hardware Reset Value ++LED0L 0x0003 ++LED1L 0x0000 ++LED2L 0x0000 ++LED3L 0x0020 ++ ++| 15 | | | | | | | 8 | ++========================================= ++| RES | ++========================================= ++ ++| 7 | | | | | | | 0 | ++========================================= ++| BLINKS | PULSE | ++========================================= ++ ++Field Bits Type Description ++BLINKS 7:4 RW Slow Blinkin Configuration ++ --- ++ 0x0 (0000b) NONE No Blinking ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s ++ 0x8 (1000b) PDOWN Blink when device is powered-down ++ 0x9 (1001b) EEE Blink when device is in EEE mode ++ 0xA (1010b) ANEG Blink when auto-negotiation is running ++ 0xB (1011b) ABIST Blink when analog self-test is running ++ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning ++ ++PULSE 3:0 RW Pulsing Configuration ++ The pulse field is a mask field by which certain events can be combined ++ --- ++ 0x0 (0000b) NONE No pulsing ++ 0x1 (0001b) TXACT Transmit activity ++ 0x2 (0010b) RXACT Receive activity ++ 0x4 (0100b) COL Collision ++ 0x8 (1000b) RES Reserved diff --git a/target/linux/lantiq/patches-5.4/0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch b/target/linux/lantiq/patches-5.4/0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch new file mode 100644 index 0000000000..a364d6d67b --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch @@ -0,0 +1,55 @@ +From d0ee51bbb7ce9880749a3d4794ec1fbbcda0f381 Mon Sep 17 00:00:00 2001 +From: Mathias Kresin +Date: Sun, 7 Jul 2019 21:45:51 +0200 +Subject: [PATCH] MIPS: lantiq revert DSA switch driver PMU/clock changes + +Switch back to the former used names, to make the legacy switch driver +happy. + +Signed-off-by: Mathias Kresin +--- + arch/mips/lantiq/xway/sysctrl.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -503,7 +503,7 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI); + clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI); + clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL); +- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP); ++ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP); + clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); + clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); + } else if (of_machine_is_compatible("lantiq,ar10")) { +@@ -511,11 +511,11 @@ void __init ltq_soc_init(void) + ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz()); + clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0); + clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1); +- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | ++ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | + PMU_PPE_DP | PMU_PPE_TC); + clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); +- clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY); +- clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY); ++ clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY); ++ clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY); + clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); + clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE); + clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); +@@ -534,12 +534,12 @@ void __init ltq_soc_init(void) + clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS); + + clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); +- clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, ++ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, + PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB | PMU_PPE_TOP); +- clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY); +- clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY); ++ clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY); ++ clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY); + clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO); + clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); + clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); diff --git a/target/linux/lantiq/patches-5.4/0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch b/target/linux/lantiq/patches-5.4/0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch new file mode 100644 index 0000000000..6a2143e17e --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch @@ -0,0 +1,3470 @@ +From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Mon, 22 Oct 2012 12:22:23 +0200 +Subject: NET: MIPS: lantiq: adds xrx200 ethernet and switch driver + +--- + drivers/net/ethernet/Kconfig | 8 +- + drivers/net/ethernet/Makefile | 1 + + drivers/net/ethernet/lantiq_pce.h | 163 +++ + drivers/net/ethernet/lantiq_xrx200_legacy.c | 1798 +++++++++++++++++++++++++++++++ + drivers/net/ethernet/lantiq_xrx200_legacy.h | 1328 +++++++++++++++++++++++ + 5 files changed, 3297 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/lantiq_pce.h + create mode 100644 drivers/net/ethernet/lantiq_xrx200_legacy.c + create mode 100644 drivers/net/ethernet/lantiq_xrx200_legacy.h + +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -108,7 +108,13 @@ config LANTIQ_ETOP + tristate "Lantiq SoC ETOP driver" + depends on SOC_TYPE_XWAY + ---help--- +- Support for the MII0 inside the Lantiq SoC ++ Support for the MII0 inside the Lantiq ADSL SoC ++ ++config LANTIQ_XRX200_LEGACY ++ tristate "Lantiq SoC XRX200 driver" ++ depends on SOC_TYPE_XWAY ++ ---help--- ++ Support for the MII0 inside the Lantiq VDSL SoC + + config LANTIQ_XRX200 + tristate "Lantiq / Intel xRX200 PMAC network driver" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -51,6 +51,7 @@ obj-$(CONFIG_JME) += jme.o + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o + obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o ++obj-$(CONFIG_LANTIQ_XRX200_LEGACY) += lantiq_xrx200_legacy.o + obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ + obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/ + obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_pce.h +@@ -0,0 +1,163 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2012 John Crispin ++ * ++ * PCE microcode extracted from UGW5.2 switch api ++ */ ++ ++/* Switch API Micro Code V0.3 */ ++enum { ++ OUT_MAC0 = 0, ++ OUT_MAC1, ++ OUT_MAC2, ++ OUT_MAC3, ++ OUT_MAC4, ++ OUT_MAC5, ++ OUT_ETHTYP, ++ OUT_VTAG0, ++ OUT_VTAG1, ++ OUT_ITAG0, ++ OUT_ITAG1, /*10 */ ++ OUT_ITAG2, ++ OUT_ITAG3, ++ OUT_IP0, ++ OUT_IP1, ++ OUT_IP2, ++ OUT_IP3, ++ OUT_SIP0, ++ OUT_SIP1, ++ OUT_SIP2, ++ OUT_SIP3, /*20*/ ++ OUT_SIP4, ++ OUT_SIP5, ++ OUT_SIP6, ++ OUT_SIP7, ++ OUT_DIP0, ++ OUT_DIP1, ++ OUT_DIP2, ++ OUT_DIP3, ++ OUT_DIP4, ++ OUT_DIP5, /*30*/ ++ OUT_DIP6, ++ OUT_DIP7, ++ OUT_SESID, ++ OUT_PROT, ++ OUT_APP0, ++ OUT_APP1, ++ OUT_IGMP0, ++ OUT_IGMP1, ++ OUT_IPOFF, /*39*/ ++ OUT_NONE = 63 ++}; ++ ++/* parser's microcode length type */ ++#define INSTR 0 ++#define IPV6 1 ++#define LENACCU 2 ++ ++/* parser's microcode flag type */ ++enum { ++ FLAG_ITAG = 0, ++ FLAG_VLAN, ++ FLAG_SNAP, ++ FLAG_PPPOE, ++ FLAG_IPV6, ++ FLAG_IPV6FL, ++ FLAG_IPV4, ++ FLAG_IGMP, ++ FLAG_TU, ++ FLAG_HOP, ++ FLAG_NN1, /*10 */ ++ FLAG_NN2, ++ FLAG_END, ++ FLAG_NO, /*13*/ ++}; ++ ++/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */ ++#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ ++ { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }} ++struct pce_microcode { ++ unsigned short val[4]; ++/* unsigned short val_2; ++ unsigned short val_1; ++ unsigned short val_0;*/ ++} pce_microcode[] = { ++ /* value mask ns fields L type flags ipv4_len */ ++ MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0), ++ MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0), ++ MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1), ++ MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0), ++ MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0), ++ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0), ++ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0), ++ MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0), ++ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0), ++ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++}; +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_xrx200_legacy.c +@@ -0,0 +1,1927 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland ++ * Copyright (C) 2012 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "lantiq_pce.h" ++#include "lantiq_xrx200_legacy.h" ++ ++#define SW_POLLING ++#define SW_ROUTING ++ ++#ifdef SW_ROUTING ++#define XRX200_MAX_DEV 2 ++#else ++#define XRX200_MAX_DEV 1 ++#endif ++ ++#define XRX200_MAX_VLAN 64 ++#define XRX200_PCE_ACTVLAN_IDX 0x01 ++#define XRX200_PCE_VLANMAP_IDX 0x02 ++ ++#define XRX200_MAX_PORT 7 ++#define XRX200_MAX_DMA 8 ++ ++#define XRX200_HEADROOM 4 ++ ++#define XRX200_TX_TIMEOUT (10 * HZ) ++ ++/* port type */ ++#define XRX200_PORT_TYPE_PHY 1 ++#define XRX200_PORT_TYPE_MAC 2 ++ ++/* DMA */ ++#define XRX200_DMA_DATA_LEN 0x600 ++#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0 ++#define XRX200_DMA_RX 0 ++#define XRX200_DMA_TX 1 ++#define XRX200_DMA_TX_2 3 ++#define XRX200_DMA_IS_TX(x) (x%2) ++#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x)) ++ ++/* fetch / store dma */ ++#define FDMA_PCTRL0 0x2A00 ++#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18)) ++#define SDMA_PCTRL0 0x2F00 ++#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18)) ++ ++/* buffer management */ ++#define BM_PCFG0 0x200 ++#define BM_PCFGx(x) (BM_PCFG0 + (x * 8)) ++ ++/* MDIO */ ++#define MDIO_GLOB 0x0000 ++#define MDIO_CTRL 0x0020 ++#define MDIO_READ 0x0024 ++#define MDIO_WRITE 0x0028 ++#define MDIO_PHY0 0x0054 ++#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned))) ++#define MDIO_CLK_CFG0 0x002C ++#define MDIO_CLK_CFG1 0x0030 ++ ++#define MDIO_GLOB_ENABLE 0x8000 ++#define MDIO_BUSY BIT(12) ++#define MDIO_RD BIT(11) ++#define MDIO_WR BIT(10) ++#define MDIO_MASK 0x1f ++#define MDIO_ADDRSHIFT 5 ++#define MDIO1_25MHZ 9 ++ ++#define MDIO_PHY_LINK_DOWN 0x4000 ++#define MDIO_PHY_LINK_UP 0x2000 ++ ++#define MDIO_PHY_SPEED_M10 0x0000 ++#define MDIO_PHY_SPEED_M100 0x0800 ++#define MDIO_PHY_SPEED_G1 0x1000 ++ ++#define MDIO_PHY_FDUP_EN 0x0200 ++#define MDIO_PHY_FDUP_DIS 0x0600 ++ ++#define MDIO_PHY_LINK_MASK 0x6000 ++#define MDIO_PHY_SPEED_MASK 0x1800 ++#define MDIO_PHY_FDUP_MASK 0x0600 ++#define MDIO_PHY_ADDR_MASK 0x001f ++#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \ ++ MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK ++ ++/* MII */ ++#define MII_CFG(p) (p * 8) ++ ++#define MII_CFG_EN BIT(14) ++ ++#define MII_CFG_MODE_MIIP 0x0 ++#define MII_CFG_MODE_MIIM 0x1 ++#define MII_CFG_MODE_RMIIP 0x2 ++#define MII_CFG_MODE_RMIIM 0x3 ++#define MII_CFG_MODE_RGMII 0x4 ++#define MII_CFG_MODE_MASK 0xf ++ ++#define MII_CFG_RATE_M2P5 0x00 ++#define MII_CFG_RATE_M25 0x10 ++#define MII_CFG_RATE_M125 0x20 ++#define MII_CFG_RATE_M50 0x30 ++#define MII_CFG_RATE_AUTO 0x40 ++#define MII_CFG_RATE_MASK 0x70 ++ ++/* cpu port mac */ ++#define PMAC_HD_CTL 0x0000 ++#define PMAC_RX_IPG 0x0024 ++#define PMAC_EWAN 0x002c ++ ++#define PMAC_IPG_MASK 0xf ++#define PMAC_HD_CTL_AS 0x0008 ++#define PMAC_HD_CTL_AC 0x0004 ++#define PMAC_HD_CTL_RC 0x0010 ++#define PMAC_HD_CTL_RXSH 0x0040 ++#define PMAC_HD_CTL_AST 0x0080 ++#define PMAC_HD_CTL_RST 0x0100 ++ ++/* PCE */ ++#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4)) ++#define PCE_TBL_MASK 0x1120 ++#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4)) ++#define PCE_TBL_ADDR 0x1138 ++#define PCE_TBL_CTRL 0x113c ++#define PCE_PMAP1 0x114c ++#define PCE_PMAP2 0x1150 ++#define PCE_PMAP3 0x1154 ++#define PCE_GCTRL_REG(x) (0x1158 + (x * 4)) ++#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4)) ++ ++#define PCE_TBL_BUSY BIT(15) ++#define PCE_TBL_CFG_ADDR_MASK 0x1f ++#define PCE_TBL_CFG_ADWR 0x20 ++#define PCE_TBL_CFG_ADWR_MASK 0x60 ++#define PCE_INGRESS BIT(11) ++ ++/* MAC */ ++#define MAC_FLEN_REG (0x2314) ++#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4)) ++ ++/* buffer management */ ++#define BM_PCFG(p) (0x200 + (p * 8)) ++ ++/* special tag in TX path header */ ++#define SPID_SHIFT 24 ++#define DPID_SHIFT 16 ++#define DPID_ENABLE 1 ++#define SPID_CPU_PORT 2 ++#define PORT_MAP_SEL BIT(15) ++#define PORT_MAP_EN BIT(14) ++#define PORT_MAP_SHIFT 1 ++#define PORT_MAP_MASK 0x3f ++ ++#define SPPID_MASK 0x7 ++#define SPPID_SHIFT 4 ++ ++/* MII regs not yet in linux */ ++#define MDIO_DEVAD_NONE (-1) ++#define ADVERTIZE_MPD (1 << 10) ++ ++struct xrx200_port { ++ u8 num; ++ u8 phy_addr; ++ u16 flags; ++ phy_interface_t phy_if; ++ ++ int link; ++ int gpio; ++ enum of_gpio_flags gpio_flags; ++ ++ struct phy_device *phydev; ++ struct device_node *phy_node; ++}; ++ ++struct xrx200_chan { ++ int idx; ++ int refcount; ++ int tx_free; ++ ++ struct net_device dummy_dev; ++ struct net_device *devs[XRX200_MAX_DEV]; ++ ++ struct tasklet_struct tasklet; ++ struct napi_struct napi; ++ struct ltq_dma_channel dma; ++ struct sk_buff *skb[LTQ_DESC_NUM]; ++ ++ spinlock_t lock; ++}; ++ ++struct xrx200_hw { ++ struct clk *clk; ++ struct mii_bus *mii_bus; ++ u8 phy_addr[XRX200_MAX_PORT]; ++ ++ struct xrx200_chan chan[XRX200_MAX_DMA]; ++ u16 vlan_vid[XRX200_MAX_VLAN]; ++ u16 vlan_port_map[XRX200_MAX_VLAN]; ++ ++ struct net_device *devs[XRX200_MAX_DEV]; ++ int num_devs; ++ ++ int port_map[XRX200_MAX_PORT]; ++ unsigned short wan_map; ++ ++ struct switch_dev swdev; ++}; ++ ++struct xrx200_priv { ++ struct net_device_stats stats; ++ int id; ++ ++ struct xrx200_port port[XRX200_MAX_PORT]; ++ int num_port; ++ bool wan; ++ bool sw; ++ unsigned short port_map; ++ unsigned char mac[6]; ++ ++ struct xrx200_hw *hw; ++}; ++ ++static __iomem void *xrx200_switch_membase; ++static __iomem void *xrx200_mii_membase; ++static __iomem void *xrx200_mdio_membase; ++static __iomem void *xrx200_pmac_membase; ++ ++#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x)) ++#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y)) ++#define ltq_switch_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_switch_membase + (z)) ++ ++#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x)) ++#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y)) ++#define ltq_mdio_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_mdio_membase + (z)) ++ ++#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x)) ++#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y)) ++#define ltq_mii_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_mii_membase + (z)) ++ ++#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x)) ++#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y)) ++#define ltq_pmac_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_pmac_membase + (z)) ++ ++#define XRX200_GLOBAL_REGATTR(reg) \ ++ .id = reg, \ ++ .type = SWITCH_TYPE_INT, \ ++ .set = xrx200_set_global_attr, \ ++ .get = xrx200_get_global_attr ++ ++#define XRX200_PORT_REGATTR(reg) \ ++ .id = reg, \ ++ .type = SWITCH_TYPE_INT, \ ++ .set = xrx200_set_port_attr, \ ++ .get = xrx200_get_port_attr ++ ++static int xrx200sw_read_x(int reg, int x) ++{ ++ int value, mask, addr; ++ ++ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); ++ value = ltq_switch_r32(addr); ++ mask = (1 << xrx200sw_reg[reg].size) - 1; ++ value = (value >> xrx200sw_reg[reg].shift); ++ ++ return (value & mask); ++} ++ ++static int xrx200sw_read(int reg) ++{ ++ return xrx200sw_read_x(reg, 0); ++} ++ ++static void xrx200sw_write_x(int value, int reg, int x) ++{ ++ int mask, addr; ++ ++ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); ++ mask = (1 << xrx200sw_reg[reg].size) - 1; ++ mask = (mask << xrx200sw_reg[reg].shift); ++ value = (value << xrx200sw_reg[reg].shift) & mask; ++ ++ ltq_switch_w32_mask(mask, value, addr); ++} ++ ++static void xrx200sw_write(int value, int reg) ++{ ++ xrx200sw_write_x(value, reg, 0); ++} ++ ++struct xrx200_pce_table_entry { ++ int index; // PCE_TBL_ADDR.ADDR = pData->table_index ++ int table; // PCE_TBL_CTRL.ADDR = pData->table ++ unsigned short key[8]; ++ unsigned short val[5]; ++ unsigned short mask; ++ unsigned short type; ++ unsigned short valid; ++ unsigned short gmap; ++}; ++ ++static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl) ++{ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // prepare the table access: ++ // PCE_TBL_ADDR.ADDR = pData->table_index ++ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); ++ // PCE_TBL_CTRL.ADDR = pData->table ++ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); ++ ++ //(address-based read) ++ xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD ++ ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access ++ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // read the keys ++ tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7); ++ tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6); ++ tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5); ++ tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4); ++ tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3); ++ tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2); ++ tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1); ++ tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0); ++ ++ // read the values ++ tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4); ++ tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3); ++ tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2); ++ tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1); ++ tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0); ++ ++ // read the mask ++ tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0); ++ // read the type ++ tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE); ++ // read the valid flag ++ tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD); ++ // read the group map ++ tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP); ++ ++ return 0; ++} ++ ++static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl) ++{ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // prepare the table access: ++ // PCE_TBL_ADDR.ADDR = pData->table_index ++ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); ++ // PCE_TBL_CTRL.ADDR = pData->table ++ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); ++ ++ //(address-based write) ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD ++ ++ // read the keys ++ xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7); ++ xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6); ++ xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5); ++ xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4); ++ xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3); ++ xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2); ++ xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1); ++ xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0); ++ ++ // read the values ++ xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4); ++ xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3); ++ xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2); ++ xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1); ++ xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0); ++ ++ // read the mask ++ xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0); ++ // read the type ++ xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE); ++ // read the valid flag ++ xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD); ++ // read the group map ++ xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP); ++ ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access ++ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ return 0; ++} ++ ++static void xrx200sw_fixup_pvids(void) ++{ ++ int index, p, portmap, untagged; ++ struct xrx200_pce_table_entry tem; ++ struct xrx200_pce_table_entry tev; ++ ++ portmap = 0; ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ portmap |= BIT(p); ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ ++ for (index = XRX200_MAX_VLAN; index-- > 0;) ++ { ++ tev.index = index; ++ xrx200_pce_table_entry_read(&tev); ++ ++ if (tev.valid == 0) ++ continue; ++ ++ tem.index = index; ++ xrx200_pce_table_entry_read(&tem); ++ ++ if (tem.val[0] == 0) ++ continue; ++ ++ untagged = portmap & (tem.val[1] ^ tem.val[2]); ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ if (untagged & BIT(p)) ++ { ++ portmap &= ~BIT(p); ++ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); ++ } ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ if (portmap & BIT(p)) ++ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); ++ } ++} ++ ++// swconfig interface ++static void xrx200_hw_init(struct xrx200_hw *hw); ++ ++// global ++static int xrx200sw_reset_switch(struct switch_dev *dev) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ ++ xrx200_hw_init(hw); ++ ++ return 0; ++} ++ ++static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ int p; ++ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) { ++ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p); ++ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p); ++ } ++ ++ xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN); ++ return 0; ++} ++ ++static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ val->value.i = xrx200sw_read(attr->id); ++ return 0; ++} ++ ++static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ xrx200sw_write(val->value.i, attr->id); ++ return 0; ++} ++ ++static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ val->value.i = xrx200sw_read(attr->id); ++ return 0; ++} ++ ++// vlan ++static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ int i; ++ struct xrx200_pce_table_entry tev; ++ struct xrx200_pce_table_entry tem; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ ++ for (i = 0; i < XRX200_MAX_VLAN; i++) ++ { ++ tev.index = i; ++ xrx200_pce_table_entry_read(&tev); ++ if (tev.key[0] == val->value.i && i != val->port_vlan) ++ return -EINVAL; ++ } ++ ++ hw->vlan_vid[val->port_vlan] = val->value.i; ++ ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ tev.key[0] = val->value.i; ++ tev.valid = val->value.i > 0; ++ xrx200_pce_table_entry_write(&tev); ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ tem.val[0] = val->value.i; ++ xrx200_pce_table_entry_write(&tem); ++ ++ xrx200sw_fixup_pvids(); ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry te; ++ ++ te.table = XRX200_PCE_ACTVLAN_IDX; ++ te.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&te); ++ val->value.i = te.key[0]; ++ ++ return 0; ++} ++ ++static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ int i, portmap, tagmap, untagged; ++ struct xrx200_pce_table_entry tem; ++ ++ portmap = 0; ++ tagmap = 0; ++ for (i = 0; i < val->len; i++) ++ { ++ struct switch_port *p = &val->value.ports[i]; ++ ++ portmap |= (1 << p->id); ++ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ++ tagmap |= (1 << p->id); ++ } ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ ++ untagged = portmap ^ tagmap; ++ for (i = 0; i < XRX200_MAX_VLAN; i++) ++ { ++ tem.index = i; ++ xrx200_pce_table_entry_read(&tem); ++ ++ if (tem.val[0] == 0) ++ continue; ++ ++ if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i)) ++ return -EINVAL; ++ } ++ ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ ++ // auto-enable this vlan if not enabled already ++ if (tem.val[0] == 0) ++ { ++ struct switch_val v; ++ v.port_vlan = val->port_vlan; ++ v.value.i = val->port_vlan; ++ if(xrx200sw_set_vlan_vid(dev, NULL, &v)) ++ return -EINVAL; ++ ++ //read updated tem ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ } ++ ++ tem.val[1] = portmap; ++ tem.val[2] = tagmap; ++ xrx200_pce_table_entry_write(&tem); ++ ++ ltq_switch_w32_mask(0, portmap, PCE_PMAP2); ++ ltq_switch_w32_mask(0, portmap, PCE_PMAP3); ++ hw->vlan_port_map[val->port_vlan] = portmap; ++ ++ xrx200sw_fixup_pvids(); ++ ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ int i; ++ unsigned short ports, tags; ++ struct xrx200_pce_table_entry tem; ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ ++ ports = tem.val[1]; ++ tags = tem.val[2]; ++ ++ for (i = 0; i < XRX200_MAX_PORT; i++) { ++ struct switch_port *p; ++ ++ if (!(ports & (1 << i))) ++ continue; ++ ++ p = &val->value.ports[val->len++]; ++ p->id = i; ++ if (tags & (1 << i)) ++ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); ++ else ++ p->flags = 0; ++ } ++ ++ return 0; ++} ++ ++static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ ++ if (tev.key[0] == 0) ++ return -EINVAL; ++ ++ tev.valid = val->value.i; ++ xrx200_pce_table_entry_write(&tev); ++ ++ xrx200sw_fixup_pvids(); ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ val->value.i = tev.valid; ++ ++ return 0; ++} ++ ++// port ++static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port); ++ xrx200_pce_table_entry_read(&tev); ++ ++ *val = tev.key[0]; ++ return 0; ++} ++ ++static int xrx200sw_get_port_link(struct switch_dev *dev, ++ int port, ++ struct switch_port_link *link) ++{ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port); ++ if (!link->link) ++ return 0; ++ ++ link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port); ++ ++ link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010); ++ link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020); ++ link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port)); ++ ++ link->speed = SWITCH_PORT_SPEED_10; ++ if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port)) ++ link->speed = SWITCH_PORT_SPEED_100; ++ if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port)) ++ link->speed = SWITCH_PORT_SPEED_1000; ++ ++ return 0; ++} ++ ++static int xrx200sw_set_port_link(struct switch_dev *dev, int port, ++ struct switch_port_link *link) ++{ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ return switch_generic_set_link(dev, port, link); ++} ++ ++static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val); ++static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg); ++ ++static int xrx200sw_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ ++ *value = xrx200_mdio_rd(hw->mii_bus, hw->phy_addr[addr], reg); ++ ++ return 0; ++} ++ ++static int xrx200sw_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ ++ return xrx200_mdio_wr(hw->mii_bus, hw->phy_addr[addr], reg, value); ++} ++ ++static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if (val->port_vlan >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ xrx200sw_write_x(val->value.i, attr->id, val->port_vlan); ++ return 0; ++} ++ ++static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if (val->port_vlan >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ val->value.i = xrx200sw_read_x(attr->id, val->port_vlan); ++ return 0; ++} ++ ++// attributes ++static struct switch_attr xrx200sw_globals[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .set = xrx200_set_vlan_mode_enable, ++ .get = xrx200_get_vlan_mode_enable, ++ .name = "enable_vlan", ++ .description = "Enable VLAN mode", ++ .max = 1}, ++}; ++ ++static struct switch_attr xrx200sw_port[] = { ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR), ++ .name = "uvr", ++ .description = "Unknown VLAN Rule", ++ .max = 1, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR), ++ .name = "vsr", ++ .description = "VLAN Security Rule", ++ .max = 1, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR), ++ .name = "vinr", ++ .description = "VLAN Ingress Tag Rule", ++ .max = 2, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM), ++ .name = "tvm", ++ .description = "Transparent VLAN Mode", ++ .max = 1, ++ }, ++}; ++ ++static struct switch_attr xrx200sw_vlan[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "vid", ++ .description = "VLAN ID (0-4094)", ++ .set = xrx200sw_set_vlan_vid, ++ .get = xrx200sw_get_vlan_vid, ++ .max = 4094, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable", ++ .description = "Enable VLAN", ++ .set = xrx200sw_set_vlan_enable, ++ .get = xrx200sw_get_vlan_enable, ++ .max = 1, ++ }, ++}; ++ ++static const struct switch_dev_ops xrx200sw_ops = { ++ .attr_global = { ++ .attr = xrx200sw_globals, ++ .n_attr = ARRAY_SIZE(xrx200sw_globals), ++ }, ++ .attr_port = { ++ .attr = xrx200sw_port, ++ .n_attr = ARRAY_SIZE(xrx200sw_port), ++ }, ++ .attr_vlan = { ++ .attr = xrx200sw_vlan, ++ .n_attr = ARRAY_SIZE(xrx200sw_vlan), ++ }, ++ .get_vlan_ports = xrx200sw_get_vlan_ports, ++ .set_vlan_ports = xrx200sw_set_vlan_ports, ++ .get_port_pvid = xrx200sw_get_port_pvid, ++ .reset_switch = xrx200sw_reset_switch, ++ .get_port_link = xrx200sw_get_port_link, ++ .set_port_link = xrx200sw_set_port_link, ++// .get_port_stats = xrx200sw_get_port_stats, //TODO ++ .phy_read16 = xrx200sw_phy_read16, ++ .phy_write16 = xrx200sw_phy_write16, ++}; ++ ++static int xrx200sw_init(struct xrx200_hw *hw) ++{ ++ int netdev_num; ++ ++ for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++) ++ { ++ struct switch_dev *swdev; ++ struct net_device *dev = hw->devs[netdev_num]; ++ struct xrx200_priv *priv = netdev_priv(dev); ++ if (!priv->sw) ++ continue; ++ ++ swdev = &hw->swdev; ++ ++ swdev->name = "Lantiq XRX200 Switch"; ++ swdev->vlans = XRX200_MAX_VLAN; ++ swdev->ports = XRX200_MAX_PORT; ++ swdev->cpu_port = 6; ++ swdev->ops = &xrx200sw_ops; ++ ++ register_switch(swdev, dev); ++ return 0; // enough switches ++ } ++ return 0; ++} ++ ++static int xrx200_open(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ int i; ++ ++ for (i = 0; i < XRX200_MAX_DMA; i++) { ++ if (!priv->hw->chan[i].dma.irq) ++ continue; ++ spin_lock_bh(&priv->hw->chan[i].lock); ++ if (!priv->hw->chan[i].refcount) { ++ if (XRX200_DMA_IS_RX(i)) ++ napi_enable(&priv->hw->chan[i].napi); ++ ltq_dma_open(&priv->hw->chan[i].dma); ++ ltq_dma_enable_irq(&priv->hw->chan[i].dma); ++ } ++ priv->hw->chan[i].refcount++; ++ spin_unlock_bh(&priv->hw->chan[i].lock); ++ } ++ for (i = 0; i < priv->num_port; i++) ++ if (priv->port[i].phydev) ++ phy_start(priv->port[i].phydev); ++ netif_wake_queue(dev); ++ ++ return 0; ++} ++ ++static int xrx200_close(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ int i; ++ ++ netif_stop_queue(dev); ++ ++ for (i = 0; i < priv->num_port; i++) ++ if (priv->port[i].phydev) ++ phy_stop(priv->port[i].phydev); ++ ++ for (i = 0; i < XRX200_MAX_DMA; i++) { ++ if (!priv->hw->chan[i].dma.irq) ++ continue; ++ ++ priv->hw->chan[i].refcount--; ++ if (!priv->hw->chan[i].refcount) { ++ if (XRX200_DMA_IS_RX(i)) ++ napi_disable(&priv->hw->chan[i].napi); ++ spin_lock_bh(&priv->hw->chan[i].lock); ++ ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma); ++ spin_unlock_bh(&priv->hw->chan[i].lock); ++ } ++ } ++ ++ return 0; ++} ++ ++static int xrx200_alloc_skb(struct xrx200_chan *ch) ++{ ++#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD) ++ ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD); ++ if (!ch->skb[ch->dma.desc]) ++ goto skip; ++ ++ skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD); ++ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->dma.dev, ++ ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN, ++ DMA_FROM_DEVICE); ++ ch->dma.desc_base[ch->dma.desc].addr = ++ CPHYSADDR(ch->skb[ch->dma.desc]->data); ++ skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); ++ ++skip: ++ ch->dma.desc_base[ch->dma.desc].ctl = ++ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | ++ XRX200_DMA_DATA_LEN; ++ ++ return 0; ++} ++ ++static void xrx200_hw_receive(struct xrx200_chan *ch, int id) ++{ ++ struct net_device *dev = ch->devs[id]; ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ int len = (desc->ctl & LTQ_DMA_SIZE_MASK); ++ int ret; ++ ++ ret = xrx200_alloc_skb(ch); ++ ++ ch->dma.desc++; ++ ch->dma.desc %= LTQ_DESC_NUM; ++ ++ if (ret) { ++ netdev_err(dev, ++ "failed to allocate new rx buffer\n"); ++ return; ++ } ++ ++ skb_put(skb, len); ++#ifdef SW_ROUTING ++ skb_pull(skb, 8); ++#endif ++ skb->dev = dev; ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_receive_skb(skb); ++ priv->stats.rx_packets++; ++ priv->stats.rx_bytes+=len; ++} ++ ++static int xrx200_poll_rx(struct napi_struct *napi, int budget) ++{ ++ struct xrx200_chan *ch = container_of(napi, ++ struct xrx200_chan, napi); ++ struct xrx200_priv *priv = netdev_priv(ch->devs[0]); ++ int rx = 0; ++ int complete = 0; ++ ++ while ((rx < budget) && !complete) { ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++#ifdef SW_ROUTING ++ struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ u8 *special_tag = (u8*)skb->data; ++ int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK; ++ xrx200_hw_receive(ch, priv->hw->port_map[port]); ++#else ++ xrx200_hw_receive(ch, 0); ++#endif ++ rx++; ++ } else { ++ complete = 1; ++ } ++ } ++ ++ if (complete || !rx) { ++ napi_complete(&ch->napi); ++ ltq_dma_enable_irq(&ch->dma); ++ } ++ ++ return rx; ++} ++ ++static void xrx200_tx_housekeeping(unsigned long ptr) ++{ ++ struct xrx200_chan *ch = (struct xrx200_chan *) ptr; ++ int pkts = 0; ++ int i; ++ ++ spin_lock_bh(&ch->lock); ++ ltq_dma_ack_irq(&ch->dma); ++ while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ struct sk_buff *skb = ch->skb[ch->tx_free]; ++ ++ pkts++; ++ ch->skb[ch->tx_free] = NULL; ++ dev_kfree_skb(skb); ++ memset(&ch->dma.desc_base[ch->tx_free], 0, ++ sizeof(struct ltq_dma_desc)); ++ ch->tx_free++; ++ ch->tx_free %= LTQ_DESC_NUM; ++ } ++ ltq_dma_enable_irq(&ch->dma); ++ spin_unlock_bh(&ch->lock); ++ ++ if (!pkts) ++ return; ++ ++ for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) ++ netif_wake_queue(ch->devs[i]); ++} ++ ++static struct net_device_stats *xrx200_get_stats (struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ ++ return &priv->stats; ++} ++ ++static void xrx200_tx_timeout(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ ++ printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name); ++ ++ priv->stats.tx_errors++; ++ netif_wake_queue(dev); ++} ++ ++static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct xrx200_chan *ch; ++ struct ltq_dma_desc *desc; ++ u32 byte_offset; ++ int ret = NETDEV_TX_OK; ++ int len; ++#ifdef SW_ROUTING ++ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE; ++#endif ++ if(priv->id) ++ ch = &priv->hw->chan[XRX200_DMA_TX_2]; ++ else ++ ch = &priv->hw->chan[XRX200_DMA_TX]; ++ ++ desc = &ch->dma.desc_base[ch->dma.desc]; ++ ++ skb->dev = dev; ++ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; ++ ++#ifdef SW_ROUTING ++ if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) { ++ u16 port_map = priv->port_map; ++ ++ if (priv->sw && skb->protocol == htons(ETH_P_8021Q)) { ++ u16 vid; ++ int i; ++ ++ port_map = 0; ++ if (!__vlan_get_tag(skb, &vid)) { ++ for (i = 0; i < XRX200_MAX_VLAN; i++) { ++ if (priv->hw->vlan_vid[i] != vid) ++ continue; ++ port_map = priv->hw->vlan_port_map[i]; ++ break; ++ } ++ } ++ } ++ ++ special_tag |= (port_map << PORT_MAP_SHIFT) | ++ PORT_MAP_SEL | PORT_MAP_EN; ++ } ++ if(priv->wan) ++ special_tag |= (1 << DPID_SHIFT); ++ if(skb_headroom(skb) < 4) { ++ struct sk_buff *tmp = skb_realloc_headroom(skb, 4); ++ dev_kfree_skb_any(skb); ++ skb = tmp; ++ } ++ skb_push(skb, 4); ++ memcpy(skb->data, &special_tag, sizeof(u32)); ++ len += 4; ++#endif ++ ++ /* dma needs to start on a 16 byte aligned address */ ++ byte_offset = CPHYSADDR(skb->data) % 16; ++ ++ spin_lock_bh(&ch->lock); ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { ++ netdev_err(dev, "tx ring full\n"); ++ netif_stop_queue(dev); ++ ret = NETDEV_TX_BUSY; ++ goto out; ++ } ++ ++ ch->skb[ch->dma.desc] = skb; ++ ++ netif_trans_update(dev); ++ ++ desc->addr = ((unsigned int) dma_map_single(ch->dma.dev, skb->data, len, ++ DMA_TO_DEVICE)) - byte_offset; ++ wmb(); ++ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | ++ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); ++ ch->dma.desc++; ++ ch->dma.desc %= LTQ_DESC_NUM; ++ if (ch->dma.desc == ch->tx_free) ++ netif_stop_queue(dev); ++ ++ ++ priv->stats.tx_packets++; ++ priv->stats.tx_bytes+=len; ++ ++out: ++ spin_unlock_bh(&ch->lock); ++ ++ return ret; ++} ++ ++static irqreturn_t xrx200_dma_irq(int irq, void *priv) ++{ ++ struct xrx200_hw *hw = priv; ++ int chnr = irq - XRX200_DMA_IRQ; ++ struct xrx200_chan *ch = &hw->chan[chnr]; ++ ++ ltq_dma_disable_irq(&ch->dma); ++ ltq_dma_ack_irq(&ch->dma); ++ ++ if (chnr % 2) ++ tasklet_schedule(&ch->tasklet); ++ else ++ napi_schedule(&ch->napi); ++ ++ return IRQ_HANDLED; ++} ++ ++static int xrx200_dma_init(struct device *dev, struct xrx200_hw *hw) ++{ ++ int i, err = 0; ++ ++ ltq_dma_init_port(DMA_PORT_ETOP); ++ ++ for (i = 0; i < 8 && !err; i++) { ++ int irq = XRX200_DMA_IRQ + i; ++ struct xrx200_chan *ch = &hw->chan[i]; ++ ++ spin_lock_init(&ch->lock); ++ ++ ch->idx = ch->dma.nr = i; ++ ch->dma.dev = dev; ++ ++ if (i == XRX200_DMA_TX) { ++ ltq_dma_alloc_tx(&ch->dma); ++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw); ++ } else if (i == XRX200_DMA_TX_2) { ++ ltq_dma_alloc_tx(&ch->dma); ++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw); ++ } else if (i == XRX200_DMA_RX) { ++ ltq_dma_alloc_rx(&ch->dma); ++ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; ++ ch->dma.desc++) ++ if (xrx200_alloc_skb(ch)) ++ err = -ENOMEM; ++ ch->dma.desc = 0; ++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw); ++ } else ++ continue; ++ ++ if (!err) ++ ch->dma.irq = irq; ++ else ++ pr_err("net-xrx200: failed to request irq %d\n", irq); ++ } ++ ++ return err; ++} ++ ++#ifdef SW_POLLING ++static void xrx200_gmac_update(struct xrx200_port *port) ++{ ++ u16 phyaddr = port->phydev->mdio.addr & MDIO_PHY_ADDR_MASK; ++ u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK; ++ u16 miirate = 0; ++ ++ switch (port->phydev->speed) { ++ case SPEED_1000: ++ phyaddr |= MDIO_PHY_SPEED_G1; ++ miirate = MII_CFG_RATE_M125; ++ break; ++ ++ case SPEED_100: ++ phyaddr |= MDIO_PHY_SPEED_M100; ++ switch (miimode) { ++ case MII_CFG_MODE_RMIIM: ++ case MII_CFG_MODE_RMIIP: ++ miirate = MII_CFG_RATE_M50; ++ break; ++ default: ++ miirate = MII_CFG_RATE_M25; ++ break; ++ } ++ break; ++ ++ default: ++ phyaddr |= MDIO_PHY_SPEED_M10; ++ miirate = MII_CFG_RATE_M2P5; ++ break; ++ } ++ ++ if (port->phydev->link) ++ phyaddr |= MDIO_PHY_LINK_UP; ++ else ++ phyaddr |= MDIO_PHY_LINK_DOWN; ++ ++ if (port->phydev->duplex == DUPLEX_FULL) ++ phyaddr |= MDIO_PHY_FDUP_EN; ++ else ++ phyaddr |= MDIO_PHY_FDUP_DIS; ++ ++ ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num)); ++ ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num)); ++ udelay(1); ++} ++#else ++static void xrx200_gmac_update(struct xrx200_port *port) ++{ ++ ++} ++#endif ++ ++static void xrx200_mdio_link(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ int i; ++ ++ for (i = 0; i < priv->num_port; i++) { ++ if (!priv->port[i].phydev) ++ continue; ++ ++ if (priv->port[i].link != priv->port[i].phydev->link) { ++ xrx200_gmac_update(&priv->port[i]); ++ priv->port[i].link = priv->port[i].phydev->link; ++ netdev_info(dev, "port %d %s link\n", ++ priv->port[i].num, ++ (priv->port[i].link)?("got"):("lost")); ++ } ++ } ++} ++ ++static inline int xrx200_mdio_poll(struct mii_bus *bus) ++{ ++ unsigned cnt = 10000; ++ ++ while (likely(cnt--)) { ++ unsigned ctrl = ltq_mdio_r32(MDIO_CTRL); ++ if ((ctrl & MDIO_BUSY) == 0) ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) ++{ ++ if (xrx200_mdio_poll(bus)) ++ return 1; ++ ++ ltq_mdio_w32(val, MDIO_WRITE); ++ ltq_mdio_w32(MDIO_BUSY | MDIO_WR | ++ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | ++ (reg & MDIO_MASK), ++ MDIO_CTRL); ++ ++ return 0; ++} ++ ++static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg) ++{ ++ if (xrx200_mdio_poll(bus)) ++ return -1; ++ ++ ltq_mdio_w32(MDIO_BUSY | MDIO_RD | ++ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | ++ (reg & MDIO_MASK), ++ MDIO_CTRL); ++ ++ if (xrx200_mdio_poll(bus)) ++ return -1; ++ ++ return ltq_mdio_r32(MDIO_READ); ++} ++ ++static int xrx200_phy_has_link(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ int i; ++ ++ for (i = 0; i < priv->num_port; i++) { ++ if (!priv->port[i].phydev) ++ continue; ++ ++ if (priv->port[i].phydev->link) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static void xrx200_phy_link_change(struct phy_device *phydev, bool up, bool do_carrier) ++{ ++ struct net_device *netdev = phydev->attached_dev; ++ ++ if (do_carrier) { ++ if (up) ++ netif_carrier_on(netdev); ++ else if (!xrx200_phy_has_link(netdev)) ++ netif_carrier_off(netdev); ++ } ++ ++ phydev->adjust_link(netdev); ++} ++ ++static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ unsigned val; ++ ++ phydev = mdiobus_get_phy(priv->hw->mii_bus, port->phy_addr); ++ ++ if (!phydev) { ++ netdev_err(dev, "no PHY found\n"); ++ return -ENODEV; ++ } ++ ++ phydev = phy_connect(dev, phydev_name(phydev), &xrx200_mdio_link, ++ port->phy_if); ++ ++ if (IS_ERR(phydev)) { ++ netdev_err(dev, "Could not attach to PHY\n"); ++ return PTR_ERR(phydev); ++ } ++ ++ linkmode_zero(phydev->supported); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported); ++ linkmode_set_bit_array(phy_10_100_features_array, ++ ARRAY_SIZE(phy_10_100_features_array), ++ phydev->supported); ++ linkmode_set_bit_array(phy_gbit_features_array, ++ ARRAY_SIZE(phy_gbit_features_array), ++ phydev->supported); ++ linkmode_copy(phydev->advertising, phydev->supported); ++ ++ port->phydev = phydev; ++ phydev->phy_link_change = xrx200_phy_link_change; ++ ++ phy_attached_info(phydev); ++ ++#ifdef SW_POLLING ++ phy_read_status(phydev); ++ ++ val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); ++ val |= ADVERTIZE_MPD; ++ xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); ++ xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040); ++ ++ phy_start_aneg(phydev); ++#endif ++ return 0; ++} ++ ++static void xrx200_port_config(struct xrx200_priv *priv, ++ const struct xrx200_port *port) ++{ ++ u16 miimode = 0; ++ ++ switch (port->num) { ++ case 0: /* xMII0 */ ++ case 1: /* xMII1 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ if (port->flags & XRX200_PORT_TYPE_PHY) ++ /* MII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ else ++ /* MII PHY mode, connected to external MAC */ ++ miimode = MII_CFG_MODE_MIIP; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ if (port->flags & XRX200_PORT_TYPE_PHY) ++ /* RMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RMIIM; ++ else ++ /* RMII PHY mode, connected to external MAC */ ++ miimode = MII_CFG_MODE_RMIIP; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ /* RGMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RGMII; ++ break; ++ default: ++ break; ++ } ++ break; ++ case 2: /* internal GPHY0 */ ++ case 3: /* internal GPHY0 */ ++ case 4: /* internal GPHY1 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ case PHY_INTERFACE_MODE_GMII: ++ /* MII MAC mode, connected to internal GPHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ break; ++ default: ++ break; ++ } ++ break; ++ case 5: /* internal GPHY1 or xMII2 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ /* MII MAC mode, connected to internal GPHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ /* RGMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RGMII; ++ break; ++ default: ++ break; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN, ++ MII_CFG(port->num)); ++} ++ ++static int xrx200_init(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct sockaddr mac; ++ int err, i; ++ ++#ifndef SW_POLLING ++ unsigned int reg = 0; ++ ++ /* enable auto polling */ ++ for (i = 0; i < priv->num_port; i++) ++ reg |= BIT(priv->port[i].num); ++ ltq_mdio_w32(reg, MDIO_CLK_CFG0); ++ ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1); ++#endif ++ ++ /* setup each port */ ++ for (i = 0; i < priv->num_port; i++) ++ xrx200_port_config(priv, &priv->port[i]); ++ ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ if (!is_valid_ether_addr(mac.sa_data)) { ++ pr_warn("net-xrx200: invalid MAC, using random\n"); ++ eth_random_addr(mac.sa_data); ++ dev->addr_assign_type |= NET_ADDR_RANDOM; ++ } ++ ++ err = eth_mac_addr(dev, &mac); ++ if (err) ++ goto err_netdev; ++ ++ for (i = 0; i < priv->num_port; i++) ++ if (xrx200_mdio_probe(dev, &priv->port[i])) ++ pr_warn("xrx200-mdio: probing phy of port %d failed\n", ++ priv->port[i].num); ++ ++ return 0; ++ ++err_netdev: ++ unregister_netdev(dev); ++ free_netdev(dev); ++ return err; ++} ++ ++static void xrx200_pci_microcode(void) ++{ ++ int i; ++ ++ ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK, ++ PCE_TBL_CFG_ADWR, PCE_TBL_CTRL); ++ ltq_switch_w32(0, PCE_TBL_MASK); ++ ++ for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) { ++ ltq_switch_w32(i, PCE_TBL_ADDR); ++ ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0)); ++ ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1)); ++ ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2)); ++ ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3)); ++ ++ // start the table access: ++ ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL); ++ while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY); ++ } ++ ++ /* tell the switch that the microcode is loaded */ ++ ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0)); ++} ++ ++static void xrx200_hw_init(struct xrx200_hw *hw) ++{ ++ int i; ++ ++ /* enable clock gate */ ++ clk_enable(hw->clk); ++ ++ ltq_switch_w32(1, 0); ++ mdelay(100); ++ ltq_switch_w32(0, 0); ++ /* ++ * TODO: we should really disbale all phys/miis here and explicitly ++ * enable them in the device secific init function ++ */ ++ ++ /* disable port fetch/store dma */ ++ for (i = 0; i < 7; i++ ) { ++ ltq_switch_w32(0, FDMA_PCTRLx(i)); ++ ltq_switch_w32(0, SDMA_PCTRLx(i)); ++ } ++ ++ /* enable Switch */ ++ ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB); ++ ++ /* load the pce microcode */ ++ xrx200_pci_microcode(); ++ ++ /* Default unknown Broadcat/Multicast/Unicast port maps */ ++ ltq_switch_w32(0x40, PCE_PMAP1); ++ ltq_switch_w32(0x40, PCE_PMAP2); ++ ltq_switch_w32(0x40, PCE_PMAP3); ++ ++ /* RMON Counter Enable for all physical ports */ ++ for (i = 0; i < 7; i++) ++ ltq_switch_w32(0x1, BM_PCFG(i)); ++ ++ /* disable auto polling */ ++ ltq_mdio_w32(0x0, MDIO_CLK_CFG0); ++ ++ /* enable port statistic counters */ ++ for (i = 0; i < 7; i++) ++ ltq_switch_w32(0x1, BM_PCFGx(i)); ++ ++ /* set IPG to 12 */ ++ ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG); ++ ++#ifdef SW_ROUTING ++ /* enable status header, enable CRC */ ++ ltq_pmac_w32_mask(0, ++ PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, ++ PMAC_HD_CTL); ++#else ++ /* disable status header, enable CRC */ ++ ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, ++ PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, ++ PMAC_HD_CTL); ++#endif ++ ++ /* enable port fetch/store dma & VLAN Modification */ ++ for (i = 0; i < 7; i++ ) { ++ ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i)); ++ ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i)); ++ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0)); ++ } ++ ++ /* enable special tag insertion on cpu port */ ++ ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6)); ++ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0)); ++ ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2)); ++ ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG); ++ xrx200sw_write_x(1, XRX200_BM_QUEUE_GCTRL_GL_MOD, 0); ++ ++ for (i = 0; i < XRX200_MAX_VLAN; i++) ++ hw->vlan_vid[i] = i; ++} ++ ++static void xrx200_hw_cleanup(struct xrx200_hw *hw) ++{ ++ int i; ++ ++ /* disable the switch */ ++ ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB); ++ ++ /* free the channels and IRQs */ ++ for (i = 0; i < 2; i++) { ++ ltq_dma_free(&hw->chan[i].dma); ++ if (hw->chan[i].dma.irq) ++ free_irq(hw->chan[i].dma.irq, hw); ++ } ++ ++ /* free the allocated RX ring */ ++ for (i = 0; i < LTQ_DESC_NUM; i++) ++ dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]); ++ ++ /* clear the mdio bus */ ++ mdiobus_unregister(hw->mii_bus); ++ mdiobus_free(hw->mii_bus); ++ ++ /* release the clock */ ++ clk_disable(hw->clk); ++ clk_put(hw->clk); ++} ++ ++static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np) ++{ ++ hw->mii_bus = mdiobus_alloc(); ++ if (!hw->mii_bus) ++ return -ENOMEM; ++ ++ hw->mii_bus->read = xrx200_mdio_rd; ++ hw->mii_bus->write = xrx200_mdio_wr; ++ hw->mii_bus->name = "lantiq,xrx200-mdio"; ++ snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); ++ ++ if (of_mdiobus_register(hw->mii_bus, np)) { ++ mdiobus_free(hw->mii_bus); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port) ++{ ++ const __be32 *addr, *id = of_get_property(port, "reg", NULL); ++ struct xrx200_port *p = &priv->port[priv->num_port]; ++ ++ if (!id) ++ return; ++ ++ memset(p, 0, sizeof(struct xrx200_port)); ++ p->phy_node = of_parse_phandle(port, "phy-handle", 0); ++ addr = of_get_property(p->phy_node, "reg", NULL); ++ if (!addr) ++ return; ++ ++ p->num = *id; ++ p->phy_addr = *addr; ++ p->phy_if = of_get_phy_mode(port); ++ if (p->phy_addr > 0x10) ++ p->flags = XRX200_PORT_TYPE_MAC; ++ else ++ p->flags = XRX200_PORT_TYPE_PHY; ++ priv->num_port++; ++ ++ p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags); ++ if (gpio_is_valid(p->gpio)) ++ if (!gpio_request(p->gpio, "phy-reset")) { ++ gpio_direction_output(p->gpio, ++ (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0)); ++ udelay(100); ++ gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); ++ } ++ /* is this port a wan port ? */ ++ if (priv->wan) ++ priv->hw->wan_map |= BIT(p->num); ++ ++ priv->port_map |= BIT(p->num); ++ ++ /* store the port id in the hw struct so we can map ports -> devices */ ++ priv->hw->port_map[p->num] = priv->hw->num_devs; ++ ++ /* store the phy addr in the hw struct so we can map ports -> phys */ ++ priv->hw->phy_addr[p->num] = p->phy_addr; ++} ++ ++static const struct net_device_ops xrx200_netdev_ops = { ++ .ndo_init = xrx200_init, ++ .ndo_open = xrx200_open, ++ .ndo_stop = xrx200_close, ++ .ndo_start_xmit = xrx200_start_xmit, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_get_stats = xrx200_get_stats, ++ .ndo_tx_timeout = xrx200_tx_timeout, ++}; ++ ++static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface, struct device *dev) ++{ ++ struct xrx200_priv *priv; ++ struct device_node *port; ++ const __be32 *wan; ++ const u8 *mac; ++ ++ /* alloc the network device */ ++ hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv)); ++ if (!hw->devs[hw->num_devs]) ++ return; ++ ++ /* setup the network device */ ++ strcpy(hw->devs[hw->num_devs]->name, "eth%d"); ++ hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops; ++ hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT; ++ hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM; ++ SET_NETDEV_DEV(hw->devs[hw->num_devs], dev); ++ ++ /* setup our private data */ ++ priv = netdev_priv(hw->devs[hw->num_devs]); ++ priv->hw = hw; ++ priv->id = hw->num_devs; ++ ++ mac = of_get_mac_address(iface); ++ if (!IS_ERR(mac)) ++ memcpy(priv->mac, mac, ETH_ALEN); ++ ++ /* is this the wan interface ? */ ++ wan = of_get_property(iface, "lantiq,wan", NULL); ++ if (wan && (*wan == 1)) ++ priv->wan = 1; ++ ++ /* should the switch be enabled on this interface ? */ ++ if (of_find_property(iface, "lantiq,switch", NULL)) ++ priv->sw = 1; ++ ++ /* load the ports that are part of the interface */ ++ for_each_child_of_node(iface, port) ++ if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port")) ++ xrx200_of_port(priv, port); ++ ++ /* register the actual device */ ++ if (!register_netdev(hw->devs[hw->num_devs])) ++ hw->num_devs++; ++} ++ ++static struct xrx200_hw xrx200_hw; ++ ++static int xrx200_probe(struct platform_device *pdev) ++{ ++ struct resource *res[4]; ++ struct device_node *mdio_np, *iface_np, *phy_np; ++ struct of_phandle_iterator it; ++ int err; ++ int i; ++ ++ /* load the memory ranges */ ++ for (i = 0; i < 4; i++) { ++ res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ if (!res[i]) { ++ dev_err(&pdev->dev, "failed to get resources\n"); ++ return -ENOENT; ++ } ++ } ++ xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]); ++ xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]); ++ xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]); ++ xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]); ++ if (!xrx200_switch_membase || !xrx200_mdio_membase || ++ !xrx200_mii_membase || !xrx200_pmac_membase) { ++ dev_err(&pdev->dev, "failed to request and remap io ranges \n"); ++ return -ENOMEM; ++ } ++ ++ of_for_each_phandle(&it, err, pdev->dev.of_node, "lantiq,phys", NULL, 0) { ++ phy_np = it.node; ++ if (phy_np) { ++ struct platform_device *phy = of_find_device_by_node(phy_np); ++ ++ of_node_put(phy_np); ++ if (!platform_get_drvdata(phy)) ++ return -EPROBE_DEFER; ++ } ++ } ++ ++ /* get the clock */ ++ xrx200_hw.clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(xrx200_hw.clk)) { ++ dev_err(&pdev->dev, "failed to get clock\n"); ++ return PTR_ERR(xrx200_hw.clk); ++ } ++ ++ /* bring up the dma engine and IP core */ ++ xrx200_dma_init(&pdev->dev, &xrx200_hw); ++ xrx200_hw_init(&xrx200_hw); ++ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]); ++ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]); ++ ++ /* bring up the mdio bus */ ++ mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL, ++ "lantiq,xrx200-mdio"); ++ if (mdio_np) ++ if (xrx200_of_mdio(&xrx200_hw, mdio_np)) ++ dev_err(&pdev->dev, "mdio probe failed\n"); ++ ++ /* load the interfaces */ ++ for_each_child_of_node(pdev->dev.of_node, iface_np) ++ if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) { ++ if (xrx200_hw.num_devs < XRX200_MAX_DEV) ++ xrx200_of_iface(&xrx200_hw, iface_np, &pdev->dev); ++ else ++ dev_err(&pdev->dev, ++ "only %d interfaces allowed\n", ++ XRX200_MAX_DEV); ++ } ++ ++ if (!xrx200_hw.num_devs) { ++ xrx200_hw_cleanup(&xrx200_hw); ++ dev_err(&pdev->dev, "failed to load interfaces\n"); ++ return -ENOENT; ++ } ++ ++ xrx200sw_init(&xrx200_hw); ++ ++ /* set wan port mask */ ++ ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN); ++ ++ for (i = 0; i < xrx200_hw.num_devs; i++) { ++ xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i]; ++ xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i]; ++ xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i]; ++ } ++ ++ /* setup NAPI */ ++ init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev); ++ netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev, ++ &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32); ++ ++ platform_set_drvdata(pdev, &xrx200_hw); ++ ++ return 0; ++} ++ ++static int xrx200_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct xrx200_priv *priv; ++ ++ if (!dev) ++ return 0; ++ ++ priv = netdev_priv(dev); ++ ++ /* free stack related instances */ ++ netif_stop_queue(dev); ++ netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi); ++ ++ /* shut down hardware */ ++ xrx200_hw_cleanup(&xrx200_hw); ++ ++ /* remove the actual device */ ++ unregister_netdev(dev); ++ free_netdev(dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id xrx200_match[] = { ++ { .compatible = "lantiq,xrx200-net" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, xrx200_match); ++ ++static struct platform_driver xrx200_driver = { ++ .probe = xrx200_probe, ++ .remove = xrx200_remove, ++ .driver = { ++ .name = "lantiq,xrx200-net", ++ .of_match_table = xrx200_match, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(xrx200_driver); ++ ++MODULE_AUTHOR("John Crispin "); ++MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_xrx200_legacy.h +@@ -0,0 +1,1328 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2013 Antonios Vamporakis ++ * ++ * VR9 switch registers extracted from 310TUJ0 switch api ++ * WARNING mult values of 0x00 may not be correct ++ * ++ */ ++ ++enum { ++// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */ ++// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */ ++// XRX200_ETHSW_SWRES_R0, /* Register Configuration */ ++// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */ ++// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */ ++// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */ ++// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */ ++// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */ ++// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */ ++// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */ ++// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */ ++// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */ ++// XRX200_ETHSW_DBG_MODE, /* Debug Mode */ ++// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */ ++// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */ ++// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */ ++// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */ ++// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */ ++// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */ ++// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */ ++// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */ ++// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */ ++// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */ ++// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */ ++// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */ ++// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */ ++// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */ ++// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */ ++// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */ ++// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */ ++// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */ ++// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */ ++// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */ ++// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */ ++// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */ ++// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */ ++// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */ ++// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */ ++// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */ ++// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */ ++// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */ ++// XRX200_ETHSW_CAP_6_APPL, /* Application table size */ ++// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */ ++// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */ ++// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */ ++// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */ ++// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */ ++// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */ ++// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */ ++// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */ ++// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */ ++// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */ ++// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */ ++// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */ ++// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */ ++// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */ ++// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */ ++// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */ ++// XRX200_ETHSW_IER, /* Interrupt Enable Register */ ++// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */ ++// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */ ++// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */ ++// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */ ++// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */ ++// XRX200_ETHSW_ISR, /* Interrupt Status Register */ ++// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */ ++// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */ ++// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */ ++// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */ ++// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */ ++// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */ ++// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */ ++// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */ ++// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */ ++// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */ ++// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */ ++// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */ ++// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */ ++// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */ ++// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */ ++// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */ ++// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */ ++// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */ ++// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */ ++// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */ ++// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */ ++// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */ ++// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */ ++// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */ ++// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */ ++// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */ ++// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */ ++// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */ ++// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */ ++// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */ ++// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */ ++// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */ ++// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */ ++// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */ ++// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */ ++// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */ ++// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */ ++// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */ ++// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */ ++// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */ ++// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */ ++// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */ ++// XRX200_BM_RAM_ADDR, /* RAM Address Register */ ++// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */ ++// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */ ++// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */ ++// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ ++// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */ ++// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */ ++// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */ ++// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */ ++// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */ ++// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */ ++// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */ ++// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */ ++// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */ ++// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */ ++// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */ ++// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */ ++// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */ ++// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */ ++// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */ ++// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */ ++// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */ ++// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */ ++// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */ ++// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */ ++ XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */ ++// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */ ++// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */ ++// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */ ++// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */ ++// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */ ++// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */ ++// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */ ++// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */ ++// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */ ++// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */ ++// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */ ++// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */ ++// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */ ++// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */ ++// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */ ++// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */ ++// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */ ++// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ ++// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */ ++// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ ++// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */ ++// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */ ++// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */ ++// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */ ++// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */ ++// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */ ++// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */ ++// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */ ++// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */ ++// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */ ++// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */ ++// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */ ++// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */ ++// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */ ++// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */ ++// XRX200_BM_CISEL_PORT, /* Port Number */ ++// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */ ++// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */ ++// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */ ++// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */ ++// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */ ++// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */ ++// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */ ++// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */ ++// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */ ++// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */ ++// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */ ++// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */ ++// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */ ++// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */ ++// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */ ++// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */ ++// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */ ++// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */ ++// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */ ++// XRX200_RS_CBS_CBS, /* Committed Burst Size */ ++// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */ ++// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */ ++// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */ ++// XRX200_RS_CIR_EXP_EXP, /* Exponent */ ++// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */ ++// XRX200_RS_CIR_MANT_MANT, /* Mantissa */ ++ XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */ ++// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */ ++// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */ ++// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */ ++// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */ ++// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */ ++// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */ ++// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */ ++ XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */ ++// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */ ++// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */ ++ XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */ ++// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */ ++// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */ ++// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */ ++// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */ ++// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */ ++// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */ ++ XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */ ++// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */ ++ XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */ ++ XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */ ++ XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */ ++ XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */ ++ XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ ++ XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */ ++// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */ ++// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */ ++// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */ ++// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */ ++// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */ ++// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */ ++// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */ ++// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */ ++// XRX200_PCE_PMAP_1, /* Port Map Register 1 */ ++// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */ ++// XRX200_PCE_PMAP_2, /* Port Map Register 2 */ ++// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */ ++// XRX200_PCE_PMAP_3, /* Port Map Register 3 */ ++// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */ ++// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */ ++// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */ ++ XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */ ++// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */ ++// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */ ++// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */ ++// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */ ++// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */ ++// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */ ++// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */ ++// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */ ++// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */ ++// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */ ++// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */ ++// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */ ++// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */ ++// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */ ++// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */ ++// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */ ++// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */ ++// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */ ++// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */ ++// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */ ++// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */ ++// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */ ++// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */ ++// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */ ++// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */ ++// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */ ++// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */ ++// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */ ++// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */ ++// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */ ++// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */ ++// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */ ++// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */ ++// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */ ++// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */ ++// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */ ++// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */ ++// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */ ++// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */ ++// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */ ++// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */ ++// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */ ++// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */ ++// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */ ++// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */ ++// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */ ++// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */ ++// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */ ++// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */ ++// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */ ++// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */ ++// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */ ++// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */ ++// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */ ++// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */ ++// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */ ++// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */ ++// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */ ++// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */ ++// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */ ++// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */ ++// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */ ++// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */ ++// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */ ++// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */ ++// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */ ++// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */ ++// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */ ++// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */ ++// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */ ++// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */ ++// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */ ++// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */ ++// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */ ++ XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */ ++// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */ ++// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */ ++// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */ ++// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */ ++// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */ ++// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */ ++// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */ ++// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */ ++// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */ ++// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */ ++// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */ ++// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */ ++// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */ ++// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */ ++// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */ ++// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */ ++// XRX200_WOL_CTRL_PORT, /* WoL Enable */ ++// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */ ++ XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */ ++ XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */ ++ XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */ ++ XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */ ++ XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */ ++// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */ ++ XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */ ++// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */ ++// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */ ++// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */ ++// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */ ++// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */ ++// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */ ++// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */ ++// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */ ++// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */ ++// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */ ++// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */ ++// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */ ++// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */ ++// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */ ++// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */ ++// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */ ++// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */ ++// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */ ++// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */ ++// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */ ++// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */ ++// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */ ++// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */ ++// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */ ++// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */ ++// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */ ++// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */ ++// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */ ++// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */ ++// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */ ++// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */ ++// XRX200_MAC_TEST, /* MAC Test Register */ ++// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */ ++// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */ ++// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */ ++// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */ ++// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */ ++// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */ ++// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */ ++// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */ ++// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */ ++// XRX200_MAC_FLEN, /* MAC Frame Length Register */ ++// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */ ++// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */ ++// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */ ++// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */ ++// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */ ++// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */ ++// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */ ++// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */ ++// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */ ++// XRX200_MAC_PSTAT, /* MAC Port Status Register */ ++// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */ ++ XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */ ++ XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */ ++ XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */ ++// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */ ++// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */ ++ XRX200_MAC_PSTAT_LSTAT, /* Link Status */ ++// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */ ++// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */ ++// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */ ++// XRX200_MAC_PISR, /* MAC Interrupt Status Register */ ++// XRX200_MAC_PISR_PACT, /* PHY Active Status */ ++// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */ ++// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */ ++// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */ ++// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */ ++// XRX200_MAC_PISR_JAM, /* Jam Status Detected */ ++// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */ ++// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */ ++// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */ ++// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */ ++// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */ ++// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */ ++// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */ ++// XRX200_MAC_PIER_PACT, /* PHY Active Status */ ++// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */ ++// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */ ++// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */ ++// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */ ++// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */ ++// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */ ++// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */ ++// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */ ++// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */ ++// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */ ++// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */ ++// XRX200_MAC_CTRL_0, /* MAC Control Register0 */ ++// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */ ++// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */ ++// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */ ++// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */ ++ XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */ ++// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */ ++// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */ ++// XRX200_MAC_CTRL_1, /* MAC Control Register1 */ ++// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */ ++// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */ ++// XRX200_MAC_CTRL_2, /* MAC Control Register2 */ ++// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */ ++// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */ ++// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */ ++// XRX200_MAC_CTRL_3, /* MAC Control Register3 */ ++// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */ ++// XRX200_MAC_CTRL_4, /* MAC Control Register4 */ ++// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */ ++// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */ ++// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */ ++// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */ ++// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */ ++// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */ ++// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */ ++// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */ ++// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */ ++// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */ ++// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */ ++// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */ ++// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */ ++// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */ ++// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */ ++// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */ ++// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */ ++// XRX200_MAC_TESTEN, /* MAC Test Enable Register */ ++// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */ ++// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */ ++// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */ ++// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */ ++// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */ ++// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */ ++// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */ ++// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */ ++// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */ ++// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */ ++// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */ ++// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */ ++// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */ ++// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */ ++// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */ ++// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */ ++// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */ ++// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */ ++// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */ ++// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */ ++// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */ ++// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */ ++// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */ ++// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */ ++// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */ ++// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */ ++// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */ ++// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */ ++// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */ ++// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */ ++// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */ ++// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */ ++// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */ ++// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */ ++// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */ ++// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */ ++// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */ ++// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ ++// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */ ++// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ ++// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */ ++// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */ ++// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */ ++// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */ ++// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */ ++// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */ ++// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */ ++// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */ ++// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */ ++// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */ ++// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */ ++// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */ ++// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */ ++// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */ ++// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */ ++// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */ ++// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */ ++// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */ ++// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */ ++// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */ ++// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */ ++// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */ ++// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */ ++// XRX200_SDMA_IER_BFULL, /* Buffer Full */ ++// XRX200_SDMA_IER_FERR, /* Frame Error */ ++// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */ ++// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */ ++// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */ ++// XRX200_SDMA_ISR_BFULL, /* Buffer Full */ ++// XRX200_SDMA_ISR_FERR, /* Frame Error */ ++// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */ ++// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */ ++// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */ ++// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */ ++// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */ ++// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */ ++// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */ ++// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */ ++// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */ ++// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */ ++// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */ ++// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */ ++// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */ ++// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */ ++// XRX200_SDMA_PCTRL_PEN, /* Port Enable */ ++// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */ ++// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */ ++// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */ ++// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */ ++// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */ ++// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */ ++// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */ ++// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ ++// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */ ++// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ ++}; ++ ++ ++struct xrx200sw_reg { ++ int offset; ++ int shift; ++ int size; ++ int mult; ++} xrx200sw_reg[] = { ++// offeset shift size mult ++// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */ ++// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */ ++// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */ ++// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */ ++// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */ ++// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */ ++// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */ ++// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */ ++// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */ ++// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */ ++// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */ ++// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */ ++// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */ ++// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */ ++// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */ ++// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */ ++// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */ ++// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */ ++// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */ ++// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */ ++// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */ ++// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */ ++// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */ ++// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */ ++// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */ ++// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */ ++// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */ ++// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */ ++// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */ ++// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */ ++// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */ ++// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */ ++// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */ ++// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */ ++// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */ ++// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */ ++// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */ ++// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */ ++// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */ ++// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */ ++// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */ ++// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */ ++// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */ ++// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */ ++// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */ ++// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */ ++// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */ ++// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */ ++// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */ ++// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */ ++// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */ ++// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */ ++// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */ ++// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */ ++// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */ ++// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */ ++// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */ ++// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */ ++// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */ ++// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */ ++// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */ ++// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */ ++// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */ ++// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */ ++// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */ ++// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */ ++// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */ ++// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */ ++// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */ ++// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */ ++// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */ ++// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */ ++// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */ ++// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */ ++// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */ ++// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */ ++// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */ ++// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */ ++// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */ ++// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */ ++// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */ ++// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */ ++// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */ ++// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */ ++// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */ ++// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */ ++// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */ ++// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */ ++// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */ ++// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */ ++// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */ ++// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */ ++// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */ ++// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */ ++// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */ ++// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */ ++// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */ ++// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */ ++// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */ ++// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */ ++// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */ ++// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */ ++// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */ ++// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */ ++// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */ ++// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */ ++// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */ ++// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */ ++// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */ ++// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */ ++// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */ ++// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */ ++// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */ ++// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */ ++// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */ ++// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */ ++// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */ ++// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */ ++// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */ ++// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */ ++// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */ ++// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */ ++// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */ ++// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */ ++// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */ ++// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */ ++// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */ ++// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */ ++// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */ ++// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */ ++// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */ ++// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */ ++// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */ ++// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */ ++// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */ ++// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */ ++// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */ ++// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */ ++// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */ ++// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */ ++// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */ ++// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */ ++ {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */ ++// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */ ++// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */ ++// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */ ++// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */ ++// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */ ++// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */ ++// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */ ++// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */ ++// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */ ++// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */ ++// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */ ++// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */ ++// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */ ++// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */ ++// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */ ++// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */ ++// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */ ++// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */ ++// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */ ++// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */ ++// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */ ++// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */ ++// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */ ++// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ ++// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */ ++// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ ++// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */ ++// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */ ++// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */ ++// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */ ++// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */ ++// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */ ++// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */ ++// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */ ++// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */ ++// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */ ++// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */ ++// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */ ++// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */ ++// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */ ++// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */ ++// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */ ++// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */ ++// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */ ++// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */ ++// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */ ++// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */ ++// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */ ++// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */ ++// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */ ++// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */ ++// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */ ++// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */ ++// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */ ++// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */ ++// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */ ++// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */ ++// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */ ++// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */ ++// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */ ++// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */ ++// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */ ++// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */ ++// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */ ++// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */ ++// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */ ++// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */ ++// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */ ++ {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */ ++// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */ ++ {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */ ++// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */ ++ {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */ ++// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */ ++ {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */ ++// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */ ++ {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */ ++// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */ ++ {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */ ++// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */ ++ {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */ ++// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */ ++ {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */ ++// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */ ++ {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */ ++// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */ ++ {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */ ++// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */ ++ {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */ ++// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */ ++ {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */ ++// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */ ++ {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */ ++// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */ ++ {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */ ++// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */ ++// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */ ++ {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */ ++// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */ ++ {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */ ++ {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */ ++ {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */ ++ {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */ ++ {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */ ++ {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */ ++// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */ ++// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */ ++// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */ ++// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */ ++// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */ ++// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */ ++// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */ ++// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */ ++// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */ ++// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */ ++// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */ ++// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */ ++// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */ ++// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */ ++// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */ ++// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */ ++ {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */ ++// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */ ++// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */ ++// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */ ++// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */ ++// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */ ++// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */ ++// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */ ++// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */ ++// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */ ++// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */ ++// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */ ++// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */ ++// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */ ++// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */ ++// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */ ++// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */ ++// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */ ++// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */ ++// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */ ++// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */ ++// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */ ++// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */ ++// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */ ++// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */ ++// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */ ++// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */ ++// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */ ++// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */ ++// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */ ++// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */ ++// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */ ++// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */ ++// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */ ++// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */ ++// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */ ++// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */ ++// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */ ++// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */ ++// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */ ++// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */ ++// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */ ++// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */ ++// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */ ++// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */ ++// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */ ++// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */ ++// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */ ++// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */ ++// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */ ++// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */ ++// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */ ++// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */ ++// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */ ++// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */ ++// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */ ++// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */ ++// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */ ++// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */ ++// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */ ++// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */ ++// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */ ++// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */ ++// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */ ++// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */ ++// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */ ++// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */ ++// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */ ++// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */ ++// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */ ++// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */ ++// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */ ++// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */ ++// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */ ++// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */ ++// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */ ++// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */ ++// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */ ++// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */ ++// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */ ++// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */ ++// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */ ++// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */ ++// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */ ++// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */ ++// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */ ++// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */ ++// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */ ++// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */ ++// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */ ++// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */ ++// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */ ++// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */ ++// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */ ++// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */ ++// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */ ++// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */ ++// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */ ++// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */ ++// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */ ++// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */ ++// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */ ++// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */ ++// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */ ++// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */ ++// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */ ++// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */ ++// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */ ++// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */ ++// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */ ++// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */ ++// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */ ++// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */ ++// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */ ++// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */ ++// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */ ++// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */ ++ {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */ ++// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */ ++// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */ ++// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */ ++// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */ ++// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */ ++// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */ ++// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */ ++// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */ ++// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */ ++// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */ ++// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */ ++// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */ ++// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */ ++// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */ ++// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */ ++// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */ ++// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */ ++// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */ ++// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */ ++// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */ ++// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */ ++// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */ ++// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */ ++// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */ ++// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */ ++// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */ ++ {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */ ++ {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */ ++ {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */ ++ {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */ ++ {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */ ++// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */ ++ {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */ ++// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */ ++// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */ ++// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */ ++// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */ ++// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */ ++// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */ ++// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */ ++// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */ ++// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */ ++// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */ ++// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */ ++// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */ ++// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */ ++// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */ ++// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */ ++// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */ ++// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */ ++// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */ ++// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */ ++// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */ ++// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */ ++// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */ ++// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */ ++// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */ ++// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */ ++// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */ ++// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */ ++// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */ ++// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */ ++// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */ ++// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */ ++// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */ ++// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */ ++// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */ ++// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */ ++// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */ ++// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */ ++// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */ ++// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */ ++// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */ ++// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */ ++// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */ ++// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */ ++// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */ ++// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */ ++// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */ ++// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */ ++// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */ ++// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */ ++// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */ ++// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */ ++// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */ ++// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */ ++ {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */ ++ {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */ ++ {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */ ++// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */ ++// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */ ++// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */ ++// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */ ++ {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */ ++// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */ ++// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */ ++// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */ ++// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */ ++// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */ ++// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */ ++// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */ ++// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */ ++// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */ ++// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */ ++// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */ ++// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */ ++// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */ ++// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */ ++// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */ ++// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */ ++// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */ ++// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */ ++// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */ ++// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */ ++// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */ ++// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */ ++// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */ ++// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */ ++// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */ ++// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */ ++// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */ ++// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */ ++// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */ ++// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */ ++// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */ ++// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */ ++// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */ ++// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */ ++// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */ ++// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */ ++// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */ ++// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */ ++// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */ ++// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */ ++// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */ ++ {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */ ++// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */ ++// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */ ++// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */ ++// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */ ++// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */ ++// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */ ++// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */ ++// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */ ++// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */ ++// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */ ++// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */ ++// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */ ++// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */ ++// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */ ++// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */ ++// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */ ++// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */ ++// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */ ++// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */ ++// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */ ++// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */ ++// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */ ++// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */ ++// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */ ++// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */ ++// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */ ++// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */ ++// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */ ++// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */ ++// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */ ++// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */ ++// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */ ++// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */ ++// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */ ++// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */ ++// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */ ++// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */ ++// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */ ++// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */ ++// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */ ++// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */ ++// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */ ++// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */ ++// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */ ++// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */ ++// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */ ++// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */ ++// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */ ++// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */ ++// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */ ++// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */ ++// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */ ++// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */ ++// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */ ++// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */ ++// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */ ++// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */ ++// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */ ++// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */ ++// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */ ++// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */ ++// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */ ++// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */ ++// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */ ++// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */ ++// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */ ++// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */ ++// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */ ++// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */ ++// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */ ++// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */ ++// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */ ++// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */ ++// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */ ++// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */ ++// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */ ++// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */ ++// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */ ++// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */ ++// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */ ++// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */ ++// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */ ++// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */ ++// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */ ++// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */ ++// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */ ++// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */ ++// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */ ++// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */ ++// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */ ++// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */ ++// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */ ++// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */ ++// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */ ++// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */ ++// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */ ++// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */ ++// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */ ++// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */ ++// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */ ++// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */ ++// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */ ++// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */ ++// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */ ++// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */ ++// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */ ++// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */ ++// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */ ++// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */ ++// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */ ++// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */ ++// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */ ++// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */ ++// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */ ++// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */ ++// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */ ++// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */ ++// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */ ++// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */ ++// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */ ++// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */ ++// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */ ++// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */ ++// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */ ++// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */ ++// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */ ++// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */ ++// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */ ++}; ++ ++ diff --git a/target/linux/lantiq/patches-5.4/0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch b/target/linux/lantiq/patches-5.4/0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch new file mode 100644 index 0000000000..8fd29161fe --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch @@ -0,0 +1,352 @@ +From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001 +From: Mathias Kresin +Date: Sun, 7 Jul 2019 21:48:56 +0200 +Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader + +Upstream, the GPHY Firmware loader has been merged into the DSA switch +driver. But we don't use the driver yet, so bring it back. + +Signed-off-by: Mathias Kresin +--- + .../bindings/mips/lantiq/rcu-gphy.txt | 36 +++ + .../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++ + arch/mips/configs/xway_defconfig | 1 + + arch/mips/lantiq/Kconfig | 4 + + drivers/soc/lantiq/Makefile | 1 + + drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++ + 6 files changed, 284 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt + create mode 100644 drivers/soc/lantiq/gphy.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt +@@ -0,0 +1,37 @@ ++Lantiq XWAY SoC GPHY binding ++============================ ++ ++This binding describes a software-defined ethernet PHY, provided by the RCU ++module on newer Lantiq XWAY SoCs (xRX200 and newer). ++ ++------------------------------------------------------------------------------- ++Required properties: ++- compatible : Should be one of ++ "lantiq,xrx200-gphy" ++ "lantiq,xrx200a1x-gphy" ++ "lantiq,xrx200a2x-gphy" ++ "lantiq,xrx300-gphy" ++ "lantiq,xrx330-gphy" ++- reg : Addrress of the GPHY FW load address register ++- resets : Must reference the RCU GPHY reset bit ++- reset-names : One entry, value must be "gphy" or optional "gphy2" ++- clocks : A reference to the (PMU) GPHY clock gate ++ ++Optional properties: ++- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in ++ ++ ++ ++------------------------------------------------------------------------------- ++Example for the GPHys on the xRX200 SoCs: ++ ++#include ++ gphy0: gphy@20 { ++ compatible = "lantiq,xrx200a2x-gphy"; ++ reg = <0x20 0x4>; ++ ++ resets = <&reset0 31 30>, <&reset1 7 7>; ++ reset-names = "gphy", "gphy2"; ++ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>; ++ lantiq,gphy-mode = ; ++ }; +--- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt ++++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt +@@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200 + ranges = <0x0 0x203000 0x100>; + big-endian; + ++ gphy0: gphy@20 { ++ compatible = "lantiq,xrx200a2x-gphy"; ++ reg = <0x20 0x4>; ++ ++ resets = <&reset0 31 30>, <&reset1 7 7>; ++ reset-names = "gphy", "gphy2"; ++ lantiq,gphy-mode = ; ++ }; ++ ++ gphy1: gphy@68 { ++ compatible = "lantiq,xrx200a2x-gphy"; ++ reg = <0x68 0x4>; ++ ++ resets = <&reset0 29 28>, <&reset1 6 6>; ++ reset-names = "gphy", "gphy2"; ++ lantiq,gphy-mode = ; ++ }; ++ + reset0: reset-controller@10 { + compatible = "lantiq,xrx200-reset"; + reg = <0x10 4>, <0x14 4>; +--- a/arch/mips/configs/xway_defconfig ++++ b/arch/mips/configs/xway_defconfig +@@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y + # CONFIG_COMPAT_BRK is not set + CONFIG_LANTIQ=y + CONFIG_PCI_LANTIQ=y ++CONFIG_XRX200_PHY_FW=y + CONFIG_CPU_MIPS32_R2=y + CONFIG_MIPS_VPE_LOADER=y + CONFIG_NR_CPUS=2 +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI + depends on PCIE_LANTIQ && PCI_MSI + default y + ++config XRX200_PHY_FW ++ bool "XRX200 PHY firmware loader" ++ depends on SOC_XWAY ++ + endif +--- a/drivers/soc/lantiq/Makefile ++++ b/drivers/soc/lantiq/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-y += fpi-bus.o ++obj-$(CONFIG_XRX200_PHY_FW) += gphy.o +--- /dev/null ++++ b/drivers/soc/lantiq/gphy.c +@@ -0,0 +1,235 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2012 John Crispin ++ * Copyright (C) 2016 Martin Blumenstingl ++ * Copyright (C) 2017 Hauke Mehrtens ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define XRX200_GPHY_FW_ALIGN (16 * 1024) ++ ++struct xway_gphy_priv { ++ struct clk *gphy_clk_gate; ++ struct reset_control *gphy_reset; ++ struct reset_control *gphy_reset2; ++ void __iomem *membase; ++ char *fw_name; ++}; ++ ++struct xway_gphy_match_data { ++ char *fe_firmware_name; ++ char *ge_firmware_name; ++}; ++ ++static const struct xway_gphy_match_data xrx200a1x_gphy_data = { ++ .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", ++ .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", ++}; ++ ++static const struct xway_gphy_match_data xrx200a2x_gphy_data = { ++ .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", ++ .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", ++}; ++ ++static const struct xway_gphy_match_data xrx300_gphy_data = { ++ .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", ++ .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", ++}; ++ ++static const struct of_device_id xway_gphy_match[] = { ++ { .compatible = "lantiq,xrx200-gphy", .data = NULL }, ++ { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data }, ++ { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data }, ++ { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data }, ++ { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, xway_gphy_match); ++ ++static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv, ++ dma_addr_t *dev_addr) ++{ ++ const struct firmware *fw; ++ void *fw_addr; ++ dma_addr_t dma_addr; ++ size_t size; ++ int ret; ++ ++ ret = request_firmware(&fw, priv->fw_name, dev); ++ if (ret) { ++ dev_err(dev, "failed to load firmware: %s, error: %i\n", ++ priv->fw_name, ret); ++ return ret; ++ } ++ ++ /* ++ * GPHY cores need the firmware code in a persistent and contiguous ++ * memory area with a 16 kB boundary aligned start address. ++ */ ++ size = fw->size + XRX200_GPHY_FW_ALIGN; ++ ++ fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); ++ if (fw_addr) { ++ fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); ++ *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); ++ memcpy(fw_addr, fw->data, fw->size); ++ } else { ++ dev_err(dev, "failed to alloc firmware memory\n"); ++ ret = -ENOMEM; ++ } ++ ++ release_firmware(fw); ++ ++ return ret; ++} ++ ++static int xway_gphy_of_probe(struct platform_device *pdev, ++ struct xway_gphy_priv *priv) ++{ ++ struct device *dev = &pdev->dev; ++ const struct xway_gphy_match_data *gphy_fw_name_cfg; ++ u32 gphy_mode; ++ int ret; ++ struct resource *res_gphy; ++ ++ gphy_fw_name_cfg = of_device_get_match_data(dev); ++ ++ if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy")) ++ switch (ltq_soc_type()) { ++ case SOC_TYPE_VR9: ++ gphy_fw_name_cfg = &xrx200a1x_gphy_data; ++ break; ++ case SOC_TYPE_VR9_2: ++ gphy_fw_name_cfg = &xrx200a2x_gphy_data; ++ break; ++ } ++ ++ priv->gphy_clk_gate = devm_clk_get(dev, NULL); ++ if (IS_ERR(priv->gphy_clk_gate)) { ++ dev_err(dev, "Failed to lookup gate clock\n"); ++ return PTR_ERR(priv->gphy_clk_gate); ++ } ++ ++ res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ priv->membase = devm_ioremap_resource(dev, res_gphy); ++ if (IS_ERR(priv->membase)) ++ return PTR_ERR(priv->membase); ++ ++ priv->gphy_reset = devm_reset_control_get(dev, "gphy"); ++ if (IS_ERR(priv->gphy_reset)) { ++ if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER) ++ dev_err(dev, "Failed to lookup gphy reset\n"); ++ return PTR_ERR(priv->gphy_reset); ++ } ++ ++ priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2"); ++ if (IS_ERR(priv->gphy_reset2)) ++ return PTR_ERR(priv->gphy_reset2); ++ ++ ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode); ++ /* Default to GE mode */ ++ if (ret) ++ gphy_mode = GPHY_MODE_GE; ++ ++ switch (gphy_mode) { ++ case GPHY_MODE_FE: ++ priv->fw_name = gphy_fw_name_cfg->fe_firmware_name; ++ break; ++ case GPHY_MODE_GE: ++ priv->fw_name = gphy_fw_name_cfg->ge_firmware_name; ++ break; ++ default: ++ dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int xway_gphy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct xway_gphy_priv *priv; ++ dma_addr_t fw_addr = 0; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ ret = xway_gphy_of_probe(pdev, priv); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(priv->gphy_clk_gate); ++ if (ret) ++ return ret; ++ ++ ret = xway_gphy_load(dev, priv, &fw_addr); ++ if (ret) { ++ clk_disable_unprepare(priv->gphy_clk_gate); ++ return ret; ++ } ++ ++ reset_control_assert(priv->gphy_reset); ++ reset_control_assert(priv->gphy_reset2); ++ ++ iowrite32be(fw_addr, priv->membase); ++ ++ reset_control_deassert(priv->gphy_reset); ++ reset_control_deassert(priv->gphy_reset2); ++ ++ platform_set_drvdata(pdev, priv); ++ ++ return ret; ++} ++ ++static int xway_gphy_remove(struct platform_device *pdev) ++{ ++ struct xway_gphy_priv *priv = platform_get_drvdata(pdev); ++ ++ iowrite32be(0, priv->membase); ++ ++ clk_disable_unprepare(priv->gphy_clk_gate); ++ ++ return 0; ++} ++ ++static struct platform_driver xway_gphy_driver = { ++ .probe = xway_gphy_probe, ++ .remove = xway_gphy_remove, ++ .driver = { ++ .name = "xway-rcu-gphy", ++ .of_match_table = xway_gphy_match, ++ }, ++}; ++ ++module_platform_driver(xway_gphy_driver); ++ ++MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); ++MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); ++MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); ++MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); ++MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); ++MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); ++MODULE_AUTHOR("Martin Blumenstingl "); ++MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/patches-5.4/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-5.4/0028-NET-lantiq-various-etop-fixes.patch new file mode 100644 index 0000000000..094496a16d --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0028-NET-lantiq-various-etop-fixes.patch @@ -0,0 +1,866 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 22:45:34 +0200 +Subject: [PATCH 28/36] NET: lantiq: various etop fixes + +Signed-off-by: John Crispin +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* + * +- * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011-12 John Crispin + */ + + #include +@@ -20,11 +20,16 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include ++#include ++#include ++#include ++#include + + #include + +@@ -32,7 +37,7 @@ + #include + #include + +-#define LTQ_ETOP_MDIO 0x11804 ++#define LTQ_ETOP_MDIO_ACC 0x11804 + #define MDIO_REQUEST 0x80000000 + #define MDIO_READ 0x40000000 + #define MDIO_ADDR_MASK 0x1f +@@ -41,44 +46,91 @@ + #define MDIO_REG_OFFSET 0x10 + #define MDIO_VAL_MASK 0xffff + +-#define PPE32_CGEN 0x800 +-#define LQ_PPE32_ENET_MAC_CFG 0x1840 ++#define LTQ_ETOP_MDIO_CFG 0x11800 ++#define MDIO_CFG_MASK 0x6 ++ ++#define LTQ_ETOP_CFG 0x11808 ++#define LTQ_ETOP_IGPLEN 0x11820 ++#define LTQ_ETOP_MAC_CFG 0x11840 + + #define LTQ_ETOP_ENETS0 0x11850 + #define LTQ_ETOP_MAC_DA0 0x1186C + #define LTQ_ETOP_MAC_DA1 0x11870 +-#define LTQ_ETOP_CFG 0x16020 +-#define LTQ_ETOP_IGPLEN 0x16080 ++ ++#define MAC_CFG_MASK 0xfff ++#define MAC_CFG_CGEN (1 << 11) ++#define MAC_CFG_DUPLEX (1 << 2) ++#define MAC_CFG_SPEED (1 << 1) ++#define MAC_CFG_LINK (1 << 0) + + #define MAX_DMA_CHAN 0x8 + #define MAX_DMA_CRC_LEN 0x4 + #define MAX_DMA_DATA_LEN 0x600 + + #define ETOP_FTCU BIT(28) +-#define ETOP_MII_MASK 0xf +-#define ETOP_MII_NORMAL 0xd +-#define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 +-#define ETOP_CGEN 0x800 ++#define ETOP_CFG_MII0 0x01 + +-/* use 2 static channels for TX/RX */ +-#define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 +-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) ++#define ETOP_CFG_MASK 0xfff ++#define ETOP_CFG_FEN0 (1 << 8) ++#define ETOP_CFG_SEN0 (1 << 6) ++#define ETOP_CFG_OFF1 (1 << 3) ++#define ETOP_CFG_REMII0 (1 << 1) ++#define ETOP_CFG_OFF0 (1 << 0) ++ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++#define LTQ_GBIT_RGMII_CTL 0x78 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ ++#define MDC_CLOCK_MASK 0xff000000 ++#define MDC_CLOCK_OFFSET 24 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 + ++#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ + #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) + #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +-#define DRV_VERSION "1.0" ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ ++#define DRV_VERSION "1.2" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { +- int idx; + int tx_free; ++ int irq; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; +@@ -88,23 +140,36 @@ struct ltq_etop_chan { + struct ltq_etop_priv { + struct net_device *netdev; + struct platform_device *pdev; +- struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + +- struct ltq_etop_chan ch[MAX_DMA_CHAN]; +- int tx_free[MAX_DMA_CHAN >> 1]; ++ struct ltq_etop_chan txch; ++ struct ltq_etop_chan rxch; + +- spinlock_t lock; ++ int tx_irq; ++ int rx_irq; ++ ++ unsigned char mac[6]; ++ int mii_mode; ++ ++ spinlock_t lock; ++ ++ struct clk *clk_ppe; ++ struct clk *clk_switch; ++ struct clk *clk_ephy; ++ struct clk *clk_ephycgu; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + +- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); ++ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, +@@ -139,8 +204,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); ++ skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); ++ ch->netdev->stats.rx_packets++; ++ ch->netdev->stats.rx_bytes += len; + } + + static int +@@ -148,7 +216,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + { + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); ++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + int work_done = 0; ++ unsigned long flags; + + while (work_done < budget) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +@@ -160,7 +230,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + } + if (work_done < budget) { + napi_complete_done(&ch->napi, work_done); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + } + return work_done; + } +@@ -172,12 +244,14 @@ ltq_etop_poll_tx(struct napi_struct *nap + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = +- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); ++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ ch->netdev->stats.tx_packets++; ++ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, +@@ -190,7 +264,9 @@ ltq_etop_poll_tx(struct napi_struct *nap + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + return 1; + } + +@@ -198,9 +274,10 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; +- +- napi_schedule(&priv->ch[ch].napi); ++ if (irq == priv->txch.dma.irq) ++ napi_schedule(&priv->txch.napi); ++ else ++ napi_schedule(&priv->rxch.napi); + return IRQ_HANDLED; + } + +@@ -212,7 +289,7 @@ ltq_etop_free_channel(struct net_device + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); +- if (IS_RX(ch->idx)) { ++ if (ch == &priv->txch) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); +@@ -223,66 +300,135 @@ static void + ltq_etop_hw_exit(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; + +- ltq_pmu_disable(PMU_PPE); +- for (i = 0; i < MAX_DMA_CHAN; i++) +- if (IS_TX(i) || IS_RX(i)) +- ltq_etop_free_channel(dev, &priv->ch[i]); ++ clk_disable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) ++ clk_disable(priv->clk_switch); ++ ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_disable(priv->clk_ephy); ++ clk_disable(priv->clk_ephycgu); ++ } ++ ++ ltq_etop_free_channel(dev, &priv->txch); ++ ltq_etop_free_channel(dev, &priv->rxch); ++} ++ ++static void ++ltq_etop_gbit_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ ++ clk_enable(priv->clk_switch); ++ ++ /* enable gbit port0 on the SoC */ ++ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /* disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); ++ /* set mdc clock to 2.5 MHz */ ++ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, ++ LTQ_GBIT_RGMII_CTL); + } + + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ int mii_mode = priv->mii_mode; + +- ltq_pmu_enable(PMU_PPE); ++ clk_enable(priv->clk_ppe); + +- switch (priv->pldata->mii_mode) { ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ ltq_etop_gbit_init(dev); ++ /* force the etops link to the gbit to MII */ ++ mii_mode = PHY_INTERFACE_MODE_MII; ++ } ++ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); ++ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | ++ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); ++ ++ switch (mii_mode) { + case PHY_INTERFACE_MODE_RMII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_REVERSE, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_NORMAL, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + default: ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_enable(priv->clk_ephy); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ clk_enable(priv->clk_ephycgu); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", +- priv->pldata->mii_mode); ++ mii_mode); + return -ENOTSUPP; + } + +- /* enable crc generation */ +- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); ++ return 0; ++} ++ ++static int ++ltq_etop_dma_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ int tx = priv->tx_irq - LTQ_DMA_ETOP; ++ int rx = priv->rx_irq - LTQ_DMA_ETOP; ++ int err; + + ltq_dma_init_port(DMA_PORT_ETOP); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- ch->idx = ch->dma.nr = i; +- ch->dma.dev = &priv->pdev->dev; +- +- if (IS_TX(i)) { +- ltq_dma_alloc_tx(&ch->dma); +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); +- } else if (IS_RX(i)) { +- ltq_dma_alloc_rx(&ch->dma); +- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; +- ch->dma.desc++) +- if (ltq_etop_alloc_skb(ch)) +- return -ENOMEM; +- ch->dma.desc = 0; +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); ++ priv->txch.dma.nr = tx; ++ priv->txch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_tx(&priv->txch.dma); ++ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); ++ if (err) { ++ netdev_err(dev, "failed to allocate tx irq\n"); ++ goto err_out; ++ } ++ priv->txch.dma.irq = priv->tx_irq; ++ ++ priv->rxch.dma.nr = rx; ++ priv->rxch.dma.dev = &priv->pdev->dev; ++ ltq_dma_alloc_rx(&priv->rxch.dma); ++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; ++ priv->rxch.dma.desc++) { ++ if (ltq_etop_alloc_skb(&priv->rxch)) { ++ netdev_err(dev, "failed to allocate skbs\n"); ++ err = -ENOMEM; ++ goto err_out; + } +- ch->dma.irq = irq; + } +- return 0; ++ priv->rxch.dma.desc = 0; ++ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); ++ if (err) ++ netdev_err(dev, "failed to allocate rx irq\n"); ++ else ++ priv->rxch.dma.irq = priv->rx_irq; ++err_out: ++ return err; + } + + static void +@@ -301,6 +447,39 @@ static const struct ethtool_ops ltq_etop + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -308,9 +487,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); + return 0; + } + +@@ -321,12 +500,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; ++ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; + return val; + } + +@@ -342,7 +521,10 @@ ltq_etop_mdio_probe(struct net_device *d + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev; + +- phydev = phy_find_first(priv->mii_bus); ++ if (of_machine_is_compatible("lantiq,ase")) ++ phydev = mdiobus_get_phy(priv->mii_bus, 8); ++ else ++ phydev = mdiobus_get_phy(priv->mii_bus, 0); + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -350,14 +532,17 @@ ltq_etop_mdio_probe(struct net_device *d + } + + phydev = phy_connect(dev, phydev_name(phydev), +- <q_etop_mdio_link, priv->pldata->mii_mode); ++ <q_etop_mdio_link, priv->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + +- phy_set_max_speed(phydev, SPEED_100); ++ if (of_machine_is_compatible("lantiq,ar9")) ++ phy_set_max_speed(phydev, SPEED_1000); ++ else ++ phy_set_max_speed(phydev, SPEED_100); + + phy_attached_info(phydev); + +@@ -378,8 +563,13 @@ ltq_etop_mdio_init(struct net_device *de + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +@@ -416,18 +606,21 @@ static int + ltq_etop_open(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ napi_enable(&priv->txch.napi); ++ napi_enable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_open(&priv->txch.dma); ++ ltq_dma_enable_irq(&priv->txch.dma); ++ ltq_dma_open(&priv->rxch.dma); ++ ltq_dma_enable_irq(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (dev->phydev) ++ phy_start(dev->phydev); + +- if (!IS_TX(i) && (!IS_RX(i))) +- continue; +- ltq_dma_open(&ch->dma); +- ltq_dma_enable_irq(&ch->dma); +- napi_enable(&ch->napi); +- } +- phy_start(dev->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -436,18 +629,19 @@ static int + ltq_etop_stop(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + + netif_tx_stop_all_queues(dev); +- phy_stop(dev->phydev); +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- if (!IS_RX(i) && !IS_TX(i)) +- continue; +- napi_disable(&ch->napi); +- ltq_dma_close(&ch->dma); +- } ++ if (dev->phydev) ++ phy_stop(dev->phydev); ++ napi_disable(&priv->txch.napi); ++ napi_disable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_close(&priv->txch.dma); ++ ltq_dma_close(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ + return 0; + } + +@@ -457,16 +651,16 @@ ltq_etop_tx(struct sk_buff *skb, struct + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); +- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; +- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; ++ struct ltq_dma_desc *desc = ++ &priv->txch.dma.desc_base[priv->txch.dma.desc]; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { +- dev_kfree_skb_any(skb); ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ++ priv->txch.skb[priv->txch.dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; +@@ -474,7 +668,7 @@ ltq_etop_tx(struct sk_buff *skb, struct + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; +- ch->skb[ch->dma.desc] = skb; ++ priv->txch.skb[priv->txch.dma.desc] = skb; + + netif_trans_update(dev); + +@@ -484,11 +678,11 @@ ltq_etop_tx(struct sk_buff *skb, struct + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); +- ch->dma.desc++; +- ch->dma.desc %= LTQ_DESC_NUM; ++ priv->txch.dma.desc++; ++ priv->txch.dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + +- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +@@ -499,11 +693,14 @@ ltq_etop_change_mtu(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; ++ int max; + + dev->mtu = new_mtu; + ++ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; ++ + spin_lock_irqsave(&priv->lock, flags); +- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); ++ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +@@ -563,6 +760,9 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { +@@ -580,9 +780,10 @@ ltq_etop_init(struct net_device *dev) + dev->addr_assign_type = NET_ADDR_RANDOM; + + ltq_etop_set_multicast_list(dev); +- err = ltq_etop_mdio_init(dev); +- if (err) +- goto err_netdev; ++ if (!ltq_etop_mdio_init(dev)) ++ dev->ethtool_ops = <q_etop_ethtool_ops; ++ else ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: +@@ -602,6 +803,9 @@ ltq_etop_tx_timeout(struct net_device *d + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + netif_trans_update(dev); + netif_wake_queue(dev); + return; +@@ -625,14 +829,19 @@ static const struct net_device_ops ltq_e + .ndo_tx_timeout = ltq_etop_tx_timeout, + }; + +-static int __init +-ltq_etop_probe(struct platform_device *pdev) ++static int ltq_etop_probe(struct platform_device *pdev) + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res, irqres[2]; ++ const u8 *mac; + int err; +- int i; ++ ++ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); ++ if (err != 2) { ++ dev_err(&pdev->dev, "failed to get etop irqs\n"); ++ return -EINVAL; ++ } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -658,31 +867,62 @@ ltq_etop_probe(struct platform_device *p + goto err_out; + } + +- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); +- if (!dev) { +- err = -ENOMEM; +- goto err_out; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } + } ++ ++ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; +- dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pdev = pdev; +- priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; ++ priv->tx_irq = irqres[0].start; ++ priv->rx_irq = irqres[1].start; ++ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); ++ ++ mac = of_get_mac_address(pdev->dev.of_node); ++ if (mac) ++ memcpy(priv->mac, mac, ETH_ALEN); ++ ++ priv->clk_ppe = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_ppe)) ++ return PTR_ERR(priv->clk_ppe); ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->clk_switch = clk_get(&pdev->dev, "switch"); ++ if (IS_ERR(priv->clk_switch)) ++ return PTR_ERR(priv->clk_switch); ++ } ++ if (of_machine_is_compatible("lantiq,ase")) { ++ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); ++ if (IS_ERR(priv->clk_ephy)) ++ return PTR_ERR(priv->clk_ephy); ++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); ++ if (IS_ERR(priv->clk_ephycgu)) ++ return PTR_ERR(priv->clk_ephycgu); ++ } ++ + spin_lock_init(&priv->lock); + SET_NETDEV_DEV(dev, &pdev->dev); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- if (IS_TX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_tx, 8); +- else if (IS_RX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_rx, 32); +- priv->ch[i].netdev = dev; +- } ++ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); ++ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); ++ priv->txch.netdev = dev; ++ priv->rxch.netdev = dev; + + err = register_netdev(dev); + if (err) +@@ -711,31 +951,22 @@ ltq_etop_remove(struct platform_device * + return 0; + } + ++static const struct of_device_id ltq_etop_match[] = { ++ { .compatible = "lantiq,etop-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_etop_match); ++ + static struct platform_driver ltq_mii_driver = { ++ .probe = ltq_etop_probe, + .remove = ltq_etop_remove, + .driver = { + .name = "ltq_etop", ++ .of_match_table = ltq_etop_match, + }, + }; + +-int __init +-init_ltq_etop(void) +-{ +- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); +- +- if (ret) +- pr_err("ltq_etop: Error registering platform driver!"); +- return ret; +-} +- +-static void __exit +-exit_ltq_etop(void) +-{ +- platform_driver_unregister(<q_mii_driver); +-} +- +-module_init(init_ltq_etop); +-module_exit(exit_ltq_etop); ++module_platform_driver(ltq_mii_driver); + + MODULE_AUTHOR("John Crispin "); + MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch b/target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch new file mode 100644 index 0000000000..419516978c --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch @@ -0,0 +1,169 @@ +From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 12 Aug 2014 20:49:27 +0200 +Subject: [PATCH 30/36] GPIO: add named gpio exports + +Signed-off-by: John Crispin +--- + drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ + drivers/gpio/gpiolib.c | 11 +++++-- + include/asm-generic/gpio.h | 5 +++ + include/linux/gpio/consumer.h | 8 +++++ + 4 files changed, 90 insertions(+), 2 deletions(-) + +--- a/drivers/gpio/gpiolib-of.c ++++ b/drivers/gpio/gpiolib-of.c +@@ -19,6 +19,8 @@ + #include + #include + #include ++#include ++#include + + #include "gpiolib.h" + #include "gpiolib-of.h" +@@ -915,3 +917,72 @@ void of_gpiochip_remove(struct gpio_chip + { + of_node_put(chip->of_node); + } ++ ++#ifdef CONFIG_GPIO_SYSFS ++ ++static struct of_device_id gpio_export_ids[] = { ++ { .compatible = "gpio-export" }, ++ { /* sentinel */ } ++}; ++ ++static int of_gpio_export_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct device_node *cnp; ++ u32 val; ++ int nb = 0; ++ ++ for_each_child_of_node(np, cnp) { ++ const char *name = NULL; ++ int gpio; ++ bool dmc; ++ int max_gpio = 1; ++ int i; ++ ++ of_property_read_string(cnp, "gpio-export,name", &name); ++ ++ if (!name) ++ max_gpio = of_gpio_count(cnp); ++ ++ for (i = 0; i < max_gpio; i++) { ++ unsigned flags = 0; ++ enum of_gpio_flags of_flags; ++ ++ gpio = of_get_gpio_flags(cnp, i, &of_flags); ++ if (!gpio_is_valid(gpio)) ++ return gpio; ++ ++ if (of_flags == OF_GPIO_ACTIVE_LOW) ++ flags |= GPIOF_ACTIVE_LOW; ++ ++ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) ++ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; ++ else ++ flags |= GPIOF_IN; ++ ++ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) ++ continue; ++ ++ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); ++ gpio_export_with_name(gpio, dmc, name); ++ nb++; ++ } ++ } ++ ++ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); ++ ++ return 0; ++} ++ ++static struct platform_driver gpio_export_driver = { ++ .driver = { ++ .name = "gpio-export", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(gpio_export_ids), ++ }, ++ .probe = of_gpio_export_probe, ++}; ++ ++module_platform_driver(gpio_export_driver); ++ ++#endif +--- a/include/asm-generic/gpio.h ++++ b/include/asm-generic/gpio.h +@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g + return gpiod_export(gpio_to_desc(gpio), direction_may_change); + } + ++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); ++static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) ++{ ++ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); ++} ++ + static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) + { +--- a/include/linux/gpio/consumer.h ++++ b/include/linux/gpio/consumer.h +@@ -668,6 +668,7 @@ static inline void devm_acpi_dev_remove_ + + #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) + ++int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); + int gpiod_export(struct gpio_desc *desc, bool direction_may_change); + int gpiod_export_link(struct device *dev, const char *name, + struct gpio_desc *desc); +@@ -675,6 +676,13 @@ void gpiod_unexport(struct gpio_desc *de + + #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ + ++static inline int _gpiod_export(struct gpio_desc *desc, ++ bool direction_may_change, ++ const char *name) ++{ ++ return -ENOSYS; ++} ++ + static inline int gpiod_export(struct gpio_desc *desc, + bool direction_may_change) + { +--- a/drivers/gpio/gpiolib-sysfs.c ++++ b/drivers/gpio/gpiolib-sysfs.c +@@ -563,7 +563,7 @@ static struct class gpio_class = { + * + * Returns zero on success, else an error. + */ +-int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) + { + struct gpio_chip *chip; + struct gpio_device *gdev; +@@ -625,6 +625,8 @@ int gpiod_export(struct gpio_desc *desc, + offset = gpio_chip_hwgpio(desc); + if (chip->names && chip->names[offset]) + ioname = chip->names[offset]; ++ if (name) ++ ioname = name; + + dev = device_create_with_groups(&gpio_class, &gdev->dev, + MKDEV(0, 0), data, gpio_groups, +@@ -646,6 +648,12 @@ err_unlock: + gpiod_dbg(desc, "%s: status %d\n", __func__, status); + return status; + } ++EXPORT_SYMBOL_GPL(__gpiod_export); ++ ++int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++{ ++ return __gpiod_export(desc, direction_may_change, NULL); ++} + EXPORT_SYMBOL_GPL(gpiod_export); + + static int match_export(struct device *dev, const void *desc) diff --git a/target/linux/lantiq/patches-5.4/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-5.4/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch new file mode 100644 index 0000000000..2493da32ec --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch @@ -0,0 +1,1034 @@ +From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:26:42 +0200 +Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master + +This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/i2c/busses/Kconfig | 10 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ + drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ + 4 files changed, 992 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-lantiq.c + create mode 100644 drivers/i2c/busses/i2c-lantiq.h + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -729,6 +729,16 @@ config I2C_MESON + If you say yes to this option, support will be included for the + I2C interface on the Amlogic Meson family of SoCs. + ++config I2C_LANTIQ ++ tristate "Lantiq I2C interface" ++ depends on LANTIQ && SOC_FALCON ++ help ++ If you say yes to this option, support will be included for the ++ Lantiq I2C core. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-lantiq. ++ + config I2C_MPC + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" + depends on PPC +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -73,6 +73,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l + obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o + obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o + obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o ++obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o + obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o + obj-$(CONFIG_I2C_MESON) += i2c-meson.o + obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.c +@@ -0,0 +1,747 @@ ++ ++/* ++ * Lantiq I2C bus adapter ++ * ++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * Copyright (C) 2012 Thomas Langer ++ */ ++ ++#include ++#include ++#include ++#include /* for kzalloc, kfree */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "i2c-lantiq.h" ++ ++/* ++ * CURRENT ISSUES: ++ * - no high speed support ++ * - ten bit mode is not tested (no slave devices) ++ */ ++ ++/* access macros */ ++#define i2c_r32(reg) \ ++ __raw_readl(&(priv->membase)->reg) ++#define i2c_w32(val, reg) \ ++ __raw_writel(val, &(priv->membase)->reg) ++#define i2c_w32_mask(clear, set, reg) \ ++ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) ++ ++#define DRV_NAME "i2c-lantiq" ++#define DRV_VERSION "1.00" ++ ++#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ ++ ++#ifdef DEBUG ++#define LTQ_I2C_XFER_TIMEOUT (25*HZ) ++#else ++#define LTQ_I2C_XFER_TIMEOUT HZ ++#endif ++ ++#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ ++ I2C_IMSC_I2C_ERR_INT_EN) ++ ++#define LTQ_I2C_ARB_LOST (1 << 0) ++#define LTQ_I2C_NACK (1 << 1) ++#define LTQ_I2C_RX_UFL (1 << 2) ++#define LTQ_I2C_RX_OFL (1 << 3) ++#define LTQ_I2C_TX_UFL (1 << 4) ++#define LTQ_I2C_TX_OFL (1 << 5) ++ ++struct ltq_i2c { ++ struct mutex mutex; ++ ++ ++ /* active clock settings */ ++ unsigned int input_clock; /* clock input for i2c hardware block */ ++ unsigned int i2c_clock; /* approximated bus clock in kHz */ ++ ++ struct clk *clk_gate; ++ struct clk *clk_input; ++ ++ ++ /* resources (memory and interrupts) */ ++ int irq_lb; /* last burst irq */ ++ ++ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ ++ ++ struct i2c_adapter adap; ++ struct device *dev; ++ ++ struct completion cmd_complete; ++ ++ ++ /* message transfer data */ ++ struct i2c_msg *current_msg; /* current message */ ++ int msgs_num; /* number of messages to handle */ ++ u8 *msg_buf; /* current buffer */ ++ u32 msg_buf_len; /* remaining length of current buffer */ ++ int msg_err; /* error status of the current transfer */ ++ ++ ++ /* master status codes */ ++ enum { ++ STATUS_IDLE, ++ STATUS_ADDR, /* address phase */ ++ STATUS_WRITE, ++ STATUS_READ, ++ STATUS_READ_END, ++ STATUS_STOP ++ } status; ++}; ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); ++ ++static inline void enable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); ++} ++static inline void disable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); ++} ++ ++static void prepare_msg_send_addr(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ ++ u16 addr = msg->addr; ++ ++ /* new i2c_msg */ ++ priv->msg_buf = msg->buf; ++ priv->msg_buf_len = msg->len; ++ if (rd) ++ priv->status = STATUS_READ; ++ else ++ priv->status = STATUS_WRITE; ++ ++ /* send slave address */ ++ if (msg->flags & I2C_M_TEN) { ++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); ++ i2c_w32(addr & 0xff, txd); ++ } else { ++ i2c_w32((addr & 0x7f) << 1 | rd, txd); ++ } ++} ++ ++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; ++ ++ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); ++ ++ priv->status = STATUS_ADDR; ++ ++ if (!(msg->flags & I2C_M_RD)) ++ len += msg->len; ++ else ++ /* set maximum received packet size (before rx int!) */ ++ i2c_w32(msg->len, mrps_ctrl); ++ i2c_w32(len, tps_ctrl); ++ enable_burst_irq(priv); ++} ++ ++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ unsigned int input_clock = clk_get_rate(priv->clk_input); ++ u32 dec, inc = 1; ++ ++ /* clock changed? */ ++ if (priv->input_clock == input_clock) ++ return 0; ++ ++ /* ++ * this formula is only an approximation, found by the recommended ++ * values in the "I2C Architecture Specification 1.7.1" ++ */ ++ dec = input_clock / (priv->i2c_clock * 2); ++ if (dec <= 6) ++ return -ENXIO; ++ ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | ++ (dec << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ ++ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", ++ input_clock, priv->i2c_clock, dec); ++ ++ priv->input_clock = input_clock; ++ return 0; ++} ++ ++static int ltq_i2c_hw_init(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++#ifndef DEBUG ++ /* set normal operation clock divider */ ++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); ++#else ++ /* for debugging a higher divider value! */ ++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); ++#endif ++ ++ /* setup clock */ ++ ret = ltq_i2c_hw_set_clock(adap); ++ if (ret != 0) { ++ dev_warn(priv->dev, "invalid clock settings\n"); ++ return ret; ++ } ++ ++ /* configure fifo */ ++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ ++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ ++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ ++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ ++ fifo_cfg); ++ ++ /* configure address */ ++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in ++ the fifo */ ++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ ++ I2C_ADDR_CFG_MnS_EN | /* we are master device */ ++ 0, /* our slave address (not used!) */ ++ addr_cfg); ++ ++ /* enable bus */ ++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); ++ ++ return 0; ++} ++ ++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); ++ ++ do { ++ u32 stat = i2c_r32(bus_stat); ++ ++ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(priv->dev, "timeout waiting for bus ready\n"); ++ return -ETIMEDOUT; ++} ++ ++static void ltq_i2c_tx(struct ltq_i2c *priv, int last) ++{ ++ if (priv->msg_buf_len && priv->msg_buf) { ++ i2c_w32(*priv->msg_buf, txd); ++ ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else ++ priv->msg_buf = NULL; ++ } else { ++ last = 1; ++ } ++ ++ if (last) ++ disable_burst_irq(priv); ++} ++ ++static void ltq_i2c_rx(struct ltq_i2c *priv, int last) ++{ ++ u32 fifo_stat, timeout; ++ if (priv->msg_buf_len && priv->msg_buf) { ++ timeout = 5000000; ++ do { ++ fifo_stat = i2c_r32(ffs_stat); ++ } while (!fifo_stat && --timeout); ++ if (!timeout) { ++ last = 1; ++ pr_debug("\nrx timeout\n"); ++ goto err; ++ } ++ while (fifo_stat) { ++ *priv->msg_buf = i2c_r32(rxd); ++ if (--priv->msg_buf_len) { ++ priv->msg_buf++; ++ } else { ++ priv->msg_buf = NULL; ++ last = 1; ++ break; ++ } ++ /* ++ * do not read more than burst size, otherwise no "last ++ * burst" is generated and the transaction is blocked! ++ */ ++ fifo_stat = 0; ++ } ++ } else { ++ last = 1; ++ } ++err: ++ if (last) { ++ disable_burst_irq(priv); ++ ++ if (priv->status == STATUS_READ_END) { ++ /* ++ * do the STATUS_STOP and complete() here, as sometimes ++ * the tx_end is already seen before this is finished ++ */ ++ priv->status = STATUS_STOP; ++ complete(&priv->cmd_complete); ++ } else { ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++ priv->status = STATUS_READ_END; ++ } ++ } ++} ++ ++static void ltq_i2c_xfer_init(struct ltq_i2c *priv) ++{ ++ /* enable interrupts */ ++ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); ++ ++ /* trigger transfer of first msg */ ++ ltq_i2c_set_tx_len(priv); ++} ++ ++static void dump_msgs(struct i2c_msg msgs[], int num, int rx) ++{ ++#if defined(DEBUG) ++ int i, j; ++ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); ++ for (i = 0; i < num; i++) { ++ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, ++ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', ++ msgs[i].len, msgs[i].addr); ++ if (!(msgs[i].flags & I2C_M_RD) || rx) { ++ for (j = 0; j < msgs[i].len; j++) ++ pr_debug("%02X ", msgs[i].buf[j]); ++ } ++ pr_debug("\n"); ++ } ++#endif ++} ++ ++static void ltq_i2c_release_bus(struct ltq_i2c *priv) ++{ ++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++} ++ ++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], ++ int num) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ int ret; ++ ++ dev_dbg(priv->dev, "xfer %u messages\n", num); ++ dump_msgs(msgs, num, 0); ++ ++ mutex_lock(&priv->mutex); ++ ++ init_completion(&priv->cmd_complete); ++ priv->current_msg = msgs; ++ priv->msgs_num = num; ++ priv->msg_err = 0; ++ priv->status = STATUS_IDLE; ++ ++ /* wait for the bus to become ready */ ++ ret = ltq_i2c_wait_bus_not_busy(priv); ++ if (ret) ++ goto done; ++ ++ while (priv->msgs_num) { ++ /* start the transfers */ ++ ltq_i2c_xfer_init(priv); ++ ++ /* wait for transfers to complete */ ++ ret = wait_for_completion_interruptible_timeout( ++ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); ++ if (ret == 0) { ++ dev_err(priv->dev, "controller timed out\n"); ++ ltq_i2c_hw_init(adap); ++ ret = -ETIMEDOUT; ++ goto done; ++ } else if (ret < 0) ++ goto done; ++ ++ if (priv->msg_err) { ++ if (priv->msg_err & LTQ_I2C_NACK) ++ ret = -ENXIO; ++ else ++ ret = -EREMOTEIO; ++ goto done; ++ } ++ if (--priv->msgs_num) ++ priv->current_msg++; ++ } ++ /* no error? */ ++ ret = num; ++ ++done: ++ ltq_i2c_release_bus(priv); ++ ++ mutex_unlock(&priv->mutex); ++ ++ if (ret >= 0) ++ dump_msgs(msgs, num, 1); ++ ++ pr_debug("XFER ret %d\n", ret); ++ return ret; ++} ++ ++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) ++{ ++ struct ltq_i2c *priv = dev_id; ++ struct i2c_msg *msg = priv->current_msg; ++ int last = (irq == priv->irq_lb); ++ ++ if (last) ++ pr_debug("LB "); ++ else ++ pr_debug("B "); ++ ++ if (msg->flags & I2C_M_RD) { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("X"); ++ prepare_msg_send_addr(priv); ++ disable_burst_irq(priv); ++ break; ++ case STATUS_READ: ++ case STATUS_READ_END: ++ pr_debug("R"); ++ ltq_i2c_rx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status R %d\n", priv->status); ++ break; ++ } ++ } else { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("x"); ++ prepare_msg_send_addr(priv); ++ break; ++ case STATUS_WRITE: ++ pr_debug("w"); ++ ltq_i2c_tx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status W %d\n", priv->status); ++ break; ++ } ++ } ++ ++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); ++ return IRQ_HANDLED; ++} ++ ++static void ltq_i2c_isr_prot(struct ltq_i2c *priv) ++{ ++ u32 i_pro = i2c_r32(p_irqss); ++ ++ pr_debug("i2c-p"); ++ ++ /* not acknowledge */ ++ if (i_pro & I2C_P_IRQSS_NACK) { ++ priv->msg_err |= LTQ_I2C_NACK; ++ pr_debug(" nack"); ++ } ++ ++ /* arbitration lost */ ++ if (i_pro & I2C_P_IRQSS_AL) { ++ priv->msg_err |= LTQ_I2C_ARB_LOST; ++ pr_debug(" arb-lost"); ++ } ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) ++ pr_debug(" rx"); ++ ++ /* tx end */ ++ if (i_pro & I2C_P_IRQSS_TX_END) ++ pr_debug(" txend"); ++ pr_debug("\n"); ++ ++ if (!priv->msg_err) { ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) { ++ priv->status = STATUS_READ; ++ enable_burst_irq(priv); ++ } ++ if (i_pro & I2C_P_IRQSS_TX_END) { ++ if (priv->status == STATUS_READ) ++ priv->status = STATUS_READ_END; ++ else { ++ disable_burst_irq(priv); ++ priv->status = STATUS_STOP; ++ } ++ } ++ } ++ ++ i2c_w32(i_pro, p_irqsc); ++} ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) ++{ ++ u32 i_raw, i_err = 0; ++ struct ltq_i2c *priv = dev_id; ++ ++ i_raw = i2c_r32(mis); ++ pr_debug("i_raw 0x%08X\n", i_raw); ++ ++ /* error interrupt */ ++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { ++ i_err = i2c_r32(err_irqss); ++ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", ++ i_err, i2c_r32(bus_stat)); ++ ++ /* tx fifo overflow (8) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_OFL) ++ priv->msg_err |= LTQ_I2C_TX_OFL; ++ ++ /* tx fifo underflow (4) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_UFL) ++ priv->msg_err |= LTQ_I2C_TX_UFL; ++ ++ /* rx fifo overflow (2) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_OFL) ++ priv->msg_err |= LTQ_I2C_RX_OFL; ++ ++ /* rx fifo underflow (1) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_UFL) ++ priv->msg_err |= LTQ_I2C_RX_UFL; ++ ++ i2c_w32(i_err, err_irqsc); ++ } ++ ++ /* protocol interrupt */ ++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) ++ ltq_i2c_isr_prot(priv); ++ ++ if ((priv->msg_err) || (priv->status == STATUS_STOP)) ++ complete(&priv->cmd_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 ltq_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | ++ I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm ltq_i2c_algorithm = { ++ .master_xfer = ltq_i2c_xfer, ++ .functionality = ltq_i2c_functionality, ++}; ++ ++static int ltq_i2c_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct ltq_i2c *priv; ++ struct i2c_adapter *adap; ++ struct resource *mmres, irqres[4]; ++ int ret = 0; ++ ++ dev_dbg(&pdev->dev, "probing\n"); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ret = of_irq_to_resource_table(node, irqres, 4); ++ if (!mmres || (ret != 4)) { ++ dev_err(&pdev->dev, "no resources\n"); ++ return -ENODEV; ++ } ++ ++ /* allocate private data */ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "can't allocate private data\n"); ++ return -ENOMEM; ++ } ++ ++ adap = &priv->adap; ++ i2c_set_adapdata(adap, priv); ++ adap->owner = THIS_MODULE; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); ++ adap->algo = <q_i2c_algorithm; ++ adap->dev.parent = &pdev->dev; ++ adap->dev.of_node = pdev->dev.of_node; ++ ++ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { ++ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); ++ priv->i2c_clock = 100000; ++ } ++ ++ init_completion(&priv->cmd_complete); ++ mutex_init(&priv->mutex); ++ ++ priv->membase = devm_ioremap_resource(&pdev->dev, mmres); ++ if (IS_ERR(priv->membase)) ++ return PTR_ERR(priv->membase); ++ ++ priv->dev = &pdev->dev; ++ priv->irq_lb = irqres[0].start; ++ ++ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, ++ 0x0, "i2c lb", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", ++ irqres[0].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, ++ 0x0, "i2c b", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get burst IRQ %d\n", ++ irqres[1].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, ++ 0x0, "i2c err", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get error IRQ %d\n", ++ irqres[2].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, ++ 0x0, "i2c p", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", ++ irqres[3].start); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); ++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, ++ irqres[1].start, irqres[2].start, irqres[3].start); ++ ++ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_gate)) { ++ dev_err(&pdev->dev, "failed to get i2c clk\n"); ++ return -ENOENT; ++ } ++ ++ /* this is a static clock, which has no refcounting */ ++ priv->clk_input = clk_get_fpi(); ++ if (IS_ERR(priv->clk_input)) { ++ dev_err(&pdev->dev, "failed to get fpi clk\n"); ++ return -ENOENT; ++ } ++ ++ clk_activate(priv->clk_gate); ++ ++ /* add our adapter to the i2c stack */ ++ ret = i2c_add_numbered_adapter(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't register I2C adapter\n"); ++ goto out; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ i2c_set_adapdata(adap, priv); ++ ++ /* print module version information */ ++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", ++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, ++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); ++ ++ /* initialize HW */ ++ ret = ltq_i2c_hw_init(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't configure adapter\n"); ++ i2c_del_adapter(adap); ++ platform_set_drvdata(pdev, NULL); ++ goto out; ++ } else { ++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); ++ } ++ ++out: ++ /* if init failed, we need to deactivate the clock gate */ ++ if (ret) ++ clk_deactivate(priv->clk_gate); ++ ++ return ret; ++} ++ ++static int ltq_i2c_remove(struct platform_device *pdev) ++{ ++ struct ltq_i2c *priv = platform_get_drvdata(pdev); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++ /* power down the core */ ++ clk_deactivate(priv->clk_gate); ++ ++ /* remove driver */ ++ i2c_del_adapter(&priv->adap); ++ kfree(priv); ++ ++ dev_dbg(&pdev->dev, "removed\n"); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++static const struct of_device_id ltq_i2c_match[] = { ++ { .compatible = "lantiq,lantiq-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_i2c_match); ++ ++static struct platform_driver ltq_i2c_driver = { ++ .probe = ltq_i2c_probe, ++ .remove = ltq_i2c_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_i2c_match, ++ }, ++}; ++ ++module_platform_driver(ltq_i2c_driver); ++ ++MODULE_DESCRIPTION("Lantiq I2C bus adapter"); ++MODULE_AUTHOR("Thomas Langer "); ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.h +@@ -0,0 +1,234 @@ ++#ifndef I2C_LANTIQ_H ++#define I2C_LANTIQ_H ++ ++/* I2C register structure */ ++struct lantiq_reg_i2c { ++ /* I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /* Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /* I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /* Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /* ++ * I2C RUN Control Register ++ * This register enables and disables the I2C peripheral. Before ++ * enabling, the I2C has to be configured properly. After enabling ++ * no configuration is possible ++ */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /* ++ * I2C End Data Control Register ++ * This register is used to either turn around the data transmission ++ * direction or to address another slave without sending a stop ++ * condition. Also the software can stop the slave-transmitter by ++ * sending a not-accolade when working as master-receiver or even ++ * stop data transmission immediately when operating as ++ * master-transmitter. The writing to the bits of this control ++ * register is only effective when in MASTER RECEIVES BYTES, MASTER ++ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state ++ */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /* ++ * I2C Fractional Divider Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_HIGH_CFG has ++ * the same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /* ++ * I2C Fractional Divider (highspeed mode) Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_CFG has the ++ * same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /* I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /* I2C Bus Status Register ++ * This register gives a status information of the I2C. This additional ++ * information can be used by the software to start proper actions. ++ */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /* I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /* I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /* I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /* I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /* I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /* Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /* I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /* Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /* I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /* I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /* I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /* Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /* I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /* I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /* I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /* Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /* I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /* I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /* I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /* I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /* I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /* I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /* Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /* I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /* Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /* I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /* Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++/* ++ * Clock Divider for Normal Run Mode ++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long ++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx ++ * on reading. ++ */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++ ++/* Fields of "I2C Identification Register" */ ++/* Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/* Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/* field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/* Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/* Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/* TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/* 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/* Stop on Packet End Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/* Stop on Not Acknowledge Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/* Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/* Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/* Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/* Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/* Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/* I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/* ++ * The device is working as master and has claimed the control on the ++ * I2C-bus (busy master). ++ */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++ ++/* Fields of "I2C RUN Control Register" */ ++/* Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/* ++ * Set End of Transmission ++ * Note:Do not write '1' to this bit when bus is free. This will cause an ++ * abort after the first byte when a new transfer is started. ++ */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/* NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++ ++ ++#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-5.4/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-5.4/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch new file mode 100644 index 0000000000..82567be690 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -0,0 +1,218 @@ +From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:42:14 +0200 +Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling + +Signed-off-by: John Crispin +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + + arch/mips/lantiq/xway/Makefile | 3 + + arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ + arch/mips/lantiq/xway/eth_mac.c | 25 ++++ + drivers/net/ethernet/lantiq_etop.c | 6 +- + 5 files changed, 172 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c + create mode 100644 arch/mips/lantiq/xway/eth_mac.c + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev, + extern void ltq_pmu_enable(unsigned int module); + extern void ltq_pmu_disable(unsigned int module); + ++/* allow the ethernet driver to load a flash mapped mac addr */ ++const u8* ltq_get_eth_mac(void); ++ + #endif /* CONFIG_SOC_TYPE_XWAY */ + #endif /* _LTQ_XWAY_H__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -8,3 +8,6 @@ obj-y += timer.o + endif + + obj-y += vmmc.o ++ ++obj-y += eth_mac.o ++obj-$(CONFIG_PCI) += ath5k_eep.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/ath5k_eep.c +@@ -0,0 +1,136 @@ ++/* ++ * Copyright (C) 2011 Luca Olivetti ++ * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011 Andrej Vlašić ++ * Copyright (C) 2013 Álvaro Fernández Rojas ++ * Copyright (C) 2013 Daniel Gimpelevich ++ * Copyright (C) 2015 Vittorio Gambaletta ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++struct ath5k_platform_data ath5k_pdata; ++static u8 athxk_eeprom_mac[6]; ++ ++static int ath5k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath5k_pdata; ++ return 0; ++} ++ ++static int ath5k_eep_load; ++int __init of_ath5k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; ++ int mac_offset; ++ u32 mac_inc = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ list = of_get_property(np, "ath,eep-flash", &i); ++ if (!list || (i != (2 * sizeof(*list)))) ++ return -ENODEV; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENODEV; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ the_mtd = get_mtd_device_nm(part); ++ if (IS_ERR(the_mtd)) ++ return -ENODEV; ++ ++ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); ++ ++ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, ++ &flash_readlen, (void *) ath5k_pdata.eeprom_data); ++ ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ size_t mac_readlen; ++ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, ++ (void *) athxk_eeprom_mac); ++ } ++ put_mtd_device(the_mtd); ++ ++ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) ++ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) ++ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ random_ether_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath5k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath5k_eeprom_ids[] = { ++ { .compatible = "ath5k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath5k_eeprom_driver = { ++ .driver = { ++ .name = "ath5k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath5k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath5k_eeprom_init(void) ++{ ++ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++ ++ if (ret) ++ ath5k_eep_load = 1; ++ ++ return ret; ++} ++ ++static int __init of_ath5k_eeprom_init_late(void) ++{ ++ if (!ath5k_eep_load) ++ return 0; ++ ++ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++} ++late_initcall(of_ath5k_eeprom_init_late); ++subsys_initcall(of_ath5k_eeprom_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/eth_mac.c +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++static u8 eth_mac[6]; ++static int eth_mac_set; ++ ++const u8* ltq_get_eth_mac(void) ++{ ++ return eth_mac; ++} ++ ++static int __init setup_ethaddr(char *str) ++{ ++ eth_mac_set = mac_pton(str, eth_mac); ++ return !eth_mac_set; ++} ++early_param("ethaddr", setup_ethaddr); +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -764,7 +764,11 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + +- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); ++ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); ++ ++ if (priv->mac && !is_valid_ether_addr(mac.sa_data)) ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-5.4/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-5.4/0042-arch-mips-increase-io_space_limit.patch new file mode 100644 index 0000000000..7c0d10ed10 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0042-arch-mips-increase-io_space_limit.patch @@ -0,0 +1,23 @@ +From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jun 2016 13:12:20 +0200 +Subject: [PATCH] arch: mips: increase io_space_limit + +this value comes from x86 and breaks some pci devices + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/io.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/io.h ++++ b/arch/mips/include/asm/io.h +@@ -53,7 +53,7 @@ + + /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ + +-#define IO_SPACE_LIMIT 0xffff ++#define IO_SPACE_LIMIT 0xffffffff + + /* + * On MIPS I/O ports are memory mapped, so we access them using normal diff --git a/target/linux/lantiq/patches-5.4/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-5.4/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch new file mode 100644 index 0000000000..d63d48ad1f --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch @@ -0,0 +1,78 @@ +From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:55:24 +0100 +Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs + +The size of the internal RAM of the DesignWare USB controller changed +between the different Lantiq SoCs. We have the following sizes: + +Amazon + Danube: 8 KByte +Amazon SE + arx100: 2 KByte +xrx200 + xrx300: 2.5 KByte + +For Danube SoC we do not provide the params and let the driver decide +to use sane defaults, for the Amazon SE and arx100 we use small fifos +and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. +The auto detection of max_transfer_size and max_packet_count should +work, so remove it. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- + 1 file changed, 39 insertions(+), 7 deletions(-) + +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -92,7 +92,14 @@ static void dwc2_set_rk_params(struct dw + p->power_down = 0; + } + +-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) ++static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; ++} ++ ++static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; + +@@ -100,12 +107,20 @@ static void dwc2_set_ltq_params(struct d + p->host_rx_fifo_size = 288; + p->host_nperio_tx_fifo_size = 128; + p->host_perio_tx_fifo_size = 96; +- p->max_transfer_size = 65535; +- p->max_packet_count = 511; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; + } + ++static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; ++ p->host_rx_fifo_size = 288; ++ p->host_nperio_tx_fifo_size = 128; ++ p->host_perio_tx_fifo_size = 136; ++} ++ + static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; +@@ -167,8 +182,11 @@ const struct of_device_id dwc2_of_match_ + { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, + { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, + { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, +- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, +- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, ++ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params }, ++ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params }, ++ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params }, ++ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params }, + { .compatible = "snps,dwc2" }, + { .compatible = "samsung,s3c6400-hsotg", + .data = dwc2_set_s3c6400_params }, diff --git a/target/linux/lantiq/patches-5.4/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-5.4/0051-MIPS-lantiq-improve-USB-initialization.patch new file mode 100644 index 0000000000..3f276e1158 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0051-MIPS-lantiq-improve-USB-initialization.patch @@ -0,0 +1,49 @@ +From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 6 Jan 2017 17:40:12 +0100 +Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization + +This adds code to initialize the USB controller and PHY also on Danube, +Amazon SE and AR10. This code is based on the Vendor driver from +different UGW versions and compared to the hardware documentation. + +Signed-off-by: Hauke Mehrtens +--- + arch/mips/lantiq/xway/sysctrl.c | 20 +++++++ + 2 files changed, 110 insertions(+), 30 deletions(-) + + +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -244,6 +244,25 @@ static void pmu_disable(struct clk *clk) + pr_warn("deactivating PMU module failed!"); + } + ++static void usb_set_clock(void) ++{ ++ unsigned int val = ltq_cgu_r32(ifccr); ++ ++ if (of_machine_is_compatible("lantiq,ar10") || ++ of_machine_is_compatible("lantiq,grx390")) { ++ val &= ~0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ar9") || ++ of_machine_is_compatible("lantiq,vr9")) { ++ /* TODO: this depends on the XTAL frequency */ ++ val |= 0x03; /* XTAL divided by 3 */ ++ } else if (of_machine_is_compatible("lantiq,ase")) { ++ val |= 0x20; /* from XTAL */ ++ } else if (of_machine_is_compatible("lantiq,danube")) { ++ val |= 0x30; /* 12 MHz, generated from 36 MHz */ ++ } ++ ltq_cgu_w32(val, ifccr); ++} ++ + /* the pci enable helper */ + static int pci_enable(struct clk *clk) + { +@@ -565,4 +584,5 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } ++ usb_set_clock(); + } diff --git a/target/linux/lantiq/patches-5.4/0101-find_active_root.patch b/target/linux/lantiq/patches-5.4/0101-find_active_root.patch new file mode 100644 index 0000000000..b6b4ab7409 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0101-find_active_root.patch @@ -0,0 +1,93 @@ +--- a/drivers/mtd/parsers/ofpart.c ++++ b/drivers/mtd/parsers/ofpart.c +@@ -21,6 +21,38 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, ++ loff_t offset) ++{ ++ static uint8_t root_id; ++ int err, len; ++ ++ err = mtd_read(master, offset, 0x01, &len, &root_id); ++ ++ if (mtd_is_bitflip(err) || !err) ++ return &root_id; ++ ++ return NULL; ++} ++ ++static void brnboot_set_active_root_part(struct mtd_partition *pparts, ++ struct device_node **part_nodes, ++ int nr_parts, ++ uint8_t *root_id) ++{ ++ int i; ++ ++ for (i = 0; i < nr_parts; i++) { ++ int part_root_id; ++ ++ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) ++ && part_root_id == *root_id) { ++ pparts[i].name = "firmware"; ++ break; ++ } ++ } ++} ++ + static int parse_fixed_partitions(struct mtd_info *master, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -32,7 +64,8 @@ static int parse_fixed_partitions(struct + struct device_node *pp; + int nr_parts, i, ret = 0; + bool dedicated = true; +- ++ uint8_t *proot_id = NULL; ++ struct device_node **part_nodes; + + /* Pull of_node from the master device node */ + mtd_node = mtd_get_of_node(master); +@@ -68,7 +101,9 @@ static int parse_fixed_partitions(struct + return 0; + + parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); +- if (!parts) ++ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL); ++ ++ if (!parts || !part_nodes) + return -ENOMEM; + + i = 0; +@@ -117,12 +152,22 @@ static int parse_fixed_partitions(struct + if (of_get_property(pp, "lock", &len)) + parts[i].mask_flags |= MTD_POWERUP_LOCK; + ++ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) ++ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); ++ ++ part_nodes[i] = pp; ++ + i++; + } + + if (!nr_parts) + goto ofpart_none; + ++ if (proot_id) ++ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); ++ ++ kfree(part_nodes); ++ + *pparts = parts; + return nr_parts; + +@@ -133,6 +178,7 @@ ofpart_fail: + ofpart_none: + of_node_put(pp); + kfree(parts); ++ kfree(part_nodes); + return ret; + } + diff --git a/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch new file mode 100644 index 0000000000..bc02a58b1c --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0151-lantiq-ifxmips_pcie-use-of.patch @@ -0,0 +1,387 @@ +--- a/arch/mips/pci/ifxmips_pcie.c ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -16,8 +16,15 @@ + #include + #include + #include ++#include ++#include ++#include ++#include + #include + ++#include ++#include ++ + #include "ifxmips_pcie.h" + #include "ifxmips_pcie_reg.h" + +@@ -40,6 +47,10 @@ + static DEFINE_SPINLOCK(ifx_pcie_lock); + + u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++static int pcie_reset_gpio; ++static struct phy *ltq_pcie_phy; ++static struct reset_control *ltq_pcie_reset; ++static struct regmap *ltq_rcu_regmap; + + static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { + { +@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ... + printk("%s", buf); + } + ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ gpio_direction_output(pcie_reset_gpio, 1); ++ gpio_set_value(pcie_reset_gpio, 1); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(pcie_reset_gpio, 0); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(pcie_reset_gpio, 1); ++} + + static inline int pcie_ltssm_enable(int pcie_port) + { +@@ -988,10 +1015,22 @@ int ifx_pcie_bios_plat_dev_init(struct + static int + pcie_rc_initialize(int pcie_port) + { +- int i; ++ int i, ret; + #define IFX_PCIE_PHY_LOOP_CNT 5 + +- pcie_rcu_endian_setup(pcie_port); ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M, ++ IFX_RCU_AHB_BE_PCIE_M); ++ ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ IFX_RCU_AHB_BE_PCIE_S); ++#else ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, ++ 0x0); ++#endif ++ ++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M, ++ 0x0); + + pcie_ep_gpio_rst_init(pcie_port); + +@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port) + * reset PCIe PHY will solve this issue + */ + for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { +- /* Disable PCIe PHY Analog part for sanity check */ +- pcie_phy_pmu_disable(pcie_port); +- +- pcie_phy_rst_assert(pcie_port); +- pcie_phy_rst_deassert(pcie_port); +- +- /* Make sure PHY PLL is stable */ +- udelay(20); +- +- /* PCIe Core reset enabled, low active, sw programmed */ +- pcie_core_rst_assert(pcie_port); ++ ret = phy_init(ltq_pcie_phy); ++ if (ret) ++ continue; + + /* Put PCIe EP in reset status */ + pcie_device_rst_assert(pcie_port); + +- /* PCI PHY & Core reset disabled, high active, sw programmed */ +- pcie_core_rst_deassert(pcie_port); ++ udelay(1); ++ reset_control_deassert(ltq_pcie_reset); + +- /* Already in a quiet state, program PLL, enable PHY, check ready bit */ +- pcie_phy_clock_mode_setup(pcie_port); ++ ret = phy_power_on(ltq_pcie_phy); ++ if (ret) { ++ phy_exit(ltq_pcie_phy); ++ continue; ++ } + + /* Enable PCIe PHY and Clock */ + pcie_core_pmu_setup(pcie_port); +@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port) + /* Once link is up, break out */ + if (pcie_app_loigc_setup(pcie_port) == 0) + break; ++ ++ phy_power_off(ltq_pcie_phy); ++ reset_control_assert(ltq_pcie_reset); ++ phy_exit(ltq_pcie_phy); + } + if (i >= IFX_PCIE_PHY_LOOP_CNT) { + printk(KERN_ERR "%s link up failed!!!!!\n", __func__); +@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port) + return 0; + } + +-static int __init ifx_pcie_bios_init(void) ++static int ifx_pcie_bios_probe(struct platform_device *pdev) + { ++ struct device_node *node = pdev->dev.of_node; + void __iomem *io_map_base; + int pcie_port; + int startup_port; ++ struct device_node *np; ++ struct pci_bus *bus; ++ ++ /* ++ * In case a PCI device is physical present, the Lantiq PCI driver need ++ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them ++ * will work. ++ * ++ * In case the lantiq PCI driver is enabled in the device tree, check if ++ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already ++ * registered. ++ * ++ * It will fail if there is another PCI controller, this controller is ++ * registered before the Lantiq PCIe driver is probe and the lantiq PCI ++ */ ++ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway"); ++ ++ if (of_device_is_available(np)) { ++ bus = pci_find_next_bus(bus); ++ ++ if (!bus) ++ return -EPROBE_DEFER; ++ } + + /* Enable AHB Master/ Slave */ + pcie_ahb_pmu_setup(); + + startup_port = IFX_PCIE_PORT0; +- ++ ++ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie"); ++ if (IS_ERR(ltq_pcie_phy)) { ++ dev_err(&pdev->dev, "failed to get the PCIe PHY\n"); ++ return PTR_ERR(ltq_pcie_phy); ++ } ++ ++ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL); ++ if (IS_ERR(ltq_pcie_reset)) { ++ dev_err(&pdev->dev, "failed to get the PCIe reset line\n"); ++ return PTR_ERR(ltq_pcie_reset); ++ } ++ ++ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu"); ++ if (IS_ERR(ltq_rcu_regmap)) ++ return PTR_ERR(ltq_rcu_regmap); ++ ++ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); ++ if (gpio_is_valid(pcie_reset_gpio)) { ++ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset"); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio); ++ return ret; ++ } ++ gpio_direction_output(pcie_reset_gpio, 1); ++ } ++ + for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ + if (pcie_rc_initialize(pcie_port) == 0) { + IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", +@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi + return -ENOMEM; + } + ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); + + register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); + /* XXX, clear error status */ +@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi + + return 0; + } ++ ++static const struct of_device_id ifxmips_pcie_match[] = { ++ { .compatible = "lantiq,pcie-xrx200" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); ++ ++static struct platform_driver ltq_pci_driver = { ++ .probe = ifx_pcie_bios_probe, ++ .driver = { ++ .name = "pcie-xrx200", ++ .owner = THIS_MODULE, ++ .of_match_table = ifxmips_pcie_match, ++ }, ++}; ++ ++int __init ifx_pcie_bios_init(void) ++{ ++ int ret = platform_driver_register(<q_pci_driver); ++ if (ret) ++ pr_info("pcie-xrx200: Error registering platform driver!"); ++ return ret; ++} ++ + arch_initcall(ifx_pcie_bios_init); + + MODULE_LICENSE("GPL"); +--- a/arch/mips/pci/ifxmips_pcie_vr9.h ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -22,8 +22,6 @@ + #include + #include + +-#define IFX_PCIE_GPIO_RESET 494 +- + #define IFX_REG_R32 ltq_r32 + #define IFX_REG_W32 ltq_w32 + #define CONFIG_IFX_PCIE_HW_SWAP +@@ -53,21 +51,6 @@ + #define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) + + +-static inline void pcie_ep_gpio_rst_init(int pcie_port) +-{ +- +- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +- gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- +-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ +-} +- + static inline void pcie_ahb_pmu_setup(void) + { + /* Enable AHB bus master/slave */ +@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo + //AHBS_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_rcu_endian_setup(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +-#ifdef CONFIG_IFX_PCIE_HW_SWAP +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg |= IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#else +- reg |= IFX_RCU_AHB_BE_PCIE_M; +- reg &= ~IFX_RCU_AHB_BE_PCIE_S; +- reg &= ~IFX_RCU_AHB_BE_XBAR_M; +-#endif /* CONFIG_IFX_PCIE_HW_SWAP */ +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +- IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); +-} +- + static inline void pcie_phy_pmu_enable(int pcie_port) + { + struct clk *clk; +@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable( + // PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); + } + +-static inline void pcie_pdi_big_endian(int pcie_port) +-{ +- u32 reg; +- +- /* SRAM2PDI endianness control. */ +- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +- /* Config AHB->PCIe and PDI endianness */ +- reg |= IFX_RCU_AHB_BE_PCIE_PDI; +- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +-} +- + static inline void pcie_pdi_pmu_enable(int pcie_port) + { + /* Enable PDI to access PCIe PHY register */ +@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i + //PDI_PMU_SETUP(IFX_PMU_ENABLE); + } + +-static inline void pcie_core_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- +- /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ +- reg |= 0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_core_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- /* Reset PCIe PHY & Core, bit 22 */ +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00400000; +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_assert(int pcie_port) +-{ +- u32 reg; +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg |= 0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_phy_rst_deassert(int pcie_port) +-{ +- u32 reg; +- +- /* Make sure one micro-second delay */ +- udelay(1); +- +- reg = IFX_REG_R32(IFX_RCU_RST_REQ); +- reg &= ~0x00001000; /* Bit 12 */ +- IFX_REG_W32(reg, IFX_RCU_RST_REQ); +-} +- +-static inline void pcie_device_rst_assert(int pcie_port) +-{ +- gpio_set_value(IFX_PCIE_GPIO_RESET, 0); +-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- +-static inline void pcie_device_rst_deassert(int pcie_port) +-{ +- mdelay(100); +- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); +-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); +- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); +-} +- + static inline void pcie_core_pmu_setup(int pcie_port) + { + struct clk *clk; +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -51,7 +51,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o + obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o +-obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o + obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o diff --git a/target/linux/lantiq/patches-5.4/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.4/0152-lantiq-VPE.patch new file mode 100644 index 0000000000..f454055824 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0152-lantiq-VPE.patch @@ -0,0 +1,180 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2375,6 +2375,12 @@ config MIPS_VPE_LOADER + Includes a loader for loading an elf relocatable object + onto another VPE and running it. + ++config IFX_VPE_EXT ++ bool "IFX APRP Extensions" ++ depends on MIPS_VPE_LOADER ++ help ++ IFX included extensions in APRP ++ + config MIPS_VPE_LOADER_CMP + bool + default "y" +--- a/arch/mips/include/asm/vpe.h ++++ b/arch/mips/include/asm/vpe.h +@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc); + + int __init vpe_module_init(void); + void __exit vpe_module_exit(void); ++ ++/* For the explanation of the APIs please refer the section "MT APRP Kernel ++ * Programming" in AR9 SW Architecture Specification ++ */ ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); ++int32_t vpe1_sw_stop(uint32_t flags); ++uint32_t vpe1_get_load_addr(uint32_t flags); ++uint32_t vpe1_get_max_mem(uint32_t flags); ++ + #endif /* _ASM_VPE_H */ +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v) + struct vpe_notifications *notifier; + unsigned int vpeflags; + struct tc *t; ++ unsigned long physical_memsize = 0L; + + /* check we are the Master VPE */ + local_irq_save(flags); +@@ -417,6 +418,8 @@ int __init vpe_module_init(void) + } + + v->ntcs = hw_tcs - aprp_cpu_index(); ++ write_tc_c0_tcbind((read_tc_c0_tcbind() & ++ ~TCBIND_CURVPE) | 1); + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); +@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void) + release_vpe(v); + } + } ++ ++#ifdef CONFIG_IFX_VPE_EXT ++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) ++{ ++ enum vpe_state state; ++ struct vpe *v = get_vpe(tclimit); ++ struct vpe_notifications *not; ++ ++ if (tcmask || flags) { ++ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); ++ return -1; ++ } ++ ++ state = xchg(&v->state, VPE_STATE_INUSE); ++ if (state != VPE_STATE_UNUSED) { ++ vpe_stop(v); ++ ++ list_for_each_entry(not, &v->notify, list) { ++ not->stop(tclimit); ++ } ++ } ++ ++ v->__start = (unsigned long)sw_start_addr; ++ ++ if (!vpe_run(v)) { ++ pr_debug("VPE loader: VPE1 running successfully\n"); ++ return 0; ++ } ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_start); ++ ++int32_t vpe1_sw_stop(uint32_t flags) ++{ ++ struct vpe *v = get_vpe(tclimit); ++ ++ if (!vpe_free(v)) { ++ pr_debug("RP Stopped\n"); ++ return 0; ++ } else ++ return -1; ++} ++EXPORT_SYMBOL(vpe1_sw_stop); ++#endif +--- a/arch/mips/kernel/vpe.c ++++ b/arch/mips/kernel/vpe.c +@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { + .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) + }; + ++#ifdef CONFIG_IFX_VPE_EXT ++unsigned int vpe1_load_addr; ++ ++static int __init load_address(char *str) ++{ ++ get_option(&str, &vpe1_load_addr); ++ return 1; ++} ++__setup("vpe1_load_addr=", load_address); ++ ++static unsigned int vpe1_mem; ++static int __init vpe1mem(char *str) ++{ ++ vpe1_mem = memparse(str, &str); ++ return 1; ++} ++__setup("vpe1_mem=", vpe1mem); ++ ++uint32_t vpe1_get_load_addr(uint32_t flags) ++{ ++ return vpe1_load_addr; ++} ++EXPORT_SYMBOL(vpe1_get_load_addr); ++ ++uint32_t vpe1_get_max_mem(uint32_t flags) ++{ ++ if (!vpe1_mem) ++ return P_SIZE; ++ else ++ return vpe1_mem; ++} ++EXPORT_SYMBOL(vpe1_get_max_mem); ++ ++#endif ++ + /* get the vpe associated with this minor */ + struct vpe *get_vpe(int minor) + { +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -34,10 +34,14 @@ unsigned long physical_memsize = 0L; + */ + static struct ltq_soc_info soc_info; + ++/* for Multithreading (APRP), vpe.c will use it */ ++unsigned long cp0_memsize; ++ + const char *get_system_type(void) + { + return soc_info.sys_type; + } ++EXPORT_SYMBOL(ltq_soc_type); + + int ltq_soc_type(void) + { +--- a/arch/mips/include/asm/mipsmtregs.h ++++ b/arch/mips/include/asm/mipsmtregs.h +@@ -32,6 +32,9 @@ + #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) + #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) + ++#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) ++#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) ++ + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) + #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) + +@@ -378,6 +381,8 @@ do { \ + #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) + #define read_vpe_c0_vpeconf1() mftc0(1, 3) + #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) ++#define read_vpe_c0_vpeopt() mftc0(1, 7) ++#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) + #define read_vpe_c0_count() mftc0(9, 0) + #define write_vpe_c0_count(val) mttc0(9, 0, val) + #define read_vpe_c0_status() mftc0(12, 0) diff --git a/target/linux/lantiq/patches-5.4/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-5.4/0154-lantiq-pci-bar11mask-fix.patch new file mode 100644 index 0000000000..d6556d115d --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0154-lantiq-pci-bar11mask-fix.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/pci/pci-lantiq.c ++++ b/arch/mips/pci/pci-lantiq.c +@@ -59,6 +59,8 @@ + #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) + #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) + ++extern u32 max_low_pfn; ++ + __iomem void *ltq_pci_mapped_cfg; + static __iomem void *ltq_pci_membase; + +@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi + u32 mem, bar11mask; + + /* BAR11MASK value depends on available memory on system. */ +- mem = get_num_physpages() * PAGE_SIZE; +- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; ++ mem = max_low_pfn << PAGE_SHIFT; ++ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; + + return bar11mask; + } diff --git a/target/linux/lantiq/patches-5.4/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-5.4/0155-lantiq-VPE-nosmp.patch new file mode 100644 index 0000000000..898c2d4821 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0155-lantiq-VPE-nosmp.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/kernel/vpe-mt.c ++++ b/arch/mips/kernel/vpe-mt.c +@@ -132,7 +132,10 @@ int vpe_run(struct vpe *v) + * kernels need to turn it on, even if that wasn't the pre-dvpe() state. + */ + #ifdef CONFIG_SMP +- evpe(vpeflags); ++ if (!setup_max_cpus) /* nosmp is set */ ++ evpe(EVPE_ENABLE); ++ else ++ evpe(vpeflags); + #else + evpe(EVPE_ENABLE); + #endif diff --git a/target/linux/lantiq/patches-5.4/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-5.4/0160-owrt-lantiq-multiple-flash.patch new file mode 100644 index 0000000000..796220b2bc --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0160-owrt-lantiq-multiple-flash.patch @@ -0,0 +1,220 @@ +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -36,13 +37,16 @@ enum { + LTQ_NOR_NORMAL + }; + ++#define MAX_RESOURCES 4 ++ + struct ltq_mtd { +- struct resource *res; +- struct mtd_info *mtd; +- struct map_info *map; ++ struct mtd_info *mtd[MAX_RESOURCES]; ++ struct mtd_info *cmtd; ++ struct map_info map[MAX_RESOURCES]; + }; + + static const char ltq_map_name[] = "ltq_nor"; ++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; + + static map_word + ltq_read16(struct map_info *map, unsigned long adr) +@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign + } + + static int ++ltq_mtd_remove(struct platform_device *pdev) ++{ ++ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); ++ int i; ++ ++ if (ltq_mtd == NULL) ++ return 0; ++ ++ if (ltq_mtd->cmtd) { ++ mtd_device_unregister(ltq_mtd->cmtd); ++ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) ++ mtd_concat_destroy(ltq_mtd->cmtd); ++ } ++ ++ for (i = 0; i < MAX_RESOURCES; i++) { ++ if (ltq_mtd->mtd[i] != NULL) ++ map_destroy(ltq_mtd->mtd[i]); ++ } ++ ++ kfree(ltq_mtd); ++ ++ return 0; ++} ++ ++static int + ltq_mtd_probe(struct platform_device *pdev) + { + struct ltq_mtd *ltq_mtd; + struct cfi_private *cfi; +- int err; ++ int err = 0; ++ int i; ++ int devices_found = 0; ++ ++ static const char *rom_probe_types[] = { ++ "cfi_probe", "jedec_probe", NULL ++ }; ++ const char **type; + + ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL); + if (!ltq_mtd) +@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd + + platform_set_drvdata(pdev, ltq_mtd); + +- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!ltq_mtd->res) { +- dev_err(&pdev->dev, "failed to get memory resource\n"); +- return -ENOENT; ++ for (i = 0; i < pdev->num_resources; i++) { ++ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", ++ (unsigned long long)resource_size(&pdev->resource[i]), ++ (unsigned long long)pdev->resource[i].start); ++ ++ if (!devm_request_mem_region(&pdev->dev, ++ pdev->resource[i].start, ++ resource_size(&pdev->resource[i]), ++ dev_name(&pdev->dev))) { ++ dev_err(&pdev->dev, "Could not reserve memory region\n"); ++ return -ENOMEM; ++ } ++ ++ ltq_mtd->map[i].name = ltq_map_name; ++ ltq_mtd->map[i].bankwidth = 2; ++ ltq_mtd->map[i].read = ltq_read16; ++ ltq_mtd->map[i].write = ltq_write16; ++ ltq_mtd->map[i].copy_from = ltq_copy_from; ++ ltq_mtd->map[i].copy_to = ltq_copy_to; ++ ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map[i].phys = NO_XIP; ++ else ++ ltq_mtd->map[i].phys = pdev->resource[i].start; ++ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); ++ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, ++ ltq_mtd->map[i].size); ++ if (IS_ERR(ltq_mtd->map[i].virt)) ++ return PTR_ERR(ltq_mtd->map[i].virt); ++ ++ if (ltq_mtd->map[i].virt == NULL) { ++ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); ++ err = PTR_ERR(ltq_mtd->map[i].virt); ++ goto err_out; ++ } ++ ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; ++ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) ++ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; ++ ++ if (!ltq_mtd->mtd[i]) { ++ dev_err(&pdev->dev, "probing failed\n"); ++ return -ENXIO; ++ } else { ++ devices_found++; ++ } ++ ++ ltq_mtd->mtd[i]->owner = THIS_MODULE; ++ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; ++ ++ cfi = ltq_mtd->map[i].fldrv_priv; ++ cfi->addr_unlock1 ^= 1; ++ cfi->addr_unlock2 ^= 1; + } + +- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), +- GFP_KERNEL); +- if (!ltq_mtd->map) +- return -ENOMEM; +- +- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) +- ltq_mtd->map->phys = NO_XIP; +- else +- ltq_mtd->map->phys = ltq_mtd->res->start; +- ltq_mtd->res->start; +- ltq_mtd->map->size = resource_size(ltq_mtd->res); +- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); +- if (IS_ERR(ltq_mtd->map->virt)) +- return PTR_ERR(ltq_mtd->map->virt); +- +- ltq_mtd->map->name = ltq_map_name; +- ltq_mtd->map->bankwidth = 2; +- ltq_mtd->map->read = ltq_read16; +- ltq_mtd->map->write = ltq_write16; +- ltq_mtd->map->copy_from = ltq_copy_from; +- ltq_mtd->map->copy_to = ltq_copy_to; +- +- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; +- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); +- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; +- +- if (!ltq_mtd->mtd) { +- dev_err(&pdev->dev, "probing failed\n"); +- return -ENXIO; ++ if (devices_found == 1) { ++ ltq_mtd->cmtd = ltq_mtd->mtd[0]; ++ } else if (devices_found > 1) { ++ /* ++ * We detected multiple devices. Concatenate them together. ++ */ ++ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); ++ if (ltq_mtd->cmtd == NULL) ++ err = -ENXIO; + } + +- ltq_mtd->mtd->dev.parent = &pdev->dev; +- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); +- +- cfi = ltq_mtd->map->fldrv_priv; +- cfi->addr_unlock1 ^= 1; +- cfi->addr_unlock2 ^= 1; ++ ltq_mtd->cmtd->dev.parent = &pdev->dev; ++ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); + +- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); ++ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); + if (err) { + dev_err(&pdev->dev, "failed to add partitions\n"); +- goto err_destroy; ++ goto err_out; + } + + return 0; + +-err_destroy: +- map_destroy(ltq_mtd->mtd); ++err_out: ++ ltq_mtd_remove(pdev); + return err; + } + +-static int +-ltq_mtd_remove(struct platform_device *pdev) +-{ +- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); +- +- if (ltq_mtd && ltq_mtd->mtd) { +- mtd_device_unregister(ltq_mtd->mtd); +- map_destroy(ltq_mtd->mtd); +- } +- return 0; +-} +- + static const struct of_device_id ltq_mtd_match[] = { + { .compatible = "lantiq,nor" }, + {}, diff --git a/target/linux/lantiq/patches-5.4/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-5.4/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch new file mode 100644 index 0000000000..d153c521d3 --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -39,7 +39,7 @@ + /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ + + // debugging, turns off buffer write mode if set to 1 +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + /* Intel chips */ + #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..1beef0e1fe --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -422,6 +422,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -585,4 +599,6 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); + } + usb_set_clock(); ++ ++ set_phy_clock_source(np_cgu); + } diff --git a/target/linux/lantiq/patches-5.4/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-5.4/0701-NET-lantiq-etop-of-mido.patch new file mode 100644 index 0000000000..2cc541ae3c --- /dev/null +++ b/target/linux/lantiq/patches-5.4/0701-NET-lantiq-etop-of-mido.patch @@ -0,0 +1,37 @@ +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + +@@ -553,7 +554,8 @@ static int + ltq_etop_mdio_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int err; ++ struct device_node *mdio_np = NULL; ++ int err, ret; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { +@@ -573,7 +575,15 @@ ltq_etop_mdio_init(struct net_device *de + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +- if (mdiobus_register(priv->mii_bus)) { ++ ++ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); ++ ++ if (mdio_np) ++ ret = of_mdiobus_register(priv->mii_bus, mdio_np); ++ else ++ ret = mdiobus_register(priv->mii_bus); ++ ++ if (ret) { + err = -ENXIO; + goto err_out_free_mdiobus; + } diff --git a/target/linux/lantiq/base-files/etc/board.d/01_leds b/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds similarity index 80% rename from target/linux/lantiq/base-files/etc/board.d/01_leds rename to target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds index 4476a7eb43..b4d26d37ff 100755 --- a/target/linux/lantiq/base-files/etc/board.d/01_leds +++ b/target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds @@ -1,7 +1,6 @@ #!/bin/sh # # Copyright (C) 2011-2015 OpenWrt.org -# based on ar71xx # . /lib/functions/leds.sh @@ -32,38 +31,9 @@ led_dsl="$(get_dt_led dsl)" board=$(board_name) case "$board" in -allnet,all0333cj) - ucidef_set_led_netdev "lan" "lan" "all0333cj:green:lan" "eth0.1" - ;; -arcadyan,arv4525pw) - ucidef_set_led_netdev "wifi" "wifi" "arv4525pw:green:wlan" "wlan0" - ;; -arcadyan,arv7506pw11) - ucidef_set_led_wlan "wifi" "wifi" "arv7506pw11:green:wlan" "phy0radio" - ;; arcadyan,arv7519rw22) ucidef_set_led_netdev "lan" "lan" "arv7519rw22:green:lan" "eth0.1" ;; -arcadyan,arv752dpw22) - ucidef_set_led_wlan "wifi" "wifi" "arv752dpw22:red:wifi" "phy0radio" - ;; -bt,homehub-v5a) - ucidef_set_led_default "dimmed" "dimmed" "dimmed" "0" - ;; -netgear,dm200) - ucidef_set_led_netdev "lan" "lan" "dm200:green:lan" "eth0" - ;; -avm,fritz3370-rev2-hynix|\ -avm,fritz3370-rev2-micron) - ucidef_set_led_switch "lan" "LAN" "fritz3370:green:lan" "switch0" "0x17" - ;; -avm,fritz7320) - ucidef_set_led_netdev "wifi" "wifi" "fritz7320:green:wlan" "wlan0" - ;; -zyxel,p-2812hnu-f1|\ -zyxel,p-2812hnu-f3) - ucidef_set_led_wlan "wifi" "wifi" "p2812hnufx:green:wlan" "phy0radio" - ;; arcadyan,vgv7510kw22-nor|\ arcadyan,vgv7510kw22-brn) ucidef_set_led_wlan "wifi" "wifi" "vgv7510kw22:green:wlan" "phy0radio" @@ -72,6 +42,13 @@ arcadyan,vgv7519-nor|\ arcadyan,vgv7519-brn) ucidef_set_led_wlan "wifi" "wifi" "vgv7519:green:wireless" "phy0radio" ;; +avm,fritz3370-rev2-hynix|\ +avm,fritz3370-rev2-micron) + ucidef_set_led_switch "lan" "LAN" "fritz3370:green:lan" "switch0" "0x17" + ;; +bt,homehub-v5a) + ucidef_set_led_default "dimmed" "dimmed" "dimmed" "0" + ;; buffalo,wbmr-300hpd) ucidef_set_led_switch "lan1" "LAN1" "wbmr300:green:lan1" "switch0" "0x08" ucidef_set_led_switch "lan2" "LAN2" "wbmr300:green:lan2" "switch0" "0x04" @@ -79,7 +56,12 @@ buffalo,wbmr-300hpd) ucidef_set_led_switch "lan3" "LAN3" "wbmr300:green:lan3" "switch0" "0x20" ucidef_set_led_default "router" "router" "wbmr300:green:router" "1" ;; -*) +netgear,dm200) + ucidef_set_led_netdev "lan" "lan" "dm200:green:lan" "eth0" + ;; +zyxel,p-2812hnu-f1|\ +zyxel,p-2812hnu-f3) + ucidef_set_led_wlan "wifi" "wifi" "p2812hnufx:green:wlan" "phy0radio" ;; esac diff --git a/target/linux/lantiq/xrx200/base-files/etc/board.d/02_network b/target/linux/lantiq/xrx200/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..f39898263d --- /dev/null +++ b/target/linux/lantiq/xrx200/base-files/etc/board.d/02_network @@ -0,0 +1,175 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh +. /lib/functions/lantiq.sh + +lantiq_setup_interfaces() +{ + local board="$1" + + case "$board" in + alphanetworks,asl56026) + ucidef_add_switch "switch0" \ + "2:lan" "3:lan" "6t@eth0" + ;; + arcadyan,arv7519rw22) + ucidef_add_switch "switch0" \ + "0:lan:5" "2:lan:3" "3:lan:4" "4:lan:1" "5:lan:2" "6t@eth0" + ;; + arcadyan,vg3503j) + ucidef_add_switch "switch0" \ + "2:lan:2" "4:lan:1" "6t@eth0" + ;; + arcadyan,vgv7510kw22-brn|\ + arcadyan,vgv7510kw22-nor) + ucidef_add_switch "switch0" \ + "2:lan:2" "3:lan:1" "4:lan:4" "5:lan:3" "0:wan:5" "6t@eth0" + ;; + arcadyan,vgv7519-brn|\ + arcadyan,vgv7519-nor|\ + lantiq,easy80920-nand|\ + lantiq,easy80920-nor) + ucidef_add_switch "switch0" \ + "0:lan:4" "1:lan:3" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0" + ;; + avm,fritz3370-rev2-hynix|\ + avm,fritz3370-rev2-micron|\ + avm,fritz7360sl|\ + avm,fritz7362sl) + ucidef_add_switch "switch0" \ + "0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "6t@eth0" + ;; + bt,homehub-v5a) + ucidef_add_switch "switch0" \ + "0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0" + ;; + buffalo,wbmr-300hpd) + ucidef_add_switch "switch0" \ + "5:lan:2" "2:lan:3" "3:lan:4" "4:wan:1" "6t@eth0" + ;; + tplink,tdw8970|\ + tplink,tdw8980) + ucidef_add_switch "switch0" \ + "0:lan:2" "2:lan:3" "4:lan:4" "5:lan:1" "6t@eth0" + ;; + tplink,vr200|\ + tplink,vr200v) + ucidef_add_switch "switch0" \ + "0:lan" "2:lan" "4:lan" "5:lan" "6t@eth0" + ;; + zyxel,p-2812hnu-f1|\ + zyxel,p-2812hnu-f3) + ucidef_add_switch "switch0" \ + "0:lan" "1:lan" "2:lan" "4:lan" "5:wan" "6t@eth0" + ;; + *) + ucidef_set_interface_lan 'eth0' + ;; + esac +} + +lantiq_setup_dsl() +{ + local board="$1" + local annex="a" + + case "$board" in + arcadyan,vgv7510kw22-brn|\ + arcadyan,vgv7510kw22-nor|\ + avm,fritz3370-rev2-hynix|\ + avm,fritz3370-rev2-micron|\ + avm,fritz7360sl|\ + avm,fritz7362sl|\ + avm,fritz7412) + annex="b" + ;; + esac + + lantiq_setup_dsl_helper "$annex" +} + +lantiq_setup_macs() +{ + local board="$1" + local lan_mac="" + local wan_mac="" + + case "$board" in + alphanetworks,asl56026) + lan_mac=$(mtd_get_mac_ascii uboot_env ethaddr) + wan_mac=$(mtd_get_mac_ascii uboot_env wanmac) + ;; + arcadyan,arv7519rw22) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary boardconfig 0x16)" 1) + ;; + arcadyan,vg3503j|\ + lantiq,easy80920-nand|\ + lantiq,easy80920-nor|\ + zyxel,p-2812hnu-f1|\ + zyxel,p-2812hnu-f3) + lan_mac=$(mtd_get_mac_ascii uboot-env ethaddr) + wan_mac=$(macaddr_add "$lan_mac" 1) + ;; + arcadyan,vgv7510kw22-brn|\ + arcadyan,vgv7510kw22-nor) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary board_config 0x16)" 2) + ;; + arcadyan,vgv7519-brn|\ + arcadyan,vgv7519-nor) + wan_mac=$(mtd_get_mac_binary board_config 0x16) + ;; + avm,fritz3370-rev2-hynix|\ + avm,fritz3370-rev2-micron) + lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) + wan_mac=$(macaddr_add "$lan_mac" 3) + ;; + avm,fritz7360sl) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary urlader 0xa91)" 1) + ;; + avm,fritz7362sl) + lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) + wan_mac=$(fritz_tffs -n macdsl -i $(find_mtd_part "tffs (1)")) + ;; + avm,fritz7412) + tffsdev=$(find_mtd_chardev "nand-tffs") + lan_mac=$(/usr/bin/fritz_tffs_nand -d $tffsdev -n maca -o) + wan_mac=$(/usr/bin/fritz_tffs_nand -d $tffsdev -n macdsl -o) + ;; + bt,homehub-v5a) + lan_mac=$(mtd_get_mac_binary_ubi caldata 0x110c) + wan_mac=$(macaddr_add "$lan_mac" 1) + ;; + buffalo,wbmr-300hpd) + lan_mac=$(mtd_get_mac_ascii ubootconfig ethaddr) + wan_mac="$lan_mac" + ;; + netgear,dm200) + lan_mac=$(mtd_get_mac_binary ART 0x0) + wan_mac=$(macaddr_add "$lan_mac" 1) + ;; + tplink,tdw8970|\ + tplink,tdw8980) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary boardconfig 0xf100)" 1) + ;; + tplink,vr200|\ + tplink,vr200v) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary romfile 0xf100)" 1) + ;; + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" "$lan_mac" + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" +} + +board_config_update +board=$(board_name) +lantiq_setup_interfaces $board +lantiq_setup_dsl $board +lantiq_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/11-ath10k-caldata similarity index 100% rename from target/linux/lantiq/base-files/etc/hotplug.d/firmware/11-ath10k-caldata rename to target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/11-ath10k-caldata diff --git a/target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom b/target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom new file mode 100644 index 0000000000..cb91237400 --- /dev/null +++ b/target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom @@ -0,0 +1,161 @@ +#!/bin/sh +# Based on ar71xx 10-ath9k-eeprom + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/functions.sh +. /lib/functions/system.sh +. /lib/upgrade/nand.sh + +# xor multiple hex values of the same length +xor() { + local val + local ret="0x$1" + local retlen=${#1} + + shift + while [ -n "$1" ]; do + val="0x$1" + ret=$((ret ^ val)) + shift + done + + printf "%0${retlen}x" "$ret" +} + +ath9k_eeprom_die() { + echo "ath9k eeprom: $*" + exit 1 +} + +ath9k_eeprom_extract_raw() { + local source=$1 + local offset=$2 + local swap=$3 + local size=4096 + local bs=1 + local conv= + + if [ $swap -gt 0 ]; then + bs=2 + conv="conv=swab" + size=$((size / bs)) + offset=$((offset / bs)) + fi + + dd if=$source of=/lib/firmware/$FIRMWARE bs=$bs skip=$offset count=$size $conv 2>/dev/null || \ + ath9k_eeprom_die "failed to extract from $mtd" +} + +ath9k_eeprom_extract_reverse() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + local reversed + local caldata + + mtd=$(find_mtd_chardev "$part") + reversed=$(hexdump -v -s $offset -n $count -e '/1 "%02x "' $mtd) + + for byte in $reversed; do + caldata="\x${byte}${caldata}" + done + + printf "%b" "$caldata" > /lib/firmware/$FIRMWARE +} + +ath9k_eeprom_extract() { + local part=$1 + local offset=$2 + local swap=$3 + local mtd + + mtd=$(find_mtd_chardev $part) + [ -n "$mtd" ] || \ + ath9k_eeprom_die "no mtd device found for partition $part" + + ath9k_eeprom_extract_raw $mtd $offset $swap +} + +ath9k_ubi_eeprom_extract() { + local part=$1 + local offset=$2 + local swap=$3 + local ubidev=$(nand_find_ubi $CI_UBIPART) + local ubi + + ubi=$(nand_find_volume $ubidev $part) + [ -n "$ubi" ] || \ + ath9k_eeprom_die "no UBI volume found for $part" + + ath9k_eeprom_extract_raw /dev/$ubi $offset $swap +} + +ath9k_patch_fw_mac_crc() { + local mac=$1 + local mac_offset=$2 + local chksum_offset=$((mac_offset - 10)) + + ath9k_patch_fw_mac "${mac}" "${mac_offset}" "${chksum_offset}" +} + +ath9k_patch_fw_mac() { + local mac=$1 + local mac_offset=$2 + local chksum_offset=$3 + local xor_mac + local xor_fw_mac + local xor_fw_chksum + + [ -z "$mac" -o -z "$mac_offset" ] && return + + [ -n "$chksum_offset" ] && { + xor_mac=${mac//:/} + xor_mac="${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}" + + xor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE) + xor_fw_mac="${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}" + + xor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE) + xor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac) + + printf "%b" "\x${xor_fw_chksum:0:2}\x${xor_fw_chksum:2:2}" | \ + dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=$chksum_offset count=2 + } + + macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=$mac_offset count=6 +} + +case "$FIRMWARE" in + "ath9k-eeprom-pci-0000:00:0e.0.bin" | \ + "ath9k-eeprom-pci-0000:01:00.0.bin" | \ + "ath9k-eeprom-pci-0000:02:00.0.bin") + board=$(board_name) + + case "$board" in + avm,fritz3370-rev2-hynix|\ + avm,fritz3370-rev2-micron|\ + avm,fritz7362sl) + ath9k_eeprom_extract_reverse "urlader" 5441 1088 + ;; + avm,fritz7360sl) + ath9k_eeprom_extract "urlader" 2437 0 + ;; + avm,fritz7412) + /usr/bin/fritz_cal_extract -i 1 -s 0x1e000 -e 0x207 -l 4096 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader") + ;; + bt,homehub-v5a) + ath9k_ubi_eeprom_extract "caldata" 4096 0 + ath9k_patch_fw_mac_crc $(macaddr_add $(mtd_get_mac_binary_ubi caldata 4364) +2) 268 + ;; + tplink,tdw8970|\ + tplink,tdw8980) + ath9k_eeprom_extract "boardconfig" 135168 0 + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/lantiq/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh similarity index 91% rename from target/linux/lantiq/base-files/lib/upgrade/platform.sh rename to target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh index c47ff78fb2..dcd797c30d 100755 --- a/target/linux/lantiq/base-files/lib/upgrade/platform.sh +++ b/target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh @@ -13,8 +13,6 @@ platform_do_upgrade() { avm,fritz3370-rev2-micron|\ avm,fritz7362sl|\ avm,fritz7412|\ - bt,homehub-v2b|\ - bt,homehub-v3a|\ bt,homehub-v5a|\ zyxel,p-2812hnu-f1|\ zyxel,p-2812hnu-f3) diff --git a/target/linux/lantiq/xrx200/config-5.4 b/target/linux/lantiq/xrx200/config-5.4 new file mode 100644 index 0000000000..cad6ebf1ae --- /dev/null +++ b/target/linux/lantiq/xrx200/config-5.4 @@ -0,0 +1,106 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HWMON=y +CONFIG_ICPLUS_PHY=y +CONFIG_IFX_VPE_EXT=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INTEL_XWAY_PHY=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_XRX200_LEGACY=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_FPAFF is not set +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +CONFIG_MIPS_VPE_APSP_API=y +CONFIG_MIPS_VPE_APSP_API_MT=y +CONFIG_MIPS_VPE_LOADER=y +CONFIG_MIPS_VPE_LOADER_MT=y +CONFIG_MIPS_VPE_LOADER_TOM=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NR_CPUS=2 +CONFIG_PADATA=y +CONFIG_PCI=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_LANTIQ=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PHY_LANTIQ_VRX200_PCIE=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8367B_PHY=y +CONFIG_RTL8367_PHY=y +CONFIG_SENSORS_LTQ_CPUTEMP=y +CONFIG_SGL_ALLOC=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SWCONFIG_LEDS=y +CONFIG_SYNC_R4K=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_SUPPORT=y +CONFIG_XPS=y +CONFIG_XRX200_PHY_FW=y +CONFIG_XXHASH=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway/base-files/etc/board.d/01_leds b/target/linux/lantiq/xway/base-files/etc/board.d/01_leds new file mode 100755 index 0000000000..82a39f4648 --- /dev/null +++ b/target/linux/lantiq/xway/base-files/etc/board.d/01_leds @@ -0,0 +1,44 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/leds.sh +. /lib/functions/uci-defaults.sh + +board_config_update + +led_wifi="$(get_dt_led wifi)" +[ -n "$led_wifi" ] && ucidef_set_led_wlan "wifi" "wifi" "$led_wifi" "phy0tpt" + +led_usb="$(get_dt_led usb)" +[ -n "$led_usb" ] && ucidef_set_led_usbdev "usb" "usb" "$led_usb" "1-1" + +led_usb2="$(get_dt_led usb2)" +[ -n "$led_usb2" ] && ucidef_set_led_usbdev "usb2" "usb2" "$led_usb2" "2-1" + +led_dsl="$(get_dt_led dsl)" +[ -n "$led_dsl" ] && { + led_internet="$(get_dt_led internet)" + if [ -n "$led_internet" ]; then + ucidef_set_led_default "dsl" "dsl" "$led_dsl" "0" + ucidef_set_led_netdev "internet" "internet" "$led_internet" "pppoe-wan" + else + ucidef_set_led_netdev "dsl" "dsl" "$led_dsl" "dsl0" + fi +} + +board=$(board_name) + +case "$board" in +arcadyan,arv7506pw11) + ucidef_set_led_wlan "wifi" "wifi" "arv7506pw11:green:wlan" "phy0radio" + ;; +arcadyan,arv752dpw22) + ucidef_set_led_wlan "wifi" "wifi" "arv752dpw22:red:wifi" "phy0radio" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/xway/base-files/etc/board.d/02_network b/target/linux/lantiq/xway/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..89368d8bfb --- /dev/null +++ b/target/linux/lantiq/xway/base-files/etc/board.d/02_network @@ -0,0 +1,118 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh +. /lib/functions/lantiq.sh + +lantiq_setup_interfaces() +{ + local board="$1" + + case "$board" in + arcadyan,arv4510pw) + ucidef_add_switch "switch0" \ + "0:lan:4" "2:lan:2" "1:lan:3" "3:lan:1" "5t@eth0" + ;; + arcadyan,arv4519pw|\ + arcadyan,arv7510pw22|\ + arcadyan,arv7518pw|\ + arcadyan,arv752dpw22|\ + arcadyan,arv8539pw22|\ + buffalo,wbmr-hp-g300h) + ucidef_add_switch "switch0" \ + "0t@eth0" "2:lan" "3:lan" "4:lan" "5:lan" + ;; + arcadyan,arv7506pw11|\ + audiocodes,mp-252|\ + siemens,gigaset-sx76x) + ucidef_add_switch "switch0" \ + "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5t@eth0" + ;; + arcadyan,arv7519pw|\ + zte,h201l) + ucidef_add_switch "switch0" \ + "0:lan" "1:lan" "2:lan" "3:lan" "4t@eth0" + ;; + bt,homehub-v2b) + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "5t@eth0" + ;; + netgear,dgn3500|\ + netgear,dgn3500b) + ucidef_add_switch "switch0" \ + "0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5t@eth0" + ;; + zyxel,p-2601hn) + ucidef_add_switch "switch0" \ + "0:lan" "1:lan" "2:lan" "3:lan" "5t@eth0" + ;; + *) + ucidef_set_interface_lan 'eth0' + ;; + esac +} + +lantiq_setup_dsl() +{ + local board="$1" + local annex="a" + + case "$board" in + arcadyan,arv7506pw11|\ + arcadyan,arv7525pw|\ + arcadyan,arv752dpw|\ + arcadyan,arv752dpw22|\ + arcadyan,arv8539pw22|\ + avm,fritz7312|\ + avm,fritz7320|\ + siemens,gigaset-sx76x|\ + zte,h201l) + annex="b" + ;; + esac + + lantiq_setup_dsl_helper "$annex" +} + +lantiq_setup_macs() +{ + local board="$1" + local lan_mac="" + local wan_mac="" + + case "$board" in + arcadyan,arv4510pw|\ + bt,homehub-v2b|\ + bt,homehub-v3a|\ + netgear,dgn3500|\ + netgear,dgn3500b) + lan_mac=$(mtd_get_mac_ascii uboot-env ethaddr) + wan_mac=$(macaddr_add "$lan_mac" 1) + ;; + arcadyan,arv7506pw11) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary board_config 0x16)" 2) + ;; + arcadyan,arv7519pw) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary board_config 0x16)" 1) + ;; + avm,fritz7312|\ + avm,fritz7320) + wan_mac=$(macaddr_add "$(mtd_get_mac_binary urlader 0xa91)" 1) + ;; + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" "$lan_mac" + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" +} + +board_config_update +board=$(board_name) +lantiq_setup_interfaces $board +lantiq_setup_dsl $board +lantiq_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom b/target/linux/lantiq/xway/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom similarity index 86% rename from target/linux/lantiq/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom rename to target/linux/lantiq/xway/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom index 6ae5e3cfe9..a5ffa918f5 100644 --- a/target/linux/lantiq/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom +++ b/target/linux/lantiq/xway/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom @@ -148,28 +148,13 @@ case "$FIRMWARE" in ath9k_eeprom_extract "art-copy" 0 1 ath9k_patch_fw_mac_crc $(macaddr_add $(mtd_get_mac_ascii uboot_env ethaddr) +2) 268 ;; - bt,homehub-v5a) - ath9k_ubi_eeprom_extract "caldata" 4096 0 - ath9k_patch_fw_mac_crc $(macaddr_add $(mtd_get_mac_binary_ubi caldata 4364) +2) 268 - ;; netgear,dgn3500|netgear,dgn3500b) ath9k_eeprom_extract "calibration" 61440 0 ath9k_patch_fw_mac_crc $(macaddr_add $(mtd_get_mac_ascii uboot-env ethaddr) +2) 524 ;; - avm,fritz3370-rev2-hynix|\ - avm,fritz3370-rev2-micron|\ - avm,fritz7362sl) - ath9k_eeprom_extract_reverse "urlader" 5441 1088 - ;; - avm,fritz7312|avm,fritz7320|avm,fritz7360sl) + avm,fritz7312|avm,fritz7320) ath9k_eeprom_extract "urlader" 2437 0 ;; - avm,fritz7412) - /usr/bin/fritz_cal_extract -i 1 -s 0x1e000 -e 0x207 -l 4096 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader") - ;; - tplink,tdw8970|tplink,tdw8980) - ath9k_eeprom_extract "boardconfig" 135168 0 - ;; *) ath9k_eeprom_die "board $board is not supported yet" ;; diff --git a/target/linux/lantiq/xway/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/xway/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000000..5ef0a0ddb9 --- /dev/null +++ b/target/linux/lantiq/xway/base-files/lib/upgrade/platform.sh @@ -0,0 +1,20 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +platform_check_image() { + return 0 +} + +platform_do_upgrade() { + local board=$(board_name) + + case "$board" in + bt,homehub-v2b|\ + bt,homehub-v3a) + nand_do_upgrade $1 + ;; + *) + default_do_upgrade "$1" + ;; + esac +} diff --git a/target/linux/lantiq/xway/config-4.19 b/target/linux/lantiq/xway/config-4.19 index 64a6c55832..6075cec522 100644 --- a/target/linux/lantiq/xway/config-4.19 +++ b/target/linux/lantiq/xway/config-4.19 @@ -6,7 +6,6 @@ CONFIG_CRC16=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y -CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_POLLDEV=y @@ -26,9 +25,6 @@ CONFIG_MTD_UBI_BLOCK=y # CONFIG_MTD_UBI_GLUEBI is not set CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_NLS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y CONFIG_PCI=y # CONFIG_PCIE_LANTIQ is not set CONFIG_PCI_DOMAINS=y diff --git a/target/linux/lantiq/xway/config-5.4 b/target/linux/lantiq/xway/config-5.4 new file mode 100644 index 0000000000..16e9de8f95 --- /dev/null +++ b/target/linux/lantiq/xway/config-5.4 @@ -0,0 +1,47 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_NAND_XWAY=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NLS=y +CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8367B_PHY=y +CONFIG_RTL8367_PHY=y +CONFIG_SGL_ALLOC=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +# CONFIG_UBIFS_FS_ZLIB is not set +# CONFIG_UBIFS_FS_ZSTD is not set +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_SUPPORT=y diff --git a/target/linux/lantiq/xway_legacy/base-files/etc/board.d/01_leds b/target/linux/lantiq/xway_legacy/base-files/etc/board.d/01_leds new file mode 100755 index 0000000000..4200dcb0c8 --- /dev/null +++ b/target/linux/lantiq/xway_legacy/base-files/etc/board.d/01_leds @@ -0,0 +1,41 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/leds.sh +. /lib/functions/uci-defaults.sh + +board_config_update + +led_wifi="$(get_dt_led wifi)" +[ -n "$led_wifi" ] && ucidef_set_led_wlan "wifi" "wifi" "$led_wifi" "phy0tpt" + +led_usb="$(get_dt_led usb)" +[ -n "$led_usb" ] && ucidef_set_led_usbdev "usb" "usb" "$led_usb" "1-1" + +led_usb2="$(get_dt_led usb2)" +[ -n "$led_usb2" ] && ucidef_set_led_usbdev "usb2" "usb2" "$led_usb2" "2-1" + +led_dsl="$(get_dt_led dsl)" +[ -n "$led_dsl" ] && { + led_internet="$(get_dt_led internet)" + if [ -n "$led_internet" ]; then + ucidef_set_led_default "dsl" "dsl" "$led_dsl" "0" + ucidef_set_led_netdev "internet" "internet" "$led_internet" "pppoe-wan" + else + ucidef_set_led_netdev "dsl" "dsl" "$led_dsl" "dsl0" + fi +} + +board=$(board_name) + +case "$board" in +arcadyan,arv4525pw) + ucidef_set_led_netdev "wifi" "wifi" "arv4525pw:green:wlan" "wlan0" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/xway_legacy/base-files/etc/board.d/02_network b/target/linux/lantiq/xway_legacy/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..c29beb832d --- /dev/null +++ b/target/linux/lantiq/xway_legacy/base-files/etc/board.d/02_network @@ -0,0 +1,61 @@ +#!/bin/sh +# +# Copyright (C) 2011-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh +. /lib/functions/lantiq.sh + +lantiq_setup_interfaces() +{ + local board="$1" + + case "$board" in + arcadyan,arv4520pw) + ucidef_add_switch "switch0" \ + "0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5t@eth0" + ;; + *) + ucidef_set_interface_lan 'eth0' + ;; + esac +} + +lantiq_setup_dsl() +{ + local board="$1" + local annex="a" + + case "$board" in + arcadyan,arv4520pw|\ + arcadyan,arv4525pw|\ + arcadyan,arv452cqw) + annex="b" + ;; + esac + + lantiq_setup_dsl_helper "$annex" +} + +lantiq_setup_macs() +{ + local board="$1" + local lan_mac="" + local wan_mac="" + + case "$board" in + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" "$lan_mac" + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" "$wan_mac" +} + +board_config_update +board=$(board_name) +lantiq_setup_interfaces $board +lantiq_setup_dsl $board +lantiq_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/lantiq/xway_legacy/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/xway_legacy/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000000..d088601bb0 --- /dev/null +++ b/target/linux/lantiq/xway_legacy/base-files/lib/upgrade/platform.sh @@ -0,0 +1,10 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +platform_check_image() { + return 0 +} + +platform_do_upgrade() { + default_do_upgrade "$1" +} diff --git a/target/linux/lantiq/xway_legacy/config-4.19 b/target/linux/lantiq/xway_legacy/config-4.19 index feb82c5fcf..c4042f147f 100644 --- a/target/linux/lantiq/xway_legacy/config-4.19 +++ b/target/linux/lantiq/xway_legacy/config-4.19 @@ -5,7 +5,6 @@ CONFIG_CRC16=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y -CONFIG_FIRMWARE_IN_KERNEL=y # CONFIG_GPIO_SYSFS is not set # CONFIG_HW_RANDOM is not set CONFIG_INPUT=y @@ -18,9 +17,6 @@ CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y # CONFIG_MTD_PHYSMAP_OF is not set CONFIG_NLS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y CONFIG_PCI=y # CONFIG_PCIE_LANTIQ is not set CONFIG_PCI_DOMAINS=y diff --git a/target/linux/lantiq/xway_legacy/config-5.4 b/target/linux/lantiq/xway_legacy/config-5.4 new file mode 100644 index 0000000000..1d1c2f187c --- /dev/null +++ b/target/linux/lantiq/xway_legacy/config-5.4 @@ -0,0 +1,37 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_BLK_MQ_PCI=y +CONFIG_CRC16=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +# CONFIG_GPIO_SYSFS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_ETOP=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_NLS=y +CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8367B_PHY=y +CONFIG_RTL8367_PHY=y +CONFIG_SGL_ALLOC=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_SUPPORT=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/malta/Makefile b/target/linux/malta/Makefile index c71f34d109..cab5d76b1d 100644 --- a/target/linux/malta/Makefile +++ b/target/linux/malta/Makefile @@ -12,12 +12,14 @@ CPU_TYPE:=24kc SUBTARGETS:=le be le64 be64 INITRAMFS_EXTRA_FILES:= MAINTAINER:=Florian Fainelli -FEATURES:=ramdisk +FEATURES:=cpiogz ext4 ramdisk squashfs targz + +KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 -KERNEL_PATCHVER:=4.14 include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES += wpad-basic kmod-mac80211-hwsim kmod-pcnet32 +DEFAULT_PACKAGES += wpad-basic kmod-mac80211-hwsim kmod-pcnet32 mkf2fs e2fsprogs $(eval $(call BuildTarget)) diff --git a/target/linux/malta/be/config-default b/target/linux/malta/be/config-default index f51301a058..5586be6b7c 100644 --- a/target/linux/malta/be/config-default +++ b/target/linux/malta/be/config-default @@ -1,3 +1,4 @@ CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGHMEM=y diff --git a/target/linux/malta/be64/config-default b/target/linux/malta/be64/config-default index 2c0c9d2db9..3792b7fce8 100644 --- a/target/linux/malta/be64/config-default +++ b/target/linux/malta/be64/config-default @@ -1,13 +1,10 @@ # CONFIG_32BIT is not set CONFIG_64BIT=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_MMAP_RND_BITS=12 +CONFIG_ARCH_MMAP_RND_BITS_MAX=18 +CONFIG_ARCH_MMAP_RND_BITS_MIN=12 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y -CONFIG_BINFMT_ELF32=y -CONFIG_BLOCK_COMPAT=y -CONFIG_COMPAT=y -CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_CPU_MIPS64=y @@ -17,15 +14,16 @@ CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HUGEPAGES=y CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y # CONFIG_HUGETLBFS is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_MIPS32_N32=y -CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +# CONFIG_MIPS32_O32 is not set +CONFIG_MIPS_EBPF_JIT=y # CONFIG_MIPS_VA_BITS_48 is not set CONFIG_MODULES_USE_ELF_RELA=y CONFIG_PCI_BUS_ADDR_T_64BIT=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_SYSVIPC_COMPAT=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_ZONE_DMA32=y diff --git a/target/linux/malta/config-4.19 b/target/linux/malta/config-4.19 new file mode 100644 index 0000000000..f66036e27b --- /dev/null +++ b/target/linux/malta/config-4.19 @@ -0,0 +1,336 @@ +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ATA=y +CONFIG_ATA_PIIX=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_DM is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BOARD_SCACHE=y +CONFIG_BOOT_ELF32=y +CONFIG_BOUNCE=y +CONFIG_BUILTIN_DTB=y +CONFIG_CDROM=y +CONFIG_CEVT_R4K=y +CONFIG_CLKBLD_I8253=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKEVT_I8253=y +CONFIG_CLKSRC_I8253=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_BOSTON is not set +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +# CONFIG_CPU_HAS_SMARTMIPS is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_3_5_FEATURES is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS32_R5_FEATURES is not set +# CONFIG_CPU_MIPS32_R6 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_MIPS64_R6 is not set +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +# CONFIG_CPU_NEVADA is not set +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_DIRECT_OPS=y +CONFIG_DMA_MAYBE_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_NONCOHERENT_OPS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +# CONFIG_F2FS_CHECK_FS is not set +CONFIG_F2FS_FS=y +# CONFIG_F2FS_FS_SECURITY is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_STAT_FS=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_CBPF_JIT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_HAS_PCI=y +CONFIG_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_I8259=y +CONFIG_INPUT=y +# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_ISA_DMA_API=y +CONFIG_JBD2=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_KALLSYMS=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MD=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_BONITO64=y +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_MIPS_CMDLINE_FROM_DTB is not set +# CONFIG_MIPS_CMP is not set +CONFIG_MIPS_CPC=y +# CONFIG_MIPS_CPS is not set +CONFIG_MIPS_CPU_SCACHE=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_GIC=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 +CONFIG_MIPS_L1_CACHE_SHIFT_6=y +CONFIG_MIPS_MALTA=y +CONFIG_MIPS_MSC=y +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NO_APPENDED_DTB=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CFI_STAA=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_NET=y +CONFIG_PADATA=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PATA_LEGACY=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_PIIX4_POWEROFF=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_QUOTA_TREE=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RELAY=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_SCSI=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SRCU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y +CONFIG_SYS_HAS_CPU_MIPS32_R5=y +CONFIG_SYS_HAS_CPU_MIPS32_R6=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R6=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MIPS_CMP=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_RELOCATABLE=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USB_SUPPORT=y +# CONFIG_USERIO is not set +CONFIG_USE_OF=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VXFS_FS=y +CONFIG_XPS=y diff --git a/target/linux/malta/config-5.4 b/target/linux/malta/config-5.4 new file mode 100644 index 0000000000..37d3dbef9a --- /dev/null +++ b/target/linux/malta/config-5.4 @@ -0,0 +1,345 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DMA_COHERENCE_H=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ATA=y +CONFIG_ATA_PIIX=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_DM is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BOARD_SCACHE=y +CONFIG_BOOT_ELF32=y +CONFIG_BOUNCE=y +CONFIG_BUILTIN_DTB=y +CONFIG_CDROM=y +CONFIG_CEVT_R4K=y +CONFIG_CLKBLD_I8253=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKEVT_I8253=y +CONFIG_CLKSRC_I8253=y +CONFIG_CLKSRC_MIPS_GIC=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_BOSTON is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_LOAD_STORE_LR=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_CPU_HAS_SMARTMIPS is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_MICROMIPS is not set +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS32_R6 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_MIPS64_R6 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +# CONFIG_CPU_NEVADA is not set +CONFIG_CPU_R4K_CACHE_TLB=y +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_MAYBE_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EFI_EARLYCON=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +# CONFIG_F2FS_CHECK_FS is not set +CONFIG_F2FS_FS=y +# CONFIG_F2FS_FS_SECURITY is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_STAT_FS=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HW_CONSOLE=y +CONFIG_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_I8259=y +CONFIG_INPUT=y +# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_ISA_DMA_API=y +CONFIG_JBD2=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_KALLSYMS=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MD=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_BONITO64=y +CONFIG_MIPS_CLOCK_VSYSCALL=y +CONFIG_MIPS_CM=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_MIPS_CMDLINE_FROM_DTB is not set +# CONFIG_MIPS_CMP is not set +CONFIG_MIPS_CPC=y +# CONFIG_MIPS_CPS is not set +CONFIG_MIPS_CPU_SCACHE=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_EXTERNAL_TIMER=y +CONFIG_MIPS_GIC=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 +CONFIG_MIPS_L1_CACHE_SHIFT_6=y +CONFIG_MIPS_MALTA=y +CONFIG_MIPS_MSC=y +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NO_APPENDED_DTB=y +CONFIG_MIPS_NR_CPU_NR_MAP=2 +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CFI_STAA=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_NET=y +CONFIG_PADATA=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PATA_LEGACY=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_PIIX4_POWEROFF=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_QUOTA_TREE=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RELAY=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_JZ4740 is not set +CONFIG_SCSI=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SRCU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y +CONFIG_SYS_HAS_CPU_MIPS32_R5=y +CONFIG_SYS_HAS_CPU_MIPS32_R6=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R6=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MICROMIPS=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MIPS_CMP=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_RELOCATABLE=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TARGET_ISA_REV=1 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_USB_SUPPORT=y +# CONFIG_USERIO is not set +CONFIG_USE_OF=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VXFS_FS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y diff --git a/target/linux/malta/image/Makefile b/target/linux/malta/image/Makefile index d49d4a762d..72e7eab807 100644 --- a/target/linux/malta/image/Makefile +++ b/target/linux/malta/image/Makefile @@ -34,18 +34,21 @@ define Image/BuildKernel cp $(KDIR)/uImage.gz $(BIN_DIR)/$(IMG_PREFIX)-uImage-gzip endef -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) -endef - define Image/Build/Initramfs cp $(KDIR)/vmlinux-initramfs.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.elf cp $(KDIR)/vmlinux-initramfs $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.bin endef +define Image/Build/gzip + gzip -f9n $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img +endef + +$(eval $(call Image/gzip-ext4-padded-squashfs)) + define Image/Build $(call Image/Build/$(1)) - dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync + $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img + $(call Image/Build/gzip/$(1)) endef $(eval $(call BuildImage)) diff --git a/target/linux/malta/le/config-default b/target/linux/malta/le/config-default index aab569be3b..2b42a6b5b2 100644 --- a/target/linux/malta/le/config-default +++ b/target/linux/malta/le/config-default @@ -1,3 +1,4 @@ # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGHMEM=y diff --git a/target/linux/malta/le64/config-default b/target/linux/malta/le64/config-default index 28954537a9..ff4496382d 100644 --- a/target/linux/malta/le64/config-default +++ b/target/linux/malta/le64/config-default @@ -1,13 +1,10 @@ # CONFIG_32BIT is not set CONFIG_64BIT=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_MMAP_RND_BITS=12 +CONFIG_ARCH_MMAP_RND_BITS_MAX=18 +CONFIG_ARCH_MMAP_RND_BITS_MIN=12 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y -CONFIG_BINFMT_ELF32=y -CONFIG_BLOCK_COMPAT=y -CONFIG_COMPAT=y -CONFIG_COMPAT_NETLINK_MESSAGES=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64=y @@ -17,15 +14,16 @@ CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HUGEPAGES=y CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y # CONFIG_HUGETLBFS is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_MIPS32_N32=y -CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +# CONFIG_MIPS32_O32 is not set +CONFIG_MIPS_EBPF_JIT=y # CONFIG_MIPS_VA_BITS_48 is not set CONFIG_MODULES_USE_ELF_RELA=y CONFIG_PCI_BUS_ADDR_T_64BIT=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_SYSVIPC_COMPAT=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_ZONE_DMA32=y diff --git a/target/linux/sunxi/Makefile b/target/linux/sunxi/Makefile index e1630fb441..dd6785cfae 100644 --- a/target/linux/sunxi/Makefile +++ b/target/linux/sunxi/Makefile @@ -15,6 +15,7 @@ SUBTARGETS:=cortexa8 cortexa7 cortexa53 MAINTAINER:=Zoltan HERPAI KERNEL_PATCHVER:=4.19 +KERNEL_TESTING_PATCHVER:=5.4 KERNELNAME:=zImage dtbs # A10: Cortex-A8 diff --git a/target/linux/sunxi/config-5.4 b/target/linux/sunxi/config-5.4 new file mode 100644 index 0000000000..1e54e980a3 --- /dev/null +++ b/target/linux/sunxi/config-5.4 @@ -0,0 +1,589 @@ +# CONFIG_AHCI_SUNXI is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=416 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUNXI_MC_SMP=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +# CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM is not set +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CCI=y +CONFIG_ARM_CCI400_COMMON=y +CONFIG_ARM_CCI400_PORT_CTRL=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_643719=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_LPAE=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PMU=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATA=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_AXP20X_POWER=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_PM=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BOUNCE=y +CONFIG_CACHE_L2X0=y +CONFIG_CAN=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_SUNXI=y +CONFIG_CLK_SUNXI_CLOCKS=y +CONFIG_CLK_SUNXI_PRCM_SUN6I=y +CONFIG_CLK_SUNXI_PRCM_SUN8I=y +CONFIG_CLK_SUNXI_PRCM_SUN9I=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SHA1=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_SUN4I=y +CONFIG_DMA_SUN6I=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DWMAC_GENERIC=y +# CONFIG_DWMAC_SUN8I is not set +CONFIG_DWMAC_SUNXI=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_ELF_CORE=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_STAT_FS=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_FOREIGN_ENDIAN=y +CONFIG_FB_LITTLE_ENDIAN=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_TILEBLITTING=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAME_WARN=2048 +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQFD=y +CONFIG_HAVE_KVM_IRQ_BYPASS=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_SUN6I_P2WI=y +CONFIG_IIO=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_AXP20X_PEK=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_BYPASS_MANAGER=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KEYBOARD_SUN4I_LRADC=y +CONFIG_KSM=y +CONFIG_KVM=y +CONFIG_KVM_ARM_HOST=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_MMIO=y +CONFIG_KVM_VFIO=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_MACH_SUN4I=y +CONFIG_MACH_SUN5I=y +CONFIG_MACH_SUN6I=y +CONFIG_MACH_SUN7I=y +CONFIG_MACH_SUN8I=y +CONFIG_MACH_SUN9I=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_SUN4I=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_AXP20X=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SUN6I_PRCM=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SUNXI=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=8 +CONFIG_NVMEM=y +CONFIG_NVMEM_SUNXI_SID=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_SUN4I_USB=y +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +CONFIG_PHY_SUN9I_USB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AXP209=y +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN5I=y +CONFIG_PINCTRL_SUN6I_A31=y +CONFIG_PINCTRL_SUN6I_A31_R=y +CONFIG_PINCTRL_SUN8I_A23=y +CONFIG_PINCTRL_SUN8I_A23_R=y +CONFIG_PINCTRL_SUN8I_A33=y +CONFIG_PINCTRL_SUN8I_A83T=y +CONFIG_PINCTRL_SUN8I_A83T_R=y +CONFIG_PINCTRL_SUN8I_H3=y +CONFIG_PINCTRL_SUN8I_H3_R=y +CONFIG_PINCTRL_SUN8I_V3S=y +CONFIG_PINCTRL_SUN9I_A80=y +CONFIG_PINCTRL_SUN9I_A80_R=y +CONFIG_PINCTRL_SUNXI=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PWM=y +CONFIG_PWM_SUN4I=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REFCOUNT_FULL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_SY8106A=y +CONFIG_RELAY=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SATA_PMP=y +CONFIG_SCSI=y +CONFIG_SDIO_UART=y +CONFIG_SECURITYFS=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=8 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SND=y +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_PCM=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN8I_CODEC is not set +# CONFIG_SND_SUN8I_CODEC_ANALOG is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SUN4I=y +CONFIG_SPI_SUN6I=y +CONFIG_SRCU=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_SUN4I_A10_CCU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +CONFIG_SUN5I_CCU=y +CONFIG_SUN5I_HSTIMER=y +CONFIG_SUN6I_A31_CCU=y +CONFIG_SUN8I_A23_CCU=y +CONFIG_SUN8I_A33_CCU=y +CONFIG_SUN8I_A83T_CCU=y +CONFIG_SUN8I_DE2_CCU=y +CONFIG_SUN8I_H3_CCU=y +CONFIG_SUN8I_R40_CCU=y +CONFIG_SUN8I_R_CCU=y +CONFIG_SUN8I_V3S_CCU=y +CONFIG_SUN9I_A80_CCU=y +CONFIG_SUNXI_CCU=y +CONFIG_SUNXI_RSB=y +CONFIG_SUNXI_SRAM=y +CONFIG_SUNXI_WATCHDOG=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWCONFIG=y +CONFIG_SWCONFIG_B53=y +CONFIG_SWCONFIG_B53_PHY_DRIVER=y +CONFIG_SWCONFIG_B53_PHY_FIXUP=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_TASKS_RCU=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TOUCHSCREEN_PROPERTIES=y +CONFIG_TOUCHSCREEN_SUN4I=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_GADGET=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USERIO=y +CONFIG_USE_OF=y +CONFIG_VDSO=y +CONFIG_VFAT_FS=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VHOST=y +CONFIG_VHOST_NET=y +CONFIG_VIRTUALIZATION=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/sunxi/cortexa53/config-5.4 b/target/linux/sunxi/cortexa53/config-5.4 new file mode 100644 index 0000000000..6e1ef22129 --- /dev/null +++ b/target/linux/sunxi/cortexa53/config-5.4 @@ -0,0 +1,155 @@ +CONFIG_64BIT=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_SSBD=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DRM_RCAR_WRITEBACK=y +CONFIG_DWMAC_SUN8I=y +CONFIG_EFI_EARLYCON=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_FRAME_POINTER=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_HOLES_IN_ZONE=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INLINE_READ_LOCK=y +CONFIG_INLINE_READ_LOCK_BH=y +CONFIG_INLINE_READ_LOCK_IRQ=y +CONFIG_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_INLINE_READ_UNLOCK_BH=y +CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_SPIN_LOCK=y +CONFIG_INLINE_SPIN_LOCK_BH=y +CONFIG_INLINE_SPIN_LOCK_IRQ=y +CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_INLINE_SPIN_TRYLOCK=y +CONFIG_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_WRITE_LOCK=y +CONFIG_INLINE_WRITE_LOCK_BH=y +CONFIG_INLINE_WRITE_LOCK_IRQ=y +CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_INLINE_WRITE_UNLOCK_BH=y +CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_KVM_ARM_PMU=y +CONFIG_KVM_INDIRECT_VECTORS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MICREL_PHY=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_PINCTRL_SUN50I_A64=y +CONFIG_PINCTRL_SUN50I_A64_R=y +CONFIG_PINCTRL_SUN50I_H5=y +CONFIG_PINCTRL_SUN50I_H6=y +CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_REALTEK_PHY=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +# CONFIG_SND_SUN50I_CODEC_ANALOG is not set +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SUN50I_A64_CCU=y +CONFIG_SUN50I_DE2_BUS=y +CONFIG_SUN50I_ERRATUM_UNKNOWN1=y +CONFIG_SUN50I_H6_CCU=y +CONFIG_SUN50I_H6_R_CCU=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_VMAP_STACK=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/sunxi/cortexa7/config-5.4 b/target/linux/sunxi/cortexa7/config-5.4 new file mode 100644 index 0000000000..0b3697028f --- /dev/null +++ b/target/linux/sunxi/cortexa7/config-5.4 @@ -0,0 +1,15 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_DWMAC_SUN8I=y +# CONFIG_MACH_SUN4I is not set +# CONFIG_MACH_SUN5I is not set +CONFIG_MDIO_BUS_MUX=y +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +CONFIG_UNWINDER_ARM=y diff --git a/target/linux/sunxi/cortexa8/config-5.4 b/target/linux/sunxi/cortexa8/config-5.4 new file mode 100644 index 0000000000..1beb025ace --- /dev/null +++ b/target/linux/sunxi/cortexa8/config-5.4 @@ -0,0 +1,18 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_MACH_SUN6I is not set +# CONFIG_MACH_SUN7I is not set +# CONFIG_MACH_SUN8I is not set +# CONFIG_MACH_SUN9I is not set +# CONFIG_PHY_SUN9I_USB is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SUN8I_A83T_CCU is not set +CONFIG_UNWINDER_ARM=y diff --git a/target/linux/sunxi/image/Makefile b/target/linux/sunxi/image/Makefile index 705d409ac5..1b98849a50 100644 --- a/target/linux/sunxi/image/Makefile +++ b/target/linux/sunxi/image/Makefile @@ -11,6 +11,7 @@ include $(INCLUDE_DIR)/image.mk FAT32_BLOCK_SIZE=1024 FAT32_BLOCKS=$(shell echo $$(($(CONFIG_SUNXI_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE)))) +DEVICE_VARS := SUNXI_DTS SUNXI_DTS_DIR KERNEL_LOADADDR:=0x40008000 define Build/sunxi-sdcard @@ -32,7 +33,6 @@ endef # why \x00\x00\x00\x00 for zImage-initramfs define Device/Default PROFILES := Default - DEVICE_VARS := SUNXI_DTS SUNXI_DTS_DIR SUNXI_UBOOT KERNEL_NAME := zImage KERNEL := kernel-bin | uImage none IMAGES := sdcard.img.gz diff --git a/target/linux/sunxi/image/cortex-a53.mk b/target/linux/sunxi/image/cortex-a53.mk index ee4e9195cf..61e980cb35 100644 --- a/target/linux/sunxi/image/cortex-a53.mk +++ b/target/linux/sunxi/image/cortex-a53.mk @@ -6,14 +6,27 @@ # See /LICENSE for more information. # +define Device/sun50i + SUNXI_DTS_DIR := allwinner/ + KERNEL_NAME := Image + KERNEL := kernel-bin +endef + +define Device/sun50i-h5 + SOC := sun50i-h5 + $(Device/sun50i) +endef + +define Device/sun50i-a64 + SOC := sun50i-a64 + $(Device/sun50i) +endef + define Device/friendlyarm_nanopi-neo-plus2 DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi NEO Plus2 SUPPORTED_DEVICES:=nanopi-neo-plus2 - SUNXI_DTS_DIR := allwinner/ - SOC := sun50i-h5 - KERNEL_NAME := Image - KERNEL := kernel-bin + $(Device/sun50i-h5) endef TARGET_DEVICES += friendlyarm_nanopi-neo-plus2 @@ -21,10 +34,7 @@ define Device/friendlyarm_nanopi-neo2 DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi NEO2 SUPPORTED_DEVICES:=nanopi-neo2 - SUNXI_DTS_DIR := allwinner/ - SOC := sun50i-h5 - KERNEL_NAME := Image - KERNEL := kernel-bin + $(Device/sun50i-h5) endef TARGET_DEVICES += friendlyarm_nanopi-neo2 @@ -36,49 +46,53 @@ define Device/friendlyarm_nanopi-r1s kmod-brcmfmac brcmfmac-firmware-43430-sdio wpad-basic \ kmod-usb-net kmod-usb-net-rtl8152 SUPPORTED_DEVICES:=nanopi-r1s - SUNXI_DTS_DIR := allwinner/ - SOC := sun50i-h5 - KERNEL_NAME := Image - KERNEL := kernel-bin + $(Device/sun50i-h5) endef TARGET_DEVICES += friendlyarm_nanopi-r1s +define Device/olimex_a64-olinuxino + DEVICE_VENDOR := Olimex + DEVICE_MODEL := A64-Olinuxino + DEVICE_PACKAGES := kmod-rtl8723bs rtl8723bs-firmware + $(Device/sun50i-a64) + SUNXI_DTS := $$(SUNXI_DTS_DIR)$$(SOC)-olinuxino +endef +TARGET_DEVICES += olimex_a64-olinuxino + +define Device/olimex_a64-olinuxino-emmc + DEVICE_VENDOR := Olimex + DEVICE_MODEL := A64-Olinuxino + DEVICE_VARIANT := eMMC + DEVICE_PACKAGES := kmod-rtl8723bs rtl8723bs-firmware + $(Device/sun50i-a64) + SUNXI_DTS := $$(SUNXI_DTS_DIR)$$(SOC)-olinuxino-emmc +endef +TARGET_DEVICES += olimex_a64-olinuxino-emmc + define Device/pine64_pine64-plus DEVICE_VENDOR := Pine64 DEVICE_MODEL := Pine64+ - SUNXI_DTS_DIR := allwinner/ - SOC := sun50i-a64 - KERNEL_NAME := Image - KERNEL := kernel-bin + $(Device/sun50i-a64) endef TARGET_DEVICES += pine64_pine64-plus define Device/pine64_sopine-baseboard DEVICE_VENDOR := Pine64 DEVICE_MODEL := SoPine - SUNXI_DTS_DIR := allwinner/ - SOC := sun50i-a64 - KERNEL_NAME := Image - KERNEL := kernel-bin + $(Device/sun50i-a64) endef TARGET_DEVICES += pine64_sopine-baseboard define Device/xunlong_orangepi-pc2 DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi PC 2 - SUNXI_DTS_DIR := allwinner/ - SOC := sun50i-h5 - KERNEL_NAME := Image - KERNEL := kernel-bin + $(Device/sun50i-h5) endef TARGET_DEVICES += xunlong_orangepi-pc2 define Device/xunlong_orangepi-zero-plus DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi Zero Plus - SUNXI_DTS_DIR := allwinner/ - SOC := sun50i-h5 - KERNEL_NAME := Image - KERNEL := kernel-bin + $(Device/sun50i-h5) endef TARGET_DEVICES += xunlong_orangepi-zero-plus diff --git a/target/linux/sunxi/patches-5.4/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-5.4/301-orangepi_pc2_usb_otg_to_host_key_power.patch new file mode 100644 index 0000000000..af243ca3e7 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/301-orangepi_pc2_usb_otg_to_host_key_power.patch @@ -0,0 +1,20 @@ +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +@@ -98,7 +98,7 @@ + + sw4 { + label = "sw4"; +- linux,code = ; ++ linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +@@ -238,7 +238,7 @@ + }; + + &usb_otg { +- dr_mode = "otg"; ++ dr_mode = "host"; + status = "okay"; + }; + diff --git a/target/linux/sunxi/patches-5.4/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch b/target/linux/sunxi/patches-5.4/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch new file mode 100644 index 0000000000..79c1671de1 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/310-Revert-ARM-dts-sun7i-Add-BCM53125-switch-nodes-to-th.patch @@ -0,0 +1,86 @@ +From 49cd9ea6dc8d68eb519ccd9f31c9730dec8a181a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 8 Mar 2018 22:14:50 +0100 +Subject: [PATCH] Revert "ARM: dts: sun7i: Add BCM53125 switch nodes to the + lamobo-r1 board" + +This reverts the changes needed for the upstream b53 DSA switch driver +to use the OpenWrt b43 swconfig switch driver. + +This reverts commit 0cdefd5b5485ee6eb3512a75739d09a4090176ed. +This reverts commit d7b9eaff5f0ca00726336b4c0c3c29decf30412a. +--- + arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 60 ++----------------------------- + 1 file changed, 3 insertions(+), 57 deletions(-) + +--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts ++++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +@@ -120,65 +120,13 @@ + &gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; ++ phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- +- mdio { +- compatible = "snps,dwmac-mdio"; +- #address-cells = <1>; +- #size-cells = <0>; +- +- switch: ethernet-switch@1e { +- compatible = "brcm,bcm53125"; +- reg = <30>; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port0: port@0 { +- reg = <0>; +- label = "lan2"; +- }; +- +- port1: port@1 { +- reg = <1>; +- label = "lan3"; +- }; +- +- port2: port@2 { +- reg = <2>; +- label = "lan4"; +- }; +- +- port3: port@3 { +- reg = <3>; +- label = "wan"; +- }; +- +- port4: port@4 { +- reg = <4>; +- label = "lan1"; +- }; +- +- port8: port@8 { +- reg = <8>; +- label = "cpu"; +- ethernet = <&gmac>; +- phy-mode = "rgmii-txid"; +- fixed-link { +- speed = <1000>; +- full-duplex; +- }; +- }; +- }; +- }; ++ phy1: ethernet-phy@1 { ++ reg = <1>; + }; + }; + diff --git a/target/linux/sunxi/patches-5.4/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-5.4/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch new file mode 100644 index 0000000000..7c729ad4f7 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch @@ -0,0 +1,46 @@ +From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001 +From: Oskari Lemmela +Date: Mon, 31 Dec 2018 07:44:49 +0200 +Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions. + +First 896kB to u-boot. Enough space for SPL, u-boot and ATF. +Next 128kB to u-boot environment and rest to firmware. + +Firmware partition is compatible FIT image dynamic splitting. + +Signed-off-by: Oskari Lemmela +--- + .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +@@ -82,6 +82,28 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x000000 0x0E0000>; ++ }; ++ ++ partition@e0000 { ++ label = "u-boot-env"; ++ reg = <0x0E0000 0x020000>; ++ }; ++ ++ partition@100000 { ++ compatible = "denx,fit"; ++ label = "firmware"; ++ reg = <0x100000 0xF00000>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/sunxi/patches-5.4/410-v5.6-arm64-dts-allwinner-a64-olinuxino-Add-bank-supply-re.patch b/target/linux/sunxi/patches-5.4/410-v5.6-arm64-dts-allwinner-a64-olinuxino-Add-bank-supply-re.patch new file mode 100644 index 0000000000..67f7a1536e --- /dev/null +++ b/target/linux/sunxi/patches-5.4/410-v5.6-arm64-dts-allwinner-a64-olinuxino-Add-bank-supply-re.patch @@ -0,0 +1,58 @@ +From f0c3b29f56f0a946df4941edfe2d98e3e766c30f Mon Sep 17 00:00:00 2001 +From: Stefan Mavrodiev +Date: Fri, 29 Nov 2019 13:39:40 +0200 +Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: Add bank supply + regulators + +Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. This +patch adds regulators for them to the pinctrl node. + +Exception is PL which is used by the RSB bus. To avoid circular +dependencies, VCC-PL is omitted. + +On boards with eMMC, VCC-PC is supplied by ELDO1, instead of DCDC1. + +Signed-off-by: Stefan Mavrodiev +[Maxime: Changed the r_pio comment a bit] +Signed-off-by: Maxime Ripard +--- + .../dts/allwinner/sun50i-a64-olinuxino-emmc.dts | 4 ++++ + .../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 17 +++++++++++++++++ + 2 files changed, 21 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts +@@ -21,3 +21,7 @@ + cap-mmc-hw-reset; + status = "okay"; + }; ++ ++&pio { ++ vcc-pc-supply = <®_eldo1>; ++}; +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -163,6 +163,23 @@ + status = "okay"; + }; + ++&pio { ++ vcc-pc-supply = <®_dcdc1>; ++ vcc-pd-supply = <®_dcdc1>; ++ vcc-pe-supply = <®_aldo1>; ++ vcc-pg-supply = <®_dldo4>; ++}; ++ ++&r_pio { ++ /* ++ * FIXME: We can't add that supply for now since it would ++ * create a circular dependency between pinctrl, the regulator ++ * and the RSB Bus. ++ * ++ * vcc-pl-supply = <®_aldo2>; ++ */ ++}; ++ + &r_rsb { + status = "okay"; + diff --git a/target/linux/sunxi/patches-5.4/420-v5.7-arm64-dts-allwinner-a64-olinuxino-add-user-red-LED.patch b/target/linux/sunxi/patches-5.4/420-v5.7-arm64-dts-allwinner-a64-olinuxino-add-user-red-LED.patch new file mode 100644 index 0000000000..f369cb4f7c --- /dev/null +++ b/target/linux/sunxi/patches-5.4/420-v5.7-arm64-dts-allwinner-a64-olinuxino-add-user-red-LED.patch @@ -0,0 +1,32 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Petr=20=C5=A0tetiar?= +Date: Wed, 25 Mar 2020 18:11:16 +0100 +Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add user red LED +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is a red LED marked as `GPIO_LED1` on the silkscreen and connected +to PE17 by default. So lets add this missing bit in the current hardware +description. + +Signed-off-by: Petr Štetiar + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -70,6 +70,15 @@ + }; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ ++ user { ++ label = "a64-olinuxino:red:user"; ++ gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ ++ }; ++ }; ++ + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; diff --git a/target/linux/sunxi/patches-5.4/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-5.4/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch new file mode 100644 index 0000000000..fa02f48132 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch @@ -0,0 +1,32 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Petr=20=C5=A0tetiar?= +Date: Thu, 26 Mar 2020 10:09:19 +0100 +Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Petr Štetiar + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -53,6 +53,10 @@ + aliases { + ethernet0 = &emac; + serial0 = &uart0; ++ led-boot = &led_user; ++ led-failsafe = &led_user; ++ led-running = &led_user; ++ led-upgrade = &led_user; + }; + + chosen { +@@ -73,7 +77,7 @@ + leds { + compatible = "gpio-leds"; + +- user { ++ led_user: user { + label = "a64-olinuxino:red:user"; + gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + };