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rockchip: refresh RK3588 USB DP patches

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2024-02-16 16:43:25 +08:00
parent 66e530f016
commit cccc428fb4
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
16 changed files with 1039 additions and 917 deletions
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1380
target/linux/rockchip/patches-6.1/112-phy-rockchip-add-usbdp-combo-phy-driver.patch → target/linux/rockchip/patches-6.1/112-01-phy-rockchip-add-usbdp-combo-phy-driver.patch
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File diff suppressed because it is too large Load Diff

46
target/linux/rockchip/patches-6.1/112-02-arm64-dts-rockchip-Fix-usb2phy-nodename-for-rk3588.patch Normal file
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@ -0,0 +1,46 @@
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Wang <frank.wang@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 06/12] arm64: dts: rockchip: Fix usb2phy nodename for rk3588
Date: Tue, 13 Feb 2024 17:32:40 +0100 [thread overview]
Message-ID: <20240213163609.44930-7-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
usb2-phy should be named usb2phy according to the DT binding,
so let's fix it up accordingly.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -533,7 +533,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy2: usb2-phy@8000 {
+ u2phy2: usb2phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -558,7 +558,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy3: usb2-phy@c000 {
+ u2phy3: usb2phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;

64
target/linux/rockchip/patches-6.1/112-03-arm64-dts-rockchip-reorder-usb2phy-properties-for-rk3588.patch Normal file
View File

@ -0,0 +1,64 @@
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Wang <frank.wang@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 07/12] arm64: dts: rockchip: reorder usb2phy properties for rk3588
Date: Tue, 13 Feb 2024 17:32:41 +0100 [thread overview]
Message-ID: <20240213163609.44930-8-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
Reorder common DT properties alphabetically for usb2phy, according
to latest DT style rules.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -536,13 +536,13 @@
u2phy2: usb2phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy2";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy2_host: host-port {
@@ -561,13 +561,13 @@
u2phy3: usb2phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy3";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy3_host: host-port {

118
target/linux/rockchip/patches-6.1/120-04-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch → target/linux/rockchip/patches-6.1/112-04-arm64-dts-rockchip-add-USBDP-phys-on-rk3588.patch
View File

@ -1,19 +1,32 @@
From 7406ff837bff290c20e7b69fd08b1ec853e41a7f Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Apr 2023 17:49:04 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USBDP phy nodes
To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Wang <frank.wang@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 08/12] arm64: dts: rockchip: add USBDP phys on rk3588
Date: Tue, 13 Feb 2024 17:32:42 +0100 [thread overview]
Message-ID: <20240213163609.44930-9-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
Add both USB3-Displayport PHYs from RK3588.
Add both USB3-DisplayPort PHYs to RK3588 SoC DT.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 62 +++++++++++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 73 +++++++++++++++++++++++
2 files changed, 135 insertions(+)
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 61 +++++++++++++++++++
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 72 +++++++++++++++++++++++
2 files changed, 133 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -17,6 +17,37 @@
@@ -17,6 +17,36 @@
reg = <0x0 0xfd5c0000 0x0 0x100>;
};
@ -23,22 +36,21 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ };
+
+ usb2phy1_grf: syscon@fd5d4000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy1: usb2-phy@4000 {
+ u2phy1: usb2phy@4000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x4000 0x10>;
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ #clock-cells = <0>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
@ -51,17 +63,13 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +341,37 @@
@@ -310,6 +340,37 @@
};
};
+ usbdp_phy1: phy@fed90000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed90000 0x0 0x10000>;
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
+ <&cru PCLK_USBDPPHY1>,
@ -73,6 +81,10 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+ <&cru SRST_P_USBDPPHY1>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+
+ usbdp_phy1_dp: dp-port {
@ -91,7 +103,30 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
reg = <0x0 0xfee10000 0x0 0x100>;
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -979,6 +979,37 @@
@@ -507,11 +507,22 @@
reg = <0x0 0xfd5a4000 0x0 0x2000>;
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&cru PCLK_VO0GRF>;
+ };
+
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
};
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
php_grf: syscon@fd5b0000 {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b0000 0x0 0x1000>;
@@ -527,6 +538,36 @@
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
@ -101,22 +136,21 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ };
+
+ usb2phy0_grf: syscon@fd5d0000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2-phy@0 {
+ u2phy0: usb2phy@0 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x0 0x10>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
+ #clock-cells = <0>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ #clock-cells = <0>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
@ -129,35 +163,13 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d8000 0x0 0x4000>;
@@ -1004,6 +1035,17 @@
};
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&cru PCLK_VO0GRF>;
+ };
+
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5dc000 0x0 0x4000>;
@@ -2804,6 +2846,37 @@
@@ -2352,6 +2393,37 @@
#dma-cells = <1>;
};
+ usbdp_phy0: phy@fed80000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed80000 0x0 0x10000>;
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
+ <&cru PCLK_USBDPPHY0>,
@ -169,6 +181,10 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+ <&cru SRST_P_USBDPPHY0>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+
+ usbdp_phy0_dp: dp-port {

23
target/linux/rockchip/patches-6.1/120-05-arm64-dts-rockchip-rk3588s-Add-USB3-DRD-controllers.patch → target/linux/rockchip/patches-6.1/112-05-arm64-dts-rockchip-add-USB3-DRD-controllers-on-rk3588.patch
View File

@ -1,7 +1,20 @@
From 2ec7b70a0fa910b0d86636193b1d405ec778aba4 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 18 Jul 2023 19:05:38 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 DRD controllers
To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Wang <frank.wang@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 09/12] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
Date: Tue, 13 Feb 2024 17:32:43 +0100 [thread overview]
Message-ID: <20240213163609.44930-10-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
Add both USB3 dual-role controllers to the RK3588 devicetree.
@ -24,7 +37,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "host";
+ dr_mode = "otg";
+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
@ -42,7 +55,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
reg = <0x0 0xfd5b8000 0x0 0x10000>;
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -869,6 +869,28 @@
@@ -427,6 +427,28 @@
};
};

44
target/linux/rockchip/patches-6.1/121-05-arm64-dts-rockchip-rk3588-evb1-add-USB3.patch → target/linux/rockchip/patches-6.1/112-06-arm64-dts-rockchip-add-USB3-to-rk3588-evb1.patch
View File

@ -1,15 +1,28 @@
From 712da43d72dd301f8a6f3fcf6b39031558cb288f Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Wed, 26 Apr 2023 21:18:43 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb1: add USB3
To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Wang <frank.wang@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 10/12] arm64: dts: rockchip: add USB3 to rk3588-evb1
Date: Tue, 13 Feb 2024 17:32:44 +0100 [thread overview]
Message-ID: <20240213163609.44930-11-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
Add support for the boards USB3 type A, as well as its Type-C
connector.
Add support for the board's USB3 connectors. It has 1x USB Type-A
and 1x USB Type-C.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 151 ++++++++++++++++++
1 file changed, 151 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@ -40,7 +53,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
};
&combphy0_ps {
@@ -242,6 +255,56 @@
@@ -227,6 +240,56 @@
&i2c2 {
status = "okay";
@ -59,7 +72,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ try-power-role = "source";
+ op-sink-microwatt = <1000000>;
+ sink-pdos =
+ <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
@ -97,7 +110,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
@@ -328,6 +391,16 @@
@@ -313,6 +376,16 @@
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -114,7 +127,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
};
&pwm2 {
@@ -960,6 +1033,22 @@
@@ -945,6 +1018,22 @@
status = "okay";
};
@ -137,7 +150,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&u2phy2 {
status = "okay";
};
@@ -1002,3 +1091,58 @@
@@ -983,3 +1072,65 @@
&usb_host1_ohci {
status = "okay";
};
@ -170,6 +183,12 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+};
+
+&usbdp_phy1 {
+ /*
+ * USBDP PHY1 is wired to a female USB3 Type-A connector. Additionally
+ * the differential pairs 2+3 and the aux channel are wired to a RTD2166,
+ * which converts the DP signal into VGA. This is exposed on the
+ * board via a female VGA connector.
+ */
+ rockchip,dp-lane-mux = <2 3>;
+ status = "okay";
+};
@ -194,5 +213,6 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+};
+
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};

71
target/linux/rockchip/patches-6.1/112-07-arm64-dts-rockchip-add-upper-USB3-port-to-rock-5a.patch Normal file
View File

@ -0,0 +1,71 @@
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Wang <frank.wang@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 11/12] arm64: dts: rockchip: add upper USB3 port to rock-5a
Date: Tue, 13 Feb 2024 17:32:45 +0100 [thread overview]
Message-ID: <20240213163609.44930-12-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
Radxa Rock 5 Model A. The lower one is already supported.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588s-rock-5a.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -701,6 +701,14 @@
};
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -724,6 +732,15 @@
status = "okay";
};
+&usbdp_phy0 {
+ status = "okay";
+ rockchip,dp-lane-mux = <2 3>;
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
pinctrl-names = "default";
@@ -734,6 +751,11 @@
status = "okay";
};
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host1_ehci {
status = "okay";
};

70
target/linux/rockchip/patches-6.1/112-08-arm64-dts-rockchip-add-lower-USB3-port-to-rock-5b.patch Normal file
View File

@ -0,0 +1,70 @@
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Wang <frank.wang@rock-chips.com>,
Kever Yang <kever.yang@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
kernel@collabora.com
Subject: [PATCH v2 12/12] arm64: dts: rockchip: add lower USB3 port to rock-5b
Date: Tue, 13 Feb 2024 17:32:46 +0100 [thread overview]
Message-ID: <20240213163609.44930-13-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20240213163609.44930-1-sebastian.reichel@collabora.com>
Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from
Radxa Rock 5 Model B. The upper one is already supported.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-rock-5b.dts | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -748,6 +748,14 @@
status = "okay";
};
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -767,6 +775,14 @@
status = "okay";
};
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
@@ -783,6 +799,11 @@
status = "okay";
};
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host2_xhci {
status = "okay";
};

4
target/linux/rockchip/patches-6.1/120-01-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling.patch
View File

@ -536,8 +536,8 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -512,6 +954,16 @@
reg = <0x0 0xfd5a8000 0x0 0x100>;
@@ -545,6 +987,16 @@
reg = <0x0 0xfd5ac000 0x0 0x4000>;
};
+ bigcore0_grf: syscon@fd590000 {

2
target/linux/rockchip/patches-6.1/120-06-arm64-dts-rockchip-enable-RK3588-tsadc-by-default.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2733,7 +2733,6 @@
@@ -2732,7 +2732,6 @@
pinctrl-1 = <&tsadc_shut>;
pinctrl-names = "gpio", "otpout";
#thermal-sensor-cells = <1>;

4
target/linux/rockchip/patches-6.1/121-01-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-info.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -209,6 +209,21 @@
@@ -222,6 +222,21 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
@ -35,7 +35,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
@@ -963,6 +978,10 @@
@@ -1052,6 +1067,10 @@
status = "okay";
};

58
target/linux/rockchip/patches-6.1/122-03-arm64-dts-rockchip-rk3588s-rock5a-add-upper-USB3-port.patch
View File

@ -1,58 +0,0 @@
From 13d151bdf54a84410c27b76ac5dd9c66b9dbaff2 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Jul 2023 16:30:46 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588s-rock5a: add upper USB3 port
Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
Radxa Rock 5 Model A.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588s-rock-5a.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -709,6 +709,14 @@
};
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -732,6 +740,15 @@
status = "okay";
};
+&usbdp_phy0 {
+ status = "okay";
+ rockchip,dp-lane-mux = <2 3>;
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
pinctrl-names = "default";
@@ -742,6 +759,11 @@
status = "okay";
};
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host1_ehci {
status = "okay";
};

56
target/linux/rockchip/patches-6.1/123-06-arm64-dts-rockchip-rk3588-rock5b-add-lower-USB3-port.patch
View File

@ -1,56 +0,0 @@
From 9d4238932a628f850be3e14ec91d00efe4bb6ba5 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Jul 2023 17:18:17 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-rock5b: add lower USB3 port
Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from
Radxa Rock 5 Model B.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -756,6 +756,14 @@
status = "okay";
};
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -775,6 +783,14 @@
status = "okay";
};
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
@@ -791,6 +807,10 @@
status = "okay";
};
+&usb_host1_xhci {
+ status = "okay";
+};
+
&usb_host2_xhci {
status = "okay";
};

12
target/linux/rockchip/patches-6.1/123-07-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch
View File

@ -1,11 +1,17 @@
From 5c242dd9ee6e94c1f19248a48792ad0ce0bd7b4a Mon Sep 17 00:00:00 2001
From 152b46f9ad81fe60f2845c87b0298db84bbecdc9 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 25 Jul 2023 18:35:56 +0200
Subject: [PATCH] arm64: dts: rockchip: rk3588-rock5b: add USB-C support
Subject: [PATCH] [BROKEN] arm64: dts: rockchip: rk3588-rock5b: add USB-C
support
Add support for using the Radxa Rock 5 Model B USB-C port for USB in
OHCI, EHCI or XHCI mode. Displayport AltMode is not yet supported.
Note: Enabling support for the USB-C port results in a board reset
when the system is supplied with a PD capable power-supply. Until
this has been analyzed and fixed, let's disable support for the
Type-C port.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-rock-5b.dts | 119 ++++++++++++++++++
@ -62,7 +68,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vcc12v_dcin>;
+ status = "okay";
+ status = "disabled";
+
+ usb_con: connector {
+ compatible = "usb-c-connector";

2
target/linux/rockchip/patches-6.1/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch
View File

@ -11,7 +11,7 @@ Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2146,6 +2146,17 @@
@@ -2145,6 +2145,17 @@
status = "disabled";
};

2
target/linux/rockchip/patches-6.1/801-06-arm64-dts-rockchip-rk3588s-rng-use-scmi_clk.patch
View File

@ -14,7 +14,7 @@ Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2150,7 +2150,7 @@
@@ -2149,7 +2149,7 @@
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;