Merge Official Source
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
commit
d03aafed36
@ -7,9 +7,9 @@ PKG_RELEASE:=$(AUTORELEASE)
|
||||
|
||||
PKG_SOURCE_PROTO:=git
|
||||
PKG_SOURCE_URL:=https://git.openwrt.org/project/bcm63xx/u-boot.git
|
||||
PKG_SOURCE_DATE:=2022-03-03
|
||||
PKG_SOURCE_VERSION:=92e9eca819c9c898d9d2010e1a217726c42c8c47
|
||||
PKG_MIRROR_HASH:=11c37fe4c18d55e799153600d1cfd8ee9ca7da8326d0024c1d825f4a327c5f0d
|
||||
PKG_SOURCE_DATE:=2022-03-15
|
||||
PKG_SOURCE_VERSION:=0625aad74d1f5b6f9c068955ad3fd7f6df635e50
|
||||
PKG_MIRROR_HASH:=0602e0e4f101ead206940eccca832b75191905c1e81290340a89b07dbee7a6ce
|
||||
|
||||
include $(INCLUDE_DIR)/u-boot.mk
|
||||
include $(INCLUDE_DIR)/package.mk
|
||||
@ -23,10 +23,18 @@ endef
|
||||
define U-Boot/bcm4908
|
||||
NAME:=Broadcom's BCM4908
|
||||
UBOOT_CONFIG:=bcm94908
|
||||
SOC:=bcm4908
|
||||
endef
|
||||
|
||||
define U-Boot/bcm4912
|
||||
NAME:=Broadcom's BCM4912
|
||||
UBOOT_CONFIG:=bcm94912
|
||||
SOC:=bcm4912
|
||||
endef
|
||||
|
||||
UBOOT_TARGETS := \
|
||||
bcm4908
|
||||
bcm4908 \
|
||||
bcm4912
|
||||
|
||||
define Build/Prepare
|
||||
$(call Build/Prepare/Default)
|
||||
@ -40,8 +48,8 @@ endef
|
||||
|
||||
define Build/InstallDev
|
||||
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/u-boot
|
||||
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/u-boot/
|
||||
$(INSTALL_BIN) $(PKG_BUILD_DIR)/u-boot.dtb $(STAGING_DIR_IMAGE)/u-boot/
|
||||
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/u-boot/u-boot-$(SOC).bin
|
||||
$(INSTALL_BIN) $(PKG_BUILD_DIR)/u-boot.dtb $(STAGING_DIR_IMAGE)/u-boot/u-boot-$(SOC).dtb
|
||||
$(INSTALL_BIN) $(PKG_BUILD_DIR)/arch/arm/dts/*.dtb $(STAGING_DIR_IMAGE)/u-boot/
|
||||
endef
|
||||
|
||||
|
||||
@ -23,7 +23,8 @@ shipped with every firmware.
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
---
|
||||
configs/bcm94908_defconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
configs/bcm94912_defconfig | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/configs/bcm94908_defconfig
|
||||
+++ b/configs/bcm94908_defconfig
|
||||
@ -36,3 +37,14 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_ENV_VARS_UBOOT_CONFIG=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x11000
|
||||
--- a/configs/bcm94912_defconfig
|
||||
+++ b/configs/bcm94912_defconfig
|
||||
@@ -22,7 +22,7 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
-CONFIG_SPL=y
|
||||
+# CONFIG_SPL is not set
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_ENV_VARS_UBOOT_CONFIG=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
|
||||
|
||||
@ -19,8 +19,9 @@ deal with compiling SPL or TPL.
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
---
|
||||
arch/arm/mach-bcmbca/bcm4908/cpu.c | 2 +-
|
||||
arch/arm/mach-bcmbca/bcm4912/cpu.c | 2 +-
|
||||
board/broadcom/bcmbca/board.c | 4 ++--
|
||||
2 files changed, 3 insertions(+), 3 deletions(-)
|
||||
3 files changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm/mach-bcmbca/bcm4908/cpu.c
|
||||
+++ b/arch/arm/mach-bcmbca/bcm4908/cpu.c
|
||||
@ -33,6 +34,17 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
void boot_secondary_cpu(unsigned long vector)
|
||||
{
|
||||
uint32_t cpu, nr_cpus = QUAD_CPUS;
|
||||
--- a/arch/arm/mach-bcmbca/bcm4912/cpu.c
|
||||
+++ b/arch/arm/mach-bcmbca/bcm4912/cpu.c
|
||||
@@ -174,7 +174,7 @@ int bcmbca_get_boot_device(void)
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
-#if !defined(CONFIG_TPL_ATF)
|
||||
+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)
|
||||
void boot_secondary_cpu(unsigned long vector)
|
||||
{
|
||||
uint32_t cpu, nr_cpus = 4;
|
||||
--- a/board/broadcom/bcmbca/board.c
|
||||
+++ b/board/broadcom/bcmbca/board.c
|
||||
@@ -103,7 +103,7 @@ void board_spinor_init(void)
|
||||
|
||||
@ -800,7 +800,7 @@ hostapd_set_bss_options() {
|
||||
json_get_vars mobility_domain ft_psk_generate_local ft_over_ds reassociation_deadline
|
||||
|
||||
set_default mobility_domain "$(echo "$ssid" | md5sum | head -c 4)"
|
||||
set_default ft_over_ds 1
|
||||
set_default ft_over_ds 0
|
||||
set_default reassociation_deadline 1000
|
||||
|
||||
case "$auth_type" in
|
||||
|
||||
46
target/linux/bcm4908/base-files/etc/init.d/fastnetwork
Executable file
46
target/linux/bcm4908/base-files/etc/init.d/fastnetwork
Executable file
@ -0,0 +1,46 @@
|
||||
#!/bin/sh /etc/rc.common
|
||||
|
||||
START=25
|
||||
USE_PROCD=1
|
||||
|
||||
start_service() {
|
||||
reload_service
|
||||
}
|
||||
|
||||
service_triggers() {
|
||||
procd_add_reload_trigger "network"
|
||||
procd_add_reload_trigger "firewall"
|
||||
procd_add_reload_interface_trigger "lan"
|
||||
}
|
||||
|
||||
reload_service() {
|
||||
local packet_steering="$(uci -q get network.@globals[0].packet_steering)"
|
||||
local num_cpus="$(grep -c "^processor.*:" /proc/cpuinfo)"
|
||||
local flow_offloading="$(uci -q get firewall.@defaults[0].flow_offloading)"
|
||||
local flow_offloading_hw="$(uci -q get firewall.@defaults[0].flow_offloading_hw)"
|
||||
local rps_eth0=0
|
||||
local rps_br_lan=0
|
||||
|
||||
[ "$num_cpus" -le 1 ] && return
|
||||
|
||||
[ "$packet_steering" = 1 ] && {
|
||||
if [ ${flow_offloading_hw:-0} -gt 0 ]; then
|
||||
# HW offloading
|
||||
# Not implemented
|
||||
:
|
||||
elif [ ${flow_offloading:-0} -gt 0 ]; then
|
||||
# SW offloading
|
||||
# BCM4908 always reaches ~940 Mb/s
|
||||
:
|
||||
else
|
||||
# Default
|
||||
case "$num_cpus" in
|
||||
2) rps_eth0=2; rps_br_lan=2;;
|
||||
4) rps_eth0=e; rps_br_lan=e;;
|
||||
esac
|
||||
fi
|
||||
}
|
||||
|
||||
echo $rps_eth0 > /sys/class/net/eth0/queues/rx-0/rps_cpus
|
||||
echo $rps_br_lan > /sys/class/net/br-lan/queues/rx-0/rps_cpus
|
||||
}
|
||||
@ -0,0 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
uci set network.@globals[0].packet_steering="1"
|
||||
@ -5,19 +5,20 @@ include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
DEVICE_VARS += ASUS_PRODUCTID ASUS_BUILD_NO ASUS_FW_REV ASUS_EXT_NO
|
||||
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_REGION
|
||||
DEVICE_VARS += PKGTB_ITS
|
||||
DEVICE_VARS += SOC
|
||||
|
||||
define Image/Prepare
|
||||
cp bootfs-generic.its $(KDIR)/
|
||||
sed -i "s=\$$$${images_dir}=$(STAGING_DIR_IMAGE)=" $(KDIR)/bootfs-generic.its
|
||||
sed -i "s=\$$$${dts_dir}=$(DTS_DIR)=" $(KDIR)/bootfs-generic.its
|
||||
cp bootfs*.its* $(KDIR)/
|
||||
sed -i "s=\$$$${images_dir}=$(STAGING_DIR_IMAGE)=" $(KDIR)/bootfs*.its*
|
||||
sed -i "s=\$$$${dts_dir}=$(DTS_DIR)=" $(KDIR)/bootfs*.its*
|
||||
endef
|
||||
|
||||
define Build/bootfs
|
||||
cat $@ | $(STAGING_DIR_HOST)/bin/lzma e -eos -si -so > $@.tmp
|
||||
mv $@.tmp $@
|
||||
sed -i "s=\$${kernel}=$@=" $(KDIR)/bootfs-generic.its
|
||||
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $(KDIR)/bootfs-generic.its $(KDIR)/bootfs-generic.itb
|
||||
sed -i "s=\$${kernel}=$@=" $(KDIR)/bootfs*.its*
|
||||
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $(KDIR)/bootfs-bcm4908.its $(KDIR)/bootfs-bcm4908.itb
|
||||
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $(KDIR)/bootfs-bcm4912.its $(KDIR)/bootfs-bcm4912.itb
|
||||
endef
|
||||
|
||||
define Build/bcm4908asus
|
||||
@ -54,8 +55,8 @@ endef
|
||||
|
||||
define Build/pkgtb
|
||||
mv $@ $@.rootfs
|
||||
cp $(PKGTB_ITS) $@.its
|
||||
sed -i "s=\$${bootfs}=$(KDIR)/bootfs-generic.itb=" $@.its
|
||||
cp pkgtb-$(SOC).its $@.its
|
||||
sed -i "s=\$${bootfs}=$(KDIR)/bootfs-$(SOC).itb=" $@.its
|
||||
sed -i "s=\$${rootfs}=$@.rootfs=" $@.its
|
||||
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@
|
||||
endef
|
||||
@ -86,6 +87,16 @@ define Device/asus_gt-ac5300
|
||||
endef
|
||||
TARGET_DEVICES += asus_gt-ac5300
|
||||
|
||||
define Device/asus_gt-ax6000
|
||||
DEVICE_VENDOR := Asus
|
||||
DEVICE_MODEL := GT-AX6000
|
||||
DEVICE_DTS := broadcom/bcmbca/bcm4912-asus-gt-ax6000
|
||||
IMAGES := pkgtb
|
||||
IMAGE/pkgtb := append-rootfs | pkgtb
|
||||
SOC := bcm4912
|
||||
endef
|
||||
# TARGET_DEVICES += asus_gt-ax6000
|
||||
|
||||
define Device/netgear_r8000p
|
||||
DEVICE_VENDOR := Netgear
|
||||
DEVICE_MODEL := R8000P
|
||||
@ -119,7 +130,7 @@ endef
|
||||
define Device/netgear_raxe500
|
||||
DEVICE_MODEL := RAXE500
|
||||
$(Device/netgear)
|
||||
PKGTB_ITS := pkgtb-bcm4908.its
|
||||
SOC := bcm4908
|
||||
NETGEAR_BOARD_ID := U12H449T00_NETGEAR
|
||||
endef
|
||||
# TARGET_DEVICES += netgear_raxe500
|
||||
|
||||
48
target/linux/bcm4908/image/bootfs-bcm4908.its
Normal file
48
target/linux/bcm4908/image/bootfs-bcm4908.its
Normal file
@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
/include/ "bootfs.itsi"
|
||||
|
||||
/ {
|
||||
images {
|
||||
uboot {
|
||||
data = /incbin/("${images_dir}/u-boot/u-boot-bcm4908.bin");
|
||||
};
|
||||
|
||||
fdt_uboot {
|
||||
data = /incbin/("${images_dir}/u-boot/u-boot-bcm4908.dtb");
|
||||
};
|
||||
|
||||
fdt_uboot_RAX220 {
|
||||
description = "dtb";
|
||||
data = /incbin/("${images_dir}/u-boot/RAX220.dtb");
|
||||
type = "flat_dt";
|
||||
compression = "none";
|
||||
|
||||
hash-1 {
|
||||
algo = "sha256";
|
||||
};
|
||||
};
|
||||
|
||||
fdt_linux_RAX220 {
|
||||
description = "dtb";
|
||||
data = /incbin/("${dts_dir}/broadcom/bcm4908/bcm4908-netgear-raxe500.dtb");
|
||||
arch = "arm64";
|
||||
type = "flat_dt";
|
||||
compression = "none";
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
conf_ub_RAX220 {
|
||||
description = "RAX220";
|
||||
fdt = "fdt_uboot_RAX220";
|
||||
loadables = "atf", "uboot";
|
||||
};
|
||||
|
||||
conf_lx_RAX220 {
|
||||
description = "BRCM 63xxx linux";
|
||||
kernel = "kernel";
|
||||
fdt = "fdt_linux_RAX220";
|
||||
};
|
||||
};
|
||||
};
|
||||
34
target/linux/bcm4908/image/bootfs-bcm4912.its
Normal file
34
target/linux/bcm4908/image/bootfs-bcm4912.its
Normal file
@ -0,0 +1,34 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
/include/ "bootfs.itsi"
|
||||
|
||||
/ {
|
||||
images {
|
||||
uboot {
|
||||
data = /incbin/("${images_dir}/u-boot/u-boot-bcm4912.bin");
|
||||
};
|
||||
|
||||
fdt_uboot {
|
||||
data = /incbin/("${images_dir}/u-boot/u-boot-bcm4912.dtb");
|
||||
};
|
||||
|
||||
fdt_GTAX6000 {
|
||||
description = "dtb";
|
||||
data = /incbin/("${images_dir}/u-boot/GTAX6000.dtb");
|
||||
type = "flat_dt";
|
||||
compression = "none";
|
||||
|
||||
hash-1 {
|
||||
algo = "sha256";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
conf_ub_GTAX6000 {
|
||||
description = "GTAX6000";
|
||||
fdt = "fdt_GTAX6000";
|
||||
loadables = "atf", "uboot";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -24,7 +24,6 @@
|
||||
|
||||
uboot {
|
||||
description = "U-Boot";
|
||||
data = /incbin/("${images_dir}/u-boot/u-boot-nodtb.bin");
|
||||
os = "U-Boot";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
@ -53,7 +52,6 @@
|
||||
|
||||
fdt_uboot {
|
||||
description = "dtb";
|
||||
data = /incbin/("${images_dir}/u-boot/u-boot.dtb");
|
||||
type = "flat_dt";
|
||||
compression = "none";
|
||||
|
||||
@ -61,14 +59,6 @@
|
||||
algo = "sha256";
|
||||
};
|
||||
};
|
||||
|
||||
fdt_linux_RAX220 {
|
||||
description = "dtb";
|
||||
data = /incbin/("${dts_dir}/broadcom/bcm4908/bcm4908-netgear-raxe500.dtb");
|
||||
arch = "arm64";
|
||||
type = "flat_dt";
|
||||
compression = "none";
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
@ -79,11 +69,5 @@
|
||||
fdt = "fdt_uboot";
|
||||
loadables = "atf", "uboot";
|
||||
};
|
||||
|
||||
conf_lx_RAX220 {
|
||||
description = "BRCM 63xxx linux";
|
||||
kernel = "kernel";
|
||||
fdt = "fdt_linux_RAX220";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,199 @@
|
||||
From 076dcedc6628c6bf92bd17bfcf8fb7b1af62bfb6 Mon Sep 17 00:00:00 2001
|
||||
From: William Zhang <william.zhang@broadcom.com>
|
||||
Date: Wed, 1 Jun 2022 15:56:51 -0700
|
||||
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63158
|
||||
|
||||
Add DTS for ARMv8 based broadband SoC BCM63158. bcm63158.dtsi is the
|
||||
SoC description DTS header and bcm963158.dts is a simple DTS file for
|
||||
Broadcom BCM963158 Reference board that only enable the UART port.
|
||||
|
||||
Signed-off-by: William Zhang <william.zhang@broadcom.com>
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/broadcom/Makefile | 1 +
|
||||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 2 +
|
||||
.../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 128 ++++++++++++++++++
|
||||
.../boot/dts/broadcom/bcmbca/bcm963158.dts | 30 ++++
|
||||
4 files changed, 161 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/broadcom/Makefile
|
||||
+++ b/arch/arm64/boot/dts/broadcom/Makefile
|
||||
@@ -5,5 +5,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rp
|
||||
bcm2837-rpi-cm3-io3.dtb
|
||||
|
||||
subdir-y += bcm4908
|
||||
+subdir-y += bcmbca
|
||||
subdir-y += northstar2
|
||||
subdir-y += stingray
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
@@ -0,0 +1,2 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0
|
||||
+dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
|
||||
@@ -0,0 +1,128 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/irq.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "brcm,bcm63158", "brcm,bcmbca";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ B53_0: cpu@0 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x0>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_1: cpu@1 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x1>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_2: cpu@2 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x2>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_3: cpu@3 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x3>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ L2_0: l2-cache0 {
|
||||
+ compatible = "cache";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
+ };
|
||||
+
|
||||
+ pmu: pmu {
|
||||
+ compatible = "arm,cortex-a53-pmu";
|
||||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-affinity = <&B53_0>, <&B53_1>,
|
||||
+ <&B53_2>, <&B53_3>;
|
||||
+ };
|
||||
+
|
||||
+ clocks: clocks {
|
||||
+ periph_clk: periph-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-frequency = <200000000>;
|
||||
+ };
|
||||
+ uart_clk: uart-clk {
|
||||
+ compatible = "fixed-factor-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ clock-div = <4>;
|
||||
+ clock-mult = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ psci {
|
||||
+ compatible = "arm,psci-0.2";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ axi@81000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
+
|
||||
+ gic: interrupt-controller@1000 {
|
||||
+ compatible = "arm,gic-400";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ reg = <0x1000 0x1000>,
|
||||
+ <0x2000 0x2000>,
|
||||
+ <0x4000 0x2000>,
|
||||
+ <0x6000 0x2000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bus@ff800000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
+
|
||||
+ uart0: serial@12000 {
|
||||
+ compatible = "arm,pl011", "arm,primecell";
|
||||
+ reg = <0x12000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&uart_clk>, <&uart_clk>;
|
||||
+ clock-names = "uartclk", "apb_pclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm63158.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Broadcom BCM963158 Reference Board";
|
||||
+ compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x08000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,191 @@
|
||||
From 1ba56aeb391401c4cb2126c39f90b3cdbfabdb3f Mon Sep 17 00:00:00 2001
|
||||
From: William Zhang <william.zhang@broadcom.com>
|
||||
Date: Wed, 1 Jun 2022 13:17:34 -0700
|
||||
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM4912
|
||||
|
||||
Add DTS for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the
|
||||
SoC description DTS header and bcm94912.dts is a simple DTS file for
|
||||
Broadcom BCM94912 Reference board that only enable the UART port.
|
||||
|
||||
Signed-off-by: William Zhang <william.zhang@broadcom.com>
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
|
||||
.../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 128 ++++++++++++++++++
|
||||
.../boot/dts/broadcom/bcmbca/bcm94912.dts | 30 ++++
|
||||
3 files changed, 160 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
@@ -1,2 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
-dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
|
||||
+dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
|
||||
+ bcm963158.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
|
||||
@@ -0,0 +1,128 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/irq.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "brcm,bcm4912", "brcm,bcmbca";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ B53_0: cpu@0 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x0>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_1: cpu@1 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x1>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_2: cpu@2 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x2>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_3: cpu@3 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x3>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ L2_0: l2-cache0 {
|
||||
+ compatible = "cache";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
+ };
|
||||
+
|
||||
+ pmu: pmu {
|
||||
+ compatible = "arm,cortex-a53-pmu";
|
||||
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-affinity = <&B53_0>, <&B53_1>,
|
||||
+ <&B53_2>, <&B53_3>;
|
||||
+ };
|
||||
+
|
||||
+ clocks: clocks {
|
||||
+ periph_clk: periph-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-frequency = <200000000>;
|
||||
+ };
|
||||
+ uart_clk: uart-clk {
|
||||
+ compatible = "fixed-factor-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ clock-div = <4>;
|
||||
+ clock-mult = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ psci {
|
||||
+ compatible = "arm,psci-0.2";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ axi@81000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
+
|
||||
+ gic: interrupt-controller@1000 {
|
||||
+ compatible = "arm,gic-400";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ reg = <0x1000 0x1000>,
|
||||
+ <0x2000 0x2000>,
|
||||
+ <0x4000 0x2000>,
|
||||
+ <0x6000 0x2000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bus@ff800000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
+
|
||||
+ uart0: serial@12000 {
|
||||
+ compatible = "arm,pl011", "arm,primecell";
|
||||
+ reg = <0x12000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&uart_clk>, <&uart_clk>;
|
||||
+ clock-names = "uartclk", "apb_pclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm4912.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Broadcom BCM94912 Reference Board";
|
||||
+ compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x08000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,184 @@
|
||||
From e663e06bd3f21e64bc2163910f626af68add6308 Mon Sep 17 00:00:00 2001
|
||||
From: Anand Gore <anand.gore@broadcom.com>
|
||||
Date: Wed, 1 Jun 2022 13:19:56 -0700
|
||||
Subject: [PATCH] ARM64: dts: Add DTS files for bcmbca SoC BCM6858
|
||||
|
||||
Add DTS for ARMv8 based broadband SoC BCM6858. bcm6858.dtsi is the SoC
|
||||
description DTS header and bcm96858.dts is a simple DTS file for
|
||||
Broadcom BCM96858 Reference board that only enables the UART port.
|
||||
|
||||
Signed-off-by: Anand Gore <anand.gore@broadcom.com>
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
|
||||
.../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 121 ++++++++++++++++++
|
||||
.../boot/dts/broadcom/bcmbca/bcm96858.dts | 30 +++++
|
||||
3 files changed, 153 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
@@ -1,3 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
|
||||
- bcm963158.dtb
|
||||
+ bcm963158.dtb \
|
||||
+ bcm96858.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
|
||||
@@ -0,0 +1,121 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/irq.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "brcm,bcm6858", "brcm,bcmbca";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ B53_0: cpu@0 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x0>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_1: cpu@1 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x1>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_2: cpu@2 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x2>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_3: cpu@3 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x3>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+ L2_0: l2-cache0 {
|
||||
+ compatible = "cache";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
+ };
|
||||
+
|
||||
+ pmu: pmu {
|
||||
+ compatible = "arm,armv8-pmuv3";
|
||||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-affinity = <&B53_0>, <&B53_1>,
|
||||
+ <&B53_2>, <&B53_3>;
|
||||
+ };
|
||||
+
|
||||
+ clocks: clocks {
|
||||
+ periph_clk:periph-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-frequency = <200000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ psci {
|
||||
+ compatible = "arm,psci-0.2";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ axi@81000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
+
|
||||
+ gic: interrupt-controller@1000 {
|
||||
+ compatible = "arm,gic-400";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ reg = <0x1000 0x1000>, /* GICD */
|
||||
+ <0x2000 0x2000>, /* GICC */
|
||||
+ <0x4000 0x2000>, /* GICH */
|
||||
+ <0x6000 0x2000>; /* GICV */
|
||||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
+ IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bus@ff800000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0xff800000 0x62000>;
|
||||
+
|
||||
+ uart0: serial@640 {
|
||||
+ compatible = "brcm,bcm6345-uart";
|
||||
+ reg = <0x640 0x18>;
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ clock-names = "refclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm6858.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Broadcom BCM96858 Reference Board";
|
||||
+ compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x08000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,174 @@
|
||||
From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
|
||||
From: William Zhang <william.zhang@broadcom.com>
|
||||
Date: Wed, 8 Jun 2022 11:00:59 -0700
|
||||
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146
|
||||
|
||||
Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
|
||||
SoC description DTS header and bcm963146.dts is a simple DTS file for
|
||||
Broadcom BCM963146 Reference board that only enable the UART port.
|
||||
|
||||
Signed-off-by: William Zhang <william.zhang@broadcom.com>
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
|
||||
.../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 110 ++++++++++++++++++
|
||||
.../boot/dts/broadcom/bcmbca/bcm963146.dts | 30 +++++
|
||||
3 files changed, 142 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
@@ -1,4 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
|
||||
bcm963158.dtb \
|
||||
- bcm96858.dtb
|
||||
+ bcm96858.dtb \
|
||||
+ bcm963146.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
|
||||
@@ -0,0 +1,110 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/irq.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "brcm,bcm63146", "brcm,bcmbca";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ B53_0: cpu@0 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x0>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_1: cpu@1 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x1>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ L2_0: l2-cache0 {
|
||||
+ compatible = "cache";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
+ };
|
||||
+
|
||||
+ pmu: pmu {
|
||||
+ compatible = "arm,cortex-a53-pmu";
|
||||
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-affinity = <&B53_0>, <&B53_1>;
|
||||
+ };
|
||||
+
|
||||
+ clocks: clocks {
|
||||
+ periph_clk: periph-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-frequency = <200000000>;
|
||||
+ };
|
||||
+ uart_clk: uart-clk {
|
||||
+ compatible = "fixed-factor-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ clock-div = <4>;
|
||||
+ clock-mult = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ psci {
|
||||
+ compatible = "arm,psci-0.2";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ axi@81000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
+
|
||||
+ gic: interrupt-controller@1000 {
|
||||
+ compatible = "arm,gic-400";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ reg = <0x1000 0x1000>,
|
||||
+ <0x2000 0x2000>,
|
||||
+ <0x4000 0x2000>,
|
||||
+ <0x6000 0x2000>;
|
||||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
+ IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bus@ff800000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
+
|
||||
+ uart0: serial@12000 {
|
||||
+ compatible = "arm,pl011", "arm,primecell";
|
||||
+ reg = <0x12000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&uart_clk>, <&uart_clk>;
|
||||
+ clock-names = "uartclk", "apb_pclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm63146.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Broadcom BCM963146 Reference Board";
|
||||
+ compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x08000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,167 @@
|
||||
From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001
|
||||
From: William Zhang <william.zhang@broadcom.com>
|
||||
Date: Wed, 8 Jun 2022 11:04:36 -0700
|
||||
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856
|
||||
|
||||
Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the
|
||||
SoC description DTS header and bcm96856.dts is a simple DTS file for
|
||||
Broadcom BCM96956 Reference board that only enable the UART port.
|
||||
|
||||
Signed-off-by: William Zhang <william.zhang@broadcom.com>
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
|
||||
.../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 103 ++++++++++++++++++
|
||||
.../boot/dts/broadcom/bcmbca/bcm96856.dts | 30 +++++
|
||||
3 files changed, 135 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
@@ -2,4 +2,5 @@
|
||||
dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
|
||||
bcm963158.dtb \
|
||||
bcm96858.dtb \
|
||||
- bcm963146.dtb
|
||||
+ bcm963146.dtb \
|
||||
+ bcm96856.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
|
||||
@@ -0,0 +1,103 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/irq.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "brcm,bcm6856", "brcm,bcmbca";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ B53_0: cpu@0 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x0>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_1: cpu@1 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x1>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ L2_0: l2-cache0 {
|
||||
+ compatible = "cache";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
+ };
|
||||
+
|
||||
+ pmu: pmu {
|
||||
+ compatible = "arm,cortex-a53-pmu";
|
||||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-affinity = <&B53_0>, <&B53_1>;
|
||||
+ };
|
||||
+
|
||||
+ clocks: clocks {
|
||||
+ periph_clk:periph-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-frequency = <200000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ psci {
|
||||
+ compatible = "arm,psci-0.2";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ axi@81000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
+
|
||||
+ gic: interrupt-controller@1000 {
|
||||
+ compatible = "arm,gic-400";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ reg = <0x1000 0x1000>, /* GICD */
|
||||
+ <0x2000 0x2000>, /* GICC */
|
||||
+ <0x4000 0x2000>, /* GICH */
|
||||
+ <0x6000 0x2000>; /* GICV */
|
||||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
+ IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bus@ff800000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
+
|
||||
+ uart0: serial@640 {
|
||||
+ compatible = "brcm,bcm6345-uart";
|
||||
+ reg = <0x640 0x18>;
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ clock-names = "refclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm6856.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Broadcom BCM96856 Reference Board";
|
||||
+ compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x08000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,192 @@
|
||||
From eab6bb0994b806525fc5e362e8b865f61c4a9e20 Mon Sep 17 00:00:00 2001
|
||||
From: William Zhang <william.zhang@broadcom.com>
|
||||
Date: Thu, 9 Jun 2022 17:15:33 -0700
|
||||
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6813
|
||||
|
||||
Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the
|
||||
SoC description DTS header and bcm96813.dts is a simple DTS file for
|
||||
Broadcom BCM96813 Reference board that only enable the UART port.
|
||||
|
||||
Signed-off-by: William Zhang <william.zhang@broadcom.com>
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
|
||||
.../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 128 ++++++++++++++++++
|
||||
.../boot/dts/broadcom/bcmbca/bcm96813.dts | 30 ++++
|
||||
3 files changed, 160 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dt
|
||||
bcm963158.dtb \
|
||||
bcm96858.dtb \
|
||||
bcm963146.dtb \
|
||||
- bcm96856.dtb
|
||||
+ bcm96856.dtb \
|
||||
+ bcm96813.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
|
||||
@@ -0,0 +1,128 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/irq.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "brcm,bcm6813", "brcm,bcmbca";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ cpus {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ B53_0: cpu@0 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x0>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_1: cpu@1 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x1>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_2: cpu@2 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x2>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ B53_3: cpu@3 {
|
||||
+ compatible = "brcm,brahma-b53";
|
||||
+ device_type = "cpu";
|
||||
+ reg = <0x0 0x3>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ enable-method = "psci";
|
||||
+ };
|
||||
+
|
||||
+ L2_0: l2-cache0 {
|
||||
+ compatible = "cache";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
+ };
|
||||
+
|
||||
+ pmu: pmu {
|
||||
+ compatible = "arm,cortex-a53-pmu";
|
||||
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-affinity = <&B53_0>, <&B53_1>,
|
||||
+ <&B53_2>, <&B53_3>;
|
||||
+ };
|
||||
+
|
||||
+ clocks: clocks {
|
||||
+ periph_clk: periph-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-frequency = <200000000>;
|
||||
+ };
|
||||
+ uart_clk: uart-clk {
|
||||
+ compatible = "fixed-factor-clock";
|
||||
+ #clock-cells = <0>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ clock-div = <4>;
|
||||
+ clock-mult = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ psci {
|
||||
+ compatible = "arm,psci-0.2";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ axi@81000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0x81000000 0x8000>;
|
||||
+
|
||||
+ gic: interrupt-controller@1000 {
|
||||
+ compatible = "arm,gic-400";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ interrupt-controller;
|
||||
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ reg = <0x1000 0x1000>,
|
||||
+ <0x2000 0x2000>,
|
||||
+ <0x4000 0x2000>,
|
||||
+ <0x6000 0x2000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ bus@ff800000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0x0 0x0 0xff800000 0x800000>;
|
||||
+
|
||||
+ uart0: serial@12000 {
|
||||
+ compatible = "arm,pl011", "arm,primecell";
|
||||
+ reg = <0x12000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&uart_clk>, <&uart_clk>;
|
||||
+ clock-names = "uartclk", "apb_pclk";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright 2022 Broadcom Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm6813.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Broadcom BCM96813 Reference Board";
|
||||
+ compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x08000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,54 @@
|
||||
From f3f575c4bef95384e68de552c7b29938fd0d9201 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Wed, 13 Jul 2022 22:03:51 +0200
|
||||
Subject: [PATCH] arm64: dts: Add base DTS file for bcmbca device Asus
|
||||
GT-AX6000
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
It's a home router with 1 GiB of RAM, 6 Ethernet ports, 2 USB ports.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Acked-by: William Zhang <william.zhang@broadcom.com>
|
||||
Link: https://lore.kernel.org/r/20220713200351.28526-2-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 4 +++-
|
||||
.../bcmbca/bcm4912-asus-gt-ax6000.dts | 19 +++++++++++++++++++
|
||||
2 files changed, 22 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
|
||||
@@ -1,5 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
-dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
|
||||
+dtb-$(CONFIG_ARCH_BCMBCA) += \
|
||||
+ bcm4912-asus-gt-ax6000.dtb \
|
||||
+ bcm94912.dtb \
|
||||
bcm963158.dtb \
|
||||
bcm96858.dtb \
|
||||
bcm963146.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts
|
||||
@@ -0,0 +1,19 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm4912.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca";
|
||||
+ model = "Asus GT-AX6000";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x00 0x00 0x00 0x40000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
Loading…
Reference in New Issue
Block a user