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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2023-07-02 16:17:53 +08:00
commit d0858b7d59
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GPG Key ID: 6850B6345C862176
5 changed files with 92 additions and 93 deletions
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6
package/kernel/mt76/Makefile
View File

@ -8,9 +8,9 @@ PKG_LICENSE_FILES:=
PKG_SOURCE_URL:=https://github.com/openwrt/mt76
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2023-06-27
PKG_SOURCE_VERSION:=f36b921692b940bc74b155575e9a17930b42140d
PKG_MIRROR_HASH:=c26dea3a58ba03d539c8e6cc2d3c99ce0cb5bb3b1aac76cab7fea689b6a86e4c
PKG_SOURCE_DATE:=2023-06-30
PKG_SOURCE_VERSION:=1377f586c6f520a6d032053a2e9c0ebc8b277e9b
PKG_MIRROR_HASH:=785e7588139d3d56e4b142d63c5fc8b83e38bcc9c45edc7d96a0927a9a8c472d
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_USE_NINJA:=0

2
target/linux/ath79/generic/base-files/etc/board.d/02_network
View File

@ -749,7 +749,7 @@ ath79_setup_macs()
wan_mac=$(mtd_get_mac_text board_data 0x480)
label_mac=$wan_mac
;;
comfast,cf-e380ac-v2|\
comfast,cf-e380ac-v2|\
netgear,wndr3700|\
netgear,wndr3700-v2|\
netgear,wndr3800|\

5
target/linux/mediatek/dts/mt7986b-netgear-wax220.dts
View File

@ -186,6 +186,11 @@
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <256>;
mediatek,bmt-remap-range = <0x0 0x580000>;
partitions: partitions {
#address-cells = <0x1>;
#size-cells = <0x1>;

168
target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c
View File

@ -12,6 +12,8 @@
#include <linux/firmware.h>
#include <linux/crc32.h>
#include <linux/sfp.h>
#include <linux/mii.h>
#include <linux/mdio.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl83xx-phy.h"
@ -19,9 +21,6 @@
extern struct rtl83xx_soc_info soc_info;
extern struct mutex smi_lock;
#define PHY_CTRL_REG 0
#define PHY_POWER_BIT 11
#define PHY_PAGE_2 2
#define PHY_PAGE_4 4
@ -124,23 +123,23 @@ static int resume_polling(u64 saved_state)
static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
{
phy_modify(phydev, 0, BIT(11), on?0:BIT(11));
phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
}
static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
{
/* fiber ports */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
phy_modify(phydev, 0x10, BIT(11), on?0:BIT(11));
phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
/* copper ports */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), on?0:BIT(11));
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
}
static void rtl8380_phy_reset(struct phy_device *phydev)
{
phy_modify(phydev, 0, BIT(15), BIT(15));
phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
}
/* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
@ -223,9 +222,9 @@ int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
* which would otherwise read as 0.
*/
if (soc_info.id == 0x8393) {
if (phy_reg == 2)
if (phy_reg == MII_PHYSID1)
return 0x1c;
if (phy_reg == 3)
if (phy_reg == MII_PHYSID2)
return 0x8393;
}
@ -445,20 +444,20 @@ static int rtl8226_read_status(struct phy_device *phydev)
/* Link status must be read twice */
for (int i = 0; i < 2; i++)
val = phy_read_mmd(phydev, MMD_VEND2, 0xA402);
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
phydev->link = val & BIT(2) ? 1 : 0;
if (!phydev->link)
goto out;
/* Read duplex status */
val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
if (val < 0)
goto out;
phydev->duplex = !!(val & BIT(3));
/* Read speed */
val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
switch (val & 0x0630) {
case 0x0000:
phydev->speed = SPEED_10;
@ -493,34 +492,34 @@ static int rtl8226_advertise_aneg(struct phy_device *phydev)
pr_info("In %s\n", __func__);
v = phy_read_mmd(phydev, MMD_AN, 16);
v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
if (v < 0)
goto out;
v |= BIT(5); /* HD 10M */
v |= BIT(6); /* FD 10M */
v |= BIT(7); /* HD 100M */
v |= BIT(8); /* FD 100M */
v |= ADVERTISE_10HALF;
v |= ADVERTISE_10FULL;
v |= ADVERTISE_100HALF;
v |= ADVERTISE_100FULL;
ret = phy_write_mmd(phydev, MMD_AN, 16, v);
ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
/* Allow 1GBit */
v = phy_read_mmd(phydev, MMD_VEND2, 0xA412);
v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
if (v < 0)
goto out;
v |= BIT(9); /* FD 1000M */
v |= ADVERTISE_1000FULL;
ret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v);
ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
if (ret < 0)
goto out;
/* Allow 2.5G */
v = phy_read_mmd(phydev, MMD_AN, 32);
v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
if (v < 0)
goto out;
v |= BIT(7);
ret = phy_write_mmd(phydev, MMD_AN, 32, v);
v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
out:
return ret;
@ -537,22 +536,22 @@ static int rtl8226_config_aneg(struct phy_device *phydev)
if (ret)
goto out;
/* AutoNegotiationEnable */
v = phy_read_mmd(phydev, MMD_AN, 0);
v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
if (v < 0)
goto out;
v |= BIT(12); /* Enable AN */
ret = phy_write_mmd(phydev, MMD_AN, 0, v);
v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
if (ret < 0)
goto out;
/* RestartAutoNegotiation */
v = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
if (v < 0)
goto out;
v |= BIT(9);
v |= MDIO_AN_CTRL1_RESTART;
ret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v);
ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
}
/* TODO: ret = __genphy_config_aneg(phydev, ret); */
@ -569,12 +568,12 @@ static int rtl8226_get_eee(struct phy_device *phydev,
pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
val = phy_read_mmd(phydev, MMD_AN, 60);
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
if (e->eee_enabled) {
e->eee_enabled = !!(val & BIT(1));
e->eee_enabled = !!(val & MDIO_EEE_100TX);
if (!e->eee_enabled) {
val = phy_read_mmd(phydev, MMD_AN, 62);
e->eee_enabled = !!(val & BIT(0));
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
}
}
pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
@ -594,29 +593,29 @@ static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
poll_state = disable_polling(port);
/* Remember aneg state */
val = phy_read_mmd(phydev, MMD_AN, 0);
an_enabled = !!(val & BIT(12));
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
/* Setup 100/1000MBit */
val = phy_read_mmd(phydev, MMD_AN, 60);
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
if (e->eee_enabled)
val |= 0x6;
val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
else
val &= 0x6;
phy_write_mmd(phydev, MMD_AN, 60, val);
val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
/* Setup 2.5GBit */
val = phy_read_mmd(phydev, MMD_AN, 62);
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
if (e->eee_enabled)
val |= 0x1;
val |= MDIO_EEE_2_5GT;
else
val &= 0x1;
phy_write_mmd(phydev, MMD_AN, 62, val);
val &= MDIO_EEE_2_5GT;
phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
/* RestartAutoNegotiation */
val = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
val |= BIT(9);
phy_write_mmd(phydev, MMD_VEND2, 0xA400, val);
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
val |= MDIO_AN_CTRL1_RESTART;
phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
resume_polling(poll_state);
@ -748,8 +747,8 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
// int ipd_flag = 1;
// }
val = phy_read(phydev, 0);
if (val & BIT(11))
val = phy_read(phydev, MII_BMCR);
if (val & BMCR_PDOWN)
rtl8380_int_phy_on_off(phydev, true);
else
rtl8380_phy_reset(phydev);
@ -839,8 +838,8 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
val = phy_read(phydev, 0);
if (val & (1 << 11))
val = phy_read(phydev, MII_BMCR);
if (val & BMCR_PDOWN)
rtl8380_int_phy_on_off(phydev, true);
else
rtl8380_phy_reset(phydev);
@ -939,7 +938,7 @@ static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
if (val & BIT(11))
if (val & BMCR_PDOWN)
return false;
return true;
@ -958,9 +957,9 @@ static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
}
if (on) {
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), 0);
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
} else {
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BIT(11));
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
}
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
@ -1000,9 +999,9 @@ static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
val |= BIT(10);
if (set_fibre) {
val &= ~BIT(11);
val &= ~BMCR_PDOWN;
} else {
val |= BIT(11);
val |= BMCR_PDOWN;
}
phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
@ -1057,13 +1056,12 @@ void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
/* Set GPHY page to copper */
phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
val = phy_read(phydev, 0);
an_enabled = val & BIT(12);
val = phy_read(phydev, MII_BMCR);
an_enabled = val & BMCR_ANENABLE;
/* Enable 100M (bit 1) / 1000M (bit 2) EEE */
val = phy_read_mmd(phydev, 7, 60);
val |= BIT(2) | BIT(1);
phy_write_mmd(phydev, 7, 60, enable ? 0x6 : 0);
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
val |= MDIO_EEE_1000T | MDIO_EEE_100TX;
phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, enable ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
/* 500M EEE ability */
val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
@ -1075,9 +1073,9 @@ void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
/* Restart AN if enabled */
if (an_enabled) {
val = phy_read(phydev, 0);
val |= BIT(9);
phy_write(phydev, 0, val);
val = phy_read(phydev, MII_BMCR);
val |= BMCR_ANRESTART;
phy_write(phydev, MII_BMCR, val);
}
/* GPHY page back to auto */
@ -1095,7 +1093,7 @@ static int rtl8218b_get_eee(struct phy_device *phydev,
/* Set GPHY page to copper */
phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
val = phy_read_paged(phydev, 7, 60);
val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
if (e->eee_enabled) {
/* Verify vs MAC-based EEE */
e->eee_enabled = !!(val & BIT(7));
@ -1123,7 +1121,7 @@ static int rtl8218d_get_eee(struct phy_device *phydev,
/* Set GPHY page to copper */
phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
val = phy_read_paged(phydev, 7, 60);
val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
if (e->eee_enabled)
e->eee_enabled = !!(val & BIT(7));
pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
@ -1155,8 +1153,8 @@ static int rtl8214fc_set_eee(struct phy_device *phydev,
phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
/* Get auto-negotiation status */
val = phy_read(phydev, 0);
an_enabled = val & BIT(12);
val = phy_read(phydev, MII_BMCR);
an_enabled = val & BMCR_ANENABLE;
pr_info("%s: aneg: %d\n", __func__, an_enabled);
val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
@ -1164,7 +1162,7 @@ static int rtl8214fc_set_eee(struct phy_device *phydev,
phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
/* Enable 100M (bit 1) / 1000M (bit 2) EEE */
phy_write_paged(phydev, 7, 60, e->eee_enabled ? 0x6 : 0);
phy_write_paged(phydev, 7, MDIO_AN_EEE_ADV, e->eee_enabled ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
/* 500M EEE ability */
val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
@ -1178,9 +1176,9 @@ static int rtl8214fc_set_eee(struct phy_device *phydev,
/* Restart AN if enabled */
if (an_enabled) {
pr_info("%s: doing aneg\n", __func__);
val = phy_read(phydev, 0);
val |= BIT(9);
phy_write(phydev, 0, val);
val = phy_read(phydev, MII_BMCR);
val |= BMCR_ANRESTART;
phy_write(phydev, MII_BMCR, val);
}
/* GPHY page back to auto */
@ -1218,8 +1216,8 @@ static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
/* Set GPHY page to copper */
phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
val = phy_read(phydev, 0);
an_enabled = val & BIT(12);
val = phy_read(phydev, MII_BMCR);
an_enabled = val & BMCR_ANENABLE;
if (e->eee_enabled) {
/* 100/1000M EEE Capability */
@ -1245,9 +1243,9 @@ static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
/* Restart AN if enabled */
if (an_enabled) {
val = phy_read(phydev, 0);
val |= BIT(9);
phy_write(phydev, 0, val);
val = phy_read(phydev, MII_BMCR);
val |= BMCR_ANRESTART;
phy_write(phydev, MII_BMCR, val);
}
/* GPHY page back to auto */
@ -1342,7 +1340,7 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
val = phy_read(phydev, 16);
if (val & (1 << 11))
if (val & BMCR_PDOWN)
rtl8380_rtl8214fc_on_off(phydev, true);
else
rtl8380_phy_reset(phydev);
@ -2750,17 +2748,17 @@ void rtl9300_phy_enable_10g_1g(int sds_num)
u32 v;
/* Enable 1GBit PHY */
v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG);
v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
pr_info("%s 1gbit phy: %08x\n", __func__, v);
v &= ~BIT(PHY_POWER_BIT);
rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v);
v &= ~BMCR_PDOWN;
rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
/* Enable 10GBit PHY */
v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG);
v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
pr_info("%s 10gbit phy: %08x\n", __func__, v);
v &= ~BIT(PHY_POWER_BIT);
rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v);
v &= ~BMCR_PDOWN;
rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
pr_info("%s 10gbit phy after: %08x\n", __func__, v);
/* dal_longan_construct_mac_default_10gmedia_fiber */

4
target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.h
View File

@ -35,10 +35,6 @@ struct __attribute__ ((__packed__)) fw_header {
#define PHY_ID_RTL8393_I 0x001c8393
#define PHY_ID_RTL9300_I 0x70d03106
/* PHY MMD devices */
#define MMD_AN 7
#define MMD_VEND2 31
/* Registers of the internal Serdes of the 8380 */
#define RTL838X_SDS_MODE_SEL (0x0028)
#define RTL838X_SDS_CFG_REG (0x0034)