diff --git a/include/image-commands.mk b/include/image-commands.mk
index e98861ea56..6b582b0b93 100644
--- a/include/image-commands.mk
+++ b/include/image-commands.mk
@@ -152,6 +152,20 @@ define Build/append-ubi
 		$(call Build/check-size,$(UBI_NAND_SIZE_LIMIT)))
 endef
 
+define Build/ubinize-image
+	sh $(TOPDIR)/scripts/ubinize-image.sh \
+		$(if $(UBOOTENV_IN_UBI),--uboot-env) \
+		$(foreach part,$(UBINIZE_PARTS),--part $(part)) \
+		--part $(word 1,$(1))="$(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(word 2,$(1))" \
+		$@.tmp \
+		-p $(BLOCKSIZE:%k=%KiB) -m $(PAGESIZE) \
+		$(if $(SUBPAGESIZE),-s $(SUBPAGESIZE)) \
+		$(if $(VID_HDR_OFFSET),-O $(VID_HDR_OFFSET)) \
+		$(UBINIZE_OPTS)
+	cat $@.tmp >> $@
+	rm $@.tmp
+endef
+
 define Build/ubinize-kernel
 	cp $@ $@.tmp
 	sh $(TOPDIR)/scripts/ubinize-image.sh \
diff --git a/include/kernel-6.1 b/include/kernel-6.1
index 64aa8ea76b..95dede372a 100644
--- a/include/kernel-6.1
+++ b/include/kernel-6.1
@@ -1,2 +1,2 @@
-LINUX_VERSION-6.1 = .77
-LINUX_KERNEL_HASH-6.1.77 = 3b54ec567716cdfb3618caf38c58a8aab1372cc41c16430633febe9ccdb3f91d
+LINUX_VERSION-6.1 = .78
+LINUX_KERNEL_HASH-6.1.78 = 65206b969831236849c9906eba267e715734a93808e9909fd9b4f12eea10d689
diff --git a/include/package-defaults.mk b/include/package-defaults.mk
index 30b112c7d8..392aad0d5d 100644
--- a/include/package-defaults.mk
+++ b/include/package-defaults.mk
@@ -20,7 +20,7 @@ define Package/Default
   PROVIDES:=
   EXTRA_DEPENDS:=
   MAINTAINER:=$(PKG_MAINTAINER)
-  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(CURDIR))
+  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(patsubst $(TOPDIR)/package/%,feeds/base/%,$(CURDIR)))
   ifneq ($(PKG_VERSION),)
     ifneq ($(PKG_RELEASE),)
       VERSION:=$(PKG_VERSION)-$(PKG_RELEASE)
diff --git a/include/rootfs.mk b/include/rootfs.mk
index f2ed648d2f..2128aefc2a 100644
--- a/include/rootfs.mk
+++ b/include/rootfs.mk
@@ -87,6 +87,11 @@ define prepare_rootfs
 			fi; \
 		done || true \
 	)
+	awk -i inplace \
+		'/^Status:/ { \
+			if ($$3 == "user") { $$3 = "ok" } \
+			else { sub(/,\<user\>|\<user\>,/, "", $$3) } \
+		}1' $(1)/usr/lib/opkg/status
 	$(if $(SOURCE_DATE_EPOCH),sed -i "s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/" $(1)/usr/lib/opkg/status)
 	@-find $(1) -name CVS -o -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf
 	rm -rf \
diff --git a/include/toplevel.mk b/include/toplevel.mk
index f2dfde60cf..4ec99b30de 100644
--- a/include/toplevel.mk
+++ b/include/toplevel.mk
@@ -77,7 +77,8 @@ _ignore = $(foreach p,$(IGNORE_PACKAGES),--ignore $(p))
 
 prepare-tmpinfo: FORCE
 	@+$(MAKE) -r -s $(STAGING_DIR_HOST)/.prereq-build $(PREP_MK)
-	mkdir -p tmp/info
+	mkdir -p tmp/info feeds
+	[ -e $(TOPDIR)/feeds/base ] || ln -sf $(TOPDIR)/package $(TOPDIR)/feeds/base
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="packageinfo" SCAN_DIR="package" SCAN_NAME="package" SCAN_DEPTH=5 SCAN_EXTRA=""
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="targetinfo" SCAN_DIR="target/linux" SCAN_NAME="target" SCAN_DEPTH=3 SCAN_EXTRA="" SCAN_MAKEOPTS="TARGET_BUILD=1"
 	for type in package target; do \
diff --git a/package/boot/arm-trusted-firmware-mediatek/Makefile b/package/boot/arm-trusted-firmware-mediatek/Makefile
index 259a987e6b..abdd6e7e4a 100644
--- a/package/boot/arm-trusted-firmware-mediatek/Makefile
+++ b/package/boot/arm-trusted-firmware-mediatek/Makefile
@@ -26,12 +26,14 @@ include $(INCLUDE_DIR)/package.mk
 define Trusted-Firmware-A/Default
   BUILD_TARGET:=mediatek
   TFA_IMAGE:=bl2.img bl31.bin
+  HIDDEN:=y
   BOOT_DEVICE:=
   DDR3_FLYBY:=
   DDR_TYPE:=
   NAND_TYPE:=
   BOARD_QFN:=
   DRAM_USE_COMB:=
+  USE_UBI:=
 endef
 
 define Trusted-Firmware-A/mt7622-nor-1ddr
@@ -56,6 +58,14 @@ define Trusted-Firmware-A/mt7622-snand-1ddr
   BOOT_DEVICE:=snand
 endef
 
+define Trusted-Firmware-A/mt7622-snand-ubi-1ddr
+  NAME:=MediaTek MT7622 (SPI-NAND using UBI, 1x DDR3)
+  BUILD_SUBTARGET:=mt7622
+  PLAT:=mt7622
+  BOOT_DEVICE:=snand
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7622-snand-2ddr
   NAME:=MediaTek MT7622 (SPI-NAND, 2x DDR3)
   BUILD_SUBTARGET:=mt7622
@@ -64,6 +74,15 @@ define Trusted-Firmware-A/mt7622-snand-2ddr
   DDR3_FLYBY:=1
 endef
 
+define Trusted-Firmware-A/mt7622-snand-ubi-2ddr
+  NAME:=MediaTek MT7622 (SPI-NAND using UBI, 2x DDR3)
+  BUILD_SUBTARGET:=mt7622
+  PLAT:=mt7622
+  BOOT_DEVICE:=snand
+  DDR3_FLYBY:=1
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7622-emmc-1ddr
   NAME:=MediaTek MT7622 (eMMC, 1x DDR3)
   BUILD_SUBTARGET:=mt7622
@@ -191,6 +210,16 @@ define Trusted-Firmware-A/mt7986-spim-nand-ddr4
   NAND_TYPE:=spim:2k+64
 endef
 
+define Trusted-Firmware-A/mt7986-spim-nand-ubi-ddr4
+  NAME:=MediaTek MT7986 (SPI-NAND via SPIM using UBI, DDR4)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7986
+  DDR_TYPE:=ddr4
+  NAND_TYPE:=spim:2k+64
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7986-spim-nand-4k-ddr4
   NAME:=MediaTek MT7986 (SPI-NAND via SPIM, DDR4)
   BOOT_DEVICE:=spim-nand
@@ -352,6 +381,15 @@ define Trusted-Firmware-A/mt7988-snand-comb
   DRAM_USE_COMB:=1
 endef
 
+define Trusted-Firmware-A/mt7988-snand-ubi-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SNFI, UBI)
+  BOOT_DEVICE:=snand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+  USE_UBI:=1
+endef
+
 define Trusted-Firmware-A/mt7988-spim-nand-comb
   NAME:=MediaTek MT7988 (SPI-NAND via SPIM)
   BOOT_DEVICE:=spim-nand
@@ -360,11 +398,22 @@ define Trusted-Firmware-A/mt7988-spim-nand-comb
   DRAM_USE_COMB:=1
 endef
 
+define Trusted-Firmware-A/mt7988-spim-nand-ubi-comb
+  NAME:=MediaTek MT7988 (SPI-NAND via SPIM, UBI)
+  BOOT_DEVICE:=spim-nand
+  BUILD_SUBTARGET:=filogic
+  PLAT:=mt7988
+  DRAM_USE_COMB:=1
+  USE_UBI:=1
+endef
+
 TFA_TARGETS:= \
 	mt7622-nor-1ddr \
 	mt7622-nor-2ddr \
 	mt7622-snand-1ddr \
+	mt7622-snand-ubi-1ddr \
 	mt7622-snand-2ddr \
+	mt7622-snand-ubi-2ddr \
 	mt7622-emmc-1ddr \
 	mt7622-emmc-2ddr \
 	mt7622-sdmmc-1ddr \
@@ -386,6 +435,7 @@ TFA_TARGETS:= \
 	mt7986-sdmmc-ddr4 \
 	mt7986-snand-ddr4 \
 	mt7986-spim-nand-ddr4 \
+	mt7986-spim-nand-ubi-ddr4 \
 	mt7986-spim-nand-4k-ddr4 \
 	mt7988-emmc-ddr3 \
 	mt7988-nor-ddr3 \
@@ -401,7 +451,9 @@ TFA_TARGETS:= \
 	mt7988-nor-comb \
 	mt7988-sdmmc-comb \
 	mt7988-snand-comb \
-	mt7988-spim-nand-comb
+	mt7988-snand-ubi-comb \
+	mt7988-spim-nand-comb \
+	mt7988-spim-nand-ubi-comb
 
 TFA_MAKE_FLAGS += \
 	BOOT_DEVICE=$(BOOT_DEVICE) \
@@ -412,6 +464,7 @@ TFA_MAKE_FLAGS += \
 	HAVE_DRAM_OBJ_FILE=yes \
 	$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \
 	$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
+	$(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \
 	all
 
 define Package/trusted-firmware-a/install
diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic
index 5b4099f3c1..5a919b33d5 100644
--- a/package/boot/uboot-envtools/files/mediatek_filogic
+++ b/package/boot/uboot-envtools/files/mediatek_filogic
@@ -11,33 +11,46 @@ touch /etc/config/ubootenv
 
 board=$(board_name)
 
+ubootenv_add_mmc_default() {
+	local envdev="$(find_mmc_part "ubootenv" "${1:-mmcblk0}")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
+	ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+}
+
+ubootenv_add_nor_default() {
+	local envdev="/dev/mtd$(find_mtd_index "u-boot-env")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
+	ubootenv_add_uci_config "$envdev" "0x20000" "0x20000" "0x20000" "1"
+}
+
+ubootenv_add_ubi_default() {
+	. /lib/upgrade/nand.sh
+	local envubi=$(nand_find_ubi ubi)
+	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
+	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
+	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+}
+
 case "$board" in
 asus,rt-ax59u)
 	ubootenv_add_uci_config "/dev/mtd0" "0x100000" "0x20000" "0x20000"
 	;;
 bananapi,bpi-r3|\
-bananapi,bpi-r3-mini)
-	rootdev="$(cmdline_get_var root)"
-	rootdev="${rootdev##*/}"
-	rootdev="${rootdev%%p[0-9]*}"
-	case "$rootdev" in
+bananapi,bpi-r3-mini|\
+bananapi,bpi-r4)
+	. /lib/upgrade/platform.sh
+
+	bootdev="$(platform_get_bootdev)"
+	case "$bootdev" in
+	ubi*)
+		ubootenv_add_ubi_default
+		;;
 	mmc*)
-		local envdev=$(find_mmc_part "ubootenv" $rootdev)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
-		ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+		ubootenv_add_mmc_default "${bootdev%%p[0-9]*}"
 		;;
 	mtd*)
-		local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
-		ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
-		ubootenv_add_uci_config "$envdev" "0x20000" "0x20000" "0x20000" "1"
-		;;
-	ubi*)
-		. /lib/upgrade/nand.sh
-		local envubi=$(nand_find_ubi ubi)
-		local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-		local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_nor_default
 		;;
 	esac
 	;;
@@ -52,17 +65,10 @@ zbtlink,zbt-z8103ax)
 cmcc,rax3000m)
 	case "$(cmdline_get_var root)" in
 	/dev/mmc*)
-		local envdev=$(find_mmc_part "ubootenv" "mmcblk0")
-		ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
-		ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+		ubootenv_add_mmc_default
 		;;
 	*)
-		. /lib/upgrade/nand.sh
-		local envubi=$(nand_find_ubi ubi)
-		local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-		local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_ubi_default
 		;;
 	esac
 	;;
@@ -87,20 +93,13 @@ xiaomi,mi-router-ax3000t-ubootmod|\
 xiaomi,mi-router-wr30u-ubootmod|\
 xiaomi,redmi-router-ax6000-ubootmod|\
 zyxel,ex5601-t0-ubootmod)
-	. /lib/upgrade/nand.sh
-	local envubi=$(nand_find_ubi ubi)
-	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
-	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
-	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x20000" "1"
-	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x20000" "1"
+	ubootenv_add_ubi_default
 	;;
 imou,lc-hx3001-ubootmod)
 	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x80000" "1"
 	;;
 jdcloud,re-cp-03)
-	local envdev=$(find_mmc_part "ubootenv" "mmcblk0")
-	ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
-	ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
+	ubootenv_add_mmc_default
 	;;
 livinet,zr-3020|\
 livinet,zr-3020-ubootmod)
diff --git a/package/boot/uboot-envtools/files/mediatek_mt7622 b/package/boot/uboot-envtools/files/mediatek_mt7622
index fdf0d331fc..b4b1698d3f 100644
--- a/package/boot/uboot-envtools/files/mediatek_mt7622
+++ b/package/boot/uboot-envtools/files/mediatek_mt7622
@@ -9,6 +9,21 @@ touch /etc/config/ubootenv
 . /lib/uboot-envtools.sh
 . /lib/functions.sh
 
+ubootenv_add_mmc_default() {
+	local envdev="$(find_mmc_part "ubootenv" "${1:-mmcblk0}")"
+	ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
+	ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
+}
+
+ubootenv_add_ubi_default() {
+	. /lib/upgrade/nand.sh
+	local envubi=$(nand_find_ubi ubi)
+	local envdev=/dev/$(nand_find_volume $envubi ubootenv)
+	local envdev2=/dev/$(nand_find_volume $envubi ubootenv2)
+	ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1"
+}
+
 board=$(board_name)
 
 case "$board" in
@@ -17,22 +32,17 @@ dlink,eagle-pro-ai-r32-a1)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x2000" "0x2000"
 	;;
 linksys,e8450-ubi)
-	ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1"
-	ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1"
+	ubootenv_add_ubi_default
 	;;
 bananapi,bpi-r64)
-	rootdev="$(cmdline_get_var root)"
-	rootdev="${rootdev##*/}"
-	rootdev="${rootdev%%p[0-9]*}"
-	case "$rootdev" in
+	. /lib/upgrade/platform.sh
+	bootdev="$(platform_get_bootdev)"
+	case "$bootdev" in
 	mmc*)
-		local envdev=$(find_mmc_part "ubootenv" $rootdev)
-		ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
-		ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
+		ubootenv_add_mmc_default "${bootdev%p[0-9]*}"
 		;;
 	ubi*)
-		ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1"
-		ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_ubi_default
 		;;
 	esac
 	;;
@@ -42,8 +52,10 @@ buffalo,wsr-2533dhp2)
 ruijie,rg-ew3200gx-pro)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x20000" "0x20000"
 	;;
-ubnt,unifi-6-lr-ubootmod)
-	ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x4000" "0x1000"
+ubnt,unifi-6-lr-v1-ubootmod|\
+ubnt,unifi-6-lr-v2-ubootmod|\
+ubnt,unifi-6-lr-v3-ubootmod)
+	ubootenv_add_uci_config "/dev/mtd$(find_mtd_index "u-boot-env")" "0x0" "0x4000" "0x1000"
 	;;
 xiaomi,redmi-router-ax6s)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000" "0x40000"
diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile
index 3a39e05eb6..c96f7da882 100644
--- a/package/boot/uboot-mediatek/Makefile
+++ b/package/boot/uboot-mediatek/Makefile
@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2023.07.02
-PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
+PKG_VERSION:=2024.01
+PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host
 
 UBOOT_USE_INTREE_DTC:=1
@@ -75,6 +75,15 @@ define U-Boot/mt7621_nand_rfb
   UBOOT_IMAGE:=u-boot-mt7621.bin
 endef
 
+define U-Boot/mt7621_zbtlink_zbt-wg3526-16m
+  NAME:=Zbtlink ZBT-WG3526-16m
+  UBOOT_CONFIG:=mt7621_zbtlink_zbt-wg3526-16m
+  BUILD_DEVICES:=zbtlink_zbt-wg3526-16m
+  BUILD_TARGET:=ramips
+  BUILD_SUBTARGET:=mt7621
+  UBOOT_IMAGE:=u-boot-mt7621.bin
+endef
+
 define U-Boot/mt7622_rfb1
   NAME:=MT7622 Reference Board 1
   UBOOT_CONFIG:=mt7622_rfb
@@ -88,9 +97,9 @@ define U-Boot/mt7622_linksys_e8450
   BUILD_DEVICES:=linksys_e8450-ubi
   BUILD_SUBTARGET:=mt7622
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=snand
+  BL2_BOOTDEV:=snand-ubi
   BL2_DDRBLOB:=1
-  DEPENDS:=+trusted-firmware-a-mt7622-snand-1ddr
+  DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-1ddr
 endef
 
 define U-Boot/mt7622_bananapi_bpi-r64-emmc
@@ -121,9 +130,9 @@ define U-Boot/mt7622_bananapi_bpi-r64-snand
   BUILD_DEVICES:=bananapi_bpi-r64
   BUILD_SUBTARGET:=mt7622
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=snand
+  BL2_BOOTDEV:=snand-ubi
   BL2_DDRBLOB:=2
-  DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr
+  DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-2ddr
 endef
 
 define U-Boot/mt7622_ubnt_unifi-6-lr-v1
@@ -186,7 +195,7 @@ define U-Boot/mt7628_rfb
   UBOOT_IMAGE:=u-boot-with-spl.bin
 endef
 
-define U-Boot/ravpower_rp-wd009
+define U-Boot/mt7628_ravpower_rp-wd009
   NAME:=RAVPower RP-WD009
   BUILD_TARGET:=ramips
   BUILD_DEVICES:=ravpower_rp-wd009
@@ -388,10 +397,10 @@ define U-Boot/mt7986_bananapi_bpi-r3-snand
   BUILD_DEVICES:=bananapi_bpi-r3
   UBOOT_CONFIG:=mt7986a_bpi-r3-snand
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
+  BL2_BOOTDEV:=spim-nand-ubi
   BL2_SOC:=mt7986
   BL2_DDRTYPE:=ddr4
-  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
+  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4
 endef
 
 define U-Boot/mt7986_bananapi_bpi-r3-nor
@@ -425,10 +434,10 @@ define U-Boot/mt7986_bananapi_bpi-r3-mini-snand
   BUILD_DEVICES:=bananapi_bpi-r3-mini
   UBOOT_CONFIG:=mt7986a_bpi-r3-mini-snand
   UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
+  BL2_BOOTDEV:=spim-nand-ubi
   BL2_SOC:=mt7986
   BL2_DDRTYPE:=ddr4
-  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
+  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4
 endef
 
 define U-Boot/mt7986_glinet_gl-mt6000
@@ -515,6 +524,42 @@ define U-Boot/mt7986_zyxel_ex5601-t0
   DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4
 endef
 
+define U-Boot/mt7988_bananapi_bpi-r4-emmc
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-emmc
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=emmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-sdmmc
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-sdmmc
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=sdmmc
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-snand
+  NAME:=BananaPi BPi-R4
+  BUILD_SUBTARGET:=filogic
+  BUILD_DEVICES:=bananapi_bpi-r4
+  UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-snand
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=spim-nand-ubi
+  BL2_SOC:=mt7988
+  BL2_DDRTYPE:=comb
+  DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb
+endef
+
 define U-Boot/mt7988_rfb-spim-nand
   NAME:=MT7988 Reference Board
   BUILD_SUBTARGET:=filogic
@@ -581,6 +626,7 @@ UBOOT_TARGETS := \
 	mt7620_rfb \
 	mt7621_nand_rfb \
 	mt7621_rfb \
+	mt7621_zbtlink_zbt-wg3526-16m \
 	mt7622_bananapi_bpi-r64-emmc \
 	mt7622_bananapi_bpi-r64-sdmmc \
 	mt7622_bananapi_bpi-r64-snand \
@@ -592,7 +638,7 @@ UBOOT_TARGETS := \
 	mt7623n_bpir2 \
 	mt7623a_unielec_u7623 \
 	mt7628_rfb \
-	ravpower_rp-wd009 \
+	mt7628_ravpower_rp-wd009 \
 	mt7629_rfb \
 	mt7981_cmcc_rax3000m-emmc \
 	mt7981_cmcc_rax3000m-nand \
@@ -620,6 +666,9 @@ UBOOT_TARGETS := \
 	mt7986_xiaomi_redmi-router-ax6000 \
 	mt7986_zyxel_ex5601-t0 \
 	mt7986_rfb \
+	mt7988_bananapi_bpi-r4-emmc \
+	mt7988_bananapi_bpi-r4-sdmmc \
+	mt7988_bananapi_bpi-r4-snand \
 	mt7988_rfb-spim-nand \
 	mt7988_rfb-snand \
 	mt7988_rfb-nor \
diff --git a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
index 60eda91124..dcbf8b953f 100644
--- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
+++ b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch
@@ -18,9 +18,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
 +CONFIG_ENV_SIZE=0x20000
 +CONFIG_ENV_OFFSET=0x280000
- CONFIG_SYS_PROMPT="MT7622> "
  CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=25000000
+ CONFIG_SYS_LOAD_ADDR=0x4007ff28
 @@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y
  CONFIG_CMD_PING=y
  CONFIG_CMD_SMC=y
diff --git a/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch b/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch
deleted file mode 100644
index d5f6f73762..0000000000
--- a/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 19f2aa053d5531a9ca0ece04dca172a522d58b90 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Fri, 29 Jul 2022 11:32:28 +0800
-Subject: [PATCH 32/71] clk: remove log_ret from clk_get_rate
-
-The return value of clk_get_rate is ulong, an unsigned type. The size of
-ulong depends on the cpu architecture, i.e. 4 bytes on 32-bit CPUs and
-8 bytes on 64-bit CPUs.
-
-However log_ret only accepts and returns value in int type, a fixed 4-byte
-type. This may truncate the real clock value and cause unexpected error on
-64-bit platforms.
-
-This patch removes log_ret to solve this issue.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/clk/clk-uclass.c | 7 +------
- 1 file changed, 1 insertion(+), 6 deletions(-)
-
---- a/drivers/clk/clk-uclass.c
-+++ b/drivers/clk/clk-uclass.c
-@@ -471,7 +471,6 @@ void clk_free(struct clk *clk)
- ulong clk_get_rate(struct clk *clk)
- {
- 	const struct clk_ops *ops;
--	int ret;
- 
- 	debug("%s(clk=%p)\n", __func__, clk);
- 	if (!clk_valid(clk))
-@@ -481,11 +480,7 @@ ulong clk_get_rate(struct clk *clk)
- 	if (!ops->get_rate)
- 		return -ENOSYS;
- 
--	ret = ops->get_rate(clk);
--	if (ret)
--		return log_ret(ret);
--
--	return 0;
-+	return ops->get_rate(clk);
- }
- 
- struct clk *clk_get_parent(struct clk *clk)
diff --git a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
index da87978aef..9b02b4dc63 100644
--- a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
+++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch
@@ -17,37 +17,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  7 files changed, 299 insertions(+), 3 deletions(-)
  create mode 100644 env/mtd.c
 
---- a/cmd/nvedit.c
-+++ b/cmd/nvedit.c
-@@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 	defined(CONFIG_ENV_IS_IN_MMC)		|| \
- 	defined(CONFIG_ENV_IS_IN_FAT)		|| \
- 	defined(CONFIG_ENV_IS_IN_EXT4)		|| \
-+	defined(CONFIG_ENV_IS_IN_MTD)		|| \
- 	defined(CONFIG_ENV_IS_IN_NAND)		|| \
- 	defined(CONFIG_ENV_IS_IN_NVRAM)		|| \
- 	defined(CONFIG_ENV_IS_IN_ONENAND)	|| \
-@@ -61,7 +62,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- #if	!defined(ENV_IS_IN_DEVICE)		&& \
- 	!defined(CONFIG_ENV_IS_NOWHERE)
--# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\
-+# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\
- NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
- #endif
- 
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE
+@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT
  		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
  		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
  		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
 -		     !ENV_IS_IN_UBI
 +		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
- 	help
- 	  Define this if you don't want to or can't have an environment stored
- 	  on a storage medium. In this case the environment will still exist
-@@ -251,6 +251,27 @@ config ENV_IS_IN_MMC
+ 	select ENV_IS_NOWHERE
+ 
+ config ENV_IS_NOWHERE
+@@ -254,6 +254,27 @@ config ENV_IS_IN_MMC
  	  offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant".
  	  CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used.
  
@@ -75,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config ENV_IS_IN_NAND
  	bool "Environment in a NAND device"
  	depends on !CHAIN_OF_TRUST
-@@ -558,10 +579,16 @@ config ENV_ADDR_REDUND
+@@ -561,10 +582,16 @@ config ENV_ADDR_REDUND
  	  Offset from the start of the device (or partition) of the redundant
  	  environment location.
  
@@ -93,7 +74,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
  	default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
  	default 0xF0000 if ARCH_SUNXI
-@@ -609,6 +636,12 @@ config ENV_SECT_SIZE
+@@ -622,6 +649,12 @@ config ENV_SECT_SIZE
  	help
  	  Size of the sector containing the environment.
  
@@ -118,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o
 --- a/env/env.c
 +++ b/env/env.c
-@@ -69,6 +69,9 @@ static enum env_location env_locations[]
+@@ -46,6 +46,9 @@ static enum env_location env_locations[]
  #ifdef CONFIG_ENV_IS_IN_MMC
  	ENVL_MMC,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
index 93fc32cf9e..da4dce917b 100644
--- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
+++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/common/board_r.c
 +++ b/common/board_r.c
-@@ -388,6 +388,20 @@ static int initr_nand(void)
+@@ -373,6 +373,20 @@ static int initr_nand(void)
  }
  #endif
  
@@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  #if defined(CONFIG_CMD_ONENAND)
  /* go init the NAND */
  static int initr_onenand(void)
-@@ -696,6 +710,9 @@ static init_fnc_t init_sequence_r[] = {
+@@ -675,6 +689,9 @@ static init_fnc_t init_sequence_r[] = {
  #ifdef CONFIG_CMD_ONENAND
  	initr_onenand,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
index 35d8f115f6..4eb2bc9ccf 100644
--- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
+++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1353,6 +1353,12 @@ config CMD_NAND_TORTURE
+@@ -1392,6 +1392,12 @@ config CMD_NAND_TORTURE
  
  endif # CMD_NAND
  
@@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	depends on NVME
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
+@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
  endif
  obj-$(CONFIG_CMD_MUX) += mux.o
  obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
index 6336fb33f5..c6358f3287 100644
--- a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
+++ b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
@@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  #ifdef CONFIG_AUTO_COMPLETE
  static int mtd_name_complete(int argc, char *const argv[], char last_char,
  			     int maxv, char *cmdv[])
-@@ -552,6 +588,7 @@ static char mtd_help_text[] =
+@@ -551,6 +587,7 @@ U_BOOT_LONGHELP(mtd,
  	"\n"
  	"Specific functions:\n"
  	"mtd bad                               <name>\n"
@@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  	"\n"
  	"With:\n"
  	"\t<name>: NAND partition/chip name (or corresponding DM device name or OF path)\n"
-@@ -577,4 +614,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
+@@ -575,4 +612,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
  		U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase,
  					     mtd_name_complete),
  		U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad,
diff --git a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
index 0b4ee32b62..dbb1e2e59d 100644
--- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
+++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
@@ -17,37 +17,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  7 files changed, 180 insertions(+), 3 deletions(-)
  create mode 100644 env/nmbm.c
 
---- a/cmd/nvedit.c
-+++ b/cmd/nvedit.c
-@@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
- 	defined(CONFIG_ENV_IS_IN_EXT4)		|| \
- 	defined(CONFIG_ENV_IS_IN_MTD)		|| \
- 	defined(CONFIG_ENV_IS_IN_NAND)		|| \
-+	defined(CONFIG_ENV_IS_IN_NMBM)		|| \
- 	defined(CONFIG_ENV_IS_IN_NVRAM)		|| \
- 	defined(CONFIG_ENV_IS_IN_ONENAND)	|| \
- 	defined(CONFIG_ENV_IS_IN_SPI_FLASH)	|| \
-@@ -63,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
- #if	!defined(ENV_IS_IN_DEVICE)		&& \
- 	!defined(CONFIG_ENV_IS_NOWHERE)
- # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\
--NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
-+NAND|NMBM|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
- #endif
- 
- /*
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE
+@@ -59,6 +59,7 @@ config ENV_IS_DEFAULT
+ 	def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \
+ 		     !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \
  		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
++		     !ENV_IS_IN_NMBM && \
  		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
  		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
--		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
-+		     !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD
- 	help
- 	  Define this if you don't want to or can't have an environment stored
- 	  on a storage medium. In this case the environment will still exist
-@@ -312,6 +312,21 @@ config ENV_RANGE
+ 		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
+@@ -315,6 +316,21 @@ config ENV_RANGE
  	  Specifying a range with more erase blocks than are needed to hold
  	  CONFIG_ENV_SIZE allows bad blocks within the range to be avoided.
  
@@ -69,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config ENV_IS_IN_NVRAM
  	bool "Environment in a non-volatile RAM"
  	depends on !CHAIN_OF_TRUST
-@@ -588,7 +603,7 @@ config ENV_MTD_NAME
+@@ -591,7 +607,7 @@ config ENV_MTD_NAME
  config ENV_OFFSET
  	hex "Environment offset"
  	depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
@@ -90,7 +70,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
 --- a/env/env.c
 +++ b/env/env.c
-@@ -75,6 +75,9 @@ static enum env_location env_locations[]
+@@ -52,6 +52,9 @@ static enum env_location env_locations[]
  #ifdef CONFIG_ENV_IS_IN_NAND
  	ENVL_NAND,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
index f3831e07f7..e6e12ae24c 100644
--- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
+++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch
@@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1353,6 +1353,14 @@ config CMD_NAND_TORTURE
+@@ -1392,6 +1392,14 @@ config CMD_NAND_TORTURE
  
  endif # CMD_NAND
  
@@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	bool "nmbm"
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o
+@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o
  endif
  obj-$(CONFIG_CMD_MUX) += mux.o
  obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
index d9a645d20e..da09cd9c08 100644
--- a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -2848,6 +2848,100 @@ static int spi_nor_init_params(struct sp
+@@ -2854,6 +2854,100 @@ static int spi_nor_init_params(struct sp
  	return 0;
  }
  
@@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  {
  	size_t i;
-@@ -4045,6 +4139,7 @@ int spi_nor_scan(struct spi_nor *nor)
+@@ -4051,6 +4145,7 @@ int spi_nor_scan(struct spi_nor *nor)
  	nor->write = spi_nor_write_data;
  	nor->read_reg = spi_nor_read_reg;
  	nor->write_reg = spi_nor_write_reg;
diff --git a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch
index ce59cc73ae..f7cbd8d052 100644
--- a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch
@@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/cmd/sf.c
 +++ b/cmd/sf.c
-@@ -407,6 +407,14 @@ static int do_spi_protect(int argc, char
+@@ -412,6 +412,14 @@ static int do_spi_protect(int argc, char
  	return ret == 0 ? 0 : 1;
  }
  
@@ -27,22 +27,20 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  enum {
  	STAGE_ERASE,
  	STAGE_CHECK,
-@@ -601,6 +609,8 @@ static int do_spi_flash(struct cmd_tbl *
+@@ -606,6 +614,8 @@ static int do_spi_flash(struct cmd_tbl *
  		ret = do_spi_flash_erase(argc, argv);
- 	else if (strcmp(cmd, "protect") == 0)
+ 	else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
  		ret = do_spi_protect(argc, argv);
 +	else if (strcmp(cmd, "uuid") == 0)
 +		ret = do_spi_flash_read_uuid();
  	else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
  		ret = do_spi_flash_test(argc, argv);
  	else
-@@ -626,7 +636,8 @@ static const char long_help[] =
- 	"					  at `addr' to flash at `offset'\n"
- 	"					  or to start of mtd `partition'\n"
- 	"sf protect lock/unlock sector len	- protect/unprotect 'len' bytes starting\n"
--	"					  at address 'sector'"
-+	"					  at address 'sector'\n"
-+	"sf uuid					- read uuid from flash"
+@@ -636,6 +646,7 @@ U_BOOT_LONGHELP(sf,
  #ifdef CONFIG_CMD_SF_TEST
  	"\nsf test offset len		- run a very basic destructive test"
  #endif
++	"sf uuid				- read uuid from flash"
+ 	);
+ 
+ U_BOOT_CMD(
diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
index 315f7f92a3..0438895fdb 100644
--- a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
+++ b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
@@ -255,15 +255,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  };
  
  /** enum bootmenu_key - keys that can be returned by the bootmenu */
-@@ -54,6 +59,7 @@ enum bootmenu_key {
- 	BKEY_MINUS,
- 	BKEY_SPACE,
+@@ -51,6 +56,7 @@ enum bootmenu_key {
+ 	BKEY_SELECT,
+ 	BKEY_QUIT,
  	BKEY_SAVE,
 +	BKEY_CHOICE,
  
- 	BKEY_COUNT,
- };
-@@ -76,7 +82,7 @@ enum bootmenu_key {
+ 	/* 'extra' keys, which are used by menus but not cedit */
+ 	BKEY_PLUS,
+@@ -81,7 +87,7 @@ enum bootmenu_key {
   *	anything else: KEY_NONE
   */
  enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu,
@@ -272,7 +272,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  /**
   * bootmenu_loop() - handle waiting for a keypress when autoboot is disabled
-@@ -102,7 +108,7 @@ enum bootmenu_key bootmenu_autoboot_loop
+@@ -107,7 +113,7 @@ enum bootmenu_key bootmenu_autoboot_loop
   *	Space: BKEY_SPACE
   */
  enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu,
@@ -281,7 +281,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  /**
   * bootmenu_conv_key() - Convert a U-Boot keypress into a menu key
-@@ -110,6 +116,7 @@ enum bootmenu_key bootmenu_loop(struct b
+@@ -115,6 +121,7 @@ enum bootmenu_key bootmenu_loop(struct b
   * @ichar: Keypress to convert (ASCII, including control characters)
   * Returns: Menu key that corresponds to @ichar, or BKEY_NONE if none
   */
@@ -301,7 +301,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  
  		switch (key) {
  		case BKEY_UP:
-@@ -1937,7 +1937,7 @@ char *eficonfig_choice_change_boot_order
+@@ -1838,7 +1838,7 @@ char *eficonfig_choice_change_boot_order
  
  	cli_ch_init(cch);
  	while (1) {
@@ -312,7 +312,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		case BKEY_PLUS:
 --- a/boot/bootflow_menu.c
 +++ b/boot/bootflow_menu.c
-@@ -231,7 +231,7 @@ int bootflow_menu_run(struct bootstd_pri
+@@ -235,7 +235,7 @@ int bootflow_menu_run(struct bootstd_pri
  
  		key = 0;
  		if (ichar) {
diff --git a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
index 149a156ba2..f017ce92ad 100644
--- a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
+++ b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch
@@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/common/spl/spl_nand.c
 +++ b/common/spl/spl_nand.c
-@@ -16,7 +16,11 @@
+@@ -17,7 +17,11 @@
  
  uint32_t __weak spl_nand_get_uboot_raw_page(void)
  {
diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
index 93a940b943..ef20c2dfb6 100644
--- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
+++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch
@@ -89,14 +89,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		reg = <0x11014000 0x1000>;
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME
+@@ -144,9 +144,11 @@ config SYS_CONFIG_NAME
  
  config MTK_BROM_HEADER_INFO
  	string
 -	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
 +	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
  	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
- 	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
+ 	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
  	default "lk=1" if TARGET_MT7623
  
 +source "board/mediatek/mt7629/Kconfig"
diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
index cb3f1ff2af..9dc1a57722 100644
--- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
+++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch
@@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1308,6 +1308,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1425,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  	mt7623n-bananapi-bpi-r2.dtb \
  	mt7629-rfb.dtb \
  	mt7981-rfb.dtb \
diff --git a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
index bd68677eb0..15e943b1c0 100644
--- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
+++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/spi/spi-nor-core.c
 +++ b/drivers/mtd/spi/spi-nor-core.c
-@@ -673,6 +673,7 @@ static int set_4byte(struct spi_nor *nor
+@@ -674,6 +674,7 @@ static int set_4byte(struct spi_nor *nor
  	case SNOR_MFR_ISSI:
  	case SNOR_MFR_MACRONIX:
  	case SNOR_MFR_WINBOND:
@@ -45,7 +45,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -468,6 +474,16 @@ const struct flash_info spi_nor_ids[] =
+@@ -474,6 +480,16 @@ const struct flash_info spi_nor_ids[] =
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  	},
  	{
@@ -62,7 +62,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-@@ -517,6 +533,11 @@ const struct flash_info spi_nor_ids[] =
+@@ -523,6 +539,11 @@ const struct flash_info spi_nor_ids[] =
  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  	},
  	{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
index 0e233bb1d2..20489d8726 100644
--- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
+++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
@@ -20,66 +20,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  10 files changed, 923 insertions(+), 225 deletions(-)
  create mode 100644 drivers/mtd/nand/spi/etron.c
 
---- a/drivers/mtd/nand/spi/Kconfig
-+++ b/drivers/mtd/nand/spi/Kconfig
-@@ -5,3 +5,4 @@ menuconfig MTD_SPI_NAND
- 	select SPI_MEM
- 	help
- 	  This is the framework for the SPI NAND device drivers.
-+
 --- a/drivers/mtd/nand/spi/Makefile
 +++ b/drivers/mtd/nand/spi/Makefile
 @@ -1,4 +1,4 @@
  # SPDX-License-Identifier: GPL-2.0
  
--spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
-+spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o etron.o
+-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
++spinand-objs := core.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
  obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
 --- a/drivers/mtd/nand/spi/core.c
 +++ b/drivers/mtd/nand/spi/core.c
-@@ -17,6 +17,7 @@
- #include <linux/mtd/spinand.h>
- #include <linux/of.h>
- #include <linux/slab.h>
-+#include <linux/string.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
- #else
-@@ -451,10 +452,11 @@ out:
- 	return status & STATUS_BUSY ? -ETIMEDOUT : 0;
- }
- 
--static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
-+static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
-+			      u8 ndummy, u8 *buf)
- {
--	struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
--						 SPINAND_MAX_ID_LEN);
-+	struct spi_mem_op op = SPINAND_READID_OP(
-+		naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
- 	int ret;
- 
- 	ret = spi_mem_exec_op(spinand->slave, &op);
-@@ -464,18 +466,6 @@ static int spinand_read_id_op(struct spi
- 	return ret;
- }
- 
--static int spinand_reset_op(struct spinand_device *spinand)
--{
--	struct spi_mem_op op = SPINAND_RESET_OP;
--	int ret;
--
--	ret = spi_mem_exec_op(spinand->slave, &op);
--	if (ret)
--		return ret;
--
--	return spinand_wait(spinand, NULL);
--}
--
- static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
- {
- 	return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
-@@ -829,6 +819,7 @@ static const struct nand_ops spinand_ops
+@@ -822,6 +822,7 @@ static const struct nand_ops spinand_ops
  };
  
  static const struct spinand_manufacturer *spinand_manufacturers[] = {
@@ -87,140 +38,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  	&gigadevice_spinand_manufacturer,
  	&macronix_spinand_manufacturer,
  	&micron_spinand_manufacturer,
-@@ -836,24 +827,63 @@ static const struct spinand_manufacturer
- 	&winbond_spinand_manufacturer,
- };
- 
--static int spinand_manufacturer_detect(struct spinand_device *spinand)
-+static int spinand_manufacturer_match(struct spinand_device *spinand,
-+				      enum spinand_readid_method rdid_method)
- {
-+	u8 *id = spinand->id.data;
- 	unsigned int i;
- 	int ret;
- 
- 	for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
--		ret = spinand_manufacturers[i]->ops->detect(spinand);
--		if (ret > 0) {
--			spinand->manufacturer = spinand_manufacturers[i];
--			return 0;
--		} else if (ret < 0) {
--			return ret;
--		}
-+		const struct spinand_manufacturer *manufacturer =
-+			spinand_manufacturers[i];
-+
-+		if (id[0] != manufacturer->id)
-+			continue;
-+
-+		ret = spinand_match_and_init(spinand,
-+					     manufacturer->chips,
-+					     manufacturer->nchips,
-+					     rdid_method);
-+		if (ret < 0)
-+			continue;
-+
-+		spinand->manufacturer = manufacturer;
-+		return 0;
- 	}
- 
- 	return -ENOTSUPP;
- }
- 
-+static int spinand_id_detect(struct spinand_device *spinand)
-+{
-+	u8 *id = spinand->id.data;
-+	int ret;
-+
-+	ret = spinand_read_id_op(spinand, 0, 0, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
-+	if (!ret)
-+		return 0;
-+
-+	ret = spinand_read_id_op(spinand, 1, 0, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand,
-+					 SPINAND_READID_METHOD_OPCODE_ADDR);
-+	if (!ret)
-+		return 0;
-+
-+	ret = spinand_read_id_op(spinand, 0, 1, id);
-+	if (ret)
-+		return ret;
-+	ret = spinand_manufacturer_match(spinand,
-+					 SPINAND_READID_METHOD_OPCODE_DUMMY);
-+
-+	return ret;
-+}
-+
- static int spinand_manufacturer_init(struct spinand_device *spinand)
- {
- 	if (spinand->manufacturer->ops->init)
-@@ -909,9 +939,9 @@ spinand_select_op_variant(struct spinand
-  * @spinand: SPI NAND object
-  * @table: SPI NAND device description table
-  * @table_size: size of the device description table
-+ * @rdid_method: read id method to match
-  *
-- * Should be used by SPI NAND manufacturer drivers when they want to find a
-- * match between a device ID retrieved through the READ_ID command and an
-+ * Match between a device ID retrieved through the READ_ID command and an
-  * entry in the SPI NAND description table. If a match is found, the spinand
-  * object will be initialized with information provided by the matching
-  * spinand_info entry.
-@@ -920,8 +950,10 @@ spinand_select_op_variant(struct spinand
-  */
- int spinand_match_and_init(struct spinand_device *spinand,
- 			   const struct spinand_info *table,
--			   unsigned int table_size, u8 devid)
-+			   unsigned int table_size,
-+			   enum spinand_readid_method rdid_method)
- {
-+	u8 *id = spinand->id.data;
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	unsigned int i;
- 
-@@ -929,13 +961,17 @@ int spinand_match_and_init(struct spinan
- 		const struct spinand_info *info = &table[i];
- 		const struct spi_mem_op *op;
- 
--		if (devid != info->devid)
-+		if (rdid_method != info->devid.method)
-+			continue;
-+
-+		if (memcmp(id + 1, info->devid.id, info->devid.len))
- 			continue;
- 
- 		nand->memorg = table[i].memorg;
- 		nand->eccreq = table[i].eccreq;
- 		spinand->eccinfo = table[i].eccinfo;
- 		spinand->flags = table[i].flags;
-+		spinand->id.len = 1 + table[i].devid.len;
- 		spinand->select_target = table[i].select_target;
- 
- 		op = spinand_select_op_variant(spinand,
-@@ -967,17 +1003,7 @@ static int spinand_detect(struct spinand
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	int ret;
- 
--	ret = spinand_reset_op(spinand);
--	if (ret)
--		return ret;
--
--	ret = spinand_read_id_op(spinand, spinand->id.data);
--	if (ret)
--		return ret;
--
--	spinand->id.len = SPINAND_MAX_ID_LEN;
--
--	ret = spinand_manufacturer_detect(spinand);
-+	ret = spinand_id_detect(spinand);
- 	if (ret) {
- 		dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n",
- 			spinand->id.data[0], spinand->id.data[1],
 --- /dev/null
 +++ b/drivers/mtd/nand/spi/etron.c
 @@ -0,0 +1,181 @@
@@ -320,7 +137,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM73C 1Gb 3.3V */
 +	SPINAND_INFO("EM73C044VCF",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -330,7 +147,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM7xD 2Gb */
 +	SPINAND_INFO("EM73D044VCR",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -339,7 +156,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM73D044VCO",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -348,7 +165,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM78D044VCM",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -358,7 +175,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM7xE 4Gb */
 +	SPINAND_INFO("EM73E044VCE",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -367,7 +184,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM78E044VCD",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -377,7 +194,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	/* EM7xF044VCA 8Gb */
 +	SPINAND_INFO("EM73F044VCA",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -386,7 +203,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
 +	SPINAND_INFO("EM78F044VCA",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
-+		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -407,45 +224,19 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +};
 --- a/drivers/mtd/nand/spi/gigadevice.c
 +++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -22,8 +22,13 @@
+@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
  
- #define GD5FXGQXXEXXG_REG_STATUS2		0xf0
- 
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK		(7 << 4)
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS	(0 << 4)
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS	(1 << 4)
-+#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR	(7 << 4)
-+
- /* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */
--static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
-+static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-@@ -31,8 +36,17 @@ static SPINAND_OP_VARIANTS(gd5fxgq4_read
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
- 
--/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
--static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
-+static SPINAND_OP_VARIANTS(read_cache_variants_f,
-+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
-+
-+/* For Q5 devices, QUADIO use different dummy byte settings */
 +/* Q5 1Gb */
 +static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
-@@ -40,6 +54,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
- 
++		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
++
 +/* Q5 2Gb & 4Gb */
 +static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
 +		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
@@ -458,124 +249,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static SPINAND_OP_VARIANTS(write_cache_variants,
  		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
  		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-@@ -48,7 +71,65 @@ static SPINAND_OP_VARIANTS(update_cache_
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
--static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
-+static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 8;
-+	region->length = 8;
-+
-+	return 0;
-+}
-+
-+static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	if (section) {
-+		region->offset = 16 * section;
-+		region->length = 8;
-+	} else {
-+		/* section 0 has one byte reserved for bad block mark */
-+		region->offset = 1;
-+		region->length = 7;
-+	}
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
-+	.ecc = gd5fxgq4xa_ooblayout_ecc,
-+	.rfree = gd5fxgq4xa_ooblayout_free,
-+};
-+
-+static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
-+					 u8 status)
-+{
-+	switch (status & STATUS_ECC_MASK) {
-+	case STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
-+		/* 1-7 bits are flipped. return the maximum. */
-+		return 7;
-+
-+	case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
-+		return 8;
-+
-+	case STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
- 				       struct mtd_oob_region *region)
- {
- 	if (section)
-@@ -60,7 +141,7 @@ static int gd5fxgqxxexxg_ooblayout_ecc(s
- 	return 0;
- }
- 
--static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section,
-+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
- 					struct mtd_oob_region *region)
- {
- 	if (section)
-@@ -73,7 +154,13 @@ static int gd5fxgqxxexxg_ooblayout_free(
- 	return 0;
- }
- 
--static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
-+/* Valid for Q4/Q5 and Q6 (untested) devices */
-+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
-+	.ecc = gd5fxgqx_variant2_ooblayout_ecc,
-+	.rfree = gd5fxgqx_variant2_ooblayout_free,
-+};
-+
-+static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
- 					u8 status)
- {
- 	u8 status2;
-@@ -152,59 +239,214 @@ static int gd5fxgq5xexxg_ecc_get_status(
+@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status(
  	return -EINVAL;
  }
  
--static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = {
--	.ecc = gd5fxgqxxexxg_ooblayout_ecc,
--	.rfree = gd5fxgqxxexxg_ooblayout_free,
-+static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
-+					u8 status)
-+{
-+	switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) {
-+	case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS:
-+		return 3;
-+
-+	case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
-+		return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2;
-+	}
-+
-+	return -EINVAL;
-+}
-+
 +static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
 +				  struct mtd_oob_region *region)
 +{
@@ -603,90 +280,28 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
 +	.ecc = esmt_1_ooblayout_ecc,
 +	.rfree = esmt_1_ooblayout_free,
- };
- 
++ };
++
  static const struct spinand_info gigadevice_spinand_table[] = {
--	SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
--		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
 +	SPINAND_INFO("F50L1G41LB",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
--		     SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants,
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     0,
--		     SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
--				     gd5fxgq4xexxg_ecc_get_status)),
--	SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
++		          &write_cache_variants,
++		          &update_cache_variants),
++		     0,
 +		     SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
-+	SPINAND_INFO("GD5F1GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-+				     gd5fxgq4xa_ecc_get_status)),
-+	SPINAND_INFO("GD5F2GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-+				     gd5fxgq4xa_ecc_get_status)),
-+	SPINAND_INFO("GD5F4GQ4xA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
-+		     NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
-+				     gd5fxgq4xa_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ4UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4uexxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ4UFxxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq4ufxxg_ecc_get_status)),
-+	SPINAND_INFO("GD5F1GQ5UExxG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
--		     SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
-+		     SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
--		     0,
--		     SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
-+				     gd5fxgq5xexxg_ecc_get_status)),
+ 	SPINAND_INFO("GD5F1GQ4xA",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
+ 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+@@ -349,6 +405,87 @@ static const struct spinand_info gigadev
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F2GQ5UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
@@ -696,7 +311,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F4GQ6UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
@@ -706,7 +321,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F1GM7UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
 +		     NAND_ECCREQ(8, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -716,7 +331,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq4uexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F2GM7UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
-+			 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
 +			 NAND_ECCREQ(8, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -726,7 +341,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq4uexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F4GM8UExxG",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
-+			 NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
 +			 NAND_ECCREQ(8, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -736,7 +351,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq4uexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F1GQ5UExxH",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
-+			 NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
 +			 NAND_ECCREQ(4, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
 +					      &write_cache_variants,
@@ -746,7 +361,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F2GQ5UExxH",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
-+			 NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
 +			 NAND_ECCREQ(4, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
@@ -756,600 +371,21 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +				     gd5fxgq5xexxg_ecc_get_status)),
 +	SPINAND_INFO("GD5F4GQ6UExxH",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-+			 NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
++			 NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
 +			 NAND_ECCREQ(4, 512),
 +			 SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
 +					      &write_cache_variants,
 +					      &update_cache_variants),
 +			 SPINAND_HAS_QE_BIT,
 +			 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- 				     gd5fxgq5xexxg_ecc_get_status)),
- };
- 
--static int gigadevice_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * For GD NANDs, There is an address byte needed to shift in before IDs
--	 * are read out, so the first byte in raw_id is dummy.
--	 */
--	if (id[1] != SPINAND_MFR_GIGADEVICE)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
--				     ARRAY_SIZE(gigadevice_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--	.detect = gigadevice_spinand_detect,
- };
- 
- const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
- 	.id = SPINAND_MFR_GIGADEVICE,
- 	.name = "GigaDevice",
-+	.chips = gigadevice_spinand_table,
-+	.nchips = ARRAY_SIZE(gigadevice_spinand_table),
- 	.ops = &gigadevice_spinand_manuf_ops,
- };
---- a/drivers/mtd/nand/spi/macronix.c
-+++ b/drivers/mtd/nand/spi/macronix.c
-@@ -105,7 +105,8 @@ static int mx35lf1ge4ab_ecc_get_status(s
- }
- 
- static const struct spinand_info macronix_spinand_table[] = {
--	SPINAND_INFO("MX35LF1GE4AB", 0x12,
-+	SPINAND_INFO("MX35LF1GE4AB",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -114,7 +115,8 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35LF2GE4AB", 0x22,
-+	SPINAND_INFO("MX35LF2GE4AB",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
- 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -122,7 +124,96 @@ static const struct spinand_info macroni
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
--	SPINAND_INFO("MX35UF4GE4AD", 0xb7,
-+	SPINAND_INFO("MX35LF2GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35LF4GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
-+		     NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35LF1G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX35LF2G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX35LF4G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
-+	SPINAND_INFO("MX31LF1GE4BC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX31UF1GE4BC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
++			     gd5fxgq5xexxg_ecc_get_status)),
 +
-+	SPINAND_INFO("MX35LF2G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF4G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
-+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF4GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -131,7 +222,28 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF2GE4AD", 0xa6,
-+	SPINAND_INFO("MX35UF2G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
-+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF2GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -140,16 +252,28 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF2GE4AC", 0xa2,
-+	SPINAND_INFO("MX35UF2GE4AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
- 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
-+			 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1G14AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- 					      &write_cache_variants,
- 					      &update_cache_variants),
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF1GE4AD", 0x96,
-+	SPINAND_INFO("MX35UF1G24AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -158,7 +282,18 @@ static const struct spinand_info macroni
- 		     SPINAND_HAS_QE_BIT,
- 		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
- 				     mx35lf1ge4ab_ecc_get_status)),
--	SPINAND_INFO("MX35UF1GE4AC", 0x92,
-+	SPINAND_INFO("MX35UF1GE4AD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
-+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
-+				     mx35lf1ge4ab_ecc_get_status)),
-+	SPINAND_INFO("MX35UF1GE4AC",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(4, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -170,33 +305,13 @@ static const struct spinand_info macroni
- 
  };
  
--static int macronix_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
--	 * raw_id is garbage.
--	 */
--	if (id[1] != SPINAND_MFR_MACRONIX)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, macronix_spinand_table,
--				     ARRAY_SIZE(macronix_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
--	.detect = macronix_spinand_detect,
- };
- 
- const struct spinand_manufacturer macronix_spinand_manufacturer = {
- 	.id = SPINAND_MFR_MACRONIX,
- 	.name = "Macronix",
-+	.chips = macronix_spinand_table,
-+	.nchips = ARRAY_SIZE(macronix_spinand_table),
- 	.ops = &macronix_spinand_manuf_ops,
- };
---- a/drivers/mtd/nand/spi/micron.c
-+++ b/drivers/mtd/nand/spi/micron.c
-@@ -120,7 +120,8 @@ static int micron_8_ecc_get_status(struc
- 
- static const struct spinand_info micron_spinand_table[] = {
- 	/* M79A 2Gb 3.3V */
--	SPINAND_INFO("MT29F2G01ABAGD", 0x24,
-+	SPINAND_INFO("MT29F2G01ABAGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -130,7 +131,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M79A 2Gb 1.8V */
--	SPINAND_INFO("MT29F2G01ABBGD", 0x25,
-+	SPINAND_INFO("MT29F2G01ABBGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -140,7 +142,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M78A 1Gb 3.3V */
--	SPINAND_INFO("MT29F1G01ABAFD", 0x14,
-+	SPINAND_INFO("MT29F1G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -150,7 +153,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M78A 1Gb 1.8V */
--	SPINAND_INFO("MT29F1G01ABAFD", 0x15,
-+	SPINAND_INFO("MT29F1G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -160,7 +164,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M79A 4Gb 3.3V */
--	SPINAND_INFO("MT29F4G01ADAGD", 0x36,
-+	SPINAND_INFO("MT29F4G01ADAGD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -171,7 +176,8 @@ static const struct spinand_info micron_
- 				     micron_8_ecc_get_status),
- 		     SPINAND_SELECT_TARGET(micron_select_target)),
- 	/* M70A 4Gb 3.3V */
--	SPINAND_INFO("MT29F4G01ABAFD", 0x34,
-+	SPINAND_INFO("MT29F4G01ABAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -181,7 +187,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M70A 4Gb 1.8V */
--	SPINAND_INFO("MT29F4G01ABBFD", 0x35,
-+	SPINAND_INFO("MT29F4G01ABBFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -191,7 +198,8 @@ static const struct spinand_info micron_
- 		     SPINAND_ECCINFO(&micron_8_ooblayout,
- 				     micron_8_ecc_get_status)),
- 	/* M70A 8Gb 3.3V */
--	SPINAND_INFO("MT29F8G01ADAFD", 0x46,
-+	SPINAND_INFO("MT29F8G01ADAFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -202,7 +210,8 @@ static const struct spinand_info micron_
- 				     micron_8_ecc_get_status),
- 		     SPINAND_SELECT_TARGET(micron_select_target)),
- 	/* M70A 8Gb 1.8V */
--	SPINAND_INFO("MT29F8G01ADBFD", 0x47,
-+	SPINAND_INFO("MT29F8G01ADBFD",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -214,26 +223,6 @@ static const struct spinand_info micron_
- 		     SPINAND_SELECT_TARGET(micron_select_target)),
- };
- 
--static int micron_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Micron SPI NAND read ID need a dummy byte,
--	 * so the first byte in raw_id is dummy.
--	 */
--	if (id[1] != SPINAND_MFR_MICRON)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, micron_spinand_table,
--				     ARRAY_SIZE(micron_spinand_table), id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static int micron_spinand_init(struct spinand_device *spinand)
- {
- 	/*
-@@ -248,12 +237,13 @@ static int micron_spinand_init(struct sp
- }
- 
- static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
--	.detect = micron_spinand_detect,
- 	.init = micron_spinand_init,
- };
- 
- const struct spinand_manufacturer micron_spinand_manufacturer = {
- 	.id = SPINAND_MFR_MICRON,
- 	.name = "Micron",
-+	.chips = micron_spinand_table,
-+	.nchips = ARRAY_SIZE(micron_spinand_table),
- 	.ops = &micron_spinand_manuf_ops,
- };
---- a/drivers/mtd/nand/spi/toshiba.c
-+++ b/drivers/mtd/nand/spi/toshiba.c
-@@ -111,7 +111,8 @@ static int tx58cxgxsxraix_ecc_get_status
- 
- static const struct spinand_info toshiba_spinand_table[] = {
- 	/* 3.3V 1Gb (1st generation) */
--	SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
-+	SPINAND_INFO("TC58CVG0S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -121,7 +122,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 2Gb (1st generation) */
--	SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
-+	SPINAND_INFO("TC58CVG1S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -131,7 +133,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 4Gb (1st generation) */
--	SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
-+	SPINAND_INFO("TC58CVG2S0HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -141,7 +144,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 1Gb (1st generation) */
--	SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
-+	SPINAND_INFO("TC58CYG0S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -151,7 +155,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 2Gb (1st generation) */
--	SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
-+	SPINAND_INFO("TC58CYG1S3HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -161,7 +166,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 4Gb (1st generation) */
--	SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
-+	SPINAND_INFO("TC58CYG2S0HRAIG",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -176,7 +182,8 @@ static const struct spinand_info toshiba
- 	 * QE_BIT.
- 	 */
- 	/* 3.3V 1Gb (2nd generation) */
--	SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
-+	SPINAND_INFO("TC58CVG0S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -186,7 +193,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 2Gb (2nd generation) */
--	SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
-+	SPINAND_INFO("TC58CVG1S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -196,7 +204,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 4Gb (2nd generation) */
--	SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
-+	SPINAND_INFO("TC58CVG2S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -206,7 +215,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 3.3V 8Gb (2nd generation) */
--	SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
-+	SPINAND_INFO("TH58CVG3S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
- 		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -216,7 +226,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 1Gb (2nd generation) */
--	SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
-+	SPINAND_INFO("TC58CYG0S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -226,7 +237,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 2Gb (2nd generation) */
--	SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
-+	SPINAND_INFO("TC58CYG1S3HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
- 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -236,7 +248,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 4Gb (2nd generation) */
--	SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
-+	SPINAND_INFO("TC58CYG2S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
- 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -246,7 +259,8 @@ static const struct spinand_info toshiba
- 		     SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
- 				     tx58cxgxsxraix_ecc_get_status)),
- 	/* 1.8V 8Gb (2nd generation) */
--	SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
-+	SPINAND_INFO("TH58CYG3S0HRAIJ",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
- 		     NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -257,33 +271,13 @@ static const struct spinand_info toshiba
- 				     tx58cxgxsxraix_ecc_get_status)),
- };
- 
--static int toshiba_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Toshiba SPI NAND read ID needs a dummy byte,
--	 * so the first byte in id is garbage.
--	 */
--	if (id[1] != SPINAND_MFR_TOSHIBA)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, toshiba_spinand_table,
--				     ARRAY_SIZE(toshiba_spinand_table),
--				     id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
--
- static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
--	.detect = toshiba_spinand_detect,
- };
- 
- const struct spinand_manufacturer toshiba_spinand_manufacturer = {
- 	.id = SPINAND_MFR_TOSHIBA,
- 	.name = "Toshiba",
-+	.chips = toshiba_spinand_table,
-+	.nchips = ARRAY_SIZE(toshiba_spinand_table),
- 	.ops = &toshiba_spinand_manuf_ops,
- };
+ static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
 --- a/drivers/mtd/nand/spi/winbond.c
 +++ b/drivers/mtd/nand/spi/winbond.c
-@@ -19,6 +19,23 @@
+@@ -18,6 +18,23 @@
  
  #define WINBOND_CFG_BUF_READ		BIT(3)
  
@@ -1373,7 +409,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static SPINAND_OP_VARIANTS(read_cache_variants,
  		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
  		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-@@ -35,6 +52,35 @@ static SPINAND_OP_VARIANTS(update_cache_
+@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_
  		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
  		SPINAND_PROG_LOAD(false, 0, NULL, 0));
  
@@ -1409,9 +445,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
  				  struct mtd_oob_region *region)
  {
-@@ -78,8 +124,61 @@ static int w25m02gv_select_target(struct
- 	return spi_mem_exec_op(spinand->slave, &op);
- }
+@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2
+ 	.rfree = w25n02kv_ooblayout_free,
+ };
  
 +static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
 +					u8 status)
@@ -1465,77 +501,32 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	return -EINVAL;
 +}
 +
- static const struct spinand_info winbond_spinand_table[] = {
--	SPINAND_INFO("W25M02GV", 0xAB,
-+	SPINAND_INFO("W25M02GV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
- 		     NAND_ECCREQ(1, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -88,7 +187,17 @@ static const struct spinand_info winbond
+ static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
+ 				   u8 status)
+ {
+@@ -163,6 +261,15 @@ static const struct spinand_info winbond
+ 					      &update_cache_variants),
  		     0,
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
- 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
--	SPINAND_INFO("W25N01GV", 0xAA,
+ 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
 +	SPINAND_INFO("W25N01KV",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
 +					      &update_cache_variants),
 +		     0,
 +		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
-+	SPINAND_INFO("W25N01GV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
- 		     NAND_ECCREQ(1, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -96,32 +205,30 @@ static const struct spinand_info winbond
+ 	SPINAND_INFO("W25N02KV",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+@@ -172,6 +279,16 @@ static const struct spinand_info winbond
  					      &update_cache_variants),
  		     0,
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
--};
--
--/**
-- * winbond_spinand_detect - initialize device related part in spinand_device
-- * struct if it is a Winbond device.
-- * @spinand: SPI NAND device structure
-- */
--static int winbond_spinand_detect(struct spinand_device *spinand)
--{
--	u8 *id = spinand->id.data;
--	int ret;
--
--	/*
--	 * Winbond SPI NAND read ID need a dummy byte,
--	 * so the first byte in raw_id is dummy.
-+	SPINAND_INFO("W25N02KV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
-+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
-+				     w25n02kv_n04kv_ecc_get_status)),
-+	/* W25N04KV has 2-die(lun), however, it can select die automatically.
-+	 * Treat it as single die here and double block size.
- 	 */
--	if (id[1] != SPINAND_MFR_WINBOND)
--		return 0;
--
--	ret = spinand_match_and_init(spinand, winbond_spinand_table,
--				     ARRAY_SIZE(winbond_spinand_table), id[2]);
--	if (ret)
--		return ret;
--
--	return 1;
--}
+ 		     SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
 +	SPINAND_INFO("W25N04KV",
 +		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1),
++		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
 +		     NAND_ECCREQ(4, 512),
 +		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 +					      &write_cache_variants,
@@ -1543,162 +534,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +		     0,
 +		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
 +				     w25n02kv_n04kv_ecc_get_status)),
-+};
+ };
  
  static int winbond_spinand_init(struct spinand_device *spinand)
- {
-@@ -142,12 +249,13 @@ static int winbond_spinand_init(struct s
- }
- 
- static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
--	.detect = winbond_spinand_detect,
- 	.init = winbond_spinand_init,
- };
- 
- const struct spinand_manufacturer winbond_spinand_manufacturer = {
- 	.id = SPINAND_MFR_WINBOND,
- 	.name = "Winbond",
-+	.chips = winbond_spinand_table,
-+	.nchips = ARRAY_SIZE(winbond_spinand_table),
- 	.ops = &winbond_spinand_manuf_ops,
- };
 --- a/include/linux/mtd/spinand.h
 +++ b/include/linux/mtd/spinand.h
-@@ -39,15 +39,15 @@
- 		   SPI_MEM_OP_NO_DUMMY,					\
- 		   SPI_MEM_OP_NO_DATA)
- 
--#define SPINAND_READID_OP(ndummy, buf, len)				\
-+#define SPINAND_READID_OP(naddr, ndummy, buf, len)			\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
--		   SPI_MEM_OP_NO_ADDR,					\
-+		   SPI_MEM_OP_ADDR(naddr, 0, 1),			\
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
- 
- #define SPINAND_SET_FEATURE_OP(reg, valptr)				\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1),				\
--		   SPI_MEM_OP_ADDR(1, reg, 1),				\
-+		   SPI_MEM_OP_ADDR(1, reg, 1),					\
- 		   SPI_MEM_OP_NO_DUMMY,					\
- 		   SPI_MEM_OP_DATA_OUT(1, valptr, 1))
- 
-@@ -75,18 +75,36 @@
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 1))
- 
-+#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len)\
-+	SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),		\
-+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
-+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
-+		   SPI_MEM_OP_DATA_IN(len, buf, 1))
-+
- #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len)	\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
- 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 2))
- 
-+#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len)	\
-+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
-+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
-+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
-+		   SPI_MEM_OP_DATA_IN(len, buf, 2))
-+
- #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len)	\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
- 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
- 		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
- 		   SPI_MEM_OP_DATA_IN(len, buf, 4))
- 
-+#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len)	\
-+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
-+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
-+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
-+		   SPI_MEM_OP_DATA_IN(len, buf, 4))
-+
- #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len)	\
- 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),				\
- 		   SPI_MEM_OP_ADDR(2, addr, 2),				\
-@@ -153,37 +171,46 @@ struct spinand_device;
-  * @data: buffer containing the id bytes. Currently 4 bytes large, but can
-  *	  be extended if required
-  * @len: ID length
-- *
-- * struct_spinand_id->data contains all bytes returned after a READ_ID command,
-- * including dummy bytes if the chip does not emit ID bytes right after the
-- * READ_ID command. The responsibility to extract real ID bytes is left to
-- * struct_manufacurer_ops->detect().
-  */
- struct spinand_id {
- 	u8 data[SPINAND_MAX_ID_LEN];
- 	int len;
- };
- 
-+enum spinand_readid_method {
-+	SPINAND_READID_METHOD_OPCODE,
-+	SPINAND_READID_METHOD_OPCODE_ADDR,
-+	SPINAND_READID_METHOD_OPCODE_DUMMY,
-+};
-+
-+/**
-+ * struct spinand_devid - SPI NAND device id structure
-+ * @id: device id of current chip
-+ * @len: number of bytes in device id
-+ * @method: method to read chip id
-+ *	    There are 3 possible variants:
-+ *	    SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
-+ *	    after read_id opcode.
-+ *	    SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
-+ *	    read_id opcode + 1-byte address.
-+ *	    SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
-+ *	    read_id opcode + 1 dummy byte.
-+ */
-+struct spinand_devid {
-+	const u8 *id;
-+	const u8 len;
-+	const enum spinand_readid_method method;
-+};
-+
- /**
-  * struct manufacurer_ops - SPI NAND manufacturer specific operations
-- * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
-- *	    the core calls the struct_manufacurer_ops->detect() hook of each
-- *	    registered manufacturer until one of them return 1. Note that
-- *	    the first thing to check in this hook is that the manufacturer ID
-- *	    in struct_spinand_device->id matches the manufacturer whose
-- *	    ->detect() hook has been called. Should return 1 if there's a
-- *	    match, 0 if the manufacturer ID does not match and a negative
-- *	    error code otherwise. When true is returned, the core assumes
-- *	    that properties of the NAND chip (spinand->base.memorg and
-- *	    spinand->base.eccreq) have been filled
-  * @init: initialize a SPI NAND device
-  * @cleanup: cleanup a SPI NAND device
-  *
-  * Each SPI NAND manufacturer driver should implement this interface so that
-- * NAND chips coming from this vendor can be detected and initialized properly.
-+ * NAND chips coming from this vendor can be initialized properly.
-  */
- struct spinand_manufacturer_ops {
--	int (*detect)(struct spinand_device *spinand);
- 	int (*init)(struct spinand_device *spinand);
- 	void (*cleanup)(struct spinand_device *spinand);
- };
-@@ -192,15 +219,21 @@ struct spinand_manufacturer_ops {
-  * struct spinand_manufacturer - SPI NAND manufacturer instance
-  * @id: manufacturer ID
-  * @name: manufacturer name
-+ * @devid_len: number of bytes in device ID
-+ * @chips: supported SPI NANDs under current manufacturer
-+ * @nchips: number of SPI NANDs available in chips array
-  * @ops: manufacturer operations
-  */
- struct spinand_manufacturer {
- 	u8 id;
- 	char *name;
-+	const struct spinand_info *chips;
-+	const size_t nchips;
- 	const struct spinand_manufacturer_ops *ops;
+@@ -245,6 +245,7 @@ struct spinand_manufacturer {
  };
  
  /* SPI NAND manufacturers */
@@ -1706,39 +547,3 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
  extern const struct spinand_manufacturer macronix_spinand_manufacturer;
  extern const struct spinand_manufacturer micron_spinand_manufacturer;
-@@ -268,7 +301,7 @@ struct spinand_ecc_info {
-  */
- struct spinand_info {
- 	const char *model;
--	u8 devid;
-+	struct spinand_devid devid;
- 	u32 flags;
- 	struct nand_memory_organization memorg;
- 	struct nand_ecc_req eccreq;
-@@ -282,6 +315,13 @@ struct spinand_info {
- 			     unsigned int target);
- };
- 
-+#define SPINAND_ID(__method, ...)					\
-+	{								\
-+		.id = (const u8[]){ __VA_ARGS__ },			\
-+		.len = sizeof((u8[]){ __VA_ARGS__ }),			\
-+		.method = __method,					\
-+	}
-+
- #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)		\
- 	{								\
- 		.read_cache = __read,					\
-@@ -440,9 +480,10 @@ static inline void spinand_set_ofnode(st
- }
- #endif /* __UBOOT__ */
- 
--int spinand_match_and_init(struct spinand_device *dev,
-+int spinand_match_and_init(struct spinand_device *spinand,
- 			   const struct spinand_info *table,
--			   unsigned int table_size, u8 devid);
-+			   unsigned int table_size,
-+			   enum spinand_readid_method rdid_method);
- 
- int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
- int spinand_select_target(struct spinand_device *spinand, unsigned int target);
diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
index 0c68f429c6..5c90e24ebf 100644
--- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
+++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mmc/Kconfig
 +++ b/drivers/mmc/Kconfig
-@@ -820,6 +820,14 @@ config MMC_MTK
+@@ -815,6 +815,14 @@ config MMC_MTK
  	  This is needed if support for any SD/SDIO/MMC devices is required.
  	  If unsure, say N.
  
@@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  config FSL_SDHC_V2_3
 --- a/drivers/mmc/Makefile
 +++ b/drivers/mmc/Makefile
-@@ -83,3 +83,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
+@@ -82,3 +82,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
  obj-$(CONFIG_MMC_BCM2835)		+= bcm2835_sdhost.o
  obj-$(CONFIG_MMC_MTK)			+= mtk-sd.o
  obj-$(CONFIG_MMC_SDHCI_F_SDH30)		+= f_sdh30.o
@@ -42,7 +42,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +endif
 --- a/drivers/mmc/mtk-sd.c
 +++ b/drivers/mmc/mtk-sd.c
-@@ -778,18 +778,24 @@ static int msdc_ops_send_cmd(struct udev
+@@ -779,18 +779,24 @@ static int msdc_ops_send_cmd(struct udev
  	if (cmd_ret &&
  	    !(cmd_ret == -EIO &&
  	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
diff --git a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
index 98c81acdcf..fb8d15ddf9 100644
--- a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
+++ b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch
@@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -675,6 +675,12 @@ config ENV_UBI_VOLUME_REDUND
+@@ -689,6 +689,12 @@ config ENV_UBI_VOLUME_REDUND
  	help
  	  Name of the redundant volume that you want to store the environment in.
  
diff --git a/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
index cd1794f0d1..9c83e6cc25 100644
--- a/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
+++ b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/mtd/ubi/attach.c
 +++ b/drivers/mtd/ubi/attach.c
-@@ -802,6 +802,13 @@ out_unlock:
+@@ -803,6 +803,13 @@ out_unlock:
  	return err;
  }
  
@@ -29,7 +29,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  /**
   * scan_peb - scan and process UBI headers of a PEB.
   * @ubi: UBI device description object
-@@ -832,9 +839,21 @@ static int scan_peb(struct ubi_device *u
+@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u
  		return 0;
  	}
  
@@ -56,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  		break;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -745,6 +745,7 @@ struct ubi_attach_info {
+@@ -746,6 +746,7 @@ struct ubi_attach_info {
  	int mean_ec;
  	uint64_t ec_sum;
  	int ec_count;
diff --git a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
index b561a79944..f22449ae76 100644
--- a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
+++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch
@@ -24,7 +24,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
  DECLARE_GLOBAL_DATA_PTR;
  
  int board_init(void)
-@@ -24,3 +29,36 @@ int board_late_init(void)
+@@ -23,3 +28,36 @@ int board_late_init(void)
  	env_relocate();
  	return 0;
  }
diff --git a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch b/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch
deleted file mode 100644
index 645b7801c8..0000000000
--- a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch
+++ /dev/null
@@ -1,297 +0,0 @@
-From 63336ec7fd7d480ac58a91f3b20d08bf1b3a13ad Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:41 +0800
-Subject: [PATCH 01/29] arm: mediatek: retrieve ram_base from dts node for
- armv8 platform
-
-Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node
-and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed.
-
-Also, since mt7622 always passes fdt to linux kernel, there's no need to
-assign value to gd->bd->bi_boot_params.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981-emmc-rfb.dts     |  5 +++++
- arch/arm/dts/mt7981-rfb.dts          |  5 +++++
- arch/arm/dts/mt7981-sd-rfb.dts       |  5 +++++
- arch/arm/dts/mt7986a-bpi-r3-sd.dts   |  5 +++++
- arch/arm/dts/mt7986a-rfb.dts         |  5 +++++
- arch/arm/dts/mt7986a-sd-rfb.dts      |  5 +++++
- arch/arm/dts/mt7986b-rfb.dts         |  5 +++++
- arch/arm/dts/mt7986b-sd-rfb.dts      |  5 +++++
- arch/arm/mach-mediatek/mt7622/init.c | 13 +++++++++----
- arch/arm/mach-mediatek/mt7981/init.c | 11 +++++++++--
- arch/arm/mach-mediatek/mt7986/init.c | 11 +++++++++--
- board/mediatek/mt7622/mt7622_rfb.c   |  1 -
- include/configs/mt7622.h             | 10 ----------
- include/configs/mt7981.h             |  9 ---------
- include/configs/mt7986.h             |  9 ---------
- 15 files changed, 67 insertions(+), 37 deletions(-)
-
---- a/arch/arm/dts/mt7981-emmc-rfb.dts
-+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		  compatible = "regulator-fixed";
- 		  regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7981-rfb.dts
-+++ b/arch/arm/dts/mt7981-rfb.dts
-@@ -17,6 +17,11 @@
- 		stdout-path = &uart0;
- 		tick-timer = &timer0;
- 	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
- };
- 
- &uart0 {
---- a/arch/arm/dts/mt7981-sd-rfb.dts
-+++ b/arch/arm/dts/mt7981-sd-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		  compatible = "regulator-fixed";
- 		  regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x80000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986a-rfb.dts
-+++ b/arch/arm/dts/mt7986a-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_1p8v: regulator-1p8v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-1.8V";
---- a/arch/arm/dts/mt7986a-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986b-rfb.dts
-+++ b/arch/arm/dts/mt7986b-rfb.dts
-@@ -18,6 +18,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/dts/mt7986b-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
-@@ -19,6 +19,11 @@
- 		tick-timer = &timer0;
- 	};
- 
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0x40000000 0x10000000>;
-+	};
-+
- 	reg_3p3v: regulator-3p3v {
- 		compatible = "regulator-fixed";
- 		regulator-name = "fixed-3.3V";
---- a/arch/arm/mach-mediatek/mt7622/init.c
-+++ b/arch/arm/mach-mediatek/mt7622/init.c
-@@ -4,11 +4,14 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <common.h>
- #include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
--#include <asm/cache.h>
-+#include <asm/global_data.h>
-+#include <asm/u-boot.h>
-+#include <linux/sizes.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
- 
- int print_cpuinfo(void)
- {
-@@ -20,11 +23,13 @@ int dram_init(void)
- {
- 	int ret;
- 
--	ret = fdtdec_setup_memory_banksize();
-+	ret = fdtdec_setup_mem_size_base();
- 	if (ret)
- 		return ret;
--	return fdtdec_setup_mem_size_base();
- 
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
-+
-+	return 0;
- }
- 
- void reset_cpu(void)
---- a/arch/arm/mach-mediatek/mt7981/init.c
-+++ b/arch/arm/mach-mediatek/mt7981/init.c
-@@ -4,18 +4,25 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <cpu_func.h>
-+#include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
- #include <asm/system.h>
- #include <asm/global_data.h>
-+#include <asm/u-boot.h>
- #include <linux/sizes.h>
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
- int dram_init(void)
- {
--	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
- 
- 	return 0;
- }
---- a/arch/arm/mach-mediatek/mt7986/init.c
-+++ b/arch/arm/mach-mediatek/mt7986/init.c
-@@ -4,18 +4,25 @@
-  * Author: Sam Shih <sam.shih@mediatek.com>
-  */
- 
--#include <cpu_func.h>
-+#include <fdtdec.h>
- #include <init.h>
- #include <asm/armv8/mmu.h>
- #include <asm/system.h>
- #include <asm/global_data.h>
-+#include <asm/u-boot.h>
- #include <linux/sizes.h>
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
- int dram_init(void)
- {
--	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G);
- 
- 	return 0;
- }
---- a/board/mediatek/mt7622/mt7622_rfb.c
-+++ b/board/mediatek/mt7622/mt7622_rfb.c
-@@ -19,7 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
- 
- int board_init(void)
- {
--	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
- 	return 0;
- }
- 
---- a/include/configs/mt7622.h
-+++ b/include/configs/mt7622.h
-@@ -9,14 +9,4 @@
- #ifndef __MT7622_H
- #define __MT7622_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE                   CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
--/* Ethernet */
--
- #endif
---- a/include/configs/mt7981.h
-+++ b/include/configs/mt7981.h
-@@ -9,13 +9,4 @@
- #ifndef __MT7981_H
- #define __MT7981_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
- #endif
---- a/include/configs/mt7986.h
-+++ b/include/configs/mt7986.h
-@@ -9,13 +9,4 @@
- #ifndef __MT7986_H
- #define __MT7986_H
- 
--/* Uboot definition */
--#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
--
--/* SPL -> Uboot */
--#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
--
--/* DRAM */
--#define CFG_SYS_SDRAM_BASE		0x40000000
--
- #endif
diff --git a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch b/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch
deleted file mode 100644
index b64ee15171..0000000000
--- a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-From df3a0091b249ea82198ea019d145d05a7cf49c0d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:47 +0800
-Subject: [PATCH 02/29] board: mediatek: update config headers
-
-Remove unused information from include/configs/mtxxxx.h
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- include/configs/mt7620.h |  3 +--
- include/configs/mt7621.h |  6 ++----
- include/configs/mt7623.h |  8 --------
- include/configs/mt7628.h |  5 ++---
- include/configs/mt7629.h | 13 +------------
- 5 files changed, 6 insertions(+), 29 deletions(-)
-
---- a/include/configs/mt7620.h
-+++ b/include/configs/mt7620.h
-@@ -10,10 +10,9 @@
- 
- #define CFG_SYS_SDRAM_BASE		0x80000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x400000
-+#define CFG_SYS_INIT_SP_OFFSET		0x400000
- 
- /* SPL */
--
- #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
- 
- /* Dummy value */
---- a/include/configs/mt7621.h
-+++ b/include/configs/mt7621.h
-@@ -12,13 +12,11 @@
- 
- #define CFG_MAX_MEM_MAPPED		0x1c000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x800000
-+#define CFG_SYS_INIT_SP_OFFSET		0x800000
- 
- /* MMC */
- #define MMC_SUPPORTS_TUNING
- 
--/* NAND */
--
- /* Serial SPL */
- #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
- #define CFG_SYS_NS16550_CLK		50000000
-@@ -26,7 +24,7 @@
- #endif
- 
- /* Serial common */
--#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
-+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
- 					  230400, 460800, 921600 }
- 
- /* Dummy value */
---- a/include/configs/mt7623.h
-+++ b/include/configs/mt7623.h
-@@ -11,12 +11,6 @@
- 
- #include <linux/sizes.h>
- 
--/* Miscellaneous configurable options */
--
--/* Environment */
--
--/* Preloader -> Uboot */
--
- /* MMC */
- #define MMC_SUPPORTS_TUNING
- 
-@@ -32,8 +26,6 @@
- 	"fdt_addr_r=" FDT_HIGH "\0"			\
- 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
- 
--/* Ethernet */
--
- #ifdef CONFIG_DISTRO_DEFAULTS
- 
- #define BOOT_TARGET_DEVICES(func)	\
---- a/include/configs/mt7628.h
-+++ b/include/configs/mt7628.h
-@@ -10,7 +10,7 @@
- 
- #define CFG_SYS_SDRAM_BASE		0x80000000
- 
--#define CFG_SYS_INIT_SP_OFFSET	0x80000
-+#define CFG_SYS_INIT_SP_OFFSET		0x80000
- 
- /* Serial SPL */
- #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-@@ -19,11 +19,10 @@
- #endif
- 
- /* Serial common */
--#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
-+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
- 					  230400, 460800, 921600 }
- 
- /* SPL */
--
- #define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
- 
- /* Dummy value */
---- a/include/configs/mt7629.h
-+++ b/include/configs/mt7629.h
-@@ -9,21 +9,10 @@
- #ifndef __MT7629_H
- #define __MT7629_H
- 
--#include <linux/sizes.h>
--
--/* Miscellaneous configurable options */
--
--/* Environment */
--
-+/* SPL */
- #define CFG_SYS_UBOOT_BASE		(0x30000000 + CONFIG_SPL_PAD_TO)
- 
--/* SPL -> Uboot */
--
--/* UBoot -> Kernel */
--
- /* DRAM */
- #define CFG_SYS_SDRAM_BASE		0x40000000
- 
--/* Ethernet */
--
- #endif
diff --git a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch b/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch
deleted file mode 100644
index 323bb24933..0000000000
--- a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:15:54 +0800
-Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once
-
-We don't really need to switch clk rate during operating SPIM controller.
-Get clk rate only once at driver probing.
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
----
- drivers/spi/mtk_spim.c | 21 +++++++++++++--------
- 1 file changed, 13 insertions(+), 8 deletions(-)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -137,6 +137,8 @@ struct mtk_spim_capability {
-  * @state:		Controller state
-  * @sel_clk:		Pad clock
-  * @spi_clk:		Core clock
-+ * @pll_clk_rate:	Controller's PLL source clock rate, which is different
-+ *			from SPI bus clock rate
-  * @xfer_len:		Current length of data for transfer
-  * @hw_cap:		Controller capabilities
-  * @tick_dly:		Used to postpone SPI sampling time
-@@ -149,6 +151,7 @@ struct mtk_spim_priv {
- 	void __iomem *base;
- 	u32 state;
- 	struct clk sel_clk, spi_clk;
-+	u32 pll_clk_rate;
- 	u32 xfer_len;
- 	struct mtk_spim_capability hw_cap;
- 	u32 tick_dly;
-@@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s
- static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
- 				      u32 speed_hz)
- {
--	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
-+	u32 div, sck_time, cs_time, reg_val;
- 
--	spi_clk_hz = clk_get_rate(&priv->spi_clk);
--	if (speed_hz <= spi_clk_hz / 4)
--		div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
-+	if (speed_hz <= priv->pll_clk_rate / 4)
-+		div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
- 	else
- 		div = 4;
- 
-@@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct
- {
- 	struct udevice *bus = dev_get_parent(slave->dev);
- 	struct mtk_spim_priv *priv = dev_get_priv(bus);
--	u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
-+	u32 sck_l, sck_h, clk_count, reg;
- 	ulong us = 1;
- 	int ret = 0;
- 
-@@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct
- 	else
- 		clk_count = op->data.nbytes;
- 
--	spi_bus_clk = clk_get_rate(&priv->spi_clk);
- 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
- 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
--	do_div(spi_bus_clk, sck_l + sck_h + 2);
-+	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
- 
--	us = CLK_TO_US(spi_bus_clk, clk_count * 8);
-+	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
- 	us += 1000 * 1000; /* 1s tolerance */
- 
- 	if (us > UINT_MAX)
-@@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice
- 	clk_enable(&priv->sel_clk);
- 	clk_enable(&priv->spi_clk);
- 
-+	priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
-+	if (priv->pll_clk_rate == 0)
-+		return -EINVAL;
-+
- 	return 0;
- }
- 
diff --git a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch b/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch
deleted file mode 100644
index e8577f63bf..0000000000
--- a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From a7b630f02bb12f71f23866aee6f9a1a07497d475 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:02 +0800
-Subject: [PATCH 04/29] spi: mtk_spim: clear IRQ enable bits
-
-In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS.
-
-However these IRQ enable bits may be set in previous boot stage (BootROM).
-
-If we leave these bits not cleared, although u-boot has disabled IRQ and
-nothing will happen, the linux kernel may encounter panic during
-initializing the spim driver due to IRQ event happens before IRQ handler
-is properly setup.
-
-This patch clear IRQ bits to prevent this from happening.
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
----
- drivers/spi/mtk_spim.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -242,6 +242,9 @@ static int mtk_spim_hw_init(struct spi_s
- 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
- 	}
- 
-+	/* Disable interrupt enable for pause mode & normal mode */
-+	reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE);
-+
- 	/* disable dma mode */
- 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
- 
diff --git a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch b/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch
deleted file mode 100644
index 6f805765c1..0000000000
--- a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 73060da8b54e74c51ef6c1fd31c4fac6ad6b8d0e Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:07 +0800
-Subject: [PATCH 05/29] serial: mtk: initial priv data before using
-
-This patch ensures driver private data being fully initialized in
-_debug_uart_init which is not covered by .priv_auto ops.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-Reviewed-by: Stefan Roese <sr@denx.de>
----
- drivers/serial/serial_mtk.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/serial/serial_mtk.c
-+++ b/drivers/serial/serial_mtk.c
-@@ -439,6 +439,7 @@ static inline void _debug_uart_init(void
- {
- 	struct mtk_serial_priv priv;
- 
-+	memset(&priv, 0, sizeof(struct mtk_serial_priv));
- 	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
- 	priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
- 
diff --git a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch b/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch
deleted file mode 100644
index b319f5e27e..0000000000
--- a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 06e6d224f7d564a34407eba21b51797da7f22628 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:11 +0800
-Subject: [PATCH 06/29] reset: mediatek: check malloc return valaue before use
-
-This patch add missing return value check for allocating the driver's
-private data. -ENOMEM will be returned if malloc() fails.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/reset/reset-mediatek.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/reset/reset-mediatek.c
-+++ b/drivers/reset/reset-mediatek.c
-@@ -79,6 +79,9 @@ int mediatek_reset_bind(struct udevice *
- 		return ret;
- 
- 	priv = malloc(sizeof(struct mediatek_reset_priv));
-+	if (!priv)
-+		return -ENOMEM;
-+
- 	priv->regofs = regofs;
- 	priv->nr_resets = num_regs * 32;
- 	dev_set_priv(rst_dev, priv);
diff --git a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch b/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch
deleted file mode 100644
index dd00104c39..0000000000
--- a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch
+++ /dev/null
@@ -1,125 +0,0 @@
-From 77898faf6ce56eb08109cdb853f074bad5acee55 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:15 +0800
-Subject: [PATCH 07/29] i2c: mediatek: fix I2C usability for MT7981
-
-MT7981 actually uses MediaTek I2C controller v3 instead of v1.
-This patch adds support for I2C controller v3 fix fixes the I2C usability
-for MT7981.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/i2c/mtk_i2c.c | 45 +++++++++++++++++++++++++++++++++++++++++--
- 1 file changed, 43 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/mtk_i2c.c
-+++ b/drivers/i2c/mtk_i2c.c
-@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = {
- 	[REG_DCM_EN] = 0xf88,
- };
- 
-+static const uint mt_i2c_regs_v3[] = {
-+	[REG_PORT] = 0x0,
-+	[REG_INTR_MASK] = 0x8,
-+	[REG_INTR_STAT] = 0xc,
-+	[REG_CONTROL] = 0x10,
-+	[REG_TRANSFER_LEN] = 0x14,
-+	[REG_TRANSAC_LEN] = 0x18,
-+	[REG_DELAY_LEN] = 0x1c,
-+	[REG_TIMING] = 0x20,
-+	[REG_START] = 0x24,
-+	[REG_EXT_CONF] = 0x28,
-+	[REG_LTIMING] = 0x2c,
-+	[REG_HS] = 0x30,
-+	[REG_IO_CONFIG] = 0x34,
-+	[REG_FIFO_ADDR_CLR] = 0x38,
-+	[REG_TRANSFER_LEN_AUX] = 0x44,
-+	[REG_CLOCK_DIV] = 0x48,
-+	[REG_SOFTRESET] = 0x50,
-+	[REG_SLAVE_ADDR] = 0x94,
-+	[REG_DEBUGSTAT] = 0xe4,
-+	[REG_DEBUGCTRL] = 0xe8,
-+	[REG_FIFO_STAT] = 0xf4,
-+	[REG_FIFO_THRESH] = 0xf8,
-+	[REG_DCM_EN] = 0xf88,
-+};
-+
- struct mtk_i2c_soc_data {
- 	const uint *regs;
- 	uint dma_sync: 1;
-+	uint ltiming_adjust: 1;
- };
- 
- struct mtk_i2c_priv {
-@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udev
- 				(sample_cnt << HS_SAMPLE_OFFSET) |
- 				(step_cnt << HS_STEP_OFFSET);
- 		i2c_writel(priv, REG_HS, high_speed_reg);
-+		if (priv->soc_data->ltiming_adjust) {
-+			timing_reg = (sample_cnt << 12) | (step_cnt << 9);
-+			i2c_writel(priv, REG_LTIMING, timing_reg);
-+		}
- 	} else {
- 		ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
- 					      &step_cnt, &sample_cnt);
-@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udev
- 		high_speed_reg = I2C_TIME_CLR_VALUE;
- 		i2c_writel(priv, REG_TIMING, timing_reg);
- 		i2c_writel(priv, REG_HS, high_speed_reg);
-+		if (priv->soc_data->ltiming_adjust) {
-+			timing_reg = (sample_cnt << 6) | step_cnt;
-+			i2c_writel(priv, REG_LTIMING, timing_reg);
-+		}
- 	}
-+
- exit:
- 	if (mtk_i2c_clk_disable(priv))
- 		return log_msg_ret("set_speed disable clk", -1);
-@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice
- 		return log_msg_ret("probe enable clk", -1);
- 
- 	mtk_i2c_init_hw(priv);
--
- 	if (mtk_i2c_clk_disable(priv))
- 		return log_msg_ret("probe disable clk", -1);
- 
-@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevic
- static const struct mtk_i2c_soc_data mt76xx_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 0,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt7981_soc_data = {
--	.regs = mt_i2c_regs_v1,
-+	.regs = mt_i2c_regs_v3,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 1,
- };
- 
- static const struct mtk_i2c_soc_data mt7986_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8183_soc_data = {
- 	.regs = mt_i2c_regs_v2,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8518_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 0,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct mtk_i2c_soc_data mt8512_soc_data = {
- 	.regs = mt_i2c_regs_v1,
- 	.dma_sync = 1,
-+	.ltiming_adjust = 0,
- };
- 
- static const struct dm_i2c_ops mtk_i2c_ops = {
diff --git a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch b/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch
deleted file mode 100644
index 77c4023493..0000000000
--- a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From e9467f40d4327cfcb80944a0f12ae195b0d7cd40 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:19 +0800
-Subject: [PATCH 08/29] arm: dts: enable i2c support for MediaTek MT7981
-
-This patch enables i2c support for MediaTek MT7981
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm/dts/mt7981.dtsi
-+++ b/arch/arm/dts/mt7981.dtsi
-@@ -181,6 +181,20 @@
- 		status = "disabled";
- 	};
- 
-+	i2c0: i2c@11007000 {
-+		compatible = "mediatek,mt7981-i2c";
-+		reg = <0x11007000 0x1000>,
-+		      <0x10217080 0x80>;
-+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
-+			 <&infracfg_ao CK_INFRA_AP_DMA_CK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	uart0: serial@11002000 {
- 		compatible = "mediatek,hsuart";
- 		reg = <0x11002000 0x400>;
diff --git a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch
deleted file mode 100644
index 6ef62811cb..0000000000
--- a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 646dab4a8e853b2d0789fa2ff64e7c48f5396cfa Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:24 +0800
-Subject: [PATCH 09/29] pwm: mtk: add support for MediaTek MT7988 SoC
-
-This patch adds PWM support for MediaTek MT7988 SoC.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pwm/pwm-mtk.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/pwm/pwm-mtk.c
-+++ b/drivers/pwm/pwm-mtk.c
-@@ -205,12 +205,19 @@ static const struct mtk_pwm_soc mt7986_d
- 	.reg_ver = PWM_REG_V1,
- };
- 
-+static const struct mtk_pwm_soc mt7988_data = {
-+	.num_pwms = 8,
-+	.pwm45_fixup = false,
-+	.reg_ver = PWM_REG_V2,
-+};
-+
- static const struct udevice_id mtk_pwm_ids[] = {
- 	{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
- 	{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
- 	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
- 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
-+	{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
- 	{ }
- };
- 
diff --git a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
deleted file mode 100644
index 12eda828fa..0000000000
--- a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
+++ /dev/null
@@ -1,1505 +0,0 @@
-From 94306126baa215c39e9fd5328550586dedf00230 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:28 +0800
-Subject: [PATCH 10/29] clk: mediatek: add clock driver support for MediaTek
- MT7988 SoC
-
-This patch adds clock driver support for MediaTek MT7988 SoC
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/clk/mediatek/Makefile          |    1 +
- drivers/clk/mediatek/clk-mt7988.c      | 1123 ++++++++++++++++++++++++
- include/dt-bindings/clock/mt7988-clk.h |  349 ++++++++
- 3 files changed, 1473 insertions(+)
- create mode 100644 drivers/clk/mediatek/clk-mt7988.c
- create mode 100644 include/dt-bindings/clock/mt7988-clk.h
-
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7622) += clk-mt762
- obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
- obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
- obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
-+obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
- obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
- obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
- obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988.c
-@@ -0,0 +1,1123 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek clock driver for MT7988 SoC
-+ *
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dm.h>
-+#include <log.h>
-+#include <asm/arch-mediatek/reset.h>
-+#include <asm/io.h>
-+#include <dt-bindings/clock/mt7988-clk.h>
-+#include <linux/bitops.h>
-+
-+#include "clk-mtk.h"
-+
-+#define MT7988_CLK_PDN		0x250
-+#define MT7988_CLK_PDN_EN_WRITE BIT(31)
-+
-+#define MT7988_ETHDMA_RST_CTRL_OFS	0x34
-+#define MT7988_ETHWARP_RST_CTRL_OFS	0x8
-+
-+#define XTAL_FACTOR(_id, _name, _parent, _mult, _div)                          \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
-+
-+#define PLL_FACTOR(_id, _name, _parent, _mult, _div)                           \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
-+
-+#define TOP_FACTOR(_id, _name, _parent, _mult, _div)                           \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
-+
-+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div)                         \
-+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
-+
-+/* FIXED PLLS */
-+static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
-+	FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
-+	FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
-+	FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
-+	FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
-+	FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
-+	FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
-+	FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
-+	FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
-+	FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
-+	FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
-+	FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
-+	FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
-+};
-+
-+/* TOPCKGEN FIXED DIV */
-+static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
-+	XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
-+	PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
-+	PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
-+	PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
-+		   1),
-+	PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
-+	PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
-+	PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
-+	PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
-+	PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
-+	PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
-+		   128),
-+	PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
-+		   1),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
-+	PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
-+	PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
-+	PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
-+	PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
-+		   CK_APMIXED_WEDMCUPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
-+		   CK_APMIXED_NETSYSPLL, 1, 1),
-+	PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
-+	TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
-+		   1250),
-+	TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
-+		   1220),
-+	TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
-+		   1),
-+	XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
-+	TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
-+		   CK_TOP_NETSYS_MCU_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
-+		   CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
-+	TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
-+		   1, 1),
-+	TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
-+	TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
-+};
-+
-+/* TOPCKGEN MUX PARENTS */
-+static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
-+				      CK_TOP_CB_MM_D2 };
-+
-+static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					   CK_TOP_CB_NET1_D5,
-+					   CK_TOP_NET1_D5_D2 };
-+
-+static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					 CK_TOP_CB_NET2_800M,
-+					 CK_TOP_CB_MM_720M };
-+
-+static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
-+					  CK_TOP_CB_NET1_D5 };
-+
-+static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
-+
-+static const int netsys_mcu_parents[] = {
-+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
-+	CK_TOP_CB_NET1_D4,  CK_TOP_CB_NET1_D5,   CK_TOP_CB_M_416M
-+};
-+
-+static const int eip197_parents[] = {
-+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
-+	CK_TOP_CB_MM_720M,  CK_TOP_CB_NET1_D4,     CK_TOP_CB_NET1_D5
-+};
-+
-+static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					 CK_TOP_NET1_D8_D2 };
-+
-+static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
-+				    CK_TOP_M_D8_D2 };
-+
-+static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
-+					 CK_TOP_CB_MM_D4 };
-+
-+static const int emmc_400m_parents[] = {
-+	CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
-+	CK_TOP_CB_M_D2,     CK_TOP_CB_MM_D4,     CK_TOP_NET1_D8_D2
-+};
-+
-+static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
-+				   CK_TOP_CB_MM_D4,    CK_TOP_NET1_D8_D2,
-+				   CK_TOP_CB_NET2_D6,  CK_TOP_NET1_D5_D4,
-+				   CK_TOP_CB_M_D4,     CK_TOP_NET1_D8_D4 };
-+
-+static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
-+				     CK_TOP_NET1_D8_D2,  CK_TOP_CB_NET2_D6,
-+				     CK_TOP_CB_M_D4,     CK_TOP_CB_MM_D8,
-+				     CK_TOP_NET1_D8_D4,  CK_TOP_CB_M_D8 };
-+
-+static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
-+				      CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
-+				      CK_TOP_CB_MM_D8,    CK_TOP_NET1_D8_D4,
-+				      CK_TOP_MM_D6_D2,    CK_TOP_CB_M_D8 };
-+
-+static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
-+				   CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
-+				   CK_TOP_M_D8_D2,     CK_TOP_CB_RTC_32K };
-+
-+static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
-+				   CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
-+
-+static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					       CK_TOP_NET1_D5_D2 };
-+
-+static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					   CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
-+					   CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
-+
-+static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					  CK_TOP_CB_MM_D3_D5 };
-+
-+static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
-+
-+static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
-+
-+static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
-+				     CK_TOP_M_D8_D2 };
-+
-+static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
-+
-+static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					      CK_TOP_NET1_D8_D4 };
-+
-+static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
-+
-+static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
-+
-+static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					     CK_TOP_NET2_D4_D4 };
-+
-+static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					    CK_TOP_CB_NET2_D4 };
-+
-+static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
-+					 CK_TOP_NET1_D8_D16 };
-+
-+static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
-+					CK_TOP_CB_NET2_D2 };
-+
-+static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					CK_TOP_CB_NET2_800M };
-+
-+static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
-+					  CK_TOP_CB_WEDMCU_208M };
-+
-+static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
-+					     CK_TOP_CB_NET2_D8 };
-+
-+static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+						  CK_TOP_CB_NET1_D4 };
-+
-+static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
-+				      CK_TOP_CB_NET1_D8 };
-+
-+static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
-+						CK_TOP_CB_NET2_D2 };
-+
-+static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
-+
-+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
-+		_shift, _width, _gate, _upd_ofs, _upd)                         \
-+	{                                                                      \
-+		.id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs,   \
-+		.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs,              \
-+		.upd_shift = _upd, .mux_shift = _shift,                        \
-+		.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs,             \
-+		.gate_shift = _gate, .parent = _parents,                       \
-+		.num_parents = ARRAY_SIZE(_parents),                           \
-+		.flags = CLK_MUX_SETCLR_UPD,                                   \
-+	}
-+
-+/* TOPCKGEN MUX_GATE */
-+static const struct mtk_composite topckgen_mtk_muxes[] = {
-+	TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
-+		0, 2, 7, 0x1c0, 0),
-+	TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
-+		0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
-+	TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
-+		0x4, 0x8, 16, 2, 23, 0x1c0, 2),
-+	TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
-+		0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
-+	TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
-+		0x14, 0x18, 0, 1, 7, 0x1c0, 4),
-+	TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
-+		0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
-+	TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
-+		netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
-+	TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
-+		0x18, 24, 3, 31, 0x1c0, 7),
-+	TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
-+		0x24, 0x28, 0, 1, 7, 0x1c0, 8),
-+	TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
-+		2, 15, 0x1c0, 9),
-+	TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
-+		0x24, 0x28, 16, 2, 23, 0x1c0, 10),
-+	TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
-+		0x24, 0x28, 24, 3, 31, 0x1c0, 11),
-+	TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
-+		7, 0x1c0, 12),
-+	TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
-+		0x38, 8, 3, 15, 0x1c0, 13),
-+	TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
-+		16, 3, 23, 0x1c0, 14),
-+	TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
-+		0x38, 24, 3, 31, 0x1c0, 15),
-+	TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
-+		7, 0x1c0, 16),
-+	TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
-+		15, 0x1c0, 17),
-+	TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
-+		pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
-+		18),
-+	TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
-+		0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
-+	TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
-+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
-+	TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
-+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
-+	TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
-+		pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
-+	TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
-+		0x58, 24, 1, 31, 0x1c0, 23),
-+	TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
-+		0x64, 0x68, 0, 1, 7, 0x1c0, 24),
-+	TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
-+		0x64, 0x68, 8, 1, 15, 0x1c0, 25),
-+	TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
-+		0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
-+	TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
-+		0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
-+	TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
-+		usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
-+	TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
-+		15, 0x1c0, 29),
-+	TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
-+		16, 1, 23, 0x1c0, 30),
-+	TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
-+		24, 2, 31, 0x1c4, 0),
-+	TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
-+		0x88, 0, 1, 7, 0x1c4, 1),
-+	TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
-+		0x88, 8, 1, 15, 0x1c4, 2),
-+	TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
-+		0x88, 16, 1, 23, 0x1c4, 3),
-+	TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-+		usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
-+	TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-+		usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
-+	TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
-+		8, 1, 15, 0x1c4, 6),
-+	TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
-+		0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
-+	TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
-+		24, 1, 31, 0x1c4, 8),
-+	TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
-+		0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
-+	TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
-+		0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
-+	TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
-+		0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
-+	TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
-+		0xa8, 24, 1, 31, 0x1c4, 12),
-+	TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
-+		0xb8, 0, 1, 7, 0x1c4, 13),
-+	TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
-+		eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
-+	TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
-+		eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
-+	TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
-+		0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
-+	TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
-+		0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
-+	TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
-+		0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
-+	TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
-+		0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
-+	TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
-+		24, 1, 31, 0x1c4, 20),
-+	TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
-+		0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
-+	TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-+		0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
-+	TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
-+		0xd8, 16, 1, 23, 0x1c4, 23),
-+	TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
-+		0xd8, 24, 1, 31, 0x1c4, 24),
-+	TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
-+		0xe8, 0, 1, 7, 0x1c4, 25),
-+	TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
-+		0xe8, 8, 1, 15, 0x1c4, 26),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
-+		da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
-+		da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
-+		da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
-+	TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
-+		da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
-+	TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
-+		1, 23, 0x1c8, 0),
-+	TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
-+		0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
-+	TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
-+		0x108, 0, 1, 7, 0x1c8, 2),
-+	TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
-+		0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
-+	TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
-+		mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
-+		0x1c8, 4),
-+	TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
-+		pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
-+		5),
-+	TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
-+		0x118, 0, 2, 7, 0x1c8, 6),
-+	TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
-+		netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
-+		7),
-+	TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
-+		pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
-+		8),
-+	TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
-+		0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
-+	TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
-+		0x124, 0x128, 0, 1, 7, 0x1c8, 10),
-+	TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
-+		netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
-+};
-+
-+/* INFRA FIXED DIV */
-+static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
-+	TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
-+		   CK_TOP_PEXTP_TL_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
-+		   CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
-+		   CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
-+		   CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
-+	INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
-+		     1, 1),
-+	INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
-+		     1),
-+	TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
-+	TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
-+	TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
-+	TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
-+	TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
-+	INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
-+		     1, 1),
-+	TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
-+	TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
-+		   CK_TOP_EMMC_250M, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
-+		   CK_TOP_USB_FRMCNT, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
-+		   CK_TOP_USB_FRMCNT_P1, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
-+		   CK_TOP_USB_XHCI_P1, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
-+		    1),
-+	XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
-+		    1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
-+		    CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
-+		    CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
-+		    CLK_XTAL, 1, 1),
-+	XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
-+		    CLK_XTAL, 1, 1),
-+	TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
-+	TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
-+	TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
-+	TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
-+		   1),
-+	TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
-+	TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
-+		   CK_TOP_USB_SYS_P1, 1, 1),
-+};
-+
-+/* INFRASYS MUX PARENTS */
-+static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
-+					       CK_INFRA_UART_O0 };
-+
-+static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
-+					       CK_INFRA_UART_O1 };
-+
-+static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
-+					       CK_INFRA_UART_O2 };
-+
-+static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
-+
-+static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
-+
-+static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
-+					     CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
-+					     CK_INFRA_PWM_O };
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P0
-+};
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P1
-+};
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P2
-+};
-+
-+static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
-+	CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
-+	CK_INFRA_PCIE_OCC_P3
-+};
-+
-+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
-+	{                                                                      \
-+		.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0,   \
-+		.mux_clr_reg = _reg + 0x4, .mux_shift = _shift,                \
-+		.mux_mask = BIT(_width) - 1, .parent = _parents,               \
-+		.num_parents = ARRAY_SIZE(_parents),                           \
-+		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS,             \
-+	}
-+
-+/* INFRA MUX */
-+static const struct mtk_composite infracfg_mtk_mux[] = {
-+	INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-+		  infra_mux_uart0_parents, 0x10, 0, 1),
-+	INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-+		  infra_mux_uart1_parents, 0x10, 1, 1),
-+	INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-+		  infra_mux_uart2_parents, 0x10, 2, 1),
-+	INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
-+		  infra_mux_spi0_parents, 0x10, 4, 1),
-+	INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
-+		  infra_mux_spi1_parents, 0x10, 5, 1),
-+	INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
-+		  infra_mux_spi0_parents, 0x10, 6, 1),
-+	INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
-+		  0x10, 14, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
-+		  infra_pwm_bck_parents, 0x10, 16, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
-+		  infra_pwm_bck_parents, 0x10, 18, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
-+		  infra_pwm_bck_parents, 0x10, 20, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
-+		  infra_pwm_bck_parents, 0x10, 22, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
-+		  infra_pwm_bck_parents, 0x10, 24, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
-+		  infra_pwm_bck_parents, 0x10, 26, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
-+		  infra_pwm_bck_parents, 0x10, 28, 2),
-+	INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
-+		  infra_pwm_bck_parents, 0x10, 30, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
-+		  "infra_pcie_gfmux_tl_o_p0_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
-+		  "infra_pcie_gfmux_tl_o_p1_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
-+		  "infra_pcie_gfmux_tl_o_p2_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
-+	INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
-+		  "infra_pcie_gfmux_tl_o_p3_sel",
-+		  infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
-+};
-+
-+static const struct mtk_gate_regs infra_0_cg_regs = {
-+	.set_ofs = 0x10,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x18,
-+};
-+
-+static const struct mtk_gate_regs infra_1_cg_regs = {
-+	.set_ofs = 0x40,
-+	.clr_ofs = 0x44,
-+	.sta_ofs = 0x48,
-+};
-+
-+static const struct mtk_gate_regs infra_2_cg_regs = {
-+	.set_ofs = 0x50,
-+	.clr_ofs = 0x54,
-+	.sta_ofs = 0x58,
-+};
-+
-+static const struct mtk_gate_regs infra_3_cg_regs = {
-+	.set_ofs = 0x60,
-+	.clr_ofs = 0x64,
-+	.sta_ofs = 0x68,
-+};
-+
-+#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_0_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_1_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_2_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+#define GATE_INFRA3(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &infra_3_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
-+	}
-+
-+/* INFRA GATE */
-+static const struct mtk_gate infracfg_mtk_gates[] = {
-+	GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
-+		    CK_INFRA_66M_MCK, 0),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
-+		    CK_INFRA_66M_MCK, 1),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
-+		    CK_INFRA_PWM_SEL, 2),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
-+		    CK_INFRA_PWM_CK1_SEL, 3),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
-+		    CK_INFRA_PWM_CK2_SEL, 4),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
-+		    CK_INFRA_PWM_CK3_SEL, 5),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
-+		    CK_INFRA_PWM_CK4_SEL, 6),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
-+		    CK_INFRA_PWM_CK5_SEL, 7),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
-+		    CK_INFRA_PWM_CK6_SEL, 8),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
-+		    CK_INFRA_PWM_CK7_SEL, 9),
-+	GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
-+		    CK_INFRA_PWM_CK8_SEL, 10),
-+	GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
-+		    CK_INFRA_133M_MCK, 12),
-+	GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
-+		    CK_INFRA_66M_PHCK, 13),
-+	GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
-+	GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
-+	GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
-+		    16),
-+	GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
-+		    18),
-+	GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
-+		    19),
-+	GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
-+		    CK_INFRA_133M_MCK, 20),
-+	GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
-+		    CK_INFRA_66M_MCK, 21),
-+	GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
-+		    CK_INFRA_66M_MCK, 29),
-+	GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
-+		    CK_INFRA_CK_F26M, 30),
-+	GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
-+		    31),
-+	GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
-+		    CK_INFRA_CK_F26M, 0),
-+	GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
-+	GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
-+		    CK_INFRA_66M_MCK, 3),
-+	GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
-+		    CK_INFRA_66M_MCK, 4),
-+	GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
-+		    CK_INFRA_66M_MCK, 5),
-+	GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
-+		    CK_INFRA_MUX_UART0_SEL, 3),
-+	GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
-+		    CK_INFRA_MUX_UART1_SEL, 4),
-+	GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
-+		    CK_INFRA_MUX_UART2_SEL, 5),
-+	GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
-+	GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
-+	GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
-+		    CK_INFRA_66M_MCK, 11),
-+	GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
-+		    CK_INFRA_MUX_SPI0_SEL, 12),
-+	GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
-+		    CK_INFRA_MUX_SPI1_SEL, 13),
-+	GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
-+		    CK_INFRA_MUX_SPI2_SEL, 14),
-+	GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
-+		    CK_INFRA_66M_MCK, 15),
-+	GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
-+		    CK_INFRA_66M_MCK, 16),
-+	GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
-+		    CK_INFRA_66M_MCK, 17),
-+	GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
-+		    CK_INFRA_66M_MCK, 18),
-+	GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
-+	GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
-+		    CK_INFRA_F26M_O1, 20),
-+	GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
-+		    21),
-+	GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
-+		    22),
-+	GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
-+		    CK_INFRA_FMSDC2_HCK_OCC, 23),
-+	GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
-+		    CK_INFRA_PERI_133M, 24),
-+	GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
-+		    CK_INFRA_66M_PHCK, 25),
-+	GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
-+		    CK_INFRA_133M_MCK, 26),
-+	GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
-+		    27),
-+	GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
-+		    CK_INFRA_133M_MCK, 29),
-+	GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
-+		    CK_INFRA_66M_PHCK, 31),
-+	GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
-+		    CK_INFRA_133M_PHCK, 0),
-+	GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
-+		    CK_INFRA_133M_PHCK, 1),
-+	GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
-+		    CK_INFRA_66M_PHCK, 2),
-+	GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
-+		    CK_INFRA_66M_PHCK, 3),
-+	GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
-+	GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
-+		    CK_INFRA_USB_SYS_O_P1, 5),
-+	GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
-+	GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
-+		    7),
-+	GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
-+		    CK_INFRA_USB_FRMCNT_O, 8),
-+	GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
-+		    CK_INFRA_USB_FRMCNT_O_P1, 9),
-+	GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
-+		    10),
-+	GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
-+		    CK_INFRA_USB_PIPE_O_P1, 11),
-+	GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
-+		    12),
-+	GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
-+		    CK_INFRA_USB_UTMI_O_P1, 13),
-+	GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
-+		    14),
-+	GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
-+		    CK_INFRA_USB_XHCI_O_P1, 15),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
-+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-+		    CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
-+		    CK_INFRA_PCIE_PIPE_OCC_P0, 24),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
-+		    CK_INFRA_PCIE_PIPE_OCC_P1, 25),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
-+		    CK_INFRA_PCIE_PIPE_OCC_P2, 26),
-+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
-+		    CK_INFRA_PCIE_PIPE_OCC_P3, 27),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
-+		    CK_INFRA_133M_PHCK, 28),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
-+		    CK_INFRA_133M_PHCK, 29),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
-+		    CK_INFRA_133M_PHCK, 30),
-+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
-+		    CK_INFRA_133M_PHCK, 31),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
-+		    "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
-+		    "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
-+		    "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
-+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
-+		    "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
-+};
-+
-+static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
-+	.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
-+	.fclks = apmixedsys_mtk_plls,
-+	.xtal_rate = 40 * MHZ,
-+};
-+
-+static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
-+	.fdivs_offs = CK_TOP_CB_CKSQ_40M,
-+	.muxes_offs = CK_TOP_NETSYS_SEL,
-+	.fdivs = topckgen_mtk_fixed_factors,
-+	.muxes = topckgen_mtk_muxes,
-+	.flags = CLK_BYPASS_XTAL,
-+	.xtal_rate = 40 * MHZ,
-+};
-+
-+static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
-+	.fdivs_offs = CK_INFRA_CK_F26M,
-+	.muxes_offs = CK_INFRA_MUX_UART0_SEL,
-+	.fdivs = infracfg_mtk_fixed_factor,
-+	.muxes = infracfg_mtk_mux,
-+	.flags = CLK_BYPASS_XTAL,
-+	.xtal_rate = 40 * MHZ,
-+};
-+
-+static const struct udevice_id mt7988_fixed_pll_compat[] = {
-+	{ .compatible = "mediatek,mt7988-fixed-plls" },
-+	{}
-+};
-+
-+static const struct udevice_id mt7988_topckgen_compat[] = {
-+	{ .compatible = "mediatek,mt7988-topckgen" },
-+	{}
-+};
-+
-+static int mt7988_fixed_pll_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree);
-+}
-+
-+static int mt7988_topckgen_probe(struct udevice *dev)
-+{
-+	struct mtk_clk_priv *priv = dev_get_priv(dev);
-+
-+	priv->base = dev_read_addr_ptr(dev);
-+	if (!priv->base)
-+		return -ENOENT;
-+
-+	writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
-+	return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
-+}
-+
-+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
-+	.name = "mt7988-clock-fixed-pll",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_fixed_pll_compat,
-+	.probe = mt7988_fixed_pll_probe,
-+	.priv_auto = sizeof(struct mtk_clk_priv),
-+	.ops = &mtk_clk_topckgen_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_topckgen) = {
-+	.name = "mt7988-clock-topckgen",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_topckgen_compat,
-+	.probe = mt7988_topckgen_probe,
-+	.priv_auto = sizeof(struct mtk_clk_priv),
-+	.ops = &mtk_clk_topckgen_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+static const struct udevice_id mt7988_infracfg_compat[] = {
-+	{ .compatible = "mediatek,mt7988-infracfg" },
-+	{}
-+};
-+
-+static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
-+	{ .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
-+	{}
-+};
-+
-+static int mt7988_infracfg_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
-+}
-+
-+static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
-+					infracfg_mtk_gates);
-+}
-+
-+U_BOOT_DRIVER(mtk_clk_infracfg) = {
-+	.name = "mt7988-clock-infracfg",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_infracfg_compat,
-+	.probe = mt7988_infracfg_probe,
-+	.priv_auto = sizeof(struct mtk_clk_priv),
-+	.ops = &mtk_clk_infrasys_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
-+	.name = "mt7988-clock-infracfg_ao_cgs",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_infracfg_ao_cgs_compat,
-+	.probe = mt7988_infracfg_ao_cgs_probe,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+	.flags = DM_FLAG_PRE_RELOC,
-+};
-+
-+/* ETHDMA */
-+
-+static const struct mtk_gate_regs ethdma_cg_regs = {
-+	.set_ofs = 0x30,
-+	.clr_ofs = 0x30,
-+	.sta_ofs = 0x30,
-+};
-+
-+#define GATE_ETHDMA(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &ethdma_cg_regs,         \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate ethdma_mtk_gate[] = {
-+	GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
-+};
-+
-+static int mt7988_ethdma_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					ethdma_mtk_gate);
-+}
-+
-+static int mt7988_ethdma_bind(struct udevice *dev)
-+{
-+	int ret = 0;
-+
-+	if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
-+		ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1);
-+		if (ret)
-+			debug("Warning: failed to bind reset controller\n");
-+	}
-+
-+	return ret;
-+}
-+
-+static const struct udevice_id mt7988_ethdma_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-ethdma",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_ethdma) = {
-+	.name = "mt7988-clock-ethdma",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_ethdma_compat,
-+	.probe = mt7988_ethdma_probe,
-+	.bind = mt7988_ethdma_bind,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
-+
-+/* SGMIISYS_0 */
-+
-+static const struct mtk_gate_regs sgmii0_cg_regs = {
-+	.set_ofs = 0xE4,
-+	.clr_ofs = 0xE4,
-+	.sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &sgmii0_cg_regs,         \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
-+};
-+
-+static int mt7988_sgmiisys_0_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					sgmiisys_0_mtk_gate);
-+}
-+
-+static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-sgmiisys_0",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = {
-+	.name = "mt7988-clock-sgmiisys_0",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_sgmiisys_0_compat,
-+	.probe = mt7988_sgmiisys_0_probe,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
-+
-+/* SGMIISYS_1 */
-+
-+static const struct mtk_gate_regs sgmii1_cg_regs = {
-+	.set_ofs = 0xE4,
-+	.clr_ofs = 0xE4,
-+	.sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &sgmii1_cg_regs,         \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
-+	/* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
-+	GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
-+};
-+
-+static int mt7988_sgmiisys_1_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					sgmiisys_1_mtk_gate);
-+}
-+
-+static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-sgmiisys_1",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = {
-+	.name = "mt7988-clock-sgmiisys_1",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_sgmiisys_1_compat,
-+	.probe = mt7988_sgmiisys_1_probe,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
-+
-+/* ETHWARP */
-+
-+static const struct mtk_gate_regs ethwarp_cg_regs = {
-+	.set_ofs = 0x14,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x14,
-+};
-+
-+#define GATE_ETHWARP(_id, _name, _parent, _shift)                              \
-+	{                                                                      \
-+		.id = _id, .parent = _parent, .regs = &ethwarp_cg_regs,        \
-+		.shift = _shift,                                               \
-+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
-+	}
-+
-+static const struct mtk_gate ethwarp_mtk_gate[] = {
-+	GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
-+		     CK_TOP_NETSYS_WED_MCU, 13),
-+	GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
-+		     CK_TOP_NETSYS_WED_MCU, 14),
-+	GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
-+		     CK_TOP_NETSYS_WED_MCU, 15),
-+};
-+
-+static int mt7988_ethwarp_probe(struct udevice *dev)
-+{
-+	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-+					ethwarp_mtk_gate);
-+}
-+
-+static int mt7988_ethwarp_bind(struct udevice *dev)
-+{
-+	int ret = 0;
-+
-+	if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
-+		ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2);
-+		if (ret)
-+			debug("Warning: failed to bind reset controller\n");
-+	}
-+
-+	return ret;
-+}
-+
-+static const struct udevice_id mt7988_ethwarp_compat[] = {
-+	{
-+		.compatible = "mediatek,mt7988-ethwarp",
-+	},
-+	{}
-+};
-+
-+U_BOOT_DRIVER(mtk_clk_ethwarp) = {
-+	.name = "mt7988-clock-ethwarp",
-+	.id = UCLASS_CLK,
-+	.of_match = mt7988_ethwarp_compat,
-+	.probe = mt7988_ethwarp_probe,
-+	.bind = mt7988_ethwarp_bind,
-+	.priv_auto = sizeof(struct mtk_cg_priv),
-+	.ops = &mtk_clk_gate_ops,
-+};
---- /dev/null
-+++ b/include/dt-bindings/clock/mt7988-clk.h
-@@ -0,0 +1,349 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
-+ *
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT7988_H
-+#define _DT_BINDINGS_CLK_MT7988_H
-+
-+/* INFRACFG */
-+/* mtk_fixed_factor */
-+#define CK_INFRA_CK_F26M	  0
-+#define CK_INFRA_PWM_O		  1
-+#define CK_INFRA_PCIE_OCC_P0	  2
-+#define CK_INFRA_PCIE_OCC_P1	  3
-+#define CK_INFRA_PCIE_OCC_P2	  4
-+#define CK_INFRA_PCIE_OCC_P3	  5
-+#define CK_INFRA_133M_HCK	  6
-+#define CK_INFRA_133M_PHCK	  7
-+#define CK_INFRA_66M_PHCK	  8
-+#define CK_INFRA_FAUD_L_O	  9
-+#define CK_INFRA_FAUD_AUD_O	  10
-+#define CK_INFRA_FAUD_EG2_O	  11
-+#define CK_INFRA_I2C_O		  12
-+#define CK_INFRA_UART_O0	  13
-+#define CK_INFRA_UART_O1	  14
-+#define CK_INFRA_UART_O2	  15
-+#define CK_INFRA_NFI_O		  16
-+#define CK_INFRA_SPINFI_O	  17
-+#define CK_INFRA_SPI0_O		  18
-+#define CK_INFRA_SPI1_O		  19
-+#define CK_INFRA_LB_MUX_FRTC	  20
-+#define CK_INFRA_FRTC		  21
-+#define CK_INFRA_FMSDC400_O	  22
-+#define CK_INFRA_FMSDC2_HCK_OCC	  23
-+#define CK_INFRA_PERI_133M	  24
-+#define CK_INFRA_USB_O		  25
-+#define CK_INFRA_USB_O_P1	  26
-+#define CK_INFRA_USB_FRMCNT_O	  27
-+#define CK_INFRA_USB_FRMCNT_O_P1  28
-+#define CK_INFRA_USB_XHCI_O	  29
-+#define CK_INFRA_USB_XHCI_O_P1	  30
-+#define CK_INFRA_USB_PIPE_O	  31
-+#define CK_INFRA_USB_PIPE_O_P1	  32
-+#define CK_INFRA_USB_UTMI_O	  33
-+#define CK_INFRA_USB_UTMI_O_P1	  34
-+#define CK_INFRA_PCIE_PIPE_OCC_P0 35
-+#define CK_INFRA_PCIE_PIPE_OCC_P1 36
-+#define CK_INFRA_PCIE_PIPE_OCC_P2 37
-+#define CK_INFRA_PCIE_PIPE_OCC_P3 38
-+#define CK_INFRA_F26M_O0	  39
-+#define CK_INFRA_F26M_O1	  40
-+#define CK_INFRA_133M_MCK	  41
-+#define CK_INFRA_66M_MCK	  42
-+#define CK_INFRA_PERI_66M_O	  43
-+#define CK_INFRA_USB_SYS_O	  44
-+#define CK_INFRA_USB_SYS_O_P1	  45
-+
-+/* INFRACFG_AO */
-+#define GATE_OFFSET 65
-+/* mtk_mux */
-+#define CK_INFRA_MUX_UART0_SEL		46 /* Linux CLK ID (0) */
-+#define CK_INFRA_MUX_UART1_SEL		47 /* Linux CLK ID (1) */
-+#define CK_INFRA_MUX_UART2_SEL		48 /* Linux CLK ID (2) */
-+#define CK_INFRA_MUX_SPI0_SEL		49 /* Linux CLK ID (3) */
-+#define CK_INFRA_MUX_SPI1_SEL		50 /* Linux CLK ID (4) */
-+#define CK_INFRA_MUX_SPI2_SEL		51 /* Linux CLK ID (5) */
-+#define CK_INFRA_PWM_SEL		52 /* Linux CLK ID (6) */
-+#define CK_INFRA_PWM_CK1_SEL		53 /* Linux CLK ID (7) */
-+#define CK_INFRA_PWM_CK2_SEL		54 /* Linux CLK ID (8) */
-+#define CK_INFRA_PWM_CK3_SEL		55 /* Linux CLK ID (9) */
-+#define CK_INFRA_PWM_CK4_SEL		56 /* Linux CLK ID (10) */
-+#define CK_INFRA_PWM_CK5_SEL		57 /* Linux CLK ID (11) */
-+#define CK_INFRA_PWM_CK6_SEL		58 /* Linux CLK ID (12) */
-+#define CK_INFRA_PWM_CK7_SEL		59 /* Linux CLK ID (13) */
-+#define CK_INFRA_PWM_CK8_SEL		60 /* Linux CLK ID (14) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
-+#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
-+/* mtk_gate */
-+#define CK_INFRA_66M_GPT_BCK	     (65 - GATE_OFFSET) /* Linux CLK ID (19) */
-+#define CK_INFRA_66M_PWM_HCK	     (66 - GATE_OFFSET) /* Linux CLK ID (20) */
-+#define CK_INFRA_66M_PWM_BCK	     (67 - GATE_OFFSET) /* Linux CLK ID (21) */
-+#define CK_INFRA_66M_PWM_CK1	     (68 - GATE_OFFSET) /* Linux CLK ID (22) */
-+#define CK_INFRA_66M_PWM_CK2	     (69 - GATE_OFFSET) /* Linux CLK ID (23) */
-+#define CK_INFRA_66M_PWM_CK3	     (70 - GATE_OFFSET) /* Linux CLK ID (24) */
-+#define CK_INFRA_66M_PWM_CK4	     (71 - GATE_OFFSET) /* Linux CLK ID (25) */
-+#define CK_INFRA_66M_PWM_CK5	     (72 - GATE_OFFSET) /* Linux CLK ID (26) */
-+#define CK_INFRA_66M_PWM_CK6	     (73 - GATE_OFFSET) /* Linux CLK ID (27) */
-+#define CK_INFRA_66M_PWM_CK7	     (74 - GATE_OFFSET) /* Linux CLK ID (28) */
-+#define CK_INFRA_66M_PWM_CK8	     (75 - GATE_OFFSET) /* Linux CLK ID (29) */
-+#define CK_INFRA_133M_CQDMA_BCK	     (76 - GATE_OFFSET) /* Linux CLK ID (30) */
-+#define CK_INFRA_66M_AUD_SLV_BCK     (77 - GATE_OFFSET) /* Linux CLK ID (31) */
-+#define CK_INFRA_AUD_26M	     (78 - GATE_OFFSET) /* Linux CLK ID (32) */
-+#define CK_INFRA_AUD_L		     (79 - GATE_OFFSET) /* Linux CLK ID (33) */
-+#define CK_INFRA_AUD_AUD	     (80 - GATE_OFFSET) /* Linux CLK ID (34) */
-+#define CK_INFRA_AUD_EG2	     (81 - GATE_OFFSET) /* Linux CLK ID (35) */
-+#define CK_INFRA_DRAMC_F26M	     (82 - GATE_OFFSET) /* Linux CLK ID (36) */
-+#define CK_INFRA_133M_DBG_ACKM	     (83 - GATE_OFFSET) /* Linux CLK ID (37) */
-+#define CK_INFRA_66M_AP_DMA_BCK	     (84 - GATE_OFFSET) /* Linux CLK ID (38) */
-+#define CK_INFRA_66M_SEJ_BCK	     (85 - GATE_OFFSET) /* Linux CLK ID (39) */
-+#define CK_INFRA_PRE_CK_SEJ_F13M     (86 - GATE_OFFSET) /* Linux CLK ID (40) */
-+#define CK_INFRA_66M_TRNG	     (87 - GATE_OFFSET) /* Linux CLK ID (41) */
-+#define CK_INFRA_26M_THERM_SYSTEM    (88 - GATE_OFFSET) /* Linux CLK ID (42) */
-+#define CK_INFRA_I2C_BCK	     (89 - GATE_OFFSET) /* Linux CLK ID (43) */
-+#define CK_INFRA_66M_UART0_PCK	     (90 - GATE_OFFSET) /* Linux CLK ID (44) */
-+#define CK_INFRA_66M_UART1_PCK	     (91 - GATE_OFFSET) /* Linux CLK ID (45) */
-+#define CK_INFRA_66M_UART2_PCK	     (92 - GATE_OFFSET) /* Linux CLK ID (46) */
-+#define CK_INFRA_52M_UART0_CK	     (93 - GATE_OFFSET) /* Linux CLK ID (47) */
-+#define CK_INFRA_52M_UART1_CK	     (94 - GATE_OFFSET) /* Linux CLK ID (48) */
-+#define CK_INFRA_52M_UART2_CK	     (95 - GATE_OFFSET) /* Linux CLK ID (49) */
-+#define CK_INFRA_NFI		     (96 - GATE_OFFSET) /* Linux CLK ID (50) */
-+#define CK_INFRA_SPINFI		     (97 - GATE_OFFSET) /* Linux CLK ID (51) */
-+#define CK_INFRA_66M_NFI_HCK	     (98 - GATE_OFFSET) /* Linux CLK ID (52) */
-+#define CK_INFRA_104M_SPI0	     (99 - GATE_OFFSET) /* Linux CLK ID (53) */
-+#define CK_INFRA_104M_SPI1	     (100 - GATE_OFFSET) /* Linux CLK ID (54) */
-+#define CK_INFRA_104M_SPI2_BCK	     (101 - GATE_OFFSET) /* Linux CLK ID (55) */
-+#define CK_INFRA_66M_SPI0_HCK	     (102 - GATE_OFFSET) /* Linux CLK ID (56) */
-+#define CK_INFRA_66M_SPI1_HCK	     (103 - GATE_OFFSET) /* Linux CLK ID (57) */
-+#define CK_INFRA_66M_SPI2_HCK	     (104 - GATE_OFFSET) /* Linux CLK ID (58) */
-+#define CK_INFRA_66M_FLASHIF_AXI     (105 - GATE_OFFSET) /* Linux CLK ID (59) */
-+#define CK_INFRA_RTC		     (106 - GATE_OFFSET) /* Linux CLK ID (60) */
-+#define CK_INFRA_26M_ADC_BCK	     (107 - GATE_OFFSET) /* Linux CLK ID (61) */
-+#define CK_INFRA_RC_ADC		     (108 - GATE_OFFSET) /* Linux CLK ID (62) */
-+#define CK_INFRA_MSDC400	     (109 - GATE_OFFSET) /* Linux CLK ID (63) */
-+#define CK_INFRA_MSDC2_HCK	     (110 - GATE_OFFSET) /* Linux CLK ID (64) */
-+#define CK_INFRA_133M_MSDC_0_HCK     (111 - GATE_OFFSET) /* Linux CLK ID (65) */
-+#define CK_INFRA_66M_MSDC_0_HCK	     (112 - GATE_OFFSET) /* Linux CLK ID (66) */
-+#define CK_INFRA_133M_CPUM_BCK	     (113 - GATE_OFFSET) /* Linux CLK ID (67) */
-+#define CK_INFRA_BIST2FPC	     (114 - GATE_OFFSET) /* Linux CLK ID (68) */
-+#define CK_INFRA_I2C_X16W_MCK_CK_P1  (115 - GATE_OFFSET) /* Linux CLK ID (69) */
-+#define CK_INFRA_I2C_X16W_PCK_CK_P1  (116 - GATE_OFFSET) /* Linux CLK ID (70) */
-+#define CK_INFRA_133M_USB_HCK	     (117 - GATE_OFFSET) /* Linux CLK ID (71) */
-+#define CK_INFRA_133M_USB_HCK_CK_P1  (118 - GATE_OFFSET) /* Linux CLK ID (72) */
-+#define CK_INFRA_66M_USB_HCK	     (119 - GATE_OFFSET) /* Linux CLK ID (73) */
-+#define CK_INFRA_66M_USB_HCK_CK_P1   (120 - GATE_OFFSET) /* Linux CLK ID (74) */
-+#define CK_INFRA_USB_SYS	     (121 - GATE_OFFSET) /* Linux CLK ID (75) */
-+#define CK_INFRA_USB_SYS_CK_P1	     (122 - GATE_OFFSET) /* Linux CLK ID (76) */
-+#define CK_INFRA_USB_REF	     (123 - GATE_OFFSET) /* Linux CLK ID (77) */
-+#define CK_INFRA_USB_CK_P1	     (124 - GATE_OFFSET) /* Linux CLK ID (78) */
-+#define CK_INFRA_USB_FRMCNT	     (125 - GATE_OFFSET) /* Linux CLK ID (79) */
-+#define CK_INFRA_USB_FRMCNT_CK_P1    (126 - GATE_OFFSET) /* Linux CLK ID (80) */
-+#define CK_INFRA_USB_PIPE	     (127 - GATE_OFFSET) /* Linux CLK ID (81) */
-+#define CK_INFRA_USB_PIPE_CK_P1	     (128 - GATE_OFFSET) /* Linux CLK ID (82) */
-+#define CK_INFRA_USB_UTMI	     (129 - GATE_OFFSET) /* Linux CLK ID (83) */
-+#define CK_INFRA_USB_UTMI_CK_P1	     (130 - GATE_OFFSET) /* Linux CLK ID (84) */
-+#define CK_INFRA_USB_XHCI	     (131 - GATE_OFFSET) /* Linux CLK ID (85) */
-+#define CK_INFRA_USB_XHCI_CK_P1	     (132 - GATE_OFFSET) /* Linux CLK ID (86) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P0    (133 - GATE_OFFSET) /* Linux CLK ID (87) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P1    (134 - GATE_OFFSET) /* Linux CLK ID (88) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P2    (135 - GATE_OFFSET) /* Linux CLK ID (89) */
-+#define CK_INFRA_PCIE_GFMUX_TL_P3    (136 - GATE_OFFSET) /* Linux CLK ID (90) */
-+#define CK_INFRA_PCIE_PIPE_P0	     (137 - GATE_OFFSET) /* Linux CLK ID (91) */
-+#define CK_INFRA_PCIE_PIPE_P1	     (138 - GATE_OFFSET) /* Linux CLK ID (92) */
-+#define CK_INFRA_PCIE_PIPE_P2	     (139 - GATE_OFFSET) /* Linux CLK ID (93) */
-+#define CK_INFRA_PCIE_PIPE_P3	     (140 - GATE_OFFSET) /* Linux CLK ID (94) */
-+#define CK_INFRA_133M_PCIE_CK_P0     (141 - GATE_OFFSET) /* Linux CLK ID (95) */
-+#define CK_INFRA_133M_PCIE_CK_P1     (142 - GATE_OFFSET) /* Linux CLK ID (96) */
-+#define CK_INFRA_133M_PCIE_CK_P2     (143 - GATE_OFFSET) /* Linux CLK ID (97) */
-+#define CK_INFRA_133M_PCIE_CK_P3     (144 - GATE_OFFSET) /* Linux CLK ID (98) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P1                                           \
-+	(146 - GATE_OFFSET) /* Linux CLK ID (100) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P2                                           \
-+	(147 - GATE_OFFSET) /* Linux CLK ID (101) */
-+#define CK_INFRA_PCIE_PERI_26M_CK_P3                                           \
-+	(148 - GATE_OFFSET) /* Linux CLK ID (102) */
-+
-+/* TOPCKGEN */
-+/* mtk_fixed_factor */
-+#define CK_TOP_CB_CKSQ_40M    0 /* Linux CLK ID (74) */
-+#define CK_TOP_CB_M_416M      1 /* Linux CLK ID (75) */
-+#define CK_TOP_CB_M_D2	      2 /* Linux CLK ID (76) */
-+#define CK_TOP_M_D3_D2	      3 /* Linux CLK ID (77) */
-+#define CK_TOP_CB_M_D4	      4 /* Linux CLK ID (78) */
-+#define CK_TOP_CB_M_D8	      5 /* Linux CLK ID (79) */
-+#define CK_TOP_M_D8_D2	      6 /* Linux CLK ID (80) */
-+#define CK_TOP_CB_MM_720M     7 /* Linux CLK ID (81) */
-+#define CK_TOP_CB_MM_D2	      8 /* Linux CLK ID (82) */
-+#define CK_TOP_CB_MM_D3_D5    9 /* Linux CLK ID (83) */
-+#define CK_TOP_CB_MM_D4	      10 /* Linux CLK ID (84) */
-+#define CK_TOP_MM_D6_D2	      11 /* Linux CLK ID (85) */
-+#define CK_TOP_CB_MM_D8	      12 /* Linux CLK ID (86) */
-+#define CK_TOP_CB_APLL2_196M  13 /* Linux CLK ID (87) */
-+#define CK_TOP_CB_APLL2_D4    14 /* Linux CLK ID (88) */
-+#define CK_TOP_CB_NET1_D4     15 /* Linux CLK ID (89) */
-+#define CK_TOP_CB_NET1_D5     16 /* Linux CLK ID (90) */
-+#define CK_TOP_NET1_D5_D2     17 /* Linux CLK ID (91) */
-+#define CK_TOP_NET1_D5_D4     18 /* Linux CLK ID (92) */
-+#define CK_TOP_CB_NET1_D8     19 /* Linux CLK ID (93) */
-+#define CK_TOP_NET1_D8_D2     20 /* Linux CLK ID (94) */
-+#define CK_TOP_NET1_D8_D4     21 /* Linux CLK ID (95) */
-+#define CK_TOP_NET1_D8_D8     22 /* Linux CLK ID (96) */
-+#define CK_TOP_NET1_D8_D16    23 /* Linux CLK ID (97) */
-+#define CK_TOP_CB_NET2_800M   24 /* Linux CLK ID (98) */
-+#define CK_TOP_CB_NET2_D2     25 /* Linux CLK ID (99) */
-+#define CK_TOP_CB_NET2_D4     26 /* Linux CLK ID (100) */
-+#define CK_TOP_NET2_D4_D4     27 /* Linux CLK ID (101) */
-+#define CK_TOP_NET2_D4_D8     28 /* Linux CLK ID (102) */
-+#define CK_TOP_CB_NET2_D6     29 /* Linux CLK ID (103) */
-+#define CK_TOP_CB_NET2_D8     30 /* Linux CLK ID (104) */
-+#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
-+#define CK_TOP_CB_SGM_325M    32 /* Linux CLK ID (106) */
-+#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
-+#define CK_TOP_CB_MSDC_400M   34 /* Linux CLK ID (108) */
-+#define CK_TOP_CKSQ_40M_D2    35 /* Linux CLK ID (109) */
-+#define CK_TOP_CB_RTC_32K     36 /* Linux CLK ID (110) */
-+#define CK_TOP_CB_RTC_32P7K   37 /* Linux CLK ID (111) */
-+#define CK_TOP_INFRA_F32K     38 /* Linux CLK ID (112) */
-+#define CK_TOP_CKSQ_SRC	      39 /* Linux CLK ID (113) */
-+#define CK_TOP_NETSYS_2X      40 /* Linux CLK ID (114) */
-+#define CK_TOP_NETSYS_GSW     41 /* Linux CLK ID (115) */
-+#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
-+#define CK_TOP_EIP197	      43 /* Linux CLK ID (117) */
-+#define CK_TOP_EMMC_250M      44 /* Linux CLK ID (118) */
-+#define CK_TOP_EMMC_400M      45 /* Linux CLK ID (119) */
-+#define CK_TOP_SPI	      46 /* Linux CLK ID (120) */
-+#define CK_TOP_SPIM_MST	      47 /* Linux CLK ID (121) */
-+#define CK_TOP_NFI1X	      48 /* Linux CLK ID (122) */
-+#define CK_TOP_SPINFI_BCK     49 /* Linux CLK ID (123) */
-+#define CK_TOP_I2C_BCK	      50 /* Linux CLK ID (124) */
-+#define CK_TOP_USB_SYS	      51 /* Linux CLK ID (125) */
-+#define CK_TOP_USB_SYS_P1     52 /* Linux CLK ID (126) */
-+#define CK_TOP_USB_XHCI	      53 /* Linux CLK ID (127) */
-+#define CK_TOP_USB_XHCI_P1    54 /* Linux CLK ID (128) */
-+#define CK_TOP_USB_FRMCNT     55 /* Linux CLK ID (129) */
-+#define CK_TOP_USB_FRMCNT_P1  56 /* Linux CLK ID (130) */
-+#define CK_TOP_AUD	      57 /* Linux CLK ID (131) */
-+#define CK_TOP_A1SYS	      58 /* Linux CLK ID (132) */
-+#define CK_TOP_AUD_L	      59 /* Linux CLK ID (133) */
-+#define CK_TOP_A_TUNER	      60 /* Linux CLK ID (134) */
-+#define CK_TOP_SYSAXI	      61 /* Linux CLK ID (135) */
-+#define CK_TOP_INFRA_F26M     62 /* Linux CLK ID (136) */
-+#define CK_TOP_USB_REF	      63 /* Linux CLK ID (137) */
-+#define CK_TOP_USB_CK_P1      64 /* Linux CLK ID (138) */
-+/* mtk_mux */
-+#define CK_TOP_NETSYS_SEL	      65 /* Linux CLK ID (0) */
-+#define CK_TOP_NETSYS_500M_SEL	      66 /* Linux CLK ID (1) */
-+#define CK_TOP_NETSYS_2X_SEL	      67 /* Linux CLK ID (2) */
-+#define CK_TOP_NETSYS_GSW_SEL	      68 /* Linux CLK ID (3) */
-+#define CK_TOP_ETH_GMII_SEL	      69 /* Linux CLK ID (4) */
-+#define CK_TOP_NETSYS_MCU_SEL	      70 /* Linux CLK ID (5) */
-+#define CK_TOP_NETSYS_PAO_2X_SEL      71 /* Linux CLK ID (6) */
-+#define CK_TOP_EIP197_SEL	      72 /* Linux CLK ID (7) */
-+#define CK_TOP_AXI_INFRA_SEL	      73 /* Linux CLK ID (8) */
-+#define CK_TOP_UART_SEL		      74 /* Linux CLK ID (9) */
-+#define CK_TOP_EMMC_250M_SEL	      75 /* Linux CLK ID (10) */
-+#define CK_TOP_EMMC_400M_SEL	      76 /* Linux CLK ID (11) */
-+#define CK_TOP_SPI_SEL		      77 /* Linux CLK ID (12) */
-+#define CK_TOP_SPIM_MST_SEL	      78 /* Linux CLK ID (13) */
-+#define CK_TOP_NFI1X_SEL	      79 /* Linux CLK ID (14) */
-+#define CK_TOP_SPINFI_SEL	      80 /* Linux CLK ID (15) */
-+#define CK_TOP_PWM_SEL		      81 /* Linux CLK ID (16) */
-+#define CK_TOP_I2C_SEL		      82 /* Linux CLK ID (17) */
-+#define CK_TOP_PCIE_MBIST_250M_SEL    83 /* Linux CLK ID (18) */
-+#define CK_TOP_PEXTP_TL_SEL	      84 /* Linux CLK ID (19) */
-+#define CK_TOP_PEXTP_TL_P1_SEL	      85 /* Linux CLK ID (20) */
-+#define CK_TOP_PEXTP_TL_P2_SEL	      86 /* Linux CLK ID (21) */
-+#define CK_TOP_PEXTP_TL_P3_SEL	      87 /* Linux CLK ID (22) */
-+#define CK_TOP_USB_SYS_SEL	      88 /* Linux CLK ID (23) */
-+#define CK_TOP_USB_SYS_P1_SEL	      89 /* Linux CLK ID (24) */
-+#define CK_TOP_USB_XHCI_SEL	      90 /* Linux CLK ID (25) */
-+#define CK_TOP_USB_XHCI_P1_SEL	      91 /* Linux CLK ID (26) */
-+#define CK_TOP_USB_FRMCNT_SEL	      92 /* Linux CLK ID (27) */
-+#define CK_TOP_USB_FRMCNT_P1_SEL      93 /* Linux CLK ID (28) */
-+#define CK_TOP_AUD_SEL		      94 /* Linux CLK ID (29) */
-+#define CK_TOP_A1SYS_SEL	      95 /* Linux CLK ID (30) */
-+#define CK_TOP_AUD_L_SEL	      96 /* Linux CLK ID (31) */
-+#define CK_TOP_A_TUNER_SEL	      97 /* Linux CLK ID (32) */
-+#define CK_TOP_SSPXTP_SEL	      98 /* Linux CLK ID (33) */
-+#define CK_TOP_USB_PHY_SEL	      99 /* Linux CLK ID (34) */
-+#define CK_TOP_USXGMII_SBUS_0_SEL     100 /* Linux CLK ID (35) */
-+#define CK_TOP_USXGMII_SBUS_1_SEL     101 /* Linux CLK ID (36) */
-+#define CK_TOP_SGM_0_SEL	      102 /* Linux CLK ID (37) */
-+#define CK_TOP_SGM_SBUS_0_SEL	      103 /* Linux CLK ID (38) */
-+#define CK_TOP_SGM_1_SEL	      104 /* Linux CLK ID (39) */
-+#define CK_TOP_SGM_SBUS_1_SEL	      105 /* Linux CLK ID (40) */
-+#define CK_TOP_XFI_PHY_0_XTAL_SEL     106 /* Linux CLK ID (41) */
-+#define CK_TOP_XFI_PHY_1_XTAL_SEL     107 /* Linux CLK ID (42) */
-+#define CK_TOP_SYSAXI_SEL	      108 /* Linux CLK ID (43) */
-+#define CK_TOP_SYSAPB_SEL	      109 /* Linux CLK ID (44) */
-+#define CK_TOP_ETH_REFCK_50M_SEL      110 /* Linux CLK ID (45) */
-+#define CK_TOP_ETH_SYS_200M_SEL	      111 /* Linux CLK ID (46) */
-+#define CK_TOP_ETH_SYS_SEL	      112 /* Linux CLK ID (47) */
-+#define CK_TOP_ETH_XGMII_SEL	      113 /* Linux CLK ID (48) */
-+#define CK_TOP_BUS_TOPS_SEL	      114 /* Linux CLK ID (49) */
-+#define CK_TOP_NPU_TOPS_SEL	      115 /* Linux CLK ID (50) */
-+#define CK_TOP_DRAMC_SEL	      116 /* Linux CLK ID (51) */
-+#define CK_TOP_DRAMC_MD32_SEL	      117 /* Linux CLK ID (52) */
-+#define CK_TOP_INFRA_F26M_SEL	      118 /* Linux CLK ID (53) */
-+#define CK_TOP_PEXTP_P0_SEL	      119 /* Linux CLK ID (54) */
-+#define CK_TOP_PEXTP_P1_SEL	      120 /* Linux CLK ID (55) */
-+#define CK_TOP_PEXTP_P2_SEL	      121 /* Linux CLK ID (56) */
-+#define CK_TOP_PEXTP_P3_SEL	      122 /* Linux CLK ID (57) */
-+#define CK_TOP_DA_XTP_GLB_P0_SEL      123 /* Linux CLK ID (58) */
-+#define CK_TOP_DA_XTP_GLB_P1_SEL      124 /* Linux CLK ID (59) */
-+#define CK_TOP_DA_XTP_GLB_P2_SEL      125 /* Linux CLK ID (60) */
-+#define CK_TOP_DA_XTP_GLB_P3_SEL      126 /* Linux CLK ID (61) */
-+#define CK_TOP_CKM_SEL		      127 /* Linux CLK ID (62) */
-+#define CK_TOP_DA_SELM_XTAL_SEL	      128 /* Linux CLK ID (63) */
-+#define CK_TOP_PEXTP_SEL	      129 /* Linux CLK ID (64) */
-+#define CK_TOP_TOPS_P2_26M_SEL	      130 /* Linux CLK ID (65) */
-+#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
-+#define CK_TOP_NETSYS_SYNC_250M_SEL   132 /* Linux CLK ID (67) */
-+#define CK_TOP_MACSEC_SEL	      133 /* Linux CLK ID (68) */
-+#define CK_TOP_NETSYS_TOPS_400M_SEL   134 /* Linux CLK ID (69) */
-+#define CK_TOP_NETSYS_PPEFB_250M_SEL  135 /* Linux CLK ID (70) */
-+#define CK_TOP_NETSYS_WARP_SEL	      136 /* Linux CLK ID (71) */
-+#define CK_TOP_ETH_MII_SEL	      137 /* Linux CLK ID (72) */
-+#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
-+
-+/* APMIXEDSYS */
-+/* mtk_pll_data */
-+#define CK_APMIXED_NETSYSPLL  0
-+#define CK_APMIXED_MPLL	      1
-+#define CK_APMIXED_MMPLL      2
-+#define CK_APMIXED_APLL2      3
-+#define CK_APMIXED_NET1PLL    4
-+#define CK_APMIXED_NET2PLL    5
-+#define CK_APMIXED_WEDMCUPLL  6
-+#define CK_APMIXED_SGMPLL     7
-+#define CK_APMIXED_ARM_B      8
-+#define CK_APMIXED_CCIPLL2_B  9
-+#define CK_APMIXED_USXGMIIPLL 10
-+#define CK_APMIXED_MSDCPLL    11
-+
-+/* ETHSYS ETH DMA  */
-+/* mtk_gate */
-+#define CK_ETHDMA_FE_EN 0
-+
-+/* SGMIISYS_0 */
-+/* mtk_gate */
-+#define CK_SGM0_TX_EN 0
-+#define CK_SGM0_RX_EN 1
-+
-+/* SGMIISYS_1 */
-+/* mtk_gate */
-+#define CK_SGM1_TX_EN 0
-+#define CK_SGM1_RX_EN 1
-+
-+/* ETHWARP */
-+/* mtk_gate */
-+#define CK_ETHWARP_WOCPU2_EN 0
-+#define CK_ETHWARP_WOCPU1_EN 1
-+#define CK_ETHWARP_WOCPU0_EN 2
-+
-+#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch
deleted file mode 100644
index f14c383638..0000000000
--- a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:33 +0800
-Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek
- MT7988 SoC
-
-This patch adds reset bits for MediaTek MT7988
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++
- 1 file changed, 31 insertions(+)
- create mode 100644 include/dt-bindings/reset/mt7988-reset.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/mt7988-reset.h
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2023 MediaTek Inc.
-+ */
-+
-+#ifndef _DT_BINDINGS_MTK_RESET_H_
-+#define _DT_BINDINGS_MTK_RESET_H_
-+
-+/* ETHDMA Subsystem resets */
-+#define ETHDMA_FE_RST			6
-+#define ETHDMA_PMTR_RST			8
-+#define ETHDMA_GMAC_RST			23
-+#define ETHDMA_WDMA0_RST		24
-+#define ETHDMA_WDMA1_RST		25
-+#define ETHDMA_WDMA2_RST		26
-+#define ETHDMA_PPE0_RST			29
-+#define ETHDMA_PPE1_RST			30
-+#define ETHDMA_PPE2_RST			31
-+
-+/* ETHWARP Subsystem resets */
-+#define ETHWARP_GSW_RST			9
-+#define ETHWARP_EIP197_RST		10
-+#define ETHWARP_WOCPU0_RST		32
-+#define ETHWARP_WOCPU1_RST		33
-+#define ETHWARP_WOCPU2_RST		34
-+#define ETHWARP_WOX_NET_MUX_RST		35
-+#define ETHWARP_WED0_RST		36
-+#define ETHWARP_WED1_RST		37
-+#define ETHWARP_WED2_RST		38
-+
-+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch b/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch
deleted file mode 100644
index 4085f11541..0000000000
--- a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch
+++ /dev/null
@@ -1,2267 +0,0 @@
-From 30227fcf55ac95ad6778de2fc3e6d1e00cf82566 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:37 +0800
-Subject: [PATCH 12/29] pinctrl: mediatek: convert most definitions to const
-
-There exists a situation of the mediatek pinctrl driver that may return
-wrong pin function value for the pinmux driver:
-- All pin function arrays are defined without const
-- Some pin function arrays contain all-zero value, e.g.:
-  static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
-- These arrays will be put into .bss section during compilation
-- .bss section has no "a" attribute and does not exist in the final binary
-  file after objcopy.
-- FDT binary blob is appended to the u-boot binary, which occupies the
-  .bss section.
-- During board_f stage, .bss has not been initialized, and contains the
-  data of FDT, which is not full-zero data.
-- pinctrl driver is initialized in board_f stage, and it will get wrong
-  data if another driver is going to set default pinctrl.
-
-Since pinmux information and soc data are only meant to be read-only, thus
-should be declared as const. This will force all pinctrl data being put
-into .rodata section. Since .rodata has "a" attribute, even the all-zero
-data will be allocated and filled with correct value in to u-boot binary.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mt7622.c     | 474 ++++++-------
- drivers/pinctrl/mediatek/pinctrl-mt7623.c     | 650 +++++++++---------
- drivers/pinctrl/mediatek/pinctrl-mt7629.c     | 174 ++---
- drivers/pinctrl/mediatek/pinctrl-mt7981.c     | 270 ++++----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c     | 145 ++--
- drivers/pinctrl/mediatek/pinctrl-mt8512.c     |  24 +-
- drivers/pinctrl/mediatek/pinctrl-mt8516.c     |  18 +-
- drivers/pinctrl/mediatek/pinctrl-mt8518.c     |  20 +-
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c |   4 +-
- drivers/pinctrl/mediatek/pinctrl-mtk-common.h |   8 +-
- 10 files changed, 898 insertions(+), 889 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-@@ -233,283 +233,285 @@ static const struct mtk_pin_desc mt7622_
-  */
- 
- /* EMMC */
--static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
--static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_emmc_pins[] = {
-+	40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
-+static const int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
--static int mt7622_emmc_rst_pins[] = { 37, };
--static int mt7622_emmc_rst_funcs[] = { 1, };
-+static const int mt7622_emmc_rst_pins[] = { 37, };
-+static const int mt7622_emmc_rst_funcs[] = { 1, };
- 
- /* LED for EPHY */
--static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
--static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
--static int mt7622_ephy0_led_pins[] = { 86, };
--static int mt7622_ephy0_led_funcs[] = { 0, };
--static int mt7622_ephy1_led_pins[] = { 91, };
--static int mt7622_ephy1_led_funcs[] = { 2, };
--static int mt7622_ephy2_led_pins[] = { 92, };
--static int mt7622_ephy2_led_funcs[] = { 2, };
--static int mt7622_ephy3_led_pins[] = { 93, };
--static int mt7622_ephy3_led_funcs[] = { 2, };
--static int mt7622_ephy4_led_pins[] = { 94, };
--static int mt7622_ephy4_led_funcs[] = { 2, };
-+static const int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
-+static const int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
-+static const int mt7622_ephy0_led_pins[] = { 86, };
-+static const int mt7622_ephy0_led_funcs[] = { 0, };
-+static const int mt7622_ephy1_led_pins[] = { 91, };
-+static const int mt7622_ephy1_led_funcs[] = { 2, };
-+static const int mt7622_ephy2_led_pins[] = { 92, };
-+static const int mt7622_ephy2_led_funcs[] = { 2, };
-+static const int mt7622_ephy3_led_pins[] = { 93, };
-+static const int mt7622_ephy3_led_funcs[] = { 2, };
-+static const int mt7622_ephy4_led_pins[] = { 94, };
-+static const int mt7622_ephy4_led_funcs[] = { 2, };
- 
- /* Embedded Switch */
--static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
--				 62, 63, 64, 65, 66, 67, 68, 69, 70, };
--static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--				  0, 0, 0, 0, 0, 0, 0, 0, 0, };
--static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
--static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
--static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
--					  68, 69, 70, };
--static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
--					   0, 0, 0, };
-+static const int mt7622_esw_pins[] = {
-+	51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
-+	69, 70, };
-+static const int mt7622_esw_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-+static const int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
-+static const int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-+static const int mt7622_esw_p2_p3_p4_pins[] = {
-+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-+static const int mt7622_esw_p2_p3_p4_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- /* RGMII via ESW */
--static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
--					   67, 68, 69, 70, };
--static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--					    0, };
-+static const int mt7622_rgmii_via_esw_pins[] = {
-+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-+static const int mt7622_rgmii_via_esw_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- 
- /* RGMII via GMAC1 */
--static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
--					     67, 68, 69, 70, };
--static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
--					      2, };
-+static const int mt7622_rgmii_via_gmac1_pins[] = {
-+	59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-+static const int mt7622_rgmii_via_gmac1_funcs[] = {
-+	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
- /* RGMII via GMAC2 */
--static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
--					     33, 34, 35, 36, };
--static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--					      0, };
-+static const int mt7622_rgmii_via_gmac2_pins[] = {
-+	25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, };
-+static const int mt7622_rgmii_via_gmac2_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- 
- /* I2C */
--static int mt7622_i2c0_pins[] = { 14, 15, };
--static int mt7622_i2c0_funcs[] = { 0, 0, };
--static int mt7622_i2c1_0_pins[] = { 55, 56, };
--static int mt7622_i2c1_0_funcs[] = { 0, 0, };
--static int mt7622_i2c1_1_pins[] = { 73, 74, };
--static int mt7622_i2c1_1_funcs[] = { 3, 3, };
--static int mt7622_i2c1_2_pins[] = { 87, 88, };
--static int mt7622_i2c1_2_funcs[] = { 0, 0, };
--static int mt7622_i2c2_0_pins[] = { 57, 58, };
--static int mt7622_i2c2_0_funcs[] = { 0, 0, };
--static int mt7622_i2c2_1_pins[] = { 75, 76, };
--static int mt7622_i2c2_1_funcs[] = { 3, 3, };
--static int mt7622_i2c2_2_pins[] = { 89, 90, };
--static int mt7622_i2c2_2_funcs[] = { 0, 0, };
-+static const int mt7622_i2c0_pins[] = { 14, 15, };
-+static const int mt7622_i2c0_funcs[] = { 0, 0, };
-+static const int mt7622_i2c1_0_pins[] = { 55, 56, };
-+static const int mt7622_i2c1_0_funcs[] = { 0, 0, };
-+static const int mt7622_i2c1_1_pins[] = { 73, 74, };
-+static const int mt7622_i2c1_1_funcs[] = { 3, 3, };
-+static const int mt7622_i2c1_2_pins[] = { 87, 88, };
-+static const int mt7622_i2c1_2_funcs[] = { 0, 0, };
-+static const int mt7622_i2c2_0_pins[] = { 57, 58, };
-+static const int mt7622_i2c2_0_funcs[] = { 0, 0, };
-+static const int mt7622_i2c2_1_pins[] = { 75, 76, };
-+static const int mt7622_i2c2_1_funcs[] = { 3, 3, };
-+static const int mt7622_i2c2_2_pins[] = { 89, 90, };
-+static const int mt7622_i2c2_2_funcs[] = { 0, 0, };
- 
- /* I2S */
--static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
--static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
--static int mt7622_i2s1_in_data_pins[] = { 1, };
--static int mt7622_i2s1_in_data_funcs[] = { 0, };
--static int mt7622_i2s2_in_data_pins[] = { 16, };
--static int mt7622_i2s2_in_data_funcs[] = { 0, };
--static int mt7622_i2s3_in_data_pins[] = { 17, };
--static int mt7622_i2s3_in_data_funcs[] = { 0, };
--static int mt7622_i2s4_in_data_pins[] = { 18, };
--static int mt7622_i2s4_in_data_funcs[] = { 0, };
--static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
--static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
--static int mt7622_i2s1_out_data_pins[] = { 2, };
--static int mt7622_i2s1_out_data_funcs[] = { 0, };
--static int mt7622_i2s2_out_data_pins[] = { 19, };
--static int mt7622_i2s2_out_data_funcs[] = { 0, };
--static int mt7622_i2s3_out_data_pins[] = { 20, };
--static int mt7622_i2s3_out_data_funcs[] = { 0, };
--static int mt7622_i2s4_out_data_pins[] = { 21, };
--static int mt7622_i2s4_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-+static const int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
-+static const int mt7622_i2s1_in_data_pins[] = { 1, };
-+static const int mt7622_i2s1_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s2_in_data_pins[] = { 16, };
-+static const int mt7622_i2s2_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s3_in_data_pins[] = { 17, };
-+static const int mt7622_i2s3_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s4_in_data_pins[] = { 18, };
-+static const int mt7622_i2s4_in_data_funcs[] = { 0, };
-+static const int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-+static const int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
-+static const int mt7622_i2s1_out_data_pins[] = { 2, };
-+static const int mt7622_i2s1_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s2_out_data_pins[] = { 19, };
-+static const int mt7622_i2s2_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s3_out_data_pins[] = { 20, };
-+static const int mt7622_i2s3_out_data_funcs[] = { 0, };
-+static const int mt7622_i2s4_out_data_pins[] = { 21, };
-+static const int mt7622_i2s4_out_data_funcs[] = { 0, };
- 
- /* IR */
--static int mt7622_ir_0_tx_pins[] = { 16, };
--static int mt7622_ir_0_tx_funcs[] = { 4, };
--static int mt7622_ir_1_tx_pins[] = { 59, };
--static int mt7622_ir_1_tx_funcs[] = { 5, };
--static int mt7622_ir_2_tx_pins[] = { 99, };
--static int mt7622_ir_2_tx_funcs[] = { 3, };
--static int mt7622_ir_0_rx_pins[] = { 17, };
--static int mt7622_ir_0_rx_funcs[] = { 4, };
--static int mt7622_ir_1_rx_pins[] = { 60, };
--static int mt7622_ir_1_rx_funcs[] = { 5, };
--static int mt7622_ir_2_rx_pins[] = { 100, };
--static int mt7622_ir_2_rx_funcs[] = { 3, };
-+static const int mt7622_ir_0_tx_pins[] = { 16, };
-+static const int mt7622_ir_0_tx_funcs[] = { 4, };
-+static const int mt7622_ir_1_tx_pins[] = { 59, };
-+static const int mt7622_ir_1_tx_funcs[] = { 5, };
-+static const int mt7622_ir_2_tx_pins[] = { 99, };
-+static const int mt7622_ir_2_tx_funcs[] = { 3, };
-+static const int mt7622_ir_0_rx_pins[] = { 17, };
-+static const int mt7622_ir_0_rx_funcs[] = { 4, };
-+static const int mt7622_ir_1_rx_pins[] = { 60, };
-+static const int mt7622_ir_1_rx_funcs[] = { 5, };
-+static const int mt7622_ir_2_rx_pins[] = { 100, };
-+static const int mt7622_ir_2_rx_funcs[] = { 3, };
- 
- /* MDIO */
--static int mt7622_mdc_mdio_pins[] = { 23, 24, };
--static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
-+static const int mt7622_mdc_mdio_pins[] = { 23, 24, };
-+static const int mt7622_mdc_mdio_funcs[] = { 0, 0, };
- 
- /* PCIE */
--static int mt7622_pcie0_0_waken_pins[] = { 14, };
--static int mt7622_pcie0_0_waken_funcs[] = { 2, };
--static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
--static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
--static int mt7622_pcie0_1_waken_pins[] = { 79, };
--static int mt7622_pcie0_1_waken_funcs[] = { 4, };
--static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
--static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
--static int mt7622_pcie1_0_waken_pins[] = { 14, };
--static int mt7622_pcie1_0_waken_funcs[] = { 3, };
--static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
--static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
--
--static int mt7622_pcie0_pad_perst_pins[] = { 83, };
--static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
--static int mt7622_pcie1_pad_perst_pins[] = { 84, };
--static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
-+static const int mt7622_pcie0_0_waken_pins[] = { 14, };
-+static const int mt7622_pcie0_0_waken_funcs[] = { 2, };
-+static const int mt7622_pcie0_0_clkreq_pins[] = { 15, };
-+static const int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
-+static const int mt7622_pcie0_1_waken_pins[] = { 79, };
-+static const int mt7622_pcie0_1_waken_funcs[] = { 4, };
-+static const int mt7622_pcie0_1_clkreq_pins[] = { 80, };
-+static const int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
-+static const int mt7622_pcie1_0_waken_pins[] = { 14, };
-+static const int mt7622_pcie1_0_waken_funcs[] = { 3, };
-+static const int mt7622_pcie1_0_clkreq_pins[] = { 15, };
-+static const int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
-+
-+static const int mt7622_pcie0_pad_perst_pins[] = { 83, };
-+static const int mt7622_pcie0_pad_perst_funcs[] = { 0, };
-+static const int mt7622_pcie1_pad_perst_pins[] = { 84, };
-+static const int mt7622_pcie1_pad_perst_funcs[] = { 0, };
- 
- /* PMIC bus */
--static int mt7622_pmic_bus_pins[] = { 71, 72, };
--static int mt7622_pmic_bus_funcs[] = { 0, 0, };
-+static const int mt7622_pmic_bus_pins[] = { 71, 72, };
-+static const int mt7622_pmic_bus_funcs[] = { 0, 0, };
- 
- /* Parallel NAND */
--static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
--				   48, 49, 50, };
--static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--				    0, };
-+static const int mt7622_pnand_pins[] = {
-+	37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, };
-+static const int mt7622_pnand_funcs[] = {
-+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
- 
- /* PWM */
--static int mt7622_pwm_ch1_0_pins[] = { 51, };
--static int mt7622_pwm_ch1_0_funcs[] = { 3, };
--static int mt7622_pwm_ch1_1_pins[] = { 73, };
--static int mt7622_pwm_ch1_1_funcs[] = { 4, };
--static int mt7622_pwm_ch1_2_pins[] = { 95, };
--static int mt7622_pwm_ch1_2_funcs[] = { 0, };
--static int mt7622_pwm_ch2_0_pins[] = { 52, };
--static int mt7622_pwm_ch2_0_funcs[] = { 3, };
--static int mt7622_pwm_ch2_1_pins[] = { 74, };
--static int mt7622_pwm_ch2_1_funcs[] = { 4, };
--static int mt7622_pwm_ch2_2_pins[] = { 96, };
--static int mt7622_pwm_ch2_2_funcs[] = { 0, };
--static int mt7622_pwm_ch3_0_pins[] = { 53, };
--static int mt7622_pwm_ch3_0_funcs[] = { 3, };
--static int mt7622_pwm_ch3_1_pins[] = { 75, };
--static int mt7622_pwm_ch3_1_funcs[] = { 4, };
--static int mt7622_pwm_ch3_2_pins[] = { 97, };
--static int mt7622_pwm_ch3_2_funcs[] = { 0, };
--static int mt7622_pwm_ch4_0_pins[] = { 54, };
--static int mt7622_pwm_ch4_0_funcs[] = { 3, };
--static int mt7622_pwm_ch4_1_pins[] = { 67, };
--static int mt7622_pwm_ch4_1_funcs[] = { 3, };
--static int mt7622_pwm_ch4_2_pins[] = { 76, };
--static int mt7622_pwm_ch4_2_funcs[] = { 4, };
--static int mt7622_pwm_ch4_3_pins[] = { 98, };
--static int mt7622_pwm_ch4_3_funcs[] = { 0, };
--static int mt7622_pwm_ch5_0_pins[] = { 68, };
--static int mt7622_pwm_ch5_0_funcs[] = { 3, };
--static int mt7622_pwm_ch5_1_pins[] = { 77, };
--static int mt7622_pwm_ch5_1_funcs[] = { 4, };
--static int mt7622_pwm_ch5_2_pins[] = { 99, };
--static int mt7622_pwm_ch5_2_funcs[] = { 0, };
--static int mt7622_pwm_ch6_0_pins[] = { 69, };
--static int mt7622_pwm_ch6_0_funcs[] = { 3, };
--static int mt7622_pwm_ch6_1_pins[] = { 78, };
--static int mt7622_pwm_ch6_1_funcs[] = { 4, };
--static int mt7622_pwm_ch6_2_pins[] = { 81, };
--static int mt7622_pwm_ch6_2_funcs[] = { 4, };
--static int mt7622_pwm_ch6_3_pins[] = { 100, };
--static int mt7622_pwm_ch6_3_funcs[] = { 0, };
--static int mt7622_pwm_ch7_0_pins[] = { 70, };
--static int mt7622_pwm_ch7_0_funcs[] = { 3, };
--static int mt7622_pwm_ch7_1_pins[] = { 82, };
--static int mt7622_pwm_ch7_1_funcs[] = { 4, };
--static int mt7622_pwm_ch7_2_pins[] = { 101, };
--static int mt7622_pwm_ch7_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch1_0_pins[] = { 51, };
-+static const int mt7622_pwm_ch1_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch1_1_pins[] = { 73, };
-+static const int mt7622_pwm_ch1_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch1_2_pins[] = { 95, };
-+static const int mt7622_pwm_ch1_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch2_0_pins[] = { 52, };
-+static const int mt7622_pwm_ch2_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch2_1_pins[] = { 74, };
-+static const int mt7622_pwm_ch2_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch2_2_pins[] = { 96, };
-+static const int mt7622_pwm_ch2_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch3_0_pins[] = { 53, };
-+static const int mt7622_pwm_ch3_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch3_1_pins[] = { 75, };
-+static const int mt7622_pwm_ch3_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch3_2_pins[] = { 97, };
-+static const int mt7622_pwm_ch3_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch4_0_pins[] = { 54, };
-+static const int mt7622_pwm_ch4_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch4_1_pins[] = { 67, };
-+static const int mt7622_pwm_ch4_1_funcs[] = { 3, };
-+static const int mt7622_pwm_ch4_2_pins[] = { 76, };
-+static const int mt7622_pwm_ch4_2_funcs[] = { 4, };
-+static const int mt7622_pwm_ch4_3_pins[] = { 98, };
-+static const int mt7622_pwm_ch4_3_funcs[] = { 0, };
-+static const int mt7622_pwm_ch5_0_pins[] = { 68, };
-+static const int mt7622_pwm_ch5_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch5_1_pins[] = { 77, };
-+static const int mt7622_pwm_ch5_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch5_2_pins[] = { 99, };
-+static const int mt7622_pwm_ch5_2_funcs[] = { 0, };
-+static const int mt7622_pwm_ch6_0_pins[] = { 69, };
-+static const int mt7622_pwm_ch6_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch6_1_pins[] = { 78, };
-+static const int mt7622_pwm_ch6_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch6_2_pins[] = { 81, };
-+static const int mt7622_pwm_ch6_2_funcs[] = { 4, };
-+static const int mt7622_pwm_ch6_3_pins[] = { 100, };
-+static const int mt7622_pwm_ch6_3_funcs[] = { 0, };
-+static const int mt7622_pwm_ch7_0_pins[] = { 70, };
-+static const int mt7622_pwm_ch7_0_funcs[] = { 3, };
-+static const int mt7622_pwm_ch7_1_pins[] = { 82, };
-+static const int mt7622_pwm_ch7_1_funcs[] = { 4, };
-+static const int mt7622_pwm_ch7_2_pins[] = { 101, };
-+static const int mt7622_pwm_ch7_2_funcs[] = { 0, };
- 
- /* SD */
--static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
--static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
--static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
--static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
-+static const int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
-+static const int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
- 
- /* Serial NAND */
--static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
--static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+static const int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
-+static const int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
- 
- /* SPI NOR */
--static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
--static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
-+static const int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
-+static const int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
- 
- /* SPIC */
--static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
--static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
--static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
--static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
--static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
--static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
--static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
--static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
--static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
--static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
--static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
--static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
-+static const int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
-+static const int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
-+static const int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
-+static const int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
-+static const int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
-+static const int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
-+static const int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
-+static const int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
-+static const int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
- 
- /* TDM */
--static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
--static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
--static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_0_out_data_pins[] = { 20, };
--static int mt7622_tdm_0_out_data_funcs[] = { 3, };
--static int mt7622_tdm_0_in_data_pins[] = { 21, };
--static int mt7622_tdm_0_in_data_funcs[] = { 3, };
--static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
--static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
--static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
--static int mt7622_tdm_1_out_data_pins[] = { 55, };
--static int mt7622_tdm_1_out_data_funcs[] = { 3, };
--static int mt7622_tdm_1_in_data_pins[] = { 56, };
--static int mt7622_tdm_1_in_data_funcs[] = { 3, };
-+static const int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
-+static const int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
-+static const int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_0_out_data_pins[] = { 20, };
-+static const int mt7622_tdm_0_out_data_funcs[] = { 3, };
-+static const int mt7622_tdm_0_in_data_pins[] = { 21, };
-+static const int mt7622_tdm_0_in_data_funcs[] = { 3, };
-+static const int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
-+static const int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
-+static const int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static const int mt7622_tdm_1_out_data_pins[] = { 55, };
-+static const int mt7622_tdm_1_out_data_funcs[] = { 3, };
-+static const int mt7622_tdm_1_in_data_pins[] = { 56, };
-+static const int mt7622_tdm_1_in_data_funcs[] = { 3, };
- 
- /* UART */
--static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
--static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
--static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
--static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
--static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
--static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
--static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
--static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
--static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
--static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
--static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
--static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
--static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
--static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
--static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
--static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
--static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
--static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
--static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
--static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
--static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
--static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
--static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
--static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
--static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
--static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
--static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
--static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
--static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
--static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
--static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
--static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
--static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
--static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
-+static const int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
-+static const int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
-+static const int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
-+static const int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
-+static const int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
-+static const int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
-+static const int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
-+static const int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
-+static const int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
-+static const int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
-+static const int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
-+static const int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
-+static const int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
-+static const int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
-+static const int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
-+static const int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
-+static const int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
-+static const int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
-+static const int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
-+static const int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
-+static const int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
-+static const int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
-+static const int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
-+static const int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
-+static const int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
-+static const int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
-+static const int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
-+static const int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
-+static const int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
-+static const int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
-+static const int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
- 
- /* Watchdog */
--static int mt7622_watchdog_pins[] = { 78, };
--static int mt7622_watchdog_funcs[] = { 0, };
-+static const int mt7622_watchdog_pins[] = { 78, };
-+static const int mt7622_watchdog_funcs[] = { 0, };
- 
- /* WLAN LED */
--static int mt7622_wled_pins[] = { 85, };
--static int mt7622_wled_funcs[] = { 0, };
-+static const int mt7622_wled_pins[] = { 85, };
-+static const int mt7622_wled_funcs[] = { 0, };
- 
- static const struct mtk_group_desc mt7622_groups[] = {
- 	PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
-@@ -719,7 +721,7 @@ static const struct mtk_function_desc mt
- 	{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7622_data = {
-+static const struct mtk_pinctrl_soc mt7622_data = {
- 	.name = "mt7622_pinctrl",
- 	.reg_cal = mt7622_reg_cals,
- 	.pins = mt7622_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-@@ -692,377 +692,377 @@ static const struct mtk_pin_desc mt7623_
-  */
- 
- /* AUDIO EXT CLK */
--static int mt7623_aud_ext_clk0_pins[] = { 208, };
--static int mt7623_aud_ext_clk0_funcs[] = { 1, };
--static int mt7623_aud_ext_clk1_pins[] = { 209, };
--static int mt7623_aud_ext_clk1_funcs[] = { 1, };
-+static const int mt7623_aud_ext_clk0_pins[] = { 208, };
-+static const int mt7623_aud_ext_clk0_funcs[] = { 1, };
-+static const int mt7623_aud_ext_clk1_pins[] = { 209, };
-+static const int mt7623_aud_ext_clk1_funcs[] = { 1, };
- 
- /* DISP PWM */
--static int mt7623_disp_pwm_0_pins[] = { 72, };
--static int mt7623_disp_pwm_0_funcs[] = { 5, };
--static int mt7623_disp_pwm_1_pins[] = { 203, };
--static int mt7623_disp_pwm_1_funcs[] = { 2, };
--static int mt7623_disp_pwm_2_pins[] = { 208, };
--static int mt7623_disp_pwm_2_funcs[] = { 5, };
-+static const int mt7623_disp_pwm_0_pins[] = { 72, };
-+static const int mt7623_disp_pwm_0_funcs[] = { 5, };
-+static const int mt7623_disp_pwm_1_pins[] = { 203, };
-+static const int mt7623_disp_pwm_1_funcs[] = { 2, };
-+static const int mt7623_disp_pwm_2_pins[] = { 208, };
-+static const int mt7623_disp_pwm_2_funcs[] = { 5, };
- 
- /* ESW */
--static int mt7623_esw_int_pins[] = { 273, };
--static int mt7623_esw_int_funcs[] = { 1, };
--static int mt7623_esw_rst_pins[] = { 277, };
--static int mt7623_esw_rst_funcs[] = { 1, };
-+static const int mt7623_esw_int_pins[] = { 273, };
-+static const int mt7623_esw_int_funcs[] = { 1, };
-+static const int mt7623_esw_rst_pins[] = { 277, };
-+static const int mt7623_esw_rst_funcs[] = { 1, };
- 
- /* EPHY */
--static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
--				  269, 270, 271, 272, 274, };
--static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
-+					269, 270, 271, 272, 274, };
-+static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* EXT_SDIO */
--static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
--static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
-+static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
- 
- /* HDMI RX */
--static int mt7623_hdmi_rx_pins[] = { 247, 248, };
--static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
--static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
--static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
-+static const int mt7623_hdmi_rx_pins[] = { 247, 248, };
-+static const int mt7623_hdmi_rx_funcs[] = { 1, 1 };
-+static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
-+static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
- 
- /* HDMI TX */
--static int mt7623_hdmi_cec_pins[] = { 122, };
--static int mt7623_hdmi_cec_funcs[] = { 1, };
--static int mt7623_hdmi_htplg_pins[] = { 123, };
--static int mt7623_hdmi_htplg_funcs[] = { 1, };
--static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
--static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
-+static const int mt7623_hdmi_cec_pins[] = { 122, };
-+static const int mt7623_hdmi_cec_funcs[] = { 1, };
-+static const int mt7623_hdmi_htplg_pins[] = { 123, };
-+static const int mt7623_hdmi_htplg_funcs[] = { 1, };
-+static const int mt7623_hdmi_i2c_pins[] = { 124, 125, };
-+static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
- 
- /* I2C */
--static int mt7623_i2c0_pins[] = { 75, 76, };
--static int mt7623_i2c0_funcs[] = { 1, 1, };
--static int mt7623_i2c1_0_pins[] = { 57, 58, };
--static int mt7623_i2c1_0_funcs[] = { 1, 1, };
--static int mt7623_i2c1_1_pins[] = { 242, 243, };
--static int mt7623_i2c1_1_funcs[] = { 4, 4, };
--static int mt7623_i2c1_2_pins[] = { 85, 86, };
--static int mt7623_i2c1_2_funcs[] = { 3, 3, };
--static int mt7623_i2c1_3_pins[] = { 105, 106, };
--static int mt7623_i2c1_3_funcs[] = { 3, 3, };
--static int mt7623_i2c1_4_pins[] = { 124, 125, };
--static int mt7623_i2c1_4_funcs[] = { 4, 4, };
--static int mt7623_i2c2_0_pins[] = { 77, 78, };
--static int mt7623_i2c2_0_funcs[] = { 1, 1, };
--static int mt7623_i2c2_1_pins[] = { 89, 90, };
--static int mt7623_i2c2_1_funcs[] = { 3, 3, };
--static int mt7623_i2c2_2_pins[] = { 109, 110, };
--static int mt7623_i2c2_2_funcs[] = { 3, 3, };
--static int mt7623_i2c2_3_pins[] = { 122, 123, };
--static int mt7623_i2c2_3_funcs[] = { 4, 4, };
-+static const int mt7623_i2c0_pins[] = { 75, 76, };
-+static const int mt7623_i2c0_funcs[] = { 1, 1, };
-+static const int mt7623_i2c1_0_pins[] = { 57, 58, };
-+static const int mt7623_i2c1_0_funcs[] = { 1, 1, };
-+static const int mt7623_i2c1_1_pins[] = { 242, 243, };
-+static const int mt7623_i2c1_1_funcs[] = { 4, 4, };
-+static const int mt7623_i2c1_2_pins[] = { 85, 86, };
-+static const int mt7623_i2c1_2_funcs[] = { 3, 3, };
-+static const int mt7623_i2c1_3_pins[] = { 105, 106, };
-+static const int mt7623_i2c1_3_funcs[] = { 3, 3, };
-+static const int mt7623_i2c1_4_pins[] = { 124, 125, };
-+static const int mt7623_i2c1_4_funcs[] = { 4, 4, };
-+static const int mt7623_i2c2_0_pins[] = { 77, 78, };
-+static const int mt7623_i2c2_0_funcs[] = { 1, 1, };
-+static const int mt7623_i2c2_1_pins[] = { 89, 90, };
-+static const int mt7623_i2c2_1_funcs[] = { 3, 3, };
-+static const int mt7623_i2c2_2_pins[] = { 109, 110, };
-+static const int mt7623_i2c2_2_funcs[] = { 3, 3, };
-+static const int mt7623_i2c2_3_pins[] = { 122, 123, };
-+static const int mt7623_i2c2_3_funcs[] = { 4, 4, };
- 
- /* I2S */
--static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
--static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
--static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
--static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
--static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
--static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
--static int mt7623_i2s2_data_in_pins[] = { 51, };
--static int mt7623_i2s2_data_in_funcs[] = { 1, };
--static int mt7623_i2s2_data_0_pins[] = { 203, };
--static int mt7623_i2s2_data_0_funcs[] = { 9, };
--static int mt7623_i2s2_data_1_pins[] = { 38,  };
--static int mt7623_i2s2_data_1_funcs[] = { 4, };
--static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
--static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
--static int mt7623_i2s3_data_in_pins[] = { 190, };
--static int mt7623_i2s3_data_in_funcs[] = { 1, };
--static int mt7623_i2s3_data_0_pins[] = { 204, };
--static int mt7623_i2s3_data_0_funcs[] = { 9, };
--static int mt7623_i2s3_data_1_pins[] = { 2, };
--static int mt7623_i2s3_data_1_funcs[] = { 0, };
--static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
--static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
--static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
--static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
-+static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
-+static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
-+static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-+static const int mt7623_i2s2_data_in_pins[] = { 51, };
-+static const int mt7623_i2s2_data_in_funcs[] = { 1, };
-+static const int mt7623_i2s2_data_0_pins[] = { 203, };
-+static const int mt7623_i2s2_data_0_funcs[] = { 9, };
-+static const int mt7623_i2s2_data_1_pins[] = { 38,  };
-+static const int mt7623_i2s2_data_1_funcs[] = { 4, };
-+static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
-+static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
-+static const int mt7623_i2s3_data_in_pins[] = { 190, };
-+static const int mt7623_i2s3_data_in_funcs[] = { 1, };
-+static const int mt7623_i2s3_data_0_pins[] = { 204, };
-+static const int mt7623_i2s3_data_0_funcs[] = { 9, };
-+static const int mt7623_i2s3_data_1_pins[] = { 2, };
-+static const int mt7623_i2s3_data_1_funcs[] = { 0, };
-+static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
-+static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
-+static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
- 
- /* IR */
--static int mt7623_ir_pins[] = { 46, };
--static int mt7623_ir_funcs[] = { 1, };
-+static const int mt7623_ir_pins[] = { 46, };
-+static const int mt7623_ir_funcs[] = { 1, };
- 
- /* LCD */
--static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
--				     99, 100, };
--static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
--static int mt7623_dsi_te_pins[] = { 84, };
--static int mt7623_dsi_te_funcs[] = { 1, };
--static int mt7623_lcm_rst_pins[] = { 83, };
--static int mt7623_lcm_rst_funcs[] = { 1, };
-+static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
-+					   99, 100, };
-+static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_dsi_te_pins[] = { 84, };
-+static const int mt7623_dsi_te_funcs[] = { 1, };
-+static const int mt7623_lcm_rst_pins[] = { 83, };
-+static const int mt7623_lcm_rst_funcs[] = { 1, };
- 
- /* MDC/MDIO */
--static int mt7623_mdc_mdio_pins[] = { 275, 276, };
--static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7623_mdc_mdio_pins[] = { 275, 276, };
-+static const int mt7623_mdc_mdio_funcs[] = { 1, 1, };
- 
- /* MSDC */
--static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
--				   119, 120, 121, };
--static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
--static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
--static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
--static int mt7623_msdc1_ins_pins[] = { 261, };
--static int mt7623_msdc1_ins_funcs[] = { 1, };
--static int mt7623_msdc1_wp_0_pins[] = { 29, };
--static int mt7623_msdc1_wp_0_funcs[] = { 1, };
--static int mt7623_msdc1_wp_1_pins[] = { 55, };
--static int mt7623_msdc1_wp_1_funcs[] = { 3, };
--static int mt7623_msdc1_wp_2_pins[] = { 209, };
--static int mt7623_msdc1_wp_2_funcs[] = { 2, };
--static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
--static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
--static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
--				   257, 258, 259, 260, };
--static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
-+					 119, 120, 121, };
-+static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
-+static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc1_ins_pins[] = { 261, };
-+static const int mt7623_msdc1_ins_funcs[] = { 1, };
-+static const int mt7623_msdc1_wp_0_pins[] = { 29, };
-+static const int mt7623_msdc1_wp_0_funcs[] = { 1, };
-+static const int mt7623_msdc1_wp_1_pins[] = { 55, };
-+static const int mt7623_msdc1_wp_1_funcs[] = { 3, };
-+static const int mt7623_msdc1_wp_2_pins[] = { 209, };
-+static const int mt7623_msdc1_wp_2_funcs[] = { 2, };
-+static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
-+static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
-+					 257, 258, 259, 260, };
-+static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* NAND */
--static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
--				   116, 117, 118, 119, 120, 121, };
--static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
--				   4, 4, };
--static int mt7623_nandc_ceb0_pins[] = { 45, };
--static int mt7623_nandc_ceb0_funcs[] = { 1, };
--static int mt7623_nandc_ceb1_pins[] = { 44, };
--static int mt7623_nandc_ceb1_funcs[] = { 1, };
-+static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
-+					 116, 117, 118, 119, 120, 121, };
-+static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-+					  4, 4, };
-+static const int mt7623_nandc_ceb0_pins[] = { 45, };
-+static const int mt7623_nandc_ceb0_funcs[] = { 1, };
-+static const int mt7623_nandc_ceb1_pins[] = { 44, };
-+static const int mt7623_nandc_ceb1_funcs[] = { 1, };
- 
- /* RTC */
--static int mt7623_rtc_pins[] = { 10, };
--static int mt7623_rtc_funcs[] = { 1, };
-+static const int mt7623_rtc_pins[] = { 10, };
-+static const int mt7623_rtc_funcs[] = { 1, };
- 
- /* OTG */
--static int mt7623_otg_iddig0_0_pins[] = { 29, };
--static int mt7623_otg_iddig0_0_funcs[] = { 1, };
--static int mt7623_otg_iddig0_1_pins[] = { 44, };
--static int mt7623_otg_iddig0_1_funcs[] = { 2, };
--static int mt7623_otg_iddig0_2_pins[] = { 236, };
--static int mt7623_otg_iddig0_2_funcs[] = { 2, };
--static int mt7623_otg_iddig1_0_pins[] = { 27, };
--static int mt7623_otg_iddig1_0_funcs[] = { 2, };
--static int mt7623_otg_iddig1_1_pins[] = { 47, };
--static int mt7623_otg_iddig1_1_funcs[] = { 2, };
--static int mt7623_otg_iddig1_2_pins[] = { 238, };
--static int mt7623_otg_iddig1_2_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
--static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
--static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
--static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
--static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
--static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
--static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
--static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
--static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
-+static const int mt7623_otg_iddig0_0_pins[] = { 29, };
-+static const int mt7623_otg_iddig0_0_funcs[] = { 1, };
-+static const int mt7623_otg_iddig0_1_pins[] = { 44, };
-+static const int mt7623_otg_iddig0_1_funcs[] = { 2, };
-+static const int mt7623_otg_iddig0_2_pins[] = { 236, };
-+static const int mt7623_otg_iddig0_2_funcs[] = { 2, };
-+static const int mt7623_otg_iddig1_0_pins[] = { 27, };
-+static const int mt7623_otg_iddig1_0_funcs[] = { 2, };
-+static const int mt7623_otg_iddig1_1_pins[] = { 47, };
-+static const int mt7623_otg_iddig1_1_funcs[] = { 2, };
-+static const int mt7623_otg_iddig1_2_pins[] = { 238, };
-+static const int mt7623_otg_iddig1_2_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
-+static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
-+static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
-+static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
-+static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
-+static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
-+static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
-+static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
-+static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
- 
- /* PCIE */
--static int mt7623_pcie0_0_perst_pins[] = { 208, };
--static int mt7623_pcie0_0_perst_funcs[] = { 3, };
--static int mt7623_pcie0_1_perst_pins[] = { 22, };
--static int mt7623_pcie0_1_perst_funcs[] = { 2, };
--static int mt7623_pcie1_0_perst_pins[] = { 209, };
--static int mt7623_pcie1_0_perst_funcs[] = { 3, };
--static int mt7623_pcie1_1_perst_pins[] = { 23, };
--static int mt7623_pcie1_1_perst_funcs[] = { 2, };
--static int mt7623_pcie2_0_perst_pins[] = { 24, };
--static int mt7623_pcie2_0_perst_funcs[] = { 2, };
--static int mt7623_pcie2_1_perst_pins[] = { 29, };
--static int mt7623_pcie2_1_perst_funcs[] = { 6, };
--static int mt7623_pcie0_0_wake_pins[] = { 28, };
--static int mt7623_pcie0_0_wake_funcs[] = { 6, };
--static int mt7623_pcie0_1_wake_pins[] = { 251, };
--static int mt7623_pcie0_1_wake_funcs[] = { 6, };
--static int mt7623_pcie1_0_wake_pins[] = { 27, };
--static int mt7623_pcie1_0_wake_funcs[] = { 6, };
--static int mt7623_pcie1_1_wake_pins[] = { 253, };
--static int mt7623_pcie1_1_wake_funcs[] = { 6, };
--static int mt7623_pcie2_0_wake_pins[] = { 26, };
--static int mt7623_pcie2_0_wake_funcs[] = { 6, };
--static int mt7623_pcie2_1_wake_pins[] = { 255, };
--static int mt7623_pcie2_1_wake_funcs[] = { 6, };
--static int mt7623_pcie0_clkreq_pins[] = { 250, };
--static int mt7623_pcie0_clkreq_funcs[] = { 6, };
--static int mt7623_pcie1_clkreq_pins[] = { 252, };
--static int mt7623_pcie1_clkreq_funcs[] = { 6, };
--static int mt7623_pcie2_clkreq_pins[] = { 254, };
--static int mt7623_pcie2_clkreq_funcs[] = { 6, };
-+static const int mt7623_pcie0_0_perst_pins[] = { 208, };
-+static const int mt7623_pcie0_0_perst_funcs[] = { 3, };
-+static const int mt7623_pcie0_1_perst_pins[] = { 22, };
-+static const int mt7623_pcie0_1_perst_funcs[] = { 2, };
-+static const int mt7623_pcie1_0_perst_pins[] = { 209, };
-+static const int mt7623_pcie1_0_perst_funcs[] = { 3, };
-+static const int mt7623_pcie1_1_perst_pins[] = { 23, };
-+static const int mt7623_pcie1_1_perst_funcs[] = { 2, };
-+static const int mt7623_pcie2_0_perst_pins[] = { 24, };
-+static const int mt7623_pcie2_0_perst_funcs[] = { 2, };
-+static const int mt7623_pcie2_1_perst_pins[] = { 29, };
-+static const int mt7623_pcie2_1_perst_funcs[] = { 6, };
-+static const int mt7623_pcie0_0_wake_pins[] = { 28, };
-+static const int mt7623_pcie0_0_wake_funcs[] = { 6, };
-+static const int mt7623_pcie0_1_wake_pins[] = { 251, };
-+static const int mt7623_pcie0_1_wake_funcs[] = { 6, };
-+static const int mt7623_pcie1_0_wake_pins[] = { 27, };
-+static const int mt7623_pcie1_0_wake_funcs[] = { 6, };
-+static const int mt7623_pcie1_1_wake_pins[] = { 253, };
-+static const int mt7623_pcie1_1_wake_funcs[] = { 6, };
-+static const int mt7623_pcie2_0_wake_pins[] = { 26, };
-+static const int mt7623_pcie2_0_wake_funcs[] = { 6, };
-+static const int mt7623_pcie2_1_wake_pins[] = { 255, };
-+static const int mt7623_pcie2_1_wake_funcs[] = { 6, };
-+static const int mt7623_pcie0_clkreq_pins[] = { 250, };
-+static const int mt7623_pcie0_clkreq_funcs[] = { 6, };
-+static const int mt7623_pcie1_clkreq_pins[] = { 252, };
-+static const int mt7623_pcie1_clkreq_funcs[] = { 6, };
-+static const int mt7623_pcie2_clkreq_pins[] = { 254, };
-+static const int mt7623_pcie2_clkreq_funcs[] = { 6, };
- /* the pcie_*_rev are only used for MT7623 */
--static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
--static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
--static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
--static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
--static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
--static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
--static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
--static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
--static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
--static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
--static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
--static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
-+static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
-+static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
-+static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
-+static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
-+static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
-+static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
-+static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
-+static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
-+static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
-+static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
-+static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
-+static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
- 
- /* PCM */
--static int mt7623_pcm_clk_0_pins[] = { 18, };
--static int mt7623_pcm_clk_0_funcs[] = { 1, };
--static int mt7623_pcm_clk_1_pins[] = { 17, };
--static int mt7623_pcm_clk_1_funcs[] = { 3, };
--static int mt7623_pcm_clk_2_pins[] = { 35, };
--static int mt7623_pcm_clk_2_funcs[] = { 3, };
--static int mt7623_pcm_clk_3_pins[] = { 50, };
--static int mt7623_pcm_clk_3_funcs[] = { 3, };
--static int mt7623_pcm_clk_4_pins[] = { 74, };
--static int mt7623_pcm_clk_4_funcs[] = { 3, };
--static int mt7623_pcm_clk_5_pins[] = { 191, };
--static int mt7623_pcm_clk_5_funcs[] = { 3, };
--static int mt7623_pcm_clk_6_pins[] = { 196, };
--static int mt7623_pcm_clk_6_funcs[] = { 3, };
--static int mt7623_pcm_sync_0_pins[] = { 19, };
--static int mt7623_pcm_sync_0_funcs[] = { 1, };
--static int mt7623_pcm_sync_1_pins[] = { 30, };
--static int mt7623_pcm_sync_1_funcs[] = { 3, };
--static int mt7623_pcm_sync_2_pins[] = { 36, };
--static int mt7623_pcm_sync_2_funcs[] = { 3, };
--static int mt7623_pcm_sync_3_pins[] = { 52, };
--static int mt7623_pcm_sync_3_funcs[] = { 31, };
--static int mt7623_pcm_sync_4_pins[] = { 73, };
--static int mt7623_pcm_sync_4_funcs[] = { 3, };
--static int mt7623_pcm_sync_5_pins[] = { 192, };
--static int mt7623_pcm_sync_5_funcs[] = { 3, };
--static int mt7623_pcm_sync_6_pins[] = { 197, };
--static int mt7623_pcm_sync_6_funcs[] = { 3, };
--static int mt7623_pcm_rx_0_pins[] = { 20, };
--static int mt7623_pcm_rx_0_funcs[] = { 1, };
--static int mt7623_pcm_rx_1_pins[] = { 16, };
--static int mt7623_pcm_rx_1_funcs[] = { 3, };
--static int mt7623_pcm_rx_2_pins[] = { 34, };
--static int mt7623_pcm_rx_2_funcs[] = { 3, };
--static int mt7623_pcm_rx_3_pins[] = { 51, };
--static int mt7623_pcm_rx_3_funcs[] = { 3, };
--static int mt7623_pcm_rx_4_pins[] = { 72, };
--static int mt7623_pcm_rx_4_funcs[] = { 3, };
--static int mt7623_pcm_rx_5_pins[] = { 190, };
--static int mt7623_pcm_rx_5_funcs[] = { 3, };
--static int mt7623_pcm_rx_6_pins[] = { 195, };
--static int mt7623_pcm_rx_6_funcs[] = { 3, };
--static int mt7623_pcm_tx_0_pins[] = { 21, };
--static int mt7623_pcm_tx_0_funcs[] = { 1, };
--static int mt7623_pcm_tx_1_pins[] = { 32, };
--static int mt7623_pcm_tx_1_funcs[] = { 3, };
--static int mt7623_pcm_tx_2_pins[] = { 33, };
--static int mt7623_pcm_tx_2_funcs[] = { 3, };
--static int mt7623_pcm_tx_3_pins[] = { 38, };
--static int mt7623_pcm_tx_3_funcs[] = { 3, };
--static int mt7623_pcm_tx_4_pins[] = { 49, };
--static int mt7623_pcm_tx_4_funcs[] = { 3, };
--static int mt7623_pcm_tx_5_pins[] = { 189, };
--static int mt7623_pcm_tx_5_funcs[] = { 3, };
--static int mt7623_pcm_tx_6_pins[] = { 194, };
--static int mt7623_pcm_tx_6_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_0_pins[] = { 18, };
-+static const int mt7623_pcm_clk_0_funcs[] = { 1, };
-+static const int mt7623_pcm_clk_1_pins[] = { 17, };
-+static const int mt7623_pcm_clk_1_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_2_pins[] = { 35, };
-+static const int mt7623_pcm_clk_2_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_3_pins[] = { 50, };
-+static const int mt7623_pcm_clk_3_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_4_pins[] = { 74, };
-+static const int mt7623_pcm_clk_4_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_5_pins[] = { 191, };
-+static const int mt7623_pcm_clk_5_funcs[] = { 3, };
-+static const int mt7623_pcm_clk_6_pins[] = { 196, };
-+static const int mt7623_pcm_clk_6_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_0_pins[] = { 19, };
-+static const int mt7623_pcm_sync_0_funcs[] = { 1, };
-+static const int mt7623_pcm_sync_1_pins[] = { 30, };
-+static const int mt7623_pcm_sync_1_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_2_pins[] = { 36, };
-+static const int mt7623_pcm_sync_2_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_3_pins[] = { 52, };
-+static const int mt7623_pcm_sync_3_funcs[] = { 31, };
-+static const int mt7623_pcm_sync_4_pins[] = { 73, };
-+static const int mt7623_pcm_sync_4_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_5_pins[] = { 192, };
-+static const int mt7623_pcm_sync_5_funcs[] = { 3, };
-+static const int mt7623_pcm_sync_6_pins[] = { 197, };
-+static const int mt7623_pcm_sync_6_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_0_pins[] = { 20, };
-+static const int mt7623_pcm_rx_0_funcs[] = { 1, };
-+static const int mt7623_pcm_rx_1_pins[] = { 16, };
-+static const int mt7623_pcm_rx_1_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_2_pins[] = { 34, };
-+static const int mt7623_pcm_rx_2_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_3_pins[] = { 51, };
-+static const int mt7623_pcm_rx_3_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_4_pins[] = { 72, };
-+static const int mt7623_pcm_rx_4_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_5_pins[] = { 190, };
-+static const int mt7623_pcm_rx_5_funcs[] = { 3, };
-+static const int mt7623_pcm_rx_6_pins[] = { 195, };
-+static const int mt7623_pcm_rx_6_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_0_pins[] = { 21, };
-+static const int mt7623_pcm_tx_0_funcs[] = { 1, };
-+static const int mt7623_pcm_tx_1_pins[] = { 32, };
-+static const int mt7623_pcm_tx_1_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_2_pins[] = { 33, };
-+static const int mt7623_pcm_tx_2_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_3_pins[] = { 38, };
-+static const int mt7623_pcm_tx_3_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_4_pins[] = { 49, };
-+static const int mt7623_pcm_tx_4_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_5_pins[] = { 189, };
-+static const int mt7623_pcm_tx_5_funcs[] = { 3, };
-+static const int mt7623_pcm_tx_6_pins[] = { 194, };
-+static const int mt7623_pcm_tx_6_funcs[] = { 3, };
- 
- /* PWM */
--static int mt7623_pwm_ch1_0_pins[] = { 203, };
--static int mt7623_pwm_ch1_0_funcs[] = { 1, };
--static int mt7623_pwm_ch1_1_pins[] = { 208, };
--static int mt7623_pwm_ch1_1_funcs[] = { 2, };
--static int mt7623_pwm_ch1_2_pins[] = { 72, };
--static int mt7623_pwm_ch1_2_funcs[] = { 4, };
--static int mt7623_pwm_ch1_3_pins[] = { 88, };
--static int mt7623_pwm_ch1_3_funcs[] = { 3, };
--static int mt7623_pwm_ch1_4_pins[] = { 108, };
--static int mt7623_pwm_ch1_4_funcs[] = { 3, };
--static int mt7623_pwm_ch2_0_pins[] = { 204, };
--static int mt7623_pwm_ch2_0_funcs[] = { 1, };
--static int mt7623_pwm_ch2_1_pins[] = { 53, };
--static int mt7623_pwm_ch2_1_funcs[] = { 5, };
--static int mt7623_pwm_ch2_2_pins[] = { 88, };
--static int mt7623_pwm_ch2_2_funcs[] = { 6, };
--static int mt7623_pwm_ch2_3_pins[] = { 108, };
--static int mt7623_pwm_ch2_3_funcs[] = { 6, };
--static int mt7623_pwm_ch2_4_pins[] = { 209, };
--static int mt7623_pwm_ch2_4_funcs[] = { 5, };
--static int mt7623_pwm_ch3_0_pins[] = { 205, };
--static int mt7623_pwm_ch3_0_funcs[] = { 1, };
--static int mt7623_pwm_ch3_1_pins[] = { 55, };
--static int mt7623_pwm_ch3_1_funcs[] = { 5, };
--static int mt7623_pwm_ch3_2_pins[] = { 89, };
--static int mt7623_pwm_ch3_2_funcs[] = { 6, };
--static int mt7623_pwm_ch3_3_pins[] = { 109, };
--static int mt7623_pwm_ch3_3_funcs[] = { 6, };
--static int mt7623_pwm_ch4_0_pins[] = { 206, };
--static int mt7623_pwm_ch4_0_funcs[] = { 1, };
--static int mt7623_pwm_ch4_1_pins[] = { 90, };
--static int mt7623_pwm_ch4_1_funcs[] = { 6, };
--static int mt7623_pwm_ch4_2_pins[] = { 110, };
--static int mt7623_pwm_ch4_2_funcs[] = { 6, };
--static int mt7623_pwm_ch4_3_pins[] = { 124, };
--static int mt7623_pwm_ch4_3_funcs[] = { 5, };
--static int mt7623_pwm_ch5_0_pins[] = { 207, };
--static int mt7623_pwm_ch5_0_funcs[] = { 1, };
--static int mt7623_pwm_ch5_1_pins[] = { 125, };
--static int mt7623_pwm_ch5_1_funcs[] = { 5, };
-+static const int mt7623_pwm_ch1_0_pins[] = { 203, };
-+static const int mt7623_pwm_ch1_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch1_1_pins[] = { 208, };
-+static const int mt7623_pwm_ch1_1_funcs[] = { 2, };
-+static const int mt7623_pwm_ch1_2_pins[] = { 72, };
-+static const int mt7623_pwm_ch1_2_funcs[] = { 4, };
-+static const int mt7623_pwm_ch1_3_pins[] = { 88, };
-+static const int mt7623_pwm_ch1_3_funcs[] = { 3, };
-+static const int mt7623_pwm_ch1_4_pins[] = { 108, };
-+static const int mt7623_pwm_ch1_4_funcs[] = { 3, };
-+static const int mt7623_pwm_ch2_0_pins[] = { 204, };
-+static const int mt7623_pwm_ch2_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch2_1_pins[] = { 53, };
-+static const int mt7623_pwm_ch2_1_funcs[] = { 5, };
-+static const int mt7623_pwm_ch2_2_pins[] = { 88, };
-+static const int mt7623_pwm_ch2_2_funcs[] = { 6, };
-+static const int mt7623_pwm_ch2_3_pins[] = { 108, };
-+static const int mt7623_pwm_ch2_3_funcs[] = { 6, };
-+static const int mt7623_pwm_ch2_4_pins[] = { 209, };
-+static const int mt7623_pwm_ch2_4_funcs[] = { 5, };
-+static const int mt7623_pwm_ch3_0_pins[] = { 205, };
-+static const int mt7623_pwm_ch3_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch3_1_pins[] = { 55, };
-+static const int mt7623_pwm_ch3_1_funcs[] = { 5, };
-+static const int mt7623_pwm_ch3_2_pins[] = { 89, };
-+static const int mt7623_pwm_ch3_2_funcs[] = { 6, };
-+static const int mt7623_pwm_ch3_3_pins[] = { 109, };
-+static const int mt7623_pwm_ch3_3_funcs[] = { 6, };
-+static const int mt7623_pwm_ch4_0_pins[] = { 206, };
-+static const int mt7623_pwm_ch4_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch4_1_pins[] = { 90, };
-+static const int mt7623_pwm_ch4_1_funcs[] = { 6, };
-+static const int mt7623_pwm_ch4_2_pins[] = { 110, };
-+static const int mt7623_pwm_ch4_2_funcs[] = { 6, };
-+static const int mt7623_pwm_ch4_3_pins[] = { 124, };
-+static const int mt7623_pwm_ch4_3_funcs[] = { 5, };
-+static const int mt7623_pwm_ch5_0_pins[] = { 207, };
-+static const int mt7623_pwm_ch5_0_funcs[] = { 1, };
-+static const int mt7623_pwm_ch5_1_pins[] = { 125, };
-+static const int mt7623_pwm_ch5_1_funcs[] = { 5, };
- 
- /* PWRAP */
--static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
--static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
-+static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
- 
- /* SPDIF */
--static int mt7623_spdif_in0_0_pins[] = { 56, };
--static int mt7623_spdif_in0_0_funcs[] = { 3, };
--static int mt7623_spdif_in0_1_pins[] = { 201, };
--static int mt7623_spdif_in0_1_funcs[] = { 1, };
--static int mt7623_spdif_in1_0_pins[] = { 54, };
--static int mt7623_spdif_in1_0_funcs[] = { 3, };
--static int mt7623_spdif_in1_1_pins[] = { 202, };
--static int mt7623_spdif_in1_1_funcs[] = { 1, };
--static int mt7623_spdif_out_pins[] = { 202, };
--static int mt7623_spdif_out_funcs[] = { 1, };
-+static const int mt7623_spdif_in0_0_pins[] = { 56, };
-+static const int mt7623_spdif_in0_0_funcs[] = { 3, };
-+static const int mt7623_spdif_in0_1_pins[] = { 201, };
-+static const int mt7623_spdif_in0_1_funcs[] = { 1, };
-+static const int mt7623_spdif_in1_0_pins[] = { 54, };
-+static const int mt7623_spdif_in1_0_funcs[] = { 3, };
-+static const int mt7623_spdif_in1_1_pins[] = { 202, };
-+static const int mt7623_spdif_in1_1_funcs[] = { 1, };
-+static const int mt7623_spdif_out_pins[] = { 202, };
-+static const int mt7623_spdif_out_funcs[] = { 1, };
- 
- /* SPI */
--static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
--static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
--static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
--static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
--static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
--static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
-+static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
-+static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
-+static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
- 
- /* UART */
--static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
--static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
--static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
--static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
--static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
--static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
--static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
--static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
--static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
--static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
--static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
--static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
--static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
--static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
--static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
--static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
--static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
--static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
--static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
--static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
--static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
-+static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
-+static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
-+static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
-+static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
-+static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
-+static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
-+static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
-+static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
-+static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
-+static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
-+static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
-+static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
-+static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
-+static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
-+static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
-+static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
-+static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
-+static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
- 
- /* Watchdog */
--static int mt7623_watchdog_0_pins[] = { 11, };
--static int mt7623_watchdog_0_funcs[] = { 1, };
--static int mt7623_watchdog_1_pins[] = { 121, };
--static int mt7623_watchdog_1_funcs[] = { 5, };
-+static const int mt7623_watchdog_0_pins[] = { 11, };
-+static const int mt7623_watchdog_0_funcs[] = { 1, };
-+static const int mt7623_watchdog_1_pins[] = { 121, };
-+static const int mt7623_watchdog_1_funcs[] = { 5, };
- 
- static const struct mtk_group_desc mt7623_groups[] = {
- 	PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
-@@ -1362,7 +1362,7 @@ static const struct mtk_function_desc mt
- 	{"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7623_data = {
-+static const struct mtk_pinctrl_soc mt7623_data = {
- 	.name = "mt7623_pinctrl",
- 	.reg_cal = mt7623_reg_cals,
- 	.pins = mt7623_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-@@ -180,118 +180,118 @@ static const struct mtk_pin_desc mt7629_
-  */
- 
- /* WF 5G */
--static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
--static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
-+static const int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* LED for EPHY */
--static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
--static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
--static int mt7629_ephy_led0_pins[] = { 12, };
--static int mt7629_ephy_led0_funcs[] = { 1, };
--static int mt7629_ephy_led1_pins[] = { 13, };
--static int mt7629_ephy_led1_funcs[] = { 1, };
--static int mt7629_ephy_led2_pins[] = { 14, };
--static int mt7629_ephy_led2_funcs[] = { 1, };
--static int mt7629_ephy_led3_pins[] = { 15, };
--static int mt7629_ephy_led3_funcs[] = { 1, };
--static int mt7629_ephy_led4_pins[] = { 16, };
--static int mt7629_ephy_led4_funcs[] = { 1, };
--static int mt7629_wf2g_led_pins[] = { 17, };
--static int mt7629_wf2g_led_funcs[] = { 1, };
--static int mt7629_wf5g_led_pins[] = { 18, };
--static int mt7629_wf5g_led_funcs[] = { 1, };
-+static const int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
-+static const int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7629_ephy_led0_pins[] = { 12, };
-+static const int mt7629_ephy_led0_funcs[] = { 1, };
-+static const int mt7629_ephy_led1_pins[] = { 13, };
-+static const int mt7629_ephy_led1_funcs[] = { 1, };
-+static const int mt7629_ephy_led2_pins[] = { 14, };
-+static const int mt7629_ephy_led2_funcs[] = { 1, };
-+static const int mt7629_ephy_led3_pins[] = { 15, };
-+static const int mt7629_ephy_led3_funcs[] = { 1, };
-+static const int mt7629_ephy_led4_pins[] = { 16, };
-+static const int mt7629_ephy_led4_funcs[] = { 1, };
-+static const int mt7629_wf2g_led_pins[] = { 17, };
-+static const int mt7629_wf2g_led_funcs[] = { 1, };
-+static const int mt7629_wf5g_led_pins[] = { 18, };
-+static const int mt7629_wf5g_led_funcs[] = { 1, };
- 
- /* LED for EPHY used as JTAG */
--static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
--static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
-+static const int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, };
-+static const int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, };
- 
- /* Watchdog */
--static int mt7629_watchdog_pins[] = { 11, };
--static int mt7629_watchdog_funcs[] = { 1, };
-+static const int mt7629_watchdog_pins[] = { 11, };
-+static const int mt7629_watchdog_funcs[] = { 1, };
- 
- /* LED for GPHY */
--static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
--static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
--static int mt7629_gphy_led1_0_pins[] = { 21, };
--static int mt7629_gphy_led1_0_funcs[] = { 2, };
--static int mt7629_gphy_led2_0_pins[] = { 22, };
--static int mt7629_gphy_led2_0_funcs[] = { 2, };
--static int mt7629_gphy_led3_0_pins[] = { 23, };
--static int mt7629_gphy_led3_0_funcs[] = { 2, };
--static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
--static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
--static int mt7629_gphy_led1_1_pins[] = { 57, };
--static int mt7629_gphy_led1_1_funcs[] = { 1, };
--static int mt7629_gphy_led2_1_pins[] = { 58, };
--static int mt7629_gphy_led2_1_funcs[] = { 1, };
--static int mt7629_gphy_led3_1_pins[] = { 59, };
--static int mt7629_gphy_led3_1_funcs[] = { 1, };
-+static const int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
-+static const int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
-+static const int mt7629_gphy_led1_0_pins[] = { 21, };
-+static const int mt7629_gphy_led1_0_funcs[] = { 2, };
-+static const int mt7629_gphy_led2_0_pins[] = { 22, };
-+static const int mt7629_gphy_led2_0_funcs[] = { 2, };
-+static const int mt7629_gphy_led3_0_pins[] = { 23, };
-+static const int mt7629_gphy_led3_0_funcs[] = { 2, };
-+static const int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
-+static const int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
-+static const int mt7629_gphy_led1_1_pins[] = { 57, };
-+static const int mt7629_gphy_led1_1_funcs[] = { 1, };
-+static const int mt7629_gphy_led2_1_pins[] = { 58, };
-+static const int mt7629_gphy_led2_1_funcs[] = { 1, };
-+static const int mt7629_gphy_led3_1_pins[] = { 59, };
-+static const int mt7629_gphy_led3_1_funcs[] = { 1, };
- 
- /* I2C */
--static int mt7629_i2c_0_pins[] = { 19, 20, };
--static int mt7629_i2c_0_funcs[] = { 1, 1, };
--static int mt7629_i2c_1_pins[] = { 53, 54, };
--static int mt7629_i2c_1_funcs[] = { 1, 1, };
-+static const int mt7629_i2c_0_pins[] = { 19, 20, };
-+static const int mt7629_i2c_0_funcs[] = { 1, 1, };
-+static const int mt7629_i2c_1_pins[] = { 53, 54, };
-+static const int mt7629_i2c_1_funcs[] = { 1, 1, };
- 
- /* SPI */
--static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
--static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
--static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
--static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
--static int mt7629_spi_wp_pins[] = { 66, };
--static int mt7629_spi_wp_funcs[] = { 1, };
--static int mt7629_spi_hold_pins[] = { 67, };
--static int mt7629_spi_hold_funcs[] = { 1, };
-+static const int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
-+static const int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
-+static const int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7629_spi_wp_pins[] = { 66, };
-+static const int mt7629_spi_wp_funcs[] = { 1, };
-+static const int mt7629_spi_hold_pins[] = { 67, };
-+static const int mt7629_spi_hold_funcs[] = { 1, };
- 
- /* UART */
--static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
--static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
--static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
--static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
--static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
--static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
--static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
--static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
--static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
--static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
--static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
--static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
--static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
--static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
--static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
--static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
--static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
-+static const int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
-+static const int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
-+static const int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
-+static const int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
-+static const int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
-+static const int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
-+static const int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
-+static const int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
-+static const int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
-+static const int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
-+static const int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
-+static const int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
-+static const int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
-+static const int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
-+static const int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
-+static const int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
- 
- /* MDC/MDIO */
--static int mt7629_mdc_mdio_pins[] = { 49, 50, };
--static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7629_mdc_mdio_pins[] = { 49, 50, };
-+static const int mt7629_mdc_mdio_funcs[] = { 1, 1, };
- 
- /* PCIE */
--static int mt7629_pcie_pereset_pins[] = { 51, };
--static int mt7629_pcie_pereset_funcs[] = { 1, };
--static int mt7629_pcie_wake_pins[] = { 55, };
--static int mt7629_pcie_wake_funcs[] = { 1, };
--static int mt7629_pcie_clkreq_pins[] = { 56, };
--static int mt7629_pcie_clkreq_funcs[] = { 1, };
-+static const int mt7629_pcie_pereset_pins[] = { 51, };
-+static const int mt7629_pcie_pereset_funcs[] = { 1, };
-+static const int mt7629_pcie_wake_pins[] = { 55, };
-+static const int mt7629_pcie_wake_funcs[] = { 1, };
-+static const int mt7629_pcie_clkreq_pins[] = { 56, };
-+static const int mt7629_pcie_clkreq_funcs[] = { 1, };
- 
- /* PWM */
--static int mt7629_pwm_0_pins[] = { 52, };
--static int mt7629_pwm_0_funcs[] = { 1, };
--static int mt7629_pwm_1_pins[] = { 61, };
--static int mt7629_pwm_1_funcs[] = { 2, };
-+static const int mt7629_pwm_0_pins[] = { 52, };
-+static const int mt7629_pwm_0_funcs[] = { 1, };
-+static const int mt7629_pwm_1_pins[] = { 61, };
-+static const int mt7629_pwm_1_funcs[] = { 2, };
- 
- /* WF 2G */
--static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
--static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
-+static const int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- /* SNFI */
--static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
--static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+static const int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
-+static const int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
- 
- /* SPI NOR */
--static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
--static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
-+static const int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
-+static const int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
- 
- static const struct mtk_group_desc mt7629_groups[] = {
- 	PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
-@@ -385,7 +385,7 @@ static const struct mtk_function_desc mt
- 	{"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7629_data = {
-+static const struct mtk_pinctrl_soc mt7629_data = {
- 	.name = "mt7629_pinctrl",
- 	.reg_cal = mt7629_reg_cals,
- 	.pins = mt7629_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -570,242 +570,246 @@ static const struct mtk_pin_desc mt7981_
- };
- 
- /* WA_AICE */
--static int mt7981_wa_aice1_pins[] = { 0, 1, };
--static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-+static const int mt7981_wa_aice1_pins[] = { 0, 1, };
-+static const int mt7981_wa_aice1_funcs[] = { 2, 2, };
- 
--static int mt7981_wa_aice2_pins[] = { 0, 1, };
--static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-+static const int mt7981_wa_aice2_pins[] = { 0, 1, };
-+static const int mt7981_wa_aice2_funcs[] = { 3, 3, };
- 
--static int mt7981_wa_aice3_pins[] = { 28, 29, };
--static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-+static const int mt7981_wa_aice3_pins[] = { 28, 29, };
-+static const int mt7981_wa_aice3_funcs[] = { 3, 3, };
- 
--static int mt7981_wm_aice1_pins[] = { 9, 10, };
--static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-+static const int mt7981_wm_aice1_pins[] = { 9, 10, };
-+static const int mt7981_wm_aice1_funcs[] = { 2, 2, };
- 
--static int mt7981_wm_aice2_pins[] = { 30, 31, };
--static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-+static const int mt7981_wm_aice2_pins[] = { 30, 31, };
-+static const int mt7981_wm_aice2_funcs[] = { 5, 5, };
- 
- /* WM_UART */
--static int mt7981_wm_uart_0_pins[] = { 0, 1, };
--static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-+static const int mt7981_wm_uart_0_pins[] = { 0, 1, };
-+static const int mt7981_wm_uart_0_funcs[] = { 5, 5, };
- 
--static int mt7981_wm_uart_1_pins[] = { 20, 21, };
--static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-+static const int mt7981_wm_uart_1_pins[] = { 20, 21, };
-+static const int mt7981_wm_uart_1_funcs[] = { 4, 4, };
- 
--static int mt7981_wm_uart_2_pins[] = { 30, 31, };
--static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-+static const int mt7981_wm_uart_2_pins[] = { 30, 31, };
-+static const int mt7981_wm_uart_2_funcs[] = { 3, 3, };
- 
- /* DFD */
--static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
--static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-+static const int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-+static const int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
- 
- /* SYS_WATCHDOG */
--static int mt7981_watchdog_pins[] = { 2, };
--static int mt7981_watchdog_funcs[] = { 1, };
-+static const int mt7981_watchdog_pins[] = { 2, };
-+static const int mt7981_watchdog_funcs[] = { 1, };
- 
--static int mt7981_watchdog1_pins[] = { 13, };
--static int mt7981_watchdog1_funcs[] = { 5, };
-+static const int mt7981_watchdog1_pins[] = { 13, };
-+static const int mt7981_watchdog1_funcs[] = { 5, };
- 
- /* PCIE_PERESET_N */
--static int mt7981_pcie_pereset_pins[] = { 3, };
--static int mt7981_pcie_pereset_funcs[] = { 1, };
-+static const int mt7981_pcie_pereset_pins[] = { 3, };
-+static const int mt7981_pcie_pereset_funcs[] = { 1, };
- 
- /* JTAG */
--static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
--static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-+static const int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
- 
- /* WM_JTAG */
--static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
--static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-+static const int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-+static const int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
- 
--static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
--static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+static const int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-+static const int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
- 
- /* WO0_JTAG */
--static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
--static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-+static const int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-+static const int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
- 
--static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
--static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+static const int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-+static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
- 
- /* UART2 */
--static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
--static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-+static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
- 
- /* GBE_LED0 */
--static int mt7981_gbe_led0_pins[] = { 8, };
--static int mt7981_gbe_led0_funcs[] = { 3, };
-+static const int mt7981_gbe_led0_pins[] = { 8, };
-+static const int mt7981_gbe_led0_funcs[] = { 3, };
- 
- /* PTA_EXT */
--static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
--static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-+static const int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-+static const int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
- 
--static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
--static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-+static const int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-+static const int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
- 
- /* PWM2 */
--static int mt7981_pwm2_pins[] = { 7, };
--static int mt7981_pwm2_funcs[] = { 4, };
-+static const int mt7981_pwm2_pins[] = { 7, };
-+static const int mt7981_pwm2_funcs[] = { 4, };
- 
- /* NET_WO0_UART_TXD */
--static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
--static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-+static const int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-+static const int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
- 
--static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
--static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-+static const int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-+static const int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
- 
--static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
--static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-+static const int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-+static const int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
- 
- /* SPI1 */
--static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
--static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-+static const int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-+static const int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
- 
- /* I2C */
--static int mt7981_i2c0_0_pins[] = { 6, 7, };
--static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-+static const int mt7981_i2c0_0_pins[] = { 6, 7, };
-+static const int mt7981_i2c0_0_funcs[] = { 6, 6, };
- 
--static int mt7981_i2c0_1_pins[] = { 30, 31, };
--static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-+static const int mt7981_i2c0_1_pins[] = { 30, 31, };
-+static const int mt7981_i2c0_1_funcs[] = { 4, 4, };
- 
--static int mt7981_i2c0_2_pins[] = { 36, 37, };
--static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-+static const int mt7981_i2c0_2_pins[] = { 36, 37, };
-+static const int mt7981_i2c0_2_funcs[] = { 2, 2, };
- 
--static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
--static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-+static const int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-+static const int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
- 
--static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
--static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-+static const int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-+static const int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
- 
--static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
--static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-+static const int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-+static const int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
- 
--static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
--static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-+static const int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-+static const int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
- 
- /* DFD_NTRST */
--static int mt7981_dfd_ntrst_pins[] = { 8, };
--static int mt7981_dfd_ntrst_funcs[] = { 6, };
-+static const int mt7981_dfd_ntrst_pins[] = { 8, };
-+static const int mt7981_dfd_ntrst_funcs[] = { 6, };
- 
- /* PWM0 */
--static int mt7981_pwm0_0_pins[] = { 13, };
--static int mt7981_pwm0_0_funcs[] = { 2, };
-+static const int mt7981_pwm0_0_pins[] = { 13, };
-+static const int mt7981_pwm0_0_funcs[] = { 2, };
- 
--static int mt7981_pwm0_1_pins[] = { 15, };
--static int mt7981_pwm0_1_funcs[] = { 1, };
-+static const int mt7981_pwm0_1_pins[] = { 15, };
-+static const int mt7981_pwm0_1_funcs[] = { 1, };
- 
- /* PWM1 */
--static int mt7981_pwm1_0_pins[] = { 14, };
--static int mt7981_pwm1_0_funcs[] = { 2, };
-+static const int mt7981_pwm1_0_pins[] = { 14, };
-+static const int mt7981_pwm1_0_funcs[] = { 2, };
- 
--static int mt7981_pwm1_1_pins[] = { 15, };
--static int mt7981_pwm1_1_funcs[] = { 3, };
-+static const int mt7981_pwm1_1_pins[] = { 15, };
-+static const int mt7981_pwm1_1_funcs[] = { 3, };
- 
- /* GBE_LED1 */
--static int mt7981_gbe_led1_pins[] = { 13, };
--static int mt7981_gbe_led1_funcs[] = { 3, };
-+static const int mt7981_gbe_led1_pins[] = { 13, };
-+static const int mt7981_gbe_led1_funcs[] = { 3, };
- 
- /* PCM */
--static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
--static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-+static const int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-+static const int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
- 
- /* UDI */
--static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
--static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-+static const int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-+static const int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
- 
- /* DRV_VBUS */
--static int mt7981_drv_vbus_pins[] = { 14, };
--static int mt7981_drv_vbus_funcs[] = { 1, };
-+static const int mt7981_drv_vbus_pins[] = { 14, };
-+static const int mt7981_drv_vbus_funcs[] = { 1, };
- 
- /* EMMC */
--static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
--static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+static const int mt7981_emmc_45_pins[] = {
-+	15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-+static const int mt7981_emmc_45_funcs[] = {
-+	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
- /* SNFI */
--static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
--static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-+static const int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-+static const int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
- 
- /* SPI0 */
--static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
--static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-+static const int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
- 
- /* SPI0 */
--static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
--static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-+static const int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-+static const int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
- 
- /* SPI1 */
--static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
--static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-+static const int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
- 
- /* SPI2 */
--static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
--static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-+static const int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
- 
- /* SPI2 */
--static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
--static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-+static const int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-+static const int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
- 
- /* UART1 */
--static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
--static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-+static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
--static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-+static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-+static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
- 
- /* UART2 */
--static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
--static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-+static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
- 
- /* UART0 */
--static int mt7981_uart0_pins[] = { 32, 33, };
--static int mt7981_uart0_funcs[] = { 1, 1, };
-+static const int mt7981_uart0_pins[] = { 32, 33, };
-+static const int mt7981_uart0_funcs[] = { 1, 1, };
- 
- /* PCIE_CLK_REQ */
--static int mt7981_pcie_clk_pins[] = { 34, };
--static int mt7981_pcie_clk_funcs[] = { 2, };
-+static const int mt7981_pcie_clk_pins[] = { 34, };
-+static const int mt7981_pcie_clk_funcs[] = { 2, };
- 
- /* PCIE_WAKE_N */
--static int mt7981_pcie_wake_pins[] = { 35, };
--static int mt7981_pcie_wake_funcs[] = { 2, };
-+static const int mt7981_pcie_wake_pins[] = { 35, };
-+static const int mt7981_pcie_wake_funcs[] = { 2, };
- 
- /* MDC_MDIO */
--static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
--static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-+static const int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
- 
--static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
--static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-+static const int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-+static const int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
- 
- /* WF0_MODE1 */
--static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
--				       50, 51, 52, 53, 54, 55, 56 };
--static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
--					1, 1, 1, 1 };
-+static const int mt7981_wf0_mode1_pins[] = {
-+	40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-+static const int mt7981_wf0_mode1_funcs[] = {
-+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
- 
- /* WF0_MODE3 */
--static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
--static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+static const int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-+static const int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
- 
- /* WF2G_LED */
--static int mt7981_wf2g_led0_pins[] = { 30, };
--static int mt7981_wf2g_led0_funcs[] = { 2, };
-+static const int mt7981_wf2g_led0_pins[] = { 30, };
-+static const int mt7981_wf2g_led0_funcs[] = { 2, };
- 
--static int mt7981_wf2g_led1_pins[] = { 34, };
--static int mt7981_wf2g_led1_funcs[] = { 1, };
-+static const int mt7981_wf2g_led1_pins[] = { 34, };
-+static const int mt7981_wf2g_led1_funcs[] = { 1, };
- 
- /* WF5G_LED */
--static int mt7981_wf5g_led0_pins[] = { 31, };
--static int mt7981_wf5g_led0_funcs[] = { 2, };
-+static const int mt7981_wf5g_led0_pins[] = { 31, };
-+static const int mt7981_wf5g_led0_funcs[] = { 2, };
- 
--static int mt7981_wf5g_led1_pins[] = { 35, };
--static int mt7981_wf5g_led1_funcs[] = { 1, };
-+static const int mt7981_wf5g_led1_pins[] = { 35, };
-+static const int mt7981_wf5g_led1_funcs[] = { 1, };
- 
- /* MT7531_INT */
--static int mt7981_mt7531_int_pins[] = { 38, };
--static int mt7981_mt7531_int_funcs[] = { 1, };
-+static const int mt7981_mt7531_int_pins[] = { 38, };
-+static const int mt7981_mt7531_int_funcs[] = { 1, };
- 
- /* ANT_SEL */
--static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
--static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-+static const int mt7981_ant_sel_pins[] = {
-+	14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-+static const int mt7981_ant_sel_funcs[] = {
-+	6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
- 
- static const struct mtk_group_desc mt7981_groups[] = {
- 	/* @GPIO(0,1): WA_AICE(2) */
-@@ -1012,7 +1016,7 @@ static const char *const mt7981_pinctrl_
- 	"iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
- };
- 
--static struct mtk_pinctrl_soc mt7981_data = {
-+static const struct mtk_pinctrl_soc mt7981_data = {
- 	.name = "mt7981_pinctrl",
- 	.reg_cal = mt7981_reg_cals,
- 	.pins = mt7981_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -554,114 +554,117 @@ static const struct mtk_io_type_desc mt7
-  * The hardware probably has multiple combinations of these pinouts.
-  */
- 
--static int mt7986_watchdog_pins[] = { 0, };
--static int mt7986_watchdog_funcs[] = { 1, };
-+static const int mt7986_watchdog_pins[] = { 0, };
-+static const int mt7986_watchdog_funcs[] = { 1, };
- 
--static int mt7986_wifi_led_pins[] = { 1, 2, };
--static int mt7986_wifi_led_funcs[] = { 1, 1, };
-+static const int mt7986_wifi_led_pins[] = { 1, 2, };
-+static const int mt7986_wifi_led_funcs[] = { 1, 1, };
- 
--static int mt7986_i2c_pins[] = { 3, 4, };
--static int mt7986_i2c_funcs[] = { 1, 1, };
-+static const int mt7986_i2c_pins[] = { 3, 4, };
-+static const int mt7986_i2c_funcs[] = { 1, 1, };
- 
--static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
--static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-+static const int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
--static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-+static const int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_pwm1_1_pins[] = { 20, };
--static int mt7986_pwm1_1_funcs[] = { 2, };
-+static const int mt7986_pwm1_1_pins[] = { 20, };
-+static const int mt7986_pwm1_1_funcs[] = { 2, };
- 
--static int mt7986_pwm0_pins[] = { 21, };
--static int mt7986_pwm0_funcs[] = { 1, };
-+static const int mt7986_pwm0_pins[] = { 21, };
-+static const int mt7986_pwm0_funcs[] = { 1, };
- 
--static int mt7986_pwm1_0_pins[] = { 22, };
--static int mt7986_pwm1_0_funcs[] = { 1, };
-+static const int mt7986_pwm1_0_pins[] = { 22, };
-+static const int mt7986_pwm1_0_funcs[] = { 1, };
- 
--static int mt7986_emmc_45_pins[] = {
-+static const int mt7986_emmc_45_pins[] = {
- 	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
--static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+static const int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
--static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
--static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-+static const int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
--static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-+static const int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
--static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-+static const int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
--static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-+static const int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
-+static const int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
-+static const int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
--static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-+static const int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
--static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-+static const int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-+static const int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
- 
--static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
--static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-+static const int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-+static const int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
- 
--static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
--static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-+static const int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-+static const int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
- 
--static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
--static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-+static const int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-+static const int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
- 
--static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
--static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-+static const int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-+static const int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
- 
--static int mt7986_uart0_pins[] = { 39, 40, };
--static int mt7986_uart0_funcs[] = { 1, 1, };
-+static const int mt7986_uart0_pins[] = { 39, 40, };
-+static const int mt7986_uart0_funcs[] = { 1, 1, };
- 
--static int mt7986_pcie_reset_pins[] = { 41, };
--static int mt7986_pcie_reset_funcs[] = { 1, };
-+static const int mt7986_pcie_reset_pins[] = { 41, };
-+static const int mt7986_pcie_reset_funcs[] = { 1, };
- 
--static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
--static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-+static const int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
--static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-+static const int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_emmc_51_pins[] = {
-+static const int mt7986_emmc_51_pins[] = {
- 	50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
--static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_emmc_51_funcs[] = {
-+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
--static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-+static const int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
--static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-+static const int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-+static const int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_switch_int_pins[] = { 66, };
--static int mt7986_switch_int_funcs[] = { 1, };
-+static const int mt7986_switch_int_pins[] = { 66, };
-+static const int mt7986_switch_int_funcs[] = { 1, };
- 
--static int mt7986_mdc_mdio_pins[] = { 67, 68, };
--static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-+static const int mt7986_mdc_mdio_pins[] = { 67, 68, };
-+static const int mt7986_mdc_mdio_funcs[] = { 1, 1, };
- 
--static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
--static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_wf_2g_pins[] = {
-+	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-+static const int mt7986_wf_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
--static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt7986_wf_5g_pins[] = {
-+	91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-+static const int mt7986_wf_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
--static int mt7986_wf_dbdc_pins[] = {
-+static const int mt7986_wf_dbdc_pins[] = {
- 	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
--static int mt7986_wf_dbdc_funcs[] = {
-+static const int mt7986_wf_dbdc_funcs[] = {
- 	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
--static int mt7986_pcie_clk_pins[] = { 9, };
--static int mt7986_pcie_clk_funcs[] = { 1, };
-+static const int mt7986_pcie_clk_pins[] = { 9, };
-+static const int mt7986_pcie_clk_funcs[] = { 1, };
- 
--static int mt7986_pcie_wake_pins[] = { 10, };
--static int mt7986_pcie_wake_funcs[] = { 1, };
-+static const int mt7986_pcie_wake_pins[] = { 10, };
-+static const int mt7986_pcie_wake_funcs[] = { 1, };
- 
- static const struct mtk_group_desc mt7986_groups[] = {
- 	PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
-@@ -738,7 +741,7 @@ static const struct mtk_function_desc mt
- 	{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt7986_data = {
-+static const struct mtk_pinctrl_soc mt7986_data = {
- 	.name = "mt7986_pinctrl",
- 	.reg_cal = mt7986_reg_cals,
- 	.pins = mt7986_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
-@@ -315,12 +315,12 @@ static const struct mtk_pin_desc mt8512_
-  */
- 
- /* UART */
--static int mt8512_uart0_0_rxd_txd_pins[]		= { 52, 53, };
--static int mt8512_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8512_uart1_0_rxd_txd_pins[]		= { 54, 55, };
--static int mt8512_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8512_uart2_0_rxd_txd_pins[]		= { 28, 29, };
--static int mt8512_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8512_uart0_0_rxd_txd_pins[]		= { 52, 53, };
-+static const int mt8512_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8512_uart1_0_rxd_txd_pins[]		= { 54, 55, };
-+static const int mt8512_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8512_uart2_0_rxd_txd_pins[]		= { 28, 29, };
-+static const int mt8512_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
- 
- /* Joint those groups owning the same capability in user point of view which
-  * allows that people tend to use through the device tree.
-@@ -330,13 +330,13 @@ static const char *const mt8512_uart_gro
- 						"uart2_0_rxd_txd", };
- 
- /* SNAND */
--static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
--static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-+static const int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
-+static const int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
- 
- /* MMC0 */
--static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
--				   85, 86, };
--static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
-+					 85, 86, };
-+static const int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- static const struct mtk_group_desc mt8512_groups[] = {
- 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
-@@ -356,7 +356,7 @@ static const struct mtk_function_desc mt
- 	{"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt8512_data = {
-+static const struct mtk_pinctrl_soc mt8512_data = {
- 	.name = "mt8512_pinctrl",
- 	.reg_cal = mt8512_reg_cals,
- 	.pins = mt8512_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-@@ -326,12 +326,12 @@ static const struct mtk_pin_desc mt8516_
-  */
- 
- /* UART */
--static int mt8516_uart0_0_rxd_txd_pins[]		= { 62, 63, };
--static int mt8516_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8516_uart1_0_rxd_txd_pins[]		= { 64, 65, };
--static int mt8516_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8516_uart2_0_rxd_txd_pins[]		= { 34, 35, };
--static int mt8516_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8516_uart0_0_rxd_txd_pins[]		= { 62, 63, };
-+static const int mt8516_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8516_uart1_0_rxd_txd_pins[]		= { 64, 65, };
-+static const int mt8516_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8516_uart2_0_rxd_txd_pins[]		= { 34, 35, };
-+static const int mt8516_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
- 
- /* Joint those groups owning the same capability in user point of view which
-  * allows that people tend to use through the device tree.
-@@ -341,9 +341,9 @@ static const char *const mt8516_uart_gro
- 						"uart2_0_rxd_txd", };
- 
- /* MMC0 */
--static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
--				   119, 120, };
--static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
-+					 118, 119, 120, };
-+static const int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- static const struct mtk_group_desc mt8516_groups[] = {
- 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
---- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
-@@ -346,12 +346,12 @@ static const struct mtk_pin_desc mt8518_
-  */
- 
- /* UART */
--static int mt8518_uart0_0_rxd_txd_pins[]		= { 104, 105, };
--static int mt8518_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8518_uart1_0_rxd_txd_pins[]		= { 52, 53, };
--static int mt8518_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
--static int mt8518_uart2_0_rxd_txd_pins[]		= { 106, 107, };
--static int mt8518_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8518_uart0_0_rxd_txd_pins[]		= { 104, 105, };
-+static const int mt8518_uart0_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8518_uart1_0_rxd_txd_pins[]		= { 52, 53, };
-+static const int mt8518_uart1_0_rxd_txd_funcs[]		= {  1,  1, };
-+static const int mt8518_uart2_0_rxd_txd_pins[]		= { 106, 107, };
-+static const int mt8518_uart2_0_rxd_txd_funcs[]		= {  1,  1, };
- 
- /* Joint those groups owning the same capability in user point of view which
-  * allows that people tend to use through the device tree.
-@@ -361,9 +361,9 @@ static const char *const mt8518_uart_gro
- 						"uart2_0_rxd_txd", };
- 
- /* MMC0 */
--static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
--				   12, 13, };
--static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-+static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11,
-+					 12, 13, };
-+static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
- 
- static const struct mtk_group_desc mt8518_groups[] = {
- 	PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd),
-@@ -380,7 +380,7 @@ static const struct mtk_function_desc mt
- 	{"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)},
- };
- 
--static struct mtk_pinctrl_soc mt8518_data = {
-+static const struct mtk_pinctrl_soc mt8518_data = {
- 	.name = "mt8518_pinctrl",
- 	.reg_cal = mt8518_reg_cals,
- 	.pins = mt8518_pins,
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -314,7 +314,7 @@ static int mtk_pinmux_group_set(struct u
- 	int i;
- 
- 	for (i = 0; i < grp->num_pins; i++) {
--		int *pin_modes = grp->data;
-+		const int *pin_modes = grp->data;
- 
- 		mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
- 				 pin_modes[i]);
-@@ -769,7 +769,7 @@ static int mtk_gpiochip_register(struct
- #endif
- 
- int mtk_pinctrl_common_probe(struct udevice *dev,
--			     struct mtk_pinctrl_soc *soc)
-+			     const struct mtk_pinctrl_soc *soc)
- {
- 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
- 	int ret = 0;
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
-@@ -174,9 +174,9 @@ struct mtk_pin_desc {
-  */
- struct mtk_group_desc {
- 	const char *name;
--	int *pins;
-+	const int *pins;
- 	int num_pins;
--	void *data;
-+	const void *data;
- };
- 
- /**
-@@ -233,7 +233,7 @@ struct mtk_pinctrl_soc {
-  */
- struct mtk_pinctrl_priv {
- 	void __iomem *base[MAX_BASE_CALC];
--	struct mtk_pinctrl_soc *soc;
-+	const struct mtk_pinctrl_soc *soc;
- };
- 
- extern const struct pinctrl_ops mtk_pinctrl_ops;
-@@ -242,7 +242,7 @@ extern const struct pinctrl_ops mtk_pinc
- void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
- void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set);
- int mtk_pinctrl_common_probe(struct udevice *dev,
--			     struct mtk_pinctrl_soc *soc);
-+			     const struct mtk_pinctrl_soc *soc);
- 
- #if CONFIG_IS_ENABLED(PINCONF)
- 
diff --git a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch b/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch
deleted file mode 100644
index d83a89ab37..0000000000
--- a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 783c46d29f8b186bd65f3e83f38ad883e8bcec69 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:42 +0800
-Subject: [PATCH 13/29] pinctrl: mediatek: fix the return value in driving
- configuration functions
-
-The original mediatek pinctrl functions for driving configuration
-'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input
-parameters are not supported.
-This patch fixes the return value in those functions.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -513,7 +513,7 @@ int mtk_pinconf_drive_set_v0(struct udev
- 			return err;
- 	}
- 
--	return 0;
-+	return err;
- }
- 
- int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
-@@ -531,7 +531,7 @@ int mtk_pinconf_drive_set_v1(struct udev
- 			return err;
- 	}
- 
--	return 0;
-+	return err;
- }
- 
- int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
diff --git a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch b/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch
deleted file mode 100644
index 7cb185ff42..0000000000
--- a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 090351b416e57e0f7b5d1a4c87d4ed9ab4f5c89b Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:46 +0800
-Subject: [PATCH 14/29] pinctrl: mediatek: add pinmux_set ops support
-
-This patch adds pinmux_set ops for mediatek pinctrl framework
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
-@@ -304,6 +304,19 @@ static const char *mtk_get_function_name
- 	return priv->soc->funcs[selector].name;
- }
- 
-+static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector,
-+			  unsigned int func_selector)
-+{
-+	int err;
-+
-+	err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE,
-+			       func_selector);
-+	if (err)
-+		return err;
-+
-+	return 0;
-+}
-+
- static int mtk_pinmux_group_set(struct udevice *dev,
- 				unsigned int group_selector,
- 				unsigned int func_selector)
-@@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops
- 	.get_group_name = mtk_get_group_name,
- 	.get_functions_count = mtk_get_functions_count,
- 	.get_function_name = mtk_get_function_name,
-+	.pinmux_set = mtk_pinmux_set,
- 	.pinmux_group_set = mtk_pinmux_group_set,
- #if CONFIG_IS_ENABLED(PINCONF)
- 	.pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
diff --git a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch
deleted file mode 100644
index cfc7c32ba3..0000000000
--- a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch
+++ /dev/null
@@ -1,1315 +0,0 @@
-From 5e821f4ebd9da4ccf3c8871e402996f6a6eb8d1c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:50 +0800
-Subject: [PATCH 15/29] pinctrl: mediatek: add pinctrl driver for MT7988 SoC
-
-This patch adds pinctrl and gpio support for MT7988 SoC
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/pinctrl/mediatek/Kconfig          |    4 +
- drivers/pinctrl/mediatek/Makefile         |    1 +
- drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1274 +++++++++++++++++++++
- 3 files changed, 1279 insertions(+)
- create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c
-
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -24,6 +24,10 @@ config PINCTRL_MT7986
- 	bool "MT7986 SoC pinctrl driver"
- 	select PINCTRL_MTK
- 
-+config PINCTRL_MT7988
-+	bool "MT7988 SoC pinctrl driver"
-+	select PINCTRL_MTK
-+
- config PINCTRL_MT8512
- 	bool "MT8512 SoC pinctrl driver"
- 	select PINCTRL_MTK
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-
- obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
- obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
-+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
- obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
- obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
- obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
---- /dev/null
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
-@@ -0,0 +1,1274 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dm.h>
-+#include "pinctrl-mtk-common.h"
-+
-+enum MT7988_PINCTRL_REG_PAGE {
-+	GPIO_BASE,
-+	IOCFG_TR_BASE,
-+	IOCFG_BR_BASE,
-+	IOCFG_RB_BASE,
-+	IOCFG_LB_BASE,
-+	IOCFG_TL_BASE,
-+};
-+
-+#define MT7988_TYPE0_PIN(_number, _name)                                       \
-+	MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
-+
-+#define MT7988_TYPE1_PIN(_number, _name)                                       \
-+	MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
-+
-+#define MT7988_TYPE2_PIN(_number, _name)                                       \
-+	MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2)
-+
-+#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)     \
-+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs,      \
-+			    _s_bit, _x_bits, 32, 0)
-+
-+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-+		       _x_bits)                                                \
-+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
-+			    _s_bit, _x_bits, 32, 0)
-+
-+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
-+			_x_bits)                                               \
-+	PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
-+			    _s_bit, _x_bits, 32, 1)
-+
-+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
-+	PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1),
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
-+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
-+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
-+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1),
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1),
-+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1),
-+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
-+	PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
-+
-+	PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3),
-+	PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3),
-+	PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3),
-+	PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
-+	PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
-+	PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
-+	PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
-+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
-+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
-+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1),
-+	PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1),
-+
-+	PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1),
-+	PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1),
-+	PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1),
-+	PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1),
-+	PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1),
-+	PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1),
-+	PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1),
-+	PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1),
-+	PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1),
-+	PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1),
-+	PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1),
-+	PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1),
-+	PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1),
-+	PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1),
-+	PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1),
-+	PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1),
-+	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1),
-+	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1),
-+	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1),
-+	PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1),
-+	PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1),
-+	PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1),
-+	PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1),
-+	PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1),
-+	PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1),
-+	PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1),
-+	PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1),
-+	PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1),
-+	PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1),
-+	PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1),
-+	PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1),
-+
-+	PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1),
-+	PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1),
-+	PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1),
-+	PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1),
-+	PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1),
-+	PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1),
-+	PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1),
-+	PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1),
-+	PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1),
-+	PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1),
-+	PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1),
-+	PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1),
-+	PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1),
-+
-+	PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
-+	PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1),
-+	PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1),
-+
-+	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1),
-+	PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1),
-+	PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1),
-+	PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
-+};
-+
-+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
-+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
-+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
-+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
-+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
-+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
-+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
-+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
-+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
-+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
-+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
-+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
-+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
-+};
-+
-+static const struct mtk_pin_desc mt7988_pins[] = {
-+	MT7988_TYPE0_PIN(0, "UART2_RXD"),
-+	MT7988_TYPE0_PIN(1, "UART2_TXD"),
-+	MT7988_TYPE0_PIN(2, "UART2_CTS"),
-+	MT7988_TYPE0_PIN(3, "UART2_RTS"),
-+	MT7988_TYPE0_PIN(4, "GPIO_A"),
-+	MT7988_TYPE0_PIN(5, "SMI_0_MDC"),
-+	MT7988_TYPE0_PIN(6, "SMI_0_MDIO"),
-+	MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"),
-+	MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
-+	MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"),
-+	MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
-+	MT7988_TYPE0_PIN(11, "GPIO_P"),
-+	MT7988_TYPE0_PIN(12, "WATCHDOG"),
-+	MT7988_TYPE1_PIN(13, "GPIO_RESET"),
-+	MT7988_TYPE1_PIN(14, "GPIO_WPS"),
-+	MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"),
-+	MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"),
-+	MT7988_TYPE2_PIN(17, "I2C_1_SCL"),
-+	MT7988_TYPE2_PIN(18, "I2C_1_SDA"),
-+	MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"),
-+	MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"),
-+	MT7988_TYPE0_PIN(21, "PWMD1"),
-+	MT7988_TYPE0_PIN(22, "SPI0_WP"),
-+	MT7988_TYPE0_PIN(23, "SPI0_HOLD"),
-+	MT7988_TYPE0_PIN(24, "SPI0_CSB"),
-+	MT7988_TYPE0_PIN(25, "SPI0_MISO"),
-+	MT7988_TYPE0_PIN(26, "SPI0_MOSI"),
-+	MT7988_TYPE0_PIN(27, "SPI0_CLK"),
-+	MT7988_TYPE0_PIN(28, "SPI1_CSB"),
-+	MT7988_TYPE0_PIN(29, "SPI1_MISO"),
-+	MT7988_TYPE0_PIN(30, "SPI1_MOSI"),
-+	MT7988_TYPE0_PIN(31, "SPI1_CLK"),
-+	MT7988_TYPE0_PIN(32, "SPI2_CLK"),
-+	MT7988_TYPE0_PIN(33, "SPI2_MOSI"),
-+	MT7988_TYPE0_PIN(34, "SPI2_MISO"),
-+	MT7988_TYPE0_PIN(35, "SPI2_CSB"),
-+	MT7988_TYPE0_PIN(36, "SPI2_HOLD"),
-+	MT7988_TYPE0_PIN(37, "SPI2_WP"),
-+	MT7988_TYPE0_PIN(38, "EMMC_RSTB"),
-+	MT7988_TYPE0_PIN(39, "EMMC_DSL"),
-+	MT7988_TYPE0_PIN(40, "EMMC_CK"),
-+	MT7988_TYPE0_PIN(41, "EMMC_CMD"),
-+	MT7988_TYPE0_PIN(42, "EMMC_DATA_7"),
-+	MT7988_TYPE0_PIN(43, "EMMC_DATA_6"),
-+	MT7988_TYPE0_PIN(44, "EMMC_DATA_5"),
-+	MT7988_TYPE0_PIN(45, "EMMC_DATA_4"),
-+	MT7988_TYPE0_PIN(46, "EMMC_DATA_3"),
-+	MT7988_TYPE0_PIN(47, "EMMC_DATA_2"),
-+	MT7988_TYPE0_PIN(48, "EMMC_DATA_1"),
-+	MT7988_TYPE0_PIN(49, "EMMC_DATA_0"),
-+	MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"),
-+	MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"),
-+	MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"),
-+	MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"),
-+	MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"),
-+	MT7988_TYPE0_PIN(55, "UART0_RXD"),
-+	MT7988_TYPE0_PIN(56, "UART0_TXD"),
-+	MT7988_TYPE0_PIN(57, "PWMD0"),
-+	MT7988_TYPE0_PIN(58, "JTAG_JTDI"),
-+	MT7988_TYPE0_PIN(59, "JTAG_JTDO"),
-+	MT7988_TYPE0_PIN(60, "JTAG_JTMS"),
-+	MT7988_TYPE0_PIN(61, "JTAG_JTCLK"),
-+	MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"),
-+	MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"),
-+	MT7988_TYPE0_PIN(64, "LED_A"),
-+	MT7988_TYPE0_PIN(65, "LED_B"),
-+	MT7988_TYPE0_PIN(66, "LED_C"),
-+	MT7988_TYPE0_PIN(67, "LED_D"),
-+	MT7988_TYPE0_PIN(68, "LED_E"),
-+	MT7988_TYPE0_PIN(69, "GPIO_B"),
-+	MT7988_TYPE0_PIN(70, "GPIO_C"),
-+	MT7988_TYPE2_PIN(71, "I2C_2_SCL"),
-+	MT7988_TYPE2_PIN(72, "I2C_2_SDA"),
-+	MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"),
-+	MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"),
-+	MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"),
-+	MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
-+	MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"),
-+	MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
-+	MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"),
-+	MT7988_TYPE0_PIN(80, "UART1_RXD"),
-+	MT7988_TYPE0_PIN(81, "UART1_TXD"),
-+	MT7988_TYPE0_PIN(82, "UART1_CTS"),
-+	MT7988_TYPE0_PIN(83, "UART1_RTS"),
-+};
-+
-+/* jtag */
-+static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
-+static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
-+
-+static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
-+
-+static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
-+
-+static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
-+static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
-+
-+static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
-+static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+/* int_usxgmii */
-+static const int mt7988_int_usxgmii_pins[] = { 2, 3 };
-+static const int mt7988_int_usxgmii_funcs[] = { 3, 3 };
-+
-+/* pwm */
-+static const int mt7988_pwm0_pins[] = { 57 };
-+static const int mt7988_pwm0_funcs[] = { 1 };
-+
-+static const int mt7988_pwm1_pins[] = { 21 };
-+static const int mt7988_pwm1_funcs[] = { 1 };
-+
-+static const int mt7988_pwm2_pins[] = { 80 };
-+static const int mt7988_pwm2_funcs[] = { 2 };
-+
-+static const int mt7988_pwm3_pins[] = { 81 };
-+static const int mt7988_pwm3_funcs[] = { 2 };
-+
-+static const int mt7988_pwm4_pins[] = { 82 };
-+static const int mt7988_pwm4_funcs[] = { 2 };
-+
-+static const int mt7988_pwm5_pins[] = { 83 };
-+static const int mt7988_pwm5_funcs[] = { 2 };
-+
-+static const int mt7988_pwm6_pins[] = { 69 };
-+static const int mt7988_pwm6_funcs[] = { 3 };
-+
-+static const int mt7988_pwm7_pins[] = { 70 };
-+static const int mt7988_pwm7_funcs[] = { 3 };
-+
-+/* dfd */
-+static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
-+static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+/* i2c */
-+static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
-+static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
-+static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
-+
-+static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
-+static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
-+static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
-+
-+static const int mt7988_i2c0_0_pins[] = { 5, 6 };
-+static const int mt7988_i2c0_0_funcs[] = { 2, 2 };
-+
-+static const int mt7988_i2c1_sfp_pins[] = { 5, 6 };
-+static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
-+
-+static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
-+static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
-+static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
-+
-+static const int mt7988_i2c0_1_pins[] = { 15, 16 };
-+static const int mt7988_i2c0_1_funcs[] = { 1, 1 };
-+
-+static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
-+static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
-+
-+static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
-+static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
-+
-+static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
-+static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
-+
-+static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
-+static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
-+
-+static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
-+static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
-+
-+static const int mt7988_i2c1_0_pins[] = { 17, 18 };
-+static const int mt7988_i2c1_0_funcs[] = { 1, 1 };
-+
-+static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
-+static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
-+
-+static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
-+static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
-+
-+static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
-+static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
-+
-+static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
-+static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
-+static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
-+
-+static const int mt7988_i2c1_2_pins[] = { 69, 70 };
-+static const int mt7988_i2c1_2_funcs[] = { 2, 2 };
-+
-+static const int mt7988_i2c2_0_pins[] = { 69, 70 };
-+static const int mt7988_i2c2_0_funcs[] = { 4, 4 };
-+
-+static const int mt7988_i2c2_1_pins[] = { 71, 72 };
-+static const int mt7988_i2c2_1_funcs[] = { 1, 1 };
-+
-+/* eth */
-+static const int mt7988_mdc_mdio0_pins[] = { 5, 6 };
-+static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
-+
-+static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
-+static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
-+
-+static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
-+static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
-+
-+static const int mt7988_mdc_mdio1_pins[] = { 69, 70 };
-+static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
-+
-+/* pcie */
-+static const int mt7988_pcie_wake_n0_0_pins[] = { 7 };
-+static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
-+static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n3_0_pins[] = { 9 };
-+static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n3_pins[] = { 10 };
-+static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
-+static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
-+static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
-+
-+static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
-+static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
-+
-+static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
-+static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
-+
-+static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
-+static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
-+static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
-+
-+static const int mt7988_pcie_wake_n0_1_pins[] = { 13 };
-+static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_wake_n3_1_pins[] = { 14 };
-+static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
-+static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
-+static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
-+static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
-+
-+static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
-+static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
-+static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n1_0_pins[] = { 75 };
-+static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n1_pins[] = { 76 };
-+static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n2_0_pins[] = { 77 };
-+static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
-+static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
-+
-+static const int mt7988_pcie_wake_n2_1_pins[] = { 79 };
-+static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
-+
-+/* pmic */
-+static const int mt7988_pmic_pins[] = { 11 };
-+static const int mt7988_pmic_funcs[] = { 1 };
-+
-+/* watchdog */
-+static const int mt7988_watchdog_pins[] = { 12 };
-+static const int mt7988_watchdog_funcs[] = { 1 };
-+
-+/* spi */
-+static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
-+static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
-+
-+static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
-+static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
-+static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
-+static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
-+static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
-+
-+/* flash */
-+static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
-+static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+
-+static const int mt7988_emmc_45_pins[] = {
-+	21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 };
-+static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
-+
-+static const int mt7988_emmc_51_pins[] = {
-+	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 };
-+static const int mt7988_emmc_51_funcs[] = {
-+	1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-+
-+/* uart */
-+static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
-+static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_tops_uart0_0_pins[] = { 22, 23 };
-+static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
-+
-+static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
-+static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
-+static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
-+static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
-+
-+static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
-+static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
-+static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
-+static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
-+
-+static const int mt7988_tops_uart1_0_pins[] = { 28, 29 };
-+static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
-+
-+static const int mt7988_tops_uart0_1_pins[] = { 30, 31 };
-+static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
-+
-+static const int mt7988_tops_uart1_1_pins[] = { 36, 37 };
-+static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
-+
-+static const int mt7988_uart0_pins[] = { 55, 56 };
-+static const int mt7988_uart0_funcs[] = { 1, 1 };
-+
-+static const int mt7988_tops_uart0_2_pins[] = { 55, 56 };
-+static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
-+
-+static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
-+static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
-+static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
-+
-+static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
-+static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
-+
-+static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
-+static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-+static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
-+
-+static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
-+static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
-+static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
-+
-+static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
-+static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
-+
-+/* udi */
-+static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
-+static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
-+
-+/* pcm */
-+static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 };
-+static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 };
-+
-+/* led */
-+static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
-+static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 };
-+
-+static const int mt7988_2p5gbe_led1_pins[] = { 62 };
-+static const int mt7988_2p5gbe_led1_funcs[] = { 6 };
-+
-+static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 };
-+static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 };
-+
-+static const int mt7988_2p5gbe_led0_pins[] = { 68 };
-+static const int mt7988_2p5gbe_led0_funcs[] = { 1 };
-+
-+/* usb */
-+static const int mt7988_drv_vbus_p1_pins[] = { 63 };
-+static const int mt7988_drv_vbus_p1_funcs[] = { 1 };
-+
-+static const int mt7988_drv_vbus_pins[] = { 79 };
-+static const int mt7988_drv_vbus_funcs[] = { 1 };
-+
-+static const struct mtk_group_desc mt7988_groups[] = {
-+	PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
-+	PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
-+	PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
-+	PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
-+	PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
-+	PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
-+	PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
-+	PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
-+	PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
-+	PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
-+	PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
-+	PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
-+	PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
-+	PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
-+	PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
-+	PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
-+	PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
-+	PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
-+	PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
-+	PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
-+	PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
-+	PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
-+	PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
-+	PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
-+	PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
-+	PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
-+	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
-+	PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
-+	PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
-+	PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
-+	PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
-+	PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
-+	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
-+	PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
-+	PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
-+	PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
-+	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
-+	PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
-+	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
-+	PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
-+	PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
-+	PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-+	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
-+	PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
-+	PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
-+	PINCTRL_PIN_GROUP("udi", mt7988_udi),
-+	PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
-+	PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
-+	PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
-+	PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
-+	PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
-+	PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
-+	PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
-+	PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
-+	PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
-+	PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
-+	PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
-+	PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
-+	PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
-+	PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
-+	PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
-+	PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
-+	PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1),
-+	PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
-+	PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0),
-+	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
-+	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
-+	PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
-+	PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
-+	PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
-+	PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
-+	PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
-+	PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
-+	PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
-+	PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
-+	PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
-+	PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
-+	PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
-+	PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
-+	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
-+	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
-+	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
-+	PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
-+	PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
-+	PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-+	PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
-+	PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
-+	PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
-+};
-+
-+static const struct mtk_io_type_desc mt7988_io_type_desc[] = {
-+	[IO_TYPE_GRP0] = {
-+		.name = "18OD33",
-+		.bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
-+		.drive_set = mtk_pinconf_drive_set_v1,
-+		.input_enable = mtk_pinconf_input_enable_v1,
-+	},
-+	[IO_TYPE_GRP1] = {
-+		.name = "18A01",
-+		.bias_set = mtk_pinconf_bias_set_pu_pd,
-+		.drive_set = mtk_pinconf_drive_set_v1,
-+		.input_enable = mtk_pinconf_input_enable_v1,
-+	},
-+	[IO_TYPE_GRP2] = {
-+		.name = "I2C",
-+		.input_enable = mtk_pinconf_input_enable_v1,
-+	},
-+};
-+
-+/* Joint those groups owning the same capability in user point of view which
-+ * allows that people tend to use through the device tree.
-+ */
-+static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag",
-+	"wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", };
-+static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", };
-+static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3",
-+	"pwm4", "pwm5", "pwm6", "pwm7" };
-+static const char *const mt7988_dfd_groups[] = { "dfd", };
-+static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0",
-+	"xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0",
-+	"i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1",
-+	"u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1",
-+	"xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1",
-+	"xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0",
-+	"i2c2_1", };
-+static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0",
-+	"2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", };
-+static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0",
-+	"pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3",
-+	"pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2",
-+	"pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1",
-+	"pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1",
-+	"pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0",
-+	"cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", };
-+static const char *const mt7988_pmic_groups[] = { "pmic", };
-+static const char *const mt7988_wdt_groups[] = { "watchdog", };
-+static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold",
-+	"spi1", "spi2", "spi2_wp_hold", };
-+static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi",
-+	"emmc_51" };
-+static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0",
-+	"uart2_0", "uart1_0", "uart2_1",
-+	"net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0",
-+	"tops_uart1_0", "ops_uart0_1", "ops_uart1_1",
-+	"uart0", "tops_uart0_2", "uart1_1",
-+	"uart2_3", "uart1_2", "tops_uart1_2",
-+	"net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", };
-+static const char *const mt7988_udi_groups[] = { "udi", };
-+static const char *const mt7988_pcm_groups[] = { "pcm", };
-+static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1",
-+	"gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", };
-+static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", };
-+
-+static const struct mtk_function_desc mt7988_functions[] = {
-+	{"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)},
-+	{"int_usxgmii", mt7988_int_usxgmii_groups,
-+			ARRAY_SIZE(mt7988_int_usxgmii_groups)},
-+	{"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)},
-+	{"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)},
-+	{"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)},
-+	{"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)},
-+	{"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)},
-+	{"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)},
-+	{"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)},
-+	{"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)},
-+	{"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)},
-+	{"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)},
-+	{"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)},
-+	{"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)},
-+	{"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)},
-+	{"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)},
-+};
-+
-+static const char *const mt7988_pinctrl_register_base_names[] = {
-+	"gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base",
-+	"iocfg_lb_base", "iocfg_tl_base",
-+};
-+
-+static const struct mtk_pinctrl_soc mt7988_data = {
-+	.name = "mt7988_pinctrl",
-+	.reg_cal = mt7988_reg_cals,
-+	.pins = mt7988_pins,
-+	.npins = ARRAY_SIZE(mt7988_pins),
-+	.grps = mt7988_groups,
-+	.ngrps = ARRAY_SIZE(mt7988_groups),
-+	.funcs = mt7988_functions,
-+	.nfuncs = ARRAY_SIZE(mt7988_functions),
-+	.io_type = mt7988_io_type_desc,
-+	.ntype = ARRAY_SIZE(mt7988_io_type_desc),
-+	.gpio_mode = 0,
-+	.base_names = mt7988_pinctrl_register_base_names,
-+	.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
-+	.base_calc = 1,
-+};
-+
-+static int mtk_pinctrl_mt7988_probe(struct udevice *dev)
-+{
-+	return mtk_pinctrl_common_probe(dev, &mt7988_data);
-+}
-+
-+static const struct udevice_id mt7988_pctrl_match[] = {
-+	{.compatible = "mediatek,mt7988-pinctrl"},
-+	{ /* sentinel */ }
-+};
-+
-+U_BOOT_DRIVER(mt7988_pinctrl) = {
-+	.name = "mt7988_pinctrl",
-+	.id = UCLASS_PINCTRL,
-+	.of_match = mt7988_pctrl_match,
-+	.ops = &mtk_pinctrl_ops,
-+	.probe = mtk_pinctrl_mt7988_probe,
-+	.priv_auto = sizeof(struct mtk_pinctrl_priv),
-+};
diff --git a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch b/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch
deleted file mode 100644
index e3e6212742..0000000000
--- a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From a0405999ebecf21ed9f76f1dc9420682cd3feba0 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:54 +0800
-Subject: [PATCH 16/29] net: mediatek: connect switch to PSE only when starting
- eth is requested
-
-So far the switch is initialized in probe stage and is connected to PSE
-unconditionally. This will cause all packets being flooded to PSE and may
-cause PSE hang before entering linux.
-
-This patch changes the connection between switch and PSE:
-- Still initialize switch in probe stage, but disconnect it with PSE
-- Connect switch with PSE on eth start
-- Disconnect on eth stop
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 44 ++++++++++++++++++++++++++++++++++++++++---
- 1 file changed, 41 insertions(+), 3 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -123,8 +123,10 @@ struct mtk_eth_priv {
- 
- 	enum mtk_switch sw;
- 	int (*switch_init)(struct mtk_eth_priv *priv);
-+	void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable);
- 	u32 mt753x_smi_addr;
- 	u32 mt753x_phy_base;
-+	u32 mt753x_pmcr;
- 
- 	struct gpio_desc rst_gpio;
- 	int mcm;
-@@ -613,6 +615,16 @@ static int mt7530_pad_clk_setup(struct m
- 	return 0;
- }
- 
-+static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
- static int mt7530_setup(struct mtk_eth_priv *priv)
- {
- 	u16 phy_addr, phy_val;
-@@ -663,11 +675,14 @@ static int mt7530_setup(struct mtk_eth_p
- 	      FORCE_DPX | FORCE_LINK;
- 
- 	/* MT7530 Port6: Forced 1000M/FD, FC disabled */
--	mt753x_reg_write(priv, PMCR_REG(6), val);
-+	priv->mt753x_pmcr = val;
- 
- 	/* MT7530 Port5: Forced link down */
- 	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
- 
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
-+
- 	/* MT7530 Port6: Set to RGMII */
- 	mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
- 
-@@ -823,6 +838,17 @@ static void mt7531_phy_setting(struct mt
- 	}
- }
- 
-+static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE_LNK;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
- static int mt7531_setup(struct mtk_eth_priv *priv)
- {
- 	u16 phy_addr, phy_val;
-@@ -882,8 +908,11 @@ static int mt7531_setup(struct mtk_eth_p
- 	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
- 	       FORCE_LINK;
- 
--	mt753x_reg_write(priv, PMCR_REG(5), pmcr);
--	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+	priv->mt753x_pmcr = pmcr;
-+
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
- 
- 	/* Turn on PHYs */
- 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-@@ -1227,6 +1256,9 @@ static int mtk_eth_start(struct udevice
- 
- 	mtk_eth_fifo_init(priv);
- 
-+	if (priv->switch_mac_control)
-+		priv->switch_mac_control(priv, true);
-+
- 	/* Start PHY */
- 	if (priv->sw == SW_NONE) {
- 		ret = mtk_phy_start(priv);
-@@ -1245,6 +1277,9 @@ static void mtk_eth_stop(struct udevice
- {
- 	struct mtk_eth_priv *priv = dev_get_priv(dev);
- 
-+	if (priv->switch_mac_control)
-+		priv->switch_mac_control(priv, false);
-+
- 	mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
- 		     TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
- 	udelay(500);
-@@ -1484,16 +1519,19 @@ static int mtk_eth_of_to_plat(struct ude
- 	/* check for switch first, otherwise phy will be used */
- 	priv->sw = SW_NONE;
- 	priv->switch_init = NULL;
-+	priv->switch_mac_control = NULL;
- 	str = dev_read_string(dev, "mediatek,switch");
- 
- 	if (str) {
- 		if (!strcmp(str, "mt7530")) {
- 			priv->sw = SW_MT7530;
- 			priv->switch_init = mt7530_setup;
-+			priv->switch_mac_control = mt7530_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 		} else if (!strcmp(str, "mt7531")) {
- 			priv->sw = SW_MT7531;
- 			priv->switch_init = mt7531_setup;
-+			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 		} else {
- 			printf("error: unsupported switch\n");
diff --git a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch b/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch
deleted file mode 100644
index c8823ac545..0000000000
--- a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From d9a52701f6677889cc3332ab7a888f35cd69cc76 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:16:59 +0800
-Subject: [PATCH 17/29] net: mediatek: optimize the switch reset delay wait
- time
-
-Not all switches requires 1 second delay after deasserting reset.
-MT7531 requires only maximum 200ms.
-
-This patch defines dedicated reset wait time for each switch chip, and will
-significantly improve the boot time for boards using MT7531.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -127,6 +127,7 @@ struct mtk_eth_priv {
- 	u32 mt753x_smi_addr;
- 	u32 mt753x_phy_base;
- 	u32 mt753x_pmcr;
-+	u32 mt753x_reset_wait_time;
- 
- 	struct gpio_desc rst_gpio;
- 	int mcm;
-@@ -943,12 +944,12 @@ int mt753x_switch_init(struct mtk_eth_pr
- 		reset_assert(&priv->rst_mcm);
- 		udelay(1000);
- 		reset_deassert(&priv->rst_mcm);
--		mdelay(1000);
-+		mdelay(priv->mt753x_reset_wait_time);
- 	} else if (dm_gpio_is_valid(&priv->rst_gpio)) {
- 		dm_gpio_set_value(&priv->rst_gpio, 0);
- 		udelay(1000);
- 		dm_gpio_set_value(&priv->rst_gpio, 1);
--		mdelay(1000);
-+		mdelay(priv->mt753x_reset_wait_time);
- 	}
- 
- 	ret = priv->switch_init(priv);
-@@ -1528,11 +1529,13 @@ static int mtk_eth_of_to_plat(struct ude
- 			priv->switch_init = mt7530_setup;
- 			priv->switch_mac_control = mt7530_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 1000;
- 		} else if (!strcmp(str, "mt7531")) {
- 			priv->sw = SW_MT7531;
- 			priv->switch_init = mt7531_setup;
- 			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 200;
- 		} else {
- 			printf("error: unsupported switch\n");
- 			return -EINVAL;
diff --git a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch b/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch
deleted file mode 100644
index 5214e842c8..0000000000
--- a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From c44f6ac1a31961b0d4faf982ee42167de5ac1672 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:03 +0800
-Subject: [PATCH 18/29] net: mediatek: fix direct MDIO clause 45 access via SoC
-
-The original direct MDIO clause 45 access via SoC is missing the
-data output. This patch adds it back to ensure MDIO clause 45 can
-work properly for external PHYs.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -198,7 +198,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
- 	      (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
- 	      (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
- 
--	if (cmd == MDIO_CMD_WRITE)
-+	if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
- 		val |= data & MDIO_RW_DATA_M;
- 
- 	mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
-@@ -210,7 +210,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
- 		return ret;
- 	}
- 
--	if (cmd == MDIO_CMD_READ) {
-+	if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
- 		val = mtk_gmac_read(priv, GMAC_PIAC_REG);
- 		return val & MDIO_RW_DATA_M;
- 	}
diff --git a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch b/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch
deleted file mode 100644
index 9350ca04dc..0000000000
--- a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 9d35558bedfb82860c63cc11d3426afcbd82cb5c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:07 +0800
-Subject: [PATCH 19/29] net: mediatek: add missing static qualifier
-
-mt7531_mmd_ind_read and mt753x_switch_init are defined without static.
-Since they're not used outside this file, we should add them back.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-
-fixup to add static qualifier
----
- drivers/net/mtk_eth.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -436,7 +436,8 @@ static int mt7531_mii_ind_write(struct m
- 			     MDIO_ST_C22);
- }
- 
--int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
-+static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
-+			       u16 reg)
- {
- 	u8 phy_addr;
- 	int ret;
-@@ -934,7 +935,7 @@ static int mt7531_setup(struct mtk_eth_p
- 	return 0;
- }
- 
--int mt753x_switch_init(struct mtk_eth_priv *priv)
-+static int mt753x_switch_init(struct mtk_eth_priv *priv)
- {
- 	int ret;
- 	int i;
diff --git a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch b/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch
deleted file mode 100644
index 45acbc36ac..0000000000
--- a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From 8e59c3cc700a6efb8db574f3c8e18b6181b4a07d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:13 +0800
-Subject: [PATCH 20/29] net: mediatek: add support for SGMII 1Gbps
- auto-negotiation mode
-
-Existing SGMII support of mtk-eth is actually a MediaTek-specific
-2.5Gbps high-speed SGMII (HSGMII) which does not support
-auto-negotiation mode.
-
-This patch adds SGMII 1Gbps auto-negotiation mode and rename the
-existing HSGMII to 2500basex.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 46 +++++++++++++++++++++++++++++++++++++------
- drivers/net/mtk_eth.h |  2 ++
- 2 files changed, 42 insertions(+), 6 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -893,7 +893,7 @@ static int mt7531_setup(struct mtk_eth_p
- 		if (!port5_sgmii)
- 			mt7531_port_rgmii_init(priv, 5);
- 		break;
--	case PHY_INTERFACE_MODE_SGMII:
-+	case PHY_INTERFACE_MODE_2500BASEX:
- 		mt7531_port_sgmii_init(priv, 6);
- 		if (port5_sgmii)
- 			mt7531_port_sgmii_init(priv, 5);
-@@ -986,6 +986,7 @@ static void mtk_phy_link_adjust(struct m
- 	      (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
- 	      MAC_MODE | FORCE_MODE |
- 	      MAC_TX_EN | MAC_RX_EN |
-+	      DEL_RXFIFO_CLR |
- 	      BKOFF_EN | BACKPR_EN;
- 
- 	switch (priv->phydev->speed) {
-@@ -996,6 +997,7 @@ static void mtk_phy_link_adjust(struct m
- 		mcr |= (SPEED_100M << FORCE_SPD_S);
- 		break;
- 	case SPEED_1000:
-+	case SPEED_2500:
- 		mcr |= (SPEED_1000M << FORCE_SPD_S);
- 		break;
- 	};
-@@ -1048,7 +1050,8 @@ static int mtk_phy_start(struct mtk_eth_
- 		return 0;
- 	}
- 
--	mtk_phy_link_adjust(priv);
-+	if (!priv->force_mode)
-+		mtk_phy_link_adjust(priv);
- 
- 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
- 	      (phydev->duplex) ? "full" : "half",
-@@ -1076,7 +1079,31 @@ static int mtk_phy_probe(struct udevice
- 	return 0;
- }
- 
--static void mtk_sgmii_init(struct mtk_eth_priv *priv)
-+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
-+{
-+	/* Set SGMII GEN1 speed(1G) */
-+	clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
-+			SGMSYS_SPEED_2500, 0);
-+
-+	/* Enable SGMII AN */
-+	setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
-+		     SGMII_AN_ENABLE);
-+
-+	/* SGMII AN mode setting */
-+	writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
-+
-+	/* SGMII PN SWAP setting */
-+	if (priv->pn_swap) {
-+		setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
-+			     SGMII_PN_SWAP_TX_RX);
-+	}
-+
-+	/* Release PHYA power down state */
-+	clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
-+			SGMII_PHYA_PWD, 0);
-+}
-+
-+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
- {
- 	/* Set SGMII GEN2 speed(2.5G) */
- 	setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
-@@ -1111,10 +1138,14 @@ static void mtk_mac_init(struct mtk_eth_
- 		ge_mode = GE_MODE_RGMII;
- 		break;
- 	case PHY_INTERFACE_MODE_SGMII:
-+	case PHY_INTERFACE_MODE_2500BASEX:
- 		ge_mode = GE_MODE_RGMII;
- 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
--		mtk_sgmii_init(priv);
-+		if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
-+			mtk_sgmii_an_init(priv);
-+		else
-+			mtk_sgmii_force_init(priv);
- 		break;
- 	case PHY_INTERFACE_MODE_MII:
- 	case PHY_INTERFACE_MODE_GMII:
-@@ -1148,6 +1179,7 @@ static void mtk_mac_init(struct mtk_eth_
- 			mcr |= SPEED_100M << FORCE_SPD_S;
- 			break;
- 		case SPEED_1000:
-+		case SPEED_2500:
- 			mcr |= SPEED_1000M << FORCE_SPD_S;
- 			break;
- 		}
-@@ -1490,13 +1522,15 @@ static int mtk_eth_of_to_plat(struct ude
- 		priv->duplex = ofnode_read_bool(subnode, "full-duplex");
- 
- 		if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
--		    priv->speed != SPEED_1000) {
-+		    priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
-+		    priv->speed != SPEED_10000) {
- 			printf("error: no valid speed set in fixed-link\n");
- 			return -EINVAL;
- 		}
- 	}
- 
--	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
-+	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
-+	    priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
- 		/* get corresponding sgmii phandle */
- 		ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
- 						 NULL, 0, 0, &args);
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -69,6 +69,7 @@ enum mkt_eth_capabilities {
- #define SGMII_AN_RESTART		BIT(9)
- 
- #define SGMSYS_SGMII_MODE		0x20
-+#define SGMII_AN_MODE			0x31120103
- #define SGMII_FORCE_MODE		0x31120019
- 
- #define SGMSYS_QPHY_PWR_STATE_CTRL	0xe8
-@@ -168,6 +169,7 @@ enum mkt_eth_capabilities {
- #define FORCE_MODE			BIT(15)
- #define MAC_TX_EN			BIT(14)
- #define MAC_RX_EN			BIT(13)
-+#define DEL_RXFIFO_CLR			BIT(12)
- #define BKOFF_EN			BIT(9)
- #define BACKPR_EN			BIT(8)
- #define FORCE_RX_FC			BIT(5)
diff --git a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch b/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch
deleted file mode 100644
index 27612fd9e4..0000000000
--- a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From 64ef7e977767e3b1305fb94a5169d8b7d3b19b6c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:18 +0800
-Subject: [PATCH 21/29] arm: dts: mediatek: convert gmac link mode to
- 2500base-x
-
-Now that individual 2.5Gbps SGMII support has been added to
-mtk-eth, all boards that use 2.5Gbps link with mt7531 must be
-converted to use "2500base-x" instead of "sgmii".
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
-[also convert BPi-R3]
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 4 ++--
- arch/arm/dts/mt7622-rfb.dts              | 4 ++--
- arch/arm/dts/mt7629-rfb.dts              | 4 ++--
- arch/arm/dts/mt7981-emmc-rfb.dts         | 4 ++--
- arch/arm/dts/mt7981-rfb.dts              | 4 ++--
- arch/arm/dts/mt7981-sd-rfb.dts           | 4 ++--
- arch/arm/dts/mt7986a-bpi-r3-sd.dts       | 4 ++--
- arch/arm/dts/mt7986a-rfb.dts             | 4 ++--
- arch/arm/dts/mt7986a-sd-rfb.dts          | 4 ++--
- arch/arm/dts/mt7986b-rfb.dts             | 4 ++--
- arch/arm/dts/mt7986b-sd-rfb.dts          | 4 ++--
- 11 files changed, 22 insertions(+), 22 deletions(-)
-
---- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
-@@ -224,12 +224,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7622-rfb.dts
-+++ b/arch/arm/dts/mt7622-rfb.dts
-@@ -240,12 +240,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7629-rfb.dts
-+++ b/arch/arm/dts/mt7629-rfb.dts
-@@ -25,12 +25,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-emmc-rfb.dts
-+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-rfb.dts
-+++ b/arch/arm/dts/mt7981-rfb.dts
-@@ -37,12 +37,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7981-sd-rfb.dts
-+++ b/arch/arm/dts/mt7981-sd-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
-@@ -76,12 +76,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-rfb.dts
-+++ b/arch/arm/dts/mt7986a-rfb.dts
-@@ -55,12 +55,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986a-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
-@@ -47,12 +47,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986b-rfb.dts
-+++ b/arch/arm/dts/mt7986b-rfb.dts
-@@ -46,12 +46,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
---- a/arch/arm/dts/mt7986b-sd-rfb.dts
-+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
-@@ -47,12 +47,12 @@
- &eth {
- 	status = "okay";
- 	mediatek,gmac-id = <0>;
--	phy-mode = "sgmii";
-+	phy-mode = "2500base-x";
- 	mediatek,switch = "mt7531";
- 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
- 
- 	fixed-link {
--		speed = <1000>;
-+		speed = <2500>;
- 		full-duplex;
- 	};
- };
diff --git a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch b/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch
deleted file mode 100644
index c7e49ff304..0000000000
--- a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:22 +0800
-Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode
- for MT7981
-
-MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
-register must be set to connect the SGMII phy to GMAC2.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h | 16 ++++++++++++++++
- 2 files changed, 48 insertions(+), 1 deletion(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -103,6 +103,8 @@ struct mtk_eth_priv {
- 
- 	struct regmap *ethsys_regmap;
- 
-+	struct regmap *infra_regmap;
-+
- 	struct mii_dev *mdio_bus;
- 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
- 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
-@@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et
- 	regmap_write(priv->ethsys_regmap, reg, val);
- }
- 
-+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
-+			  u32 set)
-+{
-+	uint val;
-+
-+	regmap_read(priv->infra_regmap, reg, &val);
-+	val &= ~clr;
-+	val |= set;
-+	regmap_write(priv->infra_regmap, reg, val);
-+}
-+
- /* Direct MDIO clause 22/45 access via SoC */
- static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
- 		      u32 cmd, u32 st)
-@@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_
- 		break;
- 	case PHY_INTERFACE_MODE_SGMII:
- 	case PHY_INTERFACE_MODE_2500BASEX:
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
-+			mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
-+				      SGMII_QPHY_SEL);
-+		}
-+
- 		ge_mode = GE_MODE_RGMII;
- 		mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
- 			       SYSCFG0_SGMII_SEL(priv->gmac_id));
-@@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude
- 	if (IS_ERR(priv->ethsys_regmap))
- 		return PTR_ERR(priv->ethsys_regmap);
- 
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
-+		/* get corresponding infracfg phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
-+						 NULL, 0, 0, &args);
-+
-+		if (ret)
-+			return ret;
-+
-+		priv->infra_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->infra_regmap))
-+			return PTR_ERR(priv->infra_regmap);
-+	}
-+
- 	/* Reset controllers */
- 	ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
- 	if (ret) {
-@@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_
- };
- 
- static const struct mtk_soc_data mt7981_data = {
--	.caps = MT7986_CAPS,
-+	.caps = MT7981_CAPS,
- 	.ana_rgc3 = 0x128,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -15,27 +15,38 @@
- enum mkt_eth_capabilities {
- 	MTK_TRGMII_BIT,
- 	MTK_TRGMII_MT7621_CLK_BIT,
-+	MTK_U3_COPHY_V2_BIT,
-+	MTK_INFRA_BIT,
- 	MTK_NETSYS_V2_BIT,
- 
- 	/* PATH BITS */
- 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
-+	MTK_ETH_PATH_GMAC2_SGMII_BIT,
- };
- 
- #define MTK_TRGMII			BIT(MTK_TRGMII_BIT)
- #define MTK_TRGMII_MT7621_CLK		BIT(MTK_TRGMII_MT7621_CLK_BIT)
-+#define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
-+#define MTK_INFRA			BIT(MTK_INFRA_BIT)
- #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
- 
- /* Supported path present on SoCs */
- #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
- 
-+#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
-+
- #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
- 
-+#define MTK_GMAC2_U3_QPHY	(MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
-+
- #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
- 
- #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
- 
- #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
- 
-+#define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
-+
- #define MT7986_CAPS  (MTK_NETSYS_V2)
- 
- /* Frame Engine Register Bases */
-@@ -56,6 +67,11 @@ enum mkt_eth_capabilities {
- #define ETHSYS_CLKCFG0_REG		0x2c
- #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
- 
-+/* Top misc registers */
-+#define USB_PHY_SWITCH_REG		0x218
-+#define QPHY_SEL_MASK			0x3
-+#define SGMII_QPHY_SEL			0x2
-+
- /* SYSCFG0_GE_MODE: GE Modes */
- #define GE_MODE_RGMII			0
- #define GE_MODE_MII			1
diff --git a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch b/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch
deleted file mode 100644
index 63c25304a0..0000000000
--- a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 64dab5fc8405005a78bdf1e0035d8b754cdf0c7e Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:27 +0800
-Subject: [PATCH 23/29] arm: dts: mediatek: add infracfg registers to support
- GMAC/USB3 Co-PHY
-
-This patch adds infracfg to eth node to support enabling GMAC2.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/dts/mt7981.dtsi
-+++ b/arch/arm/dts/mt7981.dtsi
-@@ -266,6 +266,7 @@
- 		reset-names = "fe";
- 		mediatek,ethsys = <&ethsys>;
- 		mediatek,sgmiisys = <&sgmiisys0>;
-+		mediatek,infracfg = <&topmisc>;
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 		status = "disabled";
-@@ -284,6 +285,12 @@
- 		#clock-cells = <1>;
- 	};
- 
-+	topmisc: topmisc@11d10000 {
-+		compatible = "mediatek,mt7981-topmisc", "syscon";
-+		reg = <0x11d10000 0x10000>;
-+		#clock-cells = <1>;
-+	};
-+
- 	spi0: spi@1100a000 {
- 		compatible = "mediatek,ipm-spi";
- 		reg = <0x1100a000 0x100>;
diff --git a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch b/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch
deleted file mode 100644
index 67288c749e..0000000000
--- a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch
+++ /dev/null
@@ -1,341 +0,0 @@
-From d62b483092035bc86d1db83ea4ac29bfa7bba77d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:31 +0800
-Subject: [PATCH 24/29] net: mediatek: add USXGMII support
-
-This patch adds support for USXGMII of SoC.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 230 +++++++++++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h |  24 +++++
- 2 files changed, 251 insertions(+), 3 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -105,6 +105,11 @@ struct mtk_eth_priv {
- 
- 	struct regmap *infra_regmap;
- 
-+	struct regmap *usxgmii_regmap;
-+	struct regmap *xfi_pextp_regmap;
-+	struct regmap *xfi_pll_regmap;
-+	struct regmap *toprgu_regmap;
-+
- 	struct mii_dev *mdio_bus;
- 	int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
- 	int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
-@@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk
- 	return 0;
- }
- 
-+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
-+{
-+	u16 lcl_adv = 0, rmt_adv = 0;
-+	u8 flowctrl;
-+	u32 mcr;
-+
-+	mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
-+	mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
-+
-+	if (priv->phydev->duplex) {
-+		if (priv->phydev->pause)
-+			rmt_adv = LPA_PAUSE_CAP;
-+		if (priv->phydev->asym_pause)
-+			rmt_adv |= LPA_PAUSE_ASYM;
-+
-+		if (priv->phydev->advertising & ADVERTISED_Pause)
-+			lcl_adv |= ADVERTISE_PAUSE_CAP;
-+		if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
-+			lcl_adv |= ADVERTISE_PAUSE_ASYM;
-+
-+		flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
-+
-+		if (flowctrl & FLOW_CTRL_TX)
-+			mcr |= XGMAC_FORCE_TX_FC;
-+		if (flowctrl & FLOW_CTRL_RX)
-+			mcr |= XGMAC_FORCE_RX_FC;
-+
-+		debug("rx pause %s, tx pause %s\n",
-+		      flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
-+		      flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
-+	}
-+
-+	mcr &= ~(XGMAC_TRX_DISABLE);
-+	mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
-+}
-+
- static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
- {
- 	u16 lcl_adv = 0, rmt_adv = 0;
-@@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_
- 		return 0;
- 	}
- 
--	if (!priv->force_mode)
--		mtk_phy_link_adjust(priv);
-+	if (!priv->force_mode) {
-+		if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
-+			mtk_xphy_link_adjust(priv);
-+		else
-+			mtk_phy_link_adjust(priv);
-+	}
- 
- 	debug("Speed: %d, %s duplex%s\n", phydev->speed,
- 	      (phydev->duplex) ? "full" : "half",
-@@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct
- 			SGMII_PHYA_PWD, 0);
- }
- 
-+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
-+{
-+	u32 val = 0;
-+
-+	/* Add software workaround for USXGMII PLL TCL issue */
-+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
-+		     RG_XFI_PLL_ANA_SWWA);
-+
-+	regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
-+	val |= RG_XFI_PLL_EN;
-+	regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
-+}
-+
-+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
-+{
-+	switch (priv->gmac_id) {
-+	case 1:
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
-+		break;
-+	case 2:
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
-+		regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
-+		regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
-+		break;
-+	}
-+
-+	mdelay(10);
-+}
-+
-+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
-+{
-+	regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
-+	regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
-+	ndelay(1020);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
-+	ndelay(1020);
-+	regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
-+
-+	regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
-+	regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
-+	regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
-+	regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
-+	regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
-+	regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
-+	regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
-+	regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
-+	regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
-+	regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
-+	regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
-+	udelay(150);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
-+	udelay(15);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
-+	ndelay(1020);
-+	regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
-+	udelay(100);
-+	regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
-+	regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
-+	regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
-+	udelay(400);
-+}
-+
-+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
-+{
-+	mtk_xfi_pll_enable(priv);
-+	mtk_usxgmii_reset(priv);
-+	mtk_usxgmii_setup_phya_an_10000(priv);
-+}
-+
- static void mtk_mac_init(struct mtk_eth_priv *priv)
- {
- 	int i, ge_mode = 0;
-@@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_
- 	}
- }
- 
-+static void mtk_xmac_init(struct mtk_eth_priv *priv)
-+{
-+	u32 sts;
-+
-+	switch (priv->phy_interface) {
-+	case PHY_INTERFACE_MODE_USXGMII:
-+		mtk_usxgmii_an_init(priv);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	/* Set GMAC to the correct mode */
-+	mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
-+		       SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
-+		       0);
-+
-+	if (priv->gmac_id == 1) {
-+		mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
-+			      NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
-+	} else if (priv->gmac_id == 2) {
-+		sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id));
-+		sts |= XGMAC_FORCE_LINK;
-+		mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts);
-+	}
-+
-+	/* Force GMAC link down */
-+	mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
-+}
-+
- static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
- {
- 	char *pkt_base = priv->pkt_pool;
-@@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice
- 				ARCH_DMA_MINALIGN);
- 
- 	/* Set MAC mode */
--	mtk_mac_init(priv);
-+	if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII)
-+		mtk_xmac_init(priv);
-+	else
-+		mtk_mac_init(priv);
- 
- 	/* Probe phy if switch is not specified */
- 	if (priv->sw == SW_NONE)
-@@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct ude
- 		}
- 
- 		priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
-+	} else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
-+		/* get corresponding usxgmii phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->usxgmii_regmap))
-+			return PTR_ERR(priv->usxgmii_regmap);
-+
-+		/* get corresponding xfi_pextp phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->xfi_pextp_regmap))
-+			return PTR_ERR(priv->xfi_pextp_regmap);
-+
-+		/* get corresponding xfi_pll phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->xfi_pll_regmap))
-+			return PTR_ERR(priv->xfi_pll_regmap);
-+
-+		/* get corresponding toprgu phandle */
-+		ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
-+						 NULL, 0, 0, &args);
-+		if (ret)
-+			return ret;
-+
-+		priv->toprgu_regmap = syscon_node_to_regmap(args.node);
-+		if (IS_ERR(priv->toprgu_regmap))
-+			return PTR_ERR(priv->toprgu_regmap);
- 	}
- 
- 	/* check for switch first, otherwise phy will be used */
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -68,6 +68,11 @@ enum mkt_eth_capabilities {
- #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
- 
- /* Top misc registers */
-+#define TOPMISC_NETSYS_PCS_MUX		0x84
-+#define NETSYS_PCS_MUX_MASK		GENMASK(1, 0)
-+#define MUX_G2_USXGMII_SEL		BIT(1)
-+#define MUX_HSGMII1_G1_SEL		BIT(0)
-+
- #define USB_PHY_SWITCH_REG		0x218
- #define QPHY_SEL_MASK			0x3
- #define SGMII_QPHY_SEL			0x2
-@@ -98,6 +103,15 @@ enum mkt_eth_capabilities {
- #define SGMSYS_GEN2_SPEED_V2		0x128
- #define SGMSYS_SPEED_2500		BIT(2)
- 
-+/* USXGMII subsystem config registers */
-+/* Register to control USXGMII XFI PLL digital */
-+#define XFI_PLL_DIG_GLB8		0x08
-+#define RG_XFI_PLL_EN			BIT(31)
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8		0x108
-+#define RG_XFI_PLL_ANA_SWWA		0x02283248
-+
- /* Frame Engine Registers */
- #define FE_GLO_MISC_REG			0x124
- #define PDMA_VER_V2			BIT(4)
-@@ -221,6 +235,16 @@ enum mkt_eth_capabilities {
- #define TD_DM_DRVP_S			0
- #define TD_DM_DRVP_M			0x0f
- 
-+/* XGMAC Status Registers */
-+#define XGMAC_STS(x)			(((x) == 2) ? 0x001C : 0x000C)
-+#define XGMAC_FORCE_LINK		BIT(15)
-+
-+/* XGMAC Registers */
-+#define XGMAC_PORT_MCR(x)		(0x2000 + (((x) - 1) * 0x1000))
-+#define XGMAC_TRX_DISABLE		0xf
-+#define XGMAC_FORCE_TX_FC		BIT(5)
-+#define XGMAC_FORCE_RX_FC		BIT(4)
-+
- /* MT7530 Registers */
- 
- #define PCR_REG(p)			(0x2004 + (p) * 0x100)
diff --git a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch b/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch
deleted file mode 100644
index 691b59faed..0000000000
--- a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch
+++ /dev/null
@@ -1,221 +0,0 @@
-From 7d201749cc49a58fb5e791d1e099ec3e3489e16d Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:37 +0800
-Subject: [PATCH 25/29] net: mediatek: add support for NETSYS v3
-
-This patch adds support for NETSYS v3 hardware.
-Comparing to NETSYS v2, NETSYS v3 has three GMACs.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 49 ++++++++++++++++++++++++++++++++-----------
- drivers/net/mtk_eth.h |  7 +++++++
- 2 files changed, 44 insertions(+), 12 deletions(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -76,6 +76,7 @@ enum mtk_switch {
-  * @caps			Flags shown the extra capability for the SoC
-  * @ana_rgc3:			The offset for register ANA_RGC3 related to
-  *				sgmiisys syscon
-+ * @gdma_count:			Number of GDMAs
-  * @pdma_base:			Register base of PDMA block
-  * @txd_size:			Tx DMA descriptor size.
-  * @rxd_size:			Rx DMA descriptor size.
-@@ -83,6 +84,7 @@ enum mtk_switch {
- struct mtk_soc_data {
- 	u32 caps;
- 	u32 ana_rgc3;
-+	u32 gdma_count;
- 	u32 pdma_base;
- 	u32 txd_size;
- 	u32 rxd_size;
-@@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_et
- {
- 	u32 gdma_base;
- 
--	if (no == 1)
-+	if (no == 2)
-+		gdma_base = GDMA3_BASE;
-+	else if (no == 1)
- 		gdma_base = GDMA2_BASE;
- 	else
- 		gdma_base = GDMA1_BASE;
-@@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk
- 		txd->txd1 = virt_to_phys(pkt_base);
- 		txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
- 
--		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
-+			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
-+							   15 : priv->gmac_id + 1);
-+		else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
- 			txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
- 		else
- 			txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
-@@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk
- 
- 		rxd->rxd1 = virt_to_phys(pkt_base);
- 
--		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+		if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+		    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 			rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
- 		else
- 			rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
-@@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk
- static int mtk_eth_start(struct udevice *dev)
- {
- 	struct mtk_eth_priv *priv = dev_get_priv(dev);
--	int ret;
-+	int i, ret;
- 
- 	/* Reset FE */
- 	reset_assert(&priv->rst_fe);
-@@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice
- 	reset_deassert(&priv->rst_fe);
- 	mdelay(10);
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
- 
- 	/* Packets forward to PDMA */
- 	mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
- 
--	if (priv->gmac_id == 0)
--		mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
--	else
--		mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
-+	for (i = 0; i < priv->soc->gdma_count; i++) {
-+		if (i == priv->gmac_id)
-+			continue;
-+
-+		mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
-+	}
-+
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
-+		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
-+			       GDMA_CPU_BRIDGE_EN);
-+	}
- 
- 	udelay(500);
- 
-@@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice *
- 	flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
- 			   roundup(length, ARCH_DMA_MINALIGN));
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
- 	else
- 		txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
-@@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice *
- 		return -EAGAIN;
- 	}
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
- 	else
- 		length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
-@@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevi
- 
- 	rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
- 
--	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
-+	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
-+	    MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
- 		rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
- 	else
- 		rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
-@@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct ude
- static const struct mtk_soc_data mt7986_data = {
- 	.caps = MT7986_CAPS,
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
- 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_
- static const struct mtk_soc_data mt7981_data = {
- 	.caps = MT7981_CAPS,
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V2_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma_v2),
- 	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_
- 
- static const struct mtk_soc_data mt7629_data = {
- 	.ana_rgc3 = 0x128,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_
- 
- static const struct mtk_soc_data mt7623_data = {
- 	.caps = MT7623_CAPS,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_
- 
- static const struct mtk_soc_data mt7622_data = {
- 	.ana_rgc3 = 0x2028,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_
- 
- static const struct mtk_soc_data mt7621_data = {
- 	.caps = MT7621_CAPS,
-+	.gdma_count = 2,
- 	.pdma_base = PDMA_V1_BASE,
- 	.txd_size = sizeof(struct mtk_tx_dma),
- 	.rxd_size = sizeof(struct mtk_rx_dma),
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -18,6 +18,7 @@ enum mkt_eth_capabilities {
- 	MTK_U3_COPHY_V2_BIT,
- 	MTK_INFRA_BIT,
- 	MTK_NETSYS_V2_BIT,
-+	MTK_NETSYS_V3_BIT,
- 
- 	/* PATH BITS */
- 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
-@@ -29,6 +30,7 @@ enum mkt_eth_capabilities {
- #define MTK_U3_COPHY_V2			BIT(MTK_U3_COPHY_V2_BIT)
- #define MTK_INFRA			BIT(MTK_INFRA_BIT)
- #define MTK_NETSYS_V2			BIT(MTK_NETSYS_V2_BIT)
-+#define MTK_NETSYS_V3			BIT(MTK_NETSYS_V3_BIT)
- 
- /* Supported path present on SoCs */
- #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
-@@ -52,8 +54,10 @@ enum mkt_eth_capabilities {
- /* Frame Engine Register Bases */
- #define PDMA_V1_BASE			0x0800
- #define PDMA_V2_BASE			0x6000
-+#define PDMA_V3_BASE			0x6800
- #define GDMA1_BASE			0x0500
- #define GDMA2_BASE			0x1500
-+#define GDMA3_BASE			0x0540
- #define GMAC_BASE			0x10000
- 
- /* Ethernet subsystem registers */
-@@ -153,6 +157,9 @@ enum mkt_eth_capabilities {
- #define UN_DP_S				0
- #define UN_DP_M				0x0f
- 
-+#define GDMA_EG_CTRL_REG		0x004
-+#define GDMA_CPU_BRIDGE_EN		BIT(31)
-+
- #define GDMA_MAC_LSB_REG		0x008
- 
- #define GDMA_MAC_MSB_REG		0x00c
diff --git a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
deleted file mode 100644
index 29e8649052..0000000000
--- a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
+++ /dev/null
@@ -1,327 +0,0 @@
-From 59dba9d87c9caf04a5d797af46699055a53870f4 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:41 +0800
-Subject: [PATCH 26/29] net: mediatek: add support for MediaTek MT7988 SoC
-
-This patch adds support for MediaTek MT7988.
-
-MT7988 features MediaTek NETSYS v3, including three GMACs, and two
-of them supports 10Gbps USXGMII.
-
-MT7988 embeds a MT7531 switch (not MCM) which supports accessing
-internal registers through MMIO instead of MDIO.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/net/mtk_eth.c | 158 +++++++++++++++++++++++++++++++++++++++++-
- drivers/net/mtk_eth.h |  20 ++++++
- 2 files changed, 177 insertions(+), 1 deletion(-)
-
---- a/drivers/net/mtk_eth.c
-+++ b/drivers/net/mtk_eth.c
-@@ -54,6 +54,16 @@
- 	(DP_PDMA << MC_DP_S) | \
- 	(DP_PDMA << UN_DP_S))
- 
-+#define GDMA_BRIDGE_TO_CPU \
-+	(0xC0000000 | \
-+	GDM_ICS_EN | \
-+	GDM_TCS_EN | \
-+	GDM_UCS_EN | \
-+	(DP_PDMA << MYMAC_DP_S) | \
-+	(DP_PDMA << BC_DP_S) | \
-+	(DP_PDMA << MC_DP_S) | \
-+	(DP_PDMA << UN_DP_S))
-+
- #define GDMA_FWD_DISCARD \
- 	(0x20000000 | \
- 	GDM_ICS_EN | \
-@@ -68,7 +78,8 @@
- enum mtk_switch {
- 	SW_NONE,
- 	SW_MT7530,
--	SW_MT7531
-+	SW_MT7531,
-+	SW_MT7988,
- };
- 
- /* struct mtk_soc_data -	This is the structure holding all differences
-@@ -102,6 +113,7 @@ struct mtk_eth_priv {
- 	void __iomem *fe_base;
- 	void __iomem *gmac_base;
- 	void __iomem *sgmii_base;
-+	void __iomem *gsw_base;
- 
- 	struct regmap *ethsys_regmap;
- 
-@@ -171,6 +183,11 @@ static void mtk_gdma_write(struct mtk_et
- 	writel(val, priv->fe_base + gdma_base + reg);
- }
- 
-+static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
-+{
-+	clrsetbits_le32(priv->fe_base + reg, clr, set);
-+}
-+
- static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
- {
- 	return readl(priv->gmac_base + reg);
-@@ -208,6 +225,16 @@ static void mtk_infra_rmw(struct mtk_eth
- 	regmap_write(priv->infra_regmap, reg, val);
- }
- 
-+static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
-+{
-+	return readl(priv->gsw_base + reg);
-+}
-+
-+static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
-+{
-+	writel(val, priv->gsw_base + reg);
-+}
-+
- /* Direct MDIO clause 22/45 access via SoC */
- static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
- 		      u32 cmd, u32 st)
-@@ -342,6 +369,11 @@ static int mt753x_reg_read(struct mtk_et
- {
- 	int ret, low_word, high_word;
- 
-+	if (priv->sw == SW_MT7988) {
-+		*data = mtk_gsw_read(priv, reg);
-+		return 0;
-+	}
-+
- 	/* Write page address */
- 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
- 	if (ret)
-@@ -367,6 +399,11 @@ static int mt753x_reg_write(struct mtk_e
- {
- 	int ret;
- 
-+	if (priv->sw == SW_MT7988) {
-+		mtk_gsw_write(priv, reg, data);
-+		return 0;
-+	}
-+
- 	/* Write page address */
- 	ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
- 	if (ret)
-@@ -537,6 +574,7 @@ static int mtk_mdio_register(struct udev
- 		priv->mmd_write = mtk_mmd_ind_write;
- 		break;
- 	case SW_MT7531:
-+	case SW_MT7988:
- 		priv->mii_read = mt7531_mii_ind_read;
- 		priv->mii_write = mt7531_mii_ind_write;
- 		priv->mmd_read = mt7531_mmd_ind_read;
-@@ -957,6 +995,103 @@ static int mt7531_setup(struct mtk_eth_p
- 	return 0;
- }
- 
-+static void mt7988_phy_setting(struct mtk_eth_priv *priv)
-+{
-+	u16 val;
-+	u32 i;
-+
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		/* Enable HW auto downshift */
-+		priv->mii_write(priv, i, 0x1f, 0x1);
-+		val = priv->mii_read(priv, i, PHY_EXT_REG_14);
-+		val |= PHY_EN_DOWN_SHFIT;
-+		priv->mii_write(priv, i, PHY_EXT_REG_14, val);
-+
-+		/* PHY link down power saving enable */
-+		val = priv->mii_read(priv, i, PHY_EXT_REG_17);
-+		val |= PHY_LINKDOWN_POWER_SAVING_EN;
-+		priv->mii_write(priv, i, PHY_EXT_REG_17, val);
-+	}
-+}
-+
-+static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
-+{
-+	u32 pmcr = FORCE_MODE_LNK;
-+
-+	if (enable)
-+		pmcr = priv->mt753x_pmcr;
-+
-+	mt753x_reg_write(priv, PMCR_REG(6), pmcr);
-+}
-+
-+static int mt7988_setup(struct mtk_eth_priv *priv)
-+{
-+	u16 phy_addr, phy_val;
-+	u32 pmcr;
-+	int i;
-+
-+	priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
-+
-+	priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
-+				MT753X_SMI_ADDR_MASK;
-+
-+	/* Turn off PHYs */
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
-+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
-+		phy_val |= BMCR_PDOWN;
-+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
-+	}
-+
-+	switch (priv->phy_interface) {
-+	case PHY_INTERFACE_MODE_USXGMII:
-+		/* Use CPU bridge instead of actual USXGMII path */
-+
-+		/* Set GDM1 no drop */
-+		mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
-+
-+		/* Enable GDM1 to GSW CPU bridge */
-+		mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
-+
-+		/* XGMAC force link up */
-+		mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
-+
-+		/* Setup GSW CPU bridge IPG */
-+		mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
-+			     (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
-+		break;
-+	default:
-+		printf("Error: MT7988 GSW does not support %s interface\n",
-+		       phy_string_for_interface(priv->phy_interface));
-+		break;
-+	}
-+
-+	pmcr = MT7988_FORCE_MODE |
-+	       (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
-+	       MAC_MODE | MAC_TX_EN | MAC_RX_EN |
-+	       BKOFF_EN | BACKPR_EN |
-+	       FORCE_RX_FC | FORCE_TX_FC |
-+	       (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
-+	       FORCE_LINK;
-+
-+	priv->mt753x_pmcr = pmcr;
-+
-+	/* Keep MAC link down before starting eth */
-+	mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
-+
-+	/* Turn on PHYs */
-+	for (i = 0; i < MT753X_NUM_PHYS; i++) {
-+		phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
-+		phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
-+		phy_val &= ~BMCR_PDOWN;
-+		priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
-+	}
-+
-+	mt7988_phy_setting(priv);
-+
-+	return 0;
-+}
-+
- static int mt753x_switch_init(struct mtk_eth_priv *priv)
- {
- 	int ret;
-@@ -1497,6 +1632,11 @@ static int mtk_eth_start(struct udevice
- 	}
- 
- 	if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
-+		if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
-+			mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
-+				       GDMA_BRIDGE_TO_CPU);
-+		}
-+
- 		mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
- 			       GDMA_CPU_BRIDGE_EN);
- 	}
-@@ -1845,6 +1985,12 @@ static int mtk_eth_of_to_plat(struct ude
- 			priv->switch_mac_control = mt7531_mac_control;
- 			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
- 			priv->mt753x_reset_wait_time = 200;
-+		} else if (!strcmp(str, "mt7988")) {
-+			priv->sw = SW_MT7988;
-+			priv->switch_init = mt7988_setup;
-+			priv->switch_mac_control = mt7988_mac_control;
-+			priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
-+			priv->mt753x_reset_wait_time = 50;
- 		} else {
- 			printf("error: unsupported switch\n");
- 			return -EINVAL;
-@@ -1879,6 +2025,15 @@ static int mtk_eth_of_to_plat(struct ude
- 	return 0;
- }
- 
-+static const struct mtk_soc_data mt7988_data = {
-+	.caps = MT7988_CAPS,
-+	.ana_rgc3 = 0x128,
-+	.gdma_count = 3,
-+	.pdma_base = PDMA_V3_BASE,
-+	.txd_size = sizeof(struct mtk_tx_dma_v2),
-+	.rxd_size = sizeof(struct mtk_rx_dma_v2),
-+};
-+
- static const struct mtk_soc_data mt7986_data = {
- 	.caps = MT7986_CAPS,
- 	.ana_rgc3 = 0x128,
-@@ -1930,6 +2085,7 @@ static const struct mtk_soc_data mt7621_
- };
- 
- static const struct udevice_id mtk_eth_ids[] = {
-+	{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
- 	{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
- 	{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
- 	{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
---- a/drivers/net/mtk_eth.h
-+++ b/drivers/net/mtk_eth.h
-@@ -51,6 +51,8 @@ enum mkt_eth_capabilities {
- 
- #define MT7986_CAPS  (MTK_NETSYS_V2)
- 
-+#define MT7988_CAPS  (MTK_NETSYS_V3 | MTK_INFRA)
-+
- /* Frame Engine Register Bases */
- #define PDMA_V1_BASE			0x0800
- #define PDMA_V2_BASE			0x6000
-@@ -59,6 +61,7 @@ enum mkt_eth_capabilities {
- #define GDMA2_BASE			0x1500
- #define GDMA3_BASE			0x0540
- #define GMAC_BASE			0x10000
-+#define GSW_BASE			0x20000
- 
- /* Ethernet subsystem registers */
- 
-@@ -117,6 +120,9 @@ enum mkt_eth_capabilities {
- #define RG_XFI_PLL_ANA_SWWA		0x02283248
- 
- /* Frame Engine Registers */
-+#define PSE_NO_DROP_CFG_REG		0x108
-+#define PSE_NO_DROP_GDM1		BIT(1)
-+
- #define FE_GLO_MISC_REG			0x124
- #define PDMA_VER_V2			BIT(4)
- 
-@@ -187,6 +193,17 @@ enum mkt_eth_capabilities {
- #define MDIO_RW_DATA_S			0
- #define MDIO_RW_DATA_M			0xffff
- 
-+#define GMAC_XGMAC_STS_REG		0x000c
-+#define P1_XGMAC_FORCE_LINK		BIT(15)
-+
-+#define GMAC_MAC_MISC_REG		0x0010
-+
-+#define GMAC_GSW_CFG_REG		0x0080
-+#define GSWTX_IPG_M			0xF0000
-+#define GSWTX_IPG_S			16
-+#define GSWRX_IPG_M			0xF
-+#define GSWRX_IPG_S			0
-+
- /* MDIO_CMD: MDIO commands */
- #define MDIO_CMD_ADDR			0
- #define MDIO_CMD_WRITE			1
-@@ -285,6 +302,9 @@ enum mkt_eth_capabilities {
- 					FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
- 					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
- 					FORCE_MODE_LNK
-+#define MT7988_FORCE_MODE		FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
-+					FORCE_MODE_DPX   | FORCE_MODE_SPD | \
-+					FORCE_MODE_LNK
- 
- /* MT7531 SGMII Registers */
- #define MT7531_SGMII_REG_BASE		0x5000
diff --git a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch b/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch
deleted file mode 100644
index 07620f77b3..0000000000
--- a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 757b997f1f5a958e6fec3d5aee1ff5cdf5766711 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:45 +0800
-Subject: [PATCH 27/29] tools: mtk_image: use uint32_t for ghf header magic and
- version
-
-This patch converts magic and version fields of ghf common header
-to one field with the type of uint32_t to make this header flexible
-for futher updates.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- tools/mtk_image.c | 10 ++++++----
- tools/mtk_image.h |  6 +++---
- 2 files changed, 9 insertions(+), 7 deletions(-)
-
---- a/tools/mtk_image.c
-+++ b/tools/mtk_image.c
-@@ -542,11 +542,13 @@ static void put_brom_layout_header(struc
- 	hdr->type = cpu_to_le32(type);
- }
- 
--static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
--				  int type, int ver)
-+static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size,
-+				  uint16_t type, uint8_t ver)
- {
--	memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic));
--	gfh->version = ver;
-+	uint32_t magic_version = GFH_HEADER_MAGIC |
-+				 (uint32_t)ver << GFH_HEADER_VERSION_SHIFT;
-+
-+	gfh->magic_version = cpu_to_le32(magic_version);
- 	gfh->size = cpu_to_le16(size);
- 	gfh->type = cpu_to_le16(type);
- }
---- a/tools/mtk_image.h
-+++ b/tools/mtk_image.h
-@@ -63,13 +63,13 @@ struct gen_device_header {
- 
- /* BootROM header definitions */
- struct gfh_common_header {
--	uint8_t magic[3];
--	uint8_t version;
-+	uint32_t magic_version;
- 	uint16_t size;
- 	uint16_t type;
- };
- 
--#define GFH_HEADER_MAGIC	"MMM"
-+#define GFH_HEADER_MAGIC		0x4D4D4D
-+#define GFH_HEADER_VERSION_SHIFT	24
- 
- #define GFH_TYPE_FILE_INFO	0
- #define GFH_TYPE_BL_INFO	1
diff --git a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
deleted file mode 100644
index f54a028b42..0000000000
--- a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch
+++ /dev/null
@@ -1,606 +0,0 @@
-From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:49 +0800
-Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC
-
-This patch adds basic support for MediaTek MT7988 SoC.
-This includes files that will initialize the SoC after boot and
-its device tree.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7988-u-boot.dtsi               |  25 ++
- arch/arm/dts/mt7988.dtsi                      | 391 ++++++++++++++++++
- arch/arm/mach-mediatek/Kconfig                |  13 +-
- arch/arm/mach-mediatek/Makefile               |   1 +
- arch/arm/mach-mediatek/mt7988/Makefile        |   4 +
- arch/arm/mach-mediatek/mt7988/init.c          |  63 +++
- arch/arm/mach-mediatek/mt7988/lowlevel_init.S |  30 ++
- 7 files changed, 526 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi
- create mode 100644 arch/arm/dts/mt7988.dtsi
- create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile
- create mode 100644 arch/arm/mach-mediatek/mt7988/init.c
- create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S
-
---- /dev/null
-+++ b/arch/arm/dts/mt7988-u-boot.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+&system_clk {
-+	bootph-all;
-+};
-+
-+&spi_clk {
-+	bootph-all;
-+};
-+
-+&uart0 {
-+	bootph-all;
-+};
-+
-+&uart1 {
-+	bootph-all;
-+};
-+
-+&uart2 {
-+	bootph-all;
-+};
---- /dev/null
-+++ b/arch/arm/dts/mt7988.dtsi
-@@ -0,0 +1,391 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/clock/mt7988-clk.h>
-+#include <dt-bindings/reset/mt7988-reset.h>
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	compatible = "mediatek,mt7988-rfb";
-+	interrupt-parent = <&gic>;
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	cpus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		cpu0: cpu@0 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x0>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu1: cpu@1 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x1>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu2: cpu@2 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x2>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+
-+		cpu3: cpu@3 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a73";
-+			reg = <0x3>;
-+			mediatek,hwver = <&hwver>;
-+		};
-+	};
-+
-+	system_clk: dummy40m {
-+		compatible = "fixed-clock";
-+		clock-frequency = <40000000>;
-+		#clock-cells = <0>;
-+	};
-+
-+	spi_clk: dummy208m {
-+		compatible = "fixed-clock";
-+		clock-frequency = <208000000>;
-+		#clock-cells = <0>;
-+	};
-+
-+	hwver: hwver {
-+		compatible = "mediatek,hwver", "syscon";
-+		reg = <0 0x8000000 0 0x1000>;
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupt-parent = <&gic>;
-+		clock-frequency = <13000000>;
-+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-+	};
-+
-+	watchdog: watchdog@1001c000 {
-+		compatible = "mediatek,mt7622-wdt",
-+			     "mediatek,mt6589-wdt",
-+			     "syscon";
-+		reg = <0 0x1001c000 0 0x1000>;
-+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-+		#reset-cells = <1>;
-+	};
-+
-+	gic: interrupt-controller@c000000 {
-+		compatible = "arm,gic-v3";
-+		#interrupt-cells = <3>;
-+		interrupt-parent = <&gic>;
-+		interrupt-controller;
-+		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-+		      <0 0x0c080000 0 0x200000>; /* GICR */
-+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-+	};
-+
-+	infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
-+		compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
-+		reg = <0 0x10001000 0 0x1000>;
-+		clock-parent = <&infracfg_ao>;
-+		#clock-cells = <1>;
-+	};
-+
-+	apmixedsys: apmixedsys@1001e000 {
-+		compatible = "mediatek,mt7988-fixed-plls", "syscon";
-+		reg = <0 0x1001e000 0 0x1000>;
-+		#clock-cells = <1>;
-+	};
-+
-+	topckgen: topckgen@1001b000 {
-+		compatible = "mediatek,mt7988-topckgen", "syscon";
-+		reg = <0 0x1001b000 0 0x1000>;
-+		clock-parent = <&apmixedsys>;
-+		#clock-cells = <1>;
-+	};
-+
-+	pinctrl: pinctrl@1001f000 {
-+		compatible = "mediatek,mt7988-pinctrl";
-+		reg = <0 0x1001f000 0 0x1000>,
-+		      <0 0x11c10000 0 0x1000>,
-+		      <0 0x11d00000 0 0x1000>,
-+		      <0 0x11d20000 0 0x1000>,
-+		      <0 0x11e00000 0 0x1000>,
-+		      <0 0x11f00000 0 0x1000>,
-+		      <0 0x1000b000 0 0x1000>;
-+		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
-+			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-+			    "eint";
-+		gpio: gpio-controller {
-+			gpio-controller;
-+			#gpio-cells = <2>;
-+		};
-+	};
-+
-+	sgmiisys0: syscon@10060000 {
-+		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
-+		reg = <0 0x10060000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	sgmiisys1: syscon@10070000 {
-+		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
-+		reg = <0 0x10070000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	usxgmiisys0: syscon@10080000 {
-+		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
-+		reg = <0 0x10080000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	usxgmiisys1: syscon@10081000 {
-+		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
-+		reg = <0 0x10081000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pextp0: syscon@11f20000 {
-+		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
-+		reg = <0 0x11f20000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pextp1: syscon@11f30000 {
-+		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
-+		reg = <0 0x11f30000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	xfi_pll: syscon@11f40000 {
-+		compatible = "mediatek,mt7988-xfi_pll", "syscon";
-+		reg = <0 0x11f40000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	topmisc: topmisc@11d10000 {
-+		compatible = "mediatek,mt7988-topmisc", "syscon",
-+			     "mediatek,mt7988-power-controller";
-+		reg = <0 0x11d10000 0 0x10000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	infracfg_ao: infracfg@10001000 {
-+		compatible = "mediatek,mt7988-infracfg", "syscon";
-+		reg = <0 0x10001000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+	};
-+
-+	uart0: serial@11000000 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000000 0 0x100>;
-+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O0>;
-+		status = "disabled";
-+	};
-+
-+	uart1: serial@11000100 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000100 0 0x100>;
-+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O1>;
-+		status = "disabled";
-+	};
-+
-+	uart2: serial@11000200 {
-+		compatible = "mediatek,hsuart";
-+		reg = <0 0x11000200 0 0x100>;
-+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
-+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+				  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+					 <&infracfg_ao CK_INFRA_UART_O2>;
-+		status = "disabled";
-+	};
-+
-+	i2c0: i2c@11003000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11003000 0 0x1000>,
-+		      <0 0x10217080 0 0x80>;
-+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	i2c1: i2c@11004000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11004000 0 0x1000>,
-+		      <0 0x10217100 0 0x80>;
-+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	i2c2: i2c@11005000 {
-+		compatible = "mediatek,mt7988-i2c",
-+			     "mediatek,mt7981-i2c";
-+		reg = <0 0x11005000 0 0x1000>,
-+		      <0 0x10217180 0 0x80>;
-+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-div = <1>;
-+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
-+		clock-names = "main", "dma";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
-+	pwm: pwm@10048000 {
-+		compatible = "mediatek,mt7988-pwm";
-+		reg = <0 0x10048000 0 0x1000>;
-+		#pwm-cells = <2>;
-+		clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
-+			 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
-+		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-+			      "pwm4","pwm5","pwm6","pwm7","pwm8";
-+		status = "disabled";
-+	};
-+
-+	snand: snand@11001000 {
-+		compatible = "mediatek,mt7988-snand",
-+			     "mediatek,mt7986-snand";
-+		reg = <0 0x11001000 0 0x1000>,
-+		      <0 0x11002000 0 0x1000>;
-+		reg-names = "nfi", "ecc";
-+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao CK_INFRA_SPINFI>,
-+			 <&infracfg_ao CK_INFRA_NFI>,
-+			 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
-+		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-+		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
-+				  <&topckgen CK_TOP_NFI1X_SEL>;
-+		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
-+					 <&topckgen CK_TOP_CB_M_D8>;
-+		status = "disabled";
-+	};
-+
-+	spi0: spi@1100a000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11007000 0 0x100>;
-+		clocks = <&spi_clk>,
-+			 <&spi_clk>;
-+		clock-names = "sel-clk", "spi-clk";
-+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	spi1: spi@1100b000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11008000 0 0x100>;
-+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	spi2: spi@11009000 {
-+		compatible = "mediatek,ipm-spi";
-+		reg = <0 0x11009000 0 0x100>;
-+		clocks = <&spi_clk>,
-+			 <&spi_clk>;
-+		clock-names = "sel-clk", "spi-clk";
-+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};
-+
-+	mmc0: mmc@11230000 {
-+		compatible = "mediatek,mt7988-mmc",
-+			     "mediatek,mt7986-mmc";
-+		reg = <0 0x11230000 0 0x1000>;
-+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
-+			 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
-+			 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
-+			 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
-+		clock-names = "source", "hclk", "source_cg", "axi_cg";
-+		status = "disabled";
-+	};
-+
-+	ethdma: syscon@15000000 {
-+		compatible = "mediatek,mt7988-ethdma", "syscon";
-+		reg = <0 0x15000000 0 0x20000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	ethwarp: syscon@15031000 {
-+		compatible = "mediatek,mt7988-ethwarp", "syscon";
-+		reg = <0 0x15031000 0 0x1000>;
-+		clock-parent = <&topckgen>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	eth: ethernet@15100000 {
-+		compatible = "mediatek,mt7988-eth", "syscon";
-+		reg = <0 0x15100000 0 0x20000>;
-+		mediatek,ethsys = <&ethdma>;
-+		mediatek,sgmiisys = <&sgmiisys0>;
-+		mediatek,usxgmiisys = <&usxgmiisys0>;
-+		mediatek,xfi_pextp = <&xfi_pextp0>;
-+		mediatek,xfi_pll = <&xfi_pll>;
-+		mediatek,infracfg = <&topmisc>;
-+		mediatek,toprgu = <&watchdog>;
-+		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
-+		reset-names = "fe", "mcm";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		mediatek,mcm;
-+		status = "disabled";
-+	};
-+};
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -58,6 +58,15 @@ config TARGET_MT7986
- 	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
- 	  Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
- 
-+config TARGET_MT7988
-+	bool "MediaTek MT7988 SoC"
-+	select ARM64
-+	select CPU
-+	help
-+	  The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
-+	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
-+	  10 Gigabit Ethernet , I2C, and PCIe.
-+
- config TARGET_MT8183
- 	bool "MediaTek MT8183 SoC"
- 	select ARM64
-@@ -104,6 +113,7 @@ config SYS_BOARD
- 	default "mt7629" if TARGET_MT7629
- 	default "mt7981" if TARGET_MT7981
- 	default "mt7986" if TARGET_MT7986
-+	default "mt7988" if TARGET_MT7988
- 	default "mt8183" if TARGET_MT8183
- 	default "mt8512" if TARGET_MT8512
- 	default "mt8516" if TARGET_MT8516
-@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
- 	default "mt7629" if TARGET_MT7629
- 	default "mt7981" if TARGET_MT7981
- 	default "mt7986" if TARGET_MT7986
-+	default "mt7988" if TARGET_MT7988
- 	default "mt8183" if TARGET_MT8183
- 	default "mt8512" if TARGET_MT8512
- 	default "mt8516" if TARGET_MT8516
-@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
- 	string
- 	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
- 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
--	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
-+	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
- 	default "lk=1" if TARGET_MT7623
- 
- source "board/mediatek/mt7629/Kconfig"
---- a/arch/arm/mach-mediatek/Makefile
-+++ b/arch/arm/mach-mediatek/Makefile
-@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
- obj-$(CONFIG_TARGET_MT7629) += mt7629/
- obj-$(CONFIG_TARGET_MT7981) += mt7981/
- obj-$(CONFIG_TARGET_MT7986) += mt7986/
-+obj-$(CONFIG_TARGET_MT7988) += mt7988/
- obj-$(CONFIG_TARGET_MT8183) += mt8183/
- obj-$(CONFIG_TARGET_MT8516) += mt8516/
- obj-$(CONFIG_TARGET_MT8518) += mt8518/
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y += init.o
-+obj-y += lowlevel_init.o
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/init.c
-@@ -0,0 +1,63 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <fdtdec.h>
-+#include <init.h>
-+#include <asm/armv8/mmu.h>
-+#include <asm/global_data.h>
-+#include <asm/u-boot.h>
-+#include <asm/system.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+#define SZ_8G				_AC(0x200000000, ULL)
-+
-+int dram_init(void)
-+{
-+	int ret;
-+
-+	ret = fdtdec_setup_mem_size_base();
-+	if (ret)
-+		return ret;
-+
-+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
-+
-+	return 0;
-+}
-+
-+int dram_init_banksize(void)
-+{
-+	gd->bd->bi_dram[0].start = gd->ram_base;
-+	gd->bd->bi_dram[0].size = gd->ram_size;
-+
-+	return 0;
-+}
-+
-+void reset_cpu(ulong addr)
-+{
-+	psci_system_reset();
-+}
-+
-+static struct mm_region mt7988_mem_map[] = {
-+	{
-+		/* DDR */
-+		.virt = 0x40000000UL,
-+		.phys = 0x40000000UL,
-+		.size = 0x200000000ULL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
-+	}, {
-+		.virt = 0x00000000UL,
-+		.phys = 0x00000000UL,
-+		.size = 0x40000000UL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-+			 PTE_BLOCK_NON_SHARE |
-+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-+	}, {
-+		0,
-+	}
-+};
-+
-+struct mm_region *mem_map = mt7988_mem_map;
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
-@@ -0,0 +1,30 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2020 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/*
-+ * Switch from AArch64 EL2 to AArch32 EL2
-+ * @param inputs:
-+ * x0: argument, zero
-+ * x1: machine nr
-+ * x2: fdt address
-+ * x3: input argument
-+ * x4: kernel entry point
-+ * @param outputs for secure firmware:
-+ * x0: function id
-+ * x1: kernel entry point
-+ * x2: machine nr
-+ * x3: fdt address
-+*/
-+
-+.global armv8_el2_to_aarch32
-+armv8_el2_to_aarch32:
-+	mov     x3, x2
-+	mov     x2, x1
-+	mov     x1, x4
-+	mov	x4, #0
-+	ldr x0, =0x82000200
-+	SMC #0
-+	ret
diff --git a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch
deleted file mode 100644
index ef41f4d56a..0000000000
--- a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch
+++ /dev/null
@@ -1,575 +0,0 @@
-From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 19 Jul 2023 17:17:54 +0800
-Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards
-
-This patch adds general board files based on MT7988 SoCs.
-
-MT7988 uses one mmc controller for booting from both SD and eMMC,
-and the pins of mmc controller booting from SD are also shared with
-one of spi controllers.
-So two configs are need for these boot types:
-
-1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC
-2. mt7988_sd_rfb_defconfig - SPI-NAND and SD
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/Makefile              |   2 +
- arch/arm/dts/mt7988-rfb.dts        | 182 +++++++++++++++++++++++++++++
- arch/arm/dts/mt7988-sd-rfb.dts     | 134 +++++++++++++++++++++
- board/mediatek/mt7988/MAINTAINERS  |   7 ++
- board/mediatek/mt7988/Makefile     |   3 +
- board/mediatek/mt7988/mt7988_rfb.c |  10 ++
- configs/mt7988_rfb_defconfig       |  83 +++++++++++++
- configs/mt7988_sd_rfb_defconfig    |  71 +++++++++++
- include/configs/mt7988.h           |  14 +++
- 9 files changed, 506 insertions(+)
- create mode 100644 arch/arm/dts/mt7988-rfb.dts
- create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts
- create mode 100644 board/mediatek/mt7988/MAINTAINERS
- create mode 100644 board/mediatek/mt7988/Makefile
- create mode 100644 board/mediatek/mt7988/mt7988_rfb.c
- create mode 100644 configs/mt7988_rfb_defconfig
- create mode 100644 configs/mt7988_sd_rfb_defconfig
- create mode 100644 include/configs/mt7988.h
-
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
- 	mt7986b-sd-rfb.dtb \
- 	mt7986a-emmc-rfb.dtb \
- 	mt7986b-emmc-rfb.dtb \
-+	mt7988-rfb.dtb \
-+	mt7988-sd-rfb.dtb \
- 	mt8183-pumpkin.dtb \
- 	mt8512-bm1-emmc.dtb \
- 	mt8516-pumpkin.dtb \
---- /dev/null
-+++ b/arch/arm/dts/mt7988-rfb.dts
-@@ -0,0 +1,182 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include "mt7988.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	model = "mt7988-rfb";
-+	compatible = "mediatek,mt7988-rfb";
-+
-+	chosen {
-+		stdout-path = &uart0;
-+	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0 0x40000000 0 0x10000000>;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-1.8V";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+	mediatek,gmac-id = <0>;
-+	phy-mode = "usxgmii";
-+	mediatek,switch = "mt7988";
-+
-+	fixed-link {
-+		speed = <1000>;
-+		full-duplex;
-+		pause;
-+	};
-+};
-+
-+&pinctrl {
-+	i2c1_pins: i2c1-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c1_0";
-+		};
-+	};
-+
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
-+				 "pwm5", "pwm6", "pwm7";
-+		};
-+	};
-+
-+	spi0_pins: spi0-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	spi2_pins: spi2-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi2", "spi2_wp_hold";
-+		};
-+	};
-+
-+	mmc0_pins_default: mmc0default {
-+		mux {
-+			function = "flash";
-+			groups =  "emmc_51";
-+		};
-+
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+		};
-+
-+		conf-clk {
-+			pins = "EMMC_CK";
-+		};
-+
-+		conf-dsl {
-+			pins = "EMMC_DSL";
-+		};
-+
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&spi2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi2_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nor@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	max-frequency = <52000000>;
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	cap-mmc-hw-reset;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_1p8v>;
-+	non-removable;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/arch/arm/dts/mt7988-sd-rfb.dts
-@@ -0,0 +1,134 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+#include "mt7988.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	model = "mt7988-rfb";
-+	compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
-+
-+	chosen {
-+		stdout-path = &uart0;
-+	};
-+
-+	memory@40000000 {
-+		device_type = "memory";
-+		reg = <0 0x40000000 0 0x10000000>;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+	mediatek,gmac-id = <0>;
-+	phy-mode = "usxgmii";
-+	mediatek,switch = "mt7988";
-+
-+	fixed-link {
-+		speed = <1000>;
-+		full-duplex;
-+		pause;
-+	};
-+};
-+
-+&pinctrl {
-+	i2c1_pins: i2c1-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c1_0";
-+		};
-+	};
-+
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
-+				 "pwm5", "pwm6", "pwm7";
-+		};
-+	};
-+
-+	spi0_pins: spi0-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	mmc1_pins_default: mmc1default {
-+		mux {
-+			function = "flash";
-+			groups =  "emmc_45";
-+		};
-+
-+		conf-cmd-dat {
-+			pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
-+			       "SPI2_CLK", "SPI2_HOLD";
-+			input-enable;
-+		};
-+
-+		conf-clk {
-+			pins = "SPI2_WP";
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+	must_tx;
-+	enhance_timing;
-+	dma_ext;
-+	ipm_design;
-+	support_quad;
-+	tick_dly = <2>;
-+	sample_sel = <0>;
-+
-+	spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <52000000>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc1_pins_default>;
-+	max-frequency = <52000000>;
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_3p3v>;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/board/mediatek/mt7988/MAINTAINERS
-@@ -0,0 +1,7 @@
-+MT7988
-+M:	Sam Shih <sam.shih@mediatek.com>
-+S:	Maintained
-+F:	board/mediatek/mt7988
-+F:	include/configs/mt7988.h
-+F:	configs/mt7988_rfb_defconfig
-+F:	configs/mt7988_sd_rfb_defconfig
---- /dev/null
-+++ b/board/mediatek/mt7988/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y	+= mt7988_rfb.o
---- /dev/null
-+++ b/board/mediatek/mt7988/mt7988_rfb.c
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+int board_init(void)
-+{
-+	return 0;
-+}
---- /dev/null
-+++ b/configs/mt7988_rfb_defconfig
-@@ -0,0 +1,83 @@
-+CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_POSITION_INDEPENDENT=y
-+CONFIG_ARCH_MEDIATEK=y
-+CONFIG_TEXT_BASE=0x41e00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
-+CONFIG_SYS_PROMPT="MT7988> "
-+CONFIG_TARGET_MT7988=y
-+CONFIG_DEBUG_UART_BASE=0x11000000
-+CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_SYS_LOAD_ADDR=0x50000000
-+CONFIG_DEBUG_UART=y
-+# CONFIG_AUTOBOOT is not set
-+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_LOG=y
-+CONFIG_SYS_CBSIZE=512
-+CONFIG_SYS_PBSIZE=1049
-+# CONFIG_BOOTM_NETBSD is not set
-+# CONFIG_BOOTM_PLAN9 is not set
-+# CONFIG_BOOTM_RTEMS is not set
-+# CONFIG_BOOTM_VXWORKS is not set
-+# CONFIG_CMD_ELF is not set
-+CONFIG_CMD_CLK=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_SMC=y
-+CONFIG_DOS_PARTITION=y
-+CONFIG_EFI_PARTITION=y
-+CONFIG_PARTITION_TYPE_GUID=y
-+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_NETMASK=y
-+CONFIG_NETMASK="255.255.255.0"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.2"
-+CONFIG_PROT_TCP=y
-+CONFIG_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_DM_SPI_FLASH=y
-+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-+CONFIG_SPI_FLASH_EON=y
-+CONFIG_SPI_FLASH_GIGADEVICE=y
-+CONFIG_SPI_FLASH_ISSI=y
-+CONFIG_SPI_FLASH_MACRONIX=y
-+CONFIG_SPI_FLASH_SPANSION=y
-+CONFIG_SPI_FLASH_STMICRO=y
-+CONFIG_SPI_FLASH_WINBOND=y
-+CONFIG_SPI_FLASH_XMC=y
-+CONFIG_SPI_FLASH_XTX=y
-+CONFIG_SPI_FLASH_MTD=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_MEDIATEK_ETH=y
-+CONFIG_PINCTRL=y
-+CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7988=y
-+CONFIG_POWER_DOMAIN=y
-+CONFIG_MTK_POWER_DOMAIN=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_MTK_SERIAL=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
-+CONFIG_LZO=y
-+CONFIG_HEXDUMP=y
-+# CONFIG_EFI_LOADER is not set
---- /dev/null
-+++ b/configs/mt7988_sd_rfb_defconfig
-@@ -0,0 +1,71 @@
-+CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_POSITION_INDEPENDENT=y
-+CONFIG_ARCH_MEDIATEK=y
-+CONFIG_TEXT_BASE=0x41e00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
-+CONFIG_SYS_PROMPT="MT7988> "
-+CONFIG_TARGET_MT7988=y
-+CONFIG_DEBUG_UART_BASE=0x11000000
-+CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_SYS_LOAD_ADDR=0x50000000
-+CONFIG_DEBUG_UART=y
-+# CONFIG_AUTOBOOT is not set
-+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_LOG=y
-+CONFIG_SYS_CBSIZE=512
-+CONFIG_SYS_PBSIZE=1049
-+# CONFIG_BOOTM_NETBSD is not set
-+# CONFIG_BOOTM_PLAN9 is not set
-+# CONFIG_BOOTM_RTEMS is not set
-+# CONFIG_BOOTM_VXWORKS is not set
-+# CONFIG_CMD_ELF is not set
-+CONFIG_CMD_CLK=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_SMC=y
-+CONFIG_DOS_PARTITION=y
-+CONFIG_EFI_PARTITION=y
-+CONFIG_PARTITION_TYPE_GUID=y
-+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_NETMASK=y
-+CONFIG_NETMASK="255.255.255.0"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.2"
-+CONFIG_PROT_TCP=y
-+CONFIG_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_MEDIATEK_ETH=y
-+CONFIG_PINCTRL=y
-+CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7988=y
-+CONFIG_POWER_DOMAIN=y
-+CONFIG_MTK_POWER_DOMAIN=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_MTK_SERIAL=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
-+CONFIG_LZO=y
-+CONFIG_HEXDUMP=y
-+# CONFIG_EFI_LOADER is not set
---- /dev/null
-+++ b/include/configs/mt7988.h
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Configuration for MediaTek MT7988 SoC
-+ *
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#ifndef __MT7988_H
-+#define __MT7988_H
-+
-+#define CFG_MAX_MEM_MAPPED		0xC0000000
-+
-+#endif
diff --git a/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch b/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch
deleted file mode 100644
index 3cfc684956..0000000000
--- a/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7 Mon Sep 17 00:00:00 2001
-Message-ID: <4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7.1690828424.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 31 Jul 2023 19:25:04 +0100
-Subject: [PATCH] ram: mediatek: include <linux/sizes.h> for SZ_* macros
-To: Ryder Lee <ryder.lee@mediatek.com>,
-    Weijie Gao <weijie.gao@mediatek.com>,
-    Chunfeng Yun <chunfeng.yun@mediatek.com>,
-    GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
-    u-boot@lists.denx.de
-
-Something between U-Boot 2023.04 and 2023.07.02 resulted in no longer
-implicitely including <linux/sizes.h> in the DDR3 RAM driver for the
-MT7929 SoC. The result is a build failure:
-drivers/ram/mediatek/ddr3-mt7629.c: In function 'mtk_ddr3_get_info':
-drivers/ram/mediatek/ddr3-mt7629.c:734:30: error: 'SZ_128M' undeclared (first use in this function)
-  734 |                 info->size = SZ_128M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:734:30: note: each undeclared identifier is reported only once for each function it appears in
-drivers/ram/mediatek/ddr3-mt7629.c:737:30: error: 'SZ_256M' undeclared (first use in this function)
-  737 |                 info->size = SZ_256M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:740:30: error: 'SZ_512M' undeclared (first use in this function)
-  740 |                 info->size = SZ_512M;
-      |                              ^~~~~~~
-drivers/ram/mediatek/ddr3-mt7629.c:743:30: error: 'SZ_1G' undeclared (first use in this function)
-  743 |                 info->size = SZ_1G;
-      |                              ^~~~~
-
-Include <linux/sizes.h> so SZ_* is defined.
-
-Reported-by: Tianling Shen <cnsztl@immortalwrt.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/ram/mediatek/ddr3-mt7629.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/ram/mediatek/ddr3-mt7629.c
-+++ b/drivers/ram/mediatek/ddr3-mt7629.c
-@@ -14,6 +14,7 @@
- #include <asm/io.h>
- #include <linux/bitops.h>
- #include <linux/delay.h>
-+#include <linux/sizes.h>
- 
- /* EMI */
- #define EMI_CONA			0x000
diff --git a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
index a34dcddd71..747aa2e5da 100644
--- a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
+++ b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm/dts/mt7988.dtsi
 +++ b/arch/arm/dts/mt7988.dtsi
-@@ -61,6 +61,30 @@
+@@ -62,6 +62,30 @@
  		#clock-cells = <0>;
  	};
  
diff --git a/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch b/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch
deleted file mode 100644
index f047518852..0000000000
--- a/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From patchwork Mon Aug 21 19:38:23 2023
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 1823742
-X-Patchwork-Delegate: trini@ti.com
-Return-Path: <u-boot-bounces@lists.denx.de>
-X-Original-To: incoming@patchwork.ozlabs.org
-Delivered-To: patchwork-incoming@legolas.ozlabs.org
-Date: Mon, 21 Aug 2023 20:38:23 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: Sam Shih <sam.shih@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>,
- Lorenzo Bianconi <lorenzo@kernel.org>, u-boot@lists.denx.de
-Subject: [PATCH] configs: set CONFIG_LMB_MAX_REGIONS=64 for MT7988 boards
-Message-ID: 
- <568a8030acf9056266b5c96055cea54f810496c9.1692646620.git.daniel@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-BeenThere: u-boot@lists.denx.de
-X-Mailman-Version: 2.1.39
-Precedence: list
-List-Id: U-Boot discussion <u-boot.lists.denx.de>
-List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
-List-Archive: <https://lists.denx.de/pipermail/u-boot/>
-List-Post: <mailto:u-boot@lists.denx.de>
-List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
-List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=subscribe>
-Errors-To: u-boot-bounces@lists.denx.de
-Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
-
-Similar to MT7981 and MT7986 also MT7988 can have a high number of
-reserved-memory regions used by the various hardware offloading
-subsystems.
-
-Raise CONFIG_LMB_MAX_REGIONS to 64 to avoid errors when trying to boot
-Linux with more then 6 reserved regions:
-
-ERROR: reserving fdt memory region failed (addr=4f700000 size=240000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15194000 size=1000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15294000 size=1000 flags=4)
-ERROR: reserving fdt memory region failed (addr=15394000 size=1000 flags=4)
-ERROR: Failed to allocate 0xb161 bytes below 0x80000000.
-device tree - allocation error
-
-Fixes: bc4adc97cfb ("board: mediatek: add MT7988 reference boards")
-Reported-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- configs/mt7988_rfb_defconfig    | 1 +
- configs/mt7988_sd_rfb_defconfig | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/configs/mt7988_rfb_defconfig
-+++ b/configs/mt7988_rfb_defconfig
-@@ -81,3 +81,4 @@ CONFIG_MTK_SPIM=y
- CONFIG_LZO=y
- CONFIG_HEXDUMP=y
- # CONFIG_EFI_LOADER is not set
-+CONFIG_LMB_MAX_REGIONS=64
---- a/configs/mt7988_sd_rfb_defconfig
-+++ b/configs/mt7988_sd_rfb_defconfig
-@@ -69,3 +69,4 @@ CONFIG_MTK_SPIM=y
- CONFIG_LZO=y
- CONFIG_HEXDUMP=y
- # CONFIG_EFI_LOADER is not set
-+CONFIG_LMB_MAX_REGIONS=64
diff --git a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
index c7dcf9a1ba..da1d985688 100644
--- a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
+++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
@@ -1,8 +1,8 @@
 --- a/configs/mt7988_sd_rfb_defconfig
 +++ b/configs/mt7988_sd_rfb_defconfig
-@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
  CONFIG_DEBUG_UART_CLOCK=40000000
- CONFIG_SYS_LOAD_ADDR=0x50000000
+ CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
 +CONFIG_OF_LIBFDT_OVERLAY=y
 +CONFIG_SMBIOS_PRODUCT_NAME=""
@@ -157,9 +157,9 @@
  CONFIG_MTD=y
 --- a/configs/mt7988_rfb_defconfig
 +++ b/configs/mt7988_rfb_defconfig
-@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
  CONFIG_DEBUG_UART_CLOCK=40000000
- CONFIG_SYS_LOAD_ADDR=0x50000000
+ CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
 +CONFIG_OF_LIBFDT_OVERLAY=y
 +CONFIG_SMBIOS_PRODUCT_NAME=""
diff --git a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
index f5234ea085..bd4c6b55f0 100644
--- a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
+++ b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7981_emmc_rfb_defconfig
 +++ b/configs/mt7981_emmc_rfb_defconfig
-@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
@@ -87,7 +87,7 @@
  CONFIG_CLK=y
 --- a/configs/mt7981_rfb_defconfig
 +++ b/configs/mt7981_rfb_defconfig
-@@ -12,7 +12,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -11,7 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
@@ -191,7 +191,7 @@
  CONFIG_MTD_SPI_NAND=y
 --- a/configs/mt7981_sd_rfb_defconfig
 +++ b/configs/mt7981_sd_rfb_defconfig
-@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
+@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000
  CONFIG_DEBUG_UART_CLOCK=40000000
  CONFIG_SYS_LOAD_ADDR=0x46000000
  CONFIG_DEBUG_UART=y
diff --git a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
index 2d61d6f4a7..3bf033f814 100644
--- a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
+++ b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch
@@ -5,6 +5,6 @@
  			imx8image.o \
  			imx8mimage.o \
 -			kwbimage.o \
- 			lib/md5.o \
+ 			generated/lib/md5.o \
  			lpc32xximage.o \
  			mxsimage.o \
diff --git a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
index 411f99467b..9a9224963d 100644
--- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
+++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -1070,7 +1070,7 @@ quiet_cmd_pad_cat = CAT     $@
+@@ -1083,7 +1083,7 @@ quiet_cmd_pad_cat = CAT     $@
  cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
  
  quiet_cmd_lzma = LZMA    $@
diff --git a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
index cd65c1321f..86a424e8b7 100644
--- a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
+++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch
@@ -1,6 +1,6 @@
 --- a/tools/image-host.c
 +++ b/tools/image-host.c
-@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
+@@ -1137,6 +1137,7 @@ static int fit_config_add_verification_d
   * 2) get public key (X509_get_pubkey)
   * 3) provide der format (d2i_RSAPublicKey)
   */
@@ -8,7 +8,7 @@
  static int read_pub_key(const char *keydir, const void *name,
  			unsigned char **pubkey, int *pubkey_len)
  {
-@@ -1178,6 +1179,13 @@ err_cert:
+@@ -1190,6 +1191,13 @@ err_cert:
  	fclose(f);
  	return ret;
  }
diff --git a/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch b/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch
deleted file mode 100644
index c4e0fff921..0000000000
--- a/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 41f225dae30ea6ddcff10f120a9e732f994d3a07 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nicol=C3=B2=20Veronese?= <nicveronese@gmail.com>
-Date: Tue, 3 Oct 2023 23:46:52 +0200
-Subject: [PATCH] spi: mtk_spim: prevent global pll clock override
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-With commit 793e6230118032a099ec42a1ea67f434721edcc0
- a new system to calculate the SPI clocks has been added.
-
-Unfortunately, the do_div macro overrides the global
- priv->pll_clk_rate field. This will cause to have a reduced
- clock rate on each subsequent SPI call.
-
-Signed-off-by: Valerio 'ftp21' Mancini <ftp21@ftp21.eu>
-Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
----
- drivers/spi/mtk_spim.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/spi/mtk_spim.c
-+++ b/drivers/spi/mtk_spim.c
-@@ -409,7 +409,7 @@ static int mtk_spim_transfer_wait(struct
- {
- 	struct udevice *bus = dev_get_parent(slave->dev);
- 	struct mtk_spim_priv *priv = dev_get_priv(bus);
--	u32 sck_l, sck_h, clk_count, reg;
-+	u32 pll_clk, sck_l, sck_h, clk_count, reg;
- 	ulong us = 1;
- 	int ret = 0;
- 
-@@ -418,11 +418,12 @@ static int mtk_spim_transfer_wait(struct
- 	else
- 		clk_count = op->data.nbytes;
- 
-+	pll_clk = priv->pll_clk_rate;
- 	sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
- 	sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
--	do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
-+	do_div(pll_clk, sck_l + sck_h + 2);
- 
--	us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
-+	us = CLK_TO_US(pll_clk, clk_count * 8);
- 	us += 1000 * 1000; /* 1s tolerance */
- 
- 	if (us > UINT_MAX)
diff --git a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
index 67405eb15a..f8e8659952 100644
--- a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
+++ b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
@@ -58,7 +58,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -77,6 +77,21 @@ config PHY_ADIN
+@@ -77,6 +77,37 @@ config PHY_ADIN
  	help
  		Add support for configuring RGMII on Analog Devices ADIN PHYs.
  
@@ -76,6 +76,22 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +	depends on PHY_AIROHA
 +	help
 +		AIROHA EN8811H supported.
++
++choice
++	prompt "Location of the Airoha PHY firmware"
++	default PHY_AIROHA_FW_IN_UBI
++	depends on PHY_AIROHA_EN8811H
++
++config PHY_AIROHA_FW_IN_MMC
++	bool "Airoha firmware in MMC boot1 partition"
++
++config PHY_AIROHA_FW_IN_UBI
++	bool "Airoha firmware in UBI volume en8811h-fw on NAND flash"
++
++config PHY_AIROHA_FW_IN_MTD
++	bool "Airoha firmware in MTD partition on raw flash"
++
++endchoice
 +
  menuconfig PHY_AQUANTIA
  	bool "Aquantia Ethernet PHYs support"
@@ -727,7 +743,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +    return 0;
 +}
 +#endif
-\ No newline at end of file
 --- /dev/null
 +++ b/drivers/net/phy/air_en8801s.h
 @@ -0,0 +1,267 @@
@@ -997,10 +1012,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +unsigned long airoha_pbus_read(struct mii_dev *bus, int pbus_addr, int pbus_reg);
 +int airoha_pbus_write(struct mii_dev *bus, int pbus_addr, int pbus_reg, unsigned long pbus_data);
 +int airoha_phy_process(void);
-+#endif /* __AIROHA_H */
++#endif /* __EN8801S_H */
 --- /dev/null
 +++ b/drivers/net/phy/air_en8811h.c
-@@ -0,0 +1,649 @@
+@@ -0,0 +1,725 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*************************************************
 + * FILE NAME:  air_en8811h.c
@@ -1014,11 +1029,24 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +/* INCLUDE FILE DECLARATIONS
 +*/
 +#include <common.h>
++#include <eth_phy.h>
 +#include <phy.h>
 +#include <errno.h>
++#include <malloc.h>
 +#include <version.h>
 +#include "air_en8811h.h"
-+#include "air_en8811h_fw.h"
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_UBI
++#include <ubi_uboot.h>
++#endif
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_MMC
++#include <mmc.h>
++#endif
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_MTD
++#include <mtd.h>
++#endif
 +
 +#if AIR_UBOOT_REVISION > 0x202004
 +#include <linux/delay.h>
@@ -1330,7 +1358,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +
 +static int en8811h_led_init(struct phy_device *phydev)
 +{
-+
 +    unsigned int led_gpio = 0, reg_value = 0;
 +    u16 cl45_data = led_dur;
 +    int ret, led_id;
@@ -1380,10 +1407,69 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +}
 +#endif /* AIR_LED_SUPPORT */
 +
++static char *firmware_buf;
 +static int en8811h_load_firmware(struct phy_device *phydev)
 +{
++    u32 pbus_value;
 +    int ret = 0;
-+    u32 pbus_value = 0;
++
++    if (!firmware_buf) {
++        firmware_buf = malloc(EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE);
++        if (!firmware_buf) {
++            printf("[Airoha] cannot allocated buffer for firmware.\n");
++            return -ENOMEM;
++        }
++
++#ifdef CONFIG_PHY_AIROHA_FW_IN_UBI
++        ret = ubi_volume_read("en8811h-fw", firmware_buf, EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE);
++        if (ret) {
++            printf("[Airoha] read firmware from UBI failed.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return ret;
++        }
++#elif defined(CONFIG_PHY_AIROHA_FW_IN_MMC)
++        struct mmc *mmc = find_mmc_device(0);
++        if (!mmc) {
++            printf("[Airoha] opening MMC device failed.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -ENODEV;
++        }
++        if (mmc_init(mmc)) {
++            printf("[Airoha] initializing MMC device failed.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -ENODEV;
++        }
++        if (IS_SD(mmc)) {
++            printf("[Airoha] SD card is not supported.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -EINVAL;
++        }
++        ret = mmc_set_part_conf(mmc, 1, 2, 2);
++        if (ret) {
++            printf("[Airoha] cannot access eMMC boot1 hw partition.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return ret;
++        }
++        ret = blk_dread(mmc_get_blk_desc(mmc), 0, 0x120, firmware_buf);
++        mmc_set_part_conf(mmc, 1, 1, 0);
++        if (ret != 0x120) {
++            printf("[Airoha] cannot read firmware from eMMC.\n");
++            free(firmware_buf);
++            firmware_buf = NULL;
++            return -EIO;
++        }
++#else
++#warning EN8811H firmware loading not implemented
++        free(firmware_buf);
++        firmware_buf = NULL;
++        return -EOPNOTSUPP;
++#endif
++    }
 +
 +    ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x0);
 +    if (ret < 0)
@@ -1394,13 +1480,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +    if (ret < 0)
 +        return ret;
 +    /* Download DM */
-+    ret = MDIOWriteBuf(phydev, 0x00000000, EthMD32_dm_size, EthMD32_dm);
++    ret = MDIOWriteBuf(phydev, 0x00000000, EN8811H_MD32_DM_SIZE, firmware_buf);
 +    if (ret < 0) {
 +        printf("[Airoha] MDIOWriteBuf 0x00000000 fail.\n");
 +        return ret;
 +    }
 +    /* Download PM */
-+    ret = MDIOWriteBuf(phydev, 0x00100000, EthMD32_pm_size, EthMD32_pm);
++    ret = MDIOWriteBuf(phydev, 0x00100000, EN8811H_MD32_DSP_SIZE, firmware_buf + EN8811H_MD32_DM_SIZE);
 +    if (ret < 0) {
 +        printf("[Airoha] MDIOWriteBuf 0x00100000 fail.\n");
 +        return ret;
@@ -1418,10 +1504,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +
 +static int en8811h_config(struct phy_device *phydev)
 +{
-+    ofnode node = phy_get_ofnode(phydev);
 +    int ret = 0;
-+    int reg_value, pid1 = 0, pid2 = 0;
-+    u32 pbus_value, retry;
++    int pid1 = 0, pid2 = 0;
 +
 +    ret = air_pbus_reg_write(phydev, 0xcf928 , 0x0);
 +    if (ret < 0)
@@ -1429,11 +1513,39 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +
 +    pid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
 +    pid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
-+    printf("PHY = %x - %x\n", pid1, pid2);
 +    if ((EN8811H_PHY_ID1 != pid1) || (EN8811H_PHY_ID2 != pid2)) {
 +        printf("EN8811H does not exist !\n");
 +        return -ENODEV;
 +    }
++
++    return 0;
++}
++
++static int en8811h_get_autonego(struct phy_device *phydev, int *an)
++{
++    int reg;
++    reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
++    if (reg < 0)
++        return -EINVAL;
++    if (reg & BMCR_ANENABLE)
++        *an = AUTONEG_ENABLE;
++    else
++        *an = AUTONEG_DISABLE;
++    return 0;
++}
++
++static int en8811h_startup(struct phy_device *phydev)
++{
++    ofnode node = phy_get_ofnode(phydev);
++    int ret = 0, lpagb = 0, lpa = 0, common_adv_gb = 0, common_adv = 0, advgb = 0, adv = 0, reg = 0, an = AUTONEG_DISABLE, bmcr = 0, reg_value;
++    int old_link = phydev->link;
++    u32 pbus_value = 0, retry;
++
++    eth_phy_reset(phydev->dev, 1);
++    mdelay(10);
++    eth_phy_reset(phydev->dev, 0);
++    mdelay(1);
++
 +    ret = en8811h_load_firmware(phydev);
 +    if (ret) {
 +        printf("EN8811H load firmware fail.\n");
@@ -1492,27 +1604,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +    }
 +#endif
 +    printf("EN8811H initialize OK ! (%s)\n", EN8811H_DRIVER_VERSION);
-+    return 0;
-+}
-+
-+static int en8811h_get_autonego(struct phy_device *phydev, int *an)
-+{
-+    int reg;
-+    reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
-+    if (reg < 0)
-+        return -EINVAL;
-+    if (reg & BMCR_ANENABLE)
-+        *an = AUTONEG_ENABLE;
-+    else
-+        *an = AUTONEG_DISABLE;
-+    return 0;
-+}
-+
-+static int en8811h_startup(struct phy_device *phydev)
-+{
-+    int ret = 0, lpagb = 0, lpa = 0, common_adv_gb = 0, common_adv = 0, advgb = 0, adv = 0, reg = 0, an = AUTONEG_DISABLE, bmcr = 0;
-+    int old_link = phydev->link;
-+    u32 pbus_value = 0;
 +
 +    ret = genphy_update_link(phydev);
 +    if (ret)
@@ -1652,7 +1743,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +#endif
 --- /dev/null
 +++ b/drivers/net/phy/air_en8811h.h
-@@ -0,0 +1,160 @@
+@@ -0,0 +1,163 @@
 +/* SPDX-License-Identifier: GPL-2.0 */
 +/*************************************************
 + * FILE NAME:  air_en8811h.h
@@ -1680,6 +1771,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +#define EN8811H_PHY_READY           0x02
 +#define MAX_RETRY                   5
 +
++#define EN8811H_MD32_DM_SIZE   0x4000
++#define EN8811H_MD32_DSP_SIZE  0x20000
++
 +#define EN8811H_TX_POLARITY_NORMAL   0x1
 +#define EN8811H_TX_POLARITY_REVERSE  0x0
 +
@@ -1813,9233 +1907,23 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +
 +#endif /* End of __EN8811H_MD32_H */
 +
---- /dev/null
-+++ b/drivers/net/phy/air_en8811h_fw.h
-@@ -0,0 +1,9227 @@
-+#ifndef __EN8811H_MD32_H
-+#define __EN8811H_MD32_H
-+
-+const long int EthMD32_dm_size = 16384;
-+const unsigned char EthMD32_dm[16384] = {
-+    0x15, 0x17, 0x16, 0x12, 0x13, 0x11, 0x10, 0x00, 0x01, 0x03, 0x02, 0x06, 0x07, 0x05, 0x04, 0x0C,
-+    0x0D, 0x0F, 0x0E, 0x0A, 0x0B, 0x09, 0x08, 0x00, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
-+    0x10, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x05, 0x06, 0x00, 0x00,
-+    0x00, 0x09, 0x00, 0x00, 0x17, 0x19, 0x1B, 0x1D, 0x1F, 0x22, 0x25, 0x28, 0x2A, 0x2D, 0x31, 0x35,
-+    0x38, 0x3C, 0x40, 0x44, 0x48, 0x4E, 0x53, 0x58, 0x5E, 0x66, 0x6D, 0x74, 0x89, 0x00, 0x00, 0x00,
-+    0x3E, 0x3C, 0x2D, 0x24, 0x1E, 0x19, 0x15, 0x12, 0x0F, 0x0C, 0x0A, 0x08, 0x06, 0x05, 0x03, 0x01,
-+    0x7A, 0x78, 0x69, 0x61, 0x5A, 0x55, 0x52, 0x4E, 0x4B, 0x49, 0x46, 0x44, 0x42, 0x41, 0x3F, 0x3E,
-+    0xB6, 0xB5, 0xA6, 0x9D, 0x97, 0x92, 0x8E, 0x8A, 0x87, 0x85, 0x83, 0x81, 0x7F, 0x7D, 0x7B, 0x7A,
-+    0xFF, 0xF1, 0xE2, 0xD9, 0xD3, 0xCE, 0xCA, 0xC7, 0xC4, 0xC1, 0xBF, 0xBD, 0xBB, 0xB9, 0xB8, 0xB6,
-+    0x0C, 0x0C, 0x09, 0x07, 0x06, 0x05, 0x04, 0x04, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x00,
-+    0x18, 0x18, 0x15, 0x13, 0x12, 0x11, 0x10, 0x10, 0x0F, 0x0F, 0x0E, 0x0E, 0x0D, 0x0D, 0x0D, 0x0C,
-+    0x24, 0x24, 0x21, 0x1F, 0x1E, 0x1D, 0x1C, 0x1C, 0x1B, 0x1B, 0x1A, 0x1A, 0x19, 0x19, 0x19, 0x18,
-+    0x33, 0x30, 0x2D, 0x2B, 0x2A, 0x29, 0x28, 0x28, 0x27, 0x27, 0x26, 0x26, 0x25, 0x25, 0x25, 0x24,
-+    0xFF, 0x01, 0xFF, 0x01, 0xFF, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01,
-+    0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01,
-+    0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01, 0x68, 0x01,
-+    0x68, 0x01, 0x00, 0x00, 0x68, 0x03, 0x68, 0x03, 0x68, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
-+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
-+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
-+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0xCC, 0x8E, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x17, 0xC2, 0x8F,
-+    0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x07, 0xAA, 0x83, 0xFF, 0x00, 0x00, 0x00, 0x08, 0x0F, 0xAA, 0x83,
-+    0x00, 0xFF, 0x00, 0x00, 0x00, 0x04, 0xAE, 0x83, 0x1F, 0x00, 0x00, 0x00, 0x05, 0x09, 0xAE, 0x83,
-+    0xE0, 0x03, 0x00, 0x00, 0x0A, 0x0E, 0xAE, 0x83, 0x00, 0x7C, 0x00, 0x00, 0x0F, 0x13, 0xAE, 0x83,
-+    0x00, 0x80, 0x0F, 0x00, 0x00, 0x17, 0xCC, 0x8E, 0xFF, 0xFF, 0xFF, 0x00, 0x0E, 0x11, 0x84, 0x96,
-+    0x00, 0xC0, 0x03, 0x00, 0x12, 0x15, 0x84, 0x96, 0x00, 0x00, 0x3C, 0x00, 0x04, 0x06, 0x8C, 0x96,
-+    0x70, 0x00, 0x00, 0x00, 0x07, 0x09, 0x8C, 0x96, 0x80, 0x03, 0x00, 0x00, 0x0A, 0x0C, 0x8C, 0x96,
-+    0x00, 0x1C, 0x00, 0x00, 0x0D, 0x0F, 0x8C, 0x96, 0x00, 0xE0, 0x00, 0x00, 0x10, 0x12, 0x8C, 0x96,
-+    0x00, 0x00, 0x07, 0x00, 0x13, 0x15, 0x8C, 0x96, 0x00, 0x00, 0x38, 0x00, 0x08, 0x0A, 0x98, 0x96,
-+    0x00, 0x07, 0x00, 0x00, 0x0B, 0x0D, 0x98, 0x96, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x10, 0x98, 0x96,
-+    0x00, 0xC0, 0x01, 0x00, 0x08, 0x0A, 0x9A, 0x96, 0x00, 0x07, 0x00, 0x00, 0x0B, 0x0D, 0x9A, 0x96,
-+    0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x9E, 0x96, 0x01, 0x00, 0x00, 0x00, 0x01, 0x0A, 0x9E, 0x96,
-+    0xFE, 0x07, 0x00, 0x00, 0x0B, 0x14, 0x9E, 0x96, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xA0, 0x96,
-+    0x01, 0x00, 0x00, 0x00, 0x01, 0x0A, 0xA0, 0x96, 0xFE, 0x07, 0x00, 0x00, 0x0B, 0x14, 0xA0, 0x96,
-+    0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xA2, 0x96, 0x01, 0x00, 0x00, 0x00, 0x01, 0x0A, 0xA2, 0x96,
-+    0xFE, 0x07, 0x00, 0x00, 0x0B, 0x15, 0xA2, 0x96, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x02, 0xA6, 0x96,
-+    0x07, 0x00, 0x00, 0x00, 0x03, 0x05, 0xA6, 0x96, 0x38, 0x00, 0x00, 0x00, 0x06, 0x06, 0xA6, 0x96,
-+    0x40, 0x00, 0x00, 0x00, 0x07, 0x10, 0xA6, 0x96, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x09, 0xA8, 0x96,
-+    0xFF, 0x03, 0x00, 0x00, 0x0A, 0x13, 0xA8, 0x96, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x02, 0xB6, 0x96,
-+    0x07, 0x00, 0x00, 0x00, 0x03, 0x05, 0xB6, 0x96, 0x38, 0x00, 0x00, 0x00, 0x06, 0x06, 0xB6, 0x96,
-+    0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0xB8, 0x96, 0xFF, 0x01, 0x00, 0x00, 0x09, 0x11, 0xB8, 0x96,
-+    0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0x80, 0x8F, 0x01, 0x00, 0x00, 0x00, 0x11, 0x13, 0x82, 0x8F,
-+    0x00, 0x00, 0x0E, 0x00, 0x14, 0x16, 0x82, 0x8F, 0x00, 0x00, 0x70, 0x00, 0x02, 0x06, 0xAE, 0x8F,
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-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-+};
-+
-+const long int EthMD32_pm_size = 131072;
-+const unsigned char EthMD32_pm[131072] = {
-+    0x1E, 0x00, 0x00, 0x40, 0x1E, 0x00, 0x00, 0x72, 0x1E, 0x00, 0x00, 0x6E, 0x1E, 0x00, 0x00, 0x70,
-+    0x1E, 0x00, 0x00, 0x6A, 0x1E, 0x00, 0x00, 0x68, 0x1E, 0x00, 0x00, 0x66, 0x1E, 0x00, 0x00, 0x6C,
-+    0x1E, 0x00, 0x00, 0x6C, 0x1E, 0x00, 0x00, 0x68, 0x1E, 0x00, 0x00, 0x66, 0x1E, 0x00, 0x00, 0x5C,
-+    0x1E, 0x00, 0x00, 0x5A, 0x1E, 0x00, 0x00, 0x58, 0x1E, 0x00, 0x00, 0x56, 0x1E, 0x00, 0x6B, 0xF8,
-+    0x1E, 0x00, 0x6B, 0xA0, 0x1E, 0x00, 0x6B, 0xCC, 0x1E, 0x00, 0x6B, 0x6E, 0x1E, 0x00, 0x6B, 0x3E,
-+    0x1E, 0x00, 0x6B, 0x0E, 0x1E, 0x00, 0x6C, 0x1E, 0x1E, 0x00, 0x72, 0x94, 0x1E, 0x00, 0x6A, 0xDA,
-+    0x1E, 0x00, 0x6A, 0xAA, 0x1E, 0x00, 0x7E, 0xE6, 0x1E, 0x00, 0x80, 0x1A, 0x1E, 0x00, 0x80, 0xDC,
-+    0x1E, 0x00, 0x6A, 0x74, 0x1E, 0x00, 0x83, 0x3E, 0x1E, 0x00, 0x84, 0xBC, 0x1E, 0x00, 0x69, 0xDA,
-+    0x98, 0x0F, 0x0F, 0x00, 0x04, 0x0E, 0x0D, 0x08, 0x68, 0xEE, 0x0F, 0x00, 0x04, 0x01, 0x0D, 0x03,
-+    0x04, 0x11, 0x0F, 0x00, 0x04, 0x02, 0x0D, 0x08, 0x68, 0x22, 0x1C, 0x00, 0x18, 0x12, 0x04, 0x01,
-+    0xE1, 0x23, 0x04, 0x1C, 0x62, 0x32, 0x0C, 0x00, 0x03, 0x33, 0x1C, 0x80, 0x14, 0x40, 0x06, 0xF0,
-+    0x04, 0x01, 0x09, 0x00, 0x01, 0x22, 0x1D, 0x83, 0xF8, 0x40, 0x1C, 0x80, 0x10, 0x60, 0x06, 0xD0,
-+    0x01, 0x01, 0x09, 0x00, 0x01, 0x33, 0x1D, 0x83, 0xF8, 0x60, 0x93, 0x03, 0x93, 0x04, 0x1F, 0x00,
-+    0x86, 0xCF, 0x93, 0x13, 0x1F, 0x00, 0x00, 0x04, 0x1E, 0x00, 0x00, 0x00, 0x98, 0x11, 0x05, 0xC0,
-+    0x00, 0x20, 0xA0, 0x3F, 0x05, 0x80, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00,
-+    0x05, 0xA0, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00, 0x00, 0x03, 0xDE, 0xC1,
-+    0x04, 0x89, 0x9B, 0x11, 0x92, 0x02, 0xB2, 0x86, 0xB1, 0x87, 0x44, 0xBB, 0x27, 0xF3, 0x1B, 0xD1,
-+    0x8E, 0xC0, 0x04, 0x15, 0x40, 0x07, 0x07, 0x00, 0x80, 0x21, 0xB2, 0x06, 0xA8, 0x88, 0xA9, 0x01,
-+    0x04, 0x01, 0xE1, 0x81, 0x06, 0x1F, 0xFC, 0x8E, 0x04, 0x1D, 0x68, 0x82, 0x04, 0x01, 0xE1, 0x61,
-+    0x08, 0x00, 0x04, 0x26, 0x13, 0x00, 0xF1, 0x16, 0x00, 0x03, 0xDE, 0x81, 0x04, 0x89, 0x9B, 0x16,
-+    0x08, 0x00, 0xE3, 0x23, 0xB3, 0x54, 0xA8, 0x51, 0xAA, 0x55, 0x04, 0x0D, 0xC5, 0x01, 0x04, 0x16,
-+    0x20, 0x01, 0x88, 0x41, 0xA3, 0x83, 0xA8, 0x51, 0x43, 0x08, 0xAA, 0x53, 0x04, 0x0D, 0xC3, 0x01,
-+    0x04, 0x16, 0x20, 0x01, 0xB4, 0x51, 0xA9, 0x53, 0xA8, 0x51, 0xAA, 0x54, 0x04, 0x0D, 0xC4, 0x01,
-+    0x04, 0x16, 0x20, 0x01, 0x06, 0x1F, 0xFE, 0x4E, 0x88, 0x31, 0x04, 0x1D, 0x68, 0x43, 0xA3, 0x83,
-+    0xA8, 0x51, 0x43, 0x08, 0xAA, 0x53, 0x04, 0x0D, 0xC3, 0x01, 0x04, 0x16, 0x20, 0x01, 0xB4, 0x51,
-+    0xA9, 0x53, 0xA8, 0x51, 0xAA, 0x55, 0x04, 0x0D, 0xC5, 0x01, 0x04, 0x16, 0x20, 0x01, 0x88, 0x31,
-+    0xA3, 0x84, 0xA8, 0x51, 0x43, 0x08, 0xAA, 0x53, 0x04, 0x0D, 0xC3, 0x01, 0x04, 0x16, 0x20, 0x01,
-+    0xB4, 0x51, 0xA9, 0x53, 0xA8, 0x51, 0xAA, 0x54, 0x04, 0x0D, 0xC4, 0x01, 0x04, 0x16, 0x20, 0x01,
-+    0x88, 0x31, 0xA3, 0x88, 0xA8, 0x51, 0x43, 0x08, 0xAA, 0x53, 0x04, 0x0D, 0xC3, 0x01, 0x04, 0x16,
-+    0x20, 0x01, 0x14, 0x80, 0xC2, 0x40, 0xB5, 0x51, 0x97, 0xE1, 0x08, 0x00, 0x08, 0x65, 0x08, 0xFF,
-+    0xFC, 0x14, 0xB3, 0xB1, 0x0C, 0x00, 0xC0, 0x83, 0xA7, 0xE1, 0x1B, 0xC9, 0x08, 0x60, 0x14, 0x88,
-+    0xB2, 0x60, 0x93, 0x61, 0x15, 0x98, 0x98, 0x60, 0x93, 0x63, 0x87, 0xC2, 0xB3, 0x2A, 0xA8, 0x21,
-+    0xAA, 0x29, 0x04, 0x0D, 0xC9, 0x01, 0x04, 0x16, 0x20, 0x01, 0x06, 0x1F, 0xFA, 0x9E, 0x88, 0xA1,
-+    0x04, 0x1D, 0x68, 0x9A, 0xA3, 0x8A, 0xA8, 0x21, 0x43, 0x08, 0xAA, 0x2A, 0x04, 0x0D, 0xCA, 0x01,
-+    0x04, 0x16, 0x20, 0x01, 0xB4, 0x21, 0xA9, 0x2A, 0xA8, 0x21, 0xAA, 0x2D, 0x04, 0x0D, 0xCD, 0x01,
-+    0x04, 0x16, 0x20, 0x01, 0x88, 0xA1, 0xA3, 0x89, 0xA8, 0x21, 0x43, 0x08, 0xAA, 0x29, 0x04, 0x0D,
-+    0xC9, 0x01, 0x04, 0x16, 0x20, 0x01, 0xB4, 0x21, 0xA9, 0x2A, 0xA8, 0x21, 0xAA, 0x29, 0x04, 0x0D,
-+    0xC9, 0x01, 0x04, 0x16, 0x20, 0x01, 0x06, 0x1F, 0xF8, 0x9E, 0x88, 0xA1, 0x04, 0x1D, 0x68, 0x9A,
-+    0xA3, 0x8A, 0xA8, 0x21, 0x43, 0x08, 0xAA, 0x2A, 0x04, 0x0D, 0xCA, 0x01, 0x04, 0x16, 0x20, 0x01,
-+    0xB4, 0x21, 0xA9, 0x2A, 0xA8, 0x21, 0xAA, 0x2D, 0x04, 0x0D, 0xCD, 0x01, 0x04, 0x16, 0x20, 0x01,
-+    0x88, 0xA1, 0xA3, 0x89, 0xA8, 0x21, 0xA1, 0x30, 0x43, 0x08, 0xAA, 0x29, 0x81, 0x48, 0x91, 0x28,
-+    0x1D, 0x83, 0x52, 0x20, 0x80, 0x70, 0xBC, 0x31, 0x07, 0x00, 0x80, 0x20, 0x4B, 0xF7, 0x20, 0x3F,
-+    0x87, 0xE2, 0xB3, 0x0A, 0xA8, 0x03, 0xAA, 0x09, 0x04, 0x0D, 0xC9, 0x03, 0x04, 0x16, 0x20, 0x03,
-+    0x06, 0x1F, 0xF8, 0x9E, 0x88, 0xA3, 0x04, 0x1D, 0x68, 0x9A, 0xA3, 0xAA, 0xA8, 0x03, 0x43, 0x09,
-+    0xAA, 0x0A, 0x04, 0x0D, 0xCA, 0x03, 0x04, 0x16, 0x20, 0x03, 0xB6, 0x83, 0xAA, 0x8A, 0xA9, 0x83,
-+    0xAB, 0x8D, 0x04, 0x0D, 0xCD, 0x03, 0x04, 0x16, 0x20, 0x03, 0x88, 0xA3, 0xA3, 0xA9, 0xA9, 0x81,
-+    0x86, 0x11, 0x93, 0x53, 0xB2, 0x29, 0x04, 0x0D, 0xC9, 0x01, 0x04, 0x16, 0x20, 0x01, 0xA1, 0x4F,
-+    0xB6, 0x21, 0x15, 0x83, 0x9A, 0x60, 0x93, 0x61, 0xB2, 0x09, 0xA9, 0x03, 0xAB, 0x0A, 0x04, 0x0D,
-+    0xCA, 0x03, 0x04, 0x16, 0x20, 0x03, 0x06, 0x0F, 0xF8, 0xAE, 0x88, 0x93, 0xA3, 0xAA, 0xA9, 0x01,
-+    0x43, 0x08, 0xA1, 0x69, 0x87, 0xF2, 0x80, 0x70, 0x1C, 0x83, 0x84, 0x20, 0x07, 0x00, 0x80, 0x20,
-+    0x1E, 0x1F, 0xFF, 0xBE, 0x49, 0x80, 0xAD, 0x24, 0xAD, 0xA5, 0xAE, 0x25, 0xA0, 0x2F, 0xAC, 0xA0,
-+    0xB6, 0x20, 0x80, 0x00, 0xB9, 0xB3, 0x0F, 0x01, 0x47, 0x01, 0x0D, 0xAE, 0x14, 0x11, 0x1B, 0x00,
-+    0x03, 0x31, 0x93, 0x13, 0x00, 0x00, 0x14, 0x01, 0x00, 0x00, 0x0C, 0x86, 0x04, 0x0C, 0xE6, 0x36,
-+    0x07, 0x00, 0x60, 0x01, 0x4C, 0x0B, 0x72, 0xA8, 0x07, 0x00, 0x61, 0x01, 0xF2, 0x28, 0xF3, 0x68,
-+    0x1C, 0x83, 0xFE, 0xC0, 0x07, 0x00, 0x60, 0x01, 0xA0, 0x3F, 0xA1, 0x7D, 0x00, 0x00, 0x14, 0x01,
-+    0x00, 0x40, 0x82, 0x08, 0x0F, 0xDE, 0x75, 0x01, 0x49, 0x84, 0xA8, 0x75, 0x0F, 0x08, 0x0C, 0x06,
-+    0x0D, 0xF0, 0x34, 0x66, 0x0D, 0x02, 0xBC, 0x1D, 0x85, 0x60, 0x0F, 0x08, 0x0C, 0x07, 0x0D, 0xF0,
-+    0x8C, 0x77, 0xB6, 0x0D, 0xA8, 0x71, 0x0F, 0x78, 0xD3, 0x05, 0x88, 0x71, 0x0D, 0x9B, 0xF1, 0x5D,
-+    0x00, 0x08, 0x0C, 0xF5, 0x48, 0xE2, 0xB6, 0x0D, 0x0F, 0x08, 0x0C, 0x02, 0x0D, 0xF0, 0x04, 0x22,
-+    0x14, 0xC0, 0x38, 0x20, 0x0F, 0x08, 0x0C, 0x0A, 0x0D, 0xEF, 0xEC, 0xAA, 0x04, 0x88, 0x69, 0x41,
-+    0xBD, 0x31, 0xA8, 0x71, 0x88, 0x21, 0xA8, 0x0D, 0x20, 0x11, 0x60, 0x3D, 0xB6, 0x0D, 0xA8, 0x71,
-+    0x88, 0x51, 0xA8, 0x0D, 0x20, 0x48, 0x00, 0x2D, 0xB6, 0x0D, 0xA8, 0x71, 0x88, 0xA1, 0xAB, 0x81,
-+    0x80, 0x40, 0x1C, 0x83, 0xF8, 0x20, 0x86, 0x19, 0x08, 0x00, 0x40, 0x33, 0xA8, 0x71, 0x88, 0x16,
-+    0xB6, 0x50, 0xA8, 0x71, 0xA0, 0x2F, 0x88, 0x17, 0xB6, 0x60, 0x80, 0x00, 0x00, 0x40, 0x82, 0x04,
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-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-+};
-+#endif /* End of __EN8801H_MD32_H */
+--- a/drivers/net/eth-phy-uclass.c
++++ b/drivers/net/eth-phy-uclass.c
+@@ -155,7 +155,7 @@ static int eth_phy_of_to_plat(struct ude
+ 	return 0;
+ }
+ 
+-static void eth_phy_reset(struct udevice *dev, int value)
++void eth_phy_reset(struct udevice *dev, int value)
+ {
+ 	struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev);
+ 	u32 delay;
+--- a/include/eth_phy.h
++++ b/include/eth_phy.h
+@@ -14,5 +14,6 @@ int eth_phy_binds_nodes(struct udevice *
+ int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus);
+ struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev);
+ int eth_phy_get_addr(struct udevice *dev);
++void eth_phy_reset(struct udevice *dev, int value);
+ 
+ #endif
diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
index ae7623086e..28175e02e8 100644
--- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
+++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
@@ -1,6 +1,6 @@
 --- a/cmd/bootm.c
 +++ b/cmd/bootm.c
-@@ -259,6 +259,67 @@ U_BOOT_CMD(
+@@ -245,6 +245,67 @@ U_BOOT_CMD(
  /* iminfo - print header info for a requested image */
  /*******************************************************************/
  #if defined(CONFIG_CMD_IMI)
@@ -120,7 +120,7 @@
  		   int arch, int ph_type, int bootstage_id,
 --- a/include/image.h
 +++ b/include/image.h
-@@ -1047,6 +1047,7 @@ int fit_parse_subimage(const char *spec,
+@@ -1049,6 +1049,7 @@ int fit_parse_subimage(const char *spec,
  		ulong *addr, const char **image_name);
  
  int fit_get_subimage_count(const void *fit, int images_noffset);
diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
index d91b9904cb..7bf87ef7b5 100644
--- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
+++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
@@ -1,6 +1,6 @@
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -602,6 +602,12 @@ config CMD_ENV_EXISTS
+@@ -622,6 +622,12 @@ config CMD_ENV_EXISTS
  	  Check if a variable is defined in the environment for use in
  	  shell scripting.
  
@@ -15,7 +15,7 @@
  	help
 --- a/cmd/nvedit.c
 +++ b/cmd/nvedit.c
-@@ -408,6 +408,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in
+@@ -385,6 +385,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in
  }
  #endif
  
@@ -76,7 +76,7 @@
  #if defined(CONFIG_CMD_ENV_CALLBACK)
  static int print_static_binding(const char *var_name, const char *callback_name,
  				void *priv)
-@@ -1228,6 +1282,9 @@ static struct cmd_tbl cmd_env_sub[] = {
+@@ -1201,6 +1255,9 @@ static struct cmd_tbl cmd_env_sub[] = {
  	U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""),
  #endif
  	U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
@@ -86,7 +86,7 @@
  #if defined(CONFIG_CMD_RUN)
  	U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
  #endif
-@@ -1319,6 +1376,9 @@ static char env_help_text[] =
+@@ -1284,6 +1341,9 @@ U_BOOT_LONGHELP(env,
  #if defined(CONFIG_CMD_NVEDIT_EFI)
  	"env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n"
  #endif
@@ -96,7 +96,7 @@
  #if defined(CONFIG_CMD_RUN)
  	"env run var [...] - run commands in an environment variable\n"
  #endif
-@@ -1428,6 +1488,17 @@ U_BOOT_CMD(
+@@ -1392,6 +1452,17 @@ U_BOOT_CMD(
  );
  #endif
  
diff --git a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch
index d0abcb1acc..48556937bd 100644
--- a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch
+++ b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch
@@ -67,7 +67,7 @@
  	U_BOOT_CMD_MKENT(display, 3, 0, pstore_display, "", ""),
  	U_BOOT_CMD_MKENT(save, 4, 0, pstore_save, "", ""),
  };
-@@ -560,6 +613,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,
+@@ -566,6 +619,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,
  	   "  'pmsg-size' is the size of the user space logs record.\n"
  	   "  'ecc-size' enables/disables ECC support and specifies ECC buffer size in\n"
  	   "  bytes (0 disables it, 1 is a special value, means 16 bytes ECC).\n"
diff --git a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch
new file mode 100644
index 0000000000..fd5fdd814b
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch
@@ -0,0 +1,11 @@
+--- a/drivers/mmc/mmc_write.c
++++ b/drivers/mmc/mmc_write.c
+@@ -80,7 +80,7 @@ ulong mmc_berase(struct blk_desc *block_
+ 	u32 start_rem, blkcnt_rem, erase_args = 0;
+ 	struct mmc *mmc = find_mmc_device(dev_num);
+ 	lbaint_t blk = 0, blk_r = 0;
+-	int timeout_ms = 1000;
++	int timeout_ms = blkcnt;
+ 
+ 	if (!mmc)
+ 		return -1;
diff --git a/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch
new file mode 100644
index 0000000000..28d7e0a3f6
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch
@@ -0,0 +1,67 @@
+--- a/board/mediatek/mt7988/mt7988_rfb.c
++++ b/board/mediatek/mt7988/mt7988_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -44,3 +46,54 @@ int board_late_init(void)
+ 	env_relocate();
+ 	return 0;
+ }
++
++#define	MT7988_BOOT_NOR		0
++#define	MT7988_BOOT_SPIM_NAND	1
++#define	MT7988_BOOT_EMMC	2
++#define	MT7988_BOOT_SNFI_NAND	3
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++	switch ((readl(0x1001f6f0) & 0xc00) >> 10) {
++	case MT7988_BOOT_NOR:
++		media = "rootdisk-nor";
++		break
++		;;
++	case MT7988_BOOT_SPIM_NAND:
++		media = "rootdisk-spim-nand";
++		break
++		;;
++	case MT7988_BOOT_EMMC:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case MT7988_BOOT_SNFI_NAND:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}
diff --git a/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch b/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch
new file mode 100644
index 0000000000..3312162765
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch
@@ -0,0 +1,67 @@
+--- a/board/mediatek/mt7986/mt7986_rfb.c
++++ b/board/mediatek/mt7986/mt7986_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -83,3 +85,54 @@ int board_nmbm_init(void)
+ 
+ 	return 0;
+ }
++
++#define	MT7986_BOOT_NOR		0
++#define	MT7986_BOOT_SPIM_NAND	1
++#define	MT7986_BOOT_EMMC	2
++#define	MT7986_BOOT_SNFI_NAND	3
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle;
++
++	switch ((readl(0x1001f6f0) & 0x300) >> 8) {
++	case MT7986_BOOT_NOR:
++		media = "rootdisk-nor";
++		break
++		;;
++	case MT7986_BOOT_SPIM_NAND:
++		media = "rootdisk-spim-nand";
++		break
++		;;
++	case MT7986_BOOT_EMMC:
++		media = "rootdisk-emmc";
++		break
++		;;
++	case MT7986_BOOT_SNFI_NAND:
++		media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}
diff --git a/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch
new file mode 100644
index 0000000000..70cbf6b463
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch
@@ -0,0 +1,141 @@
+--- a/board/mediatek/mt7622/mt7622_rfb.c
++++ b/board/mediatek/mt7622/mt7622_rfb.c
+@@ -11,7 +11,9 @@
+ #include <env.h>
+ #include <init.h>
+ #include <asm/global_data.h>
++#include <asm/io.h>
+ #include <linux/delay.h>
++#include <linux/libfdt.h>
+ 
+ #ifndef CONFIG_RESET_BUTTON_LABEL
+ #define CONFIG_RESET_BUTTON_LABEL "reset"
+@@ -22,10 +24,43 @@
+ #include <nmbm/nmbm.h>
+ #include <nmbm/nmbm-mtd.h>
+ 
++#define MT7622_TOPRGUSTRAP_PAR			0x10212060
++#define MT7622_BOOT_SEQ_MASK			0x18
++#define MT7622_BOOT_SEQ_SHIFT			3
++#define MT7622_BOOT_SEQ_NOR_EMMC_SDXC		0x0
++#define MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC	0x1
++#define MT7622_BOOT_SEQ_NAND_EMMC_SDXC		0x2
++#define MT7622_BOOT_SEQ_SDXC_EMMC_NAND		0x3
++
++#define MT7622_GPIO_MODE0			0x10211300
++#define MT7622_GPIO_NAND_MODE_MASK		0x00f00000
++#define MT7622_GPIO_NAND_MODE_SHIFT		20
++#define MT7622_GPIO_NAND_MODE_EMMC		0x2
++#define MT7622_GPIO_RGMII_MODE_MASK		0x0000f000
++#define MT7622_GPIO_RGMII_MODE_SHIFT		12
++#define MT7622_GPIO_RGMII_MODE_SDCX		0x2
++#define MT7622_GPIO_SPI_MODE_MASK		0x00000f00
++#define MT7622_GPIO_SPI_MODE_SHIFT		8
++#define MT7622_GPIO_SPI_MODE_NAND		0x2
++
++#define MT7622_MSDC_INT				0x1124000C
++#define MT7622_MSDC_INT_BD_CS_ERR		0x200
++
+ DECLARE_GLOBAL_DATA_PTR;
+ 
++static int	gpio_mode0;
++static int	msdc_int;
++
+ int board_init(void)
+ {
++	/*
++	 * Save content of GPIO_MODE0 as left behind by the BootROM.
++	 * Also grab MSDC1 INT status to see if BootROM has been reading
++	 * from SD card.
++	 * Together this will allow to infer the device used for booting.
++	 */
++	gpio_mode0 = readl(MT7622_GPIO_MODE0);
++	msdc_int = readl(MT7622_MSDC_INT);
+ 	return 0;
+ }
+ 
+@@ -83,3 +118,84 @@ int board_nmbm_init(void)
+ 
+ 	return 0;
+ }
++
++int ft_system_setup(void *blob, struct bd_info *bd)
++{
++	bool pinctrl_set_mmc = false;
++	bool pinctrl_set_snfi = false;
++	bool pinctrl_set_emmc = false;
++	bool msdc_bd_cs_err = false;
++
++	const u32 *media_handle_p;
++	int chosen, len, ret;
++	const char *media;
++	u32 media_handle, strap;
++
++	if ((gpio_mode0 & MT7622_GPIO_RGMII_MODE_MASK) >>
++	    MT7622_GPIO_RGMII_MODE_SHIFT == MT7622_GPIO_RGMII_MODE_SDCX)
++		pinctrl_set_mmc = true;
++
++	if ((gpio_mode0 & MT7622_GPIO_SPI_MODE_MASK) >>
++	    MT7622_GPIO_SPI_MODE_SHIFT == MT7622_GPIO_SPI_MODE_NAND)
++		pinctrl_set_snfi = true;
++
++	if ((gpio_mode0 & MT7622_GPIO_NAND_MODE_MASK) >>
++	    MT7622_GPIO_NAND_MODE_SHIFT == MT7622_GPIO_NAND_MODE_EMMC)
++		pinctrl_set_emmc = true;
++
++	if (msdc_int & MT7622_MSDC_INT_BD_CS_ERR)
++		msdc_bd_cs_err = true;
++
++	strap = readl(MT7622_TOPRGUSTRAP_PAR);
++	strap &= MT7622_BOOT_SEQ_MASK;
++	strap >>= MT7622_BOOT_SEQ_SHIFT;
++	switch (strap) {
++	case MT7622_BOOT_SEQ_NOR_EMMC_SDXC:
++		if (!pinctrl_set_emmc)
++			media = "rootdisk-nor";
++		else if (pinctrl_set_mmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	case MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC:
++		if (pinctrl_set_snfi)
++			media = "rootdisk-snfi";
++		else if (pinctrl_set_emmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	case MT7622_BOOT_SEQ_NAND_EMMC_SDXC:
++	case MT7622_BOOT_SEQ_SDXC_EMMC_NAND:
++		if (!pinctrl_set_emmc && pinctrl_set_mmc)
++			media = "rootdisk-nand";
++		else if (pinctrl_set_emmc)
++			media = "rootdisk-emmc";
++		else
++			media = "rootdisk-sd";
++		break
++		;;
++	}
++
++	chosen = fdt_path_offset(blob, "/chosen");
++	if (chosen <= 0)
++		return 0;
++
++	media_handle_p = fdt_getprop(blob, chosen, media, &len);
++	if (media_handle_p <= 0 || len != 4)
++		return 0;
++
++	media_handle = *media_handle_p;
++	ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
++	if (ret) {
++		printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
++		return ret;
++	}
++
++	printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
++
++	return 0;
++}
diff --git a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch
index a137fa0eba..2b56f7f73f 100644
--- a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch
+++ b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7623n_bpir2_defconfig
 +++ b/configs/mt7623n_bpir2_defconfig
-@@ -7,35 +7,105 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
+@@ -7,34 +7,105 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
  CONFIG_NR_DRAM_BANKS=1
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@@ -8,13 +8,10 @@
 +CONFIG_ENV_SIZE=0x10000
  CONFIG_ENV_OFFSET=0x100000
  CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2"
--CONFIG_SYS_PROMPT="U-Boot> "
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_TARGET_MT7623=y
  CONFIG_SYS_LOAD_ADDR=0x84000000
  CONFIG_FIT=y
--CONFIG_FIT_VERBOSE=y
+ CONFIG_FIT_VERBOSE=y
 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
 +CONFIG_LED=y
 +CONFIG_LED_BLINK=y
@@ -38,6 +35,9 @@
 +CONFIG_CFB_CONSOLE_ANSI=y
 +CONFIG_CMD_ENV_FLAGS=y
  # CONFIG_DISPLAY_BOARDINFO is not set
+-CONFIG_SYS_PROMPT="U-Boot> "
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_SYS_MAXARGS=8
  CONFIG_SYS_PBSIZE=1049
  CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -70,7 +70,6 @@
  CONFIG_CMD_MMC=y
  CONFIG_CMD_READ=y
 -# CONFIG_CMD_SETEXPR is not set
- # CONFIG_CMD_NFS is not set
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_PXE=y
@@ -111,7 +110,7 @@
  CONFIG_USE_IPADDR=y
  CONFIG_IPADDR="192.168.1.1"
  CONFIG_USE_SERVERIP=y
-@@ -47,6 +117,12 @@ CONFIG_CLK=y
+@@ -46,6 +117,12 @@ CONFIG_CLK=y
  CONFIG_SUPPORT_EMMC_BOOT=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_MTK=y
@@ -124,7 +123,7 @@
  CONFIG_PHY_FIXED=y
  CONFIG_MEDIATEK_ETH=y
  CONFIG_PINCTRL=y
-@@ -56,10 +132,13 @@ CONFIG_POWER_DOMAIN=y
+@@ -55,10 +132,13 @@ CONFIG_POWER_DOMAIN=y
  CONFIG_MTK_POWER_DOMAIN=y
  CONFIG_DM_SERIAL=y
  CONFIG_MTK_SERIAL=y
diff --git a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch
index 0ddb2b9086..5b1010c005 100644
--- a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch
+++ b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7623a_unielec_u7623_02_defconfig
 +++ b/configs/mt7623a_unielec_u7623_02_defconfig
-@@ -7,34 +7,110 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
+@@ -7,33 +7,109 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
  CONFIG_NR_DRAM_BANKS=1
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10
@@ -8,13 +8,10 @@
 +CONFIG_ENV_SIZE=0x10000
  CONFIG_ENV_OFFSET=0x100000
  CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc"
--CONFIG_SYS_PROMPT="U-Boot> "
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_TARGET_MT7623=y
  CONFIG_SYS_LOAD_ADDR=0x84000000
  CONFIG_FIT=y
--CONFIG_FIT_VERBOSE=y
+ CONFIG_FIT_VERBOSE=y
 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
 +CONFIG_LED=y
 +CONFIG_LED_BLINK=y
@@ -38,6 +35,9 @@
 +CONFIG_CFB_CONSOLE_ANSI=y
 +CONFIG_CMD_ENV_FLAGS=y
  # CONFIG_DISPLAY_BOARDINFO is not set
+-CONFIG_SYS_PROMPT="U-Boot> "
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_SYS_PROMPT="MT7623> "
  CONFIG_SYS_MAXARGS=8
  CONFIG_SYS_PBSIZE=1049
  CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -71,7 +71,6 @@
  CONFIG_CMD_MMC=y
  CONFIG_CMD_READ=y
 -# CONFIG_CMD_SETEXPR is not set
- # CONFIG_CMD_NFS is not set
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_PXE=y
@@ -110,13 +109,12 @@
  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 +CONFIG_SYS_MMC_ENV_DEV=0
 +CONFIG_ENV_OVERWRITE=y
-+CONFIG_ENV_IS_IN_MMC=y
  CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_NETCONSOLE=y
  CONFIG_USE_IPADDR=y
  CONFIG_IPADDR="192.168.1.1"
  CONFIG_USE_SERVERIP=y
-@@ -46,6 +122,11 @@ CONFIG_CLK=y
+@@ -45,6 +121,11 @@ CONFIG_CLK=y
  CONFIG_SUPPORT_EMMC_BOOT=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_MTK=y
@@ -128,7 +126,7 @@
  CONFIG_PHY_FIXED=y
  CONFIG_MEDIATEK_ETH=y
  CONFIG_PINCTRL=y
-@@ -55,9 +136,12 @@ CONFIG_POWER_DOMAIN=y
+@@ -54,9 +135,12 @@ CONFIG_POWER_DOMAIN=y
  CONFIG_MTK_POWER_DOMAIN=y
  CONFIG_DM_SERIAL=y
  CONFIG_MTK_SERIAL=y
diff --git a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
index c9da03c725..2ec5770806 100644
--- a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
+++ b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
@@ -9,7 +9,7 @@
  		ethernet0 = &eth;
  	};
  
-@@ -208,17 +208,11 @@
+@@ -208,16 +208,27 @@
  	};
  };
  
@@ -22,12 +22,26 @@
 +	pinctrl-0 = <&snfi_pins>;
 +	quad-spi;
  	status = "okay";
--
+ 
 -	spi-flash@0{
 -		compatible = "jedec,spi-nor";
 -		reg = <0>;
 -		bootph-all;
--	};
++	partitions {
++		compatible = "fixed-partitions";
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		partition@0 {
++			label = "bl2";
++			reg = <0x0 0x80000>;
++		};
++
++		partition@80000 {
++			label = "ubi";
++			reg = <0x80000 0x7f80000>;
++			compatible = "linux,ubi";
++		};
+ 	};
  };
  
- &uart0 {
diff --git a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
index 1a26fec577..d97f2ec6b9 100644
--- a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
+++ b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
@@ -17,6 +17,7 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-sdmmc_env"
 +CONFIG_NET_RANDOM_ETHADDR=y
@@ -126,7 +127,6 @@
 +CONFIG_PCI=y
 +CONFIG_MTD=y
 +CONFIG_MTD_UBI_FASTMAP=y
-+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)"
 +CONFIG_DM_PCI=y
 +CONFIG_PCIE_MEDIATEK=y
 +CONFIG_PINCTRL=y
@@ -167,11 +167,11 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/bananapi_bpi-r64-sdmmc_env
-@@ -0,0 +1,82 @@
+@@ -0,0 +1,81 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x48000000
-+bootargs=root=/dev/mmcblk1p65
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
 +bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
@@ -210,7 +210,6 @@
 +boot_ubi=ubi part ubi && setenv bootargs && run boot_ubi_production ; run boot_ubi_recovery
 +boot_ubi_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr ; led $bootled_pwr off
 +boot_ubi_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off
-+check_ubi=ubi part ubi || run ubi_format
 +emmc_init=run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
 +emmc_init_bl=run sdmmc_read_emmc_bl2 && run emmc_write_bl2 && run sdmmc_read_emmc_hdr && run emmc_write_hdr && run sdmmc_read_emmc_fip && run emmc_write_fip
 +emmc_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run emmc_write_production
@@ -220,7 +219,7 @@
 +emmc_write_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
 +emmc_write_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
 +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
-+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
 +part_default=production
 +part_recovery=recovery
 +reset_factory=eraseenv && reset
@@ -233,26 +232,26 @@
 +sdmmc_read_snand_fip=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x2400 && mmc read $loadaddr $offset 0x1000
 +sdmmc_write_production=mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_write_vol
 +sdmmc_write_recovery=mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol
-+snand_write_fip=mtd erase fip && mtd write fip $loadaddr
-+snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
-+ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
-+ubi_init=run ubi_init_bl && ubi detach && mtd erase ubi && ubi part ubi && run ubi_create_env && run ubi_init_openwrt
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x20000 && mtd write bl2 $loadaddr 0x20000 0x20000 && mtd write bl2 $loadaddr 0x40000 0x20000 && mtd write bl2 $loadaddr 0x60000 0x20000
++ubi_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic
++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi
++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt
 +ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
-+ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run snand_write_fip
++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
-+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
-+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
 --- /dev/null
 +++ b/configs/mt7622_bananapi_bpi-r64-emmc_defconfig
-@@ -0,0 +1,151 @@
+@@ -0,0 +1,152 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -269,6 +268,7 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-emmc_env"
 +CONFIG_NET_RANDOM_ETHADDR=y
@@ -411,7 +411,7 @@
 +serverip=192.168.1.254
 +loadaddr=0x48000000
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0
 +bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata
@@ -455,7 +455,7 @@
 +emmc_read_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
 +emmc_read_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
 +mmc_write_vol=imszb $fileaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $fileaddr 0x$part_addr 0x$image_size
-+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size
 +part_default=production
 +part_recovery=recovery
 +reset_factory=eraseenv && reset
@@ -481,6 +481,7 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-snand_env"
 +CONFIG_DISTRO_DEFAULTS=y
@@ -574,7 +575,6 @@
 +CONFIG_PCI=y
 +CONFIG_MTD=y
 +CONFIG_MTD_UBI_FASTMAP=y
-+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)"
 +CONFIG_DM_PCI=y
 +CONFIG_PCIE_MEDIATEK=y
 +CONFIG_PINCTRL=y
@@ -613,11 +613,11 @@
 +CONFIG_SERVERIP="192.168.1.3"
 --- /dev/null
 +++ b/bananapi_bpi-r64-snand_env
-@@ -0,0 +1,57 @@
+@@ -0,0 +1,56 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x48000000
-+bootargs=root=/dev/ubiblock0_2p1
++bootargs=ubi.block=0,fit root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
 +bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1
 +bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1
@@ -652,22 +652,21 @@
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip
 +boot_ubi=ubi part ubi && run boot_production ; run boot_recovery
-+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
-+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x20000 && mtd write bl2 $loadaddr 0x20000 0x20000 && mtd write bl2 $loadaddr 0x40000 0x20000 && mtd write bl2 $loadaddr 0x60000 0x20000
 +check_ubi=ubi part ubi || run ubi_format
-+reset_factory=mw $loadaddr 0x0 0x100000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x100000 ; ubi write $loadaddr ubootenv2 0x100000 ; ubi remove rootfs_data
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
++reset_factory=mw $loadaddr 0x0 0x1f000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
 +ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ; fi
 +ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ; fi
-+_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3
-+_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format
-+_firstboot=setenv _firstboot ; run _switch_to_menu ; run check_ubi ; run _init_env ; run boot_first
++_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic
++_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
index 9cd344a286..dab7072a61 100644
--- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
+++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch
@@ -1,6 +1,6 @@
 --- /dev/null
 +++ b/configs/mt7622_linksys_e8450_defconfig
-@@ -0,0 +1,141 @@
+@@ -0,0 +1,140 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -17,7 +17,6 @@
 +CONFIG_DEBUG_UART_CLOCK=25000000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi"
 +CONFIG_DEBUG_UART=y
-+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),1280k(fip),1024k(factory),256k(reserved),-(ubi)"
 +CONFIG_SMBIOS_PRODUCT_NAME=""
 +CONFIG_AUTOBOOT_KEYED=y
 +CONFIG_BOOTDELAY=30
@@ -144,7 +143,7 @@
 +CONFIG_USB_STORAGE=y
 --- /dev/null
 +++ b/arch/arm/dts/mt7622-linksys-e8450-ubi.dts
-@@ -0,0 +1,197 @@
+@@ -0,0 +1,214 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2019 MediaTek Inc.
@@ -307,6 +306,23 @@
 +	pinctrl-0 = <&snfi_pins>;
 +	status = "okay";
 +	quad-spi;
++
++	partitions {
++		compatible = "fixed-partitions";
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		partition@0 {
++			label = "bl2";
++			reg = <0x0 0x80000>;
++		};
++
++		partition@80000 {
++			label = "ubi";
++			reg = <0x80000 0x7f80000>;
++			compatible = "linux,ubi";
++		};
++	};
 +};
 +
 +&uart0 {
@@ -344,7 +360,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1305,6 +1305,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1422,6 +1422,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  	mt7622-rfb.dtb \
  	mt7623a-unielec-u7623-02-emmc.dtb \
  	mt7622-bananapi-bpi-r64.dtb \
@@ -354,8 +370,8 @@
  	mt7981-rfb.dtb \
 --- /dev/null
 +++ b/linksys_e8450_env
-@@ -0,0 +1,57 @@
-+ethaddr_factory=mtd read spi-nand0 0x40080000 0x220000 0x20000 && env readmem -b ethaddr 0x4009fff4 0x6 ; setenv ethaddr_factory
+@@ -0,0 +1,54 @@
++ethaddr_factory=ubi read 0x40080000 factory && env readmem -b ethaddr 0x400ffff4 0x6 ; setenv ethaddr_factory
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x48000000
@@ -387,28 +403,26 @@
 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 +boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 +boot_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off
-+boot_serial_write_bl2=loadx $loadaddr 115200 && run boot_write_bl2
-+boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip
++boot_serial_write_bl2=loadx $loadaddr 115200 && run snand_write_bl2
++boot_serial_write_fip=loadx $loadaddr 115200 && run ubi_write_fip
 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip
 +boot_ubi=ubi part ubi && run boot_production ; run boot_recovery
-+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
-+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
-+check_ubi=ubi part ubi || run ubi_format
-+reset_factory=mw $loadaddr 0x0 0x100000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x100000 ; ubi write $loadaddr ubootenv2 0x100000 ; ubi remove rootfs_data
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
++snand_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=ubi check fip || ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
 +ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ; fi
 +ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ; fi
-+_create_env=ubi create ubootenv 0x100000 dynamic ; ubi create ubootenv2 0x100000 dynamic
++_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic
 +_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format
-+_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run check_ubi ; run _init_env ; run boot_first
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
index 51bdab73dd..58d0243c2e 100644
--- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
+++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
@@ -841,7 +841,7 @@
 +};
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1306,6 +1306,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1423,6 +1423,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  	mt7623a-unielec-u7623-02-emmc.dtb \
  	mt7622-bananapi-bpi-r64.dtb \
  	mt7622-linksys-e8450-ubi.dtb \
@@ -1019,7 +1019,7 @@
  
  DECLARE_GLOBAL_DATA_PTR;
  
-@@ -412,6 +413,20 @@ static int initr_onenand(void)
+@@ -397,6 +398,20 @@ static int initr_onenand(void)
  }
  #endif
  
@@ -1040,7 +1040,7 @@
  #ifdef CONFIG_MMC
  static int initr_mmc(void)
  {
-@@ -713,6 +728,9 @@ static init_fnc_t init_sequence_r[] = {
+@@ -692,6 +707,9 @@ static init_fnc_t init_sequence_r[] = {
  #ifdef CONFIG_NMBM_MTD
  	initr_nmbm,
  #endif
diff --git a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
index 3cd4d1b2df..4ee87ce3d2 100644
--- a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
+++ b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
@@ -22,7 +22,7 @@ Subject: [PATCH] add support for RAVPower RP-WD009
 
 --- a/arch/mips/dts/Makefile
 +++ b/arch/mips/dts/Makefile
-@@ -25,6 +25,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m
+@@ -26,6 +26,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m
  dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
  dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
  dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
diff --git a/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch
new file mode 100644
index 0000000000..872b60b8d9
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch
@@ -0,0 +1,314 @@
+--- /dev/null
++++ b/configs/mt7621_zbtlink_zbt-wg3526-16m_defconfig
+@@ -0,0 +1,138 @@
++CONFIG_MIPS=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_MALLOC_LEN=0x100000
++CONFIG_SPL_LIBCOMMON_SUPPORT=y
++CONFIG_SPL_LIBGENERIC_SUPPORT=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_SIZE=0x1000
++CONFIG_ENV_IS_IN_MTD=y
++CONFIG_ENV_MTD_NAME="nor0"
++CONFIG_ENV_SIZE_REDUND=0x10000
++CONFIG_ENV_SIZE=0x10000
++CONFIG_ENV_OFFSET=0x30000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_RESET_BUTTON_SETTLE_DELAY=400
++CONFIG_BOOTP_SEND_HOSTNAME=y
++# CONFIG_BOOTSTD is not set
++CONFIG_DEFAULT_ENV_FILE="zbtlink_zbt-wg3526-16m_env"
++CONFIG_DEFAULT_DEVICE_TREE="zbtlink,zbt-wg3526"
++CONFIG_SPL_BSS_MAX_SIZE=0x80000
++CONFIG_SPL_BSS_START_ADDR=0x80140000
++CONFIG_SPL_SERIAL=y
++CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
++CONFIG_SPL=y
++CONFIG_DEBUG_UART_BASE=0xbe000c00
++CONFIG_DEBUG_UART_CLOCK=50000000
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_LOAD_ADDR=0x83000000
++CONFIG_SYS_MIPS_TIMER_FREQ=440000000
++CONFIG_ARCH_MTMIPS=y
++CONFIG_SOC_MT7621=y
++# CONFIG_MIPS_CACHE_SETUP is not set
++# CONFIG_MIPS_CACHE_DISABLE is not set
++CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
++CONFIG_MIPS_BOOT_FDT=y
++CONFIG_DEBUG_UART=y
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
++CONFIG_HUSH_PARSER=y
++CONFIG_LOGLEVEL=6
++# CONFIG_LOG is not set
++# CONFIG_SYS_LONGHELP is not set
++# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
++CONFIG_SYS_CONSOLE_INFO_QUIET=y
++CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_NOR_SUPPORT=y
++CONFIG_TPL=y
++# CONFIG_TPL_FRAMEWORK is not set
++CONFIG_LEGACY_IMAGE_FORMAT=y
++# CONFIG_BOOTM_NETBSD is not set
++# CONFIG_BOOTM_PLAN9 is not set
++# CONFIG_BOOTM_RTEMS is not set
++# CONFIG_BOOTM_VXWORKS is not set
++# CONFIG_EFI is not set
++# CONFIG_EFI_LOADER is not set
++CONFIG_CMD_BOOTMENU=y
++# CONFIG_CMD_BOOTEFI is not set
++# CONFIG_CMD_BOOTD is not set
++# CONFIG_CMD_BOOTP is not set
++CONFIG_CMD_BOOTM=y
++# CONFIG_CMD_BOOTDEV is not set
++# CONFIG_CMD_BOOTFLOW is not set
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_ECHO=y
++# CONFIG_CMD_ELF is not set
++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_MTDPART=y
++# CONFIG_CMD_PCI is not set
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_TFTPBOOT=y
++# CONFIG_CMD_UNLZ4 is not set
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_DOS_PARTITION=y
++# CONFIG_SPL_DOS_PARTITION is not set
++# CONFIG_ISO_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SPL_EFI_PARTITION is not set
++CONFIG_PARTITION_TYPE_GUID=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++# CONFIG_NET_RANDOM_ETHADDR is not set
++# CONFIG_I2C is not set
++# CONFIG_INPUT is not set
++CONFIG_MMC=y
++# CONFIG_MMC_QUIRKS is not set
++# CONFIG_MMC_HW_PARTITIONING is not set
++CONFIG_MMC_MTK=y
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++CONFIG_SF_DEFAULT_SPEED=20000000
++# CONFIG_SPI_FLASH_BAR is not set
++# CONFIG_SPI_FLASH_EON is not set
++# CONFIG_SPI_FLASH_GIGADEVICE is not set
++# CONFIG_SPI_FLASH_ISSI is not set
++# CONFIG_SPI_FLASH_MACRONIX is not set
++# CONFIG_SPI_FLASH_SPANSION is not set
++# CONFIG_SPI_FLASH_STMICRO is not set
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_XMC is not set
++# CONFIG_SPI_FLASH_XTX is not set
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SPI=y
++CONFIG_MT7621_SPI=y
++CONFIG_SYSRESET=y
++CONFIG_SYSRESET_RESETCTL=y
++# CONFIG_SYS_XTRACE is not set
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_WDT=y
++CONFIG_WDT_MT7621=y
++# CONFIG_BINMAN_FDT is not set
++CONFIG_LZMA=y
++CONFIG_SPL_LZMA=y
++# CONFIG_GZIP is not set
+--- /dev/null
++++ b/zbtlink_zbt-wg3526-16m_env
+@@ -0,0 +1,36 @@
++ethaddr_factory=mtd read factory $loadaddr 0x0 0x10000 ; setexpr macoffs $loadaddr + 0xe000 ; env readmem -b ethaddr $macoffs 0x6 ; setenv ethaddr_factory
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x83000000
++bootcmd=run boot_nor
++bootdelay=0
++bootfile=immortalwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-initramfs-kernel.bin
++bootfile_uboot=u-boot-mt7621.bin
++bootfile_upg=immortalwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-squashfs-sysupgrade.bin
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot system from flash.=run boot_nor ; run bootmenu_confirm_return
++bootmenu_3=Load system via TFTP then write to flash.=run boot_tftp_sysupgrade ; run bootmenu_confirm_return
++bootmenu_4=Load U-Boot via TFTP then write to flash.=run boot_tftp_write_uboot ; run bootmenu_confirm_return
++bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset
++bootmenu_6=Reboot.=reset
++boot_first=if button reset ; then run boot_tftp ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_tftp_forever
++boot_nor=bootm 0x1fc50000
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
++boot_tftp_forever=while true ; do run boot_tftp ; sleep 1 ; done
++boot_tftp_sysupgrade=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && run nor_write_production
++boot_tftp_write_uboot=tftpboot $loadaddr $bootfile_uboot && run nor_write_uboot
++reset_factory=mtd erase u-boot-env 0x0 0x10000 && reset
++nor_pad_size=setexpr image_eb $filesize / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000
++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0xfb0000 && mtd erase firmware 0x0 0x$image_eb && mtd write firmware $loadaddr 0x0 $filesize
++nor_write_uboot=mtd erase u-boot 0x0 0x30000 && mtd write u-boot $loadaddr 0x0 0x30000
++_init_env=setenv _init_env ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/arch/mips/dts/zbtlink,zbt-wg3526.dts
+@@ -0,0 +1,131 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
++ *
++ * Author: Weijie Gao <weijie.gao@mediatek.com>
++ */
++
++/dts-v1/;
++
++#include "mt7621.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	compatible = "zbtlink,zbt-wg3526", "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
++	model = "Zbtlink WG3526";
++
++	aliases {
++		ethernet0 = &eth;
++		serial0 = &uart0;
++		spi0 = &spi;
++	};
++
++	chosen {
++		stdout-path = &uart0;
++	};
++
++	keys {
++		compatible = "gpio-keys";
++
++		reset {
++			label = "reset";
++			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led_status: status {
++			label = "green:status";
++			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
++
++&pinctrl {
++	state_default: pin_state {
++		gpios {
++			groups = "i2c", "uart3", "pcie reset";
++			function = "gpio";
++		};
++
++		wdt {
++			groups = "wdt";
++			function = "wdt rst";
++		};
++
++		jtag {
++			groups = "jtag";
++			function = "jtag";
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&gpio {
++	status = "okay";
++};
++
++&spi {
++	status = "okay";
++	num-cs = <2>;
++
++	spi-flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		spi-max-frequency = <25000000>;
++		reg = <0>;
++
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "u-boot";
++				reg = <0x0 0x30000>;
++			};
++
++			partition@30000 {
++				label = "u-boot-env";
++				reg = <0x30000 0x10000>;
++			};
++
++			factory: partition@40000 {
++				label = "factory";
++				reg = <0x40000 0x10000>;
++				read-only;
++			};
++
++			firmware: partition@50000 {
++				compatible = "denx,uimage";
++				label = "firmware";
++				reg = <0x50000 0xfb0000>;
++			};
++		};
++	};
++};
++
++&eth {
++	status = "okay";
++};
++
++&mmc {
++	cap-sd-highspeed;
++
++	status = "okay";
++};
++
++&ssusb {
++	status = "okay";
++};
++
++&u3phy {
++	status = "okay";
++};
diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
index d499b0dcc6..9e8d38d6bc 100644
--- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
+++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch
@@ -1,6 +1,6 @@
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-emmc_defconfig
-@@ -0,0 +1,196 @@
+@@ -0,0 +1,197 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -13,6 +13,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_emmc_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -199,7 +200,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-nor_defconfig
-@@ -0,0 +1,195 @@
+@@ -0,0 +1,193 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -212,6 +213,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_nor_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -271,9 +273,6 @@
 +CONFIG_CMD_SMC=y
 +CONFIG_CMD_TFTPBOOT=y
 +CONFIG_CMD_TFTPSRV=y
-+CONFIG_CMD_UBI=y
-+CONFIG_CMD_UBI_RENAME=y
-+CONFIG_CMD_UBIFS=y
 +CONFIG_CMD_ASKENV=y
 +CONFIG_CMD_PART=y
 +CONFIG_CMD_RARP=y
@@ -397,7 +396,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-sd_defconfig
-@@ -0,0 +1,196 @@
+@@ -0,0 +1,197 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -410,6 +409,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_sdmmc_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-sd.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -596,7 +596,7 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-snand_defconfig
-@@ -0,0 +1,197 @@
+@@ -0,0 +1,198 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@@ -609,6 +609,7 @@
 +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_snand_env"
 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
 +CONFIG_DEBUG_UART=y
@@ -796,12 +797,12 @@
 +CONFIG_SERVERIP="192.168.1.254"
 --- /dev/null
 +++ b/bananapi_bpi-r3_sdmmc_env
-@@ -0,0 +1,80 @@
+@@ -0,0 +1,81 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
@@ -853,26 +854,27 @@
 +sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000
 +sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
 +sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
-+mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
-+mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
++snand_write_bl2=mtd erase bl2 0x0 0x100000 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000
++nor_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
++nor_write_fip=mtd erase fip && mtd write fip $loadaddr
 +nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000
 +nor_erase_env=mtd erase u-boot-env
 +nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase fit && mtd write fit $loadaddr 0x0 $image_eb
 +nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0x900000 && mtd erase recovery 0x0 0x$image_eb && mtd write recovery $loadaddr 0x0 $image_eb
 +nor_init=run nor_init_bl && run nor_init_openwrt
-+nor_init_bl=run sdmmc_read_nor_bl2 && run mtd_write_bl2 && run sdmmc_read_nor_fip && run mtd_write_fip && run nor_erase_env
++nor_init_bl=run sdmmc_read_nor_bl2 && run nor_write_bl2 && run sdmmc_read_nor_fip && run nor_write_fip && run nor_erase_env
 +nor_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run nor_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run nor_write_production
-+ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1
 +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi
-+ubi_init=run ubi_init_bl && run ubi_format && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install
++ubi_init=run ubi_format && run ubi_init_bl && run ubi_init_openwrt && run ubi_init_emmc_install
 +ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
-+ubi_init_bl=run sdmmc_read_snand_bl2 && run mtd_write_bl2 && run sdmmc_read_snand_fip && run mtd_write_fip
++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip
 +ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
 +ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000
-+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
-+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
@@ -884,7 +886,7 @@
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mtdblock0p1
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
@@ -911,7 +913,7 @@
 +bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 +bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 +bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to flash.=run boot_tftp_write_fip ; run bootmenu_confirm_return
-+bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_preloader ; run bootmenu_confirm_return
++bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
 +bootmenu_8=Reboot.=reset
 +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
 +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
@@ -924,13 +926,13 @@
 +boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
-+boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run nor_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run nor_write_bl2
 +boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_sd ; fi
 +boot_nor=run boot_production ; run boot_recovery
-+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
-+boot_write_preloader=mtd erase bl2 && mtd write bl2 $loadaddr
 +reset_factory=mtd erase u-boot-env
++nor_write_fip=mtd erase fip && mtd write fip $loadaddr
++nor_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
 +nor_read_production=mtd read fit $loadaddr 0x0 0x20000 && imsz $loadaddr image_size && mtd read fit $loadaddr 0x0 $image_size
 +nor_read_recovery=mtd read recovery $loadaddr 0x0 0x20000 && imsz $loadaddr image_size && mtd read recovery $loadaddr 0x0 $image_size
 +nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000
@@ -942,12 +944,12 @@
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
 --- /dev/null
 +++ b/bananapi_bpi-r3_snand_env
-@@ -0,0 +1,74 @@
+@@ -0,0 +1,73 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/ubiblock0_2p1
++bootargs=root=/dev/fit0
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
 +bootconf_nor=mt7986a-bananapi-bpi-r3-nor
@@ -982,28 +984,27 @@
 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 +boot_production=run boot_update_conf ; led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 +boot_recovery=run boot_update_conf ; led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
-+boot_ubi=run boot_update_conf ; run boot_production ; run boot_recovery
++boot_ubi=run boot_production ; run boot_recovery
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2
-+boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_emmc ; else setenv bootconf  $bootconf_base#$bootconf_nand#$bootconf_sd ; fi
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_sd ; fi
 +part_default=production
 +part_recovery=recovery
-+reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
-+mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
-+mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
-+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
++reset_factory=ubi part ubi ; mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000
++snand_write_bl2=mtd erase bl2 0x0 0x100000 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic
 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 +ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install
 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
-+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
-+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
 +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
 +emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
 +emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr
@@ -1024,7 +1025,7 @@
 +serverip=192.168.1.254
 +loadaddr=0x46000000
 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0
 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
 +bootconf=config-mt7986a-bananapi-bpi-r3
 +bootconf_base=config-mt7986a-bananapi-bpi-r3
@@ -1058,7 +1059,7 @@
 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 +boot_production=run boot_update_conf ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 +boot_recovery=run boot_update_conf ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
-+boot_emmc=run boot_update_conf ; run boot_production ; run boot_recovery
++boot_emmc=run boot_production ; run boot_recovery
 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 +boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
@@ -1081,3 +1082,32 @@
 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
++++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+@@ -235,22 +235,13 @@
+ 
+ 			partition@0 {
+ 				label = "bl2";
+-				reg = <0x0 0x80000>;
++				reg = <0x0 0x200000>;
+ 			};
+ 
+-			partition@80000 {
+-				label = "factory";
+-				reg = <0x80000 0x300000>;
+-			};
+-
+-			partition@380000 {
+-				label = "fip";
+-				reg = <0x380000 0x200000>;
+-			};
+-
+-			partition@580000 {
++			partition@200000 {
+ 				label = "ubi";
+-				reg = <0x580000 0x7a80000>;
++				reg = <0x200000 0x7e00000>;
++				compatible = "linux,ubi";
+ 			};
+ 		};
+ 	};
diff --git a/package/boot/uboot-mediatek/patches/451-add-bpi-r3-mini.patch b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch
similarity index 76%
rename from package/boot/uboot-mediatek/patches/451-add-bpi-r3-mini.patch
rename to package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch
index b3506cd75c..792b54fa0a 100644
--- a/package/boot/uboot-mediatek/patches/451-add-bpi-r3-mini.patch
+++ b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch
@@ -1,288 +1,544 @@
 --- /dev/null
 +++ b/configs/mt7986a_bpi-r3-mini-emmc_defconfig
-@@ -0,0 +1,138 @@
+@@ -0,0 +1,203 @@
 +CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
++CONFIG_TARGET_MT7986=y
 +CONFIG_TEXT_BASE=0x41e00000
 +CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 +CONFIG_NR_DRAM_BANKS=1
-+CONFIG_ENV_SIZE=0x40000
-+CONFIG_ENV_OFFSET=0x400000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini"
-+CONFIG_SYS_PROMPT="MT7986> "
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_emmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb"
 +CONFIG_OF_LIBFDT_OVERLAY=y
-+CONFIG_TARGET_MT7986=y
-+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_OF_SYSTEM_SETUP=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
 +CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_ENV_OFFSET_REDUND=0x440000
-+CONFIG_SYS_LOAD_ADDR=0x46000000
-+CONFIG_PCI=y
 +CONFIG_DEBUG_UART=y
-+CONFIG_AHCI=y
-+CONFIG_FIT=y
-+CONFIG_BOOTDELAY=30
++CONFIG_SYS_LOAD_ADDR=0x46000000
++CONFIG_SMBIOS_PRODUCT_NAME=""
 +CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
 +CONFIG_AUTOBOOT_MENU_SHOW=y
-+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_PRE_CONSOLE_BUFFER=y
-+CONFIG_LOG=y
++CONFIG_CFB_CONSOLE_ANSI=y
 +CONFIG_BOARD_LATE_INIT=y
-+CONFIG_HUSH_PARSER=y
-+CONFIG_CMD_CPU=y
-+CONFIG_CMD_LICENSE=y
-+CONFIG_CMD_BOOTMENU=y
-+CONFIG_CMD_ASKENV=y
-+CONFIG_CMD_ERASEENV=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
 +CONFIG_CMD_ENV_FLAGS=y
-+CONFIG_CMD_STRINGS=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PART=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_SF_TEST=y
-+CONFIG_CMD_USB=y
-+CONFIG_CMD_DHCP=y
-+CONFIG_CMD_TFTPSRV=y
-+CONFIG_CMD_RARP=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_CDP=y
-+CONFIG_CMD_SNTP=y
-+CONFIG_CMD_DNS=y
-+CONFIG_CMD_LINK_LOCAL=y
-+CONFIG_CMD_PXE=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_SYS_PROMPT="MT7986> "
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
 +CONFIG_CMD_CACHE=y
-+CONFIG_CMD_PSTORE=y
-+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
-+CONFIG_CMD_UUID=y
-+CONFIG_CMD_HASH=y
-+CONFIG_CMD_SMC=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
 +CONFIG_CMD_EXT4=y
 +CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
 +CONFIG_CMD_FS_GENERIC=y
 +CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MDIO=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
 +CONFIG_CMD_UBI=y
 +CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MDIO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_PHY_ETHERNET_ID=y
++CONFIG_PHY_FIXED=y
++CONFIG_MTK_AHCI=y
++CONFIG_DM_ETH=y
++CONFIG_DM_ETH_PHY=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PHY_AIROHA=y
++CONFIG_PHY_AIROHA_EN8811H=y
++CONFIG_PHY_AIROHA_FW_IN_MMC=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7622=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
 +CONFIG_OF_EMBED=y
 +CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_emmc_env"
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_VERSION_VARIABLE=y
 +CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_NETCONSOLE=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.254"
 +CONFIG_REGMAP=y
 +CONFIG_SYSCON=y
-+CONFIG_SCSI_AHCI=y
-+CONFIG_AHCI_PCI=y
-+CONFIG_MTK_AHCI=y
-+CONFIG_BUTTON=y
-+CONFIG_BUTTON_GPIO=y
 +CONFIG_CLK=y
-+CONFIG_GPIO_HOG=y
-+CONFIG_LED=y
-+CONFIG_LED_BLINK=y
-+CONFIG_LED_GPIO=y
 +CONFIG_SUPPORT_EMMC_BOOT=y
 +CONFIG_MMC_HS200_SUPPORT=y
 +CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_MTD_UBI_FASTMAP=y
-+CONFIG_PHY_AIROHA=y
-+CONFIG_PHY_AIROHA_EN8811H=y
-+CONFIG_PHY_ETHERNET_ID=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_DM_MDIO=y
 +CONFIG_MEDIATEK_ETH=y
-+CONFIG_PCIE_MEDIATEK=y
-+CONFIG_PHY=y
-+CONFIG_PHY_MTK_TPHY=y
 +CONFIG_PINCTRL=y
 +CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7622=y
 +CONFIG_PINCTRL_MT7986=y
 +CONFIG_POWER_DOMAIN=y
 +CONFIG_MTK_POWER_DOMAIN=y
 +CONFIG_DM_REGULATOR=y
 +CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_DM_REGULATOR_GPIO=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_SCSI=y
-+CONFIG_DM_SCSI=y
 +CONFIG_DM_SERIAL=y
 +CONFIG_MTK_SERIAL=y
++CONFIG_HEXDUMP=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7986a_bpi-r3-mini-snand_defconfig
+@@ -0,0 +1,203 @@
++CONFIG_ARM=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TARGET_MT7986=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_snand_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_LOAD_ADDR=0x46000000
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_SYS_PROMPT="MT7986> "
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MDIO=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_DM_MDIO=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_PHY_ETHERNET_ID=y
++CONFIG_PHY_FIXED=y
++CONFIG_MTK_AHCI=y
++CONFIG_DM_ETH=y
++CONFIG_DM_ETH_PHY=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7622=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SUPPORT_EMMC_BOOT=y
 +CONFIG_SPI=y
 +CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
 +CONFIG_USB=y
++CONFIG_USB_HOST=y
 +CONFIG_USB_XHCI_HCD=y
 +CONFIG_USB_XHCI_MTK=y
 +CONFIG_USB_STORAGE=y
-+CONFIG_ZSTD=y
-+CONFIG_HEXDUMP=y
-+CONFIG_LMB_MAX_REGIONS=64
---- /dev/null
-+++ b/configs/mt7986a_bpi-r3-mini-snand_defconfig
-@@ -0,0 +1,138 @@
-+CONFIG_ARM=y
-+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
-+CONFIG_POSITION_INDEPENDENT=y
-+CONFIG_ARCH_MEDIATEK=y
-+CONFIG_TEXT_BASE=0x41e00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini"
-+CONFIG_SYS_PROMPT="MT7986> "
-+CONFIG_OF_LIBFDT_OVERLAY=y
-+CONFIG_TARGET_MT7986=y
-+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
-+CONFIG_DEBUG_UART_BASE=0x11002000
-+CONFIG_DEBUG_UART_CLOCK=40000000
-+CONFIG_SYS_LOAD_ADDR=0x46000000
-+CONFIG_PCI=y
-+CONFIG_DEBUG_UART=y
-+CONFIG_AHCI=y
-+CONFIG_FIT=y
-+CONFIG_BOOTDELAY=30
-+CONFIG_AUTOBOOT_KEYED=y
-+CONFIG_AUTOBOOT_MENU_SHOW=y
-+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb"
-+CONFIG_LOGLEVEL=7
-+CONFIG_PRE_CONSOLE_BUFFER=y
-+CONFIG_LOG=y
-+CONFIG_BOARD_LATE_INIT=y
-+CONFIG_HUSH_PARSER=y
-+CONFIG_CMD_CPU=y
-+CONFIG_CMD_LICENSE=y
-+CONFIG_CMD_BOOTMENU=y
-+CONFIG_CMD_ASKENV=y
-+CONFIG_CMD_ERASEENV=y
-+CONFIG_CMD_ENV_FLAGS=y
-+CONFIG_CMD_STRINGS=y
-+CONFIG_CMD_DM=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_PWM=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_PART=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_SF_TEST=y
-+CONFIG_CMD_USB=y
-+CONFIG_CMD_DHCP=y
-+CONFIG_CMD_TFTPSRV=y
-+CONFIG_CMD_RARP=y
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_CDP=y
-+CONFIG_CMD_SNTP=y
-+CONFIG_CMD_DNS=y
-+CONFIG_CMD_LINK_LOCAL=y
-+CONFIG_CMD_PXE=y
-+CONFIG_CMD_CACHE=y
-+CONFIG_CMD_PSTORE=y
-+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
-+CONFIG_CMD_UUID=y
-+CONFIG_CMD_HASH=y
-+CONFIG_CMD_SMC=y
-+CONFIG_CMD_EXT4=y
-+CONFIG_CMD_FAT=y
-+CONFIG_CMD_FS_GENERIC=y
-+CONFIG_CMD_FS_UUID=y
-+CONFIG_CMD_UBI=y
-+CONFIG_CMD_UBI_RENAME=y
 +CONFIG_OF_EMBED=y
 +CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 +CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_ENV_SIZE_REDUND=0x1f000
 +CONFIG_ENV_UBI_VOLUME="ubootenv"
 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_snand_env"
 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_VERSION_VARIABLE=y
 +CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_NETCONSOLE=y
-+CONFIG_USE_IPADDR=y
-+CONFIG_IPADDR="192.168.1.1"
-+CONFIG_USE_SERVERIP=y
-+CONFIG_SERVERIP="192.168.1.254"
 +CONFIG_REGMAP=y
 +CONFIG_SYSCON=y
-+CONFIG_SCSI_AHCI=y
-+CONFIG_AHCI_PCI=y
-+CONFIG_MTK_AHCI=y
-+CONFIG_BUTTON=y
-+CONFIG_BUTTON_GPIO=y
 +CONFIG_CLK=y
-+CONFIG_GPIO_HOG=y
-+CONFIG_LED=y
-+CONFIG_LED_BLINK=y
-+CONFIG_LED_GPIO=y
 +CONFIG_SUPPORT_EMMC_BOOT=y
 +CONFIG_MMC_HS200_SUPPORT=y
 +CONFIG_MMC_MTK=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_MEDIATEK_ETH=y
 +CONFIG_PHY_AIROHA=y
 +CONFIG_PHY_AIROHA_EN8811H=y
-+CONFIG_PHY_ETHERNET_ID=y
-+CONFIG_PHY_FIXED=y
-+CONFIG_DM_MDIO=y
-+CONFIG_MEDIATEK_ETH=y
-+CONFIG_PCIE_MEDIATEK=y
-+CONFIG_PHY=y
-+CONFIG_PHY_MTK_TPHY=y
++CONFIG_PHY_AIROHA_FW_IN_UBI=y
 +CONFIG_PINCTRL=y
 +CONFIG_PINCONF=y
-+CONFIG_PINCTRL_MT7622=y
 +CONFIG_PINCTRL_MT7986=y
 +CONFIG_POWER_DOMAIN=y
 +CONFIG_MTK_POWER_DOMAIN=y
 +CONFIG_DM_REGULATOR=y
 +CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_DM_REGULATOR_GPIO=y
-+CONFIG_DM_PWM=y
-+CONFIG_PWM_MTK=y
-+CONFIG_RAM=y
-+CONFIG_SCSI=y
-+CONFIG_DM_SCSI=y
 +CONFIG_DM_SERIAL=y
 +CONFIG_MTK_SERIAL=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_MTK_SPIM=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_MTK=y
-+CONFIG_USB_STORAGE=y
-+CONFIG_ZSTD=y
 +CONFIG_HEXDUMP=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++#CONFIG_DM_SPI_FLASH=y
++#CONFIG_SPI_FLASH_MTD=y
++#CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++#CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
 +CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
+--- /dev/null
++++ b/bananapi_bpi-r3-mini_snand_env
+@@ -0,0 +1,61 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x46000000
++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
++bootargs=root=ubi.block=0,fit root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
++bootconf=config-mt7986a-bananapi-bpi-r3-mini
++bootdelay=0
++bootfile=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb
++bootfile_bl2=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-preloader.bin
++bootfile_fip=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-bl31-uboot.fip
++bootfile_upg=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb
++bootfile_en8811h_fw=EthMD32.bin
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [SPI-NAND]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load Airoha EN8811H firmware via TFTP then write to NAND.=run boot_tftp_write_en8811h_fw ; run bootmenu_confirm_return
++bootmenu_7=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_8=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_9=Reboot.=reset
++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
++boot_ubi=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++boot_tftp_write_en8811h_fw=tftpboot $loadaddr $bootfile_en8811h_fw && run ubi_write_en8811h_fw
++part_default=production
++part_recovery=recovery
++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_en8811h_fw=ubi check en8811h-fw && ubi remove en8811h-fw ; ubi create en8811h-fw 0x24000 static ; ubi write $loadaddr en8811h-fw 0x24000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/bananapi_bpi-r3-mini_emmc_env
+@@ -0,0 +1,59 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x46000000
++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
++bootargs=root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
++bootconf=config-mt7986a-bananapi-bpi-r3-mini
++bootdelay=0
++bootfile=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb
++bootfile_bl2=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-preloader.bin
++bootfile_fip=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-bl31-uboot.fip
++bootfile_upg=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb
++bootfile_en8811h_fw=EthMD32.bin
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [eMMC]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load Airoha EN8811H firmware via TFTP then write to eMMC.=run boot_tftp_write_en8811h_fw ; run bootmenu_confirm_return
++bootmenu_7=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_8=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_9=Reboot.=reset
++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
++boot_emmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
++boot_tftp_write_en8811h_fw=tftpboot $loadaddr $bootfile_en8811h_fw && run emmc_write_en8811h_fw
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++emmc_write_en8811h_fw=mmc partconf 0 1 2 2 && mmc erase 0x0 0x120 && mmc write $fileaddr 0x0 0x120 ; mmc partconf 0 1 1 0
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
 --- /dev/null
 +++ b/arch/arm/dts/mt7986a-bpi-r3-mini.dts
-@@ -0,0 +1,253 @@
+@@ -0,0 +1,238 @@
 +// SPDX-License-Identifier: GPL-2.0-or-later
 +
 +/dts-v1/;
@@ -357,13 +613,13 @@
 +&eth {
 +	status = "okay";
 +	pinctrl-names = "default";
-+	pinctrl-0 = <&mdio_pins>, <&en8811_pwr_a>;
++	pinctrl-0 = <&mdio_pins>;
 +
 +	mediatek,gmac-id = <0>;
 +	phy-mode = "2500base-x";
 +	phy-handle = <&phy14>;
 +
-+	phy14: eth-phy@14 {
++	phy14: eth-phy@e {
 +		compatible = "ethernet-phy-id03a2.a411";
 +		reg = <14>;
 +
@@ -389,25 +645,25 @@
 +};
 +
 +&pinctrl {
-+	en8811_pwr_a: en8811-pwr-a {
-+		pins = "GPIO_11";
-+		drive-strength = <MTK_DRIVE_8mA>;
-+		bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
-+		output-low;
-+	};
-+
-+	en8811_pwr_b: en8811-pwr-b {
-+		pins = "GPIO_12";
-+		drive-strength = <MTK_DRIVE_8mA>;
-+		bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
-+		output-low;
-+	};
-+
 +	mdio_pins: mdio-pins {
 +		mux {
 +			function = "eth";
 +			groups = "mdc_mdio";
 +		};
++
++		conf-en8811-pwr-a {
++			pins = "GPIO_11";
++			drive-strength = <MTK_DRIVE_8mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
++			output-low;
++		};
++
++		conf-en8811-pwr-b {
++			pins = "GPIO_12";
++			drive-strength = <MTK_DRIVE_8mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
++			output-low;
++		};
 +	};
 +
 +	mmc0_pins_default: mmc0default {
@@ -502,27 +758,12 @@
 +
 +			partition@0 {
 +				label = "bl2";
-+				reg = <0x0 0x80000>;
++				reg = <0x0 0x200000>;
 +			};
 +
-+			partition@100000 {
-+				label = "orig-env";
-+				reg = <0x100000 0x80000>;
-+			};
-+
-+			partition@80000 {
-+				label = "factory";
-+				reg = <0x80000 0x300000>;
-+			};
-+
-+			partition@380000 {
-+				label = "fip";
-+				reg = <0x380000 0x200000>;
-+			};
-+
-+			partition@580000 {
++			partition@200000 {
 +				label = "ubi";
-+				reg = <0x580000 0x7a80000>;
++				reg = <0x200000 0x7e00000>;
 +			};
 +		};
 +	};
@@ -536,121 +777,3 @@
 +&watchdog {
 +	status = "disabled";
 +};
---- /dev/null
-+++ b/bananapi_bpi-r3-mini_emmc_env
-@@ -0,0 +1,55 @@
-+ipaddr=192.168.1.1
-+serverip=192.168.1.254
-+loadaddr=0x46000000
-+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mmcblk0p65
-+bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
-+bootconf=config-1
-+bootdelay=0
-+bootfile=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb
-+bootfile_bl2=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-preloader.bin
-+bootfile_fip=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-bl31-uboot.fip
-+bootfile_upg=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb
-+bootled_pwr=green:status
-+bootled_rec=green:status
-+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
-+bootmenu_default=0
-+bootmenu_delay=0
-+bootmenu_title=      ( ( ( OpenWrt ) ) )  [eMMC]
-+bootmenu_0=Initialize environment.=run _firstboot
-+bootmenu_0d=Run default boot command.=run boot_default
-+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
-+bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
-+bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
-+bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
-+bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
-+bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return
-+bootmenu_7=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
-+bootmenu_8=Reboot.=reset
-+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
-+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
-+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
-+boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
-+boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
-+boot_emmc=run boot_production ; run boot_recovery
-+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
-+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
-+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
-+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
-+mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
-+part_default=production
-+part_recovery=recovery
-+reset_factory=eraseenv && reset
-+emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
-+emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
-+emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
-+emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
-+emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
-+emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
-+_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
-+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
-+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
-+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
---- /dev/null
-+++ b/bananapi_bpi-r3-mini_snand_env
-@@ -0,0 +1,57 @@
-+ipaddr=192.168.1.1
-+serverip=192.168.1.254
-+loadaddr=0x46000000
-+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/ubiblock0_2p1
-+bootconf=config-1
-+bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
-+bootdelay=0
-+bootfile=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb
-+bootfile_bl2=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-preloader.bin
-+bootfile_fip=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-bl31-uboot.fip
-+bootfile_upg=immortalwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb
-+bootled_pwr=green:status
-+bootled_rec=green:status
-+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
-+bootmenu_default=0
-+bootmenu_delay=0
-+bootmenu_title=      ( ( ( OpenWrt ) ) )  [SPI-NAND]
-+bootmenu_0=Initialize environment.=run _firstboot
-+bootmenu_0d=Run default boot command.=run boot_default
-+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
-+bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
-+bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
-+bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
-+bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
-+bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return
-+bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
-+bootmenu_8=Reboot.=reset
-+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
-+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
-+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
-+boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
-+boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
-+boot_ubi=run boot_production ; run boot_recovery
-+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
-+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
-+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
-+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory
-+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2
-+part_default=production
-+part_recovery=recovery
-+reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
-+mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
-+mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
-+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1
-+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
-+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
-+ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
-+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
-+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
-+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
-+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
-+_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
-+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
-+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
-+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
diff --git a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch
new file mode 100644
index 0000000000..c63dbeecd9
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch
@@ -0,0 +1,998 @@
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-emmc_defconfig
+@@ -0,0 +1,180 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_emmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-sdmmc_defconfig
+@@ -0,0 +1,180 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_sdmmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-snand_defconfig
+@@ -0,0 +1,182 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_snand_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_ENV_SIZE_REDUND=0x1f000
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/bananapi_bpi-r4_sdmmc_env
+@@ -0,0 +1,66 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
++bootconf=config-mt7988a-bananapi-bpi-r4
++bootconf_sd=mt7988a-bananapi-bpi-r4-sd
++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc
++bootconf_extra=
++bootdelay=0
++bootfile=immortalwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb
++bootfile_upg=immortalwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [SD card]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Install bootloader, recovery and production to NAND.=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return
++bootmenu_7=Reboot.=reset
++bootmenu_8=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc ; led $bootled_rec off
++boot_sdmmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf#$bootconf_sd
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++sdmmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++sdmmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++sdmmc_read_snand_bl2=part start mmc 0 install part_addr && mmc read $loadaddr $part_addr 0x400
++sdmmc_read_snand_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x800 && mmc read $loadaddr $offset 0x1000
++sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000
++sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000
++ubi_create_env=ubi create ubootenv 0x100000 dynamic 1 ; ubi create ubootenv2 0x100000 dynamic 2
++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi
++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install
++ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip
++ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/bananapi_bpi-r4_snand_env
+@@ -0,0 +1,67 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 ubi.block=0,fit
++bootconf=config-mt7988a-bananapi-bpi-r4
++bootconf_extra=mt7988a-bananapi-bpi-r4-emmc
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
++bootdelay=0
++bootfile=immortalwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb
++bootfile_bl2=immortalwrt-mediatek-filogic-bananapi_bpi-r4-snand-preloader.bin
++bootfile_fip=immortalwrt-mediatek-filogic-bananapi_bpi-r4-snand-bl31-uboot.fip
++bootfile_upg=immortalwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [SPI-NAND]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=Install bootloader, recovery and production to eMMC.=if mmc partconf 0 ; then run emmc_init ; else echo "eMMC not detected" ; fi ; run bootmenu_confirm_return
++bootmenu_9=Reboot.=reset
++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
++boot_ubi=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++part_default=production
++part_recovery=recovery
++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 1 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 2
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
++emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr
++emmc_init_openwrt=run ubi_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run ubi_read_production && iminfo $loadaddr && run emmc_write_production
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_hdr=mmc erase 0x0 0x40 && mmc write $fileaddr 0x0 0x40
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/bananapi_bpi-r4_emmc_env
+@@ -0,0 +1,57 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
++bootconf=config-mt7988a-bananapi-bpi-r4
++bootconf_base=config-mt7988a-bananapi-bpi-r4
++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc
++bootconf_extra=
++bootdelay=0
++bootfile=immortalwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb
++bootfile_bl2=immortalwrt-mediatek-filogic-bananapi_bpi-r4-emmc-preloader.bin
++bootfile_fip=immortalwrt-mediatek-filogic-bananapi_bpi-r4-emmc-bl31-uboot.fip
++bootfile_upg=immortalwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title=      ( ( ( OpenWrt ) ) )  [eMMC]
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=Reboot.=reset
++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_rec off
++boot_emmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc ; fi
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       $ver"
+--- /dev/null
++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4.dtsi
+@@ -0,0 +1,199 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++#include "mt7988.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++
++/ {
++	model = "Bananapi BPI-R4";
++	compatible = "bananapi,bpi-r4", "mediatek,mt7988";
++
++	chosen {
++		stdout-path = &uart0;
++	};
++
++	memory@40000000 {
++		device_type = "memory";
++		reg = <0 0x40000000 0 0x10000000>;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	keys {
++		compatible = "gpio-keys";
++
++		wps {
++			label = "reset";
++			linux,code = <KEY_RESTART>;
++			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led_status_green: led-green {
++			label = "green:status";
++			gpios = <&gpio 79 GPIO_ACTIVE_HIGH>;
++		};
++
++		led_status_blue: led-blue {
++			label = "blue:status";
++			gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
++		};
++	};
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&i2c1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pins>;
++	status = "okay";
++};
++
++&eth {
++	status = "okay";
++	mediatek,gmac-id = <0>;
++	phy-mode = "usxgmii";
++	mediatek,switch = "mt7988";
++
++	fixed-link {
++		speed = <1000>;
++		full-duplex;
++		pause;
++	};
++};
++
++&pinctrl {
++	i2c1_pins: i2c1-pins {
++		mux {
++			function = "i2c";
++			groups = "i2c1_0";
++		};
++	};
++
++	pwm_pins: pwm-pins {
++		mux {
++			function = "pwm";
++			groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
++				 "pwm5", "pwm6", "pwm7";
++		};
++	};
++
++	spi0_pins: spi0-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	mmc0_pins_default: mmc0default {
++		mux {
++			function = "flash";
++			groups =  "emmc_51";
++		};
++
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++		};
++
++		conf-clk {
++			pins = "EMMC_CK";
++		};
++
++		conf-dsl {
++			pins = "EMMC_DSL";
++		};
++
++		conf-rst {
++			pins = "EMMC_RSTB";
++		};
++	};
++
++	mmc1_pins_default: mmc1default {
++		mux {
++			function = "flash";
++			groups =  "emmc_45";
++		};
++
++		conf-cmd-dat {
++			pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
++			       "SPI2_CLK", "SPI2_HOLD";
++			input-enable;
++		};
++
++		conf-clk {
++			pins = "SPI2_WP";
++		};
++	};
++};
++
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_pins>;
++	status = "okay";
++};
++
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>;
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "okay";
++	must_tx;
++	enhance_timing;
++	dma_ext;
++	ipm_design;
++	support_quad;
++	tick_dly = <2>;
++	sample_sel = <0>;
++
++	spi_nand@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-max-frequency = <52000000>;
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "bl2";
++				reg = <0x0 0x200000>;
++			};
++
++			partition@200000 {
++				label = "ubi";
++				reg = <0x200000 0x7e00000>;
++				compatible = "linux,ubi";
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-sd.dts
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++#include "mt7988a-bananapi-bpi-r4.dtsi"
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins_default>;
++	max-frequency = <52000000>;
++	bus-width = <4>;
++	cap-sd-highspeed;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_3p3v>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-emmc.dts
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++#include "mt7988a-bananapi-bpi-r4.dtsi"
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc0_pins_default>;
++	max-frequency = <52000000>;
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	cap-mmc-hw-reset;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++	non-removable;
++	status = "okay";
++};
diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile
index 5806654ecf..34faf5c3db 100644
--- a/package/firmware/ipq-wifi/Makefile
+++ b/package/firmware/ipq-wifi/Makefile
@@ -30,6 +30,7 @@ endef
 ALLWIFIBOARDS:= \
 	arcadyan_aw1000 \
 	buffalo_wxr-5950ax12 \
+	cmcc_rm2-6 \
 	compex_wpq873 \
 	dynalink_dl-wrx36 \
 	edgecore_eap102 \
@@ -141,6 +142,7 @@ endef
 
 $(eval $(call generate-ipq-wifi-package,arcadyan_aw1000,Arcadyan AW1000))
 $(eval $(call generate-ipq-wifi-package,buffalo_wxr-5950ax12,Buffalo WXR-5950AX12))
+$(eval $(call generate-ipq-wifi-package,cmcc_rm2-6,CMCC RM2-6))
 $(eval $(call generate-ipq-wifi-package,compex_wpq873,Compex WPQ-873))
 $(eval $(call generate-ipq-wifi-package,dynalink_dl-wrx36,Dynalink DL-WRX36))
 $(eval $(call generate-ipq-wifi-package,edgecore_eap102,Edgecore EAP102))
diff --git a/package/firmware/linux-firmware/airoha.mk b/package/firmware/linux-firmware/airoha.mk
new file mode 100644
index 0000000000..ac64d11e41
--- /dev/null
+++ b/package/firmware/linux-firmware/airoha.mk
@@ -0,0 +1,17 @@
+Package/airoha-en8811h-firmware = $(call Package/firmware-default,Airoha EN8811H 2.5G Ethernet PHY firmware)
+define Package/airoha-en8811h-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/airoha
+	$(CP) \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.dm.bin \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.DSP.bin \
+		$(1)/lib/firmware/airoha
+ifneq ($(CONFIG_TARGET_mediatek_filogic),)
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+	cat \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.dm.bin \
+		$(PKG_BUILD_DIR)/airoha/EthMD32.DSP.bin \
+		> $(STAGING_DIR_IMAGE)/EthMD32.bin
+endif
+endef
+
+$(eval $(call BuildPackage,airoha-en8811h-firmware))
diff --git a/package/firmware/linux-firmware/intel.mk b/package/firmware/linux-firmware/intel.mk
index 27b0d8ce64..19a96b2c85 100644
--- a/package/firmware/linux-firmware/intel.mk
+++ b/package/firmware/linux-firmware/intel.mk
@@ -192,6 +192,14 @@ define Package/iwlwifi-firmware-ax210/install
 endef
 $(eval $(call BuildPackage,iwlwifi-firmware-ax210))
 
+Package/iwlwifi-firmware-be200 = $(call Package/firmware-default,Intel BE200 firmware)
+define Package/iwlwifi-firmware-be200/install
+	$(INSTALL_DIR) $(1)/lib/firmware
+	$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-gl-c0-fm-c0-83.ucode $(1)/lib/firmware
+	$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-gl-c0-fm-c0.pnvm $(1)/lib/firmware
+endef
+$(eval $(call BuildPackage,iwlwifi-firmware-be200))
+
 Package/e100-firmware = $(call Package/firmware-default,Intel e100)
 define Package/e100-firmware/install
 	$(INSTALL_DIR) $(1)/lib/firmware/e100
diff --git a/package/firmware/linux-firmware/mediatek.mk b/package/firmware/linux-firmware/mediatek.mk
index a0eccb8f4d..bf6bef22a6 100644
--- a/package/firmware/linux-firmware/mediatek.mk
+++ b/package/firmware/linux-firmware/mediatek.mk
@@ -87,3 +87,12 @@ define Package/mt7986-wo-firmware/install
 		$(1)/lib/firmware/mediatek
 endef
 $(eval $(call BuildPackage,mt7986-wo-firmware))
+
+Package/mt7988-2p5g-phy-firmware = $(call Package/firmware-default,MT7988 built-in 2.5G Ethernet PHY firmware)
+define Package/mt7988-2p5g-phy-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/mediatek/mt7988
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/mediatek/mt7988/i2p5ge-phy-pmb.bin \
+		$(1)/lib/firmware/mediatek/mt7988
+endef
+$(eval $(call BuildPackage,mt7988-2p5g-phy-firmware))
diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk
index 4cf72a8064..a160e45d08 100644
--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@@ -375,6 +375,23 @@ endef
 $(eval $(call KernelPackage,phy-smsc))
 
 
+define KernelPackage/phy-airoha-en8811h
+  SUBMENU:=$(NETWORK_DEVICES_MENU)
+  TITLE:=Airoha EN8811H 2.5G Ethernet PHY
+  DEPENDS:=+airoha-en8811h-firmware +kmod-libphy @LINUX_6_1
+  KCONFIG:=CONFIG_AIR_EN8811H_PHY
+  FILES:= \
+   $(LINUX_DIR)/drivers/net/phy/air_en8811h.ko
+  AUTOLOAD:=$(call AutoLoad,18,air_en8811h,1)
+endef
+
+define KernelPackage/phy-airoha-en8811h/description
+  Kernel modules for Airoha EN8811H 2.5G Ethernet PHY
+endef
+
+$(eval $(call KernelPackage,phy-airoha-en8811h))
+
+
 define KernelPackage/phy-aquantia
   SUBMENU:=$(NETWORK_DEVICES_MENU)
   TITLE:=Aquantia Ethernet PHYs
diff --git a/package/kernel/qca-ssdk/patches/100-malibu-phy-add-support-for-manual-define-of-first-ph.patch b/package/kernel/qca-ssdk/patches/100-malibu-phy-add-support-for-manual-define-of-first-ph.patch
deleted file mode 100644
index 6aaa579c09..0000000000
--- a/package/kernel/qca-ssdk/patches/100-malibu-phy-add-support-for-manual-define-of-first-ph.patch
+++ /dev/null
@@ -1,131 +0,0 @@
-From a651d10fbd880098d7b98dee27dfd1eb15146fb2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 12 Nov 2023 18:40:22 +0100
-Subject: [PATCH] malibu-phy: add support for manual define of first phy addr
-
-The usage of first_phy_addr is EXTREMELY FRAGILE and results
-in dangerous results if the OEM (or anyone that by chance try to
-implement things in a logical manner) deviates from the default values
-from the "magical template".
-
-To be in more details. With QSDK 12.4, some tweaks were done to improve
-autoneg and now on every call of port status, the phydev is tried to
-add. This resulted in the call and log spam of an error with ports that
-are actually not present on the system with qsdk reporting phydev is
-NULL. This itself is not an error and printing the error is correct.
-
-What is actually an error from ages is setting generic bitmap reporting
-presence of port that are actually not present. This is very common on
-OEM where the switch_lan_bmp is always a variant of 0x1e (that on bitmap
-results in PORT1 PORT2 PORT3 PORT4 present) or 0x3e (PORT1 PORT2 PORT3
-PORT4 PORT5). Reality is that many device are used as AP with one LAN
-port or one WAN port. (or even exotic configuration with PORT1 not
-present and PORT2 PORT3 PORT4 present (Xiaomi 3600)
-
-With this finding one can say... ok nice, then lets update the DT and
-set the correct bitmap...
-
-Again world is a bad place and reality is that this cause wonderful
-regression in some case of by extreme luck the first ever connected
-port working and the rest of the switch dead.
-
-The problem has been bisected to all the device that doesn't have the
-PORT1 declared in any of the bitmap.
-
-With this prefaction in mind, on to the REAL problem.
-
-malibu_phy_hw_init FOR SOME REASON, set a global variable first_phy_addr
-to the first detected PHY addr that coincidentally is always PORT1.
-PORT1 addr is 0x0. The entire code in malibu_phy use this variable to
-derive the phy addrs in some function.
-
-Declaring a bitmap where the PORT1 is missing (or worse PORT4 the only
-one connected) result in first_phy_addr set to 1 or whatever phy addr is
-detected first setting wrong value all over the init stage.
-
-To fix this, introduce a new binding malibu_first_phy_addr to manually
-declare the first phy that the malibu PHY driver should use and permit
-to detach it from port bmp detection. The legacy detection is kept for
-compatibility reason.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- include/init/ssdk_dts.h  |  1 +
- include/init/ssdk_init.h |  2 ++
- src/hsl/phy/malibu_phy.c |  5 +++++
- src/init/ssdk_dts.c      | 15 +++++++++++++++
- 4 files changed, 23 insertions(+)
-
---- a/include/init/ssdk_dts.h
-+++ b/include/init/ssdk_dts.h
-@@ -146,6 +146,7 @@ a_uint32_t ssdk_wan_bmp_get(a_uint32_t d
- sw_error_t ssdk_lan_bmp_set(a_uint32_t dev_id, a_uint32_t lan_bmp);
- sw_error_t ssdk_wan_bmp_set(a_uint32_t dev_id, a_uint32_t wan_bmp);
- a_uint32_t ssdk_inner_bmp_get(a_uint32_t dev_id);
-+a_uint32_t ssdk_malibu_first_phy_addr_get(a_uint32_t dev_id);
- hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id);
- void ssdk_switch_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info);
- a_uint32_t ssdk_switch_pcie_base_get(a_uint32_t dev_id);
---- a/include/init/ssdk_init.h
-+++ b/include/init/ssdk_init.h
-@@ -194,6 +194,7 @@ enum ssdk_port_wrapper_cfg {
- 		a_uint32_t lan_bmp;
- 		a_uint32_t wan_bmp;
- 		a_uint32_t inner_bmp;
-+		a_uint32_t malibu_first_phy_addr;
- 	} ssdk_port_cfg;
- 
- 	typedef struct
-@@ -384,6 +385,7 @@ ssdk_hsl_access_mode_set(a_uint32_t dev_
- 
- a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index);
- a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
-+a_uint32_t ssdk_malibu_first_phy_addr_get(a_uint32_t dev_id);
- 
- a_uint32_t
- qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id);
---- a/src/hsl/phy/malibu_phy.c
-+++ b/src/hsl/phy/malibu_phy.c
-@@ -1945,6 +1945,11 @@ static int malibu_phy_api_ops_init(void)
- int malibu_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp)
- {
- 	static a_uint32_t phy_ops_flag = 0;
-+	a_uint32_t malibu_first_phy_addr;
-+
-+	malibu_first_phy_addr = ssdk_malibu_first_phy_addr_get(dev_id);
-+	if (malibu_first_phy_addr != MAX_PHY_ADDR)
-+		first_phy_addr = malibu_first_phy_addr;
- 
- 	if(phy_ops_flag == 0) {
- 		malibu_phy_api_ops_init();
---- a/src/init/ssdk_dts.c
-+++ b/src/init/ssdk_dts.c
-@@ -186,6 +186,13 @@ a_uint32_t ssdk_inner_bmp_get(a_uint32_t
- 	return cfg->port_cfg.inner_bmp;
- }
- 
-+a_uint32_t ssdk_malibu_first_phy_addr_get(a_uint32_t dev_id)
-+{
-+	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
-+
-+	return cfg->port_cfg.malibu_first_phy_addr;
-+}
-+
- hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id)
- {
- 	ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
-@@ -1039,6 +1046,14 @@ static void ssdk_dt_parse_port_bmp(a_uin
- 				cfg->port_cfg.inner_bmp;
- 	}
- 
-+	/* Permit to manually declare start phy addr for malibu PHY. If not found set to legacy detection. */
-+	if (!of_property_read_u32(switch_node, "malibu_first_phy_addr", &cfg->port_cfg.malibu_first_phy_addr)) {
-+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.malibu_first_phy_addr =
-+				cfg->port_cfg.malibu_first_phy_addr;
-+	} else {
-+		ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.malibu_first_phy_addr = MAX_PHY_ADDR;
-+	}
-+
- 	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.cpu_bmp = cfg->port_cfg.cpu_bmp;
- 	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.lan_bmp = cfg->port_cfg.lan_bmp;
- 	ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.wan_bmp = cfg->port_cfg.wan_bmp;
diff --git a/package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh b/package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh
index cf714c1886..babf19a7e4 100644
--- a/package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh
+++ b/package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh
@@ -77,7 +77,7 @@ hostapd_append_wpa_key_mgmt() {
 
 	[ "$fils" -gt 0 ] && {
 		case "$auth_type" in
-			eap-192)
+			eap192)
 				append wpa_key_mgmt FILS-SHA384
 				[ "${ieee80211r:-0}" -gt 0 ] && append wpa_key_mgmt FT-FILS-SHA384
 			;;
diff --git a/package/system/ca-certificates/Makefile b/package/system/ca-certificates/Makefile
index ec588cc65b..06418cebfa 100644
--- a/package/system/ca-certificates/Makefile
+++ b/package/system/ca-certificates/Makefile
@@ -7,13 +7,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ca-certificates
-PKG_VERSION:=20230311
+PKG_VERSION:=20240203
 PKG_RELEASE:=1
 PKG_MAINTAINER:=
 
 PKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@DEBIAN/pool/main/c/ca-certificates
-PKG_HASH:=83de934afa186e279d1ed08ea0d73f5cf43a6fbfb5f00874b6db3711c64576f3
+PKG_HASH:=3286d3fc42c4d11b7086711a85f865b44065ce05cf1fb5376b2abed07622a9c6
 PKG_INSTALL:=1
 
 include $(INCLUDE_DIR)/package.mk
diff --git a/package/utils/fitblk/Makefile b/package/utils/fitblk/Makefile
new file mode 100644
index 0000000000..cb9e7ebb40
--- /dev/null
+++ b/package/utils/fitblk/Makefile
@@ -0,0 +1,41 @@
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=fitblk
+PKG_RELEASE:=1
+PKG_LICENSE:=GPL-2.0-only
+PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
+
+PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)
+
+PKG_FLAGS:=nonshared
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/fitblk
+  HIDDEN:=1
+  SECTION:=base
+  CATEGORY:=Base system
+  TITLE:=fitblk firmware release tool
+  DEPENDS:=@LINUX_6_1
+endef
+
+define Package/fitblk/description
+Release uImage.FIT block devices using ioctl.
+endef
+
+define Build/Configure
+endef
+
+define Build/Compile
+	$(MAKE) -C $(PKG_BUILD_DIR) \
+		CC="$(TARGET_CC)" \
+		CFLAGS="$(TARGET_CFLAGS) -Wall -Werror" \
+		LDFLAGS="$(TARGET_LDFLAGS)"
+endef
+
+define Package/fitblk/install
+	$(INSTALL_DIR) $(1)/usr/sbin
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/fitblk $(1)/usr/sbin/
+endef
+
+$(eval $(call BuildPackage,fitblk))
diff --git a/package/utils/fitblk/src/Makefile b/package/utils/fitblk/src/Makefile
new file mode 100644
index 0000000000..064764c17d
--- /dev/null
+++ b/package/utils/fitblk/src/Makefile
@@ -0,0 +1,7 @@
+all: fitblk
+
+fitblk:
+	$(CC) $(CFLAGS) -o $@ fitblk.c $(LDFLAGS)
+
+clean:
+	rm -f fitblk
diff --git a/package/utils/fitblk/src/fitblk.c b/package/utils/fitblk/src/fitblk.c
new file mode 100644
index 0000000000..059ba6098c
--- /dev/null
+++ b/package/utils/fitblk/src/fitblk.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <stdio.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include <linux/fitblk.h>
+
+static int fitblk_release(char *device)
+{
+	int fd, ret;
+
+	fd = open(device, O_RDONLY);
+	if (fd == -1)
+		return errno;
+
+	ret = ioctl(fd, FITBLK_RELEASE, NULL);
+	close(fd);
+
+	if (ret == -1)
+		return errno;
+
+	return 0;
+}
+
+int main(int argc, char *argp[])
+{
+	int ret;
+
+	if (argc != 2) {
+		fprintf(stderr, "Release uImage.FIT sub-image block device\n");
+		fprintf(stderr, "Syntax: %s /dev/fitXXX\n", argp[0]);
+		return -EINVAL;
+	}
+
+	ret = fitblk_release(argp[1]);
+	if (ret)
+		fprintf(stderr, "fitblk: error releasing %s: %s\n", argp[1],
+			strerror(ret));
+	else
+		fprintf(stderr, "fitblk: %s released\n", argp[1]);
+
+	return ret;
+}
diff --git a/package/utils/lua/Makefile b/package/utils/lua/Makefile
index 46e7bb0dcd..36d332f1c7 100644
--- a/package/utils/lua/Makefile
+++ b/package/utils/lua/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=lua
 PKG_VERSION:=5.1.5
-PKG_RELEASE:=10
+PKG_RELEASE:=11
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://www.lua.org/ftp/ \
diff --git a/package/utils/lua/patches-host/001-include-version-number.patch b/package/utils/lua/patches-host/001-include-version-number.patch
index f769e60736..806d37003e 100644
--- a/package/utils/lua/patches-host/001-include-version-number.patch
+++ b/package/utils/lua/patches-host/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -41,10 +41,10 @@ RANLIB= ranlib
@@ -42,7 +41,7 @@ rename to doc/luac5.1.1
 diff --git a/src/Makefile b/src/Makefile
 --- a/src/Makefile
 +++ b/src/Makefile
-@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \
+@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ld
  LIB_O=	lauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \
  	lstrlib.o loadlib.o linit.o
  
diff --git a/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch b/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch
index 7f00c8c3a2..8887229589 100644
--- a/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch
+++ b/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch
@@ -1,8 +1,6 @@
-diff --git a/src/lnum.c b/src/lnum.c
-index 1456b6a2ed23..b0632b04c2b7 100644
 --- a/src/lnum.c
 +++ b/src/lnum.c
-@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {
+@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lu
  #else
        return 0;  /* Reject the number */
  #endif
@@ -11,7 +9,7 @@ index 1456b6a2ed23..b0632b04c2b7 100644
      }
    } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {
      return TK_NUMBER;	/* not in signed range, or has '.', 'e' etc. trailing */
-@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) {
+@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Inte
    return 0;
  }
  
@@ -25,8 +23,6 @@ index 1456b6a2ed23..b0632b04c2b7 100644
 +  return (unsigned LUA_INTEGER)v;
 +}
 +#endif
-diff --git a/src/lnum_config.h b/src/lnum_config.h
-index 19d7a4231a49..1092eead6629 100644
 --- a/src/lnum_config.h
 +++ b/src/lnum_config.h
 @@ -141,7 +141,12 @@
@@ -43,6 +39,3 @@ index 19d7a4231a49..1092eead6629 100644
  #endif
  #ifndef LUA_INTEGER_MIN
  # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */
--- 
-1.9.1
-
diff --git a/package/utils/lua/patches-host/100-no_readline.patch b/package/utils/lua/patches-host/100-no_readline.patch
index 209c302bb7..700114e43c 100644
--- a/package/utils/lua/patches-host/100-no_readline.patch
+++ b/package/utils/lua/patches-host/100-no_readline.patch
@@ -10,7 +10,7 @@
  #if defined(LUA_USE_MACOSX)
 --- a/src/Makefile
 +++ b/src/Makefile
-@@ -17,6 +17,7 @@
+@@ -17,6 +17,7 @@ LIBS= -lm $(MYLIBS)
  MYCFLAGS=
  MYLDFLAGS=
  MYLIBS=
@@ -18,7 +18,7 @@
  
  # == END OF USER SETTINGS. NO NEED TO CHANGE ANYTHING BELOW THIS LINE =========
  
-@@ -75,7 +76,7 @@
+@@ -75,7 +76,7 @@ echo:
  	@echo "MYLIBS = $(MYLIBS)"
  
  # convenience targets for popular platforms
@@ -27,7 +27,7 @@
  none:
  	@echo "Please choose a platform:"
  	@echo "   $(PLATS)"
-@@ -90,16 +91,16 @@
+@@ -90,16 +91,16 @@ bsd:
  	$(MAKE) all MYCFLAGS="-DLUA_USE_POSIX -DLUA_USE_DLOPEN" MYLIBS="-Wl,-E"
  
  freebsd:
diff --git a/package/utils/lua/patches-host/400-CVE-2014-5461.patch b/package/utils/lua/patches-host/400-CVE-2014-5461.patch
new file mode 100644
index 0000000000..cce73ff96b
--- /dev/null
+++ b/package/utils/lua/patches-host/400-CVE-2014-5461.patch
@@ -0,0 +1,19 @@
+From: Enrico Tassi <gareuselesinge@debian.org>
+Date: Tue, 26 Aug 2014 16:20:55 +0200
+Subject: Fix stack overflow in vararg functions
+
+---
+ src/ldo.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/ldo.c
++++ b/src/ldo.c
+@@ -274,7 +274,7 @@ int luaD_precall (lua_State *L, StkId fu
+     CallInfo *ci;
+     StkId st, base;
+     Proto *p = cl->p;
+-    luaD_checkstack(L, p->maxstacksize);
++    luaD_checkstack(L, p->maxstacksize + p->numparams);
+     func = restorestack(L, funcr);
+     if (!p->is_vararg) {  /* no varargs? */
+       base = func + 1;
diff --git a/package/utils/lua/patches/001-include-version-number.patch b/package/utils/lua/patches/001-include-version-number.patch
index f769e60736..806d37003e 100644
--- a/package/utils/lua/patches/001-include-version-number.patch
+++ b/package/utils/lua/patches/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -41,10 +41,10 @@ RANLIB= ranlib
@@ -42,7 +41,7 @@ rename to doc/luac5.1.1
 diff --git a/src/Makefile b/src/Makefile
 --- a/src/Makefile
 +++ b/src/Makefile
-@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \
+@@ -29,10 +29,10 @@ CORE_O=	lapi.o lcode.o ldebug.o ldo.o ld
  LIB_O=	lauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \
  	lstrlib.o loadlib.o linit.o
  
diff --git a/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch b/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch
index 7f00c8c3a2..8887229589 100644
--- a/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch
+++ b/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch
@@ -1,8 +1,6 @@
-diff --git a/src/lnum.c b/src/lnum.c
-index 1456b6a2ed23..b0632b04c2b7 100644
 --- a/src/lnum.c
 +++ b/src/lnum.c
-@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {
+@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lu
  #else
        return 0;  /* Reject the number */
  #endif
@@ -11,7 +9,7 @@ index 1456b6a2ed23..b0632b04c2b7 100644
      }
    } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {
      return TK_NUMBER;	/* not in signed range, or has '.', 'e' etc. trailing */
-@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) {
+@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Inte
    return 0;
  }
  
@@ -25,8 +23,6 @@ index 1456b6a2ed23..b0632b04c2b7 100644
 +  return (unsigned LUA_INTEGER)v;
 +}
 +#endif
-diff --git a/src/lnum_config.h b/src/lnum_config.h
-index 19d7a4231a49..1092eead6629 100644
 --- a/src/lnum_config.h
 +++ b/src/lnum_config.h
 @@ -141,7 +141,12 @@
@@ -43,6 +39,3 @@ index 19d7a4231a49..1092eead6629 100644
  #endif
  #ifndef LUA_INTEGER_MIN
  # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */
--- 
-1.9.1
-
diff --git a/package/utils/lua/patches/400-CVE-2014-5461.patch b/package/utils/lua/patches/400-CVE-2014-5461.patch
new file mode 100644
index 0000000000..cce73ff96b
--- /dev/null
+++ b/package/utils/lua/patches/400-CVE-2014-5461.patch
@@ -0,0 +1,19 @@
+From: Enrico Tassi <gareuselesinge@debian.org>
+Date: Tue, 26 Aug 2014 16:20:55 +0200
+Subject: Fix stack overflow in vararg functions
+
+---
+ src/ldo.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/ldo.c
++++ b/src/ldo.c
+@@ -274,7 +274,7 @@ int luaD_precall (lua_State *L, StkId fu
+     CallInfo *ci;
+     StkId st, base;
+     Proto *p = cl->p;
+-    luaD_checkstack(L, p->maxstacksize);
++    luaD_checkstack(L, p->maxstacksize + p->numparams);
+     func = restorestack(L, funcr);
+     if (!p->is_vararg) {  /* no varargs? */
+       base = func + 1;
diff --git a/package/utils/lua5.3/Makefile b/package/utils/lua5.3/Makefile
index 0a295040f2..405fa90145 100644
--- a/package/utils/lua5.3/Makefile
+++ b/package/utils/lua5.3/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=lua
 PKG_VERSION:=5.3.5
-PKG_RELEASE:=5
+PKG_RELEASE:=6
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://www.lua.org/ftp/ \
diff --git a/package/utils/lua5.3/patches-host/001-include-version-number.patch b/package/utils/lua5.3/patches-host/001-include-version-number.patch
index 78f0054960..1c9fdb250b 100644
--- a/package/utils/lua5.3/patches-host/001-include-version-number.patch
+++ b/package/utils/lua5.3/patches-host/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -12,7 +12,7 @@ PLAT= none
diff --git a/package/utils/lua5.3/patches-host/200-CVE-2019-6706.patch b/package/utils/lua5.3/patches-host/200-CVE-2019-6706.patch
new file mode 100644
index 0000000000..8024d414cc
--- /dev/null
+++ b/package/utils/lua5.3/patches-host/200-CVE-2019-6706.patch
@@ -0,0 +1,51 @@
+From 89aee84cbc9224f638f3b7951b306d2ee8ecb71e Mon Sep 17 00:00:00 2001
+From: Roberto Ierusalimschy <roberto@inf.puc-rio.br>
+Date: Wed, 27 Mar 2019 14:30:12 -0300
+Subject: [PATCH] Fixed bug in 'lua_upvaluejoin'
+
+Bug-fix: joining an upvalue with itself could cause a use-after-free
+crash.
+---
+ src/lapi.c   | 12 +++++------
+ 1 file changed, 41 insertions(+), 39 deletions(-)
+
+--- a/src/lapi.c
++++ b/src/lapi.c
+@@ -1254,13 +1254,12 @@ LUA_API const char *lua_setupvalue (lua_
+ }
+ 
+ 
+-static UpVal **getupvalref (lua_State *L, int fidx, int n, LClosure **pf) {
++static UpVal **getupvalref (lua_State *L, int fidx, int n) {
+   LClosure *f;
+   StkId fi = index2addr(L, fidx);
+   api_check(L, ttisLclosure(fi), "Lua function expected");
+   f = clLvalue(fi);
+   api_check(L, (1 <= n && n <= f->p->sizeupvalues), "invalid upvalue index");
+-  if (pf) *pf = f;
+   return &f->upvals[n - 1];  /* get its upvalue pointer */
+ }
+ 
+@@ -1269,7 +1268,7 @@ LUA_API void *lua_upvalueid (lua_State *
+   StkId fi = index2addr(L, fidx);
+   switch (ttype(fi)) {
+     case LUA_TLCL: {  /* lua closure */
+-      return *getupvalref(L, fidx, n, NULL);
++      return *getupvalref(L, fidx, n);
+     }
+     case LUA_TCCL: {  /* C closure */
+       CClosure *f = clCvalue(fi);
+@@ -1286,9 +1285,10 @@ LUA_API void *lua_upvalueid (lua_State *
+ 
+ LUA_API void lua_upvaluejoin (lua_State *L, int fidx1, int n1,
+                                             int fidx2, int n2) {
+-  LClosure *f1;
+-  UpVal **up1 = getupvalref(L, fidx1, n1, &f1);
+-  UpVal **up2 = getupvalref(L, fidx2, n2, NULL);
++  UpVal **up1 = getupvalref(L, fidx1, n1);
++  UpVal **up2 = getupvalref(L, fidx2, n2);
++  if (*up1 == *up2)
++    return;
+   luaC_upvdeccount(L, *up1);
+   *up1 = *up2;
+   (*up1)->refcount++;
diff --git a/package/utils/lua5.3/patches/001-include-version-number.patch b/package/utils/lua5.3/patches/001-include-version-number.patch
index 78f0054960..1c9fdb250b 100644
--- a/package/utils/lua5.3/patches/001-include-version-number.patch
+++ b/package/utils/lua5.3/patches/001-include-version-number.patch
@@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist.
 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
 ---
 
-diff --git a/Makefile b/Makefile
 --- a/Makefile
 +++ b/Makefile
 @@ -12,7 +12,7 @@ PLAT= none
diff --git a/package/utils/lua5.3/patches/020-shared_liblua.patch b/package/utils/lua5.3/patches/020-shared_liblua.patch
index 7fa9652290..a462fa4f1e 100644
--- a/package/utils/lua5.3/patches/020-shared_liblua.patch
+++ b/package/utils/lua5.3/patches/020-shared_liblua.patch
@@ -1,5 +1,5 @@
---- a/Makefile	2019-07-02 09:24:57.554332875 -0600
-+++ b/Makefile	2019-07-02 09:25:42.626694604 -0600
+--- a/Makefile
++++ b/Makefile
 @@ -41,7 +41,7 @@ PLATS= aix bsd c89 freebsd generic linux
  # What to install.
  TO_BIN= lua$V luac$V
@@ -19,8 +19,8 @@
  	cd doc && $(INSTALL_DATA) $(TO_MAN) $(INSTALL_MAN)
  
  uninstall:
---- a/src/ldo.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/ldo.h	2019-07-02 09:25:42.626694604 -0600
+--- a/src/ldo.h
++++ b/src/ldo.h
 @@ -47,8 +47,8 @@ LUAI_FUNC int luaD_pcall (lua_State *L,
  LUAI_FUNC int luaD_poscall (lua_State *L, CallInfo *ci, StkId firstResult,
                                            int nres);
@@ -32,8 +32,8 @@
  LUAI_FUNC void luaD_inctop (lua_State *L);
  
  LUAI_FUNC l_noret luaD_throw (lua_State *L, int errcode);
---- a/src/lfunc.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lfunc.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lfunc.h
++++ b/src/lfunc.h
 @@ -47,14 +47,14 @@ struct UpVal {
  #define upisopen(up)	((up)->v != &(up)->u.value)
  
@@ -55,8 +55,8 @@
                                           int pc);
  
  
---- a/src/lgc.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lgc.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/lgc.h
++++ b/src/lgc.h
 @@ -133,11 +133,11 @@
  
  LUAI_FUNC void luaC_fix (lua_State *L, GCObject *o);
@@ -71,8 +71,8 @@
  LUAI_FUNC void luaC_barrierback_ (lua_State *L, Table *o);
  LUAI_FUNC void luaC_upvalbarrier_ (lua_State *L, UpVal *uv);
  LUAI_FUNC void luaC_checkfinalizer (lua_State *L, GCObject *o, Table *mt);
---- a/src/llex.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/llex.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/llex.h
++++ b/src/llex.h
 @@ -73,13 +73,13 @@ typedef struct LexState {
  
  
@@ -92,8 +92,8 @@
  
  
  #endif
---- a/src/lmem.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lmem.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lmem.h
++++ b/src/lmem.h
 @@ -56,12 +56,12 @@
  #define luaM_reallocvector(L, v,oldn,n,t) \
     ((v)=cast(t *, luaM_reallocv(L, v, oldn, n, sizeof(t))))
@@ -110,8 +110,8 @@
                                 size_t size_elem, int limit,
                                 const char *what);
  
---- a/src/lobject.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lobject.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lobject.h
++++ b/src/lobject.h
 @@ -525,7 +525,7 @@ typedef struct Table {
  #define luaO_nilobject		(&luaO_nilobject_)
  
@@ -141,8 +141,8 @@
  
  
  #endif
---- a/src/lopcodes.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lopcodes.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lopcodes.h
++++ b/src/lopcodes.h
 @@ -278,7 +278,7 @@ enum OpArgMask {
    OpArgK   /* argument is a constant or register/constant */
  };
@@ -161,8 +161,8 @@
  
  
  /* number of list items to accumulate before a SETLIST instruction */
---- a/src/lstate.h	2017-04-19 11:39:34.000000000 -0600
-+++ b/src/lstate.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lstate.h
++++ b/src/lstate.h
 @@ -244,9 +244,9 @@ union GCUnion {
  
  LUAI_FUNC void luaE_setdebt (global_State *g, l_mem debt);
@@ -176,8 +176,8 @@
  
  
  #endif
---- a/src/lstring.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lstring.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/lstring.h
++++ b/src/lstring.h
 @@ -35,15 +35,15 @@
  
  LUAI_FUNC unsigned int luaS_hash (const char *str, size_t l, unsigned int seed);
@@ -198,8 +198,8 @@
  
  
  #endif
---- a/src/ltable.h	2018-05-24 13:39:05.000000000 -0600
-+++ b/src/ltable.h	2019-07-02 09:25:42.630694635 -0600
+--- a/src/ltable.h
++++ b/src/ltable.h
 @@ -41,14 +41,14 @@
  
  
@@ -218,8 +218,8 @@
  LUAI_FUNC void luaH_resize (lua_State *L, Table *t, unsigned int nasize,
                                                      unsigned int nhsize);
  LUAI_FUNC void luaH_resizearray (lua_State *L, Table *t, unsigned int nasize);
---- a/src/ltm.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/ltm.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/ltm.h
++++ b/src/ltm.h
 @@ -55,10 +55,10 @@ typedef enum {
  LUAI_DDEC const char *const luaT_typenames_[LUA_TOTALTAGS];
  
@@ -245,8 +245,8 @@
                                  const TValue *p2, TMS event);
  
  
---- a/src/lundump.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lundump.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/lundump.h
++++ b/src/lundump.h
 @@ -23,10 +23,10 @@
  #define LUAC_FORMAT	0	/* this is the official format */
  
@@ -260,8 +260,8 @@
                           void* data, int strip);
  
  #endif
---- a/src/lzio.h	2017-04-19 11:20:42.000000000 -0600
-+++ b/src/lzio.h	2019-07-02 09:25:42.634694666 -0600
+--- a/src/lzio.h
++++ b/src/lzio.h
 @@ -61,6 +61,6 @@ struct Zio {
  };
  
@@ -270,8 +270,8 @@
 +LUA_API int luaZ_fill (ZIO *z);
  
  #endif
---- a/src/Makefile	2019-07-02 09:24:57.554332875 -0600
-+++ b/src/Makefile	2019-07-02 09:25:42.630694635 -0600
+--- a/src/Makefile
++++ b/src/Makefile
 @@ -29,6 +29,7 @@ MYOBJS=
  PLATS= aix bsd c89 freebsd generic linux macosx mingw posix solaris
  
diff --git a/package/utils/lua5.3/patches/200-CVE-2019-6706.patch b/package/utils/lua5.3/patches/200-CVE-2019-6706.patch
new file mode 100644
index 0000000000..8024d414cc
--- /dev/null
+++ b/package/utils/lua5.3/patches/200-CVE-2019-6706.patch
@@ -0,0 +1,51 @@
+From 89aee84cbc9224f638f3b7951b306d2ee8ecb71e Mon Sep 17 00:00:00 2001
+From: Roberto Ierusalimschy <roberto@inf.puc-rio.br>
+Date: Wed, 27 Mar 2019 14:30:12 -0300
+Subject: [PATCH] Fixed bug in 'lua_upvaluejoin'
+
+Bug-fix: joining an upvalue with itself could cause a use-after-free
+crash.
+---
+ src/lapi.c   | 12 +++++------
+ 1 file changed, 41 insertions(+), 39 deletions(-)
+
+--- a/src/lapi.c
++++ b/src/lapi.c
+@@ -1254,13 +1254,12 @@ LUA_API const char *lua_setupvalue (lua_
+ }
+ 
+ 
+-static UpVal **getupvalref (lua_State *L, int fidx, int n, LClosure **pf) {
++static UpVal **getupvalref (lua_State *L, int fidx, int n) {
+   LClosure *f;
+   StkId fi = index2addr(L, fidx);
+   api_check(L, ttisLclosure(fi), "Lua function expected");
+   f = clLvalue(fi);
+   api_check(L, (1 <= n && n <= f->p->sizeupvalues), "invalid upvalue index");
+-  if (pf) *pf = f;
+   return &f->upvals[n - 1];  /* get its upvalue pointer */
+ }
+ 
+@@ -1269,7 +1268,7 @@ LUA_API void *lua_upvalueid (lua_State *
+   StkId fi = index2addr(L, fidx);
+   switch (ttype(fi)) {
+     case LUA_TLCL: {  /* lua closure */
+-      return *getupvalref(L, fidx, n, NULL);
++      return *getupvalref(L, fidx, n);
+     }
+     case LUA_TCCL: {  /* C closure */
+       CClosure *f = clCvalue(fi);
+@@ -1286,9 +1285,10 @@ LUA_API void *lua_upvalueid (lua_State *
+ 
+ LUA_API void lua_upvaluejoin (lua_State *L, int fidx1, int n1,
+                                             int fidx2, int n2) {
+-  LClosure *f1;
+-  UpVal **up1 = getupvalref(L, fidx1, n1, &f1);
+-  UpVal **up2 = getupvalref(L, fidx2, n2, NULL);
++  UpVal **up1 = getupvalref(L, fidx1, n1);
++  UpVal **up2 = getupvalref(L, fidx2, n2);
++  if (*up1 == *up2)
++    return;
+   luaC_upvdeccount(L, *up1);
+   *up1 = *up2;
+   (*up1)->refcount++;
diff --git a/package/utils/ugps/Makefile b/package/utils/ugps/Makefile
index 322f0d210d..66d42dca89 100644
--- a/package/utils/ugps/Makefile
+++ b/package/utils/ugps/Makefile
@@ -8,13 +8,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ugps
-PKG_RELEASE:=2
+PKG_RELEASE:=1
 
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/ugps.git
 PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-01-27
-PKG_SOURCE_VERSION:=a8171a07193351a9125024d5c759c0ebd6a6895c
-PKG_MIRROR_HASH:=9116c9698c15744bb2e36a7cfd0a73f1609b6932f32ca07da57238aea8a2d5cf
+PKG_SOURCE_DATE:=2024-02-14
+PKG_SOURCE_VERSION:=69561a074d6f50f63b82608b19041e5eb2c605a9
+PKG_MIRROR_HASH:=6a9ea235665babc22393df53e6945030a2e2264d92afccf2e9cd61fa01aa3b11
 
 PKG_MAINTAINER:=John Crispin <john@phrozen.org>
 PKG_LICENSE:=GPL-2.0+
diff --git a/scripts/ubinize-image.sh b/scripts/ubinize-image.sh
index 323eae547a..06a6310980 100755
--- a/scripts/ubinize-image.sh
+++ b/scripts/ubinize-image.sh
@@ -12,15 +12,16 @@ err=""
 ubinize_seq=""
 
 ubivol() {
-	volid=$1
-	name=$2
-	image=$3
-	autoresize=$4
-	size="$5"
+	local volid="$1"
+	local name="$2"
+	local image="$3"
+	local autoresize="$4"
+	local size="$5"
+	local voltype="${6:-dynamic}"
 	echo "[$name]"
 	echo "mode=ubi"
 	echo "vol_id=$volid"
-	echo "vol_type=dynamic"
+	echo "vol_type=$voltype"
 	echo "vol_name=$name"
 	if [ "$image" ]; then
 		echo "image=$image"
@@ -35,35 +36,47 @@ ubivol() {
 
 ubilayout() {
 	local vol_id=0
-	local rootsize=
-	local autoresize=
-	local rootfs_type="$( get_fs_type "$2" )"
+	local rootsize
+	local autoresize
+	local rootfs_type
+	local voltype
 
+	rootfs_type="$( get_fs_type "$2" )"
 	if [ "$1" = "ubootenv" ]; then
 		ubivol $vol_id ubootenv
-		vol_id=$(( $vol_id + 1 ))
+		vol_id=$(( vol_id + 1 ))
 		ubivol $vol_id ubootenv2
-		vol_id=$(( $vol_id + 1 ))
+		vol_id=$(( vol_id + 1 ))
 	fi
 	for part in $parts; do
 		name="${part%%=*}"
 		prev="$part"
 		part="${part#*=}"
+		voltype=dynamic
 		[ "$prev" = "$part" ] && part=
 
 		image="${part%%=*}"
+		if [ "${image#:}" != "$image" ]; then
+			voltype=static
+			image="${image#:}"
+		fi
 		prev="$part"
 		part="${part#*=}"
 		[ "$prev" = "$part" ] && part=
 
 		size="$part"
+		if [ -z "$size" ]; then
+			size="$( round_up "$( stat -c%s "$image" )" 1024 )"
+		else
+			size="${size}MiB"
+		fi
 
-		ubivol $vol_id "$name" "$image" "" "${size}MiB"
-		vol_id=$(( $vol_id + 1 ))
+		ubivol $vol_id "$name" "$image" "" "${size}" "$voltype"
+		vol_id=$(( vol_id + 1 ))
 	done
 	if [ "$3" ]; then
 		ubivol $vol_id kernel "$3"
-		vol_id=$(( $vol_id + 1 ))
+		vol_id=$(( vol_id + 1 ))
 	fi
 
 	if [ "$2" ]; then
@@ -77,10 +90,10 @@ ubilayout() {
 			rootsize="$( round_up "$( stat -c%s "$2" )" 1024 )"
 			;;
 		esac
-		ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize"
+		ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize" dynamic
 
-		vol_id=$(( $vol_id + 1 ))
-		[ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1
+		vol_id=$(( vol_id + 1 ))
+		[ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1 dymamic
 	fi
 }
 
@@ -116,7 +129,7 @@ while [ "$1" ]; do
 		continue
 		;;
 	"-"*)
-		ubinize_param="$@"
+		ubinize_param="$*"
 		break
 		;;
 	*)
@@ -129,7 +142,7 @@ while [ "$1" ]; do
 	esac
 done
 
-if [ ! -r "$rootfs" -a ! -r "$kernel" -a ! "$outfile" ]; then
+if [ ! -r "$rootfs" ] && [ ! -r "$kernel" ] && [ ! "$parts" ] && [ ! "$outfile" ]; then
 	echo "syntax: $0 [--uboot-env] [--part <name>=<file>] [--kernel kernelimage] [--rootfs rootfsimage] out [ubinize opts]"
 	exit 1
 fi
diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network
index 01747acae0..4ed5605fa2 100644
--- a/target/linux/ath79/generic/base-files/etc/board.d/02_network
+++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network
@@ -496,6 +496,11 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth1" "3:lan:3" "4:lan:2" "5:lan:1" "6@eth0" "2:wan:4" "1:wan:5"
 		;;
+	tplink,deco-m4r-v1|\
+	tplink,deco-s4-v2)
+		ucidef_add_switch "switch0" \
+			"0@eth0" "3:lan:1" "5:lan:2"
+		;;
 	tplink,eap225-wall-v2)
 		ucidef_add_switch "switch0" \
 			"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
@@ -572,11 +577,6 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth0" "1:lan" "2:lan"
 		;;
-	tplink,deco-m4r-v1|\
-	tplink,deco-s4-v2)
-		ucidef_add_switch "switch0" \
-			"0@eth0" "3:lan:1" "5:lan:2"
-		;;
 	hiwifi,hc6361|\
 	xiaomi,mi-router-4q|\
 	zbtlink,zbt-wd323)
diff --git a/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch
index 476a3caf3c..a89940dacb 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0111-MMC-added-alternative-MMC-driver.patch
@@ -266,7 +266,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  static inline int mmc_blk_part_switch(struct mmc_card *card,
  				      unsigned int part_type);
  static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
-@@ -3040,6 +3047,8 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3050,6 +3057,8 @@ static int mmc_blk_probe(struct mmc_card
  {
  	struct mmc_blk_data *md;
  	int ret = 0;
@@ -275,7 +275,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  
  	/*
  	 * Check that the card supports the command class(es) we need.
-@@ -3047,7 +3056,16 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3057,7 +3066,16 @@ static int mmc_blk_probe(struct mmc_card
  	if (!(card->csd.cmdclass & CCC_BLOCK_READ))
  		return -ENODEV;
  
@@ -293,7 +293,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  
  	card->complete_wq = alloc_workqueue("mmc_complete",
  					WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
-@@ -3062,6 +3080,17 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3072,6 +3090,17 @@ static int mmc_blk_probe(struct mmc_card
  		goto out_free;
  	}
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch b/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch
index c5e90fc860..3b5bfaa7e2 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0124-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch
@@ -17615,12 +17615,12 @@ Signed-off-by: Ashish Vara <ashishhvara@gmail.com>
  	 * For devices with more than one control interface, we assume the
 --- a/sound/usb/quirks.c
 +++ b/sound/usb/quirks.c
-@@ -2175,6 +2175,8 @@ static const struct usb_audio_quirk_flag
+@@ -2087,6 +2087,8 @@ static const struct usb_audio_quirk_flag
  		   QUIRK_FLAG_FIXED_RATE),
  	DEVICE_FLG(0x0ecb, 0x2069, /* JBL Quantum810 Wireless */
  		   QUIRK_FLAG_FIXED_RATE),
 +	DEVICE_FLG(0x09da, 0x2695, /* A4Tech FHD 1080p webcam */
 +		   QUIRK_FLAG_DISABLE_AUTOSUSPEND | QUIRK_FLAG_GET_SAMPLE_RATE),
- 	DEVICE_FLG(0x1bcf, 0x2283, /* NexiGo N930AF FHD Webcam */
- 		   QUIRK_FLAG_GET_SAMPLE_RATE),
- 
+ 	DEVICE_FLG(0x0fd9, 0x0008, /* Hauppauge HVR-950Q */
+ 		   QUIRK_FLAG_SHARE_MEDIA_DEVICE | QUIRK_FLAG_ALIGN_TRANSFER),
+ 	DEVICE_FLG(0x1224, 0x2a25, /* Jieli Technology USB PHY 2.0 */
diff --git a/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch b/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch
index 89d7b4eea9..102b1e2309 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0195-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch
@@ -343,7 +343,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19281,6 +19281,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19283,6 +19283,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/sony,imx412.yaml
  F:	drivers/media/i2c/imx412.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch b/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch
index a7cf1bb1f2..bae8b88490 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0196-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch
@@ -177,7 +177,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19289,6 +19289,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19291,6 +19291,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/imx477.yaml
  F:	drivers/media/i2c/imx477.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch b/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch
index 03628b3e9f..2a42b1feac 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0197-Documentation-devicetree-Add-documentation-for-imx37.patch
@@ -132,7 +132,7 @@ Signed-off-by: David Plowman <david.plowman@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19286,6 +19286,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
+@@ -19288,6 +19288,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
diff --git a/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch b/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch
index 6e51500140..541f19f261 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0528-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch
@@ -138,7 +138,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19330,6 +19330,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19332,6 +19332,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/imx519.yaml
  F:	drivers/media/i2c/imx519.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch b/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch
index 4d6227a378..ece309fc06 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0593-dt-bindings-media-i2c-Add-IMX296-CMOS-sensor-binding.patch
@@ -128,7 +128,7 @@ Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19272,6 +19272,14 @@ T:	git git://linuxtv.org/media_tree.git
+@@ -19274,6 +19274,14 @@ T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/imx290.txt
  F:	drivers/media/i2c/imx290.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch
index de983ddb15..9c084cc80f 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0594-media-i2c-IMX296-camera-sensor-driver.patch
@@ -23,7 +23,7 @@ Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19279,6 +19279,7 @@ L:	linux-media@vger.kernel.org
+@@ -19281,6 +19281,7 @@ L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
  F:	Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml
diff --git a/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch b/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch
index 374069eca5..db0e89b166 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0649-media-dt-bindings-Convert-imx290.txt-to-YAML.patch
@@ -219,7 +219,7 @@ Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19269,7 +19269,7 @@ M:	Manivannan Sadhasivam <manivannan.sad
+@@ -19271,7 +19271,7 @@ M:	Manivannan Sadhasivam <manivannan.sad
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
diff --git a/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch b/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch
index 098e6b611d..1e469f6c32 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0676-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch
@@ -271,7 +271,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -19344,7 +19344,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
+@@ -19346,7 +19346,7 @@ M:	Raspberry Pi Kernel Maintenance <kern
  L:	linux-media@vger.kernel.org
  S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
diff --git a/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch b/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch
index 88d92fbb20..7c8c49a3b5 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0864-net-macb-Also-set-DMA-coherent-mask.patch
@@ -191,7 +191,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static void macb_init_buffers(struct macb *bp)
  {
  	struct macb_queue *queue;
-@@ -915,6 +931,7 @@ static int macb_mii_init(struct macb *bp
+@@ -914,6 +930,7 @@ static int macb_mii_init(struct macb *bp
  	bp->mii_bus->name = "MACB_mii_bus";
  	bp->mii_bus->read = &macb_mdio_read;
  	bp->mii_bus->write = &macb_mdio_write;
@@ -199,7 +199,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  		 bp->pdev->name, bp->pdev->id);
  	bp->mii_bus->priv = bp;
-@@ -1584,6 +1601,11 @@ static int macb_rx(struct macb_queue *qu
+@@ -1583,6 +1600,11 @@ static int macb_rx(struct macb_queue *qu
  
  		macb_init_rx_ring(queue);
  		queue_writel(queue, RBQP, queue->rx_ring_dma);
@@ -211,7 +211,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  
  		macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
  
-@@ -1884,8 +1906,9 @@ static irqreturn_t macb_interrupt(int ir
+@@ -1883,8 +1905,9 @@ static irqreturn_t macb_interrupt(int ir
  				queue_writel(queue, ISR, MACB_BIT(TCOMP) |
  							 MACB_BIT(TXUBR));
  
@@ -222,7 +222,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  				wmb(); // ensure softirq can see update
  			}
  
-@@ -2332,6 +2355,11 @@ static netdev_tx_t macb_start_xmit(struc
+@@ -2331,6 +2354,11 @@ static netdev_tx_t macb_start_xmit(struc
  	skb_tx_timestamp(skb);
  
  	spin_lock_irq(&bp->lock);
@@ -234,7 +234,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  	spin_unlock_irq(&bp->lock);
  
-@@ -2699,6 +2727,37 @@ static void macb_configure_dma(struct ma
+@@ -2698,6 +2726,37 @@ static void macb_configure_dma(struct ma
  	}
  }
  
@@ -272,7 +272,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static void macb_init_hw(struct macb *bp)
  {
  	u32 config;
-@@ -2727,6 +2786,11 @@ static void macb_init_hw(struct macb *bp
+@@ -2726,6 +2785,11 @@ static void macb_init_hw(struct macb *bp
  	if (bp->caps & MACB_CAPS_JUMBO)
  		bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
  
@@ -284,7 +284,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	macb_configure_dma(bp);
  }
  
-@@ -3072,6 +3136,52 @@ static void gem_get_ethtool_strings(stru
+@@ -3071,6 +3135,52 @@ static void gem_get_ethtool_strings(stru
  	}
  }
  
@@ -337,7 +337,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static struct net_device_stats *macb_get_stats(struct net_device *dev)
  {
  	struct macb *bp = netdev_priv(dev);
-@@ -3664,6 +3774,8 @@ static const struct ethtool_ops macb_eth
+@@ -3663,6 +3773,8 @@ static const struct ethtool_ops macb_eth
  };
  
  static const struct ethtool_ops gem_ethtool_ops = {
@@ -346,7 +346,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	.get_regs_len		= macb_get_regs_len,
  	.get_regs		= macb_get_regs,
  	.get_wol		= macb_get_wol,
-@@ -3673,6 +3785,8 @@ static const struct ethtool_ops gem_etht
+@@ -3672,6 +3784,8 @@ static const struct ethtool_ops gem_etht
  	.get_ethtool_stats	= gem_get_ethtool_stats,
  	.get_strings		= gem_get_ethtool_strings,
  	.get_sset_count		= gem_get_sset_count,
@@ -355,7 +355,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	.get_link_ksettings     = macb_get_link_ksettings,
  	.set_link_ksettings     = macb_set_link_ksettings,
  	.get_ringparam		= macb_get_ringparam,
-@@ -4940,6 +5054,10 @@ static int macb_probe(struct platform_de
+@@ -4939,6 +5053,10 @@ static int macb_probe(struct platform_de
  
  	bp->usrio = macb_config->usrio;
  
@@ -366,7 +366,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	spin_lock_init(&bp->lock);
  
  	/* setup capabilities */
-@@ -4995,6 +5113,21 @@ static int macb_probe(struct platform_de
+@@ -4994,6 +5112,21 @@ static int macb_probe(struct platform_de
  	else
  		bp->phy_interface = interface;
  
@@ -388,7 +388,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	/* IP specific init */
  	err = init(pdev);
  	if (err)
-@@ -5071,6 +5204,19 @@ static int macb_remove(struct platform_d
+@@ -5070,6 +5203,19 @@ static int macb_remove(struct platform_d
  	return 0;
  }
  
@@ -408,7 +408,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  static int __maybe_unused macb_suspend(struct device *dev)
  {
  	struct net_device *netdev = dev_get_drvdata(dev);
-@@ -5285,6 +5431,7 @@ static const struct dev_pm_ops macb_pm_o
+@@ -5284,6 +5430,7 @@ static const struct dev_pm_ops macb_pm_o
  static struct platform_driver macb_driver = {
  	.probe		= macb_probe,
  	.remove		= macb_remove,
diff --git a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
index 2c09524dfd..e67cb66880 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
@@ -362,7 +362,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  int dwc3_host_init(struct dwc3 *dwc)
  {
 +	struct platform_device	*pdev = to_platform_device(dwc->dev);
- 	struct property_entry	props[4];
+ 	struct property_entry	props[5];
  	struct platform_device	*xhci;
  	int			ret, irq;
  	int			prop_idx = 0;
diff --git a/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch b/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch
index 82eda14173..5ea162577c 100644
--- a/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-1194-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch
@@ -67,7 +67,7 @@ Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
 +...
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17895,6 +17895,13 @@ S:	Maintained
+@@ -17897,6 +17897,13 @@ S:	Maintained
  F:	Documentation/devicetree/bindings/iio/light/bh1750.yaml
  F:	drivers/iio/light/bh1750.c
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch b/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch
index 2f3ea4b072..9888ad8ade 100644
--- a/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-1195-media-i2c-Add-driver-for-OmniVision-OV64A40.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -15321,6 +15321,14 @@ S:	Maintained
+@@ -15323,6 +15323,14 @@ S:	Maintained
  T:	git git://linuxtv.org/media_tree.git
  F:	drivers/media/i2c/ov5695.c
  
diff --git a/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch
index 209c57ca0b..e6140d9a70 100644
--- a/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch
+++ b/target/linux/bcm53xx/patches-6.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch
@@ -49,7 +49,7 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  			return UBI_IO_BAD_HDR_EBADMSG;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -820,6 +820,7 @@ extern struct mutex ubi_devices_mutex;
+@@ -822,6 +822,7 @@ extern struct mutex ubi_devices_mutex;
  extern struct blocking_notifier_head ubi_notifiers;
  
  /* attach.c */
diff --git a/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch b/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch
new file mode 100644
index 0000000000..657404196d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch
@@ -0,0 +1,33 @@
+From 1ecf9e390452e73a362ea7fbde8f3f0db83de856 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 22 Dec 2022 19:33:04 +0000
+Subject: [PATCH] mtd: ubi: wire-up parent MTD device
+
+Wire up the device parent pointer of UBI devices to their lower MTD
+device, typically an MTD partition or whole-chip device.
+
+The most noticeable change is that in sysfs, previously ubi devices
+would be could in /sys/devices/virtual/ubi while after this change they
+would be correctly attached to their parent MTD device, e.g.
+
+/sys/devices/platform/1100d000.spi/spi_master/spi1/spi1.0/mtd/mtd2/ubi0.
+
+Locating UBI devices using /sys/class/ubi/ of course still works as
+well.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+---
+ drivers/mtd/ubi/build.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -929,6 +929,7 @@ int ubi_attach_mtd_dev(struct mtd_info *
+ 	ubi->dev.release = dev_release;
+ 	ubi->dev.class = &ubi_class;
+ 	ubi->dev.groups = ubi_dev_groups;
++	ubi->dev.parent = &mtd->dev;
+ 
+ 	ubi->mtd = mtd;
+ 	ubi->ubi_num = ubi_num;
diff --git a/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch b/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch
new file mode 100644
index 0000000000..48bf986118
--- /dev/null
+++ b/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch
@@ -0,0 +1,49 @@
+From 05b8773ca33253ea562be145cf3145b05ef19f86 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 22 Dec 2022 19:33:31 +0000
+Subject: [PATCH] mtd: ubi: block: wire-up device parent
+
+ubiblock devices were previously only identifyable by their name, but
+not connected to their parent UBI volume device e.g. in sysfs.
+Properly parent ubiblock device as descendant of a UBI volume device
+to reflect device model hierachy.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+---
+ drivers/mtd/ubi/block.c | 2 +-
+ drivers/mtd/ubi/kapi.c  | 1 +
+ include/linux/mtd/ubi.h | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -452,7 +452,7 @@ int ubiblock_create(struct ubi_volume_in
+ 	list_add_tail(&dev->list, &ubiblock_devices);
+ 
+ 	/* Must be the last step: anyone can call file ops from now on */
+-	ret = add_disk(dev->gd);
++	ret = device_add_disk(vi->dev, dev->gd, NULL);
+ 	if (ret)
+ 		goto out_destroy_wq;
+ 
+--- a/drivers/mtd/ubi/kapi.c
++++ b/drivers/mtd/ubi/kapi.c
+@@ -79,6 +79,7 @@ void ubi_do_get_volume_info(struct ubi_d
+ 	vi->name_len = vol->name_len;
+ 	vi->name = vol->name;
+ 	vi->cdev = vol->cdev.dev;
++	vi->dev = &vol->dev;
+ }
+ 
+ /**
+--- a/include/linux/mtd/ubi.h
++++ b/include/linux/mtd/ubi.h
+@@ -110,6 +110,7 @@ struct ubi_volume_info {
+ 	int name_len;
+ 	const char *name;
+ 	dev_t cdev;
++	struct device *dev;
+ };
+ 
+ /**
diff --git a/target/linux/generic/backport-6.1/424-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch b/target/linux/generic/backport-6.1/426-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
similarity index 100%
rename from target/linux/generic/backport-6.1/424-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
rename to target/linux/generic/backport-6.1/426-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
diff --git a/target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch b/target/linux/generic/backport-6.1/714-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
similarity index 100%
rename from target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
rename to target/linux/generic/backport-6.1/714-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
diff --git a/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch b/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch
new file mode 100644
index 0000000000..2886123f2d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch
@@ -0,0 +1,103 @@
+From affa013f494486079c3c5ad2d00cebc41a3d7445 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:36 -0400
+Subject: [PATCH 01/21] net: fman: memac: Add serdes support
+
+This adds support for using a serdes which has to be configured. This is
+primarly in preparation for phylink conversion, which will then change the
+serdes mode dynamically.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ .../net/ethernet/freescale/fman/fman_memac.c  | 49 ++++++++++++++++++-
+ 1 file changed, 47 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -13,6 +13,7 @@
+ #include <linux/io.h>
+ #include <linux/phy.h>
+ #include <linux/phy_fixed.h>
++#include <linux/phy/phy.h>
+ #include <linux/of_mdio.h>
+ 
+ /* PCS registers */
+@@ -324,6 +325,7 @@ struct fman_mac {
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
++	struct phy *serdes;
+ 	struct phy_device *pcsphy;
+ 	bool allmulti_enabled;
+ };
+@@ -1203,17 +1205,56 @@ int memac_initialization(struct mac_devi
+ 		}
+ 	}
+ 
++	memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
++	err = PTR_ERR(memac->serdes);
++	if (err == -ENODEV || err == -ENOSYS) {
++		dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
++		memac->serdes = NULL;
++	} else if (IS_ERR(memac->serdes)) {
++		dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
++		goto _return_fm_mac_free;
++	} else {
++		err = phy_init(memac->serdes);
++		if (err) {
++			dev_err_probe(mac_dev->dev, err,
++				      "could not initialize serdes\n");
++			goto _return_fm_mac_free;
++		}
++
++		err = phy_power_on(memac->serdes);
++		if (err) {
++			dev_err_probe(mac_dev->dev, err,
++				      "could not power on serdes\n");
++			goto _return_phy_exit;
++		}
++
++		if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
++		    memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
++		    memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
++		    memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
++		    memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
++			err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
++					       memac->phy_if);
++			if (err) {
++				dev_err_probe(mac_dev->dev, err,
++					      "could not set serdes mode to %s\n",
++					      phy_modes(memac->phy_if));
++				goto _return_phy_power_off;
++			}
++		}
++	}
++
+ 	if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
+ 		struct phy_device *phy;
+ 
+ 		err = of_phy_register_fixed_link(mac_node);
+ 		if (err)
+-			goto _return_fm_mac_free;
++			goto _return_phy_power_off;
+ 
+ 		fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
+ 		if (!fixed_link) {
+ 			err = -ENOMEM;
+-			goto _return_fm_mac_free;
++			goto _return_phy_power_off;
+ 		}
+ 
+ 		mac_dev->phy_node = of_node_get(mac_node);
+@@ -1242,6 +1283,10 @@ int memac_initialization(struct mac_devi
+ 
+ 	goto _return;
+ 
++_return_phy_power_off:
++	phy_power_off(memac->serdes);
++_return_phy_exit:
++	phy_exit(memac->serdes);
+ _return_fixed_link_free:
+ 	kfree(fixed_link);
+ _return_fm_mac_free:
diff --git a/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch b/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch
new file mode 100644
index 0000000000..873debc080
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch
@@ -0,0 +1,384 @@
+From fe60e7154d3a35af975c5e6570d6ec31aab9a731 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:37 -0400
+Subject: [PATCH 02/21] net: fman: memac: Use lynx pcs driver
+
+Although not stated in the datasheet, as far as I can tell PCS for mEMACs
+is a "Lynx." By reusing the existing driver, we can remove the PCS
+management code from the memac driver. This requires calling some PCS
+functions manually which phylink would usually do for us, but we will let
+it do that soon.
+
+One problem is that we don't actually have a PCS for QSGMII. We pretend
+that each mEMAC's MDIO bus has four QSGMII PCSs, but this is not the case.
+Only the "base" mEMAC's MDIO bus has the four QSGMII PCSs. This is not an
+issue yet, because we never get the PCS state. However, it will be once the
+conversion to phylink is complete, since the links will appear to never
+come up. To get around this, we allow specifying multiple PCSs in pcsphy.
+This breaks backwards compatibility with old device trees, but only for
+QSGMII. IMO this is the only reasonable way to figure out what the actual
+QSGMII PCS is.
+
+Additionally, we now also support a separate XFI PCS. This can allow the
+SerDes driver to set different addresses for the SGMII and XFI PCSs so they
+can be accessed at the same time.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/freescale/fman/Kconfig   |   3 +
+ .../net/ethernet/freescale/fman/fman_memac.c  | 258 +++++++-----------
+ 2 files changed, 105 insertions(+), 156 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/Kconfig
++++ b/drivers/net/ethernet/freescale/fman/Kconfig
+@@ -4,6 +4,9 @@ config FSL_FMAN
+ 	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
+ 	select GENERIC_ALLOCATOR
+ 	select PHYLIB
++	select PHYLINK
++	select PCS
++	select PCS_LYNX
+ 	select CRC32
+ 	default n
+ 	help
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -11,43 +11,12 @@
+ 
+ #include <linux/slab.h>
+ #include <linux/io.h>
++#include <linux/pcs-lynx.h>
+ #include <linux/phy.h>
+ #include <linux/phy_fixed.h>
+ #include <linux/phy/phy.h>
+ #include <linux/of_mdio.h>
+ 
+-/* PCS registers */
+-#define MDIO_SGMII_CR			0x00
+-#define MDIO_SGMII_DEV_ABIL_SGMII	0x04
+-#define MDIO_SGMII_LINK_TMR_L		0x12
+-#define MDIO_SGMII_LINK_TMR_H		0x13
+-#define MDIO_SGMII_IF_MODE		0x14
+-
+-/* SGMII Control defines */
+-#define SGMII_CR_AN_EN			0x1000
+-#define SGMII_CR_RESTART_AN		0x0200
+-#define SGMII_CR_FD			0x0100
+-#define SGMII_CR_SPEED_SEL1_1G		0x0040
+-#define SGMII_CR_DEF_VAL		(SGMII_CR_AN_EN | SGMII_CR_FD | \
+-					 SGMII_CR_SPEED_SEL1_1G)
+-
+-/* SGMII Device Ability for SGMII defines */
+-#define MDIO_SGMII_DEV_ABIL_SGMII_MODE	0x4001
+-#define MDIO_SGMII_DEV_ABIL_BASEX_MODE	0x01A0
+-
+-/* Link timer define */
+-#define LINK_TMR_L			0xa120
+-#define LINK_TMR_H			0x0007
+-#define LINK_TMR_L_BASEX		0xaf08
+-#define LINK_TMR_H_BASEX		0x002f
+-
+-/* SGMII IF Mode defines */
+-#define IF_MODE_USE_SGMII_AN		0x0002
+-#define IF_MODE_SGMII_EN		0x0001
+-#define IF_MODE_SGMII_SPEED_100M	0x0004
+-#define IF_MODE_SGMII_SPEED_1G		0x0008
+-#define IF_MODE_SGMII_DUPLEX_HALF	0x0010
+-
+ /* Num of additional exact match MAC adr regs */
+ #define MEMAC_NUM_OF_PADDRS 7
+ 
+@@ -326,7 +295,9 @@ struct fman_mac {
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
+ 	struct phy *serdes;
+-	struct phy_device *pcsphy;
++	struct phylink_pcs *sgmii_pcs;
++	struct phylink_pcs *qsgmii_pcs;
++	struct phylink_pcs *xfi_pcs;
+ 	bool allmulti_enabled;
+ };
+ 
+@@ -487,91 +458,22 @@ static u32 get_mac_addr_hash_code(u64 et
+ 	return xor_val;
+ }
+ 
+-static void setup_sgmii_internal_phy(struct fman_mac *memac,
+-				     struct fixed_phy_status *fixed_link)
+-{
+-	u16 tmp_reg16;
+-
+-	if (WARN_ON(!memac->pcsphy))
+-		return;
+-
+-	/* SGMII mode */
+-	tmp_reg16 = IF_MODE_SGMII_EN;
+-	if (!fixed_link)
+-		/* AN enable */
+-		tmp_reg16 |= IF_MODE_USE_SGMII_AN;
+-	else {
+-		switch (fixed_link->speed) {
+-		case 10:
+-			/* For 10M: IF_MODE[SPEED_10M] = 0 */
+-		break;
+-		case 100:
+-			tmp_reg16 |= IF_MODE_SGMII_SPEED_100M;
+-		break;
+-		case 1000:
+-		default:
+-			tmp_reg16 |= IF_MODE_SGMII_SPEED_1G;
+-		break;
+-		}
+-		if (!fixed_link->duplex)
+-			tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF;
+-	}
+-	phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16);
+-
+-	/* Device ability according to SGMII specification */
+-	tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE;
+-	phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
+-
+-	/* Adjust link timer for SGMII  -
+-	 * According to Cisco SGMII specification the timer should be 1.6 ms.
+-	 * The link_timer register is configured in units of the clock.
+-	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
+-	 * unit = 1 / (125*10^6 Hz) = 8 ns.
+-	 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40
+-	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
+-	 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
+-	 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120.
+-	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
+-	 * we always set up here a value of 2.5 SGMII.
+-	 */
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H);
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L);
+-
+-	if (!fixed_link)
+-		/* Restart AN */
+-		tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
++static void setup_sgmii_internal(struct fman_mac *memac,
++				 struct phylink_pcs *pcs,
++				 struct fixed_phy_status *fixed_link)
++{
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
++	phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
++				PHY_INTERFACE_MODE_SGMII;
++	unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
++
++	linkmode_set_pause(advertising, true, true);
++	pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
++	if (fixed_link)
++		pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
++				      fixed_link->duplex);
+ 	else
+-		/* AN disabled */
+-		tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN;
+-	phy_write(memac->pcsphy, 0x0, tmp_reg16);
+-}
+-
+-static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac)
+-{
+-	u16 tmp_reg16;
+-
+-	/* AN Device capability  */
+-	tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE;
+-	phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
+-
+-	/* Adjust link timer for SGMII  -
+-	 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
+-	 * The link_timer register is configured in units of the clock.
+-	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
+-	 * unit = 1 / (125*10^6 Hz) = 8 ns.
+-	 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
+-	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
+-	 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
+-	 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
+-	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
+-	 * we always set up here a value of 2.5 SGMII.
+-	 */
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX);
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX);
+-
+-	/* Restart AN */
+-	tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
+-	phy_write(memac->pcsphy, 0x0, tmp_reg16);
++		pcs->ops->pcs_an_restart(pcs);
+ }
+ 
+ static int check_init_parameters(struct fman_mac *memac)
+@@ -983,7 +885,6 @@ static int memac_set_exception(struct fm
+ static int memac_init(struct fman_mac *memac)
+ {
+ 	struct memac_cfg *memac_drv_param;
+-	u8 i;
+ 	enet_addr_t eth_addr;
+ 	bool slow_10g_if = false;
+ 	struct fixed_phy_status *fixed_link = NULL;
+@@ -1036,32 +937,10 @@ static int memac_init(struct fman_mac *m
+ 		iowrite32be(reg32, &memac->regs->command_config);
+ 	}
+ 
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) {
+-		/* Configure internal SGMII PHY */
+-		if (memac->basex_if)
+-			setup_sgmii_internal_phy_base_x(memac);
+-		else
+-			setup_sgmii_internal_phy(memac, fixed_link);
+-	} else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
+-		/* Configure 4 internal SGMII PHYs */
+-		for (i = 0; i < 4; i++) {
+-			u8 qsmgii_phy_addr, phy_addr;
+-			/* QSGMII PHY address occupies 3 upper bits of 5-bit
+-			 * phy_address; the lower 2 bits are used to extend
+-			 * register address space and access each one of 4
+-			 * ports inside QSGMII.
+-			 */
+-			phy_addr = memac->pcsphy->mdio.addr;
+-			qsmgii_phy_addr = (u8)((phy_addr << 2) | i);
+-			memac->pcsphy->mdio.addr = qsmgii_phy_addr;
+-			if (memac->basex_if)
+-				setup_sgmii_internal_phy_base_x(memac);
+-			else
+-				setup_sgmii_internal_phy(memac, fixed_link);
+-
+-			memac->pcsphy->mdio.addr = phy_addr;
+-		}
+-	}
++	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
++		setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
++	else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
++		setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
+ 
+ 	/* Max Frame Length */
+ 	err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
+@@ -1097,12 +976,25 @@ static int memac_init(struct fman_mac *m
+ 	return 0;
+ }
+ 
++static void pcs_put(struct phylink_pcs *pcs)
++{
++	struct mdio_device *mdiodev;
++
++	if (IS_ERR_OR_NULL(pcs))
++		return;
++
++	mdiodev = lynx_get_mdio_device(pcs);
++	lynx_pcs_destroy(pcs);
++	mdio_device_free(mdiodev);
++}
++
+ static int memac_free(struct fman_mac *memac)
+ {
+ 	free_init_resources(memac);
+ 
+-	if (memac->pcsphy)
+-		put_device(&memac->pcsphy->mdio.dev);
++	pcs_put(memac->sgmii_pcs);
++	pcs_put(memac->qsgmii_pcs);
++	pcs_put(memac->xfi_pcs);
+ 
+ 	kfree(memac->memac_drv_param);
+ 	kfree(memac);
+@@ -1153,12 +1045,31 @@ static struct fman_mac *memac_config(str
+ 	return memac;
+ }
+ 
++static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,
++					    int index)
++{
++	struct device_node *node;
++	struct mdio_device *mdiodev = NULL;
++	struct phylink_pcs *pcs;
++
++	node = of_parse_phandle(mac_node, "pcsphy-handle", index);
++	if (node && of_device_is_available(node))
++		mdiodev = of_mdio_find_device(node);
++	of_node_put(node);
++
++	if (!mdiodev)
++		return ERR_PTR(-EPROBE_DEFER);
++
++	pcs = lynx_pcs_create(mdiodev);
++	return pcs;
++}
++
+ int memac_initialization(struct mac_device *mac_dev,
+ 			 struct device_node *mac_node,
+ 			 struct fman_mac_params *params)
+ {
+ 	int			 err;
+-	struct device_node	*phy_node;
++	struct phylink_pcs	*pcs;
+ 	struct fixed_phy_status *fixed_link;
+ 	struct fman_mac		*memac;
+ 
+@@ -1188,23 +1099,58 @@ int memac_initialization(struct mac_devi
+ 	memac = mac_dev->fman_mac;
+ 	memac->memac_drv_param->max_frame_length = fman_get_max_frm();
+ 	memac->memac_drv_param->reset_on_init = true;
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
+-	    memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
+-		phy_node = of_parse_phandle(mac_node, "pcsphy-handle", 0);
+-		if (!phy_node) {
+-			pr_err("PCS PHY node is not available\n");
+-			err = -EINVAL;
++
++	err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");
++	if (err >= 0) {
++		memac->xfi_pcs = memac_pcs_create(mac_node, err);
++		if (IS_ERR(memac->xfi_pcs)) {
++			err = PTR_ERR(memac->xfi_pcs);
++			dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");
+ 			goto _return_fm_mac_free;
+ 		}
++	} else if (err != -EINVAL && err != -ENODATA) {
++		goto _return_fm_mac_free;
++	}
+ 
+-		memac->pcsphy = of_phy_find_device(phy_node);
+-		if (!memac->pcsphy) {
+-			pr_err("of_phy_find_device (PCS PHY) failed\n");
+-			err = -EINVAL;
++	err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");
++	if (err >= 0) {
++		memac->qsgmii_pcs = memac_pcs_create(mac_node, err);
++		if (IS_ERR(memac->qsgmii_pcs)) {
++			err = PTR_ERR(memac->qsgmii_pcs);
++			dev_err_probe(mac_dev->dev, err,
++				      "missing qsgmii pcs\n");
+ 			goto _return_fm_mac_free;
+ 		}
++	} else if (err != -EINVAL && err != -ENODATA) {
++		goto _return_fm_mac_free;
++	}
++
++	/* For compatibility, if pcs-handle-names is missing, we assume this
++	 * phy is the first one in pcsphy-handle
++	 */
++	err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");
++	if (err == -EINVAL || err == -ENODATA)
++		pcs = memac_pcs_create(mac_node, 0);
++	else if (err < 0)
++		goto _return_fm_mac_free;
++	else
++		pcs = memac_pcs_create(mac_node, err);
++
++	if (!pcs) {
++		dev_err(mac_dev->dev, "missing pcs\n");
++		err = -ENOENT;
++		goto _return_fm_mac_free;
+ 	}
+ 
++	/* If err is set here, it means that pcs-handle-names was missing above
++	 * (and therefore that xfi_pcs cannot be set). If we are defaulting to
++	 * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.
++	 */
++	if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		memac->xfi_pcs = pcs;
++	else
++		memac->sgmii_pcs = pcs;
++
+ 	memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
+ 	err = PTR_ERR(memac->serdes);
+ 	if (err == -ENODEV || err == -ENOSYS) {
diff --git a/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch
new file mode 100644
index 0000000000..63b651bb2d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch
@@ -0,0 +1,2451 @@
+From 38e50fc3d43882a43115b4f1ca3eb88255163c5b Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:38 -0400
+Subject: [PATCH 03/21] net: dpaa: Convert to phylink
+
+This converts DPAA to phylink. All macs are converted. This should work
+with no device tree modifications (including those made in this series),
+except for QSGMII (as noted previously).
+
+The mEMAC configuration is one of the tricker areas. I have tried to
+capture all the restrictions across the various models. Most of the time,
+we assume that if the serdes supports a mode or the phy-interface-mode
+specifies it, then we support it. The only place we can't do this is
+(RG)MII, since there's no serdes. In that case, we rely on a (new)
+devicetree property. There are also several cases where half-duplex is
+broken. Unfortunately, only a single compatible is used for the MAC, so we
+have to use the board compatible instead.
+
+The 10GEC conversion is very straightforward, since it only supports XAUI.
+There is generally nothing to configure.
+
+The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
+don't support configuring the SerDes (though this can be easily added) and
+we don't have multiple PCSs. From what I can tell, there's nothing
+different in the driver or documentation between SGMII and 1000BASE-X
+except for the advertising. Similarly, I couldn't find anything about
+2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
+by any in-tree boards. Similarly, despite being mentioned in the driver, I
+couldn't find any documented SoCs which supported QSGMII.  I have left it
+unimplemented for now.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/freescale/dpaa/Kconfig   |   4 +-
+ .../net/ethernet/freescale/dpaa/dpaa_eth.c    |  89 +--
+ .../ethernet/freescale/dpaa/dpaa_ethtool.c    |  90 +--
+ drivers/net/ethernet/freescale/fman/Kconfig   |   1 -
+ .../net/ethernet/freescale/fman/fman_dtsec.c  | 458 +++++++--------
+ .../net/ethernet/freescale/fman/fman_mac.h    |  10 -
+ .../net/ethernet/freescale/fman/fman_memac.c  | 547 +++++++++---------
+ .../net/ethernet/freescale/fman/fman_tgec.c   | 131 ++---
+ drivers/net/ethernet/freescale/fman/mac.c     | 168 +-----
+ drivers/net/ethernet/freescale/fman/mac.h     |  23 +-
+ 10 files changed, 612 insertions(+), 909 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/dpaa/Kconfig
++++ b/drivers/net/ethernet/freescale/dpaa/Kconfig
+@@ -2,8 +2,8 @@
+ menuconfig FSL_DPAA_ETH
+ 	tristate "DPAA Ethernet"
+ 	depends on FSL_DPAA && FSL_FMAN
+-	select PHYLIB
+-	select FIXED_PHY
++	select PHYLINK
++	select PCS_LYNX
+ 	help
+ 	  Data Path Acceleration Architecture Ethernet driver,
+ 	  supporting the Freescale QorIQ chips.
+--- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
++++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+@@ -264,8 +264,19 @@ static int dpaa_netdev_init(struct net_d
+ 	net_dev->needed_headroom = priv->tx_headroom;
+ 	net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
+ 
+-	mac_dev->net_dev = net_dev;
++	/* The rest of the config is filled in by the mac device already */
++	mac_dev->phylink_config.dev = &net_dev->dev;
++	mac_dev->phylink_config.type = PHYLINK_NETDEV;
+ 	mac_dev->update_speed = dpaa_eth_cgr_set_speed;
++	mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
++					  dev_fwnode(mac_dev->dev),
++					  mac_dev->phy_if,
++					  mac_dev->phylink_ops);
++	if (IS_ERR(mac_dev->phylink)) {
++		err = PTR_ERR(mac_dev->phylink);
++		dev_err_probe(dev, err, "Could not create phylink\n");
++		return err;
++	}
+ 
+ 	/* start without the RUNNING flag, phylib controls it later */
+ 	netif_carrier_off(net_dev);
+@@ -273,6 +284,7 @@ static int dpaa_netdev_init(struct net_d
+ 	err = register_netdev(net_dev);
+ 	if (err < 0) {
+ 		dev_err(dev, "register_netdev() = %d\n", err);
++		phylink_destroy(mac_dev->phylink);
+ 		return err;
+ 	}
+ 
+@@ -295,8 +307,7 @@ static int dpaa_stop(struct net_device *
+ 	 */
+ 	msleep(200);
+ 
+-	if (mac_dev->phy_dev)
+-		phy_stop(mac_dev->phy_dev);
++	phylink_stop(mac_dev->phylink);
+ 	mac_dev->disable(mac_dev->fman_mac);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
+@@ -305,8 +316,7 @@ static int dpaa_stop(struct net_device *
+ 			err = error;
+ 	}
+ 
+-	if (net_dev->phydev)
+-		phy_disconnect(net_dev->phydev);
++	phylink_disconnect_phy(mac_dev->phylink);
+ 	net_dev->phydev = NULL;
+ 
+ 	msleep(200);
+@@ -834,10 +844,10 @@ static int dpaa_eth_cgr_init(struct dpaa
+ 
+ 	/* Set different thresholds based on the configured MAC speed.
+ 	 * This may turn suboptimal if the MAC is reconfigured at another
+-	 * speed, so MACs must call dpaa_eth_cgr_set_speed in their adjust_link
++	 * speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
+ 	 * callback.
+ 	 */
+-	if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
++	if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
+ 		cs_th = DPAA_CS_THRESHOLD_10G;
+ 	else
+ 		cs_th = DPAA_CS_THRESHOLD_1G;
+@@ -866,7 +876,7 @@ out_error:
+ 
+ static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
+ {
+-	struct net_device *net_dev = mac_dev->net_dev;
++	struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
+ 	struct dpaa_priv *priv = netdev_priv(net_dev);
+ 	struct qm_mcc_initcgr opts = { };
+ 	u32 cs_th;
+@@ -2905,58 +2915,6 @@ static void dpaa_eth_napi_disable(struct
+ 	}
+ }
+ 
+-static void dpaa_adjust_link(struct net_device *net_dev)
+-{
+-	struct mac_device *mac_dev;
+-	struct dpaa_priv *priv;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-	mac_dev->adjust_link(mac_dev);
+-}
+-
+-/* The Aquantia PHYs are capable of performing rate adaptation */
+-#define PHY_VEND_AQUANTIA	0x03a1b400
+-#define PHY_VEND_AQUANTIA2	0x31c31c00
+-
+-static int dpaa_phy_init(struct net_device *net_dev)
+-{
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+-	struct mac_device *mac_dev;
+-	struct phy_device *phy_dev;
+-	struct dpaa_priv *priv;
+-	u32 phy_vendor;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
+-				 &dpaa_adjust_link, 0,
+-				 mac_dev->phy_if);
+-	if (!phy_dev) {
+-		netif_err(priv, ifup, net_dev, "init_phy() failed\n");
+-		return -ENODEV;
+-	}
+-
+-	phy_vendor = phy_dev->drv->phy_id & GENMASK(31, 10);
+-	/* Unless the PHY is capable of rate adaptation */
+-	if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII ||
+-	    (phy_vendor != PHY_VEND_AQUANTIA &&
+-	     phy_vendor != PHY_VEND_AQUANTIA2)) {
+-		/* remove any features not supported by the controller */
+-		ethtool_convert_legacy_u32_to_link_mode(mask,
+-							mac_dev->if_support);
+-		linkmode_and(phy_dev->supported, phy_dev->supported, mask);
+-	}
+-
+-	phy_support_asym_pause(phy_dev);
+-
+-	mac_dev->phy_dev = phy_dev;
+-	net_dev->phydev = phy_dev;
+-
+-	return 0;
+-}
+-
+ static int dpaa_open(struct net_device *net_dev)
+ {
+ 	struct mac_device *mac_dev;
+@@ -2967,7 +2925,8 @@ static int dpaa_open(struct net_device *
+ 	mac_dev = priv->mac_dev;
+ 	dpaa_eth_napi_enable(priv);
+ 
+-	err = dpaa_phy_init(net_dev);
++	err = phylink_of_phy_connect(mac_dev->phylink,
++				     mac_dev->dev->of_node, 0);
+ 	if (err)
+ 		goto phy_init_failed;
+ 
+@@ -2982,7 +2941,7 @@ static int dpaa_open(struct net_device *
+ 		netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
+ 		goto mac_start_failed;
+ 	}
+-	phy_start(priv->mac_dev->phy_dev);
++	phylink_start(mac_dev->phylink);
+ 
+ 	netif_tx_start_all_queues(net_dev);
+ 
+@@ -2991,6 +2950,7 @@ static int dpaa_open(struct net_device *
+ mac_start_failed:
+ 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
+ 		fman_port_disable(mac_dev->port[i]);
++	phylink_disconnect_phy(mac_dev->phylink);
+ 
+ phy_init_failed:
+ 	dpaa_eth_napi_disable(priv);
+@@ -3146,10 +3106,12 @@ static int dpaa_ts_ioctl(struct net_devi
+ static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
+ {
+ 	int ret = -EINVAL;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
+ 
+ 	if (cmd == SIOCGMIIREG) {
+ 		if (net_dev->phydev)
+-			return phy_mii_ioctl(net_dev->phydev, rq, cmd);
++			return phylink_mii_ioctl(priv->mac_dev->phylink, rq,
++						 cmd);
+ 	}
+ 
+ 	if (cmd == SIOCSHWTSTAMP)
+@@ -3552,6 +3514,7 @@ static int dpaa_remove(struct platform_d
+ 
+ 	dev_set_drvdata(dev, NULL);
+ 	unregister_netdev(net_dev);
++	phylink_destroy(priv->mac_dev->phylink);
+ 
+ 	err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
+ 
+--- a/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
++++ b/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
+@@ -54,27 +54,19 @@ static char dpaa_stats_global[][ETH_GSTR
+ static int dpaa_get_link_ksettings(struct net_device *net_dev,
+ 				   struct ethtool_link_ksettings *cmd)
+ {
+-	if (!net_dev->phydev)
+-		return 0;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	phy_ethtool_ksettings_get(net_dev->phydev, cmd);
+-
+-	return 0;
++	return phylink_ethtool_ksettings_get(mac_dev->phylink, cmd);
+ }
+ 
+ static int dpaa_set_link_ksettings(struct net_device *net_dev,
+ 				   const struct ethtool_link_ksettings *cmd)
+ {
+-	int err;
+-
+-	if (!net_dev->phydev)
+-		return -ENODEV;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	err = phy_ethtool_ksettings_set(net_dev->phydev, cmd);
+-	if (err < 0)
+-		netdev_err(net_dev, "phy_ethtool_ksettings_set() = %d\n", err);
+-
+-	return err;
++	return phylink_ethtool_ksettings_set(mac_dev->phylink, cmd);
+ }
+ 
+ static void dpaa_get_drvinfo(struct net_device *net_dev,
+@@ -99,80 +91,28 @@ static void dpaa_set_msglevel(struct net
+ 
+ static int dpaa_nway_reset(struct net_device *net_dev)
+ {
+-	int err;
+-
+-	if (!net_dev->phydev)
+-		return -ENODEV;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	err = 0;
+-	if (net_dev->phydev->autoneg) {
+-		err = phy_start_aneg(net_dev->phydev);
+-		if (err < 0)
+-			netdev_err(net_dev, "phy_start_aneg() = %d\n",
+-				   err);
+-	}
+-
+-	return err;
++	return phylink_ethtool_nway_reset(mac_dev->phylink);
+ }
+ 
+ static void dpaa_get_pauseparam(struct net_device *net_dev,
+ 				struct ethtool_pauseparam *epause)
+ {
+-	struct mac_device *mac_dev;
+-	struct dpaa_priv *priv;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	if (!net_dev->phydev)
+-		return;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	epause->autoneg = mac_dev->autoneg_pause;
+-	epause->rx_pause = mac_dev->rx_pause_active;
+-	epause->tx_pause = mac_dev->tx_pause_active;
++	phylink_ethtool_get_pauseparam(mac_dev->phylink, epause);
+ }
+ 
+ static int dpaa_set_pauseparam(struct net_device *net_dev,
+ 			       struct ethtool_pauseparam *epause)
+ {
+-	struct mac_device *mac_dev;
+-	struct phy_device *phydev;
+-	bool rx_pause, tx_pause;
+-	struct dpaa_priv *priv;
+-	int err;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	phydev = net_dev->phydev;
+-	if (!phydev) {
+-		netdev_err(net_dev, "phy device not initialized\n");
+-		return -ENODEV;
+-	}
+-
+-	if (!phy_validate_pause(phydev, epause))
+-		return -EINVAL;
+-
+-	/* The MAC should know how to handle PAUSE frame autonegotiation before
+-	 * adjust_link is triggered by a forced renegotiation of sym/asym PAUSE
+-	 * settings.
+-	 */
+-	mac_dev->autoneg_pause = !!epause->autoneg;
+-	mac_dev->rx_pause_req = !!epause->rx_pause;
+-	mac_dev->tx_pause_req = !!epause->tx_pause;
+-
+-	/* Determine the sym/asym advertised PAUSE capabilities from the desired
+-	 * rx/tx pause settings.
+-	 */
+-
+-	phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause);
+-
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		netdev_err(net_dev, "set_mac_active_pause() = %d\n", err);
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	return err;
++	return phylink_ethtool_set_pauseparam(mac_dev->phylink, epause);
+ }
+ 
+ static int dpaa_get_sset_count(struct net_device *net_dev, int type)
+--- a/drivers/net/ethernet/freescale/fman/Kconfig
++++ b/drivers/net/ethernet/freescale/fman/Kconfig
+@@ -3,7 +3,6 @@ config FSL_FMAN
+ 	tristate "FMan support"
+ 	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
+ 	select GENERIC_ALLOCATOR
+-	select PHYLIB
+ 	select PHYLINK
+ 	select PCS
+ 	select PCS_LYNX
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -17,6 +17,7 @@
+ #include <linux/crc32.h>
+ #include <linux/of_mdio.h>
+ #include <linux/mii.h>
++#include <linux/netdevice.h>
+ 
+ /* TBI register addresses */
+ #define MII_TBICON		0x11
+@@ -29,9 +30,6 @@
+ #define TBICON_CLK_SELECT	0x0020	/* Clock select */
+ #define TBICON_MI_MODE		0x0010	/* GMII mode (TBI if not set) */
+ 
+-#define TBIANA_SGMII		0x4001
+-#define TBIANA_1000X		0x01a0
+-
+ /* Interrupt Mask Register (IMASK) */
+ #define DTSEC_IMASK_BREN	0x80000000
+ #define DTSEC_IMASK_RXCEN	0x40000000
+@@ -92,9 +90,10 @@
+ 
+ #define DTSEC_ECNTRL_GMIIM		0x00000040
+ #define DTSEC_ECNTRL_TBIM		0x00000020
+-#define DTSEC_ECNTRL_SGMIIM		0x00000002
+ #define DTSEC_ECNTRL_RPM		0x00000010
+ #define DTSEC_ECNTRL_R100M		0x00000008
++#define DTSEC_ECNTRL_RMM		0x00000004
++#define DTSEC_ECNTRL_SGMIIM		0x00000002
+ #define DTSEC_ECNTRL_QSGMIIM		0x00000001
+ 
+ #define TCTRL_TTSE			0x00000040
+@@ -318,7 +317,8 @@ struct fman_mac {
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
+-	struct phy_device *tbiphy;
++	struct mdio_device *tbidev;
++	struct phylink_pcs pcs;
+ };
+ 
+ static void set_dflts(struct dtsec_cfg *cfg)
+@@ -356,56 +356,14 @@ static int init(struct dtsec_regs __iome
+ 		phy_interface_t iface, u16 iface_speed, u64 addr,
+ 		u32 exception_mask, u8 tbi_addr)
+ {
+-	bool is_rgmii, is_sgmii, is_qsgmii;
+ 	enet_addr_t eth_addr;
+-	u32 tmp;
++	u32 tmp = 0;
+ 	int i;
+ 
+ 	/* Soft reset */
+ 	iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
+ 	iowrite32be(0, &regs->maccfg1);
+ 
+-	/* dtsec_id2 */
+-	tmp = ioread32be(&regs->tsec_id2);
+-
+-	/* check RGMII support */
+-	if (iface == PHY_INTERFACE_MODE_RGMII ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_RXID ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_TXID ||
+-	    iface == PHY_INTERFACE_MODE_RMII)
+-		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+-			return -EINVAL;
+-
+-	if (iface == PHY_INTERFACE_MODE_SGMII ||
+-	    iface == PHY_INTERFACE_MODE_MII)
+-		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+-			return -EINVAL;
+-
+-	is_rgmii = iface == PHY_INTERFACE_MODE_RGMII ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_ID ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_RXID ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_TXID;
+-	is_sgmii = iface == PHY_INTERFACE_MODE_SGMII;
+-	is_qsgmii = iface == PHY_INTERFACE_MODE_QSGMII;
+-
+-	tmp = 0;
+-	if (is_rgmii || iface == PHY_INTERFACE_MODE_GMII)
+-		tmp |= DTSEC_ECNTRL_GMIIM;
+-	if (is_sgmii)
+-		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
+-	if (is_qsgmii)
+-		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
+-			DTSEC_ECNTRL_QSGMIIM);
+-	if (is_rgmii)
+-		tmp |= DTSEC_ECNTRL_RPM;
+-	if (iface_speed == SPEED_100)
+-		tmp |= DTSEC_ECNTRL_R100M;
+-
+-	iowrite32be(tmp, &regs->ecntrl);
+-
+-	tmp = 0;
+-
+ 	if (cfg->tx_pause_time)
+ 		tmp |= cfg->tx_pause_time;
+ 	if (cfg->tx_pause_time_extd)
+@@ -446,17 +404,10 @@ static int init(struct dtsec_regs __iome
+ 
+ 	tmp = 0;
+ 
+-	if (iface_speed < SPEED_1000)
+-		tmp |= MACCFG2_NIBBLE_MODE;
+-	else if (iface_speed == SPEED_1000)
+-		tmp |= MACCFG2_BYTE_MODE;
+-
+ 	tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) &
+ 		MACCFG2_PREAMBLE_LENGTH_MASK;
+ 	if (cfg->tx_pad_crc)
+ 		tmp |= MACCFG2_PAD_CRC_EN;
+-	/* Full Duplex */
+-	tmp |= MACCFG2_FULL_DUPLEX;
+ 	iowrite32be(tmp, &regs->maccfg2);
+ 
+ 	tmp = (((cfg->non_back_to_back_ipg1 <<
+@@ -525,10 +476,6 @@ static void set_bucket(struct dtsec_regs
+ 
+ static int check_init_parameters(struct fman_mac *dtsec)
+ {
+-	if (dtsec->max_speed >= SPEED_10000) {
+-		pr_err("1G MAC driver supports 1G or lower speeds\n");
+-		return -EINVAL;
+-	}
+ 	if ((dtsec->dtsec_drv_param)->rx_prepend >
+ 	    MAX_PACKET_ALIGNMENT) {
+ 		pr_err("packetAlignmentPadding can't be > than %d\n",
+@@ -630,22 +577,10 @@ static int get_exception_flag(enum fman_
+ 	return bit_mask;
+ }
+ 
+-static bool is_init_done(struct dtsec_cfg *dtsec_drv_params)
+-{
+-	/* Checks if dTSEC driver parameters were initialized */
+-	if (!dtsec_drv_params)
+-		return true;
+-
+-	return false;
+-}
+-
+ static u16 dtsec_get_max_frame_length(struct fman_mac *dtsec)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 
+-	if (is_init_done(dtsec->dtsec_drv_param))
+-		return 0;
+-
+ 	return (u16)ioread32be(&regs->maxfrm);
+ }
+ 
+@@ -682,6 +617,7 @@ static void dtsec_isr(void *handle)
+ 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT);
+ 	if (event & DTSEC_IMASK_XFUNEN) {
+ 		/* FM_TX_LOCKUP_ERRATA_DTSEC6 Errata workaround */
++		/* FIXME: This races with the rest of the driver! */
+ 		if (dtsec->fm_rev_info.major == 2) {
+ 			u32 tpkt1, tmp_reg1, tpkt2, tmp_reg2, i;
+ 			/* a. Write 0x00E0_0C00 to DTSEC_ID
+@@ -814,6 +750,43 @@ static void free_init_resources(struct f
+ 	dtsec->unicast_addr_hash = NULL;
+ }
+ 
++static struct fman_mac *pcs_to_dtsec(struct phylink_pcs *pcs)
++{
++	return container_of(pcs, struct fman_mac, pcs);
++}
++
++static void dtsec_pcs_get_state(struct phylink_pcs *pcs,
++				struct phylink_link_state *state)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
++}
++
++static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++			    phy_interface_t interface,
++			    const unsigned long *advertising,
++			    bool permit_pause_to_mac)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
++					  advertising);
++}
++
++static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	phylink_mii_c22_pcs_an_restart(dtsec->tbidev);
++}
++
++static const struct phylink_pcs_ops dtsec_pcs_ops = {
++	.pcs_get_state = dtsec_pcs_get_state,
++	.pcs_config = dtsec_pcs_config,
++	.pcs_an_restart = dtsec_pcs_an_restart,
++};
++
+ static void graceful_start(struct fman_mac *dtsec)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+@@ -854,36 +827,11 @@ static void graceful_stop(struct fman_ma
+ 
+ static int dtsec_enable(struct fman_mac *dtsec)
+ {
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	/* Enable */
+-	tmp = ioread32be(&regs->maccfg1);
+-	tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
+-	iowrite32be(tmp, &regs->maccfg1);
+-
+-	/* Graceful start - clear the graceful Rx/Tx stop bit */
+-	graceful_start(dtsec);
+-
+ 	return 0;
+ }
+ 
+ static void dtsec_disable(struct fman_mac *dtsec)
+ {
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(dtsec->dtsec_drv_param));
+-
+-	/* Graceful stop - Assert the graceful Rx/Tx stop bit */
+-	graceful_stop(dtsec);
+-
+-	tmp = ioread32be(&regs->maccfg1);
+-	tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
+-	iowrite32be(tmp, &regs->maccfg1);
+ }
+ 
+ static int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
+@@ -894,11 +842,6 @@ static int dtsec_set_tx_pause_frames(str
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 ptv = 0;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+ 	if (pause_time) {
+ 		/* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
+ 		if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {
+@@ -919,8 +862,6 @@ static int dtsec_set_tx_pause_frames(str
+ 		iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
+ 			    &regs->maccfg1);
+ 
+-	graceful_start(dtsec);
+-
+ 	return 0;
+ }
+ 
+@@ -929,11 +870,6 @@ static int dtsec_accept_rx_pause_frames(
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+ 	tmp = ioread32be(&regs->maccfg1);
+ 	if (en)
+ 		tmp |= MACCFG1_RX_FLOW;
+@@ -941,17 +877,125 @@ static int dtsec_accept_rx_pause_frames(
+ 		tmp &= ~MACCFG1_RX_FLOW;
+ 	iowrite32be(tmp, &regs->maccfg1);
+ 
++	return 0;
++}
++
++static struct phylink_pcs *dtsec_select_pcs(struct phylink_config *config,
++					    phy_interface_t iface)
++{
++	struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		return &dtsec->pcs;
++	default:
++		return NULL;
++	}
++}
++
++static void dtsec_mac_config(struct phylink_config *config, unsigned int mode,
++			     const struct phylink_link_state *state)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct dtsec_regs __iomem *regs = mac_dev->fman_mac->regs;
++	u32 tmp;
++
++	switch (state->interface) {
++	case PHY_INTERFACE_MODE_RMII:
++		tmp = DTSEC_ECNTRL_RMM;
++		break;
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++		tmp = DTSEC_ECNTRL_GMIIM | DTSEC_ECNTRL_RPM;
++		break;
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		tmp = DTSEC_ECNTRL_TBIM | DTSEC_ECNTRL_SGMIIM;
++		break;
++	default:
++		dev_warn(mac_dev->dev, "cannot configure dTSEC for %s\n",
++			 phy_modes(state->interface));
++		return;
++	}
++
++	iowrite32be(tmp, &regs->ecntrl);
++}
++
++static void dtsec_link_up(struct phylink_config *config, struct phy_device *phy,
++			  unsigned int mode, phy_interface_t interface,
++			  int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *dtsec = mac_dev->fman_mac;
++	struct dtsec_regs __iomem *regs = dtsec->regs;
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++	u32 tmp;
++
++	dtsec_set_tx_pause_frames(dtsec, 0, pause_time, 0);
++	dtsec_accept_rx_pause_frames(dtsec, rx_pause);
++
++	tmp = ioread32be(&regs->ecntrl);
++	if (speed == SPEED_100)
++		tmp |= DTSEC_ECNTRL_R100M;
++	else
++		tmp &= ~DTSEC_ECNTRL_R100M;
++	iowrite32be(tmp, &regs->ecntrl);
++
++	tmp = ioread32be(&regs->maccfg2);
++	tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE | MACCFG2_FULL_DUPLEX);
++	if (speed >= SPEED_1000)
++		tmp |= MACCFG2_BYTE_MODE;
++	else
++		tmp |= MACCFG2_NIBBLE_MODE;
++
++	if (duplex == DUPLEX_FULL)
++		tmp |= MACCFG2_FULL_DUPLEX;
++
++	iowrite32be(tmp, &regs->maccfg2);
++
++	mac_dev->update_speed(mac_dev, speed);
++
++	/* Enable */
++	tmp = ioread32be(&regs->maccfg1);
++	tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
++	iowrite32be(tmp, &regs->maccfg1);
++
++	/* Graceful start - clear the graceful Rx/Tx stop bit */
+ 	graceful_start(dtsec);
++}
+ 
+-	return 0;
++static void dtsec_link_down(struct phylink_config *config, unsigned int mode,
++			    phy_interface_t interface)
++{
++	struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
++	struct dtsec_regs __iomem *regs = dtsec->regs;
++	u32 tmp;
++
++	/* Graceful stop - Assert the graceful Rx/Tx stop bit */
++	graceful_stop(dtsec);
++
++	tmp = ioread32be(&regs->maccfg1);
++	tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
++	iowrite32be(tmp, &regs->maccfg1);
+ }
+ 
++static const struct phylink_mac_ops dtsec_mac_ops = {
++	.validate = phylink_generic_validate,
++	.mac_select_pcs = dtsec_select_pcs,
++	.mac_config = dtsec_mac_config,
++	.mac_link_up = dtsec_link_up,
++	.mac_link_down = dtsec_link_down,
++};
++
+ static int dtsec_modify_mac_address(struct fman_mac *dtsec,
+ 				    const enet_addr_t *enet_addr)
+ {
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	graceful_stop(dtsec);
+ 
+ 	/* Initialize MAC Station Address registers (1 & 2)
+@@ -975,9 +1019,6 @@ static int dtsec_add_hash_mac_address(st
+ 	u32 crc = 0xFFFFFFFF;
+ 	bool mcast, ghtx;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
+@@ -1037,9 +1078,6 @@ static int dtsec_set_allmulti(struct fma
+ 	u32 tmp;
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->rctrl);
+ 	if (enable)
+ 		tmp |= RCTRL_MPROM;
+@@ -1056,9 +1094,6 @@ static int dtsec_set_tstamp(struct fman_
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 rctrl, tctrl;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	rctrl = ioread32be(&regs->rctrl);
+ 	tctrl = ioread32be(&regs->tctrl);
+ 
+@@ -1087,9 +1122,6 @@ static int dtsec_del_hash_mac_address(st
+ 	u32 crc = 0xFFFFFFFF;
+ 	bool mcast, ghtx;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
+@@ -1153,9 +1185,6 @@ static int dtsec_set_promiscuous(struct
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	/* Set unicast promiscuous */
+ 	tmp = ioread32be(&regs->rctrl);
+ 	if (new_val)
+@@ -1177,90 +1206,12 @@ static int dtsec_set_promiscuous(struct
+ 	return 0;
+ }
+ 
+-static int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
+-{
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+-	tmp = ioread32be(&regs->maccfg2);
+-
+-	/* Full Duplex */
+-	tmp |= MACCFG2_FULL_DUPLEX;
+-
+-	tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
+-	if (speed < SPEED_1000)
+-		tmp |= MACCFG2_NIBBLE_MODE;
+-	else if (speed == SPEED_1000)
+-		tmp |= MACCFG2_BYTE_MODE;
+-	iowrite32be(tmp, &regs->maccfg2);
+-
+-	tmp = ioread32be(&regs->ecntrl);
+-	if (speed == SPEED_100)
+-		tmp |= DTSEC_ECNTRL_R100M;
+-	else
+-		tmp &= ~DTSEC_ECNTRL_R100M;
+-	iowrite32be(tmp, &regs->ecntrl);
+-
+-	graceful_start(dtsec);
+-
+-	return 0;
+-}
+-
+-static int dtsec_restart_autoneg(struct fman_mac *dtsec)
+-{
+-	u16 tmp_reg16;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR);
+-
+-	tmp_reg16 &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
+-	tmp_reg16 |= (BMCR_ANENABLE | BMCR_ANRESTART |
+-		      BMCR_FULLDPLX | BMCR_SPEED1000);
+-
+-	phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-
+-	return 0;
+-}
+-
+-static void adjust_link_dtsec(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	struct fman_mac *fman_mac;
+-	bool rx_pause, tx_pause;
+-	int err;
+-
+-	fman_mac = mac_dev->fman_mac;
+-	if (!phy_dev->link) {
+-		dtsec_restart_autoneg(fman_mac);
+-
+-		return;
+-	}
+-
+-	dtsec_adjust_link(fman_mac, phy_dev->speed);
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
+-			err);
+-}
+-
+ static int dtsec_set_exception(struct fman_mac *dtsec,
+ 			       enum fman_mac_exceptions exception, bool enable)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	if (exception != FM_MAC_EX_1G_1588_TS_RX_ERR) {
+ 		bit_mask = get_exception_flag(exception);
+ 		if (bit_mask) {
+@@ -1310,12 +1261,9 @@ static int dtsec_init(struct fman_mac *d
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	struct dtsec_cfg *dtsec_drv_param;
+-	u16 max_frm_ln;
++	u16 max_frm_ln, tbicon;
+ 	int err;
+ 
+-	if (is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	if (DEFAULT_RESET_ON_INIT &&
+ 	    (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) {
+ 		pr_err("Can't reset MAC!\n");
+@@ -1330,38 +1278,19 @@ static int dtsec_init(struct fman_mac *d
+ 
+ 	err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if,
+ 		   dtsec->max_speed, dtsec->addr, dtsec->exceptions,
+-		   dtsec->tbiphy->mdio.addr);
++		   dtsec->tbidev->addr);
+ 	if (err) {
+ 		free_init_resources(dtsec);
+ 		pr_err("DTSEC version doesn't support this i/f mode\n");
+ 		return err;
+ 	}
+ 
+-	if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) {
+-		u16 tmp_reg16;
+-
+-		/* Configure the TBI PHY Control Register */
+-		tmp_reg16 = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
+-		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
+-
+-		tmp_reg16 = TBICON_CLK_SELECT;
+-		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
+-
+-		tmp_reg16 = (BMCR_RESET | BMCR_ANENABLE |
+-			     BMCR_FULLDPLX | BMCR_SPEED1000);
+-		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-
+-		if (dtsec->basex_if)
+-			tmp_reg16 = TBIANA_1000X;
+-		else
+-			tmp_reg16 = TBIANA_SGMII;
+-		phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16);
++	/* Configure the TBI PHY Control Register */
++	tbicon = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
++	mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
+ 
+-		tmp_reg16 = (BMCR_ANENABLE | BMCR_ANRESTART |
+-			     BMCR_FULLDPLX | BMCR_SPEED1000);
+-
+-		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-	}
++	tbicon = TBICON_CLK_SELECT;
++	mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
+ 
+ 	/* Max Frame Length */
+ 	max_frm_ln = (u16)ioread32be(&regs->maxfrm);
+@@ -1406,6 +1335,8 @@ static int dtsec_free(struct fman_mac *d
+ 
+ 	kfree(dtsec->dtsec_drv_param);
+ 	dtsec->dtsec_drv_param = NULL;
++	if (!IS_ERR_OR_NULL(dtsec->tbidev))
++		put_device(&dtsec->tbidev->dev);
+ 	kfree(dtsec);
+ 
+ 	return 0;
+@@ -1434,7 +1365,6 @@ static struct fman_mac *dtsec_config(str
+ 
+ 	dtsec->regs = mac_dev->vaddr;
+ 	dtsec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+-	dtsec->max_speed = params->max_speed;
+ 	dtsec->phy_if = mac_dev->phy_if;
+ 	dtsec->mac_id = params->mac_id;
+ 	dtsec->exceptions = (DTSEC_IMASK_BREN	|
+@@ -1457,7 +1387,6 @@ static struct fman_mac *dtsec_config(str
+ 	dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en;
+ 
+ 	dtsec->fm = params->fm;
+-	dtsec->basex_if = params->basex_if;
+ 
+ 	/* Save FMan revision */
+ 	fman_get_revision(dtsec->fm, &dtsec->fm_rev_info);
+@@ -1476,18 +1405,18 @@ int dtsec_initialization(struct mac_devi
+ 	int			err;
+ 	struct fman_mac		*dtsec;
+ 	struct device_node	*phy_node;
++	unsigned long		 capabilities;
++	unsigned long		*supported;
+ 
++	mac_dev->phylink_ops		= &dtsec_mac_ops;
+ 	mac_dev->set_promisc		= dtsec_set_promiscuous;
+ 	mac_dev->change_addr		= dtsec_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= dtsec_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= dtsec_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= dtsec_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= dtsec_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= dtsec_set_exception;
+ 	mac_dev->set_allmulti		= dtsec_set_allmulti;
+ 	mac_dev->set_tstamp		= dtsec_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = adjust_link_dtsec;
+ 	mac_dev->enable			= dtsec_enable;
+ 	mac_dev->disable		= dtsec_disable;
+ 
+@@ -1502,19 +1431,56 @@ int dtsec_initialization(struct mac_devi
+ 	dtsec->dtsec_drv_param->tx_pad_crc = true;
+ 
+ 	phy_node = of_parse_phandle(mac_node, "tbi-handle", 0);
+-	if (!phy_node) {
+-		pr_err("TBI PHY node is not available\n");
++	if (!phy_node || of_device_is_available(phy_node)) {
++		of_node_put(phy_node);
+ 		err = -EINVAL;
++		dev_err_probe(mac_dev->dev, err,
++			      "TBI PCS node is not available\n");
+ 		goto _return_fm_mac_free;
+ 	}
+ 
+-	dtsec->tbiphy = of_phy_find_device(phy_node);
+-	if (!dtsec->tbiphy) {
+-		pr_err("of_phy_find_device (TBI PHY) failed\n");
+-		err = -EINVAL;
++	dtsec->tbidev = of_mdio_find_device(phy_node);
++	of_node_put(phy_node);
++	if (!dtsec->tbidev) {
++		err = -EPROBE_DEFER;
++		dev_err_probe(mac_dev->dev, err,
++			      "could not find mdiodev for PCS\n");
+ 		goto _return_fm_mac_free;
+ 	}
+-	put_device(&dtsec->tbiphy->mdio.dev);
++	dtsec->pcs.ops = &dtsec_pcs_ops;
++	dtsec->pcs.poll = true;
++
++	supported = mac_dev->phylink_config.supported_interfaces;
++
++	/* FIXME: Can we use DTSEC_ID2_INT_FULL_OFF to determine if these are
++	 * supported? If not, we can determine support via the phy if SerDes
++	 * support is added.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII ||
++	    mac_dev->phy_if == PHY_INTERFACE_MODE_1000BASEX) {
++		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
++		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
++	} else if (mac_dev->phy_if == PHY_INTERFACE_MODE_2500BASEX) {
++		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
++	}
++
++	if (!(ioread32be(&dtsec->regs->tsec_id2) & DTSEC_ID2_INT_REDUCED_OFF)) {
++		phy_interface_set_rgmii(supported);
++
++		/* DTSEC_ID2_INT_REDUCED_OFF indicates that the dTSEC supports
++		 * RMII and RGMII. However, the only SoCs which support RMII
++		 * are the P1017 and P1023. Avoid advertising this mode on
++		 * other SoCs. This is a bit of a moot point, since there's no
++		 * in-tree support for ethernet on these platforms...
++		 */
++		if (of_machine_is_compatible("fsl,P1023") ||
++		    of_machine_is_compatible("fsl,P1023RDB"))
++			__set_bit(PHY_INTERFACE_MODE_RMII, supported);
++	}
++
++	capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
++	capabilities |= MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
++	mac_dev->phylink_config.mac_capabilities = capabilities;
+ 
+ 	err = dtsec_init(dtsec);
+ 	if (err < 0)
+--- a/drivers/net/ethernet/freescale/fman/fman_mac.h
++++ b/drivers/net/ethernet/freescale/fman/fman_mac.h
+@@ -170,20 +170,10 @@ struct fman_mac_params {
+ 	 * 0 - FM_MAX_NUM_OF_10G_MACS
+ 	 */
+ 	u8 mac_id;
+-	/* Note that the speed should indicate the maximum rate that
+-	 * this MAC should support rather than the actual speed;
+-	 */
+-	u16 max_speed;
+ 	/* A handle to the FM object this port related to */
+ 	void *fm;
+ 	fman_mac_exception_cb *event_cb;    /* MDIO Events Callback Routine */
+ 	fman_mac_exception_cb *exception_cb;/* Exception Callback Routine */
+-	/* SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
+-	 * and phy or backplane; Note: 1000BaseX auto-negotiation relates only
+-	 * to interface between MAC and phy/backplane, SGMII phy can still
+-	 * synchronize with far-end phy at 10Mbps, 100Mbps or 1000Mbps
+-	*/
+-	bool basex_if;
+ };
+ 
+ struct eth_hash_t {
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -278,9 +278,6 @@ struct fman_mac {
+ 	struct memac_regs __iomem *regs;
+ 	/* MAC address of device */
+ 	u64 addr;
+-	/* Ethernet physical interface */
+-	phy_interface_t phy_if;
+-	u16 max_speed;
+ 	struct mac_device *dev_id; /* device cookie used by the exception cbs */
+ 	fman_mac_exception_cb *exception_cb;
+ 	fman_mac_exception_cb *event_cb;
+@@ -293,12 +290,12 @@ struct fman_mac {
+ 	struct memac_cfg *memac_drv_param;
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+-	bool basex_if;
+ 	struct phy *serdes;
+ 	struct phylink_pcs *sgmii_pcs;
+ 	struct phylink_pcs *qsgmii_pcs;
+ 	struct phylink_pcs *xfi_pcs;
+ 	bool allmulti_enabled;
++	bool rgmii_no_half_duplex;
+ };
+ 
+ static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
+@@ -356,7 +353,6 @@ static void set_exception(struct memac_r
+ }
+ 
+ static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
+-		phy_interface_t phy_if, u16 speed, bool slow_10g_if,
+ 		u32 exceptions)
+ {
+ 	u32 tmp;
+@@ -384,41 +380,6 @@ static int init(struct memac_regs __iome
+ 	iowrite32be((u32)cfg->pause_quanta, &regs->pause_quanta[0]);
+ 	iowrite32be((u32)0, &regs->pause_thresh[0]);
+ 
+-	/* IF_MODE */
+-	tmp = 0;
+-	switch (phy_if) {
+-	case PHY_INTERFACE_MODE_XGMII:
+-		tmp |= IF_MODE_10G;
+-		break;
+-	case PHY_INTERFACE_MODE_MII:
+-		tmp |= IF_MODE_MII;
+-		break;
+-	default:
+-		tmp |= IF_MODE_GMII;
+-		if (phy_if == PHY_INTERFACE_MODE_RGMII ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_ID ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_RXID ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_TXID)
+-			tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
+-	}
+-	iowrite32be(tmp, &regs->if_mode);
+-
+-	/* TX_FIFO_SECTIONS */
+-	tmp = 0;
+-	if (phy_if == PHY_INTERFACE_MODE_XGMII) {
+-		if (slow_10g_if) {
+-			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
+-				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
+-		} else {
+-			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
+-				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
+-		}
+-	} else {
+-		tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
+-			TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
+-	}
+-	iowrite32be(tmp, &regs->tx_fifo_sections);
+-
+ 	/* clear all pending events and set-up interrupts */
+ 	iowrite32be(0xffffffff, &regs->ievent);
+ 	set_exception(regs, exceptions, true);
+@@ -458,24 +419,6 @@ static u32 get_mac_addr_hash_code(u64 et
+ 	return xor_val;
+ }
+ 
+-static void setup_sgmii_internal(struct fman_mac *memac,
+-				 struct phylink_pcs *pcs,
+-				 struct fixed_phy_status *fixed_link)
+-{
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
+-	phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
+-				PHY_INTERFACE_MODE_SGMII;
+-	unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
+-
+-	linkmode_set_pause(advertising, true, true);
+-	pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
+-	if (fixed_link)
+-		pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
+-				      fixed_link->duplex);
+-	else
+-		pcs->ops->pcs_an_restart(pcs);
+-}
+-
+ static int check_init_parameters(struct fman_mac *memac)
+ {
+ 	if (!memac->exception_cb) {
+@@ -581,41 +524,31 @@ static void free_init_resources(struct f
+ 	memac->unicast_addr_hash = NULL;
+ }
+ 
+-static bool is_init_done(struct memac_cfg *memac_drv_params)
+-{
+-	/* Checks if mEMAC driver parameters were initialized */
+-	if (!memac_drv_params)
+-		return true;
+-
+-	return false;
+-}
+-
+ static int memac_enable(struct fman_mac *memac)
+ {
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
++	int ret;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
++	ret = phy_init(memac->serdes);
++	if (ret) {
++		dev_err(memac->dev_id->dev,
++			"could not initialize serdes: %pe\n", ERR_PTR(ret));
++		return ret;
++	}
+ 
+-	tmp = ioread32be(&regs->command_config);
+-	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
+-	iowrite32be(tmp, &regs->command_config);
++	ret = phy_power_on(memac->serdes);
++	if (ret) {
++		dev_err(memac->dev_id->dev,
++			"could not power on serdes: %pe\n", ERR_PTR(ret));
++		phy_exit(memac->serdes);
++	}
+ 
+-	return 0;
++	return ret;
+ }
+ 
+ static void memac_disable(struct fman_mac *memac)
+-
+ {
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(memac->memac_drv_param));
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
+-	iowrite32be(tmp, &regs->command_config);
++	phy_power_off(memac->serdes);
++	phy_exit(memac->serdes);
+ }
+ 
+ static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
+@@ -623,9 +556,6 @@ static int memac_set_promiscuous(struct
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (new_val)
+ 		tmp |= CMD_CFG_PROMIS_EN;
+@@ -637,73 +567,12 @@ static int memac_set_promiscuous(struct
+ 	return 0;
+ }
+ 
+-static int memac_adjust_link(struct fman_mac *memac, u16 speed)
+-{
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+-	tmp = ioread32be(&regs->if_mode);
+-
+-	/* Set full duplex */
+-	tmp &= ~IF_MODE_HD;
+-
+-	if (phy_interface_mode_is_rgmii(memac->phy_if)) {
+-		/* Configure RGMII in manual mode */
+-		tmp &= ~IF_MODE_RGMII_AUTO;
+-		tmp &= ~IF_MODE_RGMII_SP_MASK;
+-		/* Full duplex */
+-		tmp |= IF_MODE_RGMII_FD;
+-
+-		switch (speed) {
+-		case SPEED_1000:
+-			tmp |= IF_MODE_RGMII_1000;
+-			break;
+-		case SPEED_100:
+-			tmp |= IF_MODE_RGMII_100;
+-			break;
+-		case SPEED_10:
+-			tmp |= IF_MODE_RGMII_10;
+-			break;
+-		default:
+-			break;
+-		}
+-	}
+-
+-	iowrite32be(tmp, &regs->if_mode);
+-
+-	return 0;
+-}
+-
+-static void adjust_link_memac(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	struct fman_mac *fman_mac;
+-	bool rx_pause, tx_pause;
+-	int err;
+-
+-	fman_mac = mac_dev->fman_mac;
+-	memac_adjust_link(fman_mac, phy_dev->speed);
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
+-			err);
+-}
+-
+ static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
+ 				     u16 pause_time, u16 thresh_time)
+ {
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->tx_fifo_sections);
+ 
+ 	GET_TX_EMPTY_DEFAULT_VALUE(tmp);
+@@ -738,9 +607,6 @@ static int memac_accept_rx_pause_frames(
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (en)
+ 		tmp &= ~CMD_CFG_PAUSE_IGNORE;
+@@ -752,12 +618,175 @@ static int memac_accept_rx_pause_frames(
+ 	return 0;
+ }
+ 
++static void memac_validate(struct phylink_config *config,
++			   unsigned long *supported,
++			   struct phylink_link_state *state)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++	unsigned long caps = config->mac_capabilities;
++
++	if (phy_interface_mode_is_rgmii(state->interface) &&
++	    memac->rgmii_no_half_duplex)
++		caps &= ~(MAC_10HD | MAC_100HD);
++
++	phylink_validate_mask_caps(supported, state, caps);
++}
++
++/**
++ * memac_if_mode() - Convert an interface mode into an IF_MODE config
++ * @interface: A phy interface mode
++ *
++ * Return: A configuration word, suitable for programming into the lower bits
++ *         of %IF_MODE.
++ */
++static u32 memac_if_mode(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_MII:
++		return IF_MODE_MII;
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++		return IF_MODE_GMII | IF_MODE_RGMII;
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_QSGMII:
++		return IF_MODE_GMII;
++	case PHY_INTERFACE_MODE_10GBASER:
++		return IF_MODE_10G;
++	default:
++		WARN_ON_ONCE(1);
++		return 0;
++	}
++}
++
++static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
++					    phy_interface_t iface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++		return memac->sgmii_pcs;
++	case PHY_INTERFACE_MODE_QSGMII:
++		return memac->qsgmii_pcs;
++	case PHY_INTERFACE_MODE_10GBASER:
++		return memac->xfi_pcs;
++	default:
++		return NULL;
++	}
++}
++
++static int memac_prepare(struct phylink_config *config, unsigned int mode,
++			 phy_interface_t iface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_10GBASER:
++		return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
++					iface);
++	default:
++		return 0;
++	}
++}
++
++static void memac_mac_config(struct phylink_config *config, unsigned int mode,
++			     const struct phylink_link_state *state)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
++	u32 tmp = ioread32be(&regs->if_mode);
++
++	tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
++	tmp |= memac_if_mode(state->interface);
++	if (phylink_autoneg_inband(mode))
++		tmp |= IF_MODE_RGMII_AUTO;
++	iowrite32be(tmp, &regs->if_mode);
++}
++
++static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
++			  unsigned int mode, phy_interface_t interface,
++			  int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *memac = mac_dev->fman_mac;
++	struct memac_regs __iomem *regs = memac->regs;
++	u32 tmp = memac_if_mode(interface);
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++
++	memac_set_tx_pause_frames(memac, 0, pause_time, 0);
++	memac_accept_rx_pause_frames(memac, rx_pause);
++
++	if (duplex == DUPLEX_HALF)
++		tmp |= IF_MODE_HD;
++
++	switch (speed) {
++	case SPEED_1000:
++		tmp |= IF_MODE_RGMII_1000;
++		break;
++	case SPEED_100:
++		tmp |= IF_MODE_RGMII_100;
++		break;
++	case SPEED_10:
++		tmp |= IF_MODE_RGMII_10;
++		break;
++	}
++	iowrite32be(tmp, &regs->if_mode);
++
++	/* TODO: EEE? */
++
++	if (speed == SPEED_10000) {
++		if (memac->fm_rev_info.major == 6 &&
++		    memac->fm_rev_info.minor == 4)
++			tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
++		else
++			tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
++		tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
++	} else {
++		tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
++		      TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
++	}
++	iowrite32be(tmp, &regs->tx_fifo_sections);
++
++	mac_dev->update_speed(mac_dev, speed);
++
++	tmp = ioread32be(&regs->command_config);
++	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static void memac_link_down(struct phylink_config *config, unsigned int mode,
++			    phy_interface_t interface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++	struct memac_regs __iomem *regs = memac->regs;
++	u32 tmp;
++
++	/* TODO: graceful */
++	tmp = ioread32be(&regs->command_config);
++	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static const struct phylink_mac_ops memac_mac_ops = {
++	.validate = memac_validate,
++	.mac_select_pcs = memac_select_pcs,
++	.mac_prepare = memac_prepare,
++	.mac_config = memac_mac_config,
++	.mac_link_up = memac_link_up,
++	.mac_link_down = memac_link_down,
++};
++
+ static int memac_modify_mac_address(struct fman_mac *memac,
+ 				    const enet_addr_t *enet_addr)
+ {
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
+ 
+ 	return 0;
+@@ -771,9 +800,6 @@ static int memac_add_hash_mac_address(st
+ 	u32 hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	if (!(addr & GROUP_ADDRESS)) {
+@@ -802,9 +828,6 @@ static int memac_set_allmulti(struct fma
+ 	u32 entry;
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	if (enable) {
+ 		for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
+ 			iowrite32be(entry | HASH_CTRL_MCAST_EN,
+@@ -834,9 +857,6 @@ static int memac_del_hash_mac_address(st
+ 	u32 hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
+@@ -864,9 +884,6 @@ static int memac_set_exception(struct fm
+ {
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	bit_mask = get_exception_flag(exception);
+ 	if (bit_mask) {
+ 		if (enable)
+@@ -886,23 +903,15 @@ static int memac_init(struct fman_mac *m
+ {
+ 	struct memac_cfg *memac_drv_param;
+ 	enet_addr_t eth_addr;
+-	bool slow_10g_if = false;
+-	struct fixed_phy_status *fixed_link = NULL;
+ 	int err;
+ 	u32 reg32 = 0;
+ 
+-	if (is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	err = check_init_parameters(memac);
+ 	if (err)
+ 		return err;
+ 
+ 	memac_drv_param = memac->memac_drv_param;
+ 
+-	if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
+-		slow_10g_if = true;
+-
+ 	/* First, reset the MAC if desired. */
+ 	if (memac_drv_param->reset_on_init) {
+ 		err = reset(memac->regs);
+@@ -918,10 +927,7 @@ static int memac_init(struct fman_mac *m
+ 		add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
+ 	}
+ 
+-	fixed_link = memac_drv_param->fixed_link;
+-
+-	init(memac->regs, memac->memac_drv_param, memac->phy_if,
+-	     memac->max_speed, slow_10g_if, memac->exceptions);
++	init(memac->regs, memac->memac_drv_param, memac->exceptions);
+ 
+ 	/* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
+ 	 * Exists only in FMan 6.0 and 6.3.
+@@ -937,11 +943,6 @@ static int memac_init(struct fman_mac *m
+ 		iowrite32be(reg32, &memac->regs->command_config);
+ 	}
+ 
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
+-		setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
+-	else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
+-		setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
+-
+ 	/* Max Frame Length */
+ 	err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
+ 				     memac_drv_param->max_frame_length);
+@@ -970,9 +971,6 @@ static int memac_init(struct fman_mac *m
+ 	fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
+ 			   FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
+ 
+-	kfree(memac_drv_param);
+-	memac->memac_drv_param = NULL;
+-
+ 	return 0;
+ }
+ 
+@@ -995,7 +993,6 @@ static int memac_free(struct fman_mac *m
+ 	pcs_put(memac->sgmii_pcs);
+ 	pcs_put(memac->qsgmii_pcs);
+ 	pcs_put(memac->xfi_pcs);
+-
+ 	kfree(memac->memac_drv_param);
+ 	kfree(memac);
+ 
+@@ -1028,8 +1025,6 @@ static struct fman_mac *memac_config(str
+ 	memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+ 
+ 	memac->regs = mac_dev->vaddr;
+-	memac->max_speed = params->max_speed;
+-	memac->phy_if = mac_dev->phy_if;
+ 	memac->mac_id = params->mac_id;
+ 	memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
+ 			     MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
+@@ -1037,7 +1032,6 @@ static struct fman_mac *memac_config(str
+ 	memac->event_cb = params->event_cb;
+ 	memac->dev_id = mac_dev;
+ 	memac->fm = params->fm;
+-	memac->basex_if = params->basex_if;
+ 
+ 	/* Save FMan revision */
+ 	fman_get_revision(memac->fm, &memac->fm_rev_info);
+@@ -1064,37 +1058,44 @@ static struct phylink_pcs *memac_pcs_cre
+ 	return pcs;
+ }
+ 
++static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
++{
++	/* If there's no serdes device, assume that it's been configured for
++	 * whatever the default interface mode is.
++	 */
++	if (!mac_dev->fman_mac->serdes)
++		return mac_dev->phy_if == iface;
++	/* Otherwise, ask the serdes */
++	return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
++			     iface, NULL);
++}
++
+ int memac_initialization(struct mac_device *mac_dev,
+ 			 struct device_node *mac_node,
+ 			 struct fman_mac_params *params)
+ {
+ 	int			 err;
++	struct device_node      *fixed;
+ 	struct phylink_pcs	*pcs;
+-	struct fixed_phy_status *fixed_link;
+ 	struct fman_mac		*memac;
++	unsigned long		 capabilities;
++	unsigned long		*supported;
+ 
++	mac_dev->phylink_ops		= &memac_mac_ops;
+ 	mac_dev->set_promisc		= memac_set_promiscuous;
+ 	mac_dev->change_addr		= memac_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= memac_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= memac_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= memac_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= memac_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= memac_set_exception;
+ 	mac_dev->set_allmulti		= memac_set_allmulti;
+ 	mac_dev->set_tstamp		= memac_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = adjust_link_memac;
+ 	mac_dev->enable			= memac_enable;
+ 	mac_dev->disable		= memac_disable;
+ 
+-	if (params->max_speed == SPEED_10000)
+-		mac_dev->phy_if = PHY_INTERFACE_MODE_XGMII;
+-
+ 	mac_dev->fman_mac = memac_config(mac_dev, params);
+-	if (!mac_dev->fman_mac) {
+-		err = -EINVAL;
+-		goto _return;
+-	}
++	if (!mac_dev->fman_mac)
++		return -EINVAL;
+ 
+ 	memac = mac_dev->fman_mac;
+ 	memac->memac_drv_param->max_frame_length = fman_get_max_frm();
+@@ -1136,9 +1137,9 @@ int memac_initialization(struct mac_devi
+ 	else
+ 		pcs = memac_pcs_create(mac_node, err);
+ 
+-	if (!pcs) {
+-		dev_err(mac_dev->dev, "missing pcs\n");
+-		err = -ENOENT;
++	if (IS_ERR(pcs)) {
++		err = PTR_ERR(pcs);
++		dev_err_probe(mac_dev->dev, err, "missing pcs\n");
+ 		goto _return_fm_mac_free;
+ 	}
+ 
+@@ -1159,84 +1160,100 @@ int memac_initialization(struct mac_devi
+ 	} else if (IS_ERR(memac->serdes)) {
+ 		dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
+ 		goto _return_fm_mac_free;
+-	} else {
+-		err = phy_init(memac->serdes);
+-		if (err) {
+-			dev_err_probe(mac_dev->dev, err,
+-				      "could not initialize serdes\n");
+-			goto _return_fm_mac_free;
+-		}
+-
+-		err = phy_power_on(memac->serdes);
+-		if (err) {
+-			dev_err_probe(mac_dev->dev, err,
+-				      "could not power on serdes\n");
+-			goto _return_phy_exit;
+-		}
+-
+-		if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
+-			err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
+-					       memac->phy_if);
+-			if (err) {
+-				dev_err_probe(mac_dev->dev, err,
+-					      "could not set serdes mode to %s\n",
+-					      phy_modes(memac->phy_if));
+-				goto _return_phy_power_off;
+-			}
+-		}
+ 	}
+ 
+-	if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
+-		struct phy_device *phy;
+-
+-		err = of_phy_register_fixed_link(mac_node);
+-		if (err)
+-			goto _return_phy_power_off;
+-
+-		fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
+-		if (!fixed_link) {
+-			err = -ENOMEM;
+-			goto _return_phy_power_off;
+-		}
++	/* The internal connection to the serdes is XGMII, but this isn't
++	 * really correct for the phy mode (which is the external connection).
++	 * However, this is how all older device trees say that they want
++	 * 10GBASE-R (aka XFI), so just convert it for them.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
+ 
+-		mac_dev->phy_node = of_node_get(mac_node);
+-		phy = of_phy_find_device(mac_dev->phy_node);
+-		if (!phy) {
+-			err = -EINVAL;
+-			of_node_put(mac_dev->phy_node);
+-			goto _return_fixed_link_free;
+-		}
++	/* TODO: The following interface modes are supported by (some) hardware
++	 * but not by this driver:
++	 * - 1000BASE-KX
++	 * - 10GBASE-KR
++	 * - XAUI/HiGig
++	 */
++	supported = mac_dev->phylink_config.supported_interfaces;
+ 
+-		fixed_link->link = phy->link;
+-		fixed_link->speed = phy->speed;
+-		fixed_link->duplex = phy->duplex;
+-		fixed_link->pause = phy->pause;
+-		fixed_link->asym_pause = phy->asym_pause;
++	/* Note that half duplex is only supported on 10/100M interfaces. */
+ 
+-		put_device(&phy->mdio.dev);
+-		memac->memac_drv_param->fixed_link = fixed_link;
++	if (memac->sgmii_pcs &&
++	    (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
++	     memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
++		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
++		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
++	}
++
++	if (memac->sgmii_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
++		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
++
++	if (memac->qsgmii_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
++		__set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
++	else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
++		dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
++
++	if (memac->xfi_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
++		__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
++	} else {
++		/* From what I can tell, no 10g macs support RGMII. */
++		phy_interface_set_rgmii(supported);
++		__set_bit(PHY_INTERFACE_MODE_MII, supported);
+ 	}
+ 
++	capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
++	capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
++
++	/* These SoCs don't support half duplex at all; there's no different
++	 * FMan version or compatible, so we just have to check the machine
++	 * compatible instead
++	 */
++	if (of_machine_is_compatible("fsl,ls1043a") ||
++	    of_machine_is_compatible("fsl,ls1046a") ||
++	    of_machine_is_compatible("fsl,B4QDS"))
++		capabilities &= ~(MAC_10HD | MAC_100HD);
++
++	mac_dev->phylink_config.mac_capabilities = capabilities;
++
++	/* The T2080 and T4240 don't support half duplex RGMII. There is no
++	 * other way to identify these SoCs, so just use the machine
++	 * compatible.
++	 */
++	if (of_machine_is_compatible("fsl,T2080QDS") ||
++	    of_machine_is_compatible("fsl,T2080RDB") ||
++	    of_machine_is_compatible("fsl,T2081QDS") ||
++	    of_machine_is_compatible("fsl,T4240QDS") ||
++	    of_machine_is_compatible("fsl,T4240RDB"))
++		memac->rgmii_no_half_duplex = true;
++
++	/* Most boards should use MLO_AN_INBAND, but existing boards don't have
++	 * a managed property. Default to MLO_AN_INBAND if nothing else is
++	 * specified. We need to be careful and not enable this if we have a
++	 * fixed link or if we are using MII or RGMII, since those
++	 * configurations modes don't use in-band autonegotiation.
++	 */
++	fixed = of_get_child_by_name(mac_node, "fixed-link");
++	if (!fixed && !of_property_read_bool(mac_node, "fixed-link") &&
++	    !of_property_read_bool(mac_node, "managed") &&
++	    mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
++	    !phy_interface_mode_is_rgmii(mac_dev->phy_if))
++		mac_dev->phylink_config.ovr_an_inband = true;
++	of_node_put(fixed);
++
+ 	err = memac_init(mac_dev->fman_mac);
+ 	if (err < 0)
+-		goto _return_fixed_link_free;
++		goto _return_fm_mac_free;
+ 
+ 	dev_info(mac_dev->dev, "FMan MEMAC\n");
+ 
+-	goto _return;
++	return 0;
+ 
+-_return_phy_power_off:
+-	phy_power_off(memac->serdes);
+-_return_phy_exit:
+-	phy_exit(memac->serdes);
+-_return_fixed_link_free:
+-	kfree(fixed_link);
+ _return_fm_mac_free:
+ 	memac_free(mac_dev->fman_mac);
+-_return:
+ 	return err;
+ }
+--- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
+@@ -13,6 +13,7 @@
+ #include <linux/bitrev.h>
+ #include <linux/io.h>
+ #include <linux/crc32.h>
++#include <linux/netdevice.h>
+ 
+ /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
+ #define TGEC_TX_IPG_LENGTH_MASK	0x000003ff
+@@ -243,10 +244,6 @@ static int init(struct tgec_regs __iomem
+ 
+ static int check_init_parameters(struct fman_mac *tgec)
+ {
+-	if (tgec->max_speed < SPEED_10000) {
+-		pr_err("10G MAC driver only support 10G speed\n");
+-		return -EINVAL;
+-	}
+ 	if (!tgec->exception_cb) {
+ 		pr_err("uninitialized exception_cb\n");
+ 		return -EINVAL;
+@@ -384,40 +381,13 @@ static void free_init_resources(struct f
+ 	tgec->unicast_addr_hash = NULL;
+ }
+ 
+-static bool is_init_done(struct tgec_cfg *cfg)
+-{
+-	/* Checks if tGEC driver parameters were initialized */
+-	if (!cfg)
+-		return true;
+-
+-	return false;
+-}
+-
+ static int tgec_enable(struct fman_mac *tgec)
+ {
+-	struct tgec_regs __iomem *regs = tgec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
+-	iowrite32be(tmp, &regs->command_config);
+-
+ 	return 0;
+ }
+ 
+ static void tgec_disable(struct fman_mac *tgec)
+ {
+-	struct tgec_regs __iomem *regs = tgec->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(tgec->cfg));
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
+-	iowrite32be(tmp, &regs->command_config);
+ }
+ 
+ static int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val)
+@@ -425,9 +395,6 @@ static int tgec_set_promiscuous(struct f
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (new_val)
+ 		tmp |= CMD_CFG_PROMIS_EN;
+@@ -444,9 +411,6 @@ static int tgec_set_tx_pause_frames(stru
+ {
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	iowrite32be((u32)pause_time, &regs->pause_quant);
+ 
+ 	return 0;
+@@ -457,9 +421,6 @@ static int tgec_accept_rx_pause_frames(s
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (!en)
+ 		tmp |= CMD_CFG_PAUSE_IGNORE;
+@@ -470,12 +431,53 @@ static int tgec_accept_rx_pause_frames(s
+ 	return 0;
+ }
+ 
++static void tgec_mac_config(struct phylink_config *config, unsigned int mode,
++			    const struct phylink_link_state *state)
++{
++}
++
++static void tgec_link_up(struct phylink_config *config, struct phy_device *phy,
++			 unsigned int mode, phy_interface_t interface,
++			 int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *tgec = mac_dev->fman_mac;
++	struct tgec_regs __iomem *regs = tgec->regs;
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++	u32 tmp;
++
++	tgec_set_tx_pause_frames(tgec, 0, pause_time, 0);
++	tgec_accept_rx_pause_frames(tgec, rx_pause);
++	mac_dev->update_speed(mac_dev, speed);
++
++	tmp = ioread32be(&regs->command_config);
++	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static void tgec_link_down(struct phylink_config *config, unsigned int mode,
++			   phy_interface_t interface)
++{
++	struct fman_mac *tgec = fman_config_to_mac(config)->fman_mac;
++	struct tgec_regs __iomem *regs = tgec->regs;
++	u32 tmp;
++
++	tmp = ioread32be(&regs->command_config);
++	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static const struct phylink_mac_ops tgec_mac_ops = {
++	.validate = phylink_generic_validate,
++	.mac_config = tgec_mac_config,
++	.mac_link_up = tgec_link_up,
++	.mac_link_down = tgec_link_down,
++};
++
+ static int tgec_modify_mac_address(struct fman_mac *tgec,
+ 				   const enet_addr_t *p_enet_addr)
+ {
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr);
+ 	set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr));
+ 
+@@ -490,9 +492,6 @@ static int tgec_add_hash_mac_address(str
+ 	u32 crc = 0xFFFFFFFF, hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	if (!(addr & GROUP_ADDRESS)) {
+@@ -525,9 +524,6 @@ static int tgec_set_allmulti(struct fman
+ 	u32 entry;
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	if (enable) {
+ 		for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
+ 			iowrite32be(entry | TGEC_HASH_MCAST_EN,
+@@ -548,9 +544,6 @@ static int tgec_set_tstamp(struct fman_m
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 
+ 	if (enable)
+@@ -572,9 +565,6 @@ static int tgec_del_hash_mac_address(str
+ 	u32 crc = 0xFFFFFFFF, hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	addr = ((*(u64 *)eth_addr) >> 16);
+ 
+ 	/* CRC calculation */
+@@ -601,22 +591,12 @@ static int tgec_del_hash_mac_address(str
+ 	return 0;
+ }
+ 
+-static void tgec_adjust_link(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-}
+-
+ static int tgec_set_exception(struct fman_mac *tgec,
+ 			      enum fman_mac_exceptions exception, bool enable)
+ {
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	bit_mask = get_exception_flag(exception);
+ 	if (bit_mask) {
+ 		if (enable)
+@@ -641,9 +621,6 @@ static int tgec_init(struct fman_mac *tg
+ 	enet_addr_t eth_addr;
+ 	int err;
+ 
+-	if (is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	if (DEFAULT_RESET_ON_INIT &&
+ 	    (fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) {
+ 		pr_err("Can't reset MAC!\n");
+@@ -753,7 +730,6 @@ static struct fman_mac *tgec_config(stru
+ 
+ 	tgec->regs = mac_dev->vaddr;
+ 	tgec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+-	tgec->max_speed = params->max_speed;
+ 	tgec->mac_id = params->mac_id;
+ 	tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT	|
+ 			    TGEC_IMASK_REM_FAULT	|
+@@ -788,17 +764,15 @@ int tgec_initialization(struct mac_devic
+ 	int err;
+ 	struct fman_mac		*tgec;
+ 
++	mac_dev->phylink_ops		= &tgec_mac_ops;
+ 	mac_dev->set_promisc		= tgec_set_promiscuous;
+ 	mac_dev->change_addr		= tgec_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= tgec_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= tgec_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= tgec_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= tgec_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= tgec_set_exception;
+ 	mac_dev->set_allmulti		= tgec_set_allmulti;
+ 	mac_dev->set_tstamp		= tgec_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = tgec_adjust_link;
+ 	mac_dev->enable			= tgec_enable;
+ 	mac_dev->disable		= tgec_disable;
+ 
+@@ -808,6 +782,19 @@ int tgec_initialization(struct mac_devic
+ 		goto _return;
+ 	}
+ 
++	/* The internal connection to the serdes is XGMII, but this isn't
++	 * really correct for the phy mode (which is the external connection).
++	 * However, this is how all older device trees say that they want
++	 * XAUI, so just convert it for them.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		mac_dev->phy_if = PHY_INTERFACE_MODE_XAUI;
++
++	__set_bit(PHY_INTERFACE_MODE_XAUI,
++		  mac_dev->phylink_config.supported_interfaces);
++	mac_dev->phylink_config.mac_capabilities =
++		MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10000FD;
++
+ 	tgec = mac_dev->fman_mac;
+ 	tgec->cfg->max_frame_length = fman_get_max_frm();
+ 	err = tgec_init(tgec);
+--- a/drivers/net/ethernet/freescale/fman/mac.c
++++ b/drivers/net/ethernet/freescale/fman/mac.c
+@@ -15,6 +15,7 @@
+ #include <linux/phy.h>
+ #include <linux/netdevice.h>
+ #include <linux/phy_fixed.h>
++#include <linux/phylink.h>
+ #include <linux/etherdevice.h>
+ #include <linux/libfdt_env.h>
+ 
+@@ -93,130 +94,8 @@ int fman_set_multi(struct net_device *ne
+ 	return 0;
+ }
+ 
+-/**
+- * fman_set_mac_active_pause
+- * @mac_dev:	A pointer to the MAC device
+- * @rx:		Pause frame setting for RX
+- * @tx:		Pause frame setting for TX
+- *
+- * Set the MAC RX/TX PAUSE frames settings
+- *
+- * Avoid redundant calls to FMD, if the MAC driver already contains the desired
+- * active PAUSE settings. Otherwise, the new active settings should be reflected
+- * in FMan.
+- *
+- * Return: 0 on success; Error code otherwise.
+- */
+-int fman_set_mac_active_pause(struct mac_device *mac_dev, bool rx, bool tx)
+-{
+-	struct fman_mac *fman_mac = mac_dev->fman_mac;
+-	int err = 0;
+-
+-	if (rx != mac_dev->rx_pause_active) {
+-		err = mac_dev->set_rx_pause(fman_mac, rx);
+-		if (likely(err == 0))
+-			mac_dev->rx_pause_active = rx;
+-	}
+-
+-	if (tx != mac_dev->tx_pause_active) {
+-		u16 pause_time = (tx ? FSL_FM_PAUSE_TIME_ENABLE :
+-					 FSL_FM_PAUSE_TIME_DISABLE);
+-
+-		err = mac_dev->set_tx_pause(fman_mac, 0, pause_time, 0);
+-
+-		if (likely(err == 0))
+-			mac_dev->tx_pause_active = tx;
+-	}
+-
+-	return err;
+-}
+-EXPORT_SYMBOL(fman_set_mac_active_pause);
+-
+-/**
+- * fman_get_pause_cfg
+- * @mac_dev:	A pointer to the MAC device
+- * @rx_pause:	Return value for RX setting
+- * @tx_pause:	Return value for TX setting
+- *
+- * Determine the MAC RX/TX PAUSE frames settings based on PHY
+- * autonegotiation or values set by eththool.
+- *
+- * Return: Pointer to FMan device.
+- */
+-void fman_get_pause_cfg(struct mac_device *mac_dev, bool *rx_pause,
+-			bool *tx_pause)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	u16 lcl_adv, rmt_adv;
+-	u8 flowctrl;
+-
+-	*rx_pause = *tx_pause = false;
+-
+-	if (!phy_dev->duplex)
+-		return;
+-
+-	/* If PAUSE autonegotiation is disabled, the TX/RX PAUSE settings
+-	 * are those set by ethtool.
+-	 */
+-	if (!mac_dev->autoneg_pause) {
+-		*rx_pause = mac_dev->rx_pause_req;
+-		*tx_pause = mac_dev->tx_pause_req;
+-		return;
+-	}
+-
+-	/* Else if PAUSE autonegotiation is enabled, the TX/RX PAUSE
+-	 * settings depend on the result of the link negotiation.
+-	 */
+-
+-	/* get local capabilities */
+-	lcl_adv = linkmode_adv_to_lcl_adv_t(phy_dev->advertising);
+-
+-	/* get link partner capabilities */
+-	rmt_adv = 0;
+-	if (phy_dev->pause)
+-		rmt_adv |= LPA_PAUSE_CAP;
+-	if (phy_dev->asym_pause)
+-		rmt_adv |= LPA_PAUSE_ASYM;
+-
+-	/* Calculate TX/RX settings based on local and peer advertised
+-	 * symmetric/asymmetric PAUSE capabilities.
+-	 */
+-	flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+-	if (flowctrl & FLOW_CTRL_RX)
+-		*rx_pause = true;
+-	if (flowctrl & FLOW_CTRL_TX)
+-		*tx_pause = true;
+-}
+-EXPORT_SYMBOL(fman_get_pause_cfg);
+-
+-#define DTSEC_SUPPORTED \
+-	(SUPPORTED_10baseT_Half \
+-	| SUPPORTED_10baseT_Full \
+-	| SUPPORTED_100baseT_Half \
+-	| SUPPORTED_100baseT_Full \
+-	| SUPPORTED_Autoneg \
+-	| SUPPORTED_Pause \
+-	| SUPPORTED_Asym_Pause \
+-	| SUPPORTED_FIBRE \
+-	| SUPPORTED_MII)
+-
+ static DEFINE_MUTEX(eth_lock);
+ 
+-static const u16 phy2speed[] = {
+-	[PHY_INTERFACE_MODE_MII]		= SPEED_100,
+-	[PHY_INTERFACE_MODE_GMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_SGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_TBI]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RMII]		= SPEED_100,
+-	[PHY_INTERFACE_MODE_RGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_ID]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_RXID]	= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_TXID]	= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RTBI]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_QSGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_XGMII]		= SPEED_10000
+-};
+-
+ static struct platform_device *dpaa_eth_add_device(int fman_id,
+ 						   struct mac_device *mac_dev)
+ {
+@@ -263,8 +142,8 @@ no_mem:
+ }
+ 
+ static const struct of_device_id mac_match[] = {
+-	{ .compatible	= "fsl,fman-dtsec", .data = dtsec_initialization },
+-	{ .compatible	= "fsl,fman-xgec", .data = tgec_initialization },
++	{ .compatible   = "fsl,fman-dtsec", .data = dtsec_initialization },
++	{ .compatible   = "fsl,fman-xgec", .data = tgec_initialization },
+ 	{ .compatible	= "fsl,fman-memac", .data = memac_initialization },
+ 	{}
+ };
+@@ -295,6 +174,7 @@ static int mac_probe(struct platform_dev
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
++	platform_set_drvdata(_of_dev, mac_dev);
+ 
+ 	/* Save private information */
+ 	mac_dev->priv = priv;
+@@ -424,57 +304,21 @@ static int mac_probe(struct platform_dev
+ 	}
+ 	mac_dev->phy_if = phy_if;
+ 
+-	priv->speed		= phy2speed[mac_dev->phy_if];
+-	params.max_speed	= priv->speed;
+-	mac_dev->if_support	= DTSEC_SUPPORTED;
+-	/* We don't support half-duplex in SGMII mode */
+-	if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII)
+-		mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
+-					SUPPORTED_100baseT_Half);
+-
+-	/* Gigabit support (no half-duplex) */
+-	if (params.max_speed == 1000)
+-		mac_dev->if_support |= SUPPORTED_1000baseT_Full;
+-
+-	/* The 10G interface only supports one mode */
+-	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
+-		mac_dev->if_support = SUPPORTED_10000baseT_Full;
+-
+-	/* Get the rest of the PHY information */
+-	mac_dev->phy_node = of_parse_phandle(mac_node, "phy-handle", 0);
+-
+-	params.basex_if		= false;
+ 	params.mac_id		= priv->cell_index;
+ 	params.fm		= (void *)priv->fman;
+ 	params.exception_cb	= mac_exception;
+ 	params.event_cb		= mac_exception;
+ 
+ 	err = init(mac_dev, mac_node, &params);
+-	if (err < 0) {
+-		dev_err(dev, "mac_dev->init() = %d\n", err);
+-		of_node_put(mac_dev->phy_node);
+-		return err;
+-	}
+-
+-	/* pause frame autonegotiation enabled */
+-	mac_dev->autoneg_pause = true;
+-
+-	/* By intializing the values to false, force FMD to enable PAUSE frames
+-	 * on RX and TX
+-	 */
+-	mac_dev->rx_pause_req = true;
+-	mac_dev->tx_pause_req = true;
+-	mac_dev->rx_pause_active = false;
+-	mac_dev->tx_pause_active = false;
+-	err = fman_set_mac_active_pause(mac_dev, true, true);
+ 	if (err < 0)
+-		dev_err(dev, "fman_set_mac_active_pause() = %d\n", err);
++		return err;
+ 
+ 	if (!is_zero_ether_addr(mac_dev->addr))
+ 		dev_info(dev, "FMan MAC address: %pM\n", mac_dev->addr);
+ 
+ 	priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);
+ 	if (IS_ERR(priv->eth_dev)) {
++		err = PTR_ERR(priv->eth_dev);
+ 		dev_err(dev, "failed to add Ethernet platform device for MAC %d\n",
+ 			priv->cell_index);
+ 		priv->eth_dev = NULL;
+--- a/drivers/net/ethernet/freescale/fman/mac.h
++++ b/drivers/net/ethernet/freescale/fman/mac.h
+@@ -9,6 +9,7 @@
+ #include <linux/device.h>
+ #include <linux/if_ether.h>
+ #include <linux/phy.h>
++#include <linux/phylink.h>
+ #include <linux/list.h>
+ 
+ #include "fman_port.h"
+@@ -24,32 +25,22 @@ struct mac_device {
+ 	struct resource		*res;
+ 	u8			 addr[ETH_ALEN];
+ 	struct fman_port	*port[2];
+-	u32			 if_support;
+-	struct phy_device	*phy_dev;
++	struct phylink		*phylink;
++	struct phylink_config	phylink_config;
+ 	phy_interface_t		phy_if;
+-	struct device_node	*phy_node;
+-	struct net_device	*net_dev;
+ 
+-	bool autoneg_pause;
+-	bool rx_pause_req;
+-	bool tx_pause_req;
+-	bool rx_pause_active;
+-	bool tx_pause_active;
+ 	bool promisc;
+ 	bool allmulti;
+ 
++	const struct phylink_mac_ops *phylink_ops;
+ 	int (*enable)(struct fman_mac *mac_dev);
+ 	void (*disable)(struct fman_mac *mac_dev);
+-	void (*adjust_link)(struct mac_device *mac_dev);
+ 	int (*set_promisc)(struct fman_mac *mac_dev, bool enable);
+ 	int (*change_addr)(struct fman_mac *mac_dev, const enet_addr_t *enet_addr);
+ 	int (*set_allmulti)(struct fman_mac *mac_dev, bool enable);
+ 	int (*set_tstamp)(struct fman_mac *mac_dev, bool enable);
+ 	int (*set_multi)(struct net_device *net_dev,
+ 			 struct mac_device *mac_dev);
+-	int (*set_rx_pause)(struct fman_mac *mac_dev, bool en);
+-	int (*set_tx_pause)(struct fman_mac *mac_dev, u8 priority,
+-			    u16 pause_time, u16 thresh_time);
+ 	int (*set_exception)(struct fman_mac *mac_dev,
+ 			     enum fman_mac_exceptions exception, bool enable);
+ 	int (*add_hash_mac_addr)(struct fman_mac *mac_dev,
+@@ -63,6 +54,12 @@ struct mac_device {
+ 	struct mac_priv_s	*priv;
+ };
+ 
++static inline struct mac_device
++*fman_config_to_mac(struct phylink_config *config)
++{
++	return container_of(config, struct mac_device, phylink_config);
++}
++
+ struct dpaa_eth_data {
+ 	struct mac_device *mac_dev;
+ 	int mac_hw_id;
diff --git a/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch b/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch
new file mode 100644
index 0000000000..06c348b1cd
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch
@@ -0,0 +1,93 @@
+From bf4de031052fe7c5309e8956c342d4e5ce79038e Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Mon, 17 Oct 2022 16:22:35 -0400
+Subject: [PATCH 04/21] net: phylink: provide phylink_validate_mask_caps()
+ helper
+
+Provide a helper that restricts the link modes according to the
+phylink capabilities.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+[rebased on net-next/master and added documentation]
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 41 +++++++++++++++++++++++++++------------
+ include/linux/phylink.h   |  3 +++
+ 2 files changed, 32 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -564,31 +564,48 @@ unsigned long phylink_get_capabilities(p
+ EXPORT_SYMBOL_GPL(phylink_get_capabilities);
+ 
+ /**
+- * phylink_generic_validate() - generic validate() callback implementation
+- * @config: a pointer to a &struct phylink_config.
++ * phylink_validate_mask_caps() - Restrict link modes based on caps
+  * @supported: ethtool bitmask for supported link modes.
+- * @state: a pointer to a &struct phylink_link_state.
++ * @state: an (optional) pointer to a &struct phylink_link_state.
++ * @mac_capabilities: bitmask of MAC capabilities
+  *
+- * Generic implementation of the validate() callback that MAC drivers can
+- * use when they pass the range of supported interfaces and MAC capabilities.
+- * This makes use of phylink_get_linkmodes().
++ * Calculate the supported link modes based on @mac_capabilities, and restrict
++ * @supported and @state based on that. Use this function if your capabiliies
++ * aren't constant, such as if they vary depending on the interface.
+  */
+-void phylink_generic_validate(struct phylink_config *config,
+-			      unsigned long *supported,
+-			      struct phylink_link_state *state)
++void phylink_validate_mask_caps(unsigned long *supported,
++				struct phylink_link_state *state,
++				unsigned long mac_capabilities)
+ {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+ 	unsigned long caps;
+ 
+ 	phylink_set_port_modes(mask);
+ 	phylink_set(mask, Autoneg);
+-	caps = phylink_get_capabilities(state->interface,
+-					config->mac_capabilities,
++	caps = phylink_get_capabilities(state->interface, mac_capabilities,
+ 					state->rate_matching);
+ 	phylink_caps_to_linkmodes(mask, caps);
+ 
+ 	linkmode_and(supported, supported, mask);
+-	linkmode_and(state->advertising, state->advertising, mask);
++	if (state)
++		linkmode_and(state->advertising, state->advertising, mask);
++}
++EXPORT_SYMBOL_GPL(phylink_validate_mask_caps);
++
++/**
++ * phylink_generic_validate() - generic validate() callback implementation
++ * @config: a pointer to a &struct phylink_config.
++ * @supported: ethtool bitmask for supported link modes.
++ * @state: a pointer to a &struct phylink_link_state.
++ *
++ * Generic implementation of the validate() callback that MAC drivers can
++ * use when they pass the range of supported interfaces and MAC capabilities.
++ */
++void phylink_generic_validate(struct phylink_config *config,
++			      unsigned long *supported,
++			      struct phylink_link_state *state)
++{
++	phylink_validate_mask_caps(supported, state, config->mac_capabilities);
+ }
+ EXPORT_SYMBOL_GPL(phylink_generic_validate);
+ 
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -558,6 +558,9 @@ void phylink_caps_to_linkmodes(unsigned
+ unsigned long phylink_get_capabilities(phy_interface_t interface,
+ 				       unsigned long mac_capabilities,
+ 				       int rate_matching);
++void phylink_validate_mask_caps(unsigned long *supported,
++				struct phylink_link_state *state,
++				unsigned long caps);
+ void phylink_generic_validate(struct phylink_config *config,
+ 			      unsigned long *supported,
+ 			      struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch b/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch
new file mode 100644
index 0000000000..e3a1dda688
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch
@@ -0,0 +1,39 @@
+From 2bf7e4a68c42eed909f3c29582e1fb85cb157e35 Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Tue, 25 Oct 2022 11:51:26 -0700
+Subject: [PATCH 05/21] phylink: require valid state argument to
+ phylink_validate_mask_caps()
+
+state is deferenced earlier in the function, the NULL check
+is pointless. Since we don't have any crash reports presumably
+it's safe to assume state is not NULL.
+
+Fixes: f392a1846489 ("net: phylink: provide phylink_validate_mask_caps() helper")
+Reviewed-by: Sean Anderson <sean.anderson@seco.com>
+Link: https://lore.kernel.org/r/20221025185126.1720553-1-kuba@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -566,7 +566,7 @@ EXPORT_SYMBOL_GPL(phylink_get_capabiliti
+ /**
+  * phylink_validate_mask_caps() - Restrict link modes based on caps
+  * @supported: ethtool bitmask for supported link modes.
+- * @state: an (optional) pointer to a &struct phylink_link_state.
++ * @state: pointer to a &struct phylink_link_state.
+  * @mac_capabilities: bitmask of MAC capabilities
+  *
+  * Calculate the supported link modes based on @mac_capabilities, and restrict
+@@ -587,8 +587,7 @@ void phylink_validate_mask_caps(unsigned
+ 	phylink_caps_to_linkmodes(mask, caps);
+ 
+ 	linkmode_and(supported, supported, mask);
+-	if (state)
+-		linkmode_and(state->advertising, state->advertising, mask);
++	linkmode_and(state->advertising, state->advertising, mask);
+ }
+ EXPORT_SYMBOL_GPL(phylink_validate_mask_caps);
+ 
diff --git a/target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch b/target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
similarity index 87%
rename from target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
rename to target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
index 81c14a0557..c217ed87b5 100644
--- a/target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
+++ b/target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
@@ -1,7 +1,7 @@
-From 9c5a170677c3c8facc83e931a57f4c99c0511ae0 Mon Sep 17 00:00:00 2001
+From f8fc363bf0c023e4736a0328174b4a24b44ab23a Mon Sep 17 00:00:00 2001
 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
 Date: Thu, 27 Oct 2022 14:10:37 +0100
-Subject: [PATCH] net: phylink: add phylink_get_link_timer_ns() helper
+Subject: [PATCH 06/21] net: phylink: add phylink_get_link_timer_ns() helper
 
 Add a helper to convert the PHY interface mode to the required link
 timer setting as stated by the appropriate standard. Inappropriate
@@ -15,7 +15,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/include/linux/phylink.h
 +++ b/include/linux/phylink.h
-@@ -614,6 +614,30 @@ int phylink_speed_up(struct phylink *pl)
+@@ -617,6 +617,30 @@ int phylink_speed_up(struct phylink *pl)
  
  void phylink_set_port_modes(unsigned long *bits);
  
diff --git a/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch
new file mode 100644
index 0000000000..28154af920
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch
@@ -0,0 +1,250 @@
+From b45b773a96b0e9e8d51e5d005485f4e376d6ce9a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 4 Nov 2022 17:13:01 +0000
+Subject: [PATCH 07/21] net: remove explicit phylink_generic_validate()
+ references
+
+Virtually all conventional network drivers are now converted to use
+phylink_generic_validate() - only DSA drivers and fman_memac remain,
+so lets remove the necessity for network drivers to explicitly set
+this member, and default to phylink_generic_validate() when unset.
+This is possible as .validate must currently be set.
+
+Any remaining instances that have not been addressed by this patch can
+be fixed up later.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Link: https://lore.kernel.org/r/E1or0FZ-001tRa-DI@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/altera/altera_tse_main.c            | 1 -
+ drivers/net/ethernet/atheros/ag71xx.c                    | 1 -
+ drivers/net/ethernet/cadence/macb_main.c                 | 1 -
+ drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c         | 1 -
+ drivers/net/ethernet/freescale/enetc/enetc_pf.c          | 1 -
+ drivers/net/ethernet/freescale/fman/fman_dtsec.c         | 1 -
+ drivers/net/ethernet/freescale/fman/fman_tgec.c          | 1 -
+ drivers/net/ethernet/marvell/mvneta.c                    | 1 -
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c          | 1 -
+ drivers/net/ethernet/marvell/prestera/prestera_main.c    | 1 -
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c              | 1 -
+ drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c | 1 -
+ drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c   | 1 -
+ drivers/net/ethernet/mscc/ocelot_net.c                   | 1 -
+ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c        | 1 -
+ drivers/net/ethernet/ti/am65-cpsw-nuss.c                 | 1 -
+ drivers/net/ethernet/xilinx/xilinx_axienet_main.c        | 1 -
+ drivers/net/phy/phylink.c                                | 5 ++++-
+ drivers/net/usb/asix_devices.c                           | 1 -
+ include/linux/phylink.h                                  | 5 +++++
+ 20 files changed, 9 insertions(+), 19 deletions(-)
+
+--- a/drivers/net/ethernet/altera/altera_tse_main.c
++++ b/drivers/net/ethernet/altera/altera_tse_main.c
+@@ -1096,7 +1096,6 @@ static struct phylink_pcs *alt_tse_selec
+ }
+ 
+ static const struct phylink_mac_ops alt_tse_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_an_restart = alt_tse_mac_an_restart,
+ 	.mac_config = alt_tse_mac_config,
+ 	.mac_link_down = alt_tse_mac_link_down,
+--- a/drivers/net/ethernet/atheros/ag71xx.c
++++ b/drivers/net/ethernet/atheros/ag71xx.c
+@@ -1086,7 +1086,6 @@ static void ag71xx_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops ag71xx_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = ag71xx_mac_config,
+ 	.mac_link_down = ag71xx_mac_link_down,
+ 	.mac_link_up = ag71xx_mac_link_up,
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -752,7 +752,6 @@ static struct phylink_pcs *macb_mac_sele
+ }
+ 
+ static const struct phylink_mac_ops macb_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = macb_mac_select_pcs,
+ 	.mac_config = macb_mac_config,
+ 	.mac_link_down = macb_mac_link_down,
+--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+@@ -235,7 +235,6 @@ static void dpaa2_mac_link_down(struct p
+ }
+ 
+ static const struct phylink_mac_ops dpaa2_mac_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = dpaa2_mac_select_pcs,
+ 	.mac_config = dpaa2_mac_config,
+ 	.mac_link_up = dpaa2_mac_link_up,
+--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
+@@ -1111,7 +1111,6 @@ static void enetc_pl_mac_link_down(struc
+ }
+ 
+ static const struct phylink_mac_ops enetc_mac_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = enetc_pl_mac_select_pcs,
+ 	.mac_config = enetc_pl_mac_config,
+ 	.mac_link_up = enetc_pl_mac_link_up,
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -986,7 +986,6 @@ static void dtsec_link_down(struct phyli
+ }
+ 
+ static const struct phylink_mac_ops dtsec_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = dtsec_select_pcs,
+ 	.mac_config = dtsec_mac_config,
+ 	.mac_link_up = dtsec_link_up,
+--- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
+@@ -469,7 +469,6 @@ static void tgec_link_down(struct phylin
+ }
+ 
+ static const struct phylink_mac_ops tgec_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = tgec_mac_config,
+ 	.mac_link_up = tgec_link_up,
+ 	.mac_link_down = tgec_link_down,
+--- a/drivers/net/ethernet/marvell/mvneta.c
++++ b/drivers/net/ethernet/marvell/mvneta.c
+@@ -4228,7 +4228,6 @@ static void mvneta_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops mvneta_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mvneta_mac_select_pcs,
+ 	.mac_prepare = mvneta_mac_prepare,
+ 	.mac_config = mvneta_mac_config,
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -6633,7 +6633,6 @@ static void mvpp2_mac_link_down(struct p
+ }
+ 
+ static const struct phylink_mac_ops mvpp2_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mvpp2_select_pcs,
+ 	.mac_prepare = mvpp2_mac_prepare,
+ 	.mac_config = mvpp2_mac_config,
+--- a/drivers/net/ethernet/marvell/prestera/prestera_main.c
++++ b/drivers/net/ethernet/marvell/prestera/prestera_main.c
+@@ -360,7 +360,6 @@ static void prestera_pcs_an_restart(stru
+ }
+ 
+ static const struct phylink_mac_ops prestera_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = prestera_mac_select_pcs,
+ 	.mac_config = prestera_mac_config,
+ 	.mac_link_down = prestera_mac_link_down,
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -654,7 +654,6 @@ static void mtk_mac_link_up(struct phyli
+ }
+ 
+ static const struct phylink_mac_ops mtk_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mtk_mac_select_pcs,
+ 	.mac_pcs_get_state = mtk_mac_pcs_get_state,
+ 	.mac_config = mtk_mac_config,
+--- a/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c
++++ b/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c
+@@ -125,7 +125,6 @@ static void lan966x_pcs_aneg_restart(str
+ }
+ 
+ const struct phylink_mac_ops lan966x_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = lan966x_phylink_mac_select,
+ 	.mac_config = lan966x_phylink_mac_config,
+ 	.mac_prepare = lan966x_phylink_mac_prepare,
+--- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
+@@ -138,7 +138,6 @@ const struct phylink_pcs_ops sparx5_phyl
+ };
+ 
+ const struct phylink_mac_ops sparx5_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = sparx5_phylink_mac_select_pcs,
+ 	.mac_config = sparx5_phylink_mac_config,
+ 	.mac_link_down = sparx5_phylink_mac_link_down,
+--- a/drivers/net/ethernet/mscc/ocelot_net.c
++++ b/drivers/net/ethernet/mscc/ocelot_net.c
+@@ -1737,7 +1737,6 @@ static void vsc7514_phylink_mac_link_up(
+ }
+ 
+ static const struct phylink_mac_ops ocelot_phylink_ops = {
+-	.validate		= phylink_generic_validate,
+ 	.mac_config		= vsc7514_phylink_mac_config,
+ 	.mac_link_down		= vsc7514_phylink_mac_link_down,
+ 	.mac_link_up		= vsc7514_phylink_mac_link_up,
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -1090,7 +1090,6 @@ static void stmmac_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = stmmac_mac_select_pcs,
+ 	.mac_config = stmmac_mac_config,
+ 	.mac_link_down = stmmac_mac_link_down,
+--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
++++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+@@ -1493,7 +1493,6 @@ static void am65_cpsw_nuss_mac_link_up(s
+ }
+ 
+ static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = am65_cpsw_nuss_mac_config,
+ 	.mac_link_down = am65_cpsw_nuss_mac_link_down,
+ 	.mac_link_up = am65_cpsw_nuss_mac_link_up,
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -1736,7 +1736,6 @@ static void axienet_mac_link_up(struct p
+ }
+ 
+ static const struct phylink_mac_ops axienet_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = axienet_mac_select_pcs,
+ 	.mac_config = axienet_mac_config,
+ 	.mac_link_down = axienet_mac_link_down,
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -651,7 +651,10 @@ static int phylink_validate_mac_and_pcs(
+ 	}
+ 
+ 	/* Then validate the link parameters with the MAC */
+-	pl->mac_ops->validate(pl->config, supported, state);
++	if (pl->mac_ops->validate)
++		pl->mac_ops->validate(pl->config, supported, state);
++	else
++		phylink_generic_validate(pl->config, supported, state);
+ 
+ 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
+ }
+--- a/drivers/net/usb/asix_devices.c
++++ b/drivers/net/usb/asix_devices.c
+@@ -787,7 +787,6 @@ static void ax88772_mac_link_up(struct p
+ }
+ 
+ static const struct phylink_mac_ops ax88772_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = ax88772_mac_config,
+ 	.mac_link_down = ax88772_mac_link_down,
+ 	.mac_link_up = ax88772_mac_link_up,
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -207,6 +207,11 @@ struct phylink_mac_ops {
+  *
+  * If the @state->interface mode is not supported, then the @supported
+  * mask must be cleared.
++ *
++ * This member is optional; if not set, the generic validator will be
++ * used making use of @config->mac_capabilities and
++ * @config->supported_interfaces to determine which link modes are
++ * supported.
+  */
+ void validate(struct phylink_config *config, unsigned long *supported,
+ 	      struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch b/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch
new file mode 100644
index 0000000000..37d82b2cd7
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch
@@ -0,0 +1,48 @@
+From a90ac762d345890b40d88a1385a34a2449c2d75e Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Mar 2023 09:23:42 +0000
+Subject: [PATCH] net: sfp: make sfp_bus_find_fwnode() take a const fwnode
+
+sfp_bus_find_fwnode() does not write to the fwnode, so let's make it
+const.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/sfp-bus.c | 2 +-
+ include/linux/sfp.h       | 5 +++--
+ 2 files changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -603,7 +603,7 @@ static void sfp_upstream_clear(struct sf
+  *	- %-ENOMEM if we failed to allocate the bus.
+  *	- an error from the upstream's connect_phy() method.
+  */
+-struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode)
++struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_reference_args ref;
+ 	struct sfp_bus *bus;
+--- a/include/linux/sfp.h
++++ b/include/linux/sfp.h
+@@ -548,7 +548,7 @@ int sfp_get_module_eeprom_by_page(struct
+ void sfp_upstream_start(struct sfp_bus *bus);
+ void sfp_upstream_stop(struct sfp_bus *bus);
+ void sfp_bus_put(struct sfp_bus *bus);
+-struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode);
++struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode);
+ int sfp_bus_add_upstream(struct sfp_bus *bus, void *upstream,
+ 			 const struct sfp_upstream_ops *ops);
+ void sfp_bus_del_upstream(struct sfp_bus *bus);
+@@ -610,7 +610,8 @@ static inline void sfp_bus_put(struct sf
+ {
+ }
+ 
+-static inline struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode)
++static inline struct sfp_bus *
++sfp_bus_find_fwnode(const struct fwnode_handle *fwnode)
+ {
+ 	return NULL;
+ }
diff --git a/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch b/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch
new file mode 100644
index 0000000000..290cb8d161
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch
@@ -0,0 +1,31 @@
+From ecec0ebbc6381a5a375f1cf10c4858f24e91e2ef Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 15 Mar 2023 14:46:49 +0000
+Subject: [PATCH] net: pcs: lynx: don't print an_enabled in pcs_get_state()
+
+an_enabled will be going away, and in any case, pcs_get_state() should
+not be updating this member. Remove the print.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/pcs/pcs-lynx.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/pcs/pcs-lynx.c
++++ b/drivers/net/pcs/pcs-lynx.c
+@@ -115,11 +115,11 @@ static void lynx_pcs_get_state(struct ph
+ 	}
+ 
+ 	dev_dbg(&lynx->mdio->dev,
+-		"mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n",
++		"mode=%s/%s/%s link=%u an_complete=%u\n",
+ 		phy_modes(state->interface),
+ 		phy_speed_to_str(state->speed),
+ 		phy_duplex_to_str(state->duplex),
+-		state->link, state->an_enabled, state->an_complete);
++		state->link, state->an_complete);
+ }
+ 
+ static int lynx_pcs_config_giga(struct mdio_device *pcs, unsigned int mode,
diff --git a/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch b/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch
new file mode 100644
index 0000000000..38ea265476
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch
@@ -0,0 +1,32 @@
+From 99d0f3a1095f4c938b1665025c29411edafe8a01 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:44 +0000
+Subject: [PATCH] net: dpaa2-mac: use Autoneg bit rather than an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. Thus, we will be removing state->an_enabled.
+
+Use the Autoneg bit in the advertising bitmap to indicate whether
+autonegotiation should be used, rather than using the an_enabled
+member which will be going away. This means we use the same condition
+as phylink_mii_c22_pcs_config().
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+@@ -158,7 +158,8 @@ static void dpaa2_mac_config(struct phyl
+ 	struct dpmac_link_state *dpmac_state = &mac->state;
+ 	int err;
+ 
+-	if (state->an_enabled)
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising))
+ 		dpmac_state->options |= DPMAC_LINK_OPT_AUTONEG;
+ 	else
+ 		dpmac_state->options &= ~DPMAC_LINK_OPT_AUTONEG;
diff --git a/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch b/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch
new file mode 100644
index 0000000000..cb9c411cfb
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch
@@ -0,0 +1,64 @@
+From 471c40bde606ec0b1ce8c616f7998739c7a783a6 Mon Sep 17 00:00:00 2001
+From: Ivan Bornyakov <i.bornyakov@metrotek.ru>
+Date: Fri, 10 Feb 2023 18:46:27 +0300
+Subject: [PATCH 10/21] net: phylink: support validated pause and autoneg in
+ fixed-link
+
+In fixed-link setup phylink_parse_fixedlink() unconditionally sets
+Pause, Asym_Pause and Autoneg bits to "supported" bitmap, while MAC may
+not support these.
+
+This leads to ethtool reporting:
+
+ > Supported pause frame use: Symmetric Receive-only
+ > Supports auto-negotiation: Yes
+
+regardless of what is actually supported.
+
+Instead of unconditionally set Pause, Asym_Pause and Autoneg it is
+sensible to set them according to validated "supported" bitmap, i.e. the
+result of phylink_validate().
+
+Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -709,6 +709,7 @@ static int phylink_parse_fixedlink(struc
+ 				   struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *fixed_node;
++	bool pause, asym_pause, autoneg;
+ 	const struct phy_setting *s;
+ 	struct gpio_desc *desc;
+ 	u32 speed;
+@@ -781,13 +782,23 @@ static int phylink_parse_fixedlink(struc
+ 	linkmode_copy(pl->link_config.advertising, pl->supported);
+ 	phylink_validate(pl, pl->supported, &pl->link_config);
+ 
++	pause = phylink_test(pl->supported, Pause);
++	asym_pause = phylink_test(pl->supported, Asym_Pause);
++	autoneg = phylink_test(pl->supported, Autoneg);
+ 	s = phy_lookup_setting(pl->link_config.speed, pl->link_config.duplex,
+ 			       pl->supported, true);
+ 	linkmode_zero(pl->supported);
+ 	phylink_set(pl->supported, MII);
+-	phylink_set(pl->supported, Pause);
+-	phylink_set(pl->supported, Asym_Pause);
+-	phylink_set(pl->supported, Autoneg);
++
++	if (pause)
++		phylink_set(pl->supported, Pause);
++
++	if (asym_pause)
++		phylink_set(pl->supported, Asym_Pause);
++
++	if (autoneg)
++		phylink_set(pl->supported, Autoneg);
++
+ 	if (s) {
+ 		__set_bit(s->bit, pl->supported);
+ 		__set_bit(s->bit, pl->link_config.lp_advertising);
diff --git a/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch b/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch
new file mode 100644
index 0000000000..03b4f9d0c4
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch
@@ -0,0 +1,177 @@
+From 7211ffd70941933a7825a56cf480f07ee81c321c Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:54 +0000
+Subject: [PATCH 11/21] net: phylink: remove an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. state->an_enabled is now no longer used by any
+drivers, so lets kill this duplication.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 37 +++++++++++++++++--------------------
+ include/linux/phylink.h   |  2 --
+ 2 files changed, 17 insertions(+), 22 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -841,7 +841,6 @@ static int phylink_parse_mode(struct phy
+ 		phylink_set(pl->supported, Autoneg);
+ 		phylink_set(pl->supported, Asym_Pause);
+ 		phylink_set(pl->supported, Pause);
+-		pl->link_config.an_enabled = true;
+ 		pl->cfg_link_an_mode = MLO_AN_INBAND;
+ 
+ 		switch (pl->link_config.interface) {
+@@ -944,9 +943,6 @@ static int phylink_parse_mode(struct phy
+ 				    "failed to validate link configuration for in-band status\n");
+ 			return -EINVAL;
+ 		}
+-
+-		/* Check if MAC/PCS also supports Autoneg. */
+-		pl->link_config.an_enabled = phylink_test(pl->supported, Autoneg);
+ 	}
+ 
+ 	return 0;
+@@ -956,7 +952,8 @@ static void phylink_apply_manual_flow(st
+ 				      struct phylink_link_state *state)
+ {
+ 	/* If autoneg is disabled, pause AN is also disabled */
+-	if (!state->an_enabled)
++	if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			       state->advertising))
+ 		state->pause &= ~MLO_PAUSE_AN;
+ 
+ 	/* Manual configuration of pause modes */
+@@ -996,21 +993,22 @@ static void phylink_mac_config(struct ph
+ 			       const struct phylink_link_state *state)
+ {
+ 	phylink_dbg(pl,
+-		    "%s: mode=%s/%s/%s/%s/%s adv=%*pb pause=%02x link=%u an=%u\n",
++		    "%s: mode=%s/%s/%s/%s/%s adv=%*pb pause=%02x link=%u\n",
+ 		    __func__, phylink_an_mode_str(pl->cur_link_an_mode),
+ 		    phy_modes(state->interface),
+ 		    phy_speed_to_str(state->speed),
+ 		    phy_duplex_to_str(state->duplex),
+ 		    phy_rate_matching_to_str(state->rate_matching),
+ 		    __ETHTOOL_LINK_MODE_MASK_NBITS, state->advertising,
+-		    state->pause, state->link, state->an_enabled);
++		    state->pause, state->link);
+ 
+ 	pl->mac_ops->mac_config(pl->config, pl->cur_link_an_mode, state);
+ }
+ 
+ static void phylink_mac_pcs_an_restart(struct phylink *pl)
+ {
+-	if (pl->link_config.an_enabled &&
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      pl->link_config.advertising) &&
+ 	    phy_interface_mode_is_8023z(pl->link_config.interface) &&
+ 	    phylink_autoneg_inband(pl->cur_link_an_mode)) {
+ 		if (pl->pcs)
+@@ -1137,9 +1135,9 @@ static void phylink_mac_pcs_get_state(st
+ 	linkmode_copy(state->advertising, pl->link_config.advertising);
+ 	linkmode_zero(state->lp_advertising);
+ 	state->interface = pl->link_config.interface;
+-	state->an_enabled = pl->link_config.an_enabled;
+ 	state->rate_matching = pl->link_config.rate_matching;
+-	if (state->an_enabled) {
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising)) {
+ 		state->speed = SPEED_UNKNOWN;
+ 		state->duplex = DUPLEX_UNKNOWN;
+ 		state->pause = MLO_PAUSE_NONE;
+@@ -1531,7 +1529,6 @@ struct phylink *phylink_create(struct ph
+ 	pl->link_config.pause = MLO_PAUSE_AN;
+ 	pl->link_config.speed = SPEED_UNKNOWN;
+ 	pl->link_config.duplex = DUPLEX_UNKNOWN;
+-	pl->link_config.an_enabled = true;
+ 	pl->mac_ops = mac_ops;
+ 	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
+ 	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
+@@ -2155,8 +2152,9 @@ static void phylink_get_ksettings(const
+ 		kset->base.speed = state->speed;
+ 		kset->base.duplex = state->duplex;
+ 	}
+-	kset->base.autoneg = state->an_enabled ? AUTONEG_ENABLE :
+-				AUTONEG_DISABLE;
++	kset->base.autoneg = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					       state->advertising) ?
++				AUTONEG_ENABLE : AUTONEG_DISABLE;
+ }
+ 
+ /**
+@@ -2303,9 +2301,8 @@ int phylink_ethtool_ksettings_set(struct
+ 	/* We have ruled out the case with a PHY attached, and the
+ 	 * fixed-link cases.  All that is left are in-band links.
+ 	 */
+-	config.an_enabled = kset->base.autoneg == AUTONEG_ENABLE;
+ 	linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, config.advertising,
+-			 config.an_enabled);
++			 kset->base.autoneg == AUTONEG_ENABLE);
+ 
+ 	/* If this link is with an SFP, ensure that changes to advertised modes
+ 	 * also cause the associated interface to be selected such that the
+@@ -2339,13 +2336,14 @@ int phylink_ethtool_ksettings_set(struct
+ 	}
+ 
+ 	/* If autonegotiation is enabled, we must have an advertisement */
+-	if (config.an_enabled && phylink_is_empty_linkmode(config.advertising))
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      config.advertising) &&
++	    phylink_is_empty_linkmode(config.advertising))
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&pl->state_mutex);
+ 	pl->link_config.speed = config.speed;
+ 	pl->link_config.duplex = config.duplex;
+-	pl->link_config.an_enabled = config.an_enabled;
+ 
+ 	if (pl->link_config.interface != config.interface) {
+ 		/* The interface changed, e.g. 1000base-X <-> 2500base-X */
+@@ -2951,7 +2949,6 @@ static int phylink_sfp_config_phy(struct
+ 	config.speed = SPEED_UNKNOWN;
+ 	config.duplex = DUPLEX_UNKNOWN;
+ 	config.pause = MLO_PAUSE_AN;
+-	config.an_enabled = pl->link_config.an_enabled;
+ 
+ 	/* Ignore errors if we're expecting a PHY to attach later */
+ 	ret = phylink_validate(pl, support, &config);
+@@ -3020,7 +3017,6 @@ static int phylink_sfp_config_optical(st
+ 	config.speed = SPEED_UNKNOWN;
+ 	config.duplex = DUPLEX_UNKNOWN;
+ 	config.pause = MLO_PAUSE_AN;
+-	config.an_enabled = true;
+ 
+ 	/* For all the interfaces that are supported, reduce the sfp_support
+ 	 * mask to only those link modes that can be supported.
+@@ -3354,7 +3350,8 @@ void phylink_mii_c22_pcs_decode_state(st
+ 	/* If there is no link or autonegotiation is disabled, the LP advertisement
+ 	 * data is not meaningful, so don't go any further.
+ 	 */
+-	if (!state->link || !state->an_enabled)
++	if (!state->link || !linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					       state->advertising))
+ 		return;
+ 
+ 	switch (state->interface) {
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -93,7 +93,6 @@ static inline bool phylink_autoneg_inban
+  *   the medium link mode (@speed and @duplex) and the speed/duplex of the phy
+  *   interface mode (@interface) are different.
+  * @link: true if the link is up.
+- * @an_enabled: true if autonegotiation is enabled/desired.
+  * @an_complete: true if autonegotiation has completed.
+  */
+ struct phylink_link_state {
+@@ -105,7 +104,6 @@ struct phylink_link_state {
+ 	int pause;
+ 	int rate_matching;
+ 	unsigned int link:1;
+-	unsigned int an_enabled:1;
+ 	unsigned int an_complete:1;
+ };
+ 
diff --git a/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch b/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch
new file mode 100644
index 0000000000..c06a367b8b
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch
@@ -0,0 +1,88 @@
+From a3555d1f5c208f0a63eafee77381f68d304a0512 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 May 2023 17:58:37 +0100
+Subject: [PATCH 12/21] net: phylink: constify fwnode arguments
+
+Both phylink_create() and phylink_fwnode_phy_connect() do not modify
+the fwnode argument that they are passed, so lets constify these.
+
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 11 ++++++-----
+ include/linux/phylink.h   |  9 +++++----
+ 2 files changed, 11 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -706,7 +706,7 @@ static int phylink_validate(struct phyli
+ }
+ 
+ static int phylink_parse_fixedlink(struct phylink *pl,
+-				   struct fwnode_handle *fwnode)
++				   const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *fixed_node;
+ 	bool pause, asym_pause, autoneg;
+@@ -817,7 +817,8 @@ static int phylink_parse_fixedlink(struc
+ 	return 0;
+ }
+ 
+-static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
++static int phylink_parse_mode(struct phylink *pl,
++			      const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *dn;
+ 	const char *managed;
+@@ -1440,7 +1441,7 @@ static void phylink_fixed_poll(struct ti
+ static const struct sfp_upstream_ops sfp_phylink_ops;
+ 
+ static int phylink_register_sfp(struct phylink *pl,
+-				struct fwnode_handle *fwnode)
++				const struct fwnode_handle *fwnode)
+ {
+ 	struct sfp_bus *bus;
+ 	int ret;
+@@ -1479,7 +1480,7 @@ static int phylink_register_sfp(struct p
+  * must use IS_ERR() to check for errors from this function.
+  */
+ struct phylink *phylink_create(struct phylink_config *config,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       phy_interface_t iface,
+ 			       const struct phylink_mac_ops *mac_ops)
+ {
+@@ -1809,7 +1810,7 @@ EXPORT_SYMBOL_GPL(phylink_of_phy_connect
+  * Returns 0 on success or a negative errno.
+  */
+ int phylink_fwnode_phy_connect(struct phylink *pl,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       u32 flags)
+ {
+ 	struct fwnode_handle *phy_fwnode;
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -568,16 +568,17 @@ void phylink_generic_validate(struct phy
+ 			      unsigned long *supported,
+ 			      struct phylink_link_state *state);
+ 
+-struct phylink *phylink_create(struct phylink_config *, struct fwnode_handle *,
+-			       phy_interface_t iface,
+-			       const struct phylink_mac_ops *mac_ops);
++struct phylink *phylink_create(struct phylink_config *,
++			       const struct fwnode_handle *,
++			       phy_interface_t,
++			       const struct phylink_mac_ops *);
+ void phylink_destroy(struct phylink *);
+ bool phylink_expects_phy(struct phylink *pl);
+ 
+ int phylink_connect_phy(struct phylink *, struct phy_device *);
+ int phylink_of_phy_connect(struct phylink *, struct device_node *, u32 flags);
+ int phylink_fwnode_phy_connect(struct phylink *pl,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       u32 flags);
+ void phylink_disconnect_phy(struct phylink *);
+ 
diff --git a/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch b/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch
new file mode 100644
index 0000000000..2649634dc7
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch
@@ -0,0 +1,38 @@
+From 4a0faa02d419a6728abef0f1d8a32d8c35ef95e6 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Mar 2023 09:23:53 +0000
+Subject: [PATCH] net: phy: constify fwnode_get_phy_node() fwnode argument
+
+fwnode_get_phy_node() does not motify the fwnode structure, so make
+the argument const,
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy_device.c | 2 +-
+ include/linux/phy.h          | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -3003,7 +3003,7 @@ EXPORT_SYMBOL_GPL(device_phy_find_device
+  * and "phy-device" are not supported in ACPI. DT supports all the three
+  * named references to the phy node.
+  */
+-struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode)
++struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *phy_node;
+ 
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -1473,7 +1473,7 @@ int fwnode_get_phy_id(struct fwnode_hand
+ struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode);
+ struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode);
+ struct phy_device *device_phy_find_device(struct device *dev);
+-struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode);
++struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode);
+ struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
+ int phy_device_register(struct phy_device *phy);
+ void phy_device_free(struct phy_device *phydev);
diff --git a/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch b/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch
new file mode 100644
index 0000000000..5eba18b026
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch
@@ -0,0 +1,44 @@
+From cc73de0411f7d3cdd157564a78f7a39058420ff8 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 13 May 2023 22:03:45 +0100
+Subject: [PATCH 13/21] net: phylink: fix ksettings_set() ethtool call
+
+While testing a Fiberstore SFP-10G-T module (which uses 10GBASE-R with
+rate adaption) in a Clearfog platform (which can't do that) it was
+found that the PHYs advertisement was not limited according to the
+hosts capabilities when using ethtool to change it.
+
+Fix this by ensuring that we mask the advertisement with the computed
+support mask as the very first thing we do.
+
+Fixes: cbc1bb1e4689 ("net: phylink: simplify phy case for ksettings_set method")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -2226,6 +2226,10 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	ASSERT_RTNL();
+ 
++	/* Mask out unsupported advertisements */
++	linkmode_and(config.advertising, kset->link_modes.advertising,
++		     pl->supported);
++
+ 	if (pl->phydev) {
+ 		/* We can rely on phylib for this update; we also do not need
+ 		 * to update the pl->link_config settings:
+@@ -2250,10 +2254,6 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	config = pl->link_config;
+ 
+-	/* Mask out unsupported advertisements */
+-	linkmode_and(config.advertising, kset->link_modes.advertising,
+-		     pl->supported);
+-
+ 	/* FIXME: should we reject autoneg if phy/mac does not support it? */
+ 	switch (kset->base.autoneg) {
+ 	case AUTONEG_DISABLE:
diff --git a/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch b/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch
new file mode 100644
index 0000000000..79de6122b7
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch
@@ -0,0 +1,149 @@
+From 0100d1c5789018ba77bf2f4fab3bd91ecece7b3b Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 17 May 2023 11:38:12 +0100
+Subject: [PATCH 14/21] net: sfp: add support for setting signalling rate
+
+Add support to the SFP layer to allow phylink to set the signalling
+rate for a SFP module. The rate given will be in units of kilo-baud
+(1000 baud).
+
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 24 ++++++++++++++++++++++++
+ drivers/net/phy/sfp-bus.c | 20 ++++++++++++++++++++
+ drivers/net/phy/sfp.c     |  5 +++++
+ drivers/net/phy/sfp.h     |  1 +
+ include/linux/sfp.h       |  6 ++++++
+ 5 files changed, 56 insertions(+)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -156,6 +156,23 @@ static const char *phylink_an_mode_str(u
+ 	return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
+ }
+ 
++static unsigned int phylink_interface_signal_rate(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX: /* 1.25Mbd */
++		return 1250;
++	case PHY_INTERFACE_MODE_2500BASEX: /* 3.125Mbd */
++		return 3125;
++	case PHY_INTERFACE_MODE_5GBASER: /* 5.15625Mbd */
++		return 5156;
++	case PHY_INTERFACE_MODE_10GBASER: /* 10.3125Mbd */
++		return 10313;
++	default:
++		return 0;
++	}
++}
++
+ /**
+  * phylink_interface_max_speed() - get the maximum speed of a phy interface
+  * @interface: phy interface mode defined by &typedef phy_interface_t
+@@ -1024,6 +1041,7 @@ static void phylink_major_config(struct
+ {
+ 	struct phylink_pcs *pcs = NULL;
+ 	bool pcs_changed = false;
++	unsigned int rate_kbd;
+ 	int err;
+ 
+ 	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+@@ -1083,6 +1101,12 @@ static void phylink_major_config(struct
+ 				    ERR_PTR(err));
+ 	}
+ 
++	if (pl->sfp_bus) {
++		rate_kbd = phylink_interface_signal_rate(state->interface);
++		if (rate_kbd)
++			sfp_upstream_set_signal_rate(pl->sfp_bus, rate_kbd);
++	}
++
+ 	phylink_pcs_poll_start(pl);
+ }
+ 
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -586,6 +586,26 @@ static void sfp_upstream_clear(struct sf
+ }
+ 
+ /**
++ * sfp_upstream_set_signal_rate() - set data signalling rate
++ * @bus: a pointer to the &struct sfp_bus structure for the sfp module
++ * @rate_kbd: signalling rate in units of 1000 baud
++ *
++ * Configure the rate select settings on the SFP module for the signalling
++ * rate (not the same as the data rate).
++ *
++ * Locks that may be held:
++ *  Phylink's state_mutex
++ *  rtnl lock
++ *  SFP's sm_mutex
++ */
++void sfp_upstream_set_signal_rate(struct sfp_bus *bus, unsigned int rate_kbd)
++{
++	if (bus->registered)
++		bus->socket_ops->set_signal_rate(bus->sfp, rate_kbd);
++}
++EXPORT_SYMBOL_GPL(sfp_upstream_set_signal_rate);
++
++/**
+  * sfp_bus_find_fwnode() - parse and locate the SFP bus from fwnode
+  * @fwnode: firmware node for the parent device (MAC or PHY)
+  *
+--- a/drivers/net/phy/sfp.c
++++ b/drivers/net/phy/sfp.c
+@@ -2474,6 +2474,10 @@ static void sfp_stop(struct sfp *sfp)
+ 	sfp_sm_event(sfp, SFP_E_DEV_DOWN);
+ }
+ 
++static void sfp_set_signal_rate(struct sfp *sfp, unsigned int rate_kbd)
++{
++}
++
+ static int sfp_module_info(struct sfp *sfp, struct ethtool_modinfo *modinfo)
+ {
+ 	/* locking... and check module is present */
+@@ -2552,6 +2556,7 @@ static const struct sfp_socket_ops sfp_m
+ 	.detach = sfp_detach,
+ 	.start = sfp_start,
+ 	.stop = sfp_stop,
++	.set_signal_rate = sfp_set_signal_rate,
+ 	.module_info = sfp_module_info,
+ 	.module_eeprom = sfp_module_eeprom,
+ 	.module_eeprom_by_page = sfp_module_eeprom_by_page,
+--- a/drivers/net/phy/sfp.h
++++ b/drivers/net/phy/sfp.h
+@@ -19,6 +19,7 @@ struct sfp_socket_ops {
+ 	void (*detach)(struct sfp *sfp);
+ 	void (*start)(struct sfp *sfp);
+ 	void (*stop)(struct sfp *sfp);
++	void (*set_signal_rate)(struct sfp *sfp, unsigned int rate_kbd);
+ 	int (*module_info)(struct sfp *sfp, struct ethtool_modinfo *modinfo);
+ 	int (*module_eeprom)(struct sfp *sfp, struct ethtool_eeprom *ee,
+ 			     u8 *data);
+--- a/include/linux/sfp.h
++++ b/include/linux/sfp.h
+@@ -547,6 +547,7 @@ int sfp_get_module_eeprom_by_page(struct
+ 				  struct netlink_ext_ack *extack);
+ void sfp_upstream_start(struct sfp_bus *bus);
+ void sfp_upstream_stop(struct sfp_bus *bus);
++void sfp_upstream_set_signal_rate(struct sfp_bus *bus, unsigned int rate_kbd);
+ void sfp_bus_put(struct sfp_bus *bus);
+ struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode);
+ int sfp_bus_add_upstream(struct sfp_bus *bus, void *upstream,
+@@ -606,6 +607,11 @@ static inline void sfp_upstream_stop(str
+ {
+ }
+ 
++static inline void sfp_upstream_set_signal_rate(struct sfp_bus *bus,
++						unsigned int rate_kbd)
++{
++}
++
+ static inline void sfp_bus_put(struct sfp_bus *bus)
+ {
+ }
diff --git a/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch b/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch
new file mode 100644
index 0000000000..8a694c86da
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch
@@ -0,0 +1,147 @@
+From b84acdb07222a701bfc6403b374249c86f97d18d Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@armlinux.org.uk>
+Date: Fri, 19 May 2023 14:03:59 +0100
+Subject: [PATCH 15/21] net: phy: add helpers for comparing phy IDs
+
+There are several places which open code comparing PHY IDs. Provide a
+couple of helpers to assist with this, using a slightly simpler test
+than the original:
+
+- phy_id_compare() compares two arbitary PHY IDs and a mask of the
+  significant bits in the ID.
+- phydev_id_compare() compares the bound phydev with the specified
+  PHY ID, using the bound driver's mask.
+
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/micrel.c     |  6 +++---
+ drivers/net/phy/phy_device.c | 16 +++++++---------
+ drivers/net/phy/phylink.c    |  4 ++--
+ include/linux/phy.h          | 28 ++++++++++++++++++++++++++++
+ 4 files changed, 40 insertions(+), 14 deletions(-)
+
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -620,7 +620,7 @@ static int ksz8051_ksz8795_match_phy_dev
+ {
+ 	int ret;
+ 
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
++	if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
+ 		return 0;
+ 
+ 	ret = phy_read(phydev, MII_BMSR);
+@@ -1455,7 +1455,7 @@ static int ksz9x31_cable_test_fault_leng
+ 	 *
+ 	 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
+ 	 */
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131)
++	if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
+ 		dt = clamp(dt - 22, 0, 255);
+ 
+ 	return (dt * 400) / 10;
+@@ -1887,7 +1887,7 @@ static __always_inline int ksz886x_cable
+ 	 */
+ 	dt = FIELD_GET(data_mask, status);
+ 
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_LAN8814)
++	if (phydev_id_compare(phydev, PHY_ID_LAN8814))
+ 		return ((dt - 22) * 800) / 10;
+ 	else
+ 		return (dt * 400) / 10;
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -422,8 +422,7 @@ int phy_unregister_fixup(const char *bus
+ 		fixup = list_entry(pos, struct phy_fixup, list);
+ 
+ 		if ((!strcmp(fixup->bus_id, bus_id)) &&
+-		    ((fixup->phy_uid & phy_uid_mask) ==
+-		     (phy_uid & phy_uid_mask))) {
++		    phy_id_compare(fixup->phy_uid, phy_uid, phy_uid_mask)) {
+ 			list_del(&fixup->list);
+ 			kfree(fixup);
+ 			ret = 0;
+@@ -459,8 +458,8 @@ static int phy_needs_fixup(struct phy_de
+ 		if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0)
+ 			return 0;
+ 
+-	if ((fixup->phy_uid & fixup->phy_uid_mask) !=
+-	    (phydev->phy_id & fixup->phy_uid_mask))
++	if (!phy_id_compare(phydev->phy_id, fixup->phy_uid,
++			    fixup->phy_uid_mask))
+ 		if (fixup->phy_uid != PHY_ANY_UID)
+ 			return 0;
+ 
+@@ -507,15 +506,14 @@ static int phy_bus_match(struct device *
+ 			if (phydev->c45_ids.device_ids[i] == 0xffffffff)
+ 				continue;
+ 
+-			if ((phydrv->phy_id & phydrv->phy_id_mask) ==
+-			    (phydev->c45_ids.device_ids[i] &
+-			     phydrv->phy_id_mask))
++			if (phy_id_compare(phydev->c45_ids.device_ids[i],
++					   phydrv->phy_id, phydrv->phy_id_mask))
+ 				return 1;
+ 		}
+ 		return 0;
+ 	} else {
+-		return (phydrv->phy_id & phydrv->phy_id_mask) ==
+-			(phydev->phy_id & phydrv->phy_id_mask);
++		return phy_id_compare(phydev->phy_id, phydrv->phy_id,
++				      phydrv->phy_id_mask);
+ 	}
+ }
+ 
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3151,8 +3151,8 @@ static void phylink_sfp_link_up(void *up
+  */
+ static bool phylink_phy_no_inband(struct phy_device *phy)
+ {
+-	return phy->is_c45 &&
+-		(phy->c45_ids.device_ids[1] & 0xfffffff0) == 0xae025150;
++	return phy->is_c45 && phy_id_compare(phy->c45_ids.device_ids[1],
++					     0xae025150, 0xfffffff0);
+ }
+ 
+ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -993,6 +993,34 @@ struct phy_driver {
+ #define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
+ #define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
+ 
++/**
++ * phy_id_compare - compare @id1 with @id2 taking account of @mask
++ * @id1: first PHY ID
++ * @id2: second PHY ID
++ * @mask: the PHY ID mask, set bits are significant in matching
++ *
++ * Return true if the bits from @id1 and @id2 specified by @mask match.
++ * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask).
++ */
++static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask)
++{
++	return !((id1 ^ id2) & mask);
++}
++
++/**
++ * phydev_id_compare - compare @id with the PHY's Clause 22 ID
++ * @phydev: the PHY device
++ * @id: the PHY ID to be matched
++ *
++ * Compare the @phydev clause 22 ID with the provided @id and return true or
++ * false depending whether it matches, using the bound driver mask. The
++ * @phydev must be bound to a driver.
++ */
++static inline bool phydev_id_compare(struct phy_device *phydev, u32 id)
++{
++	return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask);
++}
++
+ /* A Structure for boards to register fixups with the PHY Lib */
+ struct phy_fixup {
+ 	struct list_head list;
diff --git a/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch b/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch
new file mode 100644
index 0000000000..5970355a6c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch
@@ -0,0 +1,71 @@
+From 441e1e44301fc5762a06737f8ec04bf1ce3fb039 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 20 May 2023 11:41:42 +0100
+Subject: [PATCH 16/21] net: phylink: require supported_interfaces to be filled
+
+We have been requiring the supported_interfaces bitmap to be filled in
+by MAC drivers that have a mac_select_pcs() method. Now that all MAC
+drivers fill in the supported_interfaces bitmap, it is time to enforce
+this. We have already required supported_interfaces to be set in order
+for optical SFPs to be configured in commit f81fa96d8a6c ("net: phylink:
+use phy_interface_t bitmaps for optical modules").
+
+Refuse phylink creation if supported_interfaces is empty, and remove
+code to deal with cases where this mask is empty.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1q0K1u-006EIP-ET@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 26 +++++++++++---------------
+ 1 file changed, 11 insertions(+), 15 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -710,14 +710,11 @@ static int phylink_validate(struct phyli
+ {
+ 	const unsigned long *interfaces = pl->config->supported_interfaces;
+ 
+-	if (!phy_interface_empty(interfaces)) {
+-		if (state->interface == PHY_INTERFACE_MODE_NA)
+-			return phylink_validate_mask(pl, supported, state,
+-						     interfaces);
++	if (state->interface == PHY_INTERFACE_MODE_NA)
++		return phylink_validate_mask(pl, supported, state, interfaces);
+ 
+-		if (!test_bit(state->interface, interfaces))
+-			return -EINVAL;
+-	}
++	if (!test_bit(state->interface, interfaces))
++		return -EINVAL;
+ 
+ 	return phylink_validate_mac_and_pcs(pl, supported, state);
+ }
+@@ -1512,19 +1509,18 @@ struct phylink *phylink_create(struct ph
+ 	struct phylink *pl;
+ 	int ret;
+ 
+-	if (mac_ops->mac_select_pcs &&
+-	    mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) !=
+-	      ERR_PTR(-EOPNOTSUPP))
+-		using_mac_select_pcs = true;
+-
+ 	/* Validate the supplied configuration */
+-	if (using_mac_select_pcs &&
+-	    phy_interface_empty(config->supported_interfaces)) {
++	if (phy_interface_empty(config->supported_interfaces)) {
+ 		dev_err(config->dev,
+-			"phylink: error: empty supported_interfaces but mac_select_pcs() method present\n");
++			"phylink: error: empty supported_interfaces\n");
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
++	if (mac_ops->mac_select_pcs &&
++	    mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) !=
++	      ERR_PTR(-EOPNOTSUPP))
++		using_mac_select_pcs = true;
++
+ 	pl = kzalloc(sizeof(*pl), GFP_KERNEL);
+ 	if (!pl)
+ 		return ERR_PTR(-ENOMEM);
diff --git a/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch b/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch
new file mode 100644
index 0000000000..3a26b4b600
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch
@@ -0,0 +1,64 @@
+From 4b624a39f2ab523ca6a6ad9448fab1deb7b101e2 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 11:15:53 +0100
+Subject: [PATCH 17/21] net: phylink: remove duplicated linkmode pause
+ resolution
+
+Phylink had two chunks of code virtually the same for resolving the
+negotiated pause modes. Factor this down to one function.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 15 ++++-----------
+ 1 file changed, 4 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -976,11 +976,10 @@ static void phylink_apply_manual_flow(st
+ 		state->pause = pl->link_config.pause;
+ }
+ 
+-static void phylink_resolve_flow(struct phylink_link_state *state)
++static void phylink_resolve_an_pause(struct phylink_link_state *state)
+ {
+ 	bool tx_pause, rx_pause;
+ 
+-	state->pause = MLO_PAUSE_NONE;
+ 	if (state->duplex == DUPLEX_FULL) {
+ 		linkmode_resolve_pause(state->advertising,
+ 				       state->lp_advertising,
+@@ -1192,7 +1191,8 @@ static void phylink_get_fixed_state(stru
+ 	else if (pl->link_gpio)
+ 		state->link = !!gpiod_get_value_cansleep(pl->link_gpio);
+ 
+-	phylink_resolve_flow(state);
++	state->pause = MLO_PAUSE_NONE;
++	phylink_resolve_an_pause(state);
+ }
+ 
+ static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)
+@@ -3215,7 +3215,6 @@ static const struct sfp_upstream_ops sfp
+ static void phylink_decode_c37_word(struct phylink_link_state *state,
+ 				    uint16_t config_reg, int speed)
+ {
+-	bool tx_pause, rx_pause;
+ 	int fd_bit;
+ 
+ 	if (speed == SPEED_2500)
+@@ -3234,13 +3233,7 @@ static void phylink_decode_c37_word(stru
+ 		state->link = false;
+ 	}
+ 
+-	linkmode_resolve_pause(state->advertising, state->lp_advertising,
+-			       &tx_pause, &rx_pause);
+-
+-	if (tx_pause)
+-		state->pause |= MLO_PAUSE_TX;
+-	if (rx_pause)
+-		state->pause |= MLO_PAUSE_RX;
++	phylink_resolve_an_pause(state);
+ }
+ 
+ static void phylink_decode_sgmii_word(struct phylink_link_state *state,
diff --git a/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch b/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch
new file mode 100644
index 0000000000..2b2634f80c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch
@@ -0,0 +1,76 @@
+From aa8b6bd2b1f235b262bd27f317a0516f196c2c6a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 11:15:58 +0100
+Subject: [PATCH 18/21] net: phylink: add function to resolve clause 73
+ negotiation
+
+Add a function to resolve clause 73 negotiation according to the
+priority resolution function described in clause 73.3.6.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 39 +++++++++++++++++++++++++++++++++++++++
+ include/linux/phylink.h   |  2 ++
+ 2 files changed, 41 insertions(+)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3212,6 +3212,45 @@ static const struct sfp_upstream_ops sfp
+ 
+ /* Helpers for MAC drivers */
+ 
++static struct {
++	int bit;
++	int speed;
++} phylink_c73_priority_resolution[] = {
++	{ ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, SPEED_100000 },
++	{ ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, SPEED_100000 },
++	/* 100GBASE-KP4 and 100GBASE-CR10 not supported */
++	{ ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, SPEED_40000 },
++	{ ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, SPEED_40000 },
++	{ ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, SPEED_10000 },
++	{ ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, SPEED_10000 },
++	/* 5GBASE-KR not supported */
++	{ ETHTOOL_LINK_MODE_2500baseX_Full_BIT, SPEED_2500 },
++	{ ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, SPEED_1000 },
++};
++
++void phylink_resolve_c73(struct phylink_link_state *state)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(phylink_c73_priority_resolution); i++) {
++		int bit = phylink_c73_priority_resolution[i].bit;
++		if (linkmode_test_bit(bit, state->advertising) &&
++		    linkmode_test_bit(bit, state->lp_advertising))
++			break;
++	}
++
++	if (i < ARRAY_SIZE(phylink_c73_priority_resolution)) {
++		state->speed = phylink_c73_priority_resolution[i].speed;
++		state->duplex = DUPLEX_FULL;
++	} else {
++		/* negotiation failure */
++		state->link = false;
++	}
++
++	phylink_resolve_an_pause(state);
++}
++EXPORT_SYMBOL_GPL(phylink_resolve_c73);
++
+ static void phylink_decode_c37_word(struct phylink_link_state *state,
+ 				    uint16_t config_reg, int speed)
+ {
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -656,6 +656,8 @@ int phylink_mii_c22_pcs_config(struct md
+ 			       const unsigned long *advertising);
+ void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
+ 
++void phylink_resolve_c73(struct phylink_link_state *state);
++
+ void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
+ 				   struct phylink_link_state *state);
+ 
diff --git a/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch b/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch
new file mode 100644
index 0000000000..eea99a5d78
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch
@@ -0,0 +1,100 @@
+From 796d709363135a6bd6a8ccc07b509c939e5b855f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 16:31:50 +0100
+Subject: [PATCH 19/21] net: phylink: provide phylink_pcs_config() and
+ phylink_pcs_link_up()
+
+Add two helper functions for calling PCS methods. phylink_pcs_config()
+allows us to handle PCS configuration specifics in one location, rather
+than the two call sites. phylink_pcs_link_up() gives us consistency.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1q1TzK-007Exd-Rs@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 53 ++++++++++++++++++++++++---------------
+ 1 file changed, 33 insertions(+), 20 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -991,6 +991,25 @@ static void phylink_resolve_an_pause(str
+ 	}
+ }
+ 
++static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++			      const struct phylink_link_state *state,
++			      bool permit_pause_to_mac)
++{
++	if (!pcs)
++		return 0;
++
++	return pcs->ops->pcs_config(pcs, mode, state->interface,
++				    state->advertising, permit_pause_to_mac);
++}
++
++static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++				phy_interface_t interface, int speed,
++				int duplex)
++{
++	if (pcs && pcs->ops->pcs_link_up)
++		pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
++}
++
+ static void phylink_pcs_poll_stop(struct phylink *pl)
+ {
+ 	if (pl->cfg_link_an_mode == MLO_AN_INBAND)
+@@ -1074,18 +1093,15 @@ static void phylink_major_config(struct
+ 
+ 	phylink_mac_config(pl, state);
+ 
+-	if (pl->pcs) {
+-		err = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
+-					       state->interface,
+-					       state->advertising,
+-					       !!(pl->link_config.pause &
+-						  MLO_PAUSE_AN));
+-		if (err < 0)
+-			phylink_err(pl, "pcs_config failed: %pe\n",
+-				    ERR_PTR(err));
+-		if (err > 0)
+-			restart = true;
+-	}
++	err = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode, state,
++				 !!(pl->link_config.pause &
++				    MLO_PAUSE_AN));
++	if (err < 0)
++		phylink_err(pl, "pcs_config failed: %pe\n",
++			    ERR_PTR(err));
++	else if (err > 0)
++		restart = true;
++
+ 	if (restart)
+ 		phylink_mac_pcs_an_restart(pl);
+ 
+@@ -1136,11 +1152,9 @@ static int phylink_change_inband_advert(
+ 	 * restart negotiation if the pcs_config() helper indicates that
+ 	 * the programmed advertisement has changed.
+ 	 */
+-	ret = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
+-				       pl->link_config.interface,
+-				       pl->link_config.advertising,
+-				       !!(pl->link_config.pause &
+-					  MLO_PAUSE_AN));
++	ret = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode,
++				 &pl->link_config,
++				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1272,9 +1286,8 @@ static void phylink_link_up(struct phyli
+ 
+ 	pl->cur_interface = link_state.interface;
+ 
+-	if (pl->pcs && pl->pcs->ops->pcs_link_up)
+-		pl->pcs->ops->pcs_link_up(pl->pcs, pl->cur_link_an_mode,
+-					  pl->cur_interface, speed, duplex);
++	phylink_pcs_link_up(pl->pcs, pl->cur_link_an_mode, pl->cur_interface,
++			    speed, duplex);
+ 
+ 	pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode,
+ 				 pl->cur_interface, speed, duplex,
diff --git a/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch b/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch
new file mode 100644
index 0000000000..2f7f7a5737
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch
@@ -0,0 +1,55 @@
+From 11933aa76865621d8e82553c8f3bc07796a5aaa2 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Thu, 1 Jun 2023 10:12:06 +0100
+Subject: [PATCH 20/21] net: phylink: actually fix ksettings_set() ethtool call
+
+Raju Lakkaraju reported that the below commit caused a regression
+with Lan743x drivers and a 2.5G SFP. Sadly, this is because the commit
+was utterly wrong. Let's fix this properly by not moving the
+linkmode_and(), but instead copying the link ksettings and then
+modifying the advertising mask before passing the modified link
+ksettings to phylib.
+
+Fixes: df0acdc59b09 ("net: phylink: fix ksettings_set() ethtool call")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1q4eLm-00Ayxk-GZ@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -2259,11 +2259,13 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	ASSERT_RTNL();
+ 
+-	/* Mask out unsupported advertisements */
+-	linkmode_and(config.advertising, kset->link_modes.advertising,
+-		     pl->supported);
+-
+ 	if (pl->phydev) {
++		struct ethtool_link_ksettings phy_kset = *kset;
++
++		linkmode_and(phy_kset.link_modes.advertising,
++			     phy_kset.link_modes.advertising,
++			     pl->supported);
++
+ 		/* We can rely on phylib for this update; we also do not need
+ 		 * to update the pl->link_config settings:
+ 		 * - the configuration returned via ksettings_get() will come
+@@ -2282,10 +2284,13 @@ int phylink_ethtool_ksettings_set(struct
+ 		 *   the presence of a PHY, this should not be changed as that
+ 		 *   should be determined from the media side advertisement.
+ 		 */
+-		return phy_ethtool_ksettings_set(pl->phydev, kset);
++		return phy_ethtool_ksettings_set(pl->phydev, &phy_kset);
+ 	}
+ 
+ 	config = pl->link_config;
++	/* Mask out unsupported advertisements */
++	linkmode_and(config.advertising, kset->link_modes.advertising,
++		     pl->supported);
+ 
+ 	/* FIXME: should we reject autoneg if phy/mac does not support it? */
+ 	switch (kset->base.autoneg) {
diff --git a/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch b/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch
new file mode 100644
index 0000000000..e1a8539aae
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch
@@ -0,0 +1,324 @@
+From 79b07c3e9c4a2272927be8848c26b372516e1958 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:22 +0100
+Subject: [PATCH 21/21] net: phylink: add PCS negotiation mode
+
+PCS have to work out whether they should enable PCS negotiation by
+looking at the "mode" and "interface" arguments, and the Autoneg bit
+in the advertising mask.
+
+This leads to some complex logic, so lets pull that out into phylink
+and instead pass a "neg_mode" argument to the PCS configuration and
+link up methods, instead of the "mode" argument.
+
+In order to transition drivers, add a "neg_mode" flag to the phylink
+PCS structure to PCS can indicate whether they want to be passed the
+neg_mode or the old mode argument.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8De-00EaFA-Ht@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c |  45 +++++++++++++----
+ include/linux/phylink.h   | 104 +++++++++++++++++++++++++++++++++++---
+ 2 files changed, 132 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -71,6 +71,7 @@ struct phylink {
+ 	struct mutex state_mutex;
+ 	struct phylink_link_state phy_state;
+ 	struct work_struct resolve;
++	unsigned int pcs_neg_mode;
+ 
+ 	bool mac_link_dropped;
+ 	bool using_mac_select_pcs;
+@@ -991,23 +992,23 @@ static void phylink_resolve_an_pause(str
+ 	}
+ }
+ 
+-static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      const struct phylink_link_state *state,
+ 			      bool permit_pause_to_mac)
+ {
+ 	if (!pcs)
+ 		return 0;
+ 
+-	return pcs->ops->pcs_config(pcs, mode, state->interface,
++	return pcs->ops->pcs_config(pcs, neg_mode, state->interface,
+ 				    state->advertising, permit_pause_to_mac);
+ }
+ 
+-static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface, int speed,
+ 				int duplex)
+ {
+ 	if (pcs && pcs->ops->pcs_link_up)
+-		pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
++		pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
+ }
+ 
+ static void phylink_pcs_poll_stop(struct phylink *pl)
+@@ -1057,10 +1058,15 @@ static void phylink_major_config(struct
+ 	struct phylink_pcs *pcs = NULL;
+ 	bool pcs_changed = false;
+ 	unsigned int rate_kbd;
++	unsigned int neg_mode;
+ 	int err;
+ 
+ 	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+ 
++	pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
++						state->interface,
++						state->advertising);
++
+ 	if (pl->using_mac_select_pcs) {
+ 		pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
+ 		if (IS_ERR(pcs)) {
+@@ -1093,9 +1099,12 @@ static void phylink_major_config(struct
+ 
+ 	phylink_mac_config(pl, state);
+ 
+-	err = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode, state,
+-				 !!(pl->link_config.pause &
+-				    MLO_PAUSE_AN));
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs && pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
++	err = phylink_pcs_config(pl->pcs, neg_mode, state,
++				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (err < 0)
+ 		phylink_err(pl, "pcs_config failed: %pe\n",
+ 			    ERR_PTR(err));
+@@ -1130,6 +1139,7 @@ static void phylink_major_config(struct
+  */
+ static int phylink_change_inband_advert(struct phylink *pl)
+ {
++	unsigned int neg_mode;
+ 	int ret;
+ 
+ 	if (test_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state))
+@@ -1148,12 +1158,20 @@ static int phylink_change_inband_advert(
+ 		    __ETHTOOL_LINK_MODE_MASK_NBITS, pl->link_config.advertising,
+ 		    pl->link_config.pause);
+ 
++	/* Recompute the PCS neg mode */
++	pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
++					pl->link_config.interface,
++					pl->link_config.advertising);
++
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
+ 	/* Modern PCS-based method; update the advert at the PCS, and
+ 	 * restart negotiation if the pcs_config() helper indicates that
+ 	 * the programmed advertisement has changed.
+ 	 */
+-	ret = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode,
+-				 &pl->link_config,
++	ret = phylink_pcs_config(pl->pcs, neg_mode, &pl->link_config,
+ 				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (ret < 0)
+ 		return ret;
+@@ -1256,6 +1274,7 @@ static void phylink_link_up(struct phyli
+ 			    struct phylink_link_state link_state)
+ {
+ 	struct net_device *ndev = pl->netdev;
++	unsigned int neg_mode;
+ 	int speed, duplex;
+ 	bool rx_pause;
+ 
+@@ -1286,8 +1305,12 @@ static void phylink_link_up(struct phyli
+ 
+ 	pl->cur_interface = link_state.interface;
+ 
+-	phylink_pcs_link_up(pl->pcs, pl->cur_link_an_mode, pl->cur_interface,
+-			    speed, duplex);
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs && pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
++	phylink_pcs_link_up(pl->pcs, neg_mode, pl->cur_interface, speed,
++			    duplex);
+ 
+ 	pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode,
+ 				 pl->cur_interface, speed, duplex,
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -21,6 +21,24 @@ enum {
+ 	MLO_AN_FIXED,	/* Fixed-link mode */
+ 	MLO_AN_INBAND,	/* In-band protocol */
+ 
++	/* PCS "negotiation" mode.
++	 *  PHYLINK_PCS_NEG_NONE - protocol has no inband capability
++	 *  PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
++	 *  PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
++	 *				      1000base-X with autoneg off
++	 *  PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
++	 * Additionally, this can be tested using bitmasks:
++	 *  PHYLINK_PCS_NEG_INBAND - inband mode selected
++	 *  PHYLINK_PCS_NEG_ENABLED - negotiation mode enabled
++	 */
++	PHYLINK_PCS_NEG_NONE = 0,
++	PHYLINK_PCS_NEG_ENABLED = BIT(4),
++	PHYLINK_PCS_NEG_OUTBAND = BIT(5),
++	PHYLINK_PCS_NEG_INBAND = BIT(6),
++	PHYLINK_PCS_NEG_INBAND_DISABLED = PHYLINK_PCS_NEG_INBAND,
++	PHYLINK_PCS_NEG_INBAND_ENABLED = PHYLINK_PCS_NEG_INBAND |
++					 PHYLINK_PCS_NEG_ENABLED,
++
+ 	/* MAC_SYM_PAUSE and MAC_ASYM_PAUSE are used when configuring our
+ 	 * autonegotiation advertisement. They correspond to the PAUSE and
+ 	 * ASM_DIR bits defined by 802.3, respectively.
+@@ -80,6 +98,70 @@ static inline bool phylink_autoneg_inban
+ }
+ 
+ /**
++ * phylink_pcs_neg_mode() - helper to determine PCS inband mode
++ * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @interface: interface mode to be used
++ * @advertising: adertisement ethtool link mode mask
++ *
++ * Determines the negotiation mode to be used by the PCS, and returns
++ * one of:
++ * %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
++ * %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
++ *   will be used.
++ * %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg disabled
++ * %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
++ *
++ * Note: this is for cases where the PCS itself is involved in negotiation
++ * (e.g. Clause 37, SGMII and similar) not Clause 73.
++ */
++static inline unsigned int phylink_pcs_neg_mode(unsigned int mode,
++						phy_interface_t interface,
++						const unsigned long *advertising)
++{
++	unsigned int neg_mode;
++
++	switch (interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_QUSGMII:
++	case PHY_INTERFACE_MODE_USXGMII:
++		/* These protocols are designed for use with a PHY which
++		 * communicates its negotiation result back to the MAC via
++		 * inband communication. Note: there exist PHYs that run
++		 * with SGMII but do not send the inband data.
++		 */
++		if (!phylink_autoneg_inband(mode))
++			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++		else
++			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++		break;
++
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		/* 1000base-X is designed for use media-side for Fibre
++		 * connections, and thus the Autoneg bit needs to be
++		 * taken into account. We also do this for 2500base-X
++		 * as well, but drivers may not support this, so may
++		 * need to override this.
++		 */
++		if (!phylink_autoneg_inband(mode))
++			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					   advertising))
++			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++		else
++			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
++		break;
++
++	default:
++		neg_mode = PHYLINK_PCS_NEG_NONE;
++		break;
++	}
++
++	return neg_mode;
++}
++
++/**
+  * struct phylink_link_state - link state structure
+  * @advertising: ethtool bitmask containing advertised link modes
+  * @lp_advertising: ethtool bitmask containing link partner advertised link
+@@ -436,6 +518,7 @@ struct phylink_pcs_ops;
+ /**
+  * struct phylink_pcs - PHYLINK PCS instance
+  * @ops: a pointer to the &struct phylink_pcs_ops structure
++ * @neg_mode: provide PCS neg mode via "mode" argument
+  * @poll: poll the PCS for link changes
+  *
+  * This structure is designed to be embedded within the PCS private data,
+@@ -443,6 +526,7 @@ struct phylink_pcs_ops;
+  */
+ struct phylink_pcs {
+ 	const struct phylink_pcs_ops *ops;
++	bool neg_mode;
+ 	bool poll;
+ };
+ 
+@@ -460,12 +544,12 @@ struct phylink_pcs_ops {
+ 			    const struct phylink_link_state *state);
+ 	void (*pcs_get_state)(struct phylink_pcs *pcs,
+ 			      struct phylink_link_state *state);
+-	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode,
++	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			  phy_interface_t interface,
+ 			  const unsigned long *advertising,
+ 			  bool permit_pause_to_mac);
+ 	void (*pcs_an_restart)(struct phylink_pcs *pcs);
+-	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int mode,
++	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			    phy_interface_t interface, int speed, int duplex);
+ };
+ 
+@@ -508,7 +592,7 @@ void pcs_get_state(struct phylink_pcs *p
+ /**
+  * pcs_config() - Configure the PCS mode and advertisement
+  * @pcs: a pointer to a &struct phylink_pcs.
+- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @neg_mode: link negotiation mode (see below)
+  * @interface: interface mode to be used
+  * @advertising: adertisement ethtool link mode mask
+  * @permit_pause_to_mac: permit forwarding pause resolution to MAC
+@@ -526,8 +610,12 @@ void pcs_get_state(struct phylink_pcs *p
+  * For 1000BASE-X, the advertisement should be programmed into the PCS.
+  *
+  * For most 10GBASE-R, there is no advertisement.
++ *
++ * The %neg_mode argument should be tested via the phylink_mode_*() family of
++ * functions, or for PCS that set pcs->neg_mode true, should be tested
++ * against the %PHYLINK_PCS_NEG_* definitions.
+  */
+-int pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++int pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 	       phy_interface_t interface, const unsigned long *advertising,
+ 	       bool permit_pause_to_mac);
+ 
+@@ -543,7 +631,7 @@ void pcs_an_restart(struct phylink_pcs *
+ /**
+  * pcs_link_up() - program the PCS for the resolved link configuration
+  * @pcs: a pointer to a &struct phylink_pcs.
+- * @mode: link autonegotiation mode
++ * @neg_mode: link negotiation mode (see below)
+  * @interface: link &typedef phy_interface_t mode
+  * @speed: link speed
+  * @duplex: link duplex
+@@ -552,8 +640,12 @@ void pcs_an_restart(struct phylink_pcs *
+  * the resolved link parameters. For example, a PCS operating in SGMII
+  * mode without in-band AN needs to be manually configured for the link
+  * and duplex setting. Otherwise, this should be a no-op.
++ *
++ * The %mode argument should be tested via the phylink_mode_*() family of
++ * functions, or for PCS that set pcs->neg_mode true, should be tested
++ * against the %PHYLINK_PCS_NEG_* definitions.
+  */
+-void pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 		 phy_interface_t interface, int speed, int duplex);
+ #endif
+ 
diff --git a/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch b/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch
new file mode 100644
index 0000000000..473e9d5836
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch
@@ -0,0 +1,45 @@
+From cdb08aa0473730315dbc088d5394e59622314034 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:27 +0100
+Subject: [PATCH 1/2] net: phylink: convert phylink_mii_c22_pcs_config() to
+ neg_mode
+
+Use phylink_pcs_neg_mode() for phylink_mii_c22_pcs_config(). This
+results in no functional change.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Dj-00EaFG-Mt@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3558,6 +3558,7 @@ int phylink_mii_c22_pcs_config(struct md
+ 			       phy_interface_t interface,
+ 			       const unsigned long *advertising)
+ {
++	unsigned int neg_mode;
+ 	bool changed = 0;
+ 	u16 bmcr;
+ 	int ret, adv;
+@@ -3571,15 +3572,13 @@ int phylink_mii_c22_pcs_config(struct md
+ 		changed = ret;
+ 	}
+ 
+-	/* Ensure ISOLATE bit is disabled */
+-	if (mode == MLO_AN_INBAND &&
+-	    (interface == PHY_INTERFACE_MODE_SGMII ||
+-	     interface == PHY_INTERFACE_MODE_QSGMII ||
+-	     linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)))
++	neg_mode = phylink_pcs_neg_mode(mode, interface, advertising);
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ 		bmcr = BMCR_ANENABLE;
+ 	else
+ 		bmcr = 0;
+ 
++	/* Configure the inband state. Ensure ISOLATE bit is disabled */
+ 	ret = mdiodev_modify(pcs, MII_BMCR, BMCR_ANENABLE | BMCR_ISOLATE, bmcr);
+ 	if (ret < 0)
+ 		return ret;
diff --git a/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch
new file mode 100644
index 0000000000..5572850e95
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch
@@ -0,0 +1,187 @@
+From febf2aaf05641f3258cc30e072aff65cffc7c82c Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:32 +0100
+Subject: [PATCH 2/2] net: phylink: pass neg_mode into
+ phylink_mii_c22_pcs_config()
+
+Convert fman_dtsec, xilinx_axienet and pcs-lynx to pass the neg_mode
+into phylink_mii_c22_pcs_config(). Where appropriate, drivers are
+updated to have neg_mode passed into their pcs_config() and
+pcs_link_up() functions. For other drivers, we just hoist the call
+to phylink_pcs_neg_mode() to their pcs_config() method out of
+phylink_mii_c22_pcs_config().
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Do-00EaFM-Ra@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../net/ethernet/freescale/fman/fman_dtsec.c   |  7 ++++---
+ .../net/ethernet/xilinx/xilinx_axienet_main.c  |  6 ++++--
+ drivers/net/pcs/pcs-lynx.c                     | 18 ++++++++++++------
+ drivers/net/phy/phylink.c                      |  9 ++++-----
+ include/linux/phylink.h                        |  5 +++--
+ 5 files changed, 27 insertions(+), 18 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -763,15 +763,15 @@ static void dtsec_pcs_get_state(struct p
+ 	phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
+ }
+ 
+-static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			    phy_interface_t interface,
+ 			    const unsigned long *advertising,
+ 			    bool permit_pause_to_mac)
+ {
+ 	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
+ 
+-	return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
+-					  advertising);
++	return phylink_mii_c22_pcs_config(dtsec->tbidev, interface,
++					  advertising, neg_mode);
+ }
+ 
+ static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
+@@ -1447,6 +1447,7 @@ int dtsec_initialization(struct mac_devi
+ 		goto _return_fm_mac_free;
+ 	}
+ 	dtsec->pcs.ops = &dtsec_pcs_ops;
++	dtsec->pcs.neg_mode = true;
+ 	dtsec->pcs.poll = true;
+ 
+ 	supported = mac_dev->phylink_config.supported_interfaces;
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -1631,7 +1631,7 @@ static void axienet_pcs_an_restart(struc
+ 	phylink_mii_c22_pcs_an_restart(pcs_phy);
+ }
+ 
+-static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      phy_interface_t interface,
+ 			      const unsigned long *advertising,
+ 			      bool permit_pause_to_mac)
+@@ -1653,7 +1653,8 @@ static int axienet_pcs_config(struct phy
+ 		}
+ 	}
+ 
+-	ret = phylink_mii_c22_pcs_config(pcs_phy, mode, interface, advertising);
++	ret = phylink_mii_c22_pcs_config(pcs_phy, interface, advertising,
++					 neg_mode);
+ 	if (ret < 0)
+ 		netdev_warn(ndev, "Failed to configure PCS: %d\n", ret);
+ 
+@@ -2129,6 +2130,7 @@ static int axienet_probe(struct platform
+ 		}
+ 		of_node_put(np);
+ 		lp->pcs.ops = &axienet_pcs_ops;
++		lp->pcs.neg_mode = true;
+ 		lp->pcs.poll = true;
+ 	}
+ 
+--- a/drivers/net/pcs/pcs-lynx.c
++++ b/drivers/net/pcs/pcs-lynx.c
+@@ -122,9 +122,10 @@ static void lynx_pcs_get_state(struct ph
+ 		state->link, state->an_complete);
+ }
+ 
+-static int lynx_pcs_config_giga(struct mdio_device *pcs, unsigned int mode,
++static int lynx_pcs_config_giga(struct mdio_device *pcs,
+ 				phy_interface_t interface,
+-				const unsigned long *advertising)
++				const unsigned long *advertising,
++				unsigned int neg_mode)
+ {
+ 	u32 link_timer;
+ 	u16 if_mode;
+@@ -137,8 +138,9 @@ static int lynx_pcs_config_giga(struct m
+ 
+ 		if_mode = 0;
+ 	} else {
++		/* SGMII and QSGMII */
+ 		if_mode = IF_MODE_SGMII_EN;
+-		if (mode == MLO_AN_INBAND) {
++		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ 			if_mode |= IF_MODE_USE_SGMII_AN;
+ 
+ 			/* Adjust link timer for SGMII */
+@@ -154,7 +156,8 @@ static int lynx_pcs_config_giga(struct m
+ 	if (err)
+ 		return err;
+ 
+-	return phylink_mii_c22_pcs_config(pcs, mode, interface, advertising);
++	return phylink_mii_c22_pcs_config(pcs, interface, advertising,
++					  neg_mode);
+ }
+ 
+ static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode,
+@@ -181,13 +184,16 @@ static int lynx_pcs_config(struct phylin
+ 			   bool permit)
+ {
+ 	struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
++	unsigned int neg_mode;
++
++	neg_mode = phylink_pcs_neg_mode(mode, ifmode, advertising);
+ 
+ 	switch (ifmode) {
+ 	case PHY_INTERFACE_MODE_1000BASEX:
+ 	case PHY_INTERFACE_MODE_SGMII:
+ 	case PHY_INTERFACE_MODE_QSGMII:
+-		return lynx_pcs_config_giga(lynx->mdio, mode, ifmode,
+-					    advertising);
++		return lynx_pcs_config_giga(lynx->mdio, ifmode, advertising,
++					    neg_mode);
+ 	case PHY_INTERFACE_MODE_2500BASEX:
+ 		if (phylink_autoneg_inband(mode)) {
+ 			dev_err(&lynx->mdio->dev,
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3545,20 +3545,20 @@ EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_en
+ /**
+  * phylink_mii_c22_pcs_config() - configure clause 22 PCS
+  * @pcs: a pointer to a &struct mdio_device.
+- * @mode: link autonegotiation mode
+  * @interface: the PHY interface mode being configured
+  * @advertising: the ethtool advertisement mask
++ * @neg_mode: PCS negotiation mode
+  *
+  * Configure a Clause 22 PCS PHY with the appropriate negotiation
+  * parameters for the @mode, @interface and @advertising parameters.
+  * Returns negative error number on failure, zero if the advertisement
+  * has not changed, or positive if there is a change.
+  */
+-int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
++int phylink_mii_c22_pcs_config(struct mdio_device *pcs,
+ 			       phy_interface_t interface,
+-			       const unsigned long *advertising)
++			       const unsigned long *advertising,
++			       unsigned int neg_mode)
+ {
+-	unsigned int neg_mode;
+ 	bool changed = 0;
+ 	u16 bmcr;
+ 	int ret, adv;
+@@ -3572,7 +3572,6 @@ int phylink_mii_c22_pcs_config(struct md
+ 		changed = ret;
+ 	}
+ 
+-	neg_mode = phylink_pcs_neg_mode(mode, interface, advertising);
+ 	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ 		bmcr = BMCR_ANENABLE;
+ 	else
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -743,9 +743,10 @@ void phylink_mii_c22_pcs_get_state(struc
+ 				   struct phylink_link_state *state);
+ int phylink_mii_c22_pcs_encode_advertisement(phy_interface_t interface,
+ 					     const unsigned long *advertising);
+-int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
++int phylink_mii_c22_pcs_config(struct mdio_device *pcs,
+ 			       phy_interface_t interface,
+-			       const unsigned long *advertising);
++			       const unsigned long *advertising,
++			       unsigned int neg_mode);
+ void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
+ 
+ void phylink_resolve_c73(struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch b/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch
new file mode 100644
index 0000000000..5e0128766c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch
@@ -0,0 +1,101 @@
+From 3b2de56a146f34e3f70a84cc3a1897064e445d16 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:43 +0100
+Subject: [PATCH] net: pcs: lynxi: update PCS driver to use neg_mode
+
+Update the Lynxi PCS driver to use neg_mode rather than the mode
+argument. This ensures that the link_up() method will always program
+the speed and duplex when negotiation is disabled.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Dz-00EaFY-5A@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c | 39 ++++++++++++++-------------------
+ 1 file changed, 16 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -102,13 +102,13 @@ static void mtk_pcs_lynxi_get_state(stru
+ 					 FIELD_GET(SGMII_LPA, adv));
+ }
+ 
+-static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int mode,
++static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface,
+ 				const unsigned long *advertising,
+ 				bool permit_pause_to_mac)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+-	bool mode_changed = false, changed, use_an;
++	bool mode_changed = false, changed;
+ 	unsigned int rgc3, sgm_mode, bmcr;
+ 	int advertise, link_timer;
+ 
+@@ -121,30 +121,22 @@ static int mtk_pcs_lynxi_config(struct p
+ 	 * we assume that fixes it's speed at bitrate = line rate (in
+ 	 * other words, 1000Mbps or 2500Mbps).
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_SGMII) {
++	if (interface == PHY_INTERFACE_MODE_SGMII)
+ 		sgm_mode = SGMII_IF_MODE_SGMII;
+-		if (phylink_autoneg_inband(mode)) {
+-			sgm_mode |= SGMII_REMOTE_FAULT_DIS |
+-				    SGMII_SPEED_DUPLEX_AN;
+-			use_an = true;
+-		} else {
+-			use_an = false;
+-		}
+-	} else if (phylink_autoneg_inband(mode)) {
+-		/* 1000base-X or 2500base-X autoneg */
+-		sgm_mode = SGMII_REMOTE_FAULT_DIS;
+-		use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+-					   advertising);
+-	} else {
++	else
+ 		/* 1000base-X or 2500base-X without autoneg */
+ 		sgm_mode = 0;
+-		use_an = false;
+-	}
+ 
+-	if (use_an)
++	if (neg_mode & PHYLINK_PCS_NEG_INBAND)
++		sgm_mode |= SGMII_REMOTE_FAULT_DIS;
++
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
++		if (interface == PHY_INTERFACE_MODE_SGMII)
++			sgm_mode |= SGMII_SPEED_DUPLEX_AN;
+ 		bmcr = BMCR_ANENABLE;
+-	else
++	} else {
+ 		bmcr = 0;
++	}
+ 
+ 	if (mpcs->interface != interface) {
+ 		link_timer = phylink_get_link_timer_ns(interface);
+@@ -216,14 +208,15 @@ static void mtk_pcs_lynxi_restart_an(str
+ 	regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART);
+ }
+ 
+-static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs, unsigned int mode,
++static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
++				  unsigned int neg_mode,
+ 				  phy_interface_t interface, int speed,
+ 				  int duplex)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ 	unsigned int sgm_mode;
+ 
+-	if (!phylink_autoneg_inband(mode)) {
++	if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ 		/* Force the speed and duplex setting */
+ 		if (speed == SPEED_10)
+ 			sgm_mode = SGMII_SPEED_10;
+@@ -286,6 +279,7 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 	mpcs->regmap = regmap;
+ 	mpcs->flags = flags;
+ 	mpcs->pcs.ops = &mtk_pcs_lynxi_ops;
++	mpcs->pcs.neg_mode = true;
+ 	mpcs->pcs.poll = true;
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ 
diff --git a/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch b/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch
new file mode 100644
index 0000000000..3dd22d2916
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch
@@ -0,0 +1,55 @@
+From 459fd2f11204c962e3153020f4f56748e0e10afb Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:49 +0000
+Subject: [PATCH] net: pcs: xpcs: use Autoneg bit rather than an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. Thus, we will be removing state->an_enabled.
+
+Use the Autoneg bit in the advertising bitmap to indicate whether
+autonegotiation should be used, rather than using the an_enabled
+member which will be going away.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/pcs/pcs-xpcs.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/pcs/pcs-xpcs.c
++++ b/drivers/net/pcs/pcs-xpcs.c
+@@ -931,6 +931,7 @@ static int xpcs_get_state_c73(struct dw_
+ 			      struct phylink_link_state *state,
+ 			      const struct xpcs_compat *compat)
+ {
++	bool an_enabled;
+ 	int ret;
+ 
+ 	/* Link needs to be read first ... */
+@@ -948,11 +949,13 @@ static int xpcs_get_state_c73(struct dw_
+ 		return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND, NULL);
+ 	}
+ 
+-	if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
++	an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++				       state->advertising);
++	if (an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
+ 		state->an_complete = true;
+ 		xpcs_read_lpa_c73(xpcs, state);
+ 		xpcs_resolve_lpa_c73(xpcs, state);
+-	} else if (state->an_enabled) {
++	} else if (an_enabled) {
+ 		state->link = 0;
+ 	} else if (state->link) {
+ 		xpcs_resolve_pma(xpcs, state);
+@@ -1007,7 +1010,8 @@ static int xpcs_get_state_c37_1000basex(
+ {
+ 	int lpa, bmsr;
+ 
+-	if (state->an_enabled) {
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising)) {
+ 		/* Reset link state */
+ 		state->link = false;
+ 
diff --git a/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch b/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch
new file mode 100644
index 0000000000..7cae8515fa
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch
@@ -0,0 +1,30 @@
+From 43fb622d91a9f408322735d2f736495c1009f575 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 9 May 2023 12:50:04 +0100
+Subject: [PATCH] net: pcs: xpcs: fix incorrect number of interfaces
+
+In synopsys_xpcs_compat[], the DW_XPCS_2500BASEX entry was setting
+the number of interfaces using the xpcs_2500basex_features array
+rather than xpcs_2500basex_interfaces. This causes us to overflow
+the array of interfaces. Fix this.
+
+Fixes: f27abde3042a ("net: pcs: add 2500BASEX support for Intel mGbE controller")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/pcs/pcs-xpcs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/pcs/pcs-xpcs.c
++++ b/drivers/net/pcs/pcs-xpcs.c
+@@ -1211,7 +1211,7 @@ static const struct xpcs_compat synopsys
+ 	[DW_XPCS_2500BASEX] = {
+ 		.supported = xpcs_2500basex_features,
+ 		.interface = xpcs_2500basex_interfaces,
+-		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
++		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
+ 		.an_mode = DW_2500BASEX,
+ 	},
+ };
diff --git a/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch b/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch
index 2e38269060..3c7bf6c132 100644
--- a/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch
+++ b/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch
@@ -27,7 +27,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1650,6 +1650,7 @@ int phy_package_join(struct phy_device *
+@@ -1648,6 +1648,7 @@ int phy_package_join(struct phy_device *
  			shared->priv_size = priv_size;
  		}
  		shared->base_addr = base_addr;
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		refcount_set(&shared->refcnt, 1);
  		bus->shared[base_addr] = shared;
  	} else {
-@@ -1673,6 +1674,63 @@ err_unlock:
+@@ -1671,6 +1672,63 @@ err_unlock:
  EXPORT_SYMBOL_GPL(phy_package_join);
  
  /**
@@ -99,7 +99,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * phy_package_leave - leave a common PHY group
   * @phydev: target phy_device struct
   *
-@@ -1688,6 +1746,10 @@ void phy_package_leave(struct phy_device
+@@ -1686,6 +1744,10 @@ void phy_package_leave(struct phy_device
  	if (!shared)
  		return;
  
@@ -110,7 +110,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
  		bus->shared[shared->base_addr] = NULL;
  		mutex_unlock(&bus->shared_lock);
-@@ -1741,6 +1803,40 @@ int devm_phy_package_join(struct device
+@@ -1739,6 +1801,40 @@ int devm_phy_package_join(struct device
  EXPORT_SYMBOL_GPL(devm_phy_package_join);
  
  /**
@@ -170,7 +170,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	refcount_t refcnt;
  	unsigned long flags;
  	size_t priv_size;
-@@ -1765,9 +1768,12 @@ int phy_ethtool_set_link_ksettings(struc
+@@ -1793,9 +1796,12 @@ int phy_ethtool_set_link_ksettings(struc
  				   const struct ethtool_link_ksettings *cmd);
  int phy_ethtool_nway_reset(struct net_device *ndev);
  int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch b/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch
index 4371599f4a..acaa4a644e 100644
--- a/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch
+++ b/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch
@@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2551,12 +2551,15 @@ EXPORT_SYMBOL(genphy_read_status);
+@@ -2549,12 +2549,15 @@ EXPORT_SYMBOL(genphy_read_status);
  /**
   * genphy_c37_read_status - check the link status and update current link state
   * @phydev: target phy_device struct
@@ -58,7 +58,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  {
  	int lpa, err, old_link = phydev->link;
  
-@@ -2566,9 +2569,13 @@ int genphy_c37_read_status(struct phy_de
+@@ -2564,9 +2567,13 @@ int genphy_c37_read_status(struct phy_de
  		return err;
  
  	/* why bother the PHY if nothing can have changed */
@@ -89,7 +89,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -1660,7 +1660,7 @@ int genphy_write_mmd_unsupported(struct
+@@ -1688,7 +1688,7 @@ int genphy_write_mmd_unsupported(struct
  
  /* Clause 37 */
  int genphy_c37_config_aneg(struct phy_device *phydev);
diff --git a/target/linux/generic/pending-6.1/778-net-phy-qca807x-move-interface-mode-check-to-.config.patch b/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch
similarity index 83%
rename from target/linux/generic/pending-6.1/778-net-phy-qca807x-move-interface-mode-check-to-.config.patch
rename to target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch
index e4e60bc3ed..53652c38fc 100644
--- a/target/linux/generic/pending-6.1/778-net-phy-qca807x-move-interface-mode-check-to-.config.patch
+++ b/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch
@@ -1,7 +1,7 @@
-From 824d6c9747fb46eadf763b879fb1c072e541a65a Mon Sep 17 00:00:00 2001
+From 3be0d950b62852a693182cb678948f481de02825 Mon Sep 17 00:00:00 2001
 From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 12 Feb 2024 12:26:41 +0100
-Subject: [PATCH net-next] net: phy: qca807x: move interface mode check to
+Date: Mon, 12 Feb 2024 12:49:34 +0100
+Subject: [PATCH] net: phy: qca807x: move interface mode check to
  .config_init_once
 
 Currently, we are checking whether the PHY package mode matches the
@@ -16,6 +16,9 @@ PHY interface modes should be populated.
 
 Fixes: d1cb613efbd3 ("net: phy: qcom: add support for QCA807x PHY Family")
 Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240212115043.1725918-1-robimarko@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 ---
  drivers/net/phy/qcom/qca807x.c | 10 +++++-----
  1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
index 5526791624..816aa67787 100644
--- a/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
+++ b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4334,6 +4334,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4333,6 +4333,7 @@ static const struct mtk_soc_data mt7986_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7986_CLKS_BITMAP,
  	.required_pctl = false,
diff --git a/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch b/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
index 95a21e1c9a..cefe1eefff 100644
--- a/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
+++ b/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
@@ -12,7 +12,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3481,11 +3481,8 @@ static void mtk_pending_work(struct work
+@@ -3480,11 +3480,8 @@ static void mtk_pending_work(struct work
  	rtnl_lock();
  
  	dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
@@ -25,7 +25,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!eth->netdev[i])
-@@ -3519,7 +3516,7 @@ static void mtk_pending_work(struct work
+@@ -3518,7 +3515,7 @@ static void mtk_pending_work(struct work
  
  	dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
  
diff --git a/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch b/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
index 8bdbfc2927..c91861a8f1 100644
--- a/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
+++ b/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
@@ -16,7 +16,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3257,6 +3257,27 @@ static void mtk_set_mcr_max_rx(struct mt
+@@ -3256,6 +3256,27 @@ static void mtk_set_mcr_max_rx(struct mt
  		mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
  }
  
@@ -44,7 +44,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int mtk_hw_init(struct mtk_eth *eth)
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3296,22 +3317,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3295,22 +3316,9 @@ static int mtk_hw_init(struct mtk_eth *e
  		return 0;
  	}
  
diff --git a/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch b/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
index 712b6a2d3a..6597eb5b74 100644
--- a/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
+++ b/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
@@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3278,7 +3278,54 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3277,7 +3277,54 @@ static void mtk_hw_reset(struct mtk_eth
  			     0x3ffffff);
  }
  
@@ -73,7 +73,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
  		       ETHSYS_DMA_AG_MAP_PPE;
-@@ -3317,7 +3364,12 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3316,7 +3363,12 @@ static int mtk_hw_init(struct mtk_eth *e
  		return 0;
  	}
  
@@ -87,7 +87,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		/* Set FE to PDMAv2 if necessary */
-@@ -3508,7 +3560,7 @@ static void mtk_pending_work(struct work
+@@ -3507,7 +3559,7 @@ static void mtk_pending_work(struct work
  	if (eth->dev->pins)
  		pinctrl_select_state(eth->dev->pins->p,
  				     eth->dev->pins->default_state);
@@ -96,7 +96,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/* restart DMA and enable IRQs */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -4110,7 +4162,7 @@ static int mtk_probe(struct platform_dev
+@@ -4109,7 +4161,7 @@ static int mtk_probe(struct platform_dev
  	eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
  	INIT_WORK(&eth->pending_work, mtk_pending_work);
  
diff --git a/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch b/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
index 9da16ec56c..55ab19f4c8 100644
--- a/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
+++ b/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
@@ -16,7 +16,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2845,14 +2845,29 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2844,14 +2844,29 @@ static void mtk_dma_free(struct mtk_eth
  	kfree(eth->scratch_head);
  }
  
@@ -48,7 +48,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	schedule_work(&eth->pending_work);
  }
  
-@@ -3332,15 +3347,17 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3331,15 +3346,17 @@ static int mtk_hw_init(struct mtk_eth *e
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	int i, val, ret;
  
@@ -72,7 +72,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (eth->ethsys)
  		regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
-@@ -3469,8 +3486,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3468,8 +3485,10 @@ static int mtk_hw_init(struct mtk_eth *e
  	return 0;
  
  err_disable_pm:
@@ -85,7 +85,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	return ret;
  }
-@@ -3532,30 +3551,53 @@ static int mtk_do_ioctl(struct net_devic
+@@ -3531,30 +3550,53 @@ static int mtk_do_ioctl(struct net_devic
  	return -EOPNOTSUPP;
  }
  
@@ -148,7 +148,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (eth->dev->pins)
  		pinctrl_select_state(eth->dev->pins->p,
-@@ -3566,15 +3608,19 @@ static void mtk_pending_work(struct work
+@@ -3565,15 +3607,19 @@ static void mtk_pending_work(struct work
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!test_bit(i, &restart))
  			continue;
diff --git a/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch b/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
index 96ebc87481..d5a7c0eba2 100644
--- a/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
+++ b/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
@@ -49,7 +49,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  };
  
  /* strings used by ethtool */
-@@ -3340,6 +3346,102 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3339,6 +3345,102 @@ static void mtk_hw_warm_reset(struct mtk
  			val, rst_mask);
  }
  
@@ -152,7 +152,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int mtk_hw_init(struct mtk_eth *eth, bool reset)
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3658,6 +3760,7 @@ static int mtk_cleanup(struct mtk_eth *e
+@@ -3657,6 +3759,7 @@ static int mtk_cleanup(struct mtk_eth *e
  	mtk_unreg_dev(eth);
  	mtk_free_dev(eth);
  	cancel_work_sync(&eth->pending_work);
@@ -160,7 +160,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	return 0;
  }
-@@ -4095,6 +4198,7 @@ static int mtk_probe(struct platform_dev
+@@ -4094,6 +4197,7 @@ static int mtk_probe(struct platform_dev
  
  	eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
  	INIT_WORK(&eth->rx_dim.work, mtk_dim_rx);
@@ -168,7 +168,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
  	INIT_WORK(&eth->tx_dim.work, mtk_dim_tx);
-@@ -4297,6 +4401,8 @@ static int mtk_probe(struct platform_dev
+@@ -4296,6 +4400,8 @@ static int mtk_probe(struct platform_dev
  	netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx);
  
  	platform_set_drvdata(pdev, eth);
diff --git a/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch b/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
index da1ce24b8f..c21d094ae8 100644
--- a/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
+++ b/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
@@ -14,7 +14,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3689,6 +3689,11 @@ static void mtk_pending_work(struct work
+@@ -3688,6 +3688,11 @@ static void mtk_pending_work(struct work
  	set_bit(MTK_RESETTING, &eth->state);
  
  	mtk_prepare_for_reset(eth);
@@ -26,7 +26,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -3726,6 +3731,8 @@ static void mtk_pending_work(struct work
+@@ -3725,6 +3730,8 @@ static void mtk_pending_work(struct work
  
  	clear_bit(MTK_RESETTING, &eth->state);
  
diff --git a/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch b/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
index c3b8af0b2b..046a581224 100644
--- a/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
+++ b/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -945,7 +945,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -944,7 +944,7 @@ static int mtk_init_fq_dma(struct mtk_et
  {
  	const struct mtk_soc_data *soc = eth->soc;
  	dma_addr_t phy_ring_tail;
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	dma_addr_t dma_addr;
  	int i;
  
-@@ -2209,19 +2209,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2208,19 +2208,25 @@ static int mtk_tx_alloc(struct mtk_eth *
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	int i, sz = soc->txrx.txd_size;
  	struct mtk_tx_dma_v2 *txd;
@@ -51,7 +51,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		u32 next_ptr = ring->phys + next * sz;
  
  		txd = ring->dma + i * sz;
-@@ -2241,22 +2247,22 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2240,22 +2246,22 @@ static int mtk_tx_alloc(struct mtk_eth *
  	 * descriptors in ring->dma_pdma.
  	 */
  	if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ring->thresh = MAX_SKB_FRAGS;
  
  	/* make sure that all changes to the dma ring are flushed before we
-@@ -2268,14 +2274,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2267,14 +2273,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  		mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
  		mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
  		mtk_w32(eth,
@@ -96,7 +96,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
  		mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
  	}
-@@ -2293,7 +2299,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2292,7 +2298,7 @@ static void mtk_tx_clean(struct mtk_eth
  	int i;
  
  	if (ring->buf) {
@@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
  		kfree(ring->buf);
  		ring->buf = NULL;
-@@ -2301,14 +2307,14 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2300,14 +2306,14 @@ static void mtk_tx_clean(struct mtk_eth
  
  	if (ring->dma) {
  		dma_free_coherent(eth->dma_dev,
@@ -122,7 +122,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  				  ring->dma_pdma, ring->phys_pdma);
  		ring->dma_pdma = NULL;
  	}
-@@ -2833,7 +2839,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2832,7 +2838,7 @@ static void mtk_dma_free(struct mtk_eth
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
  		dma_free_coherent(eth->dma_dev,
diff --git a/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch b/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
index bc794a5c8a..7e879ca1d5 100644
--- a/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
+++ b/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4480,7 +4480,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4479,7 +4479,7 @@ static const struct mtk_soc_data mt7621_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7621_CLKS_BITMAP,
  	.required_pctl = false,
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	.hash_offset = 2,
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
-@@ -4519,7 +4519,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4518,7 +4518,7 @@ static const struct mtk_soc_data mt7623_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
diff --git a/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch b/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
index 48d9b31fef..8ceba7831e 100644
--- a/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
+++ b/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
@@ -139,7 +139,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* Configure duplex */
  	if (duplex == DUPLEX_FULL)
  		mcr |= MAC_MCR_FORCE_DPX;
-@@ -1106,7 +1181,8 @@ static void mtk_tx_set_dma_desc_v1(struc
+@@ -1105,7 +1180,8 @@ static void mtk_tx_set_dma_desc_v1(struc
  
  	WRITE_ONCE(desc->txd1, info->addr);
  
@@ -149,7 +149,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (info->last)
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
-@@ -1140,9 +1216,6 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1139,9 +1215,6 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -159,7 +159,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
-@@ -1186,11 +1259,12 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1185,11 +1258,12 @@ static int mtk_tx_map(struct sk_buff *sk
  		.gso = gso,
  		.csum = skb->ip_summed == CHECKSUM_PARTIAL,
  		.vlan = skb_vlan_tag_present(skb),
@@ -173,7 +173,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct mtk_mac *mac = netdev_priv(dev);
  	struct mtk_eth *eth = mac->hw;
  	const struct mtk_soc_data *soc = eth->soc;
-@@ -1198,8 +1272,10 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1197,8 +1271,10 @@ static int mtk_tx_map(struct sk_buff *sk
  	struct mtk_tx_dma *itxd_pdma, *txd_pdma;
  	struct mtk_tx_buf *itx_buf, *tx_buf;
  	int i, n_desc = 1;
@@ -184,7 +184,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	itxd = ring->next_free;
  	itxd_pdma = qdma_to_pdma(ring, itxd);
  	if (itxd == ring->last_free)
-@@ -1248,7 +1324,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1247,7 +1323,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  			txd_info.size = min_t(unsigned int, frag_size,
  					      soc->txrx.dma_max_len);
@@ -193,7 +193,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
  					!(frag_size - txd_info.size);
  			txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
-@@ -1287,7 +1363,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1286,7 +1362,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			txd_pdma->txd2 |= TX_DMA_LS1;
  	}
  
@@ -202,7 +202,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	skb_tx_timestamp(skb);
  
  	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
-@@ -1299,8 +1375,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1298,8 +1374,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	wmb();
  
  	if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
@@ -212,7 +212,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
  	} else {
  		int next_idx;
-@@ -1369,7 +1444,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1368,7 +1443,7 @@ static void mtk_wake_queue(struct mtk_et
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!eth->netdev[i])
  			continue;
@@ -221,7 +221,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  }
  
-@@ -1393,7 +1468,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1392,7 +1467,7 @@ static netdev_tx_t mtk_start_xmit(struct
  
  	tx_num = mtk_cal_txd_req(eth, skb);
  	if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
@@ -230,7 +230,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		netif_err(eth, tx_queued, dev,
  			  "Tx Ring full when queue awake!\n");
  		spin_unlock(&eth->page_lock);
-@@ -1419,7 +1494,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1418,7 +1493,7 @@ static netdev_tx_t mtk_start_xmit(struct
  		goto drop;
  
  	if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
@@ -239,7 +239,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	spin_unlock(&eth->page_lock);
  
-@@ -1586,10 +1661,12 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1585,10 +1660,12 @@ static int mtk_xdp_submit_frame(struct m
  	struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
  	const struct mtk_soc_data *soc = eth->soc;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
@@ -252,7 +252,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	};
  	int err, index = 0, n_desc = 1, nr_frags;
  	struct mtk_tx_buf *htx_buf, *tx_buf;
-@@ -1639,6 +1716,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1638,6 +1715,7 @@ static int mtk_xdp_submit_frame(struct m
  		memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  		txd_info.size = skb_frag_size(&sinfo->frags[index]);
  		txd_info.last = index + 1 == nr_frags;
@@ -260,7 +260,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		data = skb_frag_address(&sinfo->frags[index]);
  
  		index++;
-@@ -1993,8 +2071,46 @@ rx_done:
+@@ -1992,8 +2070,46 @@ rx_done:
  	return done;
  }
  
@@ -308,7 +308,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
-@@ -2026,12 +2142,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2025,12 +2141,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
  			break;
  
  		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
@@ -323,7 +323,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			budget--;
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2050,7 +2163,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2049,7 +2162,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
  }
  
  static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
@@ -332,7 +332,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct mtk_tx_buf *tx_buf;
-@@ -2068,12 +2181,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
+@@ -2067,12 +2180,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
  			break;
  
  		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
@@ -347,7 +347,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			budget--;
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2095,26 +2204,15 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2094,26 +2203,15 @@ static int mtk_poll_tx(struct mtk_eth *e
  {
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct dim_sample dim_sample = {};
@@ -379,7 +379,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
  			  &dim_sample);
-@@ -2124,7 +2222,7 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2123,7 +2221,7 @@ static int mtk_poll_tx(struct mtk_eth *e
  	    (atomic_read(&ring->free_count) > ring->thresh))
  		mtk_wake_queue(eth);
  
@@ -388,7 +388,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static void mtk_handle_status_irq(struct mtk_eth *eth)
-@@ -2210,6 +2308,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2209,6 +2307,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  	int i, sz = soc->txrx.txd_size;
  	struct mtk_tx_dma_v2 *txd;
  	int ring_size;
@@ -396,7 +396,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
  		ring_size = MTK_QDMA_RING_SIZE;
-@@ -2277,8 +2376,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2276,8 +2375,25 @@ static int mtk_tx_alloc(struct mtk_eth *
  			ring->phys + ((ring_size - 1) * sz),
  			soc->reg_map->qdma.crx_ptr);
  		mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
@@ -424,7 +424,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	} else {
  		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
  		mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
-@@ -2963,7 +3079,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2962,7 +3078,7 @@ static int mtk_start_dma(struct mtk_eth
  		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
  			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
  			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
@@ -433,7 +433,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		else
  			val |= MTK_RX_BT_32DWORDS;
  		mtk_w32(eth, val, reg_map->qdma.glo_cfg);
-@@ -3009,6 +3125,45 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3008,6 +3124,45 @@ static void mtk_gdm_config(struct mtk_et
  	mtk_w32(eth, 0, MTK_RST_GL);
  }
  
@@ -479,7 +479,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int mtk_open(struct net_device *dev)
  {
  	struct mtk_mac *mac = netdev_priv(dev);
-@@ -3051,7 +3206,8 @@ static int mtk_open(struct net_device *d
+@@ -3050,7 +3205,8 @@ static int mtk_open(struct net_device *d
  		refcount_inc(&eth->dma_refcnt);
  
  	phylink_start(mac->phylink);
@@ -489,7 +489,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3760,8 +3916,12 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3759,8 +3915,12 @@ static int mtk_unreg_dev(struct mtk_eth
  	int i;
  
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
@@ -502,7 +502,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		unregister_netdev(eth->netdev[i]);
  	}
  
-@@ -3978,6 +4138,23 @@ static int mtk_set_rxnfc(struct net_devi
+@@ -3977,6 +4137,23 @@ static int mtk_set_rxnfc(struct net_devi
  	return ret;
  }
  
@@ -526,7 +526,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static const struct ethtool_ops mtk_ethtool_ops = {
  	.get_link_ksettings	= mtk_get_link_ksettings,
  	.set_link_ksettings	= mtk_set_link_ksettings,
-@@ -4012,6 +4189,7 @@ static const struct net_device_ops mtk_n
+@@ -4011,6 +4188,7 @@ static const struct net_device_ops mtk_n
  	.ndo_setup_tc		= mtk_eth_setup_tc,
  	.ndo_bpf		= mtk_xdp,
  	.ndo_xdp_xmit		= mtk_xdp_xmit,
@@ -534,7 +534,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  };
  
  static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
-@@ -4021,6 +4199,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4020,6 +4198,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	struct phylink *phylink;
  	struct mtk_mac *mac;
  	int id, err;
@@ -542,7 +542,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (!_id) {
  		dev_err(eth->dev, "missing mac id\n");
-@@ -4038,7 +4217,10 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4037,7 +4216,10 @@ static int mtk_add_mac(struct mtk_eth *e
  		return -EINVAL;
  	}
  
@@ -554,7 +554,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (!eth->netdev[id]) {
  		dev_err(eth->dev, "alloc_etherdev failed\n");
  		return -ENOMEM;
-@@ -4146,6 +4328,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4145,6 +4327,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	else
  		eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
  
diff --git a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
index b45a33c4cb..b8e3452f30 100644
--- a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
+++ b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
@@ -22,7 +22,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  #include "mtk_eth_soc.h"
  #include "mtk_wed.h"
-@@ -2022,16 +2023,22 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2021,16 +2022,22 @@ static int mtk_poll_rx(struct napi_struc
  						htons(RX_DMA_VPID(trxd.rxd4)),
  						RX_DMA_VID(trxd.rxd4));
  			} else if (trxd.rxd2 & RX_DMA_VTAG) {
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		}
  
  		skb_record_rx_queue(skb, 0);
-@@ -2859,15 +2866,30 @@ static netdev_features_t mtk_fix_feature
+@@ -2858,15 +2865,30 @@ static netdev_features_t mtk_fix_feature
  
  static int mtk_set_features(struct net_device *dev, netdev_features_t features)
  {
@@ -88,7 +88,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  /* wait for DMA to finish whatever it is doing before we start using it again */
-@@ -3164,11 +3186,45 @@ found:
+@@ -3163,11 +3185,45 @@ found:
  	return NOTIFY_DONE;
  }
  
@@ -135,7 +135,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
-@@ -3689,6 +3745,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3688,6 +3744,10 @@ static int mtk_hw_init(struct mtk_eth *e
  	 */
  	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
  	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
@@ -146,7 +146,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* Enable RX VLan Offloading */
  	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
-@@ -3908,6 +3968,12 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3907,6 +3967,12 @@ static int mtk_free_dev(struct mtk_eth *
  		free_netdev(eth->netdev[i]);
  	}
  
diff --git a/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch b/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
index 42c745d02f..a88df2b8e3 100644
--- a/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
+++ b/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3202,7 +3202,8 @@ static int mtk_open(struct net_device *d
+@@ -3201,7 +3201,8 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
  			struct metadata_dst *md_dst = eth->dsa_meta[i];
  
-@@ -3219,7 +3220,8 @@ static int mtk_open(struct net_device *d
+@@ -3218,7 +3219,8 @@ static int mtk_open(struct net_device *d
  		}
  	} else {
  		/* Hardware special tag parsing needs to be disabled if at least
diff --git a/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch b/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
index 39874c9d1c..8da728b9e9 100644
--- a/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
+++ b/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
@@ -23,7 +23,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3137,7 +3137,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3136,7 +3136,7 @@ static void mtk_gdm_config(struct mtk_et
  
  		val |= config;
  
@@ -32,7 +32,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			val |= MTK_GDMA_SPECIAL_TAG;
  
  		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3202,8 +3202,7 @@ static int mtk_open(struct net_device *d
+@@ -3201,8 +3201,7 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -42,7 +42,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
  			struct metadata_dst *md_dst = eth->dsa_meta[i];
  
-@@ -3220,8 +3219,7 @@ static int mtk_open(struct net_device *d
+@@ -3219,8 +3218,7 @@ static int mtk_open(struct net_device *d
  		}
  	} else {
  		/* Hardware special tag parsing needs to be disabled if at least
diff --git a/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch b/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
index a9879ebfa9..51cd572ab2 100644
--- a/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
+++ b/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
@@ -77,7 +77,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1878,7 +1878,9 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1877,7 +1877,9 @@ static int mtk_poll_rx(struct napi_struc
  
  	while (done < budget) {
  		unsigned int pktlen, *rxdcsum;
@@ -87,7 +87,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		dma_addr_t dma_addr;
  		u32 hash, reason;
  		int mac = 0;
-@@ -2018,27 +2020,29 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2017,27 +2019,29 @@ static int mtk_poll_rx(struct napi_struc
  
  		if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
  			if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
diff --git a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
index 089f25545d..a1247218b0 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
@@ -57,7 +57,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		mtk_eth_path_name(path), __func__, updated);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4804,6 +4804,26 @@ static const struct mtk_soc_data mt7629_
+@@ -4803,6 +4803,26 @@ static const struct mtk_soc_data mt7629_
  	},
  };
  
@@ -84,7 +84,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static const struct mtk_soc_data mt7986_data = {
  	.reg_map = &mt7986_reg_map,
  	.ana_rgc3 = 0x128,
-@@ -4846,6 +4866,7 @@ const struct of_device_id of_mtk_match[]
+@@ -4845,6 +4865,7 @@ const struct of_device_id of_mtk_match[]
  	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
  	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
  	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
diff --git a/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch b/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
index ea20bd87f7..1cb1f40538 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
@@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -745,8 +745,10 @@ static const struct phylink_mac_ops mtk_
+@@ -744,8 +744,10 @@ static const struct phylink_mac_ops mtk_
  
  static int mtk_mdio_init(struct mtk_eth *eth)
  {
@@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
  	if (!mii_np) {
-@@ -773,6 +775,25 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -772,6 +774,25 @@ static int mtk_mdio_init(struct mtk_eth
  	eth->mii_bus->parent = eth->dev;
  
  	snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
diff --git a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
index 15295959c1..110944658d 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
@@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	return NULL;
-@@ -4017,8 +4018,17 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -4016,8 +4017,17 @@ static int mtk_unreg_dev(struct mtk_eth
  	return 0;
  }
  
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	mtk_unreg_dev(eth);
  	mtk_free_dev(eth);
  	cancel_work_sync(&eth->pending_work);
-@@ -4458,6 +4468,36 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4457,6 +4467,36 @@ void mtk_eth_set_dma_device(struct mtk_e
  	rtnl_unlock();
  }
  
@@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mtk_probe(struct platform_device *pdev)
  {
  	struct resource *res = NULL;
-@@ -4521,13 +4561,7 @@ static int mtk_probe(struct platform_dev
+@@ -4520,13 +4560,7 @@ static int mtk_probe(struct platform_dev
  	}
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
@@ -130,7 +130,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (err)
  			return err;
-@@ -4538,14 +4572,17 @@ static int mtk_probe(struct platform_dev
+@@ -4537,14 +4571,17 @@ static int mtk_probe(struct platform_dev
  							    "mediatek,pctl");
  		if (IS_ERR(eth->pctl)) {
  			dev_err(&pdev->dev, "no pctl regmap found\n");
@@ -151,7 +151,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	if (eth->soc->offload_version) {
-@@ -4704,6 +4741,8 @@ err_deinit_hw:
+@@ -4703,6 +4740,8 @@ err_deinit_hw:
  	mtk_hw_deinit(eth);
  err_wed_exit:
  	mtk_wed_exit();
diff --git a/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
index df8d642794..93eaffa19e 100644
--- a/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
+++ b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4692,8 +4692,8 @@ static int mtk_probe(struct platform_dev
+@@ -4691,8 +4691,8 @@ static int mtk_probe(struct platform_dev
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
  
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			if (!eth->ppe[i]) {
  				err = -ENOMEM;
  				goto err_deinit_ppe;
-@@ -4817,6 +4817,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4816,6 +4816,7 @@ static const struct mtk_soc_data mt7622_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 2,
@@ -46,7 +46,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4854,6 +4855,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4853,6 +4854,7 @@ static const struct mtk_soc_data mt7629_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
@@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4874,6 +4876,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4873,6 +4875,7 @@ static const struct mtk_soc_data mt7981_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4894,6 +4897,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4893,6 +4896,7 @@ static const struct mtk_soc_data mt7986_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
diff --git a/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch b/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
index d6309964c3..217e517c3a 100644
--- a/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
+++ b/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
@@ -17,7 +17,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1898,9 +1898,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1897,9 +1897,7 @@ static int mtk_poll_rx(struct napi_struc
  
  	while (done < budget) {
  		unsigned int pktlen, *rxdcsum;
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		dma_addr_t dma_addr;
  		u32 hash, reason;
  		int mac = 0;
-@@ -2035,36 +2033,21 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2034,36 +2032,21 @@ static int mtk_poll_rx(struct napi_struc
  			skb_checksum_none_assert(skb);
  		skb->protocol = eth_type_trans(skb, netdev);
  
@@ -70,7 +70,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		skb_record_rx_queue(skb, 0);
  		napi_gro_receive(napi, skb);
  
-@@ -2890,29 +2873,11 @@ static netdev_features_t mtk_fix_feature
+@@ -2889,29 +2872,11 @@ static netdev_features_t mtk_fix_feature
  
  static int mtk_set_features(struct net_device *dev, netdev_features_t features)
  {
@@ -100,7 +100,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3226,30 +3191,6 @@ static int mtk_open(struct net_device *d
+@@ -3225,30 +3190,6 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -131,7 +131,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
  		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3288,6 +3229,35 @@ static int mtk_open(struct net_device *d
+@@ -3287,6 +3228,35 @@ static int mtk_open(struct net_device *d
  	phylink_start(mac->phylink);
  	netif_tx_start_all_queues(dev);
  
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3772,10 +3742,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3771,10 +3741,9 @@ static int mtk_hw_init(struct mtk_eth *e
  	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
  		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
@@ -180,7 +180,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* set interrupt delays based on current Net DIM sample */
  	mtk_dim_rx(&eth->rx_dim.work);
-@@ -4415,7 +4384,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4414,7 +4383,7 @@ static int mtk_add_mac(struct mtk_eth *e
  		eth->netdev[id]->hw_features |= NETIF_F_LRO;
  
  	eth->netdev[id]->vlan_features = eth->soc->hw_features &
diff --git a/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
index a0b9b6a299..d7d1c08fce 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
@@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4766,7 +4766,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4765,7 +4765,7 @@ static const struct mtk_soc_data mt7621_
  	.required_pctl = false,
  	.offload_version = 1,
  	.hash_offset = 2,
@@ -26,7 +26,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4787,7 +4787,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4786,7 +4786,7 @@ static const struct mtk_soc_data mt7622_
  	.offload_version = 2,
  	.hash_offset = 2,
  	.has_accounting = true,
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4806,7 +4806,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4805,7 +4805,7 @@ static const struct mtk_soc_data mt7623_
  	.required_pctl = true,
  	.offload_version = 1,
  	.hash_offset = 2,
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4844,8 +4844,8 @@ static const struct mtk_soc_data mt7981_
+@@ -4843,8 +4843,8 @@ static const struct mtk_soc_data mt7981_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 4,
@@ -54,7 +54,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4865,8 +4865,8 @@ static const struct mtk_soc_data mt7986_
+@@ -4864,8 +4864,8 @@ static const struct mtk_soc_data mt7986_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 4,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
index 8914e8da96..fb54f404b2 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
@@ -95,7 +95,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  				/* mt7623_pad_clk_setup */
  				for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
-@@ -4343,13 +4315,19 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4342,13 +4314,19 @@ static int mtk_add_mac(struct mtk_eth *e
  	mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
  		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
  
@@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
  		__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -4807,6 +4785,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4806,6 +4784,7 @@ static const struct mtk_soc_data mt7623_
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
index 351568f187..293066fa9a 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
@@ -62,15 +62,15 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
  			      phy_interface_t interface)
  {
-@@ -709,7 +677,6 @@ static void mtk_mac_link_up(struct phyli
+@@ -708,7 +676,6 @@ static void mtk_mac_link_up(struct phyli
+ 
  static const struct phylink_mac_ops mtk_phylink_ops = {
- 	.validate = phylink_generic_validate,
  	.mac_select_pcs = mtk_mac_select_pcs,
 -	.mac_pcs_get_state = mtk_mac_pcs_get_state,
  	.mac_config = mtk_mac_config,
  	.mac_finish = mtk_mac_finish,
  	.mac_link_down = mtk_mac_link_down,
-@@ -4310,8 +4277,6 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4309,8 +4276,6 @@ static int mtk_add_mac(struct mtk_eth *e
  
  	mac->phylink_config.dev = &eth->netdev[id]->dev;
  	mac->phylink_config.type = PHYLINK_NETDEV;
diff --git a/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
index f479522339..25c87b0415 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
@@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
  
  	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-@@ -956,7 +956,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -955,7 +955,7 @@ static bool mtk_rx_get_desc(struct mtk_e
  	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
  	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
  	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
@@ -41,7 +41,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
  		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
  	}
-@@ -1014,7 +1014,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1013,7 +1013,7 @@ static int mtk_init_fq_dma(struct mtk_et
  
  		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
  		txd->txd4 = 0;
@@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			txd->txd5 = 0;
  			txd->txd6 = 0;
  			txd->txd7 = 0;
-@@ -1205,7 +1205,7 @@ static void mtk_tx_set_dma_desc(struct n
+@@ -1204,7 +1204,7 @@ static void mtk_tx_set_dma_desc(struct n
  	struct mtk_mac *mac = netdev_priv(dev);
  	struct mtk_eth *eth = mac->hw;
  
@@ -59,7 +59,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		mtk_tx_set_dma_desc_v2(dev, txd, info);
  	else
  		mtk_tx_set_dma_desc_v1(dev, txd, info);
-@@ -1512,7 +1512,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1511,7 +1511,7 @@ static void mtk_update_rx_cpu_idx(struct
  
  static bool mtk_page_pool_enabled(struct mtk_eth *eth)
  {
@@ -68,7 +68,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
-@@ -1854,7 +1854,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1853,7 +1853,7 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -77,7 +77,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
  		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1949,7 +1949,7 @@ static int mtk_poll_rx(struct napi_struc
  		skb->dev = netdev;
  		bytes += skb->len;
  
@@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
  			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
  			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -1975,8 +1975,8 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1974,8 +1974,8 @@ static int mtk_poll_rx(struct napi_struc
  		/* When using VLAN untagging in combination with DSA, the
  		 * hardware treats the MTK special tag as a VLAN and untags it.
  		 */
@@ -97,7 +97,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
  
  			if (port < ARRAY_SIZE(eth->dsa_meta) &&
-@@ -2286,7 +2286,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2285,7 +2285,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  		txd->txd2 = next_ptr;
  		txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
  		txd->txd4 = 0;
@@ -106,7 +106,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			txd->txd5 = 0;
  			txd->txd6 = 0;
  			txd->txd7 = 0;
-@@ -2339,14 +2339,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2338,14 +2338,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
  			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
  			      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
@@ -123,7 +123,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
  	} else {
  		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
-@@ -2475,7 +2475,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2474,7 +2474,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
@@ -132,7 +132,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			rxd->rxd5 = 0;
  			rxd->rxd6 = 0;
  			rxd->rxd7 = 0;
-@@ -3026,7 +3026,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -3025,7 +3025,7 @@ static int mtk_start_dma(struct mtk_eth
  		       MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
  		       MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
  
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
  			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
  			       MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
-@@ -3168,7 +3168,7 @@ static int mtk_open(struct net_device *d
+@@ -3167,7 +3167,7 @@ static int mtk_open(struct net_device *d
  	phylink_start(mac->phylink);
  	netif_tx_start_all_queues(dev);
  
@@ -150,7 +150,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		return 0;
  
  	if (mtk_uses_dsa(dev) && !eth->prog) {
-@@ -3433,7 +3433,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3432,7 +3432,7 @@ static void mtk_hw_reset(struct mtk_eth
  {
  	u32 val;
  
@@ -159,7 +159,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  		val = RSTCTRL_PPE0_V2;
  	} else {
-@@ -3445,7 +3445,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3444,7 +3444,7 @@ static void mtk_hw_reset(struct mtk_eth
  
  	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  
@@ -168,7 +168,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  			     0x3ffffff);
  }
-@@ -3471,7 +3471,7 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3470,7 +3470,7 @@ static void mtk_hw_warm_reset(struct mtk
  		return;
  	}
  
@@ -177,7 +177,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
  	else
  		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
-@@ -3641,7 +3641,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3640,7 +3640,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	else
  		mtk_hw_reset(eth);
  
@@ -186,7 +186,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* Set FE to PDMAv2 if necessary */
  		val = mtk_r32(eth, MTK_FE_GLO_MISC);
  		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -3678,7 +3678,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3677,7 +3677,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	 */
  	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
  	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
@@ -195,7 +195,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
  		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
  
-@@ -3700,7 +3700,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3699,7 +3699,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
@@ -204,7 +204,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4489,7 +4489,7 @@ static int mtk_probe(struct platform_dev
+@@ -4488,7 +4488,7 @@ static int mtk_probe(struct platform_dev
  		}
  	}
  
@@ -213,7 +213,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  		if (!res) {
  			err = -EINVAL;
-@@ -4597,9 +4597,8 @@ static int mtk_probe(struct platform_dev
+@@ -4596,9 +4596,8 @@ static int mtk_probe(struct platform_dev
  	}
  
  	if (eth->soc->offload_version) {
@@ -224,7 +224,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
-@@ -4691,6 +4690,7 @@ static const struct mtk_soc_data mt2701_
+@@ -4690,6 +4689,7 @@ static const struct mtk_soc_data mt2701_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
@@ -232,7 +232,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4707,6 +4707,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4706,6 +4706,7 @@ static const struct mtk_soc_data mt7621_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7621_CLKS_BITMAP,
  	.required_pctl = false,
@@ -240,7 +240,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4727,6 +4728,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4726,6 +4727,7 @@ static const struct mtk_soc_data mt7622_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7622_CLKS_BITMAP,
  	.required_pctl = false,
@@ -248,7 +248,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 2,
  	.has_accounting = true,
-@@ -4747,6 +4749,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4746,6 +4748,7 @@ static const struct mtk_soc_data mt7623_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
@@ -256,7 +256,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4769,6 +4772,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4768,6 +4771,7 @@ static const struct mtk_soc_data mt7629_
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
  	.has_accounting = true,
@@ -264,7 +264,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4786,6 +4790,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4785,6 +4789,7 @@ static const struct mtk_soc_data mt7981_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7981_CLKS_BITMAP,
  	.required_pctl = false,
@@ -272,7 +272,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 4,
  	.has_accounting = true,
-@@ -4807,6 +4812,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4806,6 +4811,7 @@ static const struct mtk_soc_data mt7986_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7986_CLKS_BITMAP,
  	.required_pctl = false,
@@ -280,7 +280,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 4,
  	.has_accounting = true,
-@@ -4827,6 +4833,7 @@ static const struct mtk_soc_data rt5350_
+@@ -4826,6 +4832,7 @@ static const struct mtk_soc_data rt5350_
  	.hw_features = MTK_HW_FEATURES_MT7628,
  	.required_clks = MT7628_CLKS_BITMAP,
  	.required_pctl = false,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
index 5ac9d61ab4..8071658313 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -882,7 +882,7 @@ static void mtk_stats_update(struct mtk_
+@@ -881,7 +881,7 @@ static void mtk_stats_update(struct mtk_
  {
  	int i;
  
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->mac[i] || !eth->mac[i]->hw_stats)
  			continue;
  		if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
-@@ -1387,7 +1387,7 @@ static int mtk_queue_stopped(struct mtk_
+@@ -1386,7 +1386,7 @@ static int mtk_queue_stopped(struct mtk_
  {
  	int i;
  
@@ -35,7 +35,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		if (netif_queue_stopped(eth->netdev[i]))
-@@ -1401,7 +1401,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1400,7 +1400,7 @@ static void mtk_wake_queue(struct mtk_et
  {
  	int i;
  
@@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		netif_tx_wake_all_queues(eth->netdev[i]);
-@@ -1860,7 +1860,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1859,7 +1859,7 @@ static int mtk_poll_rx(struct napi_struc
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
  			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
  
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			     !eth->netdev[mac]))
  			goto release_desc;
  
-@@ -2900,7 +2900,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2899,7 +2899,7 @@ static void mtk_dma_free(struct mtk_eth
  	const struct mtk_soc_data *soc = eth->soc;
  	int i;
  
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
-@@ -3054,8 +3054,13 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3053,8 +3053,13 @@ static void mtk_gdm_config(struct mtk_et
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		return;
  
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		/* default setup the forward port to send frame to PDMA */
  		val &= ~0xffff;
-@@ -3065,7 +3070,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3064,7 +3069,7 @@ static void mtk_gdm_config(struct mtk_et
  
  		val |= config;
  
@@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			val |= MTK_GDMA_SPECIAL_TAG;
  
  		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3662,15 +3667,15 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3661,15 +3666,15 @@ static int mtk_hw_init(struct mtk_eth *e
  	 * up with the more appropriate value when mtk_mac_config call is being
  	 * invoked.
  	 */
@@ -109,7 +109,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	/* Indicates CDM to parse the MTK special tag from CPU
-@@ -3850,7 +3855,7 @@ static void mtk_pending_work(struct work
+@@ -3849,7 +3854,7 @@ static void mtk_pending_work(struct work
  	mtk_prepare_for_reset(eth);
  
  	/* stop all devices to make sure that dma is properly shut down */
@@ -118,7 +118,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
  			continue;
  
-@@ -3866,8 +3871,8 @@ static void mtk_pending_work(struct work
+@@ -3865,8 +3870,8 @@ static void mtk_pending_work(struct work
  	mtk_hw_init(eth, true);
  
  	/* restart DMA and enable IRQs */
@@ -129,7 +129,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			continue;
  
  		if (mtk_open(eth->netdev[i])) {
-@@ -3894,7 +3899,7 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3893,7 +3898,7 @@ static int mtk_free_dev(struct mtk_eth *
  {
  	int i;
  
@@ -138,7 +138,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		free_netdev(eth->netdev[i]);
-@@ -3913,7 +3918,7 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3912,7 +3917,7 @@ static int mtk_unreg_dev(struct mtk_eth
  {
  	int i;
  
@@ -147,7 +147,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct mtk_mac *mac;
  		if (!eth->netdev[i])
  			continue;
-@@ -4214,7 +4219,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4213,7 +4218,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  
  	id = be32_to_cpup(_id);
@@ -156,7 +156,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev_err(eth->dev, "%d is not a valid mac id\n", id);
  		return -EINVAL;
  	}
-@@ -4359,7 +4364,7 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4358,7 +4363,7 @@ void mtk_eth_set_dma_device(struct mtk_e
  
  	rtnl_lock();
  
@@ -165,7 +165,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev = eth->netdev[i];
  
  		if (!dev || !(dev->flags & IFF_UP))
-@@ -4665,7 +4670,7 @@ static int mtk_remove(struct platform_de
+@@ -4664,7 +4669,7 @@ static int mtk_remove(struct platform_de
  	int i;
  
  	/* stop all devices to make sure that dma is properly shut down */
diff --git a/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
index bf6ef4c137..1a9b31f526 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -862,17 +862,32 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -861,17 +861,32 @@ void mtk_stats_update_mac(struct mtk_mac
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
  		hw_stats->rx_flow_control_packets +=
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	u64_stats_update_end(&hw_stats->syncp);
-@@ -1176,7 +1191,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1175,7 +1190,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -74,7 +74,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -1187,6 +1205,8 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1186,6 +1204,8 @@ static void mtk_tx_set_dma_desc_v2(struc
  		/* tx checksum offload */
  		if (info->csum)
  			data |= TX_DMA_CHKSUM_V2;
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  	WRITE_ONCE(desc->txd5, data);
  
-@@ -1252,8 +1272,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1251,8 +1271,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	mtk_tx_set_dma_desc(dev, itxd, &txd_info);
  
  	itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
@@ -93,7 +93,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
  		     k++);
  
-@@ -1301,8 +1320,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1300,8 +1319,7 @@ static int mtk_tx_map(struct sk_buff *sk
  				memset(tx_buf, 0, sizeof(*tx_buf));
  			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  			tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
@@ -103,7 +103,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
  				     txd_info.size, k++);
-@@ -1604,7 +1622,7 @@ static int mtk_xdp_frame_map(struct mtk_
+@@ -1603,7 +1621,7 @@ static int mtk_xdp_frame_map(struct mtk_
  	}
  	mtk_tx_set_dma_desc(dev, txd, txd_info);
  
@@ -112,7 +112,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
  	tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  
-@@ -1854,11 +1872,24 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1853,11 +1871,24 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
  			     !eth->netdev[mac]))
-@@ -2080,7 +2111,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2079,7 +2110,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
  
  	while ((cpu != dma) && budget) {
  		u32 next_cpu = desc->txd2;
@@ -149,7 +149,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
  		if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
-@@ -2088,15 +2118,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2087,15 +2117,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
  
  		tx_buf = mtk_desc_to_tx_buf(ring, desc,
  					    eth->soc->txrx.txd_size);
@@ -167,7 +167,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			budget--;
  		}
-@@ -3705,7 +3733,24 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3704,7 +3732,24 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
@@ -193,7 +193,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4267,7 +4312,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4266,7 +4311,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  	spin_lock_init(&mac->hw_stats->stats_lock);
  	u64_stats_init(&mac->hw_stats->syncp);
diff --git a/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
index 97a2992cfe..8c24321dd4 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
@@ -219,7 +219,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return;
  
  err_phy:
-@@ -726,11 +842,15 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -725,11 +841,15 @@ static int mtk_mdio_init(struct mtk_eth
  	}
  	divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
  
@@ -239,7 +239,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
  
-@@ -1191,10 +1311,19 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1190,10 +1310,19 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -263,7 +263,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -4361,6 +4490,17 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4360,6 +4489,17 @@ static int mtk_add_mac(struct mtk_eth *e
  			  mac->phylink_config.supported_interfaces);
  	}
  
@@ -281,7 +281,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4881,6 +5021,24 @@ static const struct mtk_soc_data mt7986_
+@@ -4880,6 +5020,24 @@ static const struct mtk_soc_data mt7986_
  	},
  };
  
@@ -306,7 +306,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static const struct mtk_soc_data rt5350_data = {
  	.reg_map = &mt7628_reg_map,
  	.caps = MT7628_CAPS,
-@@ -4899,14 +5057,15 @@ static const struct mtk_soc_data rt5350_
+@@ -4898,14 +5056,15 @@ static const struct mtk_soc_data rt5350_
  };
  
  const struct of_device_id of_mtk_match[] = {
diff --git a/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
index 62c38c7137..3dc4662d1a 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1659,7 +1659,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1658,7 +1658,7 @@ static void mtk_update_rx_cpu_idx(struct
  
  static bool mtk_page_pool_enabled(struct mtk_eth *eth)
  {
diff --git a/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
index b175aedf0c..32f26d7d27 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5029,6 +5029,9 @@ static const struct mtk_soc_data mt7988_
+@@ -5028,6 +5028,9 @@ static const struct mtk_soc_data mt7988_
  	.required_clks = MT7988_CLKS_BITMAP,
  	.required_pctl = false,
  	.version = 3,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
index bf0a39b9d3..876bdd5dd3 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5031,6 +5031,7 @@ static const struct mtk_soc_data mt7988_
+@@ -5030,6 +5030,7 @@ static const struct mtk_soc_data mt7988_
  	.version = 3,
  	.offload_version = 2,
  	.hash_offset = 4,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
index a4ff5a292e..05a18364d6 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3595,19 +3595,34 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3594,19 +3594,34 @@ static void mtk_hw_reset(struct mtk_eth
  {
  	u32 val;
  
@@ -56,7 +56,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  			     0x3ffffff);
  }
-@@ -3633,13 +3648,21 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3632,13 +3647,21 @@ static void mtk_hw_warm_reset(struct mtk
  		return;
  	}
  
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
  
-@@ -3991,11 +4014,17 @@ static void mtk_prepare_for_reset(struct
+@@ -3990,11 +4013,17 @@ static void mtk_prepare_for_reset(struct
  	u32 val;
  	int i;
  
@@ -106,7 +106,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* adjust PPE configurations to prepare for reset */
  	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
-@@ -4056,11 +4085,18 @@ static void mtk_pending_work(struct work
+@@ -4055,11 +4084,18 @@ static void mtk_pending_work(struct work
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
index 872262b0f8..74ac8dc898 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1119,10 +1119,13 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1118,10 +1118,13 @@ static int mtk_init_fq_dma(struct mtk_et
  	dma_addr_t dma_addr;
  	int i;
  
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (unlikely(!eth->scratch_ring))
  		return -ENOMEM;
  
-@@ -2430,8 +2433,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2429,8 +2432,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  	if (!ring->buf)
  		goto no_tx_mem;
  
@@ -55,7 +55,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (!ring->dma)
  		goto no_tx_mem;
  
-@@ -2530,8 +2539,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2529,8 +2538,7 @@ static void mtk_tx_clean(struct mtk_eth
  		kfree(ring->buf);
  		ring->buf = NULL;
  	}
@@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  ring->dma_size * soc->txrx.txd_size,
  				  ring->dma, ring->phys);
-@@ -2550,9 +2558,14 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2549,9 +2557,14 @@ static int mtk_rx_alloc(struct mtk_eth *
  {
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	struct mtk_rx_ring *ring;
@@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (rx_flag == MTK_RX_FLAGS_QDMA) {
  		if (ring_no)
  			return -EINVAL;
-@@ -2587,9 +2600,20 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2586,9 +2599,20 @@ static int mtk_rx_alloc(struct mtk_eth *
  		ring->page_pool = pp;
  	}
  
@@ -105,7 +105,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (!ring->dma)
  		return -ENOMEM;
  
-@@ -2674,7 +2698,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2673,7 +2697,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  	return 0;
  }
  
@@ -114,7 +114,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	int i;
  
-@@ -2697,7 +2721,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2696,7 +2720,7 @@ static void mtk_rx_clean(struct mtk_eth
  		ring->data = NULL;
  	}
  
@@ -123,7 +123,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  ring->dma_size * eth->soc->txrx.rxd_size,
  				  ring->dma, ring->phys);
-@@ -3060,7 +3084,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3059,7 +3083,7 @@ static void mtk_dma_free(struct mtk_eth
  	for (i = 0; i < MTK_MAX_DEVS; i++)
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
@@ -132,7 +132,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
  				  eth->scratch_ring, eth->phy_scratch_ring);
-@@ -3068,13 +3092,13 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3067,13 +3091,13 @@ static void mtk_dma_free(struct mtk_eth
  		eth->phy_scratch_ring = 0;
  	}
  	mtk_tx_clean(eth);
@@ -149,7 +149,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	kfree(eth->scratch_head);
-@@ -4642,7 +4666,7 @@ static int mtk_sgmii_init(struct mtk_eth
+@@ -4641,7 +4665,7 @@ static int mtk_sgmii_init(struct mtk_eth
  
  static int mtk_probe(struct platform_device *pdev)
  {
@@ -158,7 +158,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct device_node *mac_np;
  	struct mtk_eth *eth;
  	int err, i;
-@@ -4662,6 +4686,20 @@ static int mtk_probe(struct platform_dev
+@@ -4661,6 +4685,20 @@ static int mtk_probe(struct platform_dev
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		eth->ip_align = NET_IP_ALIGN;
  
@@ -179,7 +179,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	spin_lock_init(&eth->page_lock);
  	spin_lock_init(&eth->tx_irq_lock);
  	spin_lock_init(&eth->rx_irq_lock);
-@@ -4725,6 +4763,18 @@ static int mtk_probe(struct platform_dev
+@@ -4724,6 +4762,18 @@ static int mtk_probe(struct platform_dev
  			err = -EINVAL;
  			goto err_destroy_sgmii;
  		}
diff --git a/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
index 9266c33f82..1584dfd07c 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
@@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1312,6 +1312,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1311,6 +1311,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  	data = TX_DMA_PLEN0(info->size);
  	if (info->last)
  		data |= TX_DMA_LS0;
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	WRITE_ONCE(desc->txd3, data);
  
  	 /* set forward port */
-@@ -1981,6 +1985,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1980,6 +1984,7 @@ static int mtk_poll_rx(struct napi_struc
  	bool xdp_flush = false;
  	int idx;
  	struct sk_buff *skb;
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u8 *data, *new_data;
  	struct mtk_rx_dma_v2 *rxd, trxd;
  	int done = 0, bytes = 0;
-@@ -2096,7 +2101,10 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2095,7 +2100,10 @@ static int mtk_poll_rx(struct napi_struc
  				goto release_desc;
  			}
  
@@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					 ring->buf_size, DMA_FROM_DEVICE);
  
  			skb = build_skb(data, ring->frag_size);
-@@ -2162,6 +2170,9 @@ release_desc:
+@@ -2161,6 +2169,9 @@ release_desc:
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
@@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		ring->calc_idx = idx;
  		done++;
  	}
-@@ -2654,6 +2665,9 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2653,6 +2664,9 @@ static int mtk_rx_alloc(struct mtk_eth *
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
@@ -70,7 +70,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
  		if (mtk_is_netsys_v2_or_greater(eth)) {
-@@ -2700,6 +2714,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2699,6 +2713,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
  {
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int i;
  
  	if (ring->data && ring->dma) {
-@@ -2713,7 +2728,10 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2712,7 +2727,10 @@ static void mtk_rx_clean(struct mtk_eth
  			if (!rxd->rxd1)
  				continue;
  
@@ -90,7 +90,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					 ring->buf_size, DMA_FROM_DEVICE);
  			mtk_rx_put_buff(ring, ring->data[i], false);
  		}
-@@ -4700,6 +4718,14 @@ static int mtk_probe(struct platform_dev
+@@ -4699,6 +4717,14 @@ static int mtk_probe(struct platform_dev
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch b/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
index 697c2db145..5b27458eb8 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1989,11 +1989,11 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1988,11 +1988,11 @@ static int mtk_poll_rx(struct napi_struc
  	u8 *data, *new_data;
  	struct mtk_rx_dma_v2 *rxd, trxd;
  	int done = 0, bytes = 0;
@@ -32,7 +32,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		u32 hash, reason;
  		int mac = 0;
  
-@@ -2170,7 +2170,8 @@ release_desc:
+@@ -2169,7 +2169,8 @@ release_desc:
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
diff --git a/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch b/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
index 07c087260c..aa0d730bc8 100644
--- a/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
+++ b/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
@@ -46,7 +46,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2975,13 +2975,25 @@ static void stmmac_tx_timer_arm(struct s
+@@ -2974,13 +2974,25 @@ static void stmmac_tx_timer_arm(struct s
  {
  	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
  	u32 tx_coal_timer = priv->tx_coal_timer[queue];
diff --git a/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
index e94a2ca819..4e9e951598 100644
--- a/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
+++ b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
@@ -18,7 +18,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2528,9 +2528,13 @@ static void stmmac_bump_dma_threshold(st
+@@ -2527,9 +2527,13 @@ static void stmmac_bump_dma_threshold(st
   * @priv: driver private structure
   * @budget: napi budget limiting this functions packet handling
   * @queue: TX queue index
@@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
  	unsigned int bytes_compl = 0, pkts_compl = 0;
-@@ -2693,7 +2697,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2692,7 +2696,7 @@ static int stmmac_tx_clean(struct stmmac
  
  	/* We still have pending packets, let's call for a new scheduling */
  	if (tx_q->dirty_tx != tx_q->cur_tx)
@@ -42,7 +42,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	__netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
  
-@@ -5486,12 +5490,13 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5485,12 +5489,13 @@ static int stmmac_napi_poll_tx(struct na
  	struct stmmac_channel *ch =
  		container_of(napi, struct stmmac_channel, tx_napi);
  	struct stmmac_priv *priv = ch->priv_data;
@@ -57,7 +57,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	work_done = min(work_done, budget);
  
  	if (work_done < budget && napi_complete_done(napi, work_done)) {
-@@ -5502,6 +5507,10 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5501,6 +5506,10 @@ static int stmmac_napi_poll_tx(struct na
  		spin_unlock_irqrestore(&ch->lock, flags);
  	}
  
@@ -68,7 +68,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	return work_done;
  }
  
-@@ -5510,12 +5519,13 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5509,12 +5518,13 @@ static int stmmac_napi_poll_rxtx(struct
  	struct stmmac_channel *ch =
  		container_of(napi, struct stmmac_channel, rxtx_napi);
  	struct stmmac_priv *priv = ch->priv_data;
@@ -83,7 +83,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	tx_done = min(tx_done, budget);
  
  	rx_done = stmmac_rx_zc(priv, budget, chan);
-@@ -5540,6 +5550,10 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5539,6 +5549,10 @@ static int stmmac_napi_poll_rxtx(struct
  		spin_unlock_irqrestore(&ch->lock, flags);
  	}
  
diff --git a/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch b/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
index cc8cbf5a16..bce54eba4f 100644
--- a/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
+++ b/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
@@ -27,7 +27,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/common.h
 +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
-@@ -286,7 +286,7 @@ struct stmmac_safety_stats {
+@@ -287,7 +287,7 @@ struct stmmac_safety_stats {
  #define MIN_DMA_RIWT		0x10
  #define DEF_DMA_RIWT		0xa0
  /* Tx coalesce parameters */
diff --git a/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
index 893a81246d..f82c8fc622 100644
--- a/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
+++ b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
@@ -27,15 +27,15 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  /**
-@@ -71,6 +75,7 @@ struct phylink {
- 	struct mutex state_mutex;
+@@ -72,6 +76,7 @@ struct phylink {
  	struct phylink_link_state phy_state;
  	struct work_struct resolve;
+ 	unsigned int pcs_neg_mode;
 +	unsigned int pcs_state;
  
  	bool mac_link_dropped;
  	bool using_mac_select_pcs;
-@@ -990,6 +995,22 @@ static void phylink_mac_pcs_an_restart(s
+@@ -992,6 +997,22 @@ static void phylink_resolve_an_pause(str
  	}
  }
  
@@ -55,16 +55,17 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	return err;
 +}
 +
- static void phylink_major_config(struct phylink *pl, bool restart,
- 				  const struct phylink_link_state *state)
- {
-@@ -1026,11 +1047,16 @@ static void phylink_major_config(struct
+ static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      const struct phylink_link_state *state,
+ 			      bool permit_pause_to_mac)
+@@ -1094,11 +1115,17 @@ static void phylink_major_config(struct
  	/* If we have a new PCS, switch to the new PCS after preparing the MAC
  	 * for the change.
  	 */
 -	if (pcs_changed)
 +	if (pcs_changed) {
 +		phylink_pcs_disable(pl->pcs);
++
  		pl->pcs = pcs;
 +	}
  
@@ -73,18 +74,18 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed)
 +		phylink_pcs_enable(pl->pcs);
 +
- 	if (pl->pcs) {
- 		err = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
- 					       state->interface,
-@@ -1502,6 +1528,7 @@ struct phylink *phylink_create(struct ph
+ 	neg_mode = pl->cur_link_an_mode;
+ 	if (pl->pcs && pl->pcs->neg_mode)
+ 		neg_mode = pl->pcs_neg_mode;
+@@ -1586,6 +1613,7 @@ struct phylink *phylink_create(struct ph
+ 	pl->link_config.pause = MLO_PAUSE_AN;
  	pl->link_config.speed = SPEED_UNKNOWN;
  	pl->link_config.duplex = DUPLEX_UNKNOWN;
- 	pl->link_config.an_enabled = true;
 +	pl->pcs_state = PCS_STATE_DOWN;
  	pl->mac_ops = mac_ops;
  	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
  	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
-@@ -1903,6 +1930,8 @@ void phylink_start(struct phylink *pl)
+@@ -1987,6 +2015,8 @@ void phylink_start(struct phylink *pl)
  	if (pl->netdev)
  		netif_carrier_off(pl->netdev);
  
@@ -93,7 +94,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* Apply the link configuration to the MAC when starting. This allows
  	 * a fixed-link to start with the correct parameters, and also
  	 * ensures that we set the appropriate advertisement for Serdes links.
-@@ -1913,6 +1942,8 @@ void phylink_start(struct phylink *pl)
+@@ -1997,6 +2027,8 @@ void phylink_start(struct phylink *pl)
  	 */
  	phylink_mac_initial_config(pl, true);
  
@@ -102,7 +103,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
  
  	if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
-@@ -1931,15 +1962,9 @@ void phylink_start(struct phylink *pl)
+@@ -2015,15 +2047,9 @@ void phylink_start(struct phylink *pl)
  			poll = true;
  	}
  
@@ -120,7 +121,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (poll)
  		mod_timer(&pl->link_poll, jiffies + HZ);
  	if (pl->phydev)
-@@ -1976,6 +2001,10 @@ void phylink_stop(struct phylink *pl)
+@@ -2060,6 +2086,10 @@ void phylink_stop(struct phylink *pl)
  	}
  
  	phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED);
@@ -133,7 +134,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
 --- a/include/linux/phylink.h
 +++ b/include/linux/phylink.h
-@@ -446,6 +446,8 @@ struct phylink_pcs {
+@@ -533,6 +533,8 @@ struct phylink_pcs {
  /**
   * struct phylink_pcs_ops - MAC PCS operations structure.
   * @pcs_validate: validate the link configuration.
@@ -142,7 +143,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @pcs_get_state: read the current MAC PCS link state from the hardware.
   * @pcs_config: configure the MAC PCS for the selected mode and state.
   * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
-@@ -455,6 +457,8 @@ struct phylink_pcs {
+@@ -542,6 +544,8 @@ struct phylink_pcs {
  struct phylink_pcs_ops {
  	int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported,
  			    const struct phylink_link_state *state);
@@ -150,8 +151,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	void (*pcs_disable)(struct phylink_pcs *pcs);
  	void (*pcs_get_state)(struct phylink_pcs *pcs,
  			      struct phylink_link_state *state);
- 	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode,
-@@ -485,6 +489,18 @@ int pcs_validate(struct phylink_pcs *pcs
+ 	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int neg_mode,
+@@ -572,6 +576,18 @@ int pcs_validate(struct phylink_pcs *pcs
  		 const struct phylink_link_state *state);
  
  /**
diff --git a/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
index eb9b4b7c09..6b6369761a 100644
--- a/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
+++ b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
@@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/pcs/pcs-mtk-lynxi.c
 +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
-@@ -241,11 +241,19 @@ static void mtk_pcs_lynxi_link_up(struct
+@@ -234,11 +234,19 @@ static void mtk_pcs_lynxi_link_up(struct
  	}
  }
  
diff --git a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
index 70a3a4ad5c..0d2c0bcd83 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
@@ -48,7 +48,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  #include <linux/netdevice.h>
  #include <linux/phy.h>
  #include <linux/phy_led_triggers.h>
-@@ -644,6 +646,7 @@ struct phy_device *phy_device_create(str
+@@ -642,6 +644,7 @@ struct phy_device *phy_device_create(str
  	device_initialize(&mdiodev->dev);
  
  	dev->state = PHY_DOWN;
@@ -56,7 +56,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	mutex_init(&dev->lock);
  	INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
-@@ -3037,6 +3040,74 @@ static bool phy_drv_supports_irq(struct
+@@ -3035,6 +3038,74 @@ static bool phy_drv_supports_irq(struct
  	return phydrv->config_intr && phydrv->handle_interrupt;
  }
  
@@ -131,7 +131,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  /**
   * fwnode_mdio_find_device - Given a fwnode, find the mdio_device
   * @fwnode: pointer to the mdio_device's fwnode
-@@ -3215,6 +3286,11 @@ static int phy_probe(struct device *dev)
+@@ -3213,6 +3284,11 @@ static int phy_probe(struct device *dev)
  	/* Set the state to READY by default */
  	phydev->state = PHY_READY;
  
diff --git a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index e2e7bd65b1..4873c40a77 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -20,7 +20,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3040,11 +3040,18 @@ static bool phy_drv_supports_irq(struct
+@@ -3038,11 +3038,18 @@ static bool phy_drv_supports_irq(struct
  	return phydrv->config_intr && phydrv->handle_interrupt;
  }
  
@@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static int of_phy_led(struct phy_device *phydev,
-@@ -3061,12 +3068,14 @@ static int of_phy_led(struct phy_device
+@@ -3059,12 +3066,14 @@ static int of_phy_led(struct phy_device
  		return -ENOMEM;
  
  	cdev = &phyled->led_cdev;
diff --git a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index 804caf5d35..00bdcc5468 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3054,6 +3054,22 @@ static int phy_led_set_brightness(struct
+@@ -3052,6 +3052,22 @@ static int phy_led_set_brightness(struct
  	return err;
  }
  
@@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int of_phy_led(struct phy_device *phydev,
  		      struct device_node *led)
  {
-@@ -3076,6 +3092,8 @@ static int of_phy_led(struct phy_device
+@@ -3074,6 +3090,8 @@ static int of_phy_led(struct phy_device
  
  	if (phydev->drv->led_brightness_set)
  		cdev->brightness_set_blocking = phy_led_set_brightness;
diff --git a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
index 226c135f3c..3b68403690 100644
--- a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
+++ b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3316,7 +3316,8 @@ static int phy_probe(struct device *dev)
+@@ -3314,7 +3314,8 @@ static int phy_probe(struct device *dev)
  	/* Get the LEDs from the device tree, and instantiate standard
  	 * LEDs for them.
  	 */
diff --git a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
index 5bb92bc946..622bb9e94a 100644
--- a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
+++ b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3077,6 +3077,7 @@ static int of_phy_led(struct phy_device
+@@ -3075,6 +3075,7 @@ static int of_phy_led(struct phy_device
  	struct led_init_data init_data = {};
  	struct led_classdev *cdev;
  	struct phy_led *phyled;
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int err;
  
  	phyled = devm_kzalloc(dev, sizeof(*phyled), GFP_KERNEL);
-@@ -3086,10 +3087,13 @@ static int of_phy_led(struct phy_device
+@@ -3084,10 +3085,13 @@ static int of_phy_led(struct phy_device
  	cdev = &phyled->led_cdev;
  	phyled->phydev = phydev;
  
diff --git a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
index f7952d9f0c..80197e963b 100644
--- a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
+++ b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
@@ -22,7 +22,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3070,6 +3070,15 @@ static int phy_led_blink_set(struct led_
+@@ -3068,6 +3068,15 @@ static int phy_led_blink_set(struct led_
  	return err;
  }
  
@@ -38,7 +38,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int of_phy_led(struct phy_device *phydev,
  		      struct device_node *led)
  {
-@@ -3103,7 +3112,7 @@ static int of_phy_led(struct phy_device
+@@ -3101,7 +3110,7 @@ static int of_phy_led(struct phy_device
  	init_data.fwnode = of_fwnode_handle(led);
  	init_data.devname_mandatory = true;
  
@@ -47,7 +47,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (err)
  		return err;
  
-@@ -3132,6 +3141,7 @@ static int of_phy_leds(struct phy_device
+@@ -3130,6 +3139,7 @@ static int of_phy_leds(struct phy_device
  		err = of_phy_led(phydev, led);
  		if (err) {
  			of_node_put(led);
@@ -55,7 +55,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			return err;
  		}
  	}
-@@ -3337,6 +3347,9 @@ static int phy_remove(struct device *dev
+@@ -3335,6 +3345,9 @@ static int phy_remove(struct device *dev
  
  	cancel_delayed_work_sync(&phydev->state_queue);
  
diff --git a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index 947db79f06..505513a53f 100644
--- a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -23,7 +23,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3070,6 +3070,61 @@ static int phy_led_blink_set(struct led_
+@@ -3068,6 +3068,61 @@ static int phy_led_blink_set(struct led_
  	return err;
  }
  
@@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void phy_leds_unregister(struct phy_device *phydev)
  {
  	struct phy_led *phyled;
-@@ -3107,6 +3162,19 @@ static int of_phy_led(struct phy_device
+@@ -3105,6 +3160,19 @@ static int of_phy_led(struct phy_device
  		cdev->brightness_set_blocking = phy_led_set_brightness;
  	if (phydev->drv->led_blink_set)
  		cdev->blink_set = phy_led_blink_set;
diff --git a/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
index 1f49b3af0c..0182e6d1a2 100644
--- a/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
+++ b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
@@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3140,6 +3140,7 @@ static int of_phy_led(struct phy_device
+@@ -3138,6 +3138,7 @@ static int of_phy_led(struct phy_device
  	struct device *dev = &phydev->mdio.dev;
  	struct led_init_data init_data = {};
  	struct led_classdev *cdev;
@@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct phy_led *phyled;
  	u32 index;
  	int err;
-@@ -3157,6 +3158,21 @@ static int of_phy_led(struct phy_device
+@@ -3155,6 +3156,21 @@ static int of_phy_led(struct phy_device
  	if (index > U8_MAX)
  		return -EINVAL;
  
diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15
index 760a59b1bd..586f415d9c 100644
--- a/target/linux/generic/config-5.15
+++ b/target/linux/generic/config-5.15
@@ -2072,7 +2072,6 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
-# CONFIG_FIT_PARTITION is not set
 # CONFIG_FIXED_PHY is not set
 CONFIG_FLATMEM=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1
index eb8ccb58bc..89560f6dff 100644
--- a/target/linux/generic/config-6.1
+++ b/target/linux/generic/config-6.1
@@ -730,6 +730,7 @@ CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_BLK_DEV_ZONED is not set
 # CONFIG_BLK_INLINE_ENCRYPTION is not set
+# CONFIG_BLK_NVMEM is not set
 # CONFIG_BLK_SED_OPAL is not set
 # CONFIG_BLK_WBT is not set
 CONFIG_BLOCK=y
@@ -2169,7 +2170,6 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
-# CONFIG_FIT_PARTITION is not set
 # CONFIG_FIXED_PHY is not set
 CONFIG_FLATMEM=y
 CONFIG_FLATMEM_MANUAL=y
@@ -4058,6 +4058,7 @@ CONFIG_MTD_SPLIT_SUPPORT=y
 # CONFIG_MTD_UBI is not set
 # CONFIG_MTD_UBI_FASTMAP is not set
 # CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_NVMEM is not set
 # CONFIG_MTD_UIMAGE_SPLIT is not set
 # CONFIG_MTD_VIRT_CONCAT is not set
 # CONFIG_MTK_DEVAPC is not set
@@ -4857,6 +4858,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCNET32 is not set
 # CONFIG_PCPU_DEV_REFCNT is not set
 # CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PCS_MTK_USXGMII is not set
 # CONFIG_PCS_XPCS is not set
 # CONFIG_PD6729 is not set
 # CONFIG_PDA_POWER is not set
@@ -4891,6 +4893,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
 # CONFIG_PHY_MTK_HDMI is not set
 # CONFIG_PHY_MTK_MIPI_DSI is not set
+# CONFIG_PHY_MTK_XFI_TPHY is not set
 # CONFIG_PHY_MVEBU_CP110_UTMI is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
 # CONFIG_PHY_PISTACHIO_USB is not set
@@ -7092,6 +7095,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_UHID is not set
 CONFIG_UID16=y
 # CONFIG_UIO is not set
+# CONFIG_UIMAGE_FIT_BLK is not set
 # CONFIG_ULTRA is not set
 # CONFIG_ULTRIX_PARTITION is not set
 # CONFIG_UNICODE is not set
diff --git a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch b/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch
deleted file mode 100644
index 13a16b6fa0..0000000000
--- a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <openwrt-devel@lists.openwrt.org>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h                     |  2 ++
- block/partitions/Kconfig        |  7 +++++++
- block/partitions/Makefile       |  1 +
- block/partitions/check.h        |  3 +++
- block/partitions/core.c         | 17 +++++++++++++++++
- block/partitions/efi.c          |  8 ++++++++
- block/partitions/efi.h          |  3 +++
- block/partitions/msdos.c        | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c       |  2 ++
- drivers/mtd/ubi/block.c         |  3 +++
- include/linux/msdos_partition.h |  1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -354,6 +354,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE	0
- #define ADDPART_FLAG_RAID	1
- #define ADDPART_FLAG_WHOLEDISK	2
-+#define ADDPART_FLAG_READONLY	4
-+#define ADDPART_FLAG_ROOTDEV	8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- 		sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -101,6 +101,13 @@ config ATARI_PARTITION
- 	  Say Y here if you would like to use hard disks under Linux which
- 	  were partitioned under the Atari OS.
- 
-+config FIT_PARTITION
-+	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+	default n
-+	help
-+	  Say Y here if your system needs to mount the filesystem part of
-+	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- 	bool "IBM disk label and partition support"
- 	depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -58,6 +58,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -68,3 +69,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -12,6 +12,10 @@
- #include <linux/vmalloc.h>
- #include <linux/blktrace_api.h>
- #include <linux/raid/detect.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
-+
- #include "check.h"
- 
- static int (*check_part[])(struct parsed_partitions *) = {
-@@ -48,6 +52,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- 	efi_partition,		/* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+	fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- 	sgi_partition,
- #endif
-@@ -408,6 +415,11 @@ static struct block_device *add_partitio
- 			goto out_del;
- 	}
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if (flags & ADDPART_FLAG_READONLY)
-+		bdev->bd_read_only = true;
-+#endif
-+
- 	/* everything is up and running, commence */
- 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- 	if (err)
-@@ -595,6 +607,11 @@ static bool blk_add_partition(struct gen
- 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
- 		md_autodetect_dev(part->bd_dev);
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+		ROOT_DEV = part->bd_dev;
-+#endif
-+
- 	return true;
- }
- 
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- 	gpt_entry *ptes = NULL;
- 	u32 i;
- 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+#endif
- 
- 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- 		kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- 				ARRAY_SIZE(ptes[i].partition_name));
- 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- 		state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+		/* If this is a U-Boot FIT volume it may have subpartitions */
-+		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- 	}
- 	kfree(ptes);
- 	kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -52,6 +52,9 @@
- #define PARTITION_LINUX_LVM_GUID \
-     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
-               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
- 
- typedef struct _gpt_header {
- 	__le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
- 
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+			  sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- 	unsigned char id;
- 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- 	{UNIXWARE_PARTITION, parse_unixware},
- 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
- 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+	{FIT_PARTITION, parse_fit_mbr},
- 	{0, NULL},
- };
- 
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -345,6 +345,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- 	gd->first_minor = (new->devnum) << tr->part_bits;
- 	gd->minors = 1 << tr->part_bits;
- 	gd->fops = &mtd_block_ops;
-+	if (IS_ENABLED(CONFIG_FIT_PARTITION) && !mtd_type_is_nand(new->mtd))
-+		gd->flags |= GENHD_FL_EXT_DEVT;
- 
- 	if (tr->part_bits)
- 		if (new->devnum < 26)
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -428,6 +428,9 @@ int ubiblock_create(struct ubi_volume_in
- 		goto out_cleanup_disk;
- 	}
- 	gd->private_data = dev;
-+#ifdef CONFIG_FIT_PARTITION
-+	gd->flags |= GENHD_FL_EXT_DEVT;
-+#endif
- 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- 	set_capacity(gd, disk_capacity);
- 	dev->gd = gd;
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- 	LINUX_LVM_PARTITION = 0x8e,
- 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
- 
-+	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
- 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
- 	NEW_SOLARIS_X86_PARTITION = 0xbf,
- 
diff --git a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
index 9ff45a414e..f753b590e7 100644
--- a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
+++ b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -36,7 +36,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
 --- /dev/null
 +++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,698 @@
+@@ -0,0 +1,699 @@
 +/*
 + * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
 + *
@@ -574,6 +574,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +	if (!net)
 +		write_pnet(&table->ft.net, xt_net(par));
 +
++	__set_bit(NF_FLOW_HW_BIDIRECTIONAL, &flow->flags);
 +	if (flow_offload_add(&table->ft, flow) < 0)
 +		goto err_flow_add;
 +
diff --git a/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch b/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
index b213d804aa..673082d840 100644
--- a/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
+++ b/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
@@ -92,7 +92,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +
  comment "MII PHY device drivers"
  
- config AMD_PHY
+ config AIR_EN8811H_PHY
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
 @@ -24,6 +24,21 @@ libphy-$(CONFIG_LED_TRIGGER_PHY)	+= phy_
diff --git a/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch b/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
index 8b7f2f0955..a2bd3a3dbb 100644
--- a/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
+++ b/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/pcs/pcs-mtk-lynxi.c
 +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
-@@ -92,14 +92,23 @@ static void mtk_pcs_lynxi_get_state(stru
+@@ -114,14 +114,23 @@ static void mtk_pcs_lynxi_get_state(stru
  				    struct phylink_link_state *state)
  {
  	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
@@ -40,14 +40,14 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	phylink_mii_c22_pcs_decode_state(state, bmsr, FIELD_GET(SGMII_LPA, adv));
  }
  
- static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int mode,
-@@ -134,7 +143,8 @@ static int mtk_pcs_lynxi_config(struct p
- 		/* 1000base-X or 2500base-X autoneg */
- 		sgm_mode = SGMII_REMOTE_FAULT_DIS;
- 		use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
--					   advertising);
-+					   advertising) &&
-+			 !(interface == PHY_INTERFACE_MODE_2500BASEX);
- 	} else {
- 		/* 1000base-X or 2500base-X without autoneg */
- 		sgm_mode = 0;
+ static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
+@@ -163,7 +172,8 @@ static int mtk_pcs_lynxi_config(struct p
+ 	if (neg_mode & PHYLINK_PCS_NEG_INBAND)
+ 		sgm_mode |= SGMII_REMOTE_FAULT_DIS;
+ 
+-	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED &&
++	    interface != PHY_INTERFACE_MODE_2500BASEX) {
+ 		if (interface == PHY_INTERFACE_MODE_SGMII)
+ 			sgm_mode |= SGMII_SPEED_DUPLEX_AN;
+ 		bmcr = BMCR_ANENABLE;
diff --git a/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch b/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
index 27c87d5b65..bb21bb39d3 100644
--- a/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
+++ b/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
@@ -46,7 +46,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		} else if (event == SFP_E_TIMEOUT || event == SFP_E_TX_CLEAR) {
  	init_done:
  			/* Create mdiobus and start trying for PHY */
-@@ -2573,10 +2577,12 @@ static void sfp_check_state(struct sfp *
+@@ -2578,10 +2582,12 @@ static void sfp_check_state(struct sfp *
  	mutex_lock(&sfp->st_mutex);
  	state = sfp_get_state(sfp);
  	changed = state ^ sfp->state;
diff --git a/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch b/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch
new file mode 100644
index 0000000000..063d3fa79c
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch
@@ -0,0 +1,121 @@
+From ffbbe7d66872ff8957dad2136133e28a1fd5d437 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 22:51:05 +0100
+Subject: [PATCH 01/15] dt-bindings: mtd: add basic bindings for UBI
+
+Add basic bindings for UBI devices and volumes.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/mtd/partitions/linux,ubi.yaml    | 65 +++++++++++++++++++
+ .../bindings/mtd/partitions/ubi-volume.yaml   | 35 ++++++++++
+ 2 files changed, 100 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+ create mode 100644 Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+@@ -0,0 +1,65 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Unsorted Block Images
++
++description: |
++  UBI ("Unsorted Block Images") is a volume management system for raw
++  flash devices which manages multiple logical volumes on a single
++  physical flash device and spreads the I/O load (i.e wear-leveling)
++  across the whole flash chip.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++allOf:
++  - $ref: partition.yaml#
++
++properties:
++  compatible:
++    const: linux,ubi
++
++  volumes:
++    type: object
++    description: UBI Volumes
++
++    patternProperties:
++      "^ubi-volume-.*$":
++        $ref: /schemas/mtd/partitions/ubi-volume.yaml#
++
++    unevaluatedProperties: false
++
++required:
++  - compatible
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    partitions {
++        compatible = "fixed-partitions";
++        #address-cells = <1>;
++        #size-cells = <1>;
++
++        partition@0 {
++            reg = <0x0 0x100000>;
++            label = "bootloader";
++            read-only;
++        };
++
++        partition@100000 {
++            reg = <0x100000 0x1ff00000>;
++            label = "ubi";
++            compatible = "linux,ubi";
++
++            volumes {
++                ubi-volume-caldata {
++                    volid = <2>;
++                    volname = "rf";
++                };
++            };
++        };
++    };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+@@ -0,0 +1,35 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: UBI volume
++
++description: |
++  This binding describes a single UBI volume. Volumes can be matches either
++  by their ID or their name, or both.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  volid:
++    $ref: "/schemas/types.yaml#/definitions/uint32"
++    description:
++      Match UBI volume ID
++
++  volname:
++    $ref: "/schemas/types.yaml#/definitions/string"
++    description:
++      Match UBI volume ID
++
++anyOf:
++  - required:
++    - volid
++
++  - required:
++    - volname
++
++# This is a generic file other binding inherit from and extend
++additionalProperties: true
diff --git a/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch b/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch
new file mode 100644
index 0000000000..823c8e83b7
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch
@@ -0,0 +1,48 @@
+From e4dad3aa5c3ab9c553555dd23c0b85f725f2eb51 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 22:53:01 +0100
+Subject: [PATCH 02/15] dt-bindings: mtd: ubi-volume: allow UBI volumes to
+ provide NVMEM
+
+UBI volumes may be used to contain NVMEM bits, typically device MAC
+addresses or wireless radio calibration data.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../devicetree/bindings/mtd/partitions/linux,ubi.yaml  | 10 ++++++++++
+ .../devicetree/bindings/mtd/partitions/ubi-volume.yaml |  5 +++++
+ 2 files changed, 15 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
++++ b/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+@@ -59,6 +59,16 @@ examples:
+                 ubi-volume-caldata {
+                     volid = <2>;
+                     volname = "rf";
++
++                    nvmem-layout {
++                        compatible = "fixed-layout";
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++
++                        eeprom@0 {
++                            reg = <0x0 0x1000>;
++                        };
++                    };
+                 };
+             };
+         };
+--- a/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
++++ b/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+@@ -24,6 +24,11 @@ properties:
+     description:
+       Match UBI volume ID
+ 
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++    description:
++      This container may reference an NVMEM layout parser.
++
+ anyOf:
+   - required:
+     - volid
diff --git a/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch b/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch
new file mode 100644
index 0000000000..eda3b108da
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch
@@ -0,0 +1,225 @@
+From e5cf19bd8204925f3bd2067df9e867313eac388b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 1 May 2023 11:57:51 +0100
+Subject: [PATCH 03/15] mtd: ubi: block: use notifier to create ubiblock from
+ parameter
+
+Use UBI_VOLUME_ADDED notification to create ubiblock device specified
+on kernel cmdline or module parameter.
+This makes thing more simple and has the advantage that ubiblock devices
+on volumes which are not present at the time the ubi module is probed
+will still be created.
+
+Suggested-by: Zhihao Cheng <chengzhihao1@huawei.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 154 ++++++++++++++++++++++------------------
+ 1 file changed, 85 insertions(+), 69 deletions(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -33,6 +33,7 @@
+ #include <linux/kernel.h>
+ #include <linux/list.h>
+ #include <linux/mutex.h>
++#include <linux/namei.h>
+ #include <linux/slab.h>
+ #include <linux/mtd/ubi.h>
+ #include <linux/workqueue.h>
+@@ -67,10 +68,10 @@ struct ubiblock_pdu {
+ };
+ 
+ /* Numbers of elements set in the @ubiblock_param array */
+-static int ubiblock_devs __initdata;
++static int ubiblock_devs;
+ 
+ /* MTD devices specification parameters */
+-static struct ubiblock_param ubiblock_param[UBIBLOCK_MAX_DEVICES] __initdata;
++static struct ubiblock_param ubiblock_param[UBIBLOCK_MAX_DEVICES];
+ 
+ struct ubiblock {
+ 	struct ubi_volume_desc *desc;
+@@ -504,7 +505,7 @@ int ubiblock_remove(struct ubi_volume_in
+ 	}
+ 
+ 	/* Found a device, let's lock it so we can check if it's busy */
+-	mutex_lock(&dev->dev_mutex);
++	mutex_lock_nested(&dev->dev_mutex, SINGLE_DEPTH_NESTING);
+ 	if (dev->refcnt > 0) {
+ 		ret = -EBUSY;
+ 		goto out_unlock_dev;
+@@ -567,6 +568,85 @@ static int ubiblock_resize(struct ubi_vo
+ 	return 0;
+ }
+ 
++static bool
++match_volume_desc(struct ubi_volume_info *vi, const char *name, int ubi_num, int vol_id)
++{
++	int err, len;
++	struct path path;
++	struct kstat stat;
++
++	if (ubi_num == -1) {
++		/* No ubi num, name must be a vol device path */
++		err = kern_path(name, LOOKUP_FOLLOW, &path);
++		if (err)
++			return false;
++
++		err = vfs_getattr(&path, &stat, STATX_TYPE, AT_STATX_SYNC_AS_STAT);
++		path_put(&path);
++		if (err)
++			return false;
++
++		if (!S_ISCHR(stat.mode))
++			return false;
++
++		if (vi->ubi_num != ubi_major2num(MAJOR(stat.rdev)))
++			return false;
++
++		if (vi->vol_id != MINOR(stat.rdev) - 1)
++			return false;
++
++		return true;
++	}
++
++	if (vol_id == -1) {
++		if (vi->ubi_num != ubi_num)
++			return false;
++
++		len = strnlen(name, UBI_VOL_NAME_MAX + 1);
++		if (len < 1 || vi->name_len != len)
++			return false;
++
++		if (strcmp(name, vi->name))
++			return false;
++
++		return true;
++	}
++
++	if (vi->ubi_num != ubi_num)
++		return false;
++
++	if (vi->vol_id != vol_id)
++		return false;
++
++	return true;
++}
++
++static void
++ubiblock_create_from_param(struct ubi_volume_info *vi)
++{
++	int i, ret = 0;
++	struct ubiblock_param *p;
++
++	/*
++	 * Iterate over ubiblock cmdline parameters. If a parameter matches the
++	 * newly added volume create the ubiblock device for it.
++	 */
++	for (i = 0; i < ubiblock_devs; i++) {
++		p = &ubiblock_param[i];
++
++		if (!match_volume_desc(vi, p->name, p->ubi_num, p->vol_id))
++			continue;
++
++		ret = ubiblock_create(vi);
++		if (ret) {
++			pr_err(
++			       "UBI: block: can't add '%s' volume on ubi%d_%d, err=%d\n",
++			       vi->name, p->ubi_num, p->vol_id, ret);
++		}
++		break;
++	}
++}
++
+ static int ubiblock_notify(struct notifier_block *nb,
+ 			 unsigned long notification_type, void *ns_ptr)
+ {
+@@ -574,10 +654,7 @@ static int ubiblock_notify(struct notifi
+ 
+ 	switch (notification_type) {
+ 	case UBI_VOLUME_ADDED:
+-		/*
+-		 * We want to enforce explicit block device creation for
+-		 * volumes, so when a volume is added we do nothing.
+-		 */
++		ubiblock_create_from_param(&nt->vi);
+ 		break;
+ 	case UBI_VOLUME_REMOVED:
+ 		ubiblock_remove(&nt->vi);
+@@ -603,56 +680,6 @@ static struct notifier_block ubiblock_no
+ 	.notifier_call = ubiblock_notify,
+ };
+ 
+-static struct ubi_volume_desc * __init
+-open_volume_desc(const char *name, int ubi_num, int vol_id)
+-{
+-	if (ubi_num == -1)
+-		/* No ubi num, name must be a vol device path */
+-		return ubi_open_volume_path(name, UBI_READONLY);
+-	else if (vol_id == -1)
+-		/* No vol_id, must be vol_name */
+-		return ubi_open_volume_nm(ubi_num, name, UBI_READONLY);
+-	else
+-		return ubi_open_volume(ubi_num, vol_id, UBI_READONLY);
+-}
+-
+-static void __init ubiblock_create_from_param(void)
+-{
+-	int i, ret = 0;
+-	struct ubiblock_param *p;
+-	struct ubi_volume_desc *desc;
+-	struct ubi_volume_info vi;
+-
+-	/*
+-	 * If there is an error creating one of the ubiblocks, continue on to
+-	 * create the following ubiblocks. This helps in a circumstance where
+-	 * the kernel command-line specifies multiple block devices and some
+-	 * may be broken, but we still want the working ones to come up.
+-	 */
+-	for (i = 0; i < ubiblock_devs; i++) {
+-		p = &ubiblock_param[i];
+-
+-		desc = open_volume_desc(p->name, p->ubi_num, p->vol_id);
+-		if (IS_ERR(desc)) {
+-			pr_err(
+-			       "UBI: block: can't open volume on ubi%d_%d, err=%ld\n",
+-			       p->ubi_num, p->vol_id, PTR_ERR(desc));
+-			continue;
+-		}
+-
+-		ubi_get_volume_info(desc, &vi);
+-		ubi_close_volume(desc);
+-
+-		ret = ubiblock_create(&vi);
+-		if (ret) {
+-			pr_err(
+-			       "UBI: block: can't add '%s' volume on ubi%d_%d, err=%d\n",
+-			       vi.name, p->ubi_num, p->vol_id, ret);
+-			continue;
+-		}
+-	}
+-}
+-
+ static void ubiblock_remove_all(void)
+ {
+ 	struct ubiblock *next;
+@@ -678,18 +705,7 @@ int __init ubiblock_init(void)
+ 	if (ubiblock_major < 0)
+ 		return ubiblock_major;
+ 
+-	/*
+-	 * Attach block devices from 'block=' module param.
+-	 * Even if one block device in the param list fails to come up,
+-	 * still allow the module to load and leave any others up.
+-	 */
+-	ubiblock_create_from_param();
+-
+-	/*
+-	 * Block devices are only created upon user requests, so we ignore
+-	 * existing volumes.
+-	 */
+-	ret = ubi_register_volume_notifier(&ubiblock_notifier, 1);
++	ret = ubi_register_volume_notifier(&ubiblock_notifier, 0);
+ 	if (ret)
+ 		goto err_unreg;
+ 	return 0;
diff --git a/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch b/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch
new file mode 100644
index 0000000000..6e10e5ebed
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch
@@ -0,0 +1,264 @@
+From 471a17d8d1b838092d1a76e48cdce8b5b67ff809 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 27 Nov 2023 01:54:28 +0000
+Subject: [PATCH 04/15] mtd: ubi: attach from device tree
+
+Introduce device tree compatible 'linux,ubi' and attach compatible MTD
+devices using the MTD add notifier. This is needed for a UBI device to
+be available early at boot (and not only after late_initcall), so
+volumes on them can be used eg. as NVMEM providers for other drivers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/build.c | 146 ++++++++++++++++++++++++++++------------
+ drivers/mtd/ubi/cdev.c  |   2 +-
+ drivers/mtd/ubi/ubi.h   |   2 +-
+ 3 files changed, 106 insertions(+), 44 deletions(-)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -27,6 +27,7 @@
+ #include <linux/log2.h>
+ #include <linux/kthread.h>
+ #include <linux/kernel.h>
++#include <linux/of.h>
+ #include <linux/slab.h>
+ #include <linux/major.h>
+ #include "ubi.h"
+@@ -1071,6 +1072,7 @@ out_free:
+  * ubi_detach_mtd_dev - detach an MTD device.
+  * @ubi_num: UBI device number to detach from
+  * @anyway: detach MTD even if device reference count is not zero
++ * @have_lock: called by MTD notifier holding mtd_table_mutex
+  *
+  * This function destroys an UBI device number @ubi_num and detaches the
+  * underlying MTD device. Returns zero in case of success and %-EBUSY if the
+@@ -1080,7 +1082,7 @@ out_free:
+  * Note, the invocations of this function has to be serialized by the
+  * @ubi_devices_mutex.
+  */
+-int ubi_detach_mtd_dev(int ubi_num, int anyway)
++int ubi_detach_mtd_dev(int ubi_num, int anyway, bool have_lock)
+ {
+ 	struct ubi_device *ubi;
+ 
+@@ -1136,7 +1138,11 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 	vfree(ubi->peb_buf);
+ 	vfree(ubi->fm_buf);
+ 	ubi_msg(ubi, "mtd%d is detached", ubi->mtd->index);
+-	put_mtd_device(ubi->mtd);
++	if (have_lock)
++		__put_mtd_device(ubi->mtd);
++	else
++		put_mtd_device(ubi->mtd);
++
+ 	put_device(&ubi->dev);
+ 	return 0;
+ }
+@@ -1213,43 +1219,43 @@ static struct mtd_info * __init open_mtd
+ 	return mtd;
+ }
+ 
+-static int __init ubi_init(void)
++static void ubi_notify_add(struct mtd_info *mtd)
+ {
+-	int err, i, k;
++	struct device_node *np = mtd_get_of_node(mtd);
++	int err;
+ 
+-	/* Ensure that EC and VID headers have correct size */
+-	BUILD_BUG_ON(sizeof(struct ubi_ec_hdr) != 64);
+-	BUILD_BUG_ON(sizeof(struct ubi_vid_hdr) != 64);
++	if (!of_device_is_compatible(np, "linux,ubi"))
++		return;
+ 
+-	if (mtd_devs > UBI_MAX_DEVICES) {
+-		pr_err("UBI error: too many MTD devices, maximum is %d\n",
+-		       UBI_MAX_DEVICES);
+-		return -EINVAL;
+-	}
++	/*
++	 * we are already holding &mtd_table_mutex, but still need
++	 * to bump refcount
++	 */
++	err = __get_mtd_device(mtd);
++	if (err)
++		return;
+ 
+-	/* Create base sysfs directory and sysfs files */
+-	err = class_register(&ubi_class);
++	/* called while holding mtd_table_mutex */
++	mutex_lock_nested(&ubi_devices_mutex, SINGLE_DEPTH_NESTING);
++	err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0, false);
++	mutex_unlock(&ubi_devices_mutex);
+ 	if (err < 0)
+-		return err;
+-
+-	err = misc_register(&ubi_ctrl_cdev);
+-	if (err) {
+-		pr_err("UBI error: cannot register device\n");
+-		goto out;
+-	}
++		__put_mtd_device(mtd);
++}
+ 
+-	ubi_wl_entry_slab = kmem_cache_create("ubi_wl_entry_slab",
+-					      sizeof(struct ubi_wl_entry),
+-					      0, 0, NULL);
+-	if (!ubi_wl_entry_slab) {
+-		err = -ENOMEM;
+-		goto out_dev_unreg;
+-	}
++static void ubi_notify_remove(struct mtd_info *mtd)
++{
++	WARN(1, "mtd%d removed despite UBI still being attached", mtd->index);
++}
+ 
+-	err = ubi_debugfs_init();
+-	if (err)
+-		goto out_slab;
++static struct mtd_notifier ubi_mtd_notifier = {
++	.add = ubi_notify_add,
++	.remove = ubi_notify_remove,
++};
+ 
++static int __init ubi_init_attach(void)
++{
++	int err, i, k;
+ 
+ 	/* Attach MTD devices */
+ 	for (i = 0; i < mtd_devs; i++) {
+@@ -1297,25 +1303,79 @@ static int __init ubi_init(void)
+ 		}
+ 	}
+ 
++	return 0;
++
++out_detach:
++	for (k = 0; k < i; k++)
++		if (ubi_devices[k]) {
++			mutex_lock(&ubi_devices_mutex);
++			ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1, false);
++			mutex_unlock(&ubi_devices_mutex);
++		}
++	return err;
++}
++#ifndef CONFIG_MTD_UBI_MODULE
++late_initcall(ubi_init_attach);
++#endif
++
++static int __init ubi_init(void)
++{
++	int err;
++
++	/* Ensure that EC and VID headers have correct size */
++	BUILD_BUG_ON(sizeof(struct ubi_ec_hdr) != 64);
++	BUILD_BUG_ON(sizeof(struct ubi_vid_hdr) != 64);
++
++	if (mtd_devs > UBI_MAX_DEVICES) {
++		pr_err("UBI error: too many MTD devices, maximum is %d\n",
++		       UBI_MAX_DEVICES);
++		return -EINVAL;
++	}
++
++	/* Create base sysfs directory and sysfs files */
++	err = class_register(&ubi_class);
++	if (err < 0)
++		return err;
++
++	err = misc_register(&ubi_ctrl_cdev);
++	if (err) {
++		pr_err("UBI error: cannot register device\n");
++		goto out;
++	}
++
++	ubi_wl_entry_slab = kmem_cache_create("ubi_wl_entry_slab",
++					      sizeof(struct ubi_wl_entry),
++					      0, 0, NULL);
++	if (!ubi_wl_entry_slab) {
++		err = -ENOMEM;
++		goto out_dev_unreg;
++	}
++
++	err = ubi_debugfs_init();
++	if (err)
++		goto out_slab;
++
+ 	err = ubiblock_init();
+ 	if (err) {
+ 		pr_err("UBI error: block: cannot initialize, error %d\n", err);
+ 
+ 		/* See comment above re-ubi_is_module(). */
+ 		if (ubi_is_module())
+-			goto out_detach;
++			goto out_slab;
++	}
++
++	register_mtd_user(&ubi_mtd_notifier);
++
++	if (ubi_is_module()) {
++		err = ubi_init_attach();
++		if (err)
++			goto out_mtd_notifier;
+ 	}
+ 
+ 	return 0;
+ 
+-out_detach:
+-	for (k = 0; k < i; k++)
+-		if (ubi_devices[k]) {
+-			mutex_lock(&ubi_devices_mutex);
+-			ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1);
+-			mutex_unlock(&ubi_devices_mutex);
+-		}
+-	ubi_debugfs_exit();
++out_mtd_notifier:
++	unregister_mtd_user(&ubi_mtd_notifier);
+ out_slab:
+ 	kmem_cache_destroy(ubi_wl_entry_slab);
+ out_dev_unreg:
+@@ -1325,18 +1385,20 @@ out:
+ 	pr_err("UBI error: cannot initialize UBI, error %d\n", err);
+ 	return err;
+ }
+-late_initcall(ubi_init);
++device_initcall(ubi_init);
++
+ 
+ static void __exit ubi_exit(void)
+ {
+ 	int i;
+ 
+ 	ubiblock_exit();
++	unregister_mtd_user(&ubi_mtd_notifier);
+ 
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++)
+ 		if (ubi_devices[i]) {
+ 			mutex_lock(&ubi_devices_mutex);
+-			ubi_detach_mtd_dev(ubi_devices[i]->ubi_num, 1);
++			ubi_detach_mtd_dev(ubi_devices[i]->ubi_num, 1, false);
+ 			mutex_unlock(&ubi_devices_mutex);
+ 		}
+ 	ubi_debugfs_exit();
+--- a/drivers/mtd/ubi/cdev.c
++++ b/drivers/mtd/ubi/cdev.c
+@@ -1065,7 +1065,7 @@ static long ctrl_cdev_ioctl(struct file
+ 		}
+ 
+ 		mutex_lock(&ubi_devices_mutex);
+-		err = ubi_detach_mtd_dev(ubi_num, 0);
++		err = ubi_detach_mtd_dev(ubi_num, 0, false);
+ 		mutex_unlock(&ubi_devices_mutex);
+ 		break;
+ 	}
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -939,7 +939,7 @@ int ubi_io_write_vid_hdr(struct ubi_devi
+ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
+ 		       int vid_hdr_offset, int max_beb_per1024,
+ 		       bool disable_fm);
+-int ubi_detach_mtd_dev(int ubi_num, int anyway);
++int ubi_detach_mtd_dev(int ubi_num, int anyway, bool have_lock);
+ struct ubi_device *ubi_get_device(int ubi_num);
+ void ubi_put_device(struct ubi_device *ubi);
+ struct ubi_device *ubi_get_by_major(int major);
diff --git a/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch b/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch
new file mode 100644
index 0000000000..d5da37b856
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch
@@ -0,0 +1,226 @@
+From 2d664266cfdd114cc7a1fa28dd64275e99222455 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 8 Jun 2023 17:18:09 +0100
+Subject: [PATCH 05/15] mtd: ubi: introduce pre-removal notification for UBI
+ volumes
+
+Introduce a new notification type UBI_VOLUME_SHUTDOWN to inform users
+that a volume is just about to be removed.
+This is needed because users (such as the NVMEM subsystem) expect that
+at the time their removal function is called, the parenting device is
+still available (for removal of sysfs nodes, for example, in case of
+NVMEM which otherwise WARNs on volume removal).
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 26 ++++++++++++++++++++++++++
+ drivers/mtd/ubi/build.c | 20 +++++++++++++++-----
+ drivers/mtd/ubi/kapi.c  |  2 +-
+ drivers/mtd/ubi/ubi.h   |  2 ++
+ drivers/mtd/ubi/vmt.c   | 17 +++++++++++++++--
+ include/linux/mtd/ubi.h |  2 ++
+ 6 files changed, 61 insertions(+), 8 deletions(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -568,6 +568,29 @@ static int ubiblock_resize(struct ubi_vo
+ 	return 0;
+ }
+ 
++static int ubiblock_shutdown(struct ubi_volume_info *vi)
++{
++	struct ubiblock *dev;
++	struct gendisk *disk;
++	int ret = 0;
++
++	mutex_lock(&devices_mutex);
++	dev = find_dev_nolock(vi->ubi_num, vi->vol_id);
++	if (!dev) {
++		ret = -ENODEV;
++		goto out_unlock;
++	}
++	disk = dev->gd;
++
++out_unlock:
++	mutex_unlock(&devices_mutex);
++
++	if (!ret)
++		blk_mark_disk_dead(disk);
++
++	return ret;
++};
++
+ static bool
+ match_volume_desc(struct ubi_volume_info *vi, const char *name, int ubi_num, int vol_id)
+ {
+@@ -659,6 +682,9 @@ static int ubiblock_notify(struct notifi
+ 	case UBI_VOLUME_REMOVED:
+ 		ubiblock_remove(&nt->vi);
+ 		break;
++	case UBI_VOLUME_SHUTDOWN:
++		ubiblock_shutdown(&nt->vi);
++		break;
+ 	case UBI_VOLUME_RESIZED:
+ 		ubiblock_resize(&nt->vi);
+ 		break;
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -89,7 +89,7 @@ static struct ubi_device *ubi_devices[UB
+ /* Serializes UBI devices creations and removals */
+ DEFINE_MUTEX(ubi_devices_mutex);
+ 
+-/* Protects @ubi_devices and @ubi->ref_count */
++/* Protects @ubi_devices, @ubi->ref_count and @ubi->is_dead */
+ static DEFINE_SPINLOCK(ubi_devices_lock);
+ 
+ /* "Show" method for files in '/<sysfs>/class/ubi/' */
+@@ -258,6 +258,9 @@ struct ubi_device *ubi_get_device(int ub
+ 
+ 	spin_lock(&ubi_devices_lock);
+ 	ubi = ubi_devices[ubi_num];
++	if (ubi && ubi->is_dead)
++		ubi = NULL;
++
+ 	if (ubi) {
+ 		ubi_assert(ubi->ref_count >= 0);
+ 		ubi->ref_count += 1;
+@@ -295,7 +298,7 @@ struct ubi_device *ubi_get_by_major(int
+ 	spin_lock(&ubi_devices_lock);
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++) {
+ 		ubi = ubi_devices[i];
+-		if (ubi && MAJOR(ubi->cdev.dev) == major) {
++		if (ubi && !ubi->is_dead && MAJOR(ubi->cdev.dev) == major) {
+ 			ubi_assert(ubi->ref_count >= 0);
+ 			ubi->ref_count += 1;
+ 			get_device(&ubi->dev);
+@@ -324,7 +327,7 @@ int ubi_major2num(int major)
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++) {
+ 		struct ubi_device *ubi = ubi_devices[i];
+ 
+-		if (ubi && MAJOR(ubi->cdev.dev) == major) {
++		if (ubi && !ubi->is_dead && MAJOR(ubi->cdev.dev) == major) {
+ 			ubi_num = ubi->ubi_num;
+ 			break;
+ 		}
+@@ -511,7 +514,7 @@ static void ubi_free_volumes_from(struct
+ 	int i;
+ 
+ 	for (i = from; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) {
+-		if (!ubi->volumes[i])
++		if (!ubi->volumes[i] || ubi->volumes[i]->is_dead)
+ 			continue;
+ 		ubi_eba_replace_table(ubi->volumes[i], NULL);
+ 		ubi_fastmap_destroy_checkmap(ubi->volumes[i]);
+@@ -1094,10 +1097,10 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 		return -EINVAL;
+ 
+ 	spin_lock(&ubi_devices_lock);
+-	put_device(&ubi->dev);
+ 	ubi->ref_count -= 1;
+ 	if (ubi->ref_count) {
+ 		if (!anyway) {
++			ubi->ref_count += 1;
+ 			spin_unlock(&ubi_devices_lock);
+ 			return -EBUSY;
+ 		}
+@@ -1105,6 +1108,13 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 		ubi_err(ubi, "%s reference count %d, destroy anyway",
+ 			ubi->ubi_name, ubi->ref_count);
+ 	}
++	ubi->is_dead = true;
++	spin_unlock(&ubi_devices_lock);
++
++	ubi_notify_all(ubi, UBI_VOLUME_SHUTDOWN, NULL);
++
++	spin_lock(&ubi_devices_lock);
++	put_device(&ubi->dev);
+ 	ubi_devices[ubi_num] = NULL;
+ 	spin_unlock(&ubi_devices_lock);
+ 
+--- a/drivers/mtd/ubi/kapi.c
++++ b/drivers/mtd/ubi/kapi.c
+@@ -152,7 +152,7 @@ struct ubi_volume_desc *ubi_open_volume(
+ 
+ 	spin_lock(&ubi->volumes_lock);
+ 	vol = ubi->volumes[vol_id];
+-	if (!vol)
++	if (!vol || vol->is_dead)
+ 		goto out_unlock;
+ 
+ 	err = -EBUSY;
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -345,6 +345,7 @@ struct ubi_volume {
+ 	int writers;
+ 	int exclusive;
+ 	int metaonly;
++	bool is_dead;
+ 
+ 	int reserved_pebs;
+ 	int vol_type;
+@@ -564,6 +565,7 @@ struct ubi_device {
+ 	spinlock_t volumes_lock;
+ 	int ref_count;
+ 	int image_seq;
++	bool is_dead;
+ 
+ 	int rsvd_pebs;
+ 	int avail_pebs;
+--- a/drivers/mtd/ubi/vmt.c
++++ b/drivers/mtd/ubi/vmt.c
+@@ -59,7 +59,7 @@ static ssize_t vol_attribute_show(struct
+ 	struct ubi_device *ubi = vol->ubi;
+ 
+ 	spin_lock(&ubi->volumes_lock);
+-	if (!ubi->volumes[vol->vol_id]) {
++	if (!ubi->volumes[vol->vol_id] || ubi->volumes[vol->vol_id]->is_dead) {
+ 		spin_unlock(&ubi->volumes_lock);
+ 		return -ENODEV;
+ 	}
+@@ -189,7 +189,7 @@ int ubi_create_volume(struct ubi_device
+ 
+ 	/* Ensure that the name is unique */
+ 	for (i = 0; i < ubi->vtbl_slots; i++)
+-		if (ubi->volumes[i] &&
++		if (ubi->volumes[i] && !ubi->volumes[i]->is_dead &&
+ 		    ubi->volumes[i]->name_len == req->name_len &&
+ 		    !strcmp(ubi->volumes[i]->name, req->name)) {
+ 			ubi_err(ubi, "volume \"%s\" exists (ID %d)",
+@@ -352,6 +352,19 @@ int ubi_remove_volume(struct ubi_volume_
+ 		err = -EBUSY;
+ 		goto out_unlock;
+ 	}
++
++	/*
++	 * Mark volume as dead at this point to prevent that anyone
++	 * can take a reference to the volume from now on.
++	 * This is necessary as we have to release the spinlock before
++	 * calling ubi_volume_notify.
++	 */
++	vol->is_dead = true;
++	spin_unlock(&ubi->volumes_lock);
++
++	ubi_volume_notify(ubi, vol, UBI_VOLUME_SHUTDOWN);
++
++	spin_lock(&ubi->volumes_lock);
+ 	ubi->volumes[vol_id] = NULL;
+ 	spin_unlock(&ubi->volumes_lock);
+ 
+--- a/include/linux/mtd/ubi.h
++++ b/include/linux/mtd/ubi.h
+@@ -192,6 +192,7 @@ struct ubi_device_info {
+  *			or a volume was removed)
+  * @UBI_VOLUME_RESIZED: a volume has been re-sized
+  * @UBI_VOLUME_RENAMED: a volume has been re-named
++ * @UBI_VOLUME_SHUTDOWN: a volume is going to removed, shutdown users
+  * @UBI_VOLUME_UPDATED: data has been written to a volume
+  *
+  * These constants define which type of event has happened when a volume
+@@ -202,6 +203,7 @@ enum {
+ 	UBI_VOLUME_REMOVED,
+ 	UBI_VOLUME_RESIZED,
+ 	UBI_VOLUME_RENAMED,
++	UBI_VOLUME_SHUTDOWN,
+ 	UBI_VOLUME_UPDATED,
+ };
+ 
diff --git a/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch b/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch
new file mode 100644
index 0000000000..1322766965
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch
@@ -0,0 +1,65 @@
+From 3a041ee543cdf2e707a1dd72946cd6a583509b28 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Jul 2023 19:26:37 +0100
+Subject: [PATCH 06/15] mtd: ubi: populate ubi volume fwnode
+
+Look for the 'volumes' subnode of an MTD partition attached to a UBI
+device and attach matching child nodes to UBI volumes.
+This allows UBI volumes to be referenced in device tree, e.g. for use
+as NVMEM providers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/vmt.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/drivers/mtd/ubi/vmt.c
++++ b/drivers/mtd/ubi/vmt.c
+@@ -124,6 +124,31 @@ static void vol_release(struct device *d
+ 	kfree(vol);
+ }
+ 
++static struct fwnode_handle *find_volume_fwnode(struct ubi_volume *vol)
++{
++	struct fwnode_handle *fw_vols, *fw_vol;
++	const char *volname;
++	u32 volid;
++
++	fw_vols = device_get_named_child_node(vol->dev.parent->parent, "volumes");
++	if (!fw_vols)
++		return NULL;
++
++	fwnode_for_each_child_node(fw_vols, fw_vol) {
++		if (!fwnode_property_read_string(fw_vol, "volname", &volname) &&
++		    strncmp(volname, vol->name, vol->name_len))
++			continue;
++
++		if (!fwnode_property_read_u32(fw_vol, "volid", &volid) &&
++		    vol->vol_id != volid)
++			continue;
++
++		return fw_vol;
++	}
++
++	return NULL;
++}
++
+ /**
+  * ubi_create_volume - create volume.
+  * @ubi: UBI device description object
+@@ -223,6 +248,7 @@ int ubi_create_volume(struct ubi_device
+ 	vol->name_len  = req->name_len;
+ 	memcpy(vol->name, req->name, vol->name_len);
+ 	vol->ubi = ubi;
++	device_set_node(&vol->dev, find_volume_fwnode(vol));
+ 
+ 	/*
+ 	 * Finish all pending erases because there may be some LEBs belonging
+@@ -605,6 +631,7 @@ int ubi_add_volume(struct ubi_device *ub
+ 	vol->dev.class = &ubi_class;
+ 	vol->dev.groups = volume_dev_groups;
+ 	dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id);
++	device_set_node(&vol->dev, find_volume_fwnode(vol));
+ 	err = device_register(&vol->dev);
+ 	if (err) {
+ 		cdev_del(&vol->cdev);
diff --git a/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch b/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch
new file mode 100644
index 0000000000..9e6fbea38c
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch
@@ -0,0 +1,243 @@
+From 7eb6666348f3f2d1f7308c712fa5903cbe189401 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 8 Jun 2023 17:22:04 +0100
+Subject: [PATCH 07/15] mtd: ubi: provide NVMEM layer over UBI volumes
+
+In an ideal world we would like UBI to be used where ever possible on a
+NAND chip. And with UBI support in ARM Trusted Firmware and U-Boot it
+is possible to achieve an (almost-)all-UBI flash layout. Hence the need
+for a way to also use UBI volumes to store board-level constants, such
+as MAC addresses and calibration data of wireless interfaces.
+
+Add UBI volume NVMEM driver module exposing UBI volumes as NVMEM
+providers. Allow UBI devices to have a "volumes" firmware subnode with
+volumes which may be compatible with "nvmem-cells".
+Access to UBI volumes via the NVMEM interface at this point is
+read-only, and it is slow, opening and closing the UBI volume for each
+access due to limitations of the NVMEM provider API.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/Kconfig  |  12 +++
+ drivers/mtd/ubi/Makefile |   1 +
+ drivers/mtd/ubi/nvmem.c  | 188 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 201 insertions(+)
+ create mode 100644 drivers/mtd/ubi/nvmem.c
+
+--- a/drivers/mtd/ubi/Kconfig
++++ b/drivers/mtd/ubi/Kconfig
+@@ -104,4 +104,16 @@ config MTD_UBI_BLOCK
+ 
+ 	   If in doubt, say "N".
+ 
++config MTD_UBI_NVMEM
++	tristate "UBI virtual NVMEM"
++	default n
++	depends on NVMEM
++	help
++	   This option enabled an additional driver exposing UBI volumes as NVMEM
++	   providers, intended for platforms where UBI is part of the firmware
++	   specification and used to store also e.g. MAC addresses or board-
++	   specific Wi-Fi calibration data.
++
++	   If in doubt, say "N".
++
+ endif # MTD_UBI
+--- a/drivers/mtd/ubi/Makefile
++++ b/drivers/mtd/ubi/Makefile
+@@ -7,3 +7,4 @@ ubi-$(CONFIG_MTD_UBI_FASTMAP) += fastmap
+ ubi-$(CONFIG_MTD_UBI_BLOCK) += block.o
+ 
+ obj-$(CONFIG_MTD_UBI_GLUEBI) += gluebi.o
++obj-$(CONFIG_MTD_UBI_NVMEM) += nvmem.o
+--- /dev/null
++++ b/drivers/mtd/ubi/nvmem.c
+@@ -0,0 +1,188 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ */
++
++/* UBI NVMEM provider */
++#include "ubi.h"
++#include <linux/nvmem-provider.h>
++#include <asm/div64.h>
++
++/* List of all NVMEM devices */
++static LIST_HEAD(nvmem_devices);
++static DEFINE_MUTEX(devices_mutex);
++
++struct ubi_nvmem {
++	struct nvmem_device *nvmem;
++	int ubi_num;
++	int vol_id;
++	int usable_leb_size;
++	struct list_head list;
++};
++
++static int ubi_nvmem_reg_read(void *priv, unsigned int from,
++			      void *val, size_t bytes)
++{
++	int err = 0, lnum = from, offs, bytes_left = bytes, to_read;
++	struct ubi_nvmem *unv = priv;
++	struct ubi_volume_desc *desc;
++
++	desc = ubi_open_volume(unv->ubi_num, unv->vol_id, UBI_READONLY);
++	if (IS_ERR(desc))
++		return PTR_ERR(desc);
++
++	offs = do_div(lnum, unv->usable_leb_size);
++	while (bytes_left) {
++		to_read = unv->usable_leb_size - offs;
++
++		if (to_read > bytes_left)
++			to_read = bytes_left;
++
++		err = ubi_read(desc, lnum, val, offs, to_read);
++		if (err)
++			break;
++
++		lnum += 1;
++		offs = 0;
++		bytes_left -= to_read;
++		val += to_read;
++	}
++	ubi_close_volume(desc);
++
++	if (err)
++		return err;
++
++	return bytes_left == 0 ? 0 : -EIO;
++}
++
++static int ubi_nvmem_add(struct ubi_volume_info *vi)
++{
++	struct device_node *np = dev_of_node(vi->dev);
++	struct nvmem_config config = {};
++	struct ubi_nvmem *unv;
++	int ret;
++
++	if (!np)
++		return 0;
++
++	if (!of_get_child_by_name(np, "nvmem-layout"))
++		return 0;
++
++	if (WARN_ON_ONCE(vi->usable_leb_size <= 0) ||
++	    WARN_ON_ONCE(vi->size <= 0))
++		return -EINVAL;
++
++	unv = kzalloc(sizeof(struct ubi_nvmem), GFP_KERNEL);
++	if (!unv)
++		return -ENOMEM;
++
++	config.id = NVMEM_DEVID_NONE;
++	config.dev = vi->dev;
++	config.name = dev_name(vi->dev);
++	config.owner = THIS_MODULE;
++	config.priv = unv;
++	config.reg_read = ubi_nvmem_reg_read;
++	config.size = vi->usable_leb_size * vi->size;
++	config.word_size = 1;
++	config.stride = 1;
++	config.read_only = true;
++	config.root_only = true;
++	config.ignore_wp = true;
++	config.of_node = np;
++
++	unv->ubi_num = vi->ubi_num;
++	unv->vol_id = vi->vol_id;
++	unv->usable_leb_size = vi->usable_leb_size;
++	unv->nvmem = nvmem_register(&config);
++	if (IS_ERR(unv->nvmem)) {
++		ret = dev_err_probe(vi->dev, PTR_ERR(unv->nvmem),
++				    "Failed to register NVMEM device\n");
++		kfree(unv);
++		return ret;
++	}
++
++	mutex_lock(&devices_mutex);
++	list_add_tail(&unv->list, &nvmem_devices);
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++}
++
++static void ubi_nvmem_remove(struct ubi_volume_info *vi)
++{
++	struct ubi_nvmem *unv_c, *unv = NULL;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry(unv_c, &nvmem_devices, list)
++		if (unv_c->ubi_num == vi->ubi_num && unv_c->vol_id == vi->vol_id) {
++			unv = unv_c;
++			break;
++		}
++
++	if (!unv) {
++		mutex_unlock(&devices_mutex);
++		return;
++	}
++
++	list_del(&unv->list);
++	mutex_unlock(&devices_mutex);
++	nvmem_unregister(unv->nvmem);
++	kfree(unv);
++}
++
++/**
++ * nvmem_notify - UBI notification handler.
++ * @nb: registered notifier block
++ * @l: notification type
++ * @ns_ptr: pointer to the &struct ubi_notification object
++ */
++static int nvmem_notify(struct notifier_block *nb, unsigned long l,
++			 void *ns_ptr)
++{
++	struct ubi_notification *nt = ns_ptr;
++
++	switch (l) {
++	case UBI_VOLUME_RESIZED:
++		ubi_nvmem_remove(&nt->vi);
++		fallthrough;
++	case UBI_VOLUME_ADDED:
++		ubi_nvmem_add(&nt->vi);
++		break;
++	case UBI_VOLUME_SHUTDOWN:
++		ubi_nvmem_remove(&nt->vi);
++		break;
++	default:
++		break;
++	}
++	return NOTIFY_OK;
++}
++
++static struct notifier_block nvmem_notifier = {
++	.notifier_call = nvmem_notify,
++};
++
++static int __init ubi_nvmem_init(void)
++{
++	return ubi_register_volume_notifier(&nvmem_notifier, 0);
++}
++
++static void __exit ubi_nvmem_exit(void)
++{
++	struct ubi_nvmem *unv, *tmp;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry_safe(unv, tmp, &nvmem_devices, list) {
++		nvmem_unregister(unv->nvmem);
++		list_del(&unv->list);
++		kfree(unv);
++	}
++	mutex_unlock(&devices_mutex);
++
++	ubi_unregister_volume_notifier(&nvmem_notifier);
++}
++
++module_init(ubi_nvmem_init);
++module_exit(ubi_nvmem_exit);
++MODULE_DESCRIPTION("NVMEM layer over UBI volumes");
++MODULE_AUTHOR("Daniel Golle");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch b/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch
new file mode 100644
index 0000000000..d0727faf3d
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch
@@ -0,0 +1,120 @@
+From 9ffc1d7d73609a89eb264d6066340f8b7b3b0ebe Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 21:19:45 +0100
+Subject: [PATCH 08/15] dt-bindings: block: add basic bindings for block
+ devices
+
+Add bindings for block devices which are used to allow referencing
+nvmem bits on them.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/block/block-device.yaml          | 22 ++++++++
+ .../devicetree/bindings/block/partition.yaml  | 50 +++++++++++++++++++
+ .../devicetree/bindings/block/partitions.yaml | 20 ++++++++
+ 3 files changed, 92 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/block/block-device.yaml
+ create mode 100644 Documentation/devicetree/bindings/block/partition.yaml
+ create mode 100644 Documentation/devicetree/bindings/block/partitions.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/block-device.yaml
+@@ -0,0 +1,22 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/block-device.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: block storage device
++
++description: |
++  This binding is generic and describes a block-oriented storage device.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  partitions:
++    $ref: /schemas/block/partitions.yaml
++
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++
++unevaluatedProperties: false
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/partition.yaml
+@@ -0,0 +1,50 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/partition.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Partition on a block device
++
++description: |
++  This binding describes a partition on a block device.
++  Partitions may be matched by a combination of partition number, name,
++  and UUID.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  $nodename:
++    pattern: '^block-partition-.+$'
++
++  partnum:
++    description:
++      Matches partition by number if present.
++
++  partname:
++    "$ref": "/schemas/types.yaml#/definitions/string"
++    description:
++      Matches partition by PARTNAME if present.
++
++  uuid:
++    "$ref": "/schemas/types.yaml#/definitions/string"
++    description:
++      Matches partition by PARTUUID if present.
++
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++    description:
++      This container may reference an NVMEM layout parser.
++
++anyOf:
++  - required:
++    - partnum
++
++  - required:
++    - partname
++
++  - required:
++    - uuid
++
++unevaluatedProperties: false
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/partitions.yaml
+@@ -0,0 +1,20 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/partitions.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Partitions on block devices
++
++description: |
++  This binding is generic and describes the content of the partitions container
++  node.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++patternProperties:
++  "^block-partition-.+$":
++    $ref: partition.yaml
++
++unevaluatedProperties: false
diff --git a/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch b/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch
new file mode 100644
index 0000000000..8aa5cba678
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch
@@ -0,0 +1,77 @@
+From 614f4f6fdda09e30ecf7ef6c8091579db15018cb Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Jul 2023 17:51:03 +0100
+Subject: [PATCH 09/15] block: partitions: populate fwnode
+
+Let block partitions to be represented by a firmware node and hence
+allow them to being referenced e.g. for use with blk-nvmem.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/partitions/core.c | 41 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+--- a/block/partitions/core.c
++++ b/block/partitions/core.c
+@@ -10,6 +10,8 @@
+ #include <linux/ctype.h>
+ #include <linux/vmalloc.h>
+ #include <linux/raid/detect.h>
++#include <linux/property.h>
++
+ #include "check.h"
+ 
+ static int (*check_part[])(struct parsed_partitions *) = {
+@@ -298,6 +300,43 @@ static ssize_t whole_disk_show(struct de
+ }
+ static DEVICE_ATTR(whole_disk, 0444, whole_disk_show, NULL);
+ 
++static struct fwnode_handle *find_partition_fwnode(struct block_device *bdev)
++{
++	struct fwnode_handle *fw_parts, *fw_part;
++	struct device *ddev = disk_to_dev(bdev->bd_disk);
++	const char *partname, *uuid;
++	u32 partno;
++
++	fw_parts = device_get_named_child_node(ddev, "partitions");
++	if (!fw_parts)
++		fw_parts = device_get_named_child_node(ddev->parent, "partitions");
++
++	if (!fw_parts)
++		return NULL;
++
++	fwnode_for_each_child_node(fw_parts, fw_part) {
++		if (!fwnode_property_read_string(fw_part, "uuid", &uuid) &&
++		    (!bdev->bd_meta_info || strncmp(uuid,
++						    bdev->bd_meta_info->uuid,
++						    PARTITION_META_INFO_UUIDLTH)))
++			continue;
++
++		if (!fwnode_property_read_string(fw_part, "partname", &partname) &&
++		    (!bdev->bd_meta_info || strncmp(partname,
++						    bdev->bd_meta_info->volname,
++						    PARTITION_META_INFO_VOLNAMELTH)))
++			continue;
++
++		if (!fwnode_property_read_u32(fw_part, "partno", &partno) &&
++		    bdev->bd_partno != partno)
++			continue;
++
++		return fw_part;
++	}
++
++	return NULL;
++}
++
+ /*
+  * Must be called either with open_mutex held, before a disk can be opened or
+  * after all disk users are gone.
+@@ -380,6 +419,8 @@ static struct block_device *add_partitio
+ 			goto out_put;
+ 	}
+ 
++	device_set_node(pdev, find_partition_fwnode(bdev));
++
+ 	/* delay uevent until 'holders' subdir is created */
+ 	dev_set_uevent_suppress(pdev, 1);
+ 	err = device_add(pdev);
diff --git a/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch b/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch
new file mode 100644
index 0000000000..4cbec14f5c
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch
@@ -0,0 +1,29 @@
+From 65f3ff9672ccd5ee78937047e7a2fc696eee1c8f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:07:16 +0100
+Subject: [PATCH 10/15] block: add new genhd flag GENHD_FL_NVMEM
+
+Add new flag to destinguish block devices which may act as an NVMEM
+provider.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ include/linux/blkdev.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/blkdev.h
++++ b/include/linux/blkdev.h
+@@ -87,11 +87,13 @@ struct partition_meta_info {
+  * ``GENHD_FL_NO_PART``: partition support is disabled.  The kernel will not
+  * scan for partitions from add_disk, and users can't add partitions manually.
+  *
++ * ``GENHD_FL_NVMEM``: the block device should be considered as NVMEM provider.
+  */
+ enum {
+ 	GENHD_FL_REMOVABLE			= 1 << 0,
+ 	GENHD_FL_HIDDEN				= 1 << 1,
+ 	GENHD_FL_NO_PART			= 1 << 2,
++	GENHD_FL_NVMEM				= 1 << 3,
+ };
+ 
+ enum {
diff --git a/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch b/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch
new file mode 100644
index 0000000000..e18b0c3a5c
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch
@@ -0,0 +1,235 @@
+From b9936aa8a3775c2027f655d91a206d0e6e1c7ec0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 11 Jul 2023 00:17:31 +0100
+Subject: [PATCH 11/15] block: implement NVMEM provider
+
+On embedded devices using an eMMC it is common that one or more partitions
+on the eMMC are used to store MAC addresses and Wi-Fi calibration EEPROM
+data. Allow referencing the partition in device tree for the kernel and
+Wi-Fi drivers accessing it via the NVMEM layer.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/Kconfig     |   9 +++
+ block/Makefile    |   1 +
+ block/blk-nvmem.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 196 insertions(+)
+ create mode 100644 block/blk-nvmem.c
+
+--- a/block/Kconfig
++++ b/block/Kconfig
+@@ -203,6 +203,15 @@ config BLK_INLINE_ENCRYPTION_FALLBACK
+ 	  by falling back to the kernel crypto API when inline
+ 	  encryption hardware is not present.
+ 
++config BLK_NVMEM
++	bool "Block device NVMEM provider"
++	depends on OF
++	depends on NVMEM
++	help
++	  Allow block devices (or partitions) to act as NVMEM prodivers,
++	  typically used with eMMC to store MAC addresses or Wi-Fi
++	  calibration data on embedded devices.
++
+ source "block/partitions/Kconfig"
+ 
+ config BLOCK_COMPAT
+--- a/block/Makefile
++++ b/block/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_BLK_DEV_ZONED)	+= blk-zoned
+ obj-$(CONFIG_BLK_WBT)		+= blk-wbt.o
+ obj-$(CONFIG_BLK_DEBUG_FS)	+= blk-mq-debugfs.o
+ obj-$(CONFIG_BLK_DEBUG_FS_ZONED)+= blk-mq-debugfs-zoned.o
++obj-$(CONFIG_BLK_NVMEM)		+= blk-nvmem.o
+ obj-$(CONFIG_BLK_SED_OPAL)	+= sed-opal.o
+ obj-$(CONFIG_BLK_PM)		+= blk-pm.o
+ obj-$(CONFIG_BLK_INLINE_ENCRYPTION)	+= blk-crypto.o blk-crypto-profile.o \
+--- /dev/null
++++ b/block/blk-nvmem.c
+@@ -0,0 +1,186 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * block device NVMEM provider
++ *
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ *
++ * Useful on devices using a partition on an eMMC for MAC addresses or
++ * Wi-Fi calibration EEPROM data.
++ */
++
++#include "blk.h"
++#include <linux/nvmem-provider.h>
++#include <linux/of.h>
++#include <linux/pagemap.h>
++#include <linux/property.h>
++
++/* List of all NVMEM devices */
++static LIST_HEAD(nvmem_devices);
++static DEFINE_MUTEX(devices_mutex);
++
++struct blk_nvmem {
++	struct nvmem_device *nvmem;
++	struct block_device *bdev;
++	struct list_head list;
++};
++
++static int blk_nvmem_reg_read(void *priv, unsigned int from,
++			      void *val, size_t bytes)
++{
++	unsigned long offs = from & ~PAGE_MASK, to_read;
++	pgoff_t f_index = from >> PAGE_SHIFT;
++	struct address_space *mapping;
++	struct blk_nvmem *bnv = priv;
++	size_t bytes_left = bytes;
++	struct folio *folio;
++	void *p;
++	int ret;
++
++	if (!bnv->bdev)
++		return -ENODEV;
++
++	if (!bnv->bdev->bd_disk)
++		return -EINVAL;
++
++	if (!bnv->bdev->bd_disk->fops)
++		return -EIO;
++
++	if (!bnv->bdev->bd_disk->fops->open)
++		return -EIO;
++
++	ret = bnv->bdev->bd_disk->fops->open(bnv->bdev, FMODE_READ);
++	if (ret)
++		return ret;
++
++	mapping = bnv->bdev->bd_inode->i_mapping;
++
++	while (bytes_left) {
++		folio = read_mapping_folio(mapping, f_index++, NULL);
++		if (IS_ERR(folio)) {
++			ret = PTR_ERR(folio);
++			goto err_release_bdev;
++		}
++		to_read = min_t(unsigned long, bytes_left, PAGE_SIZE - offs);
++		p = folio_address(folio) + offset_in_folio(folio, offs);
++		memcpy(val, p, to_read);
++		offs = 0;
++		bytes_left -= to_read;
++		val += to_read;
++		folio_put(folio);
++	}
++
++err_release_bdev:
++	bnv->bdev->bd_disk->fops->release(bnv->bdev->bd_disk, FMODE_READ);
++
++	return ret;
++}
++
++static int blk_nvmem_register(struct device *dev, struct class_interface *iface)
++{
++	struct device_node *np = dev_of_node(dev);
++	struct block_device *bdev = dev_to_bdev(dev);
++	struct nvmem_config config = {};
++	struct blk_nvmem *bnv;
++
++	/* skip devices which do not have a device tree node */
++	if (!np)
++		return 0;
++
++	/* skip devices without an nvmem layout defined */
++	if (!of_get_child_by_name(np, "nvmem-layout"))
++		return 0;
++
++	/*
++	 * skip devices which don't have GENHD_FL_NVMEM set
++	 *
++	 * This flag is used for mtdblock and ubiblock devices because
++	 * both, MTD and UBI already implement their own NVMEM provider.
++	 * To avoid registering multiple NVMEM providers for the same
++	 * device node, don't register the block NVMEM provider for them.
++	 */
++	if (!(bdev->bd_disk->flags & GENHD_FL_NVMEM))
++		return 0;
++
++	/*
++	 * skip block device too large to be represented as NVMEM devices
++	 * which are using an 'int' as address
++	 */
++	if (bdev_nr_bytes(bdev) > INT_MAX)
++		return -EFBIG;
++
++	bnv = kzalloc(sizeof(struct blk_nvmem), GFP_KERNEL);
++	if (!bnv)
++		return -ENOMEM;
++
++	config.id = NVMEM_DEVID_NONE;
++	config.dev = &bdev->bd_device;
++	config.name = dev_name(&bdev->bd_device);
++	config.owner = THIS_MODULE;
++	config.priv = bnv;
++	config.reg_read = blk_nvmem_reg_read;
++	config.size = bdev_nr_bytes(bdev);
++	config.word_size = 1;
++	config.stride = 1;
++	config.read_only = true;
++	config.root_only = true;
++	config.ignore_wp = true;
++	config.of_node = to_of_node(dev->fwnode);
++
++	bnv->bdev = bdev;
++	bnv->nvmem = nvmem_register(&config);
++	if (IS_ERR(bnv->nvmem)) {
++		dev_err_probe(&bdev->bd_device, PTR_ERR(bnv->nvmem),
++			      "Failed to register NVMEM device\n");
++
++		kfree(bnv);
++		return PTR_ERR(bnv->nvmem);
++	}
++
++	mutex_lock(&devices_mutex);
++	list_add_tail(&bnv->list, &nvmem_devices);
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++}
++
++static void blk_nvmem_unregister(struct device *dev, struct class_interface *iface)
++{
++	struct block_device *bdev = dev_to_bdev(dev);
++	struct blk_nvmem *bnv_c, *bnv = NULL;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry(bnv_c, &nvmem_devices, list) {
++		if (bnv_c->bdev == bdev) {
++			bnv = bnv_c;
++			break;
++		}
++	}
++
++	if (!bnv) {
++		mutex_unlock(&devices_mutex);
++		return;
++	}
++
++	list_del(&bnv->list);
++	mutex_unlock(&devices_mutex);
++	nvmem_unregister(bnv->nvmem);
++	kfree(bnv);
++}
++
++static struct class_interface blk_nvmem_bus_interface __refdata = {
++	.class = &block_class,
++	.add_dev = &blk_nvmem_register,
++	.remove_dev = &blk_nvmem_unregister,
++};
++
++static int __init blk_nvmem_init(void)
++{
++	int ret;
++
++	ret = class_interface_register(&blk_nvmem_bus_interface);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++device_initcall(blk_nvmem_init);
diff --git a/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch b/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch
new file mode 100644
index 0000000000..77c9bf91a5
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch
@@ -0,0 +1,74 @@
+From 86864bf8f40e84dc881c197ef470a88668329dbf Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 21:21:45 +0100
+Subject: [PATCH 12/15] dt-bindings: mmc: mmc-card: add block device nodes
+
+Add nodes representing the block devices exposed by an MMC device
+including an example involving nvmem-cells.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../devicetree/bindings/mmc/mmc-card.yaml     | 45 +++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mmc/mmc-card.yaml
++++ b/Documentation/devicetree/bindings/mmc/mmc-card.yaml
+@@ -26,6 +26,18 @@ properties:
+       Use this to indicate that the mmc-card has a broken hpi
+       implementation, and that hpi should not be used.
+ 
++  block:
++    $ref: /schemas/block/block-device.yaml#
++    description:
++      Represents the block storage provided by an SD card or the
++      main hardware partition of an eMMC.
++
++patternProperties:
++  '^boot[0-9]+':
++    $ref: /schemas/block/block-device.yaml#
++    description:
++      Represents a boot hardware partition on an eMMC.
++
+ required:
+   - compatible
+   - reg
+@@ -42,6 +54,39 @@ examples:
+             compatible = "mmc-card";
+             reg = <0>;
+             broken-hpi;
++
++            block {
++                partitions {
++                    cal_data: block-partition-rf {
++                        partnum = <3>;
++                        partname = "rf";
++
++                        nvmem-layout {
++                            compatible = "fixed-layout";
++                            #address-cells = <1>;
++                            #size-cells = <1>;
++
++                            eeprom@0 {
++                                reg = <0x0 0x1000>;
++                            };
++                        };
++                    };
++                };
++            };
++
++            boot1 {
++                nvmem-layout {
++                    compatible = "fixed-layout";
++                    #address-cells = <1>;
++                    #size-cells = <1>;
++
++                    macaddr: macaddr@a {
++                        compatible = "mac-base";
++                        reg = <0xa 0x6>;
++                        #nvmem-cell-cells = <1>;
++                    };
++                };
++            };
+         };
+     };
+ 
diff --git a/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch b/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch
new file mode 100644
index 0000000000..fada280437
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch
@@ -0,0 +1,23 @@
+From 644942a31719de674e2aa68f83d66bd8ae7e4fb7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:12:21 +0100
+Subject: [PATCH 13/15] mmc: core: set card fwnode_handle
+
+Set fwnode in case it isn't set yet and of_node is present.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/bus.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/mmc/core/bus.c
++++ b/drivers/mmc/core/bus.c
+@@ -363,6 +363,8 @@ int mmc_add_card(struct mmc_card *card)
+ 	mmc_add_card_debugfs(card);
+ #endif
+ 	card->dev.of_node = mmc_of_find_child_device(card->host, 0);
++	if (card->dev.of_node && !card->dev.fwnode)
++		card->dev.fwnode = &card->dev.of_node->fwnode;
+ 
+ 	device_enable_async_suspend(&card->dev);
+ 
diff --git a/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch b/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch
new file mode 100644
index 0000000000..a9e53f1155
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch
@@ -0,0 +1,39 @@
+From d9143f86330dd038fc48878558dd287ceee5d3d4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:13:04 +0100
+Subject: [PATCH 14/15] mmc: block: set fwnode of disk devices
+
+Set fwnode of disk devices to 'block', 'boot0' and 'boot1' subnodes of
+the mmc-card. This is done in preparation for having the eMMC act as
+NVMEM provider.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/block.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -2484,6 +2484,8 @@ static struct mmc_blk_data *mmc_blk_allo
+ 					      int area_type,
+ 					      unsigned int part_type)
+ {
++	struct fwnode_handle *fwnode;
++	struct device *ddev;
+ 	struct mmc_blk_data *md;
+ 	int devidx, ret;
+ 	char cap_str[10];
+@@ -2580,6 +2582,13 @@ static struct mmc_blk_data *mmc_blk_allo
+ 
+ 	blk_queue_write_cache(md->queue.queue, cache_enabled, fua_enabled);
+ 
++	ddev = disk_to_dev(md->disk);
++	fwnode = device_get_named_child_node(subname ? md->parent->parent :
++						       md->parent,
++					     subname ? subname : "block");
++	if (fwnode)
++		device_set_node(ddev, fwnode);
++
+ 	string_get_size((u64)size, 512, STRING_UNITS_2,
+ 			cap_str, sizeof(cap_str));
+ 	pr_info("%s: %s %s %s %s\n",
diff --git a/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch b/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch
new file mode 100644
index 0000000000..d76e7b2fe5
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch
@@ -0,0 +1,22 @@
+From 322035ab2b0113d98b6c0ea788d971e0df2952a4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 20 Jul 2023 17:36:44 +0100
+Subject: [PATCH 15/15] mmc: block: set GENHD_FL_NVMEM
+
+Set flag to consider MMC block devices as NVMEM providers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/block.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -2538,6 +2538,7 @@ static struct mmc_blk_data *mmc_blk_allo
+ 	md->disk->major	= MMC_BLOCK_MAJOR;
+ 	md->disk->minors = perdev_minors;
+ 	md->disk->first_minor = devidx * perdev_minors;
++	md->disk->flags = GENHD_FL_NVMEM;
+ 	md->disk->fops = &mmc_bdops;
+ 	md->disk->private_data = md;
+ 	md->parent = parent;
diff --git a/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
index 765eecd9d7..2eccb9d3bb 100644
--- a/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
+++ b/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
@@ -8,10 +8,11 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/build.c
 +++ b/drivers/mtd/ubi/build.c
-@@ -1212,6 +1212,73 @@ static struct mtd_info * __init open_mtd
- 	return mtd;
- }
+@@ -1263,6 +1263,74 @@ static struct mtd_notifier ubi_mtd_notif
+ 	.remove = ubi_notify_remove,
+ };
  
++
 +/*
 + * This function tries attaching mtd partitions named either "ubi" or "data"
 + * during boot.
@@ -79,10 +80,10 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	put_mtd_device(mtd);
 +}
 +
- static int __init ubi_init(void)
+ static int __init ubi_init_attach(void)
  {
  	int err, i, k;
-@@ -1296,6 +1363,12 @@ static int __init ubi_init(void)
+@@ -1313,6 +1381,12 @@ static int __init ubi_init_attach(void)
  		}
  	}
  
@@ -92,6 +93,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	    !ubi_is_module() && !mtd_devs)
 +		ubi_auto_attach();
 +
- 	err = ubiblock_init();
- 	if (err) {
- 		pr_err("UBI error: block: cannot initialize, error %d\n", err);
+ 	return 0;
+ 
+ out_detach:
diff --git a/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
index 17e8d8bedb..a43da2a572 100644
--- a/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
+++ b/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
@@ -8,8 +8,8 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/block.c
 +++ b/drivers/mtd/ubi/block.c
-@@ -653,6 +653,47 @@ static void __init ubiblock_create_from_
- 	}
+@@ -644,10 +644,47 @@ match_volume_desc(struct ubi_volume_info
+ 	return true;
  }
  
 +#define UBIFS_NODE_MAGIC  0x06101831
@@ -24,46 +24,54 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	return magic == UBIFS_NODE_MAGIC;
 +}
 +
-+static void __init ubiblock_create_auto_rootfs(void)
++static void __init ubiblock_create_auto_rootfs(struct ubi_volume_info *vi)
 +{
-+	int ubi_num, ret, is_ubifs;
++	int ret, is_ubifs;
 +	struct ubi_volume_desc *desc;
-+	struct ubi_volume_info vi;
 +
-+	for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) {
-+		desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY);
-+		if (IS_ERR(desc))
-+			desc = ubi_open_volume_nm(ubi_num, "fit", UBI_READONLY);;
++	if (strcmp(vi->name, "rootfs") &&
++	    strcmp(vi->name, "fit"))
++		return;
 +
-+		if (IS_ERR(desc))
-+			continue;
++	desc = ubi_open_volume(vi->ubi_num, vi->vol_id, UBI_READONLY);
++	if (IS_ERR(desc))
++		return;
 +
-+		ubi_get_volume_info(desc, &vi);
-+		is_ubifs = ubi_vol_is_ubifs(desc);
-+		ubi_close_volume(desc);
-+		if (is_ubifs)
-+			break;
++	is_ubifs = ubi_vol_is_ubifs(desc);
++	ubi_close_volume(desc);
++	if (is_ubifs)
++		return;
 +
-+		ret = ubiblock_create(&vi);
-+		if (ret)
-+			pr_err("UBI error: block: can't add '%s' volume, err=%d\n",
-+				vi.name, ret);
-+		/* always break if we get here */
-+		break;
-+	}
++	ret = ubiblock_create(vi);
++	if (ret)
++		pr_err("UBI error: block: can't add '%s' volume, err=%d\n",
++			vi->name, ret);
 +}
 +
- static void ubiblock_remove_all(void)
+ static void
+ ubiblock_create_from_param(struct ubi_volume_info *vi)
  {
- 	struct ubiblock *next;
-@@ -685,6 +726,10 @@ int __init ubiblock_init(void)
- 	 */
- 	ubiblock_create_from_param();
+ 	int i, ret = 0;
++	bool got_param = false;
+ 	struct ubiblock_param *p;
  
-+	/* auto-attach "rootfs" volume if existing and non-ubifs */
-+	if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))
-+		ubiblock_create_auto_rootfs();
-+
  	/*
- 	 * Block devices are only created upon user requests, so we ignore
- 	 * existing volumes.
+@@ -660,6 +697,7 @@ ubiblock_create_from_param(struct ubi_vo
+ 		if (!match_volume_desc(vi, p->name, p->ubi_num, p->vol_id))
+ 			continue;
+ 
++		got_param = true;
+ 		ret = ubiblock_create(vi);
+ 		if (ret) {
+ 			pr_err(
+@@ -668,6 +706,10 @@ ubiblock_create_from_param(struct ubi_vo
+ 		}
+ 		break;
+ 	}
++
++	/* auto-attach "rootfs" volume if existing and non-ubifs */
++	if (!got_param && IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))
++		ubiblock_create_auto_rootfs(vi);
+ }
+ 
+ static int ubiblock_notify(struct notifier_block *nb,
diff --git a/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
index e3493ef19e..5357c7e15d 100644
--- a/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
+++ b/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
@@ -8,7 +8,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/block.c
 +++ b/drivers/mtd/ubi/block.c
-@@ -42,6 +42,7 @@
+@@ -43,6 +43,7 @@
  #include <linux/scatterlist.h>
  #include <linux/idr.h>
  #include <asm/div64.h>
@@ -16,7 +16,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #include "ubi-media.h"
  #include "ubi.h"
-@@ -459,6 +460,15 @@ int ubiblock_create(struct ubi_volume_in
+@@ -460,6 +461,15 @@ int ubiblock_create(struct ubi_volume_in
  	dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)",
  		 dev->ubi_num, dev->vol_id, vi->name);
  	mutex_unlock(&devices_mutex);
diff --git a/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
index 413431755f..fc48146221 100644
--- a/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
+++ b/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
@@ -50,7 +50,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  		break;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -778,6 +778,7 @@ struct ubi_attach_info {
+@@ -780,6 +780,7 @@ struct ubi_attach_info {
  	int mean_ec;
  	uint64_t ec_sum;
  	int ec_count;
diff --git a/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch b/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch
new file mode 100644
index 0000000000..7ee66b318c
--- /dev/null
+++ b/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch
@@ -0,0 +1,732 @@
+From 6173a065cb395d4a9528c4e49810af127db68141 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 16 Nov 2022 12:49:52 +0000
+Subject: [PATCH 1/2] block: add uImage.FIT subimage block driver
+
+Add a small block driver which exposes filesystem sub-images contained
+in U-Boot uImage.FIT images as block devices.
+
+The uImage.FIT image has to be stored directly on a block device or
+partition, MTD device or partition, or UBI volume.
+
+The driver is intended for systems using the U-Boot bootloader and
+uses the root device hint left by the bootloader (or the user) in
+the 'chosen' section of the device-tree.
+
+Example:
+/dts-v1/;
+/ {
+        chosen {
+                rootdisk = <&mmc0_part3>;
+        };
+};
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                 |   6 +
+ drivers/block/Kconfig       |  12 +
+ drivers/block/Makefile      |   2 +
+ drivers/block/fitblk.c      | 658 ++++++++++++++++++++++++++++++++++++
+ drivers/block/open          |   4 +
+ include/uapi/linux/fitblk.h |  10 +
+ 6 files changed, 692 insertions(+)
+ create mode 100644 drivers/block/fitblk.c
+ create mode 100644 drivers/block/open
+ create mode 100644 include/uapi/linux/fitblk.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -21052,6 +21052,12 @@ F:	Documentation/filesystems/ubifs-authe
+ F:	Documentation/filesystems/ubifs.rst
+ F:	fs/ubifs/
+ 
++U-BOOT UIMAGE.FIT PARSER
++M:	Daniel Golle <daniel@makrotopia.org>
++L:	linux-block@vger.kernel.org
++S:	Maintained
++F:	drivers/block/fitblk.c
++
+ UBLK USERSPACE BLOCK DRIVER
+ M:	Ming Lei <ming.lei@redhat.com>
+ L:	linux-block@vger.kernel.org
+--- a/drivers/block/Kconfig
++++ b/drivers/block/Kconfig
+@@ -383,6 +383,18 @@ config VIRTIO_BLK
+ 	  This is the virtual block driver for virtio.  It can be used with
+           QEMU based VMMs (like KVM or Xen).  Say Y or M.
+ 
++config UIMAGE_FIT_BLK
++	bool "uImage.FIT block driver"
++	help
++	  This driver allows using filesystems contained in uImage.FIT images
++	  by mapping them as block devices.
++
++	  It can currently not be built as a module due to libfdt symbols not
++	  being exported.
++
++	  Say Y if you want to mount filesystems sub-images of a uImage.FIT
++	  stored in a block device partition, mtdblock or ubiblock device.
++
+ config BLK_DEV_RBD
+ 	tristate "Rados block device (RBD)"
+ 	depends on INET && BLOCK
+--- a/drivers/block/Makefile
++++ b/drivers/block/Makefile
+@@ -39,4 +39,6 @@ obj-$(CONFIG_BLK_DEV_NULL_BLK)	+= null_b
+ 
+ obj-$(CONFIG_BLK_DEV_UBLK)			+= ublk_drv.o
+ 
++obj-$(CONFIG_UIMAGE_FIT_BLK)	+= fitblk.o
++
+ swim_mod-y	:= swim.o swim_asm.o
+--- /dev/null
++++ b/drivers/block/fitblk.c
+@@ -0,0 +1,635 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * uImage.FIT virtual block device driver.
++ *
++ * Copyright (C) 2023 Daniel Golle
++ * Copyright (C) 2007 Nick Piggin
++ * Copyright (C) 2007 Novell Inc.
++ *
++ * Initially derived from drivers/block/brd.c which is in parts derived from
++ * drivers/block/rd.c, and drivers/block/loop.c, copyright of their respective
++ * owners.
++ *
++ * uImage.FIT headers extracted from Das U-Boot
++ *  (C) Copyright 2008 Semihalf
++ *  (C) Copyright 2000-2005
++ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ */
++
++#include <linux/init.h>
++#include <linux/initrd.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/major.h>
++#include <linux/blkdev.h>
++#include <linux/blkpg.h>
++#include <linux/blk-mq.h>
++#include <linux/ctype.h>
++#include <linux/hdreg.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_fdt.h>
++#include <linux/pagemap.h>
++#include <linux/platform_device.h>
++#include <linux/property.h>
++#include <linux/refcount.h>
++#include <linux/task_work.h>
++#include <linux/types.h>
++#include <linux/libfdt.h>
++#include <linux/mtd/mtd.h>
++#include <linux/root_dev.h>
++#include <uapi/linux/fitblk.h>
++
++#define FIT_DEVICE_PREFIX	"fit"
++
++/* maximum number of pages used for the uImage.FIT index structure */
++#define FIT_MAX_PAGES		1024
++
++/* minimum free sectors to map as read-write "remainder" volume */
++#define MIN_FREE_SECT		16
++
++/* maximum number of mapped loadables */
++#define MAX_FIT_LOADABLES	16
++
++/* constants for uImage.FIT structrure traversal */
++#define FIT_IMAGES_PATH		"/images"
++#define FIT_CONFS_PATH		"/configurations"
++
++/* hash/signature/key node */
++#define FIT_HASH_NODENAME	"hash"
++#define FIT_ALGO_PROP		"algo"
++#define FIT_VALUE_PROP		"value"
++#define FIT_IGNORE_PROP		"uboot-ignore"
++#define FIT_SIG_NODENAME	"signature"
++#define FIT_KEY_REQUIRED	"required"
++#define FIT_KEY_HINT		"key-name-hint"
++
++/* cipher node */
++#define FIT_CIPHER_NODENAME	"cipher"
++#define FIT_ALGO_PROP		"algo"
++
++/* image node */
++#define FIT_DATA_PROP		"data"
++#define FIT_DATA_POSITION_PROP	"data-position"
++#define FIT_DATA_OFFSET_PROP	"data-offset"
++#define FIT_DATA_SIZE_PROP	"data-size"
++#define FIT_TIMESTAMP_PROP	"timestamp"
++#define FIT_DESC_PROP		"description"
++#define FIT_ARCH_PROP		"arch"
++#define FIT_TYPE_PROP		"type"
++#define FIT_OS_PROP		"os"
++#define FIT_COMP_PROP		"compression"
++#define FIT_ENTRY_PROP		"entry"
++#define FIT_LOAD_PROP		"load"
++
++/* configuration node */
++#define FIT_KERNEL_PROP		"kernel"
++#define FIT_FILESYSTEM_PROP	"filesystem"
++#define FIT_RAMDISK_PROP	"ramdisk"
++#define FIT_FDT_PROP		"fdt"
++#define FIT_LOADABLE_PROP	"loadables"
++#define FIT_DEFAULT_PROP	"default"
++#define FIT_SETUP_PROP		"setup"
++#define FIT_FPGA_PROP		"fpga"
++#define FIT_FIRMWARE_PROP	"firmware"
++#define FIT_STANDALONE_PROP	"standalone"
++
++/* fitblk driver data */
++static const char *_fitblk_claim_ptr = "I belong to fitblk";
++static const char *ubootver;
++struct device_node *rootdisk;
++static struct platform_device *pdev;
++static LIST_HEAD(fitblk_devices);
++static DEFINE_MUTEX(devices_mutex);
++refcount_t num_devs;
++
++struct fitblk {
++	struct platform_device	*pdev;
++	struct block_device	*lower_bdev;
++	sector_t		start_sect;
++	struct gendisk		*disk;
++	struct work_struct	remove_work;
++	struct list_head	list;
++	bool			dead;
++};
++
++static int fitblk_open(struct block_device *bdev, fmode_t mode)
++{
++	struct fitblk *fitblk = bdev->bd_disk->private_data;
++
++	if (fitblk->dead)
++		return -ENOENT;
++
++	return 0;
++}
++
++static void fitblk_release(struct gendisk *disk, fmode_t mode)
++{
++	return;
++}
++
++static void fitblk_submit_bio(struct bio *orig_bio)
++{
++	struct bio *bio = orig_bio;
++	struct fitblk *fitblk = bio->bi_bdev->bd_disk->private_data;
++
++	if (fitblk->dead)
++		return;
++
++	/* mangle bio and re-submit */
++	while (bio) {
++		bio->bi_iter.bi_sector += fitblk->start_sect;
++		bio->bi_bdev = fitblk->lower_bdev;
++		bio = bio->bi_next;
++	}
++	submit_bio(orig_bio);
++}
++
++static void fitblk_remove(struct fitblk *fitblk)
++{
++	blk_mark_disk_dead(fitblk->disk);
++	mutex_lock(&devices_mutex);
++	fitblk->dead = true;
++	list_del(&fitblk->list);
++	mutex_unlock(&devices_mutex);
++
++	schedule_work(&fitblk->remove_work);
++}
++
++static int fitblk_ioctl(struct block_device *bdev, fmode_t mode,
++			unsigned int cmd, unsigned long arg)
++{
++	struct fitblk *fitblk = bdev->bd_disk->private_data;
++
++	if (!capable(CAP_SYS_ADMIN))
++		return -EACCES;
++
++	if (fitblk->dead)
++		return -ENOENT;
++
++	switch (cmd) {
++	case FITBLK_RELEASE:
++		fitblk_remove(fitblk);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct block_device_operations fitblk_fops = {
++	.owner		= THIS_MODULE,
++	.ioctl		= fitblk_ioctl,
++	.open		= fitblk_open,
++	.release	= fitblk_release,
++	.submit_bio	= fitblk_submit_bio,
++};
++
++static void fitblk_purge(struct work_struct *work)
++{
++	struct fitblk *fitblk = container_of(work, struct fitblk, remove_work);
++
++	//del_gendisk(fitblk->disk); // causes crash, not doing it doesn't matter
++	refcount_dec(&num_devs);
++	platform_device_del(fitblk->pdev);
++	platform_device_put(fitblk->pdev);
++
++	if (refcount_dec_if_one(&num_devs)) {
++		sysfs_remove_link(&pdev->dev.kobj, "lower_dev");
++		blkdev_put(fitblk->lower_bdev, FMODE_READ | FMODE_EXCL);
++	}
++
++	kfree(fitblk);
++}
++
++static int add_fit_subimage_device(struct block_device *lower_bdev,
++				   unsigned int slot, sector_t start_sect,
++				   sector_t nr_sect, bool readonly)
++{
++	struct fitblk *fitblk;
++	struct gendisk *disk;
++	int err;
++
++	mutex_lock(&devices_mutex);
++	if (!refcount_inc_not_zero(&num_devs))
++		return -EBADF;
++
++	fitblk = kzalloc(sizeof(struct fitblk), GFP_KERNEL);
++	if (!fitblk) {
++		err = -ENOMEM;
++		goto out_unlock;
++	}
++
++	fitblk->lower_bdev = lower_bdev;
++	fitblk->start_sect = start_sect;
++	INIT_WORK(&fitblk->remove_work, fitblk_purge);
++
++	disk = blk_alloc_disk(NUMA_NO_NODE);
++	if (!disk) {
++		err = -ENOMEM;
++		goto out_free_fitblk;
++	}
++
++	disk->first_minor = 0;
++	disk->flags = lower_bdev->bd_disk->flags | GENHD_FL_NO_PART;
++	disk->fops = &fitblk_fops;
++	disk->private_data = fitblk;
++	if (readonly) {
++		set_disk_ro(disk, 1);
++		snprintf(disk->disk_name, sizeof(disk->disk_name), FIT_DEVICE_PREFIX "%u", slot);
++	} else {
++		strcpy(disk->disk_name, FIT_DEVICE_PREFIX "rw");
++	}
++
++	set_capacity(disk, nr_sect);
++
++	disk->queue->queue_flags = lower_bdev->bd_disk->queue->queue_flags;
++	memcpy(&disk->queue->limits, &lower_bdev->bd_disk->queue->limits,
++	       sizeof(struct queue_limits));
++
++	fitblk->disk = disk;
++	fitblk->pdev = platform_device_alloc(disk->disk_name, PLATFORM_DEVID_NONE);
++	if (!fitblk->pdev) {
++		err = -ENOMEM;
++		goto out_cleanup_disk;
++	}
++
++	fitblk->pdev->dev.parent = &pdev->dev;
++	err = platform_device_add(fitblk->pdev);
++	if (err)
++		goto out_put_pdev;
++
++	err = device_add_disk(&fitblk->pdev->dev, disk, NULL);
++	if (err)
++		goto out_del_pdev;
++
++	if (!ROOT_DEV)
++		ROOT_DEV = disk->part0->bd_dev;
++
++	list_add_tail(&fitblk->list, &fitblk_devices);
++
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++
++out_del_pdev:
++	platform_device_del(fitblk->pdev);
++out_put_pdev:
++	platform_device_put(fitblk->pdev);
++out_cleanup_disk:
++	put_disk(disk);
++out_free_fitblk:
++	kfree(fitblk);
++out_unlock:
++	refcount_dec(&num_devs);
++	mutex_unlock(&devices_mutex);
++	return err;
++}
++
++static int parse_fit_on_dev(struct device *dev)
++{
++	struct block_device *bdev;
++	struct address_space *mapping;
++	struct folio *folio;
++	pgoff_t f_index = 0;
++	size_t bytes_left, bytes_to_copy;
++	void *pre_fit, *fit, *fit_c;
++	u64 dsize, dsectors, imgmaxsect = 0;
++	u32 size, image_pos, image_len;
++	const __be32 *image_offset_be, *image_len_be, *image_pos_be;
++	int ret = 0, node, images, config;
++	const char *image_name, *image_type, *image_description,
++		*config_default, *config_description, *config_loadables;
++	u32 image_name_len, image_type_len, image_description_len,
++		bootconf_len, config_default_len, config_description_len,
++		config_loadables_len;
++	sector_t start_sect, nr_sects;
++	struct device_node *np = NULL;
++	const char *bootconf_c;
++	const char *loadable;
++	char *bootconf = NULL, *bootconf_term;
++	bool found;
++	int loadables_rem_len, loadable_len;
++	u16 loadcnt;
++	unsigned int slot = 0;
++
++	/* Exclusive open the block device to receive holder notifications */
++	bdev = blkdev_get_by_dev(dev->devt, FMODE_READ | FMODE_EXCL, &_fitblk_claim_ptr);
++	if (!bdev)
++		return -ENODEV;
++
++	if (IS_ERR(bdev))
++		return PTR_ERR(bdev);
++
++	mapping = bdev->bd_inode->i_mapping;
++
++	/* map first page */
++	folio = read_mapping_folio(mapping, f_index++, NULL);
++	if (IS_ERR(folio)) {
++		ret = PTR_ERR(folio);
++		goto out_blkdev;
++	}
++	pre_fit = folio_address(folio) + offset_in_folio(folio, 0);
++
++	/* uImage.FIT is based on flattened device tree structure */
++	if (fdt_check_header(pre_fit)) {
++		ret = -EINVAL;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	size = fdt_totalsize(pre_fit);
++
++	if (size > PAGE_SIZE * FIT_MAX_PAGES) {
++		ret = -EOPNOTSUPP;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	/* acquire disk size */
++	dsectors = bdev_nr_sectors(bdev);
++	dsize = dsectors << SECTOR_SHIFT;
++
++	/* abort if FIT structure is larger than disk or partition size */
++	if (size >= dsize) {
++		ret = -EFBIG;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	fit = kmalloc(size, GFP_KERNEL);
++	if (!fit) {
++		ret = -ENOMEM;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	bytes_left = size;
++	fit_c = fit;
++	while (bytes_left > 0) {
++		bytes_to_copy = min(bytes_left, folio_size(folio) - offset_in_folio(folio, 0));
++		memcpy(fit_c, pre_fit, bytes_to_copy);
++		fit_c += bytes_to_copy;
++		bytes_left -= bytes_to_copy;
++		if (bytes_left) {
++			folio_put(folio);
++			folio = read_mapping_folio(mapping, f_index++, NULL);
++			if (IS_ERR(folio)) {
++				ret = PTR_ERR(folio);
++				goto out_blkdev;
++			};
++			pre_fit = folio_address(folio) + offset_in_folio(folio, 0);
++		}
++	}
++	folio_put(folio);
++
++	/* set boot config node name U-Boot may have added to the device tree */
++	np = of_find_node_by_path("/chosen");
++	if (np) {
++		bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
++		if (bootconf_c && bootconf_len)
++			bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
++	}
++
++	if (bootconf) {
++		bootconf_term = strchr(bootconf, '#');
++		if (bootconf_term)
++			*bootconf_term = '\0';
++	}
++
++	/* find configuration path in uImage.FIT */
++	config = fdt_path_offset(fit, FIT_CONFS_PATH);
++	if (config < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n",
++			FIT_CONFS_PATH, config);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* get default configuration node name */
++	config_default =
++		fdt_getprop(fit, config, FIT_DEFAULT_PROP, &config_default_len);
++
++	/* make sure we got either default or selected boot config node name */
++	if (!config_default && !bootconf) {
++		pr_err("FIT: Cannot find default configuration\n");
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* find selected boot config node, fallback on default config node */
++	node = fdt_subnode_offset(fit, config, bootconf ?: config_default);
++	if (node < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n",
++			bootconf ?: config_default, node);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	pr_info("FIT: Detected U-Boot %s\n", ubootver);
++
++	/* get selected configuration data */
++	config_description =
++		fdt_getprop(fit, node, FIT_DESC_PROP, &config_description_len);
++	config_loadables = fdt_getprop(fit, node, FIT_LOADABLE_PROP,
++				       &config_loadables_len);
++
++	pr_info("FIT: %s configuration: \"%.*s\"%s%.*s%s\n",
++		bootconf ? "Selected" : "Default",
++		bootconf ? bootconf_len : config_default_len,
++		bootconf ?: config_default,
++		config_description ? " (" : "",
++		config_description ? config_description_len : 0,
++		config_description ?: "",
++		config_description ? ")" : "");
++
++	if (!config_loadables || !config_loadables_len) {
++		pr_err("FIT: No loadables configured in \"%s\"\n",
++			bootconf ?: config_default);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* get images path in uImage.FIT */
++	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
++	if (images < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n", FIT_IMAGES_PATH, images);
++		ret = -EINVAL;
++		goto out_bootconf;
++	}
++
++	/* iterate over images in uImage.FIT */
++	fdt_for_each_subnode(node, fit, images) {
++		image_name = fdt_get_name(fit, node, &image_name_len);
++		image_type = fdt_getprop(fit, node, FIT_TYPE_PROP, &image_type_len);
++		image_offset_be = fdt_getprop(fit, node, FIT_DATA_OFFSET_PROP, NULL);
++		image_pos_be = fdt_getprop(fit, node, FIT_DATA_POSITION_PROP, NULL);
++		image_len_be = fdt_getprop(fit, node, FIT_DATA_SIZE_PROP, NULL);
++
++		if (!image_name || !image_type || !image_len_be ||
++		    !image_name_len || !image_type_len)
++			continue;
++
++		image_len = be32_to_cpu(*image_len_be);
++		if (!image_len)
++			continue;
++
++		if (image_offset_be)
++			image_pos = be32_to_cpu(*image_offset_be) + size;
++		else if (image_pos_be)
++			image_pos = be32_to_cpu(*image_pos_be);
++		else
++			continue;
++
++		image_description = fdt_getprop(fit, node, FIT_DESC_PROP,
++						&image_description_len);
++
++		pr_info("FIT: %16s sub-image 0x%08x..0x%08x \"%.*s\"%s%.*s%s\n",
++			image_type, image_pos, image_pos + image_len - 1,
++			image_name_len, image_name, image_description ? " (" : "",
++			image_description ? image_description_len : 0,
++			image_description ?: "", image_description ? ") " : "");
++
++		/* only 'filesystem' images should be mapped as partitions */
++		if (strncmp(image_type, FIT_FILESYSTEM_PROP, image_type_len))
++			continue;
++
++		/* check if sub-image is part of configured loadables */
++		found = false;
++		loadable = config_loadables;
++		loadables_rem_len = config_loadables_len;
++		for (loadcnt = 0; loadables_rem_len > 1 &&
++				  loadcnt < MAX_FIT_LOADABLES; ++loadcnt) {
++			loadable_len =
++				strnlen(loadable, loadables_rem_len - 1) + 1;
++			loadables_rem_len -= loadable_len;
++			if (!strncmp(image_name, loadable, loadable_len)) {
++				found = true;
++				break;
++			}
++			loadable += loadable_len;
++		}
++		if (!found)
++			continue;
++
++		if (image_pos % (1 << PAGE_SHIFT)) {
++			dev_err(dev, "FIT: image %.*s start not aligned to page boundaries, skipping\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		if (image_len % (1 << PAGE_SHIFT)) {
++			dev_err(dev, "FIT: sub-image %.*s end not aligned to page boundaries, skipping\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		start_sect = image_pos >> SECTOR_SHIFT;
++		nr_sects = image_len >> SECTOR_SHIFT;
++		imgmaxsect = max_t(sector_t, imgmaxsect, start_sect + nr_sects);
++
++		if (start_sect + nr_sects > dsectors) {
++			dev_err(dev, "FIT: sub-image %.*s disk access beyond EOD\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		if (!slot) {
++			ret = sysfs_create_link_nowarn(&pdev->dev.kobj, bdev_kobj(bdev), "lower_dev");
++			if (ret && ret != -EEXIST)
++				goto out_bootconf;
++
++			ret = 0;
++		}
++
++		add_fit_subimage_device(bdev, slot++, start_sect, nr_sects, true);
++	}
++
++	if (!found || !slot)
++		goto out_bootconf;
++
++	dev_info(dev, "mapped %u uImage.FIT filesystem sub-image%s as /dev/fit%s%u%s\n",
++		 slot, (slot > 1)?"s":"", (slot > 1)?"[0...":"", slot - 1,
++		 (slot > 1)?"]":"");
++
++	/* in case uImage.FIT is stored in a partition, map the remaining space */
++	if (!bdev->bd_read_only && bdev_is_partition(bdev) &&
++	    (imgmaxsect + MIN_FREE_SECT) < dsectors) {
++		add_fit_subimage_device(bdev, slot++, imgmaxsect,
++					dsectors - imgmaxsect, false);
++		dev_info(dev, "mapped remaing space as /dev/fitrw\n");
++	}
++
++out_bootconf:
++	kfree(bootconf);
++	kfree(fit);
++out_blkdev:
++	if (!found || ret)
++		blkdev_put(bdev, FMODE_READ | FMODE_EXCL);
++
++	return ret;
++}
++
++static int fitblk_match_of_node(struct device *dev, const void *np)
++{
++	int ret;
++
++	ret = device_match_of_node(dev, np);
++	if (ret)
++		return ret;
++
++	/*
++	 * To match ubiblock and mtdblock devices by their parent ubi
++	 * or mtd device, also consider block device parent
++	 */
++	if (!dev->parent)
++		return 0;
++
++	return device_match_of_node(dev->parent, np);
++}
++
++static int fitblk_probe(struct platform_device *pdev)
++{
++	struct device *dev;
++
++	dev = class_find_device(&block_class, NULL, rootdisk, fitblk_match_of_node);
++	if (!dev)
++		return -EPROBE_DEFER;
++
++	return parse_fit_on_dev(dev);
++}
++
++static struct platform_driver fitblk_driver = {
++	.probe		= fitblk_probe,
++	.driver		= {
++		.name   = "fitblk",
++		.owner   = THIS_MODULE,
++	},
++};
++
++static int __init fitblk_init(void)
++{
++	/* detect U-Boot firmware */
++	ubootver = of_get_property(of_chosen, "u-boot,version", NULL);
++	if (!ubootver)
++		return 0;
++
++	/* parse 'rootdisk' property phandle */
++	rootdisk = of_parse_phandle(of_chosen, "rootdisk", 0);
++	if (!rootdisk)
++		return 0;
++
++	if (platform_driver_register(&fitblk_driver))
++		return -ENODEV;
++
++	refcount_set(&num_devs, 1);
++	pdev = platform_device_register_simple("fitblk", -1, NULL, 0);
++	if (IS_ERR(pdev))
++		return PTR_ERR(pdev);
++
++	return 0;
++}
++device_initcall(fitblk_init);
+--- /dev/null
++++ b/include/uapi/linux/fitblk.h
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
++#ifndef _UAPI_LINUX_FITBLK_H
++#define _UAPI_LINUX_FITBLK_H
++
++/*
++ * IOCTL commands --- we will commandeer 0x46 ('F')
++ */
++#define FITBLK_RELEASE             0x4600
++
++#endif /* _UAPI_LINUX_FITBLK_H */
diff --git a/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch b/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch
new file mode 100644
index 0000000000..685a5f9da5
--- /dev/null
+++ b/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch
@@ -0,0 +1,25 @@
+From 5ede3f8aed9a1a579bf7304142600d1f3500add9 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 12 Jun 2023 03:58:42 +0100
+Subject: [PATCH 2/2] init: bypass device lookup for /dev/fit* rootfs
+
+Allow 'rootwait' as /dev/fit* can show up late if the underlaying
+device is probed late.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ init/do_mounts.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/init/do_mounts.c
++++ b/init/do_mounts.c
+@@ -645,7 +645,8 @@ void __init prepare_namespace(void)
+ 
+ 	if (saved_root_name[0]) {
+ 		root_device_name = saved_root_name;
+-		if (!strncmp(root_device_name, "mtd", 3) ||
++		if (!strncmp(root_device_name, "fit", 3) ||
++		    !strncmp(root_device_name, "mtd", 3) ||
+ 		    !strncmp(root_device_name, "ubi", 3)) {
+ 			mount_block_root(root_device_name, root_mountflags);
+ 			goto out;
diff --git a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
index be28fdc803..842fef3a9c 100644
--- a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
+++ b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4942,6 +4942,8 @@ static int mtk_probe(struct platform_dev
+@@ -4941,6 +4941,8 @@ static int mtk_probe(struct platform_dev
  	 * for NAPI to work
  	 */
  	init_dummy_netdev(&eth->dummy_dev);
diff --git a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
index 0c88109192..e4937a1df1 100644
--- a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
+++ b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
@@ -11,7 +11,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1852,6 +1852,9 @@ void phy_detach(struct phy_device *phyde
+@@ -1850,6 +1850,9 @@ void phy_detach(struct phy_device *phyde
  	struct module *ndev_owner = NULL;
  	struct mii_bus *bus;
  
diff --git a/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch b/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch
new file mode 100644
index 0000000000..70724cb3a2
--- /dev/null
+++ b/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch
@@ -0,0 +1,24 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 14 Feb 2024 15:24:41 +0100
+Subject: [PATCH] netfilter: nf_tables: fix bidirectional offload regression
+
+Commit 8f84780b84d6 ("netfilter: flowtable: allow unidirectional rules")
+made unidirectional flow offload possible, while completely ignoring (and
+breaking) bidirectional flow offload for nftables.
+Add the missing flag that was left out as an exercise for the reader :)
+
+Cc: Vlad Buslov <vladbu@nvidia.com>
+Fixes: 8f84780b84d6 ("netfilter: flowtable: allow unidirectional rules")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/netfilter/nft_flow_offload.c
++++ b/net/netfilter/nft_flow_offload.c
+@@ -357,6 +357,7 @@ static void nft_flow_offload_eval(const
+ 		ct->proto.tcp.seen[1].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;
+ 	}
+ 
++	__set_bit(NF_FLOW_HW_BIDIRECTIONAL, &flow->flags);
+ 	ret = flow_offload_add(flowtable, flow);
+ 	if (ret < 0)
+ 		goto err_flow_add;
diff --git a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
index fe8841dd3e..a1cc109050 100644
--- a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
+++ b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
@@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1563,12 +1563,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1562,12 +1562,28 @@ static void mtk_wake_queue(struct mtk_et
  	}
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	bool gso = false;
  	int tx_num;
  
-@@ -1590,6 +1606,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1589,6 +1605,18 @@ static netdev_tx_t mtk_start_xmit(struct
  		return NETDEV_TX_BUSY;
  	}
  
@@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* TSO: fill MSS info in tcp checksum field */
  	if (skb_is_gso(skb)) {
  		if (skb_cow_head(skb, 0)) {
-@@ -1605,8 +1633,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1604,8 +1632,14 @@ static netdev_tx_t mtk_start_xmit(struct
  		}
  	}
  
diff --git a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
index 757d2edb2c..0a49c75b00 100644
--- a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
+++ b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	switch (speed) {
  	case SPEED_2500:
  	case SPEED_1000:
-@@ -3349,6 +3350,9 @@ found:
+@@ -3348,6 +3349,9 @@ found:
  	if (dp->index >= MTK_QDMA_NUM_QUEUES)
  		return NOTIFY_DONE;
  
diff --git a/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
index 23daa29998..afe561ab31 100644
--- a/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
+++ b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
@@ -1,8 +1,8 @@
-From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001
+From 91bda2f441f9e37273922028ffc48ce8e91bf5bd Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 22 Aug 2023 19:04:42 +0100
-Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes
- modes for MT7988
+Date: Tue, 12 Dec 2023 03:51:14 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
+ MT7988
 
 MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
 connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
@@ -18,50 +18,11 @@ modes.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 ---
- drivers/net/ethernet/mediatek/Kconfig        |  16 +
- drivers/net/ethernet/mediatek/Makefile       |   1 +
- drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 182 ++++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 232 ++++++-
- drivers/net/ethernet/mediatek/mtk_usxgmii.c  | 692 +++++++++++++++++++
- 6 files changed, 1215 insertions(+), 31 deletions(-)
- create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 291 +++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 107 ++++++-
+ 3 files changed, 469 insertions(+), 51 deletions(-)
 
---- a/drivers/net/ethernet/mediatek/Kconfig
-+++ b/drivers/net/ethernet/mediatek/Kconfig
-@@ -25,6 +25,22 @@ config NET_MEDIATEK_SOC
- 	  This driver supports the gigabit ethernet MACs in the
- 	  MediaTek SoC family.
- 
-+config NET_MEDIATEK_SOC_USXGMII
-+	bool "Support USXGMII SerDes on MT7988"
-+	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+	def_bool NET_MEDIATEK_SOC != n
-+	help
-+	  Include support for 10GE SerDes which can be found on MT7988.
-+	  If this kernel should run on SoCs with 10 GBit/s Ethernet you
-+	  will need to select this option to use GMAC2 and GMAC3 with
-+	  external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII
-+	  interface modes.
-+
-+	  Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS
-+	  unit (MediaTek LynxI) in MT7988 is connected via the new 10GE
-+	  SerDes, you will also need to select this option in case you
-+	  want to use any of those SerDes modes.
-+
- config NET_MEDIATEK_STAR_EMAC
- 	tristate "MediaTek STAR Ethernet MAC support"
- 	select PHYLIB
---- a/drivers/net/ethernet/mediatek/Makefile
-+++ b/drivers/net/ethernet/mediatek/Makefile
-@@ -5,6 +5,7 @@
- 
- obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
- mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
- ifdef CONFIG_DEBUG_FS
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
@@ -242,14 +203,31 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  	/* Setup proper MUXes along the path */
  	return mtk_eth_mux_setup(eth, path);
-@@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
- 	/* Setup proper MUXes along the path */
- 	return mtk_eth_mux_setup(eth, path);
- }
--
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -475,6 +475,30 @@ static void mtk_setup_bridge_switch(stru
+@@ -21,6 +21,8 @@
+ #include <linux/pinctrl/devinfo.h>
+ #include <linux/phylink.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/phy/phy.h>
+ #include <linux/jhash.h>
+ #include <linux/bitfield.h>
+ #include <net/dsa.h>
+@@ -258,12 +260,8 @@ static const char * const mtk_clks_sourc
+ 	"ethwarp_wocpu2",
+ 	"ethwarp_wocpu1",
+ 	"ethwarp_wocpu0",
+-	"top_usxgmii0_sel",
+-	"top_usxgmii1_sel",
+ 	"top_sgm0_sel",
+ 	"top_sgm1_sel",
+-	"top_xfi_phy0_xtal_sel",
+-	"top_xfi_phy1_xtal_sel",
+ 	"top_eth_gmii_sel",
+ 	"top_eth_refck_50m_sel",
+ 	"top_eth_sys_200m_sel",
+@@ -475,6 +473,30 @@ static void mtk_setup_bridge_switch(stru
  		MTK_GSW_CFG);
  }
  
@@ -280,34 +258,29 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
  					      phy_interface_t interface)
  {
-@@ -483,12 +507,20 @@ static struct phylink_pcs *mtk_mac_selec
+@@ -483,6 +505,21 @@ static struct phylink_pcs *mtk_mac_selec
  	struct mtk_eth *eth = mac->hw;
  	unsigned int sid;
  
--	if (interface == PHY_INTERFACE_MODE_SGMII ||
--	    phy_interface_mode_is_8023z(interface)) {
--		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
--		       0 : mac->id;
--
--		return eth->sgmii_pcs[sid];
-+	if ((interface == PHY_INTERFACE_MODE_SGMII ||
-+	     phy_interface_mode_is_8023z(interface)) &&
-+	    MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
-+		sid = mtk_mac2xgmii_id(eth, mac->id);
-+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII))
-+			return mtk_sgmii_wrapper_select_pcs(eth, mac->id);
-+		else
-+			return eth->sgmii_pcs[sid];
-+	} else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
-+		    interface == PHY_INTERFACE_MODE_10GBASER ||
-+		    interface == PHY_INTERFACE_MODE_5GBASER) &&
-+		   MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) &&
-+		   mac->id != MTK_GMAC1_ID) {
-+		return mtk_usxgmii_select_pcs(eth, mac->id);
- 	}
- 
- 	return NULL;
-@@ -544,7 +576,22 @@ static void mtk_mac_config(struct phylin
++	if (mtk_is_netsys_v3_or_greater(eth)) {
++		switch (interface) {
++		case PHY_INTERFACE_MODE_1000BASEX:
++		case PHY_INTERFACE_MODE_2500BASEX:
++		case PHY_INTERFACE_MODE_SGMII:
++			return mac->sgmii_pcs;
++		case PHY_INTERFACE_MODE_5GBASER:
++		case PHY_INTERFACE_MODE_10GBASER:
++		case PHY_INTERFACE_MODE_USXGMII:
++			return mac->usxgmii_pcs;
++		default:
++			return NULL;
++		}
++	}
++
+ 	if (interface == PHY_INTERFACE_MODE_SGMII ||
+ 	    phy_interface_mode_is_8023z(interface)) {
+ 		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+@@ -544,7 +581,22 @@ static void mtk_mac_config(struct phylin
  					goto init_err;
  			}
  			break;
@@ -330,7 +303,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			break;
  		default:
  			goto err_phy;
-@@ -599,8 +646,6 @@ static void mtk_mac_config(struct phylin
+@@ -599,8 +651,6 @@ static void mtk_mac_config(struct phylin
  		val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
  		val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
  		regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
@@ -339,7 +312,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	/* SGMII */
-@@ -617,21 +662,40 @@ static void mtk_mac_config(struct phylin
+@@ -617,21 +667,40 @@ static void mtk_mac_config(struct phylin
  
  		/* Save the syscfg0 value for mac_finish */
  		mac->syscfg0 = val;
@@ -387,7 +360,37 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	return;
  
  err_phy:
-@@ -677,10 +741,13 @@ static void mtk_mac_link_down(struct phy
+@@ -644,6 +713,18 @@ init_err:
+ 		mac->id, phy_modes(state->interface), err);
+ }
+ 
++static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
++			   phy_interface_t interface)
++{
++	struct mtk_mac *mac = container_of(config, struct mtk_mac,
++					   phylink_config);
++
++	if (mac->pextp && mac->interface != interface)
++		phy_reset(mac->pextp);
++
++	return 0;
++}
++
+ static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
+ 			  phy_interface_t interface)
+ {
+@@ -652,6 +733,10 @@ static int mtk_mac_finish(struct phylink
+ 	struct mtk_eth *eth = mac->hw;
+ 	u32 mcr_cur, mcr_new;
+ 
++	/* Setup PMA/PMD */
++	if (mac->pextp)
++		phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
++
+ 	/* Enable SGMII */
+ 	if (interface == PHY_INTERFACE_MODE_SGMII ||
+ 	    phy_interface_mode_is_8023z(interface))
+@@ -677,10 +762,13 @@ static void mtk_mac_link_down(struct phy
  {
  	struct mtk_mac *mac = container_of(config, struct mtk_mac,
  					   phylink_config);
@@ -404,7 +407,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  }
  
  static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
-@@ -752,13 +819,11 @@ static void mtk_set_queue_speed(struct m
+@@ -752,13 +840,11 @@ static void mtk_set_queue_speed(struct m
  	mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
  }
  
@@ -422,7 +425,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	u32 mcr;
  
  	mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
-@@ -792,6 +857,55 @@ static void mtk_mac_link_up(struct phyli
+@@ -792,9 +878,63 @@ static void mtk_mac_link_up(struct phyli
  	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
  }
  
@@ -473,12 +476,98 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	else
 +		mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
 +				    tx_pause, rx_pause);
++
++	/* Repeat pextp setup to tune link */
++	if (mac->pextp)
++		phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
 +}
 +
  static const struct phylink_mac_ops mtk_phylink_ops = {
- 	.validate = phylink_generic_validate,
  	.mac_select_pcs = mtk_mac_select_pcs,
-@@ -4617,8 +4731,21 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	.mac_config = mtk_mac_config,
++	.mac_prepare = mtk_mac_prepare,
+ 	.mac_finish = mtk_mac_finish,
+ 	.mac_link_down = mtk_mac_link_down,
+ 	.mac_link_up = mtk_mac_link_up,
+@@ -3373,6 +3513,9 @@ static int mtk_open(struct net_device *d
+ 	struct mtk_eth *eth = mac->hw;
+ 	int i, err;
+ 
++	if (mac->pextp)
++		phy_power_on(mac->pextp);
++
+ 	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
+ 	if (err) {
+ 		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+@@ -3501,6 +3644,9 @@ static int mtk_stop(struct net_device *d
+ 	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
+ 		mtk_ppe_stop(eth->ppe[i]);
+ 
++	if (mac->pextp)
++		phy_power_off(mac->pextp);
++
+ 	return 0;
+ }
+ 
+@@ -4498,6 +4644,7 @@ static const struct net_device_ops mtk_n
+ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ {
+ 	const __be32 *_id = of_get_property(np, "reg", NULL);
++	struct device_node *pcs_np;
+ 	phy_interface_t phy_mode;
+ 	struct phylink *phylink;
+ 	struct mtk_mac *mac;
+@@ -4533,16 +4680,41 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	mac->id = id;
+ 	mac->hw = eth;
+ 	mac->of_node = np;
++	pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 0);
++	if (pcs_np) {
++		mac->sgmii_pcs = mtk_pcs_lynxi_get(eth->dev, pcs_np);
++		if (IS_ERR(mac->sgmii_pcs)) {
++			if (PTR_ERR(mac->sgmii_pcs) == -EPROBE_DEFER)
++				return -EPROBE_DEFER;
+ 
+-	err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
+-	if (err == -EPROBE_DEFER)
+-		return err;
++			dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
++				PTR_ERR(mac->sgmii_pcs));
++			return PTR_ERR(mac->sgmii_pcs);
++		}
++	}
+ 
+-	if (err) {
+-		/* If the mac address is invalid, use random mac address */
+-		eth_hw_addr_random(eth->netdev[id]);
+-		dev_err(eth->dev, "generated random MAC address %pM\n",
+-			eth->netdev[id]->dev_addr);
++	pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 1);
++	if (pcs_np) {
++		mac->usxgmii_pcs = mtk_usxgmii_pcs_get(eth->dev, pcs_np);
++		if (IS_ERR(mac->usxgmii_pcs)) {
++			if (PTR_ERR(mac->usxgmii_pcs) == -EPROBE_DEFER)
++				return -EPROBE_DEFER;
++
++			dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
++				PTR_ERR(mac->usxgmii_pcs));
++			return PTR_ERR(mac->usxgmii_pcs);
++		}
++	}
++
++	if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
++		mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
++		if (IS_ERR(mac->pextp)) {
++			if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
++				dev_err(eth->dev, "cannot get PHY, error %ld\n",
++					PTR_ERR(mac->pextp));
++
++			return PTR_ERR(mac->pextp);
++		}
+ 	}
+ 
+ 	memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
+@@ -4616,8 +4788,21 @@ static int mtk_add_mac(struct mtk_eth *e
  		phy_interface_zero(mac->phylink_config.supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  mac->phylink_config.supported_interfaces);
@@ -500,23 +589,91 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4811,6 +4938,13 @@ static int mtk_probe(struct platform_dev
+@@ -4662,6 +4847,26 @@ free_netdev:
+ 	return err;
+ }
  
- 		if (err)
- 			return err;
++static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
++{
++	int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
++
++	if (err == -EPROBE_DEFER)
++		return err;
++
++	if (test_defer_only)
++		return 0;
++
++	if (err) {
++		/* If the mac address is invalid, use random mac address */
++		eth_hw_addr_random(eth->netdev[i]);
++		dev_err(eth->dev, "generated random MAC address %pM\n",
++			eth->netdev[i]);
 +	}
 +
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
-+		err = mtk_usxgmii_init(eth);
++	return 0;
++}
 +
-+		if (err)
-+			return err;
+ void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
+ {
+ 	struct net_device *dev, *tmp;
+@@ -4805,7 +5010,8 @@ static int mtk_probe(struct platform_dev
+ 			regmap_write(cci, 0, 3);
  	}
  
- 	if (eth->soc->required_pctl) {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
++	    !mtk_is_netsys_v3_or_greater(eth)) {
+ 		err = mtk_sgmii_init(eth);
+ 
+ 		if (err)
+@@ -4916,6 +5122,24 @@ static int mtk_probe(struct platform_dev
+ 		}
+ 	}
+ 
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i])
++			continue;
++
++		err = mtk_mac_assign_address(eth, i, true);
++		if (err)
++			goto err_deinit_hw;
++	}
++
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i])
++			continue;
++
++		err = mtk_mac_assign_address(eth, i, false);
++		if (err)
++			goto err_deinit_hw;
++	}
++
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
+ 		err = devm_request_irq(eth->dev, eth->irq[0],
+ 				       mtk_handle_irq, 0,
+@@ -5018,6 +5242,11 @@ static int mtk_remove(struct platform_de
+ 		mtk_stop(eth->netdev[i]);
+ 		mac = netdev_priv(eth->netdev[i]);
+ 		phylink_disconnect_phy(mac->phylink);
++		if (mac->sgmii_pcs)
++			mtk_pcs_lynxi_put(mac->sgmii_pcs);
++
++		if (mac->usxgmii_pcs)
++			mtk_usxgmii_pcs_put(mac->usxgmii_pcs);
+ 	}
+ 
+ 	mtk_wed_exit();
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -502,6 +502,21 @@
+@@ -15,6 +15,7 @@
+ #include <linux/u64_stats_sync.h>
+ #include <linux/refcount.h>
+ #include <linux/phylink.h>
++#include <linux/reset.h>
+ #include <linux/rhashtable.h>
+ #include <linux/dim.h>
+ #include <linux/bitfield.h>
+@@ -502,6 +503,21 @@
  #define INTF_MODE_RGMII_1000    (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
  #define INTF_MODE_RGMII_10_100  0
  
@@ -538,7 +695,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* GPIO port control registers for GMAC 2*/
  #define GPIO_OD33_CTRL8		0x4c0
  #define GPIO_BIAS_CTRL		0xed0
-@@ -527,6 +542,7 @@
+@@ -527,6 +543,7 @@
  #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
  #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
  #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
@@ -546,72 +703,9 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  
  /* ethernet subsystem clock register */
-@@ -559,12 +575,74 @@
- #define ETHSYS_DMA_AG_MAP_QDMA	BIT(1)
- #define ETHSYS_DMA_AG_MAP_PPE	BIT(2)
- 
-+/* USXGMII subsystem config registers */
-+/* Register to control speed */
-+#define RG_PHY_TOP_SPEED_CTRL1	0x80C
-+#define USXGMII_RATE_UPDATE_MODE	BIT(31)
-+#define USXGMII_MAC_CK_GATED	BIT(29)
-+#define USXGMII_IF_FORCE_EN	BIT(28)
-+#define USXGMII_RATE_ADAPT_MODE	GENMASK(10, 8)
-+#define USXGMII_RATE_ADAPT_MODE_X1	0
-+#define USXGMII_RATE_ADAPT_MODE_X2	1
-+#define USXGMII_RATE_ADAPT_MODE_X4	2
-+#define USXGMII_RATE_ADAPT_MODE_X10	3
-+#define USXGMII_RATE_ADAPT_MODE_X100	4
-+#define USXGMII_RATE_ADAPT_MODE_X5	5
-+#define USXGMII_RATE_ADAPT_MODE_X50	6
-+#define USXGMII_XFI_RX_MODE	GENMASK(6, 4)
-+#define USXGMII_XFI_RX_MODE_10G	0
-+#define USXGMII_XFI_RX_MODE_5G	1
-+#define USXGMII_XFI_TX_MODE	GENMASK(2, 0)
-+#define USXGMII_XFI_TX_MODE_10G	0
-+#define USXGMII_XFI_TX_MODE_5G	1
-+
-+/* Register to control PCS AN */
-+#define RG_PCS_AN_CTRL0		0x810
-+#define USXGMII_AN_RESTART	BIT(31)
-+#define USXGMII_AN_SYNC_CNT	GENMASK(30, 11)
-+#define USXGMII_AN_ENABLE	BIT(0)
-+
-+#define RG_PCS_AN_CTRL2		0x818
-+#define USXGMII_LINK_TIMER_IDLE_DETECT	GENMASK(29, 20)
-+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT	GENMASK(19, 10)
-+#define USXGMII_LINK_TIMER_AN_RESTART	GENMASK(9, 0)
-+
-+/* Register to read PCS AN status */
-+#define RG_PCS_AN_STS0		0x81c
-+#define USXGMII_PCS_AN_WORD	GENMASK(15, 0)
-+#define USXGMII_LPA_LATCH	BIT(31)
-+
-+/* Register to control USXGMII XFI PLL digital */
-+#define XFI_PLL_DIG_GLB8	0x08
-+#define RG_XFI_PLL_EN		BIT(31)
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8	0x108
-+#define RG_XFI_PLL_ANA_SWWA	0x02283248
-+
- /* Infrasys subsystem config registers */
- #define INFRA_MISC2            0x70c
- #define CO_QPHY_SEL            BIT(0)
+@@ -565,6 +582,11 @@
  #define GEPHY_MAC_SEL          BIT(1)
  
-+/* Toprgu subsystem config registers */
-+#define TOPRGU_SWSYSRST		0x18
-+#define SWSYSRST_UNLOCK_KEY	GENMASK(31, 24)
-+#define SWSYSRST_XFI_PLL_GRST	BIT(16)
-+#define SWSYSRST_XFI_PEXPT1_GRST	BIT(15)
-+#define SWSYSRST_XFI_PEXPT0_GRST	BIT(14)
-+#define SWSYSRST_XFI1_GRST	BIT(13)
-+#define SWSYSRST_XFI0_GRST	BIT(12)
-+#define SWSYSRST_SGMII1_GRST	BIT(2)
-+#define SWSYSRST_SGMII0_GRST	BIT(1)
-+#define TOPRGU_SWSYSRST_EN		0xFC
-+
  /* Top misc registers */
 +#define TOP_MISC_NETSYS_PCS_MUX	0x84
 +#define NETSYS_PCS_MUX_MASK	GENMASK(1, 0)
@@ -621,7 +715,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define USB_PHY_SWITCH_REG	0x218
  #define QPHY_SEL_MASK		GENMASK(1, 0)
  #define SGMII_QPHY_SEL		0x2
-@@ -589,6 +667,8 @@
+@@ -589,6 +611,8 @@
  #define MT7628_SDM_RBCNT	(MT7628_SDM_OFFSET + 0x10c)
  #define MT7628_SDM_CS_ERR	(MT7628_SDM_OFFSET + 0x110)
  
@@ -630,7 +724,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_FE_CDM1_FSM		0x220
  #define MTK_FE_CDM2_FSM		0x224
  #define MTK_FE_CDM3_FSM		0x238
-@@ -597,6 +677,11 @@
+@@ -597,6 +621,11 @@
  #define MTK_FE_CDM6_FSM		0x328
  #define MTK_FE_GDM1_FSM		0x228
  #define MTK_FE_GDM2_FSM		0x22C
@@ -642,7 +736,40 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_MAC_FSM(x)		(0x1010C + ((x) * 0x100))
  
-@@ -943,6 +1028,8 @@ enum mkt_eth_capabilities {
+@@ -721,12 +750,8 @@ enum mtk_clks_map {
+ 	MTK_CLK_ETHWARP_WOCPU2,
+ 	MTK_CLK_ETHWARP_WOCPU1,
+ 	MTK_CLK_ETHWARP_WOCPU0,
+-	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
+-	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
+ 	MTK_CLK_TOP_SGM_0_SEL,
+ 	MTK_CLK_TOP_SGM_1_SEL,
+-	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
+-	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
+ 	MTK_CLK_TOP_ETH_GMII_SEL,
+ 	MTK_CLK_TOP_ETH_REFCK_50M_SEL,
+ 	MTK_CLK_TOP_ETH_SYS_200M_SEL,
+@@ -797,19 +822,9 @@ enum mtk_clks_map {
+ 				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
+ 				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
+ 				 BIT_ULL(MTK_CLK_CRYPTO) | \
+-				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
+-				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
+@@ -943,6 +958,8 @@ enum mkt_eth_capabilities {
  	MTK_RGMII_BIT = 0,
  	MTK_TRGMII_BIT,
  	MTK_SGMII_BIT,
@@ -651,7 +778,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	MTK_ESW_BIT,
  	MTK_GEPHY_BIT,
  	MTK_MUX_BIT,
-@@ -963,8 +1050,11 @@ enum mkt_eth_capabilities {
+@@ -963,8 +980,11 @@ enum mkt_eth_capabilities {
  	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
  	MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
  	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
@@ -663,7 +790,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  	/* PATH BITS */
  	MTK_ETH_PATH_GMAC1_RGMII_BIT,
-@@ -972,14 +1062,21 @@ enum mkt_eth_capabilities {
+@@ -972,14 +992,21 @@ enum mkt_eth_capabilities {
  	MTK_ETH_PATH_GMAC1_SGMII_BIT,
  	MTK_ETH_PATH_GMAC2_RGMII_BIT,
  	MTK_ETH_PATH_GMAC2_SGMII_BIT,
@@ -685,7 +812,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_ESW			BIT_ULL(MTK_ESW_BIT)
  #define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)
  #define MTK_MUX			BIT_ULL(MTK_MUX_BIT)
-@@ -1002,10 +1099,16 @@ enum mkt_eth_capabilities {
+@@ -1002,10 +1029,16 @@ enum mkt_eth_capabilities {
  	BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
  #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\
  	BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
@@ -702,7 +829,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  /* Supported path present on SoCs */
  #define MTK_ETH_PATH_GMAC1_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
-@@ -1013,8 +1116,13 @@ enum mkt_eth_capabilities {
+@@ -1013,8 +1046,13 @@ enum mkt_eth_capabilities {
  #define MTK_ETH_PATH_GMAC1_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
  #define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
  #define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
@@ -716,7 +843,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
  #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
-@@ -1022,7 +1130,12 @@ enum mkt_eth_capabilities {
+@@ -1022,7 +1060,12 @@ enum mkt_eth_capabilities {
  #define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
  #define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
  #define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
@@ -729,7 +856,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  /* MUXes present on SoCs */
  /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
-@@ -1041,10 +1154,20 @@ enum mkt_eth_capabilities {
+@@ -1041,10 +1084,20 @@ enum mkt_eth_capabilities {
  	(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
  	MTK_SHARED_SGMII)
  
@@ -750,7 +877,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
  
  #define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-@@ -1076,8 +1199,12 @@ enum mkt_eth_capabilities {
+@@ -1076,8 +1129,12 @@ enum mkt_eth_capabilities {
  		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
  		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
  
@@ -765,56 +892,17 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  struct mtk_tx_dma_desc_info {
  	dma_addr_t	addr;
-@@ -1187,6 +1314,24 @@ struct mtk_soc_data {
- /* currently no SoC has more than 3 macs */
- #define MTK_MAX_DEVS	3
- 
-+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
-+ *			associated data
-+ * @regmap:		The register map pointing at the range used to setup
-+ *			USXGMII modes
-+ * @interface:		Currently selected interface mode
-+ * @id:			The element is used to record the index of PCS
-+ * @pcs:		Phylink PCS structure
-+ */
-+struct mtk_usxgmii_pcs {
-+	struct mtk_eth		*eth;
-+	struct regmap		*regmap;
-+	struct phylink_pcs	*wrapped_sgmii_pcs;
-+	phy_interface_t		interface;
-+	u8			id;
-+	unsigned int		mode;
-+	struct phylink_pcs	pcs;
-+};
-+
- /* struct mtk_eth -	This is the main datasructure for holding the state
-  *			of the driver
-  * @dev:		The device pointer
-@@ -1207,6 +1352,12 @@ struct mtk_soc_data {
-  * @infra:              The register map pointing at the range used to setup
-  *                      SGMII and GePHY path
-  * @sgmii_pcs:		Pointers to mtk-pcs-lynxi phylink_pcs instances
-+ * @sgmii_wrapped_pcs:	Pointers to NETSYSv3 wrapper PCS instances
-+ * @usxgmii_pll:	The register map pointing at the range used to control
-+ *			the USXGMII SerDes PLL
-+ * @regmap_pextp:	The register map pointing at the range used to setup
-+ *			PHYA
-+ * @usxgmii_pcs:	Pointer to array of pointers to struct for USXGMII PCS
-  * @pctl:		The register map pointing at the range used to setup
-  *			GMAC port drive/slew values
-  * @dma_refcnt:		track how many netdevs are using the DMA engine
-@@ -1250,6 +1401,10 @@ struct mtk_eth {
- 	struct regmap			*ethsys;
- 	struct regmap			*infra;
- 	struct phylink_pcs		*sgmii_pcs[MTK_MAX_DEVS];
-+	struct regmap			*toprgu;
-+	struct regmap			*usxgmii_pll;
-+	struct regmap			*regmap_pextp[MTK_MAX_DEVS];
-+	struct mtk_usxgmii_pcs		*usxgmii_pcs[MTK_MAX_DEVS];
- 	struct regmap			*pctl;
- 	bool				hwlro;
- 	refcount_t			dma_refcnt;
-@@ -1437,6 +1592,19 @@ static inline u32 mtk_get_ib2_multicast_
+@@ -1314,6 +1371,9 @@ struct mtk_mac {
+ 	struct device_node		*of_node;
+ 	struct phylink			*phylink;
+ 	struct phylink_config		phylink_config;
++	struct phylink_pcs		*sgmii_pcs;
++	struct phylink_pcs		*usxgmii_pcs;
++	struct phy			*pextp;
+ 	struct mtk_eth			*hw;
+ 	struct mtk_hw_stats		*hw_stats;
+ 	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
+@@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
  	return MTK_FOE_IB2_MULTICAST;
  }
  
@@ -834,7 +922,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* read the hardware status register */
  void mtk_stats_update_mac(struct mtk_mac *mac);
  
-@@ -1445,8 +1613,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+@@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
  u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
  
  int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
@@ -845,760 +933,3 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  int mtk_eth_offload_init(struct mtk_eth *eth);
  int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
-@@ -1456,5 +1626,63 @@ int mtk_flow_offload_cmd(struct mtk_eth
- void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
- void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
- 
-+static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
-+{
-+	int xgmii_id = mac_id;
-+
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
-+		switch (mac_id) {
-+		case MTK_GMAC1_ID:
-+		case MTK_GMAC2_ID:
-+			xgmii_id = 1;
-+			break;
-+		case MTK_GMAC3_ID:
-+			xgmii_id = 0;
-+			break;
-+		default:
-+			xgmii_id = -1;
-+		}
-+	}
-+
-+	return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id;
-+}
-+
-+static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
-+{
-+	int mac_id = xgmii_id;
-+
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
-+		switch (xgmii_id) {
-+		case 0:
-+			mac_id = 2;
-+			break;
-+		case 1:
-+			mac_id = 1;
-+			break;
-+		default:
-+			mac_id = -1;
-+		}
-+	}
-+
-+	return mac_id;
-+}
-+
-+#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id);
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
-+int mtk_usxgmii_init(struct mtk_eth *eth);
-+#else
-+static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id)
-+{
-+	return NULL;
-+}
-+
-+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id)
-+{
-+	return NULL;
-+}
-+
-+static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
-+#endif /* NET_MEDIATEK_SOC_USXGMII */
- 
- #endif /* MTK_ETH_H */
---- /dev/null
-+++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
-@@ -0,0 +1,690 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Henry Yen <henry.yen@mediatek.com>
-+ *         Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/mfd/syscon.h>
-+#include <linux/of.h>
-+#include <linux/regmap.h>
-+#include "mtk_eth_soc.h"
-+
-+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
-+{
-+	return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
-+}
-+
-+static int mtk_xfi_pextp_init(struct mtk_eth *eth)
-+{
-+	struct device *dev = eth->dev;
-+	struct device_node *r = dev->of_node;
-+	struct device_node *np;
-+	int i;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		np = of_parse_phandle(r, "mediatek,xfi-pextp", i);
-+		if (!np)
-+			break;
-+
-+		eth->regmap_pextp[i] = syscon_node_to_regmap(np);
-+		if (IS_ERR(eth->regmap_pextp[i]))
-+			return PTR_ERR(eth->regmap_pextp[i]);
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_xfi_pll_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(r, "mediatek,xfi-pll", 0);
-+	if (!np)
-+		return -1;
-+
-+	eth->usxgmii_pll = syscon_node_to_regmap(np);
-+	if (IS_ERR(eth->usxgmii_pll))
-+		return PTR_ERR(eth->usxgmii_pll);
-+
-+	return 0;
-+}
-+
-+static int mtk_toprgu_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(r, "mediatek,toprgu", 0);
-+	if (!np)
-+		return -1;
-+
-+	eth->toprgu = syscon_node_to_regmap(np);
-+	if (IS_ERR(eth->toprgu))
-+		return PTR_ERR(eth->toprgu);
-+
-+	return 0;
-+}
-+
-+static int mtk_xfi_pll_enable(struct mtk_eth *eth)
-+{
-+	u32 val = 0;
-+
-+	if (!eth->usxgmii_pll)
-+		return -EINVAL;
-+
-+	/* Add software workaround for USXGMII PLL TCL issue */
-+	regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
-+
-+	regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
-+	val |= RG_XFI_PLL_EN;
-+	regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
-+
-+	return 0;
-+}
-+
-+static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id)
-+{
-+	bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
-+		       interface == PHY_INTERFACE_MODE_USXGMII);
-+	bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
-+	bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
-+
-+	/* Setup operation mode */
-+	if (is_10g)
-+		regmap_write(pextp, 0x9024, 0x00C9071C);
-+	else
-+		regmap_write(pextp, 0x9024, 0x00D9071C);
-+
-+	if (is_5g)
-+		regmap_write(pextp, 0x2020, 0xAAA5A5AA);
-+	else
-+		regmap_write(pextp, 0x2020, 0xAA8585AA);
-+
-+	if (is_2p5g || is_5g || is_10g) {
-+		regmap_write(pextp, 0x2030, 0x0C020707);
-+		regmap_write(pextp, 0x2034, 0x0E050F0F);
-+		regmap_write(pextp, 0x2040, 0x00140032);
-+	} else {
-+		regmap_write(pextp, 0x2030, 0x0C020207);
-+		regmap_write(pextp, 0x2034, 0x0E05050F);
-+		regmap_write(pextp, 0x2040, 0x00200032);
-+	}
-+
-+	if (is_2p5g || is_10g)
-+		regmap_write(pextp, 0x50F0, 0x00C014AA);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x50F0, 0x00C018AA);
-+	else
-+		regmap_write(pextp, 0x50F0, 0x00C014BA);
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50E0, 0x3777812B);
-+		regmap_write(pextp, 0x506C, 0x005C9CFF);
-+		regmap_write(pextp, 0x5070, 0x9DFAFAFA);
-+		regmap_write(pextp, 0x5074, 0x273F3F3F);
-+		regmap_write(pextp, 0x5078, 0xA8883868);
-+		regmap_write(pextp, 0x507C, 0x14661466);
-+	} else {
-+		regmap_write(pextp, 0x50E0, 0x3777C12B);
-+		regmap_write(pextp, 0x506C, 0x005F9CFF);
-+		regmap_write(pextp, 0x5070, 0x9D9DFAFA);
-+		regmap_write(pextp, 0x5074, 0x27273F3F);
-+		regmap_write(pextp, 0x5078, 0xA7883C68);
-+		regmap_write(pextp, 0x507C, 0x11661166);
-+	}
-+
-+	if (is_2p5g || is_10g) {
-+		regmap_write(pextp, 0x5080, 0x0E000AAF);
-+		regmap_write(pextp, 0x5084, 0x08080D0D);
-+		regmap_write(pextp, 0x5088, 0x02030909);
-+	} else if (is_5g) {
-+		regmap_write(pextp, 0x5080, 0x0E001ABF);
-+		regmap_write(pextp, 0x5084, 0x080B0D0D);
-+		regmap_write(pextp, 0x5088, 0x02050909);
-+	} else {
-+		regmap_write(pextp, 0x5080, 0x0E000EAF);
-+		regmap_write(pextp, 0x5084, 0x08080E0D);
-+		regmap_write(pextp, 0x5088, 0x02030B09);
-+	}
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50E4, 0x0C000000);
-+		regmap_write(pextp, 0x50E8, 0x04000000);
-+	} else {
-+		regmap_write(pextp, 0x50E4, 0x0C0C0000);
-+		regmap_write(pextp, 0x50E8, 0x04040000);
-+	}
-+
-+	if (is_2p5g || mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x50EC, 0x0F0F0C06);
-+	else
-+		regmap_write(pextp, 0x50EC, 0x0F0F0606);
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50A8, 0x50808C8C);
-+		regmap_write(pextp, 0x6004, 0x18000000);
-+	} else {
-+		regmap_write(pextp, 0x50A8, 0x506E8C8C);
-+		regmap_write(pextp, 0x6004, 0x18190000);
-+	}
-+
-+	if (is_10g)
-+		regmap_write(pextp, 0x00F8, 0x01423342);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x00F8, 0x00A132A1);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x00F8, 0x009C329C);
-+	else
-+		regmap_write(pextp, 0x00F8, 0x00FA32FA);
-+
-+	/* Force SGDT_OUT off and select PCS */
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x00F4, 0x80201F20);
-+	else
-+		regmap_write(pextp, 0x00F4, 0x80201F21);
-+
-+	/* Force GLB_CKDET_OUT */
-+	regmap_write(pextp, 0x0030, 0x00050C00);
-+
-+	/* Force AEQ on */
-+	regmap_write(pextp, 0x0070, 0x02002800);
-+	ndelay(1020);
-+
-+	/* Setup DA default value */
-+	regmap_write(pextp, 0x30B0, 0x00000020);
-+	regmap_write(pextp, 0x3028, 0x00008A01);
-+	regmap_write(pextp, 0x302C, 0x0000A884);
-+	regmap_write(pextp, 0x3024, 0x00083002);
-+	if (mtk_interface_mode_is_xgmii(interface)) {
-+		regmap_write(pextp, 0x3010, 0x00022220);
-+		regmap_write(pextp, 0x5064, 0x0F020A01);
-+		regmap_write(pextp, 0x50B4, 0x06100600);
-+		if (interface == PHY_INTERFACE_MODE_USXGMII)
-+			regmap_write(pextp, 0x3048, 0x40704000);
-+		else
-+			regmap_write(pextp, 0x3048, 0x47684100);
-+	} else {
-+		regmap_write(pextp, 0x3010, 0x00011110);
-+		regmap_write(pextp, 0x3048, 0x40704000);
-+	}
-+
-+	if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g)
-+		regmap_write(pextp, 0x3064, 0x0000C000);
-+
-+	if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+		regmap_write(pextp, 0x3050, 0xA8000000);
-+		regmap_write(pextp, 0x3054, 0x000000AA);
-+	} else if (mtk_interface_mode_is_xgmii(interface)) {
-+		regmap_write(pextp, 0x3050, 0x00000000);
-+		regmap_write(pextp, 0x3054, 0x00000000);
-+	} else {
-+		regmap_write(pextp, 0x3050, 0xA8000000);
-+		regmap_write(pextp, 0x3054, 0x000000AA);
-+	}
-+
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x306C, 0x00000F00);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x306C, 0x22000F00);
-+	else
-+		regmap_write(pextp, 0x306C, 0x20200F00);
-+
-+	if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0)
-+		regmap_write(pextp, 0xA008, 0x0007B400);
-+
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0xA060, 0x00040000);
-+	else
-+		regmap_write(pextp, 0xA060, 0x00050000);
-+
-+	if (is_10g)
-+		regmap_write(pextp, 0x90D0, 0x00000001);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x90D0, 0x00000003);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x90D0, 0x00000005);
-+	else
-+		regmap_write(pextp, 0x90D0, 0x00000007);
-+
-+	/* Release reset */
-+	regmap_write(pextp, 0x0070, 0x0200E800);
-+	usleep_range(150, 500);
-+
-+	/* Switch to P0 */
-+	regmap_write(pextp, 0x0070, 0x0200C111);
-+	ndelay(1020);
-+	regmap_write(pextp, 0x0070, 0x0200C101);
-+	usleep_range(15, 50);
-+
-+	if (mtk_interface_mode_is_xgmii(interface)) {
-+		/* Switch to Gen3 */
-+		regmap_write(pextp, 0x0070, 0x0202C111);
-+	} else {
-+		/* Switch to Gen2 */
-+		regmap_write(pextp, 0x0070, 0x0201C111);
-+	}
-+	ndelay(1020);
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x0070, 0x0202C101);
-+	else
-+		regmap_write(pextp, 0x0070, 0x0201C101);
-+	usleep_range(100, 500);
-+	regmap_write(pextp, 0x30B0, 0x00000030);
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x00F4, 0x80201F00);
-+	else
-+		regmap_write(pextp, 0x00F4, 0x80201F01);
-+
-+	regmap_write(pextp, 0x3040, 0x30000000);
-+	usleep_range(400, 1000);
-+}
-+
-+static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
-+{
-+	u32 toggle, val;
-+
-+	if (id >= MTK_MAX_DEVS || !eth->toprgu)
-+		return;
-+
-+	switch (id) {
-+	case 0:
-+		toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST |
-+			 SWSYSRST_SGMII0_GRST;
-+		break;
-+	case 1:
-+		toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST |
-+			 SWSYSRST_SGMII1_GRST;
-+		break;
-+	default:
-+		return;
-+	}
-+
-+	/* Enable software reset */
-+	regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+	/* Assert USXGMII reset */
-+	regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST,
-+			FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle);
-+
-+	usleep_range(100, 500);
-+
-+	/* De-assert USXGMII reset */
-+	regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
-+	val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
-+	val &= ~toggle;
-+	regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
-+
-+	/* Disable software reset */
-+	regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+	mdelay(10);
-+}
-+
-+/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit
-+ * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config
-+ * also trigger an initial reset and subsequent configuration of the PHYA.
-+ */
-+struct mtk_sgmii_wrapper_pcs {
-+	struct mtk_eth		*eth;
-+	struct phylink_pcs	*wrapped_pcs;
-+	u8			id;
-+	struct phylink_pcs	pcs;
-+};
-+
-+static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs,
-+					unsigned int mode,
-+					phy_interface_t interface,
-+					const unsigned long *advertising,
-+					bool permit_pause_to_mac)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+	bool full_reconf;
-+	int ret;
-+
-+	full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface;
-+	if (full_reconf) {
-+		mtk_xfi_pll_enable(wp->eth);
-+		mtk_usxgmii_reset(wp->eth, wp->id);
-+	}
-+
-+	ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface,
-+					       advertising, permit_pause_to_mac);
-+
-+	if (full_reconf)
-+		mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id);
-+
-+	wp->eth->usxgmii_pcs[wp->id]->interface = interface;
-+
-+	return ret;
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs,
-+					    struct phylink_link_state *state)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs,
-+					  unsigned int mode,
-+					  phy_interface_t interface, int speed,
-+					  int duplex)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs);
-+
-+	wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA;
-+}
-+
-+static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = {
-+	.pcs_get_state = mtk_sgmii_wrapped_pcs_get_state,
-+	.pcs_config = mtk_sgmii_wrapped_pcs_config,
-+	.pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart,
-+	.pcs_link_up = mtk_sgmii_wrapped_pcs_link_up,
-+	.pcs_disable = mtk_sgmii_wrapped_pcs_disable,
-+};
-+
-+static int mtk_sgmii_wrapper_init(struct mtk_eth *eth)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp;
-+	int i;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		if (!eth->sgmii_pcs[i])
-+			continue;
-+
-+		if (!eth->usxgmii_pcs[i])
-+			continue;
-+
-+		/* Make sure all PCS ops are supported by wrapped PCS */
-+		if (!eth->sgmii_pcs[i]->ops->pcs_get_state ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_config ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_an_restart ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_link_up ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_disable)
-+			return -EOPNOTSUPP;
-+
-+		wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL);
-+		if (!wp)
-+			return -ENOMEM;
-+
-+		wp->wrapped_pcs = eth->sgmii_pcs[i];
-+		wp->id = i;
-+		wp->pcs.poll = true;
-+		wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops;
-+		wp->eth = eth;
-+
-+		eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs;
-+	}
-+
-+	return 0;
-+}
-+
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+	if (!eth->usxgmii_pcs[xgmii_id])
-+		return NULL;
-+
-+	return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs;
-+}
-+
-+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-+				  phy_interface_t interface,
-+				  const unsigned long *advertising,
-+				  bool permit_pause_to_mac)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	struct mtk_eth *eth = mpcs->eth;
-+	struct regmap *pextp = eth->regmap_pextp[mpcs->id];
-+	unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
-+	bool mode_changed = false;
-+
-+	if (!pextp)
-+		return -ENODEV;
-+
-+	if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+	} else if (interface == PHY_INTERFACE_MODE_10GBASER) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+		adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+	} else if (interface == PHY_INTERFACE_MODE_5GBASER) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
-+		adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
-+
-+	if (mpcs->interface != interface) {
-+		mpcs->interface = interface;
-+		mode_changed = true;
-+	}
-+
-+	mtk_xfi_pll_enable(eth);
-+	mtk_usxgmii_reset(eth, mpcs->id);
-+
-+	/* Setup USXGMII AN ctrl */
-+	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
-+			   USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
-+			   an_ctrl);
-+
-+	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
-+			   USXGMII_LINK_TIMER_IDLE_DETECT |
-+			   USXGMII_LINK_TIMER_COMP_ACK_DETECT |
-+			   USXGMII_LINK_TIMER_AN_RESTART,
-+			   link_timer);
-+
-+	mpcs->mode = mode;
-+
-+	/* Gated MAC CK */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
-+
-+	/* Enable interface force mode */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
-+
-+	/* Setup USXGMII adapt mode */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
-+			   adapt_mode);
-+
-+	/* Setup USXGMII speed */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
-+			   xfi_mode);
-+
-+	usleep_range(1, 10);
-+
-+	/* Un-gated MAC CK */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_MAC_CK_GATED, 0);
-+
-+	usleep_range(1, 10);
-+
-+	/* Disable interface force mode for the AN mode */
-+	if (an_ctrl & USXGMII_AN_ENABLE)
-+		regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+				   USXGMII_IF_FORCE_EN, 0);
-+
-+	/* Setup USXGMIISYS with the determined property */
-+	mtk_usxgmii_setup_phya(pextp, interface, mpcs->id);
-+
-+	return mode_changed;
-+}
-+
-+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
-+				      struct phylink_link_state *state)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	struct mtk_eth *eth = mpcs->eth;
-+	struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
-+	u32 val = 0;
-+
-+	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+	if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
-+		/* Refresh LPA by inverting LPA_LATCH */
-+		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+		regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
-+				   USXGMII_LPA_LATCH,
-+				   !(val & USXGMII_LPA_LATCH));
-+
-+		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+
-+		phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD,
-+							     val));
-+
-+		state->interface = mpcs->interface;
-+	} else {
-+		val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
-+
-+		if (mac->id == MTK_GMAC2_ID)
-+			val >>= 16;
-+
-+		switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
-+		case 0:
-+			state->speed = SPEED_10000;
-+			break;
-+		case 1:
-+			state->speed = SPEED_5000;
-+			break;
-+		case 2:
-+			state->speed = SPEED_2500;
-+			break;
-+		case 3:
-+			state->speed = SPEED_1000;
-+			break;
-+		}
-+
-+		state->interface = mpcs->interface;
-+		state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
-+		state->duplex = DUPLEX_FULL;
-+	}
-+
-+	/* Continuously repeat re-configuration sequence until link comes up */
-+	if (state->link == 0)
-+		mtk_usxgmii_pcs_config(pcs, mpcs->mode,
-+				       state->interface, NULL, false);
-+}
-+
-+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	unsigned int val = 0;
-+
-+	if (!mpcs->regmap)
-+		return;
-+
-+	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+	val |= USXGMII_AN_RESTART;
-+	regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
-+}
-+
-+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
-+				    phy_interface_t interface,
-+				    int speed, int duplex)
-+{
-+	/* Reconfiguring USXGMII to ensure the quality of the RX signal
-+	 * after the line side link up.
-+	 */
-+	mtk_usxgmii_pcs_config(pcs, mode,
-+			       interface, NULL, false);
-+}
-+
-+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
-+	.pcs_config = mtk_usxgmii_pcs_config,
-+	.pcs_get_state = mtk_usxgmii_pcs_get_state,
-+	.pcs_an_restart = mtk_usxgmii_pcs_restart_an,
-+	.pcs_link_up = mtk_usxgmii_pcs_link_up,
-+};
-+
-+int mtk_usxgmii_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device *dev = eth->dev;
-+	struct device_node *np;
-+	int i, ret;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
-+		if (!np)
-+			break;
-+
-+		eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL);
-+		if (!eth->usxgmii_pcs[i])
-+			return -ENOMEM;
-+
-+		eth->usxgmii_pcs[i]->id = i;
-+		eth->usxgmii_pcs[i]->eth = eth;
-+		eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
-+		if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
-+			return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
-+
-+		eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
-+		eth->usxgmii_pcs[i]->pcs.poll = true;
-+		eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
-+		eth->usxgmii_pcs[i]->mode = -1;
-+
-+		of_node_put(np);
-+	}
-+
-+	ret = mtk_xfi_pextp_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	ret = mtk_xfi_pll_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	ret = mtk_toprgu_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	return mtk_sgmii_wrapper_init(eth);
-+}
-+
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+	if (!eth->usxgmii_pcs[xgmii_id]->regmap)
-+		return NULL;
-+
-+	return &eth->usxgmii_pcs[xgmii_id]->pcs;
-+}
diff --git a/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch b/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
index bc17b3635c..b598d15866 100644
--- a/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
+++ b/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
@@ -32,7 +32,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4886,7 +4886,10 @@ static int mtk_probe(struct platform_dev
+@@ -4963,7 +4963,10 @@ static int mtk_probe(struct platform_dev
  	}
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
diff --git a/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch b/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch
new file mode 100644
index 0000000000..1f1c40b1d9
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch
@@ -0,0 +1,136 @@
+From patchwork Thu Feb  1 21:52:20 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541842
+Date: Thu, 1 Feb 2024 21:52:20 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+	Steven Liu <steven.liu@mediatek.com>,
+	John Crispin <john@phrozen.org>,
+	Chunfeng Yun <chunfeng.yun@mediatek.com>,
+	Vinod Koul <vkoul@kernel.org>,
+	Kishon Vijay Abraham I <kishon@kernel.org>,
+	Rob Herring <robh@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Qingfang Deng <dqfext@gmail.com>,
+	SkyLake Huang <SkyLake.Huang@mediatek.com>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	linux-arm-kernel@lists.infradead.org,
+	linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+	netdev@vger.kernel.org
+Subject: [PATCH 1/2] dt-bindings: phy: mediatek,xfi-tphy: add new bindings
+Message-ID: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the
+MediaTek MT7988 SoC which can operate at various interfaces modes:
+
+via USXGMII PCS:
+ * USXGMII
+ * 10GBase-R
+ * 5GBase-R
+
+via LynxI SGMII PCS:
+ * 2500Base-X
+ * 1000Base-X
+ * Cisco SGMII (MAC side)
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/phy/mediatek,xfi-tphy.yaml       | 80 +++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+@@ -0,0 +1,80 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek XFI T-PHY
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
++  used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
++  MediaTek's 10G-capabale SoCs.
++
++properties:
++  $nodename:
++    pattern: "^phy@[0-9a-f]+$"
++
++  compatible:
++    const: mediatek,mt7988-xfi-tphy
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: XFI PHY clock
++      - description: XFI register clock
++
++  clock-names:
++    items:
++      - const: xfipll
++      - const: topxtal
++
++  resets:
++    items:
++      - description: PEXTP reset
++
++  mediatek,usxgmii-performance-errata:
++    $ref: /schemas/types.yaml#/definitions/flag
++    description:
++      One instance of the T-PHY on MT7988 suffers from a performance
++      problem in 10GBase-R mode which needs a work-around in the driver.
++      The work-around is enabled using this flag.
++
++  "#phy-cells":
++    const: 0
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - resets
++  - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      phy@11f20000 {
++        compatible = "mediatek,mt7988-xfi-tphy";
++        reg = <0 0x11f20000 0 0x10000>;
++        clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
++                 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
++        clock-names = "xfipll", "topxtal";
++        resets = <&watchdog 14>;
++        mediatek,usxgmii-performance-errata;
++        #phy-cells = <0>;
++      };
++    };
++
++...
diff --git a/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch b/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
new file mode 100644
index 0000000000..d7424020a7
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
@@ -0,0 +1,497 @@
+From patchwork Thu Feb  1 21:53:06 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541843
+Date: Thu, 1 Feb 2024 21:53:06 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+	Chunfeng Yun <chunfeng.yun@mediatek.com>,
+	Vinod Koul <vkoul@kernel.org>,
+	Kishon Vijay Abraham I <kishon@kernel.org>,
+	Rob Herring <robh@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Qingfang Deng <dqfext@gmail.com>,
+	SkyLake Huang <SkyLake.Huang@mediatek.com>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	linux-arm-kernel@lists.infradead.org,
+	linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+	netdev@vger.kernel.org
+Subject: [PATCH 2/2] phy: add driver for MediaTek XFI T-PHY
+Message-ID: 
+ <dd6b40ea1f7f8459a9a2cfe7fa60c1108332ade6.1706823233.git.daniel@makrotopia.org>
+References: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+In-Reply-To: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add driver for MediaTek's XFI T-PHY, 10 Gigabit/s Ethernet SerDes PHY
+which can be found in the MT7988 SoC.
+
+The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
+PHY_INTERFACE_MODE_* corresponding to the supported modes:
+
+ * USXGMII                 \
+ * 10GBase-R                }- USXGMII PCS - XGDM  \
+ * 5GBase-R                /                        \
+                                                     }- Ethernet MAC
+ * 2500Base-X              \                        /
+ * 1000Base-X               }- LynxI PCS - GDM     /
+ * Cisco SGMII (MAC side)  /
+
+In order to work-around a performance issue present on the first of
+two XFI T-PHYs present in MT7988, special tuning is applied which can be
+selected by adding the 'mediatek,usxgmii-performance-errata' property to
+the device tree node.
+
+There is no documentation for most registers used for the
+analog/tuning part, however, most of the registers have been partially
+reverse-engineered from MediaTek's SDK implementation (an opaque
+sequence of 32-bit register writes) and descriptions for all relevant
+digital registers and bits such as resets and muxes have been supplied
+by MediaTek.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                             |   1 +
+ drivers/phy/mediatek/Kconfig            |  12 +
+ drivers/phy/mediatek/Makefile           |   1 +
+ drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 392 ++++++++++++++++++++++++
+ 4 files changed, 406 insertions(+)
+ create mode 100644 drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+
+--- a/drivers/phy/mediatek/Kconfig
++++ b/drivers/phy/mediatek/Kconfig
+@@ -13,6 +13,18 @@ config PHY_MTK_PCIE
+ 	  callback for PCIe GEN3 port, it supports software efuse
+ 	  initialization.
+ 
++config PHY_MTK_XFI_TPHY
++	tristate "MediaTek XFI T-PHY Driver"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	depends on OF && OF_ADDRESS
++	depends on HAS_IOMEM
++	select GENERIC_PHY
++	help
++	  Say 'Y' here to add support for MediaTek XFI T-PHY driver.
++	  The driver provides access to the Ethernet SerDes T-PHY supporting
++	  1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
++	  via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
++
+ config PHY_MTK_TPHY
+ 	tristate "MediaTek T-PHY Driver"
+ 	depends on ARCH_MEDIATEK || COMPILE_TEST
+--- a/drivers/phy/mediatek/Makefile
++++ b/drivers/phy/mediatek/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE)		+= phy-mtk-p
+ obj-$(CONFIG_PHY_MTK_TPHY)		+= phy-mtk-tphy.o
+ obj-$(CONFIG_PHY_MTK_UFS)		+= phy-mtk-ufs.o
+ obj-$(CONFIG_PHY_MTK_XSPHY)		+= phy-mtk-xsphy.o
++obj-$(CONFIG_PHY_MTK_XFI_TPHY)		+= phy-mtk-xfi-tphy.o
+ 
+ phy-mtk-hdmi-drv-y			:= phy-mtk-hdmi.o
+ phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-mt2701.o
+--- /dev/null
++++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+@@ -0,0 +1,392 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/* MediaTek 10GE SerDes PHY driver
++ *
++ * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org>
++ *                    Bc-bocun Chen <bc-bocun.chen@mediatek.com>
++ * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/phy.h>
++#include <linux/phy/phy.h>
++
++#define MTK_XFI_TPHY_NUM_CLOCKS		2
++
++#define REG_DIG_GLB_70			0x0070
++#define  XTP_PCS_RX_EQ_IN_PROGRESS(x)	FIELD_PREP(GENMASK(25, 24), (x))
++#define  XTP_PCS_MODE_MASK		GENMASK(17, 16)
++#define  XTP_PCS_MODE(x)		FIELD_PREP(GENMASK(17, 16), (x))
++#define  XTP_PCS_RST_B			BIT(15)
++#define  XTP_FRC_PCS_RST_B		BIT(14)
++#define  XTP_PCS_PWD_SYNC_MASK		GENMASK(13, 12)
++#define  XTP_PCS_PWD_SYNC(x)		FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x))
++#define  XTP_PCS_PWD_ASYNC_MASK		GENMASK(11, 10)
++#define  XTP_PCS_PWD_ASYNC(x)		FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x))
++#define  XTP_FRC_PCS_PWD_ASYNC		BIT(8)
++#define  XTP_PCS_UPDT			BIT(4)
++#define  XTP_PCS_IN_FR_RG		BIT(0)
++
++#define REG_DIG_GLB_F4			0x00f4
++#define  XFI_DPHY_PCS_SEL		BIT(0)
++#define   XFI_DPHY_PCS_SEL_SGMII	FIELD_PREP(XFI_DPHY_PCS_SEL, 1)
++#define   XFI_DPHY_PCS_SEL_USXGMII	FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
++#define  XFI_DPHY_AD_SGDT_FRC_EN	BIT(5)
++
++#define REG_DIG_LN_TRX_40		0x3040
++#define  XTP_LN_FRC_TX_DATA_EN		BIT(29)
++#define  XTP_LN_TX_DATA_EN		BIT(28)
++
++#define REG_DIG_LN_TRX_B0		0x30b0
++#define  XTP_LN_FRC_TX_MACCK_EN		BIT(5)
++#define  XTP_LN_TX_MACCK_EN		BIT(4)
++
++#define REG_ANA_GLB_D0			0x90d0
++#define  XTP_GLB_USXGMII_SEL_MASK	GENMASK(3, 1)
++#define  XTP_GLB_USXGMII_SEL(x)		FIELD_PREP(GENMASK(3, 1), (x))
++#define  XTP_GLB_USXGMII_EN		BIT(0)
++
++struct mtk_xfi_tphy {
++	void __iomem		*base;
++	struct device		*dev;
++	struct reset_control	*reset;
++	struct clk_bulk_data	clocks[MTK_XFI_TPHY_NUM_CLOCKS];
++	bool			da_war;
++};
++
++static void mtk_xfi_tphy_write(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			       u32 value)
++{
++	iowrite32(value, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_rmw(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			     u32 clr, u32 set)
++{
++	u32 val;
++
++	val = ioread32(xfi_tphy->base + reg);
++	val &= ~clr;
++	val |= set;
++	iowrite32(val, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_set(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			     u32 set)
++{
++	mtk_xfi_tphy_rmw(xfi_tphy, reg, 0, set);
++}
++
++static void mtk_xfi_tphy_clear(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			       u32 clr)
++{
++	mtk_xfi_tphy_rmw(xfi_tphy, reg, clr, 0);
++}
++
++static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy,
++			       phy_interface_t interface)
++{
++	bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
++	bool is_1g = (interface == PHY_INTERFACE_MODE_1000BASEX ||
++		      interface == PHY_INTERFACE_MODE_SGMII);
++	bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
++		       interface == PHY_INTERFACE_MODE_USXGMII);
++	bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
++	bool is_xgmii = (is_10g || is_5g);
++
++	dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface));
++
++	/* Setup PLL setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2030, 0x500, is_1g ? 0x0 : 0x500);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2040, 0x340000, is_1g ? 0x200000 :
++							     0x140000);
++
++	/* Setup RXFE BW setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50f0, 0xc10, is_1g ? 0x410 :
++							  is_5g ? 0x800 : 0x400);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);
++
++	/* Setup RX CDR setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5078, 0xf000400, is_5g ? 0x8000000 :
++							      0x7000400);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x507c, 0x5000500, is_5g ? 0x4000400 :
++							      0x1000100);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5080, 0x1410, is_1g ? 0x400 :
++							   is_5g ? 0x1010 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5084, 0x30300, is_1g ? 0x30300 :
++							    is_5g ? 0x30100 :
++								    0x100);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5088, 0x60200, is_1g ? 0x20200 :
++							 is_5g ? 0x40000 :
++								 0x20000);
++
++	/* Setting RXFE adaptation range setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50a8, 0xee0000, is_5g ? 0x800000 :
++							     0x6e0000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);
++	if (is_10g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x01423342);
++	else if (is_5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00a132a1);
++	else if (is_2p5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x009c329c);
++	else
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00fa32fa);
++
++	/* Force SGDT_OUT off and select PCS */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_F4,
++			 XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL,
++			 XFI_DPHY_AD_SGDT_FRC_EN |
++			 (is_xgmii ? XFI_DPHY_PCS_SEL_USXGMII :
++				     XFI_DPHY_PCS_SEL_SGMII));
++
++
++	/* Force GLB_CKDET_OUT */
++	mtk_xfi_tphy_set(xfi_tphy, 0x0030, 0xc00);
++
++	/* Force AEQ on */
++	mtk_xfi_tphy_write(xfi_tphy, REG_DIG_GLB_70,
++			   XTP_PCS_RX_EQ_IN_PROGRESS(2) |
++			   XTP_PCS_PWD_SYNC(2) |
++			   XTP_PCS_PWD_ASYNC(2));
++
++	usleep_range(1, 5);
++
++	/* Setup TX DA default value */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);
++	mtk_xfi_tphy_write(xfi_tphy, 0x3028, 0x00008a01);
++	mtk_xfi_tphy_write(xfi_tphy, 0x302c, 0x0000a884);
++	mtk_xfi_tphy_write(xfi_tphy, 0x3024, 0x00083002);
++
++	/* Setup RG default value */
++	if (is_xgmii) {
++		mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00022220);
++		mtk_xfi_tphy_write(xfi_tphy, 0x5064, 0x0f020a01);
++		mtk_xfi_tphy_write(xfi_tphy, 0x50b4, 0x06100600);
++		if (interface == PHY_INTERFACE_MODE_USXGMII)
++			mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++		else
++			mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x47684100);
++	} else {
++		mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00011110);
++		mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++	}
++
++	if (is_1g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x3064, 0x0000c000);
++
++	/* Setup RX EQ initial value */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x3050, 0xa8000000,
++			 (interface != PHY_INTERFACE_MODE_10GBASER) ?
++			  0xa8000000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x3054, 0xaa,
++			 (interface != PHY_INTERFACE_MODE_10GBASER) ?
++			  0xaa : 0x0);
++
++	if (is_xgmii)
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x00000f00);
++	else if (is_2p5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x22000f00);
++	else
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x20200f00);
++
++	if (interface == PHY_INTERFACE_MODE_10GBASER && xfi_tphy->da_war)
++		mtk_xfi_tphy_rmw(xfi_tphy, 0xa008, 0x10000, 0x10000);
++
++	mtk_xfi_tphy_rmw(xfi_tphy, 0xa060, 0x50000, is_xgmii ? 0x40000 :
++							       0x50000);
++
++	/* Setup PHYA speed */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_ANA_GLB_D0,
++			 XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN,
++			 is_10g ?  XTP_GLB_USXGMII_SEL(0) :
++			 is_5g ?   XTP_GLB_USXGMII_SEL(1) :
++			 is_2p5g ? XTP_GLB_USXGMII_SEL(2) :
++				   XTP_GLB_USXGMII_SEL(3));
++	mtk_xfi_tphy_set(xfi_tphy, REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);
++
++	/* Release reset */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_GLB_70,
++			 XTP_PCS_RST_B | XTP_FRC_PCS_RST_B);
++	usleep_range(150, 500);
++
++	/* Switch to P0 */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++			 XTP_PCS_PWD_SYNC_MASK |
++			 XTP_PCS_PWD_ASYNC_MASK,
++			 XTP_FRC_PCS_PWD_ASYNC |
++			 XTP_PCS_UPDT | XTP_PCS_IN_FR_RG);
++	usleep_range(1, 5);
++
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++	usleep_range(15, 50);
++
++	if (is_xgmii) {
++		/* Switch to Gen3 */
++		mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++				 XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++				 XTP_PCS_MODE(2) | XTP_PCS_UPDT);
++	} else {
++		/* Switch to Gen2 */
++		mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++				 XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++				 XTP_PCS_MODE(1) | XTP_PCS_UPDT);
++	}
++	usleep_range(1, 5);
++
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++
++	usleep_range(100, 500);
++
++	/* Enable MAC CK */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN);
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN);
++
++	/* Enable TX data */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_40,
++			 XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN);
++	usleep_range(400, 1000);
++}
++
++static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int
++				 submode)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	if (mode != PHY_MODE_ETHERNET)
++		return -EINVAL;
++
++	switch (submode) {
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_5GBASER:
++	case PHY_INTERFACE_MODE_10GBASER:
++	case PHY_INTERFACE_MODE_USXGMII:
++		mtk_xfi_tphy_setup(xfi_tphy, submode);
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++static int mtk_xfi_tphy_reset(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	reset_control_assert(xfi_tphy->reset);
++	usleep_range(100, 500);
++	reset_control_deassert(xfi_tphy->reset);
++	usleep_range(1, 10);
++
++	return 0;
++}
++
++static int mtk_xfi_tphy_power_on(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++}
++
++static int mtk_xfi_tphy_power_off(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++
++	return 0;
++}
++
++static const struct phy_ops mtk_xfi_tphy_ops = {
++	.power_on	= mtk_xfi_tphy_power_on,
++	.power_off	= mtk_xfi_tphy_power_off,
++	.set_mode	= mtk_xfi_tphy_set_mode,
++	.reset		= mtk_xfi_tphy_reset,
++	.owner		= THIS_MODULE,
++};
++
++static int mtk_xfi_tphy_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct phy_provider *phy_provider;
++	struct mtk_xfi_tphy *xfi_tphy;
++	struct phy *phy;
++
++	if (!np)
++		return -ENODEV;
++
++	xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL);
++	if (!xfi_tphy)
++		return -ENOMEM;
++
++	xfi_tphy->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
++	if (!xfi_tphy->base)
++		return -EIO;
++
++	xfi_tphy->dev = &pdev->dev;
++
++	xfi_tphy->clocks[0].id = "topxtal";
++	xfi_tphy->clocks[0].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[0].id);
++	if (IS_ERR(xfi_tphy->clocks[0].clk))
++		return PTR_ERR(xfi_tphy->clocks[0].clk);
++
++	xfi_tphy->clocks[1].id = "xfipll";
++	xfi_tphy->clocks[1].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[1].id);
++	if (IS_ERR(xfi_tphy->clocks[1].clk))
++		return PTR_ERR(xfi_tphy->clocks[1].clk);
++
++	xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
++	if (IS_ERR(xfi_tphy->reset))
++		return PTR_ERR(xfi_tphy->reset);
++
++	xfi_tphy->da_war = of_property_read_bool(np,
++						 "mediatek,usxgmii-performance-errata");
++
++	phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops);
++	if (IS_ERR(phy))
++		return PTR_ERR(phy);
++
++	phy_set_drvdata(phy, xfi_tphy);
++
++	phy_provider = devm_of_phy_provider_register(&pdev->dev,
++						     of_phy_simple_xlate);
++
++	return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id mtk_xfi_tphy_match[] = {
++	{ .compatible = "mediatek,mt7988-xfi-tphy", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match);
++
++static struct platform_driver mtk_xfi_tphy_driver = {
++	.probe = mtk_xfi_tphy_probe,
++	.driver = {
++		.name = "mtk-xfi-tphy",
++		.of_match_table = mtk_xfi_tphy_match,
++	},
++};
++module_platform_driver(mtk_xfi_tphy_driver);
++
++MODULE_DESCRIPTION("MediaTek XFI T-PHY driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch b/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch
new file mode 100644
index 0000000000..adb95e9587
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch
@@ -0,0 +1,371 @@
+From 4b1a2716299c0e96a698044aebf3f80513509ae7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:18 +0000
+Subject: [PATCH 3/5] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988
+
+Introduce a proper platform MFD driver for the LynxI (H)SGMII PCS which
+is going to initially be used for the MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c   | 227 ++++++++++++++++++++++++++++--
+ include/linux/pcs/pcs-mtk-lynxi.h |  11 ++
+ 2 files changed, 227 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ // Copyright (c) 2018-2019 MediaTek Inc.
+-/* A library for MediaTek SGMII circuit
++/* A library and platform driver for the MediaTek LynxI SGMII circuit
+  *
+  * Author: Sean Wang <sean.wang@mediatek.com>
+  * Author: Alexander Couzens <lynxis@fe80.eu>
+@@ -8,11 +8,17 @@
+  *
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/mdio.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mutex.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/phylink.h>
++#include <linux/platform_device.h>
+ #include <linux/regmap.h>
++#include <linux/reset.h>
+ 
+ /* SGMII subsystem config registers */
+ /* BMCR (low 16) BMSR (high 16) */
+@@ -65,6 +71,8 @@
+ #define SGMII_PN_SWAP_MASK		GENMASK(1, 0)
+ #define SGMII_PN_SWAP_TX_RX		(BIT(0) | BIT(1))
+ 
++#define MTK_NETSYS_V3_AMA_RGC3		0x128
++
+ /* struct mtk_pcs_lynxi -  This structure holds each sgmii regmap andassociated
+  *                         data
+  * @regmap:                The register map pointing at the range used to setup
+@@ -74,15 +82,29 @@
+  * @interface:             Currently configured interface mode
+  * @pcs:                   Phylink PCS structure
+  * @flags:                 Flags indicating hardware properties
++ * @rstc:                  Reset controller
++ * @sgmii_sel:             SGMII Register Clock
++ * @sgmii_rx:              SGMII RX Clock
++ * @sgmii_tx:              SGMII TX Clock
++ * @node:                  List node
+  */
+ struct mtk_pcs_lynxi {
+ 	struct regmap		*regmap;
++	struct device		*dev;
+ 	u32			ana_rgc3;
+ 	phy_interface_t		interface;
+ 	struct			phylink_pcs pcs;
+ 	u32			flags;
++	struct reset_control	*rstc;
++	struct clk		*sgmii_sel;
++	struct clk		*sgmii_rx;
++	struct clk		*sgmii_tx;
++	struct list_head	node;
+ };
+ 
++static LIST_HEAD(mtk_pcs_lynxi_instances);
++static DEFINE_MUTEX(instance_mutex);
++
+ static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
+ {
+ 	return container_of(pcs, struct mtk_pcs_lynxi, pcs);
+@@ -102,6 +124,17 @@ static void mtk_pcs_lynxi_get_state(stru
+ 					 FIELD_GET(SGMII_LPA, adv));
+ }
+ 
++static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
++{
++	if (!mpcs->rstc)
++		return;
++
++	reset_control_assert(mpcs->rstc);
++	udelay(100);
++	reset_control_deassert(mpcs->rstc);
++	mdelay(1);
++}
++
+ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface,
+ 				const unsigned long *advertising,
+@@ -148,6 +181,7 @@ static int mtk_pcs_lynxi_config(struct p
+ 				SGMII_PHYA_PWD);
+ 
+ 		/* Reset SGMII PCS state */
++		mtk_sgmii_reset(mpcs);
+ 		regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
+ 				SGMII_SW_RESET);
+ 
+@@ -234,10 +268,29 @@ static void mtk_pcs_lynxi_link_up(struct
+ 	}
+ }
+ 
++static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
++{
++	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
++
++	if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++		clk_prepare_enable(mpcs->sgmii_rx);
++		clk_prepare_enable(mpcs->sgmii_tx);
++	}
++
++	return 0;
++}
++
+ static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ 
++	regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++	if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++		clk_disable_unprepare(mpcs->sgmii_tx);
++		clk_disable_unprepare(mpcs->sgmii_rx);
++	}
++
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ }
+ 
+@@ -247,11 +300,12 @@ static const struct phylink_pcs_ops mtk_
+ 	.pcs_an_restart = mtk_pcs_lynxi_restart_an,
+ 	.pcs_link_up = mtk_pcs_lynxi_link_up,
+ 	.pcs_disable = mtk_pcs_lynxi_disable,
++	.pcs_enable = mtk_pcs_lynxi_enable,
+ };
+ 
+-struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
+-					 struct regmap *regmap, u32 ana_rgc3,
+-					 u32 flags)
++static struct phylink_pcs *mtk_pcs_lynxi_init(struct device *dev, struct regmap *regmap,
++					      u32 ana_rgc3, u32 flags,
++					      struct mtk_pcs_lynxi *prealloc)
+ {
+ 	struct mtk_pcs_lynxi *mpcs;
+ 	u32 id, ver;
+@@ -259,29 +313,33 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 
+ 	ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
+ 	if (ret < 0)
+-		return NULL;
++		return ERR_PTR(ret);
+ 
+ 	if (id != SGMII_LYNXI_DEV_ID) {
+ 		dev_err(dev, "unknown PCS device id %08x\n", id);
+-		return NULL;
++		return ERR_PTR(-ENODEV);
+ 	}
+ 
+ 	ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
+ 	if (ret < 0)
+-		return NULL;
++		return ERR_PTR(ret);
+ 
+ 	ver = FIELD_GET(SGMII_DEV_VERSION, ver);
+ 	if (ver != 0x1) {
+ 		dev_err(dev, "unknown PCS device version %04x\n", ver);
+-		return NULL;
++		return ERR_PTR(-ENODEV);
+ 	}
+ 
+ 	dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
+ 		ver);
+ 
+-	mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
+-	if (!mpcs)
+-		return NULL;
++	if (prealloc) {
++		mpcs = prealloc;
++	} else {
++		mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
++		if (!mpcs)
++			return ERR_PTR(-ENOMEM);
++	};
+ 
+ 	mpcs->ana_rgc3 = ana_rgc3;
+ 	mpcs->regmap = regmap;
+@@ -292,6 +350,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ 
+ 	return &mpcs->pcs;
++};
++
++struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
++					 struct regmap *regmap, u32 ana_rgc3,
++					 u32 flags)
++{
++	return mtk_pcs_lynxi_init(dev, regmap, ana_rgc3, flags, NULL);
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_create);
+ 
+@@ -304,4 +369,144 @@ void mtk_pcs_lynxi_destroy(struct phylin
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
+ 
++static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct mtk_pcs_lynxi *mpcs;
++	struct phylink_pcs *pcs;
++	struct regmap *regmap;
++	u32 flags = 0;
++
++	mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++	if (!mpcs)
++		return -ENOMEM;
++
++	mpcs->dev = dev;
++	regmap = syscon_node_to_regmap(np->parent);
++	if (IS_ERR(regmap))
++		return PTR_ERR(regmap);
++
++	if (of_property_read_bool(np->parent, "mediatek,pnswap"))
++		flags |= MTK_SGMII_FLAG_PN_SWAP;
++
++	mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
++	if (IS_ERR(mpcs->rstc))
++		return PTR_ERR(mpcs->rstc);
++
++	reset_control_deassert(mpcs->rstc);
++	mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
++	if (IS_ERR(mpcs->sgmii_sel))
++		return PTR_ERR(mpcs->sgmii_sel);
++
++	mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
++	if (IS_ERR(mpcs->sgmii_rx))
++		return PTR_ERR(mpcs->sgmii_rx);
++
++	mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
++	if (IS_ERR(mpcs->sgmii_tx))
++		return PTR_ERR(mpcs->sgmii_tx);
++
++	pcs = mtk_pcs_lynxi_init(dev, regmap, (uintptr_t)of_device_get_match_data(dev),
++				 flags, mpcs);
++	if (IS_ERR(pcs))
++		return PTR_ERR(pcs);
++
++	regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++	platform_set_drvdata(pdev, mpcs);
++
++	mutex_lock(&instance_mutex);
++	list_add_tail(&mpcs->node, &mtk_pcs_lynxi_instances);
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static int mtk_pcs_lynxi_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_pcs_lynxi *cur, *tmp;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry_safe(cur, tmp, &mtk_pcs_lynxi_instances, node)
++		if (cur->dev == dev) {
++			list_del(&cur->node);
++			kfree(cur);
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static const struct of_device_id mtk_pcs_lynxi_of_match[] = {
++	{ .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_pcs_lynxi_of_match);
++
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++	struct platform_device *pdev;
++	struct mtk_pcs_lynxi *mpcs;
++
++	if (!np)
++		return NULL;
++
++	if (!of_device_is_available(np))
++		return ERR_PTR(-ENODEV);
++
++	if (!of_match_node(mtk_pcs_lynxi_of_match, np))
++		return ERR_PTR(-EINVAL);
++
++	pdev = of_find_device_by_node(np);
++	if (!pdev || !platform_get_drvdata(pdev)) {
++		if (pdev)
++			put_device(&pdev->dev);
++		return ERR_PTR(-EPROBE_DEFER);
++	}
++
++	mpcs = platform_get_drvdata(pdev);
++	device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++	return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_get);
++
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs)
++{
++	struct mtk_pcs_lynxi *cur, *mpcs = NULL;
++
++	if (!pcs)
++		return;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry(cur, &mtk_pcs_lynxi_instances, node)
++		if (pcs == &cur->pcs) {
++			mpcs = cur;
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	if (WARN_ON(!mpcs))
++		return;
++
++	put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_put);
++
++static struct platform_driver mtk_pcs_lynxi_driver = {
++	.driver = {
++		.name			= "mtk-pcs-lynxi",
++		.suppress_bind_attrs	= true,
++		.of_match_table		= mtk_pcs_lynxi_of_match,
++	},
++	.probe = mtk_pcs_lynxi_probe,
++	.remove = mtk_pcs_lynxi_remove,
++};
++module_platform_driver(mtk_pcs_lynxi_driver);
++
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("MediaTek LynxI HSGMII PCS");
+ MODULE_LICENSE("GPL");
+--- a/include/linux/pcs/pcs-mtk-lynxi.h
++++ b/include/linux/pcs/pcs-mtk-lynxi.h
+@@ -10,4 +10,15 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 					 struct regmap *regmap,
+ 					 u32 ana_rgc3, u32 flags);
+ void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs);
++
++#if IS_ENABLED(CONFIG_PCS_MTK_LYNXI)
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np);
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++	return NULL;
++}
++static inline void mtk_pcs_lynxi_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_LYNXI) */
+ #endif
diff --git a/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch b/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
new file mode 100644
index 0000000000..215bd2ca2e
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
@@ -0,0 +1,81 @@
+From 7d88d79c0f65b27a92754d7547f7af098b3de67b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:31 +0000
+Subject: [PATCH 4/5] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
+ PCS
+
+MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
+it in order to configure and monitor the Ethernet SerDes link in
+USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
+legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
+interface modes are also available.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/net/pcs/mediatek,usxgmii.yaml    | 60 +++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+@@ -0,0 +1,60 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek USXGMII PCS
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek USXGMII PCS provides physical link control and status
++  for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
++  provided by the PEXTP PHY.
++  In order to also support legacy 2500Base-X, 1000Base-X and Cisco
++  SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
++  provide those interfaces modes on the same SerDes interfaces shared
++  with the USXGMII PCS.
++
++properties:
++  $nodename:
++    pattern: "^pcs@[0-9a-f]+$"
++
++  compatible:
++    const: mediatek,mt7988-usxgmiisys
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: USXGMII top-level clock
++
++  resets:
++    items:
++      - description: XFI reset
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - resets
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++    #define MT7988_TOPRGU_XFI0_GRST 12
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++        usxgmiisys0: pcs@10080000 {
++          compatible = "mediatek,mt7988-usxgmiisys";
++          reg = <0 0x10080000 0 0x1000>;
++          clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
++          resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
++        };
++    };
diff --git a/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch b/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
new file mode 100644
index 0000000000..5bd2850fec
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
@@ -0,0 +1,547 @@
+From dde0e95fff92e9f5009f3bea75278e0e34a48822 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:47 +0000
+Subject: [PATCH 5/5] net: pcs: add driver for MediaTek USXGMII PCS
+
+Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
+USXGMII, 10GBase-R and 5GBase-R interface modes.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                         |   2 +
+ drivers/net/pcs/Kconfig             |  11 +
+ drivers/net/pcs/Makefile            |   1 +
+ drivers/net/pcs/pcs-mtk-usxgmii.c   | 456 ++++++++++++++++++++++++++++
+ include/linux/pcs/pcs-mtk-usxgmii.h |  27 ++
+ 5 files changed, 497 insertions(+)
+ create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
+ create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -12934,7 +12934,9 @@ M:	Daniel Golle <daniel@makrotopia.org>
+ L:	netdev@vger.kernel.org
+ S:	Maintained
+ F:	drivers/net/pcs/pcs-mtk-lynxi.c
++F:	drivers/net/pcs/pcs-mtk-usxgmii.c
+ F:	include/linux/pcs/pcs-mtk-lynxi.h
++F:	include/linux/pcs/pcs-mtk-usxgmii.h
+ 
+ MEDIATEK I2C CONTROLLER DRIVER
+ M:	Qii Wang <qii.wang@mediatek.com>
+--- a/drivers/net/pcs/Kconfig
++++ b/drivers/net/pcs/Kconfig
+@@ -18,6 +18,17 @@ config PCS_LYNX
+ 	  This module provides helpers to phylink for managing the Lynx PCS
+ 	  which is part of the Layerscape and QorIQ Ethernet SERDES.
+ 
++config PCS_MTK_USXGMII
++	tristate "MediaTek USXGMII PCS"
++	select PCS_MTK_LYNXI
++	select PHY_MTK_PEXTP
++	select PHYLINK
++	help
++	  This module provides a driver for MediaTek's USXGMII PCS supporting
++	  10GBase-R, 5GBase-R and USXGMII interface modes.
++	  1000Base-X, 2500Base-X and Cisco SGMII are supported on the same
++	  differential pairs via an embedded LynxI PHY.
++
+ config PCS_RZN1_MIIC
+ 	tristate "Renesas RZ/N1 MII converter"
+ 	depends on OF && (ARCH_RZN1 || COMPILE_TEST)
+--- a/drivers/net/pcs/Makefile
++++ b/drivers/net/pcs/Makefile
+@@ -8,3 +8,4 @@ obj-$(CONFIG_PCS_LYNX)		+= pcs-lynx.o
+ obj-$(CONFIG_PCS_RZN1_MIIC)	+= pcs-rzn1-miic.o
+ obj-$(CONFIG_PCS_ALTERA_TSE)	+= pcs-altera-tse.o
+ obj-$(CONFIG_PCS_MTK_LYNXI)	+= pcs-mtk-lynxi.o
++obj-$(CONFIG_PCS_MTK_USXGMII)	+= pcs-mtk-usxgmii.o
+--- /dev/null
++++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
+@@ -0,0 +1,456 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ *         Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mdio.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/reset.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/platform_device.h>
++
++/* USXGMII subsystem config registers */
++/* Register to control speed */
++#define RG_PHY_TOP_SPEED_CTRL1			0x80c
++#define USXGMII_RATE_UPDATE_MODE		BIT(31)
++#define USXGMII_MAC_CK_GATED			BIT(29)
++#define USXGMII_IF_FORCE_EN			BIT(28)
++#define USXGMII_RATE_ADAPT_MODE			GENMASK(10, 8)
++#define USXGMII_RATE_ADAPT_MODE_X1		0
++#define USXGMII_RATE_ADAPT_MODE_X2		1
++#define USXGMII_RATE_ADAPT_MODE_X4		2
++#define USXGMII_RATE_ADAPT_MODE_X10		3
++#define USXGMII_RATE_ADAPT_MODE_X100		4
++#define USXGMII_RATE_ADAPT_MODE_X5		5
++#define USXGMII_RATE_ADAPT_MODE_X50		6
++#define USXGMII_XFI_RX_MODE			GENMASK(6, 4)
++#define USXGMII_XFI_TX_MODE			GENMASK(2, 0)
++#define USXGMII_XFI_MODE_10G			0
++#define USXGMII_XFI_MODE_5G			1
++#define USXGMII_XFI_MODE_2P5G			3
++
++/* Register to control PCS AN */
++#define RG_PCS_AN_CTRL0				0x810
++#define USXGMII_AN_RESTART			BIT(31)
++#define USXGMII_AN_SYNC_CNT			GENMASK(30, 11)
++#define USXGMII_AN_ENABLE			BIT(0)
++
++#define RG_PCS_AN_CTRL2				0x818
++#define USXGMII_LINK_TIMER_IDLE_DETECT		GENMASK(29, 20)
++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT	GENMASK(19, 10)
++#define USXGMII_LINK_TIMER_AN_RESTART		GENMASK(9, 0)
++
++/* Register to read PCS AN status */
++#define RG_PCS_AN_STS0				0x81c
++#define USXGMII_LPA				GENMASK(15, 0)
++#define USXGMII_LPA_LATCH			BIT(31)
++
++/* Register to read PCS link status */
++#define RG_PCS_RX_STATUS0			0x904
++#define RG_PCS_RX_STATUS_UPDATE			BIT(16)
++#define RG_PCS_RX_LINK_STATUS			BIT(2)
++
++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii PCS
++ * @pcs:		Phylink PCS structure
++ * @dev:		Pointer to device structure
++ * @base:		IO memory to access PCS hardware
++ * @clk:		Pointer to USXGMII clk
++ * @reset:		Pointer to USXGMII reset control
++ * @interface:		Currently selected interface mode
++ * @neg_mode:		Currently used phylink neg_mode
++ * @node:		List node
++ */
++struct mtk_usxgmii_pcs {
++	struct phylink_pcs		pcs;
++	struct device			*dev;
++	void __iomem			*base;
++	struct clk			*clk;
++	struct reset_control		*reset;
++	phy_interface_t			interface;
++	unsigned int			neg_mode;
++	struct list_head		node;
++};
++
++static LIST_HEAD(mtk_usxgmii_pcs_instances);
++static DEFINE_MUTEX(instance_mutex);
++
++static u32 mtk_r32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg)
++{
++	return ioread32(mpcs->base + reg);
++}
++
++static void mtk_m32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg, u32 mask, u32 set)
++{
++	u32 val;
++
++	val = ioread32(mpcs->base + reg);
++	val &= ~mask;
++	val |= set;
++	iowrite32(val, mpcs->base + reg);
++}
++
++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
++{
++	return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
++}
++
++static void mtk_usxgmii_reset(struct mtk_usxgmii_pcs *mpcs)
++{
++	reset_control_assert(mpcs->reset);
++	udelay(100);
++	reset_control_deassert(mpcs->reset);
++
++	mdelay(10);
++}
++
++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
++				  phy_interface_t interface,
++				  const unsigned long *advertising,
++				  bool permit_pause_to_mac)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++	unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
++	bool mode_changed = false;
++
++	if (interface == PHY_INTERFACE_MODE_USXGMII) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++	} else if (interface == PHY_INTERFACE_MODE_10GBASER) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else if (interface == PHY_INTERFACE_MODE_5GBASER) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else {
++		return -EINVAL;
++	}
++
++	adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
++
++	if (mpcs->interface != interface) {
++		mpcs->interface = interface;
++		mode_changed = true;
++	}
++
++	mtk_usxgmii_reset(mpcs);
++
++	/* Setup USXGMII AN ctrl */
++	mtk_m32(mpcs, RG_PCS_AN_CTRL0,
++		USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
++		an_ctrl);
++
++	mtk_m32(mpcs, RG_PCS_AN_CTRL2,
++		USXGMII_LINK_TIMER_IDLE_DETECT |
++		USXGMII_LINK_TIMER_COMP_ACK_DETECT |
++		USXGMII_LINK_TIMER_AN_RESTART,
++		link_timer);
++
++	mpcs->neg_mode = neg_mode;
++
++	/* Gated MAC CK */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
++
++	/* Enable interface force mode */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
++
++	/* Setup USXGMII adapt mode */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
++		adapt_mode);
++
++	/* Setup USXGMII speed */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
++		xfi_mode);
++
++	usleep_range(1, 10);
++
++	/* Un-gated MAC CK */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
++
++	usleep_range(1, 10);
++
++	/* Disable interface force mode for the AN mode */
++	if (an_ctrl & USXGMII_AN_ENABLE)
++		mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
++
++	return mode_changed;
++}
++
++static void mtk_usxgmii_pcs_get_fixed_speed(struct mtk_usxgmii_pcs *mpcs,
++					    struct phylink_link_state *state)
++{
++	u32 val = mtk_r32(mpcs, RG_PHY_TOP_SPEED_CTRL1);
++	int speed;
++
++	/* Calculate speed from interface speed and rate adapt mode */
++	switch (FIELD_GET(USXGMII_XFI_RX_MODE, val)) {
++	case USXGMII_XFI_MODE_10G:
++		speed = 10000;
++		break;
++	case USXGMII_XFI_MODE_5G:
++		speed = 5000;
++		break;
++	case USXGMII_XFI_MODE_2P5G:
++		speed = 2500;
++		break;
++	default:
++		state->speed = SPEED_UNKNOWN;
++		return;
++	}
++
++	switch (FIELD_GET(USXGMII_RATE_ADAPT_MODE, val)) {
++	case USXGMII_RATE_ADAPT_MODE_X100:
++		speed /= 100;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X50:
++		speed /= 50;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X10:
++		speed /= 10;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X5:
++		speed /= 5;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X4:
++		speed /= 4;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X2:
++		speed /= 2;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X1:
++		break;
++	default:
++		state->speed = SPEED_UNKNOWN;
++		return;
++	}
++
++	state->speed = speed;
++	state->duplex = DUPLEX_FULL;
++}
++
++static void mtk_usxgmii_pcs_get_an_state(struct mtk_usxgmii_pcs *mpcs,
++					 struct phylink_link_state *state)
++{
++	u16 lpa;
++
++	/* Refresh LPA by toggling LPA_LATCH */
++	mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, USXGMII_LPA_LATCH);
++	ndelay(1020);
++	mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, 0);
++	ndelay(1020);
++	lpa = FIELD_GET(USXGMII_LPA, mtk_r32(mpcs, RG_PCS_AN_STS0));
++
++	phylink_decode_usxgmii_word(state, lpa);
++}
++
++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
++				      struct phylink_link_state *state)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	/* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
++	mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
++		RG_PCS_RX_STATUS_UPDATE);
++	ndelay(1020);
++	mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
++	ndelay(1020);
++
++	/* Read USXGMII link status */
++	state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
++				mtk_r32(mpcs, RG_PCS_RX_STATUS0));
++
++	/* Continuously repeat re-configuration sequence until link comes up */
++	if (!state->link) {
++		mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
++				       state->interface, NULL, false);
++		return;
++	}
++
++	if (FIELD_GET(USXGMII_AN_ENABLE, mtk_r32(mpcs, RG_PCS_AN_CTRL0)))
++		mtk_usxgmii_pcs_get_an_state(mpcs, state);
++	else
++		mtk_usxgmii_pcs_get_fixed_speed(mpcs, state);
++}
++
++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	mtk_m32(mpcs, RG_PCS_AN_CTRL0, USXGMII_AN_RESTART, USXGMII_AN_RESTART);
++}
++
++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
++				    phy_interface_t interface,
++				    int speed, int duplex)
++{
++	/* Reconfiguring USXGMII to ensure the quality of the RX signal
++	 * after the line side link up.
++	 */
++	mtk_usxgmii_pcs_config(pcs, neg_mode, interface, NULL, false);
++}
++
++static void mtk_usxgmii_pcs_disable(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	mpcs->interface = PHY_INTERFACE_MODE_NA;
++	mpcs->neg_mode = -1;
++}
++
++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
++	.pcs_config = mtk_usxgmii_pcs_config,
++	.pcs_get_state = mtk_usxgmii_pcs_get_state,
++	.pcs_an_restart = mtk_usxgmii_pcs_restart_an,
++	.pcs_link_up = mtk_usxgmii_pcs_link_up,
++	.pcs_disable = mtk_usxgmii_pcs_disable,
++};
++
++static int mtk_usxgmii_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_usxgmii_pcs *mpcs;
++
++	mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++	if (!mpcs)
++		return -ENOMEM;
++
++	mpcs->base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(mpcs->base))
++		return PTR_ERR(mpcs->base);
++
++	mpcs->dev = dev;
++	mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
++	mpcs->pcs.poll = true;
++	mpcs->pcs.neg_mode = true;
++	mpcs->interface = PHY_INTERFACE_MODE_NA;
++	mpcs->neg_mode = -1;
++
++	mpcs->clk = devm_clk_get_enabled(mpcs->dev, NULL);
++	if (IS_ERR(mpcs->clk))
++		return PTR_ERR(mpcs->clk);
++
++	mpcs->reset = devm_reset_control_get_shared(dev, NULL);
++	if (IS_ERR(mpcs->reset))
++		return PTR_ERR(mpcs->reset);
++
++	reset_control_deassert(mpcs->reset);
++
++	platform_set_drvdata(pdev, mpcs);
++
++	mutex_lock(&instance_mutex);
++	list_add_tail(&mpcs->node, &mtk_usxgmii_pcs_instances);
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static int mtk_usxgmii_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_usxgmii_pcs *cur, *tmp;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry_safe(cur, tmp, &mtk_usxgmii_pcs_instances, node)
++		if (cur->dev == dev) {
++			list_del(&cur->node);
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static const struct of_device_id mtk_usxgmii_of_mtable[] = {
++	{ .compatible = "mediatek,mt7988-usxgmiisys" },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_usxgmii_of_mtable);
++
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++	struct platform_device *pdev;
++	struct mtk_usxgmii_pcs *mpcs;
++
++	if (!np)
++		return NULL;
++
++	if (!of_device_is_available(np))
++		return ERR_PTR(-ENODEV);
++
++	if (!of_match_node(mtk_usxgmii_of_mtable, np))
++		return ERR_PTR(-EINVAL);
++
++	pdev = of_find_device_by_node(np);
++	if (!pdev || !platform_get_drvdata(pdev)) {
++		if (pdev)
++			put_device(&pdev->dev);
++		return ERR_PTR(-EPROBE_DEFER);
++	}
++
++	mpcs = platform_get_drvdata(pdev);
++	device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++	return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_get);
++
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *cur, *mpcs = NULL;
++
++	if (!pcs)
++		return;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry(cur, &mtk_usxgmii_pcs_instances, node)
++		if (pcs == &cur->pcs) {
++			mpcs = cur;
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	if (WARN_ON(!mpcs))
++		return;
++
++	put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_put);
++
++static struct platform_driver mtk_usxgmii_driver = {
++	.driver = {
++		.name			= "mtk_usxgmii",
++		.suppress_bind_attrs	= true,
++		.of_match_table		= mtk_usxgmii_of_mtable,
++	},
++	.probe = mtk_usxgmii_probe,
++	.remove = mtk_usxgmii_remove,
++};
++module_platform_driver(mtk_usxgmii_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("MediaTek USXGMII PCS driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+--- /dev/null
++++ b/include/linux/pcs/pcs-mtk-usxgmii.h
+@@ -0,0 +1,27 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __LINUX_PCS_MTK_USXGMII_H
++#define __LINUX_PCS_MTK_USXGMII_H
++
++#include <linux/phylink.h>
++
++/**
++ * mtk_usxgmii_select_pcs() - Get MediaTek PCS instance
++ * @np:		Pointer to device node indentifying a MediaTek USXGMII PCS
++ * @mode:	Ethernet PHY interface mode
++ *
++ * Return PCS identified by a device node and the PHY interface mode in use
++ *
++ * Return:	Pointer to phylink PCS instance of NULL
++ */
++#if IS_ENABLED(CONFIG_PCS_MTK_USXGMII)
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np);
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++	return NULL;
++}
++static inline void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_USXGMII) */
++
++#endif /* __LINUX_PCS_MTK_USXGMII_H */
diff --git a/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch b/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
new file mode 100644
index 0000000000..1dfa1366eb
--- /dev/null
+++ b/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
@@ -0,0 +1,1115 @@
+From patchwork Tue Feb  6 19:47:51 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
+X-Patchwork-Id: 13547762
+X-Patchwork-Delegate: kuba@kernel.org
+From: Eric Woudstra <ericwouds@gmail.com>
+To: "David S. Miller" <davem@davemloft.net>,
+	Eric Dumazet <edumazet@google.com>,
+	Jakub Kicinski <kuba@kernel.org>,
+	Paolo Abeni <pabeni@redhat.com>,
+	Rob Herring <robh+dt@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Andrew Lunn <andrew@lunn.ch>,
+	Heiner Kallweit <hkallweit1@gmail.com>,
+	Russell King <linux@armlinux.org.uk>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	"Frank Wunderlich" <frank-w@public-files.de>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Lucien Jheng  <lucien.jheng@airoha.com>,
+	Zhi-Jun You <hujy652@protonmail.com>
+Cc: netdev@vger.kernel.org,
+	devicetree@vger.kernel.org,
+	Eric Woudstra <ericwouds@gmail.com>
+Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
+ PHY driver
+Date: Tue,  6 Feb 2024 20:47:51 +0100
+Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
+X-Mailer: git-send-email 2.42.1
+In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
+References: <20240206194751.1901802-1-ericwouds@gmail.com>
+Precedence: bulk
+X-Mailing-List: netdev@vger.kernel.org
+List-Id: <netdev.vger.kernel.org>
+List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+X-Patchwork-Delegate: kuba@kernel.org
+
+* Source originated from airoha's en8811h v1.2.1 driver
+ * Moved air_en8811h.h to air_en8811h.c
+ * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
+ * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
+ * Added .get_rate_matching()
+ * Use generic phy_read/write() and phy_read/write_mmd()
+ * Edited .get_features() to use generic C45 functions
+ * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
+ * Use led handling functions from mediatek-ge-soc.c
+ * Simplified led handling by storing led rules
+ * Cleanup macro definitions
+ * Cleanup code to pass checkpatch.pl
+ * General code cleanup
+
+Changes from original RFC patch:
+
+ * Use the correct order in Kconfig and Makefile
+ * Change some register naming to correspond with datasheet
+ * Use phy_driver .read_page() and .write_page()
+ * Use module_phy_driver()
+ * Use get_unaligned_le16() instead of macro
+ * In .config_aneg() and .read_status() use genphy_xxx() C22
+ * Use another vendor register to read real speed
+ * Load firmware only once and store firmware version
+ * Apply 2.5G LPA work-around (firmware before 24011202)
+ * Read 2.5G LPA from vendor register (firmware 24011202 and later)
+
+Changes to be committed:
+	modified:   drivers/net/phy/Kconfig
+	modified:   drivers/net/phy/Makefile
+	new file:   drivers/net/phy/air_en8811h.c
+
+Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
+---
+ drivers/net/phy/Kconfig       |    5 +
+ drivers/net/phy/Makefile      |    1 +
+ drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
+ 3 files changed, 1012 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8811h.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -69,6 +69,11 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AIR_EN8811H_PHY
++	tristate "Airoha EN8811H 2.5 Gigabit PHY"
++	help
++	  Currently supports the Airoha EN8811H PHY.
++
+ config AMD_PHY
+ 	tristate "AMD and Altima PHYs"
+ 	help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,6 +32,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
++obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,1006 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Driver for Airoha Ethernet PHYs
++ *
++ * Currently supporting the EN8811H.
++ *
++ * Limitations of the EN8811H:
++ * - Only full duplex supported
++ * - Forced speed (AN off) is not supported by hardware (100Mbps)
++ *
++ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
++ *
++ * Copyright (C) 2023 Airoha Technology Corp.
++ */
++
++#include <linux/phy.h>
++#include <linux/firmware.h>
++#include <linux/property.h>
++#include <asm/unaligned.h>
++
++#define EN8811H_PHY_ID		0x03a2a411
++
++#define EN8811H_MD32_DM		"airoha/EthMD32.dm.bin"
++#define EN8811H_MD32_DSP	"airoha/EthMD32.DSP.bin"
++
++#define AIR_FW_ADDR_DM	0x00000000
++#define AIR_FW_ADDR_DSP	0x00100000
++
++/* u32 (DWORD) component macros */
++#define LOWORD(d) ((u16)(u32)(d))
++#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
++
++/* MII Registers */
++#define AIR_AUX_CTRL_STATUS	0x1d
++#define   AIR_AUX_CTRL_STATUS_SPEED_MASK	GENMASK(4, 2)
++#define   AIR_AUX_CTRL_STATUS_SPEED_100		0x4
++#define   AIR_AUX_CTRL_STATUS_SPEED_1000	0x8
++#define   AIR_AUX_CTRL_STATUS_SPEED_2500	0xc
++
++#define AIR_EXT_PAGE_ACCESS		0x1f
++#define   AIR_PHY_PAGE_STANDARD			0x0000
++#define   AIR_PHY_PAGE_EXTENDED_4		0x0004
++
++/* MII Registers Page 4*/
++#define AIR_PBUS_MODE			0x10
++#define   AIR_PBUS_MODE_ADDR_FIXED		0x0000
++#define   AIR_PBUS_MODE_ADDR_INCR		BIT(15)
++#define AIR_PBUS_WR_ADDR_HIGH		0x11
++#define AIR_PBUS_WR_ADDR_LOW		0x12
++#define AIR_PBUS_WR_DATA_HIGH		0x13
++#define AIR_PBUS_WR_DATA_LOW		0x14
++#define AIR_PBUS_RD_ADDR_HIGH		0x15
++#define AIR_PBUS_RD_ADDR_LOW		0x16
++#define AIR_PBUS_RD_DATA_HIGH		0x17
++#define AIR_PBUS_RD_DATA_LOW		0x18
++
++/* Registers on MDIO_MMD_VEND1 */
++#define EN8811H_PHY_FW_STATUS		0x8009
++#define   EN8811H_PHY_READY			0x02
++
++#define AIR_PHY_HOST_CMD_1		0x800c
++#define AIR_PHY_HOST_CMD_1_MODE1		0x0
++#define AIR_PHY_HOST_CMD_2		0x800d
++#define AIR_PHY_HOST_CMD_2_MODE1		0x0
++#define AIR_PHY_HOST_CMD_3		0x800e
++#define AIR_PHY_HOST_CMD_3_MODE1		0x1101
++#define AIR_PHY_HOST_CMD_3_DOCMD		0x1100
++#define AIR_PHY_HOST_CMD_4		0x800f
++#define AIR_PHY_HOST_CMD_4_MODE1		0x0002
++#define AIR_PHY_HOST_CMD_4_INTCLR		0x00e4
++
++/* Registers on MDIO_MMD_VEND2 */
++#define AIR_PHY_LED_BCR			0x021
++#define   AIR_PHY_LED_BCR_MODE_MASK		GENMASK(1, 0)
++#define   AIR_PHY_LED_BCR_TIME_TEST		BIT(2)
++#define   AIR_PHY_LED_BCR_CLK_EN		BIT(3)
++#define   AIR_PHY_LED_BCR_EXT_CTRL		BIT(15)
++
++#define AIR_PHY_LED_DUR_ON		0x022
++
++#define AIR_PHY_LED_DUR_BLINK		0x023
++
++#define AIR_PHY_LED_ON(i)	       (0x024 + ((i) * 2))
++#define   AIR_PHY_LED_ON_MASK			(GENMASK(6, 0) | BIT(8))
++#define   AIR_PHY_LED_ON_LINK1000		BIT(0)
++#define   AIR_PHY_LED_ON_LINK100		BIT(1)
++#define   AIR_PHY_LED_ON_LINK10			BIT(2)
++#define   AIR_PHY_LED_ON_LINKDOWN		BIT(3)
++#define   AIR_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
++#define   AIR_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
++#define   AIR_PHY_LED_ON_FORCE_ON		BIT(6)
++#define   AIR_PHY_LED_ON_LINK2500		BIT(8)
++#define   AIR_PHY_LED_ON_POLARITY		BIT(14)
++#define   AIR_PHY_LED_ON_ENABLE			BIT(15)
++
++#define AIR_PHY_LED_BLINK(i)	       (0x025 + ((i) * 2))
++#define   AIR_PHY_LED_BLINK_1000TX		BIT(0)
++#define   AIR_PHY_LED_BLINK_1000RX		BIT(1)
++#define   AIR_PHY_LED_BLINK_100TX		BIT(2)
++#define   AIR_PHY_LED_BLINK_100RX		BIT(3)
++#define   AIR_PHY_LED_BLINK_10TX		BIT(4)
++#define   AIR_PHY_LED_BLINK_10RX		BIT(5)
++#define   AIR_PHY_LED_BLINK_COLLISION		BIT(6)
++#define   AIR_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
++#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
++#define   AIR_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
++#define   AIR_PHY_LED_BLINK_2500TX		BIT(10)
++#define   AIR_PHY_LED_BLINK_2500RX		BIT(11)
++
++/* Registers on BUCKPBUS */
++#define EN8811H_2P5G_LPA		0x3b30
++#define   EN8811H_2P5G_LPA_2P5G			BIT(0)
++
++#define EN8811H_FW_VERSION		0x3b3c
++
++#define EN8811H_POLARITY		0xca0f8
++#define   EN8811H_POLARITY_TX_NORMAL		BIT(0)
++#define   EN8811H_POLARITY_RX_REVERSE		BIT(1)
++
++#define EN8811H_GPIO_OUTPUT		0xcf8b8
++#define   EN8811H_GPIO_OUTPUT_345		(BIT(3) | BIT(4) | BIT(5))
++
++#define EN8811H_FW_CTRL_1		0x0f0018
++#define   EN8811H_FW_CTRL_1_START		0x0
++#define   EN8811H_FW_CTRL_1_FINISH		0x1
++#define EN8811H_FW_CTRL_2		0x800000
++#define EN8811H_FW_CTRL_2_LOADING		BIT(11)
++
++#define EN8811H_LED_COUNT	3
++
++/* GPIO5  <-> BASE_T_LED0
++ * GPIO4  <-> BASE_T_LED1
++ * GPIO3  <-> BASE_T_LED2
++ *
++ * Default setup suitable for 2 leds connected:
++ *    100M link up triggers led0, only led0 blinking on traffic
++ *   1000M link up triggers led1, only led1 blinking on traffic
++ *   2500M link up triggers led0 and led1, both blinking on traffic
++ * Also suitable for 1 led connected:
++ *     any link up triggers led2
++ */
++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_100)  | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_1000) | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED2  BIT(TRIGGER_NETDEV_LINK)
++
++struct led {
++	unsigned long rules;
++	unsigned long state;
++};
++
++struct en8811h_priv {
++	u32		firmware_version;
++	struct led	led[EN8811H_LED_COUNT];
++};
++
++enum {
++	AIR_PHY_LED_STATE_FORCE_ON,
++	AIR_PHY_LED_STATE_FORCE_BLINK,
++};
++
++enum {
++	AIR_PHY_LED_DUR_BLINK_32M,
++	AIR_PHY_LED_DUR_BLINK_64M,
++	AIR_PHY_LED_DUR_BLINK_128M,
++	AIR_PHY_LED_DUR_BLINK_256M,
++	AIR_PHY_LED_DUR_BLINK_512M,
++	AIR_PHY_LED_DUR_BLINK_1024M,
++};
++
++enum {
++	AIR_LED_DISABLE,
++	AIR_LED_ENABLE,
++};
++
++enum {
++	AIR_ACTIVE_LOW,
++	AIR_ACTIVE_HIGH,
++};
++
++enum {
++	AIR_LED_MODE_DISABLE,
++	AIR_LED_MODE_USER_DEFINE,
++};
++
++#define AIR_PHY_LED_DUR_UNIT	1024
++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
++
++static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++					       BIT(TRIGGER_NETDEV_LINK)        |
++					       BIT(TRIGGER_NETDEV_LINK_10)     |
++					       BIT(TRIGGER_NETDEV_LINK_100)    |
++					       BIT(TRIGGER_NETDEV_LINK_1000)   |
++					       BIT(TRIGGER_NETDEV_LINK_2500)   |
++					       BIT(TRIGGER_NETDEV_RX)          |
++					       BIT(TRIGGER_NETDEV_TX));
++
++static int air_phy_read_page(struct phy_device *phydev)
++{
++	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
++}
++
++static int air_phy_write_page(struct phy_device *phydev, int page)
++{
++	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
++}
++
++static int __air_buckpbus_reg_write(struct phy_device *phydev,
++				    u32 pbus_address, u32 pbus_data)
++{
++	int ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW,  LOWORD(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int air_buckpbus_reg_write(struct phy_device *phydev,
++				  u32 pbus_address, u32 pbus_data)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   pbus_address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++;
++}
++
++static int __air_buckpbus_reg_read(struct phy_device *phydev,
++				   u32 pbus_address, u32 *pbus_data)
++{
++	int pbus_data_low, pbus_data_high;
++	int ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW,  LOWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
++	if (pbus_data_high < 0)
++		return ret;
++
++	pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
++	if (pbus_data_low < 0)
++		return ret;
++
++	*pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
++	return 0;
++}
++
++static int air_buckpbus_reg_read(struct phy_device *phydev,
++				 u32 pbus_address, u32 *pbus_data)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   pbus_address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_write_buf(struct phy_device *phydev, u32 address,
++			   const struct firmware *fw)
++{
++	unsigned int offset;
++	int ret;
++	u16 val;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(address));
++	if (ret < 0)
++		return ret;
++
++	for (offset = 0; offset < fw->size; offset += 4) {
++		val = get_unaligned_le16(&fw->data[offset + 2]);
++		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
++		if (ret < 0)
++			return ret;
++
++		val = get_unaligned_le16(&fw->data[offset]);
++		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int air_write_buf(struct phy_device *phydev, u32 address,
++			 const struct firmware *fw)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_write_buf(phydev, address, fw);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	const struct firmware *fw1, *fw2;
++	u32 pbus_value;
++	int ret;
++
++	ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
++	if (ret < 0)
++		return ret;
++
++	ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
++	if (ret < 0)
++		goto en8811h_load_firmware_rel1;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++	pbus_value |= EN8811H_FW_CTRL_2_LOADING;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++	pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = 0;
++
++en8811h_load_firmware_out:
++	release_firmware(fw2);
++
++en8811h_load_firmware_rel1:
++	release_firmware(fw1);
++
++	if (ret < 0)
++		phydev_err(phydev, "Load firmware failed: %d\n", ret);
++
++	return ret;
++}
++
++static int en8811h_restart_host(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		return ret;
++
++	return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++}
++
++static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (on)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
++				      AIR_PHY_LED_ON(index),
++				      AIR_PHY_LED_ON_MASK,
++				      on ? AIR_PHY_LED_ON_FORCE_ON : 0);
++
++	return 0;
++}
++
++static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
++				bool blinking)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (blinking)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_write_mmd(phydev, MDIO_MMD_VEND2,
++				     AIR_PHY_LED_BLINK(index),
++				     blinking ?
++				     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
++	else
++		return 0;
++}
++
++static int air_led_blink_set(struct phy_device *phydev, u8 index,
++			     unsigned long *delay_on,
++			     unsigned long *delay_off)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool blinking = false;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++		blinking = true;
++		*delay_on = 50;
++		*delay_off = 50;
++	}
++
++	err = air_hw_led_blink_set(phydev, index, blinking);
++	if (err)
++		return err;
++
++	/* led-blink set, so switch led-on off */
++	err = air_hw_led_on_set(phydev, index, false);
++	if (err)
++		return err;
++
++	/* hw-control is off*/
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_brightness_set(struct phy_device *phydev, u8 index,
++				  enum led_brightness value)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* led-on set, so switch led-blink off */
++	err = air_hw_led_blink_set(phydev, index, false);
++	if (err)
++		return err;
++
++	err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
++	if (err)
++		return err;
++
++	/* hw-control is off */
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
++				  unsigned long *rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	*rules = priv->led[index].rules;
++
++	return 0;
++};
++
++static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
++				  unsigned long rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u16 on = 0, blink = 0;
++	int ret;
++
++	priv->led[index].rules = rules;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_10)   | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK10;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_10RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_10TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_100)  | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK100;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_100RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_100TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK1000;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_1000RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_1000TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK2500;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_2500RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_2500TX;
++	}
++
++	if (on == 0) {
++		if (rules & BIT(TRIGGER_NETDEV_RX)) {
++			blink |= AIR_PHY_LED_BLINK_10RX   |
++				 AIR_PHY_LED_BLINK_100RX  |
++				 AIR_PHY_LED_BLINK_1000RX |
++				 AIR_PHY_LED_BLINK_2500RX;
++		}
++		if (rules & BIT(TRIGGER_NETDEV_TX)) {
++			blink |= AIR_PHY_LED_BLINK_10TX   |
++				 AIR_PHY_LED_BLINK_100TX  |
++				 AIR_PHY_LED_BLINK_1000TX |
++				 AIR_PHY_LED_BLINK_2500TX;
++		}
++	}
++
++	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++		on |= AIR_PHY_LED_ON_FDX;
++
++	if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
++		on |= AIR_PHY_LED_ON_HDX;
++
++	if (blink || on) {
++		/* switch hw-control on, so led-on and led-blink are off */
++		clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
++		clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
++	} else {
++		priv->led[index].rules = 0;
++	}
++
++	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			     AIR_PHY_LED_ON_MASK, on);
++
++	if (ret < 0)
++		return ret;
++
++	return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
++			     blink);
++};
++
++static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
++{
++	int cl45_data;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
++	if (cl45_data < 0)
++		return cl45_data;
++
++	if (state == AIR_LED_ENABLE)
++		cl45_data |= AIR_PHY_LED_ON_ENABLE;
++	else
++		cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
++
++	if (pol == AIR_ACTIVE_HIGH)
++		cl45_data |= AIR_PHY_LED_ON_POLARITY;
++	else
++		cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
++
++	err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			    cl45_data);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++
++static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int cl45_data = dur;
++	int ret, i;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
++			    cl45_data);
++	if (ret < 0)
++		return ret;
++
++	cl45_data >>= 1;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
++			    cl45_data);
++	if (ret < 0)
++		return ret;
++
++	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
++	if (cl45_data < 0)
++		return cl45_data;
++
++	switch (mode) {
++	case AIR_LED_MODE_DISABLE:
++		cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
++		cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
++		break;
++	case AIR_LED_MODE_USER_DEFINE:
++		cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
++		cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
++		break;
++	default:
++		phydev_err(phydev, "LED mode %d is not supported\n", mode);
++		return -EINVAL;
++	}
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
++	if (ret < 0)
++		return ret;
++
++	for (i = 0; i < num; ++i) {
++		ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
++		if (ret < 0) {
++			phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
++			return ret;
++		}
++		air_led_hw_control_set(phydev, i, priv->led[i].rules);
++	}
++
++	return 0;
++}
++
++static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* All combinations of the supported triggers are allowed */
++	if (rules & ~en8811h_led_trig)
++		return -EOPNOTSUPP;
++
++	return 0;
++};
++
++static int en8811h_probe(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv;
++
++	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
++			    GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
++	priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
++	priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
++
++	phydev->priv = priv;
++
++	/* MDIO_DEVS1/2 empty, so set mmds_present bits here */
++	phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
++
++	return 0;
++}
++
++static int en8811h_config_init(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	int ret, pollret, reg_value;
++	u32 pbus_value;
++
++	if (!priv->firmware_version)
++		ret = en8811h_load_firmware(phydev);
++	else
++		ret = en8811h_restart_host(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Because of mdio-lock, may have to wait for multiple loads */
++	pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++					    EN8811H_PHY_FW_STATUS, reg_value,
++					    reg_value == EN8811H_PHY_READY,
++					    20000, 7500000, true);
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
++	if (ret < 0)
++		return ret;
++
++	if (pollret || !pbus_value) {
++		phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
++		return -ENODEV;
++	}
++
++	if (!priv->firmware_version) {
++		phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
++		priv->firmware_version = pbus_value;
++	}
++
++	/* Select mode 1, the only mode supported */
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
++			    AIR_PHY_HOST_CMD_1_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
++			    AIR_PHY_HOST_CMD_2_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
++			    AIR_PHY_HOST_CMD_3_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
++			    AIR_PHY_HOST_CMD_4_MODE1);
++	if (ret < 0)
++		return ret;
++
++	/* Serdes polarity */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
++	if (ret < 0)
++		return ret;
++	if (device_property_read_bool(dev, "airoha,pnswap-rx"))
++		pbus_value |=  EN8811H_POLARITY_RX_REVERSE;
++	else
++		pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
++	if (device_property_read_bool(dev, "airoha,pnswap-tx"))
++		pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
++	else
++		pbus_value |=  EN8811H_POLARITY_TX_NORMAL;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++			    AIR_LED_MODE_USER_DEFINE);
++	if (ret < 0) {
++		phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
++		return ret;
++	}
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
++	if (ret < 0)
++		return ret;
++	pbus_value |= EN8811H_GPIO_OUTPUT_345;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int en8811h_get_features(struct phy_device *phydev)
++{
++	linkmode_set_bit_array(phy_basic_ports_array,
++			       ARRAY_SIZE(phy_basic_ports_array),
++			       phydev->supported);
++
++	return genphy_c45_pma_read_abilities(phydev);
++}
++
++static int en8811h_get_rate_matching(struct phy_device *phydev,
++				     phy_interface_t iface)
++{
++	return RATE_MATCH_PAUSE;
++}
++
++static int en8811h_config_aneg(struct phy_device *phydev)
++{
++	bool changed = false;
++	int err, val;
++
++	val = 0;
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			      phydev->advertising))
++		val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
++	err =  phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				      MDIO_AN_10GBT_CTRL_ADV2_5G, val);
++	if (err < 0)
++		return err;
++	if (err > 0)
++		changed = true;
++
++	return __genphy_config_aneg(phydev, changed);
++}
++
++static int en8811h_read_status(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u32 pbus_value;
++	int ret, val;
++
++	ret = genphy_update_link(phydev);
++	if (ret)
++		return ret;
++
++	phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
++	phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++
++	ret = genphy_read_master_slave(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_read_lpa(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Get link partner 2.5GBASE-T ability from vendor register */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
++	if (ret < 0)
++		return ret;
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			 phydev->lp_advertising,
++			 pbus_value & EN8811H_2P5G_LPA_2P5G);
++
++	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	if (!phydev->link)
++		return 0;
++
++	/* Get real speed from vendor register */
++	val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
++	if (val < 0)
++		return val;
++	switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
++	case AIR_AUX_CTRL_STATUS_SPEED_2500:
++		phydev->speed = SPEED_2500;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_1000:
++		phydev->speed = SPEED_1000;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_100:
++		phydev->speed = SPEED_100;
++		break;
++	}
++
++	/* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
++	 * Firmware before version 24011202 has no vendor register 2P5G_LPA.
++	 * Assume link partner advertised it if connected at 2500Mbps.
++	 */
++	if (priv->firmware_version < 0x24011202) {
++		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++				 phydev->lp_advertising,
++				 phydev->speed == SPEED_2500);
++	}
++
++	/* Only supports full duplex */
++	phydev->duplex = DUPLEX_FULL;
++
++	return 0;
++}
++
++static int en8811h_clear_intr(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
++			    AIR_PHY_HOST_CMD_3_DOCMD);
++	if (ret < 0)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
++			    AIR_PHY_HOST_CMD_4_INTCLR);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = en8811h_clear_intr(phydev);
++	if (ret < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static struct phy_driver en8811h_driver[] = {
++{
++	PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
++	.name			= "Airoha EN8811H",
++	.probe			= en8811h_probe,
++	.get_features		= en8811h_get_features,
++	.config_init		= en8811h_config_init,
++	.get_rate_matching	= en8811h_get_rate_matching,
++	.config_aneg		= en8811h_config_aneg,
++	.read_status		= en8811h_read_status,
++	.config_intr		= en8811h_clear_intr,
++	.handle_interrupt	= en8811h_handle_interrupt,
++	.led_hw_is_supported	= en8811h_led_hw_is_supported,
++	.read_page		= air_phy_read_page,
++	.write_page		= air_phy_write_page,
++	.led_blink_set		= air_led_blink_set,
++	.led_brightness_set	= air_led_brightness_set,
++	.led_hw_control_set	= air_led_hw_control_set,
++	.led_hw_control_get	= air_led_hw_control_get,
++} };
++
++module_phy_driver(en8811h_driver);
++
++static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
++	{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
++	{ }
++};
++MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
++MODULE_FIRMWARE(EN8811H_MD32_DM);
++MODULE_FIRMWARE(EN8811H_MD32_DSP);
++
++MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
++MODULE_AUTHOR("Airoha");
++MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/imx/Makefile b/target/linux/imx/Makefile
index 5f7f9db589..8fd6f23950 100644
--- a/target/linux/imx/Makefile
+++ b/target/linux/imx/Makefile
@@ -10,8 +10,7 @@ BOARDNAME:=NXP i.MX
 FEATURES:=audio display fpu gpio pcie rtc usb usbgadget squashfs targz nand ubifs boot-part rootfs-part
 SUBTARGETS:=cortexa7 cortexa9
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/imx/config-5.15 b/target/linux/imx/config-5.15
deleted file mode 100644
index d3291a5997..0000000000
--- a/target/linux/imx/config-5.15
+++ /dev/null
@@ -1,447 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_ERRATA_814220=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-# CONFIG_ARM_IMX6Q_CPUFREQ is not set
-# CONFIG_ARM_IMX_CPUFREQ_DT is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKSRC_IMX_GPT=y
-CONFIG_CLKSRC_MMIO=y
-# CONFIG_CLK_IMX8MM is not set
-# CONFIG_CLK_IMX8MN is not set
-# CONFIG_CLK_IMX8MP is not set
-# CONFIG_CLK_IMX8MQ is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_THERMAL=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CHACHA20=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRC32_ARM_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
-# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ENGINE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ENCRYPTED_KEYS=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FEC=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FSL_DPAA2_SWITCH is not set
-CONFIG_FSL_GUTS=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-# CONFIG_GIANFAR is not set
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MXC=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_SMP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IMX=y
-# CONFIG_I2C_IMX_LPI2C is not set
-CONFIG_I2C_SLAVE=y
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_IMX2_WDT=y
-# CONFIG_IMX7ULP_WDT is not set
-# CONFIG_IMX8MM_THERMAL is not set
-CONFIG_IMX_DMA=y
-# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
-CONFIG_IMX_INTMUX=y
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_SDMA=y
-CONFIG_IMX_THERMAL=y
-# CONFIG_IMX_WEIM is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-# CONFIG_JFFS2_FS is not set
-CONFIG_KEYS=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_OF_ESDHC=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MPILIB=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_GPMI_NAND=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MX3_IPU is not set
-CONFIG_MXC_CLK=y
-CONFIG_MXS_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_TAG_DSA=y
-CONFIG_NET_DSA_TAG_DSA_COMMON=y
-CONFIG_NET_DSA_TAG_EDSA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_IMX_IIM is not set
-CONFIG_NVMEM_IMX_OCOTP=y
-# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
-# CONFIG_NVMEM_SNVS_LPGPR is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0x80000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_IMX8MM is not set
-# CONFIG_PINCTRL_IMX8MN is not set
-# CONFIG_PINCTRL_IMX8MP is not set
-# CONFIG_PINCTRL_IMX8MQ is not set
-# CONFIG_PINCTRL_IMX8ULP is not set
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_OPP=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-# CONFIG_PWM_IMX1 is not set
-CONFIG_PWM_IMX27=y
-# CONFIG_PWM_IMX_TPM is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ANATOP=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_PFUZE100=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_IMX50 is not set
-# CONFIG_SOC_IMX51 is not set
-# CONFIG_SOC_IMX53 is not set
-# CONFIG_SOC_IMX6Q is not set
-# CONFIG_SOC_IMX6SL is not set
-# CONFIG_SOC_IMX6SLL is not set
-# CONFIG_SOC_IMX6SX is not set
-# CONFIG_SOC_IMX6UL is not set
-# CONFIG_SOC_IMX7D is not set
-# CONFIG_SOC_IMX7ULP is not set
-# CONFIG_SOC_IMX8M is not set
-# CONFIG_SOC_LS1021A is not set
-# CONFIG_SOC_VF610 is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_FSL_LPSPI is not set
-# CONFIG_SPI_FSL_QUADSPI is not set
-CONFIG_SPI_IMX=y
-CONFIG_SPI_MASTER=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_STMP_DEVICE=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_IMX=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_3G is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XOR_BLOCKS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/imx/cortexa9/base-files/etc/board.d/02_network b/target/linux/imx/cortexa9/base-files/etc/board.d/02_network
index 1ef2fcdc65..3aad761a15 100644
--- a/target/linux/imx/cortexa9/base-files/etc/board.d/02_network
+++ b/target/linux/imx/cortexa9/base-files/etc/board.d/02_network
@@ -34,7 +34,7 @@ gw,imx6q-gw53xx|\
 gw,imx6q-gw5400-a|\
 gw,imx6q-gw54xx|\
 gw,imx6q-gw552x)
-	ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
+	ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
 	;;
 wand,imx6dl-wandboard)
 	ucidef_set_interface_wan 'eth0'
diff --git a/target/linux/imx/image/cortexa9.mk b/target/linux/imx/image/cortexa9.mk
index 2edbbaac47..2321469cc8 100644
--- a/target/linux/imx/image/cortexa9.mk
+++ b/target/linux/imx/image/cortexa9.mk
@@ -120,7 +120,8 @@ define Device/gateworks_ventana
 	imx6q-gw5913
   DEVICE_PACKAGES := kmod-sky2 kmod-sound-core kmod-sound-soc-imx \
 	kmod-sound-soc-imx-sgtl5000 kmod-can kmod-can-flexcan kmod-can-raw \
-	kmod-hwmon-gsc kmod-leds-gpio kmod-pps-gpio kobs-ng
+	kmod-hwmon-gsc kmod-leds-gpio kmod-pps-gpio kobs-ng \
+	kmod-gpio-button-hotplug
   KERNEL += | boot-overlay
   IMAGES := img.gz nand.ubi bootfs.tar.gz dtb
   IMAGE/nand.ubi := append-ubi
diff --git a/target/linux/imx/patches-5.15/100-bootargs.patch b/target/linux/imx/patches-5.15/100-bootargs.patch
deleted file mode 100644
index cf63a3bdb1..0000000000
--- a/target/linux/imx/patches-5.15/100-bootargs.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/imx6dl-wandboard.dts
-+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
-@@ -16,4 +16,8 @@
- 		device_type = "memory";
- 		reg = <0x10000000 0x40000000>;
- 	};
-+
-+	chosen {
-+		bootargs = "console=ttymxc0,115200";
-+	};
- };
diff --git a/target/linux/imx/patches-5.15/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch b/target/linux/imx/patches-5.15/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
deleted file mode 100644
index e14dc484b0..0000000000
--- a/target/linux/imx/patches-5.15/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
+++ /dev/null
@@ -1,96 +0,0 @@
-From 68604e89335ccb3e893b5a05b2c0d5cd2eaaf6ec Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
-Date: Tue, 3 Mar 2020 15:14:40 +0100
-Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: add status LEDs aliases
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 16 ++++++++++------
- arch/arm/boot/dts/imx6q-apalis-ixora.dts      | 12 ++++++++----
- 2 files changed, 18 insertions(+), 10 deletions(-)
-
---- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-@@ -25,6 +25,10 @@
- 		i2c2 = &i2c2;
- 		rtc0 = &rtc_i2c;
- 		rtc1 = &snvs_rtc;
-+		led-boot = &led_boot;
-+		led-failsafe = &led_failsafe;
-+		led-running = &led_running;
-+		led-upgrade = &led_upgrade;
- 	};
- 
- 	chosen {
-@@ -92,22 +96,22 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pinctrl_leds_ixora>;
- 
--		led4-green {
-+		led_running: led4-green {
- 			label = "LED_4_GREEN";
--			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
-+			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- 		};
- 
--		led4-red {
-+		led_upgrade: led4-red {
- 			label = "LED_4_RED";
--			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
- 		};
- 
--		led5-green {
-+		led_boot: led5-green {
- 			label = "LED_5_GREEN";
- 			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- 		};
- 
--		led5-red {
-+		led_failsafe: led5-red {
- 			label = "LED_5_RED";
- 			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- 		};
---- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
-@@ -24,6 +24,10 @@
- 		i2c2 = &i2c2;
- 		rtc0 = &rtc_i2c;
- 		rtc1 = &snvs_rtc;
-+		led-boot = &led_boot;
-+		led-failsafe = &led_failsafe;
-+		led-running = &led_running;
-+		led-upgrade = &led_upgrade;
- 	};
- 
- 	chosen {
-@@ -91,22 +95,22 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pinctrl_leds_ixora>;
- 
--		led4-green {
-+		led_running: led4-green {
- 			label = "LED_4_GREEN";
- 			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- 		};
- 
--		led4-red {
-+		led_upgrade: led4-red {
- 			label = "LED_4_RED";
- 			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
- 		};
- 
--		led5-green {
-+		led_boot: led5-green {
- 			label = "LED_5_GREEN";
- 			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- 		};
- 
--		led5-red {
-+		led_failsafe: led5-red {
- 			label = "LED_5_RED";
- 			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- 		};
diff --git a/target/linux/imx/patches-5.15/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch b/target/linux/imx/patches-5.15/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
deleted file mode 100644
index 8f07f0b1a5..0000000000
--- a/target/linux/imx/patches-5.15/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
-Date: Tue, 3 Mar 2020 15:15:57 +0100
-Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++-
- arch/arm/boot/dts/imx6q-apalis-ixora.dts      | 15 ++++++++++++++-
- 2 files changed, 28 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
-@@ -38,7 +38,7 @@
- 	gpio-keys {
- 		compatible = "gpio-keys";
- 		pinctrl-names = "default";
--		pinctrl-0 = <&pinctrl_gpio_keys>;
-+		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
- 
- 		wakeup {
- 			label = "Wake-Up";
-@@ -47,6 +47,13 @@
- 			debounce-interval = <10>;
- 			wakeup-source;
- 		};
-+
-+		reset {
-+			label = "reset";
-+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_RESTART>;
-+			debounce-interval = <10>;
-+		};
- 	};
- 
- 	lcd_display: disp0 {
-@@ -275,4 +282,10 @@
- 			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- 		>;
- 	};
-+
-+	pinctrl_switch3_ixora: switch3ixora {
-+		fsl,pins = <
-+			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
-+		>;
-+	};
- };
---- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
-+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
-@@ -37,7 +37,7 @@
- 	gpio-keys {
- 		compatible = "gpio-keys";
- 		pinctrl-names = "default";
--		pinctrl-0 = <&pinctrl_gpio_keys>;
-+		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
- 
- 		wakeup {
- 			label = "Wake-Up";
-@@ -46,6 +46,13 @@
- 			debounce-interval = <10>;
- 			wakeup-source;
- 		};
-+
-+		reset {
-+			label = "reset";
-+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_RESTART>;
-+			debounce-interval = <10>;
-+		};
- 	};
- 
- 	lcd_display: disp0 {
-@@ -276,4 +283,10 @@
- 			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- 		>;
- 	};
-+
-+	pinctrl_switch3_ixora: switch3ixora {
-+		fsl,pins = <
-+			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
-+		>;
-+	};
- };
diff --git a/target/linux/imx/patches-5.15/310-ARM-dts-imx7d-pico-pi-set-aliases.patch b/target/linux/imx/patches-5.15/310-ARM-dts-imx7d-pico-pi-set-aliases.patch
deleted file mode 100644
index f50199cdfc..0000000000
--- a/target/linux/imx/patches-5.15/310-ARM-dts-imx7d-pico-pi-set-aliases.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/arch/arm/boot/dts/imx7d-pico-pi.dts
-+++ b/arch/arm/boot/dts/imx7d-pico-pi.dts
-@@ -8,12 +8,20 @@
- 	model = "TechNexion PICO-IMX7D Board and PI baseboard";
- 	compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
- 
-+	aliases {
-+		led-boot = &led_system;
-+		led-failsafe = &led_system;
-+		led-running = &led_system;
-+		led-upgrade = &led_system;
-+		label-mac-device = &fec1;
-+	};
-+
- 	leds {
- 		compatible = "gpio-leds";
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pinctrl_gpio_leds>;
- 
--		led {
-+		led_system: led {
- 			label = "gpio-led";
- 			gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
- 		};
diff --git a/target/linux/imx/patches-5.15/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch b/target/linux/imx/patches-5.15/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch
deleted file mode 100644
index 5248e8c74c..0000000000
--- a/target/linux/imx/patches-5.15/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 6e8e5ccfbee7a531b035ffce3f95f3901946fa9d Mon Sep 17 00:00:00 2001
-From: Robert Nelson <robertcnelson@gmail.com>
-Date: Wed, 9 Jan 2019 14:33:24 -0600
-Subject: [PATCH] ARM: imx7d-pico-pi.dts: add default stdout-path
-
-Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
----
- arch/arm/boot/dts/imx7d-pico-pi.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm/boot/dts/imx7d-pico-pi.dts
-+++ b/arch/arm/boot/dts/imx7d-pico-pi.dts
-@@ -16,6 +16,10 @@
- 		label-mac-device = &fec1;
- 	};
- 
-+	chosen {
-+		stdout-path = "serial4:115200n8";
-+	};
-+
- 	leds {
- 		compatible = "gpio-leds";
- 		pinctrl-names = "default";
diff --git a/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch b/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
index a3d8bf0488..4b1a43259f 100644
--- a/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
+++ b/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
@@ -32,7 +32,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17066,6 +17066,13 @@ L:	netdev@vger.kernel.org
+@@ -17068,6 +17068,13 @@ L:	netdev@vger.kernel.org
  S:	Maintained
  F:	drivers/net/ethernet/qualcomm/emac/
  
diff --git a/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch b/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
index 7961c9978b..ba50d64a76 100644
--- a/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
+++ b/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
@@ -64,7 +64,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
  
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17072,6 +17072,7 @@ L:	netdev@vger.kernel.org
+@@ -17074,6 +17074,7 @@ L:	netdev@vger.kernel.org
  S:	Maintained
  F:	Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
  F:	drivers/net/ethernet/qualcomm/ipqess/
diff --git a/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch b/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch
index 515bb21707..5029b1791c 100644
--- a/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch
+++ b/target/linux/kirkwood/patches-6.1/202-linksys-find-active-root.patch
@@ -22,7 +22,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  	const char *partname;
  	struct device_node *pp;
  	int nr_parts, i, ret = 0;
-@@ -133,9 +136,15 @@ static int parse_fixed_partitions(struct
+@@ -152,9 +155,15 @@ static int parse_fixed_partitions(struct
  		parts[i].size = of_read_number(reg + a_cells, s_cells);
  		parts[i].of_node = pp;
  
@@ -41,7 +41,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  		parts[i].name = partname;
  
  		if (of_get_property(pp, "read-only", &len))
-@@ -252,6 +261,18 @@ static int __init ofpart_parser_init(voi
+@@ -271,6 +280,18 @@ static int __init ofpart_parser_init(voi
  	return 0;
  }
  
diff --git a/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
index 6af915da90..8beee8f2dc 100644
--- a/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
+++ b/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
@@ -25,7 +25,7 @@ Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
  	case PHY_INTERFACE_MODE_QUSGMII:
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -200,6 +200,7 @@ static int phylink_interface_max_speed(p
+@@ -218,6 +218,7 @@ static int phylink_interface_max_speed(p
  		return SPEED_1000;
  
  	case PHY_INTERFACE_MODE_2500BASEX:
diff --git a/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch b/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
index 265756ea70..1a1d7a0ac7 100644
--- a/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
+++ b/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
@@ -32,7 +32,7 @@ Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
 
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -487,6 +487,7 @@ unsigned long phylink_get_capabilities(p
+@@ -505,6 +505,7 @@ unsigned long phylink_get_capabilities(p
  		break;
  
  	case PHY_INTERFACE_MODE_2500BASEX:
diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile
index f73f2daef6..279c167b83 100644
--- a/target/linux/mediatek/Makefile
+++ b/target/linux/mediatek/Makefile
@@ -8,8 +8,7 @@ BOARDNAME:=MediaTek Ralink ARM
 SUBTARGETS:=mt7622 mt7623 mt7629 filogic
 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \
diff --git a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
index 5dec158a93..f58f709e1c 100644
--- a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
+++ b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
@@ -9,7 +9,8 @@ unielec,u7623-02)
 	[ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] &&
 		fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
 	;;
-bananapi,bpi-r3)
+bananapi,bpi-r3|\
+bananapi,bpi-r3-mini)
 	[ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] &&
 		fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
 	[ -z "$(fw_printenv -n eth1addr 2>/dev/null)" ] &&
diff --git a/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts b/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts
index e78db1de6c..e2b7268e85 100644
--- a/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts
+++ b/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts
@@ -10,6 +10,11 @@
 	aliases {
 		label-mac-device = &wan;
 	};
+
+	chosen {
+		rootdisk = <&ubi_rootfs>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 ubi.block=0,fit root=/dev/fit0";
+	};
 };
 
 &snand {
@@ -25,45 +30,70 @@
 		};
 
 		partition@80000 {
-			label = "fip";
-			reg = <0x80000 0x140000>;
-			read-only;
-		};
+			label = "ubi";
+			reg = <0x80000 0x7f80000>;
+			compatible = "linux,ubi";
 
-		factory: partition@1c0000 {
-			label = "factory";
-			reg = <0x1c0000 0x100000>;
-			read-only;
-
-			nvmem-layout {
-				compatible = "fixed-layout";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				macaddr_factory_7fff4: macaddr@7fff4 {
-					reg = <0x7fff4 0x6>;
+			volumes {
+				ubi-volume-ubootenv {
+					volname = "ubootenv";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
 				};
 
-				macaddr_factory_7fffa: macaddr@7fffa {
-					reg = <0x7fffa 0x6>;
+				ubi-volume-ubootenv2 {
+					volname = "ubootenv2";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
+
+				ubi_rootfs: ubi-volume-fit {
+					volname = "fit";
+				};
+
+				ubi_factory: ubi-volume-factory {
+					volname = "factory";
 				};
 			};
 		};
+	};
+};
 
-		partition@300000 {
-			label = "ubi";
-			reg = <0x300000 0x7d00000>;
+&ubi_factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eeprom_factory_0: eeprom@0 {
+			reg = <0x0 0x4da8>; /* actual length 0x400 */
+		};
+
+		eeprom_factory_5000: eeprom@5000 {
+			reg = <0x5000 0xe00>;
+		};
+
+		macaddr_factory_7fff4: macaddr@7fff4 {
+			reg = <0x7fff4 0x6>;
+		};
+
+		macaddr_factory_7fffa: macaddr@7fffa {
+			reg = <0x7fffa 0x6>;
 		};
 	};
 };
 
 &wmac {
-	mediatek,mtd-eeprom = <&factory 0x0>;
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	status = "okay";
 };
 
 &wmac1 {
-	mediatek,mtd-eeprom = <&factory 0x5000>;
+	nvmem-cells = <&eeprom_factory_5000>;
+	nvmem-cell-names = "eeprom";
 };
 
 &gmac0 {
diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts
index 7a7a8a8159..5f62ed1a45 100644
--- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts
+++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts
@@ -5,6 +5,11 @@
 / {
 	model = "Ubiquiti UniFi 6 LR v1 (U-Boot mod)";
 	compatible = "ubnt,unifi-6-lr-v1-ubootmod", "mediatek,mt7622";
+
+	chosen {
+		rootdisk = <&rootdisk>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0";
+	};
 };
 
 &nor_partitions {
@@ -54,7 +59,7 @@
 		reg = <0x120000 0xee0000>;
 	};
 
-	partition@1000000 {
+	rootdisk: partition@1000000 {
 		compatible = "denx,fit";
 		label = "firmware";
 		reg = <0x1000000 0x3000000>;
diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts
index 3a37d1d500..96effb8aab 100644
--- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts
+++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts
@@ -5,6 +5,11 @@
 / {
 	model = "Ubiquiti UniFi 6 LR v2 (U-Boot mod)";
 	compatible = "ubnt,unifi-6-lr-v2-ubootmod", "mediatek,mt7622";
+
+	chosen {
+		rootdisk = <&rootdisk>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0";
+	};
 };
 
 &nor_partitions {
@@ -54,7 +59,7 @@
 		reg = <0x120000 0xee0000>;
 	};
 
-	partition@1000000 {
+	rootdisk: partition@1000000 {
 		compatible = "denx,fit";
 		label = "firmware";
 		reg = <0x1000000 0x3000000>;
diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts
index e91aaa63f5..ec98dd262c 100644
--- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts
+++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts
@@ -5,6 +5,11 @@
 / {
 	model = "Ubiquiti UniFi 6 LR v3 (U-Boot mod)";
 	compatible = "ubnt,unifi-6-lr-v3-ubootmod", "mediatek,mt7622";
+
+	chosen {
+		rootdisk = <&rootdisk>;
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0";
+	};
 };
 
 &nor_partitions {
@@ -54,7 +59,7 @@
 		reg = <0x120000 0xee0000>;
 	};
 
-	partition@1000000 {
+	rootdisk: partition@1000000 {
 		compatible = "denx,fit";
 		label = "firmware";
 		reg = <0x1000000 0x3000000>;
diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts
index 068dd0f236..9b7c85e519 100644
--- a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts
+++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts
@@ -103,6 +103,8 @@
 
 	gmac0: mac@0 {
 		compatible = "mediatek,eth-mac";
+		nvmem-cells = <&macaddr_boot1_a 0>;
+		nvmem-cell-names = "mac-address";
 		reg = <0>;
 
 		phy-mode = "2500base-x";
@@ -111,6 +113,8 @@
 
 	gmac1: mac@1 {
 		compatible = "mediatek,eth-mac";
+		nvmem-cells = <&macaddr_boot1_a 1>;
+		nvmem-cell-names = "mac-address";
 		reg = <1>;
 		phy-mode = "gmii";
 		phy-handle = <&int_gbe_phy>;
@@ -148,4 +152,54 @@
 	vmmc-supply = <&reg_3p3v>;
 	cap-mmc-highspeed;
 	non-removable;
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+
+			partitions {
+				block-partition-u-boot-env {
+					partname = "u-boot-env";
+					nvmem-layout {
+						compatible = "u-boot,env-layout";
+					};
+				};
+			};
+		};
+
+		boot1 {
+			compatible = "block-device";
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_boot1_a: macaddr@a {
+					compatible = "mac-base";
+					reg = <0xa 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+
+				ddns@10 {
+					reg = <0x10 0x10>;
+				};
+
+				sn-bak@20 {
+					reg = <0x20 0x10>;
+				};
+
+				sn@30 {
+					reg = <0x30 0x10>;
+				};
+
+				country-code@88 {
+					reg = <0x88 0x10>;
+				};
+			};
+		};
+	};
 };
diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts
index 7c1770d6f4..09a557c0cb 100644
--- a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts
+++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts
@@ -28,9 +28,11 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
+		rootdisk-emmc = <&emmc_rootdisk>;
+		rootdisk-spim-nand = <&nand_rootdisk>;
 	};
 
-	memory@40000000 {
+	memory {
 		reg = <0 0x40000000 0 0x80000000>;
 	};
 
@@ -54,12 +56,16 @@
 		};
 
 		led-1 {
-			label = "blue:wlan2g";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <1>;
 			gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
 		};
 
 		led-2 {
-			label = "blue:wlan5g";
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <2>;
 			gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -67,7 +73,7 @@
 	fan: pwm-fan {
 		compatible = "pwm-fan";
 		#cooling-cells = <2>;
-		cooling-levels = <0 128 255>;
+		cooling-levels = <255 128 80 0>;
 		pwms = <&pwm 0 10000 0>;
 		status = "okay";
 	};
@@ -109,20 +115,24 @@
 	};
 };
 
+&auxadc {
+	status = "okay";
+};
+
 &cpu_thermal {
 	cooling-maps {
 		cpu-active-low {
-			cooling-device = <&fan 0 0>;
+			cooling-device = <&fan 1 1>;
 			trip = <&cpu_trip_active_low>;
 		};
 
 		cpu-active-med {
-			cooling-device = <&fan 1 1>;
+			cooling-device = <&fan 2 2>;
 			trip = <&cpu_trip_active_med>;
 		};
 
 		cpu-active-high {
-			cooling-device = <&fan 2 2>;
+			cooling-device = <&fan 3 3>;
 			trip = <&cpu_trip_active_high>;
 		};
 	};
@@ -140,67 +150,91 @@
 	gmac0: mac@0 {
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
+		phy-handle = <&phy14>;
 		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
 	};
 
 	gmac1: mac@1 {
 		compatible = "mediatek,eth-mac";
 		reg = <1>;
+		phy-handle = <&phy15>;
 		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
 	};
 
 	mdio: mdio-bus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		phy14: phy@14 {
+		phy14: phy@e {
 			compatible = "ethernet-phy-id03a2.a411";
 			reg = <14>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&en8811_pwr_a>;
 
-			airoha,polarity = <3>;
+			airoha,pnswap-rx;
 
 			interrupt-parent = <&pio>;
-			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
-			reset-gpios = <&pio 49 1>;
+			interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
 			reset-deassert-us = <20000>;
 
 			phy-mode = "2500base-x";
 			full-duplex;
 			pause;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					function = LED_FUNCTION_LAN;
+					color = <LED_COLOR_ID_YELLOW>;
+				};
+
+				led@1 {
+					reg = <1>;
+					function = LED_FUNCTION_LAN;
+					color = <LED_COLOR_ID_GREEN>;
+				};
+			};
 		};
 
-		phy15: phy@15 {
+		phy15: phy@f {
 			compatible = "ethernet-phy-id03a2.a411";
 			reg = <15>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&en8811_pwr_b>;
 
-			airoha,polarity = <3>;
+			airoha,pnswap-rx;
 
 			interrupt-parent = <&pio>;
-			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-			reset-gpios = <&pio 47 1>;
+			interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
 			reset-deassert-us = <20000>;
 
 			phy-mode = "2500base-x";
 			full-duplex;
 			pause;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					function = LED_FUNCTION_WAN;
+					color = <LED_COLOR_ID_YELLOW>;
+				};
+
+				led@1 {
+					reg = <1>;
+					function = LED_FUNCTION_WAN;
+					color = <LED_COLOR_ID_GREEN>;
+				};
+			};
 		};
 	};
 };
@@ -234,6 +268,20 @@
 	no-sd;
 	no-sdio;
 	status = "okay";
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+			partitions {
+				emmc_rootdisk: block-partition-production {
+					partname = "production";
+				};
+			};
+		};
+	};
 };
 
 &pcie {
@@ -474,29 +522,20 @@
 
 			partition@0 {
 				label = "bl2";
-				reg = <0x00000 0x100000>;
+				reg = <0x0 0x200000>;
 				read-only;
 			};
 
-			partition@100000 {
-				label = "u-boot-env";
-				reg = <0x100000 0x80000>;
-			};
-
-			partition@180000 {
-				label = "factory";
-				reg = <0x180000 0x200000>;
-			};
-
-			partition@380000 {
-				label = "fip";
-				reg = <0x380000 0x200000>;
-				read-only;
-			};
-
-			partition@580000 {
+			partition@200000 {
 				label = "ubi";
-				reg = <0x580000 0x7a80000>;
+				reg = <0x200000 0x7e00000>;
+				compatible = "linux,ubi";
+
+				volumes {
+					nand_rootdisk: ubi-volume-fit {
+						volname = "fit";
+					};
+				};
 			};
 		};
 	};
diff --git a/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts
index 26996e7b4a..fd0e1a6915 100644
--- a/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts
+++ b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts
@@ -13,6 +13,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		label-mac-device = &gmac1;
 		led-boot = &led_blue;
 		led-failsafe = &led_blue;
 		led-running = &led_white;
@@ -84,6 +85,8 @@
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
 		phy-mode = "2500base-x";
+		nvmem-cells = <&macaddr_factory_a 2>;
+		nvmem-cell-names = "mac-address";
 
 		fixed-link {
 			speed = <2500>;
@@ -95,6 +98,8 @@
 	gmac1: mac@1 {
 		compatible = "mediatek,eth-mac";
 		reg = <1>;
+		nvmem-cells = <&macaddr_factory_a 0>;
+		nvmem-cell-names = "mac-address";
 		phy-mode = "2500base-x";
 		phy-handle = <&phy1>;
 	};
@@ -285,6 +290,8 @@
 };
 
 &wifi {
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wf_2g_5g_pins>;
 	status = "okay";
@@ -306,4 +313,42 @@
 	no-sd;
 	no-sdio;
 	status = "okay";
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+			partitions {
+				block-partition-env {
+					partname = "u-boot-env";
+
+					nvmem-layout {
+						compatible = "u-boot,env-layout";
+					};
+				};
+
+				block-partition-factory {
+					partname = "factory";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						eeprom_factory_0: eeprom@0 {
+							reg = <0x0 0x1000>;
+						};
+
+						macaddr_factory_a: macaddr@a {
+							compatible = "mac-base";
+							reg = <0xa 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+			};
+		};
+	};
 };
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso
deleted file mode 100644
index 4d0e5c0406..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso
deleted file mode 100644
index 710e6c0bcf..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&sw_p5>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso
deleted file mode 100644
index 5b51dfd671..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			spi_nand: spi_nand@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spi-nand";
-				reg = <1>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					factory: partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0200000>;
-					};
-
-					partition@380000 {
-						label = "FIP";
-						reg = <0x380000 0x0200000>;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x4000000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&wifi>;
-		__overlay__ {
-			mediatek,mtd-eeprom = <&factory 0x0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts
deleted file mode 100644
index b2bb692956..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7981.dtsi"
-
-/ {
-	model = "MediaTek MT7981 RFB";
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x20000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
-		};
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "gmii";
-		phy-handle = <&int_gbe_phy>;
-	};
-};
-
-&mdio_bus {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	spi0_flash_pins: spi0-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
-		};
-		conf-pd {
-			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
-		};
-	};
-
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		sw_p5: port@5 {
-			reg = <5>;
-			label = "lan5";
-			status = "disabled";
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&xhci {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi
deleted file mode 100644
index cb161df81e..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ /dev/null
@@ -1,820 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mux/mux.h>
-
-/ {
-	compatible = "mediatek,mt7981";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x0>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x1>;
-		};
-	};
-
-	pwm: pwm@10048000 {
-		compatible = "mediatek,mt7981-pwm";
-		reg = <0 0x10048000 0 0x1000>;
-		#pwm-cells = <2>;
-		clocks = <&infracfg CLK_INFRA_PWM_STA>,
-			 <&infracfg CLK_INFRA_PWM_HCK>,
-			 <&infracfg CLK_INFRA_PWM1_CK>,
-			 <&infracfg CLK_INFRA_PWM2_CK>,
-			 <&infracfg CLK_INFRA_PWM3_CK>;
-		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
-		cooling-levels = <0 63 95 127 159 191 223 255>;
-		#cooling-cells = <2>;
-		status = "disabled";
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-			trips {
-				cpu_trip_active_highest: active-highest {
-					temperature = <70000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <50000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <45000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_lowest: active-lowest {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-highest {
-					/* active: set fan to cooling level 7 */
-					cooling-device = <&fan 7 7>;
-					trip = <&cpu_trip_active_highest>;
-				};
-
-				cpu-active-high {
-					/* active: set fan to cooling level 5 */
-					cooling-device = <&fan 5 5>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-med {
-					/* active: set fan to cooling level 3 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-active-low {
-					/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_low>;
-				};
-
-				cpu-active-lowest {
-					/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_lowest>;
-				};
-			};
-		};
-	};
-
-	thermal: thermal@1100c800 {
-		#thermal-sensor-cells = <1>;
-		compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
-		reg = <0 0x1100c800 0 0x800>;
-		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_THERM_CK>,
-			 <&infracfg CLK_INFRA_ADC_26M_CK>;
-		clock-names = "therm", "auxadc";
-		mediatek,auxadc = <&auxadc>;
-		mediatek,apmixedsys = <&apmixedsys>;
-		nvmem-cells = <&thermal_calibration>;
-		nvmem-cell-names = "calibration-data";
-	};
-
-	auxadc: adc@1100d000 {
-		compatible = "mediatek,mt7981-auxadc",
-			     "mediatek,mt7986-auxadc",
-			     "mediatek,mt7622-auxadc";
-		reg = <0 0x1100d000 0 0x1000>;
-		clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
-			 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-		clock-names = "main", "32k";
-		#io-channel-cells = <1>;
-	};
-
-	wdma: wdma@15104800 {
-		compatible = "mediatek,wed-wdma";
-		reg = <0 0x15104800 0 0x400>,
-		      <0 0x15104c00 0 0x400>;
-	};
-
-	ap2woccif: ap2woccif@151a5000 {
-		compatible = "mediatek,ap2woccif";
-		reg = <0 0x151a5000 0 0x1000>,
-		      <0 0x151ad000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		/* 64 KiB reserved for ramoops/pstore */
-		ramoops@42ff0000 {
-			compatible = "ramoops";
-			reg = <0 0x42ff0000 0 0x10000>;
-			record-size = <0x1000>;
-		};
-
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@47c80000 {
-			reg = <0 0x47c80000 0 0x100000>;
-			no-map;
-		};
-
-		wo_emi0: wo-emi@47d80000 {
-			reg = <0 0x47d80000 0 0x40000>;
-			no-map;
-		};
-
-		wo_data: wo-data@47dc0000 {
-			reg = <0 0x47dc0000 0 0x240000>;
-			no-map;
-		};
-	};
-
-	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
-	};
-
-	trng {
-		compatible = "mediatek,mt7981-rng";
-	};
-
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <40000000>;
-		clock-output-names = "clkxtal";
-	};
-
-	infracfg: infracfg@10001000 {
-		compatible = "mediatek,mt7981-infracfg", "syscon";
-		reg = <0 0x10001000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	topckgen: topckgen@1001B000 {
-		compatible = "mediatek,mt7981-topckgen", "syscon";
-		reg = <0 0x1001B000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	apmixedsys: apmixedsys@1001E000 {
-		compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
-		reg = <0 0x1001E000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		clock-frequency = <13000000>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
-	};
-
-	watchdog: watchdog@1001c000 {
-		compatible = "mediatek,mt7986-wdt",
-			     "mediatek,mt6589-wdt";
-		reg = <0 0x1001c000 0 0x1000>;
-		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-		#reset-cells = <1>;
-		status = "disabled";
-	};
-
-	gic: interrupt-controller@c000000 {
-		compatible = "arm,gic-v3";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-		      <0 0x0c080000 0 0x200000>; /* GICR */
-
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-			<&infracfg CLK_INFRA_UART0_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART0_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		pinctrl-0 = <&uart0_pins>;
-		pinctrl-names = "default";
-		status = "disabled";
-	};
-
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-			<&infracfg CLK_INFRA_UART1_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART1_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
-
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-			<&infracfg CLK_INFRA_UART2_CK>;
-		clock-names = "baud", "bus";
-		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-				  <&infracfg CLK_INFRA_UART2_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-					 <&topckgen CLK_TOP_UART_SEL>;
-		status = "disabled";
-	};
-
-	i2c0: i2c@11007000 {
-		compatible = "mediatek,mt7981-i2c";
-		reg = <0 0x11007000 0 0x1000>,
-		      <0 0x10217080 0 0x80>;
-		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-		clock-div = <1>;
-		clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-			 <&infracfg CLK_INFRA_AP_DMA_CK>,
-			 <&infracfg CLK_INFRA_I2C_MCK_CK>,
-			 <&infracfg CLK_INFRA_I2C_PCK_CK>;
-		clock-names = "main", "dma", "arb", "pmic";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	pcie: pcie@11280000 {
-		compatible = "mediatek,mt7981-pcie",
-			     "mediatek,mt7986-pcie";
-		device_type = "pci";
-		reg = <0 0x11280000 0 0x4000>;
-		reg-names = "pcie-mac";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-		bus-range = <0x00 0xff>;
-		ranges = <0x82000000 0 0x20000000
-			  0x0 0x20000000 0 0x10000000>;
-		status = "disabled";
-
-		clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
-			 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-			 <&infracfg CLK_INFRA_IPCIER_CK>,
-			 <&infracfg CLK_INFRA_IPCIEB_CK>;
-
-		phys = <&u3port0 PHY_TYPE_PCIE>;
-		phy-names = "pcie-phy";
-
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_intc 0>,
-				<0 0 0 2 &pcie_intc 1>,
-				<0 0 0 3 &pcie_intc 2>,
-				<0 0 0 4 &pcie_intc 3>;
-		pcie_intc: interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-		};
-	};
-
-	crypto: crypto@10320000 {
-		compatible = "inside-secure,safexcel-eip97";
-		reg = <0 0x10320000 0 0x40000>;
-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "ring0", "ring1", "ring2", "ring3";
-		clocks = <&topckgen CLK_TOP_EIP97B>;
-		clock-names = "top_eip97_ck";
-		assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
-	};
-
-	pio: pinctrl@11d00000 {
-		compatible = "mediatek,mt7981-pinctrl";
-		reg = <0 0x11d00000 0 0x1000>,
-		      <0 0x11c00000 0 0x1000>,
-		      <0 0x11c10000 0 0x1000>,
-		      <0 0x11d20000 0 0x1000>,
-		      <0 0x11e00000 0 0x1000>,
-		      <0 0x11e20000 0 0x1000>,
-		      <0 0x11f00000 0 0x1000>,
-		      <0 0x11f10000 0 0x1000>,
-		      <0 0x1000b000 0 0x1000>;
-		reg-names = "gpio", "iocfg_rt", "iocfg_rm",
-			    "iocfg_rb", "iocfg_lb", "iocfg_bl",
-			    "iocfg_tm", "iocfg_tl", "eint";
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-ranges = <&pio 0 0 56>;
-		interrupt-controller;
-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		#interrupt-cells = <2>;
-
-		mdio_pins: mdc-mdio-pins {
-			mux {
-				function = "eth";
-				groups = "smi_mdc_mdio";
-			};
-		};
-
-		uart0_pins: uart0-pins {
-			mux {
-				function = "uart";
-				groups = "uart0";
-			};
-		};
-
-		wifi_dbdc_pins: wifi-dbdc-pins {
-			mux {
-				function = "eth";
-				groups = "wf0_mode1";
-			};
-			conf {
-				pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
-				       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
-				       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
-				       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
-				       "WF_CBA_RESETB", "WF_DIG_RESETB";
-				drive-strength = <4>;
-			};
-		};
-
-		gbe_led0_pins: gbe-led0-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led0";
-			};
-		};
-
-		gbe_led1_pins: gbe-led1-pins {
-			mux {
-				function = "led";
-				groups = "gbe_led1";
-			};
-		};
-	};
-
-	ethsys: syscon@15000000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "mediatek,mt7981-ethsys",
-			     "mediatek,mt7986-ethsys",
-			     "syscon";
-		reg = <0 0x15000000 0 0x1000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	wed: wed@15010000 {
-		compatible = "mediatek,mt7981-wed",
-			     "mediatek,mt7986-wed",
-			     "syscon";
-		reg = <0 0x15010000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wo_emi0>, <&wo_data>;
-		memory-region-names = "wo-emi", "wo-data";
-		mediatek,wo-ccif = <&wo_ccif0>;
-		mediatek,wo-ilm = <&wo_ilm0>;
-		mediatek,wo-dlm = <&wo_dlm0>;
-		mediatek,wo-cpuboot = <&wo_cpuboot>;
-	};
-
-	eth: ethernet@15100000 {
-		compatible = "mediatek,mt7981-eth";
-		reg = <0 0x15100000 0 0x80000>;
-		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&ethsys CLK_ETH_FE_EN>,
-			<&ethsys CLK_ETH_GP2_EN>,
-			<&ethsys CLK_ETH_GP1_EN>,
-			<&ethsys CLK_ETH_WOCPU0_EN>,
-			<&sgmiisys0 CLK_SGM0_TX_EN>,
-			<&sgmiisys0 CLK_SGM0_RX_EN>,
-			<&sgmiisys0 CLK_SGM0_CK0_EN>,
-			<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
-			<&sgmiisys1 CLK_SGM1_TX_EN>,
-			<&sgmiisys1 CLK_SGM1_RX_EN>,
-			<&sgmiisys1 CLK_SGM1_CK1_EN>,
-			<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
-			<&topckgen CLK_TOP_SGM_REG>,
-			<&topckgen CLK_TOP_NETSYS_SEL>,
-			<&topckgen CLK_TOP_NETSYS_500M_SEL>;
-		clock-names = "fe", "gp2", "gp1", "wocpu0",
-					"sgmii_tx250m", "sgmii_rx250m",
-					"sgmii_cdr_ref", "sgmii_cdr_fb",
-					"sgmii2_tx250m", "sgmii2_rx250m",
-					"sgmii2_cdr_ref", "sgmii2_cdr_fb",
-					"sgmii_ck", "netsys0", "netsys1";
-		assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-				  <&topckgen CLK_TOP_SGM_325M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
-					 <&topckgen CLK_TOP_CB_SGM_325M>;
-		mediatek,ethsys = <&ethsys>;
-		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-		mediatek,infracfg = <&topmisc>;
-		mediatek,wed = <&wed>;
-		#reset-cells = <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-
-		mdio_bus: mdio-bus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			int_gbe_phy: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c22";
-				phy-mode = "gmii";
-				phy-is-integrated;
-				nvmem-cells = <&phy_calibration>;
-				nvmem-cell-names = "phy-cal-data";
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					int_gbe_phy_led0: int-gbe-phy-led0@0 {
-						reg = <0>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
-
-					int_gbe_phy_led1: int-gbe-phy-led1@1 {
-						reg = <1>;
-						function = LED_FUNCTION_LAN;
-						status = "disabled";
-					};
-				};
-			};
-		};
-	};
-
-	wo_dlm0: syscon@151e8000 {
-		compatible = "mediatek,mt7986-wo-dlm", "syscon";
-		reg = <0 0x151e8000 0 0x2000>;
-	};
-
-	wo_ilm0: syscon@151e0000 {
-		compatible = "mediatek,mt7986-wo-ilm", "syscon";
-		reg = <0 0x151e0000 0 0x8000>;
-	};
-
-	wo_cpuboot: syscon@15194000 {
-		compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-		reg = <0 0x15194000 0 0x1000>;
-	};
-
-	wo_ccif0: syscon@151a5000 {
-		compatible = "mediatek,mt7986-wo-ccif", "syscon";
-		reg = <0 0x151a5000 0 0x1000>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	sgmiisys0: syscon@10060000 {
-		compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
-		reg = <0 0x10060000 0 0x1000>;
-		mediatek,pnswap;
-		#clock-cells = <1>;
-	};
-
-	sgmiisys1: syscon@10070000 {
-		compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
-		reg = <0 0x10070000 0 0x1000>;
-		#clock-cells = <1>;
-	};
-
-	topmisc: topmisc@11d10000 {
-		compatible = "mediatek,mt7981-topmisc", "syscon";
-		reg = <0 0x11d10000 0 0x10000>;
-		#clock-cells = <1>;
-	};
-
-	snand: snfi@11005000 {
-		compatible = "mediatek,mt7986-snand";
-		reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
-		reg-names = "nfi", "ecc";
-		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI1_CK>,
-			 <&infracfg CLK_INFRA_NFI_HCK_CK>;
-		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-				  <&topckgen CLK_TOP_NFI1X_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
-					 <&topckgen CLK_TOP_CB_M_D8>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	mmc0: mmc@11230000 {
-		compatible = "mediatek,mt7986-mmc",
-					"mediatek,mt7981-mmc";
-		reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
-		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_MSDC_CK>,
-			 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-			 <&infracfg CLK_INFRA_MSDC_66M_CK>,
-			 <&infracfg CLK_INFRA_MSDC_133M_CK>;
-		assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
-				  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
-					 <&topckgen CLK_TOP_CB_NET2_D2>;
-		clock-names = "source", "hclk", "axi_cg", "ahb_cg";
-		status = "disabled";
-	};
-
-	wed_pcie: wed_pcie@10003000 {
-		compatible = "mediatek,wed_pcie";
-		reg = <0 0x10003000 0 0x10>;
-	};
-
-	spi0: spi@1100a000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100a000 0 0x100>;
-		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI0_CK>,
-			 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	spi1: spi@1100b000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x1100b000 0 0x100>;
-		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-			 <&infracfg CLK_INFRA_SPI1_CK>,
-			 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	spi2: spi@11009000 {
-		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0 0x11009000 0 0x100>;
-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_CB_M_D2>,
-			 <&topckgen CLK_TOP_SPI_SEL>,
-			 <&infracfg CLK_INFRA_SPI2_CK>,
-			 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
-		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-		status = "disabled";
-	};
-
-	consys: consys@10000000 {
-		compatible = "mediatek,mt7981-consys";
-		reg = <0 0x10000000 0 0x8600000>;
-		memory-region = <&wmcpu_emi>;
-	};
-
-	xhci: usb@11200000 {
-		compatible = "mediatek,mt7986-xhci",
-			     "mediatek,mtk-xhci";
-		reg = <0 0x11200000 0 0x2e00>,
-		      <0 0x11203e00 0 0x0100>;
-		reg-names = "mac", "ippc";
-		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-			 <&infracfg CLK_INFRA_IUSB_CK>,
-			 <&infracfg CLK_INFRA_IUSB_133_CK>,
-			 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-			 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-		clock-names = "sys_ck",
-			      "ref_ck",
-			      "mcu_ck",
-			      "dma_ck",
-			      "xhci_ck";
-		phys = <&u2port0 PHY_TYPE_USB2>,
-		       <&u3port0 PHY_TYPE_USB3>;
-		vusb33-supply = <&reg_3p3v>;
-		status = "disabled";
-	};
-
-	usb_phy: usb-phy@11e10000 {
-		compatible = "mediatek,mt7981",
-			     "mediatek,generic-tphy-v2";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0 0x11e10000 0x1700>;
-		status = "disabled";
-
-		u2port0: usb-phy@0 {
-			reg = <0x0 0x700>;
-			clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
-		};
-
-		u3port0: usb-phy@700 {
-			reg = <0x700 0x900>;
-			clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-			clock-names = "ref";
-			#phy-cells = <1>;
-			mediatek,syscon-type = <&topmisc 0x218 0>;
-			status = "okay";
-		};
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	efuse: efuse@11f20000 {
-		compatible = "mediatek,mt7981-efuse",
-			     "mediatek,efuse";
-		reg = <0 0x11f20000 0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		status = "okay";
-
-		thermal_calibration: thermal-calib@274 {
-			reg = <0x274 0xc>;
-		};
-
-		phy_calibration: phy-calib@8dc {
-			reg = <0x8dc 0x10>;
-		};
-
-		comb_rx_imp_p0: usb3-rx-imp@8c8 {
-			reg = <0x8c8 1>;
-			bits = <0 5>;
-		};
-
-		comb_tx_imp_p0: usb3-tx-imp@8c8 {
-			reg = <0x8c8 2>;
-			bits = <5 5>;
-		};
-
-		comb_intr_p0: usb3-intr@8c9 {
-			reg = <0x8c9 1>;
-			bits = <2 6>;
-		};
-	};
-
-	afe: audio-controller@11210000 {
-		compatible = "mediatek,mt79xx-audio";
-		reg = <0 0x11210000 0 0x9000>;
-		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-			 <&infracfg CLK_INFRA_AUD_26M_CK>,
-			 <&infracfg CLK_INFRA_AUD_L_CK>,
-			 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-			 <&infracfg CLK_INFRA_AUD_EG2_CK>,
-			 <&topckgen CLK_TOP_AUD_SEL>;
-		clock-names = "aud_bus_ck",
-			      "aud_26m_ck",
-			      "aud_l_ck",
-			      "aud_aud_ck",
-			      "aud_eg2_ck",
-			      "aud_sel";
-		assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-				  <&topckgen CLK_TOP_A1SYS_SEL>,
-				  <&topckgen CLK_TOP_AUD_L_SEL>,
-				  <&topckgen CLK_TOP_A_TUNER_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>,
-					 <&topckgen CLK_TOP_CB_APLL2_196M>,
-					 <&topckgen CLK_TOP_APLL2_D4>;
-		status = "disabled";
-	};
-
-	ice: ice_debug {
-		compatible = "mediatek,mt7981-ice_debug",
-			   "mediatek,mt2701-ice_debug";
-		clocks = <&infracfg CLK_INFRA_DBG_CK>;
-		clock-names = "ice_dbg";
-	};
-
-	wifi: wifi@18000000 {
-		compatible = "mediatek,mt7981-wmac";
-		resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-		reset-names = "consys";
-		pinctrl-0 = <&wifi_dbdc_pins>;
-		pinctrl-names = "dbdc";
-		clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
-			 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-		clock-names = "mcu", "ap2conn";
-		reg = <0 0x18000000 0 0x1000000>,
-		      <0 0x10003000 0 0x1000>,
-		      <0 0x11d10000 0 0x1000>;
-		interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-		memory-region = <&wmcpu_emi>;
-		status = "disabled";
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
deleted file mode 100644
index 779dc6782b..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x14014>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};
-
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
deleted file mode 100644
index 0846d88f62..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <daniel@makrotopia.org>
- *          Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			spi_nand: spi_nand@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x80000>;
-						read-only;
-					};
-
-					partition@80000 {
-						label = "reserved";
-						reg = <0x80000 0x300000>;
-					};
-
-					partition@380000 {
-						label = "fip";
-						reg = <0x380000 0x200000>;
-						read-only;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x7a80000>;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
deleted file mode 100644
index e48881be4e..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <daniel@makrotopia.org>
- *          Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/spi@1100a000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <10000000>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "bl2";
-						reg = <0x0 0x40000>;
-						read-only;
-					};
-
-					partition@40000 {
-						label = "u-boot-env";
-						reg = <0x40000 0x40000>;
-					};
-
-					partition@80000 {
-						label = "reserved2";
-						reg = <0x80000 0x80000>;
-					};
-
-					partition@100000 {
-						label = "fip";
-						reg = <0x100000 0x80000>;
-						read-only;
-					};
-
-					partition@180000 {
-						label = "recovery";
-						reg = <0x180000 0xa80000>;
-					};
-
-					partition@c00000 {
-						label = "fit";
-						reg = <0xc00000 0x1400000>;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
deleted file mode 100644
index f623bce075..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			status = "okay";
-		};
-	};
-};
-
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
deleted file mode 100644
index d326c416a9..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ /dev/null
@@ -1,501 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Authors: Sam.Shih <sam.shih@mediatek.com>
- *          Frank Wunderlich <frank-w@public-files.de>
- *          Daniel Golle <daniel@makrotopia.org>
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-
-#include "mt7986a.dtsi"
-
-/ {
-	model = "Bananapi BPI-R3";
-	chassis-type = "embedded";
-	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	dcin: regulator-12vd {
-		compatible = "regulator-fixed";
-		regulator-name = "12vd";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		#cooling-cells = <2>;
-		/* cooling level (0, 1, 2) - pwm inverted */
-		cooling-levels = <255 96 0>;
-		pwms = <&pwm 0 10000 0>;
-		status = "okay";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		reset-key {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
-		};
-
-		wps-key {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	/* i2c of the left SFP cage (wan) */
-	i2c_sfp1: i2c-gpio-0 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	/* i2c of the right SFP cage (lan) */
-	i2c_sfp2: i2c-gpio-1 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		green_led: led-0 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		blue_led: led-1 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_STATUS;
-			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "1.8vd";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "3.3vd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-		vin-supply = <&dcin>;
-	};
-
-	/* left SFP cage (wan) */
-	sfp1: sfp-1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp1>;
-		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-
-	/* right SFP cage (lan) */
-	sfp2: sfp-2 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp2>;
-		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-};
-
-&cpu_thermal {
-	cooling-maps {
-		cpu-active-high {
-			/* active: set fan to cooling level 2 */
-			cooling-device = <&fan 2 2>;
-			trip = <&cpu_trip_active_high>;
-		};
-
-		cpu-active-med {
-			/* active: set fan to cooling level 1 */
-			cooling-device = <&fan 1 1>;
-			trip = <&cpu_trip_active_med>;
-		};
-
-		cpu-active-low {
-			/* active: set fan to cooling level 0 */
-			cooling-device = <&fan 0 0>;
-			trip = <&cpu_trip_active_low>;
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-		sfp = <&sfp1>;
-		managed = "in-band-status";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&mdio {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c_pins>;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	i2c_pins: i2c-pins {
-		mux {
-			function = "i2c";
-			groups = "i2c";
-		};
-	};
-
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_pereset";
-		};
-	};
-
-	pwm_pins: pwm-pins {
-		mux {
-			function = "pwm";
-			groups = "pwm0", "pwm1_0";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-	};
-
-	spic_pins: spic-pins {
-		mux {
-			function = "spi";
-			groups = "spi1_0";
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1_rx_tx";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2_0_rx_tx";
-		};
-	};
-
-	wf_2g_5g_pins: wf-2g-5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf-dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_led_pins: wf-led-pins {
-		mux {
-			function = "led";
-			groups = "wifi_led";
-		};
-	};
-};
-
-&pwm {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm_pins>;
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	status = "okay";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins>;
-	status = "okay";
-};
-
-&ssusb {
-	status = "okay";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "wan";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan0";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan1";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan2";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "lan3";
-		};
-
-		port5: port@5 {
-			reg = <5>;
-			label = "lan4";
-			phy-mode = "2500base-x";
-			sfp = <&sfp2>;
-			managed = "in-band-status";
-		};
-
-		port@6 {
-			reg = <6>;
-			label = "cpu";
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&trng {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-
-	led {
-		led-active-low;
-	};
-};
-
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
deleted file mode 100644
index ce007099d2..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snand";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nand: spi_nand@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <10000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "BL2";
-				reg = <0x00000 0x0100000>;
-				read-only;
-			};
-			partition@100000 {
-				label = "u-boot-env";
-				reg = <0x0100000 0x0080000>;
-			};
-			factory: partition@180000 {
-				label = "Factory";
-				reg = <0x180000 0x0200000>;
-			};
-			partition@380000 {
-				label = "FIP";
-				reg = <0x380000 0x0200000>;
-			};
-			partition@580000 {
-				label = "ubi";
-				reg = <0x580000 0x4000000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
deleted file mode 100644
index ea148315f0..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snor";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nor: spi_nor@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@00000 {
-				label = "BL2";
-				reg = <0x00000 0x0040000>;
-			};
-			partition@40000 {
-				label = "u-boot-env";
-				reg = <0x40000 0x0010000>;
-			};
-			factory: partition@50000 {
-				label = "Factory";
-				reg = <0x50000 0x00B0000>;
-			};
-			partition@100000 {
-				label = "FIP";
-				reg = <0x100000 0x0080000>;
-			};
-			partition@180000 {
-				label = "firmware";
-				reg = <0x180000 0xE00000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
deleted file mode 100644
index 26d560bd4b..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
+++ /dev/null
@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986a.dtsi"
-
-/ {
-	model = "MediaTek MT7986a RFB";
-	compatible = "mediatek,mt7986a-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&mdio {
-	phy5: phy@5 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <5>;
-
-		reset-gpios = <&pio 6 1>;
-		reset-deassert-us = <20000>;
-	};
-
-	phy6: phy@6 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <6>;
-	};
-
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		reset-gpios = <&pio 5 0>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	hs400-ds-delay = <0x14014>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-		};
-	};
-
-	spic_pins_g2: spic-pins-29-to-32 {
-		mux {
-			function = "spi";
-			groups = "spi1_2";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins-33-to-38 {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
-			drive-strength = <8>;
-			mediatek,pull-up-adv = <0>;	/* bias-disable */
-		};
-		conf-pd {
-			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
-			drive-strength = <8>;
-			mediatek,pull-down-adv = <0>;	/* bias-disable */
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2";
-		};
-	};
-
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins_g2>;
-	status = "okay";
-
-	proslic_spi: proslic_spi@0 {
-		compatible = "silabs,proslic_spi";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-		spi-cpha = <1>;
-		spi-cpol = <1>;
-		channel_count = <1>;
-		debug_level = <4>;       /* 1 = TRC, 2 = DBG, 4 = ERR */
-		reset_gpio = <&pio 7 0>;
-		ig,enable-spi = <1>;     /* 1: Enable, 0: Disable */
-	};
-};
-
-&gmac1 {
-	phy-mode = "2500base-x";
-	phy-connection-type = "2500base-x";
-	phy-handle = <&phy6>;
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "wan";
-		};
-
-		port@5 {
-			reg = <5>;
-			label = "lan6";
-
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
deleted file mode 100644
index 64f2cf3756..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ /dev/null
@@ -1,645 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/phy/phy.h>
-
-/ {
-	compatible = "mediatek,mt7986a";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	clk40m: oscillator-40m {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x0>;
-			#cooling-cells = <2>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x1>;
-			#cooling-cells = <2>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			enable-method = "psci";
-			reg = <0x2>;
-			#cooling-cells = <2>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			enable-method = "psci";
-			compatible = "arm,cortex-a53";
-			reg = <0x3>;
-			#cooling-cells = <2>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@4fc00000 {
-			no-map;
-			reg = <0 0x4fc00000 0 0x00100000>;
-		};
-
-		wo_emi0: wo-emi@4fd00000 {
-			reg = <0 0x4fd00000 0 0x40000>;
-			no-map;
-		};
-
-		wo_emi1: wo-emi@4fd40000 {
-			reg = <0 0x4fd40000 0 0x40000>;
-			no-map;
-		};
-
-		wo_ilm0: wo-ilm@151e0000 {
-			reg = <0 0x151e0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_ilm1: wo-ilm@151f0000 {
-			reg = <0 0x151f0000 0 0x8000>;
-			no-map;
-		};
-
-		wo_data: wo-data@4fd80000 {
-			reg = <0 0x4fd80000 0 0x240000>;
-			no-map;
-		};
-
-		wo_dlm0: wo-dlm@151e8000 {
-			reg = <0 0x151e8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_dlm1: wo-dlm@151f8000 {
-			reg = <0 0x151f8000 0 0x2000>;
-			no-map;
-		};
-
-		wo_boot: wo-boot@15194000 {
-			reg = <0 0x15194000 0 0x1000>;
-			no-map;
-		};
-
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			#interrupt-cells = <3>;
-			interrupt-parent = <&gic>;
-			interrupt-controller;
-			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
-			      <0 0x0c080000 0 0x80000>,  /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7986-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		wed_pcie: wed-pcie@10003000 {
-			compatible = "mediatek,mt7986-wed-pcie",
-				     "syscon";
-			reg = <0 0x10003000 0 0x10>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7986-topckgen", "syscon";
-			reg = <0 0x1001B000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7986-wdt";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-			status = "disabled";
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7986-apmixedsys";
-			reg = <0 0x1001E000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7986a-pinctrl";
-			reg = <0 0x1001f000 0 0x1000>,
-			      <0 0x11c30000 0 0x1000>,
-			      <0 0x11c40000 0 0x1000>,
-			      <0 0x11e20000 0 0x1000>,
-			      <0 0x11e30000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x11f10000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
-				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 100>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7986-sgmiisys_0",
-				     "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7986-sgmiisys_1",
-				     "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		trng: rng@1020f000 {
-			compatible = "mediatek,mt7986-rng",
-				     "mediatek,mt7623-rng";
-			reg = <0 0x1020f000 0 0x100>;
-			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
-			clock-names = "rng";
-			status = "disabled";
-		};
-
-		crypto: crypto@10320000 {
-			compatible = "inside-secure,safexcel-eip97";
-			reg = <0 0x10320000 0 0x40000>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
-			clock-names = "infra_eip97_ck";
-			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
-			status = "disabled";
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7986-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#clock-cells = <1>;
-			#pwm-cells = <2>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_PWM_SEL>,
-				 <&infracfg CLK_INFRA_PWM_STA>,
-				 <&infracfg CLK_INFRA_PWM1_CK>,
-				 <&infracfg CLK_INFRA_PWM2_CK>;
-			clock-names = "top", "main", "pwm1", "pwm2";
-			status = "disabled";
-		};
-
-		uart0: serial@11002000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11002000 0 0x400>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-				 <&infracfg CLK_INFRA_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		uart1: serial@11003000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11003000 0 0x400>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-				 <&infracfg CLK_INFRA_UART1_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		uart2: serial@11004000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11004000 0 0x400>;
-			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-				 <&infracfg CLK_INFRA_UART2_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
-			status = "disabled";
-		};
-
-		i2c0: i2c@11008000 {
-			compatible = "mediatek,mt7986-i2c";
-			reg = <0 0x11008000 0 0x90>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <5>;
-			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-				 <&infracfg CLK_INFRA_AP_DMA_CK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@1100a000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100a000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI0_CK>,
-				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		spi1: spi@1100b000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x1100b000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-				 <&infracfg CLK_INFRA_SPI1_CK>,
-				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			status = "disabled";
-		};
-
-		auxadc: adc@1100d000 {
-			compatible = "mediatek,mt7986-auxadc";
-			reg = <0 0x1100d000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
-			clock-names = "main";
-			#io-channel-cells = <1>;
-			status = "disabled";
-		};
-
-		ssusb: usb@11200000 {
-			compatible = "mediatek,mt7986-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-				 <&infracfg CLK_INFRA_IUSB_CK>,
-				 <&infracfg CLK_INFRA_IUSB_133_CK>,
-				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-			clock-names = "sys_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck",
-				      "xhci_ck";
-			phys = <&u2port0 PHY_TYPE_USB2>,
-			       <&u3port0 PHY_TYPE_USB3>,
-			       <&u2port1 PHY_TYPE_USB2>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11c20000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
-				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-				 <&infracfg CLK_INFRA_MSDC_CK>,
-				 <&infracfg CLK_INFRA_MSDC_133M_CK>,
-				 <&infracfg CLK_INFRA_MSDC_66M_CK>;
-			clock-names = "source", "hclk", "source_cg", "bus_clk",
-				      "sys_cg";
-			status = "disabled";
-		};
-
-		thermal: thermal@1100c800 {
-			#thermal-sensor-cells = <1>;
-			compatible = "mediatek,mt7986-thermal";
-			reg = <0 0x1100c800 0 0x800>;
-			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_THERM_CK>,
-				 <&infracfg CLK_INFRA_ADC_26M_CK>,
-				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-			clock-names = "therm", "auxadc", "adc_32k";
-			mediatek,auxadc = <&auxadc>;
-			mediatek,apmixedsys = <&apmixedsys>;
-			nvmem-cells = <&thermal_calibration>;
-			nvmem-cell-names = "calibration-data";
-		};
-
-		pcie: pcie@11280000 {
-			compatible = "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			device_type = "pci";
-			#address-cells = <3>;
-			#size-cells = <2>;
-			reg = <0x00 0x11280000 0x00 0x4000>;
-			reg-names = "pcie-mac";
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			ranges = <0x82000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x10000000>;
-			clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-				 <&infracfg CLK_INFRA_IPCIE_CK>,
-				 <&infracfg CLK_INFRA_IPCIER_CK>,
-				 <&infracfg CLK_INFRA_IPCIEB_CK>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
-			status = "disabled";
-
-			phys = <&pcie_port PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			pcie_intc: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie_phy: t-phy@11c00000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			status = "disabled";
-
-			pcie_port: pcie-phy@11c00000 {
-				reg = <0 0x11c00000 0 0x20000>;
-				clocks = <&clk40m>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		efuse: efuse@11d00000 {
-			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
-			reg = <0 0x11d00000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			thermal_calibration: calib@274 {
-				reg = <0x274 0xc>;
-			};
-		};
-
-		usb_phy: t-phy@11e10000 {
-			compatible = "mediatek,mt7986-tphy",
-				     "mediatek,generic-tphy-v2";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0 0x11e10000 0x1700>;
-			status = "disabled";
-
-			u2port0: usb-phy@0 {
-				reg = <0x0 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-
-			u3port0: usb-phy@700 {
-				reg = <0x700 0x900>;
-				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			u2port1: usb-phy@1000 {
-				reg = <0x1000 0x700>;
-				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-				clock-names = "ref", "da_ref";
-				#phy-cells = <1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			 #address-cells = <1>;
-			 #size-cells = <1>;
-			 compatible = "mediatek,mt7986-ethsys",
-				      "syscon";
-			 reg = <0 0x15000000 0 0x1000>;
-			 #clock-cells = <1>;
-			 #reset-cells = <1>;
-		};
-
-		wed0: wed@15010000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15010000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif0>;
-		};
-
-		wed1: wed@15011000 {
-			compatible = "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15011000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-					<&wo_data>, <&wo_boot>;
-			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-					      "wo-data", "wo-boot";
-			mediatek,wo-ccif = <&wo_ccif1>;
-		};
-
-		wo_ccif0: syscon@151a5000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151a5000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ccif1: syscon@151ad000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151ad000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7986-eth";
-			reg = <0 0x15100000 0 0x80000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETH_FE_EN>,
-				 <&ethsys CLK_ETH_GP2_EN>,
-				 <&ethsys CLK_ETH_GP1_EN>,
-				 <&ethsys CLK_ETH_WOCPU1_EN>,
-				 <&ethsys CLK_ETH_WOCPU0_EN>,
-				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
-				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
-				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
-				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
-			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
-				      "sgmii_tx250m", "sgmii_rx250m",
-				      "sgmii_cdr_ref", "sgmii_cdr_fb",
-				      "sgmii2_tx250m", "sgmii2_rx250m",
-				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
-				      "netsys0", "netsys1";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_SGM_325M_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,wed-pcie = <&wed_pcie>;
-			mediatek,wed = <&wed0>, <&wed1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		wifi: wifi@18000000 {
-			compatible = "mediatek,mt7986-wmac";
-			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-			reset-names = "consys";
-			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
-				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-			clock-names = "mcu", "ap2conn";
-			reg = <0 0x18000000 0 0x1000000>,
-			      <0 0x10003000 0 0x1000>,
-			      <0 0x11d10000 0 0x1000>;
-			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wmcpu_emi>;
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-
-			trips {
-				cpu_trip_crit: crit {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-
-				cpu_trip_hot: hot {
-					temperature = <120000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
deleted file mode 100644
index 8cd094f7c3..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986b.dtsi"
-
-/ {
-	model = "MediaTek MT7986b RFB";
-	compatible = "mediatek,mt7986b-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy5: phy@5 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <5>;
-			reset-gpios = <&pio 6 1>;
-			reset-deassert-us = <20000>;
-			phy-mode = "2500base-x";
-		};
-
-		phy6: phy@6 {
-			compatible = "ethernet-phy-id67c9.de0a";
-			reg = <6>;
-			phy-mode = "2500base-x";
-		};
-
-		switch@1f {
-			compatible = "mediatek,mt7531";
-			reg = <31>;
-			reset-gpios = <&pio 5 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "2500base-x";
-
-					fixed-link {
-						speed = <2500>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-		};
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
deleted file mode 100644
index db5189664c..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include "mt7986a.dtsi"
-/ {
-	compatible = "mediatek,mt7986b";
-};
-
-&pio {
-	compatible = "mediatek,mt7986b-pinctrl";
-	gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
deleted file mode 100644
index 3f8ac2ae38..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_emmc_51>;
-			pinctrl-1 = <&mmc0_pins_emmc_51>;
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x12814>;
-			vqmmc-supply = <&reg_1p8v>;
-			vmmc-supply = <&reg_3p3v>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
deleted file mode 100644
index d21a61ad19..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy0: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
deleted file mode 100644
index 86ab7566dc..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "internal";
-			phy-connection-type = "internal";
-			phy = <&int_2p5g_phy>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&int_2p5g_phy>;
-		__overlay__ {
-			pinctrl-names = "i2p5gbe-led";
-			pinctrl-0 = <&i2p5gbe_led0_pins>;
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
deleted file mode 100644
index 34a23bbd7e..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy13: ethernet-phy@13 {
-				reg = <13>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy13>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
deleted file mode 100644
index ba40a119cb..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c2_0_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp1: sfp@1 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c2>;
-				mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp1>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
deleted file mode 100644
index 140391fc45..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy8: ethernet-phy@8 {
-				reg = <8>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy8>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
deleted file mode 100644
index 19e0b2799f..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy5>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
deleted file mode 100644
index b9aabd2726..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c1>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c1_sfp_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp0: sfp@0 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c1>;
-				mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
deleted file mode 100644
index 04472cc12d..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@1 {
-		target-path = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_sdcard>;
-			pinctrl-1 = <&mmc0_pins_sdcard>;
-			cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			vmmc-supply = <&reg_3p3v>;
-			vqmmc-supply = <&reg_3p3v>;
-			no-mmc;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
deleted file mode 100644
index 86b0042f64..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&snand>;
-		__overlay__ {
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&bch>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
deleted file mode 100644
index a9eca00d44..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi0_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso
deleted file mode 100644
index 33bd57b3fb..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi2_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "jedec,spi-nor";
-				spi-cal-enable;
-				spi-cal-mode = "read-data";
-				spi-cal-datalen = <7>;
-				spi-cal-data = /bits/ 8 <
-					0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
-				spi-cal-addrlen = <1>;
-				spi-cal-addr = /bits/ 32 <0x0>;
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partition@00000 {
-					label = "BL2";
-					reg = <0x00000 0x0040000>;
-				};
-				partition@40000 {
-					label = "u-boot-env";
-					reg = <0x40000 0x0010000>;
-				};
-				partition@50000 {
-					label = "Factory";
-					reg = <0x50000 0x0200000>;
-				};
-				partition@250000 {
-					label = "FIP";
-					reg = <0x250000 0x0080000>;
-				};
-				partition@2D0000 {
-					label = "firmware";
-					reg = <0x2D0000 0x1D30000>;
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
deleted file mode 100644
index 11dbf98301..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
-	model = "MediaTek MT7988A Reference Board";
-	compatible = "mediatek,mt7988a-rfb",
-		     "mediatek,mt7988";
-
-	chosen {
-		bootargs = "console=ttyS0,115200n1 loglevel=8  \
-			    earlycon=uart8250,mmio32,0x11000000 \
-			    pci=pcie_bus_perf";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-};
-
-&eth {
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-};
-
-&gmac0 {
-	status = "okay";
-};
-
-&cpu0 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&eth {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&gsw_phy0 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_phy0_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	rt5190a_64: rt5190a@64 {
-		compatible = "richtek,rt5190a";
-		reg = <0x64>;
-		/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
-		vin2-supply = <&rt5190_buck1>;
-		vin3-supply = <&rt5190_buck1>;
-		vin4-supply = <&rt5190_buck1>;
-
-		regulators {
-			rt5190_buck1: buck1 {
-				regulator-name = "rt5190a-buck1";
-				regulator-min-microvolt = <5090000>;
-				regulator-max-microvolt = <5090000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			buck2 {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			rt5190_buck3: buck3 {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-			};
-			buck4 {
-				regulator-name = "rt5190a-buck4";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			ldo {
-				regulator-name = "rt5190a-ldo";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&pcie2 {
-	status = "disabled";
-};
-
-&pcie3 {
-	status = "okay";
-};
-
-&ssusb0 {
-	status = "okay";
-};
-
-&ssusb1 {
-	status = "okay";
-};
-
-&tphy {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&xphy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
deleted file mode 100644
index 81410c017b..0000000000
--- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ /dev/null
@@ -1,1456 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/ti-syscon.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-	compatible = "mediatek,mt7988";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cci: cci {
-		compatible = "mediatek,mt7988-cci",
-			     "mediatek,mt8183-cci";
-		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
-			 <&topckgen CLK_TOP_XTAL>;
-		clock-names = "cci", "intermediate";
-		operating-points-v2 = <&cci_opp>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a73";
-			reg = <0x0>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a73";
-			reg = <0x1>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu2: cpu@2 {
-			compatible = "arm,cortex-a73";
-			reg = <0x2>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu3: cpu@3 {
-			compatible = "arm,cortex-a73";
-			reg = <0x3>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cluster0_opp: opp_table0 {
-			compatible = "operating-points-v2";
-			opp-shared;
-
-			opp00 {
-				opp-hz = /bits/ 64 <800000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp01 {
-				opp-hz = /bits/ 64 <1100000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp02 {
-				opp-hz = /bits/ 64 <1500000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp03 {
-				opp-hz = /bits/ 64 <1800000000>;
-				opp-microvolt = <900000>;
-			};
-		};
-	};
-
-	cci_opp: opp_table_cci {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp00 {
-			opp-hz = /bits/ 64 <480000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp01 {
-			opp-hz = /bits/ 64 <660000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp02 {
-			opp-hz = /bits/ 64 <900000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp03 {
-			opp-hz = /bits/ 64 <1080000000>;
-			opp-microvolt = <900000>;
-		};
-	};
-
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	pmu {
-		compatible = "arm,cortex-a73-pmu";
-		interrupt-parent = <&gic>;
-		interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reserved-memory {
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x50000>;
-			no-map;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-			      <0 0x0c080000 0 0x200000>, /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		phyfw: phy-firmware@f000000 {
-			compatible = "mediatek,2p5gphy-fw";
-			reg = <0 0x0f000000 0 0x8000>,
-			      <0 0x0f100000 0 0x20000>,
-			      <0 0x0f0f0000 0 0x200>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7988-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7988-topckgen", "syscon";
-			reg = <0 0x1001b000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7988-wdt",
-				     "mediatek,mt6589-wdt",
-				     "syscon";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7988-apmixedsys";
-			reg = <0 0x1001e000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7988-pinctrl", "syscon";
-			reg = <0 0x1001f000 0 0x1000>,
-			      <0 0x11c10000 0 0x1000>,
-			      <0 0x11d00000 0 0x1000>,
-			      <0 0x11d20000 0 0x1000>,
-			      <0 0x11e00000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio_base", "iocfg_tr_base",
-				    "iocfg_br_base", "iocfg_rb_base",
-				    "iocfg_lb_base", "iocfg_tl_base", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 84>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-
-			mdio0_pins: mdio0-pins {
-				mux {
-					function = "eth";
-					groups = "mdc_mdio0";
-				};
-
-				conf {
-					groups = "mdc_mdio0";
-					drive-strength = <MTK_DRIVE_8mA>;
-				};
-			};
-
-			i2c0_pins: i2c0-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c0_1";
-				};
-			};
-
-			i2c1_pins: i2c1-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_0";
-				};
-			};
-
-			i2c1_sfp_pins: i2c1-sfp-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_sfp";
-				};
-			};
-
-			i2c2_pins: i2c2-pins {
-				mux {
-					function = "i2c";
-					groups = "i2c2";
-				};
-			};
-
-			i2c2_0_pins: i2c2-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_0";
-				};
-			};
-
-			i2c2_1_pins: i2c2-pins-g1 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_1";
-				};
-			};
-
-			gbe0_led0_pins: gbe0-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led0";
-				};
-			};
-
-			gbe1_led0_pins: gbe1-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led0";
-				};
-			};
-
-			gbe2_led0_pins: gbe2-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led0";
-				};
-			};
-
-			gbe3_led0_pins: gbe3-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led0";
-				};
-			};
-
-			gbe0_led1_pins: gbe0-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led1";
-				};
-			};
-
-			gbe1_led1_pins: gbe1-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led1";
-				};
-			};
-
-			gbe2_led1_pins: gbe2-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led1";
-				};
-			};
-
-			gbe3_led1_pins: gbe3-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led1";
-				};
-			};
-
-			i2p5gbe_led0_pins: 2p5gbe-led0-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led0";
-				};
-			};
-
-			i2p5gbe_led1_pins: 2p5gbe-led1-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led1";
-				};
-			};
-
-			mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
-				mux {
-					function = "flash";
-					groups = "emmc_45";
-				};
-			};
-
-			mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
-				mux {
-					function = "flash";
-					groups = "emmc_51";
-				};
-			};
-
-			mmc0_pins_sdcard: mmc0-pins-sdcard {
-				mux {
-					function = "flash";
-					groups = "sdcard";
-				};
-			};
-
-			uart0_pins: uart0-pins {
-				mux {
-					function = "uart";
-					groups =  "uart0";
-				};
-			};
-
-			snfi_pins: snfi-pins {
-				mux {
-					function = "flash";
-					groups = "snfi";
-				};
-			};
-
-			spi0_pins: spi0-pins {
-				mux {
-					function = "spi";
-					groups = "spi0";
-				};
-			};
-
-			spi0_flash_pins: spi0-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi0", "spi0_wp_hold";
-				};
-			};
-
-			spi1_pins: spi1-pins {
-				mux {
-					function = "spi";
-					groups = "spi1";
-				};
-			};
-
-			spi2_pins: spi2-pins {
-				mux {
-					function = "spi";
-					groups = "spi2";
-				};
-			};
-
-			spi2_flash_pins: spi2-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi2", "spi2_wp_hold";
-				};
-			};
-
-			pcie0_pins: pcie0-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
-						 "pcie_wake_n0_0";
-				};
-			};
-
-			pcie1_pins: pcie1-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
-						 "pcie_wake_n1_0";
-				};
-			};
-
-			pcie2_pins: pcie2-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
-						 "pcie_wake_n2_0";
-				};
-			};
-
-			pcie3_pins: pcie3-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
-						 "pcie_wake_n3_0";
-				};
-			};
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7988-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#pwm-cells = <2>;
-			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK1>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK2>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK3>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK4>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK5>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK6>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK7>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK8>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-				      "pwm4","pwm5","pwm6","pwm7","pwm8";
-			status = "disabled";
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_0",
-				     "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_1",
-				     "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		usxgmiisys0: usxgmiisys@10080000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_0",
-				     "syscon";
-			reg = <0 0x10080000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		usxgmiisys1: usxgmiisys@10081000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_1",
-				     "syscon";
-			reg = <0 0x10081000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		mcusys: mcusys@100e0000 {
-			compatible = "mediatek,mt7988-mcusys", "syscon";
-			reg = <0 0x100e0000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		uart0: serial@11000000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11000000 0 0x100>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-			 * 8250-mtk driver don't control "baud" clock since commit
-			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
-			 * still need to be passed to the driver to prevent probe fail
-			 */
-			clocks = <&topckgen CLK_TOP_UART_SEL>,
-				 <&infracfg CLK_INFRA_52M_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart0_pins>;
-			status = "disabled";
-		};
-
-		snand: spi@11001000 {
-			compatible = "mediatek,mt7986-snand";
-			reg = <0 0x11001000 0 0x1000>;
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_SPINFI>,
-				 <&infracfg CLK_INFRA_NFI>;
-			clock-names = "pad_clk", "nfi_clk";
-			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-					  <&topckgen CLK_TOP_NFI1X_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
-						 <&topckgen CLK_TOP_MPLL_D8>;
-			nand-ecc-engine = <&bch>;
-			mediatek,quad-spi;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&snfi_pins>;
-			status = "disabled";
-		};
-
-		bch: ecc@11002000 {
-			compatible = "mediatek,mt7686-ecc";
-			reg = <0 0x11002000 0 0x1000>;
-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
-			clock-names = "nfiecc_clk";
-			status = "disabled";
-		};
-
-		i2c0: i2c@11003000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11003000 0 0x1000>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c1: i2c@11004000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11004000 0 0x1000>,
-			      <0 0x10217100 0 0x80>;
-			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@11005000 {
-			compatible = "mediatek,mt7988-i2c",
-				"mediatek,mt7981-i2c";
-			reg = <0 0x11005000 0 0x1000>,
-			      <0 0x10217180 0 0x80>;
-			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@11007000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11007000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI0>,
-				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi1: spi@11008000 {
-			compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
-			reg = <0 0x11008000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI1>,
-				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi1_pins>;
-			status = "disabled";
-		};
-
-		spi2: spi@11009000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11009000 0 0x100>;
-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
-				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		fan: pwm-fan {
-			compatible = "pwm-fan";
-			/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
-			cooling-levels = <0 128 255>;
-			#cooling-cells = <2>;
-			#thermal-sensor-cells = <1>;
-			status = "disabled";
-		};
-
-		lvts: lvts@1100a000 {
-			compatible = "mediatek,mt7988-lvts";
-			reg = <0 0x1100a000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
-			clock-names = "lvts_clk";
-			nvmem-cells = <&lvts_calibration>;
-			nvmem-cell-names = "e_data1";
-			#thermal-sensor-cells = <1>;
-		};
-
-		ssusb0: usb@11190000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11190000 0 0x2e00>,
-			      <0 0x11193e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&xphyu2port0 PHY_TYPE_USB2>,
-			       <&xphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS>,
-				 <&infracfg CLK_INFRA_USB_XHCI>,
-				 <&infracfg CLK_INFRA_USB_REF>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			mediatek,p0_speed_fixup;
-			status = "disabled";
-		};
-
-		ssusb1: usb@11200000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&tphyu2port0 PHY_TYPE_USB2>,
-			       <&tphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_CK_P1>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-		};
-
-		afe: audio-controller@11210000 {
-			compatible = "mediatek,mt79xx-audio";
-			reg = <0 0x11210000 0 0x9000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
-				 <&infracfg CLK_INFRA_AUD_26M>,
-				 <&infracfg CLK_INFRA_AUD_L>,
-				 <&infracfg CLK_INFRA_AUD_AUD>,
-				 <&infracfg CLK_INFRA_AUD_EG2>,
-				 <&topckgen CLK_TOP_AUD_SEL>,
-				 <&topckgen CLK_TOP_AUD_I2S_M>;
-			clock-names = "aud_bus_ck",
-				      "aud_26m_ck",
-				      "aud_l_ck",
-				      "aud_aud_ck",
-				      "aud_eg2_ck",
-				      "aud_sel",
-				      "aud_i2s_m";
-			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-					  <&topckgen CLK_TOP_A1SYS_SEL>,
-					  <&topckgen CLK_TOP_AUD_L_SEL>,
-					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>,
-						 <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc",
-				     "mediatek,mt7981-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11D60000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_MSDC400>,
-				 <&infracfg CLK_INFRA_MSDC2_HCK>,
-				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
-				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
-			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
-					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
-						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
-			clock-names = "source",
-				      "hclk",
-				      "axi_cg",
-				      "ahb_cg";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		pcie2: pcie@11280000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11280000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x20200000 0x00
-				  0x20200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <3>;
-			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie2_pins>;
-			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
-					<0 0 0 2 &pcie_intc2 1>,
-					<0 0 0 3 &pcie_intc2 2>,
-					<0 0 0 4 &pcie_intc2 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc2: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie3: pcie@11290000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11290000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x28000000 0x00
-				  0x28000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x28200000 0x00
-				  0x28200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <2>;
-			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie3_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
-					<0 0 0 2 &pcie_intc3 1>,
-					<0 0 0 3 &pcie_intc3 2>,
-					<0 0 0 4 &pcie_intc3 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc3: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie0: pcie@11300000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11300000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x30000000 0x00
-				  0x30000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x30200000 0x00
-				  0x30200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <0>;
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie0_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-					<0 0 0 2 &pcie_intc0 1>,
-					<0 0 0 3 &pcie_intc0 2>,
-					<0 0 0 4 &pcie_intc0 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc0: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie1: pcie@11310000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11310000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x38000000 0x00
-				  0x38000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x38200000 0x00
-				  0x38200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <1>;
-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie1_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-					<0 0 0 2 &pcie_intc1 1>,
-					<0 0 0 3 &pcie_intc1 2>,
-					<0 0 0 4 &pcie_intc1 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc1: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		tphy: tphy@11c50000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,generic-tphy-v2";
-			ranges;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			tphyu2port0: usb-phy@11c50000 {
-				reg = <0 0x11c50000 0 0x700>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			tphyu3port0: usb-phy@11c50700 {
-				reg = <0 0x11c50700 0 0x900>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,usb3-pll-ssc-delta;
-				mediatek,usb3-pll-ssc-delta1;
-			};
-		};
-
-		topmisc: topmisc@11d10000 {
-			compatible = "mediatek,mt7988-topmisc", "syscon",
-				     "mediatek,mt7988-power-controller";
-			reg = <0 0x11d10000 0 0x10000>;
-			#clock-cells = <1>;
-			#power-domain-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		xphy: xphy@11e10000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,xsphy";
-			ranges;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			xphyu2port0: usb-phy@11e10000 {
-				reg = <0 0x11e10000 0 0x400>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			xphyu3port0: usb-phy@11e13000 {
-				reg = <0 0x11e13400 0 0x500>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,syscon-type = <&topmisc 0x218 0>;
-			};
-		};
-
-		xfi_pextp0: xfi-pextp@11f20000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_0",
-				     "syscon";
-			reg = <0 0x11f20000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		xfi_pextp1: xfi-pextp@11f30000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_1",
-				     "syscon";
-			reg = <0 0x11f30000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		xfi_pll: xfi-pll@11f40000 {
-			compatible = "mediatek,mt7988-xfi-pll", "syscon";
-			reg = <0 0x11f40000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		efuse: efuse@11f50000 {
-			compatible = "mediatek,efuse";
-			reg = <0 0x11f50000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			lvts_calibration: calib@918 {
-				reg = <0x918 0x28>;
-			};
-
-			phy_calibration_p0: calib@940 {
-				reg = <0x940 0x10>;
-			};
-
-			phy_calibration_p1: calib@954 {
-				reg = <0x954 0x10>;
-			};
-
-			phy_calibration_p2: calib@968 {
-				reg = <0x968 0x10>;
-			};
-
-			phy_calibration_p3: calib@97c {
-				reg = <0x97c 0x10>;
-			};
-
-			cpufreq_calibration: calib@278 {
-				reg = <0x278 0x1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			compatible = "mediatek,mt7988-ethsys", "syscon";
-			reg = <0 0x15000000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-		};
-
-		switch: switch@15020000 {
-			compatible = "mediatek,mt7988-switch";
-			reg = <0 0x15020000 0 0x8000>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ethrst 0>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy0>;
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy1>;
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy2>;
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy3>;
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "internal";
-
-					fixed-link {
-						speed = <10000>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				mediatek,pio = <&pio>;
-
-				gsw_phy0: ethernet-phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <0>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p0>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy0_led0: gsw-phy0-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy0_led1: gsw-phy0-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy1: ethernet-phy@1 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <1>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p1>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy1_led0: gsw-phy1-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy1_led1: gsw-phy1-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy2: ethernet-phy@2 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <2>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p2>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy2_led0: gsw-phy2-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy2_led1: gsw-phy2-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy3: ethernet-phy@3 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <3>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p3>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy3_led0: gsw-phy3-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy3_led1: gsw-phy3-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-			};
-		};
-
-		ethwarp: syscon@15031000 {
-			compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
-			reg = <0 0x15031000 0 0x1000>;
-			#clock-cells = <1>;
-
-			ethrst: reset-controller {
-				compatible = "ti,syscon-reset";
-				#reset-cells = <1>;
-				ti,reset-bits = <
-					0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
-				>;
-			};
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7988-eth";
-			reg = <0 0x15100000 0 0x80000>,
-			      <0 0x15400000 0 0x380000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
-				 <&ethsys CLK_ETHDMA_XGP2_EN>,
-				 <&ethsys CLK_ETHDMA_XGP3_EN>,
-				 <&ethsys CLK_ETHDMA_FE_EN>,
-				 <&ethsys CLK_ETHDMA_GP2_EN>,
-				 <&ethsys CLK_ETHDMA_GP1_EN>,
-				 <&ethsys CLK_ETHDMA_GP3_EN>,
-				 <&ethsys CLK_ETHDMA_ESW_EN>,
-				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
-				 <&sgmiisys0 CLK_SGM0_TX_EN>,
-				 <&sgmiisys0 CLK_SGM0_RX_EN>,
-				 <&sgmiisys1 CLK_SGM1_TX_EN>,
-				 <&sgmiisys1 CLK_SGM1_RX_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-				 <&topckgen CLK_TOP_SGM_0_SEL>,
-				 <&topckgen CLK_TOP_SGM_1_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
-				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
-				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_MII_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
-			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
-				      "gp3", "esw", "crypto", "sgmii_tx250m",
-				      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
-				      "ethwarp_wocpu2", "ethwarp_wocpu1",
-				      "ethwarp_wocpu0", "top_usxgmii0_sel",
-				      "top_usxgmii1_sel", "top_sgm0_sel",
-				      "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
-				      "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
-				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
-				      "top_eth_sys_sel", "top_eth_xgmii_sel",
-				      "top_eth_mii_sel", "top_netsys_sel",
-				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
-				      "top_netsys_sync_250m_sel",
-				      "top_netsys_ppefb_250m_sel",
-				      "top_netsys_warp_sel";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-					  <&topckgen CLK_TOP_SGM_0_SEL>,
-					  <&topckgen CLK_TOP_SGM_1_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&topckgen CLK_TOP_NET1PLL_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
-			mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
-			mediatek,xfi-pll = <&xfi_pll>;
-			mediatek,infracfg = <&topmisc>;
-			mediatek,toprgu = <&watchdog>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			gmac0: mac@0 {
-				compatible = "mediatek,eth-mac";
-				reg = <0>;
-				phy-mode = "internal";
-				status = "disabled";
-
-				fixed-link {
-					speed = <10000>;
-					full-duplex;
-					pause;
-				};
-			};
-
-			gmac1: mac@1 {
-				compatible = "mediatek,eth-mac";
-				reg = <1>;
-				status = "disabled";
-			};
-
-			gmac2: mac@2 {
-				compatible = "mediatek,eth-mac";
-				reg = <2>;
-				status = "disabled";
-			};
-
-			mdio_bus: mdio-bus {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				/* internal 2.5G PHY */
-				int_2p5g_phy: ethernet-phy@15 {
-					compatible = "ethernet-phy-ieee802.3-c45";
-					reg = <15>;
-					phy-mode = "internal";
-				};
-			};
-		};
-
-		crypto: crypto@15600000 {
-			compatible = "inside-secure,safexcel-eip197b";
-			reg = <0 0x15600000 0 0x180000>;
-			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			status = "okay";
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&lvts 0>;
-
-			trips {
-				cpu_trip_crit: crit {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-
-				cpu_trip_hot: hot {
-					temperature = <120000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-high {
-				/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-low {
-				/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-passive {
-				/* passive: set fan to cooling level 0 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_low>;
-				};
-			};
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c
deleted file mode 100644
index 1647021de8..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-#define MT7981_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7981_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
-	    32, 0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
-	    0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
-	    0x0260, 4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027C, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
-	{ .compatible = "mediatek,mt7981-apmixedsys", },
-	{}
-};
-
-static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7981_apmixed_drv = {
-	.probe = clk_mt7981_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7981-apmixed",
-		.of_match_table = of_match_clk_mt7981_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7981_apmixed_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c
deleted file mode 100644
index 4aba657aa6..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
-	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xE4,
-	.clr_ofs = 0xE4,
-	.sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &sgmii1_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
-	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
-	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &eth_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c
deleted file mode 100644
index 8416829e35..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c
+++ /dev/null
@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-								"uart_sel" };
-
-static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
-							      "spi_sel" };
-
-static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
-							      "spim_mst_sel" };
-
-static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
-			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
-			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
-
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
-	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
-	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
-	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
-};
-
-static int clk_mt7981_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
-	{ .compatible = "mediatek,mt7981-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_infracfg_drv = {
-	.probe = clk_mt7981_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7981-infracfg",
-		.of_match_table = of_match_clk_mt7981_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7981_infracfg_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c
deleted file mode 100644
index ce6dc18672..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c
+++ /dev/null
@@ -1,450 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
-	FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
-	FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
-	FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
-	FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
-	FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
-	FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
-	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
-	FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
-	FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
-	FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
-	FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
-	FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
-	FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
-	FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
-	FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
-	FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
-	FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
-	FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
-	FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
-	FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
-	FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
-	FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
-	FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
-	FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
-	FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
-	FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
-	FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
-	FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
-	FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
-	FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
-	FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
-	FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
-	FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
-	FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
-	FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
-};
-
-static const char * const nfi1x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"cb_m_d8"
-};
-
-static const char * const spinfi_parents[] __initconst = {
-	"cksq_40m_d2",
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_mm_d8",
-	"net1_d8_d4",
-	"mm_d6_d2",
-	"cb_m_d8"
-};
-
-static const char * const spi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_net2_d6",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const uart_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d8",
-	"m_d8_d2"
-};
-
-static const char * const pwm_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"m_d8_d2",
-	"cb_rtc_32k"
-};
-
-static const char * const i2c_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"net1_d8_d4"
-};
-
-static const char * const pextp_tl_ck_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4",
-	"cb_m_d4",
-	"cb_rtc_32k"
-};
-
-static const char * const emmc_208m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_net2_d4",
-	"cb_apll2_196m",
-	"cb_mm_d4",
-	"net1_d8_d2",
-	"cb_mm_d6"
-};
-
-static const char * const emmc_400m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d2",
-	"cb_mm_d2",
-	"cb_net2_d2"
-};
-
-static const char * const csw_f26m_parents[] __initconst = {
-	"cksq_40m_d2",
-	"m_d8_d2"
-};
-
-static const char * const dramc_md32_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_m_d2",
-	"cb_wedmcu_208m"
-};
-
-static const char * const sysaxi_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d2"
-};
-
-static const char * const sysapb_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d3_d2"
-};
-
-static const char * const arm_db_main_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d6"
-};
-
-static const char * const ap2cnn_host_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d8_d4"
-};
-
-static const char * const netsys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d2"
-};
-
-static const char * const netsys_500m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5"
-};
-
-static const char * const netsys_mcu_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_720m",
-	"cb_net1_d4",
-	"cb_net1_d5",
-	"cb_m_416m"
-};
-
-static const char * const netsys_2x_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_800m",
-	"cb_mm_720m"
-};
-
-static const char * const sgm_325m_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_sgm_325m"
-};
-
-static const char * const sgm_reg_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net2_d4"
-};
-
-static const char * const eip97b_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_net1_d5",
-	"cb_m_416m",
-	"cb_mm_d2",
-	"net1_d5_d2"
-};
-
-static const char * const aud_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m"
-};
-
-static const char * const a1sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4"
-};
-
-static const char * const aud_l_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_apll2_196m",
-	"m_d8_d2"
-};
-
-static const char * const a_tuner_parents[] __initconst = {
-	"cb_cksq_40m",
-	"apll2_d4",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_parents[] __initconst = {
-	"cb_cksq_40m",
-	"m_d8_d2"
-};
-
-static const char * const u2u3_sys_parents[] __initconst = {
-	"cb_cksq_40m",
-	"net1_d5_d4"
-};
-
-static const char * const usb_frmcnt_parents[] __initconst = {
-	"cb_cksq_40m",
-	"cb_mm_d3_d5"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
-			     0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
-			     0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
-			     0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
-			     0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
-			     0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
-			     emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-				   0x1C0, 10,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
-				   31, 0x1C0, 11,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
-				   7, 0x1C0, 12,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
-				   0x1C0, 13,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
-				   23, 0x1C0, 14,
-				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
-			     0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
-			     0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
-			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
-			     7, 0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
-			     0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
-			     0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-};
-
-static struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
-		0x0420, 0, 0x0420, 8, 8),
-};
-
-static int clk_mt7981_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) +
-		 ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7981_clk_lock, clk_data);
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base,
-                        &mt7981_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
-	{ .compatible = "mediatek,mt7981-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7981_topckgen_drv = {
-	.probe = clk_mt7981_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7981-topckgen",
-		.of_match_table = of_match_clk_mt7981_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7981_topckgen_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c
deleted file mode 100644
index 76c8ebdeae..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-#define MT7986_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7986_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-		 _div_table, _parent_name)                                     \
-	{                                                                      \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-		.en_mask = _en_mask, .flags = _flags,                          \
-		.rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-		.parent_name = _parent_name,                                   \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-		 "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
-	    0x0200, 4, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-	    0x0210, 4, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-	    0x0220, 4, 0, 0x0224, 0),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
-	    0x0230, 4, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
-	    32, 0x0240, 4, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
-	    0x0250, 4, 0, 0x0254, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
-	    4, 0, 0x0264, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-	    0x0278, 4, 0, 0x027c, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
-	{ .compatible = "mediatek,mt7986-apmixedsys", },
-	{}
-};
-
-static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7986_apmixed_drv = {
-	.probe = clk_mt7986_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7986-apmixed",
-		.of_match_table = of_match_clk_mt7986_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7986_apmixed_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c
deleted file mode 100644
index ed2e7b2009..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
-	GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
-	GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
-	GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
-	GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
-	GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
-	GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift)                                  \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &eth_cg_regs, .shift = _shift,                         \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
-	}
-
-static const struct mtk_gate eth_clks[] __initconst = {
-	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
-	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
-	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
-	GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
-	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c
deleted file mode 100644
index 82279dfcf5..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c
+++ /dev/null
@@ -1,224 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
-	FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-							     "uart_sel" };
-
-static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
-							     "spi_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-			     infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-			     -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-			     -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra0_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra1_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-	{                                                                      \
-		.id = _id, .name = _name, .parent_name = _parent,              \
-		.regs = &infra2_cg_regs, .shift = _shift,                      \
-		.ops = &mtk_clk_gate_ops_setclr,                               \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
-	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
-	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
-	GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
-	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
-	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
-	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
-	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
-	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-		    14),
-	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
-	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
-	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
-	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-	GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
-	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
-	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
-	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
-		    10),
-	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
-		    13),
-	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
-		    14),
-	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
-	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
-		    17),
-	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
-		    18),
-	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
-		    19),
-	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
-	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
-	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
-		    1),
-	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
-	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
-	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
-	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
-		    13),
-	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
-	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
-};
-
-static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
-		 ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-
-}
-
-static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
-	{ .compatible = "mediatek,mt7986-infracfg", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_infracfg_drv = {
-	.probe = clk_mt7986_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7986-infracfg",
-		.of_match_table = of_match_clk_mt7986_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7986_infracfg_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c
deleted file mode 100644
index 8550e2be77..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c
+++ /dev/null
@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-	FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	/* XTAL */
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	/* MPLL */
-	FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
-	/* MMPLL */
-	FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
-	FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
-	/* APLL2 */
-	FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
-	/* NET1PLL */
-	FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
-	/* NET2PLL */
-	FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
-	FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
-	/* WEDMCUPLL */
-	FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
-	       10),
-};
-
-static const char *const nfi1x_parents[] __initconst = { "top_xtal",
-							 "top_mmpll_d8",
-							 "top_net1pll_d8_d2",
-							 "top_net2pll_d3_d2",
-							 "top_mpll_d4",
-							 "top_mmpll_d8_d2",
-							 "top_wedmcupll_d5_d2",
-							 "top_mpll_d8" };
-
-static const char *const spinfi_parents[] __initconst = {
-	"top_xtal_d2",     "top_xtal",	"top_net1pll_d5_d4",
-	"top_mpll_d4",     "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
-	"top_mmpll_d3_d8", "top_mpll_d8"
-};
-
-static const char *const spi_parents[] __initconst = {
-	"top_xtal",	  "top_mpll_d2",	"top_mmpll_d8",
-	"top_net1pll_d8_d2", "top_net2pll_d3_d2",  "top_net1pll_d5_d4",
-	"top_mpll_d4",       "top_wedmcupll_d5_d2"
-};
-
-static const char *const uart_parents[] __initconst = { "top_xtal",
-							"top_mpll_d8",
-							"top_mpll_d8_d2" };
-
-static const char *const pwm_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
-};
-
-static const char *const i2c_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
-};
-
-static const char *const pextp_tl_ck_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
-};
-
-static const char *const emmc_250m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d2"
-};
-
-static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
-							     "mpll" };
-
-static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
-							     "top_mpll_d8_d2" };
-
-static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
-							      "top_mpll_d2" };
-
-static const char *const sysaxi_parents[] __initconst = { "top_xtal",
-							  "top_net1pll_d8_d2",
-							  "top_net2pll_d4" };
-
-static const char *const sysapb_parents[] __initconst = { "top_xtal",
-							  "top_mpll_d3_d2",
-							  "top_net2pll_d4_d2" };
-
-static const char *const arm_db_main_parents[] __initconst = {
-	"top_xtal", "top_net2pll_d3_d2"
-};
-
-static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
-								"top_xtal" };
-
-static const char *const netsys_parents[] __initconst = { "top_xtal",
-							  "top_mmpll_d4" };
-
-static const char *const netsys_500m_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5"
-};
-
-static const char *const netsys_mcu_parents[] __initconst = {
-	"top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
-	"top_net1pll_d5"
-};
-
-static const char *const netsys_2x_parents[] __initconst = {
-	"top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
-};
-
-static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
-							    "sgmpll" };
-
-static const char *const sgm_reg_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d8_d4"
-};
-
-static const char *const a1sys_parents[] __initconst = { "top_xtal",
-							 "top_apll2_d4" };
-
-static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
-							       "top_mmpll_d2" };
-
-static const char *const eip_b_parents[] __initconst = { "top_xtal",
-							 "net2pll" };
-
-static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
-							 "top_mpll_d8_d2" };
-
-static const char *const a_tuner_parents[] __initconst = { "top_xtal",
-							   "top_apll2_d4",
-							   "top_mpll_d8_d2" };
-
-static const char *const u2u3_sys_parents[] __initconst = {
-	"top_xtal", "top_net1pll_d5_d4"
-};
-
-static const char *const da_u2_refsel_parents[] __initconst = {
-	"top_xtal", "top_mmpll_u2phy"
-};
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
-			     0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
-			     0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
-			     0x014, 0x018, 8, 2, 15, 0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
-			     0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
-			     31, 0x1C0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
-			     0x1C0, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
-			     emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
-			     0x1C0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
-			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
-			     0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-			     dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
-			     0x1C0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
-			     0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
-			     0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
-			     31, 0x1C0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
-			     arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-			     0x1C0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
-			     23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-			     0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-			     0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
-			     sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
-			     0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
-			     conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
-			     0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-			     f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
-			     0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-			     f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-			     a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
-			     0x1C0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
-			     0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-			     0x1C4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-			     u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
-			     0x1C4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
-			     23, 0x1C4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
-			     da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
-			     31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-			     sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
-			     0x1C4, 5),
-};
-
-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7986_clk_lock, clk_data);
-
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
-	clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
-	{ .compatible = "mediatek,mt7986-topckgen", },
-	{}
-};
-
-static struct platform_driver clk_mt7986_topckgen_drv = {
-	.probe = clk_mt7986_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7986-topckgen",
-		.of_match_table = of_match_clk_mt7986_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7986_topckgen_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c
deleted file mode 100644
index 587b70767e..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-#define MT7988_PLL_FMAX (2500UL * MHZ)
-#define MT7988_PCW_CHG_SHIFT 2
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg,           \
-		 _div_table)                                                  \
-	{                                                                     \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,   \
-		.en_mask = _en_mask, .flags = _flags,                         \
-		.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg,                       \
-		.pd_shift = _pd_shift, .tuner_reg = _tuner_reg,               \
-		.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
-		.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift,                 \
-		.pcw_chg_reg = _pcw_chg_reg,                                  \
-		.pcw_chg_shift = MT7988_PCW_CHG_SHIFT,                        \
-		.div_table = _div_table, .parent_name = "clkxtal",            \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,      \
-	    _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,          \
-	    _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg)                \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
-	    0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
-	    23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
-	    0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
-	    0x0154),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
-	    0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
-	    0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
-	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
-	    0x0204),
-	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
-	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
-	    32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
-};
-
-static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-	{
-		.compatible = "mediatek,mt7988-apmixedsys",
-	},
-	{}
-};
-
-static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7988_apmixed_drv = {
-	.probe = clk_mt7988_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7988-apmixed",
-		.of_match_table = of_match_clk_mt7988_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7988_apmixed_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c
deleted file mode 100644
index 341d0f73fd..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c
+++ /dev/null
@@ -1,299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static const struct mtk_gate_regs ethdma_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETHDMA(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethdma_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethdma_clks[] = {
-	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
-	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
-	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
-	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
-	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
-	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
-	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
-	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
-	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
-		    29),
-};
-
-static int clk_mt7988_ethsys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii0_clks[] = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
-};
-
-static int clk_mt7988_sgmii0_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii1_clks[] = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
-};
-
-static int clk_mt7988_sgmii1_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct mtk_gate_regs ethwarp_cg_regs = {
-	.set_ofs = 0x14,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x14,
-};
-
-#define GATE_ETHWARP(_id, _name, _parent, _shift)                             \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethwarp_cg_regs, .shift = _shift,                    \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethwarp_clks[] = {
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
-		     "netsys_mcu_sel", 13),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
-		     "netsys_mcu_sel", 14),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
-		     "netsys_mcu_sel", 15),
-};
-
-static int clk_mt7988_ethwarp_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks));
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_data;
-	}
-	return r;
-
-free_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_ethsys[] = {
-	{
-		.compatible = "mediatek,mt7988-ethsys",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_ethsys_drv = {
-	.probe = clk_mt7988_ethsys_probe,
-	.driver = {
-		.name = "clk-mt7988-ethsys",
-		.of_match_table = of_match_clk_mt7988_ethsys,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethsys_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii0[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_0",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_sgmii0_drv = {
-	.probe = clk_mt7988_sgmii0_probe,
-	.driver = {
-		.name = "clk-mt7988-sgmiisys_0",
-		.of_match_table = of_match_clk_mt7988_sgmii0,
-	},
-};
-builtin_platform_driver(clk_mt7988_sgmii0_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii1[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_1",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_sgmii1_drv = {
-	.probe = clk_mt7988_sgmii1_probe,
-	.driver = {
-		.name = "clk-mt7988-sgmiisys_1",
-		.of_match_table = of_match_clk_mt7988_sgmii1,
-	},
-};
-builtin_platform_driver(clk_mt7988_sgmii1_drv);
-
-static const struct of_device_id of_match_clk_mt7988_ethwarp[] = {
-	{
-		.compatible = "mediatek,mt7988-ethwarp",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_ethwarp_drv = {
-	.probe = clk_mt7988_ethwarp_probe,
-	.driver = {
-		.name = "clk-mt7988-ethwarp",
-		.of_match_table = of_match_clk_mt7988_ethwarp,
-	},
-};
-builtin_platform_driver(clk_mt7988_ethwarp_drv);
\ No newline at end of file
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c
deleted file mode 100644
index bce8d56375..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c
+++ /dev/null
@@ -1,406 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const char *const infra_mux_uart0_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart1_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart2_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
-								  "spi_sel" };
-
-static const char *const infra_mux_spi1_parents[] __initconst = {
-	"i2c_sel", "spim_mst_sel"
-};
-
-static const char *const infra_pwm_bck_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p1_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p2_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p3_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
-			     0, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
-			     1, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
-			     2, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
-			     infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
-			     "infra_pcie_gfmux_tl_o_p0_sel",
-			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
-			     0x0020, 0x0024, 0, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
-			     "infra_pcie_gfmux_tl_o_p1_sel",
-			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
-			     0x0020, 0x0024, 2, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
-			     "infra_pcie_gfmux_tl_o_p2_sel",
-			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
-			     0x0020, 0x0024, 4, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
-			     "infra_pcie_gfmux_tl_o_p3_sel",
-			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
-			     0x0020, 0x0024, 6, 2, -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x10,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x18,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra3_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra2_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra3_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                              \
-	GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                              \
-	GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                              \
-	GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA3(_id, _name, _parent, _shift)                              \
-	GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) {                   \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = _regs, .shift = _shift,                               \
-		.flags = CLK_IS_CRITICAL,                                     \
-		.ops = &mtk_clk_gate_ops_setclr,                              \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
-		    "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
-		    "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
-		    "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
-		    "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
-		    "sysaxi_sel", 0),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
-		    "sysaxi_sel", 1),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
-		    "infra_pwm_sel", 2),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
-		    "infra_pwm_ck1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
-		    "infra_pwm_ck2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
-		    "infra_pwm_ck3_sel", 5),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
-		    "infra_pwm_ck4_sel", 6),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
-		    "infra_pwm_ck5_sel", 7),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
-		    "infra_pwm_ck6_sel", 8),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
-		    "infra_pwm_ck7_sel", 9),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
-		    "infra_pwm_ck8_sel", 10),
-	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
-		    "sysaxi_sel", 12),
-	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
-		    "sysaxi_sel", 13),
-	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
-		    "csw_infra_f26m_sel", 14),
-	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
-	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
-	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
-	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
-			  "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
-	// JTAG
-	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
-			  "sysaxi_sel", 20, CLK_IS_CRITICAL),
-	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
-		    "sysaxi_sel", 21),
-	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
-		    "sysaxi_sel", 29),
-	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
-		    "csw_infra_f26m_sel", 30),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
-		    "csw_infra_f26m_sel", 0),
-	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
-	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
-		    "infra_mux_uart0_sel", 3),
-	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
-		    "infra_mux_uart1_sel", 4),
-	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
-		    "infra_mux_uart2_sel", 5),
-	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
-	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
-			  "sysaxi_sel", 11, CLK_IS_CRITICAL),
-	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
-			  "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
-		    "infra_mux_spi1_sel", 13),
-	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
-		    "infra_mux_spi2_sel", 14),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
-			  "sysaxi_sel", 15, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
-		    "sysaxi_sel", 16),
-	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
-		    "sysaxi_sel", 17),
-	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
-		    "sysaxi_sel", 18),
-	GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19),
-	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
-		    "csw_infra_f26m_sel", 20),
-	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
-		    21),
-	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
-		    22),
-	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
-		    23),
-	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
-		    "sysaxi_sel", 24),
-	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
-		    "sysaxi_sel", 25),
-	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
-		    "sysaxi_sel", 26),
-	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
-		    "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
-		    "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
-	/* INFRA3 */
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
-		    0),
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
-		    "sysaxi_sel", 1),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
-		    2),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
-		    "sysaxi_sel", 3),
-	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
-	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
-		    "usb_sys_p1_sel", 5),
-	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
-	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
-			  "usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
-			  "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
-		    "usb_phy_sel", 11),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
-		    "top_xtal", 13),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
-		    "usb_xhci_p1_sel", 15),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
-		    "top_xtal", 24),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
-		    "top_xtal", 25),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
-		    "top_xtal", 26),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
-		    "top_xtal", 27),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
-		    "sysaxi_sel", 28),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
-		    "sysaxi_sel", 29),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
-		    "sysaxi_sel", 30),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
-		    "sysaxi_sel", 31),
-};
-
-static int clk_mt7988_infracfg_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-			       clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_infracfg_data;
-	}
-	return r;
-
-free_infracfg_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-	{
-		.compatible = "mediatek,mt7988-infracfg",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_infracfg_drv = {
-	.probe = clk_mt7988_infracfg_probe,
-	.driver = {
-		.name = "clk-mt7988-infracfg",
-		.of_match_table = of_match_clk_mt7988_infracfg,
-	},
-};
-builtin_platform_driver(clk_mt7988_infracfg_drv);
diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c
deleted file mode 100644
index 917302b6df..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c
+++ /dev/null
@@ -1,522 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
-	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
-	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
-	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
-};
-
-static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
-					      "mmpll_d2" };
-
-static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
-						   "net1pll_d5_d2" };
-
-static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
-						 "mmpll" };
-
-static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
-						  "net1pll_d5" };
-
-static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
-
-static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",
-						  "mmpll",	"net1pll_d4",
-						  "net1pll_d5", "mpll" };
-
-static const char *const eip197_parents[] = { "top_xtal",   "netsyspll",
-					      "net2pll",    "mmpll",
-					      "net1pll_d4", "net1pll_d5" };
-
-static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
-
-static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
-					    "mpll_d8_d2" };
-
-static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
-						 "mmpll_d4" };
-
-static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
-						 "mmpll_d2", "mpll_d2",
-						 "mmpll_d4", "net1pll_d8_d2" };
-
-static const char *const spi_parents[] = { "top_xtal",	 "mpll_d2",
-					   "mmpll_d4",	 "net1pll_d8_d2",
-					   "net2pll_d6", "net1pll_d5_d4",
-					   "mpll_d4",	 "net1pll_d8_d4" };
-
-static const char *const nfi1x_parents[] = { "top_xtal",      "mmpll_d4",
-					     "net1pll_d8_d2", "net2pll_d6",
-					     "mpll_d4",	      "mmpll_d8",
-					     "net1pll_d8_d4", "mpll_d8" };
-
-static const char *const spinfi_parents[] = { "top_xtal_d2",   "top_xtal",
-					      "net1pll_d5_d4", "mpll_d4",
-					      "mmpll_d8",      "net1pll_d8_d4",
-					      "mmpll_d6_d2",   "mpll_d8" };
-
-static const char *const pwm_parents[] = { "top_xtal",	    "net1pll_d8_d2",
-					   "net1pll_d5_d4", "mpll_d4",
-					   "mpll_d8_d2",    "top_rtc_32k" };
-
-static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
-					   "mpll_d4", "net1pll_d8_d4" };
-
-static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
-						       "net1pll_d5_d2" };
-
-static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
-						   "mmpll_d8", "mpll_d8_d2",
-						   "top_rtc_32k" };
-
-static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
-
-static const char *const aud_parents[] = { "top_xtal", "apll2" };
-
-static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
-
-static const char *const aud_l_parents[] = { "top_xtal", "apll2",
-					     "mpll_d8_d2" };
-
-static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
-
-static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
-						      "net1pll_d8_d4" };
-
-static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
-
-static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
-
-static const char *const eth_refck_50m_parents[] = { "top_xtal",
-						     "net2pll_d4_d4" };
-
-static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
-
-static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
-						 "net1pll_d8_d8",
-						 "net1pll_d8_d16" };
-
-static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
-						"net2pll_d2" };
-
-static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
-
-static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
-						  "wedmcupll" };
-
-static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
-						     "net2pll_d8" };
-
-static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
-							  "net1pll_d4" };
-
-static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
-					      "net1pll_d8" };
-
-static const char *const netsys_tops_400m_parents[] = { "top_xtal",
-							"net2pll_d2" };
-
-static const char *const eth_mii_parents[] = { "top_xtal_d2",
-					       "net2pll_d4_d8" };
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
-			     15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
-			     0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
-			     netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
-			     31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
-			     eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
-			     0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
-			     0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
-			     23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
-			     0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
-				   axi_infra_parents, 0x020, 0x024, 0x028, 0,
-				   1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
-			     0x024, 0x028, 8, 2, 15, 0x1c0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
-			     0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
-			     0x034, 0x038, 0, 3, 7, 0x1c0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
-			     0x044, 0x048, 0, 3, 7, 0x1c0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
-			     0x044, 0x048, 8, 2, 15, 0x1c0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
-			     "pcie_mbist_250m_sel", pcie_mbist_250m_parents,
-			     0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
-			     pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
-			     31, 0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
-			     15, 0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
-			     23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
-			     eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
-			     0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
-			     0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
-			     31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
-			     usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1c0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
-			     0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
-			     0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
-			     sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
-			     0x1c4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
-			     1, 31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
-			     7, 0x1C4, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
-				   usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
-				   16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
-	/* CLK_CFG_10 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
-				   usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
-				   0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
-			     0x1C4, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
-			     0x1C4, 11),
-	/* CLK_CFG_11 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
-				   1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
-				   7, 0x1c4, 13, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
-			     eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
-			     15, 0x1C4, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
-			     eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
-			     23, 0x1C4, 15),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
-			     pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
-			     1, 31, 0x1C4, 16),
-	/* CLK_CFG_12 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
-			     eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
-			     0x1C4, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
-			     bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
-			     0x1C4, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
-			     npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
-			     0x1C4, 19),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
-				   31, 0x1C4, 20, CLK_IS_CRITICAL),
-	/* CLK_CFG_13 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
-				   2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(
-		CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-		0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
-			     0x1C4, 23),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
-			     0x1C4, 24),
-	/* CLK_CFG_14 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
-			     0x1C4, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
-			     0x1C4, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
-			     23, 0x1C4, 27),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
-			     31, 0x1C4, 28),
-	/* CLK_CFG_15 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
-			     7, 0x1C4, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
-			     15, 0x1C4, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
-			     0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
-			     0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
-	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
-			     0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
-			     sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
-			     0x1C8, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
-			     "mcusys_backup_625m_sel",
-			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
-			     16, 1, 23, 0x1C8, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
-			     "netsys_sync_250m_sel", pcie_mbist_250m_parents,
-			     0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
-	/* CLK_CFG_17 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
-			     0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
-			     "netsys_tops_400m_sel", netsys_tops_400m_parents,
-			     0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
-			     "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
-			     0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
-			     netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
-			     0x1C8, 9),
-	/* CLK_CFG_18 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
-			     eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
-			     0x1c8, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
-			     0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
-};
-
-static const struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
-		 8, 8),
-};
-
-static int clk_mt7988_topckgen_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-		 ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-				    clk_data);
-
-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-
-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-			       &mt7988_clk_lock, clk_data);
-
-	mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
-				    base, &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_topckgen_data;
-	}
-	return r;
-
-free_topckgen_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
-						   "net1pll_d4" };
-
-static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
-						   "net1pll_d4" };
-
-static struct mtk_composite mcu_muxes[] = {
-	/* bus_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
-		       mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
-	/* mp2_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
-		       mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
-};
-
-static int clk_mt7988_mcusys_probe(struct platform_device *pdev)
-{
-	struct clk_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-	void __iomem *base;
-	int nr = ARRAY_SIZE(mcu_muxes);
-
-	base = of_iomap(node, 0);
-	if (!base) {
-		pr_err("%s(): ioremap failed\n", __func__);
-		return -ENOMEM;
-	}
-
-	clk_data = mtk_alloc_clk_data(nr);
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
-				    &mt7988_clk_lock, clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_mcusys_data;
-	}
-	return r;
-
-free_mcusys_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-	{
-		.compatible = "mediatek,mt7988-topckgen",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_topckgen_drv = {
-	.probe = clk_mt7988_topckgen_probe,
-	.driver = {
-		.name = "clk-mt7988-topckgen",
-		.of_match_table = of_match_clk_mt7988_topckgen,
-	},
-};
-builtin_platform_driver(clk_mt7988_topckgen_drv);
-
-static const struct of_device_id of_match_clk_mt7988_mcusys[] = {
-	{
-		.compatible = "mediatek,mt7988-mcusys",
-	},
-	{}
-};
-
-static struct platform_driver clk_mt7988_mcusys_drv = {
-	.probe = clk_mt7988_mcusys_probe,
-	.driver = {
-		.name = "clk-mt7988-mcusys",
-		.of_match_table = of_match_clk_mt7988_mcusys,
-	},
-};
-builtin_platform_driver(clk_mt7988_mcusys_drv);
\ No newline at end of file
diff --git a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c
deleted file mode 100644
index c12e6b8eb6..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-#include <linux/bitfield.h>
-#include <linux/firmware.h>
-#include <linux/module.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/phy.h>
-
-#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
-#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
-
-#define MD32_EN_CFG			0x18
-#define   MD32_EN			BIT(0)
-
-#define BASE100T_STATUS_EXTEND		0x10
-#define BASE1000T_STATUS_EXTEND		0x11
-#define EXTEND_CTRL_AND_STATUS		0x16
-
-#define PHY_AUX_CTRL_STATUS		0x1d
-#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
-#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_LINK_STATUS_MISC	0xa2
-#define   MTK_PHY_FDX_ENABLE		BIT(5)
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL		0x24
-#define   MTK_PHY_LED0_ON_LINK1000	BIT(0)
-#define   MTK_PHY_LED0_ON_LINK100	BIT(1)
-#define   MTK_PHY_LED0_ON_LINK10	BIT(2)
-#define   MTK_PHY_LED0_ON_LINK2500	BIT(7)
-#define   MTK_PHY_LED0_POLARITY		BIT(14)
-
-#define MTK_PHY_LED1_ON_CTRL		0x26
-#define   MTK_PHY_LED1_ON_FDX		BIT(4)
-#define   MTK_PHY_LED1_ON_HDX		BIT(5)
-#define   MTK_PHY_LED1_POLARITY		BIT(14)
-
-enum {
-	PHY_AUX_SPD_10 = 0,
-	PHY_AUX_SPD_100,
-	PHY_AUX_SPD_1000,
-	PHY_AUX_SPD_2500,
-};
-
-static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
-{
-	int ret;
-	int i;
-	const struct firmware *fw;
-	struct device *dev = &phydev->mdio.dev;
-	struct device_node *np;
-	void __iomem *dmb_addr;
-	void __iomem *pmb_addr;
-	void __iomem *mcucsr_base;
-	u16 reg;
-	struct pinctrl *pinctrl;
-
-	np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
-	if (!np)
-		return -ENOENT;
-
-	dmb_addr = of_iomap(np, 0);
-	if (!dmb_addr)
-		return -ENOMEM;
-	pmb_addr = of_iomap(np, 1);
-	if (!pmb_addr)
-		return -ENOMEM;
-	mcucsr_base = of_iomap(np, 2);
-	if (!mcucsr_base)
-		return -ENOMEM;
-
-	ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDAITEK_2P5GE_PHY_DMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
-	release_firmware(fw);
-
-	ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDIATEK_2P5GE_PHY_PMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
-	release_firmware(fw);
-
-	reg = readw(mcucsr_base + MD32_EN_CFG);
-	writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
-	dev_dbg(dev, "Firmware loading/trigger ok.\n");
-
-	/* Setup LED */
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			   MTK_PHY_LED0_POLARITY);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			 MTK_PHY_LED0_ON_LINK10 |
-			 MTK_PHY_LED0_ON_LINK100 |
-			 MTK_PHY_LED0_ON_LINK1000 |
-			 MTK_PHY_LED0_ON_LINK2500);
-
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-			 MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
-
-	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
-	if (IS_ERR(pinctrl)) {
-		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
-		return PTR_ERR(pinctrl);
-	}
-
-	return 0;
-}
-
-static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
-{
-	bool changed = false;
-	u32 adv;
-	int ret;
-
-	if (phydev->autoneg == AUTONEG_DISABLE) {
-		/* Configure half duplex with genphy_setup_forced,
-		 * because genphy_c45_pma_setup_forced does not support.
-		 */
-		return phydev->duplex != DUPLEX_FULL
-			? genphy_setup_forced(phydev)
-			: genphy_c45_pma_setup_forced(phydev);
-	}
-
-	ret = genphy_c45_an_config_aneg(phydev);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
-	ret = phy_modify_changed(phydev, MII_CTRL1000,
-				 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
-				 adv);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	return genphy_c45_check_and_restart_aneg(phydev, changed);
-}
-
-static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_read_abilities(phydev);
-	if (ret)
-		return ret;
-
-	/* We don't support HDX at MAC layer on mt798x.
-	 * So mask phy's HDX capabilities, too.
-	 */
-	linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
-
-	return 0;
-}
-
-static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_update_link(phydev);
-	if (ret)
-		return ret;
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_UNKNOWN;
-	phydev->pause = 0;
-	phydev->asym_pause = 0;
-
-	if (!phydev->link)
-		return 0;
-
-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
-		ret = genphy_c45_read_lpa(phydev);
-		if (ret < 0)
-			return ret;
-
-		/* Read the link partner's 1G advertisement */
-		ret = phy_read(phydev, MII_STAT1000);
-		if (ret < 0)
-			return ret;
-		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
-	} else if (phydev->autoneg == AUTONEG_DISABLE) {
-		linkmode_zero(phydev->lp_advertising);
-	}
-
-	ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
-	if (ret < 0)
-		return ret;
-
-	switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
-	case PHY_AUX_SPD_10:
-		phydev->speed = SPEED_10;
-		break;
-	case PHY_AUX_SPD_100:
-		phydev->speed = SPEED_100;
-		break;
-	case PHY_AUX_SPD_1000:
-		phydev->speed = SPEED_1000;
-		break;
-	case PHY_AUX_SPD_2500:
-		phydev->speed = SPEED_2500;
-		phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
-		break;
-	}
-
-	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
-	if (ret < 0)
-		return ret;
-
-	phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
-
-	return 0;
-}
-
-static struct phy_driver mtk_gephy_driver[] = {
-	{
-		PHY_ID_MATCH_EXACT(0x00339c11),
-		.name		= "MediaTek MT798x 2.5GbE PHY",
-		.config_init	= mt798x_2p5ge_phy_config_init,
-		.config_aneg    = mt798x_2p5ge_phy_config_aneg,
-		.get_features	= mt798x_2p5ge_phy_get_features,
-		.read_status	= mt798x_2p5ge_phy_read_status,
-	},
-};
-
-module_phy_driver(mtk_gephy_driver);
-
-static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
-	{ PHY_ID_MATCH_VENDOR(0x00339c00) },
-	{ }
-};
-
-MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
-MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-MODULE_LICENSE("GPL");
-
-MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
-MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
-MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);
diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c
deleted file mode 100644
index 7c082dd207..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ /dev/null
@@ -1,1041 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7981 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7981_PIN(_number, _name)				\
-	MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-		      _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
-	PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
-	PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
-	PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
-	PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
-	PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
-	PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
-
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
-
-	PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
-
-	PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
-
-	PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
-
-	PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
-
-	PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
-};
-
-static const unsigned int mt7981_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
-	MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
-	MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
-	MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
-	MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
-	MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
-	MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
-	MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
-	MTK_PULL_PU_PD_TYPE,/*56*/
-};
-
-static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7981_pins[] = {
-	MT7981_PIN(0, "GPIO_WPS"),
-	MT7981_PIN(1, "GPIO_RESET"),
-	MT7981_PIN(2, "SYS_WATCHDOG"),
-	MT7981_PIN(3, "PCIE_PERESET_N"),
-	MT7981_PIN(4, "JTAG_JTDO"),
-	MT7981_PIN(5, "JTAG_JTDI"),
-	MT7981_PIN(6, "JTAG_JTMS"),
-	MT7981_PIN(7, "JTAG_JTCLK"),
-	MT7981_PIN(8, "JTAG_JTRST_N"),
-	MT7981_PIN(9, "WO_JTAG_JTDO"),
-	MT7981_PIN(10, "WO_JTAG_JTDI"),
-	MT7981_PIN(11, "WO_JTAG_JTMS"),
-	MT7981_PIN(12, "WO_JTAG_JTCLK"),
-	MT7981_PIN(13, "WO_JTAG_JTRST_N"),
-	MT7981_PIN(14, "USB_VBUS"),
-	MT7981_PIN(15, "PWM0"),
-	MT7981_PIN(16, "SPI0_CLK"),
-	MT7981_PIN(17, "SPI0_MOSI"),
-	MT7981_PIN(18, "SPI0_MISO"),
-	MT7981_PIN(19, "SPI0_CS"),
-	MT7981_PIN(20, "SPI0_HOLD"),
-	MT7981_PIN(21, "SPI0_WP"),
-	MT7981_PIN(22, "SPI1_CLK"),
-	MT7981_PIN(23, "SPI1_MOSI"),
-	MT7981_PIN(24, "SPI1_MISO"),
-	MT7981_PIN(25, "SPI1_CS"),
-	MT7981_PIN(26, "SPI2_CLK"),
-	MT7981_PIN(27, "SPI2_MOSI"),
-	MT7981_PIN(28, "SPI2_MISO"),
-	MT7981_PIN(29, "SPI2_CS"),
-	MT7981_PIN(30, "SPI2_HOLD"),
-	MT7981_PIN(31, "SPI2_WP"),
-	MT7981_PIN(32, "UART0_RXD"),
-	MT7981_PIN(33, "UART0_TXD"),
-	MT7981_PIN(34, "PCIE_CLK_REQ"),
-	MT7981_PIN(35, "PCIE_WAKE_N"),
-	MT7981_PIN(36, "SMI_MDC"),
-	MT7981_PIN(37, "SMI_MDIO"),
-	MT7981_PIN(38, "GBE_INT"),
-	MT7981_PIN(39, "GBE_RESET"),
-	MT7981_PIN(40, "WF_DIG_RESETB"),
-	MT7981_PIN(41, "WF_CBA_RESETB"),
-	MT7981_PIN(42, "WF_XO_REQ"),
-	MT7981_PIN(43, "WF_TOP_CLK"),
-	MT7981_PIN(44, "WF_TOP_DATA"),
-	MT7981_PIN(45, "WF_HB1"),
-	MT7981_PIN(46, "WF_HB2"),
-	MT7981_PIN(47, "WF_HB3"),
-	MT7981_PIN(48, "WF_HB4"),
-	MT7981_PIN(49, "WF_HB0"),
-	MT7981_PIN(50, "WF_HB0_B"),
-	MT7981_PIN(51, "WF_HB5"),
-	MT7981_PIN(52, "WF_HB6"),
-	MT7981_PIN(53, "WF_HB7"),
-	MT7981_PIN(54, "WF_HB8"),
-	MT7981_PIN(55, "WF_HB9"),
-	MT7981_PIN(56, "WF_HB10"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-/* WA_AICE */
-static int mt7981_wa_aice1_pins[] = { 0, 1, };
-static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wa_aice2_pins[] = { 0, 1, };
-static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-
-static int mt7981_wa_aice3_pins[] = { 28, 29, };
-static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-
-static int mt7981_wm_aice1_pins[] = { 9, 10, };
-static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wm_aice2_pins[] = { 30, 31, };
-static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-
-/* WM_UART */
-static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-
-static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-
-static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-
-/* DFD */
-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-
-/* SYS_WATCHDOG */
-static int mt7981_watchdog_pins[] = { 2, };
-static int mt7981_watchdog_funcs[] = { 1, };
-
-static int mt7981_watchdog1_pins[] = { 13, };
-static int mt7981_watchdog1_funcs[] = { 5, };
-
-/* PCIE_PERESET_N */
-static int mt7981_pcie_pereset_pins[] = { 3, };
-static int mt7981_pcie_pereset_funcs[] = { 1, };
-
-/* JTAG */
-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-
-/* WM_JTAG */
-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-
-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* WO0_JTAG */
-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-
-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* UART2 */
-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
-static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
-
-/* GBE_LED0 */
-static int mt7981_gbe_led0_pins[] = { 8, };
-static int mt7981_gbe_led0_funcs[] = { 3, };
-
-/* PTA_EXT */
-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-
-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-
-/* PWM2 */
-static int mt7981_pwm2_pins[] = { 7, };
-static int mt7981_pwm2_funcs[] = { 4, };
-
-/* NET_WO0_UART_TXD */
-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-
-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-
-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-
-/* SPI1 */
-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-
-/* I2C */
-static int mt7981_i2c0_0_pins[] = { 6, 7, };
-static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-
-static int mt7981_i2c0_1_pins[] = { 30, 31, };
-static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-
-static int mt7981_i2c0_2_pins[] = { 36, 37, };
-static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-
-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-
-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-
-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-
-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-
-/* DFD_NTRST */
-static int mt7981_dfd_ntrst_pins[] = { 8, };
-static int mt7981_dfd_ntrst_funcs[] = { 6, };
-
-/* PWM0 */
-static int mt7981_pwm0_0_pins[] = { 13, };
-static int mt7981_pwm0_0_funcs[] = { 2, };
-
-static int mt7981_pwm0_1_pins[] = { 15, };
-static int mt7981_pwm0_1_funcs[] = { 1, };
-
-/* PWM1 */
-static int mt7981_pwm1_0_pins[] = { 14, };
-static int mt7981_pwm1_0_funcs[] = { 2, };
-
-static int mt7981_pwm1_1_pins[] = { 15, };
-static int mt7981_pwm1_1_funcs[] = { 3, };
-
-/* GBE_LED1 */
-static int mt7981_gbe_led1_pins[] = { 13, };
-static int mt7981_gbe_led1_funcs[] = { 3, };
-
-/* PCM */
-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-
-/* UDI */
-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-
-/* DRV_VBUS */
-static int mt7981_drv_vbus_pins[] = { 14, };
-static int mt7981_drv_vbus_funcs[] = { 1, };
-
-/* EMMC */
-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-/* SNFI */
-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-
-/* SPI0 */
-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI0 */
-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-
-/* SPI1 */
-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-
-/* UART1 */
-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-
-static int mt7981_uart1_2_pins[] = { 9, 10, };
-static int mt7981_uart1_2_funcs[] = { 2, 2, };
-
-/* UART2 */
-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-/* UART0 */
-static int mt7981_uart0_pins[] = { 32, 33, };
-static int mt7981_uart0_funcs[] = { 1, 1, };
-
-/* PCIE_CLK_REQ */
-static int mt7981_pcie_clk_pins[] = { 34, };
-static int mt7981_pcie_clk_funcs[] = { 2, };
-
-/* PCIE_WAKE_N */
-static int mt7981_pcie_wake_pins[] = { 35, };
-static int mt7981_pcie_wake_funcs[] = { 2, };
-
-/* MDC_MDIO */
-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-
-/* WF0_MODE1 */
-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* WF0_MODE3 */
-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-/* WF2G_LED */
-static int mt7981_wf2g_led0_pins[] = { 30, };
-static int mt7981_wf2g_led0_funcs[] = { 2, };
-
-static int mt7981_wf2g_led1_pins[] = { 34, };
-static int mt7981_wf2g_led1_funcs[] = { 1, };
-
-/* WF5G_LED */
-static int mt7981_wf5g_led0_pins[] = { 31, };
-static int mt7981_wf5g_led0_funcs[] = { 2, };
-
-static int mt7981_wf5g_led1_pins[] = { 35, };
-static int mt7981_wf5g_led1_funcs[] = { 1, };
-
-/* MT7531_INT */
-static int mt7981_mt7531_int_pins[] = { 38, };
-static int mt7981_mt7531_int_funcs[] = { 1, };
-
-/* ANT_SEL */
-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-
-static const struct group_desc mt7981_groups[] = {
-	/* @GPIO(0,1): WA_AICE(2) */
-	PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
-	/* @GPIO(0,1): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
-	/* @GPIO(0,1): WM_UART(5) */
-	PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
-	/* @GPIO(0,1,4,5): DFD(6) */
-	PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
-	/* @GPIO(2): SYS_WATCHDOG(1) */
-	PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
-	/* @GPIO(3): PCIE_PERESET_N(1) */
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
-	/* @GPIO(4,8) JTAG(1) */
-	PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
-	/* @GPIO(4,8) WM_JTAG(2) */
-	PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
-	/* @GPIO(9,13) WO0_JTAG(1) */
-	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
-	/* @GPIO(4,7) WM_JTAG(3) */
-	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-	/* @GPIO(4,5) WM_JTAG(4) */
-	PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
-	/* @GPIO(8) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
-	/* @GPIO(4,6) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
-	/* @GPIO(7) PWM2(4) */
-	PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
-	/* @GPIO(8) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
-	/* @GPIO(4,7) SPI1(5) */
-	PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
-	/* @GPIO(6,7) I2C(5) */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
-	/* @GPIO(0,1,4,5): DFD_NTRST(6) */
-	PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
-	/* @GPIO(9,10): WM_AICE(2) */
-	PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
-	/* @GPIO(13): PWM0(2) */
-	PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
-	/* @GPIO(15): PWM0(1) */
-	PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
-	/* @GPIO(14): PWM1(2) */
-	PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
-	/* @GPIO(15): PWM1(3) */
-	PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
-	/* @GPIO(14) NET_WO0_UART_TXD(3) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
-	/* @GPIO(15) NET_WO0_UART_TXD(4) */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
-	/* @GPIO(13) GBE_LED0(3) */
-	PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
-	/* @GPIO(9,13) PCM(4) */
-	PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
-	/* @GPIO(13): SYS_WATCHDOG1(5) */
-	PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
-	/* @GPIO(9,13) UDI(4) */
-	PINCTRL_PIN_GROUP("udi", mt7981_udi),
-	/* @GPIO(14) DRV_VBUS(1) */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-	/* @GPIO(15,25): EMMC(2) */
-	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
-	/* @GPIO(16,21): SNFI(3) */
-	PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
-	/* @GPIO(16,19): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
-	/* @GPIO(20,21): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
-	/* @GPIO(22,25) SPI1(1) */
-	PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
-	/* @GPIO(26,29): SPI2(1) */
-	PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
-	/* @GPIO(30,31): SPI0(1) */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
-	/* @GPIO(16,19): UART1(4) */
-	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
-	/* @GPIO(26,29): UART1(2) */
-	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-	/* @GPIO(9,10): UART1(2) */
-	PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
-	/* @GPIO(22,25): UART1(3) */
-	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
-	/* @GPIO(22,24) PTA_EXT(4) */
-	PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
-	/* @GPIO(20,21): WM_UART(4) */
-	PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
-	/* @GPIO(30,31): WM_UART(3) */
-	PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
-	/* @GPIO(20,24) WM_JTAG(5) */
-	PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
-	/* @GPIO(25,29) WO0_JTAG(5) */
-	PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
-	/* @GPIO(28,29): WA_AICE(3) */
-	PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
-	/* @GPIO(30,31): WM_AICE(5) */
-	PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
-	/* @GPIO(30,31): I2C(4) */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
-	/* @GPIO(30,31): I2C(6) */
-	PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
-	/* @GPIO(32,33): I2C(1) */
-	PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
-	/* @GPIO(32,33): I2C(2) */
-	PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
-	/* @GPIO(32,33): I2C(3) */
-	PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
-	/* @GPIO(32,33): I2C(5) */
-	PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
-	/* @GPIO(34): PCIE_CLK_REQ(2) */
-	PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
-	/* @GPIO(35): PCIE_WAKE_N(2) */
-	PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
-	/* @GPIO(36,37): I2C(2) */
-	PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
-	/* @GPIO(36,37): MDC_MDIO(1) */
-	PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
-	/* @GPIO(36,37): MDC_MDIO(3) */
-	PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
-	/* @GPIO(69,85): WF0_MODE1(1) */
-	PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
-	/* @GPIO(74,80): WF0_MODE3(3) */
-	PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
-	/* @GPIO(30): WF2G_LED(2) */
-	PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
-	/* @GPIO(34): WF2G_LED(1) */
-	PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
-	/* @GPIO(31): WF5G_LED(2) */
-	PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
-	/* @GPIO(35): WF5G_LED(1) */
-	PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
-	/* @GPIO(38): MT7531_INT(1) */
-	PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
-	/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
-	PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
-	"wa_aice3", "wm_aice1_2", };
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
-	"uart1_2", "uart2_0_tx_rx",
-	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
-	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
-static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
-static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
-static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
-	"wo0_jtag_1", "wm_jtag_1", };
-static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
-	"wf2g_led1", "wf5g_led0", "wf5g_led1", };
-static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
-static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
-	"pwm1_0", "pwm1_1", };
-static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
-	"spi2_wp_hold", };
-static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
-	"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
-static const char *mt7981_pcm_groups[] = { "pcm", };
-static const char *mt7981_udi_groups[] = { "udi", };
-static const char *mt7981_usb_groups[] = { "drv_vbus", };
-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
-	"wf0_mode1", "wf0_mode3", "mt7531_int", };
-static const char *mt7981_ant_groups[] = { "ant_sel", };
-
-static const struct function_desc mt7981_functions[] = {
-	{"wa_aice",	mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
-	{"dfd",	mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
-	{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
-	{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
-	{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
-	{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
-	{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
-	{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
-	{"eth",	mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
-	{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
-	{"led",	mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
-	{"pwm",	mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
-	{"spi",	mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
-	{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
-	{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
-	{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
-	{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
-};
-
-static const struct mtk_eint_hw mt7981_eint_hw = {
-	.port_mask = 7,
-	.ports     = 7,
-	.ap_num    = ARRAY_SIZE(mt7981_pins),
-	.db_cnt    = 16,
-};
-
-static const char * const mt7981_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
-	"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
-};
-
-static struct mtk_pin_soc mt7981_data = {
-	.reg_cal = mt7981_reg_cals,
-	.pins = mt7981_pins,
-	.npins = ARRAY_SIZE(mt7981_pins),
-	.grps = mt7981_groups,
-	.ngrps = ARRAY_SIZE(mt7981_groups),
-	.funcs = mt7981_functions,
-	.nfuncs = ARRAY_SIZE(mt7981_functions),
-	.eint_hw = &mt7981_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7981_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7981_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7981_pinctrl_of_match[] = {
-	{ .compatible = "mediatek,mt7981-pinctrl", },
-	{}
-};
-
-static int mt7981_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
-}
-
-static struct platform_driver mt7981_pinctrl_driver = {
-	.driver = {
-		.name = "mt7981-pinctrl",
-		.of_match_table = mt7981_pinctrl_of_match,
-	},
-	.probe = mt7981_pinctrl_probe,
-};
-
-static int __init mt7981_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7981_pinctrl_driver);
-}
-arch_initcall(mt7981_pinctrl_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c
deleted file mode 100644
index acaac9b38a..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+++ /dev/null
@@ -1,1011 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7986 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL }
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits)	\
-		PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-			_x_bits, 32, 0)
-
-/**
- * enum - Locking variants of the iocfg bases
- *
- * MT7986 have multiple bases to program pin configuration listed as the below:
- * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
- * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
- * _i_based could be used to indicate what base the pin should be mapped into.
- *
- * Each iocfg register base control different group of pads on the SoC
- *
- *
- *  chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 | o  o  o  o  o  o  o  o |
- *  7 | o  o  o  o  o  o  o  o |
- *  6 | o  o  o  o  o  o  o  o |
- *  5 | o  o  o  o  o  o  o  o |
- *  4 | o  o  o  o  o  o  o  o |
- *  3 | o  o  o  o  o  o  o  o |
- *  2 | o  o  o  o  o  o  o  o |
- *  1 | o  o  o  o  o  o  o  o |
- *    +------------------------+
- *
- *  inside Chip carrier
- *
- *      A  B  C  D  E  F  G  H
- *    +------------------------+
- *  8 |                        |
- *  7 |        TL  TR          |
- *  6 |      +---------+       |
- *  5 |   LT |         | RT    |
- *  4 |      |         |       |
- *  3 |   LB |         | RB    |
- *  2 |      +---------+       |
- *  1 |                        |
- *    +------------------------+
- *
- */
-
-enum {
-	GPIO_BASE,
-	IOCFG_RT_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LT_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_TL_BASE,
-};
-
-static const char *const mt7986_pinctrl_register_base_names[] = {
-	"gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
-	"iocfg_tl",
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
-	PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
-	PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
-	PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
-	PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
-	PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
-	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
-	PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
-	PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
-	PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
-	PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
-	PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
-	PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
-	PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
-	PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
-	PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
-	PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
-	PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
-	PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
-};
-
-static const unsigned int mt7986_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-	MTK_PULL_PU_PD_TYPE,/*100*/
-};
-
-static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7986a_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_PIN(41, "PCIE_PERESET_N"),
-	MT7986_PIN(42, "UART1_RXD"),
-	MT7986_PIN(43, "UART1_TXD"),
-	MT7986_PIN(44, "UART1_CTS"),
-	MT7986_PIN(45, "UART1_RTS"),
-	MT7986_PIN(46, "UART2_RXD"),
-	MT7986_PIN(47, "UART2_TXD"),
-	MT7986_PIN(48, "UART2_CTS"),
-	MT7986_PIN(49, "UART2_RTS"),
-	MT7986_PIN(50, "EMMC_DATA_0"),
-	MT7986_PIN(51, "EMMC_DATA_1"),
-	MT7986_PIN(52, "EMMC_DATA_2"),
-	MT7986_PIN(53, "EMMC_DATA_3"),
-	MT7986_PIN(54, "EMMC_DATA_4"),
-	MT7986_PIN(55, "EMMC_DATA_5"),
-	MT7986_PIN(56, "EMMC_DATA_6"),
-	MT7986_PIN(57, "EMMC_DATA_7"),
-	MT7986_PIN(58, "EMMC_CMD"),
-	MT7986_PIN(59, "EMMC_CK"),
-	MT7986_PIN(60, "EMMC_DSL"),
-	MT7986_PIN(61, "EMMC_RSTB"),
-	MT7986_PIN(62, "PCM_DTX"),
-	MT7986_PIN(63, "PCM_DRX"),
-	MT7986_PIN(64, "PCM_CLK"),
-	MT7986_PIN(65, "PCM_FS"),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-static const struct mtk_pin_desc mt7986b_pins[] = {
-	MT7986_PIN(0, "SYS_WATCHDOG"),
-	MT7986_PIN(1, "WF2G_LED"),
-	MT7986_PIN(2, "WF5G_LED"),
-	MT7986_PIN(3, "I2C_SCL"),
-	MT7986_PIN(4, "I2C_SDA"),
-	MT7986_PIN(5, "GPIO_0"),
-	MT7986_PIN(6, "GPIO_1"),
-	MT7986_PIN(7, "GPIO_2"),
-	MT7986_PIN(8, "GPIO_3"),
-	MT7986_PIN(9, "GPIO_4"),
-	MT7986_PIN(10, "GPIO_5"),
-	MT7986_PIN(11, "GPIO_6"),
-	MT7986_PIN(12, "GPIO_7"),
-	MT7986_PIN(13, "GPIO_8"),
-	MT7986_PIN(14, "GPIO_9"),
-	MT7986_PIN(15, "GPIO_10"),
-	MT7986_PIN(16, "GPIO_11"),
-	MT7986_PIN(17, "GPIO_12"),
-	MT7986_PIN(18, "GPIO_13"),
-	MT7986_PIN(19, "GPIO_14"),
-	MT7986_PIN(20, "GPIO_15"),
-	MT7986_PIN(21, "PWM0"),
-	MT7986_PIN(22, "PWM1"),
-	MT7986_PIN(23, "SPI0_CLK"),
-	MT7986_PIN(24, "SPI0_MOSI"),
-	MT7986_PIN(25, "SPI0_MISO"),
-	MT7986_PIN(26, "SPI0_CS"),
-	MT7986_PIN(27, "SPI0_HOLD"),
-	MT7986_PIN(28, "SPI0_WP"),
-	MT7986_PIN(29, "SPI1_CLK"),
-	MT7986_PIN(30, "SPI1_MOSI"),
-	MT7986_PIN(31, "SPI1_MISO"),
-	MT7986_PIN(32, "SPI1_CS"),
-	MT7986_PIN(33, "SPI2_CLK"),
-	MT7986_PIN(34, "SPI2_MOSI"),
-	MT7986_PIN(35, "SPI2_MISO"),
-	MT7986_PIN(36, "SPI2_CS"),
-	MT7986_PIN(37, "SPI2_HOLD"),
-	MT7986_PIN(38, "SPI2_WP"),
-	MT7986_PIN(39, "UART0_RXD"),
-	MT7986_PIN(40, "UART0_TXD"),
-	MT7986_NOT_BALLOUT_PIN(41),
-	MT7986_NOT_BALLOUT_PIN(42),
-	MT7986_NOT_BALLOUT_PIN(43),
-	MT7986_NOT_BALLOUT_PIN(44),
-	MT7986_NOT_BALLOUT_PIN(45),
-	MT7986_NOT_BALLOUT_PIN(46),
-	MT7986_NOT_BALLOUT_PIN(47),
-	MT7986_NOT_BALLOUT_PIN(48),
-	MT7986_NOT_BALLOUT_PIN(49),
-	MT7986_NOT_BALLOUT_PIN(50),
-	MT7986_NOT_BALLOUT_PIN(51),
-	MT7986_NOT_BALLOUT_PIN(52),
-	MT7986_NOT_BALLOUT_PIN(53),
-	MT7986_NOT_BALLOUT_PIN(54),
-	MT7986_NOT_BALLOUT_PIN(55),
-	MT7986_NOT_BALLOUT_PIN(56),
-	MT7986_NOT_BALLOUT_PIN(57),
-	MT7986_NOT_BALLOUT_PIN(58),
-	MT7986_NOT_BALLOUT_PIN(59),
-	MT7986_NOT_BALLOUT_PIN(60),
-	MT7986_NOT_BALLOUT_PIN(61),
-	MT7986_NOT_BALLOUT_PIN(62),
-	MT7986_NOT_BALLOUT_PIN(63),
-	MT7986_NOT_BALLOUT_PIN(64),
-	MT7986_NOT_BALLOUT_PIN(65),
-	MT7986_PIN(66, "MT7531_INT"),
-	MT7986_PIN(67, "SMI_MDC"),
-	MT7986_PIN(68, "SMI_MDIO"),
-	MT7986_PIN(69, "WF0_DIG_RESETB"),
-	MT7986_PIN(70, "WF0_CBA_RESETB"),
-	MT7986_PIN(71, "WF0_XO_REQ"),
-	MT7986_PIN(72, "WF0_TOP_CLK"),
-	MT7986_PIN(73, "WF0_TOP_DATA"),
-	MT7986_PIN(74, "WF0_HB1"),
-	MT7986_PIN(75, "WF0_HB2"),
-	MT7986_PIN(76, "WF0_HB3"),
-	MT7986_PIN(77, "WF0_HB4"),
-	MT7986_PIN(78, "WF0_HB0"),
-	MT7986_PIN(79, "WF0_HB0_B"),
-	MT7986_PIN(80, "WF0_HB5"),
-	MT7986_PIN(81, "WF0_HB6"),
-	MT7986_PIN(82, "WF0_HB7"),
-	MT7986_PIN(83, "WF0_HB8"),
-	MT7986_PIN(84, "WF0_HB9"),
-	MT7986_PIN(85, "WF0_HB10"),
-	MT7986_PIN(86, "WF1_DIG_RESETB"),
-	MT7986_PIN(87, "WF1_CBA_RESETB"),
-	MT7986_PIN(88, "WF1_XO_REQ"),
-	MT7986_PIN(89, "WF1_TOP_CLK"),
-	MT7986_PIN(90, "WF1_TOP_DATA"),
-	MT7986_PIN(91, "WF1_HB1"),
-	MT7986_PIN(92, "WF1_HB2"),
-	MT7986_PIN(93, "WF1_HB3"),
-	MT7986_PIN(94, "WF1_HB4"),
-	MT7986_PIN(95, "WF1_HB0"),
-	MT7986_PIN(96, "WF1_HB0_B"),
-	MT7986_PIN(97, "WF1_HB5"),
-	MT7986_PIN(98, "WF1_HB6"),
-	MT7986_PIN(99, "WF1_HB7"),
-	MT7986_PIN(100, "WF1_HB8"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-static int mt7986_watchdog_pins[] = { 0, };
-static int mt7986_watchdog_funcs[] = { 1, };
-
-static int mt7986_wifi_led_pins[] = { 1, 2, };
-static int mt7986_wifi_led_funcs[] = { 1, 1, };
-
-static int mt7986_i2c_pins[] = { 3, 4, };
-static int mt7986_i2c_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_pwm1_1_pins[] = { 20, };
-static int mt7986_pwm1_1_funcs[] = { 2, };
-
-static int mt7986_pwm0_pins[] = { 21, };
-static int mt7986_pwm0_funcs[] = { 1, };
-
-static int mt7986_pwm1_0_pins[] = { 22, };
-static int mt7986_pwm1_0_funcs[] = { 1, };
-
-static int mt7986_emmc_45_pins[] = {
-	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
-
-static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
-
-static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
-
-static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
-
-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-
-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-
-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_uart0_pins[] = { 39, 40, };
-static int mt7986_uart0_funcs[] = { 1, 1, };
-
-static int mt7986_pcie_reset_pins[] = { 41, };
-static int mt7986_pcie_reset_funcs[] = { 1, };
-
-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
-static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
-static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_emmc_51_pins[] = {
-	50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_switch_int_pins[] = { 66, };
-static int mt7986_switch_int_funcs[] = { 1, };
-
-static int mt7986_mdc_mdio_pins[] = { 67, 68, };
-static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_dbdc_pins[] = {
-	74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
-static int mt7986_wf_dbdc_funcs[] = {
-	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_pcie_clk_pins[] = { 9, };
-static int mt7986_pcie_clk_funcs[] = { 1, };
-
-static int mt7986_pcie_wake_pins[] = { 10, };
-static int mt7986_pcie_wake_funcs[] = { 1, };
-
-static const struct group_desc mt7986_groups[] = {
-	PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
-	PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
-	PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
-	PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
-	PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
-	PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
-	PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
-	PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
-	PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
-	PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
-	PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
-	PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
-	PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
-	PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
-	PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
-	PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
-	PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
-	PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
-	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
-	PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
-	PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
-	PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
-	PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
-	PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
-	PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
-	PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
-	PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
-	PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
-	PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
-	PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
-	PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
-	PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
-	PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
-	PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
-	PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
-	PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-
-static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
-static const char *mt7986_emmc_groups[] = {
-	"emmc_45", "emmc_51", };
-static const char *mt7986_ethernet_groups[] = {
-	"switch_int", "mdc_mdio", };
-static const char *mt7986_i2c_groups[] = { "i2c", };
-static const char *mt7986_led_groups[] = { "wifi_led", };
-static const char *mt7986_flash_groups[] = { "snfi", };
-static const char *mt7986_pcie_groups[] = {
-	"pcie_clk", "pcie_wake", "pcie_pereset" };
-static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
-static const char *mt7986_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
-static const char *mt7986_uart_groups[] = {
-	"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
-	"uart1_2_rx_tx", "uart1_2_cts_rts",
-	"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
-	"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
-};
-static const char *mt7986_wdt_groups[] = { "watchdog", };
-static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
-
-static const struct function_desc mt7986_functions[] = {
-	{"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
-	{"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
-	{"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
-	{"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
-	{"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
-	{"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
-	{"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
-	{"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
-	{"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
-	{"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
-	{"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
-	{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
-};
-
-static const struct mtk_eint_hw mt7986a_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986a_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static const struct mtk_eint_hw mt7986b_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7986b_pins),
-	.db_cnt = 16,
-	.db_time = debounce_time_mt6765,
-};
-
-static struct mtk_pin_soc mt7986a_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986a_pins,
-	.npins = ARRAY_SIZE(mt7986a_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986a_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static struct mtk_pin_soc mt7986b_data = {
-	.reg_cal = mt7986_reg_cals,
-	.pins = mt7986b_pins,
-	.npins = ARRAY_SIZE(mt7986b_pins),
-	.grps = mt7986_groups,
-	.ngrps = ARRAY_SIZE(mt7986_groups),
-	.funcs = mt7986_functions,
-	.nfuncs = ARRAY_SIZE(mt7986_functions),
-	.eint_hw = &mt7986b_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7986_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7986_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7986a_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986a-pinctrl",},
-	{}
-};
-
-static const struct of_device_id mt7986b_pinctrl_of_match[] = {
-	{.compatible = "mediatek,mt7986b-pinctrl",},
-	{}
-};
-
-static int mt7986a_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
-}
-
-static int mt7986b_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
-}
-
-static struct platform_driver mt7986a_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986a-pinctrl",
-		.of_match_table = mt7986a_pinctrl_of_match,
-	},
-	.probe = mt7986a_pinctrl_probe,
-};
-
-static struct platform_driver mt7986b_pinctrl_driver = {
-	.driver = {
-		.name = "mt7986b-pinctrl",
-		.of_match_table = mt7986b_pinctrl_of_match,
-	},
-	.probe = mt7986b_pinctrl_probe,
-};
-
-static int __init mt7986a_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986a_pinctrl_driver);
-}
-
-static int __init mt7986b_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7986b_pinctrl_driver);
-}
-
-arch_initcall(mt7986a_pinctrl_init);
-arch_initcall(mt7986b_pinctrl_init);
diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c
deleted file mode 100644
index 659c83e997..0000000000
--- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ /dev/null
@@ -1,1466 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7988 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-enum MT7988_PINCTRL_REG_PAGE {
-	GPIO_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_BR_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TL_BASE,
-};
-
-#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits)                                                \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
-			_x_bits)                                               \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
-	PIN_FIELD(0, 83, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
-	PIN_FIELD(0, 83, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
-	PIN_FIELD(0, 83, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
-	PIN_FIELD(0, 83, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
-	PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
-	PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
-	PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
-	PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
-	PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3),
-	PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3),
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7988_pins[] = {
-	MT7988_PIN(0, "UART2_RXD"),
-	MT7988_PIN(1, "UART2_TXD"),
-	MT7988_PIN(2, "UART2_CTS"),
-	MT7988_PIN(3, "UART2_RTS"),
-	MT7988_PIN(4, "GPIO_A"),
-	MT7988_PIN(5, "SMI_0_MDC"),
-	MT7988_PIN(6, "SMI_0_MDIO"),
-	MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"),
-	MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
-	MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"),
-	MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
-	MT7988_PIN(11, "GPIO_P"),
-	MT7988_PIN(12, "WATCHDOG"),
-	MT7988_PIN(13, "GPIO_RESET"),
-	MT7988_PIN(14, "GPIO_WPS"),
-	MT7988_PIN(15, "PMIC_I2C_SCL"),
-	MT7988_PIN(16, "PMIC_I2C_SDA"),
-	MT7988_PIN(17, "I2C_1_SCL"),
-	MT7988_PIN(18, "I2C_1_SDA"),
-	MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"),
-	MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"),
-	MT7988_PIN(21, "PWMD1"),
-	MT7988_PIN(22, "SPI0_WP"),
-	MT7988_PIN(23, "SPI0_HOLD"),
-	MT7988_PIN(24, "SPI0_CSB"),
-	MT7988_PIN(25, "SPI0_MISO"),
-	MT7988_PIN(26, "SPI0_MOSI"),
-	MT7988_PIN(27, "SPI0_CLK"),
-	MT7988_PIN(28, "SPI1_CSB"),
-	MT7988_PIN(29, "SPI1_MISO"),
-	MT7988_PIN(30, "SPI1_MOSI"),
-	MT7988_PIN(31, "SPI1_CLK"),
-	MT7988_PIN(32, "SPI2_CLK"),
-	MT7988_PIN(33, "SPI2_MOSI"),
-	MT7988_PIN(34, "SPI2_MISO"),
-	MT7988_PIN(35, "SPI2_CSB"),
-	MT7988_PIN(36, "SPI2_HOLD"),
-	MT7988_PIN(37, "SPI2_WP"),
-	MT7988_PIN(38, "EMMC_RSTB"),
-	MT7988_PIN(39, "EMMC_DSL"),
-	MT7988_PIN(40, "EMMC_CK"),
-	MT7988_PIN(41, "EMMC_CMD"),
-	MT7988_PIN(42, "EMMC_DATA_7"),
-	MT7988_PIN(43, "EMMC_DATA_6"),
-	MT7988_PIN(44, "EMMC_DATA_5"),
-	MT7988_PIN(45, "EMMC_DATA_4"),
-	MT7988_PIN(46, "EMMC_DATA_3"),
-	MT7988_PIN(47, "EMMC_DATA_2"),
-	MT7988_PIN(48, "EMMC_DATA_1"),
-	MT7988_PIN(49, "EMMC_DATA_0"),
-	MT7988_PIN(50, "PCM_FS_I2S_LRCK"),
-	MT7988_PIN(51, "PCM_CLK_I2S_BCLK"),
-	MT7988_PIN(52, "PCM_DRX_I2S_DIN"),
-	MT7988_PIN(53, "PCM_DTX_I2S_DOUT"),
-	MT7988_PIN(54, "PCM_MCK_I2S_MCLK"),
-	MT7988_PIN(55, "UART0_RXD"),
-	MT7988_PIN(56, "UART0_TXD"),
-	MT7988_PIN(57, "PWMD0"),
-	MT7988_PIN(58, "JTAG_JTDI"),
-	MT7988_PIN(59, "JTAG_JTDO"),
-	MT7988_PIN(60, "JTAG_JTMS"),
-	MT7988_PIN(61, "JTAG_JTCLK"),
-	MT7988_PIN(62, "JTAG_JTRST_N"),
-	MT7988_PIN(63, "USB_DRV_VBUS_P1"),
-	MT7988_PIN(64, "LED_A"),
-	MT7988_PIN(65, "LED_B"),
-	MT7988_PIN(66, "LED_C"),
-	MT7988_PIN(67, "LED_D"),
-	MT7988_PIN(68, "LED_E"),
-	MT7988_PIN(69, "GPIO_B"),
-	MT7988_PIN(70, "GPIO_C"),
-	MT7988_PIN(71, "I2C_2_SCL"),
-	MT7988_PIN(72, "I2C_2_SDA"),
-	MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"),
-	MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"),
-	MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"),
-	MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
-	MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"),
-	MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
-	MT7988_PIN(79, "USB_DRV_VBUS_P0"),
-	MT7988_PIN(80, "UART1_RXD"),
-	MT7988_PIN(81, "UART1_TXD"),
-	MT7988_PIN(82, "UART1_CTS"),
-	MT7988_PIN(83, "UART1_RTS"),
-};
-
-/* jtag */
-static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
-
-static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
-
-static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
-
-static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
-
-static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
-
-static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* int_usxgmii */
-static int mt7988_int_usxgmii_pins[] = { 2, 3 };
-static int mt7988_int_usxgmii_funcs[] = { 3, 3 };
-
-/* pwm */
-static int mt7988_pwm0_pins[] = { 57 };
-static int mt7988_pwm0_funcs[] = { 1 };
-
-static int mt7988_pwm1_pins[] = { 21 };
-static int mt7988_pwm1_funcs[] = { 1 };
-
-static int mt7988_pwm2_pins[] = { 80 };
-static int mt7988_pwm2_funcs[] = { 2 };
-
-static int mt7988_pwm3_pins[] = { 81 };
-static int mt7988_pwm3_funcs[] = { 2 };
-
-static int mt7988_pwm4_pins[] = { 82 };
-static int mt7988_pwm4_funcs[] = { 2 };
-
-static int mt7988_pwm5_pins[] = { 83 };
-static int mt7988_pwm5_funcs[] = { 2 };
-
-static int mt7988_pwm6_pins[] = { 69 };
-static int mt7988_pwm6_funcs[] = { 3 };
-
-static int mt7988_pwm7_pins[] = { 70 };
-static int mt7988_pwm7_funcs[] = { 3 };
-
-/* dfd */
-static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2c */
-static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_0_pins[] = { 5, 6 };
-static int mt7988_i2c0_0_funcs[] = { 2, 2 };
-
-static int mt7988_i2c1_sfp_pins[] = { 5, 6 };
-static int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
-
-static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_1_pins[] = { 15, 16 };
-static int mt7988_i2c0_1_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
-static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
-
-static int mt7988_i2c1_0_pins[] = { 17, 18 };
-static int mt7988_i2c1_0_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
-static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
-
-static int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c1_2_pins[] = { 69, 70 };
-static int mt7988_i2c1_2_funcs[] = { 2, 2 };
-
-static int mt7988_i2c2_0_pins[] = { 69, 70 };
-static int mt7988_i2c2_0_funcs[] = { 4, 4 };
-
-static int mt7988_i2c2_1_pins[] = { 71, 72 };
-static int mt7988_i2c2_1_funcs[] = { 1, 1 };
-
-/* eth */
-static int mt7988_mdc_mdio0_pins[] = { 5, 6 };
-static int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
-
-static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
-static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
-static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_mdc_mdio1_pins[] = { 69, 70 };
-static int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
-
-/* pcie */
-static int mt7988_pcie_wake_n0_0_pins[] = { 7 };
-static int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
-static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n3_0_pins[] = { 9 };
-static int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n3_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
-
-static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_pcie_wake_n0_1_pins[] = { 13 };
-static int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_wake_n3_1_pins[] = { 14 };
-static int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
-static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
-static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
-static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
-static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
-static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n1_0_pins[] = { 75 };
-static int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n1_pins[] = { 76 };
-static int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_0_pins[] = { 77 };
-static int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
-static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_1_pins[] = { 79 };
-static int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
-
-/* pmic */
-static int mt7988_pmic_pins[] = { 11 };
-static int mt7988_pmic_funcs[] = { 1 };
-
-/* watchdog */
-static int mt7988_watchdog_pins[] = { 12 };
-static int mt7988_watchdog_funcs[] = { 1 };
-
-/* spi */
-static int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
-static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
-
-static int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
-static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
-static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
-static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
-static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
-
-/* flash */
-static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
-static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-static int mt7988_emmc_45_pins[] = {
-	21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
-};
-static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 };
-static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43,
-				     44, 45, 46, 47, 48, 49 };
-static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* uart */
-static int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
-static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart0_0_pins[] = { 22, 23 };
-static int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
-
-static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
-static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
-static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
-static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
-static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_tops_uart1_0_pins[] = { 28, 29 };
-static int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart0_1_pins[] = { 30, 31 };
-static int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart1_1_pins[] = { 36, 37 };
-static int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
-
-static int mt7988_uart0_pins[] = { 55, 56 };
-static int mt7988_uart0_funcs[] = { 1, 1 };
-
-static int mt7988_tops_uart0_2_pins[] = { 55, 56 };
-static int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
-
-static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
-static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
-static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-static int mt7988_tops_uart1_2_funcs[] = {
-	4,
-	4,
-};
-
-static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
-static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
-static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
-static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
-
-/* udi */
-static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
-static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2s */
-static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
-
-/* pcm */
-static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
-static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
-
-/* led */
-static int mt7988_gbe0_led1_pins[] = { 58 };
-static int mt7988_gbe0_led1_funcs[] = { 6 };
-static int mt7988_gbe1_led1_pins[] = { 59 };
-static int mt7988_gbe1_led1_funcs[] = { 6 };
-static int mt7988_gbe2_led1_pins[] = { 60 };
-static int mt7988_gbe2_led1_funcs[] = { 6 };
-static int mt7988_gbe3_led1_pins[] = { 61 };
-static int mt7988_gbe3_led1_funcs[] = { 6 };
-
-static int mt7988_2p5gbe_led1_pins[] = { 62 };
-static int mt7988_2p5gbe_led1_funcs[] = { 6 };
-
-static int mt7988_gbe0_led0_pins[] = { 64 };
-static int mt7988_gbe0_led0_funcs[] = { 1 };
-static int mt7988_gbe1_led0_pins[] = { 65 };
-static int mt7988_gbe1_led0_funcs[] = { 1 };
-static int mt7988_gbe2_led0_pins[] = { 66 };
-static int mt7988_gbe2_led0_funcs[] = { 1 };
-static int mt7988_gbe3_led0_pins[] = { 67 };
-static int mt7988_gbe3_led0_funcs[] = { 1 };
-
-static int mt7988_2p5gbe_led0_pins[] = { 68 };
-static int mt7988_2p5gbe_led0_funcs[] = { 1 };
-
-/* usb */
-static int mt7988_drv_vbus_p1_pins[] = { 63 };
-static int mt7988_drv_vbus_p1_funcs[] = { 1 };
-
-static int mt7988_drv_vbus_pins[] = { 79 };
-static int mt7988_drv_vbus_funcs[] = { 1 };
-
-static const struct group_desc mt7988_groups[] = {
-	/*  @GPIO(0,1,2,3): uart2 */
-	PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
-	/*  @GPIO(0,1,2,3,4): tops_jtag0_0 */
-	PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
-	/*  @GPIO(2,3): int_usxgmii */
-	PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
-	/*  @GPIO(0,1,2,3,4): dfd */
-	PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
-	/*  @GPIO(0,1): xfi_phy0_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
-	/*  @GPIO(0,1): xfi_phy1_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
-	/*  @GPIO(5,6) i2c0_0 */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
-	/*  @GPIO(5,6) i2c1_sfp */
-	PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
-	/*  @GPIO(5,6) xfi_pextp_phy0_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
-	/*  @GPIO(5,6) xfi_pextp_phy1_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
-	/*  @GPIO(5,6) mdc_mdio0 */
-	PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
-	/*  @GPIO(7): pcie_wake_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
-	/*  @GPIO(8): pcie_clk_req_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
-	/*  @GPIO(9): pcie_wake_n3_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
-	/*  @GPIO(10): pcie_clk_req_n3 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
-	/*  @GPIO(10): pcie_clk_req_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
-	/*  @GPIO(7,8) pcie_p0_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
-	/*  @GPIO(7,8) pcie_p1_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
-	/*  @GPIO(7,8) pcie_p2_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
-	/*  @GPIO(9,10) pcie_p3_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
-	/*  @GPIO(9,10) ckm_phy_i2c */
-	PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
-	/*  @GPIO(11): pmic */
-	PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
-	/*  @GPIO(12): watchdog */
-	PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
-	/*  @GPIO(13): pcie_wake_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
-	/*  @GPIO(14): pcie_wake_n3_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
-	/*  @GPIO(15,16) i2c0_1 */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
-	/*  @GPIO(15,16) u30_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
-	/*  @GPIO(15,16) u32_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
-	/*  @GPIO(15,16) xfi_phy0_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
-	/*  @GPIO(15,16) xfi_phy1_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
-	/*  @GPIO(15,16) xfi_phy_pll_i2c2 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
-	/*  @GPIO(17,18) i2c1_0 */
-	PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
-	/*  @GPIO(17,18) u30_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
-	/*  @GPIO(17,18) u32_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
-	/*  @GPIO(17,18) xfi_phy_pll_i2c3 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
-	/*  @GPIO(17,18) sgmii0_i2c */
-	PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
-	/*  @GPIO(17,18) sgmii1_i2c */
-	PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
-	/*  @GPIO(19): pcie_2l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
-	/*  @GPIO(20): pcie_1l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
-	/*  @GPIO(21): pwm1 */
-	PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
-	/*  @GPIO(22,23) spi0_wp_hold */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
-	/*  @GPIO(24,25,26,27) spi0 */
-	PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
-	/*  @GPIO(28,29,30,31) spi1 */
-	PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
-	/*  @GPIO(32,33,34,35) spi2 */
-	PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
-	/*  @GPIO(36,37) spi2_wp_hold */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
-	/*  @GPIO(22,23,24,25,26,27) snfi */
-	PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
-	/*  @GPIO(22,23) tops_uart0_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
-	/*  @GPIO(28,29,30,31) uart2_0 */
-	PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
-	/*  @GPIO(32,33,34,35) uart1_0 */
-	PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
-	/*  @GPIO(32,33,34,35) uart2_1 */
-	PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
-	/*  @GPIO(28) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(29) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(30) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(28,29) tops_uart1_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
-	/*  @GPIO(30,31) tops_uart0_1 */
-	PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
-	/*  @GPIO(36,37) tops_uart1_1 */
-	PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
-	/*  @GPIO(32,33,34,35,36) udi */
-	PINCTRL_PIN_GROUP("udi", mt7988_udi),
-	/*  @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */
-	PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
-	/*  @GPIO(32,33,34,35,36,37) sdcard */
-	PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard),
-	/*  @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */
-	PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
-	/*  @GPIO(28,29) 2p5g_ext_mdio */
-	PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
-	/*  @GPIO(30,31) gbe_ext_mdio */
-	PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
-	/*  @GPIO(50,51,52,53,54) i2s */
-	PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
-	/*  @GPIO(50,51,52,53) pcm */
-	PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
-	/*  @GPIO(55,56) uart0 */
-	PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
-	/*  @GPIO(55,56) tops_uart0_2 */
-	PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
-	/*  @GPIO(50,51,52,53) uart2_2 */
-	PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
-	/*  @GPIO(50,51,52,53,54) wo0_jtag */
-	PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
-	/*  @GPIO(50,51,52,53,54) wo1-wo1_jtag */
-	PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
-	/*  @GPIO(50,51,52,53,54) wo2_jtag */
-	PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
-	/*  @GPIO(57) pwm0 */
-	PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
-	/*  @GPIO(58,59,60,61,62) jtag */
-	PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
-	/*  @GPIO(58,59,60,61,62) tops_jtag0_1 */
-	PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
-	/*  @GPIO(58,59,60,61) uart2_3 */
-	PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
-	/*  @GPIO(58,59,60,61) uart1_1 */
-	PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
-	/*  @GPIO(58,59,60,61) gbe_led1 */
-	PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1),
-	PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1),
-	PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1),
-	PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1),
-	/*  @GPIO(62) 2p5gbe_led1 */
-	PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
-	/*  @GPIO(64,65,66,67) gbe_led0 */
-	PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0),
-	PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0),
-	PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0),
-	PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0),
-	/*  @GPIO(68) 2p5gbe_led0 */
-	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
-	/*  @GPIO(63) drv_vbus_p1 */
-	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
-	/*  @GPIO(63) pcie_clk_req_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
-	/*  @GPIO(69, 70) mdc_mdio1 */
-	PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
-	/*  @GPIO(69, 70) i2c1_2 */
-	PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
-	/*  @GPIO(69) pwm6 */
-	PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
-	/*  @GPIO(70) pwm7 */
-	PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
-	/*  @GPIO(69,70) i2c2_0 */
-	PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
-	/*  @GPIO(71,72) i2c2_1 */
-	PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
-	/*  @GPIO(73) pcie_2l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
-	/*  @GPIO(74) pcie_1l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
-	/*  @GPIO(75) pcie_wake_n1_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
-	/*  @GPIO(76) pcie_clk_req_n1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
-	/*  @GPIO(77) pcie_wake_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
-	/*  @GPIO(78) pcie_clk_req_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
-	/*  @GPIO(79) drv_vbus */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
-	/*  @GPIO(79) pcie_wake_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
-	/*  @GPIO(80,81,82,83) uart1_2 */
-	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
-	/*  @GPIO(80) pwm2 */
-	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
-	/*  @GPIO(81) pwm3 */
-	PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
-	/*  @GPIO(82) pwm4 */
-	PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
-	/*  @GPIO(83) pwm5 */
-	PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
-	/*  @GPIO(80) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(81) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(82) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(80,81) tops_uart1_2 */
-	PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
-	/*  @GPIO(80) net_wo0_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
-	/*  @GPIO(81) net_wo1_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
-	/*  @GPIO(82) net_wo2_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7988_jtag_groups[] = {
-	"tops_jtag0_0", "wo0_jtag", "wo1_jtag",
-	"wo2_jtag",	"jtag",	    "tops_jtag0_1",
-};
-static const char *mt7988_int_usxgmii_groups[] = {
-	"int_usxgmii",
-};
-static const char *mt7988_pwm_groups[] = {
-	"pwm0", "pwm1", "pwm2", "pwm3", "pwm4",	"pwm5",	"pwm6", "pwm7"
-};
-static const char *mt7988_dfd_groups[] = {
-	"dfd",
-};
-static const char *mt7988_i2c_groups[] = {
-	"xfi_phy0_i2c0",
-	"xfi_phy1_i2c0",
-	"xfi_phy_pll_i2c0",
-	"xfi_phy_pll_i2c1",
-	"i2c0_0",
-	"i2c1_sfp",
-	"xfi_pextp_phy0_i2c",
-	"xfi_pextp_phy1_i2c",
-	"i2c0_1",
-	"u30_phy_i2c0",
-	"u32_phy_i2c0",
-	"xfi_phy0_i2c1",
-	"xfi_phy1_i2c1",
-	"xfi_phy_pll_i2c2",
-	"i2c1_0",
-	"u30_phy_i2c1",
-	"u32_phy_i2c1",
-	"xfi_phy_pll_i2c3",
-	"sgmii0_i2c",
-	"sgmii1_i2c",
-	"i2c1_2",
-	"i2c2_0",
-	"i2c2_1",
-};
-static const char *mt7988_ethernet_groups[] = {
-	"mdc_mdio0",
-	"2p5g_ext_mdio",
-	"gbe_ext_mdio",
-	"mdc_mdio1",
-};
-static const char *mt7988_pcie_groups[] = {
-	"pcie_wake_n0_0",    "pcie_clk_req_n0_0", "pcie_wake_n3_0",
-	"pcie_clk_req_n3",   "pcie_p0_phy_i2c",	  "pcie_p1_phy_i2c",
-	"pcie_p3_phy_i2c",   "pcie_p2_phy_i2c",	  "ckm_phy_i2c",
-	"pcie_wake_n0_1",    "pcie_wake_n3_1",	  "pcie_2l_0_pereset",
-	"pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset",
-	"pcie_1l_0_pereset", "pcie_wake_n1_0",	  "pcie_clk_req_n1",
-	"pcie_wake_n2_0",    "pcie_clk_req_n2_0", "pcie_wake_n2_1",
-	"pcie_clk_req_n0_1"
-};
-static const char *mt7988_pmic_groups[] = {
-	"pmic",
-};
-static const char *mt7988_wdt_groups[] = {
-	"watchdog",
-};
-static const char *mt7988_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
-};
-static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
-						    "emmc_51" };
-static const char *mt7988_uart_groups[] = {
-	"uart2",
-	"tops_uart0_0",
-	"uart2_0",
-	"uart1_0",
-	"uart2_1",
-	"net_wo0_uart_txd_0",
-	"net_wo1_uart_txd_0",
-	"net_wo2_uart_txd_0",
-	"tops_uart1_0",
-	"ops_uart0_1",
-	"ops_uart1_1",
-	"uart0",
-	"tops_uart0_2",
-	"uart1_1",
-	"uart2_3",
-	"uart1_2",
-	"tops_uart1_2",
-	"net_wo0_uart_txd_1",
-	"net_wo1_uart_txd_1",
-	"net_wo2_uart_txd_1",
-};
-static const char *mt7988_udi_groups[] = {
-	"udi",
-};
-static const char *mt7988_audio_groups[] = {
-	"i2s", "pcm",
-};
-static const char *mt7988_led_groups[] = {
-	"gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
-	"gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
-	"wf5g_led0",   "wf5g_led1",
-};
-static const char *mt7988_usb_groups[] = {
-	"drv_vbus",
-	"drv_vbus_p1",
-};
-
-static const struct function_desc mt7988_functions[] = {
-	{ "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
-	{ "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
-	{ "int_usxgmii", mt7988_int_usxgmii_groups,
-	  ARRAY_SIZE(mt7988_int_usxgmii_groups) },
-	{ "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) },
-	{ "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) },
-	{ "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) },
-	{ "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
-	{ "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
-	{ "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
-	{ "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
-	{ "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) },
-	{ "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
-	{ "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
-	{ "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
-	{ "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
-	{ "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
-};
-
-static const struct mtk_eint_hw mt7988_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7988_pins),
-	.db_cnt = 16,
-};
-
-static const char *mt7988_pinctrl_register_base_names[] = {
-	"gpio_base",	 "iocfg_tr_base", "iocfg_br_base",
-	"iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-};
-
-static struct mtk_pin_soc mt7988_data = {
-	.reg_cal = mt7988_reg_cals,
-	.pins = mt7988_pins,
-	.npins = ARRAY_SIZE(mt7988_pins),
-	.grps = mt7988_groups,
-	.ngrps = ARRAY_SIZE(mt7988_groups),
-	.funcs = mt7988_functions,
-	.nfuncs = ARRAY_SIZE(mt7988_functions),
-	.eint_hw = &mt7988_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7988_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7988_pinctrl_of_match[] = {
-	{
-		.compatible = "mediatek,mt7988-pinctrl",
-	},
-	{}
-};
-
-static int mt7988_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7988_data);
-}
-
-static struct platform_driver mt7988_pinctrl_driver = {
-	.driver = {
-		.name = "mt7988-pinctrl",
-		.of_match_table = mt7988_pinctrl_of_match,
-	},
-	.probe = mt7988_pinctrl_probe,
-};
-
-static int __init mt7988_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7988_pinctrl_driver);
-}
-arch_initcall(mt7988_pinctrl_init);
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h
deleted file mode 100644
index 192f8cefb5..0000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7981_H
-#define _DT_BINDINGS_CLK_MT7981_H
-
-/* TOPCKGEN */
-#define CLK_TOP_CB_CKSQ_40M		0
-#define CLK_TOP_CB_M_416M		1
-#define CLK_TOP_CB_M_D2			2
-#define CLK_TOP_CB_M_D3			3
-#define CLK_TOP_M_D3_D2			4
-#define CLK_TOP_CB_M_D4			5
-#define CLK_TOP_CB_M_D8			6
-#define CLK_TOP_M_D8_D2			7
-#define CLK_TOP_CB_MM_720M		8
-#define CLK_TOP_CB_MM_D2		9
-#define CLK_TOP_CB_MM_D3		10
-#define CLK_TOP_CB_MM_D3_D5		11
-#define CLK_TOP_CB_MM_D4		12
-#define CLK_TOP_CB_MM_D6		13
-#define CLK_TOP_MM_D6_D2		14
-#define CLK_TOP_CB_MM_D8		15
-#define CLK_TOP_CB_APLL2_196M		16
-#define CLK_TOP_APLL2_D2		17
-#define CLK_TOP_APLL2_D4		18
-#define CLK_TOP_NET1_2500M		19
-#define CLK_TOP_CB_NET1_D4		20
-#define CLK_TOP_CB_NET1_D5		21
-#define CLK_TOP_NET1_D5_D2		22
-#define CLK_TOP_NET1_D5_D4		23
-#define CLK_TOP_CB_NET1_D8		24
-#define CLK_TOP_NET1_D8_D2		25
-#define CLK_TOP_NET1_D8_D4		26
-#define CLK_TOP_CB_NET2_800M		27
-#define CLK_TOP_CB_NET2_D2		28
-#define CLK_TOP_CB_NET2_D4		29
-#define CLK_TOP_NET2_D4_D2		30
-#define CLK_TOP_NET2_D4_D4		31
-#define CLK_TOP_CB_NET2_D6		32
-#define CLK_TOP_CB_WEDMCU_208M		33
-#define CLK_TOP_CB_SGM_325M		34
-#define CLK_TOP_CKSQ_40M_D2		35
-#define CLK_TOP_CB_RTC_32K		36
-#define CLK_TOP_CB_RTC_32P7K		37
-#define CLK_TOP_USB_TX250M		38
-#define CLK_TOP_FAUD			39
-#define CLK_TOP_NFI1X			40
-#define CLK_TOP_USB_EQ_RX250M		41
-#define CLK_TOP_USB_CDR_CK		42
-#define CLK_TOP_USB_LN0_CK		43
-#define CLK_TOP_SPINFI_BCK		44
-#define CLK_TOP_SPI			45
-#define CLK_TOP_SPIM_MST		46
-#define CLK_TOP_UART_BCK		47
-#define CLK_TOP_PWM_BCK			48
-#define CLK_TOP_I2C_BCK			49
-#define CLK_TOP_PEXTP_TL		50
-#define CLK_TOP_EMMC_208M		51
-#define CLK_TOP_EMMC_400M		52
-#define CLK_TOP_DRAMC_REF		53
-#define CLK_TOP_DRAMC_MD32		54
-#define CLK_TOP_SYSAXI			55
-#define CLK_TOP_SYSAPB			56
-#define CLK_TOP_ARM_DB_MAIN		57
-#define CLK_TOP_AP2CNN_HOST		58
-#define CLK_TOP_NETSYS			59
-#define CLK_TOP_NETSYS_500M		60
-#define CLK_TOP_NETSYS_WED_MCU		61
-#define CLK_TOP_NETSYS_2X		62
-#define CLK_TOP_SGM_325M		63
-#define CLK_TOP_SGM_REG			64
-#define CLK_TOP_F26M			65
-#define CLK_TOP_EIP97B			66
-#define CLK_TOP_USB3_PHY		67
-#define CLK_TOP_AUD			68
-#define CLK_TOP_A1SYS			69
-#define CLK_TOP_AUD_L			70
-#define CLK_TOP_A_TUNER			71
-#define CLK_TOP_U2U3_REF		72
-#define CLK_TOP_U2U3_SYS		73
-#define CLK_TOP_U2U3_XHCI		74
-#define CLK_TOP_USB_FRMCNT		75
-#define CLK_TOP_NFI1X_SEL		76
-#define CLK_TOP_SPINFI_SEL		77
-#define CLK_TOP_SPI_SEL			78
-#define CLK_TOP_SPIM_MST_SEL		79
-#define CLK_TOP_UART_SEL		80
-#define CLK_TOP_PWM_SEL			81
-#define CLK_TOP_I2C_SEL			82
-#define CLK_TOP_PEXTP_TL_SEL		83
-#define CLK_TOP_EMMC_208M_SEL		84
-#define CLK_TOP_EMMC_400M_SEL		85
-#define CLK_TOP_F26M_SEL		86
-#define CLK_TOP_DRAMC_SEL		87
-#define CLK_TOP_DRAMC_MD32_SEL		88
-#define CLK_TOP_SYSAXI_SEL		89
-#define CLK_TOP_SYSAPB_SEL		90
-#define CLK_TOP_ARM_DB_MAIN_SEL		91
-#define CLK_TOP_AP2CNN_HOST_SEL		92
-#define CLK_TOP_NETSYS_SEL		93
-#define CLK_TOP_NETSYS_500M_SEL		94
-#define CLK_TOP_NETSYS_MCU_SEL		95
-#define CLK_TOP_NETSYS_2X_SEL		96
-#define CLK_TOP_SGM_325M_SEL		97
-#define CLK_TOP_SGM_REG_SEL		98
-#define CLK_TOP_EIP97B_SEL		99
-#define CLK_TOP_USB3_PHY_SEL		100
-#define CLK_TOP_AUD_SEL			101
-#define CLK_TOP_A1SYS_SEL		102
-#define CLK_TOP_AUD_L_SEL		103
-#define CLK_TOP_A_TUNER_SEL		104
-#define CLK_TOP_U2U3_SEL		105
-#define CLK_TOP_U2U3_SYS_SEL		106
-#define CLK_TOP_U2U3_XHCI_SEL		107
-#define CLK_TOP_USB_FRMCNT_SEL		108
-#define CLK_TOP_AUD_I2S_M		109
-
-/* INFRACFG */
-#define CLK_INFRA_66M_MCK		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_SPI2_SEL		6
-#define CLK_INFRA_PWM1_SEL		7
-#define CLK_INFRA_PWM2_SEL		8
-#define CLK_INFRA_PWM3_SEL		9
-#define CLK_INFRA_PWM_BSEL		10
-#define CLK_INFRA_PCIE_SEL		11
-#define CLK_INFRA_GPT_STA		12
-#define CLK_INFRA_PWM_HCK		13
-#define CLK_INFRA_PWM_STA		14
-#define CLK_INFRA_PWM1_CK		15
-#define CLK_INFRA_PWM2_CK		16
-#define CLK_INFRA_PWM3_CK		17
-#define CLK_INFRA_CQ_DMA_CK		18
-#define CLK_INFRA_AUD_BUS_CK		19
-#define CLK_INFRA_AUD_26M_CK		20
-#define CLK_INFRA_AUD_L_CK		21
-#define CLK_INFRA_AUD_AUD_CK		22
-#define CLK_INFRA_AUD_EG2_CK		23
-#define CLK_INFRA_DRAMC_26M_CK		24
-#define CLK_INFRA_DBG_CK		25
-#define CLK_INFRA_AP_DMA_CK		26
-#define CLK_INFRA_SEJ_CK		27
-#define CLK_INFRA_SEJ_13M_CK		28
-#define CLK_INFRA_THERM_CK		29
-#define CLK_INFRA_I2C0_CK		30
-#define CLK_INFRA_UART0_CK		31
-#define CLK_INFRA_UART1_CK		32
-#define CLK_INFRA_UART2_CK		33
-#define CLK_INFRA_SPI2_CK		34
-#define CLK_INFRA_SPI2_HCK_CK		35
-#define CLK_INFRA_NFI1_CK		36
-#define CLK_INFRA_SPINFI1_CK		37
-#define CLK_INFRA_NFI_HCK_CK		38
-#define CLK_INFRA_SPI0_CK		39
-#define CLK_INFRA_SPI1_CK		40
-#define CLK_INFRA_SPI0_HCK_CK		41
-#define CLK_INFRA_SPI1_HCK_CK		42
-#define CLK_INFRA_FRTC_CK		43
-#define CLK_INFRA_MSDC_CK		44
-#define CLK_INFRA_MSDC_HCK_CK		45
-#define CLK_INFRA_MSDC_133M_CK		46
-#define CLK_INFRA_MSDC_66M_CK		47
-#define CLK_INFRA_ADC_26M_CK		48
-#define CLK_INFRA_ADC_FRC_CK		49
-#define CLK_INFRA_FBIST2FPC_CK		50
-#define CLK_INFRA_I2C_MCK_CK		51
-#define CLK_INFRA_I2C_PCK_CK		52
-#define CLK_INFRA_IUSB_133_CK		53
-#define CLK_INFRA_IUSB_66M_CK		54
-#define CLK_INFRA_IUSB_SYS_CK		55
-#define CLK_INFRA_IUSB_CK		56
-#define CLK_INFRA_IPCIE_CK		57
-#define CLK_INFRA_IPCIE_PIPE_CK		58
-#define CLK_INFRA_IPCIER_CK		59
-#define CLK_INFRA_IPCIEB_CK		60
-
-/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* SGMIISYS_0 */
-#define CLK_SGM0_TX_EN			0
-#define CLK_SGM0_RX_EN			1
-#define CLK_SGM0_CK0_EN			2
-#define CLK_SGM0_CDR_CK0_EN		3
-
-/* SGMIISYS_1 */
-#define CLK_SGM1_TX_EN			0
-#define CLK_SGM1_RX_EN			1
-#define CLK_SGM1_CK1_EN			2
-#define CLK_SGM1_CDR_CK1_EN		3
-
-/* ETHSYS */
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU0_EN		3
-
-#endif /* _DT_BINDINGS_CLK_MT7981_H */
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h
deleted file mode 100644
index 77cfea4a8e..0000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7988_H
-#define _DT_BINDINGS_CLK_MT7988_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_NETSYSPLL  0
-#define CLK_APMIXED_MPLL       1
-#define CLK_APMIXED_MMPLL      2
-#define CLK_APMIXED_APLL2      3
-#define CLK_APMIXED_NET1PLL    4
-#define CLK_APMIXED_NET2PLL    5
-#define CLK_APMIXED_WEDMCUPLL  6
-#define CLK_APMIXED_SGMPLL     7
-#define CLK_APMIXED_ARM_B      8
-#define CLK_APMIXED_CCIPLL2_B  9
-#define CLK_APMIXED_USXGMIIPLL 10
-#define CLK_APMIXED_MSDCPLL    11
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL		       0
-#define CLK_TOP_XTAL_D2		       1
-#define CLK_TOP_RTC_32K		       2
-#define CLK_TOP_RTC_32P7K	       3
-#define CLK_TOP_MPLL_D2		       4
-#define CLK_TOP_MPLL_D3_D2	       5
-#define CLK_TOP_MPLL_D4		       6
-#define CLK_TOP_MPLL_D8		       7
-#define CLK_TOP_MPLL_D8_D2	       8
-#define CLK_TOP_MMPLL_D2	       9
-#define CLK_TOP_MMPLL_D3_D5	       10
-#define CLK_TOP_MMPLL_D4	       11
-#define CLK_TOP_MMPLL_D6_D2	       12
-#define CLK_TOP_MMPLL_D8	       13
-#define CLK_TOP_APLL2_D4	       14
-#define CLK_TOP_NET1PLL_D4	       15
-#define CLK_TOP_NET1PLL_D5	       16
-#define CLK_TOP_NET1PLL_D5_D2	       17
-#define CLK_TOP_NET1PLL_D5_D4	       18
-#define CLK_TOP_NET1PLL_D8	       19
-#define CLK_TOP_NET1PLL_D8_D2	       20
-#define CLK_TOP_NET1PLL_D8_D4	       21
-#define CLK_TOP_NET1PLL_D8_D8	       22
-#define CLK_TOP_NET1PLL_D8_D16	       23
-#define CLK_TOP_NET2PLL_D2	       24
-#define CLK_TOP_NET2PLL_D4	       25
-#define CLK_TOP_NET2PLL_D4_D4	       26
-#define CLK_TOP_NET2PLL_D4_D8	       27
-#define CLK_TOP_NET2PLL_D6	       28
-#define CLK_TOP_NET2PLL_D8	       29
-#define CLK_TOP_NETSYS_SEL	       30
-#define CLK_TOP_NETSYS_500M_SEL	       31
-#define CLK_TOP_NETSYS_2X_SEL	       32
-#define CLK_TOP_NETSYS_GSW_SEL	       33
-#define CLK_TOP_ETH_GMII_SEL	       34
-#define CLK_TOP_NETSYS_MCU_SEL	       35
-#define CLK_TOP_NETSYS_PAO_2X_SEL      36
-#define CLK_TOP_EIP197_SEL	       37
-#define CLK_TOP_AXI_INFRA_SEL	       38
-#define CLK_TOP_UART_SEL	       39
-#define CLK_TOP_EMMC_250M_SEL	       40
-#define CLK_TOP_EMMC_400M_SEL	       41
-#define CLK_TOP_SPI_SEL		       42
-#define CLK_TOP_SPIM_MST_SEL	       43
-#define CLK_TOP_NFI1X_SEL	       44
-#define CLK_TOP_SPINFI_SEL	       45
-#define CLK_TOP_PWM_SEL		       46
-#define CLK_TOP_I2C_SEL		       47
-#define CLK_TOP_PCIE_MBIST_250M_SEL    48
-#define CLK_TOP_PEXTP_TL_SEL	       49
-#define CLK_TOP_PEXTP_TL_P1_SEL	       50
-#define CLK_TOP_PEXTP_TL_P2_SEL	       51
-#define CLK_TOP_PEXTP_TL_P3_SEL	       52
-#define CLK_TOP_USB_SYS_SEL	       53
-#define CLK_TOP_USB_SYS_P1_SEL	       54
-#define CLK_TOP_USB_XHCI_SEL	       55
-#define CLK_TOP_USB_XHCI_P1_SEL	       56
-#define CLK_TOP_USB_FRMCNT_SEL	       57
-#define CLK_TOP_USB_FRMCNT_P1_SEL      58
-#define CLK_TOP_AUD_SEL		       59
-#define CLK_TOP_A1SYS_SEL	       60
-#define CLK_TOP_AUD_L_SEL	       61
-#define CLK_TOP_A_TUNER_SEL	       62
-#define CLK_TOP_SSPXTP_SEL	       63
-#define CLK_TOP_USB_PHY_SEL	       64
-#define CLK_TOP_USXGMII_SBUS_0_SEL     65
-#define CLK_TOP_USXGMII_SBUS_1_SEL     66
-#define CLK_TOP_SGM_0_SEL	       67
-#define CLK_TOP_SGM_SBUS_0_SEL	       68
-#define CLK_TOP_SGM_1_SEL	       69
-#define CLK_TOP_SGM_SBUS_1_SEL	       70
-#define CLK_TOP_XFI_PHY_0_XTAL_SEL     71
-#define CLK_TOP_XFI_PHY_1_XTAL_SEL     72
-#define CLK_TOP_SYSAXI_SEL	       73
-#define CLK_TOP_SYSAPB_SEL	       74
-#define CLK_TOP_ETH_REFCK_50M_SEL      75
-#define CLK_TOP_ETH_SYS_200M_SEL       76
-#define CLK_TOP_ETH_SYS_SEL	       77
-#define CLK_TOP_ETH_XGMII_SEL	       78
-#define CLK_TOP_BUS_TOPS_SEL	       79
-#define CLK_TOP_NPU_TOPS_SEL	       80
-#define CLK_TOP_DRAMC_SEL	       81
-#define CLK_TOP_DRAMC_MD32_SEL	       82
-#define CLK_TOP_INFRA_F26M_SEL	       83
-#define CLK_TOP_PEXTP_P0_SEL	       84
-#define CLK_TOP_PEXTP_P1_SEL	       85
-#define CLK_TOP_PEXTP_P2_SEL	       86
-#define CLK_TOP_PEXTP_P3_SEL	       87
-#define CLK_TOP_DA_XTP_GLB_P0_SEL      88
-#define CLK_TOP_DA_XTP_GLB_P1_SEL      89
-#define CLK_TOP_DA_XTP_GLB_P2_SEL      90
-#define CLK_TOP_DA_XTP_GLB_P3_SEL      91
-#define CLK_TOP_CKM_SEL		       92
-#define CLK_TOP_DA_SEL		       93
-#define CLK_TOP_PEXTP_SEL	       94
-#define CLK_TOP_TOPS_P2_26M_SEL	       95
-#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
-#define CLK_TOP_NETSYS_SYNC_250M_SEL   97
-#define CLK_TOP_MACSEC_SEL	       98
-#define CLK_TOP_NETSYS_TOPS_400M_SEL   99
-#define CLK_TOP_NETSYS_PPEFB_250M_SEL  100
-#define CLK_TOP_NETSYS_WARP_SEL	       101
-#define CLK_TOP_ETH_MII_SEL	       102
-#define CLK_TOP_NPU_SEL		       103
-#define CLK_TOP_AUD_I2S_M	       104
-
-/* MCUSYS */
-
-#define CLK_MCU_BUS_DIV_SEL 0
-#define CLK_MCU_ARM_DIV_SEL 1
-
-/* INFRACFG_AO */
-
-#define CLK_INFRA_MUX_UART0_SEL		 0
-#define CLK_INFRA_MUX_UART1_SEL		 1
-#define CLK_INFRA_MUX_UART2_SEL		 2
-#define CLK_INFRA_MUX_SPI0_SEL		 3
-#define CLK_INFRA_MUX_SPI1_SEL		 4
-#define CLK_INFRA_MUX_SPI2_SEL		 5
-#define CLK_INFRA_PWM_SEL		 6
-#define CLK_INFRA_PWM_CK1_SEL		 7
-#define CLK_INFRA_PWM_CK2_SEL		 8
-#define CLK_INFRA_PWM_CK3_SEL		 9
-#define CLK_INFRA_PWM_CK4_SEL		 10
-#define CLK_INFRA_PWM_CK5_SEL		 11
-#define CLK_INFRA_PWM_CK6_SEL		 12
-#define CLK_INFRA_PWM_CK7_SEL		 13
-#define CLK_INFRA_PWM_CK8_SEL		 14
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
-
-/* INFRACFG */
-
-#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
-#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
-#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
-#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
-#define CLK_INFRA_66M_GPT_BCK	      23
-#define CLK_INFRA_66M_PWM_HCK	      24
-#define CLK_INFRA_66M_PWM_BCK	      25
-#define CLK_INFRA_66M_PWM_CK1	      26
-#define CLK_INFRA_66M_PWM_CK2	      27
-#define CLK_INFRA_66M_PWM_CK3	      28
-#define CLK_INFRA_66M_PWM_CK4	      29
-#define CLK_INFRA_66M_PWM_CK5	      30
-#define CLK_INFRA_66M_PWM_CK6	      31
-#define CLK_INFRA_66M_PWM_CK7	      32
-#define CLK_INFRA_66M_PWM_CK8	      33
-#define CLK_INFRA_133M_CQDMA_BCK      34
-#define CLK_INFRA_66M_AUD_SLV_BCK     35
-#define CLK_INFRA_AUD_26M	      36
-#define CLK_INFRA_AUD_L		      37
-#define CLK_INFRA_AUD_AUD	      38
-#define CLK_INFRA_AUD_EG2	      39
-#define CLK_INFRA_DRAMC_F26M	      40
-#define CLK_INFRA_133M_DBG_ACKM	      41
-#define CLK_INFRA_66M_AP_DMA_BCK      42
-#define CLK_INFRA_66M_SEJ_BCK	      43
-#define CLK_INFRA_PRE_CK_SEJ_F13M     44
-#define CLK_INFRA_26M_THERM_SYSTEM    45
-#define CLK_INFRA_I2C_BCK	      46
-#define CLK_INFRA_52M_UART0_CK	      47
-#define CLK_INFRA_52M_UART1_CK	      48
-#define CLK_INFRA_52M_UART2_CK	      49
-#define CLK_INFRA_NFI		      50
-#define CLK_INFRA_SPINFI	      51
-#define CLK_INFRA_66M_NFI_HCK	      52
-#define CLK_INFRA_104M_SPI0	      53
-#define CLK_INFRA_104M_SPI1	      54
-#define CLK_INFRA_104M_SPI2_BCK	      55
-#define CLK_INFRA_66M_SPI0_HCK	      56
-#define CLK_INFRA_66M_SPI1_HCK	      57
-#define CLK_INFRA_66M_SPI2_HCK	      58
-#define CLK_INFRA_66M_FLASHIF_AXI     59
-#define CLK_INFRA_RTC		      60
-#define CLK_INFRA_26M_ADC_BCK	      61
-#define CLK_INFRA_RC_ADC	      62
-#define CLK_INFRA_MSDC400	      63
-#define CLK_INFRA_MSDC2_HCK	      64
-#define CLK_INFRA_133M_MSDC_0_HCK     65
-#define CLK_INFRA_66M_MSDC_0_HCK      66
-#define CLK_INFRA_133M_CPUM_BCK	      67
-#define CLK_INFRA_BIST2FPC	      68
-#define CLK_INFRA_I2C_X16W_MCK_CK_P1  69
-#define CLK_INFRA_I2C_X16W_PCK_CK_P1  70
-#define CLK_INFRA_133M_USB_HCK	      71
-#define CLK_INFRA_133M_USB_HCK_CK_P1  72
-#define CLK_INFRA_66M_USB_HCK	      73
-#define CLK_INFRA_66M_USB_HCK_CK_P1   74
-#define CLK_INFRA_USB_SYS	      75
-#define CLK_INFRA_USB_SYS_CK_P1	      76
-#define CLK_INFRA_USB_REF	      77
-#define CLK_INFRA_USB_CK_P1	      78
-#define CLK_INFRA_USB_FRMCNT	      79
-#define CLK_INFRA_USB_FRMCNT_CK_P1    80
-#define CLK_INFRA_USB_PIPE	      81
-#define CLK_INFRA_USB_PIPE_CK_P1      82
-#define CLK_INFRA_USB_UTMI	      83
-#define CLK_INFRA_USB_UTMI_CK_P1      84
-#define CLK_INFRA_USB_XHCI	      85
-#define CLK_INFRA_USB_XHCI_CK_P1      86
-#define CLK_INFRA_PCIE_GFMUX_TL_P0    87
-#define CLK_INFRA_PCIE_GFMUX_TL_P1    88
-#define CLK_INFRA_PCIE_GFMUX_TL_P2    89
-#define CLK_INFRA_PCIE_GFMUX_TL_P3    90
-#define CLK_INFRA_PCIE_PIPE_P0	      91
-#define CLK_INFRA_PCIE_PIPE_P1	      92
-#define CLK_INFRA_PCIE_PIPE_P2	      93
-#define CLK_INFRA_PCIE_PIPE_P3	      94
-#define CLK_INFRA_133M_PCIE_CK_P0     95
-#define CLK_INFRA_133M_PCIE_CK_P1     96
-#define CLK_INFRA_133M_PCIE_CK_P2     97
-#define CLK_INFRA_133M_PCIE_CK_P3     98
-
-/* ETHDMA */
-
-#define CLK_ETHDMA_XGP1_EN   0
-#define CLK_ETHDMA_XGP2_EN   1
-#define CLK_ETHDMA_XGP3_EN   2
-#define CLK_ETHDMA_FE_EN     3
-#define CLK_ETHDMA_GP2_EN    4
-#define CLK_ETHDMA_GP1_EN    5
-#define CLK_ETHDMA_GP3_EN    6
-#define CLK_ETHDMA_ESW_EN    7
-#define CLK_ETHDMA_CRYPT0_EN 8
-#define CLK_ETHDMA_NR_CLK    9
-
-/* SGMIISYS_0 */
-
-#define CLK_SGM0_TX_EN	  0
-#define CLK_SGM0_RX_EN	  1
-#define CLK_SGMII0_NR_CLK 2
-
-/* SGMIISYS_1 */
-
-#define CLK_SGM1_TX_EN	  0
-#define CLK_SGM1_RX_EN	  1
-#define CLK_SGMII1_NR_CLK 2
-
-/* ETHWARP */
-
-#define CLK_ETHWARP_WOCPU2_EN 0
-#define CLK_ETHWARP_WOCPU1_EN 1
-#define CLK_ETHWARP_WOCPU0_EN 2
-#define CLK_ETHWARP_NR_CLK    3
-
-#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h
deleted file mode 100644
index 5a9b169324..0000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7986_H
-#define _DT_BINDINGS_CLK_MT7986_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_ARMPLL		0
-#define CLK_APMIXED_NET2PLL		1
-#define CLK_APMIXED_MMPLL		2
-#define CLK_APMIXED_SGMPLL		3
-#define CLK_APMIXED_WEDMCUPLL		4
-#define CLK_APMIXED_NET1PLL		5
-#define CLK_APMIXED_MPLL		6
-#define CLK_APMIXED_APLL2		7
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL			0
-#define CLK_TOP_XTAL_D2			1
-#define CLK_TOP_RTC_32K			2
-#define CLK_TOP_RTC_32P7K		3
-#define CLK_TOP_MPLL_D2			4
-#define CLK_TOP_MPLL_D4			5
-#define CLK_TOP_MPLL_D8			6
-#define CLK_TOP_MPLL_D8_D2		7
-#define CLK_TOP_MPLL_D3_D2		8
-#define CLK_TOP_MMPLL_D2		9
-#define CLK_TOP_MMPLL_D4		10
-#define CLK_TOP_MMPLL_D8		11
-#define CLK_TOP_MMPLL_D8_D2		12
-#define CLK_TOP_MMPLL_D3_D8		13
-#define CLK_TOP_MMPLL_U2PHY		14
-#define CLK_TOP_APLL2_D4		15
-#define CLK_TOP_NET1PLL_D4		16
-#define CLK_TOP_NET1PLL_D5		17
-#define CLK_TOP_NET1PLL_D5_D2		18
-#define CLK_TOP_NET1PLL_D5_D4		19
-#define CLK_TOP_NET1PLL_D8_D2		20
-#define CLK_TOP_NET1PLL_D8_D4		21
-#define CLK_TOP_NET2PLL_D4		22
-#define CLK_TOP_NET2PLL_D4_D2		23
-#define CLK_TOP_NET2PLL_D3_D2		24
-#define CLK_TOP_WEDMCUPLL_D5_D2		25
-#define CLK_TOP_NFI1X_SEL		26
-#define CLK_TOP_SPINFI_SEL		27
-#define CLK_TOP_SPI_SEL			28
-#define CLK_TOP_SPIM_MST_SEL		29
-#define CLK_TOP_UART_SEL		30
-#define CLK_TOP_PWM_SEL			31
-#define CLK_TOP_I2C_SEL			32
-#define CLK_TOP_PEXTP_TL_SEL		33
-#define CLK_TOP_EMMC_250M_SEL		34
-#define CLK_TOP_EMMC_416M_SEL		35
-#define CLK_TOP_F_26M_ADC_SEL		36
-#define CLK_TOP_DRAMC_SEL		37
-#define CLK_TOP_DRAMC_MD32_SEL		38
-#define CLK_TOP_SYSAXI_SEL		39
-#define CLK_TOP_SYSAPB_SEL		40
-#define CLK_TOP_ARM_DB_MAIN_SEL		41
-#define CLK_TOP_ARM_DB_JTSEL		42
-#define CLK_TOP_NETSYS_SEL		43
-#define CLK_TOP_NETSYS_500M_SEL		44
-#define CLK_TOP_NETSYS_MCU_SEL		45
-#define CLK_TOP_NETSYS_2X_SEL		46
-#define CLK_TOP_SGM_325M_SEL		47
-#define CLK_TOP_SGM_REG_SEL		48
-#define CLK_TOP_A1SYS_SEL		49
-#define CLK_TOP_CONN_MCUSYS_SEL		50
-#define CLK_TOP_EIP_B_SEL		51
-#define CLK_TOP_PCIE_PHY_SEL		52
-#define CLK_TOP_USB3_PHY_SEL		53
-#define CLK_TOP_F26M_SEL		54
-#define CLK_TOP_AUD_L_SEL		55
-#define CLK_TOP_A_TUNER_SEL		56
-#define CLK_TOP_U2U3_SEL		57
-#define CLK_TOP_U2U3_SYS_SEL		58
-#define CLK_TOP_U2U3_XHCI_SEL		59
-#define CLK_TOP_DA_U2_REFSEL		60
-#define CLK_TOP_DA_U2_CK_1P_SEL		61
-#define CLK_TOP_AP2CNN_HOST_SEL		62
-#define CLK_TOP_JTAG			63
-
-/* INFRACFG */
-
-#define CLK_INFRA_SYSAXI_D2		0
-#define CLK_INFRA_UART0_SEL		1
-#define CLK_INFRA_UART1_SEL		2
-#define CLK_INFRA_UART2_SEL		3
-#define CLK_INFRA_SPI0_SEL		4
-#define CLK_INFRA_SPI1_SEL		5
-#define CLK_INFRA_PWM1_SEL		6
-#define CLK_INFRA_PWM2_SEL		7
-#define CLK_INFRA_PWM_BSEL		8
-#define CLK_INFRA_PCIE_SEL		9
-#define CLK_INFRA_GPT_STA		10
-#define CLK_INFRA_PWM_HCK		11
-#define CLK_INFRA_PWM_STA		12
-#define CLK_INFRA_PWM1_CK		13
-#define CLK_INFRA_PWM2_CK		14
-#define CLK_INFRA_CQ_DMA_CK		15
-#define CLK_INFRA_EIP97_CK		16
-#define CLK_INFRA_AUD_BUS_CK		17
-#define CLK_INFRA_AUD_26M_CK		18
-#define CLK_INFRA_AUD_L_CK		19
-#define CLK_INFRA_AUD_AUD_CK		20
-#define CLK_INFRA_AUD_EG2_CK		21
-#define CLK_INFRA_DRAMC_26M_CK		22
-#define CLK_INFRA_DBG_CK		23
-#define CLK_INFRA_AP_DMA_CK		24
-#define CLK_INFRA_SEJ_CK		25
-#define CLK_INFRA_SEJ_13M_CK		26
-#define CLK_INFRA_THERM_CK		27
-#define CLK_INFRA_I2C0_CK		28
-#define CLK_INFRA_UART0_CK		29
-#define CLK_INFRA_UART1_CK		30
-#define CLK_INFRA_UART2_CK		31
-#define CLK_INFRA_NFI1_CK		32
-#define CLK_INFRA_SPINFI1_CK		33
-#define CLK_INFRA_NFI_HCK_CK		34
-#define CLK_INFRA_SPI0_CK		35
-#define CLK_INFRA_SPI1_CK		36
-#define CLK_INFRA_SPI0_HCK_CK		37
-#define CLK_INFRA_SPI1_HCK_CK		38
-#define CLK_INFRA_FRTC_CK		39
-#define CLK_INFRA_MSDC_CK		40
-#define CLK_INFRA_MSDC_HCK_CK		41
-#define CLK_INFRA_MSDC_133M_CK		42
-#define CLK_INFRA_MSDC_66M_CK		43
-#define CLK_INFRA_ADC_26M_CK		44
-#define CLK_INFRA_ADC_FRC_CK		45
-#define CLK_INFRA_FBIST2FPC_CK		46
-#define CLK_INFRA_IUSB_133_CK		47
-#define CLK_INFRA_IUSB_66M_CK		48
-#define CLK_INFRA_IUSB_SYS_CK		49
-#define CLK_INFRA_IUSB_CK		50
-#define CLK_INFRA_IPCIE_CK		51
-#define CLK_INFRA_IPCIE_PIPE_CK		52
-#define CLK_INFRA_IPCIER_CK		53
-#define CLK_INFRA_IPCIEB_CK		54
-#define CLK_INFRA_TRNG_CK		55
-
-/* SGMIISYS_0 */
-
-#define CLK_SGMII0_TX250M_EN		0
-#define CLK_SGMII0_RX250M_EN		1
-#define CLK_SGMII0_CDR_REF		2
-#define CLK_SGMII0_CDR_FB		3
-
-/* SGMIISYS_1 */
-
-#define CLK_SGMII1_TX250M_EN		0
-#define CLK_SGMII1_RX250M_EN		1
-#define CLK_SGMII1_CDR_REF		2
-#define CLK_SGMII1_CDR_FB		3
-
-/* ETHSYS */
-
-#define CLK_ETH_FE_EN			0
-#define CLK_ETH_GP2_EN			1
-#define CLK_ETH_GP1_EN			2
-#define CLK_ETH_WOCPU1_EN		3
-#define CLK_ETH_WOCPU0_EN		4
-
-#endif /* _DT_BINDINGS_CLK_MT7986_H */
diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h b/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h
deleted file mode 100644
index af3d16c811..0000000000
--- a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2022 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
-#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
-
-/* INFRACFG resets */
-#define MT7986_INFRACFG_PEXTP_MAC_SW_RST	6
-#define MT7986_INFRACFG_SSUSB_SW_RST		7
-#define MT7986_INFRACFG_EIP97_SW_RST		8
-#define MT7986_INFRACFG_AUDIO_SW_RST		13
-#define MT7986_INFRACFG_CQ_DMA_SW_RST		14
-
-#define MT7986_INFRACFG_TRNG_SW_RST		17
-#define MT7986_INFRACFG_AP_DMA_SW_RST		32
-#define MT7986_INFRACFG_I2C_SW_RST		33
-#define MT7986_INFRACFG_NFI_SW_RST		34
-#define MT7986_INFRACFG_SPI0_SW_RST		35
-#define MT7986_INFRACFG_SPI1_SW_RST		36
-#define MT7986_INFRACFG_UART0_SW_RST		37
-#define MT7986_INFRACFG_UART1_SW_RST		38
-#define MT7986_INFRACFG_UART2_SW_RST		39
-#define MT7986_INFRACFG_AUXADC_SW_RST		43
-
-#define MT7986_INFRACFG_APXGPT_SW_RST		66
-#define MT7986_INFRACFG_PWM_SW_RST		68
-
-#define MT7986_INFRACFG_SW_RST_NUM		69
-
-/* TOPRGU resets */
-#define MT7986_TOPRGU_APMIXEDSYS_SW_RST		0
-#define MT7986_TOPRGU_SGMII0_SW_RST		1
-#define MT7986_TOPRGU_SGMII1_SW_RST		2
-#define MT7986_TOPRGU_INFRA_SW_RST		3
-#define MT7986_TOPRGU_U2PHY_SW_RST		5
-#define MT7986_TOPRGU_PCIE_SW_RST		6
-#define MT7986_TOPRGU_SSUSB_SW_RST		7
-#define MT7986_TOPRGU_ETHDMA_SW_RST		20
-#define MT7986_TOPRGU_CONSYS_SW_RST		23
-
-#define MT7986_TOPRGU_SW_RST_NUM		24
-
-/* ETHSYS Subsystem resets */
-#define MT7986_ETHSYS_FE_SW_RST			6
-#define MT7986_ETHSYS_PMTR_SW_RST		8
-#define MT7986_ETHSYS_GMAC_SW_RST		23
-#define MT7986_ETHSYS_PPE0_SW_RST		30
-#define MT7986_ETHSYS_PPE1_SW_RST		31
-
-#define MT7986_ETHSYS_SW_RST_NUM		32
-
-#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index cb161df81e..acd40194b7 100644
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -235,7 +235,7 @@
 	};
 
 	apmixedsys: apmixedsys@1001E000 {
-		compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
+		compatible = "mediatek,mt7981-apmixedsys", "syscon";
 		reg = <0 0x1001E000 0 0x1000>;
 		#clock-cells = <1>;
 	};
@@ -450,7 +450,6 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "mediatek,mt7981-ethsys",
-			     "mediatek,mt7986-ethsys",
 			     "syscon";
 		reg = <0 0x15000000 0 0x1000>;
 		#clock-cells = <1>;
@@ -568,14 +567,14 @@
 	};
 
 	sgmiisys0: syscon@10060000 {
-		compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
+		compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
 		reg = <0 0x10060000 0 0x1000>;
 		mediatek,pnswap;
 		#clock-cells = <1>;
 	};
 
 	sgmiisys1: syscon@10070000 {
-		compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
+		compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
 		reg = <0 0x10070000 0 0x1000>;
 		#clock-cells = <1>;
 	};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
new file mode 100644
index 0000000000..4945185d69
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@0 {
+		target-path = "/soc/mmc@11230000";
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&mmc0_pins_emmc_51>;
+			pinctrl-1 = <&mmc0_pins_emmc_51>;
+			bus-width = <8>;
+			max-frequency = <200000000>;
+			cap-mmc-highspeed;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			hs400-ds-delay = <0x12814>;
+			vqmmc-supply = <&reg_1p8v>;
+			vmmc-supply = <&reg_3p3v>;
+			non-removable;
+			no-sd;
+			no-sdio;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			card@0 {
+				compatible = "mmc-card";
+				reg = <0>;
+
+				block {
+					compatible = "block-device";
+					partitions {
+						block-partition-env {
+							partname = "ubootenv";
+							nvmem-layout {
+								compatible = "u-boot,env-layout";
+							};
+						};
+						emmc_rootfs: block-partition-production {
+							partname = "production";
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-emmc = <&emmc_rootfs>;
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso
new file mode 100644
index 0000000000..39910b8cfe
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@0 {
+		target = <&pcf8563>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
new file mode 100644
index 0000000000..1f5e1491a4
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@1 {
+		target-path = "/soc/mmc@11230000";
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&mmc0_pins_sdcard>;
+			pinctrl-1 = <&mmc0_pins_sdcard>;
+			cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+			bus-width = <4>;
+			max-frequency = <52000000>;
+			cap-sd-highspeed;
+			vmmc-supply = <&reg_3p3v>;
+			vqmmc-supply = <&reg_3p3v>;
+			no-mmc;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			card@0 {
+				compatible = "mmc-card";
+				reg = <0>;
+
+				block {
+					compatible = "block-device";
+					partitions {
+						block-partition-env {
+							partname = "ubootenv";
+							nvmem-layout {
+								compatible = "u-boot,env-layout";
+							};
+						};
+						sd_rootfs: block-partition-production {
+							partname = "production";
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-sd = <&sd_rootfs>;
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso
new file mode 100644
index 0000000000..8a029b149f
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+
+	fragment@0 {
+		target-path = "/";
+		__overlay__ {
+			wifi_12v: regulator-wifi-12v {
+				compatible = "regulator-fixed";
+				regulator-name = "wifi";
+				regulator-min-microvolt = <12000000>;
+				regulator-max-microvolt = <12000000>;
+				gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				regulator-always-on;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c_wifi>;
+		__overlay__ {
+			// 5G WIFI MAC Address EEPROM
+			wifi_eeprom@51 {
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_5g: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+				};
+			};
+
+			// 6G WIFI MAC Address EEPROM
+			wifi_eeprom@52 {
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_6g: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&pcie0>;
+		__overlay__ {
+			pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+
+				wifi@0,0 {
+					compatible = "mediatek,mt76";
+					reg = <0x0000 0 0 0 0>;
+					nvmem-cell-names = "mac-address";
+					nvmem-cells = <&macaddr_5g>;
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&pcie1>;
+		__overlay__ {
+			pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+
+				wifi@0,0 {
+					compatible = "mediatek,mt76";
+					reg = <0x0000 0 0 0 0>;
+					nvmem-cell-names = "mac-address";
+					nvmem-cells = <&macaddr_6g>;
+				};
+			};
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
new file mode 100644
index 0000000000..416958428f
--- /dev/null
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+	model = "Bananapi BPI-R4";
+	compatible = "bananapi,bpi-r4",
+		     "mediatek,mt7988";
+
+	aliases {
+		serial0 = &uart0;
+		led-boot = &led_green;
+		led-failsafe = &led_green;
+		led-running = &led_green;
+		led-upgrade = &led_green;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
+		rootdisk-spim-nand = <&ubi_rootfs>;
+	};
+
+	memory {
+		reg = <0x00 0x40000000 0x00 0x10000000>;
+	};
+
+	/* SFP1 cage (WAN) */
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
+
+	/* SFP2 cage (LAN) */
+	sfp2: sfp2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp2>;
+		los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "WPS";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_green: led-green {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led_blue: led-blue {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gmac1 {
+	sfp = <&sfp2>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
+	status = "okay";
+};
+
+&gmac2 {
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
+	status = "okay";
+};
+
+&switch {
+	status = "okay";
+};
+
+&gsw_phy0 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_port0 {
+	label = "wan";
+};
+
+&gsw_phy0_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_phy1_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_phy2_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_phy3_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&cpu0 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	rt5190a_64: rt5190a@64 {
+		compatible = "richtek,rt5190a";
+		reg = <0x64>;
+		vin2-supply = <&rt5190_buck1>;
+		vin3-supply = <&rt5190_buck1>;
+		vin4-supply = <&rt5190_buck1>;
+
+		regulators {
+			rt5190_buck1: buck1 {
+				regulator-name = "rt5190a-buck1";
+				regulator-min-microvolt = <5090000>;
+				regulator-max-microvolt = <5090000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			buck2 {
+				regulator-name = "vcore";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			rt5190_buck3: buck3 {
+				regulator-name = "vproc";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+			buck4 {
+				regulator-name = "rt5190a-buck4";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			ldo {
+				regulator-name = "rt5190a-ldo";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_1_pins>;
+	status = "okay";
+
+	pca9545: i2c-switch@70 {
+		reg = <0x70>;
+		compatible = "nxp,pca9545";
+		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c_rtc: i2c@0 { //eeprom,rtc,ngff
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+			};
+
+			eeprom@57 {
+				compatible = "atmel,24c02";
+				reg = <0x57>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+			};
+
+			pcf8563: rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+				status = "disabled";
+			};
+		};
+
+		i2c_sfp1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+
+		i2c_sfp2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+
+		i2c_wifi: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
+};
+
+/* mPCIe SIM2 */
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+/* mPCIe SIM3 */
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
+/* M.2 key-B SIM1 */
+&pcie2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_pins>;
+	status = "okay";
+};
+
+/* M.2 key-M SSD */
+&pcie3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_pins>;
+	status = "okay";
+};
+
+&ssusb1 {
+	status = "okay";
+};
+
+&tphy {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-buswidth = <4>;
+		spi-rx-buswidth = <4>;
+	};
+};
+
+&spi_nand {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "bl2";
+			reg = <0x0 0x200000>;
+			read-only;
+		};
+
+		partition@200000 {
+			label = "ubi";
+			reg = <0x200000 0x7e00000>;
+			compatible = "linux,ubi";
+
+			volumes {
+				ubi-volume-ubootenv {
+					volname = "ubootenv";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
+
+				ubi-volume-ubootenv2 {
+					volname = "ubootenv2";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
+
+				ubi_rootfs: ubi-volume-fit {
+					volname = "fit";
+				};
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_2_lite_pins>;
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_3_pins>;
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&xphy {
+	status = "okay";
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 81410c017b..904339335f 100644
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -10,9 +10,18 @@
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
 #include <dt-bindings/thermal/thermal.h>
 
+/* TOPRGU resets */
+#define MT7988_TOPRGU_SGMII0_GRST		1
+#define MT7988_TOPRGU_SGMII1_GRST		2
+#define MT7988_TOPRGU_XFI0_GRST			12
+#define MT7988_TOPRGU_XFI1_GRST			13
+#define MT7988_TOPRGU_XFI_PEXTP0_GRST		14
+#define MT7988_TOPRGU_XFI_PEXTP1_GRST		15
+#define MT7988_TOPRGU_XFI_PLL_GRST		16
+
 / {
 	compatible = "mediatek,mt7988";
 	interrupt-parent = <&gic>;
@@ -138,6 +147,15 @@
 		clock-output-names = "clkxtal";
 	};
 
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
+		cooling-levels = <0 128 255>;
+		#cooling-cells = <2>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
 	pmu {
 		compatible = "arm,cortex-a73-pmu";
 		interrupt-parent = <&gic>;
@@ -200,15 +218,15 @@
 
 		phyfw: phy-firmware@f000000 {
 			compatible = "mediatek,2p5gphy-fw";
-			reg = <0 0x0f000000 0 0x8000>,
-			      <0 0x0f100000 0 0x20000>,
-			      <0 0x0f0f0000 0 0x200>;
+			reg = <0 0x0f100000 0 0x20000>,
+			      <0 0x0f0f0018 0 0x20>;
 		};
 
 		infracfg: infracfg@10001000 {
 			compatible = "mediatek,mt7988-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		topckgen: topckgen@1001b000 {
@@ -404,6 +422,69 @@
 				};
 			};
 
+			uart1_0_pins: uart1-0-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_0";
+				};
+			};
+
+			uart1_1_pins: uart1-1-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_1";
+				};
+			};
+
+			uart1_2_pins: uart1-2-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_2";
+				};
+			};
+
+			uart1_2_lite_pins: uart1-2-lite-pins {
+				mux {
+					function = "uart";
+					groups =  "uart1_2_lite";
+				};
+			};
+
+			uart2_pins: uart2-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2";
+				};
+			};
+
+			uart2_0_pins: uart2-0-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_0";
+				};
+			};
+
+			uart2_1_pins: uart2-1-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_1";
+				};
+			};
+
+			uart2_2_pins: uart2-2-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_2";
+				};
+			};
+
+			uart2_3_pins: uart2-3-pins {
+				mux {
+					function = "uart";
+					groups =  "uart2_3";
+				};
+			};
+
 			snfi_pins: snfi-pins {
 				mux {
 					function = "flash";
@@ -500,34 +581,52 @@
 
 		sgmiisys0: syscon@10060000 {
 			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_0",
-				     "syscon";
+				     "mediatek,mt7988-sgmiisys0",
+				     "syscon",
+				     "simple-mfd";
 			reg = <0 0x10060000 0 0x1000>;
+			resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
 			#clock-cells = <1>;
+
+			sgmiipcs0: pcs {
+				compatible = "mediatek,mt7988-sgmii";
+				clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
+					 <&sgmiisys0 CLK_SGM0_TX_EN>,
+					 <&sgmiisys0 CLK_SGM0_RX_EN>;
+				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+			};
 		};
 
 		sgmiisys1: syscon@10070000 {
 			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys_1",
-				     "syscon";
+				     "mediatek,mt7988-sgmiisys1",
+				     "syscon",
+				     "simple-mfd";
 			reg = <0 0x10070000 0 0x1000>;
+			resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
 			#clock-cells = <1>;
+
+			sgmiipcs1: pcs {
+				compatible = "mediatek,mt7988-sgmii";
+				clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
+					 <&sgmiisys1 CLK_SGM1_TX_EN>,
+					 <&sgmiisys1 CLK_SGM1_RX_EN>;
+				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+			};
 		};
 
-		usxgmiisys0: usxgmiisys@10080000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_0",
-				     "syscon";
+		usxgmiisys0: pcs@10080000 {
+			compatible = "mediatek,mt7988-usxgmiisys";
 			reg = <0 0x10080000 0 0x1000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
+			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
 		};
 
-		usxgmiisys1: usxgmiisys@10081000 {
-			compatible = "mediatek,mt7988-usxgmiisys",
-				     "mediatek,mt7988-usxgmiisys_1",
-				     "syscon";
+		usxgmiisys1: pcs@10081000 {
+			compatible = "mediatek,mt7988-usxgmiisys";
 			reg = <0 0x10081000 0 0x1000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
+			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
 		};
 
 		mcusys: mcusys@100e0000 {
@@ -558,6 +657,46 @@
 			status = "disabled";
 		};
 
+		uart1: serial@11000100 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000100 0 0x100>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			 * 8250-mtk driver don't control "baud" clock since commit
+			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+			 * still need to be passed to the driver to prevent probe fail
+			 */
+			clocks = <&topckgen CLK_TOP_UART_SEL>,
+				 <&infracfg CLK_INFRA_52M_UART1_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_MUX_UART1_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			status = "disabled";
+		};
+
+		uart2: serial@11000200 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000200 0 0x100>;
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			 * 8250-mtk driver don't control "baud" clock since commit
+			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+			 * still need to be passed to the driver to prevent probe fail
+			 */
+			clocks = <&topckgen CLK_TOP_UART_SEL>,
+				 <&infracfg CLK_INFRA_52M_UART2_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_MUX_UART2_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			status = "disabled";
+		};
+
 		snand: spi@11001000 {
 			compatible = "mediatek,mt7986-snand";
 			reg = <0 0x11001000 0 0x1000>;
@@ -679,22 +818,15 @@
 			status = "disabled";
 		};
 
-		fan: pwm-fan {
-			compatible = "pwm-fan";
-			/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
-			cooling-levels = <0 128 255>;
-			#cooling-cells = <2>;
-			#thermal-sensor-cells = <1>;
-			status = "disabled";
-		};
-
 		lvts: lvts@1100a000 {
-			compatible = "mediatek,mt7988-lvts";
+			compatible = "mediatek,mt7988-lvts-ap";
 			reg = <0 0x1100a000 0 0x1000>;
 			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
 			clock-names = "lvts_clk";
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
 			nvmem-cells = <&lvts_calibration>;
-			nvmem-cell-names = "e_data1";
+			nvmem-cell-names = "lvts-calib-data-1";
 			#thermal-sensor-cells = <1>;
 		};
 
@@ -1016,25 +1148,29 @@
 			};
 		};
 
-		xfi_pextp0: xfi-pextp@11f20000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_0",
-				     "syscon";
+		xfi_tphy0: phy@11f20000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
 			reg = <0 0x11f20000 0 0x10000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			mediatek,usxgmii-performance-errata;
+			#phy-cells = <0>;
 		};
 
-		xfi_pextp1: xfi-pextp@11f30000 {
-			compatible = "mediatek,mt7988-xfi-pextp",
-				     "mediatek,mt7988-xfi-pextp_1",
-				     "syscon";
+		xfi_tphy1: phy@11f30000 {
+			compatible = "mediatek,mt7988-xfi-tphy";
 			reg = <0 0x11f30000 0 0x10000>;
-			#clock-cells = <1>;
+			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
+			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+			clock-names = "xfipll", "topxtal";
+			#phy-cells = <0>;
 		};
 
-		xfi_pll: xfi-pll@11f40000 {
-			compatible = "mediatek,mt7988-xfi-pll", "syscon";
+		xfi_pll: clock-controller@11f40000 {
+			compatible = "mediatek,mt7988-xfi-pll";
 			reg = <0 0x11f40000 0 0x1000>;
+			resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
 			#clock-cells = <1>;
 		};
 
@@ -1085,7 +1221,7 @@
 			#interrupt-cells = <1>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ethrst 0>;
+			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 
@@ -1093,28 +1229,28 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				port@0 {
+				gsw_port0: port@0 {
 					reg = <0>;
 					label = "lan0";
 					phy-mode = "internal";
 					phy-handle = <&gsw_phy0>;
 				};
 
-				port@1 {
+				gsw_port1: port@1 {
 					reg = <1>;
 					label = "lan1";
 					phy-mode = "internal";
 					phy-handle = <&gsw_phy1>;
 				};
 
-				port@2 {
+				gsw_port2: port@2 {
 					reg = <2>;
 					label = "lan2";
 					phy-mode = "internal";
 					phy-handle = <&gsw_phy2>;
 				};
 
-				port@3 {
+				gsw_port3: port@3 {
 					reg = <3>;
 					label = "lan3";
 					phy-mode = "internal";
@@ -1241,18 +1377,11 @@
 			};
 		};
 
-		ethwarp: syscon@15031000 {
-			compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
+		ethwarp: clock-controller@15031000 {
+			compatible = "mediatek,mt7988-ethwarp";
 			reg = <0 0x15031000 0 0x1000>;
 			#clock-cells = <1>;
-
-			ethrst: reset-controller {
-				compatible = "ti,syscon-reset";
-				#reset-cells = <1>;
-				ti,reset-bits = <
-					0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
-				>;
-			};
+			#reset-cells = <1>;
 		};
 
 		eth: ethernet@15100000 {
@@ -1272,19 +1401,9 @@
 				 <&ethsys CLK_ETHDMA_GP3_EN>,
 				 <&ethsys CLK_ETHDMA_ESW_EN>,
 				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
-				 <&sgmiisys0 CLK_SGM0_TX_EN>,
-				 <&sgmiisys0 CLK_SGM0_RX_EN>,
-				 <&sgmiisys1 CLK_SGM1_TX_EN>,
-				 <&sgmiisys1 CLK_SGM1_RX_EN>,
 				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
 				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
 				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-				 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-				 <&topckgen CLK_TOP_SGM_0_SEL>,
-				 <&topckgen CLK_TOP_SGM_1_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
-				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
 				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
 				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
 				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
@@ -1298,13 +1417,9 @@
 				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
 				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
 			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
-				      "gp3", "esw", "crypto", "sgmii_tx250m",
-				      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+				      "gp3", "esw", "crypto",
 				      "ethwarp_wocpu2", "ethwarp_wocpu1",
-				      "ethwarp_wocpu0", "top_usxgmii0_sel",
-				      "top_usxgmii1_sel", "top_sgm0_sel",
-				      "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
-				      "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
+				      "ethwarp_wocpu0", "top_eth_gmii_sel",
 				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
 				      "top_eth_sys_sel", "top_eth_xgmii_sel",
 				      "top_eth_mii_sel", "top_netsys_sel",
@@ -1325,13 +1440,7 @@
 						 <&apmixedsys CLK_APMIXED_SGMPLL>,
 						 <&apmixedsys CLK_APMIXED_SGMPLL>;
 			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
-			mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
-			mediatek,xfi-pll = <&xfi_pll>;
 			mediatek,infracfg = <&topmisc>;
-			mediatek,toprgu = <&watchdog>;
-			#reset-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
@@ -1352,12 +1461,16 @@
 				compatible = "mediatek,eth-mac";
 				reg = <1>;
 				status = "disabled";
+				pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
+				phys = <&xfi_tphy1>;
 			};
 
 			gmac2: mac@2 {
 				compatible = "mediatek,eth-mac";
 				reg = <2>;
 				status = "disabled";
+				pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
+				phys = <&xfi_tphy0>;
 			};
 
 			mdio_bus: mdio-bus {
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c
deleted file mode 100644
index 3f1edc231e..0000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include "clk-pll.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-#define MT7988_PLL_FMAX (2500UL * MHZ)
-#define MT7988_PCW_CHG_SHIFT 2
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg,           \
-		 _div_table)                                                  \
-	{                                                                     \
-		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,   \
-		.en_mask = _en_mask, .flags = _flags,                         \
-		.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX,  \
-		.pcwbits = _pcwbits, .pd_reg = _pd_reg,                       \
-		.pd_shift = _pd_shift, .tuner_reg = _tuner_reg,               \
-		.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
-		.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift,                 \
-		.pcw_chg_reg = _pcw_chg_reg,                                  \
-		.pcw_chg_shift = MT7988_PCW_CHG_SHIFT,                        \
-		.div_table = _div_table, .parent_name = "clkxtal",            \
-	}
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,      \
-	    _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,          \
-	    _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg)                \
-	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
-		 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,     \
-		 _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
-
-static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
-	    0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
-	    23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
-	    0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
-	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
-	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
-	    0x0154),
-	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
-	    0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
-	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
-	    0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
-	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
-	    (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
-	    0x0204),
-	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
-	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
-	    HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
-	    32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
-};
-
-static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-	{ .compatible = "mediatek,mt7988-apmixedsys", },
-	{ /* sentinel */ }
-};
-
-static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-{
-	struct clk_hw_onecell_data *clk_data;
-	struct device_node *node = pdev->dev.of_node;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-	if (!clk_data)
-		return -ENOMEM;
-
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-	if (r) {
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-		goto free_apmixed_data;
-	}
-	return r;
-
-free_apmixed_data:
-	mtk_free_clk_data(clk_data);
-	return r;
-}
-
-static struct platform_driver clk_mt7988_apmixed_drv = {
-	.probe = clk_mt7988_apmixed_probe,
-	.driver = {
-		.name = "clk-mt7988-apmixed",
-		.of_match_table = of_match_clk_mt7988_apmixed,
-	},
-};
-builtin_platform_driver(clk_mt7988_apmixed_drv);
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c
deleted file mode 100644
index 14b877f8cb..0000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c
+++ /dev/null
@@ -1,141 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static const struct mtk_gate_regs ethdma_cg_regs = {
-	.set_ofs = 0x30,
-	.clr_ofs = 0x30,
-	.sta_ofs = 0x30,
-};
-
-#define GATE_ETHDMA(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethdma_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethdma_clks[] = {
-	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
-	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
-	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
-	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
-	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
-	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
-	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
-	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
-	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
-		    29),
-};
-
-static const struct mtk_clk_desc ethdma_desc = {
-	.clks = ethdma_clks,
-	.num_clks = ARRAY_SIZE(ethdma_clks),
-};
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii0_clks[] = {
-	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
-	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
-};
-
-static const struct mtk_clk_desc sgmii0_desc = {
-	.clks = sgmii0_clks,
-	.num_clks = ARRAY_SIZE(sgmii0_clks),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
-	.set_ofs = 0xe4,
-	.clr_ofs = 0xe4,
-	.sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift)                              \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &sgmii1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate sgmii1_clks[] = {
-	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
-	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
-};
-
-static const struct mtk_clk_desc sgmii1_desc = {
-	.clks = sgmii1_clks,
-	.num_clks = ARRAY_SIZE(sgmii1_clks),
-};
-
-static const struct mtk_gate_regs ethwarp_cg_regs = {
-	.set_ofs = 0x14,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x14,
-};
-
-#define GATE_ETHWARP(_id, _name, _parent, _shift)                             \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &ethwarp_cg_regs, .shift = _shift,                    \
-		.ops = &mtk_clk_gate_ops_no_setclr_inv,                       \
-	}
-
-static const struct mtk_gate ethwarp_clks[] = {
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
-		     "netsys_mcu_sel", 13),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
-		     "netsys_mcu_sel", 14),
-	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
-		     "netsys_mcu_sel", 15),
-};
-
-static const struct mtk_clk_desc ethwarp_desc = {
-	.clks = ethwarp_clks,
-	.num_clks = ARRAY_SIZE(ethwarp_clks),
-};
-
-static const struct of_device_id of_match_clk_mt7986_eth[] = {
-	{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
-	{ .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
-	{ .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
-	{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
-
-static struct platform_driver clk_mt7988_eth_drv = {
-	.driver = {
-		.name = "clk-mt7988-eth",
-		.of_match_table = of_match_clk_mt7986_eth,
-	},
-	.probe = mtk_clk_simple_probe,
-	.remove = mtk_clk_simple_remove,
-};
-module_platform_driver(clk_mt7988_eth_drv);
-
-MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c
deleted file mode 100644
index a5d21d756d..0000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c
+++ /dev/null
@@ -1,376 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const char *const infra_mux_uart0_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart1_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_uart2_parents[] __initconst = {
-	"csw_infra_f26m_sel", "uart_sel"
-};
-
-static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
-								  "spi_sel" };
-
-static const char *const infra_mux_spi1_parents[] __initconst = {
-	"i2c_sel", "spim_mst_sel"
-};
-
-static const char *const infra_pwm_bck_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p1_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p2_sel"
-};
-
-static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
-	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
-	"pextp_tl_p3_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
-	/* MODULE_CLK_SEL_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
-			     0, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
-			     1, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
-			     2, 1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
-			     infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
-			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
-			     1, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
-			     2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
-			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
-			     2, -1, -1, -1),
-	/* MODULE_CLK_SEL_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
-			     "infra_pcie_gfmux_tl_o_p0_sel",
-			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
-			     0x0020, 0x0024, 0, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
-			     "infra_pcie_gfmux_tl_o_p1_sel",
-			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
-			     0x0020, 0x0024, 2, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
-			     "infra_pcie_gfmux_tl_o_p2_sel",
-			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
-			     0x0020, 0x0024, 4, 2, -1, -1, -1),
-	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
-			     "infra_pcie_gfmux_tl_o_p3_sel",
-			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
-			     0x0020, 0x0024, 6, 2, -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
-	.set_ofs = 0x10,
-	.clr_ofs = 0x14,
-	.sta_ofs = 0x18,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
-	.set_ofs = 0x40,
-	.clr_ofs = 0x44,
-	.sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
-	.set_ofs = 0x50,
-	.clr_ofs = 0x54,
-	.sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra3_cg_regs = {
-	.set_ofs = 0x60,
-	.clr_ofs = 0x64,
-	.sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra0_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra1_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra2_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                \
-	{                                                                     \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = &infra3_cg_regs, .shift = _shift,                     \
-		.ops = &mtk_clk_gate_ops_setclr, .flags = _flags,             \
-	}
-
-#define GATE_INFRA0(_id, _name, _parent, _shift)                              \
-	GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA1(_id, _name, _parent, _shift)                              \
-	GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA2(_id, _name, _parent, _shift)                              \
-	GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_INFRA3(_id, _name, _parent, _shift)                              \
-	GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
-
-#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) {                   \
-		.id = _id, .name = _name, .parent_name = _parent,             \
-		.regs = _regs, .shift = _shift,                               \
-		.flags = CLK_IS_CRITICAL,                                     \
-		.ops = &mtk_clk_gate_ops_setclr,                              \
-	}
-
-static const struct mtk_gate infra_clks[] = {
-	/* INFRA0 */
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
-		    "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
-		    "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
-		    "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
-	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
-		    "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
-	/* INFRA1 */
-	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
-		    "sysaxi_sel", 0),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
-		    "sysaxi_sel", 1),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
-		    "infra_pwm_sel", 2),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
-		    "infra_pwm_ck1_sel", 3),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
-		    "infra_pwm_ck2_sel", 4),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
-		    "infra_pwm_ck3_sel", 5),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
-		    "infra_pwm_ck4_sel", 6),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
-		    "infra_pwm_ck5_sel", 7),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
-		    "infra_pwm_ck6_sel", 8),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
-		    "infra_pwm_ck7_sel", 9),
-	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
-		    "infra_pwm_ck8_sel", 10),
-	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
-		    "sysaxi_sel", 12),
-	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
-		    "sysaxi_sel", 13),
-	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
-		    "csw_infra_f26m_sel", 14),
-	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
-	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
-	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
-	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
-			  "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
-	// JTAG
-	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
-			  "sysaxi_sel", 20, CLK_IS_CRITICAL),
-	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
-		    "sysaxi_sel", 21),
-	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
-		    "sysaxi_sel", 29),
-	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
-		    "csw_infra_f26m_sel", 30),
-	/* INFRA2 */
-	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
-		    "csw_infra_f26m_sel", 0),
-	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
-	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
-		    "infra_mux_uart0_sel", 3),
-	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
-		    "infra_mux_uart1_sel", 4),
-	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
-		    "infra_mux_uart2_sel", 5),
-	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
-	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
-			  "sysaxi_sel", 11, CLK_IS_CRITICAL),
-	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
-			  "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
-		    "infra_mux_spi1_sel", 13),
-	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
-		    "infra_mux_spi2_sel", 14),
-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
-			  "sysaxi_sel", 15, CLK_IS_CRITICAL),
-	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
-		    "sysaxi_sel", 16),
-	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
-		    "sysaxi_sel", 17),
-	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
-		    "sysaxi_sel", 18),
-	GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19),
-	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
-		    "csw_infra_f26m_sel", 20),
-	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
-		    21),
-	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
-		    22),
-	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
-		    23),
-	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
-		    "sysaxi_sel", 24),
-	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
-		    "sysaxi_sel", 25),
-	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
-		    "sysaxi_sel", 26),
-	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
-		    "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
-	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
-		    "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
-	/* INFRA3 */
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
-		    0),
-	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
-		    "sysaxi_sel", 1),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
-		    2),
-	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
-		    "sysaxi_sel", 3),
-	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
-	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
-		    "usb_sys_p1_sel", 5),
-	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
-	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
-			  "usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
-	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
-			  "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
-		    "usb_phy_sel", 11),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
-	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
-		    "top_xtal", 13),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
-	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
-		    "usb_xhci_p1_sel", 15),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
-	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
-		    "top_xtal", 24),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
-		    "top_xtal", 25),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
-		    "top_xtal", 26),
-	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
-		    "top_xtal", 27),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
-		    "sysaxi_sel", 28),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
-		    "sysaxi_sel", 29),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
-		    "sysaxi_sel", 30),
-	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
-		    "sysaxi_sel", 31),
-};
-
-static const struct mtk_clk_desc infra_desc = {
-	.clks = infra_clks,
-	.num_clks = ARRAY_SIZE(infra_clks),
-	.mux_clks = infra_muxes,
-	.num_mux_clks = ARRAY_SIZE(infra_muxes),
-	.clk_lock = &mt7988_clk_lock,
-};
-
-static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-	{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
-
-static struct platform_driver clk_mt7988_infracfg_drv = {
-	.driver = {
-		.name = "clk-mt7988-infracfg",
-		.of_match_table = of_match_clk_mt7988_infracfg,
-	},
-	.probe = mtk_clk_simple_probe,
-	.remove = mtk_clk_simple_remove,
-};
-module_platform_driver(clk_mt7988_infracfg_drv);
diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c
deleted file mode 100644
index b0745d6508..0000000000
--- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c
+++ /dev/null
@@ -1,446 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-
-static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
-	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
-	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
-	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
-	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
-	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
-	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
-	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
-	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
-	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
-	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
-	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
-	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
-	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
-	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
-	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
-	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
-	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
-	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
-	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
-	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
-	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
-	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
-	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
-	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
-	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
-};
-
-static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
-					      "mmpll_d2" };
-
-static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
-						   "net1pll_d5_d2" };
-
-static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
-						 "mmpll" };
-
-static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
-						  "net1pll_d5" };
-
-static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
-
-static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",
-						  "mmpll",	"net1pll_d4",
-						  "net1pll_d5", "mpll" };
-
-static const char *const eip197_parents[] = { "top_xtal",   "netsyspll",
-					      "net2pll",    "mmpll",
-					      "net1pll_d4", "net1pll_d5" };
-
-static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
-
-static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
-					    "mpll_d8_d2" };
-
-static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
-						 "mmpll_d4" };
-
-static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
-						 "mmpll_d2", "mpll_d2",
-						 "mmpll_d4", "net1pll_d8_d2" };
-
-static const char *const spi_parents[] = { "top_xtal",	 "mpll_d2",
-					   "mmpll_d4",	 "net1pll_d8_d2",
-					   "net2pll_d6", "net1pll_d5_d4",
-					   "mpll_d4",	 "net1pll_d8_d4" };
-
-static const char *const nfi1x_parents[] = { "top_xtal",      "mmpll_d4",
-					     "net1pll_d8_d2", "net2pll_d6",
-					     "mpll_d4",	      "mmpll_d8",
-					     "net1pll_d8_d4", "mpll_d8" };
-
-static const char *const spinfi_parents[] = { "top_xtal_d2",   "top_xtal",
-					      "net1pll_d5_d4", "mpll_d4",
-					      "mmpll_d8",      "net1pll_d8_d4",
-					      "mmpll_d6_d2",   "mpll_d8" };
-
-static const char *const pwm_parents[] = { "top_xtal",	    "net1pll_d8_d2",
-					   "net1pll_d5_d4", "mpll_d4",
-					   "mpll_d8_d2",    "top_rtc_32k" };
-
-static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
-					   "mpll_d4", "net1pll_d8_d4" };
-
-static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
-						       "net1pll_d5_d2" };
-
-static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
-						   "mmpll_d8", "mpll_d8_d2",
-						   "top_rtc_32k" };
-
-static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
-
-static const char *const aud_parents[] = { "top_xtal", "apll2" };
-
-static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
-
-static const char *const aud_l_parents[] = { "top_xtal", "apll2",
-					     "mpll_d8_d2" };
-
-static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
-
-static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
-						      "net1pll_d8_d4" };
-
-static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
-
-static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
-
-static const char *const eth_refck_50m_parents[] = { "top_xtal",
-						     "net2pll_d4_d4" };
-
-static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
-
-static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
-						 "net1pll_d8_d8",
-						 "net1pll_d8_d16" };
-
-static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
-						"net2pll_d2" };
-
-static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
-
-static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
-						  "wedmcupll" };
-
-static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
-						     "net2pll_d8" };
-
-static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
-							  "net1pll_d4" };
-
-static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
-					      "net1pll_d8" };
-
-static const char *const netsys_tops_400m_parents[] = { "top_xtal",
-							"net2pll_d2" };
-
-static const char *const eth_mii_parents[] = { "top_xtal_d2",
-					       "net2pll_d4_d8" };
-
-static const struct mtk_mux top_muxes[] = {
-	/* CLK_CFG_0 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-			     0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-			     netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
-			     15, 0x1C0, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-			     netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
-			     0x1C0, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
-			     netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
-			     31, 0x1C0, 3),
-	/* CLK_CFG_1 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
-			     eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
-			     0x1C0, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
-			     0x1C0, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
-			     netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
-			     23, 0x1C0, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
-			     0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
-	/* CLK_CFG_2 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
-				   axi_infra_parents, 0x020, 0x024, 0x028, 0,
-				   1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
-			     0x024, 0x028, 8, 2, 15, 0x1c0, 9),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
-			     emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
-			     0x1C0, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-			     emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
-			     0x1C0, 11),
-	/* CLK_CFG_3 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
-			     0x034, 0x038, 0, 3, 7, 0x1c0, 12),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-			     0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-			     0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-			     0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
-	/* CLK_CFG_4 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
-			     0x044, 0x048, 0, 3, 7, 0x1c0, 16),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
-			     0x044, 0x048, 8, 2, 15, 0x1c0, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
-			     "pcie_mbist_250m_sel", pcie_mbist_250m_parents,
-			     0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
-			     pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
-			     31, 0x1C0, 19),
-	/* CLK_CFG_5 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
-			     0x1C0, 20),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
-			     15, 0x1C0, 21),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
-			     pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
-			     23, 0x1C0, 22),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
-			     eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
-			     0x1C0, 23),
-	/* CLK_CFG_6 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
-			     0x1C0, 24),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
-			     0x1C0, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
-			     eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
-			     0x1C0, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-			     usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
-			     31, 0x1C0, 27),
-	/* CLK_CFG_7 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
-			     usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-			     0x1C0, 28),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
-			     0x074, 0x078, 8, 1, 15, 0x1c0, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-			     0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-			     0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
-	/* CLK_CFG_8 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
-			     0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
-			     0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
-			     sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
-			     0x1c4, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
-			     1, 31, 0x1C4, 4),
-	/* CLK_CFG_9 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
-			     7, 0x1C4, 5),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
-				   usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
-				   16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
-			     0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
-	/* CLK_CFG_10 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
-				   usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
-				   0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
-			     0x1C4, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
-			     sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
-			     0x1C4, 11),
-	/* CLK_CFG_11 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-				   axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
-				   1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-				   sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
-				   7, 0x1c4, 13, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
-			     eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
-			     15, 0x1C4, 14),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
-			     eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
-			     23, 0x1C4, 15),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
-			     pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
-			     1, 31, 0x1C4, 16),
-	/* CLK_CFG_12 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
-			     eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
-			     0x1C4, 17),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
-			     bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
-			     0x1C4, 18),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
-			     npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
-			     0x1C4, 19),
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-				   sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
-				   31, 0x1C4, 20, CLK_IS_CRITICAL),
-	/* CLK_CFG_13 */
-	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-				   dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
-				   2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD_FLAGS(
-		CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-		0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
-			     0x1C4, 23),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
-			     sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
-			     0x1C4, 24),
-	/* CLK_CFG_14 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
-			     0x1C4, 25),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
-			     sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
-			     0x1C4, 26),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
-			     23, 0x1C4, 27),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
-			     da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
-			     31, 0x1C4, 28),
-	/* CLK_CFG_15 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
-			     7, 0x1C4, 29),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
-			     da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
-			     15, 0x1C4, 30),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
-			     0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
-			     0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
-	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
-			     0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
-			     sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
-			     0x1C8, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
-			     "mcusys_backup_625m_sel",
-			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
-			     16, 1, 23, 0x1C8, 4),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
-			     "netsys_sync_250m_sel", pcie_mbist_250m_parents,
-			     0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
-	/* CLK_CFG_17 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
-			     0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
-			     "netsys_tops_400m_sel", netsys_tops_400m_parents,
-			     0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
-			     "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
-			     0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
-			     netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
-			     0x1C8, 9),
-	/* CLK_CFG_18 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
-			     eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
-			     0x1c8, 10),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
-			     0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
-};
-
-static const struct mtk_composite top_aud_divs[] = {
-	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
-		 8, 8),
-};
-
-static const struct mtk_clk_desc topck_desc = {
-	.fixed_clks = top_fixed_clks,
-	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
-	.factor_clks = top_divs,
-	.num_factor_clks = ARRAY_SIZE(top_divs),
-	.mux_clks = top_muxes,
-	.num_mux_clks = ARRAY_SIZE(top_muxes),
-	.composite_clks = top_aud_divs,
-	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
-	.clk_lock = &mt7988_clk_lock,
-};
-
-static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
-						   "net1pll_d4" };
-
-static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
-						   "net1pll_d4" };
-
-static struct mtk_composite mcu_muxes[] = {
-	/* bus_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
-		       mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
-	/* mp2_pll_divider_cfg */
-	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
-		       mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
-};
-
-static const struct mtk_clk_desc mcusys_desc = {
-	.composite_clks = mcu_muxes,
-	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
-};
-
-static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-	{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
-	{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
-
-static struct platform_driver clk_mt7988_topckgen_drv = {
-	.probe = mtk_clk_simple_probe,
-	.remove = mtk_clk_simple_remove,
-	.driver = {
-		.name = "clk-mt7988-topckgen",
-		.of_match_table = of_match_clk_mt7988_topckgen,
-	},
-};
-module_platform_driver(clk_mt7988_topckgen_drv);
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
index c12e6b8eb6..e2e06d1eca 100644
--- a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
+++ b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
@@ -7,37 +7,50 @@
 #include <linux/of_platform.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/phy.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
 
-#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
-#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
+#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
 
-#define MD32_EN_CFG			0x18
-#define   MD32_EN			BIT(0)
+#define MD32_EN					BIT(0)
+#define PMEM_PRIORITY				BIT(8)
+#define DMEM_PRIORITY				BIT(16)
 
-#define BASE100T_STATUS_EXTEND		0x10
-#define BASE1000T_STATUS_EXTEND		0x11
-#define EXTEND_CTRL_AND_STATUS		0x16
+#define BASE100T_STATUS_EXTEND			0x10
+#define BASE1000T_STATUS_EXTEND			0x11
+#define EXTEND_CTRL_AND_STATUS			0x16
 
-#define PHY_AUX_CTRL_STATUS		0x1d
-#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
-#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
+#define PHY_AUX_CTRL_STATUS			0x1d
+#define   PHY_AUX_DPX_MASK			GENMASK(5, 5)
+#define   PHY_AUX_SPEED_MASK			GENMASK(4, 2)
 
 /* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_LINK_STATUS_MISC	0xa2
-#define   MTK_PHY_FDX_ENABLE		BIT(5)
+#define MTK_PHY_LINK_STATUS_MISC		0xa2
+#define   MTK_PHY_FDX_ENABLE			BIT(5)
+
+#define MTK_PHY_LPI_PCS_DSP_CTRL		0x121
+#define   MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK	GENMASK(12, 8)
 
 /* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL		0x24
-#define   MTK_PHY_LED0_ON_LINK1000	BIT(0)
-#define   MTK_PHY_LED0_ON_LINK100	BIT(1)
-#define   MTK_PHY_LED0_ON_LINK10	BIT(2)
-#define   MTK_PHY_LED0_ON_LINK2500	BIT(7)
-#define   MTK_PHY_LED0_POLARITY		BIT(14)
+#define MTK_PHY_LED0_ON_CTRL			0x24
+#define   MTK_PHY_LED0_ON_LINK1000		BIT(0)
+#define   MTK_PHY_LED0_ON_LINK100		BIT(1)
+#define   MTK_PHY_LED0_ON_LINK10		BIT(2)
+#define   MTK_PHY_LED0_ON_LINK2500		BIT(7)
+#define   MTK_PHY_LED0_POLARITY			BIT(14)
 
-#define MTK_PHY_LED1_ON_CTRL		0x26
-#define   MTK_PHY_LED1_ON_FDX		BIT(4)
-#define   MTK_PHY_LED1_ON_HDX		BIT(5)
-#define   MTK_PHY_LED1_POLARITY		BIT(14)
+#define MTK_PHY_LED1_ON_CTRL			0x26
+#define   MTK_PHY_LED1_ON_FDX			BIT(4)
+#define   MTK_PHY_LED1_ON_HDX			BIT(5)
+#define   MTK_PHY_LED1_POLARITY			BIT(14)
+
+#define MTK_EXT_PAGE_ACCESS			0x1f
+#define MTK_PHY_PAGE_STANDARD			0x0000
+#define MTK_PHY_PAGE_EXTENDED_52B5		0x52b5
+
+struct mtk_i2p5ge_phy_priv {
+	bool fw_loaded;
+};
 
 enum {
 	PHY_AUX_SPD_10 = 0,
@@ -46,67 +59,89 @@ enum {
 	PHY_AUX_SPD_2500,
 };
 
-static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
+static int mtk_2p5ge_phy_read_page(struct phy_device *phydev)
 {
-	int ret;
-	int i;
+	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+}
+
+static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page)
+{
+	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+}
+
+static int mt7988_2p5ge_phy_probe(struct phy_device *phydev)
+{
+	struct mtk_i2p5ge_phy_priv *phy_priv;
+
+	phy_priv = devm_kzalloc(&phydev->mdio.dev,
+				sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
+	if (!phy_priv)
+		return -ENOMEM;
+
+	phydev->priv = phy_priv;
+
+	return 0;
+}
+
+static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
+{
+	int ret, i;
 	const struct firmware *fw;
 	struct device *dev = &phydev->mdio.dev;
 	struct device_node *np;
-	void __iomem *dmb_addr;
 	void __iomem *pmb_addr;
-	void __iomem *mcucsr_base;
+	void __iomem *md32_en_cfg_base;
+	struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv;
 	u16 reg;
 	struct pinctrl *pinctrl;
 
-	np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
-	if (!np)
-		return -ENOENT;
+	if (!phy_priv->fw_loaded) {
+		np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
+		if (!np)
+			return -ENOENT;
+		pmb_addr = of_iomap(np, 0);
+		if (!pmb_addr)
+			return -ENOMEM;
+		md32_en_cfg_base = of_iomap(np, 1);
+		if (!md32_en_cfg_base)
+			return -ENOMEM;
 
-	dmb_addr = of_iomap(np, 0);
-	if (!dmb_addr)
-		return -ENOMEM;
-	pmb_addr = of_iomap(np, 1);
-	if (!pmb_addr)
-		return -ENOMEM;
-	mcucsr_base = of_iomap(np, 2);
-	if (!mcucsr_base)
-		return -ENOMEM;
+		ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
+		if (ret) {
+			dev_err(dev, "failed to load firmware: %s, ret: %d\n",
+				MT7988_2P5GE_PMB, ret);
+			return ret;
+		}
 
-	ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDAITEK_2P5GE_PHY_DMB_FW, ret);
-		return ret;
+		reg = readw(md32_en_cfg_base);
+		if (reg & MD32_EN) {
+			phy_set_bits(phydev, 0, BIT(15));
+			usleep_range(10000, 11000);
+		}
+		phy_set_bits(phydev, 0, BIT(11));
+
+		/* Write magic number to safely stall MCU */
+		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
+		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
+
+		for (i = 0; i < fw->size - 1; i += 4)
+			writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
+		release_firmware(fw);
+
+		writew(reg & ~MD32_EN, md32_en_cfg_base);
+		writew(reg | MD32_EN, md32_en_cfg_base);
+		phy_set_bits(phydev, 0, BIT(15));
+		dev_info(dev, "Firmware loading/trigger ok.\n");
+
+		phy_priv->fw_loaded = true;
 	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
-	release_firmware(fw);
-
-	ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
-	if (ret) {
-		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-			MEDIATEK_2P5GE_PHY_PMB_FW, ret);
-		return ret;
-	}
-	for (i = 0; i < fw->size - 1; i += 4)
-		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
-	release_firmware(fw);
-
-	reg = readw(mcucsr_base + MD32_EN_CFG);
-	writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
-	dev_dbg(dev, "Firmware loading/trigger ok.\n");
 
 	/* Setup LED */
-	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			   MTK_PHY_LED0_POLARITY);
-
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
 			 MTK_PHY_LED0_ON_LINK10 |
 			 MTK_PHY_LED0_ON_LINK100 |
 			 MTK_PHY_LED0_ON_LINK1000 |
 			 MTK_PHY_LED0_ON_LINK2500);
-
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
 			 MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
 
@@ -116,10 +151,20 @@ static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
 		return PTR_ERR(pinctrl);
 	}
 
+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
+		       MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
+
+	/* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+	__phy_write(phydev, 0x11, 0xfbfa);
+	__phy_write(phydev, 0x12, 0xc3);
+	__phy_write(phydev, 0x10, 0x87f8);
+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
 	return 0;
 }
 
-static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
+static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev)
 {
 	bool changed = false;
 	u32 adv;
@@ -152,7 +197,7 @@ static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
 	return genphy_c45_check_and_restart_aneg(phydev, changed);
 }
 
-static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
+static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev)
 {
 	int ret;
 
@@ -160,7 +205,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
 	if (ret)
 		return ret;
 
-	/* We don't support HDX at MAC layer on mt798x.
+	/* We don't support HDX at MAC layer on mt7988.
 	 * So mask phy's HDX capabilities, too.
 	 */
 	linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
@@ -176,7 +221,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
 	return 0;
 }
 
-static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
+static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev)
 {
 	int ret;
 
@@ -189,9 +234,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
 	phydev->pause = 0;
 	phydev->asym_pause = 0;
 
-	if (!phydev->link)
-		return 0;
-
 	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
 		ret = genphy_c45_read_lpa(phydev);
 		if (ret < 0)
@@ -222,7 +264,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
 		break;
 	case PHY_AUX_SPD_2500:
 		phydev->speed = SPEED_2500;
-		phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
 		break;
 	}
 
@@ -231,18 +272,32 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
 		return ret;
 
 	phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
+	/* FIXME: The current firmware always enables rate adaptation mode. */
+	phydev->rate_matching = RATE_MATCH_PAUSE;
 
 	return 0;
 }
 
+static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
+					      phy_interface_t iface)
+{
+	return RATE_MATCH_PAUSE;
+}
+
 static struct phy_driver mtk_gephy_driver[] = {
 	{
-		PHY_ID_MATCH_EXACT(0x00339c11),
+		PHY_ID_MATCH_MODEL(0x00339c11),
 		.name		= "MediaTek MT798x 2.5GbE PHY",
-		.config_init	= mt798x_2p5ge_phy_config_init,
-		.config_aneg    = mt798x_2p5ge_phy_config_aneg,
-		.get_features	= mt798x_2p5ge_phy_get_features,
-		.read_status	= mt798x_2p5ge_phy_read_status,
+		.probe		= mt7988_2p5ge_phy_probe,
+		.config_init	= mt7988_2p5ge_phy_config_init,
+		.config_aneg    = mt7988_2p5ge_phy_config_aneg,
+		.get_features	= mt7988_2p5ge_phy_get_features,
+		.read_status	= mt7988_2p5ge_phy_read_status,
+		.get_rate_matching	= mt7988_2p5ge_phy_get_rate_matching,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.read_page	= mtk_2p5ge_phy_read_page,
+		.write_page	= mtk_2p5ge_phy_write_page,
 	},
 };
 
@@ -258,5 +313,4 @@ MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
 MODULE_LICENSE("GPL");
 
 MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
-MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
-MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);
+MODULE_FIRMWARE(MT7988_2P5GE_PMB);
diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
index 49c0be1bba..9f92911245 100644
--- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
@@ -596,6 +596,51 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
 	PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
 };
 
+static const unsigned int mt7988_pull_type[] = {
+	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,    /*7*/
+	MTK_PULL_PU_PD_TYPE,    /*8*/ MTK_PULL_PU_PD_TYPE,    /*9*/
+	MTK_PULL_PU_PD_TYPE,    /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,    /*13*/
+	MTK_PULL_PU_PD_TYPE,    /*14*/ MTK_PULL_PD_TYPE,       /*15*/
+	MTK_PULL_PD_TYPE,       /*16*/ MTK_PULL_PD_TYPE,       /*17*/
+	MTK_PULL_PD_TYPE,       /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,    /*63*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE,       /*71*/
+	MTK_PULL_PD_TYPE,       /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,    /*75*/
+	MTK_PULL_PU_PD_TYPE,    /*76*/ MTK_PULL_PU_PD_TYPE,    /*77*/
+	MTK_PULL_PU_PD_TYPE,    /*78*/ MTK_PULL_PU_PD_TYPE,    /*79*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/
+};
+
 static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
@@ -992,11 +1037,11 @@ static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
 static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
 static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
 
+static int mt7988_uart1_2_lite_pins[] = { 80, 81 };
+static int mt7988_uart1_2_lite_funcs[] = { 1, 1 };
+
 static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-static int mt7988_tops_uart1_2_funcs[] = {
-	4,
-	4,
-};
+static int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
 
 static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
 static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
@@ -1254,6 +1299,8 @@ static const struct group_desc mt7988_groups[] = {
 	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
 	/*  @GPIO(80,81,82,83) uart1_2 */
 	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
+	/*  @GPIO(80,81) uart1_2_lite */
+	PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite),
 	/*  @GPIO(80) pwm2 */
 	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
 	/*  @GPIO(81) pwm3 */
@@ -1363,6 +1410,7 @@ static const char * const mt7988_uart_groups[] = {
 	"uart1_1",
 	"uart2_3",
 	"uart1_2",
+	"uart1_2_lite",
 	"tops_uart1_2",
 	"net_wo0_uart_txd_1",
 	"net_wo1_uart_txd_1",
@@ -1433,6 +1481,9 @@ static struct mtk_pin_soc mt7988_data = {
 	.bias_disable_get = mtk_pinconf_bias_disable_get,
 	.bias_set = mtk_pinconf_bias_set,
 	.bias_get = mtk_pinconf_bias_get,
+	.pull_type = mt7988_pull_type,
+	.bias_set_combo = mtk_pinconf_bias_set_combo,
+	.bias_get_combo = mtk_pinconf_bias_get_combo,
 	.drive_set = mtk_pinconf_drive_set_rev1,
 	.drive_get = mtk_pinconf_drive_get_rev1,
 	.adv_pull_get = mtk_pinconf_adv_pull_get,
diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h
deleted file mode 100644
index 77cfea4a8e..0000000000
--- a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2023 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7988_H
-#define _DT_BINDINGS_CLK_MT7988_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_NETSYSPLL  0
-#define CLK_APMIXED_MPLL       1
-#define CLK_APMIXED_MMPLL      2
-#define CLK_APMIXED_APLL2      3
-#define CLK_APMIXED_NET1PLL    4
-#define CLK_APMIXED_NET2PLL    5
-#define CLK_APMIXED_WEDMCUPLL  6
-#define CLK_APMIXED_SGMPLL     7
-#define CLK_APMIXED_ARM_B      8
-#define CLK_APMIXED_CCIPLL2_B  9
-#define CLK_APMIXED_USXGMIIPLL 10
-#define CLK_APMIXED_MSDCPLL    11
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL		       0
-#define CLK_TOP_XTAL_D2		       1
-#define CLK_TOP_RTC_32K		       2
-#define CLK_TOP_RTC_32P7K	       3
-#define CLK_TOP_MPLL_D2		       4
-#define CLK_TOP_MPLL_D3_D2	       5
-#define CLK_TOP_MPLL_D4		       6
-#define CLK_TOP_MPLL_D8		       7
-#define CLK_TOP_MPLL_D8_D2	       8
-#define CLK_TOP_MMPLL_D2	       9
-#define CLK_TOP_MMPLL_D3_D5	       10
-#define CLK_TOP_MMPLL_D4	       11
-#define CLK_TOP_MMPLL_D6_D2	       12
-#define CLK_TOP_MMPLL_D8	       13
-#define CLK_TOP_APLL2_D4	       14
-#define CLK_TOP_NET1PLL_D4	       15
-#define CLK_TOP_NET1PLL_D5	       16
-#define CLK_TOP_NET1PLL_D5_D2	       17
-#define CLK_TOP_NET1PLL_D5_D4	       18
-#define CLK_TOP_NET1PLL_D8	       19
-#define CLK_TOP_NET1PLL_D8_D2	       20
-#define CLK_TOP_NET1PLL_D8_D4	       21
-#define CLK_TOP_NET1PLL_D8_D8	       22
-#define CLK_TOP_NET1PLL_D8_D16	       23
-#define CLK_TOP_NET2PLL_D2	       24
-#define CLK_TOP_NET2PLL_D4	       25
-#define CLK_TOP_NET2PLL_D4_D4	       26
-#define CLK_TOP_NET2PLL_D4_D8	       27
-#define CLK_TOP_NET2PLL_D6	       28
-#define CLK_TOP_NET2PLL_D8	       29
-#define CLK_TOP_NETSYS_SEL	       30
-#define CLK_TOP_NETSYS_500M_SEL	       31
-#define CLK_TOP_NETSYS_2X_SEL	       32
-#define CLK_TOP_NETSYS_GSW_SEL	       33
-#define CLK_TOP_ETH_GMII_SEL	       34
-#define CLK_TOP_NETSYS_MCU_SEL	       35
-#define CLK_TOP_NETSYS_PAO_2X_SEL      36
-#define CLK_TOP_EIP197_SEL	       37
-#define CLK_TOP_AXI_INFRA_SEL	       38
-#define CLK_TOP_UART_SEL	       39
-#define CLK_TOP_EMMC_250M_SEL	       40
-#define CLK_TOP_EMMC_400M_SEL	       41
-#define CLK_TOP_SPI_SEL		       42
-#define CLK_TOP_SPIM_MST_SEL	       43
-#define CLK_TOP_NFI1X_SEL	       44
-#define CLK_TOP_SPINFI_SEL	       45
-#define CLK_TOP_PWM_SEL		       46
-#define CLK_TOP_I2C_SEL		       47
-#define CLK_TOP_PCIE_MBIST_250M_SEL    48
-#define CLK_TOP_PEXTP_TL_SEL	       49
-#define CLK_TOP_PEXTP_TL_P1_SEL	       50
-#define CLK_TOP_PEXTP_TL_P2_SEL	       51
-#define CLK_TOP_PEXTP_TL_P3_SEL	       52
-#define CLK_TOP_USB_SYS_SEL	       53
-#define CLK_TOP_USB_SYS_P1_SEL	       54
-#define CLK_TOP_USB_XHCI_SEL	       55
-#define CLK_TOP_USB_XHCI_P1_SEL	       56
-#define CLK_TOP_USB_FRMCNT_SEL	       57
-#define CLK_TOP_USB_FRMCNT_P1_SEL      58
-#define CLK_TOP_AUD_SEL		       59
-#define CLK_TOP_A1SYS_SEL	       60
-#define CLK_TOP_AUD_L_SEL	       61
-#define CLK_TOP_A_TUNER_SEL	       62
-#define CLK_TOP_SSPXTP_SEL	       63
-#define CLK_TOP_USB_PHY_SEL	       64
-#define CLK_TOP_USXGMII_SBUS_0_SEL     65
-#define CLK_TOP_USXGMII_SBUS_1_SEL     66
-#define CLK_TOP_SGM_0_SEL	       67
-#define CLK_TOP_SGM_SBUS_0_SEL	       68
-#define CLK_TOP_SGM_1_SEL	       69
-#define CLK_TOP_SGM_SBUS_1_SEL	       70
-#define CLK_TOP_XFI_PHY_0_XTAL_SEL     71
-#define CLK_TOP_XFI_PHY_1_XTAL_SEL     72
-#define CLK_TOP_SYSAXI_SEL	       73
-#define CLK_TOP_SYSAPB_SEL	       74
-#define CLK_TOP_ETH_REFCK_50M_SEL      75
-#define CLK_TOP_ETH_SYS_200M_SEL       76
-#define CLK_TOP_ETH_SYS_SEL	       77
-#define CLK_TOP_ETH_XGMII_SEL	       78
-#define CLK_TOP_BUS_TOPS_SEL	       79
-#define CLK_TOP_NPU_TOPS_SEL	       80
-#define CLK_TOP_DRAMC_SEL	       81
-#define CLK_TOP_DRAMC_MD32_SEL	       82
-#define CLK_TOP_INFRA_F26M_SEL	       83
-#define CLK_TOP_PEXTP_P0_SEL	       84
-#define CLK_TOP_PEXTP_P1_SEL	       85
-#define CLK_TOP_PEXTP_P2_SEL	       86
-#define CLK_TOP_PEXTP_P3_SEL	       87
-#define CLK_TOP_DA_XTP_GLB_P0_SEL      88
-#define CLK_TOP_DA_XTP_GLB_P1_SEL      89
-#define CLK_TOP_DA_XTP_GLB_P2_SEL      90
-#define CLK_TOP_DA_XTP_GLB_P3_SEL      91
-#define CLK_TOP_CKM_SEL		       92
-#define CLK_TOP_DA_SEL		       93
-#define CLK_TOP_PEXTP_SEL	       94
-#define CLK_TOP_TOPS_P2_26M_SEL	       95
-#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
-#define CLK_TOP_NETSYS_SYNC_250M_SEL   97
-#define CLK_TOP_MACSEC_SEL	       98
-#define CLK_TOP_NETSYS_TOPS_400M_SEL   99
-#define CLK_TOP_NETSYS_PPEFB_250M_SEL  100
-#define CLK_TOP_NETSYS_WARP_SEL	       101
-#define CLK_TOP_ETH_MII_SEL	       102
-#define CLK_TOP_NPU_SEL		       103
-#define CLK_TOP_AUD_I2S_M	       104
-
-/* MCUSYS */
-
-#define CLK_MCU_BUS_DIV_SEL 0
-#define CLK_MCU_ARM_DIV_SEL 1
-
-/* INFRACFG_AO */
-
-#define CLK_INFRA_MUX_UART0_SEL		 0
-#define CLK_INFRA_MUX_UART1_SEL		 1
-#define CLK_INFRA_MUX_UART2_SEL		 2
-#define CLK_INFRA_MUX_SPI0_SEL		 3
-#define CLK_INFRA_MUX_SPI1_SEL		 4
-#define CLK_INFRA_MUX_SPI2_SEL		 5
-#define CLK_INFRA_PWM_SEL		 6
-#define CLK_INFRA_PWM_CK1_SEL		 7
-#define CLK_INFRA_PWM_CK2_SEL		 8
-#define CLK_INFRA_PWM_CK3_SEL		 9
-#define CLK_INFRA_PWM_CK4_SEL		 10
-#define CLK_INFRA_PWM_CK5_SEL		 11
-#define CLK_INFRA_PWM_CK6_SEL		 12
-#define CLK_INFRA_PWM_CK7_SEL		 13
-#define CLK_INFRA_PWM_CK8_SEL		 14
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
-#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
-
-/* INFRACFG */
-
-#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
-#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
-#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
-#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
-#define CLK_INFRA_66M_GPT_BCK	      23
-#define CLK_INFRA_66M_PWM_HCK	      24
-#define CLK_INFRA_66M_PWM_BCK	      25
-#define CLK_INFRA_66M_PWM_CK1	      26
-#define CLK_INFRA_66M_PWM_CK2	      27
-#define CLK_INFRA_66M_PWM_CK3	      28
-#define CLK_INFRA_66M_PWM_CK4	      29
-#define CLK_INFRA_66M_PWM_CK5	      30
-#define CLK_INFRA_66M_PWM_CK6	      31
-#define CLK_INFRA_66M_PWM_CK7	      32
-#define CLK_INFRA_66M_PWM_CK8	      33
-#define CLK_INFRA_133M_CQDMA_BCK      34
-#define CLK_INFRA_66M_AUD_SLV_BCK     35
-#define CLK_INFRA_AUD_26M	      36
-#define CLK_INFRA_AUD_L		      37
-#define CLK_INFRA_AUD_AUD	      38
-#define CLK_INFRA_AUD_EG2	      39
-#define CLK_INFRA_DRAMC_F26M	      40
-#define CLK_INFRA_133M_DBG_ACKM	      41
-#define CLK_INFRA_66M_AP_DMA_BCK      42
-#define CLK_INFRA_66M_SEJ_BCK	      43
-#define CLK_INFRA_PRE_CK_SEJ_F13M     44
-#define CLK_INFRA_26M_THERM_SYSTEM    45
-#define CLK_INFRA_I2C_BCK	      46
-#define CLK_INFRA_52M_UART0_CK	      47
-#define CLK_INFRA_52M_UART1_CK	      48
-#define CLK_INFRA_52M_UART2_CK	      49
-#define CLK_INFRA_NFI		      50
-#define CLK_INFRA_SPINFI	      51
-#define CLK_INFRA_66M_NFI_HCK	      52
-#define CLK_INFRA_104M_SPI0	      53
-#define CLK_INFRA_104M_SPI1	      54
-#define CLK_INFRA_104M_SPI2_BCK	      55
-#define CLK_INFRA_66M_SPI0_HCK	      56
-#define CLK_INFRA_66M_SPI1_HCK	      57
-#define CLK_INFRA_66M_SPI2_HCK	      58
-#define CLK_INFRA_66M_FLASHIF_AXI     59
-#define CLK_INFRA_RTC		      60
-#define CLK_INFRA_26M_ADC_BCK	      61
-#define CLK_INFRA_RC_ADC	      62
-#define CLK_INFRA_MSDC400	      63
-#define CLK_INFRA_MSDC2_HCK	      64
-#define CLK_INFRA_133M_MSDC_0_HCK     65
-#define CLK_INFRA_66M_MSDC_0_HCK      66
-#define CLK_INFRA_133M_CPUM_BCK	      67
-#define CLK_INFRA_BIST2FPC	      68
-#define CLK_INFRA_I2C_X16W_MCK_CK_P1  69
-#define CLK_INFRA_I2C_X16W_PCK_CK_P1  70
-#define CLK_INFRA_133M_USB_HCK	      71
-#define CLK_INFRA_133M_USB_HCK_CK_P1  72
-#define CLK_INFRA_66M_USB_HCK	      73
-#define CLK_INFRA_66M_USB_HCK_CK_P1   74
-#define CLK_INFRA_USB_SYS	      75
-#define CLK_INFRA_USB_SYS_CK_P1	      76
-#define CLK_INFRA_USB_REF	      77
-#define CLK_INFRA_USB_CK_P1	      78
-#define CLK_INFRA_USB_FRMCNT	      79
-#define CLK_INFRA_USB_FRMCNT_CK_P1    80
-#define CLK_INFRA_USB_PIPE	      81
-#define CLK_INFRA_USB_PIPE_CK_P1      82
-#define CLK_INFRA_USB_UTMI	      83
-#define CLK_INFRA_USB_UTMI_CK_P1      84
-#define CLK_INFRA_USB_XHCI	      85
-#define CLK_INFRA_USB_XHCI_CK_P1      86
-#define CLK_INFRA_PCIE_GFMUX_TL_P0    87
-#define CLK_INFRA_PCIE_GFMUX_TL_P1    88
-#define CLK_INFRA_PCIE_GFMUX_TL_P2    89
-#define CLK_INFRA_PCIE_GFMUX_TL_P3    90
-#define CLK_INFRA_PCIE_PIPE_P0	      91
-#define CLK_INFRA_PCIE_PIPE_P1	      92
-#define CLK_INFRA_PCIE_PIPE_P2	      93
-#define CLK_INFRA_PCIE_PIPE_P3	      94
-#define CLK_INFRA_133M_PCIE_CK_P0     95
-#define CLK_INFRA_133M_PCIE_CK_P1     96
-#define CLK_INFRA_133M_PCIE_CK_P2     97
-#define CLK_INFRA_133M_PCIE_CK_P3     98
-
-/* ETHDMA */
-
-#define CLK_ETHDMA_XGP1_EN   0
-#define CLK_ETHDMA_XGP2_EN   1
-#define CLK_ETHDMA_XGP3_EN   2
-#define CLK_ETHDMA_FE_EN     3
-#define CLK_ETHDMA_GP2_EN    4
-#define CLK_ETHDMA_GP1_EN    5
-#define CLK_ETHDMA_GP3_EN    6
-#define CLK_ETHDMA_ESW_EN    7
-#define CLK_ETHDMA_CRYPT0_EN 8
-#define CLK_ETHDMA_NR_CLK    9
-
-/* SGMIISYS_0 */
-
-#define CLK_SGM0_TX_EN	  0
-#define CLK_SGM0_RX_EN	  1
-#define CLK_SGMII0_NR_CLK 2
-
-/* SGMIISYS_1 */
-
-#define CLK_SGM1_TX_EN	  0
-#define CLK_SGM1_RX_EN	  1
-#define CLK_SGMII1_NR_CLK 2
-
-/* ETHWARP */
-
-#define CLK_ETHWARP_WOCPU2_EN 0
-#define CLK_ETHWARP_WOCPU1_EN 1
-#define CLK_ETHWARP_WOCPU0_EN 2
-#define CLK_ETHWARP_NR_CLK    3
-
-#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/target/linux/generic/files/block/partitions/fit.c b/target/linux/mediatek/files/block/partitions/fit.c
similarity index 98%
rename from target/linux/generic/files/block/partitions/fit.c
rename to target/linux/mediatek/files/block/partitions/fit.c
index 91b25e0581..463cd4e9ab 100644
--- a/target/linux/generic/files/block/partitions/fit.c
+++ b/target/linux/mediatek/files/block/partitions/fit.c
@@ -144,6 +144,10 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector,
 
 	np = of_find_node_by_path("/chosen");
 	if (np) {
+		/* new fitblk driver should take over if /chosen/rootdisk is defined */
+		if (of_get_property(np, "rootdisk", NULL))
+			return 0;
+
 		bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
 		if (bootconf_c && bootconf_len)
 			bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
diff --git a/target/linux/mediatek/files/drivers/net/phy/air_en8811h.h b/target/linux/mediatek/files/drivers/net/phy/air_en8811h.h
deleted file mode 100644
index fd05577597..0000000000
--- a/target/linux/mediatek/files/drivers/net/phy/air_en8811h.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*************************************************
- * FILE NAME:  air_en8811h.h
- * PURPOSE:
- *      EN8811H PHY Driver for Linux
- * NOTES:
- *
- *  Copyright (C) 2023 Airoha Technology Corp.
- *************************************************/
-#ifndef __EN8811H_H
-#define __EN8811H_H
-
-#define EN8811H_PHY_ID1             0x03a2
-#define EN8811H_PHY_ID2             0xa411
-#define EN8811H_PHY_ID              ((EN8811H_PHY_ID1 << 16) | EN8811H_PHY_ID2)
-#define EN8811H_PHY_READY           0x02
-#define MAX_RETRY                   25
-
-#define EN8811H_TX_POL_NORMAL   0x1
-#define EN8811H_TX_POL_REVERSE  0x0
-
-#define EN8811H_RX_POL_NORMAL   (0x0 << 1)
-#define EN8811H_RX_POL_REVERSE  (0x1 << 1)
-
-
-/***************************************************************
- * The following led_cfg example is for reference only.
- * LED0 Link 2500/Blink 2500 TxRx   (GPIO5)    <-> BASE_T_LED0,
- * LED1 Link 1000/Blink 1000 TxRx   (GPIO4)    <-> BASE_T_LED1,
- * LED2 Link 100 /Blink 100  TxRx   (GPIO3)    <-> BASE_T_LED2,
- ***************************************************************/
-/* User-defined.B */
-#define AIR_LED0_ON     (LED_ON_EVT_LINK_2500M)
-#define AIR_LED0_BLK    (LED_BLK_EVT_2500M_TX_ACT | LED_BLK_EVT_2500M_RX_ACT)
-#define AIR_LED1_ON     (LED_ON_EVT_LINK_1000M)
-#define AIR_LED1_BLK    (LED_BLK_EVT_1000M_TX_ACT | LED_BLK_EVT_1000M_RX_ACT)
-#define AIR_LED2_ON     (LED_ON_EVT_LINK_100M)
-#define AIR_LED2_BLK    (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT)
-/* User-defined.E */
-
-/* CL45 MDIO control */
-#define MII_MMD_ACC_CTL_REG         0x0d
-#define MII_MMD_ADDR_DATA_REG       0x0e
-#define MMD_OP_MODE_DATA            BIT(14)
-
-#define EN8811H_DRIVER_VERSION      "v1.2.4"
-
-#define LED_ON_CTRL(i)              (0x024 + ((i)*2))
-#define LED_ON_EN                   (1 << 15)
-#define LED_ON_POL                  (1 << 14)
-#define LED_ON_EVT_MASK             (0x1ff)
-/* LED ON Event Option.B */
-#define LED_ON_EVT_LINK_2500M       (1 << 8)
-#define LED_ON_EVT_FORCE            (1 << 6)
-#define LED_ON_EVT_LINK_DOWN        (1 << 3)
-#define LED_ON_EVT_LINK_100M        (1 << 1)
-#define LED_ON_EVT_LINK_1000M       (1 << 0)
-/* LED ON Event Option.E */
-
-#define LED_BLK_CTRL(i)             (0x025 + ((i)*2))
-#define LED_BLK_EVT_MASK            (0xfff)
-/* LED Blinking Event Option.B*/
-#define LED_BLK_EVT_2500M_RX_ACT    (1 << 11)
-#define LED_BLK_EVT_2500M_TX_ACT    (1 << 10)
-#define LED_BLK_EVT_FORCE           (1 << 9)
-#define LED_BLK_EVT_100M_RX_ACT     (1 << 3)
-#define LED_BLK_EVT_100M_TX_ACT     (1 << 2)
-#define LED_BLK_EVT_1000M_RX_ACT    (1 << 1)
-#define LED_BLK_EVT_1000M_TX_ACT    (1 << 0)
-/* LED Blinking Event Option.E*/
-#define EN8811H_LED_COUNT           3
-
-#define LED_BCR                     (0x021)
-#define LED_BCR_EXT_CTRL            (1 << 15)
-#define LED_BCR_CLK_EN              (1 << 3)
-#define LED_BCR_TIME_TEST           (1 << 2)
-#define LED_BCR_MODE_MASK           (3)
-#define LED_BCR_MODE_DISABLE        (0)
-
-#define LED_ON_DUR                  (0x022)
-#define LED_ON_DUR_MASK             (0xffff)
-
-#define LED_BLK_DUR                 (0x023)
-#define LED_BLK_DUR_MASK            (0xffff)
-
-#define UNIT_LED_BLINK_DURATION     1024
-
-#define GET_BIT(val, bit) ((val & BIT(bit)) >> bit)
-
-#define INVALID_DATA                0xffff
-#define PBUS_INVALID_DATA           0xffffffff
-
-struct en8811h_priv {
-	struct dentry       *debugfs_root;
-	unsigned int        dm_crc32;
-	unsigned int        dsp_crc32;
-	char                buf[512];
-	int                 pol;
-};
-
-struct air_base_t_led_cfg {
-	u16 en;
-	u16 gpio;
-	u16 pol;
-	u16 on_cfg;
-	u16 blk_cfg;
-};
-enum air_led_gpio {
-	AIR_LED2_GPIO3 = 3,
-	AIR_LED1_GPIO4,
-	AIR_LED0_GPIO5,
-	AIR_LED_LAST
-};
-
-enum air_base_t_led {
-	AIR_BASE_T_LED0,
-	AIR_BASE_T_LED1,
-	AIR_BASE_T_LED2,
-	AIR_BASE_T_LED3
-};
-
-enum air_led_blk_dur {
-	AIR_LED_BLK_DUR_32M,
-	AIR_LED_BLK_DUR_64M,
-	AIR_LED_BLK_DUR_128M,
-	AIR_LED_BLK_DUR_256M,
-	AIR_LED_BLK_DUR_512M,
-	AIR_LED_BLK_DUR_1024M,
-	AIR_LED_BLK_DUR_LAST
-};
-
-enum air_led_polarity {
-	AIR_ACTIVE_LOW,
-	AIR_ACTIVE_HIGH,
-};
-enum air_led_mode {
-	AIR_LED_MODE_DISABLE,
-	AIR_LED_MODE_USER_DEFINE,
-	AIR_LED_MODE_LAST
-};
-
-#endif /* End of __EN8811H_H */
diff --git a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_api.c b/target/linux/mediatek/files/drivers/net/phy/air_en8811h_api.c
deleted file mode 100644
index a73bcee534..0000000000
--- a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_api.c
+++ /dev/null
@@ -1,1419 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*************************************************
- * FILE NAME:  air_en8811h_api.c
- * PURPOSE:
- *      EN8811H PHY Driver for Linux
- * NOTES:
- *
- *  Copyright (C) 2023 Airoha Technology Corp.
- *************************************************/
-
-/* INCLUDE FILE DECLARATIONS
-*/
-#include <linux/uaccess.h>
-#include <linux/trace_seq.h>
-#include <linux/seq_file.h>
-#include <linux/u64_stats_sync.h>
-#include <linux/dma-mapping.h>
-#include <linux/netdevice.h>
-#include <linux/ctype.h>
-#include <linux/of_mdio.h>
-#include <linux/of_address.h>
-#include <linux/mii.h>
-#include <linux/phy.h>
-#include <linux/debugfs.h>
-
-#include "air_en8811h.h"
-#include "air_en8811h_api.h"
-
-/*
-struct air_phy_debug {
-	struct dentry *root;
-};
-struct air_phy_debug air_debug;
-*/
-
-static const char * const tx_rx_string[32] = {
-	"Tx Reverse, Rx Normal",
-	"Tx Normal, Rx Normal",
-	"Tx Reverse, Rx Reverse",
-	"Tx Normal, Rx Reverse",
-};
-
-/* Airoha MII read function */
-static int __air_mii_cl22_read(struct mii_bus *ebus,
-					int addr, unsigned int phy_register)
-{
-	int read_data;
-#if (KERNEL_VERSION(4, 16, 0) < LINUX_VERSION_CODE)
-	read_data = __mdiobus_read(ebus, addr, phy_register);
-#else
-	read_data = ebus->read(ebus, addr, phy_register);
-#endif
-	return read_data;
-}
-/* Airoha MII write function */
-static int __air_mii_cl22_write(struct mii_bus *ebus, int addr,
-			unsigned int phy_register, unsigned int write_data)
-{
-	int ret = 0;
-#if (KERNEL_VERSION(4, 16, 0) < LINUX_VERSION_CODE)
-	ret = __mdiobus_write(ebus, addr, phy_register, write_data);
-#else
-	ret = ebus->write(ebus, addr, phy_register, write_data);
-#endif
-	return ret;
-}
-
-/* Airoha MII read function */
-int air_mii_cl22_read(struct mii_bus *ebus, int addr, unsigned int phy_register)
-{
-	int read_data;
-
-	mutex_lock(&ebus->mdio_lock);
-	read_data = __air_mii_cl22_read(ebus, addr, phy_register);
-	mutex_unlock(&ebus->mdio_lock);
-	return read_data;
-}
-/* Airoha MII write function */
-int air_mii_cl22_write(struct mii_bus *ebus, int addr,
-			unsigned int phy_register, unsigned int write_data)
-{
-	int ret = 0;
-
-	mutex_lock(&ebus->mdio_lock);
-	ret = __air_mii_cl22_write(ebus, addr, phy_register, write_data);
-	mutex_unlock(&ebus->mdio_lock);
-	return ret;
-}
-
-int __air_mii_cl45_read(struct phy_device *phydev, int devad, u16 reg)
-{
-	int ret = 0;
-	int data;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	ret |= __air_mii_cl22_write(mbus, addr, MII_MMD_ACC_CTL_REG, devad);
-	ret |= __air_mii_cl22_write(mbus, addr, MII_MMD_ADDR_DATA_REG, reg);
-	ret |= __air_mii_cl22_write(mbus, addr,
-			MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
-	if (ret) {
-		dev_err(dev, "__air_mii_cl22_write, ret: %d\n", ret);
-		return INVALID_DATA;
-	}
-	data = __air_mii_cl22_read(mbus, addr, MII_MMD_ADDR_DATA_REG);
-	return data;
-}
-
-int __air_mii_cl45_write(struct phy_device *phydev,
-					int devad, u16 reg, u16 write_data)
-{
-	int ret = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	ret |= __air_mii_cl22_write(mbus, addr, MII_MMD_ACC_CTL_REG, devad);
-	ret |= __air_mii_cl22_write(mbus, addr, MII_MMD_ADDR_DATA_REG, reg);
-	ret |= __air_mii_cl22_write(mbus, addr,
-		MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
-	ret |= __air_mii_cl22_write(mbus, addr,
-			MII_MMD_ADDR_DATA_REG, write_data);
-	if (ret) {
-		dev_err(dev, "__air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-	return 0;
-}
-
-int air_mii_cl45_read(struct phy_device *phydev, int devad, u16 reg)
-{
-	int data;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-
-	mutex_lock(&mbus->mdio_lock);
-	data = __air_mii_cl45_read(phydev, devad, reg);
-	mutex_unlock(&mbus->mdio_lock);
-	if (data == INVALID_DATA) {
-		dev_err(dev, "__airoha_cl45_read fail\n");
-		return INVALID_DATA;
-	}
-	return data;
-}
-
-int air_mii_cl45_write(struct phy_device *phydev,
-				int devad, u16 reg, u16 write_data)
-{
-	int ret = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-
-	mutex_lock(&mbus->mdio_lock);
-	ret |= __air_mii_cl45_write(phydev, devad, reg, write_data);
-	mutex_unlock(&mbus->mdio_lock);
-	if (ret) {
-		dev_err(dev, "__airoha_cl45_write, ret: %d\n", ret);
-		return ret;
-	}
-	return ret;
-}
-
-/* EN8811H PBUS read function */
-static unsigned int __air_pbus_reg_read(struct phy_device *phydev,
-		unsigned int pbus_address)
-{
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-	struct device *dev = phydev_dev(phydev);
-	unsigned int pbus_data_low, pbus_data_high;
-	unsigned int pbus_data;
-	int ret = 0;
-
-	ret |= __air_mii_cl22_write(mbus, (addr + 8),
-			0x1F, (pbus_address >> 6));
-	pbus_data_low = __air_mii_cl22_read(mbus, (addr + 8),
-				((pbus_address >> 2) & 0xf));
-	pbus_data_high = __air_mii_cl22_read(mbus, (addr + 8), 0x10);
-	pbus_data = (pbus_data_high << 16) + pbus_data_low;
-	if (ret) {
-		dev_err(dev, "%s: ret: %d\n", __func__, ret);
-		return ret;
-	}
-	return pbus_data;
-}
-
-unsigned int air_pbus_reg_read(struct phy_device *phydev,
-		unsigned int pbus_address)
-{
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	struct device *dev = phydev_dev(phydev);
-	int ret = 0;
-	unsigned int data;
-
-	mutex_lock(&mbus->mdio_lock);
-	data = __air_pbus_reg_read(phydev, pbus_address);
-	mutex_unlock(&mbus->mdio_lock);
-	if (ret) {
-		dev_err(dev, "%s: ret: %d\n", __func__, ret);
-		return ret;
-	}
-	return data;
-}
-
-/* EN8811H PBUS write function */
-static int __air_pbus_reg_write(struct phy_device *phydev,
-		unsigned int pbus_address, unsigned long pbus_data)
-{
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-	struct device *dev = phydev_dev(phydev);
-	int ret = 0;
-
-	ret |= __air_mii_cl22_write(mbus, (addr + 8),
-			0x1F, (pbus_address >> 6));
-	ret |= __air_mii_cl22_write(mbus, (addr + 8),
-			((pbus_address >> 2) & 0xf), (pbus_data & 0xFFFF));
-	ret |= __air_mii_cl22_write(mbus, (addr + 8),
-			0x10, (pbus_data >> 16));
-	if (ret) {
-		dev_err(dev, "%s: ret: %d\n", __func__, ret);
-		return ret;
-	}
-	return 0;
-}
-
-int air_pbus_reg_write(struct phy_device *phydev,
-		unsigned int pbus_address, unsigned int pbus_data)
-{
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	struct device *dev = phydev_dev(phydev);
-	int ret = 0;
-
-	mutex_lock(&mbus->mdio_lock);
-	ret |= __air_pbus_reg_write(phydev, pbus_address, pbus_data);
-	mutex_unlock(&mbus->mdio_lock);
-	if (ret) {
-		dev_err(dev, "%s: ret: %d\n", __func__, ret);
-		return ret;
-	}
-	return 0;
-}
-/* EN8811H BUCK write function */
-static int __air_buckpbus_reg_write(struct phy_device *phydev,
-			unsigned int pbus_address, unsigned int pbus_data)
-{
-	int ret = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	/* page 4 */
-	ret |= __air_mii_cl22_write(mbus, addr, 0x1F, 4);
-	ret |= __air_mii_cl22_write(mbus, addr, 0x10, 0);
-	ret |= __air_mii_cl22_write(mbus, addr,
-			0x11, ((pbus_address >> 16) & 0xffff));
-	ret |= __air_mii_cl22_write(mbus, addr,
-			0x12, (pbus_address & 0xffff));
-	ret |= __air_mii_cl22_write(mbus, addr,
-			0x13, ((pbus_data >> 16) & 0xffff));
-	ret |= __air_mii_cl22_write(mbus, addr, 0x14, (pbus_data & 0xffff));
-	ret |= __air_mii_cl22_write(mbus, addr, 0x1F, 0);
-	if (ret < 0) {
-		dev_err(dev, "__air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-	return 0;
-}
-
-/* EN8811H BUCK read function */
-static unsigned int __air_buckpbus_reg_read(struct phy_device *phydev,
-			unsigned int pbus_address)
-{
-	unsigned int pbus_data = 0, pbus_data_low, pbus_data_high;
-	int ret = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	/* page 4 */
-	ret |= __air_mii_cl22_write(mbus, addr, 0x1F, 4);
-	ret |= __air_mii_cl22_write(mbus, addr, 0x10, 0);
-	ret |= __air_mii_cl22_write(mbus, addr,
-			0x15, ((pbus_address >> 16) & 0xffff));
-	ret |= __air_mii_cl22_write(mbus, addr,
-			0x16, (pbus_address & 0xffff));
-	if (ret) {
-		dev_err(dev, "__air_mii_cl22_write, ret: %d\n", ret);
-		return PBUS_INVALID_DATA;
-	}
-
-	pbus_data_high = __air_mii_cl22_read(mbus, addr, 0x17);
-	pbus_data_low = __air_mii_cl22_read(mbus, addr, 0x18);
-	pbus_data = (pbus_data_high << 16) + pbus_data_low;
-	ret |= __air_mii_cl22_write(mbus, addr, 0x1F, 0);
-	if (ret) {
-		dev_err(dev, "__air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-	return pbus_data;
-}
-
-unsigned int air_buckpbus_reg_read(struct phy_device *phydev,
-			unsigned int pbus_address)
-{
-	unsigned int data;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-
-	mutex_lock(&mbus->mdio_lock);
-	data = __air_buckpbus_reg_read(phydev, pbus_address);
-	mutex_unlock(&mbus->mdio_lock);
-	if (data == INVALID_DATA) {
-		dev_err(dev, "__air_buckpbus_reg_read fail\n");
-		return INVALID_DATA;
-	}
-	return data;
-}
-
-int air_buckpbus_reg_write(struct phy_device *phydev,
-		unsigned int pbus_address, unsigned int pbus_data)
-{
-	int ret = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-
-	mutex_lock(&mbus->mdio_lock);
-	ret |= __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
-	mutex_unlock(&mbus->mdio_lock);
-	if (ret) {
-		dev_err(dev, "__air_buckpbus_reg_write, ret: %d\n", ret);
-		return ret;
-	}
-	return ret;
-}
-#if defined(CONFIG_OF)
-int en8811h_of_init(struct phy_device *phydev)
-{
-	struct device *dev = phydev_dev(phydev);
-	struct device_node *of_node = dev->of_node;
-	struct en8811h_priv *priv = phydev->priv;
-	u32 val = 0;
-
-	dev_info(dev, "%s: start\n", __func__);
-	if (of_find_property(of_node, "airoha,polarity", NULL)) {
-		if (of_property_read_u32(of_node, "airoha,polarity",
-					 &val) != 0) {
-			phydev_err(phydev, "airoha,polarity value is invalid.");
-			return -EINVAL;
-		}
-		if (val < AIR_POL_TX_REV_RX_NOR ||
-		    val > AIR_POL_TX_NOR_RX_REV) {
-			phydev_err(phydev,
-				   "airoha,polarity value %u out of range.",
-				   val);
-			return -EINVAL;
-		}
-		priv->pol = val;
-	} else
-		priv->pol = AIR_POL_TX_NOR_RX_NOR;
-
-	return 0;
-}
-#else
-int en8811h_of_init(struct phy_device *phydev)
-{
-	return -ESRCH;
-}
-#endif /* CONFIG_OF */
-
-static int air_resolve_an_speed(struct phy_device *phydev)
-{
-	int lpagb = 0, advgb = 0, common_adv_gb = 0;
-	int lpa = 0, adv = 0, common_adv = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	dev_dbg(dev, "AN mode!\n");
-	dev_dbg(dev, "SPEED 1000/100!\n");
-	lpagb = air_mii_cl22_read(mbus,
-				addr, MII_STAT1000);
-	if (lpagb < 0)
-		return lpagb;
-	advgb = air_mii_cl22_read(mbus,
-				addr, MII_CTRL1000);
-	if (adv < 0)
-		return adv;
-	common_adv_gb = (lpagb & (advgb << 2));
-
-	lpa = air_mii_cl22_read(mbus, addr, MII_LPA);
-	if (lpa < 0)
-		return lpa;
-	adv = air_mii_cl22_read(mbus,
-				addr, MII_ADVERTISE);
-	if (adv < 0)
-		return adv;
-	phydev->pause = GET_BIT(adv, 10);
-	phydev->asym_pause = GET_BIT(adv, 11);
-	common_adv = (lpa & adv);
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_HALF;
-	if (common_adv_gb & (LPA_1000FULL | LPA_1000HALF)) {
-		phydev->speed = SPEED_1000;
-		if (common_adv_gb & LPA_1000FULL)
-			phydev->duplex = DUPLEX_FULL;
-	} else if (common_adv & (LPA_100FULL | LPA_100HALF)) {
-		phydev->speed = SPEED_100;
-		if (common_adv & LPA_100FULL)
-			phydev->duplex = DUPLEX_FULL;
-	} else {
-		if (common_adv & LPA_10FULL)
-			phydev->duplex = DUPLEX_FULL;
-	}
-	return 0;
-}
-
-int air_get_autonego(struct phy_device *phydev, int *an)
-{
-	int reg;
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	reg = air_mii_cl22_read(mbus, addr, MII_BMCR);
-	if (reg < 0)
-		return -EINVAL;
-	if (reg & BMCR_ANENABLE)
-		*an = AUTONEG_ENABLE;
-	else
-		*an = AUTONEG_DISABLE;
-	return 0;
-}
-
-static int air_read_status(struct phy_device *phydev)
-{
-	int ret = 0, reg = 0, an = AUTONEG_DISABLE, bmcr = 0;
-	u32 pbus_value = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_UNKNOWN;
-	phydev->pause = 0;
-	phydev->asym_pause = 0;
-	phydev->link = 0;
-	phydev->autoneg = AUTONEG_DISABLE;
-	reg = air_mii_cl22_read(mbus, addr, MII_BMSR);
-	if (reg < 0) {
-		dev_err(dev, "MII_BMSR reg %d!\n", reg);
-		return reg;
-	}
-	reg = air_mii_cl22_read(mbus, addr, MII_BMSR);
-	if (reg < 0) {
-		dev_err(dev, "MII_BMSR reg %d!\n", reg);
-		return reg;
-	}
-	if (reg & BMSR_LSTATUS) {
-		phydev->link = 1;
-		ret = air_get_autonego(phydev, &an);
-		if (ret < 0)
-			return ret;
-		phydev->autoneg = an;
-		pbus_value = air_buckpbus_reg_read(phydev, 0x109D4);
-		if (0x10 & pbus_value) {
-			phydev->speed = SPEED_2500;
-			phydev->duplex = DUPLEX_FULL;
-		} else {
-			ret = air_get_autonego(phydev, &an);
-			if (phydev->autoneg == AUTONEG_ENABLE) {
-				ret = air_resolve_an_speed(phydev);
-				if (ret < 0)
-					return ret;
-			} else {
-				dev_dbg(dev, "Force mode!\n");
-				bmcr = air_mii_cl22_read(mbus, addr, MII_BMCR);
-
-				if (bmcr < 0)
-					return bmcr;
-
-				if (bmcr & BMCR_FULLDPLX)
-					phydev->duplex = DUPLEX_FULL;
-				else
-					phydev->duplex = DUPLEX_HALF;
-
-				if (bmcr & BMCR_SPEED1000)
-					phydev->speed = SPEED_1000;
-				else if (bmcr & BMCR_SPEED100)
-					phydev->speed = SPEED_100;
-				else
-					phydev->speed = SPEED_UNKNOWN;
-			}
-		}
-	}
-
-	return ret;
-}
-#ifdef CONFIG_AIROHA_EN8811H_PHY_DEBUGFS
-static void air_polarity_help(void)
-{
-	pr_notice("\nUsage:\n"
-			"[debugfs] = /sys/kernel/debug/mdio-bus\':[phy_addr]\n"
-			"echo [tx polarity] [rx polarity] > /[debugfs]/polarity\n"
-			"option: tx_normal, tx_reverse, rx_normal, rx_revers\n");
-}
-
-static int air_set_polarity(struct phy_device *phydev, int tx_rx)
-{
-	int ret = 0;
-	unsigned int pbus_data = 0;
-
-	pr_debug("\nPolarit %s\n", tx_rx_string[tx_rx]);
-	pbus_data = air_buckpbus_reg_read(phydev, 0xca0f8) & ~(BIT(0) | BIT(1));
-	pbus_data |= tx_rx;
-	ret = air_buckpbus_reg_write(phydev, 0xca0f8, pbus_data);
-	if (ret < 0)
-		pr_notice("\n%s:air_buckpbus_reg_write fail\n", __func__);
-	pbus_data = air_buckpbus_reg_read(phydev, 0xca0f8);
-	pr_notice("\nPolarity %s confirm....(%02lx)\n",
-			tx_rx_string[tx_rx], pbus_data & (BIT(0) | BIT(1)));
-
-	return ret;
-}
-
-static int air_set_mode(struct phy_device *phydev, int dbg_mode)
-{
-	int ret = 0, val = 0;
-	unsigned int pbus_data = 0;
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	switch (dbg_mode) {
-	case AIR_PORT_MODE_FORCE_100:
-		pr_notice("\nForce 100M\n");
-		val = air_mii_cl22_read(mbus, addr, MII_ADVERTISE) | BIT(8);
-		ret = air_mii_cl22_write(mbus, addr, MII_ADVERTISE, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_CTRL1000) & ~BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_CTRL1000, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl45_read(phydev, 0x7, 0x20) & ~BIT(7);
-		ret = air_mii_cl45_write(phydev, 0x7, 0x20, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_BMCR) | BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_BMCR, val);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	case AIR_PORT_MODE_FORCE_1000:
-		pr_notice("\nForce 1000M\n");
-		val = air_mii_cl22_read(mbus, addr, MII_ADVERTISE) & ~BIT(8);
-		ret = air_mii_cl22_write(mbus, addr, MII_ADVERTISE, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_CTRL1000) | BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_CTRL1000, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl45_read(phydev, 0x7, 0x20) & ~BIT(7);
-		ret = air_mii_cl45_write(phydev, 0x7, 0x20, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_BMCR) | BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_BMCR, val);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	case AIR_PORT_MODE_FORCE_2500:
-		pr_notice("\nForce 2500M\n");
-		val = air_mii_cl22_read(mbus, addr, MII_ADVERTISE) & ~BIT(8);
-		ret = air_mii_cl22_write(mbus, addr, MII_ADVERTISE, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_CTRL1000) & ~BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_CTRL1000, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl45_read(phydev, 0x7, 0x20) | BIT(7);
-		ret = air_mii_cl45_write(phydev, 0x7, 0x20, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_BMCR) | BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_BMCR, val);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	case AIR_PORT_MODE_AUTONEGO:
-		pr_notice("\nAutonego mode\n");
-		val = air_mii_cl22_read(mbus, addr, MII_ADVERTISE) | BIT(8);
-		ret = air_mii_cl22_write(mbus, addr, MII_ADVERTISE, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_CTRL1000) | BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_CTRL1000, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl45_read(phydev, 0x7, 0x20) | BIT(7);
-		ret = air_mii_cl45_write(phydev, 0x7, 0x20, val);
-		if (unlikely(ret < 0))
-			break;
-		val = air_mii_cl22_read(mbus, addr, MII_BMCR) | BIT(9);
-		ret = air_mii_cl22_write(mbus, addr, MII_BMCR, val);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	case AIR_PORT_MODE_POWER_DOWN:
-		pr_notice("\nPower Down\n");
-		val = air_mii_cl22_read(mbus, addr, MII_BMCR) | BIT(11);
-		ret = air_mii_cl22_write(mbus, addr, MII_BMCR, val);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	case AIR_PORT_MODE_POWER_UP:
-		pr_notice("\nPower Up\n");
-		val = air_mii_cl22_read(mbus, addr, MII_BMCR) & ~BIT(11);
-		ret = air_mii_cl22_write(mbus, addr, MII_BMCR, val);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	case AIR_PORT_MODE_SSC_DISABLE:
-		pr_notice("\nSSC Disabled\n");
-		pbus_data = air_buckpbus_reg_read(phydev, 0xca000);
-		pbus_data &= ~BIT(21);
-		ret = air_buckpbus_reg_write(phydev, 0xca000, pbus_data);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	case AIR_PORT_MODE_SSC_ENABLE:
-		pr_notice("\nSSC Enabled\n");
-		pbus_data = air_buckpbus_reg_read(phydev, 0xca000);
-		pbus_data |= BIT(21);
-		ret = air_buckpbus_reg_write(phydev, 0xca000, pbus_data);
-		if (unlikely(ret < 0))
-			break;
-		break;
-	default:
-		pr_notice("\nWrong Port mode\n");
-		break;
-	}
-	return ret;
-}
-
-static int airphy_info_show(struct seq_file *seq, void *v)
-{
-	struct phy_device *phydev = seq->private;
-	struct en8811h_priv *priv = phydev->priv;
-	unsigned int val = 0;
-
-	seq_puts(seq, "<<AIR EN8811H Driver info>>\n");
-	seq_printf(seq, "| Driver Version       : %s\n",
-							EN8811H_DRIVER_VERSION);
-	val = air_buckpbus_reg_read(phydev, 0xcf914);
-	seq_printf(seq, "| Boot mode            : %s\n",
-		((val & BIT(24)) >> 24) ? "Flash" : "Download Code");
-	seq_printf(seq, "| EthMD32.dm.bin  CRC32: %08x\n",
-				priv->dm_crc32);
-	seq_printf(seq, "| EthMD32.DSP.bin CRC32: %08x\n",
-				priv->dsp_crc32);
-	val = air_buckpbus_reg_read(phydev, 0x3b3c);
-	seq_printf(seq, "| MD32 FW Version      : %08x\n", val);
-	val = air_mii_cl45_read(phydev, 0x1e, 0x8009);
-	seq_printf(seq, "| MD32 FW Status       : %08x\n",
-				air_mii_cl45_read(phydev, 0x1e, 0x8009));
-	val = (air_buckpbus_reg_read(phydev, 0xca0f8) & 0x3);
-	seq_printf(seq, "| Tx, Rx Polarity      : %s(%02d)\n",
-						tx_rx_string[val], val);
-	seq_puts(seq, "\n");
-
-	return 0;
-}
-
-static int airphy_info_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, airphy_info_show, inode->i_private);
-}
-
-static int airphy_fcm_counter_show(struct phy_device *phydev,
-				struct seq_file *seq)
-{
-	int ret = 0;
-	u32 pkt_cnt = 0;
-
-	seq_puts(seq, "|\t<<FCM Counter>>\n");
-	seq_puts(seq, "| Rx from Line side_S      :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe0090);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| Rx from Line side_T      :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe0094);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| Tx to System side_S      :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe009c);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| Tx to System side_T      :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe00A0);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| Rx from System side_S    :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe0078);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| Rx from System side_T    :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe007C);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| Tx to Line side_S        :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe0084);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| Tx to Line side_T        :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xe0088);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	ret = air_buckpbus_reg_write(phydev, 0xe0074, 0xf);
-	if (ret < 0)
-		return ret;
-	return 0;
-}
-
-static int airphy_ss_counter_show(struct phy_device *phydev,
-				struct seq_file *seq)
-{
-	int ret = 0;
-	u32 pkt_cnt = 0;
-
-	seq_puts(seq, "|\t<<SS Counter>>\n");
-	ret = air_buckpbus_reg_write(phydev, 0xC602C, 0x3);
-	if (ret < 0)
-		return ret;
-	seq_puts(seq, "| TX Start                 :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xC60B0);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| TX Terminal              :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xC60B4);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| RX Start                 :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xC60BC);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	seq_puts(seq, "| RX Terminal              :");
-	pkt_cnt = air_buckpbus_reg_read(phydev, 0xC60C0);
-	seq_printf(seq, "%010u |\n", pkt_cnt);
-	ret = air_buckpbus_reg_write(phydev, 0xC602C, 0x4);
-	if (ret < 0)
-		return ret;
-	return 0;
-}
-
-static int airphy_counter_show(struct seq_file *seq, void *v)
-{
-	struct phy_device *phydev = seq->private;
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int ret = 0, addr = phydev_addr(phydev);
-	u32 pkt_cnt = 0;
-
-	ret = air_read_status(phydev);
-	if (ret < 0)
-		return ret;
-	seq_puts(seq, "==========AIR PHY COUNTER==========\n");
-	if (phydev->link) {
-		ret = airphy_ss_counter_show(phydev, seq);
-		if (ret < 0)
-			return ret;
-	}
-	ret = airphy_fcm_counter_show(phydev, seq);
-	if (ret < 0)
-		return ret;
-	if (phydev->link) {
-		seq_puts(seq, "|\t<<MAC Counter>>\n");
-		seq_puts(seq, "| Tx Error from System side:");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x131000);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx Error to System side  :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x132000);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Tx from System side      :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x131004);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx to System Side        :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x132004);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-	}
-	if (phydev->link && phydev->speed == SPEED_2500) {
-		seq_puts(seq, "|\t<<LS Counter>>\n");
-		ret = air_buckpbus_reg_write(phydev, 0x30718, 0x10);
-		if (ret < 0)
-			return ret;
-		ret = air_buckpbus_reg_write(phydev, 0x30718, 0x0);
-		if (ret < 0)
-			return ret;
-		seq_puts(seq, "|\tBefore EF\n");
-		seq_puts(seq, "| Tx to Line side_S        :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x3071c);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Tx to Line side_T        :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30720);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Tx_ENC                   :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30724);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx from Line side_S      :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x3072c);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx from Line side_T      :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30730);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx_DEC                   :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30728);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "|\tAfter EF\n");
-		seq_puts(seq, "| Tx to Line side_S        :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30734);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Tx to Line side_T        :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30738);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx from Line side_S      :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30764);
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx from Line side_T      :");
-		pkt_cnt = air_buckpbus_reg_read(phydev, 0x30768);
-		seq_printf(seq, "%010u |\n\n", pkt_cnt);
-		ret = air_buckpbus_reg_write(phydev, 0x30718, 0x13);
-		if (ret < 0)
-			return ret;
-		ret = air_buckpbus_reg_write(phydev, 0x30718, 0x3);
-		if (ret < 0)
-			return ret;
-		ret = air_buckpbus_reg_write(phydev, 0x30718, 0x10);
-		if (ret < 0)
-			return ret;
-		ret = air_buckpbus_reg_write(phydev, 0x30718, 0x0);
-		if (ret < 0)
-			return ret;
-	}
-	if (phydev->link && ((phydev->speed != SPEED_2500))) {
-		seq_puts(seq, "|\t<<LS Counter>>\n");
-		ret = air_mii_cl22_write(mbus, addr, 0x1f, 1);
-		if (ret < 0)
-			return ret;
-		seq_puts(seq, "| Rx from Line side        :");
-		pkt_cnt = air_mii_cl22_read(mbus, addr, 0x12) & 0x7fff;
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Rx Error from Line side  :");
-		pkt_cnt = air_mii_cl22_read(mbus, addr, 0x17) & 0xff;
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		ret = air_mii_cl22_write(mbus, addr, 0x1f, 0);
-		if (ret < 0)
-			return ret;
-		ret = air_mii_cl22_write(mbus, addr, 0x1f, 0x52B5);
-		if (ret < 0)
-			return ret;
-		ret = air_mii_cl22_write(mbus, addr, 0x10, 0xBF92);
-		if (ret < 0)
-			return ret;
-		seq_puts(seq, "| Tx to Line side          :");
-		pkt_cnt = (air_mii_cl22_read(mbus, addr, 0x11) & 0x7ffe) >> 1;
-		seq_printf(seq, "%010u |\n", pkt_cnt);
-		seq_puts(seq, "| Tx Error to Line side    :");
-		pkt_cnt = air_mii_cl22_read(mbus, addr, 0x12);
-		pkt_cnt &= 0x7f;
-		seq_printf(seq, "%010u |\n\n", pkt_cnt);
-		ret = air_mii_cl22_write(mbus, addr, 0x1f, 0);
-		if (ret < 0)
-			return ret;
-	}
-	return ret;
-}
-
-static int airphy_counter_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, airphy_counter_show, inode->i_private);
-}
-
-static ssize_t airphy_polarity_write(struct file *file, const char __user *ptr,
-					size_t len, loff_t *off)
-{
-	struct phy_device *phydev = file->private_data;
-	char buf[32], param1[32], param2[32];
-	int count = len, ret = 0, tx_rx = 0;
-
-	memset(buf, 0, 32);
-	memset(param1, 0, 32);
-	memset(param2, 0, 32);
-
-	if (count > sizeof(buf) - 1)
-		return -EINVAL;
-	if (copy_from_user(buf, ptr, len))
-		return -EFAULT;
-	if (sscanf(buf, "%s %s", param1, param2) == -1)
-		return -EFAULT;
-
-	if (!strncmp("tx_normal", param1, strlen("tx_normal"))) {
-		if (!strncmp("rx_normal", param2, strlen("rx_normal")))
-			tx_rx = AIR_POL_TX_NOR_RX_NOR;
-		else if (!strncmp("rx_reverse", param2, strlen("rx_reverse")))
-			tx_rx = AIR_POL_TX_NOR_RX_REV;
-		else {
-			pr_notice("\nRx param is not correct.\n");
-			return -EINVAL;
-		}
-	} else if (!strncmp("tx_reverse", param1, strlen("tx_reverse"))) {
-		if (!strncmp("rx_normal", param2, strlen("rx_normal")))
-			tx_rx = AIR_POL_TX_REV_RX_NOR;
-		else if (!strncmp("rx_reverse", param2, strlen("rx_reverse")))
-			tx_rx = AIR_POL_TX_REV_RX_REV;
-		else {
-			pr_notice("\nRx param is not correct.\n");
-			return -EINVAL;
-		}
-	} else {
-		air_polarity_help();
-		return count;
-	}
-	pr_notice("\nSet Polarity %s\n", tx_rx_string[tx_rx]);
-	ret = air_set_polarity(phydev, tx_rx);
-	if (ret < 0)
-		return ret;
-	return count;
-}
-static void airphy_port_mode_help(void)
-{
-	pr_notice("\nUsage:\n"
-			"[debugfs] = /sys/kernel/debug/mdio-bus\':[phy_addr]\n"
-			"echo [mode] [para] > /[debugfs]/port_mode\n"
-			"echo re-an > /[debugfs]/port_mode\n"
-			"echo auto > /[debugfs]/port_mode\n"
-			"echo 2500 > /[debugfs]/port_mode\n"
-			"echo 1000 > /[debugfs]/port_mode\n"
-			"echo 100 > /[debugfs]/port_mode\n"
-			"echo ssc ena/dis > /[debugfs]/port_mode\n"
-			"echo power up/down >  /[debugfs]/port_mode\n");
-}
-
-static ssize_t airphy_port_mode(struct file *file, const char __user *ptr,
-					size_t len, loff_t *off)
-{
-	struct phy_device *phydev = file->private_data;
-	char buf[32], cmd[32], param[32];
-	int count = len, ret = 0;
-	int num = 0, val = 0;
-
-	memset(buf, 0, 32);
-	memset(cmd, 0, 32);
-	memset(param, 0, 32);
-
-	if (count > sizeof(buf) - 1)
-		return -EINVAL;
-	if (copy_from_user(buf, ptr, len))
-		return -EFAULT;
-
-	num = sscanf(buf, "%s %s", cmd, param);
-	if (num < 1 || num > 3)
-		return -EFAULT;
-
-	if (!strncmp("auto", cmd, strlen("auto")))
-		ret = air_set_mode(phydev, AIR_PORT_MODE_AUTONEGO);
-	else if (!strncmp("2500", cmd, strlen("2500")))
-		ret = air_set_mode(phydev, AIR_PORT_MODE_FORCE_2500);
-	else if (!strncmp("1000", cmd, strlen("1000")))
-		ret = air_set_mode(phydev, AIR_PORT_MODE_FORCE_1000);
-	else if (!strncmp("100", cmd, strlen("100")))
-		ret = air_set_mode(phydev, AIR_PORT_MODE_FORCE_100);
-	else if (!strncmp("re-an", cmd, strlen("re-an"))) {
-		val = phy_read(phydev, MII_BMCR) | BIT(9);
-		ret = phy_write(phydev, MII_BMCR, val);
-	} else if (!strncmp("power", cmd, strlen("power"))) {
-		if (!strncmp("down", param, strlen("down")))
-			ret = air_set_mode(phydev, AIR_PORT_MODE_POWER_DOWN);
-		else if (!strncmp("up", param, strlen("up")))
-			ret = air_set_mode(phydev, AIR_PORT_MODE_POWER_UP);
-	} else if (!strncmp("ssc", cmd, strlen("ssc"))) {
-		if (!strncmp("dis", param, strlen("dis")))
-			ret = air_set_mode(phydev, AIR_PORT_MODE_SSC_DISABLE);
-		else if (!strncmp("ena", param, strlen("ena")))
-			ret = air_set_mode(phydev, AIR_PORT_MODE_SSC_ENABLE);
-	} else if (!strncmp("help", cmd, strlen("help"))) {
-		airphy_port_mode_help();
-	}
-
-	if (ret < 0)
-		return ret;
-
-	return count;
-}
-
-static void airphy_debugfs_buckpbus_help(void)
-{
-	pr_notice("\nUsage:\n"
-			"[debugfs] = /sys/kernel/debug/mdio-bus\':[phy_addr]\n"
-			"Read:\n"
-			"echo r [buckpbus_register] > /[debugfs]/buckpbus_op\n"
-			"Write:\n"
-			"echo w [buckpbus_register] [value] > /[debugfs]/buckpbus_op\n");
-}
-
-
-static ssize_t airphy_debugfs_buckpbus(struct file *file,
-					const char __user *buffer, size_t count,
-					loff_t *data)
-{
-	struct phy_device *phydev = file->private_data;
-	char buf[64];
-	int ret = 0;
-	unsigned int reg, val;
-
-	memset(buf, 0, 64);
-	if (count > sizeof(buf) - 1)
-		return -EINVAL;
-	if (copy_from_user(buf, buffer, count))
-		return -EFAULT;
-
-	if (buf[0] == 'w') {
-		if (sscanf(buf, "w %x %x", &reg, &val) == -1)
-			return -EFAULT;
-
-		pr_notice("\nphy=%d, reg=0x%x, val=0x%x\n",
-			phydev_addr(phydev), reg, val);
-		ret = air_buckpbus_reg_write(phydev, reg, val);
-		if (ret < 0) {
-			pr_notice("\nbuckpbus_reg_write fail\n");
-			return -EIO;
-		}
-		val = air_buckpbus_reg_read(phydev, reg);
-		pr_notice("\nphy=%d, reg=0x%x, val=0x%x confirm..\n",
-			phydev_addr(phydev), reg, val);
-	} else if (buf[0] == 'r') {
-		if (sscanf(buf, "r %x", &reg) == -1)
-			return -EFAULT;
-
-		val = air_buckpbus_reg_read(phydev, reg);
-		pr_notice("\nphy=%d, reg=0x%x, val=0x%x\n",
-		phydev_addr(phydev), reg, val);
-	} else
-		airphy_debugfs_buckpbus_help();
-
-	return count;
-}
-
-static ssize_t airphy_debugfs_pbus(struct file *file,
-					const char __user *buffer, size_t count,
-					loff_t *data)
-{
-	struct phy_device *phydev = file->private_data;
-	char buf[64];
-	int ret = 0;
-	unsigned int reg, val;
-
-	memset(buf, 0, 64);
-	if (copy_from_user(buf, buffer, count))
-		return -EFAULT;
-
-	if (buf[0] == 'w') {
-		if (sscanf(buf, "w %x %x", &reg, &val) == -1)
-			return -EFAULT;
-
-		pr_notice("\nphy=%d, reg=0x%x, val=0x%x\n",
-			phydev_addr(phydev), reg, val);
-		ret = air_pbus_reg_write(phydev, reg, val);
-		if (ret < 0) {
-			pr_notice("\npbus_reg_write fail\n");
-			return -EIO;
-		}
-		val = air_pbus_reg_read(phydev, reg);
-		pr_notice("\nphy=%d, reg=0x%x, val=0x%x confirm..\n",
-			phydev_addr(phydev), reg, val);
-	} else if (buf[0] == 'r') {
-		if (sscanf(buf, "r %x", &reg) == -1)
-			return -EFAULT;
-
-		val = air_pbus_reg_read(phydev, reg);
-		pr_notice("\nphy=%d, reg=0x%x, val=0x%x\n",
-		phydev_addr(phydev), reg, val);
-	} else
-		airphy_debugfs_buckpbus_help();
-
-	return count;
-}
-
-static int airphy_link_status(struct seq_file *seq, void *v)
-{
-	int ret = 0;
-	struct phy_device *phydev = seq->private;
-
-	ret = air_read_status(phydev);
-	if (ret < 0)
-		return ret;
-
-	seq_printf(seq, "%s Information:\n", dev_name(phydev_dev(phydev)));
-	seq_printf(seq, "\tPHYAD: %02d\n", phydev_addr(phydev));
-	seq_printf(seq, "\tLink Status: %s\n", phydev->link ? "UP" : "DOWN");
-	if (phydev->link) {
-		seq_printf(seq, "\tAuto-Nego: %s\n",
-				phydev->autoneg ? "on" : "off");
-		seq_puts(seq, "\tSpeed: ");
-		if (phydev->speed == SPEED_UNKNOWN)
-			seq_printf(seq, "Unknown! (%i)\n", phydev->speed);
-		else
-			seq_printf(seq, "%uMb/s\n", phydev->speed);
-
-		seq_printf(seq, "\tDuplex: %s\n",
-				phydev->duplex ? "Full" : "Half");
-		seq_puts(seq, "\n");
-	}
-
-	return ret;
-}
-
-static int airphy_link_status_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, airphy_link_status, inode->i_private);
-}
-
-static int dbg_regs_show(struct seq_file *seq, void *v)
-{
-	struct phy_device *phydev = seq->private;
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	seq_puts(seq, "\t<<DEBUG REG DUMP>>\n");
-	seq_printf(seq, "| RG_MII_BMCR           : 0x%08x |\n",
-		   air_mii_cl22_read(mbus, addr, MII_BMCR));
-	seq_printf(seq, "| RG_MII_BMSR           : 0x%08x |\n",
-		   air_mii_cl22_read(mbus, addr, MII_BMSR));
-	seq_printf(seq, "| RG_MII_ADVERTISE      : 0x%08x |\n",
-		   air_mii_cl22_read(mbus, addr, MII_ADVERTISE));
-	seq_printf(seq, "| RG_MII_LPA            : 0x%08x |\n",
-		   air_mii_cl22_read(mbus, addr, MII_LPA));
-	seq_printf(seq, "| RG_MII_CTRL1000       : 0x%08x |\n",
-		   air_mii_cl22_read(mbus, addr, MII_CTRL1000));
-	seq_printf(seq, "| RG_MII_STAT1000       : 0x%08x |\n",
-		   air_mii_cl22_read(mbus, addr, MII_STAT1000));
-	seq_printf(seq, "| RG_MII_REF_CLK        : 0x%08x |\n",
-		   air_mii_cl22_read(mbus, addr, 0x1d));
-	seq_printf(seq, "| RG_HW_STRAP1          : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xcf910));
-	seq_printf(seq, "| RG_HW_STRAP2          : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xcf914));
-	seq_printf(seq, "| RG_SYS_LINK_MODE      : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xe0004));
-	seq_printf(seq, "| RG_FCM_CTRL           : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xe000C));
-	seq_printf(seq, "| RG_SS_PAUSE_TIME      : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xe0020));
-	seq_printf(seq, "| RG_MIN_IPG_NUM        : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xe002C));
-	seq_printf(seq, "| RG_CTROL_0            : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xc0000));
-	seq_printf(seq, "| RG_LINK_STATUS        : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xc0b04));
-	seq_printf(seq, "| RG_LINK_PARTNER_AN    : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0xc0014));
-	seq_printf(seq, "| RG_FN_PWR_CTRL_STATUS : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0x1020c));
-	seq_printf(seq, "| RG_WHILE_LOOP_COUNT   : 0x%08x |\n",
-		   air_buckpbus_reg_read(phydev, 0x3A48));
-
-	return 0;
-}
-
-static int airphy_dbg_regs_show_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, dbg_regs_show, inode->i_private);
-}
-
-
-static int airphy_temp_show(struct seq_file *seq, void *v)
-{
-	struct phy_device *phydev = seq->private;
-	int ret = 0;
-	u32 pbus_value = 0;
-
-	seq_puts(seq, "<<AIR EN8811H Temp>>\n");
-	air_mii_cl45_write(phydev, 0x1e, 0x800e, 0x1100);
-	air_mii_cl45_write(phydev, 0x1e, 0x800f, 0xe5);
-	pbus_value = air_buckpbus_reg_read(phydev, 0x3B38);
-	seq_printf(seq, "| Temperature  : %dC |\n",
-						pbus_value);
-	seq_puts(seq, "\n");
-
-	return 0;
-}
-
-static int airphy_temp_show_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, airphy_temp_show, inode->i_private);
-}
-
-
-static unsigned int air_read_lp_speed(struct phy_device *phydev)
-{
-	int val = 0, an = AUTONEG_DISABLE;
-	unsigned int ret = 0;
-	int count = 15, i, lpa, lpagb;
-	struct air_lp_speed *m;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	val = air_mii_cl22_read(mbus, addr, MII_BMCR) | BIT(9);
-	ret = air_mii_cl22_write(mbus, addr, MII_BMCR, val);
-	if (unlikely(ret < 0))
-		return ret;
-	msleep(1500);
-	do {
-		msleep(100);
-		ret = air_mii_cl45_read(phydev, MDIO_MMD_AN, 0x21);
-		ret &= BIT(5);
-		if (ret)
-			break;
-		count--;
-	} while (count);
-
-	count = 10;
-	do {
-		msleep(500);
-		val = air_mii_cl22_read(mbus, addr, MII_BMSR);
-		if (val < 0) {
-			dev_err(dev, "MII_BMSR reg 0x%x!\n", val);
-			return val;
-		}
-		val = air_mii_cl22_read(mbus, addr, MII_BMSR);
-		if (val < 0) {
-			dev_err(dev, "MII_BMSR reg 0x%x!\n", val);
-			return val;
-		}
-		dev_dbg(dev, "val 0x%x\n", val);
-		if (val & BMSR_LSTATUS) {
-			val = air_mii_cl22_read(mbus, addr, MII_LPA);
-			if (val < 0)
-				return val;
-			lpa = (val & (BIT(5) | BIT(6) | BIT(7) | BIT(8))) >> 5;
-			val = air_mii_cl22_read(mbus, addr, MII_STAT1000);
-			if (val < 0)
-				return val;
-			lpagb = GET_BIT(val, 11) << 4;
-			ret |= (lpagb | lpa);
-			return ret;
-		}
-	} while (count--);
-
-	return 0;
-}
-
-static int airphy_lp_speed(struct seq_file *seq, void *v)
-{
-	unsigned int ret = 0, val = 0, did1 = 0, i;
-	struct phy_device *phydev = seq->private;
-	static const struct {
-		unsigned int bit_index;
-		const char *name;
-	} mode_defs[] = {
-		{ AIR_LINK_MODE_10baseT_Half_BIT,
-		"10baseT/Half" },
-		{ AIR_LINK_MODE_10baseT_Full_BIT,
-		"10baseT/Full" },
-		{ AIR_LINK_MODE_100baseT_Half_BIT,
-		"100baseT/Half" },
-		{ AIR_LINK_MODE_100baseT_Full_BIT,
-		"100baseT/Full" },
-		{ AIR_LINK_MODE_1000baseT_Full_BIT,
-		"1000baseT/Full" },
-		{ AIR_LINK_MODE_2500baseT_Full_BIT,
-		"2500baseT/Full" }
-	};
-
-	seq_printf(seq, "%s Link Partner Ability:\n",
-			dev_name(phydev_dev(phydev)));
-	ret = air_read_lp_speed(phydev);
-	if (val < 0)
-		return val;
-	for (i = 0; i < ARRAY_SIZE(mode_defs); i++) {
-		if (ret & BIT(mode_defs[i].bit_index)) {
-			seq_printf(seq, "\t\t\t %s\n",
-						mode_defs[i].name);
-			did1++;
-		}
-	}
-	if (did1 == 0)
-		seq_puts(seq, "\t\t\t Not reported\n");
-
-	return 0;
-}
-
-static int airphy_lp_speed_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, airphy_lp_speed, inode->i_private);
-}
-
-static const struct file_operations airphy_lp_speed_fops = {
-	.owner = THIS_MODULE,
-	.open = airphy_lp_speed_open,
-	.read = seq_read,
-	.llseek = noop_llseek,
-	.release = single_release,
-};
-
-static const struct file_operations airphy_info_fops = {
-	.owner = THIS_MODULE,
-	.open = airphy_info_open,
-	.read = seq_read,
-	.llseek = noop_llseek,
-	.release = single_release,
-};
-
-static const struct file_operations airphy_counter_fops = {
-	.owner = THIS_MODULE,
-	.open = airphy_counter_open,
-	.read = seq_read,
-	.llseek = noop_llseek,
-	.release = single_release,
-};
-
-static const struct file_operations airphy_debugfs_buckpbus_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.write = airphy_debugfs_buckpbus,
-	.llseek = noop_llseek,
-};
-
-static const struct file_operations airphy_debugfs_pbus_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.write = airphy_debugfs_pbus,
-	.llseek = noop_llseek,
-};
-
-static const struct file_operations airphy_port_mode_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.write = airphy_port_mode,
-	.llseek = noop_llseek,
-};
-
-static const struct file_operations airphy_polarity_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.write = airphy_polarity_write,
-	.llseek = noop_llseek,
-};
-
-static const struct file_operations airphy_link_status_fops = {
-	.owner = THIS_MODULE,
-	.open = airphy_link_status_open,
-	.read = seq_read,
-	.llseek = noop_llseek,
-	.release = single_release,
-};
-
-static const struct file_operations airphy_dbg_reg_show_fops = {
-	.owner = THIS_MODULE,
-	.open = airphy_dbg_regs_show_open,
-	.read = seq_read,
-	.llseek = noop_llseek,
-	.release = single_release,
-};
-
-static const struct file_operations airphy_temp_fops = {
-	.owner = THIS_MODULE,
-	.open = airphy_temp_show_open,
-	.read = seq_read,
-	.llseek = noop_llseek,
-	.release = single_release,
-};
-
-int airphy_debugfs_init(struct phy_device *phydev)
-{
-	int ret = 0;
-	struct en8811h_priv *priv = phydev->priv;
-	struct dentry *dir = priv->debugfs_root;
-
-	dev_dbg(phydev_dev(phydev), "%s: start\n", __func__);
-	dir = debugfs_create_dir(dev_name(phydev_dev(phydev)), NULL);
-	if (!dir) {
-		dev_err(phydev_dev(phydev), "%s:err at %d\n",
-					 __func__, __LINE__);
-		ret = -ENOMEM;
-	}
-	debugfs_create_file(DEBUGFS_DRIVER_INFO, S_IFREG | 0444,
-					dir, phydev,
-					&airphy_info_fops);
-	debugfs_create_file(DEBUGFS_COUNTER, S_IFREG | 0444,
-					dir, phydev,
-					&airphy_counter_fops);
-	debugfs_create_file(DEBUGFS_BUCKPBUS_OP, S_IFREG | 0200,
-					dir, phydev,
-					&airphy_debugfs_buckpbus_fops);
-	debugfs_create_file(DEBUGFS_PBUS_OP, S_IFREG | 0200,
-					dir, phydev,
-					&airphy_debugfs_pbus_fops);
-	debugfs_create_file(DEBUGFS_PORT_MODE, S_IFREG | 0200,
-					dir, phydev,
-					&airphy_port_mode_fops);
-	debugfs_create_file(DEBUGFS_POLARITY, S_IFREG | 0200,
-					dir, phydev,
-					&airphy_polarity_fops);
-	debugfs_create_file(DEBUGFS_LINK_STATUS, S_IFREG | 0444,
-					dir, phydev,
-					&airphy_link_status_fops);
-	debugfs_create_file(DEBUGFS_DBG_REG_SHOW, S_IFREG | 0444,
-					dir, phydev,
-					&airphy_dbg_reg_show_fops);
-	debugfs_create_file(DEBUGFS_TEMPERATURE, S_IFREG | 0444,
-					dir, phydev,
-					&airphy_temp_fops);
-	debugfs_create_file(DEBUGFS_LP_SPEED, S_IFREG | 0444,
-					dir, phydev,
-					&airphy_lp_speed_fops);
-
-	priv->debugfs_root = dir;
-	return ret;
-}
-
-void airphy_debugfs_remove(struct phy_device *phydev)
-{
-	struct en8811h_priv *priv = phydev->priv;
-
-	debugfs_remove_recursive(priv->debugfs_root);
-	priv->debugfs_root = NULL;
-}
-#endif /*CONFIG_AIROHA_EN8811H_PHY_DEBUGFS*/
diff --git a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_api.h b/target/linux/mediatek/files/drivers/net/phy/air_en8811h_api.h
deleted file mode 100644
index 9715a58994..0000000000
--- a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_api.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*************************************************
- * FILE NAME:  air_en8811h_api.h
- * PURPOSE:
- *      EN8811H PHY Driver for Linux
- * NOTES:
- *
- *  Copyright (C) 2023 Airoha Technology Corp.
- *************************************************/
-#ifndef __EN8811H_API_H
-#define __EN8811H_API_H
-#include <linux/version.h>
-
-#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
-#define phydev_mdio_bus(_dev) (_dev->bus)
-#define phydev_addr(_dev) (_dev->addr)
-#define phydev_dev(_dev) (&_dev->dev)
-#else
-#define phydev_mdio_bus(_dev) (_dev->mdio.bus)
-#define phydev_addr(_dev) (_dev->mdio.addr)
-#define phydev_dev(_dev) (&_dev->mdio.dev)
-#endif
-
-#define DEBUGFS_COUNTER		        "counter"
-#define DEBUGFS_DRIVER_INFO	        "drvinfo"
-#define DEBUGFS_PORT_MODE           "port_mode"
-#define DEBUGFS_BUCKPBUS_OP         "buckpbus_op"
-#define DEBUGFS_PBUS_OP             "pbus_op"
-#define DEBUGFS_POLARITY            "polarity"
-#define DEBUGFS_LINK_STATUS         "link_status"
-#define DEBUGFS_DBG_REG_SHOW        "dbg_regs_show"
-#define DEBUGFS_TEMPERATURE         "temp"
-#define DEBUGFS_LP_SPEED            "lp_speed"
-
-enum air_port_mode {
-	AIR_PORT_MODE_FORCE_100,
-	AIR_PORT_MODE_FORCE_1000,
-	AIR_PORT_MODE_FORCE_2500,
-	AIR_PORT_MODE_AUTONEGO,
-	AIR_PORT_MODE_POWER_DOWN,
-	AIR_PORT_MODE_POWER_UP,
-	AIR_PORT_MODE_SSC_DISABLE,
-	AIR_PORT_MODE_SSC_ENABLE,
-	AIR_PORT_MODE_LAST = 0xFF,
-};
-
-enum air_polarity {
-	AIR_POL_TX_REV_RX_NOR,
-	AIR_POL_TX_NOR_RX_NOR,
-	AIR_POL_TX_REV_RX_REV,
-	AIR_POL_TX_NOR_RX_REV,
-	AIR_POL_TX_NOR_RX_LAST = 0xff,
-};
-
-/* Link mode bit indices */
-enum air_link_mode_bit {
-	AIR_LINK_MODE_10baseT_Half_BIT	 = 0,
-	AIR_LINK_MODE_10baseT_Full_BIT	 = 1,
-	AIR_LINK_MODE_100baseT_Half_BIT	 = 2,
-	AIR_LINK_MODE_100baseT_Full_BIT	 = 3,
-	AIR_LINK_MODE_1000baseT_Full_BIT = 4,
-	AIR_LINK_MODE_2500baseT_Full_BIT = 5,
-};
-
-#ifndef unlikely
-#  define unlikely(x)	(x)
-#endif
-int air_pbus_reg_write(struct phy_device *phydev,
-	unsigned int pbus_address, unsigned int pbus_data);
-int air_mii_cl22_write(struct mii_bus *ebus, int addr,
-	unsigned int phy_register, unsigned int write_data);
-int air_mii_cl22_read(struct mii_bus *ebus,
-	int addr, unsigned int phy_register);
-int __air_mii_cl45_read(struct phy_device *phydev, int devad, u16 reg);
-int __air_mii_cl45_write(struct phy_device *phydev,
-	int devad, u16 reg, u16 write_data);
-int air_mii_cl45_read(struct phy_device *phydev, int devad, u16 reg);
-int air_mii_cl45_write(struct phy_device *phydev,
-	int devad, u16 reg, u16 write_data);
-unsigned int air_buckpbus_reg_read(struct phy_device *phydev,
-	unsigned int pbus_address);
-int air_buckpbus_reg_write(struct phy_device *phydev,
-	unsigned int pbus_address, unsigned int pbus_data);
-int en8811h_of_init(struct phy_device *phydev);
-#ifdef CONFIG_AIROHA_EN8811H_PHY_DEBUGFS
-int airphy_debugfs_init(struct phy_device *phydev);
-void airphy_debugfs_remove(struct phy_device *phydev);
-#endif /*CONFIG_AIROHA_EN8811H_PHY_DEBUGFS*/
-#endif /* End of __EN8811H_API_H */
diff --git a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_fw.h b/target/linux/mediatek/files/drivers/net/phy/air_en8811h_fw.h
deleted file mode 100644
index 7f0dd16ba1..0000000000
--- a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_fw.h
+++ /dev/null
@@ -1,9225 +0,0 @@
-#ifndef __EN8811H_MD32_H
-#define __EN8811H_MD32_H
-const long int EthMD32_dm_size = 16384;
-const unsigned char EthMD32_dm[16384] = {
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-    0xFF, 0x03, 0xFF, 0x03, 0xFF, 0x03, 0xFF, 0x03, 0xFF, 0x03, 0xFF, 0x03, 0xFF, 0x03, 0xFF, 0x03,
-    0xFF, 0x03, 0xFF, 0x03, 0xFF, 0x03, 0x00, 0x00, 0x01, 0xE0, 0x01, 0xF0, 0x01, 0xFC, 0x01, 0xFC,
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-};
-const long int EthMD32_pm_size = 131072;
-const unsigned char EthMD32_pm[131072] = {
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-    0x1E, 0x00, 0x85, 0xD0, 0x1E, 0x00, 0x87, 0x7C, 0x1E, 0x00, 0x88, 0xB4, 0x1E, 0x00, 0x89, 0x76,
-    0x1E, 0x00, 0x6D, 0x52, 0x1E, 0x00, 0x8B, 0xD8, 0x1E, 0x00, 0x8D, 0xB4, 0x1E, 0x00, 0x6C, 0xB8,
-    0x98, 0x0F, 0x0F, 0x00, 0x04, 0x0E, 0x0D, 0x09, 0x98, 0xEE, 0x0F, 0x00, 0x04, 0x01, 0x0D, 0x03,
-    0xB0, 0x11, 0x0F, 0x00, 0x04, 0x02, 0x0D, 0x09, 0x98, 0x22, 0x1C, 0x00, 0x18, 0x12, 0x04, 0x01,
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-    0x04, 0x01, 0x09, 0x00, 0x01, 0x22, 0x1D, 0x83, 0xF8, 0x40, 0x1C, 0x80, 0x10, 0x60, 0x06, 0xD0,
-    0x01, 0x01, 0x09, 0x00, 0x01, 0x33, 0x1D, 0x83, 0xF8, 0x60, 0x93, 0x03, 0x93, 0x04, 0x1F, 0x00,
-    0x8F, 0xBB, 0x93, 0x13, 0x1F, 0x00, 0x00, 0x04, 0x1E, 0x00, 0x00, 0x00, 0x98, 0x11, 0x05, 0xC0,
-    0x00, 0x20, 0xA0, 0x3F, 0x05, 0x80, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00,
-    0x05, 0xA0, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00, 0x05, 0xA0, 0x00, 0x00, 0x49, 0x0B, 0xF0, 0x07,
-    0x0F, 0x08, 0x11, 0x02, 0x49, 0x84, 0x26, 0x9F, 0x00, 0x40, 0x95, 0xC3, 0x00, 0x40, 0x43, 0x49,
-    0x00, 0x00, 0x10, 0x0A, 0x0F, 0x08, 0xFA, 0x0D, 0x0D, 0x00, 0x34, 0xDD, 0x14, 0xC0, 0x9A, 0x04,
-    0x96, 0xB6, 0x97, 0xC1, 0x14, 0xC0, 0x08, 0x10, 0x96, 0xC5, 0x96, 0xC4, 0xB4, 0xB0, 0x4B, 0x62,
-    0x70, 0x0C, 0xA0, 0x00, 0x1C, 0xC0, 0x2A, 0x10, 0x04, 0x1D, 0x61, 0xCF, 0x88, 0x8F, 0x0D, 0x80,
-    0x00, 0x2B, 0x20, 0x00, 0x3F, 0xBB, 0x0C, 0x00, 0x01, 0xCF, 0x20, 0x00, 0x2F, 0xBF, 0x06, 0x30,
-    0x00, 0xFF, 0x10, 0xC0, 0x0B, 0xE0, 0xA8, 0x3B, 0x44, 0x7D, 0xA1, 0x83, 0x89, 0xFB, 0x43, 0x0E,
-    0x34, 0xBB, 0x49, 0x86, 0x24, 0xC4, 0xA0, 0x00, 0x1C, 0xC0, 0x10, 0x10, 0xB0, 0xCB, 0x18, 0x00,
-    0x04, 0xB4, 0x06, 0x5F, 0xFC, 0xC6, 0xC4, 0xB4, 0x86, 0x1C, 0x00, 0x00, 0x13, 0x65, 0xB4, 0x84,
-    0x10, 0x00, 0x32, 0x45, 0x98, 0x35, 0x06, 0x0F, 0xFC, 0x46, 0x18, 0xC0, 0x34, 0x87, 0x98, 0x25,
-    0xA8, 0x24, 0x88, 0xD4, 0x04, 0x09, 0xE7, 0xCF, 0x49, 0xFE, 0x28, 0x3B, 0x44, 0x5F, 0xA8, 0x3B,
-    0x20, 0x12, 0x00, 0xFB, 0xB6, 0x3B, 0x06, 0x10, 0x00, 0x49, 0x44, 0x62, 0x78, 0xAD, 0x93, 0x95,
-    0xEA, 0x24, 0x08, 0x00, 0x80, 0x88, 0x86, 0x17, 0xA4, 0x9F, 0x96, 0x9E, 0xA0, 0x3F, 0xA8, 0x24,
-    0x88, 0xD4, 0x04, 0x09, 0xE7, 0xAC, 0x49, 0xE2, 0xA8, 0x3B, 0x44, 0x5E, 0x28, 0x3B, 0x20, 0x12,
-    0x00, 0xCB, 0xB6, 0x3B, 0x06, 0x10, 0x00, 0x49, 0x88, 0x54, 0x98, 0x45, 0x49, 0xCA, 0xF8, 0xAD,
-    0xA1, 0x69, 0xEA, 0x24, 0xA1, 0x56, 0x00, 0x01, 0x00, 0x0C, 0x80, 0x00, 0x00, 0x40, 0x95, 0xC7,
-    0x0F, 0x08, 0x80, 0x06, 0x0D, 0x00, 0xF4, 0x66, 0xA8, 0x61, 0x88, 0x61, 0xAB, 0x81, 0x20, 0x20,
-    0x44, 0x11, 0xBC, 0x81, 0x98, 0x31, 0x0F, 0x08, 0x00, 0x06, 0xA0, 0x2F, 0x08, 0x11, 0xFC, 0x66,
-    0xB6, 0x51, 0xA8, 0x61, 0x88, 0x16, 0xAB, 0xD1, 0x20, 0x20, 0x58, 0x11, 0xBC, 0x31, 0x4C, 0x10,
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-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-#endif /* End of __EN8801H_MD32_H */
diff --git a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_main.c b/target/linux/mediatek/files/drivers/net/phy/air_en8811h_main.c
deleted file mode 100644
index 4fdbf074a8..0000000000
--- a/target/linux/mediatek/files/drivers/net/phy/air_en8811h_main.c
+++ /dev/null
@@ -1,457 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*************************************************
- * FILE NAME:  air_en8811h_main.c
- * PURPOSE:
- *      EN8811H PHY Driver for Linux
- * NOTES:
- *
- *  Copyright (C) 2023 Airoha Technology Corp.
- *************************************************/
-
-/* INCLUDE FILE DECLARATIONS
-*/
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mii.h>
-#include <linux/phy.h>
-#include <linux/delay.h>
-#include <linux/ethtool.h>
-#include <linux/delay.h>
-#include <linux/debugfs.h>
-#include "air_en8811h_api.h"
-#include "air_en8811h_fw.h"
-#include "air_en8811h.h"
-
-MODULE_DESCRIPTION("Airoha EN8811H PHY Drivers");
-MODULE_AUTHOR("Airoha");
-MODULE_LICENSE("GPL");
-
-/**************************
- * GPIO5  <-> BASE_T_LED0,
- * GPIO4  <-> BASE_T_LED1,
- * GPIO3  <-> BASE_T_LED2,
- **************************/
-/* User-defined.B */
-#define AIR_LED_SUPPORT
-#ifdef AIR_LED_SUPPORT
-static const struct air_base_t_led_cfg led_cfg[3] = {
-/********************************************************************
- *Enable,     GPIO,        LED Polarity,    LED ON,     LED Blink
-*********************************************************************/
-	{1,	 AIR_LED0_GPIO5, AIR_ACTIVE_HIGH, AIR_LED0_ON, AIR_LED0_BLK},
-	{1,	 AIR_LED1_GPIO4, AIR_ACTIVE_HIGH, AIR_LED1_ON, AIR_LED1_BLK},
-	{1,	 AIR_LED2_GPIO3, AIR_ACTIVE_HIGH, AIR_LED2_ON, AIR_LED2_BLK},
-};
-static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M;
-#endif
-/* User-defined.E */
-
-/***********************************************************
- *                  F U N C T I O N S
- ***********************************************************/
-
-
-static int MDIOWriteBuf(struct phy_device *phydev, unsigned long address,
-		unsigned long array_size, const unsigned char *buffer)
-{
-	unsigned int write_data, offset;
-	int ret = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-	/* page 4 */
-	ret = air_mii_cl22_write(mbus, addr, 0x1F, 4);
-	if (ret < 0) {
-		dev_err(dev, "air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-	/* address increment*/
-	ret = air_mii_cl22_write(mbus, addr, 0x10, 0x8000);
-	if (ret < 0) {
-		dev_err(dev, "air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-	ret = air_mii_cl22_write(mbus, addr, 0x11,
-					(u32)((address >> 16) & 0xffff));
-	if (ret < 0) {
-		dev_err(dev, "air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-	ret = air_mii_cl22_write(mbus, addr, 0x12, (u32)(address & 0xffff));
-	if (ret < 0) {
-		dev_err(dev, "air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-
-	for (offset = 0; offset < array_size; offset += 4) {
-		write_data = (buffer[offset + 3] << 8) | buffer[offset + 2];
-		ret = air_mii_cl22_write(mbus, addr, 0x13, write_data);
-		if (ret < 0) {
-			dev_err(dev, "air_mii_cl22_write, ret: %d\n", ret);
-			return ret;
-		}
-		write_data = (buffer[offset + 1] << 8) | buffer[offset];
-		ret = air_mii_cl22_write(mbus, addr, 0x14, write_data);
-		if (ret < 0) {
-			dev_err(dev, "air_mii_cl22_write, ret: %d\n", ret);
-			return ret;
-		}
-	}
-	ret = air_mii_cl22_write(mbus, addr, 0x1F, 0);
-	if (ret < 0) {
-		dev_err(dev, "air_mii_cl22_write, ret: %d\n", ret);
-		return ret;
-	}
-	return 0;
-}
-
-static int en8811h_load_firmware(struct phy_device *phydev)
-{
-	struct device *dev = phydev_dev(phydev);
-	int ret = 0;
-	u32 pbus_value = 0;
-	struct en8811h_priv *priv = phydev->priv;
-
-	ret = air_buckpbus_reg_write(phydev,
-					0x0f0018, 0x0);
-	if (ret < 0)
-		return ret;
-	pbus_value = air_buckpbus_reg_read(phydev, 0x800000);
-	pbus_value |= BIT(11);
-	ret = air_buckpbus_reg_write(phydev,
-					0x800000, pbus_value);
-	if (ret < 0)
-		return ret;
-	/* Download DM */
-	ret = MDIOWriteBuf(phydev, 0x00000000, EthMD32_dm_size, EthMD32_dm);
-	if (ret < 0) {
-		dev_err(dev,
-			"MDIOWriteBuf 0x00000000 fail, ret: %d\n", ret);
-		return ret;
-	}
-
-	/* Download PM */
-	ret = MDIOWriteBuf(phydev, 0x00100000, EthMD32_pm_size, EthMD32_pm);
-	if (ret < 0) {
-		dev_err(dev,
-			"MDIOWriteBuf 0x00100000 fail , ret: %d\n", ret);
-		return ret;
-	}
-	pbus_value = air_buckpbus_reg_read(phydev, 0x800000);
-	pbus_value &= ~BIT(11);
-	ret = air_buckpbus_reg_write(phydev, 0x800000, pbus_value);
-	if (ret < 0)
-		return ret;
-	ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x01);
-	if (ret < 0)
-		return ret;
-	return 0;
-}
-
-#ifdef AIR_LED_SUPPORT
-static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity,
-				int polar, u16 on_evt, u16 blk_evt)
-{
-	int ret = 0;
-
-	if (polar == AIR_ACTIVE_HIGH)
-		on_evt |= LED_ON_POL;
-	else
-		on_evt &= ~LED_ON_POL;
-
-	ret = air_mii_cl45_write(phydev, 0x1f,
-			LED_ON_CTRL(entity), on_evt | LED_ON_EN);
-	if (ret < 0)
-		return ret;
-	ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt);
-	if (ret < 0)
-		return ret;
-	return 0;
-}
-
-static int airoha_led_set_mode(struct phy_device *phydev, u8 mode)
-{
-	u16 cl45_data;
-	int err = 0;
-	struct device *dev = phydev_dev(phydev);
-
-	cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_BCR);
-	switch (mode) {
-	case AIR_LED_MODE_DISABLE:
-		cl45_data &= ~LED_BCR_EXT_CTRL;
-		cl45_data &= ~LED_BCR_MODE_MASK;
-		cl45_data |= LED_BCR_MODE_DISABLE;
-		break;
-	case AIR_LED_MODE_USER_DEFINE:
-		cl45_data |= LED_BCR_EXT_CTRL;
-		cl45_data |= LED_BCR_CLK_EN;
-		break;
-	default:
-		dev_err(dev, "LED mode%d is not supported!\n", mode);
-		return -EINVAL;
-	}
-	err = air_mii_cl45_write(phydev, 0x1f, LED_BCR, cl45_data);
-	if (err < 0)
-		return err;
-	return 0;
-}
-
-static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state)
-{
-	u16 cl45_data = 0;
-	int err;
-
-	cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_ON_CTRL(entity));
-	if (state == 1)
-		cl45_data |= LED_ON_EN;
-	else
-		cl45_data &= ~LED_ON_EN;
-
-	err = air_mii_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), cl45_data);
-	if (err < 0)
-		return err;
-	return 0;
-}
-
-static int en8811h_led_init(struct phy_device *phydev)
-{
-
-	unsigned long led_gpio = 0, reg_value = 0;
-	u16 cl45_data = led_dur;
-	int ret = 0, id;
-	struct device *dev = phydev_dev(phydev);
-
-	ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_DUR, cl45_data);
-	if (ret < 0)
-		return ret;
-	cl45_data >>= 1;
-	ret = air_mii_cl45_write(phydev, 0x1f, LED_ON_DUR, cl45_data);
-	if (ret < 0)
-		return ret;
-	ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE);
-	if (ret != 0) {
-		dev_err(dev, "led_set_mode fail(ret:%d)!\n", ret);
-		return ret;
-	}
-	for (id = 0; id < EN8811H_LED_COUNT; id++) {
-		/* LED0 <-> GPIO5, LED1 <-> GPIO4, LED0 <-> GPIO3 */
-		if (led_cfg[id].gpio != (id + (AIR_LED0_GPIO5 - (2 * id)))) {
-			dev_err(dev, "LED%d uses incorrect GPIO%d !\n",
-							id, led_cfg[id].gpio);
-			return -EINVAL;
-		}
-		ret = airoha_led_set_state(phydev, id, led_cfg[id].en);
-		if (ret != 0) {
-			dev_err(dev, "led_set_state fail(ret:%d)!\n", ret);
-			return ret;
-		}
-		if (led_cfg[id].en == 1) {
-			led_gpio |= BIT(led_cfg[id].gpio);
-			ret = airoha_led_set_usr_def(phydev, id,
-				led_cfg[id].pol, led_cfg[id].on_cfg,
-				led_cfg[id].blk_cfg);
-			if (ret != 0) {
-				dev_err(dev, "led_set_usr_def fail!\n");
-				return ret;
-			}
-		}
-	}
-	reg_value = air_buckpbus_reg_read(phydev, 0xcf8b8) | led_gpio;
-	ret = air_buckpbus_reg_write(phydev, 0xcf8b8, reg_value);
-	if (ret < 0)
-		return ret;
-	dev_info(dev, "LED initialize OK !\n");
-	return 0;
-}
-#endif /* AIR_LED_SUPPORT */
-#if (KERNEL_VERSION(4, 5, 0) < LINUX_VERSION_CODE)
-static int en8811h_get_features(struct phy_device *phydev)
-{
-	int ret;
-	struct device *dev = phydev_dev(phydev);
-
-	dev_dbg(dev, "%s()\n", __func__);
-	ret = air_pbus_reg_write(phydev, 0xcf928, 0x0);
-	if (ret < 0)
-		return ret;
-	ret = genphy_read_abilities(phydev);
-	if (ret)
-		return ret;
-	/* EN8811H supports 100M/1G/2.5G speed. */
-	linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
-			phydev->supported);
-	linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
-			phydev->supported);
-	linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
-			phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
-			phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
-			phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
-			phydev->supported);
-	return 0;
-}
-#endif
-
-static int en8811h_probe(struct phy_device *phydev)
-{
-	int ret = 0;
-	int reg_value, pid1 = 0, pid2 = 0;
-	u32 retry, pbus_value = 0;
-	struct device *dev = phydev_dev(phydev);
-	struct mii_bus *mbus = phydev_mdio_bus(phydev);
-	int addr = phydev_addr(phydev);
-
-	struct en8811h_priv *priv;
-
-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-	phydev->priv = priv;
-	ret = air_pbus_reg_write(phydev, 0xcf928, 0x0);
-	if (ret < 0)
-		goto priv_free;
-	pid1 = air_mii_cl22_read(mbus, addr, MII_PHYSID1);
-	pid2 = air_mii_cl22_read(mbus, addr, MII_PHYSID2);
-	dev_info(dev, "PHY = %x - %x\n", pid1, pid2);
-	if ((pid1 != EN8811H_PHY_ID1) || (pid2 != EN8811H_PHY_ID2)) {
-		dev_err(dev, "EN8811H dose not exist!!\n");
-		kfree(priv);
-		return -ENODEV;
-	}
-	pbus_value = air_buckpbus_reg_read(phydev, 0xcf914);
-	dev_info(dev, "Bootmode: %s\n",
-			(GET_BIT(pbus_value, 24) ? "Flash" : "Download Code"));
-
-	ret = en8811h_load_firmware(phydev);
-	if (ret < 0) {
-		dev_err(dev, "EN8811H load firmware fail.\n");
-		goto priv_free;
-	}
-#ifdef CONFIG_AIROHA_EN8811H_PHY_DEBUGFS
-	ret = airphy_debugfs_init(phydev);
-	if (ret < 0) {
-		dev_err(dev, "air_debug_procfs_init fail. (ret=%d)\n", ret);
-		airphy_debugfs_remove(phydev);
-		goto priv_free;
-	}
-#endif /* CONFIG_AIROHA_EN8811H_PHY_DEBUGFS */
-	retry = MAX_RETRY;
-	do {
-		mdelay(300);
-		reg_value = air_mii_cl45_read(phydev, 0x1e, 0x8009);
-		if (reg_value == EN8811H_PHY_READY) {
-			dev_info(dev, "EN8811H PHY ready!\n");
-			break;
-		}
-		retry--;
-	} while (retry);
-	if (retry == 0) {
-		dev_err(dev, "MD32 FW is not ready.(Status 0x%x)\n", reg_value);
-		pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c);
-		dev_err(dev,
-			"Check MD32 FW Version(0x3b3c) : %08x\n", pbus_value);
-		dev_err(dev,
-			"EN8811H initialize fail!\n");
-		goto priv_free;
-	}
-	/* Mode selection*/
-	dev_info(dev, "EN8811H Mode 1 !\n");
-	ret = air_mii_cl45_write(phydev, 0x1e, 0x800c, 0x0);
-	if (ret < 0)
-		goto priv_free;
-	ret = air_mii_cl45_write(phydev, 0x1e, 0x800d, 0x0);
-	if (ret < 0)
-		goto priv_free;
-	ret = air_mii_cl45_write(phydev, 0x1e, 0x800e, 0x1101);
-	if (ret < 0)
-		goto priv_free;
-	ret = air_mii_cl45_write(phydev, 0x1e, 0x800f, 0x0002);
-	if (ret < 0)
-		goto priv_free;
-	/* Serdes polarity */
-	ret = en8811h_of_init(phydev);
-	if (ret < 0)
-		goto priv_free;
-	pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8);
-	pbus_value &= ~0x3;
-#if defined(CONFIG_OF)
-	pbus_value |= priv->pol;
-#else
-	pbus_value |= (EN8811H_RX_POL_NORMAL | EN8811H_TX_POL_NORMAL);
-#endif
-	ret = air_buckpbus_reg_write(phydev, 0xca0f8, pbus_value);
-	if (ret < 0)
-		goto priv_free;
-	pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8);
-	dev_info(dev, "Tx, Rx Polarity : %08x\n", pbus_value);
-	pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c);
-	dev_info(dev, "MD32 FW Version : %08x\n", pbus_value);
-#if defined(AIR_LED_SUPPORT)
-	ret = en8811h_led_init(phydev);
-	if (ret < 0) {
-		dev_err(dev, "en8811h_led_init fail. (ret=%d)\n", ret);
-		goto priv_free;
-	}
-#endif
-	dev_info(dev, "EN8811H initialize OK! (%s)\n", EN8811H_DRIVER_VERSION);
-	return 0;
-priv_free:
-	kfree(priv);
-	return ret;
-}
-void en8811h_remove(struct phy_device *phydev)
-{
-
-	struct en8811h_priv *priv = phydev->priv;
-	struct device *dev = phydev_dev(phydev);
-
-	dev_dbg(dev, "%s: start\n", __func__);
-	if (priv) {
-		dev_info(dev, "%s: airphy_debugfs_remove\n", __func__);
-#ifdef CONFIG_AIROHA_EN8811H_PHY_DEBUGFS
-		airphy_debugfs_remove(phydev);
-#endif /*CONFIG_AIROHA_EN8811H_PHY_DEBUGFS*/
-		kfree(priv);
-	}
-}
-
-static struct phy_driver en8811h_driver[] = {
-{
-	.phy_id         = EN8811H_PHY_ID,
-	.name           = "Airoha EN8811H",
-	.phy_id_mask    = 0x0ffffff0,
-	.probe          = en8811h_probe,
-	.remove         = en8811h_remove,
-#if (KERNEL_VERSION(4, 5, 0) < LINUX_VERSION_CODE)
-	.get_features   = en8811h_get_features,
-	.read_mmd       = __air_mii_cl45_read,
-	.write_mmd      = __air_mii_cl45_write,
-#endif
-} };
-
-int __init en8811h_phy_driver_register(void)
-{
-	int ret;
-#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
-	ret = phy_driver_register(en8811h_driver);
-#else
-	ret = phy_driver_register(en8811h_driver, THIS_MODULE);
-#endif
-	if (!ret)
-		return 0;
-
-	phy_driver_unregister(en8811h_driver);
-	return ret;
-}
-
-void __exit en8811h_phy_driver_unregister(void)
-{
-	phy_driver_unregister(en8811h_driver);
-}
-
-module_init(en8811h_phy_driver_register);
-module_exit(en8811h_phy_driver_unregister);
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
index 05fce5d7be..d0b4792274 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
@@ -12,8 +12,18 @@ abt,asr3000-ubootmod)
 	ucidef_set_led_netdev "wlan5g" "WLAN5G" "green:wlan5g" "phy1-ap0"
 	;;
 bananapi,bpi-r3-mini)
-	ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0"
-	ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0"
+	ucidef_set_led_netdev "lan1" "LAN" "mdio-bus:0e:green:lan" "eth0" "link_2500 link_1000 tx rx"
+	ucidef_set_led_netdev "lan2" "LAN" "mdio-bus:0e:yellow:lan" "eth0" "link_2500 link_100 tx rx"
+	ucidef_set_led_netdev "wan1" "WAN" "mdio-bus:0f:green:wan" "eth1" "link_2500 link_1000 tx rx"
+	ucidef_set_led_netdev "wan2" "WAN" "mdio-bus:0f:yellow:wan" "eth1" "link_2500 link_100 tx rx"
+	ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan-1" "phy0-ap0"
+	ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan-2" "phy1-ap0"
+	;;
+bananapi,bpi-r4)
+	ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:lan" "wan" "link tx rx"
+	ucidef_set_led_netdev "lan1" "lan1" "mt7530-0:01:green:lan" "lan1" "link tx rx"
+	ucidef_set_led_netdev "lan2" "lan2" "mt7530-0:02:green:lan" "lan2" "link tx rx"
+	ucidef_set_led_netdev "lan3" "lan3" "mt7530-0:03:green:lan" "lan3" "link tx rx"
 	;;
 confiabits,mt7981)
 	ucidef_set_led_netdev "lan1" "lan1" "blue:lan-1" "lan1" "link tx rx"
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
index d1812103b5..e85db48020 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
@@ -50,7 +50,11 @@ mediatek_setup_interfaces()
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan"
 		;;
 	bananapi,bpi-r3-mini)
-		ucidef_set_interfaces_lan_wan "eth0" "eth1"
+		ucidef_set_interfaces_lan_wan eth0 eth1
+		;;
+	bananapi,bpi-r4)
+		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 eth1" "wan eth2"
+		;;
 		;;
 	comfast,cf-e393ax)
 		ucidef_set_interfaces_lan_wan "lan1" eth1
@@ -135,16 +139,6 @@ mediatek_setup_macs()
 		;;
 		esac
 		;;
-	glinet,gl-mt2500)
-		label_mac="$(get_mac_binary "/dev/mmcblk0boot1" 0xA)"
-		wan_mac="$label_mac"
-		lan_mac="$(macaddr_add $label_mac 1)"
-		;;
-	glinet,gl-mt6000)
-		label_mac=$(mmc_get_mac_binary factory 0x0a)
-		wan_mac=$label_mac
-		lan_mac=$(macaddr_add "$label_mac" 2)
-		;;
 	h3c,magic-nx30-pro|\
 	h3c,magic-nx30-pro-nmbm)
 		wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr)
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version
index e0e1a8ecc7..9090b6ede0 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version
@@ -5,8 +5,9 @@
 board_config_update
 
 case "$(board_name)" in
-	bananapi,bpi-r3)
-		ucidef_set_compat_version "1.1"
+	bananapi,bpi-r3|\
+	bananapi,bpi-r3-mini)
+		ucidef_set_compat_version "1.2"
 		;;
 esac
 
diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
index 22ab26608f..1ec648584d 100644
--- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
+++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
@@ -72,7 +72,6 @@ case "$FIRMWARE" in
 		CI_UBIPART="UBI_DEV"
 		caldata_extract_ubi "Factory" 0x0 0x1000
 		;;
-	glinet,gl-mt6000|\
 	jdcloud,re-cp-03)
 		caldata_extract_mmc "factory" 0x0 0x1000
 		;;
diff --git a/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version
index 4486f2f090..6dcf80010d 100644
--- a/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version
+++ b/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version
@@ -1,8 +1,9 @@
 . /lib/functions.sh
 
 case "$(board_name)" in
-	bananapi,bpi-r3)
-	uci set system.@system[0].compat_version="1.1"
+	bananapi,bpi-r3|\
+	bananapi,bpi-r3-mini)
+	uci set system.@system[0].compat_version="1.2"
 	uci commit system
 	;;
 esac
diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
index 1b608dc1c5..9177237821 100755
--- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
@@ -1,4 +1,5 @@
 REQUIRE_IMAGE_METADATA=1
+RAMFS_COPY_BIN='fitblk'
 
 asus_initial_setup()
 {
@@ -59,6 +60,21 @@ xiaomi_initial_setup()
 	esac
 }
 
+platform_get_bootdev() {
+	local rootdisk="$(cat /sys/firmware/devicetree/base/chosen/rootdisk)"
+	local handle bootdev
+	for handle in /sys/class/block/*/of_node/phandle /sys/class/block/*/device/of_node/phandle; do
+		[ ! -e "$handle" ] && continue
+		if [ "$rootdisk" = "$(cat $handle)" ]; then
+			bootdev="${handle%/of_node/phandle}"
+			bootdev="${bootdev%/device}"
+			bootdev="${bootdev#/sys/class/block/}"
+			echo "$bootdev"
+			break
+		fi
+	done
+}
+
 platform_do_upgrade() {
 	local board=$(board_name)
 
@@ -80,18 +96,18 @@ platform_do_upgrade() {
 		nand_do_upgrade "$1"
 		;;
 	bananapi,bpi-r3|\
-	bananapi,bpi-r3-mini)
-		local rootdev="$(cmdline_get_var root)"
-		rootdev="${rootdev##*/}"
-		rootdev="${rootdev%p[0-9]*}"
-		case "$rootdev" in
-		mmc*)
-			CI_ROOTDEV="$rootdev"
-			CI_KERNPART="production"
+	bananapi,bpi-r3-mini|\
+	bananapi,bpi-r4)
+		[ -e /dev/fit0 ] && fitblk /dev/fit0
+		[ -e /dev/fitrw ] && fitblk /dev/fitrw
+		bootdev="$(platform_get_bootdev)"
+		case "$bootdev" in
+		mmcblk*)
+			EMMC_KERN_DEV="/dev/$bootdev"
 			emmc_do_upgrade "$1"
 			;;
 		mtdblock*)
-			PART_NAME="fit"
+			PART_NAME="/dev/mtd${bootdev:8}"
 			default_do_upgrade "$1"
 			;;
 		ubiblock*)
@@ -176,7 +192,7 @@ platform_check_image() {
 
 	case "$board" in
 	bananapi,bpi-r3|\
-	bananapi,bpi-r3-mini|\
+	bananapi,bpi-r4|\
 	cmcc,rax3000m)
 		[ "$magic" != "d00dfeed" ] && {
 			echo "Invalid image type."
@@ -204,6 +220,13 @@ platform_copy_config() {
 		;;
 	bananapi,bpi-r3|\
 	bananapi,bpi-r3-mini|\
+	bananapi,bpi-r4)
+		case "$(platform_get_bootdev)" in
+		mmcblk*)
+			emmc_copy_config
+			;;
+		esac
+		;;
 	cmcc,rax3000m)
 		case "$(cmdline_get_var root)" in
 		/dev/mmc*)
diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15
deleted file mode 100644
index c4948e3129..0000000000
--- a/target/linux/mediatek/filogic/config-5.15
+++ /dev/null
@@ -1,445 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_AIROHA_EN8811H_PHY=y
-# CONFIG_AIROHA_EN8811H_PHY_DEBUGFS is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2712 is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7981=y
-CONFIG_COMMON_CLK_MT7981_ETHSYS=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_COMMON_CLK_MT7988=y
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-CONFIG_LEDS_SMARTRG_LED=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAXLINEAR_GPHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_2P5G_PHY=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_GE_SOC_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-CONFIG_NET_DSA_MT7530_MMIO=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_USXGMII=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-# CONFIG_PCIE_MEDIATEK is not set
-CONFIG_PCIE_MEDIATEK_GEN3=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-CONFIG_PHY_MTK_XSPHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-# CONFIG_PINCTRL_MT7622 is not set
-CONFIG_PINCTRL_MT7981=y
-CONFIG_PINCTRL_MT7986=y
-CONFIG_PINCTRL_MT7988=y
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-CONFIG_PINCTRL_MT8516=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-CONFIG_REGULATOR_RT5190A=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_TI_SYSCON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1
index d3ad7ecc00..34aa2e76b6 100644
--- a/target/linux/mediatek/filogic/config-6.1
+++ b/target/linux/mediatek/filogic/config-6.1
@@ -1,8 +1,5 @@
 CONFIG_64BIT=y
 # CONFIG_AHCI_MTK is not set
-CONFIG_AIROHA_EN8811H_PHY=y
-# CONFIG_AIROHA_EN8811H_PHY_DEBUGFS is not set
-CONFIG_AQUANTIA_PHY=y
 CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
 CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y
@@ -46,6 +43,7 @@ CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_NVMEM=y
 CONFIG_BLK_PM=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
@@ -256,6 +254,7 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_NVMEM=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 # CONFIG_MTK_CMDQ is not set
 # CONFIG_MTK_CQDMA is not set
@@ -266,6 +265,9 @@ CONFIG_MTK_SCPSYS=y
 CONFIG_MTK_SCPSYS_PM_DOMAINS=y
 # CONFIG_MTK_SVS is not set
 CONFIG_MTK_THERMAL=y
+CONFIG_MTK_SOC_THERMAL=y
+CONFIG_MTK_LVTS_THERMAL=y
+CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
 CONFIG_MTK_TIMER=y
 # CONFIG_MTK_UART_APDMA is not set
 CONFIG_MUTEX_SPIN_ON_OWNER=y
@@ -279,7 +281,6 @@ CONFIG_NET_DSA_MT7530_MMIO=y
 CONFIG_NET_DSA_TAG_MTK=y
 CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_USXGMII=y
 CONFIG_NET_MEDIATEK_SOC_WED=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
@@ -326,6 +327,7 @@ CONFIG_PCI_DOMAINS_GENERIC=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
 CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PCS_MTK_USXGMII=y
 CONFIG_PERF_EVENTS=y
 CONFIG_PGTABLE_LEVELS=3
 CONFIG_PHYLIB=y
@@ -336,6 +338,7 @@ CONFIG_PHYS_ADDR_T_64BIT=y
 # CONFIG_PHY_MTK_PCIE is not set
 CONFIG_PHY_MTK_TPHY=y
 # CONFIG_PHY_MTK_UFS is not set
+CONFIG_PHY_MTK_XFI_TPHY=y
 CONFIG_PHY_MTK_XSPHY=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_MT2712 is not set
@@ -460,6 +463,7 @@ CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_UBIFS_FS=y
 # CONFIG_UCLAMP_TASK is not set
+CONFIG_UIMAGE_FIT_BLK=y
 # CONFIG_UNMAP_KERNEL_AT_EL0 is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_VMAP_STACK=y
diff --git a/target/linux/mediatek/filogic/target.mk b/target/linux/mediatek/filogic/target.mk
index 1977ff566c..6d593f1ab2 100644
--- a/target/linux/mediatek/filogic/target.mk
+++ b/target/linux/mediatek/filogic/target.mk
@@ -2,7 +2,7 @@ ARCH:=aarch64
 SUBTARGET:=filogic
 BOARDNAME:=Filogic 8x0 (MT798x)
 CPU_TYPE:=cortex-a53
-DEFAULT_PACKAGES += kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools bridger
+DEFAULT_PACKAGES += kmod-phy-aquantia kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools bridger
 KERNELNAME:=Image dtbs
 
 define Target/Description
diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk
index 0add050db1..430be3e389 100644
--- a/target/linux/mediatek/image/filogic.mk
+++ b/target/linux/mediatek/image/filogic.mk
@@ -249,7 +249,8 @@ define Device/bananapi_bpi-r3
 		       mt7986a-bananapi-bpi-r3-respeaker-2mics
   DEVICE_DTS_DIR := $(DTS_DIR)/
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware automount
+  DEVICE_PACKAGES := fitblk kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 \
+		     e2fsprogs f2fsck mkf2fs mt7986-wo-firmware automount
   IMAGES := sysupgrade.itb
   KERNEL_LOADADDR := 0x44000000
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
@@ -262,7 +263,7 @@ define Device/bananapi_bpi-r3
   ARTIFACT/emmc-bl31-uboot.fip	:= mt7986-bl31-uboot bananapi_bpi-r3-emmc
   ARTIFACT/nor-preloader.bin	:= mt7986-bl2 nor-ddr4
   ARTIFACT/nor-bl31-uboot.fip	:= mt7986-bl31-uboot bananapi_bpi-r3-nor
-  ARTIFACT/snand-preloader.bin	:= mt7986-bl2 spim-nand-ddr4
+  ARTIFACT/snand-preloader.bin	:= mt7986-bl2 spim-nand-ubi-ddr4
   ARTIFACT/snand-bl31-uboot.fip	:= mt7986-bl31-uboot bananapi_bpi-r3-snand
   ARTIFACT/sdcard.img.gz	:= mt798x-gpt sdmmc |\
 				   pad-to 17k | mt7986-bl2 sdmmc-ddr4 |\
@@ -270,7 +271,7 @@ define Device/bananapi_bpi-r3
 				$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
 				   pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\
 				) \
-				   pad-to 44M | mt7986-bl2 spim-nand-ddr4 |\
+				   pad-to 44M | mt7986-bl2 spim-nand-ubi-ddr4 |\
 				   pad-to 45M | mt7986-bl31-uboot bananapi_bpi-r3-snand |\
 				   pad-to 49M | mt7986-bl2 nor-ddr4 |\
 				   pad-to 50M | mt7986-bl31-uboot bananapi_bpi-r3-nor |\
@@ -289,8 +290,8 @@ endif
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata
   DEVICE_DTC_FLAGS := --pad 4096
-  DEVICE_COMPAT_VERSION := 1.1
-  DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update
+  DEVICE_COMPAT_VERSION := 1.2
+  DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update
 endef
 TARGET_DEVICES += bananapi_bpi-r3
 
@@ -298,33 +299,94 @@ define Device/bananapi_bpi-r3-mini
   DEVICE_VENDOR := Bananapi
   DEVICE_MODEL := BPi-R3 Mini
   DEVICE_DTS := mt7986a-bananapi-bpi-r3-mini
+  DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3-mini
   DEVICE_DTS_DIR := ../dts
-  DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mt7986-firmware mt7986-wo-firmware \
-	kmod-nvme kmod-usb3 automount f2fsck mkf2fs \
-	kmod-usb-net-cdc-mbim kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi
+  DEVICE_PACKAGES := fitblk kmod-hwmon-pwmfan kmod-mt7986-firmware kmod-phy-airoha-en8811h \
+		     kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware automount
   KERNEL_LOADADDR := 0x44000000
   KERNEL := kernel-bin | gzip
   KERNEL_INITRAMFS := kernel-bin | lzma | \
-	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+    fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
-  IMAGES := sysupgrade.itb
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  KERNEL_IN_UBI := 1
+  UBOOTENV_IN_UBI := 1
+  IMAGES := snand-factory.bin sysupgrade.itb
+ifeq ($(DUMP),)
   IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
+endif
   IMAGE/sysupgrade.itb := append-kernel | \
-	fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | \
-	pad-rootfs | append-metadata
+    fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | \
+    pad-rootfs | append-metadata
   ARTIFACTS := \
        emmc-gpt.bin emmc-preloader.bin emmc-bl31-uboot.fip \
-       snand-preloader.bin snand-bl31-uboot.fip
+       snand-factory.bin snand-preloader.bin snand-bl31-uboot.fip
   ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc
   ARTIFACT/emmc-preloader.bin := mt7986-bl2 emmc-ddr4
   ARTIFACT/emmc-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-mini-emmc
-  ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ddr4
+  ARTIFACT/snand-factory.bin := mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 256k | \
+				mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 512k | \
+				mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 768k | \
+				mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 2048k | \
+				ubinize-image fit squashfs-sysupgrade.itb
+  ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ubi-ddr4
   ARTIFACT/snand-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-mini-snand
+  UBINIZE_PARTS := fip=:$(STAGING_DIR_IMAGE)/mt7986_bananapi_bpi-r3-mini-snand-u-boot.fip
+ifneq ($(CONFIG_PACKAGE_airoha-en8811h-firmware),)
+  UBINIZE_PARTS += en8811h-fw=:$(STAGING_DIR_IMAGE)/EthMD32.bin
+endif
+  DEVICE_COMPAT_VERSION := 1.2
+  DEVICE_COMPAT_MESSAGE := Flash layout changes require bootloader update
 endef
 TARGET_DEVICES += bananapi_bpi-r3-mini
 
+define Device/bananapi_bpi-r4
+  DEVICE_VENDOR := Bananapi
+  DEVICE_MODEL := BPi-R4
+  DEVICE_DTS := mt7988a-bananapi-bpi-r4
+  DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4
+  DEVICE_DTS_DIR := $(DTS_DIR)/
+  DEVICE_DTS_LOADADDR := 0x45f00000
+  DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd mt7988a-bananapi-bpi-r4-wifi-mt7996a
+  DEVICE_DTC_FLAGS := --pad 4096
+  DEVICE_PACKAGES := fitblk kmod-hwmon-pwmfan kmod-i2c-mux-pca954x kmod-eeprom-at24 kmod-mt7996-firmware \
+		     kmod-rtc-pcf8563 kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs
+  IMAGES := sysupgrade.itb
+  KERNEL_LOADADDR := 0x46000000
+  KERNEL_INITRAMFS_SUFFIX := -recovery.itb
+  ARTIFACTS := \
+	       emmc-preloader.bin emmc-bl31-uboot.fip \
+	       sdcard.img.gz \
+	       snand-preloader.bin snand-bl31-uboot.fip
+  ARTIFACT/emmc-preloader.bin	:= mt7988-bl2 emmc-comb
+  ARTIFACT/emmc-bl31-uboot.fip	:= mt7988-bl31-uboot bananapi_bpi-r4-emmc
+  ARTIFACT/snand-preloader.bin	:= mt7988-bl2 spim-nand-ubi-comb
+  ARTIFACT/snand-bl31-uboot.fip	:= mt7988-bl31-uboot bananapi_bpi-r4-snand
+  ARTIFACT/sdcard.img.gz	:= mt798x-gpt sdmmc |\
+				   pad-to 17k | mt7988-bl2 sdmmc-comb |\
+				   pad-to 6656k | mt7988-bl31-uboot bananapi_bpi-r4-sdmmc |\
+				$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
+				   pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\
+				) \
+				   pad-to 44M | mt7988-bl2 spim-nand-ubi-comb |\
+				   pad-to 45M | mt7988-bl31-uboot bananapi_bpi-r4-snand |\
+				   pad-to 51M | mt7988-bl2 emmc-comb |\
+				   pad-to 52M | mt7988-bl31-uboot bananapi_bpi-r4-emmc |\
+				   pad-to 56M | mt798x-gpt emmc |\
+				$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
+				   pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
+				) \
+				  gzip
+  IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
+  KERNEL			:= kernel-bin | gzip
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += bananapi_bpi-r4
+
 define Device/cetron_ct3003-stock
   DEVICE_VENDOR := Cetron
   DEVICE_MODEL := CT3003
@@ -803,7 +865,7 @@ define Device/mediatek_mt7988a-rfb
   DEVICE_DTS_DIR := $(DTS_DIR)/
   DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x45f00000
-  DEVICE_PACKAGES := kmod-sfp
+  DEVICE_PACKAGES := mt7988-2p5g-phy-firmware kmod-sfp
   KERNEL_LOADADDR := 0x46000000
   KERNEL := kernel-bin | gzip
   KERNEL_INITRAMFS := kernel-bin | lzma | \
diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk
index 7df5eade82..220e72ba99 100644
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@@ -90,7 +90,7 @@ define Device/bananapi_bpi-r64
   DEVICE_MODEL := BPi-R64
   DEVICE_DTS := mt7622-bananapi-bpi-r64
   DEVICE_DTS_OVERLAY := mt7622-bananapi-bpi-r64-pcie1 mt7622-bananapi-bpi-r64-sata
-  DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3 e2fsprogs mkf2fs f2fsck
+  DEVICE_PACKAGES := fitblk kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3 e2fsprogs mkf2fs f2fsck
   DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x43f00000
   ARTIFACTS := emmc-preloader.bin emmc-bl31-uboot.fip sdcard.img.gz snand-preloader.bin snand-bl31-uboot.fip
@@ -98,7 +98,7 @@ define Device/bananapi_bpi-r64
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   ARTIFACT/emmc-preloader.bin	:= bl2 emmc-2ddr
   ARTIFACT/emmc-bl31-uboot.fip	:= bl31-uboot bananapi_bpi-r64-emmc
-  ARTIFACT/snand-preloader.bin	:= bl2 snand-2ddr
+  ARTIFACT/snand-preloader.bin	:= bl2 snand-ubi-2ddr
   ARTIFACT/snand-bl31-uboot.fip	:= bl31-uboot bananapi_bpi-r64-snand
   ARTIFACT/sdcard.img.gz	:= mt7622-gpt sdmmc |\
 				   pad-to 512k | bl2 sdmmc-2ddr |\
@@ -109,7 +109,7 @@ define Device/bananapi_bpi-r64
 				   pad-to 38912k | mt7622-gpt emmc |\
 				   pad-to 39424k | bl2 emmc-2ddr |\
 				   pad-to 40960k | bl31-uboot bananapi_bpi-r64-emmc |\
-				   pad-to 43008k | bl2 snand-2ddr |\
+				   pad-to 43008k | bl2 snand-ubi-2ddr |\
 				   pad-to 43520k | bl31-uboot bananapi_bpi-r64-snand |\
 				$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS), \
 				   pad-to 46080k | append-image squashfs-sysupgrade.itb | check-size |\
@@ -121,8 +121,8 @@ endif
   KERNEL			:= kernel-bin | gzip
   KERNEL_INITRAMFS		:= kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd | pad-to 128k
   IMAGE/sysupgrade.itb		:= append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata
-  DEVICE_COMPAT_VERSION := 1.1
-  DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update
+  DEVICE_COMPAT_VERSION := 1.2
+  DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update
 endef
 TARGET_DEVICES += bananapi_bpi-r64
 
@@ -256,7 +256,7 @@ define Device/linksys_e8450-ubi
   DEVICE_ALT0_VARIANT := UBI
   DEVICE_DTS := mt7622-linksys-e8450-ubi
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7915-firmware kmod-usb3
+  DEVICE_PACKAGES := fitblk kmod-mt7915-firmware kmod-usb3
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -270,8 +270,10 @@ define Device/linksys_e8450-ubi
   IMAGES := sysupgrade.itb
   IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
   ARTIFACTS := preloader.bin bl31-uboot.fip
-  ARTIFACT/preloader.bin := bl2 snand-1ddr
+  ARTIFACT/preloader.bin := bl2 snand-ubi-1ddr
   ARTIFACT/bl31-uboot.fip := bl31-uboot linksys_e8450
+  DEVICE_COMPAT_VERSION := 2.0
+  DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update
 endef
 TARGET_DEVICES += linksys_e8450-ubi
 
@@ -300,7 +302,7 @@ define Device/mediatek_mt7622-rfb1-ubi
                 check-size $$$$(IMAGE_SIZE)
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
-TARGET_DEVICES += mediatek_mt7622-rfb1-ubi
+# TARGET_DEVICES += mediatek_mt7622-rfb1-ubi
 
 define Device/netgear_wax206
   $(Device/dsa-migration)
@@ -375,7 +377,7 @@ define Device/ubnt_unifi-6-lr-v1-ubootmod
   DEVICE_VARIANT := v1 U-Boot mod
   DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v1-ubootmod
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7915-firmware kmod-leds-ubnt-ledbar
+  DEVICE_PACKAGES := fitblk kmod-mt7915-firmware kmod-leds-ubnt-ledbar
   KERNEL := kernel-bin | lzma
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
@@ -405,7 +407,7 @@ define Device/ubnt_unifi-6-lr-v2-ubootmod
   DEVICE_VARIANT := v2 U-Boot mod
   DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v2-ubootmod
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7915-firmware
+  DEVICE_PACKAGES := fitblk kmod-mt7915-firmware
   KERNEL := kernel-bin | lzma
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
@@ -434,7 +436,7 @@ define Device/ubnt_unifi-6-lr-v3-ubootmod
   DEVICE_VARIANT := v3 U-Boot mod
   DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v3-ubootmod
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7915-firmware
+  DEVICE_PACKAGES := fitblk kmod-mt7915-firmware
   KERNEL := kernel-bin | lzma
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
@@ -464,4 +466,4 @@ define Device/xiaomi_redmi-router-ax6s
   IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
-TARGET_DEVICES += xiaomi_redmi-router-ax6s
+# TARGET_DEVICES += xiaomi_redmi-router-ax6s
diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version
index c8fb2c08f6..68c397a95c 100644
--- a/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version
+++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version
@@ -6,7 +6,10 @@ board_config_update
 
 case "$(board_name)" in
 	bananapi,bpi-r64)
-		ucidef_set_compat_version "1.1"
+		ucidef_set_compat_version "1.2"
+		;;
+	linksys,e8450-ubi)
+		ucidef_set_compat_version "2.0"
 		;;
 esac
 
diff --git a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version
index 8331037869..6309728e4b 100644
--- a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version
+++ b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version
@@ -1,11 +1,18 @@
 . /lib/functions.sh
 
 case "$(board_name)" in
-	bananapi,bpi-r64|\
+	bananapi,bpi-r64)
+	uci set system.@system[0].compat_version="1.2"
+	uci commit system
+	;;
 	buffalo,wsr-2533dhp2)
 	uci set system.@system[0].compat_version="1.1"
 	uci commit system
 	;;
+	linksys,e8450-ubi)
+	uci set system.@system[0].compat_version="2.0"
+	uci commit system
+	;;
 esac
 
 exit 0
diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
index 3a2d7a4cd6..f5d938e65e 100755
--- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
@@ -1,26 +1,50 @@
 REQUIRE_IMAGE_METADATA=1
+RAMFS_COPY_BIN='fitblk'
+
+platform_get_bootdev() {
+	local rootdisk="$(cat /sys/firmware/devicetree/base/chosen/rootdisk)"
+	local handle bootdev
+	for handle in /sys/class/block/*/of_node/phandle /sys/class/block/*/device/of_node/phandle; do
+		[ ! -e "$handle" ] && continue
+		if [ "$rootdisk" = "$(cat $handle)" ]; then
+			bootdev="${handle%/of_node/phandle}"
+			bootdev="${bootdev%/device}"
+			bootdev="${bootdev#/sys/class/block/}"
+			echo "$bootdev"
+			break
+		fi
+	done
+}
 
 platform_do_upgrade() {
 	local board=$(board_name)
 	local file_type=$(identify $1)
 
 	case "$board" in
-	bananapi,bpi-r64)
-		local rootdev="$(cmdline_get_var root)"
-		rootdev="${rootdev##*/}"
-		rootdev="${rootdev%p[0-9]*}"
-		case "$rootdev" in
-		mmc*)
-			CI_ROOTDEV="$rootdev"
-			CI_KERNPART="production"
+	bananapi,bpi-r64|\
+	linksys,e8450-ubi|\
+	ubnt,unifi-6-lr-v1-ubootmod|\
+	ubnt,unifi-6-lr-v2-ubootmod|\
+	ubnt,unifi-6-lr-v3-ubootmod)
+		[ -e /dev/fit0 ] && fitblk /dev/fit0
+		[ -e /dev/fitrw ] && fitblk /dev/fitrw
+		bootdev="$(platform_get_bootdev)"
+		case "$bootdev" in
+		mmcblk*)
+			EMMC_KERN_DEV="/dev/$bootdev"
 			emmc_do_upgrade "$1"
 			;;
-		*)
+		mtdblock*)
+			PART_NAME="/dev/mtd${bootdev:8}"
+			default_do_upgrade "$1"
+			;;
+		ubiblock*)
 			CI_KERNPART="fit"
 			nand_do_upgrade "$1"
 			;;
 		esac
 		;;
+
 	buffalo,wsr-2533dhp2|\
 	buffalo,wsr-3200ax4s)
 		local magic="$(get_magic_long "$1")"
@@ -43,10 +67,6 @@ platform_do_upgrade() {
 	xiaomi,redmi-router-ax6s)
 		nand_do_upgrade "$1"
 		;;
-	linksys,e8450-ubi)
-		CI_KERNPART="fit"
-		nand_do_upgrade "$1"
-		;;
 	linksys,e8450)
 		if grep -q mtdparts=slave /proc/cmdline; then
 			PART_NAME=firmware2
@@ -99,9 +119,7 @@ platform_check_image() {
 platform_copy_config() {
 	case "$(board_name)" in
 	bananapi,bpi-r64)
-		export_bootdevice
-		export_partdevice rootdev 0
-		if echo $rootdev | grep -q mmc; then
+		if platform_get_bootdev | grep -q mmc; then
 			emmc_copy_config
 		fi
 		;;
diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15
deleted file mode 100644
index 7c146c7fb3..0000000000
--- a/target/linux/mediatek/mt7622/config-5.15
+++ /dev/null
@@ -1,445 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-# CONFIG_AIROHA_EN8811H_PHY is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-CONFIG_COMMON_CLK_MT7622=y
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MEDIATEK_2P5G_PHY is not set
-CONFIG_MEDIATEK_GE_PHY=y
-# CONFIG_MEDIATEK_GE_SOC_PHY is not set
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-CONFIG_PINCTRL_MT7622=y
-# CONFIG_PINCTRL_MT7981 is not set
-# CONFIG_PINCTRL_MT7986 is not set
-# CONFIG_PINCTRL_MT7988 is not set
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-CONFIG_PINCTRL_MT8516=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-# CONFIG_REGULATOR_RT5190A is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTL8367S_GSW=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7622/config-6.1 b/target/linux/mediatek/mt7622/config-6.1
index 007d437070..6a245a3438 100644
--- a/target/linux/mediatek/mt7622/config-6.1
+++ b/target/linux/mediatek/mt7622/config-6.1
@@ -258,6 +258,7 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_NVMEM=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 # CONFIG_MTK_CMDQ is not set
 # CONFIG_MTK_CQDMA is not set
@@ -268,6 +269,8 @@ CONFIG_MTK_SCPSYS=y
 CONFIG_MTK_SCPSYS_PM_DOMAINS=y
 # CONFIG_MTK_SVS is not set
 CONFIG_MTK_THERMAL=y
+CONFIG_MTK_SOC_THERMAL=y
+# CONFIG_MTK_LVTS_THERMAL is not set
 CONFIG_MTK_TIMER=y
 # CONFIG_MTK_UART_APDMA is not set
 CONFIG_MUTEX_SPIN_ON_OWNER=y
@@ -454,6 +457,7 @@ CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_UBIFS_FS=y
 # CONFIG_UCLAMP_TASK is not set
+CONFIG_UIMAGE_FIT_BLK=y
 # CONFIG_UNMAP_KERNEL_AT_EL0 is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_VMAP_STACK=y
diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15
deleted file mode 100644
index eebe00b7d2..0000000000
--- a/target/linux/mediatek/mt7623/config-5.15
+++ /dev/null
@@ -1,578 +0,0 @@
-# CONFIG_AIO is not set
-# CONFIG_AIROHA_EN8811H_PHY is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
-CONFIG_ARM_DMA_USE_IOMMU=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_LED=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLEANCACHE=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-CONFIG_COMMON_CLK_MT2701_AUDSYS=y
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
-CONFIG_COMMON_CLK_MT2701_G3DSYS=y
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
-# CONFIG_COMMON_CLK_MT7622 is not set
-# CONFIG_COMMON_CLK_MT7629 is not set
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEBUG_MT6589_UART0=y
-# CONFIG_DEBUG_MT8127_UART0 is not set
-# CONFIG_DEBUG_MT8135_UART3 is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0x11004000
-CONFIG_DEBUG_UART_VIRT=0xf1004000
-CONFIG_DEBUG_UNCOMPRESS=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DISPLAY_CONNECTOR=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_LIMA=y
-CONFIG_DRM_LVDS_CODEC=y
-CONFIG_DRM_MEDIATEK=y
-CONFIG_DRM_MEDIATEK_HDMI=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
-CONFIG_DRM_SCHED=y
-CONFIG_DRM_SIMPLE_BRIDGE=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KEYBOARD_MTK_PMIC=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_MT6323=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-CONFIG_MACH_MT7623=y
-# CONFIG_MACH_MT7629 is not set
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTK_CMDQ=y
-CONFIG_MTK_CMDQ_MBOX=y
-CONFIG_MTK_CQDMA=y
-# CONFIG_MTK_HSDMA is not set
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_IOMMU=y
-CONFIG_MTK_IOMMU_V1=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_SMI=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MTK_EFUSE=y
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MTK_HDMI=y
-CONFIG_PHY_MTK_MIPI_DSI=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT2701=y
-CONFIG_PINCTRL_MT6397=y
-CONFIG_PINCTRL_MT7623=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_MT6323 is not set
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MT6323=y
-# CONFIG_REGULATOR_MT6358 is not set
-# CONFIG_REGULATOR_MT6380 is not set
-# CONFIG_REGULATOR_MT6397 is not set
-# CONFIG_REGULATOR_RT5190A is not set
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MT6397 is not set
-# CONFIG_RTC_DRV_MT7622 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-# CONFIG_SPI_MTK_NOR is not set
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_F_ECM=y
-CONFIG_USB_F_MASS_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_USB_G_MULTI=y
-CONFIG_USB_G_MULTI_CDC=y
-# CONFIG_USB_G_MULTI_RNDIS is not set
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_INVENTRA_DMA=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_MEDIATEK=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_U_ETHER=y
-CONFIG_USB_U_SERIAL=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7623/config-6.1 b/target/linux/mediatek/mt7623/config-6.1
index 06bffc9d8b..1d0df86a98 100644
--- a/target/linux/mediatek/mt7623/config-6.1
+++ b/target/linux/mediatek/mt7623/config-6.1
@@ -386,6 +386,8 @@ CONFIG_MTK_SCPSYS_PM_DOMAINS=y
 CONFIG_MTK_SMI=y
 # CONFIG_MTK_SVS is not set
 CONFIG_MTK_THERMAL=y
+CONFIG_MTK_SOC_THERMAL=y
+# CONFIG_MTK_LVTS_THERMAL is not set
 CONFIG_MTK_TIMER=y
 # CONFIG_MTK_UART_APDMA is not set
 # CONFIG_MUSB_PIO_ONLY is not set
diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15
deleted file mode 100644
index 802d00e679..0000000000
--- a/target/linux/mediatek/mt7629/config-5.15
+++ /dev/null
@@ -1,327 +0,0 @@
-# CONFIG_AIROHA_EN8811H_PHY is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2701 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7629=y
-CONFIG_COMMON_CLK_MT7629_ETHSYS=y
-CONFIG_COMMON_CLK_MT7629_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEFAULT_HOSTNAME="(mt7629)"
-CONFIG_DIMLIB=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-# CONFIG_MACH_MT7623 is not set
-CONFIG_MACH_MT7629=y
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_PMIC_WRAP is not set
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_TIMER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NETFILTER=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MTK_EFUSE is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT7629=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_SWAP is not set
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7629/config-6.1 b/target/linux/mediatek/mt7629/config-6.1
index c8cd473c55..d1b9d6c81e 100644
--- a/target/linux/mediatek/mt7629/config-6.1
+++ b/target/linux/mediatek/mt7629/config-6.1
@@ -108,6 +108,7 @@ CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_SUPPORT=y
 CONFIG_EINT_MTK=y
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+# CONFIG_FIT_PARTITION is not set
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_FRAME_WARN=1024
diff --git a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch
deleted file mode 100644
index 1f9e24a4d2..0000000000
--- a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch
+++ /dev/null
@@ -1,119 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -1,7 +1,6 @@
- /*
-- * Copyright (c) 2017 MediaTek Inc.
-- * Author: Ming Huang <ming.huang@mediatek.com>
-- *	   Sean Wang <sean.wang@mediatek.com>
-+ * Copyright (c) 2018 MediaTek Inc.
-+ * Author: Ryder Lee <ryder.lee@mediatek.com>
-  *
-  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
-  */
-@@ -23,7 +22,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {
-@@ -40,23 +39,22 @@
- 
- 	gpio-keys {
- 		compatible = "gpio-keys";
--		poll-interval = <100>;
- 
- 		factory {
- 			label = "factory";
- 			linux,code = <BTN_0>;
--			gpios = <&pio 0 0>;
-+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
- 		};
- 
- 		wps {
- 			label = "wps";
- 			linux,code = <KEY_WPS_BUTTON>;
--			gpios = <&pio 102 0>;
-+			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
- 		};
- 	};
- 
- 	memory@40000000 {
--		reg = <0 0x40000000 0 0x20000000>;
-+		reg = <0 0x40000000 0 0x40000000>;
- 	};
- 
- 	reg_1p8v: regulator-1p8v {
-@@ -132,22 +130,22 @@
- 
- 				port@0 {
- 					reg = <0>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@4 {
-@@ -236,15 +234,28 @@
- 
- &pcie {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>;
-+	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
- 	status = "okay";
- 
- 	pcie@0,0 {
- 		status = "okay";
- 	};
-+
-+	pcie@1,0 {
-+		status = "okay";
-+	};
- };
- 
- &pio {
-+	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
-+	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
-+	 */
-+	asm_sel {
-+		gpio-hog;
-+		gpios = <90 GPIO_ACTIVE_HIGH>;
-+		output-high;
-+	};
-+
- 	/* eMMC is shared pin with parallel NAND */
- 	emmc_pins_default: emmc-pins-default {
- 		mux {
-@@ -521,11 +532,11 @@
- };
- 
- &sata {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &spi0 {
diff --git a/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch
deleted file mode 100644
index 254b5f9eb7..0000000000
--- a/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch
+++ /dev/null
@@ -1,60 +0,0 @@
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -18,6 +18,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
- 	};
- 
- 	gpio-keys {
-@@ -70,6 +71,10 @@
- 		compatible = "mediatek,eth-mac";
- 		reg = <0>;
- 		phy-mode = "2500base-x";
-+
-+		nvmem-cells = <&macaddr_factory_2a>;
-+		nvmem-cell-names = "mac-address";
-+
- 		fixed-link {
- 			speed = <2500>;
- 			full-duplex;
-@@ -82,6 +87,9 @@
- 		reg = <1>;
- 		phy-mode = "gmii";
- 		phy-handle = <&phy0>;
-+
-+		nvmem-cells = <&macaddr_factory_24>;
-+		nvmem-cell-names = "mac-address";
- 	};
- 
- 	mdio: mdio-bus {
-@@ -133,8 +141,9 @@
- 			};
- 
- 			partition@b0000 {
--				label = "kernel";
-+				label = "firmware";
- 				reg = <0xb0000 0xb50000>;
-+				compatible = "denx,fit";
- 			};
- 		};
- 	};
-@@ -272,3 +281,17 @@
- 	pinctrl-0 = <&watchdog_pins>;
- 	status = "okay";
- };
-+
-+&factory {
-+	compatible = "nvmem-cells";
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+
-+	macaddr_factory_24: macaddr@24 {
-+		reg = <0x24 0x6>;
-+	};
-+
-+	macaddr_factory_2a: macaddr@2a {
-+		reg = <0x2a 0x6>;
-+	};
-+};
diff --git a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch
deleted file mode 100644
index 04df7b927b..0000000000
--- a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Fri, 29 Apr 2022 10:40:56 +0800
-Subject: [PATCH] arm: mediatek: select arch timer for mt7623
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
----
- arch/arm/mach-mediatek/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -26,6 +26,7 @@ config MACH_MT6592
- config MACH_MT7623
- 	bool "MediaTek MT7623 SoCs support"
- 	default ARCH_MEDIATEK
-+	select HAVE_ARM_ARCH_TIMER
- 
- config MACH_MT7629
- 	bool "MediaTek MT7629 SoCs support"
diff --git a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch
deleted file mode 100644
index 79b051147a..0000000000
--- a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -559,6 +559,7 @@
- 		compatible = "mediatek,mt7622-nor",
- 			     "mediatek,mt8173-nor";
- 		reg = <0 0x11014000 0 0xe0>;
-+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
- 		clocks = <&pericfg CLK_PERI_FLASH_PD>,
- 			 <&topckgen CLK_TOP_FLASH_SEL>;
- 		clock-names = "spi", "sf";
diff --git a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch
deleted file mode 100644
index da42c07728..0000000000
--- a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -111,7 +111,7 @@
- 	};
- 
- 	psci {
--		compatible  = "arm,psci-0.2";
-+		compatible  = "arm,psci-1.0";
- 		method      = "smc";
- 	};
- 
-@@ -127,6 +127,13 @@
- 		#size-cells = <2>;
- 		ranges;
- 
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;
diff --git a/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch
deleted file mode 100644
index 8dc53d2985..0000000000
--- a/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,6 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
-+		bootargs = "console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {
diff --git a/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch
deleted file mode 100644
index 07a2eae245..0000000000
--- a/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -22,7 +22,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {
diff --git a/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch
deleted file mode 100644
index 6ce85efde9..0000000000
--- a/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch
+++ /dev/null
@@ -1,37 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -18,6 +18,7 @@
- 
- 	aliases {
- 		serial0 = &uart0;
-+		ethernet0 = &gmac0;
- 	};
- 
- 	chosen {
-@@ -160,22 +161,22 @@
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@4 {
- 					reg = <4>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@6 {
diff --git a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch
deleted file mode 100644
index f728b96564..0000000000
--- a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch
+++ /dev/null
@@ -1,56 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -19,6 +19,10 @@
- 	aliases {
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
- 	};
- 
- 	chosen {
-@@ -42,8 +46,8 @@
- 		compatible = "gpio-keys";
- 
- 		factory {
--			label = "factory";
--			linux,code = <BTN_0>;
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
- 			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- 		};
- 
-@@ -57,17 +61,25 @@
- 	leds {
- 		compatible = "gpio-leds";
- 
--		green {
--			label = "bpi-r64:pio:green";
--			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
-+		led_system_blue: blue {
-+			label = "bpi-r64:pio:blue";
-+			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
- 
--		red {
--			label = "bpi-r64:pio:red";
--			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+		led_system_green: green {
-+			label = "bpi-r64:pio:green";
-+			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
-+
-+/*
-+ *		red {
-+ *			label = "bpi-r64:pio:red";
-+ *			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+ *			default-state = "off";
-+ *		};
-+ */
- 	};
- 
- 	memory@40000000 {
diff --git a/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch
deleted file mode 100644
index 1f41142aac..0000000000
--- a/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -564,12 +564,16 @@
- 	status = "okay";
- };
- 
-+&rtc {
-+	status = "disabled";
-+};
-+
- &sata {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &spi0 {
diff --git a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch
deleted file mode 100644
index 34539a5d10..0000000000
--- a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -259,14 +259,42 @@
- 	status = "disabled";
- };
- 
--&nor_flash {
--	pinctrl-names = "default";
--	pinctrl-0 = <&spi_nor_pins>;
--	status = "disabled";
-+&bch {
-+	status = "okay";
-+};
- 
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
- 	flash@0 {
--		compatible = "jedec,spi-nor";
-+		compatible = "spi-nand";
- 		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x0 0x80000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "fip";
-+				reg = <0x80000 0x200000>;
-+				read-only;
-+			};
-+
-+			partition@280000 {
-+				label = "ubi";
-+				reg = <0x280000 0x7d80000>;
-+			};
-+		};
- 	};
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch
deleted file mode 100644
index 7fb62e7403..0000000000
--- a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:38 +0100
-Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware
- engines
-
-Add the necessary helpers to register/unregister hardware ECC engines
-that will be called from ECC engine drivers.
-
-Also add helpers to get the right engine from the user
-perspective. Keep a reference of the in use ECC engine in order to
-prevent modules to be unloaded. Put the reference when the engine gets
-retired.
-
-A static list of hardware (only) ECC engines is setup to keep track of
-the registered engines.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com
-(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152)
----
- drivers/mtd/nand/core.c  | 10 +++--
- drivers/mtd/nand/ecc.c   | 88 ++++++++++++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h | 28 +++++++++++++
- 3 files changed, 123 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/core.c
-+++ b/drivers/mtd/nand/core.c
-@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct
- 		nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
-+		if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
-+			return -EPROBE_DEFER;
- 		break;
- 	default:
- 		pr_err("Missing ECC engine type\n");
-@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct
- {
- 	switch (nand->ecc.ctx.conf.engine_type) {
- 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
--		pr_err("On-host hardware ECC engines not supported yet\n");
-+		nand_ecc_put_on_host_hw_engine(nand);
- 		break;
- 	case NAND_ECC_ENGINE_TYPE_NONE:
- 	case NAND_ECC_ENGINE_TYPE_SOFT:
-@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_
- 	/* Look for the ECC engine to use */
- 	ret = nanddev_get_ecc_engine(nand);
- 	if (ret) {
--		pr_err("No ECC engine found\n");
-+		if (ret != -EPROBE_DEFER)
-+			pr_err("No ECC engine found\n");
-+
- 		return ret;
- 	}
- 
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -96,6 +96,12 @@
- #include <linux/module.h>
- #include <linux/mtd/nand.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+
-+static LIST_HEAD(on_host_hw_engines);
-+static DEFINE_MUTEX(on_host_hw_engines_mutex);
- 
- /**
-  * nand_ecc_init_ctx - Init the ECC engine context
-@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_
- }
- EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
- 
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	if (!engine)
-+		return -EINVAL;
-+
-+	/* Prevent multiple registrations of one engine */
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item == engine)
-+			return 0;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_add_tail(&engine->node, &on_host_hw_engines);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
-+
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+	if (!engine)
-+		return -EINVAL;
-+
-+	mutex_lock(&on_host_hw_engines_mutex);
-+	list_del(&engine->node);
-+	mutex_unlock(&on_host_hw_engines_mutex);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
-+
-+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
-+{
-+	struct nand_ecc_engine *item;
-+
-+	list_for_each_entry(item, &on_host_hw_engines, node)
-+		if (item->dev == dev)
-+			return item;
-+
-+	return NULL;
-+}
-+
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *engine = NULL;
-+	struct device *dev = &nand->mtd.dev;
-+	struct platform_device *pdev;
-+	struct device_node *np;
-+
-+	if (list_empty(&on_host_hw_engines))
-+		return NULL;
-+
-+	/* Check for an explicit nand-ecc-engine property */
-+	np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
-+	if (np) {
-+		pdev = of_find_device_by_node(np);
-+		if (!pdev)
-+			return ERR_PTR(-EPROBE_DEFER);
-+
-+		engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
-+		platform_device_put(pdev);
-+		of_node_put(np);
-+
-+		if (!engine)
-+			return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	if (engine)
-+		get_device(engine->dev);
-+
-+	return engine;
-+}
-+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
-+
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
-+{
-+	put_device(nand->ecc.engine->dev);
-+}
-+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops {
- };
- 
- /**
-+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated
-+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value
-+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly
-+ *                                         correction, does not need to copy
-+ *                                         data around
-+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the
-+ *                                        data into its own area before use
-+ */
-+enum nand_ecc_engine_integration {
-+	NAND_ECC_ENGINE_INTEGRATION_INVALID,
-+	NAND_ECC_ENGINE_INTEGRATION_PIPELINED,
-+	NAND_ECC_ENGINE_INTEGRATION_EXTERNAL,
-+};
-+
-+/**
-  * struct nand_ecc_engine - ECC engine abstraction for NAND devices
-+ * @dev: Host device
-+ * @node: Private field for registration time
-  * @ops: ECC engine operations
-+ * @integration: How the engine is integrated with the host
-+ *               (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines)
-+ * @priv: Private data
-  */
- struct nand_ecc_engine {
-+	struct device *dev;
-+	struct list_head node;
- 	struct nand_ecc_engine_ops *ops;
-+	enum nand_ecc_engine_integration integration;
-+	void *priv;
- };
- 
- void of_get_nand_ecc_user_config(struct nand_device *nand);
-@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_
- int nand_ecc_finish_io_req(struct nand_device *nand,
- 			   struct nand_page_io_req *req);
- bool nand_ecc_is_strong_enough(struct nand_device *nand);
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
- struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
diff --git a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch
deleted file mode 100644
index 61a39ee0e5..0000000000
--- a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:39 +0100
-Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context
-
-Introduce nand_to_ecc_ctx() which will allow to easily jump to the
-private pointer of an ECC context given a NAND device. This is very
-handy, from the prepare or finish ECC hook, to get the internal context
-out of the NAND device object.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com
-(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4)
----
- include/linux/mtd/nand.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *
- int nanddev_ecc_engine_init(struct nand_device *nand);
- void nanddev_ecc_engine_cleanup(struct nand_device *nand);
- 
-+static inline void *nand_to_ecc_ctx(struct nand_device *nand)
-+{
-+	return nand->ecc.ctx.priv;
-+}
-+
- /* BBT related functions */
- enum nand_bbt_block_status {
- 	NAND_BBT_BLOCK_STATUS_UNKNOWN,
diff --git a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch
deleted file mode 100644
index 29b62880ab..0000000000
--- a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:41 +0100
-Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a
- pilelined engine device
-
-In a pipelined engine situation, we might either have the host which
-internally has support for error correction, or have it using an
-external hardware block for this purpose. In the former case, the host
-is also the ECC engine. In the latter case, it is not. In order to get
-the right pointers on the right devices (for example: in order to devm_*
-allocate variables), let's introduce this helper which can safely be
-called by pipelined ECC engines in order to retrieve the right device
-structure.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com
-(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309)
----
- drivers/mtd/nand/ecc.c   | 31 +++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h |  1 +
- 2 files changed, 32 insertions(+)
-
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru
- }
- EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
- 
-+/*
-+ * In the case of a pipelined engine, the device registering the ECC
-+ * engine is not necessarily the ECC engine itself but may be a host controller.
-+ * It is then useful to provide a helper to retrieve the right device object
-+ * which actually represents the ECC engine.
-+ */
-+struct device *nand_ecc_get_engine_dev(struct device *host)
-+{
-+	struct platform_device *ecc_pdev;
-+	struct device_node *np;
-+
-+	/*
-+	 * If the device node contains this property, it means we need to follow
-+	 * it in order to get the right ECC engine device we are looking for.
-+	 */
-+	np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0);
-+	if (!np)
-+		return host;
-+
-+	ecc_pdev = of_find_device_by_node(np);
-+	if (!ecc_pdev) {
-+		of_node_put(np);
-+		return NULL;
-+	}
-+
-+	platform_device_put(ecc_pdev);
-+	of_node_put(np);
-+
-+	return &ecc_pdev->dev;
-+}
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
- void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
-+struct device *nand_ecc_get_engine_dev(struct device *host);
- 
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
diff --git a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch
deleted file mode 100644
index 1e7f572dd6..0000000000
--- a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:17:56 +0100
-Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure
-
-Create a spi_controller_mem_caps structure and put it within the
-spi_controller structure close to the spi_controller_mem_ops
-strucure. So far the only field in this structure is the support for dtr
-operations, but soon we will add another parameter.
-
-Also create a helper to parse the capabilities and check if the
-requested capability has been set or not.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Reviewed-by: Mark Brown <broonie@kernel.org>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com
-(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20)
----
- include/linux/spi/spi-mem.h | 11 +++++++++++
- include/linux/spi/spi.h     |  3 +++
- 2 files changed, 14 insertions(+)
-
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -286,6 +286,17 @@ struct spi_controller_mem_ops {
- };
- 
- /**
-+ * struct spi_controller_mem_caps - SPI memory controller capabilities
-+ * @dtr: Supports DTR operations
-+ */
-+struct spi_controller_mem_caps {
-+	bool dtr;
-+};
-+
-+#define spi_mem_controller_is_capable(ctlr, cap)	\
-+	((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
-+
-+/**
-  * struct spi_mem_driver - SPI memory driver
-  * @spidrv: inherit from a SPI driver
-  * @probe: probe a SPI memory. Usually where detection/initialization takes
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -23,6 +23,7 @@ struct software_node;
- struct spi_controller;
- struct spi_transfer;
- struct spi_controller_mem_ops;
-+struct spi_controller_mem_caps;
- 
- /*
-  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
-@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill
-  * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
-  *	     This field is optional and should only be implemented if the
-  *	     controller has native support for memory like operations.
-+ * @mem_caps: controller capabilities for the handling of memory operations.
-  * @unprepare_message: undo any work done by prepare_message().
-  * @slave_abort: abort the ongoing transfer request on an SPI slave controller
-  * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
-@@ -643,6 +645,7 @@ struct spi_controller {
- 
- 	/* Optimized handlers for SPI memory-like operations. */
- 	const struct spi_controller_mem_ops *mem_ops;
-+	const struct spi_controller_mem_caps *mem_caps;
- 
- 	/* gpio chip select */
- 	int			*cs_gpios;
diff --git a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch
deleted file mode 100644
index 9f01fdb835..0000000000
--- a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:17:57 +0100
-Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities
-
-Controllers can now provide a spi-mem capabilities structure. Let's make
-use of it in spi_mem_controller_default_supports_op(). As we want to
-check for DTR operations as well as normal operations in a single
-helper, let's pull the necessary checks from spi_mem_dtr_supports_op()
-for now.
-
-However, because no controller provide these extra capabilities, this
-change has no effect so far.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com
-(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37)
----
- drivers/spi/spi-mem.c | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
--	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
--		return false;
-+	struct spi_controller *ctlr = mem->spi->controller;
-+	bool op_is_dtr =
-+		op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
- 
--	if (op->cmd.nbytes != 1)
--		return false;
-+	if (op_is_dtr) {
-+		if (!spi_mem_controller_is_capable(ctlr, dtr))
-+			return false;
-+
-+		if (op->cmd.nbytes != 2)
-+			return false;
-+	} else {
-+		if (op->cmd.nbytes != 1)
-+			return false;
-+	}
- 
- 	return spi_mem_check_buswidth(mem, op);
- }
diff --git a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch
deleted file mode 100644
index c313a455b6..0000000000
--- a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch
+++ /dev/null
@@ -1,111 +0,0 @@
-From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:00 +0100
-Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper
-
-Now that spi_mem_default_supports_op() has access to the static
-controller capabilities (relating to memory operations), and now that
-these capabilities have been filled by the relevant controllers, there
-is no need for a specific helper checking only DTR operations, so let's
-just kill spi_mem_dtr_supports_op() and simply use
-spi_mem_default_supports_op() instead.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com
-(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20)
----
- drivers/spi/spi-cadence-quadspi.c |  5 +----
- drivers/spi/spi-mem.c             | 10 ----------
- drivers/spi/spi-mxic.c            | 10 +---------
- include/linux/spi/spi-mem.h       | 11 -----------
- 4 files changed, 2 insertions(+), 34 deletions(-)
-
---- a/drivers/spi/spi-cadence-quadspi.c
-+++ b/drivers/spi/spi-cadence-quadspi.c
-@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct
- 		return false;
- 	}
- 
--	if (all_true)
--		return spi_mem_dtr_supports_op(mem, op);
--	else
--		return spi_mem_default_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc
- 	return true;
- }
- 
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	if (op->cmd.nbytes != 2)
--		return false;
--
--	return spi_mem_check_buswidth(mem, op);
--}
--EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
--
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op)
- {
---- a/drivers/spi/spi-mxic.c
-+++ b/drivers/spi/spi-mxic.c
-@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi
- static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
- 				     const struct spi_mem_op *op)
- {
--	bool all_false;
--
- 	if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
- 	    op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
- 		return false;
-@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str
- 	if (op->addr.nbytes > 7)
- 		return false;
- 
--	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
--		    !op->data.dtr;
--
--	if (all_false)
--		return spi_mem_default_supports_op(mem, op);
--	else
--		return spi_mem_dtr_supports_op(mem, op);
-+	return spi_mem_default_supports_op(mem, op);
- }
- 
- static int mxic_spi_mem_exec_op(struct spi_mem *mem,
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat
- 
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- 				 const struct spi_mem_op *op);
--
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op);
--
- #else
- static inline int
- spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
-@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct
- {
- 	return false;
- }
--
--static inline
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
--			     const struct spi_mem_op *op)
--{
--	return false;
--}
- #endif /* CONFIG_SPI_MEM */
- 
- int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
diff --git a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch
deleted file mode 100644
index 6d7e47650b..0000000000
--- a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:01 +0100
-Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
- structure
-
-Soon the SPI-NAND core will need a way to request a SPI controller to
-enable ECC support for a given operation. This is because of the
-pipelined integration of certain ECC engines, which are directly managed
-by the SPI controller itself.
-
-Introduce a spi_mem_op additional field for this purpose: ecc.
-
-So far this field is left unset and checked to be false by all
-the SPI controller drivers in their ->supports_op() hook, as they all
-call spi_mem_default_supports_op().
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Acked-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com
-(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
----
- drivers/spi/spi-mem.c       | 5 +++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 9 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
- 			return false;
- 	}
- 
-+	if (op->data.ecc) {
-+		if (!spi_mem_controller_is_capable(ctlr, ecc))
-+			return false;
-+	}
-+
- 	return spi_mem_check_buswidth(mem, op);
- }
- EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
-  * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
-  * @data.buswidth: number of IO lanes used to send/receive the data
-  * @data.dtr: whether the data should be sent in DTR mode or not
-+ * @data.ecc: whether error correction is required or not
-  * @data.dir: direction of the transfer
-  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
-  *		 operation does not involve transferring data
-@@ -119,6 +120,7 @@ struct spi_mem_op {
- 	struct {
- 		u8 buswidth;
- 		u8 dtr : 1;
-+		u8 ecc : 1;
- 		enum spi_mem_data_dir dir;
- 		unsigned int nbytes;
- 		union {
-@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
- /**
-  * struct spi_controller_mem_caps - SPI memory controller capabilities
-  * @dtr: Supports DTR operations
-+ * @ecc: Supports operations with error correction
-  */
- struct spi_controller_mem_caps {
- 	bool dtr;
-+	bool ecc;
- };
- 
- #define spi_mem_controller_is_capable(ctlr, cap)	\
diff --git a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch
deleted file mode 100644
index 87c7b7cd29..0000000000
--- a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:02 +0100
-Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation
-
-As we will soon tweak the dirmap creation to act a little bit
-differently depending on the picked ECC engine, we need to initialize
-dirmaps after ECC engines. This should not have any effect as dirmaps
-are not yet used at this point.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com
-(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949)
----
- drivers/mtd/nand/spi/core.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1221,14 +1221,6 @@ static int spinand_init(struct spinand_d
- 	if (ret)
- 		goto err_free_bufs;
- 
--	ret = spinand_create_dirmaps(spinand);
--	if (ret) {
--		dev_err(dev,
--			"Failed to create direct mappings for read/write operations (err = %d)\n",
--			ret);
--		goto err_manuf_cleanup;
--	}
--
- 	ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
- 	if (ret)
- 		goto err_manuf_cleanup;
-@@ -1263,6 +1255,14 @@ static int spinand_init(struct spinand_d
- 	mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
- 	mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
- 
-+	ret = spinand_create_dirmaps(spinand);
-+	if (ret) {
-+		dev_err(dev,
-+			"Failed to create direct mappings for read/write operations (err = %d)\n",
-+			ret);
-+		goto err_cleanup_ecc_engine;
-+	}
-+
- 	return 0;
- 
- err_cleanup_ecc_engine:
diff --git a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch
deleted file mode 100644
index 35912cd2cd..0000000000
--- a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:03 +0100
-Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC
- operations
-
-In order for pipelined ECC engines to be able to enable/disable the ECC
-engine only when needed and avoid races when future parallel-operations
-will be supported, we need to provide the information about the use of
-the ECC engine in the direct mapping hooks. As direct mapping
-configurations are meant to be static, it is best to create two new
-mappings: one for regular 'raw' accesses and one for accesses involving
-correction. It is up to the driver to use or not the new ECC enable
-boolean contained in the spi-mem operation.
-
-As dirmaps are not free (they consume a few pages of MMIO address space)
-and because these extra entries are only meant to be used by pipelined
-engines, let's limit their use to this specific type of engine and save
-a bit of memory with all the other setups.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com
-(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2)
----
- drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++--
- include/linux/mtd/spinand.h |  2 ++
- 2 files changed, 35 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st
- 		}
- 	}
- 
--	rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+	else
-+		rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
-@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str
- 			       req->ooblen);
- 	}
- 
--	wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	if (req->mode == MTD_OPS_RAW)
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+	else
-+		wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
- 
- 	while (nbytes) {
- 		ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
-@@ -875,6 +881,31 @@ static int spinand_create_dirmap(struct
- 
- 	spinand->dirmaps[plane].rdesc = desc;
- 
-+	if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
-+		spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
-+		spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
-+
-+		return 0;
-+	}
-+
-+	info.op_tmpl = *spinand->op_templates.update_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].wdesc_ecc = desc;
-+
-+	info.op_tmpl = *spinand->op_templates.read_cache;
-+	info.op_tmpl.data.ecc = true;
-+	desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+					  spinand->spimem, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].rdesc_ecc = desc;
-+
- 	return 0;
- }
- 
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -392,6 +392,8 @@ struct spinand_info {
- struct spinand_dirmap {
- 	struct spi_mem_dirmap_desc *wdesc;
- 	struct spi_mem_dirmap_desc *rdesc;
-+	struct spi_mem_dirmap_desc *wdesc_ecc;
-+	struct spi_mem_dirmap_desc *rdesc_ecc;
- };
- 
- /**
diff --git a/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch b/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch
deleted file mode 100644
index fd9098eae9..0000000000
--- a/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch
+++ /dev/null
@@ -1,1383 +0,0 @@
-From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Tue, 22 Mar 2022 18:44:21 +0800
-Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module
-
-this code will be used in mediatek snfi spi-mem controller with
-pipelined ECC engine.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d)
----
- drivers/mtd/nand/Kconfig                                   | 7 +++++++
- drivers/mtd/nand/Makefile                                  | 1 +
- drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c}              | 3 +--
- drivers/mtd/nand/raw/Kconfig                               | 1 +
- drivers/mtd/nand/raw/Makefile                              | 2 +-
- drivers/mtd/nand/raw/mtk_nand.c                            | 2 +-
- .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0
- 7 files changed, 12 insertions(+), 4 deletions(-)
- rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%)
- rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT
- 	bool "Support MediaTek NAND Bad-block Management Table"
- 	default n
- 
-+config MTD_NAND_ECC_MEDIATEK
-+	tristate "Mediatek hardware ECC engine"
-+	depends on HAS_IOMEM
-+	select MTD_NAND_ECC
-+	help
-+	  This enables support for the hardware ECC engine from Mediatek.
-+
- endmenu
- 
- endmenu
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -3,6 +3,7 @@
- nandcore-objs := core.o bbt.o
- obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
- obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
-+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
- 
- obj-y	+= onenand/
- obj-y	+= raw/
---- a/drivers/mtd/nand/raw/mtk_ecc.c
-+++ /dev/null
-@@ -1,599 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0 OR MIT
--/*
-- * MTK ECC controller driver.
-- * Copyright (C) 2016  MediaTek Inc.
-- * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-- *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-- */
--
--#include <linux/platform_device.h>
--#include <linux/dma-mapping.h>
--#include <linux/interrupt.h>
--#include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/iopoll.h>
--#include <linux/of.h>
--#include <linux/of_platform.h>
--#include <linux/mutex.h>
--
--#include "mtk_ecc.h"
--
--#define ECC_IDLE_MASK		BIT(0)
--#define ECC_IRQ_EN		BIT(0)
--#define ECC_PG_IRQ_SEL		BIT(1)
--#define ECC_OP_ENABLE		(1)
--#define ECC_OP_DISABLE		(0)
--
--#define ECC_ENCCON		(0x00)
--#define ECC_ENCCNFG		(0x04)
--#define		ECC_MS_SHIFT		(16)
--#define ECC_ENCDIADDR		(0x08)
--#define ECC_ENCIDLE		(0x0C)
--#define ECC_DECCON		(0x100)
--#define ECC_DECCNFG		(0x104)
--#define		DEC_EMPTY_EN		BIT(31)
--#define		DEC_CNFG_CORRECT	(0x3 << 12)
--#define ECC_DECIDLE		(0x10C)
--#define ECC_DECENUM0		(0x114)
--
--#define ECC_TIMEOUT		(500000)
--
--#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
--#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
--
--struct mtk_ecc_caps {
--	u32 err_mask;
--	u32 err_shift;
--	const u8 *ecc_strength;
--	const u32 *ecc_regs;
--	u8 num_ecc_strength;
--	u8 ecc_mode_shift;
--	u32 parity_bits;
--	int pg_irq_sel;
--};
--
--struct mtk_ecc {
--	struct device *dev;
--	const struct mtk_ecc_caps *caps;
--	void __iomem *regs;
--	struct clk *clk;
--
--	struct completion done;
--	struct mutex lock;
--	u32 sectors;
--
--	u8 *eccdata;
--};
--
--/* ecc strength that each IP supports */
--static const u8 ecc_strength_mt2701[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60
--};
--
--static const u8 ecc_strength_mt2712[] = {
--	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
--	40, 44, 48, 52, 56, 60, 68, 72, 80
--};
--
--static const u8 ecc_strength_mt7622[] = {
--	4, 6, 8, 10, 12
--};
--
--enum mtk_ecc_regs {
--	ECC_ENCPAR00,
--	ECC_ENCIRQ_EN,
--	ECC_ENCIRQ_STA,
--	ECC_DECDONE,
--	ECC_DECIRQ_EN,
--	ECC_DECIRQ_STA,
--};
--
--static int mt2701_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt2712_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x300,
--	[ECC_ENCIRQ_EN] =       0x80,
--	[ECC_ENCIRQ_STA] =      0x84,
--	[ECC_DECDONE] =         0x124,
--	[ECC_DECIRQ_EN] =       0x200,
--	[ECC_DECIRQ_STA] =      0x204,
--};
--
--static int mt7622_ecc_regs[] = {
--	[ECC_ENCPAR00] =        0x10,
--	[ECC_ENCIRQ_EN] =       0x30,
--	[ECC_ENCIRQ_STA] =      0x34,
--	[ECC_DECDONE] =         0x11c,
--	[ECC_DECIRQ_EN] =       0x140,
--	[ECC_DECIRQ_STA] =      0x144,
--};
--
--static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
--				     enum mtk_ecc_operation op)
--{
--	struct device *dev = ecc->dev;
--	u32 val;
--	int ret;
--
--	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
--					val & ECC_IDLE_MASK,
--					10, ECC_TIMEOUT);
--	if (ret)
--		dev_warn(dev, "%s NOT idle\n",
--			 op == ECC_ENCODE ? "encoder" : "decoder");
--}
--
--static irqreturn_t mtk_ecc_irq(int irq, void *id)
--{
--	struct mtk_ecc *ecc = id;
--	u32 dec, enc;
--
--	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
--		    & ECC_IRQ_EN;
--	if (dec) {
--		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		if (dec & ecc->sectors) {
--			/*
--			 * Clear decode IRQ status once again to ensure that
--			 * there will be no extra IRQ.
--			 */
--			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
--			ecc->sectors = 0;
--			complete(&ecc->done);
--		} else {
--			return IRQ_HANDLED;
--		}
--	} else {
--		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
--		      & ECC_IRQ_EN;
--		if (enc)
--			complete(&ecc->done);
--		else
--			return IRQ_NONE;
--	}
--
--	return IRQ_HANDLED;
--}
--
--static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	u32 ecc_bit, dec_sz, enc_sz;
--	u32 reg, i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (ecc->caps->ecc_strength[i] == config->strength)
--			break;
--	}
--
--	if (i == ecc->caps->num_ecc_strength) {
--		dev_err(ecc->dev, "invalid ecc strength %d\n",
--			config->strength);
--		return -EINVAL;
--	}
--
--	ecc_bit = i;
--
--	if (config->op == ECC_ENCODE) {
--		/* configure ECC encoder (in bits) */
--		enc_sz = config->len << 3;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (enc_sz << ECC_MS_SHIFT);
--		writel(reg, ecc->regs + ECC_ENCCNFG);
--
--		if (config->mode != ECC_NFI_MODE)
--			writel(lower_32_bits(config->addr),
--			       ecc->regs + ECC_ENCDIADDR);
--
--	} else {
--		/* configure ECC decoder (in bits) */
--		dec_sz = (config->len << 3) +
--			 config->strength * ecc->caps->parity_bits;
--
--		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
--		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
--		reg |= DEC_EMPTY_EN;
--		writel(reg, ecc->regs + ECC_DECCNFG);
--
--		if (config->sectors)
--			ecc->sectors = 1 << (config->sectors - 1);
--	}
--
--	return 0;
--}
--
--void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
--		       int sectors)
--{
--	u32 offset, i, err;
--	u32 bitflips = 0;
--
--	stats->corrected = 0;
--	stats->failed = 0;
--
--	for (i = 0; i < sectors; i++) {
--		offset = (i >> 2) << 2;
--		err = readl(ecc->regs + ECC_DECENUM0 + offset);
--		err = err >> ((i % 4) * ecc->caps->err_shift);
--		err &= ecc->caps->err_mask;
--		if (err == ecc->caps->err_mask) {
--			/* uncorrectable errors */
--			stats->failed++;
--			continue;
--		}
--
--		stats->corrected += err;
--		bitflips = max_t(u32, bitflips, err);
--	}
--
--	stats->bitflips = bitflips;
--}
--EXPORT_SYMBOL(mtk_ecc_get_stats);
--
--void mtk_ecc_release(struct mtk_ecc *ecc)
--{
--	clk_disable_unprepare(ecc->clk);
--	put_device(ecc->dev);
--}
--EXPORT_SYMBOL(mtk_ecc_release);
--
--static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
--{
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
--
--	mtk_ecc_wait_idle(ecc, ECC_DECODE);
--	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
--}
--
--static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
--{
--	struct platform_device *pdev;
--	struct mtk_ecc *ecc;
--
--	pdev = of_find_device_by_node(np);
--	if (!pdev)
--		return ERR_PTR(-EPROBE_DEFER);
--
--	ecc = platform_get_drvdata(pdev);
--	if (!ecc) {
--		put_device(&pdev->dev);
--		return ERR_PTR(-EPROBE_DEFER);
--	}
--
--	clk_prepare_enable(ecc->clk);
--	mtk_ecc_hw_init(ecc);
--
--	return ecc;
--}
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
--{
--	struct mtk_ecc *ecc = NULL;
--	struct device_node *np;
--
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
--	if (np) {
--		ecc = mtk_ecc_get(np);
--		of_node_put(np);
--	}
--
--	return ecc;
--}
--EXPORT_SYMBOL(of_mtk_ecc_get);
--
--int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
--	enum mtk_ecc_operation op = config->op;
--	u16 reg_val;
--	int ret;
--
--	ret = mutex_lock_interruptible(&ecc->lock);
--	if (ret) {
--		dev_err(ecc->dev, "interrupted when attempting to lock\n");
--		return ret;
--	}
--
--	mtk_ecc_wait_idle(ecc, op);
--
--	ret = mtk_ecc_config(ecc, config);
--	if (ret) {
--		mutex_unlock(&ecc->lock);
--		return ret;
--	}
--
--	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
--		init_completion(&ecc->done);
--		reg_val = ECC_IRQ_EN;
--		/*
--		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
--		 * means this chip can only generate one ecc irq during page
--		 * read / write. If is 0, generate one ecc irq each ecc step.
--		 */
--		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
--			reg_val |= ECC_PG_IRQ_SEL;
--		if (op == ECC_ENCODE)
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--		else
--			writew(reg_val, ecc->regs +
--			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	}
--
--	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_enable);
--
--void mtk_ecc_disable(struct mtk_ecc *ecc)
--{
--	enum mtk_ecc_operation op = ECC_ENCODE;
--
--	/* find out the running operation */
--	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
--		op = ECC_DECODE;
--
--	/* disable it */
--	mtk_ecc_wait_idle(ecc, op);
--	if (op == ECC_DECODE) {
--		/*
--		 * Clear decode IRQ status in case there is a timeout to wait
--		 * decode IRQ.
--		 */
--		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
--	} else {
--		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
--	}
--
--	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
--
--	mutex_unlock(&ecc->lock);
--}
--EXPORT_SYMBOL(mtk_ecc_disable);
--
--int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
--{
--	int ret;
--
--	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
--	if (!ret) {
--		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
--			(op == ECC_ENCODE) ? "encoder" : "decoder");
--		return -ETIMEDOUT;
--	}
--
--	return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_wait_done);
--
--int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
--		   u8 *data, u32 bytes)
--{
--	dma_addr_t addr;
--	u32 len;
--	int ret;
--
--	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
--	ret = dma_mapping_error(ecc->dev, addr);
--	if (ret) {
--		dev_err(ecc->dev, "dma mapping error\n");
--		return -EINVAL;
--	}
--
--	config->op = ECC_ENCODE;
--	config->addr = addr;
--	ret = mtk_ecc_enable(ecc, config);
--	if (ret) {
--		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--		return ret;
--	}
--
--	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
--	if (ret)
--		goto timeout;
--
--	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--
--	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
--	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
--
--	/* write the parity bytes generated by the ECC back to temp buffer */
--	__ioread32_copy(ecc->eccdata,
--			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
--			round_up(len, 4));
--
--	/* copy into possibly unaligned OOB region with actual length */
--	memcpy(data + bytes, ecc->eccdata, len);
--timeout:
--
--	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
--	mtk_ecc_disable(ecc);
--
--	return ret;
--}
--EXPORT_SYMBOL(mtk_ecc_encode);
--
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
--{
--	const u8 *ecc_strength = ecc->caps->ecc_strength;
--	int i;
--
--	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
--		if (*p <= ecc_strength[i]) {
--			if (!i)
--				*p = ecc_strength[i];
--			else if (*p != ecc_strength[i])
--				*p = ecc_strength[i - 1];
--			return;
--		}
--	}
--
--	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
--}
--EXPORT_SYMBOL(mtk_ecc_adjust_strength);
--
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
--{
--	return ecc->caps->parity_bits;
--}
--EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
--	.err_mask = 0x3f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2701,
--	.ecc_regs = mt2701_ecc_regs,
--	.num_ecc_strength = 20,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 0,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
--	.err_mask = 0x7f,
--	.err_shift = 8,
--	.ecc_strength = ecc_strength_mt2712,
--	.ecc_regs = mt2712_ecc_regs,
--	.num_ecc_strength = 23,
--	.ecc_mode_shift = 5,
--	.parity_bits = 14,
--	.pg_irq_sel = 1,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
--	.err_mask = 0x1f,
--	.err_shift = 5,
--	.ecc_strength = ecc_strength_mt7622,
--	.ecc_regs = mt7622_ecc_regs,
--	.num_ecc_strength = 5,
--	.ecc_mode_shift = 4,
--	.parity_bits = 13,
--	.pg_irq_sel = 0,
--};
--
--static const struct of_device_id mtk_ecc_dt_match[] = {
--	{
--		.compatible = "mediatek,mt2701-ecc",
--		.data = &mtk_ecc_caps_mt2701,
--	}, {
--		.compatible = "mediatek,mt2712-ecc",
--		.data = &mtk_ecc_caps_mt2712,
--	}, {
--		.compatible = "mediatek,mt7622-ecc",
--		.data = &mtk_ecc_caps_mt7622,
--	},
--	{},
--};
--
--static int mtk_ecc_probe(struct platform_device *pdev)
--{
--	struct device *dev = &pdev->dev;
--	struct mtk_ecc *ecc;
--	struct resource *res;
--	u32 max_eccdata_size;
--	int irq, ret;
--
--	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
--	if (!ecc)
--		return -ENOMEM;
--
--	ecc->caps = of_device_get_match_data(dev);
--
--	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
--	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
--	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
--	max_eccdata_size = round_up(max_eccdata_size, 4);
--	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
--	if (!ecc->eccdata)
--		return -ENOMEM;
--
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	ecc->regs = devm_ioremap_resource(dev, res);
--	if (IS_ERR(ecc->regs))
--		return PTR_ERR(ecc->regs);
--
--	ecc->clk = devm_clk_get(dev, NULL);
--	if (IS_ERR(ecc->clk)) {
--		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
--		return PTR_ERR(ecc->clk);
--	}
--
--	irq = platform_get_irq(pdev, 0);
--	if (irq < 0)
--		return irq;
--
--	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
--	if (ret) {
--		dev_err(dev, "failed to set DMA mask\n");
--		return ret;
--	}
--
--	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
--	if (ret) {
--		dev_err(dev, "failed to request irq\n");
--		return -EINVAL;
--	}
--
--	ecc->dev = dev;
--	mutex_init(&ecc->lock);
--	platform_set_drvdata(pdev, ecc);
--	dev_info(dev, "probed\n");
--
--	return 0;
--}
--
--#ifdef CONFIG_PM_SLEEP
--static int mtk_ecc_suspend(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--
--	clk_disable_unprepare(ecc->clk);
--
--	return 0;
--}
--
--static int mtk_ecc_resume(struct device *dev)
--{
--	struct mtk_ecc *ecc = dev_get_drvdata(dev);
--	int ret;
--
--	ret = clk_prepare_enable(ecc->clk);
--	if (ret) {
--		dev_err(dev, "failed to enable clk\n");
--		return ret;
--	}
--
--	return 0;
--}
--
--static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
--#endif
--
--MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
--
--static struct platform_driver mtk_ecc_driver = {
--	.probe  = mtk_ecc_probe,
--	.driver = {
--		.name  = "mtk-ecc",
--		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
--#ifdef CONFIG_PM_SLEEP
--		.pm = &mtk_ecc_pm_ops,
--#endif
--	},
--};
--
--module_platform_driver(mtk_ecc_driver);
--
--MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
--MODULE_DESCRIPTION("MTK Nand ECC Driver");
--MODULE_LICENSE("Dual MIT/GPL");
---- /dev/null
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -0,0 +1,598 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * MTK ECC controller driver.
-+ * Copyright (C) 2016  MediaTek Inc.
-+ * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-+ *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/clk.h>
-+#include <linux/module.h>
-+#include <linux/iopoll.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/mutex.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+
-+#define ECC_IDLE_MASK		BIT(0)
-+#define ECC_IRQ_EN		BIT(0)
-+#define ECC_PG_IRQ_SEL		BIT(1)
-+#define ECC_OP_ENABLE		(1)
-+#define ECC_OP_DISABLE		(0)
-+
-+#define ECC_ENCCON		(0x00)
-+#define ECC_ENCCNFG		(0x04)
-+#define		ECC_MS_SHIFT		(16)
-+#define ECC_ENCDIADDR		(0x08)
-+#define ECC_ENCIDLE		(0x0C)
-+#define ECC_DECCON		(0x100)
-+#define ECC_DECCNFG		(0x104)
-+#define		DEC_EMPTY_EN		BIT(31)
-+#define		DEC_CNFG_CORRECT	(0x3 << 12)
-+#define ECC_DECIDLE		(0x10C)
-+#define ECC_DECENUM0		(0x114)
-+
-+#define ECC_TIMEOUT		(500000)
-+
-+#define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
-+#define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
-+
-+struct mtk_ecc_caps {
-+	u32 err_mask;
-+	u32 err_shift;
-+	const u8 *ecc_strength;
-+	const u32 *ecc_regs;
-+	u8 num_ecc_strength;
-+	u8 ecc_mode_shift;
-+	u32 parity_bits;
-+	int pg_irq_sel;
-+};
-+
-+struct mtk_ecc {
-+	struct device *dev;
-+	const struct mtk_ecc_caps *caps;
-+	void __iomem *regs;
-+	struct clk *clk;
-+
-+	struct completion done;
-+	struct mutex lock;
-+	u32 sectors;
-+
-+	u8 *eccdata;
-+};
-+
-+/* ecc strength that each IP supports */
-+static const u8 ecc_strength_mt2701[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60
-+};
-+
-+static const u8 ecc_strength_mt2712[] = {
-+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+	40, 44, 48, 52, 56, 60, 68, 72, 80
-+};
-+
-+static const u8 ecc_strength_mt7622[] = {
-+	4, 6, 8, 10, 12
-+};
-+
-+enum mtk_ecc_regs {
-+	ECC_ENCPAR00,
-+	ECC_ENCIRQ_EN,
-+	ECC_ENCIRQ_STA,
-+	ECC_DECDONE,
-+	ECC_DECIRQ_EN,
-+	ECC_DECIRQ_STA,
-+};
-+
-+static int mt2701_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt2712_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x300,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt7622_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x30,
-+	[ECC_ENCIRQ_STA] =      0x34,
-+	[ECC_DECDONE] =         0x11c,
-+	[ECC_DECIRQ_EN] =       0x140,
-+	[ECC_DECIRQ_STA] =      0x144,
-+};
-+
-+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
-+				     enum mtk_ecc_operation op)
-+{
-+	struct device *dev = ecc->dev;
-+	u32 val;
-+	int ret;
-+
-+	ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
-+					val & ECC_IDLE_MASK,
-+					10, ECC_TIMEOUT);
-+	if (ret)
-+		dev_warn(dev, "%s NOT idle\n",
-+			 op == ECC_ENCODE ? "encoder" : "decoder");
-+}
-+
-+static irqreturn_t mtk_ecc_irq(int irq, void *id)
-+{
-+	struct mtk_ecc *ecc = id;
-+	u32 dec, enc;
-+
-+	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
-+		    & ECC_IRQ_EN;
-+	if (dec) {
-+		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		if (dec & ecc->sectors) {
-+			/*
-+			 * Clear decode IRQ status once again to ensure that
-+			 * there will be no extra IRQ.
-+			 */
-+			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
-+			ecc->sectors = 0;
-+			complete(&ecc->done);
-+		} else {
-+			return IRQ_HANDLED;
-+		}
-+	} else {
-+		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
-+		      & ECC_IRQ_EN;
-+		if (enc)
-+			complete(&ecc->done);
-+		else
-+			return IRQ_NONE;
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	u32 ecc_bit, dec_sz, enc_sz;
-+	u32 reg, i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (ecc->caps->ecc_strength[i] == config->strength)
-+			break;
-+	}
-+
-+	if (i == ecc->caps->num_ecc_strength) {
-+		dev_err(ecc->dev, "invalid ecc strength %d\n",
-+			config->strength);
-+		return -EINVAL;
-+	}
-+
-+	ecc_bit = i;
-+
-+	if (config->op == ECC_ENCODE) {
-+		/* configure ECC encoder (in bits) */
-+		enc_sz = config->len << 3;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (enc_sz << ECC_MS_SHIFT);
-+		writel(reg, ecc->regs + ECC_ENCCNFG);
-+
-+		if (config->mode != ECC_NFI_MODE)
-+			writel(lower_32_bits(config->addr),
-+			       ecc->regs + ECC_ENCDIADDR);
-+
-+	} else {
-+		/* configure ECC decoder (in bits) */
-+		dec_sz = (config->len << 3) +
-+			 config->strength * ecc->caps->parity_bits;
-+
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
-+		reg |= DEC_EMPTY_EN;
-+		writel(reg, ecc->regs + ECC_DECCNFG);
-+
-+		if (config->sectors)
-+			ecc->sectors = 1 << (config->sectors - 1);
-+	}
-+
-+	return 0;
-+}
-+
-+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
-+		       int sectors)
-+{
-+	u32 offset, i, err;
-+	u32 bitflips = 0;
-+
-+	stats->corrected = 0;
-+	stats->failed = 0;
-+
-+	for (i = 0; i < sectors; i++) {
-+		offset = (i >> 2) << 2;
-+		err = readl(ecc->regs + ECC_DECENUM0 + offset);
-+		err = err >> ((i % 4) * ecc->caps->err_shift);
-+		err &= ecc->caps->err_mask;
-+		if (err == ecc->caps->err_mask) {
-+			/* uncorrectable errors */
-+			stats->failed++;
-+			continue;
-+		}
-+
-+		stats->corrected += err;
-+		bitflips = max_t(u32, bitflips, err);
-+	}
-+
-+	stats->bitflips = bitflips;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_stats);
-+
-+void mtk_ecc_release(struct mtk_ecc *ecc)
-+{
-+	clk_disable_unprepare(ecc->clk);
-+	put_device(ecc->dev);
-+}
-+EXPORT_SYMBOL(mtk_ecc_release);
-+
-+static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
-+{
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
-+
-+	mtk_ecc_wait_idle(ecc, ECC_DECODE);
-+	writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
-+}
-+
-+static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
-+{
-+	struct platform_device *pdev;
-+	struct mtk_ecc *ecc;
-+
-+	pdev = of_find_device_by_node(np);
-+	if (!pdev)
-+		return ERR_PTR(-EPROBE_DEFER);
-+
-+	ecc = platform_get_drvdata(pdev);
-+	if (!ecc) {
-+		put_device(&pdev->dev);
-+		return ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	clk_prepare_enable(ecc->clk);
-+	mtk_ecc_hw_init(ecc);
-+
-+	return ecc;
-+}
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
-+{
-+	struct mtk_ecc *ecc = NULL;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	if (np) {
-+		ecc = mtk_ecc_get(np);
-+		of_node_put(np);
-+	}
-+
-+	return ecc;
-+}
-+EXPORT_SYMBOL(of_mtk_ecc_get);
-+
-+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+	enum mtk_ecc_operation op = config->op;
-+	u16 reg_val;
-+	int ret;
-+
-+	ret = mutex_lock_interruptible(&ecc->lock);
-+	if (ret) {
-+		dev_err(ecc->dev, "interrupted when attempting to lock\n");
-+		return ret;
-+	}
-+
-+	mtk_ecc_wait_idle(ecc, op);
-+
-+	ret = mtk_ecc_config(ecc, config);
-+	if (ret) {
-+		mutex_unlock(&ecc->lock);
-+		return ret;
-+	}
-+
-+	if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
-+		init_completion(&ecc->done);
-+		reg_val = ECC_IRQ_EN;
-+		/*
-+		 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
-+		 * means this chip can only generate one ecc irq during page
-+		 * read / write. If is 0, generate one ecc irq each ecc step.
-+		 */
-+		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
-+			reg_val |= ECC_PG_IRQ_SEL;
-+		if (op == ECC_ENCODE)
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+		else
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_enable);
-+
-+void mtk_ecc_disable(struct mtk_ecc *ecc)
-+{
-+	enum mtk_ecc_operation op = ECC_ENCODE;
-+
-+	/* find out the running operation */
-+	if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
-+		op = ECC_DECODE;
-+
-+	/* disable it */
-+	mtk_ecc_wait_idle(ecc, op);
-+	if (op == ECC_DECODE) {
-+		/*
-+		 * Clear decode IRQ status in case there is a timeout to wait
-+		 * decode IRQ.
-+		 */
-+		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	} else {
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+	}
-+
-+	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+	mutex_unlock(&ecc->lock);
-+}
-+EXPORT_SYMBOL(mtk_ecc_disable);
-+
-+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
-+{
-+	int ret;
-+
-+	ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
-+	if (!ret) {
-+		dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
-+			(op == ECC_ENCODE) ? "encoder" : "decoder");
-+		return -ETIMEDOUT;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_wait_done);
-+
-+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
-+		   u8 *data, u32 bytes)
-+{
-+	dma_addr_t addr;
-+	u32 len;
-+	int ret;
-+
-+	addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
-+	ret = dma_mapping_error(ecc->dev, addr);
-+	if (ret) {
-+		dev_err(ecc->dev, "dma mapping error\n");
-+		return -EINVAL;
-+	}
-+
-+	config->op = ECC_ENCODE;
-+	config->addr = addr;
-+	ret = mtk_ecc_enable(ecc, config);
-+	if (ret) {
-+		dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+		return ret;
-+	}
-+
-+	ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
-+	if (ret)
-+		goto timeout;
-+
-+	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+
-+	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
-+	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
-+
-+	/* write the parity bytes generated by the ECC back to temp buffer */
-+	__ioread32_copy(ecc->eccdata,
-+			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
-+			round_up(len, 4));
-+
-+	/* copy into possibly unaligned OOB region with actual length */
-+	memcpy(data + bytes, ecc->eccdata, len);
-+timeout:
-+
-+	dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+	mtk_ecc_disable(ecc);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(mtk_ecc_encode);
-+
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
-+{
-+	const u8 *ecc_strength = ecc->caps->ecc_strength;
-+	int i;
-+
-+	for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+		if (*p <= ecc_strength[i]) {
-+			if (!i)
-+				*p = ecc_strength[i];
-+			else if (*p != ecc_strength[i])
-+				*p = ecc_strength[i - 1];
-+			return;
-+		}
-+	}
-+
-+	*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
-+}
-+EXPORT_SYMBOL(mtk_ecc_adjust_strength);
-+
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
-+{
-+	return ecc->caps->parity_bits;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
-+	.err_mask = 0x3f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2701,
-+	.ecc_regs = mt2701_ecc_regs,
-+	.num_ecc_strength = 20,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
-+	.err_mask = 0x7f,
-+	.err_shift = 8,
-+	.ecc_strength = ecc_strength_mt2712,
-+	.ecc_regs = mt2712_ecc_regs,
-+	.num_ecc_strength = 23,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
-+	.pg_irq_sel = 1,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-+	.err_mask = 0x1f,
-+	.err_shift = 5,
-+	.ecc_strength = ecc_strength_mt7622,
-+	.ecc_regs = mt7622_ecc_regs,
-+	.num_ecc_strength = 5,
-+	.ecc_mode_shift = 4,
-+	.parity_bits = 13,
-+	.pg_irq_sel = 0,
-+};
-+
-+static const struct of_device_id mtk_ecc_dt_match[] = {
-+	{
-+		.compatible = "mediatek,mt2701-ecc",
-+		.data = &mtk_ecc_caps_mt2701,
-+	}, {
-+		.compatible = "mediatek,mt2712-ecc",
-+		.data = &mtk_ecc_caps_mt2712,
-+	}, {
-+		.compatible = "mediatek,mt7622-ecc",
-+		.data = &mtk_ecc_caps_mt7622,
-+	},
-+	{},
-+};
-+
-+static int mtk_ecc_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct mtk_ecc *ecc;
-+	struct resource *res;
-+	u32 max_eccdata_size;
-+	int irq, ret;
-+
-+	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
-+	if (!ecc)
-+		return -ENOMEM;
-+
-+	ecc->caps = of_device_get_match_data(dev);
-+
-+	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
-+	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
-+	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
-+	max_eccdata_size = round_up(max_eccdata_size, 4);
-+	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
-+	if (!ecc->eccdata)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	ecc->regs = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(ecc->regs))
-+		return PTR_ERR(ecc->regs);
-+
-+	ecc->clk = devm_clk_get(dev, NULL);
-+	if (IS_ERR(ecc->clk)) {
-+		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
-+		return PTR_ERR(ecc->clk);
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0)
-+		return irq;
-+
-+	ret = dma_set_mask(dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(dev, "failed to set DMA mask\n");
-+		return ret;
-+	}
-+
-+	ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
-+	if (ret) {
-+		dev_err(dev, "failed to request irq\n");
-+		return -EINVAL;
-+	}
-+
-+	ecc->dev = dev;
-+	mutex_init(&ecc->lock);
-+	platform_set_drvdata(pdev, ecc);
-+	dev_info(dev, "probed\n");
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int mtk_ecc_suspend(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+
-+	clk_disable_unprepare(ecc->clk);
-+
-+	return 0;
-+}
-+
-+static int mtk_ecc_resume(struct device *dev)
-+{
-+	struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+	int ret;
-+
-+	ret = clk_prepare_enable(ecc->clk);
-+	if (ret) {
-+		dev_err(dev, "failed to enable clk\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
-+#endif
-+
-+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
-+
-+static struct platform_driver mtk_ecc_driver = {
-+	.probe  = mtk_ecc_probe,
-+	.driver = {
-+		.name  = "mtk-ecc",
-+		.of_match_table = of_match_ptr(mtk_ecc_dt_match),
-+#ifdef CONFIG_PM_SLEEP
-+		.pm = &mtk_ecc_pm_ops,
-+#endif
-+	},
-+};
-+
-+module_platform_driver(mtk_ecc_driver);
-+
-+MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
-+MODULE_DESCRIPTION("MTK Nand ECC Driver");
-+MODULE_LICENSE("Dual MIT/GPL");
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -360,6 +360,7 @@ config MTD_NAND_QCOM
- 
- config MTD_NAND_MTK
- 	tristate "MTK NAND controller"
-+	depends on MTD_NAND_ECC_MEDIATEK
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
- 	depends on HAS_IOMEM
- 	help
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
--obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
-+obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o
- obj-$(CONFIG_MTD_NAND_MXIC)		+= mxic_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
- obj-$(CONFIG_MTD_NAND_STM32_FMC2)	+= stm32_fmc2_nand.o
---- a/drivers/mtd/nand/raw/mtk_nand.c
-+++ b/drivers/mtd/nand/raw/mtk_nand.c
-@@ -17,7 +17,7 @@
- #include <linux/iopoll.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
--#include "mtk_ecc.h"
-+#include <linux/mtd/nand-ecc-mtk.h>
- 
- /* NAND controller register definition */
- #define NFI_CNFG		(0x00)
---- a/drivers/mtd/nand/raw/mtk_ecc.h
-+++ /dev/null
-@@ -1,47 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0 OR MIT */
--/*
-- * MTK SDG1 ECC controller
-- *
-- * Copyright (c) 2016 Mediatek
-- * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-- *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-- */
--
--#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
--#define __DRIVERS_MTD_NAND_MTK_ECC_H__
--
--#include <linux/types.h>
--
--enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
--enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
--
--struct device_node;
--struct mtk_ecc;
--
--struct mtk_ecc_stats {
--	u32 corrected;
--	u32 bitflips;
--	u32 failed;
--};
--
--struct mtk_ecc_config {
--	enum mtk_ecc_operation op;
--	enum mtk_ecc_mode mode;
--	dma_addr_t addr;
--	u32 strength;
--	u32 sectors;
--	u32 len;
--};
--
--int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
--void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
--int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
--int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
--void mtk_ecc_disable(struct mtk_ecc *);
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
--void mtk_ecc_release(struct mtk_ecc *);
--
--#endif
---- /dev/null
-+++ b/include/linux/mtd/nand-ecc-mtk.h
-@@ -0,0 +1,47 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * MTK SDG1 ECC controller
-+ *
-+ * Copyright (c) 2016 Mediatek
-+ * Authors:	Xiaolei Li		<xiaolei.li@mediatek.com>
-+ *		Jorge Ramirez-Ortiz	<jorge.ramirez-ortiz@linaro.org>
-+ */
-+
-+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
-+#define __DRIVERS_MTD_NAND_MTK_ECC_H__
-+
-+#include <linux/types.h>
-+
-+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
-+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
-+
-+struct device_node;
-+struct mtk_ecc;
-+
-+struct mtk_ecc_stats {
-+	u32 corrected;
-+	u32 bitflips;
-+	u32 failed;
-+};
-+
-+struct mtk_ecc_config {
-+	enum mtk_ecc_operation op;
-+	enum mtk_ecc_mode mode;
-+	dma_addr_t addr;
-+	u32 strength;
-+	u32 sectors;
-+	u32 len;
-+};
-+
-+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
-+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
-+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
-+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
-+void mtk_ecc_disable(struct mtk_ecc *);
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
-+void mtk_ecc_release(struct mtk_ecc *);
-+
-+#endif
diff --git a/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch
deleted file mode 100644
index ed20905012..0000000000
--- a/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch
+++ /dev/null
@@ -1,1537 +0,0 @@
-From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Sat, 2 Apr 2022 10:16:11 +0800
-Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface
-
-This driver implements support for the SPI-NAND mode of MTK NAND Flash
-Interface as a SPI-MEM controller with pipelined ECC capability.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
----
-Change since v1:
-  fix CI warnings
-
-Changes since v2:
- use streamed DMA api to avoid an extra memory copy during read
- make ECC engine config a per-nand context
- take user-requested ECC strength into account
-
-Change since v3: none
-Changes since v4:
- fix missing OOB write
- print page format with dev_dbg
- replace uint*_t copied from vendor driver with u*
-
-Changes since v5:
- add missing nfi mode register configuration in probe
- fix an off-by-one bug in mtk_snand_mac_io
-
- drivers/spi/Kconfig        |   10 +
- drivers/spi/Makefile       |    1 +
- drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1481 insertions(+)
- create mode 100644 drivers/spi/spi-mtk-snfi.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -529,6 +529,16 @@ config SPI_MTK_NOR
- 	  SPI interface as well as several SPI NOR specific instructions
- 	  via SPI MEM interface.
- 
-+config SPI_MTK_SNFI
-+	tristate "MediaTek SPI NAND Flash Interface"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	depends on MTD_NAND_ECC_MEDIATEK
-+	help
-+	  This enables support for SPI-NAND mode on the MediaTek NAND
-+	  Flash Interface found on MediaTek ARM SoCs. This controller
-+	  is implemented as a SPI-MEM controller with pipelined ECC
-+	  capcability.
-+
- config SPI_NPCM_FIU
- 	tristate "Nuvoton NPCM FLASH Interface Unit"
- 	depends on ARCH_NPCM || COMPILE_TEST
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52x
- obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
- obj-$(CONFIG_SPI_MT7621)		+= spi-mt7621.o
- obj-$(CONFIG_SPI_MTK_NOR)		+= spi-mtk-nor.o
-+obj-$(CONFIG_SPI_MTK_SNFI)		+= spi-mtk-snfi.o
- obj-$(CONFIG_SPI_MXIC)			+= spi-mxic.o
- obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
- obj-$(CONFIG_SPI_NPCM_FIU)		+= spi-npcm-fiu.o
---- /dev/null
-+++ b/drivers/spi/spi-mtk-snfi.c
-@@ -0,0 +1,1470 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface
-+//
-+// Copyright (c) 2022 Chuanhong Guo <gch981213@gmail.com>
-+//
-+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK:
-+//
-+// Copyright (C) 2020 MediaTek Inc.
-+// Author: Weijie Gao <weijie.gao@mediatek.com>
-+//
-+// This controller organize the page data as several interleaved sectors
-+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size)
-+// +---------+------+------+---------+------+------+-----+
-+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... |
-+// +---------+------+------+---------+------+------+-----+
-+// With auto-format turned on, DMA only returns this part:
-+// +---------+---------+-----+
-+// | Sector1 | Sector2 | ... |
-+// +---------+---------+-----+
-+// The FDM data will be filled to the registers, and ECC parity data isn't
-+// accessible.
-+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA
-+// in it's original order shown in the first table. ECC can't be turned on when
-+// auto-format is off.
-+//
-+// However, Linux SPI-NAND driver expects the data returned as:
-+// +------+-----+
-+// | Page | OOB |
-+// +------+-----+
-+// where the page data is continuously stored instead of interleaved.
-+// So we assume all instructions matching the page_op template between ECC
-+// prepare_io_req and finish_io_req are for page cache r/w.
-+// Here's how this spi-mem driver operates when reading:
-+//  1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off).
-+//  2. Perform page ops and let the controller fill the DMA bounce buffer with
-+//     de-interleaved sector data and set FDM registers.
-+//  3. Return the data as:
-+//     +---------+---------+-----+------+------+-----+
-+//     | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... |
-+//     +---------+---------+-----+------+------+-----+
-+//  4. For other matching spi_mem ops outside a prepare/finish_io_req pair,
-+//     read the data with auto-format off into the bounce buffer and copy
-+//     needed data to the buffer specified in the request.
-+//
-+// Write requests operates in a similar manner.
-+// As a limitation of this strategy, we won't be able to access any ECC parity
-+// data at all in Linux.
-+//
-+// Here's the bad block mark situation on MTK chips:
-+// In older chips like mt7622, MTK uses the first FDM byte in the first sector
-+// as the bad block mark. After de-interleaving, this byte appears at [pagesize]
-+// in the returned data, which is the BBM position expected by kernel. However,
-+// the conventional bad block mark is the first byte of the OOB, which is part
-+// of the last sector data in the interleaved layout. Instead of fixing their
-+// hardware, MTK decided to address this inconsistency in software. On these
-+// later chips, the BootROM expects the following:
-+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at
-+//    (page_size - (nsectors - 1) * spare_size) in the DMA buffer.
-+// 2. The original byte stored at that position in the DMA buffer will be stored
-+//    as the first byte of the FDM section in the last sector.
-+// We can't disagree with the BootROM, so after de-interleaving, we need to
-+// perform the following swaps in read:
-+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size],
-+//    which is the expected BBM position by kernel.
-+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to
-+//    [page_size - (nsectors - 1) * spare_size]
-+// Similarly, when writing, we need to perform swaps in the other direction.
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/mutex.h>
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/iopoll.h>
-+#include <linux/of_platform.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
-+#include <linux/mtd/nand.h>
-+
-+// NFI registers
-+#define NFI_CNFG 0x000
-+#define CNFG_OP_MODE_S 12
-+#define CNFG_OP_MODE_CUST 6
-+#define CNFG_OP_MODE_PROGRAM 3
-+#define CNFG_AUTO_FMT_EN BIT(9)
-+#define CNFG_HW_ECC_EN BIT(8)
-+#define CNFG_DMA_BURST_EN BIT(2)
-+#define CNFG_READ_MODE BIT(1)
-+#define CNFG_DMA_MODE BIT(0)
-+
-+#define NFI_PAGEFMT 0x0004
-+#define NFI_SPARE_SIZE_LS_S 16
-+#define NFI_FDM_ECC_NUM_S 12
-+#define NFI_FDM_NUM_S 8
-+#define NFI_SPARE_SIZE_S 4
-+#define NFI_SEC_SEL_512 BIT(2)
-+#define NFI_PAGE_SIZE_S 0
-+#define NFI_PAGE_SIZE_512_2K 0
-+#define NFI_PAGE_SIZE_2K_4K 1
-+#define NFI_PAGE_SIZE_4K_8K 2
-+#define NFI_PAGE_SIZE_8K_16K 3
-+
-+#define NFI_CON 0x008
-+#define CON_SEC_NUM_S 12
-+#define CON_BWR BIT(9)
-+#define CON_BRD BIT(8)
-+#define CON_NFI_RST BIT(1)
-+#define CON_FIFO_FLUSH BIT(0)
-+
-+#define NFI_INTR_EN 0x010
-+#define NFI_INTR_STA 0x014
-+#define NFI_IRQ_INTR_EN BIT(31)
-+#define NFI_IRQ_CUS_READ BIT(8)
-+#define NFI_IRQ_CUS_PG BIT(7)
-+
-+#define NFI_CMD 0x020
-+#define NFI_CMD_DUMMY_READ 0x00
-+#define NFI_CMD_DUMMY_WRITE 0x80
-+
-+#define NFI_STRDATA 0x040
-+#define STR_DATA BIT(0)
-+
-+#define NFI_STA 0x060
-+#define NFI_NAND_FSM GENMASK(28, 24)
-+#define NFI_FSM GENMASK(19, 16)
-+#define READ_EMPTY BIT(12)
-+
-+#define NFI_FIFOSTA 0x064
-+#define FIFO_WR_REMAIN_S 8
-+#define FIFO_RD_REMAIN_S 0
-+
-+#define NFI_ADDRCNTR 0x070
-+#define SEC_CNTR GENMASK(16, 12)
-+#define SEC_CNTR_S 12
-+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_STRADDR 0x080
-+
-+#define NFI_BYTELEN 0x084
-+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_FDM0L 0x0a0
-+#define NFI_FDM0M 0x0a4
-+#define NFI_FDML(n) (NFI_FDM0L + (n)*8)
-+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8)
-+
-+#define NFI_DEBUG_CON1 0x220
-+#define WBUF_EN BIT(2)
-+
-+#define NFI_MASTERSTA 0x224
-+#define MAS_ADDR GENMASK(11, 9)
-+#define MAS_RD GENMASK(8, 6)
-+#define MAS_WR GENMASK(5, 3)
-+#define MAS_RDDLY GENMASK(2, 0)
-+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
-+
-+// SNFI registers
-+#define SNF_MAC_CTL 0x500
-+#define MAC_XIO_SEL BIT(4)
-+#define SF_MAC_EN BIT(3)
-+#define SF_TRIG BIT(2)
-+#define WIP_READY BIT(1)
-+#define WIP BIT(0)
-+
-+#define SNF_MAC_OUTL 0x504
-+#define SNF_MAC_INL 0x508
-+
-+#define SNF_RD_CTL2 0x510
-+#define DATA_READ_DUMMY_S 8
-+#define DATA_READ_MAX_DUMMY 0xf
-+#define DATA_READ_CMD_S 0
-+
-+#define SNF_RD_CTL3 0x514
-+
-+#define SNF_PG_CTL1 0x524
-+#define PG_LOAD_CMD_S 8
-+
-+#define SNF_PG_CTL2 0x528
-+
-+#define SNF_MISC_CTL 0x538
-+#define SW_RST BIT(28)
-+#define FIFO_RD_LTC_S 25
-+#define PG_LOAD_X4_EN BIT(20)
-+#define DATA_READ_MODE_S 16
-+#define DATA_READ_MODE GENMASK(18, 16)
-+#define DATA_READ_MODE_X1 0
-+#define DATA_READ_MODE_X2 1
-+#define DATA_READ_MODE_X4 2
-+#define DATA_READ_MODE_DUAL 5
-+#define DATA_READ_MODE_QUAD 6
-+#define PG_LOAD_CUSTOM_EN BIT(7)
-+#define DATARD_CUSTOM_EN BIT(6)
-+#define CS_DESELECT_CYC_S 0
-+
-+#define SNF_MISC_CTL2 0x53c
-+#define PROGRAM_LOAD_BYTE_NUM_S 16
-+#define READ_DATA_BYTE_NUM_S 11
-+
-+#define SNF_DLY_CTL3 0x548
-+#define SFCK_SAM_DLY_S 0
-+
-+#define SNF_STA_CTL1 0x550
-+#define CUS_PG_DONE BIT(28)
-+#define CUS_READ_DONE BIT(27)
-+#define SPI_STATE_S 0
-+#define SPI_STATE GENMASK(3, 0)
-+
-+#define SNF_CFG 0x55c
-+#define SPI_MODE BIT(0)
-+
-+#define SNF_GPRAM 0x800
-+#define SNF_GPRAM_SIZE 0xa0
-+
-+#define SNFI_POLL_INTERVAL 1000000
-+
-+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };
-+
-+struct mtk_snand_caps {
-+	u16 sector_size;
-+	u16 max_sectors;
-+	u16 fdm_size;
-+	u16 fdm_ecc_size;
-+	u16 fifo_size;
-+
-+	bool bbm_swap;
-+	bool empty_page_check;
-+	u32 mastersta_mask;
-+
-+	const u8 *spare_sizes;
-+	u32 num_spare_size;
-+};
-+
-+static const struct mtk_snand_caps mt7622_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = false,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+static const struct mtk_snand_caps mt7629_snand_caps = {
-+	.sector_size = 512,
-+	.max_sectors = 8,
-+	.fdm_size = 8,
-+	.fdm_ecc_size = 1,
-+	.fifo_size = 32,
-+	.bbm_swap = true,
-+	.empty_page_check = false,
-+	.mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+	.spare_sizes = mt7622_spare_sizes,
-+	.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+struct mtk_snand_conf {
-+	size_t page_size;
-+	size_t oob_size;
-+	u8 nsectors;
-+	u8 spare_size;
-+};
-+
-+struct mtk_snand {
-+	struct spi_controller *ctlr;
-+	struct device *dev;
-+	struct clk *nfi_clk;
-+	struct clk *pad_clk;
-+	void __iomem *nfi_base;
-+	int irq;
-+	struct completion op_done;
-+	const struct mtk_snand_caps *caps;
-+	struct mtk_ecc_config *ecc_cfg;
-+	struct mtk_ecc *ecc;
-+	struct mtk_snand_conf nfi_cfg;
-+	struct mtk_ecc_stats ecc_stats;
-+	struct nand_ecc_engine ecc_eng;
-+	bool autofmt;
-+	u8 *buf;
-+	size_t buf_len;
-+};
-+
-+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand)
-+{
-+	struct nand_ecc_engine *eng = nand->ecc.engine;
-+
-+	return container_of(eng, struct mtk_snand, ecc_eng);
-+}
-+
-+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size)
-+{
-+	if (snf->buf_len >= size)
-+		return 0;
-+	kfree(snf->buf);
-+	snf->buf = kmalloc(size, GFP_KERNEL);
-+	if (!snf->buf)
-+		return -ENOMEM;
-+	snf->buf_len = size;
-+	memset(snf->buf, 0xff, snf->buf_len);
-+	return 0;
-+}
-+
-+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg)
-+{
-+	return readl(snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val)
-+{
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val)
-+{
-+	writew(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set)
-+{
-+	u32 val;
-+
-+	val = readl(snf->nfi_base + reg);
-+	val &= ~clr;
-+	val |= set;
-+	writel(val, snf->nfi_base + reg);
-+}
-+
-+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len)
-+{
-+	u32 i, val = 0, es = sizeof(u32);
-+
-+	for (i = reg; i < reg + len; i++) {
-+		if (i == reg || i % es == 0)
-+			val = nfi_read32(snf, i & ~(es - 1));
-+
-+		*data++ = (u8)(val >> (8 * (i % es)));
-+	}
-+}
-+
-+static int mtk_nfi_reset(struct mtk_snand *snf)
-+{
-+	u32 val, fifo_mask;
-+	int ret;
-+
-+	nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
-+
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI master is still busy after reset\n");
-+		return ret;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,
-+				 !(val & (NFI_FSM | NFI_NAND_FSM)), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Failed to reset NFI\n");
-+		return ret;
-+	}
-+
-+	fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) |
-+		    ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S);
-+	ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,
-+				 !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "NFI FIFOs are not empty\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_snand_mac_reset(struct mtk_snand *snf)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,
-+				 !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Failed to reset SNFI MAC\n");
-+
-+	nfi_write32(snf, SNF_MISC_CTL,
-+		    (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S));
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen)
-+{
-+	int ret;
-+	u32 val;
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);
-+	nfi_write32(snf, SNF_MAC_OUTL, outlen);
-+	nfi_write32(snf, SNF_MAC_INL, inlen);
-+
-+	nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,
-+				 val & WIP_READY, 0, SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for WIP_READY\n");
-+		goto cleanup;
-+	}
-+
-+	ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP),
-+				 0, SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for WIP cleared\n");
-+
-+cleanup:
-+	nfi_write32(snf, SNF_MAC_CTL, 0);
-+
-+	return ret;
-+}
-+
-+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op)
-+{
-+	u32 rx_len = 0;
-+	u32 reg_offs = 0;
-+	u32 val = 0;
-+	const u8 *tx_buf = NULL;
-+	u8 *rx_buf = NULL;
-+	int i, ret;
-+	u8 b;
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		rx_len = op->data.nbytes;
-+		rx_buf = op->data.buf.in;
-+	} else {
-+		tx_buf = op->data.buf.out;
-+	}
-+
-+	mtk_snand_mac_reset(snf);
-+
-+	for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) {
-+		b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->addr.nbytes; i++, reg_offs++) {
-+		b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff;
-+		val |= b << (8 * (reg_offs % 4));
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) {
-+		if (reg_offs % 4 == 3) {
-+			nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+			val = 0;
-+		}
-+	}
-+
-+	if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		for (i = 0; i < op->data.nbytes; i++, reg_offs++) {
-+			val |= tx_buf[i] << (8 * (reg_offs % 4));
-+			if (reg_offs % 4 == 3) {
-+				nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+				val = 0;
-+			}
-+		}
-+	}
-+
-+	if (reg_offs % 4)
-+		nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val);
-+
-+	for (i = 0; i < reg_offs; i += 4)
-+		dev_dbg(snf->dev, "%d: %08X", i,
-+			nfi_read32(snf, SNF_GPRAM + i));
-+
-+	dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len);
-+
-+	ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len);
-+	if (ret)
-+		return ret;
-+
-+	if (!rx_len)
-+		return 0;
-+
-+	nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len);
-+	return 0;
-+}
-+
-+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size,
-+				   u32 oob_size)
-+{
-+	int spare_idx = -1;
-+	u32 spare_size, spare_size_shift, pagesize_idx;
-+	u32 sector_size_512;
-+	u8 nsectors;
-+	int i;
-+
-+	// skip if it's already configured as required.
-+	if (snf->nfi_cfg.page_size == page_size &&
-+	    snf->nfi_cfg.oob_size == oob_size)
-+		return 0;
-+
-+	nsectors = page_size / snf->caps->sector_size;
-+	if (nsectors > snf->caps->max_sectors) {
-+		dev_err(snf->dev, "too many sectors required.\n");
-+		goto err;
-+	}
-+
-+	if (snf->caps->sector_size == 512) {
-+		sector_size_512 = NFI_SEC_SEL_512;
-+		spare_size_shift = NFI_SPARE_SIZE_S;
-+	} else {
-+		sector_size_512 = 0;
-+		spare_size_shift = NFI_SPARE_SIZE_LS_S;
-+	}
-+
-+	switch (page_size) {
-+	case SZ_512:
-+		pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_2K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+		break;
-+	case SZ_4K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+		break;
-+	case SZ_8K:
-+		if (snf->caps->sector_size == 512)
-+			pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		else
-+			pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+		break;
-+	case SZ_16K:
-+		pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+		break;
-+	default:
-+		dev_err(snf->dev, "unsupported page size.\n");
-+		goto err;
-+	}
-+
-+	spare_size = oob_size / nsectors;
-+	// If we're using the 1KB sector size, HW will automatically double the
-+	// spare size. We should only use half of the value in this case.
-+	if (snf->caps->sector_size == 1024)
-+		spare_size /= 2;
-+
-+	for (i = snf->caps->num_spare_size - 1; i >= 0; i--) {
-+		if (snf->caps->spare_sizes[i] <= spare_size) {
-+			spare_size = snf->caps->spare_sizes[i];
-+			if (snf->caps->sector_size == 1024)
-+				spare_size *= 2;
-+			spare_idx = i;
-+			break;
-+		}
-+	}
-+
-+	if (spare_idx < 0) {
-+		dev_err(snf->dev, "unsupported spare size: %u\n", spare_size);
-+		goto err;
-+	}
-+
-+	nfi_write32(snf, NFI_PAGEFMT,
-+		    (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |
-+			    (snf->caps->fdm_size << NFI_FDM_NUM_S) |
-+			    (spare_idx << spare_size_shift) |
-+			    (pagesize_idx << NFI_PAGE_SIZE_S) |
-+			    sector_size_512);
-+
-+	snf->nfi_cfg.page_size = page_size;
-+	snf->nfi_cfg.oob_size = oob_size;
-+	snf->nfi_cfg.nsectors = nsectors;
-+	snf->nfi_cfg.spare_size = spare_size;
-+
-+	dev_dbg(snf->dev, "page format: (%u + %u) * %u\n",
-+		snf->caps->sector_size, spare_size, nsectors);
-+	return snand_prepare_bouncebuf(snf, page_size + oob_size);
-+err:
-+	dev_err(snf->dev, "page size %u + %u is not supported\n", page_size,
-+		oob_size);
-+	return -EOPNOTSUPP;
-+}
-+
-+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *oobecc)
-+{
-+	// ECC area is not accessible
-+	return -ERANGE;
-+}
-+
-+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,
-+				    struct mtd_oob_region *oobfree)
-+{
-+	struct nand_device *nand = mtd_to_nanddev(mtd);
-+	struct mtk_snand *ms = nand_to_mtk_snand(nand);
-+
-+	if (section >= ms->nfi_cfg.nsectors)
-+		return -ERANGE;
-+
-+	oobfree->length = ms->caps->fdm_size - 1;
-+	oobfree->offset = section * ms->caps->fdm_size + 1;
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {
-+	.ecc = mtk_snand_ooblayout_ecc,
-+	.free = mtk_snand_ooblayout_free,
-+};
-+
-+static int mtk_snand_ecc_init_ctx(struct nand_device *nand)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
-+	struct nand_ecc_props *reqs = &nand->ecc.requirements;
-+	struct nand_ecc_props *user = &nand->ecc.user_conf;
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+	int step_size = 0, strength = 0, desired_correction = 0, steps;
-+	bool ecc_user = false;
-+	int ret;
-+	u32 parity_bits, max_ecc_bytes;
-+	struct mtk_ecc_config *ecc_cfg;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+
-+	ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
-+	if (!ecc_cfg)
-+		return -ENOMEM;
-+
-+	nand->ecc.ctx.priv = ecc_cfg;
-+
-+	if (user->step_size && user->strength) {
-+		step_size = user->step_size;
-+		strength = user->strength;
-+		ecc_user = true;
-+	} else if (reqs->step_size && reqs->strength) {
-+		step_size = reqs->step_size;
-+		strength = reqs->strength;
-+	}
-+
-+	if (step_size && strength) {
-+		steps = mtd->writesize / step_size;
-+		desired_correction = steps * strength;
-+		strength = desired_correction / snf->nfi_cfg.nsectors;
-+	}
-+
-+	ecc_cfg->mode = ECC_NFI_MODE;
-+	ecc_cfg->sectors = snf->nfi_cfg.nsectors;
-+	ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size;
-+
-+	// calculate the max possible strength under current page format
-+	parity_bits = mtk_ecc_get_parity_bits(snf->ecc);
-+	max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size;
-+	ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits;
-+	mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength);
-+
-+	// if there's a user requested strength, find the minimum strength that
-+	// meets the requirement. Otherwise use the maximum strength which is
-+	// expected by BootROM.
-+	if (ecc_user && strength) {
-+		u32 s_next = ecc_cfg->strength - 1;
-+
-+		while (1) {
-+			mtk_ecc_adjust_strength(snf->ecc, &s_next);
-+			if (s_next >= ecc_cfg->strength)
-+				break;
-+			if (s_next < strength)
-+				break;
-+			s_next = ecc_cfg->strength - 1;
-+		}
-+	}
-+
-+	mtd_set_ooblayout(mtd, &mtk_snand_ooblayout);
-+
-+	conf->step_size = snf->caps->sector_size;
-+	conf->strength = ecc_cfg->strength;
-+
-+	if (ecc_cfg->strength < strength)
-+		dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n",
-+			 strength);
-+	dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n",
-+		 ecc_cfg->strength, snf->caps->sector_size);
-+
-+	return 0;
-+}
-+
-+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand)
-+{
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+
-+	kfree(ecc_cfg);
-+}
-+
-+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand,
-+					struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+	int ret;
-+
-+	ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+				      nand->memorg.oobsize);
-+	if (ret)
-+		return ret;
-+	snf->autofmt = true;
-+	snf->ecc_cfg = ecc_cfg;
-+	return 0;
-+}
-+
-+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand,
-+				       struct nand_page_io_req *req)
-+{
-+	struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+	struct mtd_info *mtd = nanddev_to_mtd(nand);
-+
-+	snf->ecc_cfg = NULL;
-+	snf->autofmt = false;
-+	if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ))
-+		return 0;
-+
-+	if (snf->ecc_stats.failed)
-+		mtd->ecc_stats.failed += snf->ecc_stats.failed;
-+	mtd->ecc_stats.corrected += snf->ecc_stats.corrected;
-+	return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips;
-+}
-+
-+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {
-+	.init_ctx = mtk_snand_ecc_init_ctx,
-+	.cleanup_ctx = mtk_snand_ecc_cleanup_ctx,
-+	.prepare_io_req = mtk_snand_ecc_prepare_io_req,
-+	.finish_io_req = mtk_snand_ecc_finish_io_req,
-+};
-+
-+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 vall, valm;
-+	u8 *oobptr = buf;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = nfi_read32(snf, NFI_FDML(i));
-+		valm = nfi_read32(snf, NFI_FDMM(i));
-+
-+		for (j = 0; j < snf->caps->fdm_size; j++)
-+			oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
-+
-+		oobptr += snf->caps->fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf)
-+{
-+	u32 fdm_size = snf->caps->fdm_size;
-+	const u8 *oobptr = buf;
-+	u32 vall, valm;
-+	int i, j;
-+
-+	for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+		vall = 0;
-+		valm = 0;
-+
-+		for (j = 0; j < 8; j++) {
-+			if (j < 4)
-+				vall |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< (j * 8);
-+			else
-+				valm |= (j < fdm_size ? oobptr[j] : 0xff)
-+					<< ((j - 4) * 8);
-+		}
-+
-+		nfi_write32(snf, NFI_FDML(i), vall);
-+		nfi_write32(snf, NFI_FDMM(i), valm);
-+
-+		oobptr += fdm_size;
-+	}
-+}
-+
-+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf)
-+{
-+	u32 buf_bbm_pos, fdm_bbm_pos;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap [pagesize] byte on nand with the first fdm byte
-+	// in the last sector.
-+	buf_bbm_pos = snf->nfi_cfg.page_size -
-+		      (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size;
-+	fdm_bbm_pos = snf->nfi_cfg.page_size +
-+		      (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+
-+	swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]);
-+}
-+
-+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)
-+{
-+	u32 fdm_bbm_pos1, fdm_bbm_pos2;
-+
-+	if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+		return;
-+
-+	// swap the first fdm byte in the first and the last sector.
-+	fdm_bbm_pos1 = snf->nfi_cfg.page_size;
-+	fdm_bbm_pos2 = snf->nfi_cfg.page_size +
-+		       (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+	swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]);
-+}
-+
-+static int mtk_snand_read_page_cache(struct mtk_snand *snf,
-+				     const struct spi_mem_op *op)
-+{
-+	u8 *buf = snf->buf;
-+	u8 *buf_fdm = buf + snf->nfi_cfg.page_size;
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 rd_offset = 0;
-+	u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth);
-+	u32 op_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	int ret = 0;
-+	u32 rd_mode, rd_bytes, val;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+		// extract the plane bit:
-+		// Find the highest bit set in (pagesize+oobsize).
-+		// Bits higher than that in op->addr are kept and sent over SPI
-+		// Lower bits are used as an offset for copying data from DMA
-+		// bounce buffer.
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		rd_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+
-+		// check if we can dma to the caller memory
-+		if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size)
-+			buf = op->data.buf.in;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	// command and dummy cycles
-+	nfi_write32(snf, SNF_RD_CTL2,
-+		    (dummy_clk << DATA_READ_DUMMY_S) |
-+			    (op->cmd.opcode << DATA_READ_CMD_S));
-+
-+	// read address
-+	nfi_write32(snf, SNF_RD_CTL3, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD :
-+						   DATA_READ_MODE_X4;
-+	else if (op->data.buswidth == 2)
-+		rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL :
-+						   DATA_READ_MODE_X2;
-+	else
-+		rd_mode = DATA_READ_MODE_X1;
-+	rd_mode <<= DATA_READ_MODE_S;
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE,
-+		  rd_mode | DATARD_CUSTOM_EN);
-+
-+	// Set bytes to read
-+	rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes);
-+
-+	// NFI read prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN |
-+			    CNFG_READ_MODE | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+
-+	buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_DECODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom read interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);
-+	reinit_completion(&snf->op_done);
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);
-+
-+	// Start DMA read
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BRD);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for reading from cache.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup;
-+	}
-+
-+	// Wait for BUS_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val,
-+				 BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n");
-+		goto cleanup2;
-+	}
-+
-+	// Wait for bus becoming idle
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+				 !(val & snf->caps->mastersta_mask), 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret) {
-+		dev_err(snf->dev, "Timed out waiting for bus becoming idle\n");
-+		goto cleanup2;
-+	}
-+
-+	if (op->data.ecc) {
-+		ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE);
-+		if (ret) {
-+			dev_err(snf->dev, "wait ecc done timeout\n");
-+			goto cleanup2;
-+		}
-+		// save status before disabling ecc
-+		mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats,
-+				  snf->nfi_cfg.nsectors);
-+	}
-+
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+
-+	if (snf->autofmt) {
-+		mtk_snand_read_fdm(snf, buf_fdm);
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_bm_swap(snf, buf);
-+			mtk_snand_fdm_bm_swap(snf);
-+		}
-+	}
-+
-+	// copy data back
-+	if (nfi_read32(snf, NFI_STA) & READ_EMPTY) {
-+		memset(op->data.buf.in, 0xff, op->data.nbytes);
-+		snf->ecc_stats.bitflips = 0;
-+		snf->ecc_stats.failed = 0;
-+		snf->ecc_stats.corrected = 0;
-+	} else {
-+		if (buf == op->data.buf.in) {
-+			u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size;
-+			u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size;
-+
-+			if (req_left)
-+				memcpy(op->data.buf.in + snf->nfi_cfg.page_size,
-+				       buf_fdm,
-+				       cap_len < req_left ? cap_len : req_left);
-+		} else if (rd_offset < snf->buf_len) {
-+			u32 cap_len = snf->buf_len - rd_offset;
-+
-+			if (op->data.nbytes < cap_len)
-+				cap_len = op->data.nbytes;
-+			memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len);
-+		}
-+	}
-+cleanup2:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	// unmap dma only if any error happens. (otherwise it's done before
-+	// data copying)
-+	if (ret)
-+		dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+cleanup:
-+	// Stop read
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0);
-+	return ret;
-+}
-+
-+static int mtk_snand_write_page_cache(struct mtk_snand *snf,
-+				      const struct spi_mem_op *op)
-+{
-+	// the address part to be sent by the controller
-+	u32 op_addr = op->addr.val;
-+	// where to start copying data from bounce buffer
-+	u32 wr_offset = 0;
-+	u32 op_mode = 0;
-+	int ret = 0;
-+	u32 wr_mode = 0;
-+	u32 dma_len = snf->buf_len;
-+	u32 wr_bytes, val;
-+	size_t cap_len;
-+	dma_addr_t buf_dma;
-+
-+	if (snf->autofmt) {
-+		u32 last_bit;
-+		u32 mask;
-+
-+		dma_len = snf->nfi_cfg.page_size;
-+		op_mode = CNFG_AUTO_FMT_EN;
-+		if (op->data.ecc)
-+			op_mode |= CNFG_HW_ECC_EN;
-+
-+		last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+		mask = (1 << last_bit) - 1;
-+		wr_offset = op_addr & mask;
-+		op_addr &= ~mask;
-+	}
-+	mtk_snand_mac_reset(snf);
-+	mtk_nfi_reset(snf);
-+
-+	if (wr_offset)
-+		memset(snf->buf, 0xff, wr_offset);
-+
-+	cap_len = snf->buf_len - wr_offset;
-+	if (op->data.nbytes < cap_len)
-+		cap_len = op->data.nbytes;
-+	memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len);
-+	if (snf->autofmt) {
-+		if (snf->caps->bbm_swap) {
-+			mtk_snand_fdm_bm_swap(snf);
-+			mtk_snand_bm_swap(snf, snf->buf);
-+		}
-+		mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size);
-+	}
-+
-+	// Command
-+	nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S));
-+
-+	// write address
-+	nfi_write32(snf, SNF_PG_CTL2, op_addr);
-+
-+	// Set read op_mode
-+	if (op->data.buswidth == 4)
-+		wr_mode = PG_LOAD_X4_EN;
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN,
-+		  wr_mode | PG_LOAD_CUSTOM_EN);
-+
-+	// Set bytes to write
-+	wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+		   snf->nfi_cfg.nsectors;
-+	nfi_write32(snf, SNF_MISC_CTL2,
-+		    (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes);
-+
-+	// NFI write prepare
-+	nfi_write16(snf, NFI_CNFG,
-+		    (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |
-+			    CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode);
-+
-+	nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+	buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE);
-+	if (dma_mapping_error(snf->dev, buf_dma)) {
-+		dev_err(snf->dev, "DMA mapping failed.\n");
-+		goto cleanup;
-+	}
-+	nfi_write32(snf, NFI_STRADDR, buf_dma);
-+	if (op->data.ecc) {
-+		snf->ecc_cfg->op = ECC_ENCODE;
-+		ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+		if (ret)
-+			goto cleanup_dma;
-+	}
-+	// Prepare for custom write interrupt
-+	nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);
-+	reinit_completion(&snf->op_done);
-+	;
-+
-+	// Trigger NFI into custom mode
-+	nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);
-+
-+	// Start DMA write
-+	nfi_rmw32(snf, NFI_CON, 0, CON_BWR);
-+	nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+	if (!wait_for_completion_timeout(
-+		    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+		dev_err(snf->dev, "DMA timed out for program load.\n");
-+		ret = -ETIMEDOUT;
-+		goto cleanup_ecc;
-+	}
-+
-+	// Wait for NFI_SEC_CNTR returning expected value
-+	ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val,
-+				 NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+				 SNFI_POLL_INTERVAL);
-+	if (ret)
-+		dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n");
-+
-+cleanup_ecc:
-+	if (op->data.ecc)
-+		mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+	dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE);
-+cleanup:
-+	// Stop write
-+	nfi_write32(snf, NFI_CON, 0);
-+	nfi_write16(snf, NFI_CNFG, 0);
-+
-+	// Clear SNF done flag
-+	nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);
-+	nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+	// Disable interrupt
-+	nfi_read32(snf, NFI_INTR_STA);
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+	nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);
-+
-+	return ret;
-+}
-+
-+/**
-+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op.
-+ * @op spi-mem op to check
-+ *
-+ * Check whether op can be executed with read_from_cache or program_load
-+ * mode in the controller.
-+ * This controller can execute typical Read From Cache and Program Load
-+ * instructions found on SPI-NAND with 2-byte address.
-+ * DTR and cmd buswidth & nbytes should be checked before calling this.
-+ *
-+ * Return: true if the op matches the instruction template
-+ */
-+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op)
-+{
-+	if (op->addr.nbytes != 2)
-+		return false;
-+
-+	if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
-+	    op->addr.buswidth != 4)
-+		return false;
-+
-+	// match read from page instructions
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth >
-+		    DATA_READ_MAX_DUMMY)
-+			return false;
-+		// quad io / quad out
-+		if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 4)
-+			return true;
-+
-+		// dual io / dual out
-+		if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&
-+		    op->data.buswidth == 2)
-+			return true;
-+
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	} else if (op->data.dir == SPI_MEM_DATA_OUT) {
-+		// check dummy cycle first
-+		if (op->dummy.nbytes)
-+			return false;
-+		// program load quad out
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 4)
-+			return true;
-+		// standard spi
-+		if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+			return true;
-+	}
-+	return false;
-+}
-+
-+static bool mtk_snand_supports_op(struct spi_mem *mem,
-+				  const struct spi_mem_op *op)
-+{
-+	if (!spi_mem_default_supports_op(mem, op))
-+		return false;
-+	if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
-+		return false;
-+	if (mtk_snand_is_page_ops(op))
-+		return true;
-+	return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) &&
-+		(op->dummy.nbytes == 0 || op->dummy.buswidth == 1) &&
-+		(op->data.nbytes == 0 || op->data.buswidth == 1));
-+}
-+
-+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+	// page ops transfer size must be exactly ((sector_size + spare_size) *
-+	// nsectors). Limit the op size if the caller requests more than that.
-+	// exec_op will read more than needed and discard the leftover if the
-+	// caller requests less data.
-+	if (mtk_snand_is_page_ops(op)) {
-+		size_t l;
-+		// skip adjust_op_size for page ops
-+		if (ms->autofmt)
-+			return 0;
-+		l = ms->caps->sector_size + ms->nfi_cfg.spare_size;
-+		l *= ms->nfi_cfg.nsectors;
-+		if (op->data.nbytes > l)
-+			op->data.nbytes = l;
-+	} else {
-+		size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
-+
-+		if (hl >= SNF_GPRAM_SIZE)
-+			return -EOPNOTSUPP;
-+		if (op->data.nbytes > SNF_GPRAM_SIZE - hl)
-+			op->data.nbytes = SNF_GPRAM_SIZE - hl;
-+	}
-+	return 0;
-+}
-+
-+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
-+{
-+	struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+
-+	dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
-+		op->addr.val, op->addr.buswidth, op->addr.nbytes,
-+		op->data.buswidth, op->data.nbytes);
-+	if (mtk_snand_is_page_ops(op)) {
-+		if (op->data.dir == SPI_MEM_DATA_IN)
-+			return mtk_snand_read_page_cache(ms, op);
-+		else
-+			return mtk_snand_write_page_cache(ms, op);
-+	} else {
-+		return mtk_snand_mac_io(ms, op);
-+	}
-+}
-+
-+static const struct spi_controller_mem_ops mtk_snand_mem_ops = {
-+	.adjust_op_size = mtk_snand_adjust_op_size,
-+	.supports_op = mtk_snand_supports_op,
-+	.exec_op = mtk_snand_exec_op,
-+};
-+
-+static const struct spi_controller_mem_caps mtk_snand_mem_caps = {
-+	.ecc = true,
-+};
-+
-+static irqreturn_t mtk_snand_irq(int irq, void *id)
-+{
-+	struct mtk_snand *snf = id;
-+	u32 sta, ien;
-+
-+	sta = nfi_read32(snf, NFI_INTR_STA);
-+	ien = nfi_read32(snf, NFI_INTR_EN);
-+
-+	if (!(sta & ien))
-+		return IRQ_NONE;
-+
-+	nfi_write32(snf, NFI_INTR_EN, 0);
-+	complete(&snf->op_done);
-+	return IRQ_HANDLED;
-+}
-+
-+static const struct of_device_id mtk_snand_ids[] = {
-+	{ .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps },
-+	{ .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps },
-+	{},
-+};
-+
-+MODULE_DEVICE_TABLE(of, mtk_snand_ids);
-+
-+static int mtk_snand_enable_clk(struct mtk_snand *ms)
-+{
-+	int ret;
-+
-+	ret = clk_prepare_enable(ms->nfi_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable nfi clk\n");
-+		return ret;
-+	}
-+	ret = clk_prepare_enable(ms->pad_clk);
-+	if (ret) {
-+		dev_err(ms->dev, "unable to enable pad clk\n");
-+		goto err1;
-+	}
-+	return 0;
-+err1:
-+	clk_disable_unprepare(ms->nfi_clk);
-+	return ret;
-+}
-+
-+static void mtk_snand_disable_clk(struct mtk_snand *ms)
-+{
-+	clk_disable_unprepare(ms->pad_clk);
-+	clk_disable_unprepare(ms->nfi_clk);
-+}
-+
-+static int mtk_snand_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	const struct of_device_id *dev_id;
-+	struct spi_controller *ctlr;
-+	struct mtk_snand *ms;
-+	int ret;
-+
-+	dev_id = of_match_node(mtk_snand_ids, np);
-+	if (!dev_id)
-+		return -EINVAL;
-+
-+	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms));
-+	if (!ctlr)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, ctlr);
-+
-+	ms = spi_controller_get_devdata(ctlr);
-+
-+	ms->ctlr = ctlr;
-+	ms->caps = dev_id->data;
-+
-+	ms->ecc = of_mtk_ecc_get(np);
-+	if (IS_ERR(ms->ecc))
-+		return PTR_ERR(ms->ecc);
-+	else if (!ms->ecc)
-+		return -ENODEV;
-+
-+	ms->nfi_base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(ms->nfi_base)) {
-+		ret = PTR_ERR(ms->nfi_base);
-+		goto release_ecc;
-+	}
-+
-+	ms->dev = &pdev->dev;
-+
-+	ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk");
-+	if (IS_ERR(ms->nfi_clk)) {
-+		ret = PTR_ERR(ms->nfi_clk);
-+		dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk");
-+	if (IS_ERR(ms->pad_clk)) {
-+		ret = PTR_ERR(ms->pad_clk);
-+		dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret);
-+		goto release_ecc;
-+	}
-+
-+	ret = mtk_snand_enable_clk(ms);
-+	if (ret)
-+		goto release_ecc;
-+
-+	init_completion(&ms->op_done);
-+
-+	ms->irq = platform_get_irq(pdev, 0);
-+	if (ms->irq < 0) {
-+		ret = ms->irq;
-+		goto disable_clk;
-+	}
-+	ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0,
-+			       "mtk-snand", ms);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to request snfi irq\n");
-+		goto disable_clk;
-+	}
-+
-+	ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32));
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set dma mask\n");
-+		goto disable_clk;
-+	}
-+
-+	// switch to SNFI mode
-+	nfi_write32(ms, SNF_CFG, SPI_MODE);
-+
-+	// setup an initial page format for ops matching page_cache_op template
-+	// before ECC is called.
-+	ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size,
-+				      ms->caps->spare_sizes[0]);
-+	if (ret) {
-+		dev_err(ms->dev, "failed to set initial page format\n");
-+		goto disable_clk;
-+	}
-+
-+	// setup ECC engine
-+	ms->ecc_eng.dev = &pdev->dev;
-+	ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
-+	ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops;
-+	ms->ecc_eng.priv = ms;
-+
-+	ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to register ecc engine.\n");
-+		goto disable_clk;
-+	}
-+
-+	ctlr->num_chipselect = 1;
-+	ctlr->mem_ops = &mtk_snand_mem_ops;
-+	ctlr->mem_caps = &mtk_snand_mem_caps;
-+	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
-+	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
-+	ctlr->dev.of_node = pdev->dev.of_node;
-+	ret = spi_register_controller(ctlr);
-+	if (ret) {
-+		dev_err(&pdev->dev, "spi_register_controller failed.\n");
-+		goto disable_clk;
-+	}
-+
-+	return 0;
-+disable_clk:
-+	mtk_snand_disable_clk(ms);
-+release_ecc:
-+	mtk_ecc_release(ms->ecc);
-+	return ret;
-+}
-+
-+static int mtk_snand_remove(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctlr = platform_get_drvdata(pdev);
-+	struct mtk_snand *ms = spi_controller_get_devdata(ctlr);
-+
-+	spi_unregister_controller(ctlr);
-+	mtk_snand_disable_clk(ms);
-+	mtk_ecc_release(ms->ecc);
-+	kfree(ms->buf);
-+	return 0;
-+}
-+
-+static struct platform_driver mtk_snand_driver = {
-+	.probe = mtk_snand_probe,
-+	.remove = mtk_snand_remove,
-+	.driver = {
-+		.name = "mtk-snand",
-+		.of_match_table = mtk_snand_ids,
-+	},
-+};
-+
-+module_platform_driver(mtk_snand_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
-+MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver");
diff --git a/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch
deleted file mode 100644
index 01d9d12088..0000000000
--- a/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Mon, 4 Apr 2022 00:05:38 +0800
-Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if
- available
-
-The recently added ECC engine support introduced a generic property
-named nand-ecc-engine for ecc engine phandle. This patch adds support
-for this new property.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54)
----
- drivers/mtd/nand/ecc-mtk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/ecc-mtk.c
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de
- 	struct mtk_ecc *ecc = NULL;
- 	struct device_node *np;
- 
--	np = of_parse_phandle(of_node, "ecc-engine", 0);
-+	np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
-+	/* for backward compatibility */
-+	if (!np)
-+		np = of_parse_phandle(of_node, "ecc-engine", 0);
- 	if (np) {
- 		ecc = mtk_ecc_get(np);
- 		of_node_put(np);
diff --git a/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch
deleted file mode 100644
index 15d2671372..0000000000
--- a/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Sun, 3 Apr 2022 10:19:29 +0800
-Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622
-
-This patch adds a device-tree node for the MTK SPI-NAND Flash Interface
-for MT7622 device tree.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af)
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -553,6 +553,18 @@
- 		status = "disabled";
- 	};
- 
-+	snfi: spi@1100d000 {
-+		compatible = "mediatek,mt7622-snand";
-+		reg = <0 0x1100d000 0 0x1000>;
-+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+		clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+		clock-names = "nfi_clk", "pad_clk";
-+		nand-ecc-engine = <&bch>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	bch: ecc@1100e000 {
- 		compatible = "mediatek,mt7622-ecc";
- 		reg = <0 0x1100e000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch
deleted file mode 100644
index ff5521c44e..0000000000
--- a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
- static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
- {
- 	struct spinand_device *spinand = nand_to_spinand(nand);
--	u8 marker[2] = { };
-+	u8 marker[1] = { };
- 	struct nand_page_io_req req = {
- 		.pos = *pos,
- 		.ooblen = sizeof(marker),
-@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
- 
- 	spinand_select_target(spinand, pos->target);
- 	spinand_read_page(spinand, &req);
--	if (marker[0] != 0xff || marker[1] != 0xff)
-+	if (marker[0] != 0xff)
- 		return true;
- 
- 	return false;
diff --git a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch
deleted file mode 100644
index be0018a383..0000000000
--- a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
-From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
-Date: Thu, 6 Jun 2019 16:29:04 +0800
-Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
-
-Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
----
- arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7629.dtsi    | 22 ++++++++++++++++
- 3 files changed, 79 insertions(+)
-
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -272,6 +272,27 @@
- 			status = "disabled";
- 		};
- 
-+		snfi: spi@1100d000 {
-+			compatible = "mediatek,mt7629-snand";
-+			reg = <0x1100d000 0x1000>;
-+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+			clock-names = "nfi_clk", "pad_clk";
-+			nand-ecc-engine = <&bch>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		bch: ecc@1100e000 {
-+			compatible = "mediatek,mt7622-ecc";
-+			reg = <0x1100e000 0x1000>;
-+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFIECC_PD>;
-+			clock-names = "nfiecc_clk";
-+			status = "disabled";
-+		};
-+
- 		spi: spi@1100a000 {
- 			compatible = "mediatek,mt7629-spi",
- 				     "mediatek,mt7622-spi";
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -254,6 +254,50 @@
- 	};
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Bootloader";
-+				reg = <0x00000 0x0100000>;
-+				read-only;
-+			};
-+
-+			partition@100000 {
-+				label = "Config";
-+				reg = <0x100000 0x0040000>;
-+			};
-+
-+			partition@140000 {
-+				label = "factory";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "firmware";
-+				reg = <0x1c0000 0x1000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spi_pins>;
diff --git a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch
deleted file mode 100644
index 134e5997e2..0000000000
--- a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -539,6 +539,65 @@
- 	status = "disabled";
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Preloader";
-+				reg = <0x00000 0x0080000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "ATF";
-+				reg = <0x80000 0x0040000>;
-+			};
-+
-+			partition@c0000 {
-+				label = "Bootloader";
-+				reg = <0xc0000 0x0080000>;
-+			};
-+
-+			partition@140000 {
-+				label = "Config";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "Factory";
-+				reg = <0x1c0000 0x0100000>;
-+			};
-+
-+			partition@200000 {
-+				label = "firmware";
-+				reg = <0x2c0000 0x2000000>;
-+			};
-+
-+			partition@2200000 {
-+				label = "User_data";
-+				reg = <0x22c0000 0x4000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spic0_pins>;
diff --git a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
deleted file mode 100644
index 8e6935b434..0000000000
--- a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -580,7 +580,7 @@
- 				reg = <0x140000 0x0080000>;
- 			};
- 
--			partition@1c0000 {
-+			factory: partition@1c0000 {
- 				label = "Factory";
- 				reg = <0x1c0000 0x0100000>;
- 			};
-@@ -641,5 +641,6 @@
- &wmac {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&wmac_pins>;
-+	mediatek,mtd-eeprom = <&factory 0x0000>;
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch
deleted file mode 100644
index 5b63bf4226..0000000000
--- a/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -951,17 +951,15 @@
- 	};
- 
- 	crypto: crypto@1b240000 {
--		compatible = "mediatek,eip97-crypto";
-+		compatible = "inside-secure,safexcel-eip97";
- 		reg = <0 0x1b240000 0 0x20000>;
- 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
-+			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "ring0", "ring1", "ring2", "ring3";
- 		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
--		clock-names = "cryp";
--		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
--		status = "disabled";
-+		status = "okay";
- 	};
- 
- 	bdpsys: syscon@1c000000 {
diff --git a/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch
deleted file mode 100644
index 091cffc3c0..0000000000
--- a/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,7 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
--		bootargs = "console=ttyS2,115200n8 console=tty1";
-+		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {
diff --git a/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch
deleted file mode 100644
index d1bafc1526..0000000000
--- a/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,8 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		mmc0 = &mmc0;
-+		mmc1 = &mmc1;
- 	};
- 
- 	chosen {
diff --git a/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch
deleted file mode 100644
index f6745add5b..0000000000
--- a/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -17,6 +17,10 @@
- 		serial2 = &uart2;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
- 	};
- 
- 	chosen {
-@@ -112,13 +116,13 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&led_pins_a>;
- 
--		blue {
-+		led_system_blue: blue {
- 			label = "bpi-r2:pio:blue";
- 			gpios = <&pio 240 GPIO_ACTIVE_LOW>;
- 			default-state = "off";
- 		};
- 
--		green {
-+		led_system_green: green {
- 			label = "bpi-r2:pio:green";
- 			gpios = <&pio 241 GPIO_ACTIVE_LOW>;
- 			default-state = "off";
diff --git a/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch
deleted file mode 100644
index b1dd75a414..0000000000
--- a/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,7 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		ethernet0 = &gmac0;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
- 		led-boot = &led_system_green;
diff --git a/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch b/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch
deleted file mode 100644
index ba1d1fe202..0000000000
--- a/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
-From: Sungbo Eo <mans0n@gorani.run>
-Date: Sun, 8 Aug 2021 21:38:40 +0900
-Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
-
-MT7623 has an musb controller that is compatible with the one from MT2701.
-
-Signed-off-by: Sungbo Eo <mans0n@gorani.run>
----
- arch/arm/boot/dts/mt7623.dtsi  | 34 ++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623a.dtsi |  4 ++++
- 2 files changed, 38 insertions(+)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -585,6 +585,40 @@
- 		status = "disabled";
- 	};
- 
-+	usb0: usb@11200000 {
-+		compatible = "mediatek,mt7623-musb",
-+			     "mediatek,mtk-musb";
-+		reg = <0 0x11200000 0 0x1000>;
-+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "mc";
-+		phys = <&u2port2 PHY_TYPE_USB2>;
-+		dr_mode = "otg";
-+		clocks = <&pericfg CLK_PERI_USB0>,
-+			 <&pericfg CLK_PERI_USB0_MCU>,
-+			 <&pericfg CLK_PERI_USB_SLV>;
-+		clock-names = "main","mcu","univpll";
-+		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-+		status = "disabled";
-+	};
-+
-+	u2phy1: t-phy@11210000 {
-+		compatible = "mediatek,mt7623-tphy",
-+			     "mediatek,generic-tphy-v1";
-+		reg = <0 0x11210000 0 0x0800>;
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+		status = "disabled";
-+
-+		u2port2: usb-phy@11210800 {
-+			reg = <0 0x11210800 0 0x0100>;
-+			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
-+			clock-names = "ref";
-+			#phy-cells = <1>;
-+			status = "okay";
-+		};
-+	};
-+
- 	audsys: clock-controller@11220000 {
- 		compatible = "mediatek,mt7623-audsys",
- 			     "mediatek,mt2701-audsys",
---- a/arch/arm/boot/dts/mt7623a.dtsi
-+++ b/arch/arm/boot/dts/mt7623a.dtsi
-@@ -35,6 +35,10 @@
- 	clock-names = "ethif";
- };
- 
-+&usb0 {
-+	power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
-+};
-+
- &usb1 {
- 	power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
- };
diff --git a/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
deleted file mode 100644
index 80ceb490d4..0000000000
--- a/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -160,6 +160,10 @@
- 		switch@0 {
- 			compatible = "mediatek,mt7531";
- 			reg = <0>;
-+			interrupt-controller;
-+			#interrupt-cells = <1>;
-+			interrupt-parent = <&pio>;
-+			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- 			reset-gpios = <&pio 54 0>;
- 
- 			ports {
diff --git a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
deleted file mode 100644
index 39a9770d98..0000000000
--- a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From patchwork Tue Apr 26 19:51:36 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 12827872
-Return-Path: 
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-	(No client certificate requested)
-	by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF
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- id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
-Date: Tue, 26 Apr 2022 20:51:36 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
-Cc: Rob Herring <robh+dt@kernel.org>,
- Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
- Matthias Brugger <matthias.bgg@gmail.com>
-Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
-Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 
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-
-With the current range specified for the CPU interface there is an
-error message at boot:
-
-GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
-
-Setting irqchip.gicv2_force_probe=1 in bootargs results in:
-
-GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
-GIC: Adjusting CPU interface base to 0x000000001032f000
-GIC: Using split EOI/Deactivate mode
-
-Using the adjusted CPU interface base and 8K size results in only the
-final line remaining and fully working system as well as /proc/interrupts
-showing additional IPI3,4,5,6:
-
-IPI3:         0          0       CPU stop (for crash dump) interrupts
-IPI4:         0          0       Timer broadcast interrupts
-IPI5:         0          0       IRQ work interrupts
-IPI6:         0          0       CPU wake-up interrupts
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -339,7 +339,7 @@
- 		#interrupt-cells = <3>;
- 		interrupt-parent = <&gic>;
- 		reg = <0 0x10310000 0 0x1000>,
--		      <0 0x10320000 0 0x1000>,
-+		      <0 0x1032f000 0 0x2000>,
- 		      <0 0x10340000 0 0x2000>,
- 		      <0 0x10360000 0 0x2000>;
- 	};
diff --git a/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch b/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch
deleted file mode 100644
index 8851fefbb3..0000000000
--- a/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch
+++ /dev/null
@@ -1,132 +0,0 @@
-From patchwork Thu Apr 28 22:57:55 2022
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-Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
-Date: Thu, 28 Apr 2022 23:57:55 +0100
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-Errors-To: 
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-
-On an MT7622 system, the kernel complains of not being able to detect the cache
-hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
-order to fix this.
-
-Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -80,6 +80,7 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -94,6 +95,12 @@
- 			enable-method = "psci";
- 			clock-frequency = <1300000000>;
- 			cci-control-port = <&cci_control2>;
-+			next-level-cache = <&L2>;
-+		};
-+
-+		L2: l2-cache {
-+			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
diff --git a/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch b/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch
deleted file mode 100644
index 4fef9aea22..0000000000
--- a/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From patchwork Fri Apr 29 08:42:25 2022
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-Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org,
- Rui Salvaterra <rsalvaterra@gmail.com>
-Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests
-Date: Fri, 29 Apr 2022 09:42:25 +0100
-Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com>
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-
-The MT7622 device tree never bothered to specify the number of virtual DMA
-channels for the HSDMA controller, always falling back to the default value of
-3. Make this value explicit, in order to avoid the following dmesg notification:
-
-mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property
-
-Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -942,6 +942,7 @@
- 		clock-names = "hsdma";
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- 		#dma-cells = <1>;
-+		dma-requests = <3>;
- 	};
- 
- 	pcie_mirror: pcie-mirror@10000400 {
diff --git a/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch
deleted file mode 100644
index 1cfb53d620..0000000000
--- a/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
-From: Bruno Umuarama <anonimou_eu@hotmail.com>
-Date: Thu, 13 Oct 2022 21:18:21 +0000
-Subject: [PATCH] mediatek: mt7623: fix thermal zone
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Raising the temperatures for passive and active trips. @VA1DER
-proposed at issue 9396 to remove passive trip. This commit relates to
-his suggestion.
-
-Without this patch. the CPU will be throttled all the way down to 98MHz
-if the temperature rises even a degree above the trip point, and it was
-further discovered that if the internal temperature of the device is
-above the first trip point temperature when it boots then it will start
-in a throttled state and even
-$ echo disabled > /sys/class/thermal/thermal_zone0/mode
-will have no effect.
-
-The patch increases the passive trip point and active cooling map. The
-throttling temperature will then be at 77°C and 82°C, which is still a
-low enough temperature for ARM devices to not be in the real danger
-zone, and gives some operational headroom.
-
-Signed-off-by: Bruno Umuarama <anonimou_eu@hotmail.com>
----
- arch/arm/boot/dts/mt7623.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -160,13 +160,13 @@
- 
- 				trips {
- 					cpu_passive: cpu-passive {
--						temperature = <57000>;
-+						temperature = <77000>;
- 						hysteresis = <2000>;
- 						type = "passive";
- 					};
- 
- 					cpu_active: cpu-active {
--						temperature = <67000>;
-+						temperature = <82000>;
- 						hysteresis = <2000>;
- 						type = "active";
- 					};
diff --git a/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch
deleted file mode 100644
index 161c1e7516..0000000000
--- a/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -68,6 +68,14 @@
- 		#address-cells = <2>;
- 		#size-cells = <2>;
- 		ranges;
-+
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;
diff --git a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch
deleted file mode 100644
index 336920bafe..0000000000
--- a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch
+++ /dev/null
@@ -1,196 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -23,6 +23,10 @@
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
- 		ethernet1 = &gmac1;
-+		led-boot = &green_led;
-+		led-failsafe = &green_led;
-+		led-running = &green_led;
-+		led-upgrade = &blue_led;
- 	};
- 
- 	chosen {
-@@ -419,27 +423,27 @@
- 
- 		port@1 {
- 			reg = <1>;
--			label = "lan0";
-+			label = "lan1";
- 		};
- 
- 		port@2 {
- 			reg = <2>;
--			label = "lan1";
-+			label = "lan2";
- 		};
- 
- 		port@3 {
- 			reg = <3>;
--			label = "lan2";
-+			label = "lan3";
- 		};
- 
- 		port@4 {
- 			reg = <4>;
--			label = "lan3";
-+			label = "lan4";
- 		};
- 
- 		port5: port@5 {
- 			reg = <5>;
--			label = "lan4";
-+			label = "sfp2";
- 			phy-mode = "2500base-x";
- 			sfp = <&sfp2>;
- 			managed = "in-band-status";
-@@ -490,9 +494,137 @@
- 
- &wifi {
- 	status = "okay";
--	pinctrl-names = "default", "dbdc";
-+	pinctrl-names = "default";
- 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
--	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+
-+	mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
-+				0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
-+				0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
-+				0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
-+				0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
-+				0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
-+				0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
-+				0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
-+				0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
-+				0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
-+				0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
-+				0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
-+				0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
-+				0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
-+				0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
-+				0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
-+				0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
-+				0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
-+				0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
-+				0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
-+				0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
-+				0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
-+				0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
-+				0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
-+				0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
-+				0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
-+				0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
-+				0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
-+				0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
-+				0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
-+				0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
-+				0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
-+				0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
-+				0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
-+				0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
-+				0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
-+				0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
-+				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+				0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
-+				0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
-+				0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
-+				0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
-+				0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
-+				0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
-+				0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
-+				0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
-+				0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
-+				0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
- 
- 	led {
- 		led-active-low;
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -55,6 +55,7 @@
- 					partition@c00000 {
- 						label = "fit";
- 						reg = <0xc00000 0x1400000>;
-+						compatible = "denx,fit";
- 					};
- 				};
- 			};
diff --git a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
deleted file mode 100644
index cfb0556d1e..0000000000
--- a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
-From: Kristian Evensen <kristian.evensen@gmail.com>
-Date: Mon, 30 Apr 2018 14:38:01 +0200
-Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
-
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -18,6 +18,8 @@
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
- 
- /* version V1 sub-banks offset base address */
- /* banks shared by multiple phys */
-@@ -311,6 +313,9 @@
- 
- #define TPHY_CLKS_CNT	2
- 
-+#define HIF_SYSCFG1			0x14
-+#define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
-+
- enum mtk_phy_version {
- 	MTK_PHY_V1 = 1,
- 	MTK_PHY_V2,
-@@ -377,6 +382,7 @@ struct mtk_tphy {
- 	void __iomem *sif_base;	/* only shared sif */
- 	const struct mtk_phy_pdata *pdata;
- 	struct mtk_phy_instance **phys;
-+	struct regmap *hif;
- 	int nphys;
- 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
- 	int src_coef; /* coefficient for slew rate calibrate */
-@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc
- 	if (tphy->pdata->version != MTK_PHY_V1)
- 		return;
- 
-+	if (tphy->hif)
-+		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
-+				   HIF_SYSCFG1_PHY2_MASK, 0);
-+
- 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
- 	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
- 	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
-@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor
- 					 &tphy->src_coef);
- 	}
- 
-+	if (of_find_property(np, "mediatek,phy-switch", NULL)) {
-+		tphy->hif = syscon_regmap_lookup_by_phandle(np,
-+							    "mediatek,phy-switch");
-+		if (IS_ERR(tphy->hif)) {
-+			dev_err(&pdev->dev,
-+				"missing \"mediatek,phy-switch\" phandle\n");
-+			return PTR_ERR(tphy->hif);
-+		}
-+	}
-+
- 	port = 0;
- 	for_each_child_of_node(np, child_np) {
- 		struct mtk_phy_instance *instance;
diff --git a/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch
deleted file mode 100644
index 0761e1da18..0000000000
--- a/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7986
-+	bool "Mediatek MT7986 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- 	bool "Mediatek MT8167 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
diff --git a/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch b/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch
deleted file mode 100644
index 15de8aa3d4..0000000000
--- a/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -43,6 +43,15 @@ err_out:
- 	return NULL;
- }
- 
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data)
-+{
-+	if (!clk_data)
-+		return;
-+
-+	kfree(clk_data->clks);
-+	kfree(clk_data);
-+}
-+
- void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
- 		int num, struct clk_onecell_data *clk_data)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str
- 				struct clk_onecell_data *clk_data);
- 
- struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data);
- 
- #define HAVE_RST_BAR	BIT(0)
- #define PLL_AO		BIT(1)
diff --git a/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch b/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch
deleted file mode 100644
index 8e2365a498..0000000000
--- a/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch
+++ /dev/null
@@ -1,39 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
- 	  to PCI-E and USB.
- 
-+config COMMON_CLK_MT7986
-+	bool "Clock driver for MediaTek MT7986"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7986 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7986_ETHSYS
-+	bool "Clock driver for MediaTek MT7986 ETHSYS"
-+	depends on COMMON_CLK_MT7986
-+	default COMMON_CLK_MT7986
-+	help
-+	  This driver add support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7986 SoC.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
diff --git a/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch b/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch
deleted file mode 100644
index 04da1765f3..0000000000
--- a/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch
+++ /dev/null
@@ -1,917 +0,0 @@
-From 7d99750f96fc6904d54affebdc8c9b0bfae1e9e8 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Apr 2022 11:40:22 +0800
-Subject: [PATCH] spi: mediatek: backport document and driver to support mt7986
- spi design
-
-this patch add the support of ipm design and upgrade devicetree binding
-
-The patch is comming from following threads
-- https://lore.kernel.org/all/20220315032411.2826-1-leilk.liu@mediatek.com/
-- https://lore.kernel.org/all/20220401071616.8874-1-leilk.liu@mediatek.com/
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
----
- .../bindings/spi/mediatek,spi-mt65xx.yaml     | 111 ++++
- drivers/spi/spi-mt65xx.c                      | 509 ++++++++++++++++--
- 2 files changed, 572 insertions(+), 48 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-@@ -0,0 +1,111 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: SPI Bus controller for MediaTek ARM SoCs
-+
-+maintainers:
-+  - Leilk Liu <leilk.liu@mediatek.com>
-+
-+allOf:
-+  - $ref: "/schemas/spi/spi-controller.yaml#"
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - items:
-+          - enum:
-+              - mediatek,mt7629-spi
-+          - const: mediatek,mt7622-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt8516-spi
-+          - const: mediatek,mt2712-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt6779-spi
-+              - mediatek,mt8186-spi
-+              - mediatek,mt8192-spi
-+              - mediatek,mt8195-spi
-+          - const: mediatek,mt6765-spi
-+      - items:
-+          - enum:
-+              - mediatek,mt7986-spi-ipm
-+          - const: mediatek,spi-ipm
-+      - items:
-+          - enum:
-+              - mediatek,mt2701-spi
-+              - mediatek,mt2712-spi
-+              - mediatek,mt6589-spi
-+              - mediatek,mt6765-spi
-+              - mediatek,mt6893-spi
-+              - mediatek,mt7622-spi
-+              - mediatek,mt8135-spi
-+              - mediatek,mt8173-spi
-+              - mediatek,mt8183-spi
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    minItems: 3
-+    items:
-+      - description: clock used for the parent clock
-+      - description: clock used for the muxes clock
-+      - description: clock used for the clock gate
-+      - description: clock used for the AHB bus, this clock is optional
-+
-+  clock-names:
-+    minItems: 3
-+    items:
-+      - const: parent-clk
-+      - const: sel-clk
-+      - const: spi-clk
-+      - const: hclk
-+
-+  mediatek,pad-select:
-+    $ref: /schemas/types.yaml#/definitions/uint32-array
-+    minItems: 1
-+    maxItems: 4
-+    items:
-+      enum: [0, 1, 2, 3]
-+    description:
-+      specify which pins group(ck/mi/mo/cs) spi controller used.
-+      This is an array.
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - clock-names
-+  - '#address-cells'
-+  - '#size-cells'
-+
-+unevaluatedProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/mt8173-clk.h>
-+    #include <dt-bindings/gpio/gpio.h>
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+
-+    spi@1100a000 {
-+      compatible = "mediatek,mt8173-spi";
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+      reg = <0x1100a000 0x1000>;
-+      interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
-+      clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
-+               <&topckgen CLK_TOP_SPI_SEL>,
-+               <&pericfg CLK_PERI_SPI0>;
-+      clock-names = "parent-clk", "sel-clk", "spi-clk";
-+      cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
-+      mediatek,pad-select = <1>, <0>;
-+    };
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -12,11 +12,12 @@
- #include <linux/ioport.h>
- #include <linux/module.h>
- #include <linux/of.h>
--#include <linux/of_gpio.h>
-+#include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
- #include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
- #include <linux/dma-mapping.h>
- 
- #define SPI_CFG0_REG                      0x0000
-@@ -31,6 +32,7 @@
- #define SPI_CFG2_REG                      0x0028
- #define SPI_TX_SRC_REG_64                 0x002c
- #define SPI_RX_DST_REG_64                 0x0030
-+#define SPI_CFG3_IPM_REG                  0x0040
- 
- #define SPI_CFG0_SCK_HIGH_OFFSET          0
- #define SPI_CFG0_SCK_LOW_OFFSET           8
-@@ -51,6 +53,7 @@
- #define SPI_CFG1_CS_IDLE_MASK             0xff
- #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
- #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
-+#define SPI_CFG1_IPM_PACKET_LENGTH_MASK   GENMASK(31, 16)
- #define SPI_CFG2_SCK_HIGH_OFFSET          0
- #define SPI_CFG2_SCK_LOW_OFFSET           16
- 
-@@ -71,6 +74,24 @@
- #define SPI_CMD_TX_ENDIAN            BIT(15)
- #define SPI_CMD_FINISH_IE            BIT(16)
- #define SPI_CMD_PAUSE_IE             BIT(17)
-+#define SPI_CMD_IPM_NONIDLE_MODE     BIT(19)
-+#define SPI_CMD_IPM_SPIM_LOOP        BIT(21)
-+#define SPI_CMD_IPM_GET_TICKDLY_OFFSET    22
-+
-+#define SPI_CMD_IPM_GET_TICKDLY_MASK	GENMASK(24, 22)
-+
-+#define PIN_MODE_CFG(x)	((x) / 2)
-+
-+#define SPI_CFG3_IPM_HALF_DUPLEX_DIR		BIT(2)
-+#define SPI_CFG3_IPM_HALF_DUPLEX_EN		BIT(3)
-+#define SPI_CFG3_IPM_XMODE_EN			BIT(4)
-+#define SPI_CFG3_IPM_NODATA_FLAG		BIT(5)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET		8
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET	12
-+
-+#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK		GENMASK(1, 0)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_MASK		GENMASK(11, 8)
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK		GENMASK(15, 12)
- 
- #define MT8173_SPI_MAX_PAD_SEL 3
- 
-@@ -81,6 +102,9 @@
- 
- #define MTK_SPI_MAX_FIFO_SIZE 32U
- #define MTK_SPI_PACKET_SIZE 1024
-+#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
-+#define MTK_SPI_IPM_PACKET_LOOP SZ_256
-+
- #define MTK_SPI_32BITS_MASK  (0xffffffff)
- 
- #define DMA_ADDR_EXT_BITS (36)
-@@ -96,6 +120,8 @@ struct mtk_spi_compatible {
- 	bool dma_ext;
- 	/* some IC no need unprepare SPI clk */
- 	bool no_need_unprepare;
-+	/* IPM design adjust and extend register to support more features */
-+	bool ipm_design;
- };
- 
- struct mtk_spi {
-@@ -103,7 +129,7 @@ struct mtk_spi {
- 	u32 state;
- 	int pad_num;
- 	u32 *pad_sel;
--	struct clk *parent_clk, *sel_clk, *spi_clk;
-+	struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk;
- 	struct spi_transfer *cur_transfer;
- 	u32 xfer_len;
- 	u32 num_xfered;
-@@ -111,6 +137,11 @@ struct mtk_spi {
- 	u32 tx_sgl_len, rx_sgl_len;
- 	const struct mtk_spi_compatible *dev_comp;
- 	u32 spi_clk_hz;
-+	struct completion spimem_done;
-+	bool use_spimem;
-+	struct device *dev;
-+	dma_addr_t tx_dma;
-+	dma_addr_t rx_dma;
- };
- 
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -119,6 +150,12 @@ static const struct mtk_spi_compatible m
- 	.must_tx = true,
- };
- 
-+static const struct mtk_spi_compatible mtk_ipm_compat = {
-+	.enhance_timing = true,
-+	.dma_ext = true,
-+	.ipm_design = true,
-+};
-+
- static const struct mtk_spi_compatible mt6765_compat = {
- 	.need_pad_sel = true,
- 	.must_tx = true,
-@@ -160,6 +197,9 @@ static const struct mtk_chip_config mtk_
- };
- 
- static const struct of_device_id mtk_spi_of_match[] = {
-+	{ .compatible = "mediatek,spi-ipm",
-+		.data = (void *)&mtk_ipm_compat,
-+	},
- 	{ .compatible = "mediatek,mt2701-spi",
- 		.data = (void *)&mtk_common_compat,
- 	},
-@@ -278,12 +318,11 @@ static int mtk_spi_set_hw_cs_timing(stru
- 	return 0;
- }
- 
--static int mtk_spi_prepare_message(struct spi_master *master,
--				   struct spi_message *msg)
-+static int mtk_spi_hw_init(struct spi_master *master,
-+			   struct spi_device *spi)
- {
- 	u16 cpha, cpol;
- 	u32 reg_val;
--	struct spi_device *spi = msg->spi;
- 	struct mtk_chip_config *chip_config = spi->controller_data;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
-@@ -291,6 +330,15 @@ static int mtk_spi_prepare_message(struc
- 	cpol = spi->mode & SPI_CPOL ? 1 : 0;
- 
- 	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	if (mdata->dev_comp->ipm_design) {
-+		/* SPI transfer without idle time until packet length done */
-+		reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
-+		if (spi->mode & SPI_LOOP)
-+			reg_val |= SPI_CMD_IPM_SPIM_LOOP;
-+		else
-+			reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
-+	}
-+
- 	if (cpha)
- 		reg_val |= SPI_CMD_CPHA;
- 	else
-@@ -348,23 +396,39 @@ static int mtk_spi_prepare_message(struc
- 		       mdata->base + SPI_PAD_SEL_REG);
- 
- 	/* tick delay */
--	reg_val = readl(mdata->base + SPI_CFG1_REG);
- 	if (mdata->dev_comp->enhance_timing) {
--		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
--		reg_val |= ((chip_config->tick_delay & 0x7)
--			    << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+		if (mdata->dev_comp->ipm_design) {
-+			reg_val = readl(mdata->base + SPI_CMD_REG);
-+			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
-+			reg_val |= ((chip_config->tick_delay & 0x7)
-+				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
-+			writel(reg_val, mdata->base + SPI_CMD_REG);
-+		} else {
-+			reg_val = readl(mdata->base + SPI_CFG1_REG);
-+			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-+			reg_val |= ((chip_config->tick_delay & 0x7)
-+				    << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+			writel(reg_val, mdata->base + SPI_CFG1_REG);
-+		}
- 	} else {
-+		reg_val = readl(mdata->base + SPI_CFG1_REG);
- 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
- 		reg_val |= ((chip_config->tick_delay & 0x3)
- 			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
-+		writel(reg_val, mdata->base + SPI_CFG1_REG);
- 	}
--	writel(reg_val, mdata->base + SPI_CFG1_REG);
- 
- 	/* set hw cs timing */
- 	mtk_spi_set_hw_cs_timing(spi);
- 	return 0;
- }
- 
-+static int mtk_spi_prepare_message(struct spi_master *master,
-+				   struct spi_message *msg)
-+{
-+	return mtk_spi_hw_init(master, msg->spi);
-+}
-+
- static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
- {
- 	u32 reg_val;
-@@ -386,13 +450,13 @@ static void mtk_spi_set_cs(struct spi_de
- }
- 
- static void mtk_spi_prepare_transfer(struct spi_master *master,
--				     struct spi_transfer *xfer)
-+				     u32 speed_hz)
- {
- 	u32 div, sck_time, reg_val;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	if (xfer->speed_hz < mdata->spi_clk_hz / 2)
--		div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz);
-+	if (speed_hz < mdata->spi_clk_hz / 2)
-+		div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
- 	else
- 		div = 1;
- 
-@@ -423,12 +487,24 @@ static void mtk_spi_setup_packet(struct
- 	u32 packet_size, packet_loop, reg_val;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
-+	if (mdata->dev_comp->ipm_design)
-+		packet_size = min_t(u32,
-+				    mdata->xfer_len,
-+				    MTK_SPI_IPM_PACKET_SIZE);
-+	else
-+		packet_size = min_t(u32,
-+				    mdata->xfer_len,
-+				    MTK_SPI_PACKET_SIZE);
-+
- 	packet_loop = mdata->xfer_len / packet_size;
- 
- 	reg_val = readl(mdata->base + SPI_CFG1_REG);
--	reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
-+	if (mdata->dev_comp->ipm_design)
-+		reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
-+	else
-+		reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
- 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
-+	reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
- 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
- 	writel(reg_val, mdata->base + SPI_CFG1_REG);
- }
-@@ -523,7 +599,7 @@ static int mtk_spi_fifo_transfer(struct
- 	mdata->cur_transfer = xfer;
- 	mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
- 	mdata->num_xfered = 0;
--	mtk_spi_prepare_transfer(master, xfer);
-+	mtk_spi_prepare_transfer(master, xfer->speed_hz);
- 	mtk_spi_setup_packet(master);
- 
- 	if (xfer->tx_buf) {
-@@ -556,7 +632,7 @@ static int mtk_spi_dma_transfer(struct s
- 	mdata->cur_transfer = xfer;
- 	mdata->num_xfered = 0;
- 
--	mtk_spi_prepare_transfer(master, xfer);
-+	mtk_spi_prepare_transfer(master, xfer->speed_hz);
- 
- 	cmd = readl(mdata->base + SPI_CMD_REG);
- 	if (xfer->tx_buf)
-@@ -591,6 +667,19 @@ static int mtk_spi_transfer_one(struct s
- 				struct spi_device *spi,
- 				struct spi_transfer *xfer)
- {
-+	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
-+	u32 reg_val = 0;
-+
-+	/* prepare xfer direction and duplex mode */
-+	if (mdata->dev_comp->ipm_design) {
-+		if (!xfer->tx_buf || !xfer->rx_buf) {
-+			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+			if (xfer->rx_buf)
-+				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+		}
-+		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+	}
-+
- 	if (master->can_dma(master, spi, xfer))
- 		return mtk_spi_dma_transfer(master, spi, xfer);
- 	else
-@@ -614,8 +703,9 @@ static int mtk_spi_setup(struct spi_devi
- 	if (!spi->controller_data)
- 		spi->controller_data = (void *)&mtk_default_chip_info;
- 
--	if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
--		gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
-+	if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
-+		/* CS de-asserted, gpiolib will handle inversion */
-+		gpiod_direction_output(spi->cs_gpiod, 0);
- 
- 	return 0;
- }
-@@ -633,6 +723,12 @@ static irqreturn_t mtk_spi_interrupt(int
- 	else
- 		mdata->state = MTK_SPI_IDLE;
- 
-+	/* SPI-MEM ops */
-+	if (mdata->use_spimem) {
-+		complete(&mdata->spimem_done);
-+		return IRQ_HANDLED;
-+	}
-+
- 	if (!master->can_dma(master, NULL, trans)) {
- 		if (trans->rx_buf) {
- 			cnt = mdata->xfer_len / 4;
-@@ -716,6 +812,274 @@ static irqreturn_t mtk_spi_interrupt(int
- 	return IRQ_HANDLED;
- }
- 
-+static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
-+				      struct spi_mem_op *op)
-+{
-+	int opcode_len;
-+
-+	if (op->data.dir != SPI_MEM_NO_DATA) {
-+		opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
-+		if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+			op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len;
-+			/* force data buffer dma-aligned. */
-+			op->data.nbytes -= op->data.nbytes % 4;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static bool mtk_spi_mem_supports_op(struct spi_mem *mem,
-+				    const struct spi_mem_op *op)
-+{
-+	if (!spi_mem_default_supports_op(mem, op))
-+		return false;
-+
-+	if (op->addr.nbytes && op->dummy.nbytes &&
-+	    op->addr.buswidth != op->dummy.buswidth)
-+		return false;
-+
-+	if (op->addr.nbytes + op->dummy.nbytes > 16)
-+		return false;
-+
-+	if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+		if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE >
-+		    MTK_SPI_IPM_PACKET_LOOP ||
-+		    op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0)
-+			return false;
-+	}
-+
-+	return true;
-+}
-+
-+static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master,
-+				       const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(master);
-+
-+	writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK),
-+	       mdata->base + SPI_TX_SRC_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+	if (mdata->dev_comp->dma_ext)
-+		writel((u32)(mdata->tx_dma >> 32),
-+		       mdata->base + SPI_TX_SRC_REG_64);
-+#endif
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK),
-+		       mdata->base + SPI_RX_DST_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+		if (mdata->dev_comp->dma_ext)
-+			writel((u32)(mdata->rx_dma >> 32),
-+			       mdata->base + SPI_RX_DST_REG_64);
-+#endif
-+	}
-+}
-+
-+static int mtk_spi_transfer_wait(struct spi_mem *mem,
-+				 const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+	/*
-+	 * For each byte we wait for 8 cycles of the SPI clock.
-+	 * Since speed is defined in Hz and we want milliseconds,
-+	 * so it should be 8 * 1000.
-+	 */
-+	u64 ms = 8000LL;
-+
-+	if (op->data.dir == SPI_MEM_NO_DATA)
-+		ms *= 32; /* prevent we may get 0 for short transfers. */
-+	else
-+		ms *= op->data.nbytes;
-+	ms = div_u64(ms, mem->spi->max_speed_hz);
-+	ms += ms + 1000; /* 1s tolerance */
-+
-+	if (ms > UINT_MAX)
-+		ms = UINT_MAX;
-+
-+	if (!wait_for_completion_timeout(&mdata->spimem_done,
-+					 msecs_to_jiffies(ms))) {
-+		dev_err(mdata->dev, "spi-mem transfer timeout\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_spi_mem_exec_op(struct spi_mem *mem,
-+			       const struct spi_mem_op *op)
-+{
-+	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+	u32 reg_val, nio, tx_size;
-+	char *tx_tmp_buf, *rx_tmp_buf;
-+	int ret = 0;
-+
-+	mdata->use_spimem = true;
-+	reinit_completion(&mdata->spimem_done);
-+
-+	mtk_spi_reset(mdata);
-+	mtk_spi_hw_init(mem->spi->master, mem->spi);
-+	mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz);
-+
-+	reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
-+	/* opcode byte len */
-+	reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
-+	reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
-+
-+	/* addr & dummy byte len */
-+	reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
-+	if (op->addr.nbytes || op->dummy.nbytes)
-+		reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
-+			    SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET;
-+
-+	/* data byte len */
-+	if (op->data.dir == SPI_MEM_NO_DATA) {
-+		reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
-+		writel(0, mdata->base + SPI_CFG1_REG);
-+	} else {
-+		reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
-+		mdata->xfer_len = op->data.nbytes;
-+		mtk_spi_setup_packet(mem->spi->master);
-+	}
-+
-+	if (op->addr.nbytes || op->dummy.nbytes) {
-+		if (op->addr.buswidth == 1 || op->dummy.buswidth == 1)
-+			reg_val |= SPI_CFG3_IPM_XMODE_EN;
-+		else
-+			reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
-+	}
-+
-+	if (op->addr.buswidth == 2 ||
-+	    op->dummy.buswidth == 2 ||
-+	    op->data.buswidth == 2)
-+		nio = 2;
-+	else if (op->addr.buswidth == 4 ||
-+		 op->dummy.buswidth == 4 ||
-+		 op->data.buswidth == 4)
-+		nio = 4;
-+	else
-+		nio = 1;
-+
-+	reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
-+	reg_val |= PIN_MODE_CFG(nio);
-+
-+	reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+	else
-+		reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+	writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+
-+	tx_size = 1 + op->addr.nbytes + op->dummy.nbytes;
-+	if (op->data.dir == SPI_MEM_DATA_OUT)
-+		tx_size += op->data.nbytes;
-+
-+	tx_size = max_t(u32, tx_size, 32);
-+
-+	tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA);
-+	if (!tx_tmp_buf) {
-+		mdata->use_spimem = false;
-+		return -ENOMEM;
-+	}
-+
-+	tx_tmp_buf[0] = op->cmd.opcode;
-+
-+	if (op->addr.nbytes) {
-+		int i;
-+
-+		for (i = 0; i < op->addr.nbytes; i++)
-+			tx_tmp_buf[i + 1] = op->addr.val >>
-+					(8 * (op->addr.nbytes - i - 1));
-+	}
-+
-+	if (op->dummy.nbytes)
-+		memset(tx_tmp_buf + op->addr.nbytes + 1,
-+		       0xff,
-+		       op->dummy.nbytes);
-+
-+	if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
-+		memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1,
-+		       op->data.buf.out,
-+		       op->data.nbytes);
-+
-+	mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf,
-+				       tx_size, DMA_TO_DEVICE);
-+	if (dma_mapping_error(mdata->dev, mdata->tx_dma)) {
-+		ret = -ENOMEM;
-+		goto err_exit;
-+	}
-+
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
-+			rx_tmp_buf = kzalloc(op->data.nbytes,
-+					     GFP_KERNEL | GFP_DMA);
-+			if (!rx_tmp_buf) {
-+				ret = -ENOMEM;
-+				goto unmap_tx_dma;
-+			}
-+		} else {
-+			rx_tmp_buf = op->data.buf.in;
-+		}
-+
-+		mdata->rx_dma = dma_map_single(mdata->dev,
-+					       rx_tmp_buf,
-+					       op->data.nbytes,
-+					       DMA_FROM_DEVICE);
-+		if (dma_mapping_error(mdata->dev, mdata->rx_dma)) {
-+			ret = -ENOMEM;
-+			goto kfree_rx_tmp_buf;
-+		}
-+	}
-+
-+	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	reg_val |= SPI_CMD_TX_DMA;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val |= SPI_CMD_RX_DMA;
-+	writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+	mtk_spi_mem_setup_dma_xfer(mem->spi->master, op);
-+
-+	mtk_spi_enable_transfer(mem->spi->master);
-+
-+	/* Wait for the interrupt. */
-+	ret = mtk_spi_transfer_wait(mem, op);
-+	if (ret)
-+		goto unmap_rx_dma;
-+
-+	/* spi disable dma */
-+	reg_val = readl(mdata->base + SPI_CMD_REG);
-+	reg_val &= ~SPI_CMD_TX_DMA;
-+	if (op->data.dir == SPI_MEM_DATA_IN)
-+		reg_val &= ~SPI_CMD_RX_DMA;
-+	writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+unmap_rx_dma:
-+	if (op->data.dir == SPI_MEM_DATA_IN) {
-+		dma_unmap_single(mdata->dev, mdata->rx_dma,
-+				 op->data.nbytes, DMA_FROM_DEVICE);
-+		if (!IS_ALIGNED((size_t)op->data.buf.in, 4))
-+			memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
-+	}
-+kfree_rx_tmp_buf:
-+	if (op->data.dir == SPI_MEM_DATA_IN &&
-+	    !IS_ALIGNED((size_t)op->data.buf.in, 4))
-+		kfree(rx_tmp_buf);
-+unmap_tx_dma:
-+	dma_unmap_single(mdata->dev, mdata->tx_dma,
-+			 tx_size, DMA_TO_DEVICE);
-+err_exit:
-+	kfree(tx_tmp_buf);
-+	mdata->use_spimem = false;
-+
-+	return ret;
-+}
-+
-+static const struct spi_controller_mem_ops mtk_spi_mem_ops = {
-+	.adjust_op_size = mtk_spi_mem_adjust_op_size,
-+	.supports_op = mtk_spi_mem_supports_op,
-+	.exec_op = mtk_spi_mem_exec_op,
-+};
-+
- static int mtk_spi_probe(struct platform_device *pdev)
- {
- 	struct spi_master *master;
-@@ -739,6 +1103,7 @@ static int mtk_spi_probe(struct platform
- 	master->can_dma = mtk_spi_can_dma;
- 	master->setup = mtk_spi_setup;
- 	master->set_cs_timing = mtk_spi_set_hw_cs_timing;
-+	master->use_gpio_descriptors = true;
- 
- 	of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
- 	if (!of_id) {
-@@ -755,6 +1120,14 @@ static int mtk_spi_probe(struct platform
- 
- 	if (mdata->dev_comp->must_tx)
- 		master->flags = SPI_MASTER_MUST_TX;
-+	if (mdata->dev_comp->ipm_design)
-+		master->mode_bits |= SPI_LOOP;
-+
-+	if (mdata->dev_comp->ipm_design) {
-+		mdata->dev = &pdev->dev;
-+		master->mem_ops = &mtk_spi_mem_ops;
-+		init_completion(&mdata->spimem_done);
-+	}
- 
- 	if (mdata->dev_comp->need_pad_sel) {
- 		mdata->pad_num = of_property_count_u32_elems(
-@@ -831,25 +1204,40 @@ static int mtk_spi_probe(struct platform
- 		goto err_put_master;
- 	}
- 
-+	mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk");
-+	if (IS_ERR(mdata->spi_hclk)) {
-+		ret = PTR_ERR(mdata->spi_hclk);
-+		dev_err(&pdev->dev, "failed to get hclk: %d\n", ret);
-+		goto err_put_master;
-+	}
-+
-+	ret = clk_prepare_enable(mdata->spi_hclk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret);
-+		goto err_put_master;
-+	}
-+
- 	ret = clk_prepare_enable(mdata->spi_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
--		goto err_put_master;
-+		goto err_disable_spi_hclk;
- 	}
- 
- 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
--		clk_disable_unprepare(mdata->spi_clk);
--		goto err_put_master;
-+		goto err_disable_spi_clk;
- 	}
- 
- 	mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_disable(mdata->spi_clk);
--	else
-+		clk_disable(mdata->spi_hclk);
-+	} else {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	pm_runtime_enable(&pdev->dev);
- 
-@@ -862,25 +1250,12 @@ static int mtk_spi_probe(struct platform
- 			goto err_disable_runtime_pm;
- 		}
- 
--		if (!master->cs_gpios && master->num_chipselect > 1) {
-+		if (!master->cs_gpiods && master->num_chipselect > 1) {
- 			dev_err(&pdev->dev,
- 				"cs_gpios not specified and num_chipselect > 1\n");
- 			ret = -EINVAL;
- 			goto err_disable_runtime_pm;
- 		}
--
--		if (master->cs_gpios) {
--			for (i = 0; i < master->num_chipselect; i++) {
--				ret = devm_gpio_request(&pdev->dev,
--							master->cs_gpios[i],
--							dev_name(&pdev->dev));
--				if (ret) {
--					dev_err(&pdev->dev,
--						"can't get CS GPIO %i\n", i);
--					goto err_disable_runtime_pm;
--				}
--			}
--		}
- 	}
- 
- 	if (mdata->dev_comp->dma_ext)
-@@ -902,6 +1277,10 @@ static int mtk_spi_probe(struct platform
- 
- err_disable_runtime_pm:
- 	pm_runtime_disable(&pdev->dev);
-+err_disable_spi_clk:
-+	clk_disable_unprepare(mdata->spi_clk);
-+err_disable_spi_hclk:
-+	clk_disable_unprepare(mdata->spi_hclk);
- err_put_master:
- 	spi_master_put(master);
- 
-@@ -920,8 +1299,10 @@ static int mtk_spi_remove(struct platfor
- 
- 	mtk_spi_reset(mdata);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_unprepare(mdata->spi_clk);
-+		clk_unprepare(mdata->spi_hclk);
-+	}
- 
- 	pm_runtime_put_noidle(&pdev->dev);
- 	pm_runtime_disable(&pdev->dev);
-@@ -940,8 +1321,10 @@ static int mtk_spi_suspend(struct device
- 	if (ret)
- 		return ret;
- 
--	if (!pm_runtime_suspended(dev))
-+	if (!pm_runtime_suspended(dev)) {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return ret;
- }
-@@ -958,11 +1341,20 @@ static int mtk_spi_resume(struct device
- 			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
- 			return ret;
- 		}
-+
-+		ret = clk_prepare_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+			clk_disable_unprepare(mdata->spi_clk);
-+			return ret;
-+		}
- 	}
- 
- 	ret = spi_master_resume(master);
--	if (ret < 0)
-+	if (ret < 0) {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return ret;
- }
-@@ -974,10 +1366,13 @@ static int mtk_spi_runtime_suspend(struc
- 	struct spi_master *master = dev_get_drvdata(dev);
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		clk_disable(mdata->spi_clk);
--	else
-+		clk_disable(mdata->spi_hclk);
-+	} else {
- 		clk_disable_unprepare(mdata->spi_clk);
-+		clk_disable_unprepare(mdata->spi_hclk);
-+	}
- 
- 	return 0;
- }
-@@ -988,13 +1383,31 @@ static int mtk_spi_runtime_resume(struct
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 	int ret;
- 
--	if (mdata->dev_comp->no_need_unprepare)
-+	if (mdata->dev_comp->no_need_unprepare) {
- 		ret = clk_enable(mdata->spi_clk);
--	else
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
-+			return ret;
-+		}
-+		ret = clk_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+			clk_disable(mdata->spi_clk);
-+			return ret;
-+		}
-+	} else {
- 		ret = clk_prepare_enable(mdata->spi_clk);
--	if (ret < 0) {
--		dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
--		return ret;
-+		if (ret < 0) {
-+			dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret);
-+			return ret;
-+		}
-+
-+		ret = clk_prepare_enable(mdata->spi_hclk);
-+		if (ret < 0) {
-+			dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret);
-+			clk_disable_unprepare(mdata->spi_clk);
-+			return ret;
-+		}
- 	}
- 
- 	return 0;
diff --git a/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch b/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch
deleted file mode 100644
index 631eb04092..0000000000
--- a/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch
+++ /dev/null
@@ -1,39 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
- 	  to PCI-E and USB.
- 
-+config COMMON_CLK_MT7981
-+	bool "Clock driver for MediaTek MT7981"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7981 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7981_ETHSYS
-+	bool "Clock driver for MediaTek MT7981 ETHSYS"
-+	depends on COMMON_CLK_MT7981
-+	default COMMON_CLK_MT7981
-+	help
-+	  This driver add support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7981 SoC.
-+
- config COMMON_CLK_MT7986
- 	bool "Clock driver for MediaTek MT7986"
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
diff --git a/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch
deleted file mode 100644
index ae99685df4..0000000000
--- a/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7981
-+	bool "Mediatek MT7981 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT7986
- 	bool "Mediatek MT7986 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
diff --git a/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch
deleted file mode 100644
index cbee45bc1f..0000000000
--- a/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -134,6 +134,13 @@ config PINCTRL_MT7986
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7988
-+	bool "Mediatek MT7988 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- 	bool "Mediatek MT8167 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
-+obj-$(CONFIG_PINCTRL_MT7988)	+= pinctrl-mt7988.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
diff --git a/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch
deleted file mode 100644
index 23a5b7c911..0000000000
--- a/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -233,6 +233,7 @@ struct mtk_pll_data {
- 	u32 pcw_reg;
- 	int pcw_shift;
- 	u32 pcw_chg_reg;
-+	int pcw_chg_shift;
- 	const struct mtk_pll_div_table *div_table;
- 	const char *parent_name;
- 	u32 en_reg;
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct
- 			pll->data->pcw_shift);
- 	val |= pcw << pll->data->pcw_shift;
- 	writel(val, pll->pcw_addr);
--	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
-+	if (pll->data->pcw_chg_shift)
-+		chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
-+	else
-+		chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
- 	writel(chg, pll->pcw_chg_addr);
- 	if (pll->tuner_addr)
- 		writel(val + 1, pll->tuner_addr);
diff --git a/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch
deleted file mode 100644
index bf9146352a..0000000000
--- a/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -378,6 +378,15 @@ config COMMON_CLK_MT7986_ETHSYS
- 	  This driver add support for clocks for Ethernet and SGMII
- 	  required on MediaTek MT7986 SoC.
- 
-+config COMMON_CLK_MT7988
-+	bool "Clock driver for MediaTek MT7988"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7988 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -54,6 +54,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
- obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
diff --git a/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch
deleted file mode 100644
index 56ffa73c00..0000000000
--- a/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 1a7963e9843f6f1e4b02a30926d20b314c03e4df Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sat, 25 Jun 2022 02:10:13 +0800
-Subject: [PATCH] mmc: mediatek: add support for MT7986 SoC
-
-Adding mt7986 own characteristics and of_device_id to have support
-of MT7986 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a
----
- drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -540,6 +540,19 @@ static const struct mtk_mmc_compatible m
- 	.support_64g = false,
- };
- 
-+static const struct mtk_mmc_compatible mt7986_compat = {
-+	.clk_div_bits = 12,
-+	.recheck_sdio_irq = true,
-+	.hs400_tune = false,
-+	.pad_tune_reg = MSDC_PAD_TUNE0,
-+	.async_fifo = true,
-+	.data_tune = true,
-+	.busy_check = true,
-+	.stop_clk_fix = true,
-+	.enhance_rx = true,
-+	.support_64g = true,
-+};
-+
- static const struct mtk_mmc_compatible mt8516_compat = {
- 	.clk_div_bits = 12,
- 	.recheck_sdio_irq = true,
-@@ -584,6 +597,7 @@ static const struct of_device_id msdc_of
- 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
- 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
- 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
-+	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
- 	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
- 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
- 	{ .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
diff --git a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch
deleted file mode 100644
index 6814e5f5e9..0000000000
--- a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch
+++ /dev/null
@@ -1,34 +0,0 @@
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -19,6 +19,7 @@
- #include <linux/string.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-+#include <linux/mtd/mtk_bmt.h>
- 
- static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
- {
-@@ -1343,6 +1344,7 @@ static int spinand_probe(struct spi_mem
- 	if (ret)
- 		return ret;
- 
-+	mtk_bmt_attach(mtd);
- 	ret = mtd_device_register(mtd, NULL, 0);
- 	if (ret)
- 		goto err_spinand_cleanup;
-@@ -1350,6 +1352,7 @@ static int spinand_probe(struct spi_mem
- 	return 0;
- 
- err_spinand_cleanup:
-+	mtk_bmt_detach(mtd);
- 	spinand_cleanup(spinand);
- 
- 	return ret;
-@@ -1368,6 +1371,7 @@ static int spinand_remove(struct spi_mem
- 	if (ret)
- 		return ret;
- 
-+	mtk_bmt_detach(mtd);
- 	spinand_cleanup(spinand);
- 
- 	return 0;
diff --git a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch
deleted file mode 100644
index 9c1a8f284a..0000000000
--- a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -553,6 +553,7 @@
- 		spi-tx-bus-width = <4>;
- 		spi-rx-bus-width = <4>;
- 		nand-ecc-engine = <&snfi>;
-+		mediatek,bmt-v2;
- 
- 		partitions {
- 			compatible = "fixed-partitions";
diff --git a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
deleted file mode 100644
index 6baa32879b..0000000000
--- a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
-From: Davide Fioravanti <pantanastyle@gmail.com>
-Date: Fri, 8 Jan 2021 15:35:24 +0100
-Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
-
-Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
-
-Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
----
- drivers/mtd/nand/spi/Makefile  |  2 +-
- drivers/mtd/nand/spi/core.c    |  1 +
- drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
- include/linux/mtd/spinand.h    |  1 +
- 4 files changed, 79 insertions(+), 1 deletion(-)
- create mode 100644 drivers/mtd/nand/spi/fidelix.c
-
---- a/drivers/mtd/nand/spi/Makefile
-+++ b/drivers/mtd/nand/spi/Makefile
-@@ -1,3 +1,3 @@
- # SPDX-License-Identifier: GPL-2.0
--spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
-+spinand-objs := core.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
- obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -939,6 +939,7 @@ static const struct nand_ops spinand_ops
- 
- static const struct spinand_manufacturer *spinand_manufacturers[] = {
- 	&esmt_c8_spinand_manufacturer,
-+	&fidelix_spinand_manufacturer,
- 	&gigadevice_spinand_manufacturer,
- 	&etron_spinand_manufacturer,
- 	&macronix_spinand_manufacturer,
---- /dev/null
-+++ b/drivers/mtd/nand/spi/fidelix.c
-@@ -0,0 +1,76 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/kernel.h>
-+#include <linux/mtd/spinand.h>
-+
-+#define SPINAND_MFR_FIDELIX		0xE5
-+#define FIDELIX_ECCSR_MASK		0x0F
-+
-+static SPINAND_OP_VARIANTS(read_cache_variants,
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(write_cache_variants,
-+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(update_cache_variants,
-+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
-+
-+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 8;
-+	region->length = 8;
-+
-+	return 0;
-+}
-+
-+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 2;
-+	region->length = 6;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
-+	.ecc = fm35x1ga_ooblayout_ecc,
-+	.free = fm35x1ga_ooblayout_free,
-+};
-+
-+static const struct spinand_info fidelix_spinand_table[] = {
-+	SPINAND_INFO("FM35X1GA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
-+};
-+
-+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
-+};
-+
-+const struct spinand_manufacturer fidelix_spinand_manufacturer = {
-+	.id = SPINAND_MFR_FIDELIX,
-+	.name = "Fidelix",
-+	.chips = fidelix_spinand_table,
-+	.nchips = ARRAY_SIZE(fidelix_spinand_table),
-+	.ops = &fidelix_spinand_manuf_ops,
-+};
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -262,6 +262,7 @@ struct spinand_manufacturer {
- /* SPI NAND manufacturers */
- extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
- extern const struct spinand_manufacturer etron_spinand_manufacturer;
-+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
- extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
- extern const struct spinand_manufacturer macronix_spinand_manufacturer;
- extern const struct spinand_manufacturer micron_spinand_manufacturer;
diff --git a/target/linux/mediatek/patches-5.15/341-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-se.patch b/target/linux/mediatek/patches-5.15/341-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-se.patch
deleted file mode 100644
index 197c9af2b6..0000000000
--- a/target/linux/mediatek/patches-5.15/341-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-se.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-From 9471c6ebf176284108115f60e22a176e70b97c0b Mon Sep 17 00:00:00 2001
-From: Chen Minqiang <ptpt52@gmail.com>
-Date: Thu, 12 Oct 2023 06:51:40 +0800
-Subject: [PATCH] mtd: spinand: winbond: Support for W25MxxGV W25NxxKV series
-
----
- drivers/mtd/nand/spi/winbond.c | 115 +++++++++++++++++++++++++++++++++
- 1 file changed, 115 insertions(+)
-
---- a/drivers/mtd/nand/spi/winbond.c
-+++ b/drivers/mtd/nand/spi/winbond.c
-@@ -15,6 +15,23 @@
- 
- #define WINBOND_CFG_BUF_READ		BIT(3)
- 
-+#define W25N02_N04KV_STATUS_ECC_MASK		(3 << 4)
-+#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS	(0 << 4)
-+#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS	(1 << 4)
-+#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS	(3 << 4)
-+#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR	(2 << 4)
-+
-+#define W25N01_M02GV_STATUS_ECC_MASK		(3 << 4)
-+#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS	(0 << 4)
-+#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS	(1 << 4)
-+#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR	(2 << 4)
-+
-+#define W25N01KV_STATUS_ECC_MASK		(3 << 4)
-+#define W25N01KV_STATUS_ECC_NO_BITFLIPS		(0 << 4)
-+#define W25N01KV_STATUS_ECC_1_3_BITFLIPS	(1 << 4)
-+#define W25N01KV_STATUS_ECC_4_BITFLIPS		(3 << 4)
-+#define W25N01KV_STATUS_ECC_UNCOR_ERROR		(2 << 4)
-+
- static SPINAND_OP_VARIANTS(read_cache_variants,
- 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-@@ -31,6 +48,29 @@ static SPINAND_OP_VARIANTS(update_cache_
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
-+static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	return -ERANGE;
-+}
-+
-+static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 2;
-+	region->length = 14;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = {
-+	.ecc = w25n02kv_n04kv_ooblayout_ecc,
-+	.free = w25n02kv_n04kv_ooblayout_free,
-+};
-+
- static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
- 				  struct mtd_oob_region *region)
- {
-@@ -140,6 +180,58 @@ static int w25n02kv_ecc_get_status(struc
- 	return -EINVAL;
- }
- 
-+static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
-+					u8 status)
-+{
-+	switch (status & W25N01KV_STATUS_ECC_MASK) {
-+	case W25N01KV_STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case W25N01KV_STATUS_ECC_1_3_BITFLIPS:
-+		return 3;
-+
-+	case W25N01KV_STATUS_ECC_4_BITFLIPS:
-+		return 4;
-+
-+	case W25N01KV_STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
-+					u8 status)
-+{
-+	switch (status & W25N02_N04KV_STATUS_ECC_MASK) {
-+	case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS:
-+		return 0;
-+
-+	case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS:
-+		return 3;
-+
-+	case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS:
-+		return 4;
-+
-+	/* W25N02_N04KV_use internal 8bit ECC algorithm.
-+	 * But the ECC strength is 4 bit requried.
-+	 * Return 3 if the bit bit flip count less than 5.
-+	 * Return 4 if the bit bit flip count more than 5 to 8.
-+	*/
-+
-+	case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR:
-+		return -EBADMSG;
-+
-+	default:
-+		break;
-+	}
-+
-+	return -EINVAL;
-+}
-+
- static const struct spinand_info winbond_spinand_table[] = {
- 	SPINAND_INFO("W25M02GV",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
-@@ -151,6 +243,16 @@ static const struct spinand_info winbond
- 		     0,
- 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
- 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
-+	SPINAND_INFO("W25N01KV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
-+				     w25n01kv_ecc_get_status)),
- 	SPINAND_INFO("W25N01GV",
- 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
- 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-@@ -169,6 +271,19 @@ static const struct spinand_info winbond
- 					      &update_cache_variants),
- 		     0,
- 		     SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
-+	/* W25N04KV has 2-die(lun), however, it can select die automatically.
-+	 * Treat it as single die here and double block size.
-+	 */
-+	SPINAND_INFO("W25N04KV",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
-+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
-+		     NAND_ECCREQ(8, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
-+				     w25n02kv_n04kv_ecc_get_status)),
- };
- 
- static int winbond_spinand_init(struct spinand_device *spinand)
diff --git a/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch b/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch
deleted file mode 100644
index 8fad64a570..0000000000
--- a/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From 7a768326fdba542144833b9198a6d0edab52fad2 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:56 +0800
-Subject: [PATCH 01/21] cpufreq: mediatek: Cleanup variables and error handling
- in mtk_cpu_dvfs_info_init()
-
-- Remove several unnecessary varaibles in mtk_cpu_dvfs_info_init().
-- Unify error message format and use dev_err_probe() if possible.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 89 ++++++++++++------------------
- 1 file changed, 34 insertions(+), 55 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -302,96 +302,75 @@ static int mtk_cpufreq_set_target(struct
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- 	struct device *cpu_dev;
--	struct regulator *proc_reg = ERR_PTR(-ENODEV);
--	struct regulator *sram_reg = ERR_PTR(-ENODEV);
--	struct clk *cpu_clk = ERR_PTR(-ENODEV);
--	struct clk *inter_clk = ERR_PTR(-ENODEV);
- 	struct dev_pm_opp *opp;
- 	unsigned long rate;
- 	int ret;
- 
- 	cpu_dev = get_cpu_device(cpu);
- 	if (!cpu_dev) {
--		pr_err("failed to get cpu%d device\n", cpu);
-+		dev_err(cpu_dev, "failed to get cpu%d device\n", cpu);
- 		return -ENODEV;
- 	}
-+	info->cpu_dev = cpu_dev;
- 
--	cpu_clk = clk_get(cpu_dev, "cpu");
--	if (IS_ERR(cpu_clk)) {
--		if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
--			pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
--		else
--			pr_err("failed to get cpu clk for cpu%d\n", cpu);
--
--		ret = PTR_ERR(cpu_clk);
--		return ret;
--	}
--
--	inter_clk = clk_get(cpu_dev, "intermediate");
--	if (IS_ERR(inter_clk)) {
--		if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
--			pr_warn("intermediate clk for cpu%d not ready, retry.\n",
--				cpu);
--		else
--			pr_err("failed to get intermediate clk for cpu%d\n",
--			       cpu);
-+	info->cpu_clk = clk_get(cpu_dev, "cpu");
-+	if (IS_ERR(info->cpu_clk)) {
-+		ret = PTR_ERR(info->cpu_clk);
-+		return dev_err_probe(cpu_dev, ret,
-+				     "cpu%d: failed to get cpu clk\n", cpu);
-+	}
- 
--		ret = PTR_ERR(inter_clk);
-+	info->inter_clk = clk_get(cpu_dev, "intermediate");
-+	if (IS_ERR(info->inter_clk)) {
-+		ret = PTR_ERR(info->inter_clk);
-+		dev_err_probe(cpu_dev, ret,
-+			      "cpu%d: failed to get intermediate clk\n", cpu);
- 		goto out_free_resources;
- 	}
- 
--	proc_reg = regulator_get_optional(cpu_dev, "proc");
--	if (IS_ERR(proc_reg)) {
--		if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
--			pr_warn("proc regulator for cpu%d not ready, retry.\n",
--				cpu);
--		else
--			pr_err("failed to get proc regulator for cpu%d\n",
--			       cpu);
--
--		ret = PTR_ERR(proc_reg);
-+	info->proc_reg = regulator_get_optional(cpu_dev, "proc");
-+	if (IS_ERR(info->proc_reg)) {
-+		ret = PTR_ERR(info->proc_reg);
-+		dev_err_probe(cpu_dev, ret,
-+			      "cpu%d: failed to get proc regulator\n", cpu);
- 		goto out_free_resources;
- 	}
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
--	sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+	info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+	if (IS_ERR(info->sram_reg))
-+		info->sram_reg = NULL;
- 
- 	/* Get OPP-sharing information from "operating-points-v2" bindings */
- 	ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
- 	if (ret) {
--		pr_err("failed to get OPP-sharing information for cpu%d\n",
--		       cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to get OPP-sharing information\n", cpu);
- 		goto out_free_resources;
- 	}
- 
- 	ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
- 	if (ret) {
--		pr_warn("no OPP table for cpu%d\n", cpu);
-+		dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
- 		goto out_free_resources;
- 	}
- 
- 	/* Search a safe voltage for intermediate frequency. */
--	rate = clk_get_rate(inter_clk);
-+	rate = clk_get_rate(info->inter_clk);
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
- 	if (IS_ERR(opp)) {
--		pr_err("failed to get intermediate opp for cpu%d\n", cpu);
-+		dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
- 		ret = PTR_ERR(opp);
- 		goto out_free_opp_table;
- 	}
- 	info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
- 
--	info->cpu_dev = cpu_dev;
--	info->proc_reg = proc_reg;
--	info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
--	info->cpu_clk = cpu_clk;
--	info->inter_clk = inter_clk;
--
- 	/*
- 	 * If SRAM regulator is present, software "voltage tracking" is needed
- 	 * for this CPU power domain.
- 	 */
--	info->need_voltage_tracking = !IS_ERR(sram_reg);
-+	info->need_voltage_tracking = (info->sram_reg != NULL);
- 
- 	return 0;
- 
-@@ -399,14 +378,14 @@ out_free_opp_table:
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 
- out_free_resources:
--	if (!IS_ERR(proc_reg))
--		regulator_put(proc_reg);
--	if (!IS_ERR(sram_reg))
--		regulator_put(sram_reg);
--	if (!IS_ERR(cpu_clk))
--		clk_put(cpu_clk);
--	if (!IS_ERR(inter_clk))
--		clk_put(inter_clk);
-+	if (!IS_ERR(info->proc_reg))
-+		regulator_put(info->proc_reg);
-+	if (!IS_ERR(info->sram_reg))
-+		regulator_put(info->sram_reg);
-+	if (!IS_ERR(info->cpu_clk))
-+		clk_put(info->cpu_clk);
-+	if (!IS_ERR(info->inter_clk))
-+		clk_put(info->inter_clk);
- 
- 	return ret;
- }
diff --git a/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch b/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch
deleted file mode 100644
index eebeeb0902..0000000000
--- a/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 756104b856d4bc3121420af3ced342f5fc2b2123 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:57 +0800
-Subject: [PATCH 02/21] cpufreq: mediatek: Remove unused headers
-
-Remove unused headers.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -13,8 +13,6 @@
- #include <linux/platform_device.h>
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
--#include <linux/slab.h>
--#include <linux/thermal.h>
- 
- #define MIN_VOLT_SHIFT		(100000)
- #define MAX_VOLT_SHIFT		(200000)
diff --git a/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch b/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch
deleted file mode 100644
index c97d5fc3d9..0000000000
--- a/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 342d5545e9f40496db9ae0d31c2427dd5f369a43 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:58 +0800
-Subject: [PATCH 03/21] cpufreq: mediatek: Enable clocks and regulators
-
-We need to enable regulators so that the max and min requested values will
-be recorded.
-The intermediate clock is not always enabled by CCF in different projects,
-so we should enable it in the cpufreq driver.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 50 +++++++++++++++++++++++++++---
- 1 file changed, 45 insertions(+), 5 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -334,10 +334,23 @@ static int mtk_cpu_dvfs_info_init(struct
- 		goto out_free_resources;
- 	}
- 
-+	ret = regulator_enable(info->proc_reg);
-+	if (ret) {
-+		dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
-+		goto out_free_resources;
-+	}
-+
- 	/* Both presence and absence of sram regulator are valid cases. */
- 	info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
- 	if (IS_ERR(info->sram_reg))
- 		info->sram_reg = NULL;
-+	else {
-+		ret = regulator_enable(info->sram_reg);
-+		if (ret) {
-+			dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
-+			goto out_free_resources;
-+		}
-+	}
- 
- 	/* Get OPP-sharing information from "operating-points-v2" bindings */
- 	ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
-@@ -353,13 +366,21 @@ static int mtk_cpu_dvfs_info_init(struct
- 		goto out_free_resources;
- 	}
- 
-+	ret = clk_prepare_enable(info->cpu_clk);
-+	if (ret)
-+		goto out_free_opp_table;
-+
-+	ret = clk_prepare_enable(info->inter_clk);
-+	if (ret)
-+		goto out_disable_mux_clock;
-+
- 	/* Search a safe voltage for intermediate frequency. */
- 	rate = clk_get_rate(info->inter_clk);
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
- 	if (IS_ERR(opp)) {
- 		dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
- 		ret = PTR_ERR(opp);
--		goto out_free_opp_table;
-+		goto out_disable_inter_clock;
- 	}
- 	info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
-@@ -372,10 +393,21 @@ static int mtk_cpu_dvfs_info_init(struct
- 
- 	return 0;
- 
-+out_disable_inter_clock:
-+	clk_disable_unprepare(info->inter_clk);
-+
-+out_disable_mux_clock:
-+	clk_disable_unprepare(info->cpu_clk);
-+
- out_free_opp_table:
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 
- out_free_resources:
-+	if (regulator_is_enabled(info->proc_reg))
-+		regulator_disable(info->proc_reg);
-+	if (info->sram_reg && regulator_is_enabled(info->sram_reg))
-+		regulator_disable(info->sram_reg);
-+
- 	if (!IS_ERR(info->proc_reg))
- 		regulator_put(info->proc_reg);
- 	if (!IS_ERR(info->sram_reg))
-@@ -390,14 +422,22 @@ out_free_resources:
- 
- static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
- {
--	if (!IS_ERR(info->proc_reg))
-+	if (!IS_ERR(info->proc_reg)) {
-+		regulator_disable(info->proc_reg);
- 		regulator_put(info->proc_reg);
--	if (!IS_ERR(info->sram_reg))
-+	}
-+	if (!IS_ERR(info->sram_reg)) {
-+		regulator_disable(info->sram_reg);
- 		regulator_put(info->sram_reg);
--	if (!IS_ERR(info->cpu_clk))
-+	}
-+	if (!IS_ERR(info->cpu_clk)) {
-+		clk_disable_unprepare(info->cpu_clk);
- 		clk_put(info->cpu_clk);
--	if (!IS_ERR(info->inter_clk))
-+	}
-+	if (!IS_ERR(info->inter_clk)) {
-+		clk_disable_unprepare(info->inter_clk);
- 		clk_put(info->inter_clk);
-+	}
- 
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- }
diff --git a/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch b/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch
deleted file mode 100644
index 18e1da728a..0000000000
--- a/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-From a02e2b359141035d2d6999940bc1b9f83ec88587 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:27 +0800
-Subject: [PATCH 04/21] cpufreq: mediatek: Use device print to show logs
-
-- Replace pr_* with dev_* to show logs.
-- Remove usage of __func__.
-
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 54 ++++++++++++++++--------------
- 1 file changed, 28 insertions(+), 26 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -67,7 +67,8 @@ static int mtk_cpufreq_voltage_tracking(
- 
- 	old_vproc = regulator_get_voltage(proc_reg);
- 	if (old_vproc < 0) {
--		pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
-+		dev_err(info->cpu_dev,
-+			"invalid Vproc value: %d\n", old_vproc);
- 		return old_vproc;
- 	}
- 	/* Vsram should not exceed the maximum allowed voltage of SoC. */
-@@ -83,14 +84,14 @@ static int mtk_cpufreq_voltage_tracking(
- 		do {
- 			old_vsram = regulator_get_voltage(sram_reg);
- 			if (old_vsram < 0) {
--				pr_err("%s: invalid Vsram value: %d\n",
--				       __func__, old_vsram);
-+				dev_err(info->cpu_dev,
-+					"invalid Vsram value: %d\n", old_vsram);
- 				return old_vsram;
- 			}
- 			old_vproc = regulator_get_voltage(proc_reg);
- 			if (old_vproc < 0) {
--				pr_err("%s: invalid Vproc value: %d\n",
--				       __func__, old_vproc);
-+				dev_err(info->cpu_dev,
-+					"invalid Vproc value: %d\n", old_vproc);
- 				return old_vproc;
- 			}
- 
-@@ -138,14 +139,14 @@ static int mtk_cpufreq_voltage_tracking(
- 		do {
- 			old_vproc = regulator_get_voltage(proc_reg);
- 			if (old_vproc < 0) {
--				pr_err("%s: invalid Vproc value: %d\n",
--				       __func__, old_vproc);
-+				dev_err(info->cpu_dev,
-+					"invalid Vproc value: %d\n", old_vproc);
- 				return old_vproc;
- 			}
- 			old_vsram = regulator_get_voltage(sram_reg);
- 			if (old_vsram < 0) {
--				pr_err("%s: invalid Vsram value: %d\n",
--				       __func__, old_vsram);
-+				dev_err(info->cpu_dev,
-+					"invalid Vsram value: %d\n", old_vsram);
- 				return old_vsram;
- 			}
- 
-@@ -216,7 +217,7 @@ static int mtk_cpufreq_set_target(struct
- 	old_freq_hz = clk_get_rate(cpu_clk);
- 	old_vproc = regulator_get_voltage(info->proc_reg);
- 	if (old_vproc < 0) {
--		pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
-+		dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc);
- 		return old_vproc;
- 	}
- 
-@@ -224,8 +225,8 @@ static int mtk_cpufreq_set_target(struct
- 
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
- 	if (IS_ERR(opp)) {
--		pr_err("cpu%d: failed to find OPP for %ld\n",
--		       policy->cpu, freq_hz);
-+		dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
-+			policy->cpu, freq_hz);
- 		return PTR_ERR(opp);
- 	}
- 	vproc = dev_pm_opp_get_voltage(opp);
-@@ -239,8 +240,8 @@ static int mtk_cpufreq_set_target(struct
- 	if (old_vproc < target_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, target_vproc);
- 		if (ret) {
--			pr_err("cpu%d: failed to scale up voltage!\n",
--			       policy->cpu);
-+			dev_err(cpu_dev,
-+				"cpu%d: failed to scale up voltage!\n", policy->cpu);
- 			mtk_cpufreq_set_voltage(info, old_vproc);
- 			return ret;
- 		}
-@@ -249,8 +250,8 @@ static int mtk_cpufreq_set_target(struct
- 	/* Reparent the CPU clock to intermediate clock. */
- 	ret = clk_set_parent(cpu_clk, info->inter_clk);
- 	if (ret) {
--		pr_err("cpu%d: failed to re-parent cpu clock!\n",
--		       policy->cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, old_vproc);
- 		WARN_ON(1);
- 		return ret;
-@@ -259,8 +260,8 @@ static int mtk_cpufreq_set_target(struct
- 	/* Set the original PLL to target rate. */
- 	ret = clk_set_rate(armpll, freq_hz);
- 	if (ret) {
--		pr_err("cpu%d: failed to scale cpu clock rate!\n",
--		       policy->cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- 		clk_set_parent(cpu_clk, armpll);
- 		mtk_cpufreq_set_voltage(info, old_vproc);
- 		return ret;
-@@ -269,8 +270,8 @@ static int mtk_cpufreq_set_target(struct
- 	/* Set parent of CPU clock back to the original PLL. */
- 	ret = clk_set_parent(cpu_clk, armpll);
- 	if (ret) {
--		pr_err("cpu%d: failed to re-parent cpu clock!\n",
--		       policy->cpu);
-+		dev_err(cpu_dev,
-+			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, inter_vproc);
- 		WARN_ON(1);
- 		return ret;
-@@ -283,8 +284,8 @@ static int mtk_cpufreq_set_target(struct
- 	if (vproc < inter_vproc || vproc < old_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, vproc);
- 		if (ret) {
--			pr_err("cpu%d: failed to scale down voltage!\n",
--			       policy->cpu);
-+			dev_err(cpu_dev,
-+				"cpu%d: failed to scale down voltage!\n", policy->cpu);
- 			clk_set_parent(cpu_clk, info->inter_clk);
- 			clk_set_rate(armpll, old_freq_hz);
- 			clk_set_parent(cpu_clk, armpll);
-@@ -450,15 +451,16 @@ static int mtk_cpufreq_init(struct cpufr
- 
- 	info = mtk_cpu_dvfs_info_lookup(policy->cpu);
- 	if (!info) {
--		pr_err("dvfs info for cpu%d is not initialized.\n",
--		       policy->cpu);
-+		dev_err(info->cpu_dev,
-+			"dvfs info for cpu%d is not initialized.\n", policy->cpu);
- 		return -EINVAL;
- 	}
- 
- 	ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
- 	if (ret) {
--		pr_err("failed to init cpufreq table for cpu%d: %d\n",
--		       policy->cpu, ret);
-+		dev_err(info->cpu_dev,
-+			"failed to init cpufreq table for cpu%d: %d\n",
-+			policy->cpu, ret);
- 		return ret;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch b/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch
deleted file mode 100644
index 8506f4e477..0000000000
--- a/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From 35832d9f9c5c1da01420d962dc56e7e61d104829 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:28 +0800
-Subject: [PATCH 05/21] cpufreq: mediatek: Replace old_* with pre_*
-
-To make driver more readable, replace old_* with pre_*.
-
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++---------------
- 1 file changed, 42 insertions(+), 42 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -63,18 +63,18 @@ static int mtk_cpufreq_voltage_tracking(
- {
- 	struct regulator *proc_reg = info->proc_reg;
- 	struct regulator *sram_reg = info->sram_reg;
--	int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
-+	int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
- 
--	old_vproc = regulator_get_voltage(proc_reg);
--	if (old_vproc < 0) {
-+	pre_vproc = regulator_get_voltage(proc_reg);
-+	if (pre_vproc < 0) {
- 		dev_err(info->cpu_dev,
--			"invalid Vproc value: %d\n", old_vproc);
--		return old_vproc;
-+			"invalid Vproc value: %d\n", pre_vproc);
-+		return pre_vproc;
- 	}
- 	/* Vsram should not exceed the maximum allowed voltage of SoC. */
- 	new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
- 
--	if (old_vproc < new_vproc) {
-+	if (pre_vproc < new_vproc) {
- 		/*
- 		 * When scaling up voltages, Vsram and Vproc scale up step
- 		 * by step. At each step, set Vsram to (Vproc + 200mV) first,
-@@ -82,20 +82,20 @@ static int mtk_cpufreq_voltage_tracking(
- 		 * Keep doing it until Vsram and Vproc hit target voltages.
- 		 */
- 		do {
--			old_vsram = regulator_get_voltage(sram_reg);
--			if (old_vsram < 0) {
-+			pre_vsram = regulator_get_voltage(sram_reg);
-+			if (pre_vsram < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", old_vsram);
--				return old_vsram;
-+					"invalid Vsram value: %d\n", pre_vsram);
-+				return pre_vsram;
- 			}
--			old_vproc = regulator_get_voltage(proc_reg);
--			if (old_vproc < 0) {
-+			pre_vproc = regulator_get_voltage(proc_reg);
-+			if (pre_vproc < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", old_vproc);
--				return old_vproc;
-+					"invalid Vproc value: %d\n", pre_vproc);
-+				return pre_vproc;
- 			}
- 
--			vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
-+			vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
- 
- 			if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- 				vsram = MAX_VOLT_LIMIT;
-@@ -124,12 +124,12 @@ static int mtk_cpufreq_voltage_tracking(
- 			ret = regulator_set_voltage(proc_reg, vproc,
- 						    vproc + VOLT_TOL);
- 			if (ret) {
--				regulator_set_voltage(sram_reg, old_vsram,
--						      old_vsram);
-+				regulator_set_voltage(sram_reg, pre_vsram,
-+						      pre_vsram);
- 				return ret;
- 			}
- 		} while (vproc < new_vproc || vsram < new_vsram);
--	} else if (old_vproc > new_vproc) {
-+	} else if (pre_vproc > new_vproc) {
- 		/*
- 		 * When scaling down voltages, Vsram and Vproc scale down step
- 		 * by step. At each step, set Vproc to (Vsram - 200mV) first,
-@@ -137,20 +137,20 @@ static int mtk_cpufreq_voltage_tracking(
- 		 * Keep doing it until Vsram and Vproc hit target voltages.
- 		 */
- 		do {
--			old_vproc = regulator_get_voltage(proc_reg);
--			if (old_vproc < 0) {
-+			pre_vproc = regulator_get_voltage(proc_reg);
-+			if (pre_vproc < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", old_vproc);
--				return old_vproc;
-+					"invalid Vproc value: %d\n", pre_vproc);
-+				return pre_vproc;
- 			}
--			old_vsram = regulator_get_voltage(sram_reg);
--			if (old_vsram < 0) {
-+			pre_vsram = regulator_get_voltage(sram_reg);
-+			if (pre_vsram < 0) {
- 				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", old_vsram);
--				return old_vsram;
-+					"invalid Vsram value: %d\n", pre_vsram);
-+				return pre_vsram;
- 			}
- 
--			vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
-+			vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
- 			ret = regulator_set_voltage(proc_reg, vproc,
- 						    vproc + VOLT_TOL);
- 			if (ret)
-@@ -180,8 +180,8 @@ static int mtk_cpufreq_voltage_tracking(
- 			}
- 
- 			if (ret) {
--				regulator_set_voltage(proc_reg, old_vproc,
--						      old_vproc);
-+				regulator_set_voltage(proc_reg, pre_vproc,
-+						      pre_vproc);
- 				return ret;
- 			}
- 		} while (vproc > new_vproc + VOLT_TOL ||
-@@ -209,16 +209,16 @@ static int mtk_cpufreq_set_target(struct
- 	struct mtk_cpu_dvfs_info *info = policy->driver_data;
- 	struct device *cpu_dev = info->cpu_dev;
- 	struct dev_pm_opp *opp;
--	long freq_hz, old_freq_hz;
--	int vproc, old_vproc, inter_vproc, target_vproc, ret;
-+	long freq_hz, pre_freq_hz;
-+	int vproc, pre_vproc, inter_vproc, target_vproc, ret;
- 
- 	inter_vproc = info->intermediate_voltage;
- 
--	old_freq_hz = clk_get_rate(cpu_clk);
--	old_vproc = regulator_get_voltage(info->proc_reg);
--	if (old_vproc < 0) {
--		dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc);
--		return old_vproc;
-+	pre_freq_hz = clk_get_rate(cpu_clk);
-+	pre_vproc = regulator_get_voltage(info->proc_reg);
-+	if (pre_vproc < 0) {
-+		dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
-+		return pre_vproc;
- 	}
- 
- 	freq_hz = freq_table[index].frequency * 1000;
-@@ -237,12 +237,12 @@ static int mtk_cpufreq_set_target(struct
- 	 * current voltage, scale up voltage first.
- 	 */
- 	target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
--	if (old_vproc < target_vproc) {
-+	if (pre_vproc < target_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, target_vproc);
- 		if (ret) {
- 			dev_err(cpu_dev,
- 				"cpu%d: failed to scale up voltage!\n", policy->cpu);
--			mtk_cpufreq_set_voltage(info, old_vproc);
-+			mtk_cpufreq_set_voltage(info, pre_vproc);
- 			return ret;
- 		}
- 	}
-@@ -252,7 +252,7 @@ static int mtk_cpufreq_set_target(struct
- 	if (ret) {
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
--		mtk_cpufreq_set_voltage(info, old_vproc);
-+		mtk_cpufreq_set_voltage(info, pre_vproc);
- 		WARN_ON(1);
- 		return ret;
- 	}
-@@ -263,7 +263,7 @@ static int mtk_cpufreq_set_target(struct
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- 		clk_set_parent(cpu_clk, armpll);
--		mtk_cpufreq_set_voltage(info, old_vproc);
-+		mtk_cpufreq_set_voltage(info, pre_vproc);
- 		return ret;
- 	}
- 
-@@ -281,13 +281,13 @@ static int mtk_cpufreq_set_target(struct
- 	 * If the new voltage is lower than the intermediate voltage or the
- 	 * original voltage, scale down to the new voltage.
- 	 */
--	if (vproc < inter_vproc || vproc < old_vproc) {
-+	if (vproc < inter_vproc || vproc < pre_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, vproc);
- 		if (ret) {
- 			dev_err(cpu_dev,
- 				"cpu%d: failed to scale down voltage!\n", policy->cpu);
- 			clk_set_parent(cpu_clk, info->inter_clk);
--			clk_set_rate(armpll, old_freq_hz);
-+			clk_set_rate(armpll, pre_freq_hz);
- 			clk_set_parent(cpu_clk, armpll);
- 			return ret;
- 		}
diff --git a/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch b/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch
deleted file mode 100644
index 94e6617d26..0000000000
--- a/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 34737eb8d0daa0d4183f10286a2f55d8788066bc Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:29 +0800
-Subject: [PATCH 06/21] cpufreq: mediatek: Record previous target vproc value
-
-We found the buck voltage may not be exactly the same with what we set
-because CPU may share the same buck with other module.
-Therefore, we need to record the previous desired value instead of reading
-it from regulators.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -40,6 +40,7 @@ struct mtk_cpu_dvfs_info {
- 	struct list_head list_head;
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
-+	int pre_vproc;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -193,11 +194,17 @@ static int mtk_cpufreq_voltage_tracking(
- 
- static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
- {
-+	int ret;
-+
- 	if (info->need_voltage_tracking)
--		return mtk_cpufreq_voltage_tracking(info, vproc);
-+		ret = mtk_cpufreq_voltage_tracking(info, vproc);
- 	else
--		return regulator_set_voltage(info->proc_reg, vproc,
--					     vproc + VOLT_TOL);
-+		ret = regulator_set_voltage(info->proc_reg, vproc,
-+					    MAX_VOLT_LIMIT);
-+	if (!ret)
-+		info->pre_vproc = vproc;
-+
-+	return ret;
- }
- 
- static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
-@@ -215,7 +222,12 @@ static int mtk_cpufreq_set_target(struct
- 	inter_vproc = info->intermediate_voltage;
- 
- 	pre_freq_hz = clk_get_rate(cpu_clk);
--	pre_vproc = regulator_get_voltage(info->proc_reg);
-+
-+	if (unlikely(info->pre_vproc <= 0))
-+		pre_vproc = regulator_get_voltage(info->proc_reg);
-+	else
-+		pre_vproc = info->pre_vproc;
-+
- 	if (pre_vproc < 0) {
- 		dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
- 		return pre_vproc;
diff --git a/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch b/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch
deleted file mode 100644
index 4b74873b15..0000000000
--- a/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f6114c2bc563a8050e9dc874ad87e1448865f031 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:33 +0800
-Subject: [PATCH 07/21] cpufreq: mediatek: Make sram regulator optional
-
-For some MediaTek SoCs, like MT8186, it's possible that the sram regulator
-is shared between CPU and CCI.
-We hope regulator framework can return error for error handling rather
-than a dummy handler from regulator_get api.
-Therefore, we choose to use regulator_get_optional.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -354,7 +354,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 	}
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
--	info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+	info->sram_reg = regulator_get_optional(cpu_dev, "sram");
- 	if (IS_ERR(info->sram_reg))
- 		info->sram_reg = NULL;
- 	else {
diff --git a/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch b/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch
deleted file mode 100644
index f2f572a753..0000000000
--- a/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From fa7030d8ad4638acfd9e0fac84a20716d031dc95 Mon Sep 17 00:00:00 2001
-From: Wan Jiabing <wanjiabing@vivo.com>
-Date: Tue, 26 Apr 2022 19:17:14 +0800
-Subject: [PATCH 08/21] cpufreq: mediatek: Fix NULL pointer dereference in
- mediatek-cpufreq
-
-Fix following coccicheck error:
-drivers/cpufreq/mediatek-cpufreq.c:464:16-23: ERROR: info is NULL but dereferenced.
-
-Use pr_err instead of dev_err to avoid dereferring a NULL pointer.
-
-Fixes: f52b16ba9fe4 ("cpufreq: mediatek: Use device print to show logs")
-Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -463,8 +463,8 @@ static int mtk_cpufreq_init(struct cpufr
- 
- 	info = mtk_cpu_dvfs_info_lookup(policy->cpu);
- 	if (!info) {
--		dev_err(info->cpu_dev,
--			"dvfs info for cpu%d is not initialized.\n", policy->cpu);
-+		pr_err("dvfs info for cpu%d is not initialized.\n",
-+			policy->cpu);
- 		return -EINVAL;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch b/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch
deleted file mode 100644
index 23b319648d..0000000000
--- a/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch
+++ /dev/null
@@ -1,227 +0,0 @@
-From be2354b064e6bafbbad599ae2e10569ba4f7d5a6 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:19 +0800
-Subject: [PATCH 09/21] cpufreq: mediatek: Move voltage limits to platform data
-
-Voltages and shifts are defined as macros originally.
-There are different requirements of these values for each MediaTek SoCs.
-Therefore, we add the platform data and move these values into it.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
- 1 file changed, 58 insertions(+), 26 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -10,15 +10,21 @@
- #include <linux/cpumask.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/of_platform.h>
- #include <linux/platform_device.h>
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
- 
--#define MIN_VOLT_SHIFT		(100000)
--#define MAX_VOLT_SHIFT		(200000)
--#define MAX_VOLT_LIMIT		(1150000)
- #define VOLT_TOL		(10000)
- 
-+struct mtk_cpufreq_platform_data {
-+	int min_volt_shift;
-+	int max_volt_shift;
-+	int proc_max_volt;
-+	int sram_min_volt;
-+	int sram_max_volt;
-+};
-+
- /*
-  * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
-  * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
-@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
- 	int pre_vproc;
-+	const struct mtk_cpufreq_platform_data *soc_data;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu
- static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
- 					int new_vproc)
- {
-+	const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
- 	struct regulator *proc_reg = info->proc_reg;
- 	struct regulator *sram_reg = info->sram_reg;
- 	int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
-@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking(
- 		return pre_vproc;
- 	}
- 	/* Vsram should not exceed the maximum allowed voltage of SoC. */
--	new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
-+	new_vsram = min(new_vproc + soc_data->min_volt_shift,
-+			soc_data->sram_max_volt);
- 
- 	if (pre_vproc < new_vproc) {
- 		/*
-@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking(
- 				return pre_vproc;
- 			}
- 
--			vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
-+			vsram = min(new_vsram,
-+				    pre_vproc + soc_data->min_volt_shift);
- 
--			if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
--				vsram = MAX_VOLT_LIMIT;
-+			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-+				vsram = soc_data->sram_max_volt;
- 
- 				/*
- 				 * If the target Vsram hits the maximum voltage,
-@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking(
- 				ret = regulator_set_voltage(sram_reg, vsram,
- 							    vsram + VOLT_TOL);
- 
--				vproc = vsram - MIN_VOLT_SHIFT;
-+				vproc = vsram - soc_data->min_volt_shift;
- 			}
- 			if (ret)
- 				return ret;
-@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking(
- 				return pre_vsram;
- 			}
- 
--			vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
-+			vproc = max(new_vproc,
-+				    pre_vsram - soc_data->max_volt_shift);
- 			ret = regulator_set_voltage(proc_reg, vproc,
- 						    vproc + VOLT_TOL);
- 			if (ret)
-@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking(
- 			if (vproc == new_vproc)
- 				vsram = new_vsram;
- 			else
--				vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
-+				vsram = max(new_vsram,
-+					    vproc + soc_data->min_volt_shift);
- 
--			if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
--				vsram = MAX_VOLT_LIMIT;
-+			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-+				vsram = soc_data->sram_max_volt;
- 
- 				/*
- 				 * If the target Vsram hits the maximum voltage,
-@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking(
- 
- static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
- {
-+	const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
- 	int ret;
- 
- 	if (info->need_voltage_tracking)
- 		ret = mtk_cpufreq_voltage_tracking(info, vproc);
- 	else
- 		ret = regulator_set_voltage(info->proc_reg, vproc,
--					    MAX_VOLT_LIMIT);
-+					    soc_data->proc_max_volt);
- 	if (!ret)
- 		info->pre_vproc = vproc;
- 
-@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq
- 
- static int mtk_cpufreq_probe(struct platform_device *pdev)
- {
-+	const struct mtk_cpufreq_platform_data *data;
- 	struct mtk_cpu_dvfs_info *info, *tmp;
- 	int cpu, ret;
- 
-+	data = dev_get_platdata(&pdev->dev);
-+	if (!data) {
-+		dev_err(&pdev->dev,
-+			"failed to get mtk cpufreq platform data\n");
-+		return -ENODEV;
-+	}
-+
- 	for_each_possible_cpu(cpu) {
- 		info = mtk_cpu_dvfs_info_lookup(cpu);
- 		if (info)
-@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct plat
- 			goto release_dvfs_info_list;
- 		}
- 
-+		info->soc_data = data;
- 		ret = mtk_cpu_dvfs_info_init(info, cpu);
- 		if (ret) {
- 			dev_err(&pdev->dev,
-@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufre
- 	.probe		= mtk_cpufreq_probe,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1150000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1150000,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
--	{ .compatible = "mediatek,mt2701", },
--	{ .compatible = "mediatek,mt2712", },
--	{ .compatible = "mediatek,mt7622", },
--	{ .compatible = "mediatek,mt7623", },
--	{ .compatible = "mediatek,mt8167", },
--	{ .compatible = "mediatek,mt817x", },
--	{ .compatible = "mediatek,mt8173", },
--	{ .compatible = "mediatek,mt8176", },
--	{ .compatible = "mediatek,mt8183", },
--	{ .compatible = "mediatek,mt8365", },
--	{ .compatible = "mediatek,mt8516", },
--
-+	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
-@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_ini
- {
- 	struct device_node *np;
- 	const struct of_device_id *match;
-+	const struct mtk_cpufreq_platform_data *data;
- 	int err;
- 
- 	np = of_find_node_by_path("/");
-@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_ini
- 		pr_debug("Machine is not compatible with mtk-cpufreq\n");
- 		return -ENODEV;
- 	}
-+	data = match->data;
- 
- 	err = platform_driver_register(&mtk_cpufreq_platdrv);
- 	if (err)
-@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_ini
- 	 * and the device registration codes are put here to handle defer
- 	 * probing.
- 	 */
--	cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
-+	cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
-+						     data, sizeof(*data));
- 	if (IS_ERR(cpufreq_pdev)) {
- 		pr_err("failed to register mtk-cpufreq platform device\n");
- 		platform_driver_unregister(&mtk_cpufreq_platdrv);
diff --git a/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch b/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch
deleted file mode 100644
index 0ba9471ffa..0000000000
--- a/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch
+++ /dev/null
@@ -1,255 +0,0 @@
-From 944b041c91f1e1cd762c39c1222f078550149486 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Thu, 5 May 2022 19:52:20 +0800
-Subject: [PATCH 10/21] cpufreq: mediatek: Refine
- mtk_cpufreq_voltage_tracking()
-
-Because the difference of sram and proc should in a range of min_volt_shift
-and max_volt_shift. We need to adjust the sram and proc step by step.
-
-We replace VOLT_TOL (voltage tolerance) with the platform data and update the
-logic to determine the voltage boundary and invoking regulator_set_voltage.
-
-- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary
-  of sram regulator.
-- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the
-  voltage boundary of vproc regulator.
-
-Moreover, to prevent infinite loop when tracking voltage, we calculate the
-maximum value for each platform data.
-We assume min voltage is 0 and tracking target voltage using
-min_volt_shift for each iteration.
-The retry_max is 3 times of expeted iteration count.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++-------------------
- 1 file changed, 51 insertions(+), 96 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -8,6 +8,7 @@
- #include <linux/cpu.h>
- #include <linux/cpufreq.h>
- #include <linux/cpumask.h>
-+#include <linux/minmax.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_platform.h>
-@@ -15,8 +16,6 @@
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
- 
--#define VOLT_TOL		(10000)
--
- struct mtk_cpufreq_platform_data {
- 	int min_volt_shift;
- 	int max_volt_shift;
-@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- 	bool need_voltage_tracking;
- 	int pre_vproc;
- 	const struct mtk_cpufreq_platform_data *soc_data;
-+	int vtrack_max;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking(
- 	struct regulator *proc_reg = info->proc_reg;
- 	struct regulator *sram_reg = info->sram_reg;
- 	int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
-+	int retry = info->vtrack_max;
- 
- 	pre_vproc = regulator_get_voltage(proc_reg);
- 	if (pre_vproc < 0) {
-@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking(
- 			"invalid Vproc value: %d\n", pre_vproc);
- 		return pre_vproc;
- 	}
--	/* Vsram should not exceed the maximum allowed voltage of SoC. */
--	new_vsram = min(new_vproc + soc_data->min_volt_shift,
--			soc_data->sram_max_volt);
--
--	if (pre_vproc < new_vproc) {
--		/*
--		 * When scaling up voltages, Vsram and Vproc scale up step
--		 * by step. At each step, set Vsram to (Vproc + 200mV) first,
--		 * then set Vproc to (Vsram - 100mV).
--		 * Keep doing it until Vsram and Vproc hit target voltages.
--		 */
--		do {
--			pre_vsram = regulator_get_voltage(sram_reg);
--			if (pre_vsram < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", pre_vsram);
--				return pre_vsram;
--			}
--			pre_vproc = regulator_get_voltage(proc_reg);
--			if (pre_vproc < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", pre_vproc);
--				return pre_vproc;
--			}
- 
--			vsram = min(new_vsram,
--				    pre_vproc + soc_data->min_volt_shift);
-+	pre_vsram = regulator_get_voltage(sram_reg);
-+	if (pre_vsram < 0) {
-+		dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
-+		return pre_vsram;
-+	}
- 
--			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
--				vsram = soc_data->sram_max_volt;
-+	new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
-+			  soc_data->sram_min_volt, soc_data->sram_max_volt);
-+
-+	do {
-+		if (pre_vproc <= new_vproc) {
-+			vsram = clamp(pre_vproc + soc_data->max_volt_shift,
-+				      soc_data->sram_min_volt, new_vsram);
-+			ret = regulator_set_voltage(sram_reg, vsram,
-+						    soc_data->sram_max_volt);
- 
--				/*
--				 * If the target Vsram hits the maximum voltage,
--				 * try to set the exact voltage value first.
--				 */
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram);
--				if (ret)
--					ret = regulator_set_voltage(sram_reg,
--							vsram - VOLT_TOL,
--							vsram);
-+			if (ret)
-+				return ret;
- 
-+			if (vsram == soc_data->sram_max_volt ||
-+			    new_vsram == soc_data->sram_min_volt)
- 				vproc = new_vproc;
--			} else {
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram + VOLT_TOL);
--
-+			else
- 				vproc = vsram - soc_data->min_volt_shift;
--			}
--			if (ret)
--				return ret;
- 
- 			ret = regulator_set_voltage(proc_reg, vproc,
--						    vproc + VOLT_TOL);
-+						    soc_data->proc_max_volt);
- 			if (ret) {
- 				regulator_set_voltage(sram_reg, pre_vsram,
--						      pre_vsram);
-+						      soc_data->sram_max_volt);
- 				return ret;
- 			}
--		} while (vproc < new_vproc || vsram < new_vsram);
--	} else if (pre_vproc > new_vproc) {
--		/*
--		 * When scaling down voltages, Vsram and Vproc scale down step
--		 * by step. At each step, set Vproc to (Vsram - 200mV) first,
--		 * then set Vproc to (Vproc + 100mV).
--		 * Keep doing it until Vsram and Vproc hit target voltages.
--		 */
--		do {
--			pre_vproc = regulator_get_voltage(proc_reg);
--			if (pre_vproc < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vproc value: %d\n", pre_vproc);
--				return pre_vproc;
--			}
--			pre_vsram = regulator_get_voltage(sram_reg);
--			if (pre_vsram < 0) {
--				dev_err(info->cpu_dev,
--					"invalid Vsram value: %d\n", pre_vsram);
--				return pre_vsram;
--			}
--
-+		} else if (pre_vproc > new_vproc) {
- 			vproc = max(new_vproc,
- 				    pre_vsram - soc_data->max_volt_shift);
- 			ret = regulator_set_voltage(proc_reg, vproc,
--						    vproc + VOLT_TOL);
-+						    soc_data->proc_max_volt);
- 			if (ret)
- 				return ret;
- 
-@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking(
- 				vsram = max(new_vsram,
- 					    vproc + soc_data->min_volt_shift);
- 
--			if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
--				vsram = soc_data->sram_max_volt;
--
--				/*
--				 * If the target Vsram hits the maximum voltage,
--				 * try to set the exact voltage value first.
--				 */
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram);
--				if (ret)
--					ret = regulator_set_voltage(sram_reg,
--							vsram - VOLT_TOL,
--							vsram);
--			} else {
--				ret = regulator_set_voltage(sram_reg, vsram,
--							    vsram + VOLT_TOL);
--			}
--
-+			ret = regulator_set_voltage(sram_reg, vsram,
-+						    soc_data->sram_max_volt);
- 			if (ret) {
- 				regulator_set_voltage(proc_reg, pre_vproc,
--						      pre_vproc);
-+						      soc_data->proc_max_volt);
- 				return ret;
- 			}
--		} while (vproc > new_vproc + VOLT_TOL ||
--			 vsram > new_vsram + VOLT_TOL);
--	}
-+		}
-+
-+		pre_vproc = vproc;
-+		pre_vsram = vsram;
-+
-+		if (--retry < 0) {
-+			dev_err(info->cpu_dev,
-+				"over loop count, failed to set voltage\n");
-+			return -EINVAL;
-+		}
-+	} while (vproc != new_vproc || vsram != new_vsram);
- 
- 	return 0;
- }
-@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct
- 	 * If the new voltage or the intermediate voltage is higher than the
- 	 * current voltage, scale up voltage first.
- 	 */
--	target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
--	if (pre_vproc < target_vproc) {
-+	target_vproc = max(inter_vproc, vproc);
-+	if (pre_vproc <= target_vproc) {
- 		ret = mtk_cpufreq_set_voltage(info, target_vproc);
- 		if (ret) {
- 			dev_err(cpu_dev,
-@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct
- 	 */
- 	info->need_voltage_tracking = (info->sram_reg != NULL);
- 
-+	/*
-+	 * We assume min voltage is 0 and tracking target voltage using
-+	 * min_volt_shift for each iteration.
-+	 * The vtrack_max is 3 times of expeted iteration count.
-+	 */
-+	info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
-+						info->soc_data->proc_max_volt),
-+					    info->soc_data->min_volt_shift);
-+
- 	return 0;
- 
- out_disable_inter_clock:
diff --git a/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch b/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch
deleted file mode 100644
index 2cb99b907a..0000000000
--- a/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch
+++ /dev/null
@@ -1,184 +0,0 @@
-From 01be227eff7e5fc01f7c8de8f6daddd5fb17ddd1 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:21 +0800
-Subject: [PATCH 11/21] cpufreq: mediatek: Add opp notification support
-
-From this opp notifier, cpufreq should listen to opp notification and do
-proper actions when receiving events of disable and voltage adjustment.
-
-One of the user for this opp notifier is MediaTek SVS.
-The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
-suitable SVS bank voltages to OPP voltage table.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[ Viresh: Renamed opp_freq as current_freq and moved its initialization ]
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 90 +++++++++++++++++++++++++++---
- 1 file changed, 82 insertions(+), 8 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
- 	int pre_vproc;
-+	/* Avoid race condition for regulators between notify and policy */
-+	struct mutex reg_lock;
-+	struct notifier_block opp_nb;
-+	unsigned int opp_cpu;
-+	unsigned long current_freq;
- 	const struct mtk_cpufreq_platform_data *soc_data;
- 	int vtrack_max;
- };
-@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
- 
- 	pre_freq_hz = clk_get_rate(cpu_clk);
- 
-+	mutex_lock(&info->reg_lock);
-+
- 	if (unlikely(info->pre_vproc <= 0))
- 		pre_vproc = regulator_get_voltage(info->proc_reg);
- 	else
-@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
- 			dev_err(cpu_dev,
- 				"cpu%d: failed to scale up voltage!\n", policy->cpu);
- 			mtk_cpufreq_set_voltage(info, pre_vproc);
--			return ret;
-+			goto out;
- 		}
- 	}
- 
-@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, pre_vproc);
--		WARN_ON(1);
--		return ret;
-+		goto out;
- 	}
- 
- 	/* Set the original PLL to target rate. */
-@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
- 			"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- 		clk_set_parent(cpu_clk, armpll);
- 		mtk_cpufreq_set_voltage(info, pre_vproc);
--		return ret;
-+		goto out;
- 	}
- 
- 	/* Set parent of CPU clock back to the original PLL. */
-@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- 		mtk_cpufreq_set_voltage(info, inter_vproc);
--		WARN_ON(1);
--		return ret;
-+		goto out;
- 	}
- 
- 	/*
-@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
- 			clk_set_parent(cpu_clk, info->inter_clk);
- 			clk_set_rate(armpll, pre_freq_hz);
- 			clk_set_parent(cpu_clk, armpll);
--			return ret;
-+			goto out;
- 		}
- 	}
- 
--	return 0;
-+	info->current_freq = freq_hz;
-+
-+out:
-+	mutex_unlock(&info->reg_lock);
-+
-+	return ret;
- }
- 
- #define DYNAMIC_POWER "dynamic-power-coefficient"
- 
-+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
-+				    unsigned long event, void *data)
-+{
-+	struct dev_pm_opp *opp = data;
-+	struct dev_pm_opp *new_opp;
-+	struct mtk_cpu_dvfs_info *info;
-+	unsigned long freq, volt;
-+	struct cpufreq_policy *policy;
-+	int ret = 0;
-+
-+	info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
-+
-+	if (event == OPP_EVENT_ADJUST_VOLTAGE) {
-+		freq = dev_pm_opp_get_freq(opp);
-+
-+		mutex_lock(&info->reg_lock);
-+		if (info->current_freq == freq) {
-+			volt = dev_pm_opp_get_voltage(opp);
-+			ret = mtk_cpufreq_set_voltage(info, volt);
-+			if (ret)
-+				dev_err(info->cpu_dev,
-+					"failed to scale voltage: %d\n", ret);
-+		}
-+		mutex_unlock(&info->reg_lock);
-+	} else if (event == OPP_EVENT_DISABLE) {
-+		freq = dev_pm_opp_get_freq(opp);
-+
-+		/* case of current opp item is disabled */
-+		if (info->current_freq == freq) {
-+			freq = 1;
-+			new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
-+							    &freq);
-+			if (IS_ERR(new_opp)) {
-+				dev_err(info->cpu_dev,
-+					"all opp items are disabled\n");
-+				ret = PTR_ERR(new_opp);
-+				return notifier_from_errno(ret);
-+			}
-+
-+			dev_pm_opp_put(new_opp);
-+			policy = cpufreq_cpu_get(info->opp_cpu);
-+			if (policy) {
-+				cpufreq_driver_target(policy, freq / 1000,
-+						      CPUFREQ_RELATION_L);
-+				cpufreq_cpu_put(policy);
-+			}
-+		}
-+	}
-+
-+	return notifier_from_errno(ret);
-+}
-+
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- 	struct device *cpu_dev;
-@@ -357,6 +419,17 @@ static int mtk_cpu_dvfs_info_init(struct
- 	info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
- 
-+	mutex_init(&info->reg_lock);
-+	info->current_freq = clk_get_rate(info->cpu_clk);
-+
-+	info->opp_cpu = cpu;
-+	info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
-+	ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
-+	if (ret) {
-+		dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
-+		goto out_disable_inter_clock;
-+	}
-+
- 	/*
- 	 * If SRAM regulator is present, software "voltage tracking" is needed
- 	 * for this CPU power domain.
-@@ -421,6 +494,7 @@ static void mtk_cpu_dvfs_info_release(st
- 	}
- 
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
-+	dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
- }
- 
- static int mtk_cpufreq_init(struct cpufreq_policy *policy)
diff --git a/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch b/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch
deleted file mode 100644
index 76bd795c00..0000000000
--- a/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 6a1bd7cf4ed7a1948f564aaf16d34b7352c0029b Mon Sep 17 00:00:00 2001
-From: Wan Jiabing <wanjiabing@vivo.com>
-Date: Tue, 10 May 2022 17:05:31 +0800
-Subject: [PATCH 12/21] cpufreq: mediatek: Fix potential deadlock problem in
- mtk_cpufreq_set_target
-
-Fix following coccichek error:
-./drivers/cpufreq/mediatek-cpufreq.c:199:2-8: preceding lock on line
-./drivers/cpufreq/mediatek-cpufreq.c:208:2-8: preceding lock on line
-
-mutex_lock is acquired but not released before return.
-Use 'goto out' to help releasing the mutex_lock.
-
-Fixes: c210063b40ac ("cpufreq: mediatek: Add opp notification support")
-Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
-Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -196,7 +196,8 @@ static int mtk_cpufreq_set_target(struct
- 
- 	if (pre_vproc < 0) {
- 		dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
--		return pre_vproc;
-+		ret = pre_vproc;
-+		goto out;
- 	}
- 
- 	freq_hz = freq_table[index].frequency * 1000;
-@@ -205,7 +206,8 @@ static int mtk_cpufreq_set_target(struct
- 	if (IS_ERR(opp)) {
- 		dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
- 			policy->cpu, freq_hz);
--		return PTR_ERR(opp);
-+		ret = PTR_ERR(opp);
-+		goto out;
- 	}
- 	vproc = dev_pm_opp_get_voltage(opp);
- 	dev_pm_opp_put(opp);
diff --git a/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch b/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch
deleted file mode 100644
index eeaa466c32..0000000000
--- a/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch
+++ /dev/null
@@ -1,188 +0,0 @@
-From 15aaf74fb734a3e69b10d00b97b322711b81e222 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:22 +0800
-Subject: [PATCH 13/21] cpufreq: mediatek: Link CCI device to CPU
-
-In some MediaTek SoCs, like MT8183, CPU and CCI share the same power
-supplies. Cpufreq needs to check if CCI devfreq exists and wait until
-CCI devfreq ready before scaling frequency.
-
-Before CCI devfreq is ready, we record the voltage when booting to
-kernel and use the max(cpu target voltage, booting voltage) to
-prevent cpufreq adjust to the lower voltage which will cause the CCI
-crash because of high frequency and low voltage.
-
-- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start
-  DVFS when CCI is ready.
-- Add platform data for MT8183.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Kevin Hilman <khilman@baylibre.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++-
- 1 file changed, 81 insertions(+), 1 deletion(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data {
- 	int proc_max_volt;
- 	int sram_min_volt;
- 	int sram_max_volt;
-+	bool ccifreq_supported;
- };
- 
- /*
-@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data {
- struct mtk_cpu_dvfs_info {
- 	struct cpumask cpus;
- 	struct device *cpu_dev;
-+	struct device *cci_dev;
- 	struct regulator *proc_reg;
- 	struct regulator *sram_reg;
- 	struct clk *cpu_clk;
-@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- 	struct list_head list_head;
- 	int intermediate_voltage;
- 	bool need_voltage_tracking;
-+	int vproc_on_boot;
- 	int pre_vproc;
- 	/* Avoid race condition for regulators between notify and policy */
- 	struct mutex reg_lock;
-@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info {
- 	unsigned long current_freq;
- 	const struct mtk_cpufreq_platform_data *soc_data;
- 	int vtrack_max;
-+	bool ccifreq_bound;
- };
- 
- static struct platform_device *cpufreq_pdev;
-@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struc
- 	return ret;
- }
- 
-+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
-+{
-+	struct device_link *sup_link;
-+
-+	if (info->ccifreq_bound)
-+		return true;
-+
-+	sup_link = device_link_add(info->cpu_dev, info->cci_dev,
-+				   DL_FLAG_AUTOREMOVE_CONSUMER);
-+	if (!sup_link) {
-+		dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
-+		return false;
-+	}
-+
-+	if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
-+		return false;
-+
-+	info->ccifreq_bound = true;
-+
-+	return true;
-+}
-+
- static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
- 				  unsigned int index)
- {
-@@ -213,6 +239,14 @@ static int mtk_cpufreq_set_target(struct
- 	dev_pm_opp_put(opp);
- 
- 	/*
-+	 * If MediaTek cci is supported but is not ready, we will use the value
-+	 * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
-+	 * low voltage crash.
-+	 */
-+	if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
-+		vproc = max(vproc, info->vproc_on_boot);
-+
-+	/*
- 	 * If the new voltage or the intermediate voltage is higher than the
- 	 * current voltage, scale up voltage first.
- 	 */
-@@ -333,6 +367,23 @@ static int mtk_cpufreq_opp_notifier(stru
- 	return notifier_from_errno(ret);
- }
- 
-+static struct device *of_get_cci(struct device *cpu_dev)
-+{
-+	struct device_node *np;
-+	struct platform_device *pdev;
-+
-+	np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
-+	if (IS_ERR_OR_NULL(np))
-+		return NULL;
-+
-+	pdev = of_find_device_by_node(np);
-+	of_node_put(np);
-+	if (IS_ERR_OR_NULL(pdev))
-+		return NULL;
-+
-+	return &pdev->dev;
-+}
-+
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- 	struct device *cpu_dev;
-@@ -347,6 +398,16 @@ static int mtk_cpu_dvfs_info_init(struct
- 	}
- 	info->cpu_dev = cpu_dev;
- 
-+	info->ccifreq_bound = false;
-+	if (info->soc_data->ccifreq_supported) {
-+		info->cci_dev = of_get_cci(info->cpu_dev);
-+		if (IS_ERR_OR_NULL(info->cci_dev)) {
-+			ret = PTR_ERR(info->cci_dev);
-+			dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
-+			return -ENODEV;
-+		}
-+	}
-+
- 	info->cpu_clk = clk_get(cpu_dev, "cpu");
- 	if (IS_ERR(info->cpu_clk)) {
- 		ret = PTR_ERR(info->cpu_clk);
-@@ -410,6 +471,15 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (ret)
- 		goto out_disable_mux_clock;
- 
-+	if (info->soc_data->ccifreq_supported) {
-+		info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
-+		if (info->vproc_on_boot < 0) {
-+			dev_err(info->cpu_dev,
-+				"invalid Vproc value: %d\n", info->vproc_on_boot);
-+			goto out_disable_inter_clock;
-+		}
-+	}
-+
- 	/* Search a safe voltage for intermediate frequency. */
- 	rate = clk_get_rate(info->inter_clk);
- 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
-@@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform
- 	.proc_max_volt = 1150000,
- 	.sram_min_volt = 0,
- 	.sram_max_volt = 1150000,
-+	.ccifreq_supported = false,
-+};
-+
-+static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1150000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1150000,
-+	.ccifreq_supported = true,
- };
- 
- /* List of machines supported by this driver */
-@@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
- 	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- 	{ }
diff --git a/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch b/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch
deleted file mode 100644
index 31000cfbe0..0000000000
--- a/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From b6be0baa6615afc65c3963adab674e36af1d4d5f Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Thu, 5 May 2022 19:52:23 +0800
-Subject: [PATCH 14/21] cpufreq: mediatek: Add support for MT8186
-
-The platform data of MT8186 is different from previous MediaTek SoCs,
-so we add a new compatible and platform data for it.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = true,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 250000,
-+	.proc_max_volt = 1118750,
-+	.sram_min_volt = 850000,
-+	.sram_max_volt = 1118750,
-+	.ccifreq_supported = true,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
-@@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
-+	{ .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
- 	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- 	{ }
diff --git a/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch b/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch
deleted file mode 100644
index c0137894c9..0000000000
--- a/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 75d19b24aa3203d6c78e4c431c2cc07157ce12fe Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 13 Jul 2022 13:15:36 +0200
-Subject: [PATCH 15/21] cpufreq: mediatek: Handle sram regulator probe deferral
-
-If the regulator_get_optional() call for the SRAM regulator returns
-a probe deferral, we must bail out and retry probing later: failing
-to do this will produce unstabilities on platforms requiring the
-handling for this regulator.
-
-Fixes: ffa7bdf7f344 ("cpufreq: mediatek: Make sram regulator optional")
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -439,9 +439,13 @@ static int mtk_cpu_dvfs_info_init(struct
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
- 	info->sram_reg = regulator_get_optional(cpu_dev, "sram");
--	if (IS_ERR(info->sram_reg))
-+	if (IS_ERR(info->sram_reg)) {
-+		ret = PTR_ERR(info->sram_reg);
-+		if (ret == -EPROBE_DEFER)
-+			goto out_free_resources;
-+
- 		info->sram_reg = NULL;
--	else {
-+	} else {
- 		ret = regulator_enable(info->sram_reg);
- 		if (ret) {
- 			dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
diff --git a/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch b/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch
deleted file mode 100644
index 45c4477ff1..0000000000
--- a/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From dd1174c21dacacd6c0129c1dabc5decad35c02c2 Mon Sep 17 00:00:00 2001
-From: Yang Yingliang <yangyingliang@huawei.com>
-Date: Tue, 17 May 2022 21:34:50 +0800
-Subject: [PATCH 16/21] cpufreq: mediatek: fix error return code in
- mtk_cpu_dvfs_info_init()
-
-If regulator_get_voltage() fails, it should return the error code in
-mtk_cpu_dvfs_info_init().
-
-Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU")
-Reported-by: Hulk Robot <hulkci@huawei.com>
-Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (info->soc_data->ccifreq_supported) {
- 		info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
- 		if (info->vproc_on_boot < 0) {
-+			ret = info->vproc_on_boot;
- 			dev_err(info->cpu_dev,
- 				"invalid Vproc value: %d\n", info->vproc_on_boot);
- 			goto out_disable_inter_clock;
diff --git a/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch b/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch
deleted file mode 100644
index 557d02b822..0000000000
--- a/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 230a74d459244411db91bfd678f17fcf7aedfcd0 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:27 +0800
-Subject: [PATCH 17/21] cpufreq: mediatek: fix passing zero to 'PTR_ERR'
-
-In order to prevent passing zero to 'PTR_ERR' in
-mtk_cpu_dvfs_info_init(), we fix the return value of of_get_cci() using
-error pointer by explicitly casting error number.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU")
-Reported-by: Dan Carpenter <error27@gmail.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -373,13 +373,13 @@ static struct device *of_get_cci(struct
- 	struct platform_device *pdev;
- 
- 	np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
--	if (IS_ERR_OR_NULL(np))
--		return NULL;
-+	if (!np)
-+		return ERR_PTR(-ENODEV);
- 
- 	pdev = of_find_device_by_node(np);
- 	of_node_put(np);
--	if (IS_ERR_OR_NULL(pdev))
--		return NULL;
-+	if (!pdev)
-+		return ERR_PTR(-ENODEV);
- 
- 	return &pdev->dev;
- }
-@@ -401,7 +401,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 	info->ccifreq_bound = false;
- 	if (info->soc_data->ccifreq_supported) {
- 		info->cci_dev = of_get_cci(info->cpu_dev);
--		if (IS_ERR_OR_NULL(info->cci_dev)) {
-+		if (IS_ERR(info->cci_dev)) {
- 			ret = PTR_ERR(info->cci_dev);
- 			dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
- 			return -ENODEV;
diff --git a/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch b/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch
deleted file mode 100644
index 61531d38ad..0000000000
--- a/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From fced531b7c7e18192e7982637c8e8f20c29aad64 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:28 +0800
-Subject: [PATCH 18/21] cpufreq: mediatek: fix KP caused by handler usage after
- regulator_put/clk_put
-
-Any kind of failure in mtk_cpu_dvfs_info_init() will lead to calling
-regulator_put() or clk_put() and the KP will occur since the regulator/clk
-handlers are used after released in mtk_cpu_dvfs_info_release().
-
-To prevent the usage after regulator_put()/clk_put(), the regulator/clk
-handlers are addressed in a way of "Free the Last Thing Style".
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: 4b9ceb757bbb ("cpufreq: mediatek: Enable clocks and regulators")
-Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Suggested-by: Dan Carpenter <error27@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 62 +++++++++++++++---------------
- 1 file changed, 30 insertions(+), 32 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -420,7 +420,7 @@ static int mtk_cpu_dvfs_info_init(struct
- 		ret = PTR_ERR(info->inter_clk);
- 		dev_err_probe(cpu_dev, ret,
- 			      "cpu%d: failed to get intermediate clk\n", cpu);
--		goto out_free_resources;
-+		goto out_free_mux_clock;
- 	}
- 
- 	info->proc_reg = regulator_get_optional(cpu_dev, "proc");
-@@ -428,13 +428,13 @@ static int mtk_cpu_dvfs_info_init(struct
- 		ret = PTR_ERR(info->proc_reg);
- 		dev_err_probe(cpu_dev, ret,
- 			      "cpu%d: failed to get proc regulator\n", cpu);
--		goto out_free_resources;
-+		goto out_free_inter_clock;
- 	}
- 
- 	ret = regulator_enable(info->proc_reg);
- 	if (ret) {
- 		dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
--		goto out_free_resources;
-+		goto out_free_proc_reg;
- 	}
- 
- 	/* Both presence and absence of sram regulator are valid cases. */
-@@ -442,14 +442,14 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (IS_ERR(info->sram_reg)) {
- 		ret = PTR_ERR(info->sram_reg);
- 		if (ret == -EPROBE_DEFER)
--			goto out_free_resources;
-+			goto out_disable_proc_reg;
- 
- 		info->sram_reg = NULL;
- 	} else {
- 		ret = regulator_enable(info->sram_reg);
- 		if (ret) {
- 			dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
--			goto out_free_resources;
-+			goto out_free_sram_reg;
- 		}
- 	}
- 
-@@ -458,13 +458,13 @@ static int mtk_cpu_dvfs_info_init(struct
- 	if (ret) {
- 		dev_err(cpu_dev,
- 			"cpu%d: failed to get OPP-sharing information\n", cpu);
--		goto out_free_resources;
-+		goto out_disable_sram_reg;
- 	}
- 
- 	ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
- 	if (ret) {
- 		dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
--		goto out_free_resources;
-+		goto out_disable_sram_reg;
- 	}
- 
- 	ret = clk_prepare_enable(info->cpu_clk);
-@@ -533,43 +533,41 @@ out_disable_mux_clock:
- out_free_opp_table:
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 
--out_free_resources:
--	if (regulator_is_enabled(info->proc_reg))
--		regulator_disable(info->proc_reg);
--	if (info->sram_reg && regulator_is_enabled(info->sram_reg))
-+out_disable_sram_reg:
-+	if (info->sram_reg)
- 		regulator_disable(info->sram_reg);
- 
--	if (!IS_ERR(info->proc_reg))
--		regulator_put(info->proc_reg);
--	if (!IS_ERR(info->sram_reg))
-+out_free_sram_reg:
-+	if (info->sram_reg)
- 		regulator_put(info->sram_reg);
--	if (!IS_ERR(info->cpu_clk))
--		clk_put(info->cpu_clk);
--	if (!IS_ERR(info->inter_clk))
--		clk_put(info->inter_clk);
-+
-+out_disable_proc_reg:
-+	regulator_disable(info->proc_reg);
-+
-+out_free_proc_reg:
-+	regulator_put(info->proc_reg);
-+
-+out_free_inter_clock:
-+	clk_put(info->inter_clk);
-+
-+out_free_mux_clock:
-+	clk_put(info->cpu_clk);
- 
- 	return ret;
- }
- 
- static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
- {
--	if (!IS_ERR(info->proc_reg)) {
--		regulator_disable(info->proc_reg);
--		regulator_put(info->proc_reg);
--	}
--	if (!IS_ERR(info->sram_reg)) {
-+	regulator_disable(info->proc_reg);
-+	regulator_put(info->proc_reg);
-+	if (info->sram_reg) {
- 		regulator_disable(info->sram_reg);
- 		regulator_put(info->sram_reg);
- 	}
--	if (!IS_ERR(info->cpu_clk)) {
--		clk_disable_unprepare(info->cpu_clk);
--		clk_put(info->cpu_clk);
--	}
--	if (!IS_ERR(info->inter_clk)) {
--		clk_disable_unprepare(info->inter_clk);
--		clk_put(info->inter_clk);
--	}
--
-+	clk_disable_unprepare(info->cpu_clk);
-+	clk_put(info->cpu_clk);
-+	clk_disable_unprepare(info->inter_clk);
-+	clk_put(info->inter_clk);
- 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- 	dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
- }
diff --git a/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch b/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch
deleted file mode 100644
index 2b7d229f1c..0000000000
--- a/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 24bc42a2d44cb821818717a5c607270921ec5d20 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:29 +0800
-Subject: [PATCH 19/21] cpufreq: mediatek: raise proc/sram max voltage for
- MT8516
-
-Since the upper boundary of proc/sram voltage of MT8516 is 1300 mV,
-which is greater than the value of MT2701 1150 mV, we fix it by adding
-the corresponding platform data and specify proc/sram_max_volt to
-support MT8516.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data")
-Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-Reported-by: Nick Hainke <vincent@systemli.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -711,20 +711,29 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = true,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt8516_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1310000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1310000,
-+	.ccifreq_supported = false,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
- 	{ .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
- 	{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt8516", .data = &mt8516_platform_data },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
diff --git a/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch b/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch
deleted file mode 100644
index 2de8eb6394..0000000000
--- a/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From fe6ef09358dc0cfead9d383a8676fbe7a40fcef7 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 24 Mar 2023 18:11:30 +0800
-Subject: [PATCH 20/21] cpufreq: mediatek: Raise proc and sram max voltage for
- MT7622/7623
-
-During the addition of SRAM voltage tracking for CCI scaling, this
-driver got some voltage limits set for the vtrack algorithm: these
-were moved to platform data first, then enforced in a later commit
-6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-using these as max values for the regulator_set_voltage() calls.
-
-In this case, the vsram/vproc constraints for MT7622 and MT7623
-were supposed to be the same as MT2701 (and a number of other SoCs),
-but that turned out to be a mistake because the aforementioned two
-SoCs' maximum voltage for both VPROC and VPROC_SRAM is 1.36V.
-
-Fix that by adding new platform data for MT7622/7623 declaring the
-right {proc,sram}_max_volt parameter.
-
-Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data")
-Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -693,6 +693,15 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = false,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1360000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1360000,
-+	.ccifreq_supported = false,
-+};
-+
- static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
-@@ -724,8 +733,8 @@ static const struct mtk_cpufreq_platform
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
--	{ .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
-+	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
-+	{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
- 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch
deleted file mode 100644
index 6acd3d607f..0000000000
--- a/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 28 Feb 2023 19:59:22 +0800
-Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
-
-This add cpufreq support for mediatek MT7988 SoC.
-
-The platform data of MT7988 is different from previous MediaTek SoCs,
-so we add a new compatible and platform data for it.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -702,6 +702,15 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = false,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 900000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1150000,
-+	.ccifreq_supported = true,
-+};
-+
- static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
-@@ -735,6 +744,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
- 	{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
-+	{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
- 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch
deleted file mode 100644
index 6ab05b897c..0000000000
--- a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 26 May 2023 10:31:40 +0100
-Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623
-
-The MT6380 regulator typically used together with MT7622 does not
-support the current maximum processor and SRAM voltage in the cpufreq
-driver (1360000uV).
-For MT7622 limit processor and SRAM supply voltages to 1350000uV to
-avoid having the tracking algorithm request unsupported voltages from
-the regulator.
-
-On MT7623 there is no separate SRAM supply and the maximum voltage used
-is 1300000uV. Create dedicated platform data for MT7623 to cover that
-case as well.
-
-Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623")
-Suggested-by: Jia-wei Chang <Jia-wei.Chang@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform
- static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
--	.proc_max_volt = 1360000,
-+	.proc_max_volt = 1350000,
- 	.sram_min_volt = 0,
--	.sram_max_volt = 1360000,
-+	.sram_max_volt = 1350000,
-+	.ccifreq_supported = false,
-+};
-+
-+static const struct mtk_cpufreq_platform_data mt7623_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 1300000,
- 	.ccifreq_supported = false,
- };
- 
-@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
--	{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
-+	{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
- 	{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
- 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch
deleted file mode 100644
index 25ca9485e4..0000000000
--- a/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/drivers/crypto/inside-secure/safexcel.c
-+++ b/drivers/crypto/inside-secure/safexcel.c
-@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex
- 		val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
- 		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
- 	}
-+	/*
-+	 * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
-+	 */
-+	else {
-+		val = 0;
-+		val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
-+		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
-+	}
- 
- 	/* Configure wr/rd cache values */
- 	writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -315,6 +315,7 @@
- #define EIP197_MST_CTRL_RD_CACHE(n)		(((n) & 0xf) << 0)
- #define EIP197_MST_CTRL_WD_CACHE(n)		(((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 20)
-+#define EIP97_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_BYTE_SWAP		BIT(24)
- #define EIP197_MST_CTRL_NO_BYTE_SWAP		BIT(25)
- #define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)
diff --git a/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch
deleted file mode 100644
index 186c66f687..0000000000
--- a/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -737,6 +737,9 @@ enum safexcel_eip_version {
- /* Priority we use for advertising our algorithms */
- #define SAFEXCEL_CRA_PRIORITY		300
- 
-+/* System cache line size */
-+#define SYSTEM_CACHELINE_SIZE		64
-+
- /* SM3 digest result for zero length message */
- #define EIP197_SM3_ZEROM_HASH	"\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
- 				"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
---- a/drivers/crypto/inside-secure/safexcel_hash.c
-+++ b/drivers/crypto/inside-secure/safexcel_hash.c
-@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
- 	u8 block_sz;    /* block size, only set once */
- 	u8 digest_sz;   /* output digest size, only set once */
- 	__le32 state[SHA3_512_BLOCK_SIZE /
--		     sizeof(__le32)] __aligned(sizeof(__le32));
-+		     sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
- 
--	u64 len;
-+	u64 len __aligned(SYSTEM_CACHELINE_SIZE);
- 	u64 processed;
- 
- 	u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
diff --git a/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch
deleted file mode 100644
index 332f17bae7..0000000000
--- a/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From f6ba5e17bee38f8ffe118c47fbfef3cf90eb87ff Mon Sep 17 00:00:00 2001
-From: "Mingming.Su" <Mingming.Su@mediatek.com>
-Date: Wed, 30 Jun 2021 16:59:32 +0800
-Subject: [PATCH] mt7986: trng: add rng support
-
-1. Add trng compatible name for MT7986
-2. Fix mtk_rng_wait_ready() function
-
-Signed-off-by: Mingming.Su <Mingming.Su@mediatek.com>
----
- drivers/char/hw_random/mtk-rng.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/char/hw_random/mtk-rng.c
-+++ b/drivers/char/hw_random/mtk-rng.c
-@@ -22,7 +22,7 @@
- #define RNG_AUTOSUSPEND_TIMEOUT		100
- 
- #define USEC_POLL			2
--#define TIMEOUT_POLL			20
-+#define TIMEOUT_POLL			60
- 
- #define RNG_CTRL			0x00
- #define RNG_EN				BIT(0)
-@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw
- 		readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
- 					  ready & RNG_READY, USEC_POLL,
- 					  TIMEOUT_POLL);
--	return !!ready;
-+	return !!(ready & RNG_READY);
- }
- 
- static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p
- #endif	/* CONFIG_PM */
- 
- static const struct of_device_id mtk_rng_match[] = {
-+	{ .compatible = "mediatek,mt7986-rng" },
- 	{ .compatible = "mediatek,mt7623-rng" },
- 	{},
- };
diff --git a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch
deleted file mode 100644
index 3f4597c65d..0000000000
--- a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/drivers/tty/serial/8250/8250.h
-+++ b/drivers/tty/serial/8250/8250.h
-@@ -85,6 +85,7 @@ struct serial8250_config {
- #define UART_CAP_MINI	BIT(17)	/* Mini UART on BCM283X family lacks:
- 					 * STOP PARITY EPAR SPAR WLEN5 WLEN6
- 					 */
-+#define UART_CAP_NMOD	(1 << 18)	/* UART doesn't do termios */
- 
- #define UART_BUG_QUOT	BIT(0)	/* UART has buggy quot LSB */
- #define UART_BUG_TXEN	BIT(1)	/* UART has buggy TX IIR status */
---- a/drivers/tty/serial/8250/8250_port.c
-+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -289,7 +289,7 @@ static const struct serial8250_config ua
- 		.tx_loadsz	= 16,
- 		.fcr		= UART_FCR_ENABLE_FIFO |
- 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
--		.flags		= UART_CAP_FIFO,
-+		.flags		= UART_CAP_FIFO | UART_CAP_NMOD,
- 	},
- 	[PORT_NPCM] = {
- 		.name		= "Nuvoton 16550",
-@@ -2766,6 +2766,11 @@ serial8250_do_set_termios(struct uart_po
- 	unsigned long flags;
- 	unsigned int baud, quot, frac = 0;
- 
-+	if (up->capabilities & UART_CAP_NMOD) {
-+		termios->c_cflag = 0;
-+		return;
-+	}
-+
- 	if (up->capabilities & UART_CAP_MINI) {
- 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
- 		if ((termios->c_cflag & CSIZE) == CS5 ||
diff --git a/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch b/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch
deleted file mode 100644
index cc9e9c55e3..0000000000
--- a/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From: David Bauer <mail@david-bauer.net>
-To: linux-mtd@lists.infradead.org
-Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV
-Date: Sat, 13 Feb 2021 16:10:47 +0100
-
-The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K
-sectors as well as block protection and Dual-/Quad-read.
-
-Tested on: Ubiquiti UniFi 6 LR
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- drivers/mtd/spi-nor/winbond.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mtd/spi-nor/winbond.c
-+++ b/drivers/mtd/spi-nor/winbond.c
-@@ -98,6 +98,10 @@ static const struct flash_info winbond_p
- 			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- 	{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
- 			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-+	{ "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024,
-+			    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ |
-+			    SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
-+			    SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
- 	{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
- 			    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
- 	{ "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024,
diff --git a/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch
deleted file mode 100644
index a57ee25393..0000000000
--- a/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:29:51 +0800
-Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
- data
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c                 | 29 +++++++++---------------
- include/linux/platform_data/spi-mt65xx.h | 17 --------------
- 2 files changed, 11 insertions(+), 35 deletions(-)
- delete mode 100644 include/linux/platform_data/spi-mt65xx.h
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -14,7 +14,6 @@
- #include <linux/of.h>
- #include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
--#include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-@@ -142,6 +141,8 @@ struct mtk_spi {
- 	struct device *dev;
- 	dma_addr_t tx_dma;
- 	dma_addr_t rx_dma;
-+	u32 sample_sel;
-+	u32 get_tick_dly;
- };
- 
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -187,15 +188,6 @@ static const struct mtk_spi_compatible m
- 	.no_need_unprepare = true,
- };
- 
--/*
-- * A piece of default chip info unless the platform
-- * supplies it.
-- */
--static const struct mtk_chip_config mtk_default_chip_info = {
--	.sample_sel = 0,
--	.tick_delay = 0,
--};
--
- static const struct of_device_id mtk_spi_of_match[] = {
- 	{ .compatible = "mediatek,spi-ipm",
- 		.data = (void *)&mtk_ipm_compat,
-@@ -323,7 +315,6 @@ static int mtk_spi_hw_init(struct spi_ma
- {
- 	u16 cpha, cpol;
- 	u32 reg_val;
--	struct mtk_chip_config *chip_config = spi->controller_data;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
- 	cpha = spi->mode & SPI_CPHA ? 1 : 0;
-@@ -373,7 +364,7 @@ static int mtk_spi_hw_init(struct spi_ma
- 		else
- 			reg_val &= ~SPI_CMD_CS_POL;
- 
--		if (chip_config->sample_sel)
-+		if (mdata->sample_sel)
- 			reg_val |= SPI_CMD_SAMPLE_SEL;
- 		else
- 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
-@@ -400,20 +391,20 @@ static int mtk_spi_hw_init(struct spi_ma
- 		if (mdata->dev_comp->ipm_design) {
- 			reg_val = readl(mdata->base + SPI_CMD_REG);
- 			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
--			reg_val |= ((chip_config->tick_delay & 0x7)
-+			reg_val |= ((mdata->get_tick_dly & 0x7)
- 				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
- 			writel(reg_val, mdata->base + SPI_CMD_REG);
- 		} else {
- 			reg_val = readl(mdata->base + SPI_CFG1_REG);
- 			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
--			reg_val |= ((chip_config->tick_delay & 0x7)
-+			reg_val |= ((mdata->get_tick_dly & 0x7)
- 				    << SPI_CFG1_GET_TICK_DLY_OFFSET);
- 			writel(reg_val, mdata->base + SPI_CFG1_REG);
- 		}
- 	} else {
- 		reg_val = readl(mdata->base + SPI_CFG1_REG);
- 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
--		reg_val |= ((chip_config->tick_delay & 0x3)
-+		reg_val |= ((mdata->get_tick_dly & 0x3)
- 			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
- 		writel(reg_val, mdata->base + SPI_CFG1_REG);
- 	}
-@@ -700,9 +691,6 @@ static int mtk_spi_setup(struct spi_devi
- {
- 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
- 
--	if (!spi->controller_data)
--		spi->controller_data = (void *)&mtk_default_chip_info;
--
- 	if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
- 		/* CS de-asserted, gpiolib will handle inversion */
- 		gpiod_direction_output(spi->cs_gpiod, 0);
-@@ -1115,6 +1103,10 @@ static int mtk_spi_probe(struct platform
- 	mdata = spi_master_get_devdata(master);
- 	mdata->dev_comp = of_id->data;
- 
-+	/* Set device configs to default first. Calibrate it later. */
-+	mdata->sample_sel = 0;
-+	mdata->get_tick_dly = 2;
-+
- 	if (mdata->dev_comp->enhance_timing)
- 		master->mode_bits |= SPI_CS_HIGH;
- 
---- a/include/linux/platform_data/spi-mt65xx.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0-only */
--/*
-- *  MTK SPI bus driver definitions
-- *
-- * Copyright (c) 2015 MediaTek Inc.
-- * Author: Leilk Liu <leilk.liu@mediatek.com>
-- */
--
--#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
--#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
--
--/* Board specific platform_data */
--struct mtk_chip_config {
--	u32 sample_sel;
--	u32 tick_delay;
--};
--#endif
diff --git a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch
deleted file mode 100644
index e795eda3b2..0000000000
--- a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:35:52 +0800
-Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi.c       | 137 ++++++++++++++++++++++++++++++++++++++++
- include/linux/spi/spi.h |  42 ++++++++++++
- 2 files changed, 179 insertions(+)
-
---- a/drivers/spi/spi.c
-+++ b/drivers/spi/spi.c
-@@ -1246,6 +1246,70 @@ static int spi_transfer_wait(struct spi_
- 	return 0;
- }
- 
-+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
-+	int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
-+{
-+	int datalen = ctlr->cal_rule->datalen;
-+	int addrlen = ctlr->cal_rule->addrlen;
-+	u8 *buf;
-+	int ret;
-+	int i;
-+	struct list_head *cal_head, *listptr;
-+	struct spi_cal_target *target;
-+
-+	/* Calculate calibration result */
-+	int hit_val, total_hit, origin;
-+	bool hit;
-+
-+	/* Make sure we can start calibration */
-+	if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
-+		return 0;
-+
-+	buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
-+	if(!buf)
-+		return -ENOMEM;
-+
-+	ret = ctlr->append_caldata(ctlr);
-+	if (ret)
-+		goto cal_end;
-+
-+	cal_head = ctlr->cal_target;
-+	list_for_each(listptr, cal_head) {
-+		target = list_entry(listptr, struct spi_cal_target, list);
-+
-+		hit = false;
-+		hit_val = 0;
-+		total_hit = 0;
-+		origin = *target->cal_item;
-+
-+		for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
-+			*target->cal_item = i;
-+			ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
-+			if(ret)
-+				break;
-+			dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
-+			if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
-+				hit = true;
-+				hit_val += i;
-+				total_hit++;
-+				dev_dbg(&spi->dev, "golden data matches data read!\n");
-+			}
-+		}
-+		if(hit) {
-+			*target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
-+			dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
-+		} else {
-+			*target->cal_item = origin;
-+			dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
-+		}
-+	}
-+
-+cal_end:
-+	kfree(buf);
-+	return ret? ret: 0;
-+}
-+EXPORT_SYMBOL_GPL(spi_do_calibration);
-+
- static void _spi_transfer_delay_ns(u32 ns)
- {
- 	if (!ns)
-@@ -2033,6 +2097,75 @@ void spi_flush_queue(struct spi_controll
- /*-------------------------------------------------------------------------*/
- 
- #if defined(CONFIG_OF)
-+static inline void alloc_cal_data(struct list_head **cal_target,
-+	struct spi_cal_rule **cal_rule, bool enable)
-+{
-+	if(enable) {
-+		*cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
-+		INIT_LIST_HEAD(*cal_target);
-+		*cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
-+	} else {
-+		kfree(*cal_target);
-+		kfree(*cal_rule);
-+	}
-+}
-+
-+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
-+			   struct device_node *nc)
-+{
-+	u32 value;
-+	int rc;
-+	const char *cal_mode;
-+
-+	rc = of_property_read_bool(nc, "spi-cal-enable");
-+	if (rc)
-+		alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
-+	else
-+		return 0;
-+
-+	rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
-+	if(!rc) {
-+		if(strcmp("read-data", cal_mode) == 0){
-+			ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
-+		} else if(strcmp("read-pp", cal_mode) == 0) {
-+			ctlr->cal_rule->mode = SPI_CAL_READ_PP;
-+			return 0;
-+		} else if(strcmp("read-sfdp", cal_mode) == 0){
-+			ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
-+			return 0;
-+		}
-+	} else
-+		goto err;
-+
-+	ctlr->cal_rule->datalen = 0;
-+	rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
-+	if(!rc && value > 0) {
-+		ctlr->cal_rule->datalen = value;
-+
-+		ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
-+		rc = of_property_read_u8_array(nc, "spi-cal-data",
-+				ctlr->cal_rule->match_data, value);
-+		if(rc)
-+			kfree(ctlr->cal_rule->match_data);
-+	}
-+
-+	rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
-+	if(!rc && value > 0) {
-+		ctlr->cal_rule->addrlen = value;
-+
-+		ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
-+		rc = of_property_read_u32_array(nc, "spi-cal-addr",
-+				ctlr->cal_rule->addr, value);
-+		if(rc)
-+			kfree(ctlr->cal_rule->addr);
-+	}
-+	return 0;
-+
-+err:
-+	alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
-+	return 0;
-+}
-+
- static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
- 			   struct device_node *nc)
- {
-@@ -2151,6 +2284,10 @@ of_register_spi_device(struct spi_contro
- 	if (rc)
- 		goto err_out;
- 
-+	rc = of_spi_parse_cal_dt(ctlr, spi, nc);
-+	if (rc)
-+		goto err_out;
-+
- 	/* Store a pointer to the node in the device structure */
- 	of_node_get(nc);
- 	spi->dev.of_node = nc;
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -290,6 +290,40 @@ struct spi_driver {
- 	struct device_driver	driver;
- };
- 
-+enum {
-+	SPI_CAL_READ_DATA = 0,
-+	SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
-+	SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
-+};
-+
-+struct nand_addr {
-+	unsigned int lun;
-+	unsigned int plane;
-+	unsigned int eraseblock;
-+	unsigned int page;
-+	unsigned int dataoffs;
-+};
-+
-+/**
-+ * Read calibration rule from device dts node.
-+ * Once calibration result matches the rule, we regard is as success.
-+ */
-+struct spi_cal_rule {
-+	int datalen;
-+	u8 *match_data;
-+	int addrlen;
-+	u32 *addr;
-+	int mode;
-+};
-+
-+struct spi_cal_target {
-+	u32 *cal_item;
-+	int cal_min; /* min of cal_item */
-+	int cal_max; /* max of cal_item */
-+	int step; /* Increase/decrease cal_item */
-+	struct list_head list;
-+};
-+
- static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
- {
- 	return drv ? container_of(drv, struct spi_driver, driver) : NULL;
-@@ -665,6 +699,11 @@ struct spi_controller {
- 	void			*dummy_rx;
- 	void			*dummy_tx;
- 
-+	/* For calibration */
-+	int (*append_caldata)(struct spi_controller *ctlr);
-+	struct list_head *cal_target;
-+	struct spi_cal_rule *cal_rule;
-+
- 	int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
- 
- 	/*
-@@ -1477,6 +1516,9 @@ spi_register_board_info(struct spi_board
- 	{ return 0; }
- #endif
- 
-+extern int spi_do_calibration(struct spi_controller *ctlr,
-+	struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
-+
- /* If you're hotplugging an adapter with devices (parport, usb, etc)
-  * use spi_new_device() to describe each device.  You can also call
-  * spi_unregister_device() to start making that device vanish, but
diff --git a/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch
deleted file mode 100644
index aaacab0131..0000000000
--- a/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:37:55 +0800
-Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mem.c       | 8 ++++++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 12 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -410,6 +410,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
- }
- EXPORT_SYMBOL_GPL(spi_mem_exec_op);
- 
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+	int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
-+	void *priv)
-+{
-+	return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
-+}
-+EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
-+
- /**
-  * spi_mem_get_name() - Return the SPI mem device name to be used by the
-  *			upper layer if necessary
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem
- int spi_mem_exec_op(struct spi_mem *mem,
- 		    const struct spi_mem_op *op);
- 
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+			int (*cal_read)(void *, u32 *, int, u8 *, int),
-+			void *priv);
-+
- const char *spi_mem_get_name(struct spi_mem *mem);
- 
- struct spi_mem_dirmap_desc *
diff --git a/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch
deleted file mode 100644
index a64d622981..0000000000
--- a/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:03 +0800
-Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
- paramter
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -800,6 +800,21 @@ static irqreturn_t mtk_spi_interrupt(int
- 	return IRQ_HANDLED;
- }
- 
-+static int mtk_spi_append_caldata(struct spi_controller *ctlr)
-+{
-+	struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
-+	struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
-+
-+	cal_target->cal_item = &mdata->get_tick_dly;
-+	cal_target->cal_min = 0;
-+	cal_target->cal_max = 7;
-+	cal_target->step = 1;
-+
-+	list_add(&cal_target->list, ctlr->cal_target);
-+
-+	return 0;
-+}
-+
- static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
- 				      struct spi_mem_op *op)
- {
-@@ -1092,6 +1107,7 @@ static int mtk_spi_probe(struct platform
- 	master->setup = mtk_spi_setup;
- 	master->set_cs_timing = mtk_spi_set_hw_cs_timing;
- 	master->use_gpio_descriptors = true;
-+	master->append_caldata = mtk_spi_append_caldata;
- 
- 	of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
- 	if (!of_id) {
diff --git a/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch
deleted file mode 100644
index e2684eebb7..0000000000
--- a/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:56 +0800
-Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
- spinand
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -977,6 +977,56 @@ static int spinand_manufacturer_match(st
- 	return -ENOTSUPP;
- }
- 
-+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
-+	struct spinand_device *spinand = (struct spinand_device *)priv;
-+	struct device *dev = &spinand->spimem->spi->dev;
-+	struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
-+	struct nand_pos pos;
-+	struct nand_page_io_req req;
-+	u8 status;
-+	int ret;
-+
-+	if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
-+		dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
-+		return -EINVAL;
-+	}
-+
-+	ret = spinand_reset_op(spinand);
-+	if (ret)
-+		return ret;
-+
-+	/* We should store our golden data in first target because
-+	 * we can't switch target at this moment.
-+	 */
-+	pos = (struct nand_pos){
-+		.target = 0,
-+		.lun = *addr,
-+		.plane = *(addr+1),
-+		.eraseblock = *(addr+2),
-+		.page = *(addr+3),
-+	};
-+
-+	req = (struct nand_page_io_req){
-+		.pos = pos,
-+		.dataoffs = *(addr+4),
-+		.datalen = readlen,
-+		.databuf.in = buf,
-+		.mode = MTD_OPS_AUTO_OOB,
-+	};
-+
-+	ret = spinand_load_page_op(spinand, &req);
-+	if (ret)
-+		return ret;
-+
-+	ret = spinand_wait(spinand, &status);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = spi_mem_exec_op(spinand->spimem, &op);
-+
-+	return 0;
-+}
-+
- static int spinand_id_detect(struct spinand_device *spinand)
- {
- 	u8 *id = spinand->id.data;
-@@ -1227,6 +1277,10 @@ static int spinand_init(struct spinand_d
- 	if (!spinand->scratchbuf)
- 		return -ENOMEM;
- 
-+	ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
-+	if (ret)
-+		dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
-+
- 	ret = spinand_detect(spinand);
- 	if (ret)
- 		goto err_free_bufs;
diff --git a/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch
deleted file mode 100644
index 61712982fb..0000000000
--- a/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:40:59 +0800
-Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
- spi-nor
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c |  5 ++++-
- drivers/mtd/spi-nor/core.c  | 15 +++++++++++++++
- 2 files changed, 19 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1018,7 +1018,10 @@ int spinand_cal_read(void *priv, u32 *ad
- 	if (ret)
- 		return ret;
- 
--	ret = spinand_wait(spinand, &status);
-+	ret = spinand_wait(spinand,
-+			   SPINAND_READ_INITIAL_DELAY_US,
-+			   SPINAND_READ_POLL_DELAY_US,
-+			   &status);
- 	if (ret < 0)
- 		return ret;
- 
---- a/drivers/mtd/spi-nor/core.c
-+++ b/drivers/mtd/spi-nor/core.c
-@@ -3061,6 +3061,18 @@ static void spi_nor_debugfs_init(struct
- 					 info->id_len, info->id);
- }
- 
-+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
-+{
-+	struct spi_nor *nor = (struct spi_nor *)priv;
-+
-+	nor->reg_proto = SNOR_PROTO_1_1_1;
-+	nor->read_proto = SNOR_PROTO_1_1_1;
-+	nor->read_opcode = SPINOR_OP_READ;
-+	nor->read_dummy = 0;
-+
-+	return nor->controller_ops->read(nor, *addr, readlen, buf);
-+}
-+
- static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
- 						       const char *name)
- {
-@@ -3134,6 +3146,9 @@ int spi_nor_scan(struct spi_nor *nor, co
- 	if (!nor->bouncebuf)
- 		return -ENOMEM;
- 
-+	if(nor->spimem)
-+		spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
-+
- 	info = spi_nor_get_flash_info(nor, name);
- 	if (IS_ERR(info))
- 		return PTR_ERR(info);
diff --git a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch
deleted file mode 100644
index 977bdeb5b1..0000000000
--- a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -364,6 +364,12 @@ config ROCKCHIP_PHY
- 	help
- 	  Currently supports the integrated Ethernet PHY.
- 
-+config RTL8367S_GSW
-+	tristate "rtl8367 Gigabit Switch support for mt7622"
-+	depends on NET_VENDOR_MEDIATEK
-+	help
-+	  This driver supports rtl8367s in mt7622
-+
- config SMSC_PHY
- 	tristate "SMSC PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -91,6 +91,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
- obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
- obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
- obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
-+obj-$(CONFIG_RTL8367S_GSW)	+= rtk/
- obj-$(CONFIG_SMSC_PHY)		+= smsc.o
- obj-$(CONFIG_STE10XP)		+= ste10Xp.o
- obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o
diff --git a/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch b/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch
deleted file mode 100644
index 6a84ff47db..0000000000
--- a/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch
+++ /dev/null
@@ -1,332 +0,0 @@
-From: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Date: Mon, 23 Aug 2021 11:27:59 +0800
-Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
-
-There are two independent PCIe controllers in MT2712 and MT7622
-platform. Each of them should contain an independent MSI domain.
-
-In old dts architecture, MSI domain will be inherited from the root
-bridge, and all of the devices will share the same MSI domain.
-Hence that, the PCIe devices will not work properly if the irq number
-which required is more than 32.
-
-Split the PCIe node for MT2712 and MT7622 platform to comply with
-the hardware design and fix MSI issue.
-
-Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Acked-by: Ryder Lee <ryder.lee@mediatek.com>
-Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-@@ -915,64 +915,67 @@
- 		};
- 	};
- 
--	pcie: pcie@11700000 {
-+	pcie1: pcie@112ff000 {
- 		compatible = "mediatek,mt2712-pcie";
- 		device_type = "pci";
--		reg = <0 0x11700000 0 0x1000>,
--		      <0 0x112ff000 0 0x1000>;
--		reg-names = "port0", "port1";
-+		reg = <0 0x112ff000 0 0x1000>;
-+		reg-names = "port1";
-+		linux,pci-domain = <1>;
- 		#address-cells = <3>;
- 		#size-cells = <2>;
--		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
--			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
--		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
--			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
--			 <&pericfg CLK_PERI_PCIE0>,
-+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "pcie_irq";
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
- 			 <&pericfg CLK_PERI_PCIE1>;
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
--		phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
--		phy-names = "pcie-phy0", "pcie-phy1";
-+		clock-names = "sys_ck1", "ahb_ck1";
-+		phys = <&u3port1 PHY_TYPE_PCIE>;
-+		phy-names = "pcie-phy1";
- 		bus-range = <0x00 0xff>;
--		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
-+		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
-+		status = "disabled";
- 
--		pcie0: pcie@0,0 {
--			device_type = "pci";
--			status = "disabled";
--			reg = <0x0000 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+				<0 0 0 2 &pcie_intc1 1>,
-+				<0 0 0 3 &pcie_intc1 2>,
-+				<0 0 0 4 &pcie_intc1 3>;
-+		pcie_intc1: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
- 			#interrupt-cells = <1>;
--			ranges;
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
--					<0 0 0 2 &pcie_intc0 1>,
--					<0 0 0 3 &pcie_intc0 2>,
--					<0 0 0 4 &pcie_intc0 3>;
--			pcie_intc0: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
- 		};
-+	};
-+
-+	pcie0: pcie@11700000 {
-+		compatible = "mediatek,mt2712-pcie";
-+		device_type = "pci";
-+		reg = <0 0x11700000 0 0x1000>;
-+		reg-names = "port0";
-+		linux,pci-domain = <0>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "pcie_irq";
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
-+			 <&pericfg CLK_PERI_PCIE0>;
-+		clock-names = "sys_ck0", "ahb_ck0";
-+		phys = <&u3port0 PHY_TYPE_PCIE>;
-+		phy-names = "pcie-phy0";
-+		bus-range = <0x00 0xff>;
-+		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+		status = "disabled";
- 
--		pcie1: pcie@1,0 {
--			device_type = "pci";
--			status = "disabled";
--			reg = <0x0800 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+				<0 0 0 2 &pcie_intc0 1>,
-+				<0 0 0 3 &pcie_intc0 2>,
-+				<0 0 0 4 &pcie_intc0 3>;
-+		pcie_intc0: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
- 			#interrupt-cells = <1>;
--			ranges;
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
--					<0 0 0 2 &pcie_intc1 1>,
--					<0 0 0 3 &pcie_intc1 2>,
--					<0 0 0 4 &pcie_intc1 3>;
--			pcie_intc1: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -302,18 +302,16 @@
- 	};
- };
- 
--&pcie {
-+&pcie0 {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+	pinctrl-0 = <&pcie0_pins>;
- 	status = "okay";
-+};
- 
--	pcie@0,0 {
--		status = "okay";
--	};
--
--	pcie@1,0 {
--		status = "okay";
--	};
-+&pcie1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie1_pins>;
-+	status = "okay";
- };
- 
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -232,18 +232,16 @@
- 	};
- };
- 
--&pcie {
-+&pcie0 {
- 	pinctrl-names = "default";
--	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+	pinctrl-0 = <&pcie0_pins>;
- 	status = "okay";
-+};
- 
--	pcie@0,0 {
--		status = "okay";
--	};
--
--	pcie@1,0 {
--		status = "okay";
--	};
-+&pcie1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie1_pins>;
-+	status = "okay";
- };
- 
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -809,75 +809,83 @@
- 		#reset-cells = <1>;
- 	};
- 
--	pcie: pcie@1a140000 {
-+	pciecfg: pciecfg@1a140000 {
-+		compatible = "mediatek,generic-pciecfg", "syscon";
-+		reg = <0 0x1a140000 0 0x1000>;
-+	};
-+
-+	pcie0: pcie@1a143000 {
- 		compatible = "mediatek,mt7622-pcie";
- 		device_type = "pci";
--		reg = <0 0x1a140000 0 0x1000>,
--		      <0 0x1a143000 0 0x1000>,
--		      <0 0x1a145000 0 0x1000>;
--		reg-names = "subsys", "port0", "port1";
-+		reg = <0 0x1a143000 0 0x1000>;
-+		reg-names = "port0";
-+		linux,pci-domain = <0>;
- 		#address-cells = <3>;
- 		#size-cells = <2>;
--		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "pcie_irq";
- 		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
--			 <&pciesys CLK_PCIE_P1_MAC_EN>,
--			 <&pciesys CLK_PCIE_P0_AHB_EN>,
- 			 <&pciesys CLK_PCIE_P0_AHB_EN>,
- 			 <&pciesys CLK_PCIE_P0_AUX_EN>,
--			 <&pciesys CLK_PCIE_P1_AUX_EN>,
- 			 <&pciesys CLK_PCIE_P0_AXI_EN>,
--			 <&pciesys CLK_PCIE_P1_AXI_EN>,
- 			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
--			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
--			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
--			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
--			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
--			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
-+			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
-+		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
-+			      "axi_ck0", "obff_ck0", "pipe_ck0";
-+
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- 		bus-range = <0x00 0xff>;
--		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- 		status = "disabled";
- 
--		pcie0: pcie@0,0 {
--			reg = <0x0000 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+				<0 0 0 2 &pcie_intc0 1>,
-+				<0 0 0 3 &pcie_intc0 2>,
-+				<0 0 0 4 &pcie_intc0 3>;
-+		pcie_intc0: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
- 			#interrupt-cells = <1>;
--			ranges;
--			status = "disabled";
--
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
--					<0 0 0 2 &pcie_intc0 1>,
--					<0 0 0 3 &pcie_intc0 2>,
--					<0 0 0 4 &pcie_intc0 3>;
--			pcie_intc0: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
- 		};
-+	};
- 
--		pcie1: pcie@1,0 {
--			reg = <0x0800 0 0 0 0>;
--			#address-cells = <3>;
--			#size-cells = <2>;
--			#interrupt-cells = <1>;
--			ranges;
--			status = "disabled";
-+	pcie1: pcie@1a145000 {
-+		compatible = "mediatek,mt7622-pcie";
-+		device_type = "pci";
-+		reg = <0 0x1a145000 0 0x1000>;
-+		reg-names = "port1";
-+		linux,pci-domain = <1>;
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "pcie_irq";
-+		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
-+			 /* designer has connect RC1 with p0_ahb clock */
-+			 <&pciesys CLK_PCIE_P0_AHB_EN>,
-+			 <&pciesys CLK_PCIE_P1_AUX_EN>,
-+			 <&pciesys CLK_PCIE_P1_AXI_EN>,
-+			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
-+			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
-+		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
-+			      "axi_ck1", "obff_ck1", "pipe_ck1";
-+
-+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
-+		bus-range = <0x00 0xff>;
-+		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
-+		status = "disabled";
- 
--			interrupt-map-mask = <0 0 0 7>;
--			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
--					<0 0 0 2 &pcie_intc1 1>,
--					<0 0 0 3 &pcie_intc1 2>,
--					<0 0 0 4 &pcie_intc1 3>;
--			pcie_intc1: interrupt-controller {
--				interrupt-controller;
--				#address-cells = <0>;
--				#interrupt-cells = <1>;
--			};
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+				<0 0 0 2 &pcie_intc1 1>,
-+				<0 0 0 3 &pcie_intc1 2>,
-+				<0 0 0 4 &pcie_intc1 3>;
-+		pcie_intc1: interrupt-controller {
-+			interrupt-controller;
-+			#address-cells = <0>;
-+			#interrupt-cells = <1>;
- 		};
- 	};
- 
diff --git a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
deleted file mode 100644
index b7311e042d..0000000000
--- a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From: qizhong cheng <qizhong.cheng@mediatek.com>
-Date: Mon, 27 Dec 2021 21:31:10 +0800
-Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
- stabilize
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-be delayed 100ms (TPVPERL) for the power and clock to become stable.
-
-Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
-Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Acked-by: Pali Rohár <pali@kernel.org>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
- 	 */
- 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
- 
-+	/*
-+	 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-+	 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-+	 * be delayed 100ms (TPVPERL) for the power and clock to become stable.
-+	 */
-+	msleep(100);
-+
- 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/
- 	val = readl(port->base + PCIE_RST_CTRL);
- 	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
diff --git a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
deleted file mode 100644
index bf479ab53b..0000000000
--- a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -849,6 +849,12 @@
- 			#address-cells = <0>;
- 			#interrupt-cells = <1>;
- 		};
-+
-+		slot0: pcie@0,0 {
-+			reg = <0x0000 0 0 0 0>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+		};
- 	};
- 
- 	pcie1: pcie@1a145000 {
-@@ -887,6 +893,12 @@
- 			#address-cells = <0>;
- 			#interrupt-cells = <1>;
- 		};
-+
-+		slot1: pcie@1,0 {
-+			reg = <0x0800 0 0 0 0>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+		};
- 	};
- 
- 	sata: sata@1a200000 {
diff --git a/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
deleted file mode 100644
index 252ef080f5..0000000000
--- a/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
+++ /dev/null
@@ -1,203 +0,0 @@
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-Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
- srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
- linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
- jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
- yong.wu@mediatek.com, bhelgaas@google.com,
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-
-From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
-
-Remove unused property and add pciecfg node.
-
-Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
----
- arch/arm/boot/dts/mt7629-rfb.dts |  3 ++-
- arch/arm/boot/dts/mt7629.dtsi    | 23 +++++++++++++----------
- 2 files changed, 15 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -149,9 +149,10 @@
- 	};
- };
- 
--&pcie {
-+&pcie1 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pcie_pins>;
-+	status = "okay";
- };
- 
- &pciephy1 {
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -382,16 +382,21 @@
- 			#reset-cells = <1>;
- 		};
- 
--		pcie: pcie@1a140000 {
-+		pciecfg: pciecfg@1a140000 {
-+			compatible = "mediatek,mt7629-pciecfg", "syscon";
-+			reg = <0x1a140000 0x1000>;
-+		};
-+
-+		pcie1: pcie@1a145000 {
- 			compatible = "mediatek,mt7629-pcie";
- 			device_type = "pci";
--			reg = <0x1a140000 0x1000>,
--			      <0x1a145000 0x1000>;
--			reg-names = "subsys","port1";
-+			reg = <0x1a145000 0x1000>;
-+			reg-names = "port1";
-+			mediatek,pcie-cfg = <&pciecfg>;
- 			#address-cells = <3>;
- 			#size-cells = <2>;
--			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
--				     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+			interrupt-names = "pcie_irq";
- 			clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
- 				 <&pciesys CLK_PCIE_P0_AHB_EN>,
- 				 <&pciesys CLK_PCIE_P1_AUX_EN>,
-@@ -412,21 +417,19 @@
- 			power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- 			bus-range = <0x00 0xff>;
- 			ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
-+			status = "disabled";
- 
--			pcie1: pcie@1,0 {
--				device_type = "pci";
-+			slot1: pcie@1,0 {
- 				reg = <0x0800 0 0 0 0>;
- 				#address-cells = <3>;
- 				#size-cells = <2>;
- 				#interrupt-cells = <1>;
- 				ranges;
--				num-lanes = <1>;
- 				interrupt-map-mask = <0 0 0 7>;
- 				interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- 						<0 0 0 2 &pcie_intc1 1>,
- 						<0 0 0 3 &pcie_intc1 2>,
- 						<0 0 0 4 &pcie_intc1 3>;
--
- 				pcie_intc1: interrupt-controller {
- 					interrupt-controller;
- 					#address-cells = <0>;
diff --git a/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch
deleted file mode 100644
index 2bebfddf5c..0000000000
--- a/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:33:27 +0200
-Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
-
-Clearing the status needs to happen after running the handler, otherwise
-we will get an extra spurious interrupt after the cause has been cleared
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -614,9 +614,9 @@ static void mtk_pcie_intr_handler(struct
- 	if (status & INTX_MASK) {
- 		for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
- 			/* Clear the INTx */
--			writel(1 << bit, port->base + PCIE_INT_STATUS);
- 			generic_handle_domain_irq(port->irq_domain,
- 						  bit - INTX_SHIFT);
-+			writel(1 << bit, port->base + PCIE_INT_STATUS);
- 		}
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch
deleted file mode 100644
index d526aded85..0000000000
--- a/target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -319,7 +319,13 @@ static int mtk_pcie_startup_port(struct
- 	msleep(100);
- 
- 	/* De-assert reset signals */
--	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
-+	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
-+	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
-+
-+	msleep(100);
-+
-+	/* De-assert PERST# signals */
-+	val &= ~(PCIE_PE_RSTB);
- 	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
- 
- 	/* Check if the link is up or not */
diff --git a/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch
deleted file mode 100644
index da33aaa72f..0000000000
--- a/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001
-From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
-Date: Tue, 4 Jan 2022 12:07:00 +0000
-Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and
- devad fields
-
-Add a couple of helpers and definitions to extract the clause 45 regad
-and devad fields from the regnum passed into MDIO drivers.
-
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- include/linux/mdio.h | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/include/linux/mdio.h
-+++ b/include/linux/mdio.h
-@@ -7,6 +7,7 @@
- #define __LINUX_MDIO_H__
- 
- #include <uapi/linux/mdio.h>
-+#include <linux/bitfield.h>
- #include <linux/mod_devicetable.h>
- 
- /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
-@@ -14,6 +15,7 @@
-  */
- #define MII_ADDR_C45		(1<<30)
- #define MII_DEVADDR_C45_SHIFT	16
-+#define MII_DEVADDR_C45_MASK	GENMASK(20, 16)
- #define MII_REGADDR_C45_MASK	GENMASK(15, 0)
- 
- struct gpio_desc;
-@@ -355,6 +357,16 @@ static inline u32 mdiobus_c45_addr(int d
- 	return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;
- }
- 
-+static inline u16 mdiobus_c45_regad(u32 regnum)
-+{
-+	return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
-+}
-+
-+static inline u16 mdiobus_c45_devad(u32 regnum)
-+{
-+	return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
-+}
-+
- static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
- 				     u16 regnum)
- {
diff --git a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch
deleted file mode 100644
index 3f73277aa6..0000000000
--- a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 4 Jan 2022 12:07:46 +0000
-Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
- access
-
-Implement read and write access to IEEE 802.3 Clause 45 Ethernet
-phy registers while making use of new mdiobus_c45_regad and
-mdiobus_c45_devad helpers.
-
-Tested on the Ubiquiti UniFi 6 LR access point featuring
-MediaTek MT7622BV WiSoC with Aquantia AQR112C.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +
- 2 files changed, 60 insertions(+), 13 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -324,13 +324,35 @@ static int _mtk_mdio_write(struct mtk_et
- 	if (ret < 0)
- 		return ret;
- 
--	mtk_w32(eth, PHY_IAC_ACCESS |
--		     PHY_IAC_START_C22 |
--		     PHY_IAC_CMD_WRITE |
--		     PHY_IAC_REG(phy_reg) |
--		     PHY_IAC_ADDR(phy_addr) |
--		     PHY_IAC_DATA(write_data),
--		MTK_PHY_IAC);
-+	if (phy_reg & MII_ADDR_C45) {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_C45_ADDR |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
-+			MTK_PHY_IAC);
-+
-+		ret = mtk_mdio_busy_wait(eth);
-+		if (ret < 0)
-+			return ret;
-+
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_WRITE |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(write_data),
-+			MTK_PHY_IAC);
-+	} else {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C22 |
-+			     PHY_IAC_CMD_WRITE |
-+			     PHY_IAC_REG(phy_reg) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(write_data),
-+			MTK_PHY_IAC);
-+	}
- 
- 	ret = mtk_mdio_busy_wait(eth);
- 	if (ret < 0)
-@@ -347,12 +369,33 @@ static int _mtk_mdio_read(struct mtk_eth
- 	if (ret < 0)
- 		return ret;
- 
--	mtk_w32(eth, PHY_IAC_ACCESS |
--		     PHY_IAC_START_C22 |
--		     PHY_IAC_CMD_C22_READ |
--		     PHY_IAC_REG(phy_reg) |
--		     PHY_IAC_ADDR(phy_addr),
--		MTK_PHY_IAC);
-+	if (phy_reg & MII_ADDR_C45) {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_C45_ADDR |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr) |
-+			     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
-+			MTK_PHY_IAC);
-+
-+		ret = mtk_mdio_busy_wait(eth);
-+		if (ret < 0)
-+			return ret;
-+
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C45 |
-+			     PHY_IAC_CMD_C45_READ |
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+			     PHY_IAC_ADDR(phy_addr),
-+			MTK_PHY_IAC);
-+	} else {
-+		mtk_w32(eth, PHY_IAC_ACCESS |
-+			     PHY_IAC_START_C22 |
-+			     PHY_IAC_CMD_C22_READ |
-+			     PHY_IAC_REG(phy_reg) |
-+			     PHY_IAC_ADDR(phy_addr),
-+			MTK_PHY_IAC);
-+	}
- 
- 	ret = mtk_mdio_busy_wait(eth);
- 	if (ret < 0)
-@@ -899,6 +942,7 @@ static int mtk_mdio_init(struct mtk_eth
- 	eth->mii_bus->name = "mdio";
- 	eth->mii_bus->read = mtk_mdio_read;
- 	eth->mii_bus->write = mtk_mdio_write;
-+	eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
- 	eth->mii_bus->priv = eth;
- 	eth->mii_bus->parent = eth->dev;
- 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -402,9 +402,12 @@
- #define PHY_IAC_ADDR_MASK	GENMASK(24, 20)
- #define PHY_IAC_ADDR(x)		FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
- #define PHY_IAC_CMD_MASK	GENMASK(19, 18)
-+#define PHY_IAC_CMD_C45_ADDR	FIELD_PREP(PHY_IAC_CMD_MASK, 0)
- #define PHY_IAC_CMD_WRITE	FIELD_PREP(PHY_IAC_CMD_MASK, 1)
- #define PHY_IAC_CMD_C22_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 2)
-+#define PHY_IAC_CMD_C45_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 3)
- #define PHY_IAC_START_MASK	GENMASK(17, 16)
-+#define PHY_IAC_START_C45	FIELD_PREP(PHY_IAC_START_MASK, 0)
- #define PHY_IAC_START_C22	FIELD_PREP(PHY_IAC_START_MASK, 1)
- #define PHY_IAC_DATA_MASK	GENMASK(15, 0)
- #define PHY_IAC_DATA(x)		FIELD_PREP(PHY_IAC_DATA_MASK, (x))
diff --git a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
deleted file mode 100644
index 76ee2fc89a..0000000000
--- a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:42:42 +0200
-Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
-
-It improves performance by eliminating the need for a cache flush for DMA on
-attached devices
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -837,6 +837,9 @@
- 		bus-range = <0x00 0xff>;
- 		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- 		status = "disabled";
-+		dma-coherent;
-+		mediatek,hifsys = <&hifsys>;
-+		mediatek,cci-control = <&cci_control2>;
- 
- 		#interrupt-cells = <1>;
- 		interrupt-map-mask = <0 0 0 7>;
-@@ -881,6 +884,9 @@
- 		bus-range = <0x00 0xff>;
- 		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
- 		status = "disabled";
-+		dma-coherent;
-+		mediatek,hifsys = <&hifsys>;
-+		mediatek,cci-control = <&cci_control2>;
- 
- 		#interrupt-cells = <1>;
- 		interrupt-map-mask = <0 0 0 7>;
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -20,6 +20,7 @@
- #include <linux/of_address.h>
- #include <linux/of_pci.h>
- #include <linux/of_platform.h>
-+#include <linux/of_address.h>
- #include <linux/pci.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
-@@ -139,6 +140,11 @@
- #define PCIE_LINK_STATUS_V2	0x804
- #define PCIE_PORT_LINKUP_V2	BIT(10)
- 
-+/* DMA channel mapping */
-+#define HIFSYS_DMA_AG_MAP	0x008
-+#define HIFSYS_DMA_AG_MAP_PCIE0	BIT(0)
-+#define HIFSYS_DMA_AG_MAP_PCIE1	BIT(1)
-+
- struct mtk_pcie_port;
- 
- /**
-@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
- 	struct mtk_pcie_port *port, *tmp;
- 	int err, slot;
- 
-+	if (of_dma_is_coherent(node)) {
-+		struct regmap *con;
-+		u32 mask;
-+
-+		con = syscon_regmap_lookup_by_phandle(node,
-+						      "mediatek,cci-control");
-+		/* enable CPU/bus coherency */
-+		if (!IS_ERR(con))
-+			regmap_write(con, 0, 3);
-+
-+		con = syscon_regmap_lookup_by_phandle(node,
-+						      "mediatek,hifsys");
-+		if (IS_ERR(con)) {
-+			dev_err(dev, "missing hifsys node\n");
-+			return PTR_ERR(con);
-+		}
-+
-+		mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
-+		regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
-+	}
-+
- 	slot = of_get_pci_domain_nr(dev->of_node);
- 	if (slot < 0) {
- 		for_each_available_child_of_node(node, child) {
diff --git a/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch
deleted file mode 100644
index f9a5fdbd0d..0000000000
--- a/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: Jip de Beer <gpk6x3591g0l@opayq.com>
-Date: Sun, 9 Jan 2022 13:14:04 +0100
-Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
-
-The lowest frequency should be 300MHz, since that is the label
-assigned to the OPP in the mt7622.dtsi device tree, while there is one
-missing zero in the actual value.
-
-To be clear, the lowest frequency should be 300MHz instead of 30MHz.
-
-As mentioned @dangowrt on the OpenWrt forum there is no benefit in
-leaving 30MHz as the lowest frequency.
-
-Signed-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>
-Signed-off-by: Fritz D. Ansel <fdansel@yandex.ru>
----
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -24,7 +24,7 @@
- 		compatible = "operating-points-v2";
- 		opp-shared;
- 		opp-300000000 {
--			opp-hz = /bits/ 64 <30000000>;
-+			opp-hz = /bits/ 64 <300000000>;
- 			opp-microvolt = <950000>;
- 		};
- 
diff --git a/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch
deleted file mode 100644
index 52069496ca..0000000000
--- a/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -23,11 +23,17 @@
- 	cpu_opp_table: opp-table {
- 		compatible = "operating-points-v2";
- 		opp-shared;
--		opp-300000000 {
--			opp-hz = /bits/ 64 <300000000>;
--			opp-microvolt = <950000>;
--		};
--
-+		/* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low
-+		 * voltage condition that can cause a hang when rebooting the RT3200/E8450.
-+		 *
-+		 * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490
-+		 *
-+		 * opp-300000000 {
-+		 *	opp-hz = /bits/ 64 <300000000>;
-+		 *	opp-microvolt = <950000>;
-+		 * };
-+		 *
-+		 */
- 		opp-437500000 {
- 			opp-hz = /bits/ 64 <437500000>;
- 			opp-microvolt = <1000000>;
diff --git a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
deleted file mode 100644
index 72ad2a9846..0000000000
--- a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
+++ /dev/null
@@ -1,1204 +0,0 @@
-From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 11 Jun 2023 00:48:10 +0100
-Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
-
-Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
-PHYs which require calibration data from the SoC's efuse.
-Despite the similar design the driver doesn't share any code with the
-existing mediatek-ge.c.
-Add support for such PHYs by introducing a new driver with basic
-support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- MAINTAINERS                       |    9 +
- drivers/net/phy/Kconfig           |   12 +
- drivers/net/phy/Makefile          |    1 +
- drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++
- drivers/net/phy/mediatek-ge.c     |    3 +-
- 5 files changed, 1140 insertions(+), 1 deletion(-)
- create mode 100644 drivers/net/phy/mediatek-ge-soc.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -11791,6 +11791,15 @@ S:	Maintained
- F:	drivers/net/pcs/pcs-mtk-lynxi.c
- F:	include/linux/pcs/pcs-mtk-lynxi.h
- 
-+MEDIATEK ETHERNET PHY DRIVERS
-+M:	Daniel Golle <daniel@makrotopia.org>
-+M:	Qingfang Deng <dqfext@gmail.com>
-+M:	SkyLake Huang <SkyLake.Huang@mediatek.com>
-+L:	netdev@vger.kernel.org
-+S:	Maintained
-+F:	drivers/net/phy/mediatek-ge-soc.c
-+F:	drivers/net/phy/mediatek-ge.c
-+
- MEDIATEK I2C CONTROLLER DRIVER
- M:	Qii Wang <qii.wang@mediatek.com>
- L:	linux-i2c@vger.kernel.org
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -290,6 +290,18 @@ config MEDIATEK_GE_PHY
- 	help
- 	  Supports the MediaTek Gigabit Ethernet PHYs.
- 
-+config MEDIATEK_GE_SOC_PHY
-+	tristate "MediaTek SoC Ethernet PHYs"
-+	depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
-+	select NVMEM_MTK_EFUSE
-+	help
-+	  Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
-+
-+	  Include support for built-in Ethernet PHYs which are present in
-+	  the MT7981 and MT7988 SoCs. These PHYs need calibration data
-+	  present in the SoCs efuse and will dynamically calibrate VCM
-+	  (common-mode voltage) during startup.
-+
- config MICREL_PHY
- 	tristate "Micrel PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -77,6 +77,7 @@ obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
- obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o
-+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY)	+= meson-gxl.o
- obj-$(CONFIG_MICREL_KS8995MA)	+= spi_ks8995.o
- obj-$(CONFIG_MICREL_PHY)	+= micrel.o
---- /dev/null
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -0,0 +1,1116 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+#include <linux/bitfield.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_address.h>
-+#include <linux/of_platform.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/phy.h>
-+
-+#define MTK_GPHY_ID_MT7981			0x03a29461
-+#define MTK_GPHY_ID_MT7988			0x03a29481
-+
-+#define MTK_EXT_PAGE_ACCESS			0x1f
-+#define MTK_PHY_PAGE_STANDARD			0x0000
-+#define MTK_PHY_PAGE_EXTENDED_3			0x0003
-+
-+#define MTK_PHY_LPI_REG_14			0x14
-+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK	GENMASK(8, 0)
-+
-+#define MTK_PHY_LPI_REG_1c			0x1c
-+#define MTK_PHY_SMI_DET_ON_THRESH_MASK		GENMASK(13, 8)
-+
-+#define MTK_PHY_PAGE_EXTENDED_2A30		0x2a30
-+#define MTK_PHY_PAGE_EXTENDED_52B5		0x52b5
-+
-+#define ANALOG_INTERNAL_OPERATION_MAX_US	20
-+#define TXRESERVE_MIN				0
-+#define TXRESERVE_MAX				7
-+
-+#define MTK_PHY_ANARG_RG			0x10
-+#define   MTK_PHY_TCLKOFFSET_MASK		GENMASK(12, 8)
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define MTK_PHY_TXVLD_DA_RG			0x12
-+#define   MTK_PHY_DA_TX_I2MPB_A_GBE_MASK	GENMASK(15, 10)
-+#define   MTK_PHY_DA_TX_I2MPB_A_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2		0x16
-+#define   MTK_PHY_DA_TX_I2MPB_A_HBT_MASK	GENMASK(15, 10)
-+#define   MTK_PHY_DA_TX_I2MPB_A_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1		0x17
-+#define   MTK_PHY_DA_TX_I2MPB_B_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_B_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2		0x18
-+#define   MTK_PHY_DA_TX_I2MPB_B_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_B_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1		0x19
-+#define   MTK_PHY_DA_TX_I2MPB_C_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_C_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2		0x20
-+#define   MTK_PHY_DA_TX_I2MPB_C_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_C_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1		0x21
-+#define   MTK_PHY_DA_TX_I2MPB_D_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_D_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2		0x22
-+#define   MTK_PHY_DA_TX_I2MPB_D_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_D_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_RXADC_CTRL_RG7			0xc6
-+#define   MTK_PHY_DA_AD_BUF_BIAS_LP_MASK	GENMASK(9, 8)
-+
-+#define MTK_PHY_RXADC_CTRL_RG9			0xc8
-+#define   MTK_PHY_DA_RX_PSBN_TBT_MASK		GENMASK(14, 12)
-+#define   MTK_PHY_DA_RX_PSBN_HBT_MASK		GENMASK(10, 8)
-+#define   MTK_PHY_DA_RX_PSBN_GBE_MASK		GENMASK(6, 4)
-+#define   MTK_PHY_DA_RX_PSBN_LP_MASK		GENMASK(2, 0)
-+
-+#define MTK_PHY_LDO_OUTPUT_V			0xd7
-+
-+#define MTK_PHY_RG_ANA_CAL_RG0			0xdb
-+#define   MTK_PHY_RG_CAL_CKINV			BIT(12)
-+#define   MTK_PHY_RG_ANA_CALEN			BIT(8)
-+#define   MTK_PHY_RG_ZCALEN_A			BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG1			0xdc
-+#define   MTK_PHY_RG_ZCALEN_B			BIT(12)
-+#define   MTK_PHY_RG_ZCALEN_C			BIT(8)
-+#define   MTK_PHY_RG_ZCALEN_D			BIT(4)
-+#define   MTK_PHY_RG_TXVOS_CALEN		BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG5			0xe0
-+#define   MTK_PHY_RG_REXT_TRIM_MASK		GENMASK(13, 8)
-+
-+#define MTK_PHY_RG_TX_FILTER			0xfe
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120	0x120
-+#define   MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK	GENMASK(12, 8)
-+#define   MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK	GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122	0x122
-+#define   MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK	GENMASK(7, 0)
-+
-+#define MTK_PHY_RG_TESTMUX_ADC_CTRL		0x144
-+#define   MTK_PHY_RG_TXEN_DIG_MASK		GENMASK(5, 5)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B		0x172
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_A_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_B_MASK	GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D		0x173
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_C_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_D_MASK	GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_AD_CAL_COMP			0x17a
-+#define   MTK_PHY_AD_CAL_COMP_OUT_SHIFT		(8)
-+
-+#define MTK_PHY_RG_AD_CAL_CLK			0x17b
-+#define   MTK_PHY_DA_CAL_CLK			BIT(0)
-+
-+#define MTK_PHY_RG_AD_CALIN			0x17c
-+#define   MTK_PHY_DA_CALIN_FLAG			BIT(0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_A		0x17d
-+#define   MTK_PHY_DASN_DAC_IN0_A_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_B		0x17e
-+#define   MTK_PHY_DASN_DAC_IN0_B_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_C		0x17f
-+#define   MTK_PHY_DASN_DAC_IN0_C_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_D		0x180
-+#define   MTK_PHY_DASN_DAC_IN0_D_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_A		0x181
-+#define   MTK_PHY_DASN_DAC_IN1_A_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_B		0x182
-+#define   MTK_PHY_DASN_DAC_IN1_B_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_C		0x183
-+#define   MTK_PHY_DASN_DAC_IN1_C_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_D		0x184
-+#define   MTK_PHY_DASN_DAC_IN1_D_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG19b			0x19b
-+#define   MTK_PHY_BYPASS_DSP_LPI_READY		BIT(8)
-+
-+#define MTK_PHY_RG_LP_IIR2_K1_L			0x22a
-+#define MTK_PHY_RG_LP_IIR2_K1_U			0x22b
-+#define MTK_PHY_RG_LP_IIR2_K2_L			0x22c
-+#define MTK_PHY_RG_LP_IIR2_K2_U			0x22d
-+#define MTK_PHY_RG_LP_IIR2_K3_L			0x22e
-+#define MTK_PHY_RG_LP_IIR2_K3_U			0x22f
-+#define MTK_PHY_RG_LP_IIR2_K4_L			0x230
-+#define MTK_PHY_RG_LP_IIR2_K4_U			0x231
-+#define MTK_PHY_RG_LP_IIR2_K5_L			0x232
-+#define MTK_PHY_RG_LP_IIR2_K5_U			0x233
-+
-+#define MTK_PHY_RG_DEV1E_REG234			0x234
-+#define   MTK_PHY_TR_OPEN_LOOP_EN_MASK		GENMASK(0, 0)
-+#define   MTK_PHY_LPF_X_AVERAGE_MASK		GENMASK(7, 4)
-+#define   MTK_PHY_TR_LP_IIR_EEE_EN		BIT(12)
-+
-+#define MTK_PHY_RG_LPF_CNT_VAL			0x235
-+
-+#define MTK_PHY_RG_DEV1E_REG238			0x238
-+#define   MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK	GENMASK(8, 0)
-+#define   MTK_PHY_LPI_SLV_SEND_TX_EN		BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG239			0x239
-+#define   MTK_PHY_LPI_SEND_LOC_TIMER_MASK	GENMASK(8, 0)
-+#define   MTK_PHY_LPI_TXPCS_LOC_RCV		BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG27C			0x27c
-+#define   MTK_PHY_VGASTATE_FFE_THR_ST1_MASK	GENMASK(12, 8)
-+#define MTK_PHY_RG_DEV1E_REG27D			0x27d
-+#define   MTK_PHY_VGASTATE_FFE_THR_ST2_MASK	GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG2C7			0x2c7
-+#define   MTK_PHY_MAX_GAIN_MASK			GENMASK(4, 0)
-+#define   MTK_PHY_MIN_GAIN_MASK			GENMASK(12, 8)
-+
-+#define MTK_PHY_RG_DEV1E_REG2D1			0x2d1
-+#define   MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK	GENMASK(7, 0)
-+#define   MTK_PHY_LPI_SKIP_SD_SLV_TR		BIT(8)
-+#define   MTK_PHY_LPI_TR_READY			BIT(9)
-+#define   MTK_PHY_LPI_VCO_EEE_STG0_EN		BIT(10)
-+
-+#define MTK_PHY_RG_DEV1E_REG323			0x323
-+#define   MTK_PHY_EEE_WAKE_MAS_INT_DC		BIT(0)
-+#define   MTK_PHY_EEE_WAKE_SLV_INT_DC		BIT(4)
-+
-+#define MTK_PHY_RG_DEV1E_REG324			0x324
-+#define   MTK_PHY_SMI_DETCNT_MAX_MASK		GENMASK(5, 0)
-+#define   MTK_PHY_SMI_DET_MAX_EN		BIT(8)
-+
-+#define MTK_PHY_RG_DEV1E_REG326			0x326
-+#define   MTK_PHY_LPI_MODE_SD_ON		BIT(0)
-+#define   MTK_PHY_RESET_RANDUPD_CNT		BIT(1)
-+#define   MTK_PHY_TREC_UPDATE_ENAB_CLR		BIT(2)
-+#define   MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF	BIT(4)
-+#define   MTK_PHY_TR_READY_SKIP_AFE_WAKEUP	BIT(5)
-+
-+#define MTK_PHY_LDO_PUMP_EN_PAIRAB		0x502
-+#define MTK_PHY_LDO_PUMP_EN_PAIRCD		0x503
-+
-+#define MTK_PHY_DA_TX_R50_PAIR_A		0x53d
-+#define MTK_PHY_DA_TX_R50_PAIR_B		0x53e
-+#define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
-+#define MTK_PHY_DA_TX_R50_PAIR_D		0x540
-+
-+#define MTK_PHY_RG_BG_RASEL			0x115
-+#define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
-+
-+/* These macro privides efuse parsing for internal phy. */
-+#define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_C(x)			(((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_D(x)			(((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_A(x)		(((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_AMP_OFFSET_B(x)		(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_C(x)		(((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_D(x)		(((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_A(x)			(((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_B(x)			(((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_R50_C(x)			(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_D(x)			(((x) >> 6) & GENMASK(5, 0))
-+
-+#define EFS_RG_BG_RASEL(x)			(((x) >> 4) & GENMASK(2, 0))
-+#define EFS_RG_REXT_TRIM(x)			(((x) >> 7) & GENMASK(5, 0))
-+
-+enum {
-+	NO_PAIR,
-+	PAIR_A,
-+	PAIR_B,
-+	PAIR_C,
-+	PAIR_D,
-+};
-+
-+enum {
-+	GPHY_PORT0,
-+	GPHY_PORT1,
-+	GPHY_PORT2,
-+	GPHY_PORT3,
-+};
-+
-+enum calibration_mode {
-+	EFUSE_K,
-+	SW_K
-+};
-+
-+enum CAL_ITEM {
-+	REXT,
-+	TX_OFFSET,
-+	TX_AMP,
-+	TX_R50,
-+	TX_VCM
-+};
-+
-+enum CAL_MODE {
-+	EFUSE_M,
-+	SW_M
-+};
-+
-+static int mtk_socphy_read_page(struct phy_device *phydev)
-+{
-+	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-+}
-+
-+static int mtk_socphy_write_page(struct phy_device *phydev, int page)
-+{
-+	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-+}
-+
-+/* One calibration cycle consists of:
-+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
-+ *   until AD_CAL_COMP is ready to output calibration result.
-+ * 2.Wait until DA_CAL_CLK is available.
-+ * 3.Fetch AD_CAL_COMP_OUT.
-+ */
-+static int cal_cycle(struct phy_device *phydev, int devad,
-+		     u32 regnum, u16 mask, u16 cal_val)
-+{
-+	int reg_val;
-+	int ret;
-+
-+	phy_modify_mmd(phydev, devad, regnum,
-+		       mask, cal_val);
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+			 MTK_PHY_DA_CALIN_FLAG);
-+
-+	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+					MTK_PHY_RG_AD_CAL_CLK, reg_val,
-+					reg_val & MTK_PHY_DA_CAL_CLK, 500,
-+					ANALOG_INTERNAL_OPERATION_MAX_US, false);
-+	if (ret) {
-+		phydev_err(phydev, "Calibration cycle timeout\n");
-+		return ret;
-+	}
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+			   MTK_PHY_DA_CALIN_FLAG);
-+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
-+			   MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
-+	phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
-+
-+	return ret;
-+}
-+
-+static int rext_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
-+		       MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
-+		       MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
-+
-+	return 0;
-+}
-+
-+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 rext_cal_val[2];
-+
-+	rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
-+	rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
-+	rext_fill_result(phydev, rext_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
-+
-+	return 0;
-+}
-+
-+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 tx_offset_cal_val[4];
-+
-+	tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
-+	tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
-+	tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
-+	tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
-+
-+	tx_offset_fill_result(phydev, tx_offset_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	int i;
-+	int bias[16] = {};
-+	const int vals_9461[16] = { 7, 1, 4, 7,
-+				    7, 1, 4, 7,
-+				    7, 1, 4, 7,
-+				    7, 1, 4, 7 };
-+	const int vals_9481[16] = { 10, 6, 6, 10,
-+				    10, 6, 6, 10,
-+				    10, 6, 6, 10,
-+				    10, 6, 6, 10 };
-+	switch (phydev->drv->phy_id) {
-+	case MTK_GPHY_ID_MT7981:
-+		/* We add some calibration to efuse values
-+		 * due to board level influence.
-+		 * GBE: +7, TBT: +1, HBT: +4, TST: +7
-+		 */
-+		memcpy(bias, (const void *)vals_9461, sizeof(bias));
-+		break;
-+	case MTK_GPHY_ID_MT7988:
-+		memcpy(bias, (const void *)vals_9481, sizeof(bias));
-+		break;
-+	}
-+
-+	/* Prevent overflow */
-+	for (i = 0; i < 12; i++) {
-+		if (buf[i >> 2] + bias[i] > 63) {
-+			buf[i >> 2] = 63;
-+			bias[i] = 0;
-+		}
-+	}
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+		       MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+		       MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+		       MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+		       MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+		       MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+		       MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+		       MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+		       MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+		       MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+		       MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+		       MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+		       MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+		       MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+		       MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+		       MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+		       MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
-+
-+	return 0;
-+}
-+
-+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 tx_amp_cal_val[4];
-+
-+	tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
-+	tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
-+	tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
-+	tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
-+	tx_amp_fill_result(phydev, tx_amp_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
-+			      u8 txg_calen_x)
-+{
-+	int bias = 0;
-+	u16 reg, val;
-+
-+	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
-+		bias = -2;
-+
-+	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
-+
-+	switch (txg_calen_x) {
-+	case PAIR_A:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_A;
-+		break;
-+	case PAIR_B:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_B;
-+		break;
-+	case PAIR_C:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_C;
-+		break;
-+	case PAIR_D:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_D;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
-+
-+	return 0;
-+}
-+
-+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
-+			    u8 txg_calen_x)
-+{
-+	u16 tx_r50_cal_val;
-+
-+	switch (txg_calen_x) {
-+	case PAIR_A:
-+		tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
-+		break;
-+	case PAIR_B:
-+		tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
-+		break;
-+	case PAIR_C:
-+		tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
-+		break;
-+	case PAIR_D:
-+		tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+	tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
-+
-+	return 0;
-+}
-+
-+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
-+{
-+	u8 lower_idx, upper_idx, txreserve_val;
-+	u8 lower_ret, upper_ret;
-+	int ret;
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			 MTK_PHY_RG_ANA_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_CAL_CKINV);
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			 MTK_PHY_RG_TXVOS_CALEN);
-+
-+	switch (rg_txreserve_x) {
-+	case PAIR_A:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_A,
-+				   MTK_PHY_DASN_DAC_IN0_A_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_A,
-+				   MTK_PHY_DASN_DAC_IN1_A_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG0,
-+				 MTK_PHY_RG_ZCALEN_A);
-+		break;
-+	case PAIR_B:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_B,
-+				   MTK_PHY_DASN_DAC_IN0_B_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_B,
-+				   MTK_PHY_DASN_DAC_IN1_B_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_B);
-+		break;
-+	case PAIR_C:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_C,
-+				   MTK_PHY_DASN_DAC_IN0_C_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_C,
-+				   MTK_PHY_DASN_DAC_IN1_C_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_C);
-+		break;
-+	case PAIR_D:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_D,
-+				   MTK_PHY_DASN_DAC_IN0_D_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_D,
-+				   MTK_PHY_DASN_DAC_IN1_D_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_D);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		goto restore;
-+	}
-+
-+	lower_idx = TXRESERVE_MIN;
-+	upper_idx = TXRESERVE_MAX;
-+
-+	phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
-+	while ((upper_idx - lower_idx) > 1) {
-+		txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
-+		ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+				MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				txreserve_val << 12 | txreserve_val << 8 |
-+				txreserve_val << 4 | txreserve_val);
-+		if (ret == 1) {
-+			upper_idx = txreserve_val;
-+			upper_ret = ret;
-+		} else if (ret == 0) {
-+			lower_idx = txreserve_val;
-+			lower_ret = ret;
-+		} else {
-+			goto restore;
-+		}
-+	}
-+
-+	if (lower_idx == TXRESERVE_MIN) {
-+		lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+				      MTK_PHY_RXADC_CTRL_RG9,
-+				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				      lower_idx << 12 | lower_idx << 8 |
-+				      lower_idx << 4 | lower_idx);
-+		ret = lower_ret;
-+	} else if (upper_idx == TXRESERVE_MAX) {
-+		upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+				      MTK_PHY_RXADC_CTRL_RG9,
-+				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				      upper_idx << 12 | upper_idx << 8 |
-+				      upper_idx << 4 | upper_idx);
-+		ret = upper_ret;
-+	}
-+	if (ret < 0)
-+		goto restore;
-+
-+	/* We calibrate TX-VCM in different logic. Check upper index and then
-+	 * lower index. If this calibration is valid, apply lower index's result.
-+	 */
-+	ret = upper_ret - lower_ret;
-+	if (ret == 1) {
-+		ret = 0;
-+		/* Make sure we use upper_idx in our calibration system */
-+		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-+			  upper_idx << 12 | upper_idx << 8 |
-+			  upper_idx << 4 | upper_idx);
-+		phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
-+	} else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
-+		   lower_ret == 1) {
-+		ret = 0;
-+		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-+			  lower_idx << 12 | lower_idx << 8 |
-+			  lower_idx << 4 | lower_idx);
-+		phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
-+			    lower_idx);
-+	} else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
-+		   lower_ret == 0) {
-+		ret = 0;
-+		phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
-+			    upper_idx);
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+restore:
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_ANA_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			   MTK_PHY_RG_TXVOS_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_ZCALEN_A);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			   MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
-+			   MTK_PHY_RG_ZCALEN_D);
-+
-+	return ret;
-+}
-+
-+static void mt798x_phy_common_finetune(struct phy_device *phydev)
-+{
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* EnabRandUpdTrig = 1 */
-+	__phy_write(phydev, 0x11, 0x2f00);
-+	__phy_write(phydev, 0x12, 0xe);
-+	__phy_write(phydev, 0x10, 0x8fb0);
-+
-+	/* NormMseLoThresh = 85 */
-+	__phy_write(phydev, 0x11, 0x55a0);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x83aa);
-+
-+	/* TrFreeze = 0 */
-+	__phy_write(phydev, 0x11, 0x0);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9686);
-+
-+	/* SSTrKp1000Slv = 5 */
-+	__phy_write(phydev, 0x11, 0xbaef);
-+	__phy_write(phydev, 0x12, 0x2e);
-+	__phy_write(phydev, 0x10, 0x968c);
-+
-+	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
-+	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-+	 */
-+	__phy_write(phydev, 0x11, 0xd10a);
-+	__phy_write(phydev, 0x12, 0x34);
-+	__phy_write(phydev, 0x10, 0x8f82);
-+
-+	/* VcoSlicerThreshBitsHigh */
-+	__phy_write(phydev, 0x11, 0x5555);
-+	__phy_write(phydev, 0x12, 0x55);
-+	__phy_write(phydev, 0x10, 0x8ec0);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-+
-+	/* rg_tr_lpf_cnt_val = 512 */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-+
-+	/* IIR2 related */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
-+
-+	/* FFE peaking */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
-+		       MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
-+		       MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
-+
-+	/* Disable LDO pump */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
-+	/* Adjust LDO output voltage */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[8] = { 0x01ce, 0x01c1,
-+		       0x020f, 0x0202,
-+		       0x03d0, 0x03c0,
-+		       0x0013, 0x0005 };
-+	int i, k;
-+
-+	/* 100M eye finetune:
-+	 * Keep middle level of TX MLT3 shapper as default.
-+	 * Only change TX MLT3 overshoot level here.
-+	 */
-+	for (k = 0, i = 1; i < 12; i++) {
-+		if (i % 3 == 0)
-+			continue;
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+	}
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+	__phy_write(phydev, 0x11, 0xc71);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
-+	/* ResetSyncOffset = 6 */
-+	__phy_write(phydev, 0x11, 0x600);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate = 1 */
-+	__phy_write(phydev, 0x11, 0x4c2a);
-+	__phy_write(phydev, 0x12, 0x3e);
-+	__phy_write(phydev, 0x10, 0x8fa4);
-+
-+	/* FfeUpdGainForce = 4 */
-+	__phy_write(phydev, 0x11, 0x240);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9680);
-+
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7988_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-+			0x020d, 0x0206, 0x0384, 0x03d0,
-+			0x03c6, 0x030a, 0x0011, 0x0005 };
-+	int i;
-+
-+	/* Set default MLT3 shaper first */
-+	for (i = 0; i < 12; i++)
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
-+
-+	/* TCT finetune */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-+
-+	/* Disable TX power saving */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
-+	__phy_write(phydev, 0x11, 0x671);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
-+	/* ResetSyncOffset = 5 */
-+	__phy_write(phydev, 0x11, 0x500);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate is 1 at default on mt7988 */
-+
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
-+	/* TxClkOffset = 2 */
-+	__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
-+		     FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt798x_phy_eee(struct phy_device *phydev)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
-+		       MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
-+		       MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
-+		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+				  0xff));
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			   MTK_PHY_RG_TESTMUX_ADC_CTRL,
-+			   MTK_PHY_RG_TXEN_DIG_MASK);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			   MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
-+		       MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
-+		       MTK_PHY_LPI_SLV_SEND_TX_EN,
-+		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+		       MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
-+		       MTK_PHY_LPI_TXPCS_LOC_RCV,
-+		       FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
-+		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
-+		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-+		       FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
-+		       MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+		       FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+				  0x33) |
-+		       MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
-+		       MTK_PHY_LPI_VCO_EEE_STG0_EN);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
-+			 MTK_PHY_EEE_WAKE_MAS_INT_DC |
-+			 MTK_PHY_EEE_WAKE_SLV_INT_DC);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
-+		       MTK_PHY_SMI_DETCNT_MAX_MASK,
-+		       FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
-+		       MTK_PHY_SMI_DET_MAX_EN);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
-+			 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
-+			 MTK_PHY_TREC_UPDATE_ENAB_CLR |
-+			 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
-+			 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* Regsigdet_sel_1000 = 0 */
-+	__phy_write(phydev, 0x11, 0xb);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9690);
-+
-+	/* REG_EEE_st2TrKf1000 = 3 */
-+	__phy_write(phydev, 0x11, 0x114f);
-+	__phy_write(phydev, 0x12, 0x2);
-+	__phy_write(phydev, 0x10, 0x969a);
-+
-+	/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
-+	__phy_write(phydev, 0x11, 0x3028);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x969e);
-+
-+	/* RegEEE_slv_wake_int_timer_tar = 8 */
-+	__phy_write(phydev, 0x11, 0x5010);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96a0);
-+
-+	/* RegEEE_trfreeze_timer2 = 586 */
-+	__phy_write(phydev, 0x11, 0x24a);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96a8);
-+
-+	/* RegEEE100Stg1_tar = 16 */
-+	__phy_write(phydev, 0x11, 0x3210);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96b8);
-+
-+	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+	__phy_write(phydev, 0x11, 0x1463);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96ca);
-+
-+	/* DfeTailEnableVgaThresh1000 = 27 */
-+	__phy_write(phydev, 0x11, 0x36);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8f80);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
-+	__phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
-+		     FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
-+
-+	__phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
-+		     FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
-+}
-+
-+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		  u8 start_pair, u8 end_pair)
-+{
-+	u8 pair_n;
-+	int ret;
-+
-+	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+		/* TX_OFFSET & TX_AMP have no SW calibration. */
-+		switch (cal_item) {
-+		case TX_VCM:
-+			ret = tx_vcm_cal_sw(phydev, pair_n);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		if (ret)
-+			return ret;
-+	}
-+	return 0;
-+}
-+
-+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		     u8 start_pair, u8 end_pair, u32 *buf)
-+{
-+	u8 pair_n;
-+	int ret;
-+
-+	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+		/* TX_VCM has no efuse calibration. */
-+		switch (cal_item) {
-+		case REXT:
-+			ret = rext_cal_efuse(phydev, buf);
-+			break;
-+		case TX_OFFSET:
-+			ret = tx_offset_cal_efuse(phydev, buf);
-+			break;
-+		case TX_AMP:
-+			ret = tx_amp_cal_efuse(phydev, buf);
-+			break;
-+		case TX_R50:
-+			ret = tx_r50_cal_efuse(phydev, buf, pair_n);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		     enum CAL_MODE cal_mode, u8 start_pair,
-+		     u8 end_pair, u32 *buf)
-+{
-+	int ret;
-+
-+	switch (cal_mode) {
-+	case EFUSE_M:
-+		ret = cal_efuse(phydev, cal_item, start_pair,
-+				end_pair, buf);
-+		break;
-+	case SW_M:
-+		ret = cal_sw(phydev, cal_item, start_pair, end_pair);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	if (ret) {
-+		phydev_err(phydev, "cal %d failed\n", cal_item);
-+		return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mt798x_phy_calibration(struct phy_device *phydev)
-+{
-+	int ret = 0;
-+	u32 *buf;
-+	size_t len;
-+	struct nvmem_cell *cell;
-+
-+	cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
-+	if (IS_ERR(cell)) {
-+		if (PTR_ERR(cell) == -EPROBE_DEFER)
-+			return PTR_ERR(cell);
-+		return 0;
-+	}
-+
-+	buf = (u32 *)nvmem_cell_read(cell, &len);
-+	if (IS_ERR(buf))
-+		return PTR_ERR(buf);
-+	nvmem_cell_put(cell);
-+
-+	if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
-+		phydev_err(phydev, "invalid efuse data\n");
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
-+	if (ret)
-+		goto out;
-+
-+out:
-+	kfree(buf);
-+	return ret;
-+}
-+
-+static int mt798x_phy_config_init(struct phy_device *phydev)
-+{
-+	switch (phydev->drv->phy_id) {
-+	case MTK_GPHY_ID_MT7981:
-+		mt7981_phy_finetune(phydev);
-+		break;
-+	case MTK_GPHY_ID_MT7988:
-+		mt7988_phy_finetune(phydev);
-+		break;
-+	}
-+
-+	mt798x_phy_common_finetune(phydev);
-+	mt798x_phy_eee(phydev);
-+
-+	return mt798x_phy_calibration(phydev);
-+}
-+
-+static struct phy_driver mtk_socphy_driver[] = {
-+	{
-+		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-+		.name		= "MediaTek MT7981 PHY",
-+		.config_init	= mt798x_phy_config_init,
-+		.config_intr	= genphy_no_config_intr,
-+		.handle_interrupt = genphy_handle_interrupt_no_ack,
-+		.probe		= mt798x_phy_calibration,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+		.read_page	= mtk_socphy_read_page,
-+		.write_page	= mtk_socphy_write_page,
-+	},
-+	{
-+		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
-+		.name		= "MediaTek MT7988 PHY",
-+		.config_init	= mt798x_phy_config_init,
-+		.config_intr	= genphy_no_config_intr,
-+		.handle_interrupt = genphy_handle_interrupt_no_ack,
-+		.probe		= mt798x_phy_calibration,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+		.read_page	= mtk_socphy_read_page,
-+		.write_page	= mtk_socphy_write_page,
-+	},
-+};
-+
-+module_phy_driver(mtk_socphy_driver);
-+
-+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
-+	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
-+	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
-+	{ }
-+};
-+
-+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
-+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
-+MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
---- a/drivers/net/phy/mediatek-ge.c
-+++ b/drivers/net/phy/mediatek-ge.c
-@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
- module_phy_driver(mtk_gephy_driver);
- 
- static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
--	{ PHY_ID_MATCH_VENDOR(0x03a29400) },
-+	{ PHY_ID_MATCH_EXACT(0x03a29441) },
-+	{ PHY_ID_MATCH_EXACT(0x03a29412) },
- 	{ }
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch
deleted file mode 100644
index 83d0f26bf4..0000000000
--- a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch
+++ /dev/null
@@ -1,213 +0,0 @@
-From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 13 Jun 2023 03:27:14 +0100
-Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default
- state
-
-Initialize LEDs and set sane default values.
-Read boottrap register and apply LED polarities accordingly to get
-uniform behavior from all LEDs on MT7988.
-Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus
-which should point to the syscon holding the boottrap register.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++--
- 1 file changed, 136 insertions(+), 8 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -1,11 +1,13 @@
- // SPDX-License-Identifier: GPL-2.0+
- #include <linux/bitfield.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of_address.h>
- #include <linux/of_platform.h>
- #include <linux/pinctrl/consumer.h>
- #include <linux/phy.h>
-+#include <linux/regmap.h>
- 
- #define MTK_GPHY_ID_MT7981			0x03a29461
- #define MTK_GPHY_ID_MT7988			0x03a29481
-@@ -208,9 +210,40 @@
- #define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
- #define MTK_PHY_DA_TX_R50_PAIR_D		0x540
- 
-+/* Registers on MDIO_MMD_VEND2 */
-+#define MTK_PHY_LED0_ON_CTRL			0x24
-+#define MTK_PHY_LED1_ON_CTRL			0x26
-+#define   MTK_PHY_LED_ON_MASK			GENMASK(6, 0)
-+#define   MTK_PHY_LED_ON_LINK1000		BIT(0)
-+#define   MTK_PHY_LED_ON_LINK100		BIT(1)
-+#define   MTK_PHY_LED_ON_LINK10			BIT(2)
-+#define   MTK_PHY_LED_ON_LINKDOWN		BIT(3)
-+#define   MTK_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
-+#define   MTK_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
-+#define   MTK_PHY_LED_FORCE_ON			BIT(6)
-+#define   MTK_PHY_LED_POLARITY			BIT(14)
-+#define   MTK_PHY_LED_ENABLE			BIT(15)
-+
-+#define MTK_PHY_LED0_BLINK_CTRL			0x25
-+#define MTK_PHY_LED1_BLINK_CTRL			0x27
-+#define   MTK_PHY_LED_1000TX			BIT(0)
-+#define   MTK_PHY_LED_1000RX			BIT(1)
-+#define   MTK_PHY_LED_100TX			BIT(2)
-+#define   MTK_PHY_LED_100RX			BIT(3)
-+#define   MTK_PHY_LED_10TX			BIT(4)
-+#define   MTK_PHY_LED_10RX			BIT(5)
-+#define   MTK_PHY_LED_COLLISION			BIT(6)
-+#define   MTK_PHY_LED_RX_CRC_ERR		BIT(7)
-+#define   MTK_PHY_LED_RX_IDLE_ERR		BIT(8)
-+#define   MTK_PHY_LED_FORCE_BLINK		BIT(9)
-+
- #define MTK_PHY_RG_BG_RASEL			0x115
- #define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
- 
-+/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */
-+#define RG_GPIO_MISC_TPBANK0			0x6f0
-+#define   RG_GPIO_MISC_TPBANK0_BOOTMODE		GENMASK(11, 8)
-+
- /* These macro privides efuse parsing for internal phy. */
- #define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
- #define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
-@@ -238,13 +271,6 @@ enum {
- 	PAIR_D,
- };
- 
--enum {
--	GPHY_PORT0,
--	GPHY_PORT1,
--	GPHY_PORT2,
--	GPHY_PORT3,
--};
--
- enum calibration_mode {
- 	EFUSE_K,
- 	SW_K
-@@ -263,6 +289,10 @@ enum CAL_MODE {
- 	SW_M
- };
- 
-+struct mtk_socphy_shared {
-+	u32			boottrap;
-+};
-+
- static int mtk_socphy_read_page(struct phy_device *phydev)
- {
- 	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct
- 	return mt798x_phy_calibration(phydev);
- }
- 
-+static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted)
-+{
-+	struct pinctrl *pinctrl;
-+	const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE      |
-+					 MTK_PHY_LED_ON_LINK1000 |
-+					 MTK_PHY_LED_ON_LINK100  |
-+					 MTK_PHY_LED_ON_LINK10;
-+	const u16 led_blink_defaults = MTK_PHY_LED_1000TX |
-+				       MTK_PHY_LED_1000RX |
-+				       MTK_PHY_LED_100TX  |
-+				       MTK_PHY_LED_100RX  |
-+				       MTK_PHY_LED_10TX   |
-+				       MTK_PHY_LED_10RX;
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-+		      led_on_ctrl_defaults ^
-+		      (inverted ? MTK_PHY_LED_POLARITY : 0));
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-+		      led_on_ctrl_defaults);
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
-+		      led_blink_defaults);
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
-+		      led_blink_defaults);
-+
-+	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
-+	if (IS_ERR(pinctrl))
-+		dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n");
-+
-+	return 0;
-+}
-+
-+static int mt7988_phy_probe_shared(struct phy_device *phydev)
-+{
-+	struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
-+	struct mtk_socphy_shared *priv = phydev->shared->priv;
-+	struct regmap *regmap;
-+	u32 reg;
-+	int ret;
-+
-+	/* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
-+	 * LED_C and LED_D respectively. At the same time those pins are used to
-+	 * bootstrap configuration of the reference clock source (LED_A),
-+	 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
-+	 * In practise this is done using a LED and a resistor pulling the pin
-+	 * either to GND or to VIO.
-+	 * The detected value at boot time is accessible at run-time using the
-+	 * TPBANK0 register located in the gpio base of the pinctrl, in order
-+	 * to read it here it needs to be referenced by a phandle called
-+	 * 'mediatek,pio' in the MDIO bus hosting the PHY.
-+	 * The 4 bits in TPBANK0 are kept as package shared data and are used to
-+	 * set LED polarity for each of the LED0.
-+	 */
-+	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
-+	if (IS_ERR(regmap))
-+		return PTR_ERR(regmap);
-+
-+	ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
-+	if (ret)
-+		return ret;
-+
-+	priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
-+
-+	return 0;
-+}
-+
-+static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev)
-+{
-+	struct mtk_socphy_shared *priv = phydev->shared->priv;
-+
-+	if (priv->boottrap & BIT(phydev->mdio.addr))
-+		return false;
-+
-+	return true;
-+}
-+
-+static int mt7988_phy_probe(struct phy_device *phydev)
-+{
-+	int err;
-+
-+	err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
-+				    sizeof(struct mtk_socphy_shared));
-+	if (err)
-+		return err;
-+
-+	if (phy_package_probe_once(phydev)) {
-+		err = mt7988_phy_probe_shared(phydev);
-+		if (err)
-+			return err;
-+	}
-+
-+	mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
-+
-+	return mt798x_phy_calibration(phydev);
-+}
-+
- static struct phy_driver mtk_socphy_driver[] = {
- 	{
- 		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv
- 		.config_init	= mt798x_phy_config_init,
- 		.config_intr	= genphy_no_config_intr,
- 		.handle_interrupt = genphy_handle_interrupt_no_ack,
--		.probe		= mt798x_phy_calibration,
-+		.probe		= mt7988_phy_probe,
- 		.suspend	= genphy_suspend,
- 		.resume		= genphy_resume,
- 		.read_page	= mtk_socphy_read_page,
diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
deleted file mode 100644
index 6df4436ab9..0000000000
--- a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 6 Apr 2023 23:36:50 +0100
-Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
-
-MAC drivers using phylink expect SGMII in-band-status to be switched off
-when attached to a PHY. Make sure this is the case also for mxl-gpy which
-keeps SGMII in-band-status in case of SGMII interface mode is used.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
- 1 file changed, 16 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/mxl-gpy.c
-+++ b/drivers/net/phy/mxl-gpy.c
-@@ -195,8 +195,11 @@ static bool gpy_2500basex_chk(struct phy
- 
- 	phydev->speed = SPEED_2500;
- 	phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
--	phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
--		       VSPEC1_SGMII_CTRL_ANEN, 0);
-+
-+	if (!phydev->phylink)
-+		phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+			       VSPEC1_SGMII_CTRL_ANEN, 0);
-+
- 	return true;
- }
- 
-@@ -220,6 +223,14 @@ static int gpy_config_aneg(struct phy_de
- 	u32 adv;
- 	int ret;
- 
-+	/* Disable SGMII auto-negotiation if using phylink */
-+	if (phydev->phylink) {
-+		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+				     VSPEC1_SGMII_CTRL_ANEN, 0);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
- 	if (phydev->autoneg == AUTONEG_DISABLE) {
- 		/* Configure half duplex with genphy_setup_forced,
- 		 * because genphy_c45_pma_setup_forced does not support.
-@@ -310,6 +321,8 @@ static void gpy_update_interface(struct
- 	switch (phydev->speed) {
- 	case SPEED_2500:
- 		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-+		if (phydev->phylink)
-+			break;
- 		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
- 				     VSPEC1_SGMII_CTRL_ANEN, 0);
- 		if (ret < 0)
-@@ -321,7 +334,7 @@ static void gpy_update_interface(struct
- 	case SPEED_100:
- 	case SPEED_10:
- 		phydev->interface = PHY_INTERFACE_MODE_SGMII;
--		if (gpy_sgmii_aneg_en(phydev))
-+		if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
- 			break;
- 		/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
- 		 * if ANEG is disabled (in 2500-BaseX mode).
diff --git a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
deleted file mode 100644
index 7600819246..0000000000
--- a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 28 Feb 2023 17:53:37 +0000
-Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig          |   7 ++
- drivers/net/phy/Makefile         |   1 +
- drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
- 3 files changed, 226 insertions(+)
- create mode 100644 drivers/net/phy/mediatek-2p5ge.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -302,6 +302,13 @@ config MEDIATEK_GE_SOC_PHY
- 	  present in the SoCs efuse and will dynamically calibrate VCM
- 	  (common-mode voltage) during startup.
- 
-+config MEDIATEK_2P5G_PHY
-+	tristate "MediaTek 2.5G Ethernet PHY"
-+	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+	default NET_MEDIATEK_SOC
-+	help
-+	  Supports the MediaTek 2.5G Ethernet PHY.
-+
- config MICREL_PHY
- 	tristate "Micrel PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_MARVELL_10G_PHY)	+= marvell
- obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
-+obj-$(CONFIG_MEDIATEK_2P5G_PHY)	+= mediatek-2p5ge.o
- obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o
- obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY)	+= meson-gxl.o
diff --git a/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
deleted file mode 100644
index f983be4e44..0000000000
--- a/target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
+++ /dev/null
@@ -1,270 +0,0 @@
-From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
-Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 24 Jan 2024 02:27:04 +0000
-Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
-To: Daniel Golle <daniel@makrotopia.org>,
-    Qingfang Deng <dqfext@gmail.com>,
-    SkyLake Huang <SkyLake.Huang@mediatek.com>,
-    Andrew Lunn <andrew@lunn.ch>,
-    Heiner Kallweit <hkallweit1@gmail.com>,
-    Russell King <linux@armlinux.org.uk>,
-    David S. Miller <davem@davemloft.net>,
-    Eric Dumazet <edumazet@google.com>,
-    Jakub Kicinski <kuba@kernel.org>,
-    Paolo Abeni <pabeni@redhat.com>,
-    Matthias Brugger <matthias.bgg@gmail.com>,
-    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
-    netdev@vger.kernel.org,
-    linux-kernel@vger.kernel.org,
-    linux-arm-kernel@lists.infradead.org,
-    linux-mediatek@lists.infradead.org
-
-Sync initialization and calibration routines with MediaTek's reference
-driver. Improves compliance and resolves link stability issues with
-CH340 IoT devices connected to MT798x built-in PHYs.
-
-Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
- 1 file changed, 81 insertions(+), 66 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -479,7 +479,7 @@ static int tx_r50_fill_result(struct phy
- 	u16 reg, val;
- 
- 	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
--		bias = -2;
-+		bias = -1;
- 
- 	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
- 
-@@ -695,6 +695,11 @@ restore:
- static void mt798x_phy_common_finetune(struct phy_device *phydev)
- {
- 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+	__phy_write(phydev, 0x11, 0xc71);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
- 	/* EnabRandUpdTrig = 1 */
- 	__phy_write(phydev, 0x11, 0x2f00);
- 	__phy_write(phydev, 0x12, 0xe);
-@@ -705,15 +710,56 @@ static void mt798x_phy_common_finetune(s
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x83aa);
- 
--	/* TrFreeze = 0 */
-+	/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
-+	__phy_write(phydev, 0x11, 0x240);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9680);
-+
-+	/* TrFreeze = 0 (mt7988 default) */
- 	__phy_write(phydev, 0x11, 0x0);
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x9686);
- 
-+	/* SSTrKp100 = 5 */
-+	/* SSTrKf100 = 6 */
-+	/* SSTrKp1000Mas = 5 */
-+	/* SSTrKf1000Mas = 6 */
- 	/* SSTrKp1000Slv = 5 */
-+	/* SSTrKf1000Slv = 6 */
- 	__phy_write(phydev, 0x11, 0xbaef);
- 	__phy_write(phydev, 0x12, 0x2e);
- 	__phy_write(phydev, 0x10, 0x968c);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[8] = { 0x01ce, 0x01c1,
-+		       0x020f, 0x0202,
-+		       0x03d0, 0x03c0,
-+		       0x0013, 0x0005 };
-+	int i, k;
-+
-+	/* 100M eye finetune:
-+	 * Keep middle level of TX MLT3 shapper as default.
-+	 * Only change TX MLT3 overshoot level here.
-+	 */
-+	for (k = 0, i = 1; i < 12; i++) {
-+		if (i % 3 == 0)
-+			continue;
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+	}
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* ResetSyncOffset = 6 */
-+	__phy_write(phydev, 0x11, 0x600);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate = 1 */
-+	__phy_write(phydev, 0x11, 0x4c2a);
-+	__phy_write(phydev, 0x12, 0x3e);
-+	__phy_write(phydev, 0x10, 0x8fa4);
- 
- 	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
- 	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-@@ -728,7 +774,7 @@ static void mt798x_phy_common_finetune(s
- 	__phy_write(phydev, 0x10, 0x8ec0);
- 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- 
--	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
- 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- 		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- 		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-@@ -761,48 +807,6 @@ static void mt798x_phy_common_finetune(s
- 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
- }
- 
--static void mt7981_phy_finetune(struct phy_device *phydev)
--{
--	u16 val[8] = { 0x01ce, 0x01c1,
--		       0x020f, 0x0202,
--		       0x03d0, 0x03c0,
--		       0x0013, 0x0005 };
--	int i, k;
--
--	/* 100M eye finetune:
--	 * Keep middle level of TX MLT3 shapper as default.
--	 * Only change TX MLT3 overshoot level here.
--	 */
--	for (k = 0, i = 1; i < 12; i++) {
--		if (i % 3 == 0)
--			continue;
--		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
--	}
--
--	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
--	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
--	__phy_write(phydev, 0x11, 0xc71);
--	__phy_write(phydev, 0x12, 0xc);
--	__phy_write(phydev, 0x10, 0x8fae);
--
--	/* ResetSyncOffset = 6 */
--	__phy_write(phydev, 0x11, 0x600);
--	__phy_write(phydev, 0x12, 0x0);
--	__phy_write(phydev, 0x10, 0x8fc0);
--
--	/* VgaDecRate = 1 */
--	__phy_write(phydev, 0x11, 0x4c2a);
--	__phy_write(phydev, 0x12, 0x3e);
--	__phy_write(phydev, 0x10, 0x8fa4);
--
--	/* FfeUpdGainForce = 4 */
--	__phy_write(phydev, 0x11, 0x240);
--	__phy_write(phydev, 0x12, 0x0);
--	__phy_write(phydev, 0x10, 0x9680);
--
--	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
--}
--
- static void mt7988_phy_finetune(struct phy_device *phydev)
- {
- 	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-@@ -817,17 +821,7 @@ static void mt7988_phy_finetune(struct p
- 	/* TCT finetune */
- 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
- 
--	/* Disable TX power saving */
--	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
--		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
--
- 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
--
--	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
--	__phy_write(phydev, 0x11, 0x671);
--	__phy_write(phydev, 0x12, 0xc);
--	__phy_write(phydev, 0x10, 0x8fae);
--
- 	/* ResetSyncOffset = 5 */
- 	__phy_write(phydev, 0x11, 0x500);
- 	__phy_write(phydev, 0x12, 0x0);
-@@ -835,13 +829,27 @@ static void mt7988_phy_finetune(struct p
- 
- 	/* VgaDecRate is 1 at default on mt7988 */
- 
--	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+	/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
-+	 * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
-+	 */
-+	__phy_write(phydev, 0x11, 0xb90a);
-+	__phy_write(phydev, 0x12, 0x6f);
-+	__phy_write(phydev, 0x10, 0x8f82);
-+
-+	/* RemAckCntLimitCtrl = 1 */
-+	__phy_write(phydev, 0x11, 0xfbba);
-+	__phy_write(phydev, 0x12, 0xc3);
-+	__phy_write(phydev, 0x10, 0x87f8);
- 
--	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
--	/* TxClkOffset = 2 */
--	__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
--		     FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
- 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
-+
-+	/* rg_tr_lpf_cnt_val = 1023 */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
- }
- 
- static void mt798x_phy_eee(struct phy_device *phydev)
-@@ -874,11 +882,11 @@ static void mt798x_phy_eee(struct phy_de
- 		       MTK_PHY_LPI_SLV_SEND_TX_EN,
- 		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
- 
--	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
--		       MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
--		       MTK_PHY_LPI_TXPCS_LOC_RCV,
--		       FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+	/* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+			   MTK_PHY_LPI_TXPCS_LOC_RCV);
- 
-+	/* This also fixes some IoT issues, such as CH340 */
- 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
- 		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
- 		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-@@ -912,7 +920,7 @@ static void mt798x_phy_eee(struct phy_de
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x9690);
- 
--	/* REG_EEE_st2TrKf1000 = 3 */
-+	/* REG_EEE_st2TrKf1000 = 2 */
- 	__phy_write(phydev, 0x11, 0x114f);
- 	__phy_write(phydev, 0x12, 0x2);
- 	__phy_write(phydev, 0x10, 0x969a);
-@@ -937,7 +945,7 @@ static void mt798x_phy_eee(struct phy_de
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x96b8);
- 
--	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
- 	__phy_write(phydev, 0x11, 0x1463);
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x96ca);
-@@ -1198,6 +1206,13 @@ static int mt7988_phy_probe(struct phy_d
- 
- 	mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
- 
-+	/* Disable TX power saving at probing to:
-+	 * 1. Meet common mode compliance test criteria
-+	 * 2. Make sure that TX-VCM calibration works fine
-+	 */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
- 	return mt798x_phy_calibration(phydev);
- }
- 
diff --git a/target/linux/mediatek/patches-5.15/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch
deleted file mode 100644
index c10ab92a05..0000000000
--- a/target/linux/mediatek/patches-5.15/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 4a6ecbd197764499d808309f372341370a89f88c Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 11 Jun 2023 01:59:14 +0100
-Subject: [PATCH] net: phy: add driver for Airoha EN8811 2.5G PHY
-
-2500Base-T PHY with ID 0x03a2a411, needs firmware upload
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig       |   5 +
- drivers/net/phy/Makefile      |   1 +
- drivers/net/phy/air_en8811h.c | 708 ++++++++++++++++++++++++++++++++++
- drivers/net/phy/air_en8811h.h | 151 ++++++++
- 4 files changed, 865 insertions(+)
- create mode 100644 drivers/net/phy/air_en8811h.c
- create mode 100644 drivers/net/phy/air_en8811h.h
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -149,6 +149,17 @@ config MESON_GXL_PHY
- 	help
- 	  Currently has a driver for the Amlogic Meson GXL Internal PHY
- 
-+config AIROHA_EN8811H_PHY
-+	tristate "Airoha EN8811H 2.5G Gigabit PHY"
-+	help
-+	  Currently supports the Airoha EN8811H PHY.
-+
-+config AIROHA_EN8811H_PHY_DEBUGFS
-+	bool "EN8811H debugfs support"
-+	depends on AIROHA_EN8811H_PHY
-+	help
-+	  Enable creation of debugfs files for the EN8811H drivers.
-+
- config ADIN_PHY
- 	tristate "Analog Devices Industrial Ethernet PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -46,6 +46,8 @@ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
- obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
- 
- obj-$(CONFIG_ADIN_PHY)		+= adin.o
-+air_en8811h-y			:= air_en8811h_main.o air_en8811h_api.o
-+obj-$(CONFIG_AIROHA_EN8811H_PHY)	+= air_en8811h.o
- obj-$(CONFIG_AMD_PHY)		+= amd.o
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
- obj-$(CONFIG_AT803X_PHY)	+= at803x.o
diff --git a/target/linux/mediatek/patches-5.15/790-net-phy-realtek-add-led-link-select-for-RTL8221.patch b/target/linux/mediatek/patches-5.15/790-net-phy-realtek-add-led-link-select-for-RTL8221.patch
deleted file mode 100644
index b4167a03ac..0000000000
--- a/target/linux/mediatek/patches-5.15/790-net-phy-realtek-add-led-link-select-for-RTL8221.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From f9e17c264d316611c26b98ad1a3ca01c289c67b4 Mon Sep 17 00:00:00 2001
-From: Yangyu Chen <cyy@cyyself.name>
-Date: Sun, 23 Apr 2023 20:06:41 +0800
-Subject: [PATCH] net: phy: realtek: add led-link-select for RTL8221
-
-RTL8221B PHYs will select the different speeds for 3 LEDs to 10M/100M/1G
-respectively by default. Some devices like TP-LINK XDR-6088/XDR-6086
-have only one LED connects to the PHY chip LED0. If we didn't change the
-default settings, the LED will only blink at 10M speed.
-
-This patch allows configuring LED link select bitmask from DT. And it
-has been tested with TP-Link XDR6088 with different DT configurations.
-
-Signed-off-by: Yangyu Chen <cyy@cyyself.name>
----
- drivers/net/phy/realtek.c | 28 +++++++++++++++++++++++++++-
- 1 file changed, 27 insertions(+), 1 deletion(-)
-
---- a/drivers/net/phy/realtek.c
-+++ b/drivers/net/phy/realtek.c
-@@ -66,6 +66,10 @@
- #define RTL8221B_PHYCR1_ALDPS_EN		BIT(2)
- #define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN	BIT(12)
- 
-+#define RTL8221B_NR_LEDS				3
-+#define RTL8221B_LED_LINK_SELECT		0xd032
-+#define RTL8221B_LED_LINK_SELECT_OFFSET	0x2
-+
- #define RTL8366RB_POWER_SAVE			0x15
- #define RTL8366RB_POWER_SAVE_ON			BIT(12)
- 
-@@ -921,6 +925,28 @@ static irqreturn_t rtl9000a_handle_inter
- 	return IRQ_HANDLED;
- }
- 
-+static int rtl8221b_config_led(struct phy_device *phydev) {
-+	struct device *node = &phydev->mdio.dev;
-+	u32 link_select[RTL8221B_NR_LEDS];
-+	int i, val;
-+
-+	val = device_property_read_u32_array(node, "realtek,led-link-select",
-+			link_select, RTL8221B_NR_LEDS);
-+
-+	if (val)
-+		return 0;
-+
-+	for (i = 0; i < RTL8221B_NR_LEDS; i++) {
-+		val = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL,
-+			RTL8221B_LED_LINK_SELECT + i * RTL8221B_LED_LINK_SELECT_OFFSET,
-+			link_select[i]);
-+		if (val < 0)
-+			return val;
-+	}
-+
-+	return 0;
-+}
-+
- static int rtl8221b_config_init(struct phy_device *phydev)
- {
- 	u16 option_mode;
-@@ -968,7 +994,7 @@ static int rtl8221b_config_init(struct p
- 	phy_read_mmd_poll_timeout(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7587,
- 				  val, !(val & BIT(0)), 500, 100000, false);
- 
--	return 0;
-+	return rtl8221b_config_led(phydev);
- }
- 
- static int rtl8221b_ack_interrupt(struct phy_device *phydev)
diff --git a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
deleted file mode 100644
index 691a7c0398..0000000000
--- a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch
+++ /dev/null
@@ -1,225 +0,0 @@
-From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Tue, 25 Jan 2022 16:50:47 +0800
-Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support
-
-Add PCIe 2 lane efuse support in tphy driver.
-
-Signed-off-by: Jie Yang <jieyy.yang@mediatek.com>
-Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++
- 1 file changed, 140 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -44,6 +44,15 @@
- #define SSUSB_SIFSLV_V2_U3PHYD		0x200
- #define SSUSB_SIFSLV_V2_U3PHYA		0x400
- 
-+/* version V4 sub-banks offset base address */
-+/* pcie phy banks */
-+#define SSUSB_SIFSLV_V4_SPLLC		0x000
-+#define SSUSB_SIFSLV_V4_CHIP		0x100
-+#define SSUSB_SIFSLV_V4_U3PHYD		0x900
-+#define SSUSB_SIFSLV_V4_U3PHYA		0xb00
-+
-+#define SSUSB_LN1_OFFSET		0x10000
-+
- #define U3P_MISC_REG1		0x04
- #define MR1_EFUSE_AUTO_LOAD_DIS		BIT(6)
- 
-@@ -320,6 +329,7 @@ enum mtk_phy_version {
- 	MTK_PHY_V1 = 1,
- 	MTK_PHY_V2,
- 	MTK_PHY_V3,
-+	MTK_PHY_V4,
- };
- 
- struct mtk_phy_pdata {
-@@ -369,6 +379,9 @@ struct mtk_phy_instance {
- 	u32 efuse_intr;
- 	u32 efuse_tx_imp;
- 	u32 efuse_rx_imp;
-+	u32 efuse_intr_ln1;
-+	u32 efuse_tx_imp_ln1;
-+	u32 efuse_rx_imp_ln1;
- 	int eye_src;
- 	int eye_vrt;
- 	int eye_term;
-@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk
- 	}
- }
- 
-+static void phy_v4_banks_init(struct mtk_tphy *tphy,
-+			      struct mtk_phy_instance *instance)
-+{
-+	struct u2phy_banks *u2_banks = &instance->u2_banks;
-+	struct u3phy_banks *u3_banks = &instance->u3_banks;
-+
-+	switch (instance->type) {
-+	case PHY_TYPE_USB2:
-+		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
-+		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
-+		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
-+		break;
-+	case PHY_TYPE_USB3:
-+		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
-+		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
-+		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
-+		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
-+		break;
-+	case PHY_TYPE_PCIE:
-+		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC;
-+		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP;
-+		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD;
-+		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA;
-+		break;
-+	default:
-+		dev_err(tphy->dev, "incompatible PHY type\n");
-+		return;
-+	}
-+}
-+
- static void phy_parse_property(struct mtk_tphy *tphy,
- 				struct mtk_phy_instance *instance)
- {
-@@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy
- 
- 		dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
- 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
-+
-+		if (tphy->pdata->version != MTK_PHY_V4)
-+			break;
-+
-+		ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
-+		if (ret) {
-+			dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-+			break;
-+		}
-+
-+		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1);
-+		if (ret) {
-+			dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret);
-+			break;
-+		}
-+
-+		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1);
-+		if (ret) {
-+			dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret);
-+			break;
-+		}
-+
-+		/* no efuse, ignore it */
-+		if (!instance->efuse_intr_ln1 &&
-+		    !instance->efuse_rx_imp_ln1 &&
-+		    !instance->efuse_tx_imp_ln1) {
-+			dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n");
-+			instance->efuse_sw_en = 0;
-+			break;
-+		}
-+
-+		dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n",
-+			 instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1,
-+			 instance->efuse_tx_imp_ln1);
- 		break;
- 	default:
- 		dev_err(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy
- 		writel(tmp, u2_banks->com + U3P_USBPHYACR1);
- 		break;
- 	case PHY_TYPE_USB3:
-+		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
-+		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-+		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-+
-+		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
-+		tmp &= ~P3D_RG_TX_IMPEL;
-+		tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp);
-+		tmp |= P3D_RG_FORCE_TX_IMPEL;
-+		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
-+
-+		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
-+		tmp &= ~P3D_RG_RX_IMPEL;
-+		tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp);
-+		tmp |= P3D_RG_FORCE_RX_IMPEL;
-+		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
-+
-+		tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
-+		tmp &= ~P3A_RG_IEXT_INTR;
-+		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
-+		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
-+		pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n",
-+			__func__, instance->efuse_tx_imp,
-+			instance->efuse_rx_imp, instance->efuse_intr);
-+
-+		break;
- 	case PHY_TYPE_PCIE:
- 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- 		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-@@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy
- 		tmp &= ~P3A_RG_IEXT_INTR;
- 		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
- 		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
-+		if (!instance->efuse_intr_ln1 &&
-+		    !instance->efuse_rx_imp_ln1 &&
-+		    !instance->efuse_tx_imp_ln1)
-+			break;
-+
-+		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
-+		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-+		writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
-+
-+		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
-+		tmp &= ~P3D_RG_TX_IMPEL;
-+		tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1);
-+		tmp |= P3D_RG_FORCE_TX_IMPEL;
-+		writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
-+
-+		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
-+		tmp &= ~P3D_RG_RX_IMPEL;
-+		tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1);
-+		tmp |= P3D_RG_FORCE_RX_IMPEL;
-+		writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
-+
-+		tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
-+		tmp &= ~P3A_RG_IEXT_INTR;
-+		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1);
-+		writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
-+		dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n",
-+			 __func__, instance->efuse_tx_imp_ln1,
-+			 instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1);
- 		break;
- 	default:
- 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct
- 	case MTK_PHY_V3:
- 		phy_v2_banks_init(tphy, instance);
- 		break;
-+	case MTK_PHY_V4:
-+		phy_v4_banks_init(tphy, instance);
-+		break;
- 	default:
- 		dev_err(dev, "phy version is not supported\n");
- 		return ERR_PTR(-EINVAL);
-@@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v
- 	.version = MTK_PHY_V3,
- };
- 
-+static const struct mtk_phy_pdata tphy_v4_pdata = {
-+	.avoid_rx_sen_degradation = false,
-+	.sw_efuse_supported = true,
-+	.version = MTK_PHY_V4,
-+};
-+
- static const struct mtk_phy_pdata mt8173_pdata = {
- 	.avoid_rx_sen_degradation = true,
- 	.version = MTK_PHY_V1,
-@@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph
- 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
- 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
- 	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
-+	{ .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata },
- 	{ },
- };
- MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
diff --git a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
deleted file mode 100644
index 3b8285bf47..0000000000
--- a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Tue, 25 Jan 2022 19:03:34 +0800
-Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
- support
-
-add auto-load-valid check mechanism support
-
-Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
- 1 file changed, 64 insertions(+), 3 deletions(-)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -376,9 +376,13 @@ struct mtk_phy_instance {
- 	u32 type_sw_reg;
- 	u32 type_sw_index;
- 	u32 efuse_sw_en;
-+	bool efuse_alv_en;
-+	u32 efuse_autoloadvalid;
- 	u32 efuse_intr;
- 	u32 efuse_tx_imp;
- 	u32 efuse_rx_imp;
-+	bool efuse_alv_ln1_en;
-+	u32 efuse_ln1_autoloadvalid;
- 	u32 efuse_intr_ln1;
- 	u32 efuse_tx_imp_ln1;
- 	u32 efuse_rx_imp_ln1;
-@@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy
- {
- 	struct device *dev = &instance->phy->dev;
- 	int ret = 0;
-+	bool alv = false;
- 
- 	/* tphy v1 doesn't support sw efuse, skip it */
- 	if (!tphy->pdata->sw_efuse_supported) {
-@@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy
- 
- 	switch (instance->type) {
- 	case PHY_TYPE_USB2:
-+		alv = of_property_read_bool(dev->of_node, "auto_load_valid");
-+		if (alv) {
-+			instance->efuse_alv_en = alv;
-+			ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
-+							&instance->efuse_autoloadvalid);
-+			if (ret) {
-+				dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
-+				break;
-+			}
-+			dev_info(dev,
-+				"u2 auto load valid efuse: ENABLE with value: %u\n",
-+				instance->efuse_autoloadvalid);
-+		}
-+
- 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
- 		if (ret) {
- 			dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
-@@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy
- 
- 	case PHY_TYPE_USB3:
- 	case PHY_TYPE_PCIE:
-+		alv = of_property_read_bool(dev->of_node, "auto_load_valid");
-+		if (alv) {
-+			instance->efuse_alv_en = alv;
-+			ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
-+							&instance->efuse_autoloadvalid);
-+			if (ret) {
-+				dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
-+				break;
-+			}
-+			dev_info(dev,
-+				"u3 auto load valid efuse: ENABLE with value: %u\n",
-+				instance->efuse_autoloadvalid);
-+		}
-+
- 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
- 		if (ret) {
- 			dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
-@@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy
- 		if (tphy->pdata->version != MTK_PHY_V4)
- 			break;
- 
-+		alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
-+		if (alv) {
-+			instance->efuse_alv_ln1_en = alv;
-+			ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
-+							&instance->efuse_ln1_autoloadvalid);
-+			if (ret) {
-+				dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
-+				break;
-+			}
-+			dev_info(dev,
-+				"pcie auto load valid efuse: ENABLE with value: %u\n",
-+				instance->efuse_ln1_autoloadvalid);
-+		}
-+
- 		ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
- 		if (ret) {
- 			dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-@@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy
- 
- 	switch (instance->type) {
- 	case PHY_TYPE_USB2:
-+		if (instance->efuse_alv_en &&
-+		    instance->efuse_autoloadvalid == 1)
-+			break;
-+
- 		tmp = readl(u2_banks->misc + U3P_MISC_REG1);
- 		tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
- 		writel(tmp, u2_banks->misc + U3P_MISC_REG1);
-@@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy
- 		writel(tmp, u2_banks->com + U3P_USBPHYACR1);
- 		break;
- 	case PHY_TYPE_USB3:
-+		if (instance->efuse_alv_en &&
-+		    instance->efuse_autoloadvalid == 1)
-+			break;
-+
- 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- 		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
- 		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy
- 
- 		break;
- 	case PHY_TYPE_PCIE:
-+		if (instance->efuse_alv_en &&
-+		    instance->efuse_autoloadvalid == 1)
-+			break;
-+
- 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- 		tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
- 		writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy
- 		tmp &= ~P3A_RG_IEXT_INTR;
- 		tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
- 		writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
--		if (!instance->efuse_intr_ln1 &&
--		    !instance->efuse_rx_imp_ln1 &&
--		    !instance->efuse_tx_imp_ln1)
-+
-+		if ((!instance->efuse_intr_ln1 &&
-+		     !instance->efuse_rx_imp_ln1 &&
-+		     !instance->efuse_tx_imp_ln1) ||
-+		    (instance->efuse_alv_ln1_en &&
-+		     instance->efuse_ln1_autoloadvalid == 1))
- 			break;
- 
- 		tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
diff --git a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch
deleted file mode 100644
index 7a10dac051..0000000000
--- a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch
+++ /dev/null
@@ -1,23 +0,0 @@
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data
- 	.has_ck_26m_sel = true,
- };
- 
-+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
-+	.num_pwms = 2,
-+	.pwm45_fixup = false,
-+	.has_ck_26m_sel = true,
-+};
-+
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = false,
-@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med
- 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- 	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
- 	{ },
diff --git a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
deleted file mode 100644
index 65311d5718..0000000000
--- a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 30 Nov 2022 13:19:39 +0000
-Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981
-
-Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
-Brings code to assign values from efuse as well as new function to
-convert raw temperature to millidegree celsius, as found in MediaTek's
-SDK sources (but cleaned up and de-duplicated)
-
-[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++--
- 1 file changed, 132 insertions(+), 5 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -150,6 +150,20 @@
- #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
- #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
- 
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros can be used for MT7981 and MT7986.
-+ */
-+#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
-+#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
-+#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
-+
- enum {
- 	VTS1,
- 	VTS2,
-@@ -163,6 +177,7 @@ enum {
- enum mtk_thermal_version {
- 	MTK_THERMAL_V1 = 1,
- 	MTK_THERMAL_V2,
-+	MTK_THERMAL_V3,
- };
- 
- /* MT2701 thermal sensors */
-@@ -245,6 +260,27 @@ enum mtk_thermal_version {
- /* The calibration coefficient of sensor  */
- #define MT8183_CALIBRATION	153
- 
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT7986_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT7986 */
-+#define MT7986_NUM_SENSORS		1
-+
-+/* The number of banks in the MT7986 */
-+#define MT7986_NUM_ZONES		1
-+
-+/* The number of sensing points per bank */
-+#define MT7986_NUM_SENSORS_PER_ZONE	1
-+
-+/* MT7986 thermal sensors */
-+#define MT7986_TS1			0
-+
-+/* The number of controller in the MT7986 */
-+#define MT7986_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT7986_CALIBRATION		165
-+
- struct mtk_thermal;
- 
- struct thermal_bank_cfg {
-@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762
- static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
- static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
- 
-+/* MT7986 thermal sensor data */
-+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
-+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
-+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
-+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-+
- /*
-  * The MT8173 thermal controller has four banks. Each bank can read up to
-  * four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8
- 	.version = MTK_THERMAL_V1,
- };
- 
-+/*
-+ * MT7986 uses AUXADC Channel 11 for raw data access.
-+ */
-+static const struct mtk_thermal_data mt7986_thermal_data = {
-+	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT7986_NUM_ZONES,
-+	.num_sensors = MT7986_NUM_SENSORS,
-+	.vts_index = mt7986_vts_index,
-+	.cali_val = MT7986_CALIBRATION,
-+	.num_controller = MT7986_NUM_CONTROLLER,
-+	.controller_offset = mt7986_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 1,
-+			.sensors = mt7986_bank_data,
-+		},
-+	},
-+	.msr = mt7986_msr,
-+	.adcpnp = mt7986_adcpnp,
-+	.sensor_mux_values = mt7986_mux_values,
-+	.version = MTK_THERMAL_V3,
-+};
-+
- /**
-  * raw_to_mcelsius - convert a raw ADC value to mcelsius
-  * @mt:	The thermal controller
-@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
- 	return (format_2 - tmp) * 100;
- }
- 
-+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+	s32 tmp;
-+
-+	if (raw == 0)
-+		return 0;
-+
-+	raw &= 0xfff;
-+	tmp = 100000 * 15 / 16 * 10000;
-+	tmp /= 4096 - 512 + mt->adc_ge;
-+	tmp /= 1490;
-+	tmp *= raw - mt->vts[sensno] - 2900;
-+
-+	return mt->degc_cali * 500 - tmp;
-+}
-+
- /**
-  * mtk_thermal_get_bank - get bank
-  * @bank:	The bank
-@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2(
- 	return 0;
- }
- 
-+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
-+{
-+	if (!CALIB_BUF1_VALID_V3(buf[1]))
-+		return -EINVAL;
-+
-+	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-+	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-+	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-+	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-+	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-+	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
-+
-+	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-+		mt->o_slope = 0;
-+
-+	return 0;
-+}
-+
- static int mtk_thermal_get_calibration_data(struct device *dev,
- 					    struct mtk_thermal *mt)
- {
-@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d
- 
- 	/* Start with default values */
- 	mt->adc_ge = 512;
-+	mt->adc_oe = 512;
- 	for (i = 0; i < mt->conf->num_sensors; i++)
- 		mt->vts[i] = 260;
- 	mt->degc_cali = 40;
-@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d
- 		goto out;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
- 		ret = mtk_thermal_extract_efuse_v1(mt, buf);
--	else
-+		break;
-+	case MTK_THERMAL_V2:
- 		ret = mtk_thermal_extract_efuse_v2(mt, buf);
-+		break;
-+	case MTK_THERMAL_V3:
-+		ret = mtk_thermal_extract_efuse_v3(mt, buf);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		break;
-+	}
- 
- 	if (ret) {
- 		dev_info(dev, "Device not calibrated, using default calibration values\n");
-@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the
- 		.data = (void *)&mt7622_thermal_data,
- 	},
- 	{
-+		.compatible = "mediatek,mt7986-thermal",
-+		.data = (void *)&mt7986_thermal_data,
-+	},
-+	{
- 		.compatible = "mediatek,mt8183-thermal",
- 		.data = (void *)&mt8183_thermal_data,
- 	}, {
-@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat
- 		goto err_disable_clk_auxadc;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V2) {
-+	if (mt->conf->version != MTK_THERMAL_V1) {
- 		mtk_thermal_turn_on_buffer(apmixed_base);
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
--	else
-+		break;
-+	case MTK_THERMAL_V2:
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+		break;
-+	case MTK_THERMAL_V3:
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
-+		break;
-+	default:
-+		break;
-+	}
- 
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
diff --git a/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch b/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch
deleted file mode 100644
index 8f27462cbd..0000000000
--- a/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 19 Apr 2023 20:25:51 +0100
-Subject: [PATCH] pwm: mediatek: Add support for MT7981
-
-The PWM unit on MT7981 uses different register offsets than previous
-MediaTek PWM units. Add support for these new offsets and add support
-for PWM on MT7981 which has 3 PWM channels, one of them is typically
-used for a temperature controlled fan.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
- 1 file changed, 33 insertions(+), 8 deletions(-)
-
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
- 	unsigned int num_pwms;
- 	bool pwm45_fixup;
- 	bool has_ck_26m_sel;
-+	const unsigned int *reg_offset;
- };
- 
- /**
-@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
- 	const struct pwm_mediatek_of_data *soc;
- };
- 
--static const unsigned int pwm_mediatek_reg_offset[] = {
-+static const unsigned int mtk_pwm_reg_offset_v1[] = {
- 	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
- };
- 
-+static const unsigned int mtk_pwm_reg_offset_v2[] = {
-+	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
-+};
-+
- static inline struct pwm_mediatek_chip *
- to_pwm_mediatek_chip(struct pwm_chip *chip)
- {
-@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
- 				       unsigned int num, unsigned int offset,
- 				       u32 value)
- {
--	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
-+	writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
- }
- 
- static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
-@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
- 	.num_pwms = 8,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7622_pwm_data = {
- 	.num_pwms = 6,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7623_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = true,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7628_pwm_data = {
- 	.num_pwms = 4,
- 	.pwm45_fixup = true,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7629_pwm_data = {
- 	.num_pwms = 1,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt8183_pwm_data = {
- 	.num_pwms = 4,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
-+};
-+
-+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
-+	.num_pwms = 3,
-+	.pwm45_fixup = false,
-+	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v2,
- };
- 
- static const struct pwm_mediatek_of_data mt7986_pwm_data = {
- 	.num_pwms = 2,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct of_device_id pwm_mediatek_of_match[] = {
-@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
- 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
- 	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- 	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
diff --git a/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch b/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch
deleted file mode 100644
index f2be737146..0000000000
--- a/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 26564c44357e19d03c124550bbd0b5851e6638c2 Mon Sep 17 00:00:00 2001
-From: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Date: Fri, 24 Sep 2021 16:06:28 +0800
-Subject: [PATCH] dt-bindings: pinctrl: mt8195: add rsel define
-
-This patch adds rsel define for mt8195.
-
-Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- include/dt-bindings/pinctrl/mt65xx.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/include/dt-bindings/pinctrl/mt65xx.h
-+++ b/include/dt-bindings/pinctrl/mt65xx.h
-@@ -16,6 +16,15 @@
- #define MTK_PUPD_SET_R1R0_10 102
- #define MTK_PUPD_SET_R1R0_11 103
- 
-+#define MTK_PULL_SET_RSEL_000  200
-+#define MTK_PULL_SET_RSEL_001  201
-+#define MTK_PULL_SET_RSEL_010  202
-+#define MTK_PULL_SET_RSEL_011  203
-+#define MTK_PULL_SET_RSEL_100  204
-+#define MTK_PULL_SET_RSEL_101  205
-+#define MTK_PULL_SET_RSEL_110  206
-+#define MTK_PULL_SET_RSEL_111  207
-+
- #define MTK_DRIVE_2mA  2
- #define MTK_DRIVE_4mA  4
- #define MTK_DRIVE_6mA  6
diff --git a/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch b/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch
deleted file mode 100644
index aa9f879e3a..0000000000
--- a/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From d8b94c9ff96c2024a527086d850eb0b314337ff9 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 14 Sep 2021 16:51:32 +0800
-Subject: [PATCH] pinctrl: mediatek: moore: check if pin_desc is valid before
- use
-
-Certain SoC are missing the middle part gpios in consecutive pins,
-it's better to check if mtk_pin_desc is a valid pin for the extensibility
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Acked-by: Sean Wang <sean.wang@mediatek.com>
-Link: https://lore.kernel.org/r/20210914085137.31761-5-sam.shih@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-moore.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
-@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pin
- 		int pin = grp->pins[i];
- 
- 		desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+		if (!desc->name)
-+			return -ENOTSUPP;
- 
- 		mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
- 				 pin_modes[i]);
-@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enabl
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
- 				hw->soc->gpio_m);
-@@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	/* hardware would take 0 as input direction */
- 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
-@@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctr
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	switch (param) {
- 	case PIN_CONFIG_BIAS_DISABLE:
-@@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctr
- 	int cfg, err = 0;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	for (cfg = 0; cfg < num_configs; cfg++) {
- 		param = pinconf_to_config_param(configs[cfg]);
-@@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip
- 	int value, err;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
- 	if (err)
-@@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chi
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
-+	if (!desc->name) {
-+		dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
-+		return;
-+	}
- 
- 	mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
- }
-@@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gp
- 	u32 debounce;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
-+	if (!desc->name)
-+		return -ENOTSUPP;
- 
- 	if (!hw->eint ||
- 	    pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
diff --git a/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch b/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch
deleted file mode 100644
index 0f5c0495fe..0000000000
--- a/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch
+++ /dev/null
@@ -1,457 +0,0 @@
-From fb34a9ae383ae26326d4889fd2513e49f1019b88 Mon Sep 17 00:00:00 2001
-From: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Date: Fri, 24 Sep 2021 16:06:31 +0800
-Subject: [PATCH] pinctrl: mediatek: support rsel feature
-
-This patch supports rsel(resistance selection) feature for I2C pins.
-It provides more resistance selection solution in different ICs.
-It provides rsel define and si unit solution by identifying
-"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node.
-
-Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../pinctrl/mediatek/pinctrl-mtk-common-v2.c  | 231 +++++++++++++++---
- .../pinctrl/mediatek/pinctrl-mtk-common-v2.h  |  46 ++++
- drivers/pinctrl/mediatek/pinctrl-paris.c      |  60 +++--
- 3 files changed, 289 insertions(+), 48 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -665,6 +665,181 @@ out:
- 	return err;
- }
- 
-+static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw,
-+				  const struct mtk_pin_desc *desc,
-+				  u32 pullup, u32 arg, u32 *rsel_val)
-+{
-+	const struct mtk_pin_rsel *rsel;
-+	int check;
-+	bool found = false;
-+
-+	rsel = hw->soc->pin_rsel;
-+
-+	for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
-+		if (desc->number >= rsel[check].s_pin &&
-+		    desc->number <= rsel[check].e_pin) {
-+			if (pullup) {
-+				if (rsel[check].up_rsel == arg) {
-+					found = true;
-+					*rsel_val = rsel[check].rsel_index;
-+					break;
-+				}
-+			} else {
-+				if (rsel[check].down_rsel == arg) {
-+					found = true;
-+					*rsel_val = rsel[check].rsel_index;
-+					break;
-+				}
-+			}
-+		}
-+	}
-+
-+	if (!found) {
-+		dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n",
-+			arg, desc->number, desc->name);
-+		return -ENOTSUPP;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw,
-+				     const struct mtk_pin_desc *desc,
-+				     u32 pullup, u32 arg)
-+{
-+	int err, rsel_val;
-+
-+	if (hw->rsel_si_unit) {
-+		/* find pin rsel_index from pin_rsel array*/
-+		err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val);
-+		if (err)
-+			goto out;
-+	} else {
-+		if (arg < MTK_PULL_SET_RSEL_000 ||
-+		    arg > MTK_PULL_SET_RSEL_111) {
-+			err = -EINVAL;
-+			goto out;
-+		}
-+
-+		rsel_val = arg - MTK_PULL_SET_RSEL_000;
-+	}
-+
-+	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val);
-+	if (err)
-+		goto out;
-+
-+	err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE);
-+
-+out:
-+	return err;
-+}
-+
-+int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
-+			       const struct mtk_pin_desc *desc,
-+			       u32 pullup, u32 arg)
-+{
-+	int err = -ENOTSUPP;
-+	u32 try_all_type;
-+
-+	if (hw->soc->pull_type)
-+		try_all_type = hw->soc->pull_type[desc->number];
-+	else
-+		try_all_type = MTK_PULL_TYPE_MASK;
-+
-+	if (try_all_type & MTK_PULL_RSEL_TYPE) {
-+		err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
-+		err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
-+		err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc,
-+							  pullup, arg);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
-+		err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
-+
-+	if (err)
-+		dev_err(hw->dev, "Invalid pull argument\n");
-+
-+	return err;
-+}
-+EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
-+
-+static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw,
-+				const struct mtk_pin_desc *desc,
-+				u32 pullup, u32 rsel_val, u32 *si_unit)
-+{
-+	const struct mtk_pin_rsel *rsel;
-+	int check;
-+
-+	rsel = hw->soc->pin_rsel;
-+
-+	for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
-+		if (desc->number >= rsel[check].s_pin &&
-+		    desc->number <= rsel[check].e_pin) {
-+			if (rsel_val == rsel[check].rsel_index) {
-+				if (pullup)
-+					*si_unit = rsel[check].up_rsel;
-+				else
-+					*si_unit = rsel[check].down_rsel;
-+				break;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw,
-+				     const struct mtk_pin_desc *desc,
-+				     u32 *pullup, u32 *enable)
-+{
-+	int pu, pd, rsel, err;
-+
-+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel);
-+	if (err)
-+		goto out;
-+
-+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
-+	if (err)
-+		goto out;
-+
-+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+
-+	if (pu == 0 && pd == 0) {
-+		*pullup = 0;
-+		*enable = MTK_DISABLE;
-+	} else if (pu == 1 && pd == 0) {
-+		*pullup = 1;
-+		if (hw->rsel_si_unit)
-+			mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
-+		else
-+			*enable = rsel + MTK_PULL_SET_RSEL_000;
-+	} else if (pu == 0 && pd == 1) {
-+		*pullup = 0;
-+		if (hw->rsel_si_unit)
-+			mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
-+		else
-+			*enable = rsel + MTK_PULL_SET_RSEL_000;
-+	} else {
-+		err = -EINVAL;
-+		goto out;
-+	}
-+
-+out:
-+	return err;
-+}
-+
- static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
- 				const struct mtk_pin_desc *desc,
- 				u32 *pullup, u32 *enable)
-@@ -746,44 +921,40 @@ out:
- 	return err;
- }
- 
--int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
--				const struct mtk_pin_desc *desc,
--				u32 pullup, u32 arg)
--{
--	int err;
--
--	err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
--	if (!err)
--		goto out;
--
--	err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
--	if (!err)
--		goto out;
--
--	err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
--
--out:
--	return err;
--}
--EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
--
- int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
- 			      const struct mtk_pin_desc *desc,
- 			      u32 *pullup, u32 *enable)
- {
--	int err;
-+	int err = -ENOTSUPP;
-+	u32 try_all_type;
- 
--	err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
--	if (!err)
--		goto out;
-+	if (hw->soc->pull_type)
-+		try_all_type = hw->soc->pull_type[desc->number];
-+	else
-+		try_all_type = MTK_PULL_TYPE_MASK;
- 
--	err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
--	if (!err)
--		goto out;
-+	if (try_all_type & MTK_PULL_RSEL_TYPE) {
-+		err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
-+		err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
-+		if (!err)
-+			return err;
-+	}
-+
-+	if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
-+		err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc,
-+							  pullup, enable);
-+		if (!err)
-+			return err;
-+	}
- 
--	err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
-+	if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
-+		err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
- 
--out:
- 	return err;
- }
- EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-@@ -17,6 +17,22 @@
- #define MTK_ENABLE     1
- #define MTK_PULLDOWN   0
- #define MTK_PULLUP     1
-+#define MTK_PULL_PU_PD_TYPE		BIT(0)
-+#define MTK_PULL_PULLSEL_TYPE		BIT(1)
-+#define MTK_PULL_PUPD_R1R0_TYPE		BIT(2)
-+/* MTK_PULL_RSEL_TYPE can select resistance and can be
-+ * turned on/off itself. But it can't be selected pull up/down
-+ */
-+#define MTK_PULL_RSEL_TYPE		BIT(3)
-+/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
-+ * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
-+ */
-+#define MTK_PULL_PU_PD_RSEL_TYPE	(MTK_PULL_PU_PD_TYPE \
-+					| MTK_PULL_RSEL_TYPE)
-+#define MTK_PULL_TYPE_MASK	(MTK_PULL_PU_PD_TYPE |\
-+				 MTK_PULL_PULLSEL_TYPE |\
-+				 MTK_PULL_PUPD_R1R0_TYPE |\
-+				 MTK_PULL_RSEL_TYPE)
- 
- #define EINT_NA	U16_MAX
- #define NO_EINT_SUPPORT	EINT_NA
-@@ -42,6 +58,14 @@
- 	PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,	\
- 		       _x_bits, 32, 1)
- 
-+#define PIN_RSEL(_s_pin, _e_pin, _rsel_index, _up_resl, _down_rsel) {	\
-+		.s_pin = _s_pin,					\
-+		.e_pin = _e_pin,					\
-+		.rsel_index = _rsel_index,				\
-+		.up_rsel = _up_resl,					\
-+		.down_rsel = _down_rsel,				\
-+	}
-+
- /* List these attributes which could be modified for the pin */
- enum {
- 	PINCTRL_PIN_REG_MODE,
-@@ -67,6 +91,7 @@ enum {
- 	PINCTRL_PIN_REG_DRV_E0,
- 	PINCTRL_PIN_REG_DRV_E1,
- 	PINCTRL_PIN_REG_DRV_ADV,
-+	PINCTRL_PIN_REG_RSEL,
- 	PINCTRL_PIN_REG_MAX,
- };
- 
-@@ -129,6 +154,22 @@ struct mtk_pin_field_calc {
- 	u8  fixed;
- };
- 
-+/**
-+ * struct mtk_pin_rsel - the structure that provides bias resistance selection.
-+ * @s_pin:		the start pin within the rsel range
-+ * @e_pin:		the end pin within the rsel range
-+ * @rsel_index:	the rsel bias resistance index
-+ * @up_rsel:	the pullup rsel bias resistance value
-+ * @down_rsel:	the pulldown rsel bias resistance value
-+ */
-+struct mtk_pin_rsel {
-+	u16 s_pin;
-+	u16 e_pin;
-+	u16 rsel_index;
-+	u32 up_rsel;
-+	u32 down_rsel;
-+};
-+
- /* struct mtk_pin_reg_calc - the structure that holds all ranges used to
-  *			     determine which register the pin would make use of
-  *			     for certain pin attribute.
-@@ -206,6 +247,9 @@ struct mtk_pin_soc {
- 	bool				ies_present;
- 	const char * const		*base_names;
- 	unsigned int			nbase_names;
-+	const unsigned int		*pull_type;
-+	const struct mtk_pin_rsel	*pin_rsel;
-+	unsigned int			npin_rsel;
- 
- 	/* Specific pinconfig operations */
- 	int (*bias_disable_set)(struct mtk_pinctrl *hw,
-@@ -254,6 +298,8 @@ struct mtk_pinctrl {
- 	const char          **grp_names;
- 	/* lock pin's register resource to avoid multiple threads issue*/
- 	spinlock_t lock;
-+	/* identify rsel setting by si unit or rsel define in dts node */
-+	bool rsel_si_unit;
- };
- 
- void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
---- a/drivers/pinctrl/mediatek/pinctrl-paris.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
-@@ -574,8 +574,9 @@ static int mtk_hw_get_value_wrap(struct
- ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
- 	unsigned int gpio, char *buf, unsigned int buf_len)
- {
--	int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1;
-+	int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
- 	const struct mtk_pin_desc *desc;
-+	u32 try_all_type;
- 
- 	if (gpio >= hw->soc->npins)
- 		return -EINVAL;
-@@ -589,24 +590,39 @@ ssize_t mtk_pctrl_show_one_pin(struct mt
- 		pinmux -= hw->soc->nfuncs;
- 
- 	mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
--	if (pullen == MTK_PUPD_SET_R1R0_00) {
--		pullen = 0;
--		r1 = 0;
--		r0 = 0;
--	} else if (pullen == MTK_PUPD_SET_R1R0_01) {
--		pullen = 1;
--		r1 = 0;
--		r0 = 1;
--	} else if (pullen == MTK_PUPD_SET_R1R0_10) {
--		pullen = 1;
--		r1 = 1;
--		r0 = 0;
--	} else if (pullen == MTK_PUPD_SET_R1R0_11) {
-+
-+	if (hw->soc->pull_type)
-+		try_all_type = hw->soc->pull_type[desc->number];
-+
-+	if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
-+		rsel = pullen;
- 		pullen = 1;
--		r1 = 1;
--		r0 = 1;
--	} else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
--		pullen = 0;
-+	} else {
-+		/* Case for: R1R0 */
-+		if (pullen == MTK_PUPD_SET_R1R0_00) {
-+			pullen = 0;
-+			r1 = 0;
-+			r0 = 0;
-+		} else if (pullen == MTK_PUPD_SET_R1R0_01) {
-+			pullen = 1;
-+			r1 = 0;
-+			r0 = 1;
-+		} else if (pullen == MTK_PUPD_SET_R1R0_10) {
-+			pullen = 1;
-+			r1 = 1;
-+			r0 = 0;
-+		} else if (pullen == MTK_PUPD_SET_R1R0_11) {
-+			pullen = 1;
-+			r1 = 1;
-+			r0 = 1;
-+		}
-+
-+		/* Case for: RSEL */
-+		if (pullen >= MTK_PULL_SET_RSEL_000 &&
-+		    pullen <= MTK_PULL_SET_RSEL_111) {
-+			rsel = pullen - MTK_PULL_SET_RSEL_000;
-+			pullen = 1;
-+		}
- 	}
- 	len += scnprintf(buf + len, buf_len - len,
- 			"%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
-@@ -624,6 +640,8 @@ ssize_t mtk_pctrl_show_one_pin(struct mt
- 	if (r1 != -1) {
- 		len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n",
- 			r1, r0);
-+	} else if (rsel != -1) {
-+		len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel);
- 	} else {
- 		len += scnprintf(buf + len, buf_len - len, "\n");
- 	}
-@@ -966,6 +984,12 @@ int mtk_paris_pinctrl_probe(struct platf
- 
- 	hw->nbase = hw->soc->nbase_names;
- 
-+	if (of_find_property(hw->dev->of_node,
-+			     "mediatek,rsel_resistance_in_si_unit", NULL))
-+		hw->rsel_si_unit = true;
-+	else
-+		hw->rsel_si_unit = false;
-+
- 	spin_lock_init(&hw->lock);
- 
- 	err = mtk_pctrl_build_state(pdev);
diff --git a/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch b/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch
deleted file mode 100644
index 6752b4093b..0000000000
--- a/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 9f9d17c228c89e38ed612500126daf626270be9a Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Sat, 27 Nov 2021 17:08:36 +0300
-Subject: [PATCH] pinctrl: mediatek: add a check for error in
- mtk_pinconf_bias_get_rsel()
-
-All the other mtk_hw_get_value() calls have a check for "if (err)" so
-we can add one here as well.  This silences a Smatch warning:
-
-    drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:819 mtk_pinconf_bias_get_rsel()
-    error: uninitialized symbol 'pd'.
-
-Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Link: https://lore.kernel.org/r/20211127140836.GB24002@kili
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -815,6 +815,8 @@ static int mtk_pinconf_bias_get_rsel(str
- 		goto out;
- 
- 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+	if (err)
-+		goto out;
- 
- 	if (pu == 0 && pd == 0) {
- 		*pullup = 0;
diff --git a/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch b/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch
deleted file mode 100644
index 47a29fbdba..0000000000
--- a/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch
+++ /dev/null
@@ -1,297 +0,0 @@
-From e1ff91f9d2303cd4e706cc908bfca21cd17b9927 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 11 Nov 2022 10:41:06 +0100
-Subject: [PATCH] pinctrl: mediatek: Fix EINT pins input debounce time
- configuration
-
-The External Interrupt Controller (EINTC) on all of the supported
-MediaTek SoCs does support input debouncing, but not all of them
-index the debounce time values (DBNC_SETTING registers) the same way.
-
-Before this change, in some cases, as an example, requesting a debounce
-time of 16 milliseconds would mistakenly set the relative DBNC_SETTING
-register to 0x2, resulting in a way shorter debounce time of 500uS.
-
-To fix the aforementioned issue, define three different debounce_time
-arrays, reflecting the correct register index for each value and for
-each register index variant, and make sure that each SoC pinctrl
-driver uses the right one.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/mtk-eint.c       | 31 +++++++++++++++++++----
- drivers/pinctrl/mediatek/mtk-eint.h       |  6 +++++
- drivers/pinctrl/mediatek/pinctrl-mt2701.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt2712.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt6765.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt6779.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt7622.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt7623.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt7629.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8127.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8135.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8167.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8173.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8183.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8192.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8195.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8365.c |  1 +
- drivers/pinctrl/mediatek/pinctrl-mt8516.c |  1 +
- 22 files changed, 53 insertions(+), 5 deletions(-)
-
---- a/drivers/pinctrl/mediatek/mtk-eint.c
-+++ b/drivers/pinctrl/mediatek/mtk-eint.c
-@@ -24,6 +24,7 @@
- #define MTK_EINT_EDGE_SENSITIVE           0
- #define MTK_EINT_LEVEL_SENSITIVE          1
- #define MTK_EINT_DBNC_SET_DBNC_BITS	  4
-+#define MTK_EINT_DBNC_MAX		  16
- #define MTK_EINT_DBNC_RST_BIT		  (0x1 << 1)
- #define MTK_EINT_DBNC_SET_EN		  (0x1 << 0)
- 
-@@ -48,6 +49,18 @@ static const struct mtk_eint_regs mtk_ge
- 	.dbnc_clr  = 0x700,
- };
- 
-+const unsigned int debounce_time_mt2701[] = {
-+	500, 1000, 16000, 32000, 64000, 128000, 256000, 0
-+};
-+
-+const unsigned int debounce_time_mt6765[] = {
-+	125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
-+};
-+
-+const unsigned int debounce_time_mt6795[] = {
-+	500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
-+};
-+
- static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
- 					 unsigned int eint_num,
- 					 unsigned int offset)
-@@ -407,10 +420,11 @@ int mtk_eint_set_debounce(struct mtk_ein
- 	int virq, eint_offset;
- 	unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
- 		     dbnc;
--	static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
--						     64000, 128000, 256000};
- 	struct irq_data *d;
- 
-+	if (!eint->hw->db_time)
-+		return -EOPNOTSUPP;
-+
- 	virq = irq_find_mapping(eint->domain, eint_num);
- 	eint_offset = (eint_num % 4) * 8;
- 	d = irq_get_irq_data(virq);
-@@ -421,9 +435,9 @@ int mtk_eint_set_debounce(struct mtk_ein
- 	if (!mtk_eint_can_en_debounce(eint, eint_num))
- 		return -EINVAL;
- 
--	dbnc = ARRAY_SIZE(debounce_time);
--	for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
--		if (debounce <= debounce_time[i]) {
-+	dbnc = eint->num_db_time;
-+	for (i = 0; i < eint->num_db_time; i++) {
-+		if (debounce <= eint->hw->db_time[i]) {
- 			dbnc = i;
- 			break;
- 		}
-@@ -497,6 +511,13 @@ int mtk_eint_do_init(struct mtk_eint *ei
- 	if (!eint->domain)
- 		return -ENOMEM;
- 
-+	if (eint->hw->db_time) {
-+		for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
-+			if (eint->hw->db_time[i] == 0)
-+				break;
-+		eint->num_db_time = i;
-+	}
-+
- 	mtk_eint_hw_init(eint);
- 	for (i = 0; i < eint->hw->ap_num; i++) {
- 		int virq = irq_create_mapping(eint->domain, i);
---- a/drivers/pinctrl/mediatek/mtk-eint.h
-+++ b/drivers/pinctrl/mediatek/mtk-eint.h
-@@ -37,8 +37,13 @@ struct mtk_eint_hw {
- 	u8		ports;
- 	unsigned int	ap_num;
- 	unsigned int	db_cnt;
-+	const unsigned int *db_time;
- };
- 
-+extern const unsigned int debounce_time_mt2701[];
-+extern const unsigned int debounce_time_mt6765[];
-+extern const unsigned int debounce_time_mt6795[];
-+
- struct mtk_eint;
- 
- struct mtk_eint_xt {
-@@ -62,6 +67,7 @@ struct mtk_eint {
- 	/* Used to fit into various EINT device */
- 	const struct mtk_eint_hw *hw;
- 	const struct mtk_eint_regs *regs;
-+	u16 num_db_time;
- 
- 	/* Used to fit into various pinctrl device */
- 	void *pctl;
---- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
-@@ -531,6 +531,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 169,
- 		.db_cnt    = 16,
-+		.db_time   = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
-@@ -584,6 +584,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 8,
- 		.ap_num    = 229,
- 		.db_cnt    = 40,
-+		.db_time   = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
-@@ -1062,6 +1062,7 @@ static const struct mtk_eint_hw mt6765_e
- 	.ports     = 6,
- 	.ap_num    = 160,
- 	.db_cnt    = 13,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt6765_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
-@@ -737,6 +737,7 @@ static const struct mtk_eint_hw mt6779_e
- 	.ports     = 6,
- 	.ap_num    = 195,
- 	.db_cnt    = 13,
-+	.db_time   = debounce_time_mt2701,
- };
- 
- static const struct mtk_pin_soc mt6779_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-@@ -846,6 +846,7 @@ static const struct mtk_eint_hw mt7622_e
- 	.ports     = 7,
- 	.ap_num    = ARRAY_SIZE(mt7622_pins),
- 	.db_cnt    = 20,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt7622_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-@@ -1369,6 +1369,7 @@ static const struct mtk_eint_hw mt7623_e
- 	.ports     = 6,
- 	.ap_num    = 169,
- 	.db_cnt    = 20,
-+	.db_time   = debounce_time_mt2701,
- };
- 
- static struct mtk_pin_soc mt7623_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-@@ -402,6 +402,7 @@ static const struct mtk_eint_hw mt7629_e
- 	.ports     = 7,
- 	.ap_num    = ARRAY_SIZE(mt7629_pins),
- 	.db_cnt    = 16,
-+	.db_time   = debounce_time_mt2701,
- };
- 
- static struct mtk_pin_soc mt7629_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
-@@ -300,6 +300,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 143,
- 		.db_cnt    = 16,
-+		.db_time = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
-@@ -313,6 +313,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 192,
- 		.db_cnt    = 16,
-+		.db_time = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
-@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 169,
- 		.db_cnt    = 64,
-+		.db_time = debounce_time_mt6795,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
-@@ -340,6 +340,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 224,
- 		.db_cnt    = 16,
-+		.db_time   = debounce_time_mt2701,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
-@@ -545,6 +545,7 @@ static const struct mtk_eint_hw mt8183_e
- 	.ports     = 6,
- 	.ap_num    = 212,
- 	.db_cnt    = 13,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt8183_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c
-@@ -1339,6 +1339,7 @@ static const struct mtk_eint_hw mt8192_e
- 	.ports     = 7,
- 	.ap_num    = 224,
- 	.db_cnt    = 32,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
-@@ -805,6 +805,7 @@ static const struct mtk_eint_hw mt8195_e
- 	.ports     = 7,
- 	.ap_num    = 225,
- 	.db_cnt    = 32,
-+	.db_time   = debounce_time_mt6765,
- };
- 
- static const struct mtk_pin_soc mt8195_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
-@@ -466,6 +466,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 5,
- 		.ap_num = 160,
- 		.db_cnt = 160,
-+		.db_time   = debounce_time_mt6765,
- 	},
- };
- 
---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
- 		.ports     = 6,
- 		.ap_num    = 169,
- 		.db_cnt    = 64,
-+		.db_time   = debounce_time_mt6795,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch b/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch
deleted file mode 100644
index 92f4e842e8..0000000000
--- a/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 2e35b25dd8e666b8619355fc3defb1b246a5dc02 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Tue, 15 Nov 2022 09:11:07 +0100
-Subject: [PATCH] pinctrl: mediatek: Export debounce time tables
-
-The kernel test robot complains that in certain combinations
-when building the Mediatek drivers as modules we lack some
-debounce table symbols, so export them.
-
-Reported-by: kernel test robot <lkp@intel.com>
-Fixes: e1ff91f9d230 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration")
-Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/mtk-eint.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/pinctrl/mediatek/mtk-eint.c
-+++ b/drivers/pinctrl/mediatek/mtk-eint.c
-@@ -52,14 +52,17 @@ static const struct mtk_eint_regs mtk_ge
- const unsigned int debounce_time_mt2701[] = {
- 	500, 1000, 16000, 32000, 64000, 128000, 256000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt2701);
- 
- const unsigned int debounce_time_mt6765[] = {
- 	125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt6765);
- 
- const unsigned int debounce_time_mt6795[] = {
- 	500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt6795);
- 
- static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
- 					 unsigned int eint_num,
diff --git a/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch
deleted file mode 100644
index f130fdbc56..0000000000
--- a/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:01:12 +0100
-Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias
- functions
-
-Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo
-and mtk_pinconf_bias_get_combo, and make the functions able to support
-almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c.
-
-This patch enables pinctrl_moore to support these functions.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++----
- 1 file changed, 42 insertions(+), 7 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-moore.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
-@@ -8,6 +8,7 @@
-  *
-  */
- 
-+#include <dt-bindings/pinctrl/mt65xx.h>
- #include <linux/gpio/driver.h>
- #include "pinctrl-moore.h"
- 
-@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr
- {
- 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
- 	u32 param = pinconf_to_config_param(*config);
--	int val, val2, err, reg, ret = 1;
-+	int val, val2, err, pullup, reg, ret = 1;
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr
- 
- 	switch (param) {
- 	case PIN_CONFIG_BIAS_DISABLE:
--		if (hw->soc->bias_disable_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_disable_get) {
- 			err = hw->soc->bias_disable_get(hw, desc, &ret);
- 			if (err)
- 				return err;
-@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr
- 		}
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_UP:
--		if (hw->soc->bias_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+				return -EINVAL;
-+			if (!pullup)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_get) {
- 			err = hw->soc->bias_get(hw, desc, 1, &ret);
- 			if (err)
- 				return err;
-@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr
- 		}
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_DOWN:
--		if (hw->soc->bias_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+				return -EINVAL;
-+			if (pullup)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_get) {
- 			err = hw->soc->bias_get(hw, desc, 0, &ret);
- 			if (err)
- 				return err;
-@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr
- 
- 		switch (param) {
- 		case PIN_CONFIG_BIAS_DISABLE:
--			if (hw->soc->bias_disable_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_disable_set) {
- 				err = hw->soc->bias_disable_set(hw, desc);
- 				if (err)
- 					return err;
-@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr
- 			}
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_UP:
--			if (hw->soc->bias_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 1, arg);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_set) {
- 				err = hw->soc->bias_set(hw, desc, 1);
- 				if (err)
- 					return err;
-@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr
- 			}
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_DOWN:
--			if (hw->soc->bias_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 0, arg);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_set) {
- 				err = hw->soc->bias_set(hw, desc, 0);
- 				if (err)
- 					return err;
diff --git a/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch b/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch
deleted file mode 100644
index 30891d3487..0000000000
--- a/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From b77e70f6b8f2cc62fba847f3008a430a09ef275d Mon Sep 17 00:00:00 2001
-From: ChiYuan Huang <cy_huang@richtek.com>
-Date: Wed, 9 Mar 2022 16:01:42 +0800
-Subject: [PATCH 1/2] regulator: Add bindings for Richtek RT5190A PMIC
-
-Add bindings for Richtek RT5190A PMIC.
-
-Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
-Link: https://lore.kernel.org/r/1646812903-32496-2-git-send-email-u0084500@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../regulator/richtek,rt5190a-regulator.yaml  | 141 ++++++++++++++++++
- .../regulator/richtek,rt5190a-regulator.h     |  15 ++
- 2 files changed, 156 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml
- create mode 100644 include/dt-bindings/regulator/richtek,rt5190a-regulator.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml
-@@ -0,0 +1,141 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/regulator/richtek,rt5190a-regulator.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Richtek RT5190A PMIC Regulator
-+
-+maintainers:
-+  - ChiYuan Huang <cy_huang@richtek.com>
-+
-+description: |
-+  The RT5190A integrates 1 channel buck controller, 3 channels high efficiency
-+  synchronous buck converters, 1 LDO, I2C control interface and peripherial
-+  logical control.
-+
-+  It also supports mute AC OFF depop sound and quick setting storage while
-+  input power is removed.
-+
-+properties:
-+  compatible:
-+    enum:
-+      - richtek,rt5190a
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  vin2-supply:
-+    description: phandle to buck2 input voltage.
-+
-+  vin3-supply:
-+    description: phandle to buck3 input voltage.
-+
-+  vin4-supply:
-+    description: phandle to buck4 input voltage.
-+
-+  vinldo-supply:
-+    description: phandle to ldo input voltage
-+
-+  richtek,mute-enable:
-+    description: |
-+      The mute function uses 'mutein', 'muteout', and 'vdet' pins as the control
-+      signal. When enabled, The normal behavior is to bypass the 'mutein' signal
-+      'muteout'. But if the power source removal is detected from 'vdet',
-+      whatever the 'mutein' signal is, it will pull down the 'muteout' to force
-+      speakers mute. this function is commonly used to prevent the speaker pop
-+      noise during AC power turned off in the modern TV system design.
-+    type: boolean
-+
-+  regulators:
-+    type: object
-+
-+    patternProperties:
-+      "^buck[1-4]$|^ldo$":
-+        type: object
-+        $ref: regulator.yaml#
-+        description: |
-+          regulator description for buck1 and buck4.
-+
-+        properties:
-+          regulator-allowed-modes:
-+            description: |
-+             buck operating mode, only buck1/4 support mode operating.
-+              0: auto mode
-+              1: force pwm mode
-+            items:
-+              enum: [0, 1]
-+
-+          richtek,latchup-enable:
-+            type: boolean
-+            description: |
-+              If specified, undervolt protection mode changes from the default
-+              hiccup to latchup.
-+
-+        unevaluatedProperties: false
-+
-+    additionalProperties: false
-+
-+required:
-+  - compatible
-+  - reg
-+  - regulators
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+    #include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-+
-+    i2c {
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+
-+      pmic@64 {
-+        compatible = "richtek,rt5190a";
-+        reg = <0x64>;
-+        interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
-+        vin2-supply = <&rt5190_buck1>;
-+        vin3-supply = <&rt5190_buck1>;
-+        vin4-supply = <&rt5190_buck1>;
-+
-+        regulators {
-+          rt5190_buck1: buck1 {
-+            regulator-name = "rt5190a-buck1";
-+            regulator-min-microvolt = <5090000>;
-+            regulator-max-microvolt = <5090000>;
-+            regulator-allowed-modes = <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-+            regulator-boot-on;
-+          };
-+          buck2 {
-+            regulator-name = "rt5190a-buck2";
-+            regulator-min-microvolt = <600000>;
-+            regulator-max-microvolt = <1400000>;
-+            regulator-boot-on;
-+          };
-+          buck3 {
-+            regulator-name = "rt5190a-buck3";
-+            regulator-min-microvolt = <600000>;
-+            regulator-max-microvolt = <1400000>;
-+            regulator-boot-on;
-+          };
-+          buck4 {
-+            regulator-name = "rt5190a-buck4";
-+            regulator-min-microvolt = <850000>;
-+            regulator-max-microvolt = <850000>;
-+            regulator-allowed-modes = <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-+            regulator-boot-on;
-+          };
-+          ldo {
-+            regulator-name = "rt5190a-ldo";
-+            regulator-min-microvolt = <1200000>;
-+            regulator-max-microvolt = <1200000>;
-+            regulator-boot-on;
-+          };
-+        };
-+      };
-+    };
---- /dev/null
-+++ b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+
-+#ifndef __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__
-+#define __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__
-+
-+/*
-+ * BUCK/LDO mode constants which may be used in devicetree properties
-+ * (eg. regulator-allowed-modes).
-+ * See the manufacturer's datasheet for more information on these modes.
-+ */
-+
-+#define RT5190A_OPMODE_AUTO	0
-+#define RT5190A_OPMODE_FPWM	1
-+
-+#endif
diff --git a/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch b/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch
deleted file mode 100644
index 0e0f099e50..0000000000
--- a/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch
+++ /dev/null
@@ -1,562 +0,0 @@
-From 760423dfad53877b468490758fe7ea968ded9402 Mon Sep 17 00:00:00 2001
-From: ChiYuan Huang <cy_huang@richtek.com>
-Date: Wed, 9 Mar 2022 16:01:43 +0800
-Subject: [PATCH 2/2] regulator: rt5190a: Add support for Richtek RT5190A PMIC
-
-Add support for Richtek RT5190A PMIC.
-
-Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
-Link: https://lore.kernel.org/r/1646812903-32496-3-git-send-email-u0084500@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/Kconfig             |  10 +
- drivers/regulator/Makefile            |   1 +
- drivers/regulator/rt5190a-regulator.c | 513 ++++++++++++++++++++++++++
- 3 files changed, 524 insertions(+)
- create mode 100644 drivers/regulator/rt5190a-regulator.c
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -1037,6 +1037,16 @@ config REGULATOR_RT5033
- 	  RT5033 PMIC. The device supports multiple regulators like
- 	  current source, LDO and Buck.
- 
-+config REGULATOR_RT5190A
-+	tristate "Richtek RT5190A PMIC"
-+	depends on I2C
-+	select REGMAP_I2C
-+	help
-+	  This adds support for voltage regulator in Richtek RT5190A PMIC.
-+	  It integratas 1 channel buck controller, 3 channels high efficiency
-+	  buck converters, 1 LDO, mute AC OFF depop function, with the general
-+	  I2C control interface.
-+
- config REGULATOR_RT6160
- 	tristate "Richtek RT6160 BuckBoost voltage regulator"
- 	depends on I2C
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -125,6 +125,7 @@ obj-$(CONFIG_REGULATOR_ROHM)	+= rohm-reg
- obj-$(CONFIG_REGULATOR_RT4801)	+= rt4801-regulator.o
- obj-$(CONFIG_REGULATOR_RT4831)	+= rt4831-regulator.o
- obj-$(CONFIG_REGULATOR_RT5033)	+= rt5033-regulator.o
-+obj-$(CONFIG_REGULATOR_RT5190A) += rt5190a-regulator.o
- obj-$(CONFIG_REGULATOR_RT6160)	+= rt6160-regulator.o
- obj-$(CONFIG_REGULATOR_RT6245)	+= rt6245-regulator.o
- obj-$(CONFIG_REGULATOR_RTMV20)	+= rtmv20-regulator.o
---- /dev/null
-+++ b/drivers/regulator/rt5190a-regulator.c
-@@ -0,0 +1,513 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+
-+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-+#include <linux/bits.h>
-+#include <linux/i2c.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/property.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/of_regulator.h>
-+
-+#define RT5190A_REG_MANUFACTURE		0x00
-+#define RT5190A_REG_BUCK2VSEL		0x04
-+#define RT5190A_REG_BUCK3VSEL		0x05
-+#define RT5190A_REG_DCDCCNTL		0x06
-+#define RT5190A_REG_ENABLE		0x07
-+#define RT5190A_REG_DISCHARGE		0x09
-+#define RT5190A_REG_PROTMODE		0x0A
-+#define RT5190A_REG_MUTECNTL		0x0B
-+#define RT5190A_REG_PGSTAT		0x0F
-+#define RT5190A_REG_OVINT		0x10
-+#define RT5190A_REG_HOTDIEMASK		0x17
-+
-+#define RT5190A_VSEL_MASK		GENMASK(6, 0)
-+#define RT5190A_RID_BITMASK(rid)	BIT(rid + 1)
-+#define RT5190A_BUCK1_DISCHG_MASK	GENMASK(1, 0)
-+#define RT5190A_BUCK1_DISCHG_ONVAL	0x01
-+#define RT5190A_OVERVOLT_MASK		GENMASK(7, 0)
-+#define RT5190A_UNDERVOLT_MASK		GENMASK(15, 8)
-+#define RT5190A_CH234OT_MASK		BIT(29)
-+#define RT5190A_CHIPOT_MASK		BIT(28)
-+
-+#define RT5190A_BUCK23_MINUV		600000
-+#define RT5190A_BUCK23_MAXUV		1400000
-+#define RT5190A_BUCK23_STEPUV		10000
-+#define RT5190A_BUCK23_STEPNUM		((1400000 - 600000) / 10000 + 1)
-+
-+enum {
-+	RT5190A_IDX_BUCK1 = 0,
-+	RT5190A_IDX_BUCK2,
-+	RT5190A_IDX_BUCK3,
-+	RT5190A_IDX_BUCK4,
-+	RT5190A_IDX_LDO,
-+	RT5190A_MAX_IDX
-+};
-+
-+struct rt5190a_priv {
-+	struct device *dev;
-+	struct regmap *regmap;
-+	struct regulator_desc rdesc[RT5190A_MAX_IDX];
-+	struct regulator_dev *rdev[RT5190A_MAX_IDX];
-+};
-+
-+static int rt5190a_get_error_flags(struct regulator_dev *rdev,
-+				   unsigned int *flags)
-+{
-+	struct regmap *regmap = rdev_get_regmap(rdev);
-+	int rid = rdev_get_id(rdev);
-+	unsigned int pgood_stat;
-+	int ret;
-+
-+	ret = regmap_read(regmap, RT5190A_REG_PGSTAT, &pgood_stat);
-+	if (ret)
-+		return ret;
-+
-+	if (!(pgood_stat & RT5190A_RID_BITMASK(rid)))
-+		*flags = REGULATOR_ERROR_FAIL;
-+	else
-+		*flags = 0;
-+
-+	return 0;
-+}
-+
-+static int rt5190a_fixed_buck_set_mode(struct regulator_dev *rdev,
-+				       unsigned int mode)
-+{
-+	struct regmap *regmap = rdev_get_regmap(rdev);
-+	int rid = rdev_get_id(rdev);
-+	unsigned int mask = RT5190A_RID_BITMASK(rid), val;
-+
-+	switch (mode) {
-+	case REGULATOR_MODE_FAST:
-+		val = mask;
-+		break;
-+	case REGULATOR_MODE_NORMAL:
-+		val = 0;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return regmap_update_bits(regmap, RT5190A_REG_DCDCCNTL, mask, val);
-+}
-+
-+static unsigned int rt5190a_fixed_buck_get_mode(struct regulator_dev *rdev)
-+{
-+	struct regmap *regmap = rdev_get_regmap(rdev);
-+	int rid = rdev_get_id(rdev);
-+	unsigned int val;
-+	int ret;
-+
-+	ret = regmap_read(regmap, RT5190A_REG_DCDCCNTL, &val);
-+	if (ret) {
-+		dev_err(&rdev->dev, "Failed to get mode [%d]\n", ret);
-+		return ret;
-+	}
-+
-+	if (val & RT5190A_RID_BITMASK(rid))
-+		return REGULATOR_MODE_FAST;
-+
-+	return REGULATOR_MODE_NORMAL;
-+}
-+
-+static const struct regulator_ops rt5190a_ranged_buck_ops = {
-+	.enable	= regulator_enable_regmap,
-+	.disable = regulator_disable_regmap,
-+	.is_enabled = regulator_is_enabled_regmap,
-+	.set_voltage_sel = regulator_set_voltage_sel_regmap,
-+	.get_voltage_sel = regulator_get_voltage_sel_regmap,
-+	.list_voltage = regulator_list_voltage_linear,
-+	.set_active_discharge = regulator_set_active_discharge_regmap,
-+	.get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static const struct regulator_ops rt5190a_fixed_buck_ops = {
-+	.enable	= regulator_enable_regmap,
-+	.disable = regulator_disable_regmap,
-+	.is_enabled = regulator_is_enabled_regmap,
-+	.set_active_discharge = regulator_set_active_discharge_regmap,
-+	.set_mode = rt5190a_fixed_buck_set_mode,
-+	.get_mode = rt5190a_fixed_buck_get_mode,
-+	.get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static const struct regulator_ops rt5190a_fixed_ldo_ops = {
-+	.enable	= regulator_enable_regmap,
-+	.disable = regulator_disable_regmap,
-+	.is_enabled = regulator_is_enabled_regmap,
-+	.set_active_discharge = regulator_set_active_discharge_regmap,
-+	.get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static irqreturn_t rt5190a_irq_handler(int irq, void *data)
-+{
-+	struct rt5190a_priv *priv = data;
-+	__le32 raws;
-+	unsigned int events, fields;
-+	static const struct {
-+		unsigned int bitmask;
-+		unsigned int report;
-+	} event_tbl[] = {
-+		{ RT5190A_OVERVOLT_MASK, REGULATOR_ERROR_REGULATION_OUT },
-+		{ RT5190A_UNDERVOLT_MASK, REGULATOR_ERROR_UNDER_VOLTAGE }
-+	};
-+	int i, j, ret;
-+
-+	ret = regmap_raw_read(priv->regmap, RT5190A_REG_OVINT, &raws,
-+			      sizeof(raws));
-+	if (ret) {
-+		dev_err(priv->dev, "Failed to read events\n");
-+		return IRQ_NONE;
-+	}
-+
-+	events = le32_to_cpu(raws);
-+
-+	ret = regmap_raw_write(priv->regmap, RT5190A_REG_OVINT, &raws,
-+			       sizeof(raws));
-+	if (ret)
-+		dev_err(priv->dev, "Failed to write-clear events\n");
-+
-+	/* Handle OV,UV events */
-+	for (i = 0; i < ARRAY_SIZE(event_tbl); i++) {
-+		fields = events & event_tbl[i].bitmask;
-+		fields >>= ffs(event_tbl[i].bitmask) - 1;
-+
-+		for (j = 0; j < RT5190A_MAX_IDX; j++) {
-+			if (!(fields & RT5190A_RID_BITMASK(j)))
-+				continue;
-+
-+			regulator_notifier_call_chain(priv->rdev[j],
-+						      event_tbl[i].report,
-+						      NULL);
-+		}
-+	}
-+
-+	/* Handle CH234 OT event */
-+	if (events & RT5190A_CH234OT_MASK) {
-+		for (j = RT5190A_IDX_BUCK2; j < RT5190A_IDX_LDO; j++) {
-+			regulator_notifier_call_chain(priv->rdev[j],
-+						      REGULATOR_ERROR_OVER_TEMP,
-+						      NULL);
-+		}
-+	}
-+
-+	/* Warning if CHIP OT occur */
-+	if (events & RT5190A_CHIPOT_MASK)
-+		dev_warn(priv->dev, "CHIP overheat\n");
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static unsigned int rt5190a_of_map_mode(unsigned int mode)
-+{
-+	switch (mode) {
-+	case RT5190A_OPMODE_AUTO:
-+		return REGULATOR_MODE_NORMAL;
-+	case RT5190A_OPMODE_FPWM:
-+		return REGULATOR_MODE_FAST;
-+	default:
-+		return REGULATOR_MODE_INVALID;
-+	}
-+}
-+
-+static int rt5190a_of_parse_cb(struct rt5190a_priv *priv, int rid,
-+			       struct of_regulator_match *match)
-+{
-+	struct regulator_desc *desc = priv->rdesc + rid;
-+	struct regulator_init_data *init_data = match->init_data;
-+	struct device_node *np = match->of_node;
-+	bool latchup_enable;
-+	unsigned int mask = RT5190A_RID_BITMASK(rid), val;
-+
-+	switch (rid) {
-+	case RT5190A_IDX_BUCK1:
-+	case RT5190A_IDX_BUCK4:
-+	case RT5190A_IDX_LDO:
-+		init_data->constraints.apply_uV = 0;
-+
-+		if (init_data->constraints.min_uV ==
-+				init_data->constraints.max_uV)
-+			desc->fixed_uV = init_data->constraints.min_uV;
-+		else {
-+			dev_err(priv->dev,
-+				"Variable voltage for fixed regulator\n");
-+			return -EINVAL;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	latchup_enable = of_property_read_bool(np, "richtek,latchup-enable");
-+
-+	/* latchup: 0, default hiccup: 1 */
-+	val = !latchup_enable ? mask : 0;
-+
-+	return regmap_update_bits(priv->regmap, RT5190A_REG_PROTMODE, mask, val);
-+}
-+
-+static void rt5190a_fillin_regulator_desc(struct regulator_desc *desc, int rid)
-+{
-+	static const char * const regu_name[] = { "buck1", "buck2",
-+						  "buck3", "buck4",
-+						  "ldo" };
-+	static const char * const supply[] = { NULL, "vin2", "vin3", "vin4",
-+					       "vinldo" };
-+
-+	desc->name = regu_name[rid];
-+	desc->supply_name = supply[rid];
-+	desc->owner = THIS_MODULE;
-+	desc->type = REGULATOR_VOLTAGE;
-+	desc->id = rid;
-+	desc->enable_reg = RT5190A_REG_ENABLE;
-+	desc->enable_mask = RT5190A_RID_BITMASK(rid);
-+	desc->active_discharge_reg = RT5190A_REG_DISCHARGE;
-+	desc->active_discharge_mask = RT5190A_RID_BITMASK(rid);
-+	desc->active_discharge_on = RT5190A_RID_BITMASK(rid);
-+
-+	switch (rid) {
-+	case RT5190A_IDX_BUCK1:
-+		desc->active_discharge_mask = RT5190A_BUCK1_DISCHG_MASK;
-+		desc->active_discharge_on = RT5190A_BUCK1_DISCHG_ONVAL;
-+		desc->n_voltages = 1;
-+		desc->ops = &rt5190a_fixed_buck_ops;
-+		desc->of_map_mode = rt5190a_of_map_mode;
-+		break;
-+	case RT5190A_IDX_BUCK2:
-+		desc->vsel_reg = RT5190A_REG_BUCK2VSEL;
-+		desc->vsel_mask = RT5190A_VSEL_MASK;
-+		desc->min_uV = RT5190A_BUCK23_MINUV;
-+		desc->uV_step = RT5190A_BUCK23_STEPUV;
-+		desc->n_voltages = RT5190A_BUCK23_STEPNUM;
-+		desc->ops = &rt5190a_ranged_buck_ops;
-+		break;
-+	case RT5190A_IDX_BUCK3:
-+		desc->vsel_reg = RT5190A_REG_BUCK3VSEL;
-+		desc->vsel_mask = RT5190A_VSEL_MASK;
-+		desc->min_uV = RT5190A_BUCK23_MINUV;
-+		desc->uV_step = RT5190A_BUCK23_STEPUV;
-+		desc->n_voltages = RT5190A_BUCK23_STEPNUM;
-+		desc->ops = &rt5190a_ranged_buck_ops;
-+		break;
-+	case RT5190A_IDX_BUCK4:
-+		desc->n_voltages = 1;
-+		desc->ops = &rt5190a_fixed_buck_ops;
-+		desc->of_map_mode = rt5190a_of_map_mode;
-+		break;
-+	case RT5190A_IDX_LDO:
-+		desc->n_voltages = 1;
-+		desc->ops = &rt5190a_fixed_ldo_ops;
-+		break;
-+	}
-+}
-+
-+static struct of_regulator_match rt5190a_regulator_match[] = {
-+	{ .name = "buck1", },
-+	{ .name = "buck2", },
-+	{ .name = "buck3", },
-+	{ .name = "buck4", },
-+	{ .name = "ldo", }
-+};
-+
-+static int rt5190a_parse_regulator_dt_data(struct rt5190a_priv *priv)
-+{
-+	struct device_node *regulator_np;
-+	struct regulator_desc *reg_desc;
-+	struct of_regulator_match *match;
-+	int i, ret;
-+
-+	for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+		reg_desc = priv->rdesc + i;
-+		match = rt5190a_regulator_match + i;
-+
-+		rt5190a_fillin_regulator_desc(reg_desc, i);
-+
-+		match->desc = reg_desc;
-+	}
-+
-+	regulator_np = of_get_child_by_name(priv->dev->of_node, "regulators");
-+	if (!regulator_np) {
-+		dev_err(priv->dev, "Could not find 'regulators' node\n");
-+		return -ENODEV;
-+	}
-+
-+	ret = of_regulator_match(priv->dev, regulator_np,
-+				 rt5190a_regulator_match,
-+				 ARRAY_SIZE(rt5190a_regulator_match));
-+
-+	of_node_put(regulator_np);
-+
-+	if (ret < 0) {
-+		dev_err(priv->dev,
-+			"Error parsing regulator init data: %d\n", ret);
-+		return ret;
-+	}
-+
-+	for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+		match = rt5190a_regulator_match + i;
-+
-+		ret = rt5190a_of_parse_cb(priv, i, match);
-+		if (ret) {
-+			dev_err(priv->dev, "Failed in [%d] of_parse_cb\n", i);
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct reg_sequence rt5190a_init_patch[] = {
-+	{ 0x09, 0x3d, },
-+	{ 0x0a, 0x3e, },
-+	{ 0x0b, 0x01, },
-+	{ 0x10, 0xff, },
-+	{ 0x11, 0xff, },
-+	{ 0x12, 0xff, },
-+	{ 0x13, 0xff, },
-+	{ 0x14, 0, },
-+	{ 0x15, 0, },
-+	{ 0x16, 0x3e, },
-+	{ 0x17, 0, }
-+};
-+
-+static int rt5190a_device_initialize(struct rt5190a_priv *priv)
-+{
-+	bool mute_enable;
-+	int ret;
-+
-+	ret = regmap_register_patch(priv->regmap, rt5190a_init_patch,
-+				    ARRAY_SIZE(rt5190a_init_patch));
-+	if (ret) {
-+		dev_err(priv->dev, "Failed to do register patch\n");
-+		return ret;
-+	}
-+
-+	mute_enable = device_property_read_bool(priv->dev,
-+						"richtek,mute-enable");
-+
-+	if (mute_enable) {
-+		ret = regmap_write(priv->regmap, RT5190A_REG_MUTECNTL, 0x00);
-+		if (ret) {
-+			dev_err(priv->dev, "Failed to enable mute function\n");
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int rt5190a_device_check(struct rt5190a_priv *priv)
-+{
-+	u16 devid;
-+	int ret;
-+
-+	ret = regmap_raw_read(priv->regmap, RT5190A_REG_MANUFACTURE, &devid,
-+			      sizeof(devid));
-+	if (ret)
-+		return ret;
-+
-+	if (devid) {
-+		dev_err(priv->dev, "Incorrect device id 0x%04x\n", devid);
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct regmap_config rt5190a_regmap_config = {
-+	.reg_bits = 8,
-+	.val_bits = 8,
-+	.max_register = RT5190A_REG_HOTDIEMASK,
-+};
-+
-+static int rt5190a_probe(struct i2c_client *i2c)
-+{
-+	struct rt5190a_priv *priv;
-+	struct regulator_config cfg = {};
-+	int i, ret;
-+
-+	priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->dev = &i2c->dev;
-+
-+	priv->regmap = devm_regmap_init_i2c(i2c, &rt5190a_regmap_config);
-+	if (IS_ERR(priv->regmap)) {
-+		dev_err(&i2c->dev, "Failed to allocate regmap\n");
-+		return PTR_ERR(priv->regmap);
-+	}
-+
-+	ret = rt5190a_device_check(priv);
-+	if (ret) {
-+		dev_err(&i2c->dev, "Failed to check device %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = rt5190a_device_initialize(priv);
-+	if (ret) {
-+		dev_err(&i2c->dev, "Failed to initialize the device\n");
-+		return ret;
-+	}
-+
-+	ret = rt5190a_parse_regulator_dt_data(priv);
-+	if (ret) {
-+		dev_err(&i2c->dev, "Failed to parse regulator dt\n");
-+		return ret;
-+	}
-+
-+	cfg.dev = &i2c->dev;
-+	cfg.regmap = priv->regmap;
-+
-+	for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+		struct regulator_desc *desc = priv->rdesc + i;
-+		struct of_regulator_match *match = rt5190a_regulator_match + i;
-+
-+		cfg.init_data = match->init_data;
-+		cfg.of_node = match->of_node;
-+
-+		priv->rdev[i] = devm_regulator_register(&i2c->dev, desc, &cfg);
-+		if (IS_ERR(priv->rdev[i])) {
-+			dev_err(&i2c->dev, "Failed to register regulator %s\n",
-+				desc->name);
-+			return PTR_ERR(priv->rdev[i]);
-+		}
-+	}
-+
-+	if (i2c->irq) {
-+		ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
-+						rt5190a_irq_handler,
-+						IRQF_ONESHOT,
-+						dev_name(&i2c->dev), priv);
-+		if (ret) {
-+			dev_err(&i2c->dev, "Failed to register interrupt\n");
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id __maybe_unused rt5190a_device_table[] = {
-+	{ .compatible = "richtek,rt5190a", },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, rt5190a_device_table);
-+
-+static struct i2c_driver rt5190a_driver = {
-+	.driver = {
-+		.name = "rt5190a",
-+		.of_match_table = rt5190a_device_table,
-+	},
-+	.probe_new = rt5190a_probe,
-+};
-+module_i2c_driver(rt5190a_driver);
-+
-+MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
-+MODULE_DESCRIPTION("Richtek RT5190A Regulator Driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch b/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch
deleted file mode 100644
index 8b01196409..0000000000
--- a/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 95e4dfbf33dc0a0843ba20db811f7ea271235e1e Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sun, 10 Oct 2021 15:05:12 +0800
-Subject: [PATCH 01/16] i2c: mediatek: Reset the handshake signal between i2c
- and dma
-
-Due to changes in the hardware design of the handshaking signal
-between i2c and dma, it is necessary to reset the handshaking
-signal before each transfer to ensure that the multi-msgs can
-be transferred correctly.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -15,6 +15,7 @@
- #include <linux/init.h>
- #include <linux/interrupt.h>
- #include <linux/io.h>
-+#include <linux/iopoll.h>
- #include <linux/kernel.h>
- #include <linux/mm.h>
- #include <linux/module.h>
-@@ -49,6 +50,8 @@
- #define I2C_RD_TRANAC_VALUE		0x0001
- #define I2C_SCL_MIS_COMP_VALUE		0x0000
- #define I2C_CHN_CLR_FLAG		0x0000
-+#define I2C_RELIABILITY		0x0010
-+#define I2C_DMAACK_ENABLE		0x0008
- 
- #define I2C_DMA_CON_TX			0x0000
- #define I2C_DMA_CON_RX			0x0001
-@@ -851,6 +854,7 @@ static int mtk_i2c_do_transfer(struct mt
- 	u16 restart_flag = 0;
- 	u16 dma_sync = 0;
- 	u32 reg_4g_mode;
-+	u32 reg_dma_reset;
- 	u8 *dma_rd_buf = NULL;
- 	u8 *dma_wr_buf = NULL;
- 	dma_addr_t rpaddr = 0;
-@@ -864,6 +868,28 @@ static int mtk_i2c_do_transfer(struct mt
- 
- 	reinit_completion(&i2c->msg_complete);
- 
-+	if (i2c->dev_comp->apdma_sync &&
-+	    i2c->op != I2C_MASTER_WRRD && num > 1) {
-+		mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
-+		writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
-+		       i2c->pdmabase + OFFSET_RST);
-+
-+		ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
-+					 reg_dma_reset,
-+					 !(reg_dma_reset & I2C_DMA_WARM_RST),
-+					 0, 100);
-+		if (ret) {
-+			dev_err(i2c->dev, "DMA warm reset timeout\n");
-+			return -ETIMEDOUT;
-+		}
-+
-+		writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
-+		mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
-+		mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
-+		mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
-+			       OFFSET_DEBUGCTRL);
-+	}
-+
- 	control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
- 			~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
- 	if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
diff --git a/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch b/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch
deleted file mode 100644
index a2d2521c77..0000000000
--- a/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sun, 10 Oct 2021 15:05:13 +0800
-Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout
- occurs
-
-When a timeout error occurs in i2c transter, it is usually related
-to the i2c/dma IP hardware configuration. Therefore, the purpose of
-this patch is to dump the key register values of i2c/dma when a
-timeout occurs in i2c for debugging.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET {
- 	OFFSET_HS,
- 	OFFSET_SOFTRESET,
- 	OFFSET_DCM_EN,
-+	OFFSET_MULTI_DMA,
- 	OFFSET_PATH_DIR,
- 	OFFSET_DEBUGSTAT,
- 	OFFSET_DEBUGCTRL,
-@@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = {
- 	[OFFSET_TRANSFER_LEN_AUX] = 0x44,
- 	[OFFSET_CLOCK_DIV] = 0x48,
- 	[OFFSET_SOFTRESET] = 0x50,
-+	[OFFSET_MULTI_DMA] = 0x8c,
- 	[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
- 	[OFFSET_DEBUGSTAT] = 0xe4,
- 	[OFFSET_DEBUGCTRL] = 0xe8,
-@@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_
- 	return 0;
- }
- 
-+static void i2c_dump_register(struct mtk_i2c *i2c)
-+{
-+	dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
-+		mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
-+	dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
-+		mtk_i2c_readw(i2c, OFFSET_CONTROL));
-+	dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
-+		mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
-+	dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
-+		mtk_i2c_readw(i2c, OFFSET_TIMING));
-+	dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_START),
-+		mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
-+	dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_HS),
-+		mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
-+	dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_DCM_EN),
-+		mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
-+	dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
-+		mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
-+	dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
-+		mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
-+		mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
-+	if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
-+		dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
-+			mtk_i2c_readw(i2c, OFFSET_LTIMING),
-+			mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
-+	}
-+	dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_INT_FLAG),
-+		readl(i2c->pdmabase + OFFSET_INT_EN));
-+	dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_EN),
-+		readl(i2c->pdmabase + OFFSET_CON));
-+	dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
-+		readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
-+	dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
-+		readl(i2c->pdmabase + OFFSET_TX_LEN),
-+		readl(i2c->pdmabase + OFFSET_RX_LEN));
-+	dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
-+		readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
-+		readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
-+}
-+
- static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
- 			       int num, int left_num)
- {
-@@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt
- 
- 	if (ret == 0) {
- 		dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
-+		i2c_dump_register(i2c);
- 		mtk_i2c_init_hw(i2c);
- 		return -ETIMEDOUT;
- 	}
diff --git a/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch b/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch
deleted file mode 100644
index 184fe94ff8..0000000000
--- a/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 83630e3c6147bf7bb18a18f3d5a99462464f450b Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Tue, 25 Jan 2022 19:04:13 +0800
-Subject: [PATCH 03/16] i2c: mediatek: Add i2c compatible for Mediatek MT8186
-
-Add i2c compatible for MT8186. Compare to MT8192 i2c controller,
-MT8186 doesn't need handshake signal witch apdma.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -397,6 +397,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt8186_compat = {
-+	.regs = mt_i2c_regs_v2,
-+	.pmic_i2c = 0,
-+	.dcm = 0,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 0,
-+	.ltiming_adjust = 1,
-+	.apdma_sync = 0,
-+	.max_dma_support = 36,
-+};
-+
- static const struct mtk_i2c_compatible mt8192_compat = {
- 	.quirks = &mt8183_i2c_quirks,
- 	.regs = mt_i2c_regs_v2,
-@@ -418,6 +431,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
-+	{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
- 	{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
- 	{}
- };
diff --git a/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch b/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch
deleted file mode 100644
index 0ace4a6701..0000000000
--- a/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch
+++ /dev/null
@@ -1,132 +0,0 @@
-From f606aab3f1a49d723d66e14e545f6ca45005bda6 Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Thu, 17 Feb 2022 20:22:43 +0800
-Subject: [PATCH 04/16] i2c: mediatek: modify bus speed calculation formula
-
-When clock-div is 0 or greater than 1, the bus speed
-calculated by the old speed calculation formula will be
-larger than the target speed. So we update the formula.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 51 ++++++++++++++++++++++++++-------
- 1 file changed, 41 insertions(+), 10 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -67,11 +67,12 @@
- 
- #define MAX_SAMPLE_CNT_DIV		8
- #define MAX_STEP_CNT_DIV		64
--#define MAX_CLOCK_DIV			256
-+#define MAX_CLOCK_DIV_8BITS		256
-+#define MAX_CLOCK_DIV_5BITS		32
- #define MAX_HS_STEP_CNT_DIV		8
--#define I2C_STANDARD_MODE_BUFFER	(1000 / 2)
--#define I2C_FAST_MODE_BUFFER		(300 / 2)
--#define I2C_FAST_MODE_PLUS_BUFFER	(20 / 2)
-+#define I2C_STANDARD_MODE_BUFFER	(1000 / 3)
-+#define I2C_FAST_MODE_BUFFER		(300 / 3)
-+#define I2C_FAST_MODE_PLUS_BUFFER	(20 / 3)
- 
- #define I2C_CONTROL_RS                  (0x1 << 1)
- #define I2C_CONTROL_DMA_EN              (0x1 << 2)
-@@ -604,6 +605,31 @@ static int mtk_i2c_max_step_cnt(unsigned
- 		return MAX_STEP_CNT_DIV;
- }
- 
-+static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
-+				      unsigned int sample_cnt)
-+{
-+	int clk_div_restri = 0;
-+
-+	if (i2c->dev_comp->ltiming_adjust == 0)
-+		return 0;
-+
-+	if (sample_cnt == 1) {
-+		if (i2c->ac_timing.inter_clk_div == 0)
-+			clk_div_restri = 0;
-+		else
-+			clk_div_restri = 1;
-+	} else {
-+		if (i2c->ac_timing.inter_clk_div == 0)
-+			clk_div_restri = -1;
-+		else if (i2c->ac_timing.inter_clk_div == 1)
-+			clk_div_restri = 0;
-+		else
-+			clk_div_restri = 1;
-+	}
-+
-+	return clk_div_restri;
-+}
-+
- /*
-  * Check and Calculate i2c ac-timing
-  *
-@@ -732,6 +758,7 @@ static int mtk_i2c_calculate_speed(struc
- 	unsigned int best_mul;
- 	unsigned int cnt_mul;
- 	int ret = -EINVAL;
-+	int clk_div_restri = 0;
- 
- 	if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
- 		target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
-@@ -749,7 +776,8 @@ static int mtk_i2c_calculate_speed(struc
- 	 * optimizing for sample_cnt * step_cnt being minimal
- 	 */
- 	for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
--		step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
-+		clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
-+		step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt);
- 		cnt_mul = step_cnt * sample_cnt;
- 		if (step_cnt > max_step_cnt)
- 			continue;
-@@ -763,7 +791,7 @@ static int mtk_i2c_calculate_speed(struc
- 			best_mul = cnt_mul;
- 			base_sample_cnt = sample_cnt;
- 			base_step_cnt = step_cnt;
--			if (best_mul == opt_div)
-+			if (best_mul == (opt_div + clk_div_restri))
- 				break;
- 		}
- 	}
-@@ -774,7 +802,8 @@ static int mtk_i2c_calculate_speed(struc
- 	sample_cnt = base_sample_cnt;
- 	step_cnt = base_step_cnt;
- 
--	if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
-+	if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) >
-+		target_speed) {
- 		/* In this case, hardware can't support such
- 		 * low i2c_bus_freq
- 		 */
-@@ -803,13 +832,16 @@ static int mtk_i2c_set_speed(struct mtk_
- 	target_speed = i2c->speed_hz;
- 	parent_clk /= i2c->clk_src_div;
- 
--	if (i2c->dev_comp->timing_adjust)
--		max_clk_div = MAX_CLOCK_DIV;
-+	if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
-+		max_clk_div = MAX_CLOCK_DIV_5BITS;
-+	else if (i2c->dev_comp->timing_adjust)
-+		max_clk_div = MAX_CLOCK_DIV_8BITS;
- 	else
- 		max_clk_div = 1;
- 
- 	for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
- 		clk_src = parent_clk / clk_div;
-+		i2c->ac_timing.inter_clk_div = clk_div - 1;
- 
- 		if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
- 			/* Set master code speed register */
-@@ -856,7 +888,6 @@ static int mtk_i2c_set_speed(struct mtk_
- 		break;
- 	}
- 
--	i2c->ac_timing.inter_clk_div = clk_div - 1;
- 
- 	return 0;
- }
diff --git a/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch b/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch
deleted file mode 100644
index 8f3c965a8d..0000000000
--- a/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From eb4a2ae019815946f574cd9f8209e12bdcd8fd34 Mon Sep 17 00:00:00 2001
-From: Xu Wang <vulab@iscas.ac.cn>
-Date: Wed, 30 Sep 2020 08:42:33 +0000
-Subject: [PATCH 05/16] i2c: mediatek: remove redundant null check
-
-Because clk_disable_unprepare already checked NULL clock parameter,
-so the additional checks are unnecessary, just remove it
-
-Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -476,8 +476,7 @@ static int mtk_i2c_clock_enable(struct m
- 	return 0;
- 
- err_arb:
--	if (i2c->have_pmic)
--		clk_disable_unprepare(i2c->clk_pmic);
-+	clk_disable_unprepare(i2c->clk_pmic);
- err_pmic:
- 	clk_disable_unprepare(i2c->clk_main);
- err_main:
-@@ -488,11 +487,9 @@ err_main:
- 
- static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
- {
--	if (i2c->clk_arb)
--		clk_disable_unprepare(i2c->clk_arb);
-+	clk_disable_unprepare(i2c->clk_arb);
- 
--	if (i2c->have_pmic)
--		clk_disable_unprepare(i2c->clk_pmic);
-+	clk_disable_unprepare(i2c->clk_pmic);
- 
- 	clk_disable_unprepare(i2c->clk_main);
- 	clk_disable_unprepare(i2c->clk_dma);
diff --git a/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch b/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch
deleted file mode 100644
index 71d083f31a..0000000000
--- a/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch
+++ /dev/null
@@ -1,234 +0,0 @@
-From cc6faa5e0772296d815fd298c231277d47308a6a Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Thu, 3 Mar 2022 10:15:47 +0100
-Subject: [PATCH 06/16] i2c: mt65xx: Simplify with clk-bulk
-
-Since depending on the SoC or specific bus functionality some clocks
-may be optional, we cannot get the benefit of using devm_clk_bulk_get()
-but, by migrating to clk-bulk, we are able to remove the custom functions
-mtk_i2c_clock_enable() and mtk_i2c_clock_disable(), increasing common
-APIs usage, hence (lightly) decreasing kernel footprint.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 124 +++++++++++++-------------------
- 1 file changed, 51 insertions(+), 73 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -86,6 +86,27 @@
- 
- #define I2C_DRV_NAME		"i2c-mt65xx"
- 
-+/**
-+ * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
-+ *
-+ * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
-+ * @I2C_MT65XX_CLK_DMA:  DMA clock for i2c via DMA
-+ * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
-+ * @I2C_MT65XX_CLK_ARB:  Arbitrator clock for i2c
-+ * @I2C_MT65XX_CLK_MAX:  Number of supported clocks
-+ */
-+enum i2c_mt65xx_clks {
-+	I2C_MT65XX_CLK_MAIN = 0,
-+	I2C_MT65XX_CLK_DMA,
-+	I2C_MT65XX_CLK_PMIC,
-+	I2C_MT65XX_CLK_ARB,
-+	I2C_MT65XX_CLK_MAX
-+};
-+
-+static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
-+	"main", "dma", "pmic", "arb"
-+};
-+
- enum DMA_REGS_OFFSET {
- 	OFFSET_INT_FLAG = 0x0,
- 	OFFSET_INT_EN = 0x04,
-@@ -244,10 +265,7 @@ struct mtk_i2c {
- 	/* set in i2c probe */
- 	void __iomem *base;		/* i2c base addr */
- 	void __iomem *pdmabase;		/* dma base address*/
--	struct clk *clk_main;		/* main clock for i2c bus */
--	struct clk *clk_dma;		/* DMA clock for i2c via DMA */
--	struct clk *clk_pmic;		/* PMIC clock for i2c from PMIC */
--	struct clk *clk_arb;		/* Arbitrator clock for i2c */
-+	struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
- 	bool have_pmic;			/* can use i2c pins from PMIC */
- 	bool use_push_pull;		/* IO config push-pull mode */
- 
-@@ -449,52 +467,6 @@ static void mtk_i2c_writew(struct mtk_i2
- 	writew(val, i2c->base + i2c->dev_comp->regs[reg]);
- }
- 
--static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
--{
--	int ret;
--
--	ret = clk_prepare_enable(i2c->clk_dma);
--	if (ret)
--		return ret;
--
--	ret = clk_prepare_enable(i2c->clk_main);
--	if (ret)
--		goto err_main;
--
--	if (i2c->have_pmic) {
--		ret = clk_prepare_enable(i2c->clk_pmic);
--		if (ret)
--			goto err_pmic;
--	}
--
--	if (i2c->clk_arb) {
--		ret = clk_prepare_enable(i2c->clk_arb);
--		if (ret)
--			goto err_arb;
--	}
--
--	return 0;
--
--err_arb:
--	clk_disable_unprepare(i2c->clk_pmic);
--err_pmic:
--	clk_disable_unprepare(i2c->clk_main);
--err_main:
--	clk_disable_unprepare(i2c->clk_dma);
--
--	return ret;
--}
--
--static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
--{
--	clk_disable_unprepare(i2c->clk_arb);
--
--	clk_disable_unprepare(i2c->clk_pmic);
--
--	clk_disable_unprepare(i2c->clk_main);
--	clk_disable_unprepare(i2c->clk_dma);
--}
--
- static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
- {
- 	u16 control_reg;
-@@ -1191,7 +1163,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	int left_num = num;
- 	struct mtk_i2c *i2c = i2c_get_adapdata(adap);
- 
--	ret = mtk_i2c_clock_enable(i2c);
-+	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret)
- 		return ret;
- 
-@@ -1245,7 +1217,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	ret = num;
- 
- err_exit:
--	mtk_i2c_clock_disable(i2c);
-+	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	return ret;
- }
- 
-@@ -1323,9 +1295,8 @@ static int mtk_i2c_probe(struct platform
- {
- 	int ret = 0;
- 	struct mtk_i2c *i2c;
--	struct clk *clk;
- 	struct resource *res;
--	int irq;
-+	int i, irq, speed_clk;
- 
- 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
- 	if (!i2c)
-@@ -1371,35 +1342,42 @@ static int mtk_i2c_probe(struct platform
- 	if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
- 		return -EINVAL;
- 
--	i2c->clk_main = devm_clk_get(&pdev->dev, "main");
--	if (IS_ERR(i2c->clk_main)) {
-+	/* Fill in clk-bulk IDs */
-+	for (i = 0; i < I2C_MT65XX_CLK_MAX; i++)
-+		i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
-+
-+	/* Get clocks one by one, some may be optional */
-+	i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
- 		dev_err(&pdev->dev, "cannot get main clock\n");
--		return PTR_ERR(i2c->clk_main);
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
- 	}
- 
--	i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
--	if (IS_ERR(i2c->clk_dma)) {
-+	i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
- 		dev_err(&pdev->dev, "cannot get dma clock\n");
--		return PTR_ERR(i2c->clk_dma);
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
- 	}
- 
--	i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
--	if (IS_ERR(i2c->clk_arb))
--		i2c->clk_arb = NULL;
-+	i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
- 
--	clk = i2c->clk_main;
- 	if (i2c->have_pmic) {
--		i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
--		if (IS_ERR(i2c->clk_pmic)) {
-+		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
-+		if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
- 			dev_err(&pdev->dev, "cannot get pmic clock\n");
--			return PTR_ERR(i2c->clk_pmic);
-+			return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
- 		}
--		clk = i2c->clk_pmic;
-+		speed_clk = I2C_MT65XX_CLK_PMIC;
-+	} else {
-+		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
-+		speed_clk = I2C_MT65XX_CLK_MAIN;
- 	}
- 
- 	strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
- 
--	ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
-+	ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
- 	if (ret) {
- 		dev_err(&pdev->dev, "Failed to set the speed.\n");
- 		return -EINVAL;
-@@ -1414,13 +1392,13 @@ static int mtk_i2c_probe(struct platform
- 		}
- 	}
- 
--	ret = mtk_i2c_clock_enable(i2c);
-+	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret) {
- 		dev_err(&pdev->dev, "clock enable failed!\n");
- 		return ret;
- 	}
- 	mtk_i2c_init_hw(i2c);
--	mtk_i2c_clock_disable(i2c);
-+	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
- 			       IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
-@@ -1465,7 +1443,7 @@ static int mtk_i2c_resume_noirq(struct d
- 	int ret;
- 	struct mtk_i2c *i2c = dev_get_drvdata(dev);
- 
--	ret = mtk_i2c_clock_enable(i2c);
-+	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret) {
- 		dev_err(dev, "clock enable failed!\n");
- 		return ret;
-@@ -1473,7 +1451,7 @@ static int mtk_i2c_resume_noirq(struct d
- 
- 	mtk_i2c_init_hw(i2c);
- 
--	mtk_i2c_clock_disable(i2c);
-+	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	i2c_mark_adapter_resumed(&i2c->adap);
- 
diff --git a/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch b/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch
deleted file mode 100644
index fe5be94fca..0000000000
--- a/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From de054c03f90b3ea22bc346fbf78ac716df192b2d Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Mon, 7 Mar 2022 11:36:49 +0800
-Subject: [PATCH 07/16] i2c: mediatek: Add i2c compatible for Mediatek MT8168
-
-Add i2c compatible for MT8168. Compare to MT2712 i2c controller,
-MT8168 need to synchronize signal with dma.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -389,6 +389,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 32,
- };
- 
-+static const struct mtk_i2c_compatible mt8168_compat = {
-+	.regs = mt_i2c_regs_v1,
-+	.pmic_i2c = 0,
-+	.dcm = 1,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 0,
-+	.apdma_sync = 0,
-+	.max_dma_support = 33,
-+};
-+
- static const struct mtk_i2c_compatible mt8173_compat = {
- 	.regs = mt_i2c_regs_v1,
- 	.pmic_i2c = 0,
-@@ -448,6 +461,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
- 	{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
diff --git a/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch b/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch
deleted file mode 100644
index 5c4ce40765..0000000000
--- a/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 2831f9a53ec3a16012d2d23590e3ebad6084b763 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Mon, 11 Apr 2022 15:21:07 +0200
-Subject: [PATCH 08/16] i2c: mediatek: Optimize master_xfer() and avoid
- circular locking
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Especially (but not only) during probe, it may happen that multiple
-devices are communicating via i2c (or multiple i2c busses) and
-sometimes while others are probing asynchronously.
-For example, a Cr50 TPM may be filling entropy (or userspace may be
-reading random data) while the rt5682 (i2c) codec driver reads/sets
-some registers, like while getting/setting a clock's rate, which
-happens both during probe and during system operation.
-
-In this driver, the mtk_i2c_transfer() function (which is the i2c
-.master_xfer() callback) was granularly managing the clocks by
-performing a clk_bulk_prepare_enable() to start them and its inverse.
-This is not only creating possible circular locking dependencies in
-the some cases (like former explanation), but it's also suboptimal,
-as clk_core prepare/unprepare operations are using mutex locking,
-which creates a bit of unwanted overhead (for example, i2c trackpads
-will call master_xfer() every few milliseconds!).
-
-With this commit, we avoid both the circular locking and additional
-overhead by changing how we handle the clocks in this driver:
-- Prepare the clocks during probe (and PM resume)
-- Enable/disable clocks in mtk_i2c_transfer()
-- Unprepare the clocks only for driver removal (and PM suspend)
-
-For the sake of providing a full explanation: during probe, the
-clocks are not only prepared but also enabled, as this is needed
-for some hardware initialization but, after that, we are disabling
-but not unpreparing them, leaving an expected state for the
-aforementioned clock handling strategy.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 11 +++++++----
- 1 file changed, 7 insertions(+), 4 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1177,7 +1177,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	int left_num = num;
- 	struct mtk_i2c *i2c = i2c_get_adapdata(adap);
- 
--	ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	if (ret)
- 		return ret;
- 
-@@ -1231,7 +1231,7 @@ static int mtk_i2c_transfer(struct i2c_a
- 	ret = num;
- 
- err_exit:
--	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 	return ret;
- }
- 
-@@ -1412,7 +1412,7 @@ static int mtk_i2c_probe(struct platform
- 		return ret;
- 	}
- 	mtk_i2c_init_hw(i2c);
--	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
- 			       IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
-@@ -1439,6 +1439,8 @@ static int mtk_i2c_remove(struct platfor
- 
- 	i2c_del_adapter(&i2c->adap);
- 
-+	clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+
- 	return 0;
- }
- 
-@@ -1448,6 +1450,7 @@ static int mtk_i2c_suspend_noirq(struct
- 	struct mtk_i2c *i2c = dev_get_drvdata(dev);
- 
- 	i2c_mark_adapter_suspended(&i2c->adap);
-+	clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	return 0;
- }
-@@ -1465,7 +1468,7 @@ static int mtk_i2c_resume_noirq(struct d
- 
- 	mtk_i2c_init_hw(i2c);
- 
--	clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+	clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- 
- 	i2c_mark_adapter_resumed(&i2c->adap);
- 
diff --git a/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch b/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch
deleted file mode 100644
index 354f12e214..0000000000
--- a/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 6f3a5814c7aaea4176e0ac8b1ec6dc0a65aa2808 Mon Sep 17 00:00:00 2001
-From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Date: Sun, 22 May 2022 14:22:07 +0200
-Subject: [PATCH 09/16] i2c: mediatek: Fix an error handling path in
- mtk_i2c_probe()
-
-The clsk are prepared, enabled, then disabled. So if an error occurs after
-the disable step, they are still prepared.
-
-Add an error handling path to unprepare the clks in such a case, as already
-done in the .remove function.
-
-Fixes: 8b4fc246c3ff ("i2c: mediatek: Optimize master_xfer() and avoid circular locking")
-Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1420,17 +1420,22 @@ static int mtk_i2c_probe(struct platform
- 	if (ret < 0) {
- 		dev_err(&pdev->dev,
- 			"Request I2C IRQ %d fail\n", irq);
--		return ret;
-+		goto err_bulk_unprepare;
- 	}
- 
- 	i2c_set_adapdata(&i2c->adap, i2c);
- 	ret = i2c_add_adapter(&i2c->adap);
- 	if (ret)
--		return ret;
-+		goto err_bulk_unprepare;
- 
- 	platform_set_drvdata(pdev, i2c);
- 
- 	return 0;
-+
-+err_bulk_unprepare:
-+	clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+
-+	return ret;
- }
- 
- static int mtk_i2c_remove(struct platform_device *pdev)
diff --git a/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch b/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch
deleted file mode 100644
index 744aa96ed0..0000000000
--- a/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sat, 6 Aug 2022 18:02:49 +0800
-Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188
-
-Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since
-MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = {
- 	[OFFSET_DCM_EN] = 0xf88,
- };
- 
-+static const u16 mt_i2c_regs_v3[] = {
-+	[OFFSET_DATA_PORT] = 0x0,
-+	[OFFSET_INTR_MASK] = 0x8,
-+	[OFFSET_INTR_STAT] = 0xc,
-+	[OFFSET_CONTROL] = 0x10,
-+	[OFFSET_TRANSFER_LEN] = 0x14,
-+	[OFFSET_TRANSAC_LEN] = 0x18,
-+	[OFFSET_DELAY_LEN] = 0x1c,
-+	[OFFSET_TIMING] = 0x20,
-+	[OFFSET_START] = 0x24,
-+	[OFFSET_EXT_CONF] = 0x28,
-+	[OFFSET_LTIMING] = 0x2c,
-+	[OFFSET_HS] = 0x30,
-+	[OFFSET_IO_CONFIG] = 0x34,
-+	[OFFSET_FIFO_ADDR_CLR] = 0x38,
-+	[OFFSET_SDA_TIMING] = 0x3c,
-+	[OFFSET_TRANSFER_LEN_AUX] = 0x44,
-+	[OFFSET_CLOCK_DIV] = 0x48,
-+	[OFFSET_SOFTRESET] = 0x50,
-+	[OFFSET_MULTI_DMA] = 0x8c,
-+	[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
-+	[OFFSET_SLAVE_ADDR] = 0x94,
-+	[OFFSET_DEBUGSTAT] = 0xe4,
-+	[OFFSET_DEBUGCTRL] = 0xe8,
-+	[OFFSET_FIFO_STAT] = 0xf4,
-+	[OFFSET_FIFO_THRESH] = 0xf8,
-+	[OFFSET_DCM_EN] = 0xf88,
-+};
-+
- struct mtk_i2c_compatible {
- 	const struct i2c_adapter_quirks *quirks;
- 	const u16 *regs;
-@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 36,
- };
- 
-+static const struct mtk_i2c_compatible mt8188_compat = {
-+	.regs = mt_i2c_regs_v3,
-+	.pmic_i2c = 0,
-+	.dcm = 0,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 0,
-+	.ltiming_adjust = 1,
-+	.apdma_sync = 1,
-+	.max_dma_support = 36,
-+};
-+
- static const struct mtk_i2c_compatible mt8192_compat = {
- 	.quirks = &mt8183_i2c_quirks,
- 	.regs = mt_i2c_regs_v2,
-@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
- 	{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
-+	{ .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
- 	{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
- 	{}
- };
diff --git a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
deleted file mode 100644
index 46e92a92f3..0000000000
--- a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
+++ /dev/null
@@ -1,579 +0,0 @@
-From 2f4ca256a98cc19787b7c861109dd1150a21b0bf Mon Sep 17 00:00:00 2001
-From: Wolfram Sang <wsa+renesas@sang-engineering.com>
-Date: Thu, 11 Aug 2022 09:10:30 +0200
-Subject: [PATCH 11/16] i2c: move drivers from strlcpy to strscpy
-
-Follow the advice of the below link and prefer 'strscpy'. Conversion is
-easy because no driver used the return value and has been done with a
-simple sed invocation.
-
-Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/
-Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-altera.c         | 2 +-
- drivers/i2c/busses/i2c-aspeed.c         | 2 +-
- drivers/i2c/busses/i2c-au1550.c         | 2 +-
- drivers/i2c/busses/i2c-axxia.c          | 2 +-
- drivers/i2c/busses/i2c-bcm-kona.c       | 2 +-
- drivers/i2c/busses/i2c-cbus-gpio.c      | 2 +-
- drivers/i2c/busses/i2c-cht-wc.c         | 2 +-
- drivers/i2c/busses/i2c-cros-ec-tunnel.c | 2 +-
- drivers/i2c/busses/i2c-davinci.c        | 2 +-
- drivers/i2c/busses/i2c-digicolor.c      | 2 +-
- drivers/i2c/busses/i2c-eg20t.c          | 2 +-
- drivers/i2c/busses/i2c-emev2.c          | 2 +-
- drivers/i2c/busses/i2c-exynos5.c        | 2 +-
- drivers/i2c/busses/i2c-gpio.c           | 2 +-
- drivers/i2c/busses/i2c-highlander.c     | 2 +-
- drivers/i2c/busses/i2c-hix5hd2.c        | 2 +-
- drivers/i2c/busses/i2c-i801.c           | 4 ++--
- drivers/i2c/busses/i2c-ibm_iic.c        | 2 +-
- drivers/i2c/busses/i2c-icy.c            | 2 +-
- drivers/i2c/busses/i2c-imx-lpi2c.c      | 2 +-
- drivers/i2c/busses/i2c-lpc2k.c          | 2 +-
- drivers/i2c/busses/i2c-meson.c          | 2 +-
- drivers/i2c/busses/i2c-mt65xx.c         | 2 +-
- drivers/i2c/busses/i2c-mt7621.c         | 2 +-
- drivers/i2c/busses/i2c-mv64xxx.c        | 2 +-
- drivers/i2c/busses/i2c-mxs.c            | 2 +-
- drivers/i2c/busses/i2c-nvidia-gpu.c     | 2 +-
- drivers/i2c/busses/i2c-omap.c           | 2 +-
- drivers/i2c/busses/i2c-opal.c           | 4 ++--
- drivers/i2c/busses/i2c-parport.c        | 2 +-
- drivers/i2c/busses/i2c-pxa.c            | 2 +-
- drivers/i2c/busses/i2c-qcom-geni.c      | 2 +-
- drivers/i2c/busses/i2c-qup.c            | 2 +-
- drivers/i2c/busses/i2c-rcar.c           | 2 +-
- drivers/i2c/busses/i2c-riic.c           | 2 +-
- drivers/i2c/busses/i2c-rk3x.c           | 2 +-
- drivers/i2c/busses/i2c-s3c2410.c        | 2 +-
- drivers/i2c/busses/i2c-sh_mobile.c      | 2 +-
- drivers/i2c/busses/i2c-simtec.c         | 2 +-
- drivers/i2c/busses/i2c-taos-evm.c       | 2 +-
- drivers/i2c/busses/i2c-tegra-bpmp.c     | 2 +-
- drivers/i2c/busses/i2c-tegra.c          | 2 +-
- drivers/i2c/busses/i2c-uniphier-f.c     | 2 +-
- drivers/i2c/busses/i2c-uniphier.c       | 2 +-
- drivers/i2c/busses/i2c-versatile.c      | 2 +-
- drivers/i2c/busses/i2c-wmt.c            | 2 +-
- 46 files changed, 48 insertions(+), 48 deletions(-)
-
---- a/drivers/i2c/busses/i2c-altera.c
-+++ b/drivers/i2c/busses/i2c-altera.c
-@@ -447,7 +447,7 @@ static int altr_i2c_probe(struct platfor
- 	mutex_unlock(&idev->isr_mutex);
- 
- 	i2c_set_adapdata(&idev->adapter, idev);
--	strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
-+	strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
- 	idev->adapter.owner = THIS_MODULE;
- 	idev->adapter.algo = &altr_i2c_algo;
- 	idev->adapter.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-aspeed.c
-+++ b/drivers/i2c/busses/i2c-aspeed.c
-@@ -1044,7 +1044,7 @@ static int aspeed_i2c_probe_bus(struct p
- 	bus->adap.algo = &aspeed_i2c_algo;
- 	bus->adap.dev.parent = &pdev->dev;
- 	bus->adap.dev.of_node = pdev->dev.of_node;
--	strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
-+	strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
- 	i2c_set_adapdata(&bus->adap, bus);
- 
- 	bus->dev = &pdev->dev;
---- a/drivers/i2c/busses/i2c-au1550.c
-+++ b/drivers/i2c/busses/i2c-au1550.c
-@@ -321,7 +321,7 @@ i2c_au1550_probe(struct platform_device
- 	priv->adap.algo = &au1550_algo;
- 	priv->adap.algo_data = priv;
- 	priv->adap.dev.parent = &pdev->dev;
--	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
- 
- 	/* Now, set up the PSC for SMBus PIO mode. */
- 	i2c_au1550_setup(priv);
---- a/drivers/i2c/busses/i2c-axxia.c
-+++ b/drivers/i2c/busses/i2c-axxia.c
-@@ -783,7 +783,7 @@ static int axxia_i2c_probe(struct platfo
- 	}
- 
- 	i2c_set_adapdata(&idev->adapter, idev);
--	strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
-+	strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
- 	idev->adapter.owner = THIS_MODULE;
- 	idev->adapter.algo = &axxia_i2c_algo;
- 	idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
---- a/drivers/i2c/busses/i2c-bcm-kona.c
-+++ b/drivers/i2c/busses/i2c-bcm-kona.c
-@@ -849,7 +849,7 @@ static int bcm_kona_i2c_probe(struct pla
- 	adap = &dev->adapter;
- 	i2c_set_adapdata(adap, dev);
- 	adap->owner = THIS_MODULE;
--	strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
- 	adap->algo = &bcm_algo;
- 	adap->dev.parent = &pdev->dev;
- 	adap->dev.of_node = pdev->dev.of_node;
---- a/drivers/i2c/busses/i2c-cbus-gpio.c
-+++ b/drivers/i2c/busses/i2c-cbus-gpio.c
-@@ -245,7 +245,7 @@ static int cbus_i2c_probe(struct platfor
- 	adapter->nr		= pdev->id;
- 	adapter->timeout	= HZ;
- 	adapter->algo		= &cbus_i2c_algo;
--	strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name));
-+	strscpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name));
- 
- 	spin_lock_init(&chost->lock);
- 	chost->dev = &pdev->dev;
---- a/drivers/i2c/busses/i2c-cht-wc.c
-+++ b/drivers/i2c/busses/i2c-cht-wc.c
-@@ -334,7 +334,7 @@ static int cht_wc_i2c_adap_i2c_probe(str
- 	adap->adapter.class = I2C_CLASS_HWMON;
- 	adap->adapter.algo = &cht_wc_i2c_adap_algo;
- 	adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops;
--	strlcpy(adap->adapter.name, "PMIC I2C Adapter",
-+	strscpy(adap->adapter.name, "PMIC I2C Adapter",
- 		sizeof(adap->adapter.name));
- 	adap->adapter.dev.parent = &pdev->dev;
- 
---- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c
-+++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c
-@@ -267,7 +267,7 @@ static int ec_i2c_probe(struct platform_
- 	bus->dev = dev;
- 
- 	bus->adap.owner = THIS_MODULE;
--	strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name));
-+	strscpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name));
- 	bus->adap.algo = &ec_i2c_algorithm;
- 	bus->adap.algo_data = bus;
- 	bus->adap.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-davinci.c
-+++ b/drivers/i2c/busses/i2c-davinci.c
-@@ -847,7 +847,7 @@ static int davinci_i2c_probe(struct plat
- 	i2c_set_adapdata(adap, dev);
- 	adap->owner = THIS_MODULE;
- 	adap->class = I2C_CLASS_DEPRECATED;
--	strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
- 	adap->algo = &i2c_davinci_algo;
- 	adap->dev.parent = &pdev->dev;
- 	adap->timeout = DAVINCI_I2C_TIMEOUT;
---- a/drivers/i2c/busses/i2c-digicolor.c
-+++ b/drivers/i2c/busses/i2c-digicolor.c
-@@ -322,7 +322,7 @@ static int dc_i2c_probe(struct platform_
- 	if (ret < 0)
- 		return ret;
- 
--	strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
-+	strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
- 		sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &dc_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-eg20t.c
-+++ b/drivers/i2c/busses/i2c-eg20t.c
-@@ -773,7 +773,7 @@ static int pch_i2c_probe(struct pci_dev
- 
- 		pch_adap->owner = THIS_MODULE;
- 		pch_adap->class = I2C_CLASS_HWMON;
--		strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
-+		strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
- 		pch_adap->algo = &pch_algorithm;
- 		pch_adap->algo_data = &adap_info->pch_data[i];
- 
---- a/drivers/i2c/busses/i2c-emev2.c
-+++ b/drivers/i2c/busses/i2c-emev2.c
-@@ -371,7 +371,7 @@ static int em_i2c_probe(struct platform_
- 	if (IS_ERR(priv->base))
- 		return PTR_ERR(priv->base);
- 
--	strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
- 
- 	priv->sclk = devm_clk_get(&pdev->dev, "sclk");
- 	if (IS_ERR(priv->sclk))
---- a/drivers/i2c/busses/i2c-exynos5.c
-+++ b/drivers/i2c/busses/i2c-exynos5.c
-@@ -751,7 +751,7 @@ static int exynos5_i2c_probe(struct plat
- 	if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
- 		i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
- 
--	strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
- 	i2c->adap.owner   = THIS_MODULE;
- 	i2c->adap.algo    = &exynos5_i2c_algorithm;
- 	i2c->adap.retries = 3;
---- a/drivers/i2c/busses/i2c-gpio.c
-+++ b/drivers/i2c/busses/i2c-gpio.c
-@@ -436,7 +436,7 @@ static int i2c_gpio_probe(struct platfor
- 
- 	adap->owner = THIS_MODULE;
- 	if (np)
--		strlcpy(adap->name, dev_name(dev), sizeof(adap->name));
-+		strscpy(adap->name, dev_name(dev), sizeof(adap->name));
- 	else
- 		snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id);
- 
---- a/drivers/i2c/busses/i2c-highlander.c
-+++ b/drivers/i2c/busses/i2c-highlander.c
-@@ -402,7 +402,7 @@ static int highlander_i2c_probe(struct p
- 	i2c_set_adapdata(adap, dev);
- 	adap->owner = THIS_MODULE;
- 	adap->class = I2C_CLASS_HWMON;
--	strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
- 	adap->algo = &highlander_i2c_algo;
- 	adap->dev.parent = &pdev->dev;
- 	adap->nr = pdev->id;
---- a/drivers/i2c/busses/i2c-hix5hd2.c
-+++ b/drivers/i2c/busses/i2c-hix5hd2.c
-@@ -423,7 +423,7 @@ static int hix5hd2_i2c_probe(struct plat
- 	}
- 	clk_prepare_enable(priv->clk);
- 
--	strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
- 	priv->dev = &pdev->dev;
- 	priv->adap.owner = THIS_MODULE;
- 	priv->adap.algo = &hix5hd2_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-i801.c
-+++ b/drivers/i2c/busses/i2c-i801.c
-@@ -1110,7 +1110,7 @@ static void dmi_check_onboard_device(u8
- 
- 		memset(&info, 0, sizeof(struct i2c_board_info));
- 		info.addr = dmi_devices[i].i2c_addr;
--		strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
-+		strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
- 		i2c_new_client_device(adap, &info);
- 		break;
- 	}
-@@ -1266,7 +1266,7 @@ static void register_dell_lis3lv02d_i2c_
- 
- 	memset(&info, 0, sizeof(struct i2c_board_info));
- 	info.addr = dell_lis3lv02d_devices[i].i2c_addr;
--	strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
-+	strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
- 	i2c_new_client_device(&priv->adapter, &info);
- }
- 
---- a/drivers/i2c/busses/i2c-ibm_iic.c
-+++ b/drivers/i2c/busses/i2c-ibm_iic.c
-@@ -736,7 +736,7 @@ static int iic_probe(struct platform_dev
- 	adap = &dev->adap;
- 	adap->dev.parent = &ofdev->dev;
- 	adap->dev.of_node = of_node_get(np);
--	strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
-+	strscpy(adap->name, "IBM IIC", sizeof(adap->name));
- 	i2c_set_adapdata(adap, dev);
- 	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
- 	adap->algo = &iic_algo;
---- a/drivers/i2c/busses/i2c-icy.c
-+++ b/drivers/i2c/busses/i2c-icy.c
-@@ -141,7 +141,7 @@ static int icy_probe(struct zorro_dev *z
- 	i2c->adapter.owner = THIS_MODULE;
- 	/* i2c->adapter.algo assigned by i2c_pcf_add_bus() */
- 	i2c->adapter.algo_data = algo_data;
--	strlcpy(i2c->adapter.name, "ICY I2C Zorro adapter",
-+	strscpy(i2c->adapter.name, "ICY I2C Zorro adapter",
- 		sizeof(i2c->adapter.name));
- 
- 	if (!devm_request_mem_region(&z->dev,
---- a/drivers/i2c/busses/i2c-imx-lpi2c.c
-+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c
-@@ -564,7 +564,7 @@ static int lpi2c_imx_probe(struct platfo
- 	lpi2c_imx->adapter.algo		= &lpi2c_imx_algo;
- 	lpi2c_imx->adapter.dev.parent	= &pdev->dev;
- 	lpi2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
--	strlcpy(lpi2c_imx->adapter.name, pdev->name,
-+	strscpy(lpi2c_imx->adapter.name, pdev->name,
- 		sizeof(lpi2c_imx->adapter.name));
- 
- 	lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
---- a/drivers/i2c/busses/i2c-lpc2k.c
-+++ b/drivers/i2c/busses/i2c-lpc2k.c
-@@ -417,7 +417,7 @@ static int i2c_lpc2k_probe(struct platfo
- 
- 	i2c_set_adapdata(&i2c->adap, i2c);
- 	i2c->adap.owner = THIS_MODULE;
--	strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
- 	i2c->adap.algo = &i2c_lpc2k_algorithm;
- 	i2c->adap.dev.parent = &pdev->dev;
- 	i2c->adap.dev.of_node = pdev->dev.of_node;
---- a/drivers/i2c/busses/i2c-meson.c
-+++ b/drivers/i2c/busses/i2c-meson.c
-@@ -451,7 +451,7 @@ static int meson_i2c_probe(struct platfo
- 		return ret;
- 	}
- 
--	strlcpy(i2c->adap.name, "Meson I2C adapter",
-+	strscpy(i2c->adap.name, "Meson I2C adapter",
- 		sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &meson_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1432,7 +1432,7 @@ static int mtk_i2c_probe(struct platform
- 		speed_clk = I2C_MT65XX_CLK_MAIN;
- 	}
- 
--	strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
- 
- 	ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
- 	if (ret) {
---- a/drivers/i2c/busses/i2c-mt7621.c
-+++ b/drivers/i2c/busses/i2c-mt7621.c
-@@ -315,7 +315,7 @@ static int mtk_i2c_probe(struct platform
- 	adap->dev.parent = &pdev->dev;
- 	i2c_set_adapdata(adap, i2c);
- 	adap->dev.of_node = pdev->dev.of_node;
--	strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+	strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
- 
- 	platform_set_drvdata(pdev, i2c);
- 
---- a/drivers/i2c/busses/i2c-mv64xxx.c
-+++ b/drivers/i2c/busses/i2c-mv64xxx.c
-@@ -1000,7 +1000,7 @@ mv64xxx_i2c_probe(struct platform_device
- 	if (IS_ERR(drv_data->reg_base))
- 		return PTR_ERR(drv_data->reg_base);
- 
--	strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
-+	strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
- 		sizeof(drv_data->adapter.name));
- 
- 	init_waitqueue_head(&drv_data->waitq);
---- a/drivers/i2c/busses/i2c-mxs.c
-+++ b/drivers/i2c/busses/i2c-mxs.c
-@@ -838,7 +838,7 @@ static int mxs_i2c_probe(struct platform
- 		return err;
- 
- 	adap = &i2c->adapter;
--	strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
- 	adap->owner = THIS_MODULE;
- 	adap->algo = &mxs_i2c_algo;
- 	adap->quirks = &mxs_i2c_quirks;
---- a/drivers/i2c/busses/i2c-nvidia-gpu.c
-+++ b/drivers/i2c/busses/i2c-nvidia-gpu.c
-@@ -319,7 +319,7 @@ static int gpu_i2c_probe(struct pci_dev
- 
- 	i2c_set_adapdata(&i2cd->adapter, i2cd);
- 	i2cd->adapter.owner = THIS_MODULE;
--	strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
-+	strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
- 		sizeof(i2cd->adapter.name));
- 	i2cd->adapter.algo = &gpu_i2c_algorithm;
- 	i2cd->adapter.quirks = &gpu_i2c_quirks;
---- a/drivers/i2c/busses/i2c-omap.c
-+++ b/drivers/i2c/busses/i2c-omap.c
-@@ -1488,7 +1488,7 @@ omap_i2c_probe(struct platform_device *p
- 	i2c_set_adapdata(adap, omap);
- 	adap->owner = THIS_MODULE;
- 	adap->class = I2C_CLASS_DEPRECATED;
--	strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
- 	adap->algo = &omap_i2c_algo;
- 	adap->quirks = &omap_i2c_quirks;
- 	adap->dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-opal.c
-+++ b/drivers/i2c/busses/i2c-opal.c
-@@ -220,9 +220,9 @@ static int i2c_opal_probe(struct platfor
- 	adapter->dev.of_node = of_node_get(pdev->dev.of_node);
- 	pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL);
- 	if (pname)
--		strlcpy(adapter->name, pname, sizeof(adapter->name));
-+		strscpy(adapter->name, pname, sizeof(adapter->name));
- 	else
--		strlcpy(adapter->name, "opal", sizeof(adapter->name));
-+		strscpy(adapter->name, "opal", sizeof(adapter->name));
- 
- 	platform_set_drvdata(pdev, adapter);
- 	rc = i2c_add_adapter(adapter);
---- a/drivers/i2c/busses/i2c-parport.c
-+++ b/drivers/i2c/busses/i2c-parport.c
-@@ -308,7 +308,7 @@ static void i2c_parport_attach(struct pa
- 	/* Fill the rest of the structure */
- 	adapter->adapter.owner = THIS_MODULE;
- 	adapter->adapter.class = I2C_CLASS_HWMON;
--	strlcpy(adapter->adapter.name, "Parallel port adapter",
-+	strscpy(adapter->adapter.name, "Parallel port adapter",
- 		sizeof(adapter->adapter.name));
- 	adapter->algo_data = parport_algo_data;
- 	/* Slow down if we can't sense SCL */
---- a/drivers/i2c/busses/i2c-pxa.c
-+++ b/drivers/i2c/busses/i2c-pxa.c
-@@ -1463,7 +1463,7 @@ static int i2c_pxa_probe(struct platform
- 	spin_lock_init(&i2c->lock);
- 	init_waitqueue_head(&i2c->wait);
- 
--	strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
- 
- 	i2c->clk = devm_clk_get(&dev->dev, NULL);
- 	if (IS_ERR(i2c->clk)) {
---- a/drivers/i2c/busses/i2c-qcom-geni.c
-+++ b/drivers/i2c/busses/i2c-qcom-geni.c
-@@ -577,7 +577,7 @@ static int geni_i2c_probe(struct platfor
- 	i2c_set_adapdata(&gi2c->adap, gi2c);
- 	gi2c->adap.dev.parent = dev;
- 	gi2c->adap.dev.of_node = dev->of_node;
--	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
-+	strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
- 
- 	ret = geni_icc_get(&gi2c->se, "qup-memory");
- 	if (ret)
---- a/drivers/i2c/busses/i2c-qup.c
-+++ b/drivers/i2c/busses/i2c-qup.c
-@@ -1885,7 +1885,7 @@ nodma:
- 	qup->adap.dev.of_node = pdev->dev.of_node;
- 	qup->is_last = true;
- 
--	strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
-+	strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
- 
- 	pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
- 	pm_runtime_use_autosuspend(qup->dev);
---- a/drivers/i2c/busses/i2c-rcar.c
-+++ b/drivers/i2c/busses/i2c-rcar.c
-@@ -1059,7 +1059,7 @@ static int rcar_i2c_probe(struct platfor
- 	adap->bus_recovery_info = &rcar_i2c_bri;
- 	adap->quirks = &rcar_i2c_quirks;
- 	i2c_set_adapdata(adap, priv);
--	strlcpy(adap->name, pdev->name, sizeof(adap->name));
-+	strscpy(adap->name, pdev->name, sizeof(adap->name));
- 
- 	/* Init DMA */
- 	sg_init_table(&priv->sg, 1);
---- a/drivers/i2c/busses/i2c-riic.c
-+++ b/drivers/i2c/busses/i2c-riic.c
-@@ -447,7 +447,7 @@ static int riic_i2c_probe(struct platfor
- 
- 	adap = &riic->adapter;
- 	i2c_set_adapdata(adap, riic);
--	strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
-+	strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
- 	adap->owner = THIS_MODULE;
- 	adap->algo = &riic_algo;
- 	adap->dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-rk3x.c
-+++ b/drivers/i2c/busses/i2c-rk3x.c
-@@ -1247,7 +1247,7 @@ static int rk3x_i2c_probe(struct platfor
- 	/* use common interface to get I2C timing properties */
- 	i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
- 
--	strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &rk3x_i2c_algorithm;
- 	i2c->adap.retries = 3;
---- a/drivers/i2c/busses/i2c-s3c2410.c
-+++ b/drivers/i2c/busses/i2c-s3c2410.c
-@@ -1078,7 +1078,7 @@ static int s3c24xx_i2c_probe(struct plat
- 	else
- 		s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
- 
--	strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
- 	i2c->adap.owner = THIS_MODULE;
- 	i2c->adap.algo = &s3c24xx_i2c_algorithm;
- 	i2c->adap.retries = 2;
---- a/drivers/i2c/busses/i2c-sh_mobile.c
-+++ b/drivers/i2c/busses/i2c-sh_mobile.c
-@@ -930,7 +930,7 @@ static int sh_mobile_i2c_probe(struct pl
- 	adap->nr = dev->id;
- 	adap->dev.of_node = dev->dev.of_node;
- 
--	strlcpy(adap->name, dev->name, sizeof(adap->name));
-+	strscpy(adap->name, dev->name, sizeof(adap->name));
- 
- 	spin_lock_init(&pd->lock);
- 	init_waitqueue_head(&pd->wait);
---- a/drivers/i2c/busses/i2c-simtec.c
-+++ b/drivers/i2c/busses/i2c-simtec.c
-@@ -99,7 +99,7 @@ static int simtec_i2c_probe(struct platf
- 	pd->adap.algo_data = &pd->bit;
- 	pd->adap.dev.parent = &dev->dev;
- 
--	strlcpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name));
-+	strscpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name));
- 
- 	pd->bit.data = pd;
- 	pd->bit.setsda = simtec_i2c_setsda;
---- a/drivers/i2c/busses/i2c-taos-evm.c
-+++ b/drivers/i2c/busses/i2c-taos-evm.c
-@@ -239,7 +239,7 @@ static int taos_connect(struct serio *se
- 		dev_err(&serio->dev, "TAOS EVM identification failed\n");
- 		goto exit_close;
- 	}
--	strlcpy(adapter->name, name, sizeof(adapter->name));
-+	strscpy(adapter->name, name, sizeof(adapter->name));
- 
- 	/* Turn echo off for better performance */
- 	taos->state = TAOS_STATE_EOFF;
---- a/drivers/i2c/busses/i2c-tegra-bpmp.c
-+++ b/drivers/i2c/busses/i2c-tegra-bpmp.c
-@@ -305,7 +305,7 @@ static int tegra_bpmp_i2c_probe(struct p
- 
- 	i2c_set_adapdata(&i2c->adapter, i2c);
- 	i2c->adapter.owner = THIS_MODULE;
--	strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter",
-+	strscpy(i2c->adapter.name, "Tegra BPMP I2C adapter",
- 		sizeof(i2c->adapter.name));
- 	i2c->adapter.algo = &tegra_bpmp_i2c_algo;
- 	i2c->adapter.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-tegra.c
-+++ b/drivers/i2c/busses/i2c-tegra.c
-@@ -1799,7 +1799,7 @@ static int tegra_i2c_probe(struct platfo
- 	if (i2c_dev->hw->supports_bus_clear)
- 		i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
- 
--	strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
-+	strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
- 		sizeof(i2c_dev->adapter.name));
- 
- 	err = i2c_add_numbered_adapter(&i2c_dev->adapter);
---- a/drivers/i2c/busses/i2c-uniphier-f.c
-+++ b/drivers/i2c/busses/i2c-uniphier-f.c
-@@ -564,7 +564,7 @@ static int uniphier_fi2c_probe(struct pl
- 	priv->adap.algo = &uniphier_fi2c_algo;
- 	priv->adap.dev.parent = dev;
- 	priv->adap.dev.of_node = dev->of_node;
--	strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
- 	priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
- 	i2c_set_adapdata(&priv->adap, priv);
- 	platform_set_drvdata(pdev, priv);
---- a/drivers/i2c/busses/i2c-uniphier.c
-+++ b/drivers/i2c/busses/i2c-uniphier.c
-@@ -358,7 +358,7 @@ static int uniphier_i2c_probe(struct pla
- 	priv->adap.algo = &uniphier_i2c_algo;
- 	priv->adap.dev.parent = dev;
- 	priv->adap.dev.of_node = dev->of_node;
--	strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
-+	strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
- 	priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
- 	i2c_set_adapdata(&priv->adap, priv);
- 	platform_set_drvdata(pdev, priv);
---- a/drivers/i2c/busses/i2c-versatile.c
-+++ b/drivers/i2c/busses/i2c-versatile.c
-@@ -79,7 +79,7 @@ static int i2c_versatile_probe(struct pl
- 	writel(SCL | SDA, i2c->base + I2C_CONTROLS);
- 
- 	i2c->adap.owner = THIS_MODULE;
--	strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name));
-+	strscpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name));
- 	i2c->adap.algo_data = &i2c->algo;
- 	i2c->adap.dev.parent = &dev->dev;
- 	i2c->adap.dev.of_node = dev->dev.of_node;
---- a/drivers/i2c/busses/i2c-wmt.c
-+++ b/drivers/i2c/busses/i2c-wmt.c
-@@ -413,7 +413,7 @@ static int wmt_i2c_probe(struct platform
- 
- 	adap = &i2c_dev->adapter;
- 	i2c_set_adapdata(adap, i2c_dev);
--	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
-+	strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
- 	adap->owner = THIS_MODULE;
- 	adap->algo = &wmt_i2c_algo;
- 	adap->dev.parent = &pdev->dev;
diff --git a/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch
deleted file mode 100644
index 4c398c59f9..0000000000
--- a/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 9 Oct 2022 12:16:31 +0200
-Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support
-
-Add i2c support for MT7986 SoC.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt7986_compat = {
-+	.quirks = &mt7622_i2c_quirks,
-+	.regs = mt_i2c_regs_v1,
-+	.pmic_i2c = 0,
-+	.dcm = 1,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 0,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 0,
-+	.max_dma_support = 32,
-+};
-+
- static const struct mtk_i2c_compatible mt8173_compat = {
- 	.regs = mt_i2c_regs_v1,
- 	.pmic_i2c = 0,
-@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- 	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
diff --git a/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch
deleted file mode 100644
index 18c66cdac5..0000000000
--- a/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001
-From: ye xingchen <ye.xingchen@zte.com.cn>
-Date: Thu, 19 Jan 2023 17:19:58 +0800
-Subject: [PATCH 13/16] i2c: mt65xx: Use
- devm_platform_get_and_ioremap_resource()
-
-Convert platform_get_resource(), devm_ioremap_resource() to a single
-call to devm_platform_get_and_ioremap_resource(), as this is exactly
-what this function does.
-
-Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform
- {
- 	int ret = 0;
- 	struct mtk_i2c *i2c;
--	struct resource *res;
- 	int i, irq, speed_clk;
- 
- 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
- 	if (!i2c)
- 		return -ENOMEM;
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	i2c->base = devm_ioremap_resource(&pdev->dev, res);
-+	i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- 	if (IS_ERR(i2c->base))
- 		return PTR_ERR(i2c->base);
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
--	i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
-+	i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
- 	if (IS_ERR(i2c->pdmabase))
- 		return PTR_ERR(i2c->pdmabase);
- 
diff --git a/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch
deleted file mode 100644
index d000d53522..0000000000
--- a/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sat, 11 Mar 2023 12:16:54 +0100
-Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The driver can match only via the DT table so the table should be always
-used and the of_match_ptr does not have any sense (this also allows ACPI
-matching via PRP0001, even though it might not be relevant here).
-
-  drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=]
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Guenter Roeck <groeck@chromium.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr
- 	.driver = {
- 		.name = I2C_DRV_NAME,
- 		.pm = &mtk_i2c_pm,
--		.of_match_table = of_match_ptr(mtk_i2c_of_match),
-+		.of_match_table = mtk_i2c_of_match,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch
deleted file mode 100644
index e0973741e2..0000000000
--- a/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 10 Apr 2023 17:19:38 +0100
-Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC
-
-Add support for the I2C units found in the MediaTek MT7981 and MT7988
-SoCs. Just like other recent MediaTek I2C units that also uses v3
-register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being
-0x94 instead of 0x4).
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt7981_compat = {
-+	.regs = mt_i2c_regs_v3,
-+	.pmic_i2c = 0,
-+	.dcm = 0,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 1,
-+	.max_dma_support = 33
-+};
-+
- static const struct mtk_i2c_compatible mt7986_compat = {
- 	.quirks = &mt7622_i2c_quirks,
- 	.regs = mt_i2c_regs_v1,
-@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
- 	{ .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- 	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
diff --git a/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch
deleted file mode 100644
index 69cc155d8d..0000000000
--- a/target/linux/mediatek/patches-5.15/855-i2c-mt65xx-allow-optional-pmic-clock.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 26 Aug 2023 21:56:51 +0100
-Subject: [PATCH] i2c: mt65xx: allow optional pmic clock
-
-Using the I2C host controller on the MT7981 SoC requires 4 clocks to
-be enabled. One of them, the pmic clk, is only enabled in case
-'mediatek,have-pmic' is also set which has other consequences which
-are not desired in this case.
-
-Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty
-is not present and the bus is not used to connect to a pmic, but may
-still require to enable the pmic clock.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++----
- 1 file changed, 8 insertions(+), 4 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform
- 	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
- 		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
- 
-+	i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+		dev_err(&pdev->dev, "cannot get pmic clock\n");
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+	}
-+
- 	if (i2c->have_pmic) {
--		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
--		if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+		if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
- 			dev_err(&pdev->dev, "cannot get pmic clock\n");
--			return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+			return -ENODEV;
- 		}
- 		speed_clk = I2C_MT65XX_CLK_PMIC;
- 	} else {
--		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
- 		speed_clk = I2C_MT65XX_CLK_MAIN;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch b/target/linux/mediatek/patches-5.15/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch
deleted file mode 100644
index 9607eec821..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch
+++ /dev/null
@@ -1,269 +0,0 @@
-From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:33 +0800
-Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header
-
-Add header files for register definition and structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-afe-common.h |  49 +++++
- sound/soc/mediatek/mt7986/mt7986-reg.h        | 196 ++++++++++++++++++
- 2 files changed, 245 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h
-@@ -0,0 +1,49 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-afe-common.h  --  MediaTek 7986 audio driver definitions
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT_7986_AFE_COMMON_H_
-+#define _MT_7986_AFE_COMMON_H_
-+
-+#include <sound/soc.h>
-+#include <linux/clk.h>
-+#include <linux/list.h>
-+#include <linux/regmap.h>
-+#include "../common/mtk-base-afe.h"
-+
-+enum {
-+	MT7986_MEMIF_DL1,
-+	MT7986_MEMIF_VUL12,
-+	MT7986_MEMIF_NUM,
-+	MT7986_DAI_ETDM = MT7986_MEMIF_NUM,
-+	MT7986_DAI_NUM,
-+};
-+
-+enum {
-+	MT7986_IRQ_0,
-+	MT7986_IRQ_1,
-+	MT7986_IRQ_2,
-+	MT7986_IRQ_NUM,
-+};
-+
-+struct mt7986_afe_private {
-+	struct clk_bulk_data *clks;
-+	int num_clks;
-+
-+	int pm_runtime_bypass_reg_ctl;
-+
-+	/* dai */
-+	void *dai_priv[MT7986_DAI_NUM];
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev,
-+				       unsigned int rate);
-+
-+/* dai register */
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe);
-+#endif
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-reg.h
-@@ -0,0 +1,196 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-reg.h  --  MediaTek 7986 audio driver reg definition
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT7986_REG_H_
-+#define _MT7986_REG_H_
-+
-+#define AUDIO_TOP_CON2                  0x0008
-+#define AUDIO_TOP_CON4                  0x0010
-+#define AUDIO_ENGEN_CON0                0x0014
-+#define AFE_IRQ_MCU_EN                  0x0100
-+#define AFE_IRQ_MCU_STATUS              0x0120
-+#define AFE_IRQ_MCU_CLR                 0x0128
-+#define AFE_IRQ0_MCU_CFG0               0x0140
-+#define AFE_IRQ0_MCU_CFG1               0x0144
-+#define AFE_IRQ1_MCU_CFG0               0x0148
-+#define AFE_IRQ1_MCU_CFG1               0x014c
-+#define AFE_IRQ2_MCU_CFG0               0x0150
-+#define AFE_IRQ2_MCU_CFG1               0x0154
-+#define ETDM_IN5_CON0                   0x13f0
-+#define ETDM_IN5_CON1                   0x13f4
-+#define ETDM_IN5_CON2                   0x13f8
-+#define ETDM_IN5_CON3                   0x13fc
-+#define ETDM_IN5_CON4                   0x1400
-+#define ETDM_OUT5_CON0                  0x1570
-+#define ETDM_OUT5_CON4                  0x1580
-+#define ETDM_OUT5_CON5                  0x1584
-+#define ETDM_4_7_COWORK_CON0            0x15e0
-+#define ETDM_4_7_COWORK_CON1            0x15e4
-+#define AFE_CONN018_1                   0x1b44
-+#define AFE_CONN018_4                   0x1b50
-+#define AFE_CONN019_1                   0x1b64
-+#define AFE_CONN019_4                   0x1b70
-+#define AFE_CONN124_1                   0x2884
-+#define AFE_CONN124_4                   0x2890
-+#define AFE_CONN125_1                   0x28a4
-+#define AFE_CONN125_4                   0x28b0
-+#define AFE_CONN_RS_0                   0x3920
-+#define AFE_CONN_RS_3                   0x392c
-+#define AFE_CONN_16BIT_0                0x3960
-+#define AFE_CONN_16BIT_3                0x396c
-+#define AFE_CONN_24BIT_0                0x3980
-+#define AFE_CONN_24BIT_3                0x398c
-+#define AFE_MEMIF_CON0                  0x3d98
-+#define AFE_MEMIF_RD_MON                0x3da0
-+#define AFE_MEMIF_WR_MON                0x3da4
-+#define AFE_DL0_BASE_MSB                0x3e40
-+#define AFE_DL0_BASE                    0x3e44
-+#define AFE_DL0_CUR_MSB                 0x3e48
-+#define AFE_DL0_CUR                     0x3e4c
-+#define AFE_DL0_END_MSB                 0x3e50
-+#define AFE_DL0_END                     0x3e54
-+#define AFE_DL0_RCH_MON                 0x3e58
-+#define AFE_DL0_LCH_MON                 0x3e5c
-+#define AFE_DL0_CON0                    0x3e60
-+#define AFE_VUL0_BASE_MSB               0x4220
-+#define AFE_VUL0_BASE                   0x4224
-+#define AFE_VUL0_CUR_MSB                0x4228
-+#define AFE_VUL0_CUR                    0x422c
-+#define AFE_VUL0_END_MSB                0x4230
-+#define AFE_VUL0_END                    0x4234
-+#define AFE_VUL0_CON0                   0x4238
-+
-+#define AFE_MAX_REGISTER AFE_VUL0_CON0
-+#define AFE_IRQ_STATUS_BITS             0x7
-+#define AFE_IRQ_CNT_SHIFT               0
-+#define AFE_IRQ_CNT_MASK	        0xffffff
-+
-+/* AUDIO_TOP_CON2 */
-+#define CLK_OUT5_PDN                    BIT(14)
-+#define CLK_OUT5_PDN_MASK               BIT(14)
-+#define CLK_IN5_PDN                     BIT(7)
-+#define CLK_IN5_PDN_MASK                BIT(7)
-+
-+/* AUDIO_TOP_CON4 */
-+#define PDN_APLL_TUNER2                 BIT(12)
-+#define PDN_APLL_TUNER2_MASK            BIT(12)
-+
-+/* AUDIO_ENGEN_CON0 */
-+#define AUD_APLL2_EN                    BIT(3)
-+#define AUD_APLL2_EN_MASK               BIT(3)
-+#define AUD_26M_EN                      BIT(0)
-+#define AUD_26M_EN_MASK                 BIT(0)
-+
-+/* AFE_DL0_CON0 */
-+#define DL0_ON_SFT                      28
-+#define DL0_ON_MASK                     0x1
-+#define DL0_ON_MASK_SFT                 BIT(28)
-+#define DL0_MINLEN_SFT                  20
-+#define DL0_MINLEN_MASK                 0xf
-+#define DL0_MINLEN_MASK_SFT             (0xf << 20)
-+#define DL0_MODE_SFT                    8
-+#define DL0_MODE_MASK                   0x1f
-+#define DL0_MODE_MASK_SFT               (0x1f << 8)
-+#define DL0_PBUF_SIZE_SFT               5
-+#define DL0_PBUF_SIZE_MASK              0x3
-+#define DL0_PBUF_SIZE_MASK_SFT          (0x3 << 5)
-+#define DL0_MONO_SFT                    4
-+#define DL0_MONO_MASK                   0x1
-+#define DL0_MONO_MASK_SFT               BIT(4)
-+#define DL0_HALIGN_SFT                  2
-+#define DL0_HALIGN_MASK                 0x1
-+#define DL0_HALIGN_MASK_SFT             BIT(2)
-+#define DL0_HD_MODE_SFT                 0
-+#define DL0_HD_MODE_MASK                0x3
-+#define DL0_HD_MODE_MASK_SFT            (0x3 << 0)
-+
-+/* AFE_VUL0_CON0 */
-+#define VUL0_ON_SFT                     28
-+#define VUL0_ON_MASK                    0x1
-+#define VUL0_ON_MASK_SFT                BIT(28)
-+#define VUL0_MODE_SFT                   8
-+#define VUL0_MODE_MASK                  0x1f
-+#define VUL0_MODE_MASK_SFT              (0x1f << 8)
-+#define VUL0_MONO_SFT                   4
-+#define VUL0_MONO_MASK                  0x1
-+#define VUL0_MONO_MASK_SFT              BIT(4)
-+#define VUL0_HALIGN_SFT                 2
-+#define VUL0_HALIGN_MASK                0x1
-+#define VUL0_HALIGN_MASK_SFT            BIT(2)
-+#define VUL0_HD_MODE_SFT                0
-+#define VUL0_HD_MODE_MASK               0x3
-+#define VUL0_HD_MODE_MASK_SFT           (0x3 << 0)
-+
-+/* AFE_IRQ_MCU_CON */
-+#define IRQ_MCU_MODE_SFT                4
-+#define IRQ_MCU_MODE_MASK               0x1f
-+#define IRQ_MCU_MODE_MASK_SFT           (0x1f << 4)
-+#define IRQ_MCU_ON_SFT                  0
-+#define IRQ_MCU_ON_MASK                 0x1
-+#define IRQ_MCU_ON_MASK_SFT             BIT(0)
-+#define IRQ0_MCU_CLR_SFT                0
-+#define IRQ0_MCU_CLR_MASK               0x1
-+#define IRQ0_MCU_CLR_MASK_SFT           BIT(0)
-+#define IRQ1_MCU_CLR_SFT                1
-+#define IRQ1_MCU_CLR_MASK               0x1
-+#define IRQ1_MCU_CLR_MASK_SFT           BIT(1)
-+#define IRQ2_MCU_CLR_SFT                2
-+#define IRQ2_MCU_CLR_MASK               0x1
-+#define IRQ2_MCU_CLR_MASK_SFT           BIT(2)
-+
-+/* ETDM_IN5_CON2 */
-+#define IN_CLK_SRC(x)                   ((x) << 10)
-+#define IN_CLK_SRC_SFT                  10
-+#define IN_CLK_SRC_MASK                 GENMASK(12, 10)
-+
-+/* ETDM_IN5_CON3 */
-+#define IN_SEL_FS(x)                    ((x) << 26)
-+#define IN_SEL_FS_SFT                   26
-+#define IN_SEL_FS_MASK                  GENMASK(30, 26)
-+
-+/* ETDM_IN5_CON4 */
-+#define IN_RELATCH(x)                   ((x) << 20)
-+#define IN_RELATCH_SFT                  20
-+#define IN_RELATCH_MASK                 GENMASK(24, 20)
-+#define IN_CLK_INV                      BIT(18)
-+#define IN_CLK_INV_MASK                 BIT(18)
-+
-+/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
-+#define RELATCH_SRC_MASK                GENMASK(30, 28)
-+#define ETDM_CH_NUM_MASK                GENMASK(27, 23)
-+#define ETDM_WRD_LEN_MASK               GENMASK(20, 16)
-+#define ETDM_BIT_LEN_MASK               GENMASK(15, 11)
-+#define ETDM_FMT_MASK                   GENMASK(8, 6)
-+#define ETDM_SYNC                       BIT(1)
-+#define ETDM_SYNC_MASK                  BIT(1)
-+#define ETDM_EN                         BIT(0)
-+#define ETDM_EN_MASK                    BIT(0)
-+
-+/* ETDM_OUT5_CON4 */
-+#define OUT_RELATCH(x)                  ((x) << 24)
-+#define OUT_RELATCH_SFT                 24
-+#define OUT_RELATCH_MASK                GENMASK(28, 24)
-+#define OUT_CLK_SRC(x)                  ((x) << 6)
-+#define OUT_CLK_SRC_SFT                 6
-+#define OUT_CLK_SRC_MASK                GENMASK(8, 6)
-+#define OUT_SEL_FS(x)                   (x)
-+#define OUT_SEL_FS_SFT                  0
-+#define OUT_SEL_FS_MASK                 GENMASK(4, 0)
-+
-+/* ETDM_OUT5_CON5 */
-+#define ETDM_CLK_DIV                    BIT(12)
-+#define ETDM_CLK_DIV_MASK               BIT(12)
-+#define OUT_CLK_INV                     BIT(9)
-+#define OUT_CLK_INV_MASK                BIT(9)
-+
-+/* ETDM_4_7_COWORK_CON0 */
-+#define OUT_SEL(x)                      ((x) << 12)
-+#define OUT_SEL_SFT                     12
-+#define OUT_SEL_MASK                    GENMASK(15, 12)
-+#endif
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch b/target/linux/mediatek/patches-5.15/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch
deleted file mode 100644
index f22add580f..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch
+++ /dev/null
@@ -1,430 +0,0 @@
-From 948a288897015fb3ee63b3f720b396b590c17fd7 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:34 +0800
-Subject: [PATCH 2/9] ASoC: mediatek: mt7986: support etdm in platform driver
-
-Add mt7986 etdm dai driver support.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 411 ++++++++++++++++++++
- 1 file changed, 411 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -0,0 +1,411 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC Audio DAI eTDM Control
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/bitops.h>
-+#include <linux/regmap.h>
-+#include <sound/pcm_params.h>
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+
-+#define HOPPING_CLK  0
-+#define APLL_CLK     1
-+#define MTK_DAI_ETDM_FORMAT_I2S   0
-+#define MTK_DAI_ETDM_FORMAT_DSPA  4
-+#define MTK_DAI_ETDM_FORMAT_DSPB  5
-+
-+enum {
-+	MTK_ETDM_RATE_8K = 0,
-+	MTK_ETDM_RATE_12K = 1,
-+	MTK_ETDM_RATE_16K = 2,
-+	MTK_ETDM_RATE_24K = 3,
-+	MTK_ETDM_RATE_32K = 4,
-+	MTK_ETDM_RATE_48K = 5,
-+	MTK_ETDM_RATE_96K = 7,
-+	MTK_ETDM_RATE_192K = 9,
-+	MTK_ETDM_RATE_11K = 16,
-+	MTK_ETDM_RATE_22K = 17,
-+	MTK_ETDM_RATE_44K = 18,
-+	MTK_ETDM_RATE_88K = 19,
-+	MTK_ETDM_RATE_176K = 20,
-+};
-+
-+struct mtk_dai_etdm_priv {
-+	bool bck_inv;
-+	bool lrck_inv;
-+	bool slave_mode;
-+	unsigned int format;
-+};
-+
-+static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate)
-+{
-+	switch (rate) {
-+	case 8000:
-+		return MTK_ETDM_RATE_8K;
-+	case 11025:
-+		return MTK_ETDM_RATE_11K;
-+	case 12000:
-+		return MTK_ETDM_RATE_12K;
-+	case 16000:
-+		return MTK_ETDM_RATE_16K;
-+	case 22050:
-+		return MTK_ETDM_RATE_22K;
-+	case 24000:
-+		return MTK_ETDM_RATE_24K;
-+	case 32000:
-+		return MTK_ETDM_RATE_32K;
-+	case 44100:
-+		return MTK_ETDM_RATE_44K;
-+	case 48000:
-+		return MTK_ETDM_RATE_48K;
-+	case 88200:
-+		return MTK_ETDM_RATE_88K;
-+	case 96000:
-+		return MTK_ETDM_RATE_96K;
-+	case 176400:
-+		return MTK_ETDM_RATE_176K;
-+	case 192000:
-+		return MTK_ETDM_RATE_192K;
-+	default:
-+		dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+			 __func__, rate, MTK_ETDM_RATE_48K);
-+		return MTK_ETDM_RATE_48K;
-+	}
-+}
-+
-+static int get_etdm_wlen(unsigned int bitwidth)
-+{
-+	return bitwidth <= 16 ? 16 : 32;
-+}
-+
-+/* dai component */
-+/* interconnection */
-+
-+static const struct snd_kcontrol_new o124_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o125_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
-+
-+	/* DL */
-+	SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	/* UL */
-+	SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)),
-+	SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
-+	{"I150", NULL, "ETDM Capture"},
-+	{"I151", NULL, "ETDM Capture"},
-+	{"ETDM Playback", NULL, "O124"},
-+	{"ETDM Playback", NULL, "O125"},
-+	{"O124", "I032_Switch", "I032"},
-+	{"O125", "I033_Switch", "I033"},
-+};
-+
-+/* dai ops */
-+static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
-+				struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
-+
-+	ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0);
-+
-+	return 0;
-+}
-+
-+static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
-+				  struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK,
-+			   CLK_OUT5_PDN);
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK,
-+			   CLK_IN5_PDN);
-+
-+	clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+}
-+
-+static unsigned int get_etdm_ch_fixup(unsigned int channels)
-+{
-+	if (channels > 16)
-+		return 24;
-+	else if (channels > 8)
-+		return 16;
-+	else if (channels > 4)
-+		return 8;
-+	else if (channels > 2)
-+		return 4;
-+	else
-+		return 2;
-+}
-+
-+static int mtk_dai_etdm_config(struct mtk_base_afe *afe,
-+			       struct snd_pcm_hw_params *params,
-+			       struct snd_soc_dai *dai,
-+			       int stream)
-+{
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
-+	unsigned int rate = params_rate(params);
-+	unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate);
-+	unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate);
-+	unsigned int channels = params_channels(params);
-+	unsigned int bit_width = params_width(params);
-+	unsigned int wlen = get_etdm_wlen(bit_width);
-+	unsigned int val = 0;
-+	unsigned int mask = 0;
-+
-+	dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n",
-+		 __func__, stream, rate, bit_width);
-+
-+	/* CON0 */
-+	mask |= ETDM_BIT_LEN_MASK;
-+	val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1);
-+	mask |= ETDM_WRD_LEN_MASK;
-+	val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1);
-+	mask |= ETDM_FMT_MASK;
-+	val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format);
-+	mask |= ETDM_CH_NUM_MASK;
-+	val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1);
-+	mask |= RELATCH_SRC_MASK;
-+	val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK);
-+
-+	switch (stream) {
-+	case SNDRV_PCM_STREAM_PLAYBACK:
-+		/* set ETDM_OUT5_CON0 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val);
-+
-+		/* set ETDM_OUT5_CON4 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_RELATCH_MASK, OUT_RELATCH(afe_rate));
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK));
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate));
-+
-+		/* set ETDM_OUT5_CON5 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON5,
-+				   ETDM_CLK_DIV_MASK, ETDM_CLK_DIV);
-+		break;
-+	case SNDRV_PCM_STREAM_CAPTURE:
-+		/* set ETDM_IN5_CON0 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val);
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0,
-+				   ETDM_SYNC_MASK, ETDM_SYNC);
-+
-+		/* set ETDM_IN5_CON2 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON2,
-+				   IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK));
-+
-+		/* set ETDM_IN5_CON3 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON3,
-+				   IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate));
-+
-+		/* set ETDM_IN5_CON4 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON4,
-+				   IN_RELATCH_MASK, IN_RELATCH(afe_rate));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
-+				  struct snd_pcm_hw_params *params,
-+				  struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
-+				struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+	dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+				   ETDM_EN);
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+				   ETDM_EN);
-+		break;
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+				   0);
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+				   0);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	struct mtk_dai_etdm_priv *etdm_data;
-+	void *priv_data;
-+
-+	switch (dai->id) {
-+	case MT7986_DAI_ETDM:
-+		break;
-+	default:
-+		dev_warn(afe->dev, "%s(), id %d not support\n",
-+			 __func__, dai->id);
-+		return -EINVAL;
-+	}
-+
-+	priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv),
-+				 GFP_KERNEL);
-+	if (!priv_data)
-+		return -ENOMEM;
-+
-+	afe_priv->dai_priv[dai->id] = priv_data;
-+	etdm_data = afe_priv->dai_priv[dai->id];
-+
-+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+	case SND_SOC_DAIFMT_I2S:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_A:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_B:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+	case SND_SOC_DAIFMT_NB_NF:
-+		etdm_data->bck_inv = false;
-+		etdm_data->lrck_inv = false;
-+		break;
-+	case SND_SOC_DAIFMT_NB_IF:
-+		etdm_data->bck_inv = false;
-+		etdm_data->lrck_inv = true;
-+		break;
-+	case SND_SOC_DAIFMT_IB_NF:
-+		etdm_data->bck_inv = true;
-+		etdm_data->lrck_inv = false;
-+		break;
-+	case SND_SOC_DAIFMT_IB_IF:
-+		etdm_data->bck_inv = true;
-+		etdm_data->lrck_inv = true;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+	case SND_SOC_DAIFMT_CBM_CFM:
-+		etdm_data->slave_mode = true;
-+		break;
-+	case SND_SOC_DAIFMT_CBS_CFS:
-+		etdm_data->slave_mode = false;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
-+	.startup = mtk_dai_etdm_startup,
-+	.shutdown = mtk_dai_etdm_shutdown,
-+	.hw_params = mtk_dai_etdm_hw_params,
-+	.trigger = mtk_dai_etdm_trigger,
-+	.set_fmt = mtk_dai_etdm_set_fmt,
-+};
-+
-+/* dai driver */
-+#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+			SNDRV_PCM_RATE_88200 |\
-+			SNDRV_PCM_RATE_96000 |\
-+			SNDRV_PCM_RATE_176400 |\
-+			SNDRV_PCM_RATE_192000)
-+
-+#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+			  SNDRV_PCM_FMTBIT_S24_LE |\
-+			  SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
-+	{
-+		.name = "ETDM",
-+		.id = MT7986_DAI_ETDM,
-+		.capture = {
-+			.stream_name = "ETDM Capture",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_ETDM_RATES,
-+			.formats = MTK_ETDM_FORMATS,
-+		},
-+		.playback = {
-+			.stream_name = "ETDM Playback",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_ETDM_RATES,
-+			.formats = MTK_ETDM_FORMATS,
-+		},
-+		.ops = &mtk_dai_etdm_ops,
-+		.symmetric_rate = 1,
-+		.symmetric_sample_bits = 1,
-+	},
-+};
-+
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe)
-+{
-+	struct mtk_base_afe_dai *dai;
-+
-+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+	if (!dai)
-+		return -ENOMEM;
-+
-+	list_add(&dai->list, &afe->sub_dais);
-+
-+	dai->dai_drivers = mtk_dai_etdm_driver;
-+	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
-+
-+	dai->dapm_widgets = mtk_dai_etdm_widgets;
-+	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
-+	dai->dapm_routes = mtk_dai_etdm_routes;
-+	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
-+
-+	return 0;
-+}
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch b/target/linux/mediatek/patches-5.15/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch
deleted file mode 100644
index 8139fdc668..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch
+++ /dev/null
@@ -1,685 +0,0 @@
-From fc7776dee86bc07d22820a904760a95f49a2f12e Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:35 +0800
-Subject: [PATCH 3/9] ASoC: mediatek: mt7986: add platform driver
-
-Add mt7986 platform driver.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig                 |  10 +
- sound/soc/mediatek/Makefile                |   1 +
- sound/soc/mediatek/mt7986/Makefile         |   8 +
- sound/soc/mediatek/mt7986/mt7986-afe-pcm.c | 622 +++++++++++++++++++++
- 4 files changed, 641 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/Makefile
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -54,6 +54,16 @@ config SND_SOC_MT6797_MT6351
- 	  Select Y if you have such device.
- 	  If unsure select "N".
- 
-+config SND_SOC_MT7986
-+	tristate "ASoC support for Mediatek MT7986 chip"
-+	depends on ARCH_MEDIATEK
-+	select SND_SOC_MEDIATEK
-+	help
-+	  This adds ASoC platform driver support for MediaTek MT7986 chip
-+	  that can be used with other codecs.
-+	  Select Y if you have such device.
-+	  If unsure select "N".
-+
- config SND_SOC_MT8173
- 	tristate "ASoC support for Mediatek MT8173 chip"
- 	depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/Makefile
-+++ b/sound/soc/mediatek/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_SND_SOC_MEDIATEK) += common/
- obj-$(CONFIG_SND_SOC_MT2701) += mt2701/
- obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
-+obj-$(CONFIG_SND_SOC_MT7986) += mt7986/
- obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
- obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
- obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+# platform driver
-+snd-soc-mt7986-afe-objs := \
-+	mt7986-afe-pcm.o \
-+	mt7986-dai-etdm.o
-+
-+obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-@@ -0,0 +1,622 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC AFE platform driver for MT7986
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/pm_runtime.h>
-+
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+#include "../common/mtk-afe-platform-driver.h"
-+#include "../common/mtk-afe-fe-dai.h"
-+
-+enum {
-+	MTK_AFE_RATE_8K = 0,
-+	MTK_AFE_RATE_11K = 1,
-+	MTK_AFE_RATE_12K = 2,
-+	MTK_AFE_RATE_16K = 4,
-+	MTK_AFE_RATE_22K = 5,
-+	MTK_AFE_RATE_24K = 6,
-+	MTK_AFE_RATE_32K = 8,
-+	MTK_AFE_RATE_44K = 9,
-+	MTK_AFE_RATE_48K = 10,
-+	MTK_AFE_RATE_88K = 13,
-+	MTK_AFE_RATE_96K = 14,
-+	MTK_AFE_RATE_176K = 17,
-+	MTK_AFE_RATE_192K = 18,
-+};
-+
-+enum {
-+	CLK_INFRA_AUD_BUS_CK = 0,
-+	CLK_INFRA_AUD_26M_CK,
-+	CLK_INFRA_AUD_L_CK,
-+	CLK_INFRA_AUD_AUD_CK,
-+	CLK_INFRA_AUD_EG2_CK,
-+	CLK_NUM
-+};
-+
-+static const char *aud_clks[CLK_NUM] = {
-+	[CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
-+	[CLK_INFRA_AUD_26M_CK] = "aud_26m_ck",
-+	[CLK_INFRA_AUD_L_CK] = "aud_l_ck",
-+	[CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
-+	[CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate)
-+{
-+	switch (rate) {
-+	case 8000:
-+		return MTK_AFE_RATE_8K;
-+	case 11025:
-+		return MTK_AFE_RATE_11K;
-+	case 12000:
-+		return MTK_AFE_RATE_12K;
-+	case 16000:
-+		return MTK_AFE_RATE_16K;
-+	case 22050:
-+		return MTK_AFE_RATE_22K;
-+	case 24000:
-+		return MTK_AFE_RATE_24K;
-+	case 32000:
-+		return MTK_AFE_RATE_32K;
-+	case 44100:
-+		return MTK_AFE_RATE_44K;
-+	case 48000:
-+		return MTK_AFE_RATE_48K;
-+	case 88200:
-+		return MTK_AFE_RATE_88K;
-+	case 96000:
-+		return MTK_AFE_RATE_96K;
-+	case 176400:
-+		return MTK_AFE_RATE_176K;
-+	case 192000:
-+		return MTK_AFE_RATE_192K;
-+	default:
-+		dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+			 __func__, rate, MTK_AFE_RATE_48K);
-+		return MTK_AFE_RATE_48K;
-+	}
-+}
-+
-+static const struct snd_pcm_hardware mt7986_afe_hardware = {
-+	.info = SNDRV_PCM_INFO_MMAP |
-+		SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_MMAP_VALID,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+		   SNDRV_PCM_FMTBIT_S24_LE |
-+		   SNDRV_PCM_FMTBIT_S32_LE,
-+	.period_bytes_min = 256,
-+	.period_bytes_max = 4 * 48 * 1024,
-+	.periods_min = 2,
-+	.periods_max = 256,
-+	.buffer_bytes_max = 8 * 48 * 1024,
-+	.fifo_size = 0,
-+};
-+
-+static int mt7986_memif_fs(struct snd_pcm_substream *substream,
-+			   unsigned int rate)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+	return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+static int mt7986_irq_fs(struct snd_pcm_substream *substream,
-+			 unsigned int rate)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+	return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+		       SNDRV_PCM_RATE_88200 |\
-+		       SNDRV_PCM_RATE_96000 |\
-+		       SNDRV_PCM_RATE_176400 |\
-+		       SNDRV_PCM_RATE_192000)
-+
-+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+			 SNDRV_PCM_FMTBIT_S24_LE |\
-+			 SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = {
-+	/* FE DAIs: memory intefaces to CPU */
-+	{
-+		.name = "DL1",
-+		.id = MT7986_MEMIF_DL1,
-+		.playback = {
-+			.stream_name = "DL1",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_PCM_RATES,
-+			.formats = MTK_PCM_FORMATS,
-+		},
-+		.ops = &mtk_afe_fe_ops,
-+	},
-+	{
-+		.name = "UL1",
-+		.id = MT7986_MEMIF_VUL12,
-+		.capture = {
-+			.stream_name = "UL1",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_PCM_RATES,
-+			.formats = MTK_PCM_FORMATS,
-+		},
-+		.ops = &mtk_afe_fe_ops,
-+	},
-+};
-+
-+static const struct snd_kcontrol_new o018_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o019_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = {
-+	/* DL */
-+	SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
-+
-+	/* UL */
-+	SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
-+			   o018_mix, ARRAY_SIZE(o018_mix)),
-+	SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
-+			   o019_mix, ARRAY_SIZE(o019_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mt7986_memif_routes[] = {
-+	{"I032", NULL, "DL1"},
-+	{"I033", NULL, "DL1"},
-+	{"UL1", NULL, "O018"},
-+	{"UL1", NULL, "O019"},
-+	{"O018", "I150_Switch", "I150"},
-+	{"O019", "I151_Switch", "I151"},
-+};
-+
-+static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = {
-+	.name = "mt7986-afe-pcm-dai",
-+};
-+
-+static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = {
-+	[MT7986_MEMIF_DL1] = {
-+		.name = "DL1",
-+		.id = MT7986_MEMIF_DL1,
-+		.reg_ofs_base = AFE_DL0_BASE,
-+		.reg_ofs_cur = AFE_DL0_CUR,
-+		.reg_ofs_end = AFE_DL0_END,
-+		.reg_ofs_base_msb = AFE_DL0_BASE_MSB,
-+		.reg_ofs_cur_msb = AFE_DL0_CUR_MSB,
-+		.reg_ofs_end_msb = AFE_DL0_END_MSB,
-+		.fs_reg = AFE_DL0_CON0,
-+		.fs_shift =  DL0_MODE_SFT,
-+		.fs_maskbit =  DL0_MODE_MASK,
-+		.mono_reg = AFE_DL0_CON0,
-+		.mono_shift = DL0_MONO_SFT,
-+		.enable_reg = AFE_DL0_CON0,
-+		.enable_shift = DL0_ON_SFT,
-+		.hd_reg = AFE_DL0_CON0,
-+		.hd_shift = DL0_HD_MODE_SFT,
-+		.hd_align_reg = AFE_DL0_CON0,
-+		.hd_align_mshift = DL0_HALIGN_SFT,
-+		.pbuf_reg = AFE_DL0_CON0,
-+		.pbuf_shift = DL0_PBUF_SIZE_SFT,
-+		.minlen_reg = AFE_DL0_CON0,
-+		.minlen_shift = DL0_MINLEN_SFT,
-+	},
-+	[MT7986_MEMIF_VUL12] = {
-+		.name = "VUL12",
-+		.id = MT7986_MEMIF_VUL12,
-+		.reg_ofs_base = AFE_VUL0_BASE,
-+		.reg_ofs_cur = AFE_VUL0_CUR,
-+		.reg_ofs_end = AFE_VUL0_END,
-+		.reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
-+		.reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
-+		.reg_ofs_end_msb = AFE_VUL0_END_MSB,
-+		.fs_reg = AFE_VUL0_CON0,
-+		.fs_shift = VUL0_MODE_SFT,
-+		.fs_maskbit = VUL0_MODE_MASK,
-+		.mono_reg = AFE_VUL0_CON0,
-+		.mono_shift = VUL0_MONO_SFT,
-+		.enable_reg = AFE_VUL0_CON0,
-+		.enable_shift = VUL0_ON_SFT,
-+		.hd_reg = AFE_VUL0_CON0,
-+		.hd_shift = VUL0_HD_MODE_SFT,
-+		.hd_align_reg = AFE_VUL0_CON0,
-+		.hd_align_mshift = VUL0_HALIGN_SFT,
-+	},
-+};
-+
-+static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = {
-+	[MT7986_IRQ_0] = {
-+		.id = MT7986_IRQ_0,
-+		.irq_cnt_reg = AFE_IRQ0_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ0_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ0_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ0_MCU_CLR_SFT,
-+	},
-+	[MT7986_IRQ_1] = {
-+		.id = MT7986_IRQ_1,
-+		.irq_cnt_reg = AFE_IRQ1_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ1_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ1_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ1_MCU_CLR_SFT,
-+	},
-+	[MT7986_IRQ_2] = {
-+		.id = MT7986_IRQ_2,
-+		.irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ2_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ2_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ2_MCU_CLR_SFT,
-+	},
-+};
-+
-+static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+	/*
-+	 * Those auto-gen regs are read-only, so put it as volatile because
-+	 * volatile registers cannot be cached, which means that they cannot
-+	 * be set when power is off
-+	 */
-+
-+	switch (reg) {
-+	case AFE_DL0_CUR_MSB:
-+	case AFE_DL0_CUR:
-+	case AFE_DL0_RCH_MON:
-+	case AFE_DL0_LCH_MON:
-+	case AFE_VUL0_CUR_MSB:
-+	case AFE_VUL0_CUR:
-+	case AFE_IRQ_MCU_STATUS:
-+	case AFE_MEMIF_RD_MON:
-+	case AFE_MEMIF_WR_MON:
-+		return true;
-+	default:
-+		return false;
-+	};
-+}
-+
-+static const struct regmap_config mt7986_afe_regmap_config = {
-+	.reg_bits = 32,
-+	.reg_stride = 4,
-+	.val_bits = 32,
-+	.volatile_reg = mt7986_is_volatile_reg,
-+	.max_register = AFE_MAX_REGISTER,
-+	.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
-+};
-+
-+static int mt7986_init_clock(struct mtk_base_afe *afe)
-+{
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret, i;
-+
-+	afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM,
-+				sizeof(*afe_priv->clks), GFP_KERNEL);
-+	if (!afe_priv->clks)
-+		return -ENOMEM;
-+	afe_priv->num_clks = CLK_NUM;
-+
-+	for (i = 0; i < afe_priv->num_clks; i++)
-+		afe_priv->clks[i].id = aud_clks[i];
-+
-+	ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to get clocks\n");
-+
-+	return 0;
-+}
-+
-+static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev)
-+{
-+	struct mtk_base_afe *afe = dev;
-+	struct mtk_base_afe_irq *irq;
-+	u32 mcu_en, status, status_mcu;
-+	int i, ret;
-+	irqreturn_t irq_ret = IRQ_HANDLED;
-+
-+	/* get irq that is sent to MCU */
-+	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
-+
-+	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
-+	/* only care IRQ which is sent to MCU */
-+	status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
-+
-+	if (ret || status_mcu == 0) {
-+		dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
-+			__func__, ret, status, mcu_en);
-+
-+		irq_ret = IRQ_NONE;
-+		goto err_irq;
-+	}
-+
-+	for (i = 0; i < MT7986_MEMIF_NUM; i++) {
-+		struct mtk_base_afe_memif *memif = &afe->memif[i];
-+
-+		if (!memif->substream)
-+			continue;
-+
-+		if (memif->irq_usage < 0)
-+			continue;
-+
-+		irq = &afe->irqs[memif->irq_usage];
-+
-+		if (status_mcu & (1 << irq->irq_data->irq_en_shift))
-+			snd_pcm_period_elapsed(memif->substream);
-+	}
-+
-+err_irq:
-+	/* clear irq */
-+	regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
-+
-+	return irq_ret;
-+}
-+
-+static int mt7986_afe_runtime_suspend(struct device *dev)
-+{
-+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+		goto skip_regmap;
-+
-+	/* disable clk*/
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0);
-+
-+	/* make sure all irq status are cleared, twice intended */
-+	regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
-+
-+skip_regmap:
-+	clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+
-+	return 0;
-+}
-+
-+static int mt7986_afe_runtime_resume(struct device *dev)
-+{
-+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
-+
-+	ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+		return 0;
-+
-+	/* enable clk*/
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK,
-+			   AUD_APLL2_EN);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK,
-+			   AUD_26M_EN);
-+
-+	return 0;
-+}
-+
-+static int mt7986_afe_component_probe(struct snd_soc_component *component)
-+{
-+	return mtk_afe_add_sub_dai_control(component);
-+}
-+
-+static const struct snd_soc_component_driver mt7986_afe_component = {
-+	.name = AFE_PCM_NAME,
-+	.probe = mt7986_afe_component_probe,
-+	.pointer	= mtk_afe_pcm_pointer,
-+	.pcm_construct	= mtk_afe_pcm_new,
-+};
-+
-+static int mt7986_dai_memif_register(struct mtk_base_afe *afe)
-+{
-+	struct mtk_base_afe_dai *dai;
-+
-+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+	if (!dai)
-+		return -ENOMEM;
-+
-+	list_add(&dai->list, &afe->sub_dais);
-+
-+	dai->dai_drivers = mt7986_memif_dai_driver;
-+	dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver);
-+
-+	dai->dapm_widgets = mt7986_memif_widgets;
-+	dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets);
-+	dai->dapm_routes = mt7986_memif_routes;
-+	dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes);
-+
-+	return 0;
-+}
-+
-+typedef int (*dai_register_cb)(struct mtk_base_afe *);
-+static const dai_register_cb dai_register_cbs[] = {
-+	mt7986_dai_etdm_register,
-+	mt7986_dai_memif_register,
-+};
-+
-+static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev)
-+{
-+	struct mtk_base_afe *afe;
-+	struct mt7986_afe_private *afe_priv;
-+	struct device *dev;
-+	int i, irq_id, ret;
-+
-+	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
-+	if (!afe)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, afe);
-+
-+	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
-+					  GFP_KERNEL);
-+	if (!afe->platform_priv)
-+		return -ENOMEM;
-+
-+	afe_priv = afe->platform_priv;
-+	afe->dev = &pdev->dev;
-+	dev = afe->dev;
-+
-+	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(afe->base_addr))
-+		return PTR_ERR(afe->base_addr);
-+
-+	/* initial audio related clock */
-+	ret = mt7986_init_clock(afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot initialize clocks\n");
-+
-+	ret = devm_pm_runtime_enable(dev);
-+	if (ret)
-+		return ret;
-+
-+	/* enable clock for regcache get default value from hw */
-+	afe_priv->pm_runtime_bypass_reg_ctl = true;
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
-+		      &mt7986_afe_regmap_config);
-+
-+	pm_runtime_put_sync(&pdev->dev);
-+	if (IS_ERR(afe->regmap))
-+		return PTR_ERR(afe->regmap);
-+
-+	afe_priv->pm_runtime_bypass_reg_ctl = false;
-+
-+	/* init memif */
-+	afe->memif_size = MT7986_MEMIF_NUM;
-+	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
-+				  GFP_KERNEL);
-+	if (!afe->memif)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < afe->memif_size; i++) {
-+		afe->memif[i].data = &memif_data[i];
-+		afe->memif[i].irq_usage = -1;
-+	}
-+
-+	mutex_init(&afe->irq_alloc_lock);
-+
-+	/* irq initialize */
-+	afe->irqs_size = MT7986_IRQ_NUM;
-+	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
-+				 GFP_KERNEL);
-+	if (!afe->irqs)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < afe->irqs_size; i++)
-+		afe->irqs[i].irq_data = &irq_data[i];
-+
-+	/* request irq */
-+	irq_id = platform_get_irq(pdev, 0);
-+	if (irq_id < 0) {
-+		ret = irq_id;
-+		return dev_err_probe(dev, ret, "No irq found\n");
-+	}
-+	ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler,
-+			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n");
-+
-+	/* init sub_dais */
-+	INIT_LIST_HEAD(&afe->sub_dais);
-+
-+	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
-+		ret = dai_register_cbs[i](afe);
-+		if (ret)
-+			return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i);
-+	}
-+
-+	/* init dai_driver and component_driver */
-+	ret = mtk_afe_combine_sub_dai(afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
-+
-+	afe->mtk_afe_hardware = &mt7986_afe_hardware;
-+	afe->memif_fs = mt7986_memif_fs;
-+	afe->irq_fs = mt7986_irq_fs;
-+
-+	afe->runtime_resume = mt7986_afe_runtime_resume;
-+	afe->runtime_suspend = mt7986_afe_runtime_suspend;
-+
-+	/* register component */
-+	ret = devm_snd_soc_register_component(&pdev->dev,
-+					      &mt7986_afe_component,
-+					      NULL, 0);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot register AFE component\n");
-+
-+	ret = devm_snd_soc_register_component(afe->dev,
-+					      &mt7986_afe_pcm_dai_component,
-+					      afe->dai_drivers,
-+					      afe->num_dai_drivers);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n");
-+
-+	return 0;
-+}
-+
-+static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev)
-+{
-+	pm_runtime_disable(&pdev->dev);
-+	if (!pm_runtime_status_suspended(&pdev->dev))
-+		mt7986_afe_runtime_suspend(&pdev->dev);
-+}
-+
-+static const struct of_device_id mt7986_afe_pcm_dt_match[] = {
-+	{ .compatible = "mediatek,mt7986-afe" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match);
-+
-+static const struct dev_pm_ops mt7986_afe_pm_ops = {
-+	SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend,
-+			   mt7986_afe_runtime_resume, NULL)
-+};
-+
-+static struct platform_driver mt7986_afe_pcm_driver = {
-+	.driver = {
-+		   .name = "mt7986-audio",
-+		   .of_match_table = mt7986_afe_pcm_dt_match,
-+		   .pm = &mt7986_afe_pm_ops,
-+	},
-+	.probe = mt7986_afe_pcm_dev_probe,
-+	.remove_new = mt7986_afe_pcm_dev_remove,
-+};
-+module_platform_driver(mt7986_afe_pcm_driver);
-+
-+MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch b/target/linux/mediatek/patches-5.15/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch
deleted file mode 100644
index dd354c04e3..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch
+++ /dev/null
@@ -1,243 +0,0 @@
-From ddf6abc1c78072f8ccad59166be95f0ca5af8ca4 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:36 +0800
-Subject: [PATCH 4/9] ASoC: mediatek: mt7986: add machine driver with wm8960
-
-Add support for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-5-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig                |  10 ++
- sound/soc/mediatek/mt7986/Makefile        |   1 +
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 196 ++++++++++++++++++++++
- 3 files changed, 207 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-wm8960.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -64,6 +64,16 @@ config SND_SOC_MT7986
- 	  Select Y if you have such device.
- 	  If unsure select "N".
- 
-+config SND_SOC_MT7986_WM8960
-+	tristate "ASoc Audio driver for MT7986 with WM8960 codec"
-+	depends on SND_SOC_MT7986 && I2C
-+	select SND_SOC_WM8960
-+	help
-+	  This adds support for ASoC machine driver for MediaTek MT7986
-+	  boards with the WM8960 codecs.
-+	  Select Y if you have such device.
-+	  If unsure select "N".
-+
- config SND_SOC_MT8173
- 	tristate "ASoC support for Mediatek MT8173 chip"
- 	depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/mt7986/Makefile
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -6,3 +6,4 @@ snd-soc-mt7986-afe-objs := \
- 	mt7986-dai-etdm.o
- 
- obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
-+obj-$(CONFIG_SND_SOC_MT7986_WM8960) += mt7986-wm8960.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -0,0 +1,196 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * mt7986-wm8960.c  --  MT7986-WM8960 ALSA SoC machine driver
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/module.h>
-+#include <sound/soc.h>
-+
-+#include "mt7986-afe-common.h"
-+
-+struct mt7986_wm8960_priv {
-+	struct device_node *platform_node;
-+	struct device_node *codec_node;
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
-+	SND_SOC_DAPM_HP("Headphone", NULL),
-+	SND_SOC_DAPM_MIC("AMIC", NULL),
-+};
-+
-+static const struct snd_kcontrol_new mt7986_wm8960_controls[] = {
-+	SOC_DAPM_PIN_SWITCH("Headphone"),
-+	SOC_DAPM_PIN_SWITCH("AMIC"),
-+};
-+
-+SND_SOC_DAILINK_DEFS(playback,
-+	DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
-+	DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(capture,
-+	DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
-+	DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(codec,
-+	DAILINK_COMP_ARRAY(COMP_CPU("ETDM")),
-+	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+static struct snd_soc_dai_link mt7986_wm8960_dai_links[] = {
-+	/* FE */
-+	{
-+		.name = "wm8960-playback",
-+		.stream_name = "wm8960-playback",
-+		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+			    SND_SOC_DPCM_TRIGGER_POST},
-+		.dynamic = 1,
-+		.dpcm_playback = 1,
-+		SND_SOC_DAILINK_REG(playback),
-+	},
-+	{
-+		.name = "wm8960-capture",
-+		.stream_name = "wm8960-capture",
-+		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+			    SND_SOC_DPCM_TRIGGER_POST},
-+		.dynamic = 1,
-+		.dpcm_capture = 1,
-+		SND_SOC_DAILINK_REG(capture),
-+	},
-+	/* BE */
-+	{
-+		.name = "wm8960-codec",
-+		.no_pcm = 1,
-+		.dai_fmt = SND_SOC_DAIFMT_I2S |
-+			SND_SOC_DAIFMT_NB_NF |
-+			SND_SOC_DAIFMT_CBS_CFS |
-+			SND_SOC_DAIFMT_GATED,
-+		.dpcm_playback = 1,
-+		.dpcm_capture = 1,
-+		SND_SOC_DAILINK_REG(codec),
-+	},
-+};
-+
-+static struct snd_soc_card mt7986_wm8960_card = {
-+	.name = "mt7986-wm8960",
-+	.owner = THIS_MODULE,
-+	.dai_link = mt7986_wm8960_dai_links,
-+	.num_links = ARRAY_SIZE(mt7986_wm8960_dai_links),
-+	.controls = mt7986_wm8960_controls,
-+	.num_controls = ARRAY_SIZE(mt7986_wm8960_controls),
-+	.dapm_widgets = mt7986_wm8960_widgets,
-+	.num_dapm_widgets = ARRAY_SIZE(mt7986_wm8960_widgets),
-+};
-+
-+static int mt7986_wm8960_machine_probe(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = &mt7986_wm8960_card;
-+	struct snd_soc_dai_link *dai_link;
-+	struct device_node *platform, *codec;
-+	struct mt7986_wm8960_priv *priv;
-+	int ret, i;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	platform = of_get_child_by_name(pdev->dev.of_node, "platform");
-+
-+	if (platform) {
-+		priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+		of_node_put(platform);
-+
-+		if (!priv->platform_node) {
-+			dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
-+			return -EINVAL;
-+		}
-+	} else {
-+		dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
-+		return -EINVAL;
-+	}
-+
-+	for_each_card_prelinks(card, i, dai_link) {
-+		if (dai_link->platforms->name)
-+			continue;
-+		dai_link->platforms->of_node = priv->platform_node;
-+	}
-+
-+	card->dev = &pdev->dev;
-+
-+	codec = of_get_child_by_name(pdev->dev.of_node, "codec");
-+
-+	if (codec) {
-+		priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+		of_node_put(codec);
-+
-+		if (!priv->codec_node) {
-+			of_node_put(priv->platform_node);
-+			dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
-+			return -EINVAL;
-+		}
-+	} else {
-+		of_node_put(priv->platform_node);
-+		dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
-+		return -EINVAL;
-+	}
-+
-+	for_each_card_prelinks(card, i, dai_link) {
-+		if (dai_link->codecs->name)
-+			continue;
-+		dai_link->codecs->of_node = priv->codec_node;
-+	}
-+
-+	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to parse audio-routing: %d\n", ret);
-+		goto err_of_node_put;
-+	}
-+
-+	ret = devm_snd_soc_register_card(&pdev->dev, card);
-+	if (ret) {
-+		dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+		goto err_of_node_put;
-+	}
-+
-+err_of_node_put:
-+	of_node_put(priv->codec_node);
-+	of_node_put(priv->platform_node);
-+	return ret;
-+}
-+
-+static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = platform_get_drvdata(pdev);
-+	struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
-+
-+	of_node_put(priv->codec_node);
-+	of_node_put(priv->platform_node);
-+}
-+
-+static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
-+	{.compatible = "mediatek,mt7986-wm8960-sound"},
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_wm8960_machine_dt_match);
-+
-+static struct platform_driver mt7986_wm8960_machine = {
-+	.driver = {
-+		.name = "mt7986-wm8960",
-+		.of_match_table = mt7986_wm8960_machine_dt_match,
-+	},
-+	.probe = mt7986_wm8960_machine_probe,
-+	.remove_new = mt7986_wm8960_machine_remove,
-+};
-+
-+module_platform_driver(mt7986_wm8960_machine);
-+
-+/* Module information */
-+MODULE_DESCRIPTION("MT7986 WM8960 ALSA SoC machine driver");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("mt7986 wm8960 soc card");
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch b/target/linux/mediatek/patches-5.15/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch
deleted file mode 100644
index 8cf0b5464a..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 72469f950b629e57e60fbcbefed45e083619b986 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:37 +0800
-Subject: [PATCH 5/9] ASoC: dt-bindings: mediatek,mt7986-wm8960: add
- mt7986-wm8960 document
-
-Add document for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-6-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../sound/mediatek,mt7986-wm8960.yaml         | 67 +++++++++++++++++++
- 1 file changed, 67 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-@@ -0,0 +1,67 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-wm8960.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7986 sound card with WM8960 codec
-+
-+maintainers:
-+  - Maso Huang <maso.huang@mediatek.com>
-+
-+allOf:
-+  - $ref: sound-card-common.yaml#
-+
-+properties:
-+  compatible:
-+    const: mediatek,mt7986-wm8960-sound
-+
-+  platform:
-+    type: object
-+    additionalProperties: false
-+    properties:
-+      sound-dai:
-+        description: The phandle of MT7986 platform.
-+        maxItems: 1
-+    required:
-+      - sound-dai
-+
-+  codec:
-+    type: object
-+    additionalProperties: false
-+    properties:
-+      sound-dai:
-+        description: The phandle of wm8960 codec.
-+        maxItems: 1
-+    required:
-+      - sound-dai
-+
-+unevaluatedProperties: false
-+
-+required:
-+  - compatible
-+  - audio-routing
-+  - platform
-+  - codec
-+
-+examples:
-+  - |
-+    sound {
-+        compatible = "mediatek,mt7986-wm8960-sound";
-+        model = "mt7986-wm8960";
-+        audio-routing =
-+            "Headphone", "HP_L",
-+            "Headphone", "HP_R",
-+            "LINPUT1", "AMIC",
-+            "RINPUT1", "AMIC";
-+
-+        platform {
-+            sound-dai = <&afe>;
-+        };
-+
-+        codec {
-+            sound-dai = <&wm8960>;
-+        };
-+    };
-+
-+...
diff --git a/target/linux/mediatek/patches-5.15/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch b/target/linux/mediatek/patches-5.15/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch
deleted file mode 100644
index 236d6a217c..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From d16202eb38585adbc16e32d11188dbc2127015de Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:38 +0800
-Subject: [PATCH 6/9] ASoC: dt-bindings: mediatek,mt7986-afe: add audio afe
- document
-
-Add mt7986 audio afe document.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-7-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../bindings/sound/mediatek,mt7986-afe.yaml   | 160 ++++++++++++++++++
- 1 file changed, 160 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-@@ -0,0 +1,160 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek AFE PCM controller for MT7986
-+
-+maintainers:
-+  - Maso Huang <maso.huang@mediatek.com>
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - const: mediatek,mt7986-afe
-+      - items:
-+          - enum:
-+              - mediatek,mt7981-afe
-+              - mediatek,mt7988-afe
-+          - const: mediatek,mt7986-afe
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    minItems: 5
-+    items:
-+      - description: audio bus clock
-+      - description: audio 26M clock
-+      - description: audio intbus clock
-+      - description: audio hopping clock
-+      - description: audio pll clock
-+      - description: mux for pcm_mck
-+      - description: audio i2s/pcm mck
-+
-+  clock-names:
-+    minItems: 5
-+    items:
-+      - const: bus_ck
-+      - const: 26m_ck
-+      - const: l_ck
-+      - const: aud_ck
-+      - const: eg2_ck
-+      - const: sel
-+      - const: i2s_m
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - clock-names
-+
-+allOf:
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7986-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7981-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+            - description: mux for pcm_mck
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+            - const: sel
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7988-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+            - description: mux for pcm_mck
-+            - description: audio i2s/pcm mck
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+            - const: sel
-+            - const: i2s_m
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+    #include <dt-bindings/clock/mt7986-clk.h>
-+
-+    afe@11210000 {
-+        compatible = "mediatek,mt7986-afe";
-+        reg = <0x11210000 0x9000>;
-+        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+        clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_L_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
-+        clock-names = "bus_ck",
-+                      "26m_ck",
-+                      "l_ck",
-+                      "aud_ck",
-+                      "eg2_ck";
-+        assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+                          <&topckgen CLK_TOP_AUD_L_SEL>,
-+                          <&topckgen CLK_TOP_A_TUNER_SEL>;
-+        assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+                                 <&apmixedsys CLK_APMIXED_APLL2>,
-+                                 <&topckgen CLK_TOP_APLL2_D4>;
-+    };
-+
-+...
diff --git a/target/linux/mediatek/patches-5.15/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch b/target/linux/mediatek/patches-5.15/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch
deleted file mode 100644
index 413db8233f..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:17 +0800
-Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of
- mt7986_wm8960
-
-Drop the remove callback of mt7986_wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ----------
- 1 file changed, 10 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -163,15 +163,6 @@ err_of_node_put:
- 	return ret;
- }
- 
--static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
--{
--	struct snd_soc_card *card = platform_get_drvdata(pdev);
--	struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
--
--	of_node_put(priv->codec_node);
--	of_node_put(priv->platform_node);
--}
--
- static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
- 	{.compatible = "mediatek,mt7986-wm8960-sound"},
- 	{ /* sentinel */ }
-@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8
- 		.of_match_table = mt7986_wm8960_machine_dt_match,
- 	},
- 	.probe = mt7986_wm8960_machine_probe,
--	.remove_new = mt7986_wm8960_machine_remove,
- };
- 
- module_platform_driver(mt7986_wm8960_machine);
diff --git a/target/linux/mediatek/patches-5.15/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch b/target/linux/mediatek/patches-5.15/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch
deleted file mode 100644
index 5c596fc49c..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:18 +0800
-Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv
- structure
-
-Remove the mt7986_wm8960_priv structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++--------------
- 1 file changed, 12 insertions(+), 21 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -12,11 +12,6 @@
- 
- #include "mt7986-afe-common.h"
- 
--struct mt7986_wm8960_priv {
--	struct device_node *platform_node;
--	struct device_node *codec_node;
--};
--
- static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
- 	SND_SOC_DAPM_HP("Headphone", NULL),
- 	SND_SOC_DAPM_MIC("AMIC", NULL),
-@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s
- 	struct snd_soc_card *card = &mt7986_wm8960_card;
- 	struct snd_soc_dai_link *dai_link;
- 	struct device_node *platform, *codec;
--	struct mt7986_wm8960_priv *priv;
-+	struct device_node *platform_dai_node, *codec_dai_node;
- 	int ret, i;
- 
--	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
--	if (!priv)
--		return -ENOMEM;
-+	card->dev = &pdev->dev;
- 
- 	platform = of_get_child_by_name(pdev->dev.of_node, "platform");
- 
- 	if (platform) {
--		priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+		platform_dai_node = of_parse_phandle(platform, "sound-dai", 0);
- 		of_node_put(platform);
- 
--		if (!priv->platform_node) {
-+		if (!platform_dai_node) {
- 			dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
- 			return -EINVAL;
- 		}
-@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s
- 	for_each_card_prelinks(card, i, dai_link) {
- 		if (dai_link->platforms->name)
- 			continue;
--		dai_link->platforms->of_node = priv->platform_node;
-+		dai_link->platforms->of_node = platform_dai_node;
- 	}
- 
--	card->dev = &pdev->dev;
--
- 	codec = of_get_child_by_name(pdev->dev.of_node, "codec");
- 
- 	if (codec) {
--		priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+		codec_dai_node = of_parse_phandle(codec, "sound-dai", 0);
- 		of_node_put(codec);
- 
--		if (!priv->codec_node) {
--			of_node_put(priv->platform_node);
-+		if (!codec_dai_node) {
-+			of_node_put(platform_dai_node);
- 			dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
- 			return -EINVAL;
- 		}
- 	} else {
--		of_node_put(priv->platform_node);
-+		of_node_put(platform_dai_node);
- 		dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
- 		return -EINVAL;
- 	}
-@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s
- 	for_each_card_prelinks(card, i, dai_link) {
- 		if (dai_link->codecs->name)
- 			continue;
--		dai_link->codecs->of_node = priv->codec_node;
-+		dai_link->codecs->of_node = codec_dai_node;
- 	}
- 
- 	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s
- 	}
- 
- err_of_node_put:
--	of_node_put(priv->codec_node);
--	of_node_put(priv->platform_node);
-+	of_node_put(platform_dai_node);
-+	of_node_put(codec_dai_node);
- 	return ret;
- }
- 
diff --git a/target/linux/mediatek/patches-5.15/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch b/target/linux/mediatek/patches-5.15/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch
deleted file mode 100644
index d4128deabc..0000000000
--- a/target/linux/mediatek/patches-5.15/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:19 +0800
-Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker
-
-mt7986 only supports 8/12/16/24/32/48/96/192 kHz
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++----
- 1 file changed, 19 insertions(+), 4 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct
- 				  struct snd_pcm_hw_params *params,
- 				  struct snd_soc_dai *dai)
- {
-+	unsigned int rate = params_rate(params);
- 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
- 
--	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
--	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
--
--	return 0;
-+	switch (rate) {
-+	case 8000:
-+	case 12000:
-+	case 16000:
-+	case 24000:
-+	case 32000:
-+	case 48000:
-+	case 96000:
-+	case 192000:
-+		mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+		mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+		return 0;
-+	default:
-+		dev_err(afe->dev,
-+			"Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n",
-+			rate);
-+		return -EINVAL;
-+	}
- }
- 
- static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
diff --git a/target/linux/mediatek/patches-5.15/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch b/target/linux/mediatek/patches-5.15/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch
deleted file mode 100644
index a40c249257..0000000000
--- a/target/linux/mediatek/patches-5.15/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 10 Dec 2023 22:41:39 +0000
-Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of
- -EPROBE_DEFER
-
-If probe is defered no error should be printed. Mute it.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s
- 
- 	ret = devm_snd_soc_register_card(&pdev->dev, card);
- 	if (ret) {
--		dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+
- 		goto err_of_node_put;
- 	}
- 
diff --git a/target/linux/mediatek/patches-5.15/862-arm64-dts-mt7986-add-afe.patch b/target/linux/mediatek/patches-5.15/862-arm64-dts-mt7986-add-afe.patch
deleted file mode 100644
index b31710fe69..0000000000
--- a/target/linux/mediatek/patches-5.15/862-arm64-dts-mt7986-add-afe.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add afe
-
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi     | 23 +++++++++++
- 1 files changed, 23 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -248,6 +248,28 @@
- 			status = "disabled";
- 		};
- 
-+		afe: audio-controller@11210000 {
-+			compatible = "mediatek,mt7986-afe";
-+			reg = <0 0x11210000 0 0x9000>;
-+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-+				 <&infracfg CLK_INFRA_AUD_26M_CK>,
-+				 <&infracfg CLK_INFRA_AUD_L_CK>,
-+				 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-+				 <&infracfg CLK_INFRA_AUD_EG2_CK>;
-+			clock-names = "aud_bus_ck",
-+				      "aud_26m_ck",
-+				      "aud_l_ck",
-+				      "aud_aud_ck",
-+				      "aud_eg2_ck";
-+			assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+					  <&topckgen CLK_TOP_AUD_L_SEL>,
-+					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-+			assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+						 <&apmixedsys CLK_APMIXED_APLL2>,
-+						 <&topckgen CLK_TOP_APLL2_D4>;
-+		};
-+
- 		pwm: pwm@10048000 {
- 			compatible = "mediatek,mt7986-pwm";
- 			reg = <0 0x10048000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/863-arm64-dts-mt7986-add-sound-wm8960.patch b/target/linux/mediatek/patches-5.15/863-arm64-dts-mt7986-add-sound-wm8960.patch
deleted file mode 100644
index 15e30dec56..0000000000
--- a/target/linux/mediatek/patches-5.15/863-arm64-dts-mt7986-add-sound-wm8960.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add sound wm8960
-
----
- .../dts/mediatek/mt7986a-rfb-spim-nand.dts    | 39 +++++++++++++++++++
- 1 files changed, 39 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-@@ -4,6 +4,35 @@
- 
- / {
- 	compatible = "mediatek,mt7986a-rfb-snand";
-+
-+	sound_wm8960 {
-+		compatible = "mediatek,mt7986-wm8960-sound";
-+		audio-routing = "Headphone", "HP_L",
-+				"Headphone", "HP_R",
-+				"LINPUT1", "AMIC",
-+				"RINPUT1", "AMIC";
-+
-+		status = "okay";
-+
-+		platform {
-+			sound-dai = <&afe>;
-+		};
-+
-+		codec {
-+			sound-dai = <&wm8960>;
-+		};
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c_pins>;
-+	status = "okay";
-+
-+	wm8960: wm8960@1a {
-+		compatible = "wlf,wm8960";
-+		reg = <0x1a>;
-+	};
- };
- 
- &spi0 {
-@@ -50,3 +79,13 @@
- &wifi {
- 	mediatek,mtd-eeprom = <&factory 0>;
- };
-+
-+&pio {
-+	i2c_pins: i2c-pins-3-4 {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c";
-+		};
-+	};
-+};
-+
diff --git a/target/linux/mediatek/patches-5.15/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/target/linux/mediatek/patches-5.15/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch
deleted file mode 100644
index 4fc12bf402..0000000000
--- a/target/linux/mediatek/patches-5.15/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch
+++ /dev/null
@@ -1,65 +0,0 @@
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso
-@@ -0,0 +1,62 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2023 MediaTek Inc.
-+ * Author: Maso Huang <Maso.Huang@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			sound_wm8960 {
-+				compatible = "mediatek,mt7986-wm8960-sound";
-+				audio-routing = "Headphone", "HP_L",
-+					"Headphone", "HP_R",
-+					"LINPUT1", "AMIC",
-+					"RINPUT1", "AMIC";
-+
-+				status = "okay";
-+
-+				platform {
-+					sound-dai = <&afe>;
-+				};
-+
-+				codec {
-+					sound-dai = <&wm8960>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c0>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&i2c_pins>;
-+			clock-frequency = <400000>;
-+			status = "okay";
-+
-+			wm8960: wm8960@1a {
-+				compatible = "wlf,wm8960";
-+				reg = <0x1a>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&pio>;
-+		__overlay__ {
-+			i2c_pins: i2c-pins-3-4 {
-+				mux {
-+					function = "i2c";
-+					groups = "i2c";
-+				};
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
deleted file mode 100644
index f779c1e047..0000000000
--- a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
+++ /dev/null
@@ -1,65 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -318,7 +318,7 @@
- 	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
- 	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
- 	 */
--	asm_sel {
-+	asmsel: asm_sel {
- 		gpio-hog;
- 		gpios = <90 GPIO_ACTIVE_HIGH>;
- 		output-high;
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+	fragment@0 {
-+		target = <&asmsel>;
-+		__overlay__ {
-+			gpios = <90 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&sata>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sata_phy>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+	fragment@0 {
-+		target = <&asmsel>;
-+		__overlay__ {
-+			gpios = <90 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+};
diff --git a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch
deleted file mode 100644
index 54901f5549..0000000000
--- a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch
+++ /dev/null
@@ -1,54 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1730,6 +1730,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 
- endchoice
- 
-+config CMDLINE_OVERRIDE
-+	bool "Use alternative cmdline from device tree"
-+	help
-+	  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+	  be used, this is not a good option for kernels that are shared across
-+	  devices. This setting enables using "chosen/cmdline-override" as the
-+	  cmdline if it exists in the device tree.
-+
- config CMDLINE
- 	string "Default kernel command string"
- 	default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns
- 	if (p != NULL && l > 0)
- 		strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
- 
-+	/* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+	 * device tree option of chosen/bootargs-override. This is
-+	 * helpful on boards where u-boot sets bootargs, and is unable
-+	 * to be modified.
-+	 */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+	if (p != NULL && l > 0)
-+		strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- 	/*
- 	 * CONFIG_CMDLINE is meant to be a default in case nothing else
- 	 * managed to set the command line, unless CONFIG_CMDLINE_FORCE
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -2059,6 +2059,14 @@ config CMDLINE_FORCE
- 
- endchoice
- 
-+config CMDLINE_OVERRIDE
-+	bool "Use alternative cmdline from device tree"
-+	help
-+	  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+	  be used, this is not a good option for kernels that are shared across
-+	  devices. This setting enables using "chosen/cmdline-override" as the
-+	  cmdline if it exists in the device tree.
-+
- config EFI_STUB
- 	bool
- 
diff --git a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
deleted file mode 100644
index 2a863aecf9..0000000000
--- a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -645,5 +645,28 @@
- };
- 
- &wmac {
-+	mediatek,eeprom-data = <0x22760500	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x44000020	0x0		0x10002000
-+				0x4400		0x4000000	0x0		0x0
-+				0x200000b3	0x40b6c3c3	0x26000000	0x41c42600
-+				0x41c4		0x26000000	0xc0c52600	0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0xc6c6
-+				0xc3c3c2c1	0xc300c3	0x818181	0x83c1c182
-+				0x83838382	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x84002e00	0x90000087	0x8a000000	0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0xb000009	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x7707>;
-+
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch b/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch
deleted file mode 100644
index d9379721fb..0000000000
--- a/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 59b0f51335644ee603260faaa4298c0115fb7187 Mon Sep 17 00:00:00 2001
-From: Fengquan Chen <Fengquan.Chen@mediatek.com>
-Date: Tue, 14 Sep 2021 20:34:54 +0800
-Subject: [PATCH] watchdog: mtk: add disable_wdt_extrst support
-
-In some cases, we may need watchdog just to trigger an
-internal soc reset without sending any output signal.
-
-Provide a disable_wdt_extrst parameter for configuration.
-We can disable or enable it just by configuring dts.
-
-Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20210914123454.32603-3-Fengquan.Chen@mediatek.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -65,6 +65,7 @@ struct mtk_wdt_dev {
- 	void __iomem *wdt_base;
- 	spinlock_t lock; /* protects WDT_SWSYSRST reg */
- 	struct reset_controller_dev rcdev;
-+	bool disable_wdt_extrst;
- };
- 
- struct mtk_wdt_data {
-@@ -256,6 +257,8 @@ static int mtk_wdt_start(struct watchdog
- 		reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
- 	else
- 		reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
-+	if (mtk_wdt->disable_wdt_extrst)
-+		reg &= ~WDT_MODE_EXRST_EN;
- 	reg |= (WDT_MODE_EN | WDT_MODE_KEY);
- 	iowrite32(reg, wdt_base + WDT_MODE);
- 
-@@ -381,6 +384,10 @@ static int mtk_wdt_probe(struct platform
- 		if (err)
- 			return err;
- 	}
-+
-+	mtk_wdt->disable_wdt_extrst =
-+		of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
-+
- 	return 0;
- }
- 
diff --git a/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch b/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch
deleted file mode 100644
index 96fb215f76..0000000000
--- a/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 711a5b25bac95dcd1111521ed71693330e74a926 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Wed, 5 Jan 2022 18:04:56 +0800
-Subject: [PATCH] watchdog: mtk_wdt: mt7986: Add toprgu reset controller
- support
-
-Besides watchdog, the mt7986 toprgu module also provides software reset
-functionality for various peripheral subsystems
-(eg, ethernet, pcie, and connectivity)
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220105100456.7126-3-sam.shih@mediatek.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -10,6 +10,7 @@
-  */
- 
- #include <dt-bindings/reset-controller/mt2712-resets.h>
-+#include <dt-bindings/reset/mt7986-resets.h>
- #include <dt-bindings/reset-controller/mt8183-resets.h>
- #include <dt-bindings/reset-controller/mt8192-resets.h>
- #include <dt-bindings/reset/mt8195-resets.h>
-@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt2712_
- 	.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
- };
- 
-+static const struct mtk_wdt_data mt7986_data = {
-+	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
-+};
-+
- static const struct mtk_wdt_data mt8183_data = {
- 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
- };
-@@ -418,6 +423,7 @@ static int mtk_wdt_resume(struct device
- static const struct of_device_id mtk_wdt_dt_ids[] = {
- 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
- 	{ .compatible = "mediatek,mt6589-wdt" },
-+	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
- 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
- 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
- 	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
diff --git a/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch b/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch
deleted file mode 100644
index f026f5573c..0000000000
--- a/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 4 May 2022 12:03:42 +0200
-Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3
-
-This allows it to coexist with the other mtk pcie driver in the same kernel
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -1031,7 +1031,7 @@ static struct platform_driver mtk_pcie_d
- 	.probe = mtk_pcie_probe,
- 	.remove = mtk_pcie_remove,
- 	.driver = {
--		.name = "mtk-pcie",
-+		.name = "mtk-pcie-gen3",
- 		.of_match_table = mtk_pcie_of_match,
- 		.pm = &mtk_pcie_pm_ops,
- 	},
diff --git a/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch
deleted file mode 100644
index ebb6c060b5..0000000000
--- a/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -1231,10 +1231,16 @@ static int mtk_spi_probe(struct platform
- 		goto err_disable_spi_hclk;
- 	}
- 
-+	ret = clk_prepare_enable(mdata->sel_clk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret);
-+		goto err_disable_spi_clk;
-+	}
-+
- 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
--		goto err_disable_spi_clk;
-+		goto err_disable_spi_sel_clk;
- 	}
- 
- 	mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
-@@ -1285,6 +1291,8 @@ static int mtk_spi_probe(struct platform
- 
- err_disable_runtime_pm:
- 	pm_runtime_disable(&pdev->dev);
-+err_disable_spi_sel_clk:
-+	clk_disable_unprepare(mdata->sel_clk);
- err_disable_spi_clk:
- 	clk_disable_unprepare(mdata->spi_clk);
- err_disable_spi_hclk:
diff --git a/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
deleted file mode 100644
index 30be53518a..0000000000
--- a/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001
-Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 16:40:31 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename
- mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region
-
-This is a preliminary patch to move wed ilm/dlm and cpuboot properties in
-dedicated dts nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we
- }
- 
- static int
--mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index,
--			  struct mtk_wed_wo_memory_region *region)
-+mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index,
-+				   struct mtk_wed_wo_memory_region *region)
- {
- 	struct reserved_mem *rmem;
- 	struct device_node *np;
-@@ -321,7 +321,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 		if (index < 0)
- 			continue;
- 
--		ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]);
-+		ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- 		if (ret)
- 			return ret;
- 	}
diff --git a/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
deleted file mode 100644
index 3ba485346c..0000000000
--- a/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001
-Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 16:32:41 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++----------
- 1 file changed, 11 insertions(+), 10 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -121,12 +121,6 @@
- 			reg = <0 0x151f8000 0 0x2000>;
- 			no-map;
- 		};
--
--		wo_boot: wo-boot@15194000 {
--			reg = <0 0x15194000 0 0x1000>;
--			no-map;
--		};
--
- 	};
- 
- 	timer {
-@@ -540,10 +534,11 @@
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- 			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
--					<&wo_data>, <&wo_boot>;
-+					<&wo_data>;
- 			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data", "wo-boot";
-+					      "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
-+			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
- 		wed1: wed@15011000 {
-@@ -553,10 +548,11 @@
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- 			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
--					<&wo_data>, <&wo_boot>;
-+					<&wo_data>;
- 			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data", "wo-boot";
-+					      "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
-+			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
- 		wo_ccif0: syscon@151a5000 {
-@@ -573,6 +569,11 @@
- 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
-+		wo_cpuboot: syscon@15194000 {
-+			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-+			reg = <0 0x15194000 0 0x1000>;
-+		};
-+
- 		eth: ethernet@15100000 {
- 			compatible = "mediatek,mt7986-eth";
- 			reg = <0 0x15100000 0 0x80000>;
diff --git a/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
deleted file mode 100644
index b4bea2087b..0000000000
--- a/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001
-Message-Id: <f292d1bf83ec160bef2532b58aa08f5b71041923.1678716918.git.lorenzo@kernel.org>
-In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 18:13:04 +0100
-Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a
- dedicated dts node
-
-Since the cpuboot memory region is not part of the RAM SoC, move cpuboot
-in a deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where cpuboot was
-defined as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_wed_wo.h  |  3 +-
- 2 files changed, 30 insertions(+), 7 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -34,12 +34,23 @@ static struct mtk_wed_wo_memory_region m
- 
- static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
- {
--	return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+	u32 val;
-+
-+	if (!wo->boot_regmap)
-+		return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+
-+	if (regmap_read(wo->boot_regmap, reg, &val))
-+		val = ~0;
-+
-+	return val;
- }
- 
- static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
- {
--	writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+	if (wo->boot_regmap)
-+		regmap_write(wo->boot_regmap, reg, val);
-+	else
-+		writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
- }
- 
- static struct sk_buff *
-@@ -313,6 +324,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 	u32 val, boot_cr;
- 	int ret, i;
- 
-+	wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
-+							  "mediatek,wo-cpuboot");
-+
- 	/* load firmware region metadata */
- 	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
- 		int index = of_property_match_string(wo->hw->node,
-@@ -321,6 +335,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 		if (index < 0)
- 			continue;
- 
-+		if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap))
-+			continue;
-+
- 		ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- 		if (ret)
- 			return ret;
---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue {
- struct mtk_wed_wo {
- 	struct mtk_wed_hw *hw;
- 
-+	struct regmap *boot_regmap;
- 	struct mtk_wed_wo_queue q_tx;
- 	struct mtk_wed_wo_queue q_rx;
- 
diff --git a/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
deleted file mode 100644
index b4ba5b0d2d..0000000000
--- a/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001
-Message-Id: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 18:51:47 +0100
-Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts
- node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where ilm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++---
- 1 file changed, 49 insertions(+), 6 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -316,6 +316,39 @@ next:
- }
- 
- static int
-+mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo)
-+{
-+	struct mtk_wed_wo_memory_region *ilm_region;
-+	struct resource res;
-+	struct device_node *np;
-+	int ret;
-+
-+	np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0);
-+	if (!np)
-+		return 0;
-+
-+	ret = of_address_to_resource(np, 0, &res);
-+	of_node_put(np);
-+
-+	if (ret < 0)
-+		return ret;
-+
-+	ilm_region = &mem_region[MTK_WED_WO_REGION_ILM];
-+	ilm_region->phy_addr = res.start;
-+	ilm_region->size = resource_size(&res);
-+	ilm_region->addr = devm_ioremap(wo->hw->dev, res.start,
-+					resource_size(&res));
-+
-+	if (!IS_ERR(ilm_region->addr))
-+		return 0;
-+
-+	ret = PTR_ERR(ilm_region->addr);
-+	ilm_region->addr = NULL;
-+
-+	return ret;
-+}
-+
-+static int
- mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
- {
- 	const struct mtk_wed_fw_trailer *trailer;
-@@ -324,14 +357,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 	u32 val, boot_cr;
- 	int ret, i;
- 
-+	mtk_wed_mcu_load_ilm(wo);
- 	wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
- 							  "mediatek,wo-cpuboot");
- 
- 	/* load firmware region metadata */
- 	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
--		int index = of_property_match_string(wo->hw->node,
--						     "memory-region-names",
--						     mem_region[i].name);
-+		int index;
-+
-+		if (mem_region[i].addr)
-+			continue;
-+
-+		index = of_property_match_string(wo->hw->node,
-+						 "memory-region-names",
-+						 mem_region[i].name);
- 		if (index < 0)
- 			continue;
- 
diff --git a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
deleted file mode 100644
index c92fcd43ce..0000000000
--- a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001
-Message-Id: <b74ba226be2c45091b93bd49192bdd6d2178729e.1678718888.git.lorenzo@kernel.org>
-In-Reply-To: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-References: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:45:16 +0100
-Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts
- node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where dlm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- 	struct device_node *np;
- 	int index;
- 
-+	np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0);
-+	if (np) {
-+		struct resource res;
-+		int ret;
-+
-+		ret = of_address_to_resource(np, 0, &res);
-+		of_node_put(np);
-+
-+		if (ret < 0)
-+			return ret;
-+
-+		dev->rro.miod_phys = res.start;
-+		goto out;
-+	}
-+
-+	/* For backward compatibility, we need to check if DLM
-+	 * node is defined through reserved memory property.
-+	 */
- 	index = of_property_match_string(dev->hw->node, "memory-region-names",
- 					 "wo-dlm");
- 	if (index < 0)
-@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- 		return -ENODEV;
- 
- 	dev->rro.miod_phys = rmem->base;
-+out:
- 	dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
- 
- 	return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
diff --git a/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
deleted file mode 100644
index 0ba9bd7cf0..0000000000
--- a/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001
-Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:10:56 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------
- 1 file changed, 16 insertions(+), 18 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -97,16 +97,6 @@
- 			no-map;
- 		};
- 
--		wo_ilm0: wo-ilm@151e0000 {
--			reg = <0 0x151e0000 0 0x8000>;
--			no-map;
--		};
--
--		wo_ilm1: wo-ilm@151f0000 {
--			reg = <0 0x151f0000 0 0x8000>;
--			no-map;
--		};
--
- 		wo_data: wo-data@4fd80000 {
- 			reg = <0 0x4fd80000 0 0x240000>;
- 			no-map;
-@@ -533,11 +523,10 @@
- 			reg = <0 0x15010000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
--					<&wo_data>;
--			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data";
-+			memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
-+			mediatek,wo-ilm = <&wo_ilm0>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -547,11 +536,10 @@
- 			reg = <0 0x15011000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
--					<&wo_data>;
--			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data";
-+			memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
-+			mediatek,wo-ilm = <&wo_ilm1>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -569,6 +557,16 @@
- 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
-+		wo_ilm0: syscon@151e0000 {
-+			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+			reg = <0 0x151e0000 0 0x8000>;
-+		};
-+
-+		wo_ilm1: syscon@151f0000 {
-+			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+			reg = <0 0x151f0000 0 0x8000>;
-+		};
-+
- 		wo_cpuboot: syscon@15194000 {
- 			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- 			reg = <0 0x15194000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
deleted file mode 100644
index 90b2bb91a2..0000000000
--- a/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001
-Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:53:30 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++-----------
- 1 file changed, 16 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -101,16 +101,6 @@
- 			reg = <0 0x4fd80000 0 0x240000>;
- 			no-map;
- 		};
--
--		wo_dlm0: wo-dlm@151e8000 {
--			reg = <0 0x151e8000 0 0x2000>;
--			no-map;
--		};
--
--		wo_dlm1: wo-dlm@151f8000 {
--			reg = <0 0x151f8000 0 0x2000>;
--			no-map;
--		};
- 	};
- 
- 	timer {
-@@ -523,10 +513,11 @@
- 			reg = <0 0x15010000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
--			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+			memory-region = <&wo_emi0>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
- 			mediatek,wo-ilm = <&wo_ilm0>;
-+			mediatek,wo-dlm = <&wo_dlm0>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -536,10 +527,11 @@
- 			reg = <0 0x15011000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
--			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+			memory-region = <&wo_emi1>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
- 			mediatek,wo-ilm = <&wo_ilm1>;
-+			mediatek,wo-dlm = <&wo_dlm1>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -567,6 +559,16 @@
- 			reg = <0 0x151f0000 0 0x8000>;
- 		};
- 
-+		wo_dlm0: syscon@151e8000 {
-+			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+			reg = <0 0x151e8000 0 0x2000>;
-+		};
-+
-+		wo_dlm1: syscon@151f8000 {
-+			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+			reg = <0 0x151f8000 0 0x2000>;
-+		};
-+
- 		wo_cpuboot: syscon@15194000 {
- 			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- 			reg = <0 0x15194000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch
deleted file mode 100644
index f8f1156e71..0000000000
--- a/target/linux/mediatek/patches-5.15/950-smartrg-i2c-led-driver.patch
+++ /dev/null
@@ -1,34 +0,0 @@
----
- drivers/leds/Kconfig  |   10 ++++++++++
- drivers/leds/Makefile |    1 +
- 2 files changed, 11 insertions(+)
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -878,6 +878,16 @@ source "drivers/leds/blink/Kconfig"
- comment "Flash and Torch LED drivers"
- source "drivers/leds/flash/Kconfig"
- 
-+config LEDS_SMARTRG_LED
-+	tristate "LED support for Adtran SmartRG"
-+	depends on LEDS_CLASS && I2C && OF
-+	help
-+	  This option enables support for the Adtran SmartRG platform
-+	  system LED driver.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called leds-smartrg-system.
-+
- comment "LED Triggers"
- source "drivers/leds/trigger/Kconfig"
- 
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -77,6 +77,7 @@ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
- obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
- obj-$(CONFIG_LEDS_S3C24XX)		+= leds-s3c24xx.o
- obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o
-+obj-$(CONFIG_LEDS_SMARTRG_LED)		+= leds-smartrg-system.o
- obj-$(CONFIG_LEDS_SUNFIRE)		+= leds-sunfire.o
- obj-$(CONFIG_LEDS_SYSCON)		+= leds-syscon.o
- obj-$(CONFIG_LEDS_TCA6507)		+= leds-tca6507.o
diff --git a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
deleted file mode 100644
index 3b59491189..0000000000
--- a/target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
+++ /dev/null
@@ -1,599 +0,0 @@
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Thu, 2 Nov 2023 16:47:07 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields
- in mtk_soc_data struct
-
-Split tx and rx fields in mtk_soc_data struct. This is a preliminary
-patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang
-if the device receives a corrupted packet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  29 +--
- 2 files changed, 139 insertions(+), 100 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1239,7 +1239,7 @@ static int mtk_init_fq_dma(struct mtk_et
- 		eth->scratch_ring = eth->sram_base;
- 	else
- 		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
--						       cnt * soc->txrx.txd_size,
-+						       cnt * soc->tx.desc_size,
- 						       &eth->phy_scratch_ring,
- 						       GFP_KERNEL);
- 	if (unlikely(!eth->scratch_ring))
-@@ -1255,16 +1255,16 @@ static int mtk_init_fq_dma(struct mtk_et
- 	if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
- 		return -ENOMEM;
- 
--	phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
-+	phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
- 
- 	for (i = 0; i < cnt; i++) {
- 		struct mtk_tx_dma_v2 *txd;
- 
--		txd = eth->scratch_ring + i * soc->txrx.txd_size;
-+		txd = eth->scratch_ring + i * soc->tx.desc_size;
- 		txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
- 		if (i < cnt - 1)
- 			txd->txd2 = eth->phy_scratch_ring +
--				    (i + 1) * soc->txrx.txd_size;
-+				    (i + 1) * soc->tx.desc_size;
- 
- 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
- 		txd->txd4 = 0;
-@@ -1511,7 +1511,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	if (itxd == ring->last_free)
- 		return -ENOMEM;
- 
--	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 	memset(itx_buf, 0, sizeof(*itx_buf));
- 
- 	txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1552,7 +1552,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- 			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
- 			txd_info.size = min_t(unsigned int, frag_size,
--					      soc->txrx.dma_max_len);
-+					      soc->tx.dma_max_len);
- 			txd_info.qid = queue;
- 			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
- 					!(frag_size - txd_info.size);
-@@ -1565,7 +1565,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 			mtk_tx_set_dma_desc(dev, txd, &txd_info);
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			if (new_desc)
- 				memset(tx_buf, 0, sizeof(*tx_buf));
- 			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1608,7 +1608,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	} else {
- 		int next_idx;
- 
--		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
-+		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
- 					 ring->dma_size);
- 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
- 	}
-@@ -1617,7 +1617,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- err_dma:
- 	do {
--		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 
- 		/* unmap dma */
- 		mtk_tx_unmap(eth, tx_buf, false);
-@@ -1642,7 +1642,7 @@ static int mtk_cal_txd_req(struct mtk_et
- 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- 			frag = &skb_shinfo(skb)->frags[i];
- 			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
--					       eth->soc->txrx.dma_max_len);
-+					       eth->soc->tx.dma_max_len);
- 		}
- 	} else {
- 		nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1783,7 +1783,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
- 
- 		ring = &eth->rx_ring[i];
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		if (rxd->rxd2 & RX_DMA_DONE) {
- 			ring->calc_idx_update = true;
- 			return ring;
-@@ -1951,7 +1951,7 @@ static int mtk_xdp_submit_frame(struct m
- 	}
- 	htxd = txd;
- 
--	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
-+	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
- 	memset(tx_buf, 0, sizeof(*tx_buf));
- 	htx_buf = tx_buf;
- 
-@@ -1971,7 +1971,7 @@ static int mtk_xdp_submit_frame(struct m
- 				goto unmap;
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			memset(tx_buf, 0, sizeof(*tx_buf));
- 			n_desc++;
- 		}
-@@ -2008,7 +2008,7 @@ static int mtk_xdp_submit_frame(struct m
- 	} else {
- 		int idx;
- 
--		idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
-+		idx = txd_to_idx(ring, txd, soc->tx.desc_size);
- 		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
- 			MT7628_TX_CTX_IDX0);
- 	}
-@@ -2020,7 +2020,7 @@ static int mtk_xdp_submit_frame(struct m
- unmap:
- 	while (htxd != txd) {
- 		txd_pdma = qdma_to_pdma(ring, htxd);
--		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
- 		mtk_tx_unmap(eth, tx_buf, false);
- 
- 		htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2148,7 +2148,7 @@ static int mtk_poll_rx(struct napi_struc
- 			goto rx_done;
- 
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		data = ring->data[idx];
- 
- 		if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2283,7 +2283,7 @@ static int mtk_poll_rx(struct napi_struc
- 			rxdcsum = &trxd.rxd4;
- 		}
- 
--		if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
-+		if (*rxdcsum & eth->soc->rx.dma_l4_valid)
- 			skb->ip_summed = CHECKSUM_UNNECESSARY;
- 		else
- 			skb_checksum_none_assert(skb);
-@@ -2405,7 +2405,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
- 			break;
- 
- 		tx_buf = mtk_desc_to_tx_buf(ring, desc,
--					    eth->soc->txrx.txd_size);
-+					    eth->soc->tx.desc_size);
- 		if (!tx_buf->data)
- 			break;
- 
-@@ -2453,7 +2453,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
- 		}
- 		mtk_tx_unmap(eth, tx_buf, true);
- 
--		desc = ring->dma + cpu * eth->soc->txrx.txd_size;
-+		desc = ring->dma + cpu * eth->soc->tx.desc_size;
- 		ring->last_free = desc;
- 		atomic_inc(&ring->free_count);
- 
-@@ -2542,7 +2542,7 @@ static int mtk_napi_rx(struct napi_struc
- 	do {
- 		int rx_done;
- 
--		mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
-+		mtk_w32(eth, eth->soc->rx.irq_done_mask,
- 			reg_map->pdma.irq_status);
- 		rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
- 		rx_done_total += rx_done;
-@@ -2558,10 +2558,10 @@ static int mtk_napi_rx(struct napi_struc
- 			return budget;
- 
- 	} while (mtk_r32(eth, reg_map->pdma.irq_status) &
--		 eth->soc->txrx.rx_irq_done_mask);
-+		 eth->soc->rx.irq_done_mask);
- 
- 	if (napi_complete_done(napi, rx_done_total))
--		mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- 
- 	return rx_done_total;
- }
-@@ -2570,7 +2570,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- {
- 	const struct mtk_soc_data *soc = eth->soc;
- 	struct mtk_tx_ring *ring = &eth->tx_ring;
--	int i, sz = soc->txrx.txd_size;
-+	int i, sz = soc->tx.desc_size;
- 	struct mtk_tx_dma_v2 *txd;
- 	int ring_size;
- 	u32 ofs, val;
-@@ -2693,14 +2693,14 @@ static void mtk_tx_clean(struct mtk_eth
- 	}
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
- 
- 	if (ring->dma_pdma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma_pdma, ring->phys_pdma);
- 		ring->dma_pdma = NULL;
- 	}
-@@ -2755,15 +2755,15 @@ static int mtk_rx_alloc(struct mtk_eth *
- 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
- 	    rx_flag != MTK_RX_FLAGS_NORMAL) {
- 		ring->dma = dma_alloc_coherent(eth->dma_dev,
--					       rx_dma_size * eth->soc->txrx.rxd_size,
--					       &ring->phys, GFP_KERNEL);
-+				rx_dma_size * eth->soc->rx.desc_size,
-+				&ring->phys, GFP_KERNEL);
- 	} else {
- 		struct mtk_tx_ring *tx_ring = &eth->tx_ring;
- 
- 		ring->dma = tx_ring->dma + tx_ring_size *
--			    eth->soc->txrx.txd_size * (ring_no + 1);
-+			    eth->soc->tx.desc_size * (ring_no + 1);
- 		ring->phys = tx_ring->phys + tx_ring_size *
--			     eth->soc->txrx.txd_size * (ring_no + 1);
-+			     eth->soc->tx.desc_size * (ring_no + 1);
- 	}
- 
- 	if (!ring->dma)
-@@ -2774,7 +2774,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 		dma_addr_t dma_addr;
- 		void *data;
- 
--		rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + i * eth->soc->rx.desc_size;
- 		if (ring->page_pool) {
- 			data = mtk_page_pool_get_buff(ring->page_pool,
- 						      &dma_addr, GFP_KERNEL);
-@@ -2863,7 +2863,7 @@ static void mtk_rx_clean(struct mtk_eth
- 			if (!ring->data[i])
- 				continue;
- 
--			rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+			rxd = ring->dma + i * eth->soc->rx.desc_size;
- 			if (!rxd->rxd1)
- 				continue;
- 
-@@ -2880,7 +2880,7 @@ static void mtk_rx_clean(struct mtk_eth
- 
- 	if (!in_sram && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * eth->soc->txrx.rxd_size,
-+				  ring->dma_size * eth->soc->rx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
-@@ -3243,7 +3243,7 @@ static void mtk_dma_free(struct mtk_eth
- 			netdev_reset_queue(eth->netdev[i]);
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
- 		dma_free_coherent(eth->dma_dev,
--				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
-+				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
- 				  eth->scratch_ring, eth->phy_scratch_ring);
- 		eth->scratch_ring = NULL;
- 		eth->phy_scratch_ring = 0;
-@@ -3293,7 +3293,7 @@ static irqreturn_t mtk_handle_irq_rx(int
- 
- 	eth->rx_events++;
- 	if (likely(napi_schedule_prep(&eth->rx_napi))) {
--		mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 		__napi_schedule(&eth->rx_napi);
- 	}
- 
-@@ -3319,9 +3319,9 @@ static irqreturn_t mtk_handle_irq(int ir
- 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
- 
- 	if (mtk_r32(eth, reg_map->pdma.irq_mask) &
--	    eth->soc->txrx.rx_irq_done_mask) {
-+	    eth->soc->rx.irq_done_mask) {
- 		if (mtk_r32(eth, reg_map->pdma.irq_status) &
--		    eth->soc->txrx.rx_irq_done_mask)
-+		    eth->soc->rx.irq_done_mask)
- 			mtk_handle_irq_rx(irq, _eth);
- 	}
- 	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3339,10 +3339,10 @@ static void mtk_poll_controller(struct n
- 	struct mtk_eth *eth = mac->hw;
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	mtk_handle_irq_rx(eth->irq[2], dev);
- 	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- }
- #endif
- 
-@@ -3507,7 +3507,7 @@ static int mtk_open(struct net_device *d
- 		napi_enable(&eth->tx_napi);
- 		napi_enable(&eth->rx_napi);
- 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--		mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
- 		refcount_set(&eth->dma_refcnt, 1);
- 	}
- 	else
-@@ -3590,7 +3590,7 @@ static int mtk_stop(struct net_device *d
- 	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	napi_disable(&eth->tx_napi);
- 	napi_disable(&eth->rx_napi);
- 
-@@ -4066,9 +4066,9 @@ static int mtk_hw_init(struct mtk_eth *e
- 
- 	/* FE int grouping */
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
- 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
- 
- 	if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5168,11 +5168,15 @@ static const struct mtk_soc_data mt2701_
- 	.required_clks = MT7623_CLKS_BITMAP,
- 	.required_pctl = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5188,11 +5192,15 @@ static const struct mtk_soc_data mt7621_
- 	.offload_version = 1,
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5210,11 +5218,15 @@ static const struct mtk_soc_data mt7622_
- 	.hash_offset = 2,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5231,11 +5243,15 @@ static const struct mtk_soc_data mt7623_
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
- 	.disable_pll_modes = true,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5250,11 +5266,15 @@ static const struct mtk_soc_data mt7629_
- 	.required_pctl = false,
- 	.has_accounting = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5272,11 +5292,15 @@ static const struct mtk_soc_data mt7981_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5294,11 +5318,15 @@ static const struct mtk_soc_data mt7986_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5316,11 +5344,15 @@ static const struct mtk_soc_data mt7988_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5333,11 +5365,15 @@ static const struct mtk_soc_data rt5350_
- 	.required_clks = MT7628_CLKS_BITMAP,
- 	.required_pctl = false,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -326,8 +326,8 @@
- /* QDMA descriptor txd3 */
- #define TX_DMA_OWNER_CPU	BIT(31)
- #define TX_DMA_LS0		BIT(30)
--#define TX_DMA_PLEN0(x)		(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define TX_DMA_PLEN1(x)		((x) & eth->soc->txrx.dma_max_len)
-+#define TX_DMA_PLEN0(x)		(((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
-+#define TX_DMA_PLEN1(x)		((x) & eth->soc->tx.dma_max_len)
- #define TX_DMA_SWC		BIT(14)
- #define TX_DMA_PQID		GENMASK(3, 0)
- #define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
-@@ -347,8 +347,8 @@
- /* QDMA descriptor rxd2 */
- #define RX_DMA_DONE		BIT(31)
- #define RX_DMA_LSO		BIT(30)
--#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
-+#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
-+#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
- #define RX_DMA_VTAG		BIT(15)
- #define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
- #if IS_ENABLED(CONFIG_64BIT)
-@@ -1279,10 +1279,9 @@ struct mtk_reg_map {
-  * @foe_entry_size		Foe table entry size.
-  * @has_accounting		Bool indicating support for accounting of
-  *				offloaded flows.
-- * @txd_size			Tx DMA descriptor size.
-- * @rxd_size			Rx DMA descriptor size.
-- * @rx_irq_done_mask		Rx irq done register mask.
-- * @rx_dma_l4_valid		Rx DMA valid register mask.
-+ * @desc_size			Tx/Rx DMA descriptor size.
-+ * @irq_done_mask		Rx irq done register mask.
-+ * @dma_l4_valid		Rx DMA valid register mask.
-  * @dma_max_len			Max DMA tx/rx buffer length.
-  * @dma_len_offset		Tx/Rx DMA length field offset.
-  */
-@@ -1300,13 +1299,17 @@ struct mtk_soc_data {
- 	bool		has_accounting;
- 	bool		disable_pll_modes;
- 	struct {
--		u32	txd_size;
--		u32	rxd_size;
--		u32	rx_irq_done_mask;
--		u32	rx_dma_l4_valid;
-+		u32	desc_size;
- 		u32	dma_max_len;
- 		u32	dma_len_offset;
--	} txrx;
-+	} tx;
-+	struct {
-+		u32	desc_size;
-+		u32	irq_done_mask;
-+		u32	dma_l4_valid;
-+		u32	dma_max_len;
-+		u32	dma_len_offset;
-+	} rx;
- };
- 
- #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
diff --git a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
deleted file mode 100644
index 3d4d68cb81..0000000000
--- a/target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
+++ /dev/null
@@ -1,123 +0,0 @@
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 10 Oct 2023 21:06:43 +0200
-Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
- ADMAv2 on MT7981 and MT7986
-
-ADMA is plagued by RX hangs which can't easily detected and happen upon
-receival of a corrupted package.
-Use QDMA just like on netsys v1 which is also still present and usable, and
-doesn't suffer from that problem.
-
-Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
- 1 file changed, 23 insertions(+), 23 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -108,16 +108,16 @@ static const struct mtk_reg_map mt7986_r
- 	.tx_irq_mask		= 0x461c,
- 	.tx_irq_status		= 0x4618,
- 	.pdma = {
--		.rx_ptr		= 0x6100,
--		.rx_cnt_cfg	= 0x6104,
--		.pcrx_ptr	= 0x6108,
--		.glo_cfg	= 0x6204,
--		.rst_idx	= 0x6208,
--		.delay_irq	= 0x620c,
--		.irq_status	= 0x6220,
--		.irq_mask	= 0x6228,
--		.adma_rx_dbg0	= 0x6238,
--		.int_grp	= 0x6250,
-+		.rx_ptr		= 0x4100,
-+		.rx_cnt_cfg	= 0x4104,
-+		.pcrx_ptr	= 0x4108,
-+		.glo_cfg	= 0x4204,
-+		.rst_idx	= 0x4208,
-+		.delay_irq	= 0x420c,
-+		.irq_status	= 0x4220,
-+		.irq_mask	= 0x4228,
-+		.adma_rx_dbg0	= 0x4238,
-+		.int_grp	= 0x4250,
- 	},
- 	.qdma = {
- 		.qtx_cfg	= 0x4400,
-@@ -1207,7 +1207,7 @@ static bool mtk_rx_get_desc(struct mtk_e
- 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
- 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
- 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
- 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
- 	}
-@@ -2155,7 +2155,7 @@ static int mtk_poll_rx(struct napi_struc
- 			break;
- 
- 		/* find out which mac the packet come from. values start at 1 */
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
- 
- 			switch (val) {
-@@ -2267,7 +2267,7 @@ static int mtk_poll_rx(struct napi_struc
- 		skb->dev = netdev;
- 		bytes += skb->len;
- 
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
- 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
- 			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 
- 		rxd->rxd3 = 0;
- 		rxd->rxd4 = 0;
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			rxd->rxd5 = 0;
- 			rxd->rxd6 = 0;
- 			rxd->rxd7 = 0;
-@@ -4012,7 +4012,7 @@ static int mtk_hw_init(struct mtk_eth *e
- 	else
- 		mtk_hw_reset(eth);
- 
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		/* Set FE to PDMAv2 if necessary */
- 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
- 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5298,11 +5298,11 @@ static const struct mtk_soc_data mt7981_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
-@@ -5324,11 +5324,11 @@ static const struct mtk_soc_data mt7986_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch b/target/linux/mediatek/patches-5.15/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
deleted file mode 100644
index 11b52d07ab..0000000000
--- a/target/linux/mediatek/patches-5.15/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1071,13 +1071,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+	mtk_wed_dma_disable(dev);
- 	mtk_wed_set_ext_int(dev, false);
- 
- 	wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- 	wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
--	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- 
- 	if (!mtk_wed_get_rx_capa(dev))
- 		return;
-@@ -1090,7 +1090,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- 	mtk_wed_stop(dev);
--	mtk_wed_dma_disable(dev);
- 
- 	wed_clr(dev, MTK_WED_CTRL,
- 		MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2621,9 +2620,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
--	if (!dev->running)
--		return;
--
- 	mtk_wed_set_ext_int(dev, !!mask);
- 	wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
diff --git a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch b/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
similarity index 95%
rename from target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch
rename to target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
index 3e45646fdb..bb87c20a91 100644
--- a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch
+++ b/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
@@ -72,18 +72,17 @@ Subject: [PATCH] kernel: add block fit partition parser
 +int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
 --- a/block/partitions/core.c
 +++ b/block/partitions/core.c
-@@ -10,6 +10,10 @@
- #include <linux/ctype.h>
+@@ -11,6 +11,9 @@
  #include <linux/vmalloc.h>
  #include <linux/raid/detect.h>
+ #include <linux/property.h>
 +#ifdef CONFIG_FIT_PARTITION
 +#include <linux/root_dev.h>
 +#endif
-+
+ 
  #include "check.h"
  
- static int (*check_part[])(struct parsed_partitions *) = {
-@@ -46,6 +50,9 @@ static int (*check_part[])(struct parsed
+@@ -48,6 +51,9 @@ static int (*check_part[])(struct parsed
  #ifdef CONFIG_EFI_PARTITION
  	efi_partition,		/* this must come before msdos */
  #endif
@@ -93,7 +92,7 @@ Subject: [PATCH] kernel: add block fit partition parser
  #ifdef CONFIG_SGI_PARTITION
  	sgi_partition,
  #endif
-@@ -398,6 +405,11 @@ static struct block_device *add_partitio
+@@ -439,6 +445,11 @@ static struct block_device *add_partitio
  			goto out_del;
  	}
  
@@ -105,7 +104,7 @@ Subject: [PATCH] kernel: add block fit partition parser
  	/* everything is up and running, commence */
  	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
  	if (err)
-@@ -590,6 +602,11 @@ static bool blk_add_partition(struct gen
+@@ -631,6 +642,11 @@ static bool blk_add_partition(struct gen
  	    (state->parts[p].flags & ADDPART_FLAG_RAID))
  		md_autodetect_dev(part->bd_dev);
  
@@ -194,7 +193,7 @@ Subject: [PATCH] kernel: add block fit partition parser
  	set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
 --- a/drivers/mtd/ubi/block.c
 +++ b/drivers/mtd/ubi/block.c
-@@ -431,7 +431,9 @@ int ubiblock_create(struct ubi_volume_in
+@@ -432,7 +432,9 @@ int ubiblock_create(struct ubi_volume_in
  		ret = -ENODEV;
  		goto out_cleanup_disk;
  	}
diff --git a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
index bf1912a916..1cca6f3534 100644
--- a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
+++ b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -21,6 +21,10 @@
+@@ -21,6 +21,12 @@
  	aliases {
  		serial0 = &uart0;
  		ethernet0 = &gmac0;
@@ -8,10 +8,12 @@
 +		led-failsafe = &led_system_blue;
 +		led-running = &led_system_green;
 +		led-upgrade = &led_system_blue;
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
  	};
  
  	chosen {
-@@ -44,8 +48,8 @@
+@@ -44,8 +50,8 @@
  		compatible = "gpio-keys";
  
  		factory-key {
@@ -22,7 +24,7 @@
  			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  		};
  
-@@ -59,17 +63,17 @@
+@@ -59,17 +65,17 @@
  	leds {
  		compatible = "gpio-leds";
  
diff --git a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
index e30d9e5e12..0d324084b1 100644
--- a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
+++ b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -554,12 +554,16 @@
+@@ -556,12 +556,16 @@
  	status = "okay";
  };
  
diff --git a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch
index 93f87fe697..16aed70b44 100644
--- a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch
+++ b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -251,14 +251,42 @@
+@@ -253,14 +253,42 @@
  	status = "disabled";
  };
  
diff --git a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
index 676c09f656..03e7aef9f0 100644
--- a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
+++ b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -152,6 +152,10 @@
+@@ -154,6 +154,10 @@
  		switch@0 {
  			compatible = "mediatek,mt7531";
  			reg = <0>;
diff --git a/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch b/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch
new file mode 100644
index 0000000000..38510c0fc7
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch
@@ -0,0 +1,131 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+@@ -23,7 +23,27 @@
+ 			no-sd;
+ 			no-sdio;
+ 			status = "okay";
++
++			card@0 {
++				compatible = "mmc-card";
++				reg = <0>;
++
++				block {
++					compatible = "block-device";
++					partitions {
++						emmc_rootdisk: block-partition-production {
++							partname = "production";
++						};
++					};
++				};
++			};
+ 		};
+ 	};
+-};
+ 
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-emmc = <&emmc_rootdisk>;
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -29,27 +29,30 @@
+ 
+ 					partition@0 {
+ 						label = "bl2";
+-						reg = <0x0 0x100000>;
++						reg = <0x0 0x200000>;
+ 						read-only;
+ 					};
+ 
+-					partition@100000 {
+-						label = "reserved";
+-						reg = <0x100000 0x280000>;
+-					};
+-
+-					partition@380000 {
+-						label = "fip";
+-						reg = <0x380000 0x200000>;
+-						read-only;
+-					};
+-
+-					partition@580000 {
++					partition@200000 {
+ 						label = "ubi";
+-						reg = <0x580000 0x7a80000>;
++						reg = <0x200000 0x7e00000>;
++						compatible = "linux,ubi";
++
++						volumes {
++							nand_rootdisk: ubi-volume-fit {
++								volname = "fit";
++							};
++						};
+ 					};
+ 				};
+ 			};
+ 		};
+ 	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-spim-nand = <&nand_rootdisk>;
++		};
++	};
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -52,7 +52,7 @@
+ 						reg = <0x180000 0xa80000>;
+ 					};
+ 
+-					partition@c00000 {
++					nor_rootdisk: partition@c00000 {
+ 						label = "fit";
+ 						reg = <0xc00000 0x1400000>;
+ 						compatible = "denx,fit";
+@@ -61,4 +61,11 @@
+ 			};
+ 		};
+ 	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-nor = <&nor_rootdisk>;
++		};
++	};
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+@@ -17,6 +17,27 @@
+ 			max-frequency = <52000000>;
+ 			cap-sd-highspeed;
+ 			status = "okay";
++
++			card@0 {
++				compatible = "mmc-card";
++				reg = <0>;
++
++				block {
++					compatible = "block-device";
++					partitions {
++						sd_rootdisk: block-partition-production {
++							partname = "production";
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-sd = <&sd_rootdisk>;
+ 		};
+ 	};
+ };
diff --git a/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch b/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch
new file mode 100644
index 0000000000..8820d57f01
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch
@@ -0,0 +1,30 @@
+From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 18 Feb 2024 01:59:59 +0000
+Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
+
+Without the SGM_REG_SEL clock enabled the system freezes if trying to
+access registers used by MT7981 clock drivers itself.
+Mark SGM_REG_SEL as critical to make sure it is always enabled to
+prevent freezes on boot depending on probe order.
+
+Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
+@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[]
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ 			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 			     0x1C0, 21),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
+-			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
++				   0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
+ 			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
+ 	/* CLK_CFG_6 */
diff --git a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch
deleted file mode 100644
index 75ca114a58..0000000000
--- a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct
- 			pll->data->pcw_shift);
- 	val |= pcw << pll->data->pcw_shift;
- 	writel(val, pll->pcw_addr);
--	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
-+	if (pll->data->pcw_chg_shift)
-+		chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
-+	else
-+		chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
- 	writel(chg, pll->pcw_chg_addr);
- 	if (pll->tuner_addr)
- 		writel(val + 1, pll->tuner_addr);
---- a/drivers/clk/mediatek/clk-pll.h
-+++ b/drivers/clk/mediatek/clk-pll.h
-@@ -42,6 +42,7 @@ struct mtk_pll_data {
- 	u32 pcw_reg;
- 	int pcw_shift;
- 	u32 pcw_chg_reg;
-+	int pcw_chg_shift;
- 	const struct mtk_pll_div_table *div_table;
- 	const char *parent_name;
- 	u32 en_reg;
diff --git a/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch b/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch
new file mode 100644
index 0000000000..ad4ecdf83f
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch
@@ -0,0 +1,75 @@
+From cc4d9e0c77494fcf6bccbc57e23db0007cf681b7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 26 Jan 2023 03:33:46 +0000
+Subject: [PATCH] dt-bindings: clock: Add compatibles for MT7981
+
+Add compatible string for MT7981 to existing bindings at
+ - mediatek,apmixedsys.yaml
+ - mediatek,topckgen.yaml
+ - mediatek,ethsys.txt
+ - mediatek,infracfg.yaml
+ - mediatek,sgmiisys.txt
+
+Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/cc85ee470c781ff4013f6c21c92c0a21574b12b2.1674703830.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt        | 1 +
+ .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml     | 1 +
+ .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt      | 2 ++
+ .../devicetree/bindings/clock/mediatek,apmixedsys.yaml          | 1 +
+ Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml  | 1 +
+ 5 files changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+@@ -10,6 +10,7 @@ Required Properties:
+ 	- "mediatek,mt7622-ethsys", "syscon"
+ 	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+ 	- "mediatek,mt7629-ethsys", "syscon"
++	- "mediatek,mt7981-ethsys", "syscon"
+ 	- "mediatek,mt7986-ethsys", "syscon"
+ - #clock-cells: Must be 1
+ - #reset-cells: Must be 1
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+@@ -28,6 +28,7 @@ properties:
+               - mediatek,mt6797-infracfg
+               - mediatek,mt7622-infracfg
+               - mediatek,mt7629-infracfg
++              - mediatek,mt7981-infracfg
+               - mediatek,mt7986-infracfg
+               - mediatek,mt8135-infracfg
+               - mediatek,mt8167-infracfg
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+@@ -8,6 +8,8 @@ Required Properties:
+ - compatible: Should be:
+ 	- "mediatek,mt7622-sgmiisys", "syscon"
+ 	- "mediatek,mt7629-sgmiisys", "syscon"
++	- "mediatek,mt7981-sgmiisys_0", "syscon"
++	- "mediatek,mt7981-sgmiisys_1", "syscon"
+ 	- "mediatek,mt7986-sgmiisys_0", "syscon"
+ 	- "mediatek,mt7986-sgmiisys_1", "syscon"
+ - #clock-cells: Must be 1
+--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+@@ -20,6 +20,7 @@ properties:
+       - enum:
+           - mediatek,mt6797-apmixedsys
+           - mediatek,mt7622-apmixedsys
++          - mediatek,mt7981-apmixedsys
+           - mediatek,mt7986-apmixedsys
+           - mediatek,mt8135-apmixedsys
+           - mediatek,mt8173-apmixedsys
+--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+@@ -35,6 +35,7 @@ properties:
+               - mediatek,mt6779-topckgen
+               - mediatek,mt6795-topckgen
+               - mediatek,mt7629-topckgen
++              - mediatek,mt7981-topckgen
+               - mediatek,mt7986-topckgen
+               - mediatek,mt8167-topckgen
+               - mediatek,mt8183-topckgen
diff --git a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch
deleted file mode 100644
index 3ced012495..0000000000
--- a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
- 	  This driver adds support for clocks for Ethernet and SGMII
- 	  required on MediaTek MT7986 SoC.
- 
-+config COMMON_CLK_MT7988
-+	bool "Clock driver for MediaTek MT7988"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7988 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
- obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
diff --git a/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch b/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch
new file mode 100644
index 0000000000..48d3d4e90c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch
@@ -0,0 +1,107 @@
+From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:56:52 +0000
+Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT
+ schema
+
+Convert mediatek,sgmiiisys bindings to DT schema format.
+Add maintainer Matthias Brugger, no maintainers were listed in the
+original documentation.
+As this node is also referenced by the Ethernet controller and used
+as SGMII PCS add this fact to the description.
+Move the file to Documentation/devicetree/bindings/net/pcs/ which seems
+more appropriate given that the great majority of registers are related
+to SGMII PCS functionality and only one register represents clock bits.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../arm/mediatek/mediatek,sgmiisys.txt        | 27 ----------
+ .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 49 +++++++++++++++++++
+ 2 files changed, 49 insertions(+), 27 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+ create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
++++ /dev/null
+@@ -1,27 +0,0 @@
+-MediaTek SGMIISYS controller
+-============================
+-
+-The MediaTek SGMIISYS controller provides various clocks to the system.
+-
+-Required Properties:
+-
+-- compatible: Should be:
+-	- "mediatek,mt7622-sgmiisys", "syscon"
+-	- "mediatek,mt7629-sgmiisys", "syscon"
+-	- "mediatek,mt7981-sgmiisys_0", "syscon"
+-	- "mediatek,mt7981-sgmiisys_1", "syscon"
+-	- "mediatek,mt7986-sgmiisys_0", "syscon"
+-	- "mediatek,mt7986-sgmiisys_1", "syscon"
+-- #clock-cells: Must be 1
+-
+-The SGMIISYS controller uses the common clk binding from
+-Documentation/devicetree/bindings/clock/clock-bindings.txt
+-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+-
+-Example:
+-
+-sgmiisys: sgmiisys@1b128000 {
+-	compatible = "mediatek,mt7622-sgmiisys", "syscon";
+-	reg = <0 0x1b128000 0 0x1000>;
+-	#clock-cells = <1>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -0,0 +1,49 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek SGMIISYS Controller
++
++maintainers:
++  - Matthias Brugger <matthias.bgg@gmail.com>
++
++description:
++  The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
++  to the ethernet subsystem to which it is attached.
++
++properties:
++  compatible:
++    items:
++      - enum:
++          - mediatek,mt7622-sgmiisys
++          - mediatek,mt7629-sgmiisys
++          - mediatek,mt7986-sgmiisys_0
++          - mediatek,mt7986-sgmiisys_1
++      - const: syscon
++
++  reg:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++      sgmiisys: syscon@1b128000 {
++        compatible = "mediatek,mt7622-sgmiisys", "syscon";
++        reg = <0 0x1b128000 0 0x1000>;
++        #clock-cells = <1>;
++      };
++    };
diff --git a/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch
new file mode 100644
index 0000000000..62a64b9dd0
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch
@@ -0,0 +1,37 @@
+From 4f7eb19c4f44078100659f6ba073b0cc7191bc91 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:57:04 +0000
+Subject: [PATCH 2/2] dt-bindings: net: pcs: mediatek,sgmiisys: add MT7981 SoC
+
+Add mediatek,pnswap boolean property needed on many boards using the
+MediaTek MT7981 SoC.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml      | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -19,6 +19,8 @@ properties:
+       - enum:
+           - mediatek,mt7622-sgmiisys
+           - mediatek,mt7629-sgmiisys
++          - mediatek,mt7981-sgmiisys_0
++          - mediatek,mt7981-sgmiisys_1
+           - mediatek,mt7986-sgmiisys_0
+           - mediatek,mt7986-sgmiisys_1
+       - const: syscon
+@@ -29,6 +31,10 @@ properties:
+   '#clock-cells':
+     const: 1
+ 
++  mediatek,pnswap:
++    description: Invert polarity of the SGMII data lanes
++    type: boolean
++
+ required:
+   - compatible
+   - reg
diff --git a/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch b/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch
new file mode 100644
index 0000000000..946db82235
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch
@@ -0,0 +1,113 @@
+From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sun, 19 Nov 2023 22:24:16 +0100
+Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
+ to DT schema
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DT schema helps validating DTS files. Binding was moved to clock/ as
+this hardware is a clock provider. Example required a small fix for
+"reg" value (1 address cell + 1 size cell).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
+ .../bindings/clock/mediatek,ethsys.yaml       | 54 +++++++++++++++++++
+ 2 files changed, 54 insertions(+), 29 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
++++ /dev/null
+@@ -1,29 +0,0 @@
+-Mediatek ethsys controller
+-============================
+-
+-The Mediatek ethsys controller provides various clocks to the system.
+-
+-Required Properties:
+-
+-- compatible: Should be:
+-	- "mediatek,mt2701-ethsys", "syscon"
+-	- "mediatek,mt7622-ethsys", "syscon"
+-	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+-	- "mediatek,mt7629-ethsys", "syscon"
+-	- "mediatek,mt7981-ethsys", "syscon"
+-	- "mediatek,mt7986-ethsys", "syscon"
+-- #clock-cells: Must be 1
+-- #reset-cells: Must be 1
+-
+-The ethsys controller uses the common clk binding from
+-Documentation/devicetree/bindings/clock/clock-bindings.txt
+-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+-
+-Example:
+-
+-ethsys: clock-controller@1b000000 {
+-	compatible = "mediatek,mt2701-ethsys", "syscon";
+-	reg = <0 0x1b000000 0 0x1000>;
+-	#clock-cells = <1>;
+-	#reset-cells = <1>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -0,0 +1,54 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Mediatek ethsys controller
++
++description:
++  The available clocks are defined in dt-bindings/clock/mt*-clk.h.
++
++maintainers:
++  - James Liao <jamesjj.liao@mediatek.com>
++
++properties:
++  compatible:
++    oneOf:
++      - items:
++          - enum:
++              - mediatek,mt2701-ethsys
++              - mediatek,mt7622-ethsys
++              - mediatek,mt7629-ethsys
++              - mediatek,mt7981-ethsys
++              - mediatek,mt7986-ethsys
++          - const: syscon
++      - items:
++          - const: mediatek,mt7623-ethsys
++          - const: mediatek,mt2701-ethsys
++          - const: syscon
++
++  reg:
++    maxItems: 1
++
++  "#clock-cells":
++    const: 1
++
++  "#reset-cells":
++    const: 1
++
++required:
++  - reg
++  - "#clock-cells"
++  - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    clock-controller@1b000000 {
++        compatible = "mediatek,mt2701-ethsys", "syscon";
++        reg = <0x1b000000 0x1000>;
++        #clock-cells = <1>;
++        #reset-cells = <1>;
++    };
diff --git a/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch b/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch
new file mode 100644
index 0000000000..47f05e93c6
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch
@@ -0,0 +1,35 @@
+From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 17 Dec 2023 21:49:45 +0000
+Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
+ IDs
+
+Add reset ID for ethwarp subsystem allowing to reset the built-in
+Ethernet switch of the MediaTek MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+ create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
++#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
++
++/* ETHWARP resets */
++#define MT7988_ETHWARP_RST_SWITCH		0
++
++#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
diff --git a/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch b/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch
new file mode 100644
index 0000000000..cf5cae6341
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch
@@ -0,0 +1,302 @@
+From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:49:33 +0000
+Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
+
+Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
+ethernet and xfipll subsystem clocks.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../dt-bindings/clock/mediatek,mt7988-clk.h   | 280 ++++++++++++++++++
+ 1 file changed, 280 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
+@@ -0,0 +1,280 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT7988_H
++#define _DT_BINDINGS_CLK_MT7988_H
++
++/* APMIXEDSYS */
++
++#define CLK_APMIXED_NETSYSPLL			0
++#define CLK_APMIXED_MPLL			1
++#define CLK_APMIXED_MMPLL			2
++#define CLK_APMIXED_APLL2			3
++#define CLK_APMIXED_NET1PLL			4
++#define CLK_APMIXED_NET2PLL			5
++#define CLK_APMIXED_WEDMCUPLL			6
++#define CLK_APMIXED_SGMPLL			7
++#define CLK_APMIXED_ARM_B			8
++#define CLK_APMIXED_CCIPLL2_B			9
++#define CLK_APMIXED_USXGMIIPLL			10
++#define CLK_APMIXED_MSDCPLL			11
++
++/* TOPCKGEN */
++
++#define CLK_TOP_XTAL				0
++#define CLK_TOP_XTAL_D2				1
++#define CLK_TOP_RTC_32K				2
++#define CLK_TOP_RTC_32P7K			3
++#define CLK_TOP_MPLL_D2				4
++#define CLK_TOP_MPLL_D3_D2			5
++#define CLK_TOP_MPLL_D4				6
++#define CLK_TOP_MPLL_D8				7
++#define CLK_TOP_MPLL_D8_D2			8
++#define CLK_TOP_MMPLL_D2			9
++#define CLK_TOP_MMPLL_D3_D5			10
++#define CLK_TOP_MMPLL_D4			11
++#define CLK_TOP_MMPLL_D6_D2			12
++#define CLK_TOP_MMPLL_D8			13
++#define CLK_TOP_APLL2_D4			14
++#define CLK_TOP_NET1PLL_D4			15
++#define CLK_TOP_NET1PLL_D5			16
++#define CLK_TOP_NET1PLL_D5_D2			17
++#define CLK_TOP_NET1PLL_D5_D4			18
++#define CLK_TOP_NET1PLL_D8			19
++#define CLK_TOP_NET1PLL_D8_D2			20
++#define CLK_TOP_NET1PLL_D8_D4			21
++#define CLK_TOP_NET1PLL_D8_D8			22
++#define CLK_TOP_NET1PLL_D8_D16			23
++#define CLK_TOP_NET2PLL_D2			24
++#define CLK_TOP_NET2PLL_D4			25
++#define CLK_TOP_NET2PLL_D4_D4			26
++#define CLK_TOP_NET2PLL_D4_D8			27
++#define CLK_TOP_NET2PLL_D6			28
++#define CLK_TOP_NET2PLL_D8			29
++#define CLK_TOP_NETSYS_SEL			30
++#define CLK_TOP_NETSYS_500M_SEL			31
++#define CLK_TOP_NETSYS_2X_SEL			32
++#define CLK_TOP_NETSYS_GSW_SEL			33
++#define CLK_TOP_ETH_GMII_SEL			34
++#define CLK_TOP_NETSYS_MCU_SEL			35
++#define CLK_TOP_NETSYS_PAO_2X_SEL		36
++#define CLK_TOP_EIP197_SEL			37
++#define CLK_TOP_AXI_INFRA_SEL			38
++#define CLK_TOP_UART_SEL			39
++#define CLK_TOP_EMMC_250M_SEL			40
++#define CLK_TOP_EMMC_400M_SEL			41
++#define CLK_TOP_SPI_SEL				42
++#define CLK_TOP_SPIM_MST_SEL			43
++#define CLK_TOP_NFI1X_SEL			44
++#define CLK_TOP_SPINFI_SEL			45
++#define CLK_TOP_PWM_SEL				46
++#define CLK_TOP_I2C_SEL				47
++#define CLK_TOP_PCIE_MBIST_250M_SEL		48
++#define CLK_TOP_PEXTP_TL_SEL			49
++#define CLK_TOP_PEXTP_TL_P1_SEL			50
++#define CLK_TOP_PEXTP_TL_P2_SEL			51
++#define CLK_TOP_PEXTP_TL_P3_SEL			52
++#define CLK_TOP_USB_SYS_SEL			53
++#define CLK_TOP_USB_SYS_P1_SEL			54
++#define CLK_TOP_USB_XHCI_SEL			55
++#define CLK_TOP_USB_XHCI_P1_SEL			56
++#define CLK_TOP_USB_FRMCNT_SEL			57
++#define CLK_TOP_USB_FRMCNT_P1_SEL		58
++#define CLK_TOP_AUD_SEL				59
++#define CLK_TOP_A1SYS_SEL			60
++#define CLK_TOP_AUD_L_SEL			61
++#define CLK_TOP_A_TUNER_SEL			62
++#define CLK_TOP_SSPXTP_SEL			63
++#define CLK_TOP_USB_PHY_SEL			64
++#define CLK_TOP_USXGMII_SBUS_0_SEL		65
++#define CLK_TOP_USXGMII_SBUS_1_SEL		66
++#define CLK_TOP_SGM_0_SEL			67
++#define CLK_TOP_SGM_SBUS_0_SEL			68
++#define CLK_TOP_SGM_1_SEL			69
++#define CLK_TOP_SGM_SBUS_1_SEL			70
++#define CLK_TOP_XFI_PHY_0_XTAL_SEL		71
++#define CLK_TOP_XFI_PHY_1_XTAL_SEL		72
++#define CLK_TOP_SYSAXI_SEL			73
++#define CLK_TOP_SYSAPB_SEL			74
++#define CLK_TOP_ETH_REFCK_50M_SEL		75
++#define CLK_TOP_ETH_SYS_200M_SEL		76
++#define CLK_TOP_ETH_SYS_SEL			77
++#define CLK_TOP_ETH_XGMII_SEL			78
++#define CLK_TOP_BUS_TOPS_SEL			79
++#define CLK_TOP_NPU_TOPS_SEL			80
++#define CLK_TOP_DRAMC_SEL			81
++#define CLK_TOP_DRAMC_MD32_SEL			82
++#define CLK_TOP_INFRA_F26M_SEL			83
++#define CLK_TOP_PEXTP_P0_SEL			84
++#define CLK_TOP_PEXTP_P1_SEL			85
++#define CLK_TOP_PEXTP_P2_SEL			86
++#define CLK_TOP_PEXTP_P3_SEL			87
++#define CLK_TOP_DA_XTP_GLB_P0_SEL		88
++#define CLK_TOP_DA_XTP_GLB_P1_SEL		89
++#define CLK_TOP_DA_XTP_GLB_P2_SEL		90
++#define CLK_TOP_DA_XTP_GLB_P3_SEL		91
++#define CLK_TOP_CKM_SEL				92
++#define CLK_TOP_DA_SEL				93
++#define CLK_TOP_PEXTP_SEL			94
++#define CLK_TOP_TOPS_P2_26M_SEL			95
++#define CLK_TOP_MCUSYS_BACKUP_625M_SEL		96
++#define CLK_TOP_NETSYS_SYNC_250M_SEL		97
++#define CLK_TOP_MACSEC_SEL			98
++#define CLK_TOP_NETSYS_TOPS_400M_SEL		99
++#define CLK_TOP_NETSYS_PPEFB_250M_SEL		100
++#define CLK_TOP_NETSYS_WARP_SEL			101
++#define CLK_TOP_ETH_MII_SEL			102
++#define CLK_TOP_NPU_SEL				103
++#define CLK_TOP_AUD_I2S_M			104
++
++/* MCUSYS */
++
++#define CLK_MCU_BUS_DIV_SEL			0
++#define CLK_MCU_ARM_DIV_SEL			1
++
++/* INFRACFG_AO */
++
++#define CLK_INFRA_MUX_UART0_SEL			0
++#define CLK_INFRA_MUX_UART1_SEL			1
++#define CLK_INFRA_MUX_UART2_SEL			2
++#define CLK_INFRA_MUX_SPI0_SEL			3
++#define CLK_INFRA_MUX_SPI1_SEL			4
++#define CLK_INFRA_MUX_SPI2_SEL			5
++#define CLK_INFRA_PWM_SEL			6
++#define CLK_INFRA_PWM_CK1_SEL			7
++#define CLK_INFRA_PWM_CK2_SEL			8
++#define CLK_INFRA_PWM_CK3_SEL			9
++#define CLK_INFRA_PWM_CK4_SEL			10
++#define CLK_INFRA_PWM_CK5_SEL			11
++#define CLK_INFRA_PWM_CK6_SEL			12
++#define CLK_INFRA_PWM_CK7_SEL			13
++#define CLK_INFRA_PWM_CK8_SEL			14
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL	15
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL	16
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL	17
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL	18
++
++/* INFRACFG */
++
++#define CLK_INFRA_PCIE_PERI_26M_CK_P0		19
++#define CLK_INFRA_PCIE_PERI_26M_CK_P1		20
++#define CLK_INFRA_PCIE_PERI_26M_CK_P2		21
++#define CLK_INFRA_PCIE_PERI_26M_CK_P3		22
++#define CLK_INFRA_66M_GPT_BCK			23
++#define CLK_INFRA_66M_PWM_HCK			24
++#define CLK_INFRA_66M_PWM_BCK			25
++#define CLK_INFRA_66M_PWM_CK1			26
++#define CLK_INFRA_66M_PWM_CK2			27
++#define CLK_INFRA_66M_PWM_CK3			28
++#define CLK_INFRA_66M_PWM_CK4			29
++#define CLK_INFRA_66M_PWM_CK5			30
++#define CLK_INFRA_66M_PWM_CK6			31
++#define CLK_INFRA_66M_PWM_CK7			32
++#define CLK_INFRA_66M_PWM_CK8			33
++#define CLK_INFRA_133M_CQDMA_BCK		34
++#define CLK_INFRA_66M_AUD_SLV_BCK		35
++#define CLK_INFRA_AUD_26M			36
++#define CLK_INFRA_AUD_L				37
++#define CLK_INFRA_AUD_AUD			38
++#define CLK_INFRA_AUD_EG2			39
++#define CLK_INFRA_DRAMC_F26M			40
++#define CLK_INFRA_133M_DBG_ACKM			41
++#define CLK_INFRA_66M_AP_DMA_BCK		42
++#define CLK_INFRA_66M_SEJ_BCK			43
++#define CLK_INFRA_PRE_CK_SEJ_F13M		44
++#define CLK_INFRA_26M_THERM_SYSTEM		45
++#define CLK_INFRA_I2C_BCK			46
++#define CLK_INFRA_52M_UART0_CK			47
++#define CLK_INFRA_52M_UART1_CK			48
++#define CLK_INFRA_52M_UART2_CK			49
++#define CLK_INFRA_NFI				50
++#define CLK_INFRA_SPINFI			51
++#define CLK_INFRA_66M_NFI_HCK			52
++#define CLK_INFRA_104M_SPI0			53
++#define CLK_INFRA_104M_SPI1			54
++#define CLK_INFRA_104M_SPI2_BCK			55
++#define CLK_INFRA_66M_SPI0_HCK			56
++#define CLK_INFRA_66M_SPI1_HCK			57
++#define CLK_INFRA_66M_SPI2_HCK			58
++#define CLK_INFRA_66M_FLASHIF_AXI		59
++#define CLK_INFRA_RTC				60
++#define CLK_INFRA_26M_ADC_BCK			61
++#define CLK_INFRA_RC_ADC			62
++#define CLK_INFRA_MSDC400			63
++#define CLK_INFRA_MSDC2_HCK			64
++#define CLK_INFRA_133M_MSDC_0_HCK		65
++#define CLK_INFRA_66M_MSDC_0_HCK		66
++#define CLK_INFRA_133M_CPUM_BCK			67
++#define CLK_INFRA_BIST2FPC			68
++#define CLK_INFRA_I2C_X16W_MCK_CK_P1		69
++#define CLK_INFRA_I2C_X16W_PCK_CK_P1		70
++#define CLK_INFRA_133M_USB_HCK			71
++#define CLK_INFRA_133M_USB_HCK_CK_P1		72
++#define CLK_INFRA_66M_USB_HCK			73
++#define CLK_INFRA_66M_USB_HCK_CK_P1		74
++#define CLK_INFRA_USB_SYS			75
++#define CLK_INFRA_USB_SYS_CK_P1			76
++#define CLK_INFRA_USB_REF			77
++#define CLK_INFRA_USB_CK_P1			78
++#define CLK_INFRA_USB_FRMCNT			79
++#define CLK_INFRA_USB_FRMCNT_CK_P1		80
++#define CLK_INFRA_USB_PIPE			81
++#define CLK_INFRA_USB_PIPE_CK_P1		82
++#define CLK_INFRA_USB_UTMI			83
++#define CLK_INFRA_USB_UTMI_CK_P1		84
++#define CLK_INFRA_USB_XHCI			85
++#define CLK_INFRA_USB_XHCI_CK_P1		86
++#define CLK_INFRA_PCIE_GFMUX_TL_P0		87
++#define CLK_INFRA_PCIE_GFMUX_TL_P1		88
++#define CLK_INFRA_PCIE_GFMUX_TL_P2		89
++#define CLK_INFRA_PCIE_GFMUX_TL_P3		90
++#define CLK_INFRA_PCIE_PIPE_P0			91
++#define CLK_INFRA_PCIE_PIPE_P1			92
++#define CLK_INFRA_PCIE_PIPE_P2			93
++#define CLK_INFRA_PCIE_PIPE_P3			94
++#define CLK_INFRA_133M_PCIE_CK_P0		95
++#define CLK_INFRA_133M_PCIE_CK_P1		96
++#define CLK_INFRA_133M_PCIE_CK_P2		97
++#define CLK_INFRA_133M_PCIE_CK_P3		98
++
++/* ETHDMA */
++
++#define CLK_ETHDMA_XGP1_EN			0
++#define CLK_ETHDMA_XGP2_EN			1
++#define CLK_ETHDMA_XGP3_EN			2
++#define CLK_ETHDMA_FE_EN			3
++#define CLK_ETHDMA_GP2_EN			4
++#define CLK_ETHDMA_GP1_EN			5
++#define CLK_ETHDMA_GP3_EN			6
++#define CLK_ETHDMA_ESW_EN			7
++#define CLK_ETHDMA_CRYPT0_EN			8
++#define CLK_ETHDMA_NR_CLK			9
++
++/* SGMIISYS_0 */
++
++#define CLK_SGM0_TX_EN				0
++#define CLK_SGM0_RX_EN				1
++#define CLK_SGMII0_NR_CLK			2
++
++/* SGMIISYS_1 */
++
++#define CLK_SGM1_TX_EN				0
++#define CLK_SGM1_RX_EN				1
++#define CLK_SGMII1_NR_CLK			2
++
++/* ETHWARP */
++
++#define CLK_ETHWARP_WOCPU2_EN			0
++#define CLK_ETHWARP_WOCPU1_EN			1
++#define CLK_ETHWARP_WOCPU0_EN			2
++#define CLK_ETHWARP_NR_CLK			3
++
++/* XFIPLL */
++#define CLK_XFIPLL_PLL				0
++#define CLK_XFIPLL_PLL_EN			1
++
++#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch b/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch
new file mode 100644
index 0000000000..79088b461b
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch
@@ -0,0 +1,260 @@
+From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 17 Dec 2023 21:49:55 +0000
+Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
+ MT7988
+
+Add various clock controllers found in the MT7988 SoC to existing
+bindings (if applicable) and add files for the new ethwarp, mcusys
+and xfi-pll clock controllers not previously present in any SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../arm/mediatek/mediatek,infracfg.yaml       |  1 +
+ .../bindings/clock/mediatek,apmixedsys.yaml   |  1 +
+ .../bindings/clock/mediatek,ethsys.yaml       |  1 +
+ .../clock/mediatek,mt7988-ethwarp.yaml        | 52 +++++++++++++++
+ .../clock/mediatek,mt7988-xfi-pll.yaml        | 48 ++++++++++++++
+ .../bindings/clock/mediatek,topckgen.yaml     |  2 +
+ .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 65 ++++++++++++++++---
+ 7 files changed, 161 insertions(+), 9 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+@@ -30,6 +30,7 @@ properties:
+               - mediatek,mt7629-infracfg
+               - mediatek,mt7981-infracfg
+               - mediatek,mt7986-infracfg
++              - mediatek,mt7988-infracfg
+               - mediatek,mt8135-infracfg
+               - mediatek,mt8167-infracfg
+               - mediatek,mt8173-infracfg
+--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+@@ -22,6 +22,7 @@ properties:
+           - mediatek,mt7622-apmixedsys
+           - mediatek,mt7981-apmixedsys
+           - mediatek,mt7986-apmixedsys
++          - mediatek,mt7988-apmixedsys
+           - mediatek,mt8135-apmixedsys
+           - mediatek,mt8173-apmixedsys
+           - mediatek,mt8516-apmixedsys
+--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -22,6 +22,7 @@ properties:
+               - mediatek,mt7629-ethsys
+               - mediatek,mt7981-ethsys
+               - mediatek,mt7986-ethsys
++              - mediatek,mt7988-ethsys
+           - const: syscon
+       - items:
+           - const: mediatek,mt7623-ethsys
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+@@ -0,0 +1,52 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 ethwarp Controller
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The Mediatek MT7988 ethwarp controller provides clocks and resets for the
++  Ethernet related subsystems found the MT7988 SoC.
++  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
++
++properties:
++  compatible:
++    items:
++      - const: mediatek,mt7988-ethwarp
++
++  reg:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++  '#reset-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#clock-cells'
++  - '#reset-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/reset/ti-syscon.h>
++    soc {
++        #address-cells = <2>;
++        #size-cells = <2>;
++
++        clock-controller@15031000 {
++            compatible = "mediatek,mt7988-ethwarp";
++            reg = <0 0x15031000 0 0x1000>;
++            #clock-cells = <1>;
++            #reset-cells = <1>;
++        };
++    };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+@@ -0,0 +1,48 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 XFI PLL Clock Controller
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek XFI PLL controller provides the 156.25MHz clock for the
++  Ethernet SerDes PHY from the 40MHz top_xtal clock.
++
++properties:
++  compatible:
++    const: mediatek,mt7988-xfi-pll
++
++  reg:
++    maxItems: 1
++
++  resets:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - resets
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    soc {
++        #address-cells = <2>;
++        #size-cells = <2>;
++        clock-controller@11f40000 {
++            compatible = "mediatek,mt7988-xfi-pll";
++            reg = <0 0x11f40000 0 0x1000>;
++            resets = <&watchdog 16>;
++            #clock-cells = <1>;
++        };
++    };
+--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+@@ -37,6 +37,8 @@ properties:
+               - mediatek,mt7629-topckgen
+               - mediatek,mt7981-topckgen
+               - mediatek,mt7986-topckgen
++              - mediatek,mt7988-mcusys
++              - mediatek,mt7988-topckgen
+               - mediatek,mt8167-topckgen
+               - mediatek,mt8183-topckgen
+           - const: syscon
+--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -15,15 +15,22 @@ description:
+ 
+ properties:
+   compatible:
+-    items:
+-      - enum:
+-          - mediatek,mt7622-sgmiisys
+-          - mediatek,mt7629-sgmiisys
+-          - mediatek,mt7981-sgmiisys_0
+-          - mediatek,mt7981-sgmiisys_1
+-          - mediatek,mt7986-sgmiisys_0
+-          - mediatek,mt7986-sgmiisys_1
+-      - const: syscon
++    oneOf:
++      - items:
++          - enum:
++              - mediatek,mt7622-sgmiisys
++              - mediatek,mt7629-sgmiisys
++              - mediatek,mt7981-sgmiisys_0
++              - mediatek,mt7981-sgmiisys_1
++              - mediatek,mt7986-sgmiisys_0
++              - mediatek,mt7986-sgmiisys_1
++          - const: syscon
++      - items:
++          - enum:
++              - mediatek,mt7988-sgmiisys0
++              - mediatek,mt7988-sgmiisys1
++          - const: simple-mfd
++          - const: syscon
+ 
+   reg:
+     maxItems: 1
+@@ -35,11 +42,51 @@ properties:
+     description: Invert polarity of the SGMII data lanes
+     type: boolean
+ 
++  pcs:
++    type: object
++    description: MediaTek LynxI HSGMII PCS
++    properties:
++      compatible:
++        const: mediatek,mt7988-sgmii
++
++      clocks:
++        maxItems: 3
++
++      clock-names:
++        items:
++          - const: sgmii_sel
++          - const: sgmii_tx
++          - const: sgmii_rx
++
++    required:
++      - compatible
++      - clocks
++      - clock-names
++
++    additionalProperties: false
++
+ required:
+   - compatible
+   - reg
+   - '#clock-cells'
+ 
++allOf:
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - mediatek,mt7988-sgmiisys0
++              - mediatek,mt7988-sgmiisys1
++
++    then:
++      required:
++        - pcs
++
++    else:
++      properties:
++        pcs: false
++
+ additionalProperties: false
+ 
+ examples:
diff --git a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch b/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
new file mode 100644
index 0000000000..ca37fc793a
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
@@ -0,0 +1,50 @@
+From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:50:07 +0000
+Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
+
+Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
+of the previously hardcoded PCW_CHG_MASK macro if set.
+This will needed for clocks on the MT7988 SoC.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-pll.c | 5 +++--
+ drivers/clk/mediatek/clk-pll.h | 1 +
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-pll.c
++++ b/drivers/clk/mediatek/clk-pll.c
+@@ -23,7 +23,7 @@
+ #define CON0_BASE_EN		BIT(0)
+ #define CON0_PWR_ON		BIT(0)
+ #define CON0_ISO_EN		BIT(1)
+-#define PCW_CHG_MASK		BIT(31)
++#define PCW_CHG_BIT		31
+ 
+ #define AUDPLL_TUNER_EN		BIT(31)
+ 
+@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct
+ 			pll->data->pcw_shift);
+ 	val |= pcw << pll->data->pcw_shift;
+ 	writel(val, pll->pcw_addr);
+-	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
++	chg = readl(pll->pcw_chg_addr) |
++	      BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
+ 	writel(chg, pll->pcw_chg_addr);
+ 	if (pll->tuner_addr)
+ 		writel(val + 1, pll->tuner_addr);
+--- a/drivers/clk/mediatek/clk-pll.h
++++ b/drivers/clk/mediatek/clk-pll.h
+@@ -46,6 +46,7 @@ struct mtk_pll_data {
+ 	const char *parent_name;
+ 	u32 en_reg;
+ 	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
++	u8 pcw_chg_bit;
+ };
+ 
+ int mtk_clk_register_plls(struct device_node *node,
diff --git a/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch
new file mode 100644
index 0000000000..61664b934c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch
@@ -0,0 +1,1026 @@
+From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 17 Dec 2023 21:50:15 +0000
+Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC
+
+Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
+typical MediaTek designs.
+
+Also add driver for XFIPLL clock generating the 156.25MHz clock for
+the XFI SerDes. It needs an undocumented software workaround and has
+an unknown internal design.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
+[sboyd@kernel.org: Add module license to infracfg file]
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/Kconfig               |   9 +
+ drivers/clk/mediatek/Makefile              |   5 +
+ drivers/clk/mediatek/clk-mt7988-apmixed.c  | 114 ++++++++
+ drivers/clk/mediatek/clk-mt7988-eth.c      | 150 ++++++++++
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-xfipll.c   |  82 ++++++
+ 7 files changed, 960 insertions(+)
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c
+
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
+ 	  This driver adds support for clocks for Ethernet and SGMII
+ 	  required on MediaTek MT7986 SoC.
+ 
++config COMMON_CLK_MT7988
++	tristate "Clock driver for MediaTek MT7988"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	select COMMON_CLK_MEDIATEK
++	default ARCH_MEDIATEK
++	help
++	  This driver supports MediaTek MT7988 basic clocks and clocks
++	  required for various periperals found on this SoC.
++
+ config COMMON_CLK_MT8135
+ 	bool "Clock driver for MediaTek MT8135"
+ 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
+ obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+ obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
+ obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include "clk-pll.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++#define MT7988_PLL_FMAX (2500UL * MHZ)
++#define MT7988_PCW_CHG_BIT 2
++
++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg,	\
++	    _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift,		\
++	    _pcw_chg_reg)									\
++	{											\
++		.id = _id,									\
++		.name = _name,									\
++		.reg = _reg,									\
++		.pwr_reg = _pwr_reg,								\
++		.en_mask = _en_mask,								\
++		.flags = _flags,								\
++		.rst_bar_mask = BIT(_rst_bar_mask),						\
++		.fmax = MT7988_PLL_FMAX,							\
++		.pcwbits = _pcwbits,								\
++		.pd_reg = _pd_reg,								\
++		.pd_shift = _pd_shift,								\
++		.tuner_reg = _tuner_reg,							\
++		.tuner_en_reg = _tuner_en_reg,							\
++		.tuner_en_bit = _tuner_en_bit,							\
++		.pcw_reg = _pcw_reg,								\
++		.pcw_shift = _pcw_shift,							\
++		.pcw_chg_reg = _pcw_chg_reg,							\
++		.pcw_chg_bit = MT7988_PCW_CHG_BIT,						\
++		.parent_name = "clkxtal",							\
++	}
++
++static const struct mtk_pll_data plls[] = {
++	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
++	    0, 0, 0x0108, 0, 0x0104),
++	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
++	    0, 0, 0, 0x0118, 0, 0x0114),
++	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
++	    0, 0, 0, 0x0128, 0, 0x0124),
++	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
++	    0x0700, 1, 0x0138, 0, 0x0134),
++	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
++	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
++	    32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
++	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
++	    0, 0, 0x0168, 0, 0x0164),
++	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
++	    0x0178, 0, 0x0174),
++	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
++	    0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
++	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
++	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
++	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
++	    0, 0x0318, 0, 0x0314),
++};
++
++static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
++	{ .compatible = "mediatek,mt7988-apmixedsys" },
++	{ /* sentinel */ }
++};
++
++static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
++{
++	struct clk_hw_onecell_data *clk_data;
++	struct device_node *node = pdev->dev.of_node;
++	int r;
++
++	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
++	if (!clk_data)
++		return -ENOMEM;
++
++	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
++	if (r)
++		goto free_apmixed_data;
++
++	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	if (r)
++		goto unregister_plls;
++
++	return r;
++
++unregister_plls:
++	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
++free_apmixed_data:
++	mtk_free_clk_data(clk_data);
++	return r;
++}
++
++static struct platform_driver clk_mt7988_apmixed_drv = {
++	.probe = clk_mt7988_apmixed_probe,
++	.driver = {
++		.name = "clk-mt7988-apmixed",
++		.of_match_table = of_match_clk_mt7988_apmixed,
++	},
++};
++builtin_platform_driver(clk_mt7988_apmixed_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-eth.c
+@@ -0,0 +1,150 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "reset.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++static const struct mtk_gate_regs ethdma_cg_regs = {
++	.set_ofs = 0x30,
++	.clr_ofs = 0x30,
++	.sta_ofs = 0x30,
++};
++
++#define GATE_ETHDMA(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &ethdma_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate ethdma_clks[] = {
++	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
++	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
++	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
++	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
++	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
++	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
++	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
++	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
++	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
++};
++
++static const struct mtk_clk_desc ethdma_desc = {
++	.clks = ethdma_clks,
++	.num_clks = ARRAY_SIZE(ethdma_clks),
++};
++
++static const struct mtk_gate_regs sgmii_cg_regs = {
++	.set_ofs = 0xe4,
++	.clr_ofs = 0xe4,
++	.sta_ofs = 0xe4,
++};
++
++#define GATE_SGMII(_id, _name, _parent, _shift)			\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &sgmii_cg_regs,				\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate sgmii0_clks[] = {
++	GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
++	GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii0_desc = {
++	.clks = sgmii0_clks,
++	.num_clks = ARRAY_SIZE(sgmii0_clks),
++};
++
++static const struct mtk_gate sgmii1_clks[] = {
++	GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
++	GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii1_desc = {
++	.clks = sgmii1_clks,
++	.num_clks = ARRAY_SIZE(sgmii1_clks),
++};
++
++static const struct mtk_gate_regs ethwarp_cg_regs = {
++	.set_ofs = 0x14,
++	.clr_ofs = 0x14,
++	.sta_ofs = 0x14,
++};
++
++#define GATE_ETHWARP(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &ethwarp_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate ethwarp_clks[] = {
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
++};
++
++static u16 ethwarp_rst_ofs[] = { 0x8 };
++
++static u16 ethwarp_idx_map[] = {
++	[MT7988_ETHWARP_RST_SWITCH] = 9,
++};
++
++static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
++	.version = MTK_RST_SIMPLE,
++	.rst_bank_ofs = ethwarp_rst_ofs,
++	.rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
++	.rst_idx_map = ethwarp_idx_map,
++	.rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
++};
++
++static const struct mtk_clk_desc ethwarp_desc = {
++	.clks = ethwarp_clks,
++	.num_clks = ARRAY_SIZE(ethwarp_clks),
++	.rst_desc = &ethwarp_rst_desc,
++};
++
++static const struct of_device_id of_match_clk_mt7988_eth[] = {
++	{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
++	{ .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
++	{ .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
++	{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
++
++static struct platform_driver clk_mt7988_eth_drv = {
++	.driver = {
++		.name = "clk-mt7988-eth",
++		.of_match_table = of_match_clk_mt7988_eth,
++	},
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_eth_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -0,0 +1,275 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
++
++static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
++
++static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
++								 "csw_infra_f26m_sel", "sysaxi_sel",
++								 "pwm_sel" };
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
++};
++
++static const struct mtk_mux infra_muxes[] = {
++	/* MODULE_CLK_SEL_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
++			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
++			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
++			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
++			     0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
++			     0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
++			     0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
++			     0x0010, 0x0014, 14, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
++	/* MODULE_CLK_SEL_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
++			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
++			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
++			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
++			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
++			     -1, -1),
++};
++
++static const struct mtk_gate_regs infra0_cg_regs = {
++	.set_ofs = 0x10,
++	.clr_ofs = 0x14,
++	.sta_ofs = 0x18,
++};
++
++static const struct mtk_gate_regs infra1_cg_regs = {
++	.set_ofs = 0x40,
++	.clr_ofs = 0x44,
++	.sta_ofs = 0x48,
++};
++
++static const struct mtk_gate_regs infra2_cg_regs = {
++	.set_ofs = 0x50,
++	.clr_ofs = 0x54,
++	.sta_ofs = 0x58,
++};
++
++static const struct mtk_gate_regs infra3_cg_regs = {
++	.set_ofs = 0x60,
++	.clr_ofs = 0x64,
++	.sta_ofs = 0x68,
++};
++
++#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
++
++static const struct mtk_gate infra_clks[] = {
++	/* INFRA0 */
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
++		    "csw_infra_f26m_sel", 7),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
++		    "csw_infra_f26m_sel", 8),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
++		    "csw_infra_f26m_sel", 9),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
++		    "csw_infra_f26m_sel", 10),
++	/* INFRA1 */
++	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
++	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
++	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
++	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
++	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
++	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
++	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
++	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
++			  CLK_IS_CRITICAL),
++	/* JTAG */
++	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
++	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
++	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
++	/* INFRA2 */
++	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
++		    0),
++	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
++	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
++	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
++	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
++	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
++	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
++	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
++	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
++	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
++	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
++	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
++	GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
++	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
++	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
++	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
++	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
++	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
++	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
++	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
++	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
++	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
++	/* INFRA3 */
++	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
++	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
++	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
++	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
++	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
++	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
++	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
++	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
++	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
++			  9, CLK_IS_CRITICAL),
++	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
++	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
++	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
++	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
++	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
++	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
++		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
++		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
++		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
++		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
++};
++
++static const struct mtk_clk_desc infra_desc = {
++	.clks = infra_clks,
++	.num_clks = ARRAY_SIZE(infra_clks),
++	.mux_clks = infra_muxes,
++	.num_mux_clks = ARRAY_SIZE(infra_muxes),
++	.clk_lock = &mt7988_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
++	{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
++
++static struct platform_driver clk_mt7988_infracfg_drv = {
++	.driver = {
++		.name = "clk-mt7988-infracfg",
++		.of_match_table = of_match_clk_mt7988_infracfg,
++	},
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_infracfg_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c
+@@ -0,0 +1,325 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const struct mtk_fixed_clk top_fixed_clks[] = {
++	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
++};
++
++static const struct mtk_fixed_factor top_divs[] = {
++	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
++	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
++	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
++	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
++	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
++	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
++	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
++	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
++	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
++	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
++	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
++	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
++	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
++	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
++	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
++	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
++	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
++	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
++	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
++	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
++	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
++	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
++	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
++	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
++	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
++	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
++	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
++};
++
++static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
++static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
++static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
++static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
++static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
++static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",    "mmpll",
++						  "net1pll_d4", "net1pll_d5", "mpll" };
++static const char *const eip197_parents[] = { "top_xtal", "netsyspll",	"net2pll",
++					      "mmpll",	  "net1pll_d4", "net1pll_d5" };
++static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
++static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
++static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
++static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",	 "mmpll_d2",
++						 "mpll_d2",  "mmpll_d4", "net1pll_d8_d2" };
++static const char *const spi_parents[] = { "top_xtal",	    "mpll_d2",	    "mmpll_d4",
++					   "net1pll_d8_d2", "net2pll_d6",   "net1pll_d5_d4",
++					   "mpll_d4",	    "net1pll_d8_d4" };
++static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
++					     "mpll_d4",	 "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
++static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
++					      "mpll_d4",     "mmpll_d8", "net1pll_d8_d4",
++					      "mmpll_d6_d2", "mpll_d8" };
++static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
++					   "mpll_d4",  "mpll_d8_d2",	"top_rtc_32k" };
++static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
++					   "net1pll_d8_d4" };
++static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
++static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
++						   "mpll_d8_d2", "top_rtc_32k" };
++static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
++static const char *const aud_parents[] = { "top_xtal", "apll2" };
++static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
++static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
++static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
++static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
++static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
++static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
++static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
++static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
++static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
++static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
++static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
++static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
++static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
++static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
++static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
++static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
++static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
++
++static const struct mtk_mux top_muxes[] = {
++	/* CLK_CFG_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
++			     0, 2, 7, 0x1c0, 0),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
++			     0x004, 0x008, 8, 2, 15, 0x1C0, 1),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
++			     0x004, 0x008, 16, 2, 23, 0x1C0, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
++			     0x004, 0x008, 24, 2, 31, 0x1C0, 3),
++	/* CLK_CFG_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
++			     0x018, 0, 1, 7, 0x1C0, 4),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
++			     0x014, 0x018, 8, 3, 15, 0x1C0, 5),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
++			     0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
++			     24, 3, 31, 0x1c0, 7),
++	/* CLK_CFG_2 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
++				   0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
++			     15, 0x1c0, 9),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
++			     0x024, 0x028, 16, 2, 23, 0x1C0, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
++			     0x024, 0x028, 24, 3, 31, 0x1C0, 11),
++	/* CLK_CFG_3 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
++			     0x1c0, 12),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
++			     8, 3, 15, 0x1c0, 13),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
++			     3, 23, 0x1c0, 14),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
++			     24, 3, 31, 0x1c0, 15),
++	/* CLK_CFG_4 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
++			     0x1c0, 16),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
++			     0x1c0, 17),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
++			     pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
++			     0x044, 0x048, 24, 3, 31, 0x1C0, 19),
++	/* CLK_CFG_5 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 0, 3, 7, 0x1C0, 20),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 8, 3, 15, 0x1C0, 21),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 16, 3, 23, 0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
++			     0x058, 24, 1, 31, 0x1C0, 23),
++	/* CLK_CFG_6 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
++			     0x064, 0x068, 0, 1, 7, 0x1C0, 24),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
++			     0x068, 8, 1, 15, 0x1C0, 25),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
++			     0x064, 0x068, 16, 1, 23, 0x1C0, 26),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
++			     0x064, 0x068, 24, 1, 31, 0x1C0, 27),
++	/* CLK_CFG_7 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
++			     0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
++			     0x1c0, 29),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
++			     1, 23, 0x1c0, 30),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
++			     2, 31, 0x1c4, 0),
++	/* CLK_CFG_8 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
++			     0, 1, 7, 0x1c4, 1),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
++			     8, 1, 15, 0x1c4, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
++			     0x088, 16, 1, 23, 0x1c4, 3),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
++			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
++	/* CLK_CFG_9 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
++			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
++			     1, 15, 0x1c4, 6),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
++				   0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
++			     1, 31, 0x1c4, 8),
++	/* CLK_CFG_10 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
++				   0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
++			     0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
++			     0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
++	/* CLK_CFG_11 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
++				   0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
++				   0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
++			     0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
++			     0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
++			     0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
++	/* CLK_CFG_12 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
++			     0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
++			     0x0c8, 8, 2, 15, 0x1C4, 18),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
++			     0x0c8, 16, 1, 23, 0x1C4, 19),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
++				   0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
++	/* CLK_CFG_13 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
++				   0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
++				   0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
++			     0x0d8, 16, 1, 23, 0x1C4, 23),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
++			     0x0d8, 24, 1, 31, 0x1C4, 24),
++	/* CLK_CFG_14 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
++			     0x0e8, 0, 1, 7, 0x1C4, 25),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
++			     0x0e8, 8, 1, 15, 0x1C4, 26),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
++			     0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
++			     0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
++	/* CLK_CFG_15 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
++			     0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
++			     0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
++			     23, 0x1c8, 0),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
++			     31, 0x1C8, 1),
++	/* CLK_CFG_16 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
++			     0, 1, 7, 0x1c8, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
++			     0x104, 0x108, 8, 1, 15, 0x1C8, 3),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
++			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
++			     pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
++	/* CLK_CFG_17 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
++			     0, 2, 7, 0x1c8, 6),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
++			     netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
++			     pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
++			     0x114, 0x118, 24, 2, 31, 0x1C8, 9),
++	/* CLK_CFG_18 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
++			     0x128, 0, 1, 7, 0x1c8, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
++			     8, 2, 15, 0x1c8, 11),
++};
++
++static const struct mtk_composite top_aud_divs[] = {
++	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
++};
++
++static const struct mtk_clk_desc topck_desc = {
++	.fixed_clks = top_fixed_clks,
++	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
++	.factor_clks = top_divs,
++	.num_factor_clks = ARRAY_SIZE(top_divs),
++	.mux_clks = top_muxes,
++	.num_mux_clks = ARRAY_SIZE(top_muxes),
++	.composite_clks = top_aud_divs,
++	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
++	.clk_lock = &mt7988_clk_lock,
++};
++
++static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
++
++static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
++
++static struct mtk_composite mcu_muxes[] = {
++	/* bus_pll_divider_cfg */
++	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
++		       CLK_IS_CRITICAL),
++	/* mp2_pll_divider_cfg */
++	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
++		       CLK_IS_CRITICAL),
++};
++
++static const struct mtk_clk_desc mcusys_desc = {
++	.composite_clks = mcu_muxes,
++	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
++};
++
++static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
++	{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
++	{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
++
++static struct platform_driver clk_mt7988_topckgen_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt7988-topckgen",
++		.of_match_table = of_match_clk_mt7988_topckgen,
++	},
++};
++module_platform_driver(clk_mt7988_topckgen_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++/* Register to control USXGMII XFI PLL analog */
++#define XFI_PLL_ANA_GLB8		0x108
++#define RG_XFI_PLL_ANA_SWWA		0x02283248
++
++static const struct mtk_gate_regs xfipll_cg_regs = {
++	.set_ofs = 0x8,
++	.clr_ofs = 0x8,
++	.sta_ofs = 0x8,
++};
++
++#define GATE_XFIPLL(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &xfipll_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_fixed_factor xfipll_divs[] = {
++	FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
++};
++
++static const struct mtk_gate xfipll_clks[] = {
++	GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
++};
++
++static const struct mtk_clk_desc xfipll_desc = {
++	.clks = xfipll_clks,
++	.num_clks = ARRAY_SIZE(xfipll_clks),
++	.factor_clks = xfipll_divs,
++	.num_factor_clks = ARRAY_SIZE(xfipll_divs),
++};
++
++static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
++{
++	struct device_node *node = pdev->dev.of_node;
++	void __iomem *base = of_iomap(node, 0);
++
++	if (!base)
++		return -ENOMEM;
++
++	/* Apply software workaround for USXGMII PLL TCL issue */
++	writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
++	iounmap(base);
++
++	return mtk_clk_simple_probe(pdev);
++};
++
++static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
++	{ .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
++
++static struct platform_driver clk_mt7988_xfipll_drv = {
++	.driver = {
++		.name = "clk-mt7988-xfipll",
++		.of_match_table = of_match_clk_mt7988_xfipll,
++	},
++	.probe = clk_mt7988_xfipll_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_xfipll_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch b/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch
new file mode 100644
index 0000000000..cecf095e92
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch
@@ -0,0 +1,57 @@
+From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 17 Jan 2024 19:41:11 +0100
+Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
+
+Infracfg can also operate as reset controller, add support for it.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -14,6 +14,10 @@
+ #include "clk-gate.h"
+ #include "clk-mux.h"
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++#define	MT7988_INFRA_RST0_SET_OFFSET	0x70
++#define	MT7988_INFRA_RST1_SET_OFFSET	0x80
+ 
+ static DEFINE_SPINLOCK(mt7988_clk_lock);
+ 
+@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
+ 	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
+ };
+ 
++static u16 infra_rst_ofs[] = {
++	MT7988_INFRA_RST0_SET_OFFSET,
++	MT7988_INFRA_RST1_SET_OFFSET,
++};
++
++static u16 infra_idx_map[] = {
++	[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
++	[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
++};
++
++static struct mtk_clk_rst_desc infra_rst_desc = {
++	.version = MTK_RST_SET_CLR,
++	.rst_bank_ofs = infra_rst_ofs,
++	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
++	.rst_idx_map = infra_idx_map,
++	.rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
++};
++
+ static const struct mtk_clk_desc infra_desc = {
+ 	.clks = infra_clks,
+ 	.num_clks = ARRAY_SIZE(infra_clks),
+ 	.mux_clks = infra_muxes,
+ 	.num_mux_clks = ARRAY_SIZE(infra_muxes),
+ 	.clk_lock = &mt7988_clk_lock,
++	.rst_desc = &infra_rst_desc,
+ };
+ 
+ static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
diff --git a/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch b/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch
new file mode 100644
index 0000000000..d353074e84
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch
@@ -0,0 +1,25 @@
+From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 17 Jan 2024 19:41:10 +0100
+Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
+
+Add reset constants for using as index in driver and dts.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -10,4 +10,10 @@
+ /* ETHWARP resets */
+ #define MT7988_ETHWARP_RST_SWITCH		0
+ 
++/* INFRA resets */
++#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST	0
++#define MT7988_INFRA_RST1_THERM_CTRL_SWRST	1
++
++
+ #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
++
diff --git a/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch b/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch
new file mode 100644
index 0000000000..cb49ce1d25
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch
@@ -0,0 +1,125 @@
+From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 20 Nov 2023 18:22:31 +0000
+Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
+
+Add support for watchdog and reset generator unit of the MediaTek
+MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+--- a/drivers/watchdog/mtk_wdt.c
++++ b/drivers/watchdog/mtk_wdt.c
+@@ -56,9 +56,13 @@
+ #define WDT_SWSYSRST		0x18U
+ #define WDT_SWSYS_RST_KEY	0x88000000
+ 
++#define WDT_SWSYSRST_EN		0xfc
++
+ #define DRV_NAME		"mtk-wdt"
+ #define DRV_VERSION		"1.0"
+ 
++#define MT7988_TOPRGU_SW_RST_NUM	24
++
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+ static unsigned int timeout;
+ 
+@@ -68,10 +72,12 @@ struct mtk_wdt_dev {
+ 	spinlock_t lock; /* protects WDT_SWSYSRST reg */
+ 	struct reset_controller_dev rcdev;
+ 	bool disable_wdt_extrst;
++	bool has_swsysrst_en;
+ };
+ 
+ struct mtk_wdt_data {
+ 	int toprgu_sw_rst_num;
++	bool has_swsysrst_en;
+ };
+ 
+ static const struct mtk_wdt_data mt2712_data = {
+@@ -82,6 +88,11 @@ static const struct mtk_wdt_data mt7986_
+ 	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
+ };
+ 
++static const struct mtk_wdt_data mt7988_data = {
++	.toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
++	.has_swsysrst_en = true,
++};
++
+ static const struct mtk_wdt_data mt8183_data = {
+ 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
+ };
+@@ -98,6 +109,28 @@ static const struct mtk_wdt_data mt8195_
+ 	.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
+ };
+ 
++/**
++ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
++ * @data: Pointer to instance of driver data.
++ * @id: Bit number identifying the reset to be enabled or disabled.
++ * @enable: If true, enable software control for that bit, disable otherwise.
++ *
++ * Context: The caller must hold lock of struct mtk_wdt_dev.
++ */
++static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
++					unsigned long id, bool enable)
++{
++	u32 tmp;
++
++	tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
++	if (enable)
++		tmp |= BIT(id);
++	else
++		tmp &= ~BIT(id);
++
++	writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
++}
++
+ static int toprgu_reset_update(struct reset_controller_dev *rcdev,
+ 			       unsigned long id, bool assert)
+ {
+@@ -108,6 +141,9 @@ static int toprgu_reset_update(struct re
+ 
+ 	spin_lock_irqsave(&data->lock, flags);
+ 
++	if (assert && data->has_swsysrst_en)
++		toprgu_reset_sw_en_unlocked(data, id, true);
++
+ 	tmp = readl(data->wdt_base + WDT_SWSYSRST);
+ 	if (assert)
+ 		tmp |= BIT(id);
+@@ -116,6 +152,9 @@ static int toprgu_reset_update(struct re
+ 	tmp |= WDT_SWSYS_RST_KEY;
+ 	writel(tmp, data->wdt_base + WDT_SWSYSRST);
+ 
++	if (!assert && data->has_swsysrst_en)
++		toprgu_reset_sw_en_unlocked(data, id, false);
++
+ 	spin_unlock_irqrestore(&data->lock, flags);
+ 
+ 	return 0;
+@@ -393,6 +432,8 @@ static int mtk_wdt_probe(struct platform
+ 						       wdt_data->toprgu_sw_rst_num);
+ 		if (err)
+ 			return err;
++
++		mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
+ 	}
+ 
+ 	mtk_wdt->disable_wdt_extrst =
+@@ -427,6 +468,7 @@ static const struct of_device_id mtk_wdt
+ 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
+ 	{ .compatible = "mediatek,mt6589-wdt" },
+ 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
++	{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
+ 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
+ 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
+ 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
diff --git a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch
new file mode 100644
index 0000000000..1fcb1e64c7
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch
@@ -0,0 +1,99 @@
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+@@ -601,6 +601,30 @@ out:
+ 	return err;
+ }
+ 
++static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
++				const struct mtk_pin_desc *desc,
++				u32 pullup, u32 arg)
++{
++    int err, pd;
++
++	if (arg == MTK_DISABLE)
++		pd = 0;
++	else if ((arg == MTK_ENABLE) && pullup)
++		pd = 0;
++	else if ((arg == MTK_ENABLE) && !pullup)
++		pd = 1;
++	else {
++		err = -EINVAL;
++		goto out;
++	}
++
++	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
++
++out:
++	return err;
++
++}
++
+ static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
+ 				const struct mtk_pin_desc *desc,
+ 				u32 pullup, u32 arg)
+@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt
+ 			return err;
+ 	}
+ 
++	if (try_all_type & MTK_PULL_PD_TYPE) {
++		err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg);
++		if (!err)
++			return err;
++    }
++
+ 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ 		err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+ 		if (!err)
+@@ -875,6 +905,29 @@ out:
+ 	return err;
+ }
+ 
++static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
++				const struct mtk_pin_desc *desc,
++				u32 *pullup, u32 *enable)
++{
++	int err, pd;
++
++	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
++	if (err)
++		goto out;
++
++	if (pd == 0) {
++		*pullup = 0;
++		*enable = MTK_DISABLE;
++	} else if (pd == 1) {
++		*pullup = 0;
++		*enable = MTK_ENABLE;
++	} else
++		err = -EINVAL;
++
++out:
++	return err;
++}
++
+ static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
+ 				const struct mtk_pin_desc *desc,
+ 				u32 *pullup, u32 *enable)
+@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt
+ 		if (!err)
+ 			return err;
+ 	}
++
++	if (try_all_type & MTK_PULL_PD_TYPE) {
++		err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
++		if (!err)
++			return err;
++	}
+ 
+ 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ 		err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+@@ -24,6 +24,7 @@
+  * turned on/off itself. But it can't be selected pull up/down
+  */
+ #define MTK_PULL_RSEL_TYPE		BIT(3)
++#define MTK_PULL_PD_TYPE        BIT(4)
+ /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
+  * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
+  */
diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
index e96abd5170..487990ab77 100644
--- a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
+++ b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -379,6 +379,12 @@ config ROCKCHIP_PHY
+@@ -384,6 +384,12 @@ config ROCKCHIP_PHY
  	help
  	  Currently supports the integrated Ethernet PHY.
  
@@ -15,7 +15,7 @@
  	help
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
-@@ -94,6 +94,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
+@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
  obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
  obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
  obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
diff --git a/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch
new file mode 100644
index 0000000000..a597f70caa
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch
@@ -0,0 +1,167 @@
+From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 2 Jun 2023 13:06:26 +0800
+Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg
+
+Patch from Sam Shih <sam.shih@mediatek.com> found in MediaTek SDK
+released under GPL.
+
+Get syscon and use it to set the PHY type.
+Extend support to PCIe and SGMII mode in addition to USB2 and USB3.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++-
+ 1 file changed, 80 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/mediatek/phy-mtk-xsphy.c
++++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
+@@ -11,10 +11,12 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/iopoll.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
++#include <linux/regmap.h>
+ 
+ #include "phy-mtk-io.h"
+ 
+@@ -81,12 +83,22 @@
+ #define XSP_SR_COEF_DIVISOR	1000
+ #define XSP_FM_DET_CYCLE_CNT	1024
+ 
++/* PHY switch between pcie/usb3/sgmii */
++#define USB_PHY_SWITCH_CTRL	0x0
++#define RG_PHY_SW_TYPE		GENMASK(3, 0)
++#define RG_PHY_SW_PCIE		0x0
++#define RG_PHY_SW_USB3		0x1
++#define RG_PHY_SW_SGMII		0x2
++
+ struct xsphy_instance {
+ 	struct phy *phy;
+ 	void __iomem *port_base;
+ 	struct clk *ref_clk;	/* reference clock of anolog phy */
+ 	u32 index;
+ 	u32 type;
++	struct regmap *type_sw;
++	u32 type_sw_reg;
++	u32 type_sw_index;
+ 	/* only for HQA test */
+ 	int efuse_intr;
+ 	int efuse_tx_imp;
+@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt
+ 			inst->efuse_intr, inst->efuse_tx_imp,
+ 			inst->efuse_rx_imp);
+ 		break;
++	case PHY_TYPE_PCIE:
++	case PHY_TYPE_SGMII:
++		/* nothing to do */
++		break;
+ 	default:
+ 		dev_err(xsphy->dev, "incompatible phy type\n");
+ 		return;
+@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_
+ 				     RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
+ }
+ 
++/* type switch for usb3/pcie/sgmii */
++static int phy_type_syscon_get(struct xsphy_instance *instance,
++			       struct device_node *dn)
++{
++	struct of_phandle_args args;
++	int ret;
++
++	/* type switch function is optional */
++	if (!of_property_read_bool(dn, "mediatek,syscon-type"))
++		return 0;
++
++	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
++					       2, 0, &args);
++	if (ret)
++		return ret;
++
++	instance->type_sw_reg = args.args[0];
++	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
++	instance->type_sw = syscon_node_to_regmap(args.np);
++	of_node_put(args.np);
++	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
++		 instance->type_sw_reg, instance->type_sw_index);
++
++	return PTR_ERR_OR_ZERO(instance->type_sw);
++}
++
++static int phy_type_set(struct xsphy_instance *instance)
++{
++	int type;
++	u32 offset;
++
++	if (!instance->type_sw)
++		return 0;
++
++	switch (instance->type) {
++	case PHY_TYPE_USB3:
++		type = RG_PHY_SW_USB3;
++		break;
++	case PHY_TYPE_PCIE:
++		type = RG_PHY_SW_PCIE;
++		break;
++	case PHY_TYPE_SGMII:
++		type = RG_PHY_SW_SGMII;
++		break;
++	case PHY_TYPE_USB2:
++	default:
++		return 0;
++	}
++
++	offset = instance->type_sw_index * BITS_PER_BYTE;
++	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
++			   RG_PHY_SW_TYPE << offset, type << offset);
++
++	return 0;
++}
++
+ static int mtk_phy_init(struct phy *phy)
+ {
+ 	struct xsphy_instance *inst = phy_get_drvdata(phy);
+@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy)
+ 	case PHY_TYPE_USB3:
+ 		u3_phy_props_set(xsphy, inst);
+ 		break;
++	case PHY_TYPE_PCIE:
++	case PHY_TYPE_SGMII:
++		/* nothing to do, only used to set type */
++		break;
+ 	default:
+ 		dev_err(xsphy->dev, "incompatible phy type\n");
+ 		clk_disable_unprepare(inst->ref_clk);
+@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct
+ 
+ 	inst->type = args->args[0];
+ 	if (!(inst->type == PHY_TYPE_USB2 ||
+-	      inst->type == PHY_TYPE_USB3)) {
++	      inst->type == PHY_TYPE_USB3 ||
++	      inst->type == PHY_TYPE_PCIE ||
++	      inst->type == PHY_TYPE_SGMII)) {
+ 		dev_err(dev, "unsupported phy type: %d\n", inst->type);
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+ 	phy_parse_property(xsphy, inst);
++	phy_type_set(inst);
+ 
+ 	return inst->phy;
+ }
+@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo
+ 			retval = PTR_ERR(inst->ref_clk);
+ 			goto put_child;
+ 		}
++
++		retval = phy_type_syscon_get(inst, child_np);
++		if (retval)
++			goto put_child;
+ 	}
+ 
+ 	provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
diff --git a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
index a9a1fb3a5b..0bbf9ac773 100644
--- a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
+++ b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
@@ -24,9 +24,9 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -12936,6 +12936,15 @@ S:	Maintained
- F:	drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -12938,6 +12938,15 @@ F:	drivers/net/pcs/pcs-mtk-usxgmii.c
  F:	include/linux/pcs/pcs-mtk-lynxi.h
+ F:	include/linux/pcs/pcs-mtk-usxgmii.h
  
 +MEDIATEK ETHERNET PHY DRIVERS
 +M:	Daniel Golle <daniel@makrotopia.org>
@@ -42,7 +42,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  L:	linux-i2c@vger.kernel.org
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -309,6 +309,18 @@ config MEDIATEK_GE_PHY
+@@ -314,6 +314,18 @@ config MEDIATEK_GE_PHY
  	help
  	  Supports the MediaTek Gigabit Ethernet PHYs.
  
@@ -63,7 +63,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	depends on PTP_1588_CLOCK_OPTIONAL
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
-@@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
+@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
  obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
  obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
  obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o
diff --git a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
index da316049ac..b4c07a4b1f 100644
--- a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
+++ b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -321,6 +321,13 @@ config MEDIATEK_GE_SOC_PHY
+@@ -326,6 +326,13 @@ config MEDIATEK_GE_SOC_PHY
  	  present in the SoCs efuse and will dynamically calibrate VCM
  	  (common-mode voltage) during startup.
  
@@ -29,7 +29,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	depends on PTP_1588_CLOCK_OPTIONAL
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
-@@ -78,6 +78,7 @@ obj-$(CONFIG_MARVELL_10G_PHY)	+= marvell
+@@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_10G_PHY)	+= marvell
  obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
  obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
  obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
diff --git a/target/linux/mediatek/patches-6.1/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch
deleted file mode 100644
index a7e4d602ce..0000000000
--- a/target/linux/mediatek/patches-6.1/750-net-phy-add-driver-for-Airoha-EN8811-2.5G-PHY.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 4a6ecbd197764499d808309f372341370a89f88c Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 11 Jun 2023 01:59:14 +0100
-Subject: [PATCH] net: phy: add driver for Airoha EN8811 2.5G PHY
-
-2500Base-T PHY with ID 0x03a2a411, needs firmware upload
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig       |   5 +
- drivers/net/phy/Makefile      |   1 +
- drivers/net/phy/air_en8811h.c | 708 ++++++++++++++++++++++++++++++++++
- drivers/net/phy/air_en8811h.h | 151 ++++++++
- 4 files changed, 865 insertions(+)
- create mode 100644 drivers/net/phy/air_en8811h.c
- create mode 100644 drivers/net/phy/air_en8811h.h
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -156,6 +156,17 @@ config MESON_GXL_PHY
- 	help
- 	  Currently has a driver for the Amlogic Meson GXL Internal PHY
- 
-+config AIROHA_EN8811H_PHY
-+	tristate "Airoha EN8811H 2.5G Gigabit PHY"
-+	help
-+	  Currently supports the Airoha EN8811H PHY.
-+
-+config AIROHA_EN8811H_PHY_DEBUGFS
-+	bool "EN8811H debugfs support"
-+	depends on AIROHA_EN8811H_PHY
-+	help
-+	  Enable creation of debugfs files for the EN8811H drivers.
-+
- config ADIN_PHY
- 	tristate "Analog Devices Industrial Ethernet PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -47,6 +47,8 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
- 
- obj-$(CONFIG_ADIN_PHY)		+= adin.o
- obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
-+air_en8811h-y			:= air_en8811h_main.o air_en8811h_api.o
-+obj-$(CONFIG_AIROHA_EN8811H_PHY)	+= air_en8811h.o
- obj-$(CONFIG_AMD_PHY)		+= amd.o
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
- obj-$(CONFIG_AT803X_PHY)	+= at803x.o
diff --git a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
deleted file mode 100644
index c58ae96403..0000000000
--- a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 02:48:41 +0000
-Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for
- raw_to_mcelsius
-
-Instead of having if-else logic selecting either raw_to_mcelsius_v1 or
-raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function
-pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the
-probe function.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/thermal/mtk_thermal.c | 17 ++++++++++-------
- 1 file changed, 10 insertions(+), 7 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -292,6 +292,8 @@ struct mtk_thermal {
- 
- 	const struct mtk_thermal_data *conf;
- 	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
-+
-+	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
- };
- 
- /* MT8183 thermal sensor data */
-@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature(
- 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
- 		raw = readl(mt->thermal_base + conf->msr[i]);
- 
--		if (mt->conf->version == MTK_THERMAL_V1) {
--			temp = raw_to_mcelsius_v1(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		} else {
--			temp = raw_to_mcelsius_v2(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		}
-+		temp = mt->raw_to_mcelsius(
-+			mt, conf->bank_data[bank->id].sensors[i], raw);
-+
- 
- 		/*
- 		 * The first read of a sensor often contains very high bogus
-@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
-+	if (mt->conf->version == MTK_THERMAL_V1)
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-+	else
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
- 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch b/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch
new file mode 100644
index 0000000000..694b73a2b1
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch
@@ -0,0 +1,37 @@
+From f167da186acf90847e1a6d3716e253825a6218ec Mon Sep 17 00:00:00 2001
+From: Randy Dunlap <rdunlap@infradead.org>
+Date: Thu, 12 Jan 2023 22:44:49 -0800
+Subject: [PATCH 01/42] thermal/drivers/mtk_thermal: Fix kernel-doc function
+ name
+
+Use the correct function name in a kernel-doc comment to prevent
+a warning:
+
+drivers/thermal/mtk_thermal.c:562: warning: expecting prototype for raw_to_mcelsius(). Prototype was for raw_to_mcelsius_v1() instead
+
+Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
+Cc: "Rafael J. Wysocki" <rafael@kernel.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
+Cc: Amit Kucheria <amitk@kernel.org>
+Cc: Zhang Rui <rui.zhang@intel.com>
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+Cc: linux-pm@vger.kernel.org
+Cc: linux-arm-kernel@lists.infradead.org
+Cc: linux-mediatek@lists.infradead.org
+Link: https://lore.kernel.org/r/20230113064449.15061-1-rdunlap@infradead.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mtk_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mtk_thermal.c
++++ b/drivers/thermal/mtk_thermal.c
+@@ -550,7 +550,7 @@ static const struct mtk_thermal_data mt8
+ };
+ 
+ /**
+- * raw_to_mcelsius - convert a raw ADC value to mcelsius
++ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
+  * @mt:	The thermal controller
+  * @sensno:	sensor number
+  * @raw:	raw ADC value
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch b/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch
new file mode 100644
index 0000000000..aaed9d7e90
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch
@@ -0,0 +1,37 @@
+From 255509232417ee71fd606cb957d44cf6544f0c43 Mon Sep 17 00:00:00 2001
+From: ye xingchen <ye.xingchen@zte.com.cn>
+Date: Wed, 18 Jan 2023 16:37:47 +0800
+Subject: [PATCH 02/42] thermal/drivers/mtk_thermal: Use
+ devm_platform_get_and_ioremap_resource()
+
+Convert platform_get_resource(), devm_ioremap_resource() to a single
+call to devm_platform_get_and_ioremap_resource(), as this is exactly
+what this function does.
+
+Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
+Link: https://lore.kernel.org/r/202301181637472073620@zte.com.cn
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mtk_thermal.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/thermal/mtk_thermal.c
++++ b/drivers/thermal/mtk_thermal.c
+@@ -990,7 +990,6 @@ static int mtk_thermal_probe(struct plat
+ 	int ret, i, ctrl_id;
+ 	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
+ 	struct mtk_thermal *mt;
+-	struct resource *res;
+ 	u64 auxadc_phys_base, apmixed_phys_base;
+ 	struct thermal_zone_device *tzdev;
+ 	void __iomem *apmixed_base, *auxadc_base;
+@@ -1009,8 +1008,7 @@ static int mtk_thermal_probe(struct plat
+ 	if (IS_ERR(mt->clk_auxadc))
+ 		return PTR_ERR(mt->clk_auxadc);
+ 
+-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
++	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ 	if (IS_ERR(mt->thermal_base))
+ 		return PTR_ERR(mt->thermal_base);
+ 
diff --git a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch
similarity index 75%
rename from target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
rename to target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch
index c58ae96403..215b0fd7de 100644
--- a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch
@@ -1,7 +1,7 @@
-From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001
+From ca86dbd309ba03bef38ae91f037e2030bb671ab7 Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 02:48:41 +0000
-Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for
+Date: Wed, 18 Jan 2023 15:40:39 +0000
+Subject: [PATCH 03/42] thermal/drivers/mtk: Use function pointer for
  raw_to_mcelsius
 
 Instead of having if-else logic selecting either raw_to_mcelsius_v1 or
@@ -9,7 +9,11 @@ raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function
 pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the
 probe function.
 
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Link: https://lore.kernel.org/r/69c17529e8418da3eec703dde31e1b01e5b0f7e8.1674055882.git.daniel@makrotopia.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
 ---
  drivers/thermal/mtk_thermal.c | 17 ++++++++++-------
  1 file changed, 10 insertions(+), 7 deletions(-)
@@ -42,7 +46,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  		/*
  		 * The first read of a sensor often contains very high bogus
-@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat
+@@ -1073,6 +1071,11 @@ static int mtk_thermal_probe(struct plat
  		mtk_thermal_release_periodic_ts(mt, auxadc_base);
  	}
  
diff --git a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch
similarity index 89%
rename from target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
rename to target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch
index 65311d5718..ef2006775a 100644
--- a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch
@@ -1,7 +1,7 @@
-From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001
+From aec1d89dccc7cba04fdb3e52dfda328f3302ba17 Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 30 Nov 2022 13:19:39 +0000
-Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981
+Date: Wed, 18 Jan 2023 15:40:58 +0000
+Subject: [PATCH 04/42] thermal/drivers/mtk: Add support for MT7986 and MT7981
 
 Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
 Brings code to assign values from efuse as well as new function to
@@ -9,10 +9,14 @@ convert raw temperature to millidegree celsius, as found in MediaTek's
 SDK sources (but cleaned up and de-duplicated)
 
 [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b
+
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/2d341fc45266217249586eb4bd3be3ac4ca83a12.1674055882.git.daniel@makrotopia.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
 ---
- drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++--
- 1 file changed, 132 insertions(+), 5 deletions(-)
+ drivers/thermal/mtk_thermal.c | 128 ++++++++++++++++++++++++++++++++--
+ 1 file changed, 124 insertions(+), 4 deletions(-)
 
 --- a/drivers/thermal/mtk_thermal.c
 +++ b/drivers/thermal/mtk_thermal.c
@@ -117,7 +121,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +};
 +
  /**
-  * raw_to_mcelsius - convert a raw ADC value to mcelsius
+  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
   * @mt:	The thermal controller
 @@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
  	return (format_2 - tmp) * 100;
@@ -210,7 +214,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		.compatible = "mediatek,mt8183-thermal",
  		.data = (void *)&mt8183_thermal_data,
  	}, {
-@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat
+@@ -1066,15 +1184,17 @@ static int mtk_thermal_probe(struct plat
  		goto err_disable_clk_auxadc;
  	}
  
@@ -220,21 +224,13 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		mtk_thermal_release_periodic_ts(mt, auxadc_base);
  	}
  
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
+ 	if (mt->conf->version == MTK_THERMAL_V1)
  		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
 -	else
-+		break;
-+	case MTK_THERMAL_V2:
++	else if (mt->conf->version == MTK_THERMAL_V2)
  		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+		break;
-+	case MTK_THERMAL_V3:
++	else
 +		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
-+		break;
-+	default:
-+		break;
-+	}
  
  	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
  		for (i = 0; i < mt->conf->num_banks; i++)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch b/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch
new file mode 100644
index 0000000000..e102a338cd
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch
@@ -0,0 +1,2602 @@
+From 5e3aac197a74914ccec2732a89c29d960730d28f Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Thu, 9 Feb 2023 11:56:23 +0100
+Subject: [PATCH 05/42] thermal/drivers/mediatek: Relocate driver to mediatek
+ folder
+
+Add MediaTek proprietary folder to upstream more thermal zone and cooler
+drivers, relocate the original thermal controller driver to it, and rename it
+as "auxadc_thermal.c" to show its purpose more clearly.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230209105628.50294-2-bchihi@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/Kconfig                       | 14 ++++---------
+ drivers/thermal/Makefile                      |  2 +-
+ drivers/thermal/mediatek/Kconfig              | 21 +++++++++++++++++++
+ drivers/thermal/mediatek/Makefile             |  1 +
+ .../auxadc_thermal.c}                         |  2 +-
+ 5 files changed, 28 insertions(+), 12 deletions(-)
+ create mode 100644 drivers/thermal/mediatek/Kconfig
+ create mode 100644 drivers/thermal/mediatek/Makefile
+ rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%)
+
+--- a/drivers/thermal/Kconfig
++++ b/drivers/thermal/Kconfig
+@@ -412,16 +412,10 @@ config DA9062_THERMAL
+ 	  zone.
+ 	  Compatible with the DA9062 and DA9061 PMICs.
+ 
+-config MTK_THERMAL
+-	tristate "Temperature sensor driver for mediatek SoCs"
+-	depends on ARCH_MEDIATEK || COMPILE_TEST
+-	depends on HAS_IOMEM
+-	depends on NVMEM || NVMEM=n
+-	depends on RESET_CONTROLLER
+-	default y
+-	help
+-	  Enable this option if you want to have support for thermal management
+-	  controller present in Mediatek SoCs
++menu "Mediatek thermal drivers"
++depends on ARCH_MEDIATEK || COMPILE_TEST
++source "drivers/thermal/mediatek/Kconfig"
++endmenu
+ 
+ config AMLOGIC_THERMAL
+ 	tristate "Amlogic Thermal Support"
+--- a/drivers/thermal/Makefile
++++ b/drivers/thermal/Makefile
+@@ -55,7 +55,7 @@ obj-y				+= st/
+ obj-y				+= qcom/
+ obj-y				+= tegra/
+ obj-$(CONFIG_HISI_THERMAL)     += hisi_thermal.o
+-obj-$(CONFIG_MTK_THERMAL)	+= mtk_thermal.o
++obj-y				+= mediatek/
+ obj-$(CONFIG_GENERIC_ADC_THERMAL)	+= thermal-generic-adc.o
+ obj-$(CONFIG_UNIPHIER_THERMAL)	+= uniphier_thermal.o
+ obj-$(CONFIG_AMLOGIC_THERMAL)     += amlogic_thermal.o
+--- /dev/null
++++ b/drivers/thermal/mediatek/Kconfig
+@@ -0,0 +1,21 @@
++config MTK_THERMAL
++	tristate "MediaTek thermal drivers"
++	depends on THERMAL_OF
++	help
++	  This is the option for MediaTek thermal software solutions.
++	  Please enable corresponding options to get temperature
++	  information from thermal sensors or turn on throttle
++	  mechaisms for thermal mitigation.
++
++if MTK_THERMAL
++
++config MTK_SOC_THERMAL
++	tristate "AUXADC temperature sensor driver for MediaTek SoCs"
++	depends on HAS_IOMEM
++	help
++	  Enable this option if you want to get SoC temperature
++	  information for MediaTek platforms.
++	  This driver configures thermal controllers to collect
++	  temperature via AUXADC interface.
++
++endif
+--- /dev/null
++++ b/drivers/thermal/mediatek/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_MTK_SOC_THERMAL)	+= auxadc_thermal.o
+--- a/drivers/thermal/mtk_thermal.c
++++ /dev/null
+@@ -1,1254 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-/*
+- * Copyright (c) 2015 MediaTek Inc.
+- * Author: Hanyi Wu <hanyi.wu@mediatek.com>
+- *         Sascha Hauer <s.hauer@pengutronix.de>
+- *         Dawei Chien <dawei.chien@mediatek.com>
+- *         Louis Yu <louis.yu@mediatek.com>
+- */
+-
+-#include <linux/clk.h>
+-#include <linux/delay.h>
+-#include <linux/interrupt.h>
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/nvmem-consumer.h>
+-#include <linux/of.h>
+-#include <linux/of_address.h>
+-#include <linux/of_device.h>
+-#include <linux/platform_device.h>
+-#include <linux/slab.h>
+-#include <linux/io.h>
+-#include <linux/thermal.h>
+-#include <linux/reset.h>
+-#include <linux/types.h>
+-
+-#include "thermal_hwmon.h"
+-
+-/* AUXADC Registers */
+-#define AUXADC_CON1_SET_V	0x008
+-#define AUXADC_CON1_CLR_V	0x00c
+-#define AUXADC_CON2_V		0x010
+-#define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
+-
+-#define APMIXED_SYS_TS_CON1	0x604
+-
+-/* Thermal Controller Registers */
+-#define TEMP_MONCTL0		0x000
+-#define TEMP_MONCTL1		0x004
+-#define TEMP_MONCTL2		0x008
+-#define TEMP_MONIDET0		0x014
+-#define TEMP_MONIDET1		0x018
+-#define TEMP_MSRCTL0		0x038
+-#define TEMP_MSRCTL1		0x03c
+-#define TEMP_AHBPOLL		0x040
+-#define TEMP_AHBTO		0x044
+-#define TEMP_ADCPNP0		0x048
+-#define TEMP_ADCPNP1		0x04c
+-#define TEMP_ADCPNP2		0x050
+-#define TEMP_ADCPNP3		0x0b4
+-
+-#define TEMP_ADCMUX		0x054
+-#define TEMP_ADCEN		0x060
+-#define TEMP_PNPMUXADDR		0x064
+-#define TEMP_ADCMUXADDR		0x068
+-#define TEMP_ADCENADDR		0x074
+-#define TEMP_ADCVALIDADDR	0x078
+-#define TEMP_ADCVOLTADDR	0x07c
+-#define TEMP_RDCTRL		0x080
+-#define TEMP_ADCVALIDMASK	0x084
+-#define TEMP_ADCVOLTAGESHIFT	0x088
+-#define TEMP_ADCWRITECTRL	0x08c
+-#define TEMP_MSR0		0x090
+-#define TEMP_MSR1		0x094
+-#define TEMP_MSR2		0x098
+-#define TEMP_MSR3		0x0B8
+-
+-#define TEMP_SPARE0		0x0f0
+-
+-#define TEMP_ADCPNP0_1          0x148
+-#define TEMP_ADCPNP1_1          0x14c
+-#define TEMP_ADCPNP2_1          0x150
+-#define TEMP_MSR0_1             0x190
+-#define TEMP_MSR1_1             0x194
+-#define TEMP_MSR2_1             0x198
+-#define TEMP_ADCPNP3_1          0x1b4
+-#define TEMP_MSR3_1             0x1B8
+-
+-#define PTPCORESEL		0x400
+-
+-#define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
+-
+-#define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
+-#define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
+-
+-#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)
+-
+-#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
+-#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)
+-
+-#define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
+-#define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)
+-
+-/* MT8173 thermal sensors */
+-#define MT8173_TS1	0
+-#define MT8173_TS2	1
+-#define MT8173_TS3	2
+-#define MT8173_TS4	3
+-#define MT8173_TSABB	4
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT8173_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT8173 */
+-#define MT8173_NUM_SENSORS		5
+-
+-/* The number of banks in the MT8173 */
+-#define MT8173_NUM_ZONES		4
+-
+-/* The number of sensing points per bank */
+-#define MT8173_NUM_SENSORS_PER_ZONE	4
+-
+-/* The number of controller in the MT8173 */
+-#define MT8173_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT8173_CALIBRATION	165
+-
+-/*
+- * Layout of the fuses providing the calibration data
+- * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
+- * MT8183 has 6 sensors and needs 6 VTS calibration data.
+- * MT8173 has 5 sensors and needs 5 VTS calibration data.
+- * MT2701 has 3 sensors and needs 3 VTS calibration data.
+- * MT2712 has 4 sensors and needs 4 VTS calibration data.
+- */
+-#define CALIB_BUF0_VALID_V1		BIT(0)
+-#define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
+-#define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
+-#define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
+-#define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
+-#define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
+-#define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
+-#define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
+-#define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
+-#define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
+-
+-/*
+- * Layout of the fuses providing the calibration data
+- * These macros could be used for MT7622.
+- */
+-#define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
+-#define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
+-#define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
+-#define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
+-#define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
+-#define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
+-#define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
+-#define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
+-
+-/*
+- * Layout of the fuses providing the calibration data
+- * These macros can be used for MT7981 and MT7986.
+- */
+-#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
+-#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
+-#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
+-#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
+-#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
+-#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
+-#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
+-#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
+-#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
+-
+-enum {
+-	VTS1,
+-	VTS2,
+-	VTS3,
+-	VTS4,
+-	VTS5,
+-	VTSABB,
+-	MAX_NUM_VTS,
+-};
+-
+-enum mtk_thermal_version {
+-	MTK_THERMAL_V1 = 1,
+-	MTK_THERMAL_V2,
+-	MTK_THERMAL_V3,
+-};
+-
+-/* MT2701 thermal sensors */
+-#define MT2701_TS1	0
+-#define MT2701_TS2	1
+-#define MT2701_TSABB	2
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT2701_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT2701 */
+-#define MT2701_NUM_SENSORS	3
+-
+-/* The number of sensing points per bank */
+-#define MT2701_NUM_SENSORS_PER_ZONE	3
+-
+-/* The number of controller in the MT2701 */
+-#define MT2701_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT2701_CALIBRATION	165
+-
+-/* MT2712 thermal sensors */
+-#define MT2712_TS1	0
+-#define MT2712_TS2	1
+-#define MT2712_TS3	2
+-#define MT2712_TS4	3
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT2712_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT2712 */
+-#define MT2712_NUM_SENSORS	4
+-
+-/* The number of sensing points per bank */
+-#define MT2712_NUM_SENSORS_PER_ZONE	4
+-
+-/* The number of controller in the MT2712 */
+-#define MT2712_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT2712_CALIBRATION	165
+-
+-#define MT7622_TEMP_AUXADC_CHANNEL	11
+-#define MT7622_NUM_SENSORS		1
+-#define MT7622_NUM_ZONES		1
+-#define MT7622_NUM_SENSORS_PER_ZONE	1
+-#define MT7622_TS1	0
+-#define MT7622_NUM_CONTROLLER		1
+-
+-/* The maximum number of banks */
+-#define MAX_NUM_ZONES		8
+-
+-/* The calibration coefficient of sensor  */
+-#define MT7622_CALIBRATION	165
+-
+-/* MT8183 thermal sensors */
+-#define MT8183_TS1	0
+-#define MT8183_TS2	1
+-#define MT8183_TS3	2
+-#define MT8183_TS4	3
+-#define MT8183_TS5	4
+-#define MT8183_TSABB	5
+-
+-/* AUXADC channel  is used for the temperature sensors */
+-#define MT8183_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT8183 */
+-#define MT8183_NUM_SENSORS	6
+-
+-/* The number of banks in the MT8183 */
+-#define MT8183_NUM_ZONES               1
+-
+-/* The number of sensing points per bank */
+-#define MT8183_NUM_SENSORS_PER_ZONE	 6
+-
+-/* The number of controller in the MT8183 */
+-#define MT8183_NUM_CONTROLLER		2
+-
+-/* The calibration coefficient of sensor  */
+-#define MT8183_CALIBRATION	153
+-
+-/* AUXADC channel 11 is used for the temperature sensors */
+-#define MT7986_TEMP_AUXADC_CHANNEL	11
+-
+-/* The total number of temperature sensors in the MT7986 */
+-#define MT7986_NUM_SENSORS		1
+-
+-/* The number of banks in the MT7986 */
+-#define MT7986_NUM_ZONES		1
+-
+-/* The number of sensing points per bank */
+-#define MT7986_NUM_SENSORS_PER_ZONE	1
+-
+-/* MT7986 thermal sensors */
+-#define MT7986_TS1			0
+-
+-/* The number of controller in the MT7986 */
+-#define MT7986_NUM_CONTROLLER		1
+-
+-/* The calibration coefficient of sensor  */
+-#define MT7986_CALIBRATION		165
+-
+-struct mtk_thermal;
+-
+-struct thermal_bank_cfg {
+-	unsigned int num_sensors;
+-	const int *sensors;
+-};
+-
+-struct mtk_thermal_bank {
+-	struct mtk_thermal *mt;
+-	int id;
+-};
+-
+-struct mtk_thermal_data {
+-	s32 num_banks;
+-	s32 num_sensors;
+-	s32 auxadc_channel;
+-	const int *vts_index;
+-	const int *sensor_mux_values;
+-	const int *msr;
+-	const int *adcpnp;
+-	const int cali_val;
+-	const int num_controller;
+-	const int *controller_offset;
+-	bool need_switch_bank;
+-	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
+-	enum mtk_thermal_version version;
+-};
+-
+-struct mtk_thermal {
+-	struct device *dev;
+-	void __iomem *thermal_base;
+-
+-	struct clk *clk_peri_therm;
+-	struct clk *clk_auxadc;
+-	/* lock: for getting and putting banks */
+-	struct mutex lock;
+-
+-	/* Calibration values */
+-	s32 adc_ge;
+-	s32 adc_oe;
+-	s32 degc_cali;
+-	s32 o_slope;
+-	s32 o_slope_sign;
+-	s32 vts[MAX_NUM_VTS];
+-
+-	const struct mtk_thermal_data *conf;
+-	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
+-
+-	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
+-};
+-
+-/* MT8183 thermal sensor data */
+-static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
+-	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
+-};
+-
+-static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
+-};
+-
+-static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
+-	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
+-};
+-
+-static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
+-static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
+-
+-static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
+-};
+-
+-/* MT8173 thermal sensor data */
+-static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
+-	{ MT8173_TS2, MT8173_TS3 },
+-	{ MT8173_TS2, MT8173_TS4 },
+-	{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
+-	{ MT8173_TS2 },
+-};
+-
+-static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
+-};
+-
+-static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
+-};
+-
+-static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
+-static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
+-
+-static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3, VTS4, VTSABB
+-};
+-
+-/* MT2701 thermal sensor data */
+-static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
+-	MT2701_TS1, MT2701_TS2, MT2701_TSABB
+-};
+-
+-static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
+-};
+-
+-static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
+-};
+-
+-static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
+-static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
+-
+-static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3
+-};
+-
+-/* MT2712 thermal sensor data */
+-static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
+-	MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
+-};
+-
+-static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
+-};
+-
+-static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
+-	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
+-};
+-
+-static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
+-static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
+-
+-static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
+-	VTS1, VTS2, VTS3, VTS4
+-};
+-
+-/* MT7622 thermal sensor data */
+-static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
+-static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
+-static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
+-static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
+-static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
+-static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
+-
+-/* MT7986 thermal sensor data */
+-static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
+-static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
+-static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
+-static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
+-static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
+-static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
+-
+-/*
+- * The MT8173 thermal controller has four banks. Each bank can read up to
+- * four temperature sensors simultaneously. The MT8173 has a total of 5
+- * temperature sensors. We use each bank to measure a certain area of the
+- * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
+- * areas, hence is used in different banks.
+- *
+- * The thermal core only gets the maximum temperature of all banks, so
+- * the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data, and this indeed needs the temperatures of the individual banks
+- * for making better decisions.
+- */
+-static const struct mtk_thermal_data mt8173_thermal_data = {
+-	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT8173_NUM_ZONES,
+-	.num_sensors = MT8173_NUM_SENSORS,
+-	.vts_index = mt8173_vts_index,
+-	.cali_val = MT8173_CALIBRATION,
+-	.num_controller = MT8173_NUM_CONTROLLER,
+-	.controller_offset = mt8173_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 2,
+-			.sensors = mt8173_bank_data[0],
+-		}, {
+-			.num_sensors = 2,
+-			.sensors = mt8173_bank_data[1],
+-		}, {
+-			.num_sensors = 3,
+-			.sensors = mt8173_bank_data[2],
+-		}, {
+-			.num_sensors = 1,
+-			.sensors = mt8173_bank_data[3],
+-		},
+-	},
+-	.msr = mt8173_msr,
+-	.adcpnp = mt8173_adcpnp,
+-	.sensor_mux_values = mt8173_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * The MT2701 thermal controller has one bank, which can read up to
+- * three temperature sensors simultaneously. The MT2701 has a total of 3
+- * temperature sensors.
+- *
+- * The thermal core only gets the maximum temperature of this one bank,
+- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data.
+- */
+-static const struct mtk_thermal_data mt2701_thermal_data = {
+-	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
+-	.num_banks = 1,
+-	.num_sensors = MT2701_NUM_SENSORS,
+-	.vts_index = mt2701_vts_index,
+-	.cali_val = MT2701_CALIBRATION,
+-	.num_controller = MT2701_NUM_CONTROLLER,
+-	.controller_offset = mt2701_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 3,
+-			.sensors = mt2701_bank_data,
+-		},
+-	},
+-	.msr = mt2701_msr,
+-	.adcpnp = mt2701_adcpnp,
+-	.sensor_mux_values = mt2701_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * The MT2712 thermal controller has one bank, which can read up to
+- * four temperature sensors simultaneously. The MT2712 has a total of 4
+- * temperature sensors.
+- *
+- * The thermal core only gets the maximum temperature of this one bank,
+- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data.
+- */
+-static const struct mtk_thermal_data mt2712_thermal_data = {
+-	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
+-	.num_banks = 1,
+-	.num_sensors = MT2712_NUM_SENSORS,
+-	.vts_index = mt2712_vts_index,
+-	.cali_val = MT2712_CALIBRATION,
+-	.num_controller = MT2712_NUM_CONTROLLER,
+-	.controller_offset = mt2712_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 4,
+-			.sensors = mt2712_bank_data,
+-		},
+-	},
+-	.msr = mt2712_msr,
+-	.adcpnp = mt2712_adcpnp,
+-	.sensor_mux_values = mt2712_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
+- * access.
+- */
+-static const struct mtk_thermal_data mt7622_thermal_data = {
+-	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT7622_NUM_ZONES,
+-	.num_sensors = MT7622_NUM_SENSORS,
+-	.vts_index = mt7622_vts_index,
+-	.cali_val = MT7622_CALIBRATION,
+-	.num_controller = MT7622_NUM_CONTROLLER,
+-	.controller_offset = mt7622_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 1,
+-			.sensors = mt7622_bank_data,
+-		},
+-	},
+-	.msr = mt7622_msr,
+-	.adcpnp = mt7622_adcpnp,
+-	.sensor_mux_values = mt7622_mux_values,
+-	.version = MTK_THERMAL_V2,
+-};
+-
+-/*
+- * The MT8183 thermal controller has one bank for the current SW framework.
+- * The MT8183 has a total of 6 temperature sensors.
+- * There are two thermal controller to control the six sensor.
+- * The first one bind 2 sensor, and the other bind 4 sensors.
+- * The thermal core only gets the maximum temperature of all sensor, so
+- * the bank concept wouldn't be necessary here. However, the SVS (Smart
+- * Voltage Scaling) unit makes its decisions based on the same bank
+- * data, and this indeed needs the temperatures of the individual banks
+- * for making better decisions.
+- */
+-static const struct mtk_thermal_data mt8183_thermal_data = {
+-	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT8183_NUM_ZONES,
+-	.num_sensors = MT8183_NUM_SENSORS,
+-	.vts_index = mt8183_vts_index,
+-	.cali_val = MT8183_CALIBRATION,
+-	.num_controller = MT8183_NUM_CONTROLLER,
+-	.controller_offset = mt8183_tc_offset,
+-	.need_switch_bank = false,
+-	.bank_data = {
+-		{
+-			.num_sensors = 6,
+-			.sensors = mt8183_bank_data,
+-		},
+-	},
+-
+-	.msr = mt8183_msr,
+-	.adcpnp = mt8183_adcpnp,
+-	.sensor_mux_values = mt8183_mux_values,
+-	.version = MTK_THERMAL_V1,
+-};
+-
+-/*
+- * MT7986 uses AUXADC Channel 11 for raw data access.
+- */
+-static const struct mtk_thermal_data mt7986_thermal_data = {
+-	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
+-	.num_banks = MT7986_NUM_ZONES,
+-	.num_sensors = MT7986_NUM_SENSORS,
+-	.vts_index = mt7986_vts_index,
+-	.cali_val = MT7986_CALIBRATION,
+-	.num_controller = MT7986_NUM_CONTROLLER,
+-	.controller_offset = mt7986_tc_offset,
+-	.need_switch_bank = true,
+-	.bank_data = {
+-		{
+-			.num_sensors = 1,
+-			.sensors = mt7986_bank_data,
+-		},
+-	},
+-	.msr = mt7986_msr,
+-	.adcpnp = mt7986_adcpnp,
+-	.sensor_mux_values = mt7986_mux_values,
+-	.version = MTK_THERMAL_V3,
+-};
+-
+-/**
+- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
+- * @mt:	The thermal controller
+- * @sensno:	sensor number
+- * @raw:	raw ADC value
+- *
+- * This converts the raw ADC value to mcelsius using the SoC specific
+- * calibration constants
+- */
+-static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
+-{
+-	s32 tmp;
+-
+-	raw &= 0xfff;
+-
+-	tmp = 203450520 << 3;
+-	tmp /= mt->conf->cali_val + mt->o_slope;
+-	tmp /= 10000 + mt->adc_ge;
+-	tmp *= raw - mt->vts[sensno] - 3350;
+-	tmp >>= 3;
+-
+-	return mt->degc_cali * 500 - tmp;
+-}
+-
+-static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
+-{
+-	s32 format_1;
+-	s32 format_2;
+-	s32 g_oe;
+-	s32 g_gain;
+-	s32 g_x_roomt;
+-	s32 tmp;
+-
+-	if (raw == 0)
+-		return 0;
+-
+-	raw &= 0xfff;
+-	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
+-	g_oe = mt->adc_oe - 512;
+-	format_1 = mt->vts[VTS2] + 3105 - g_oe;
+-	format_2 = (mt->degc_cali * 10) >> 1;
+-	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
+-
+-	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
+-	tmp = tmp * 10 * 100 / 11;
+-
+-	if (mt->o_slope_sign == 0)
+-		tmp = tmp / (165 - mt->o_slope);
+-	else
+-		tmp = tmp / (165 + mt->o_slope);
+-
+-	return (format_2 - tmp) * 100;
+-}
+-
+-static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
+-{
+-	s32 tmp;
+-
+-	if (raw == 0)
+-		return 0;
+-
+-	raw &= 0xfff;
+-	tmp = 100000 * 15 / 16 * 10000;
+-	tmp /= 4096 - 512 + mt->adc_ge;
+-	tmp /= 1490;
+-	tmp *= raw - mt->vts[sensno] - 2900;
+-
+-	return mt->degc_cali * 500 - tmp;
+-}
+-
+-/**
+- * mtk_thermal_get_bank - get bank
+- * @bank:	The bank
+- *
+- * The bank registers are banked, we have to select a bank in the
+- * PTPCORESEL register to access it.
+- */
+-static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
+-{
+-	struct mtk_thermal *mt = bank->mt;
+-	u32 val;
+-
+-	if (mt->conf->need_switch_bank) {
+-		mutex_lock(&mt->lock);
+-
+-		val = readl(mt->thermal_base + PTPCORESEL);
+-		val &= ~0xf;
+-		val |= bank->id;
+-		writel(val, mt->thermal_base + PTPCORESEL);
+-	}
+-}
+-
+-/**
+- * mtk_thermal_put_bank - release bank
+- * @bank:	The bank
+- *
+- * release a bank previously taken with mtk_thermal_get_bank,
+- */
+-static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
+-{
+-	struct mtk_thermal *mt = bank->mt;
+-
+-	if (mt->conf->need_switch_bank)
+-		mutex_unlock(&mt->lock);
+-}
+-
+-/**
+- * mtk_thermal_bank_temperature - get the temperature of a bank
+- * @bank:	The bank
+- *
+- * The temperature of a bank is considered the maximum temperature of
+- * the sensors associated to the bank.
+- */
+-static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
+-{
+-	struct mtk_thermal *mt = bank->mt;
+-	const struct mtk_thermal_data *conf = mt->conf;
+-	int i, temp = INT_MIN, max = INT_MIN;
+-	u32 raw;
+-
+-	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
+-		raw = readl(mt->thermal_base + conf->msr[i]);
+-
+-		temp = mt->raw_to_mcelsius(
+-			mt, conf->bank_data[bank->id].sensors[i], raw);
+-
+-
+-		/*
+-		 * The first read of a sensor often contains very high bogus
+-		 * temperature value. Filter these out so that the system does
+-		 * not immediately shut down.
+-		 */
+-		if (temp > 200000)
+-			temp = 0;
+-
+-		if (temp > max)
+-			max = temp;
+-	}
+-
+-	return max;
+-}
+-
+-static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
+-{
+-	struct mtk_thermal *mt = tz->devdata;
+-	int i;
+-	int tempmax = INT_MIN;
+-
+-	for (i = 0; i < mt->conf->num_banks; i++) {
+-		struct mtk_thermal_bank *bank = &mt->banks[i];
+-
+-		mtk_thermal_get_bank(bank);
+-
+-		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
+-
+-		mtk_thermal_put_bank(bank);
+-	}
+-
+-	*temperature = tempmax;
+-
+-	return 0;
+-}
+-
+-static const struct thermal_zone_device_ops mtk_thermal_ops = {
+-	.get_temp = mtk_read_temp,
+-};
+-
+-static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
+-				  u32 apmixed_phys_base, u32 auxadc_phys_base,
+-				  int ctrl_id)
+-{
+-	struct mtk_thermal_bank *bank = &mt->banks[num];
+-	const struct mtk_thermal_data *conf = mt->conf;
+-	int i;
+-
+-	int offset = mt->conf->controller_offset[ctrl_id];
+-	void __iomem *controller_base = mt->thermal_base + offset;
+-
+-	bank->id = num;
+-	bank->mt = mt;
+-
+-	mtk_thermal_get_bank(bank);
+-
+-	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
+-	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
+-
+-	/*
+-	 * filt interval is 1 * 46.540us = 46.54us,
+-	 * sen interval is 429 * 46.540us = 19.96ms
+-	 */
+-	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
+-			TEMP_MONCTL2_SENSOR_INTERVAL(429),
+-			controller_base + TEMP_MONCTL2);
+-
+-	/* poll is set to 10u */
+-	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
+-	       controller_base + TEMP_AHBPOLL);
+-
+-	/* temperature sampling control, 1 sample */
+-	writel(0x0, controller_base + TEMP_MSRCTL0);
+-
+-	/* exceed this polling time, IRQ would be inserted */
+-	writel(0xffffffff, controller_base + TEMP_AHBTO);
+-
+-	/* number of interrupts per event, 1 is enough */
+-	writel(0x0, controller_base + TEMP_MONIDET0);
+-	writel(0x0, controller_base + TEMP_MONIDET1);
+-
+-	/*
+-	 * The MT8173 thermal controller does not have its own ADC. Instead it
+-	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
+-	 * controller has to be programmed with the physical addresses of the
+-	 * AUXADC registers and with the various bit positions in the AUXADC.
+-	 * Also the thermal controller controls a mux in the APMIXEDSYS register
+-	 * space.
+-	 */
+-
+-	/*
+-	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
+-	 * automatically by hw
+-	 */
+-	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
+-
+-	/* AHB address for auxadc mux selection */
+-	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
+-	       controller_base + TEMP_ADCMUXADDR);
+-
+-	if (mt->conf->version == MTK_THERMAL_V1) {
+-		/* AHB address for pnp sensor mux selection */
+-		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
+-		       controller_base + TEMP_PNPMUXADDR);
+-	}
+-
+-	/* AHB value for auxadc enable */
+-	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
+-
+-	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
+-	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
+-	       controller_base + TEMP_ADCENADDR);
+-
+-	/* AHB address for auxadc valid bit */
+-	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
+-	       controller_base + TEMP_ADCVALIDADDR);
+-
+-	/* AHB address for auxadc voltage output */
+-	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
+-	       controller_base + TEMP_ADCVOLTADDR);
+-
+-	/* read valid & voltage are at the same register */
+-	writel(0x0, controller_base + TEMP_RDCTRL);
+-
+-	/* indicate where the valid bit is */
+-	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
+-	       controller_base + TEMP_ADCVALIDMASK);
+-
+-	/* no shift */
+-	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
+-
+-	/* enable auxadc mux write transaction */
+-	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
+-		controller_base + TEMP_ADCWRITECTRL);
+-
+-	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
+-		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
+-		       mt->thermal_base + conf->adcpnp[i]);
+-
+-	writel((1 << conf->bank_data[num].num_sensors) - 1,
+-	       controller_base + TEMP_MONCTL0);
+-
+-	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
+-	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
+-	       controller_base + TEMP_ADCWRITECTRL);
+-
+-	mtk_thermal_put_bank(bank);
+-}
+-
+-static u64 of_get_phys_base(struct device_node *np)
+-{
+-	u64 size64;
+-	const __be32 *regaddr_p;
+-
+-	regaddr_p = of_get_address(np, 0, &size64, NULL);
+-	if (!regaddr_p)
+-		return OF_BAD_ADDR;
+-
+-	return of_translate_address(np, regaddr_p);
+-}
+-
+-static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
+-{
+-	int i;
+-
+-	if (!(buf[0] & CALIB_BUF0_VALID_V1))
+-		return -EINVAL;
+-
+-	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
+-
+-	for (i = 0; i < mt->conf->num_sensors; i++) {
+-		switch (mt->conf->vts_index[i]) {
+-		case VTS1:
+-			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
+-			break;
+-		case VTS2:
+-			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
+-			break;
+-		case VTS3:
+-			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
+-			break;
+-		case VTS4:
+-			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
+-			break;
+-		case VTS5:
+-			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
+-			break;
+-		case VTSABB:
+-			mt->vts[VTSABB] =
+-				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
+-			break;
+-		default:
+-			break;
+-		}
+-	}
+-
+-	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
+-	if (CALIB_BUF1_ID_V1(buf[1]) &
+-	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
+-		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
+-	else
+-		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
+-
+-	return 0;
+-}
+-
+-static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
+-{
+-	if (!CALIB_BUF1_VALID_V2(buf[1]))
+-		return -EINVAL;
+-
+-	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
+-	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
+-	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
+-	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
+-	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
+-	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
+-	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
+-	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
+-
+-	return 0;
+-}
+-
+-static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
+-{
+-	if (!CALIB_BUF1_VALID_V3(buf[1]))
+-		return -EINVAL;
+-
+-	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
+-	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
+-	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
+-	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
+-	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
+-	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
+-	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
+-
+-	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
+-		mt->o_slope = 0;
+-
+-	return 0;
+-}
+-
+-static int mtk_thermal_get_calibration_data(struct device *dev,
+-					    struct mtk_thermal *mt)
+-{
+-	struct nvmem_cell *cell;
+-	u32 *buf;
+-	size_t len;
+-	int i, ret = 0;
+-
+-	/* Start with default values */
+-	mt->adc_ge = 512;
+-	mt->adc_oe = 512;
+-	for (i = 0; i < mt->conf->num_sensors; i++)
+-		mt->vts[i] = 260;
+-	mt->degc_cali = 40;
+-	mt->o_slope = 0;
+-
+-	cell = nvmem_cell_get(dev, "calibration-data");
+-	if (IS_ERR(cell)) {
+-		if (PTR_ERR(cell) == -EPROBE_DEFER)
+-			return PTR_ERR(cell);
+-		return 0;
+-	}
+-
+-	buf = (u32 *)nvmem_cell_read(cell, &len);
+-
+-	nvmem_cell_put(cell);
+-
+-	if (IS_ERR(buf))
+-		return PTR_ERR(buf);
+-
+-	if (len < 3 * sizeof(u32)) {
+-		dev_warn(dev, "invalid calibration data\n");
+-		ret = -EINVAL;
+-		goto out;
+-	}
+-
+-	switch (mt->conf->version) {
+-	case MTK_THERMAL_V1:
+-		ret = mtk_thermal_extract_efuse_v1(mt, buf);
+-		break;
+-	case MTK_THERMAL_V2:
+-		ret = mtk_thermal_extract_efuse_v2(mt, buf);
+-		break;
+-	case MTK_THERMAL_V3:
+-		ret = mtk_thermal_extract_efuse_v3(mt, buf);
+-		break;
+-	default:
+-		ret = -EINVAL;
+-		break;
+-	}
+-
+-	if (ret) {
+-		dev_info(dev, "Device not calibrated, using default calibration values\n");
+-		ret = 0;
+-	}
+-
+-out:
+-	kfree(buf);
+-
+-	return ret;
+-}
+-
+-static const struct of_device_id mtk_thermal_of_match[] = {
+-	{
+-		.compatible = "mediatek,mt8173-thermal",
+-		.data = (void *)&mt8173_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt2701-thermal",
+-		.data = (void *)&mt2701_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt2712-thermal",
+-		.data = (void *)&mt2712_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt7622-thermal",
+-		.data = (void *)&mt7622_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt7986-thermal",
+-		.data = (void *)&mt7986_thermal_data,
+-	},
+-	{
+-		.compatible = "mediatek,mt8183-thermal",
+-		.data = (void *)&mt8183_thermal_data,
+-	}, {
+-	},
+-};
+-MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
+-
+-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
+-{
+-	int tmp;
+-
+-	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
+-	tmp &= ~(0x37);
+-	tmp |= 0x1;
+-	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
+-	udelay(200);
+-}
+-
+-static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
+-					    void __iomem *auxadc_base)
+-{
+-	int tmp;
+-
+-	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
+-	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
+-	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
+-	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
+-}
+-
+-static int mtk_thermal_probe(struct platform_device *pdev)
+-{
+-	int ret, i, ctrl_id;
+-	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
+-	struct mtk_thermal *mt;
+-	u64 auxadc_phys_base, apmixed_phys_base;
+-	struct thermal_zone_device *tzdev;
+-	void __iomem *apmixed_base, *auxadc_base;
+-
+-	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
+-	if (!mt)
+-		return -ENOMEM;
+-
+-	mt->conf = of_device_get_match_data(&pdev->dev);
+-
+-	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
+-	if (IS_ERR(mt->clk_peri_therm))
+-		return PTR_ERR(mt->clk_peri_therm);
+-
+-	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
+-	if (IS_ERR(mt->clk_auxadc))
+-		return PTR_ERR(mt->clk_auxadc);
+-
+-	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+-	if (IS_ERR(mt->thermal_base))
+-		return PTR_ERR(mt->thermal_base);
+-
+-	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
+-	if (ret)
+-		return ret;
+-
+-	mutex_init(&mt->lock);
+-
+-	mt->dev = &pdev->dev;
+-
+-	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
+-	if (!auxadc) {
+-		dev_err(&pdev->dev, "missing auxadc node\n");
+-		return -ENODEV;
+-	}
+-
+-	auxadc_base = of_iomap(auxadc, 0);
+-	auxadc_phys_base = of_get_phys_base(auxadc);
+-
+-	of_node_put(auxadc);
+-
+-	if (auxadc_phys_base == OF_BAD_ADDR) {
+-		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
+-		return -EINVAL;
+-	}
+-
+-	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
+-	if (!apmixedsys) {
+-		dev_err(&pdev->dev, "missing apmixedsys node\n");
+-		return -ENODEV;
+-	}
+-
+-	apmixed_base = of_iomap(apmixedsys, 0);
+-	apmixed_phys_base = of_get_phys_base(apmixedsys);
+-
+-	of_node_put(apmixedsys);
+-
+-	if (apmixed_phys_base == OF_BAD_ADDR) {
+-		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
+-		return -EINVAL;
+-	}
+-
+-	ret = device_reset_optional(&pdev->dev);
+-	if (ret)
+-		return ret;
+-
+-	ret = clk_prepare_enable(mt->clk_auxadc);
+-	if (ret) {
+-		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
+-		return ret;
+-	}
+-
+-	ret = clk_prepare_enable(mt->clk_peri_therm);
+-	if (ret) {
+-		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
+-		goto err_disable_clk_auxadc;
+-	}
+-
+-	if (mt->conf->version != MTK_THERMAL_V1) {
+-		mtk_thermal_turn_on_buffer(apmixed_base);
+-		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+-	}
+-
+-	if (mt->conf->version == MTK_THERMAL_V1)
+-		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
+-	else if (mt->conf->version == MTK_THERMAL_V2)
+-		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
+-	else
+-		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
+-
+-	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
+-		for (i = 0; i < mt->conf->num_banks; i++)
+-			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
+-					      auxadc_phys_base, ctrl_id);
+-
+-	platform_set_drvdata(pdev, mt);
+-
+-	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+-					      &mtk_thermal_ops);
+-	if (IS_ERR(tzdev)) {
+-		ret = PTR_ERR(tzdev);
+-		goto err_disable_clk_peri_therm;
+-	}
+-
+-	ret = devm_thermal_add_hwmon_sysfs(tzdev);
+-	if (ret)
+-		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
+-
+-	return 0;
+-
+-err_disable_clk_peri_therm:
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-err_disable_clk_auxadc:
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return ret;
+-}
+-
+-static int mtk_thermal_remove(struct platform_device *pdev)
+-{
+-	struct mtk_thermal *mt = platform_get_drvdata(pdev);
+-
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return 0;
+-}
+-
+-static struct platform_driver mtk_thermal_driver = {
+-	.probe = mtk_thermal_probe,
+-	.remove = mtk_thermal_remove,
+-	.driver = {
+-		.name = "mtk-thermal",
+-		.of_match_table = mtk_thermal_of_match,
+-	},
+-};
+-
+-module_platform_driver(mtk_thermal_driver);
+-
+-MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
+-MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
+-MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
+-MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+-MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
+-MODULE_DESCRIPTION("Mediatek thermal driver");
+-MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -0,0 +1,1254 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2015 MediaTek Inc.
++ * Author: Hanyi Wu <hanyi.wu@mediatek.com>
++ *         Sascha Hauer <s.hauer@pengutronix.de>
++ *         Dawei Chien <dawei.chien@mediatek.com>
++ *         Louis Yu <louis.yu@mediatek.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/thermal.h>
++#include <linux/reset.h>
++#include <linux/types.h>
++
++#include "../thermal_hwmon.h"
++
++/* AUXADC Registers */
++#define AUXADC_CON1_SET_V	0x008
++#define AUXADC_CON1_CLR_V	0x00c
++#define AUXADC_CON2_V		0x010
++#define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
++
++#define APMIXED_SYS_TS_CON1	0x604
++
++/* Thermal Controller Registers */
++#define TEMP_MONCTL0		0x000
++#define TEMP_MONCTL1		0x004
++#define TEMP_MONCTL2		0x008
++#define TEMP_MONIDET0		0x014
++#define TEMP_MONIDET1		0x018
++#define TEMP_MSRCTL0		0x038
++#define TEMP_MSRCTL1		0x03c
++#define TEMP_AHBPOLL		0x040
++#define TEMP_AHBTO		0x044
++#define TEMP_ADCPNP0		0x048
++#define TEMP_ADCPNP1		0x04c
++#define TEMP_ADCPNP2		0x050
++#define TEMP_ADCPNP3		0x0b4
++
++#define TEMP_ADCMUX		0x054
++#define TEMP_ADCEN		0x060
++#define TEMP_PNPMUXADDR		0x064
++#define TEMP_ADCMUXADDR		0x068
++#define TEMP_ADCENADDR		0x074
++#define TEMP_ADCVALIDADDR	0x078
++#define TEMP_ADCVOLTADDR	0x07c
++#define TEMP_RDCTRL		0x080
++#define TEMP_ADCVALIDMASK	0x084
++#define TEMP_ADCVOLTAGESHIFT	0x088
++#define TEMP_ADCWRITECTRL	0x08c
++#define TEMP_MSR0		0x090
++#define TEMP_MSR1		0x094
++#define TEMP_MSR2		0x098
++#define TEMP_MSR3		0x0B8
++
++#define TEMP_SPARE0		0x0f0
++
++#define TEMP_ADCPNP0_1          0x148
++#define TEMP_ADCPNP1_1          0x14c
++#define TEMP_ADCPNP2_1          0x150
++#define TEMP_MSR0_1             0x190
++#define TEMP_MSR1_1             0x194
++#define TEMP_MSR2_1             0x198
++#define TEMP_ADCPNP3_1          0x1b4
++#define TEMP_MSR3_1             0x1B8
++
++#define PTPCORESEL		0x400
++
++#define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
++
++#define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
++#define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
++
++#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)
++
++#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
++#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)
++
++#define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
++#define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)
++
++/* MT8173 thermal sensors */
++#define MT8173_TS1	0
++#define MT8173_TS2	1
++#define MT8173_TS3	2
++#define MT8173_TS4	3
++#define MT8173_TSABB	4
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT8173_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT8173 */
++#define MT8173_NUM_SENSORS		5
++
++/* The number of banks in the MT8173 */
++#define MT8173_NUM_ZONES		4
++
++/* The number of sensing points per bank */
++#define MT8173_NUM_SENSORS_PER_ZONE	4
++
++/* The number of controller in the MT8173 */
++#define MT8173_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT8173_CALIBRATION	165
++
++/*
++ * Layout of the fuses providing the calibration data
++ * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
++ * MT8183 has 6 sensors and needs 6 VTS calibration data.
++ * MT8173 has 5 sensors and needs 5 VTS calibration data.
++ * MT2701 has 3 sensors and needs 3 VTS calibration data.
++ * MT2712 has 4 sensors and needs 4 VTS calibration data.
++ */
++#define CALIB_BUF0_VALID_V1		BIT(0)
++#define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
++#define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
++#define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
++#define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
++#define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
++#define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
++#define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
++#define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
++#define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
++
++/*
++ * Layout of the fuses providing the calibration data
++ * These macros could be used for MT7622.
++ */
++#define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
++#define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
++#define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
++#define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
++#define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
++#define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
++#define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
++#define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
++
++/*
++ * Layout of the fuses providing the calibration data
++ * These macros can be used for MT7981 and MT7986.
++ */
++#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
++#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
++#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
++#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
++#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
++#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
++#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
++#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
++
++enum {
++	VTS1,
++	VTS2,
++	VTS3,
++	VTS4,
++	VTS5,
++	VTSABB,
++	MAX_NUM_VTS,
++};
++
++enum mtk_thermal_version {
++	MTK_THERMAL_V1 = 1,
++	MTK_THERMAL_V2,
++	MTK_THERMAL_V3,
++};
++
++/* MT2701 thermal sensors */
++#define MT2701_TS1	0
++#define MT2701_TS2	1
++#define MT2701_TSABB	2
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT2701_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT2701 */
++#define MT2701_NUM_SENSORS	3
++
++/* The number of sensing points per bank */
++#define MT2701_NUM_SENSORS_PER_ZONE	3
++
++/* The number of controller in the MT2701 */
++#define MT2701_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT2701_CALIBRATION	165
++
++/* MT2712 thermal sensors */
++#define MT2712_TS1	0
++#define MT2712_TS2	1
++#define MT2712_TS3	2
++#define MT2712_TS4	3
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT2712_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT2712 */
++#define MT2712_NUM_SENSORS	4
++
++/* The number of sensing points per bank */
++#define MT2712_NUM_SENSORS_PER_ZONE	4
++
++/* The number of controller in the MT2712 */
++#define MT2712_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT2712_CALIBRATION	165
++
++#define MT7622_TEMP_AUXADC_CHANNEL	11
++#define MT7622_NUM_SENSORS		1
++#define MT7622_NUM_ZONES		1
++#define MT7622_NUM_SENSORS_PER_ZONE	1
++#define MT7622_TS1	0
++#define MT7622_NUM_CONTROLLER		1
++
++/* The maximum number of banks */
++#define MAX_NUM_ZONES		8
++
++/* The calibration coefficient of sensor  */
++#define MT7622_CALIBRATION	165
++
++/* MT8183 thermal sensors */
++#define MT8183_TS1	0
++#define MT8183_TS2	1
++#define MT8183_TS3	2
++#define MT8183_TS4	3
++#define MT8183_TS5	4
++#define MT8183_TSABB	5
++
++/* AUXADC channel  is used for the temperature sensors */
++#define MT8183_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT8183 */
++#define MT8183_NUM_SENSORS	6
++
++/* The number of banks in the MT8183 */
++#define MT8183_NUM_ZONES               1
++
++/* The number of sensing points per bank */
++#define MT8183_NUM_SENSORS_PER_ZONE	 6
++
++/* The number of controller in the MT8183 */
++#define MT8183_NUM_CONTROLLER		2
++
++/* The calibration coefficient of sensor  */
++#define MT8183_CALIBRATION	153
++
++/* AUXADC channel 11 is used for the temperature sensors */
++#define MT7986_TEMP_AUXADC_CHANNEL	11
++
++/* The total number of temperature sensors in the MT7986 */
++#define MT7986_NUM_SENSORS		1
++
++/* The number of banks in the MT7986 */
++#define MT7986_NUM_ZONES		1
++
++/* The number of sensing points per bank */
++#define MT7986_NUM_SENSORS_PER_ZONE	1
++
++/* MT7986 thermal sensors */
++#define MT7986_TS1			0
++
++/* The number of controller in the MT7986 */
++#define MT7986_NUM_CONTROLLER		1
++
++/* The calibration coefficient of sensor  */
++#define MT7986_CALIBRATION		165
++
++struct mtk_thermal;
++
++struct thermal_bank_cfg {
++	unsigned int num_sensors;
++	const int *sensors;
++};
++
++struct mtk_thermal_bank {
++	struct mtk_thermal *mt;
++	int id;
++};
++
++struct mtk_thermal_data {
++	s32 num_banks;
++	s32 num_sensors;
++	s32 auxadc_channel;
++	const int *vts_index;
++	const int *sensor_mux_values;
++	const int *msr;
++	const int *adcpnp;
++	const int cali_val;
++	const int num_controller;
++	const int *controller_offset;
++	bool need_switch_bank;
++	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
++	enum mtk_thermal_version version;
++};
++
++struct mtk_thermal {
++	struct device *dev;
++	void __iomem *thermal_base;
++
++	struct clk *clk_peri_therm;
++	struct clk *clk_auxadc;
++	/* lock: for getting and putting banks */
++	struct mutex lock;
++
++	/* Calibration values */
++	s32 adc_ge;
++	s32 adc_oe;
++	s32 degc_cali;
++	s32 o_slope;
++	s32 o_slope_sign;
++	s32 vts[MAX_NUM_VTS];
++
++	const struct mtk_thermal_data *conf;
++	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
++
++	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
++};
++
++/* MT8183 thermal sensor data */
++static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
++	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
++};
++
++static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
++};
++
++static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
++	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
++};
++
++static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
++static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
++
++static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
++};
++
++/* MT8173 thermal sensor data */
++static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
++	{ MT8173_TS2, MT8173_TS3 },
++	{ MT8173_TS2, MT8173_TS4 },
++	{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
++	{ MT8173_TS2 },
++};
++
++static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
++};
++
++static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
++};
++
++static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
++static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
++
++static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3, VTS4, VTSABB
++};
++
++/* MT2701 thermal sensor data */
++static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
++	MT2701_TS1, MT2701_TS2, MT2701_TSABB
++};
++
++static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
++};
++
++static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
++};
++
++static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
++static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
++
++static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3
++};
++
++/* MT2712 thermal sensor data */
++static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
++	MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
++};
++
++static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
++};
++
++static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
++};
++
++static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
++static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
++
++static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
++	VTS1, VTS2, VTS3, VTS4
++};
++
++/* MT7622 thermal sensor data */
++static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
++static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
++static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
++static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
++static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
++static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
++
++/* MT7986 thermal sensor data */
++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
++
++/*
++ * The MT8173 thermal controller has four banks. Each bank can read up to
++ * four temperature sensors simultaneously. The MT8173 has a total of 5
++ * temperature sensors. We use each bank to measure a certain area of the
++ * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
++ * areas, hence is used in different banks.
++ *
++ * The thermal core only gets the maximum temperature of all banks, so
++ * the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data, and this indeed needs the temperatures of the individual banks
++ * for making better decisions.
++ */
++static const struct mtk_thermal_data mt8173_thermal_data = {
++	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT8173_NUM_ZONES,
++	.num_sensors = MT8173_NUM_SENSORS,
++	.vts_index = mt8173_vts_index,
++	.cali_val = MT8173_CALIBRATION,
++	.num_controller = MT8173_NUM_CONTROLLER,
++	.controller_offset = mt8173_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 2,
++			.sensors = mt8173_bank_data[0],
++		}, {
++			.num_sensors = 2,
++			.sensors = mt8173_bank_data[1],
++		}, {
++			.num_sensors = 3,
++			.sensors = mt8173_bank_data[2],
++		}, {
++			.num_sensors = 1,
++			.sensors = mt8173_bank_data[3],
++		},
++	},
++	.msr = mt8173_msr,
++	.adcpnp = mt8173_adcpnp,
++	.sensor_mux_values = mt8173_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * The MT2701 thermal controller has one bank, which can read up to
++ * three temperature sensors simultaneously. The MT2701 has a total of 3
++ * temperature sensors.
++ *
++ * The thermal core only gets the maximum temperature of this one bank,
++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data.
++ */
++static const struct mtk_thermal_data mt2701_thermal_data = {
++	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
++	.num_banks = 1,
++	.num_sensors = MT2701_NUM_SENSORS,
++	.vts_index = mt2701_vts_index,
++	.cali_val = MT2701_CALIBRATION,
++	.num_controller = MT2701_NUM_CONTROLLER,
++	.controller_offset = mt2701_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 3,
++			.sensors = mt2701_bank_data,
++		},
++	},
++	.msr = mt2701_msr,
++	.adcpnp = mt2701_adcpnp,
++	.sensor_mux_values = mt2701_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * The MT2712 thermal controller has one bank, which can read up to
++ * four temperature sensors simultaneously. The MT2712 has a total of 4
++ * temperature sensors.
++ *
++ * The thermal core only gets the maximum temperature of this one bank,
++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data.
++ */
++static const struct mtk_thermal_data mt2712_thermal_data = {
++	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
++	.num_banks = 1,
++	.num_sensors = MT2712_NUM_SENSORS,
++	.vts_index = mt2712_vts_index,
++	.cali_val = MT2712_CALIBRATION,
++	.num_controller = MT2712_NUM_CONTROLLER,
++	.controller_offset = mt2712_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 4,
++			.sensors = mt2712_bank_data,
++		},
++	},
++	.msr = mt2712_msr,
++	.adcpnp = mt2712_adcpnp,
++	.sensor_mux_values = mt2712_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
++ * access.
++ */
++static const struct mtk_thermal_data mt7622_thermal_data = {
++	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT7622_NUM_ZONES,
++	.num_sensors = MT7622_NUM_SENSORS,
++	.vts_index = mt7622_vts_index,
++	.cali_val = MT7622_CALIBRATION,
++	.num_controller = MT7622_NUM_CONTROLLER,
++	.controller_offset = mt7622_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 1,
++			.sensors = mt7622_bank_data,
++		},
++	},
++	.msr = mt7622_msr,
++	.adcpnp = mt7622_adcpnp,
++	.sensor_mux_values = mt7622_mux_values,
++	.version = MTK_THERMAL_V2,
++};
++
++/*
++ * The MT8183 thermal controller has one bank for the current SW framework.
++ * The MT8183 has a total of 6 temperature sensors.
++ * There are two thermal controller to control the six sensor.
++ * The first one bind 2 sensor, and the other bind 4 sensors.
++ * The thermal core only gets the maximum temperature of all sensor, so
++ * the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data, and this indeed needs the temperatures of the individual banks
++ * for making better decisions.
++ */
++static const struct mtk_thermal_data mt8183_thermal_data = {
++	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT8183_NUM_ZONES,
++	.num_sensors = MT8183_NUM_SENSORS,
++	.vts_index = mt8183_vts_index,
++	.cali_val = MT8183_CALIBRATION,
++	.num_controller = MT8183_NUM_CONTROLLER,
++	.controller_offset = mt8183_tc_offset,
++	.need_switch_bank = false,
++	.bank_data = {
++		{
++			.num_sensors = 6,
++			.sensors = mt8183_bank_data,
++		},
++	},
++
++	.msr = mt8183_msr,
++	.adcpnp = mt8183_adcpnp,
++	.sensor_mux_values = mt8183_mux_values,
++	.version = MTK_THERMAL_V1,
++};
++
++/*
++ * MT7986 uses AUXADC Channel 11 for raw data access.
++ */
++static const struct mtk_thermal_data mt7986_thermal_data = {
++	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT7986_NUM_ZONES,
++	.num_sensors = MT7986_NUM_SENSORS,
++	.vts_index = mt7986_vts_index,
++	.cali_val = MT7986_CALIBRATION,
++	.num_controller = MT7986_NUM_CONTROLLER,
++	.controller_offset = mt7986_tc_offset,
++	.need_switch_bank = true,
++	.bank_data = {
++		{
++			.num_sensors = 1,
++			.sensors = mt7986_bank_data,
++		},
++	},
++	.msr = mt7986_msr,
++	.adcpnp = mt7986_adcpnp,
++	.sensor_mux_values = mt7986_mux_values,
++	.version = MTK_THERMAL_V3,
++};
++
++/**
++ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
++ * @mt:	The thermal controller
++ * @sensno:	sensor number
++ * @raw:	raw ADC value
++ *
++ * This converts the raw ADC value to mcelsius using the SoC specific
++ * calibration constants
++ */
++static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
++{
++	s32 tmp;
++
++	raw &= 0xfff;
++
++	tmp = 203450520 << 3;
++	tmp /= mt->conf->cali_val + mt->o_slope;
++	tmp /= 10000 + mt->adc_ge;
++	tmp *= raw - mt->vts[sensno] - 3350;
++	tmp >>= 3;
++
++	return mt->degc_cali * 500 - tmp;
++}
++
++static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
++{
++	s32 format_1;
++	s32 format_2;
++	s32 g_oe;
++	s32 g_gain;
++	s32 g_x_roomt;
++	s32 tmp;
++
++	if (raw == 0)
++		return 0;
++
++	raw &= 0xfff;
++	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
++	g_oe = mt->adc_oe - 512;
++	format_1 = mt->vts[VTS2] + 3105 - g_oe;
++	format_2 = (mt->degc_cali * 10) >> 1;
++	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
++
++	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
++	tmp = tmp * 10 * 100 / 11;
++
++	if (mt->o_slope_sign == 0)
++		tmp = tmp / (165 - mt->o_slope);
++	else
++		tmp = tmp / (165 + mt->o_slope);
++
++	return (format_2 - tmp) * 100;
++}
++
++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
++{
++	s32 tmp;
++
++	if (raw == 0)
++		return 0;
++
++	raw &= 0xfff;
++	tmp = 100000 * 15 / 16 * 10000;
++	tmp /= 4096 - 512 + mt->adc_ge;
++	tmp /= 1490;
++	tmp *= raw - mt->vts[sensno] - 2900;
++
++	return mt->degc_cali * 500 - tmp;
++}
++
++/**
++ * mtk_thermal_get_bank - get bank
++ * @bank:	The bank
++ *
++ * The bank registers are banked, we have to select a bank in the
++ * PTPCORESEL register to access it.
++ */
++static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
++{
++	struct mtk_thermal *mt = bank->mt;
++	u32 val;
++
++	if (mt->conf->need_switch_bank) {
++		mutex_lock(&mt->lock);
++
++		val = readl(mt->thermal_base + PTPCORESEL);
++		val &= ~0xf;
++		val |= bank->id;
++		writel(val, mt->thermal_base + PTPCORESEL);
++	}
++}
++
++/**
++ * mtk_thermal_put_bank - release bank
++ * @bank:	The bank
++ *
++ * release a bank previously taken with mtk_thermal_get_bank,
++ */
++static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
++{
++	struct mtk_thermal *mt = bank->mt;
++
++	if (mt->conf->need_switch_bank)
++		mutex_unlock(&mt->lock);
++}
++
++/**
++ * mtk_thermal_bank_temperature - get the temperature of a bank
++ * @bank:	The bank
++ *
++ * The temperature of a bank is considered the maximum temperature of
++ * the sensors associated to the bank.
++ */
++static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
++{
++	struct mtk_thermal *mt = bank->mt;
++	const struct mtk_thermal_data *conf = mt->conf;
++	int i, temp = INT_MIN, max = INT_MIN;
++	u32 raw;
++
++	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
++		raw = readl(mt->thermal_base + conf->msr[i]);
++
++		temp = mt->raw_to_mcelsius(
++			mt, conf->bank_data[bank->id].sensors[i], raw);
++
++
++		/*
++		 * The first read of a sensor often contains very high bogus
++		 * temperature value. Filter these out so that the system does
++		 * not immediately shut down.
++		 */
++		if (temp > 200000)
++			temp = 0;
++
++		if (temp > max)
++			max = temp;
++	}
++
++	return max;
++}
++
++static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
++{
++	struct mtk_thermal *mt = tz->devdata;
++	int i;
++	int tempmax = INT_MIN;
++
++	for (i = 0; i < mt->conf->num_banks; i++) {
++		struct mtk_thermal_bank *bank = &mt->banks[i];
++
++		mtk_thermal_get_bank(bank);
++
++		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
++
++		mtk_thermal_put_bank(bank);
++	}
++
++	*temperature = tempmax;
++
++	return 0;
++}
++
++static const struct thermal_zone_device_ops mtk_thermal_ops = {
++	.get_temp = mtk_read_temp,
++};
++
++static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
++				  u32 apmixed_phys_base, u32 auxadc_phys_base,
++				  int ctrl_id)
++{
++	struct mtk_thermal_bank *bank = &mt->banks[num];
++	const struct mtk_thermal_data *conf = mt->conf;
++	int i;
++
++	int offset = mt->conf->controller_offset[ctrl_id];
++	void __iomem *controller_base = mt->thermal_base + offset;
++
++	bank->id = num;
++	bank->mt = mt;
++
++	mtk_thermal_get_bank(bank);
++
++	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
++	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
++
++	/*
++	 * filt interval is 1 * 46.540us = 46.54us,
++	 * sen interval is 429 * 46.540us = 19.96ms
++	 */
++	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
++			TEMP_MONCTL2_SENSOR_INTERVAL(429),
++			controller_base + TEMP_MONCTL2);
++
++	/* poll is set to 10u */
++	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
++	       controller_base + TEMP_AHBPOLL);
++
++	/* temperature sampling control, 1 sample */
++	writel(0x0, controller_base + TEMP_MSRCTL0);
++
++	/* exceed this polling time, IRQ would be inserted */
++	writel(0xffffffff, controller_base + TEMP_AHBTO);
++
++	/* number of interrupts per event, 1 is enough */
++	writel(0x0, controller_base + TEMP_MONIDET0);
++	writel(0x0, controller_base + TEMP_MONIDET1);
++
++	/*
++	 * The MT8173 thermal controller does not have its own ADC. Instead it
++	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
++	 * controller has to be programmed with the physical addresses of the
++	 * AUXADC registers and with the various bit positions in the AUXADC.
++	 * Also the thermal controller controls a mux in the APMIXEDSYS register
++	 * space.
++	 */
++
++	/*
++	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
++	 * automatically by hw
++	 */
++	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
++
++	/* AHB address for auxadc mux selection */
++	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
++	       controller_base + TEMP_ADCMUXADDR);
++
++	if (mt->conf->version == MTK_THERMAL_V1) {
++		/* AHB address for pnp sensor mux selection */
++		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
++		       controller_base + TEMP_PNPMUXADDR);
++	}
++
++	/* AHB value for auxadc enable */
++	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
++
++	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
++	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
++	       controller_base + TEMP_ADCENADDR);
++
++	/* AHB address for auxadc valid bit */
++	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
++	       controller_base + TEMP_ADCVALIDADDR);
++
++	/* AHB address for auxadc voltage output */
++	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
++	       controller_base + TEMP_ADCVOLTADDR);
++
++	/* read valid & voltage are at the same register */
++	writel(0x0, controller_base + TEMP_RDCTRL);
++
++	/* indicate where the valid bit is */
++	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
++	       controller_base + TEMP_ADCVALIDMASK);
++
++	/* no shift */
++	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
++
++	/* enable auxadc mux write transaction */
++	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
++		controller_base + TEMP_ADCWRITECTRL);
++
++	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
++		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
++		       mt->thermal_base + conf->adcpnp[i]);
++
++	writel((1 << conf->bank_data[num].num_sensors) - 1,
++	       controller_base + TEMP_MONCTL0);
++
++	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
++	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
++	       controller_base + TEMP_ADCWRITECTRL);
++
++	mtk_thermal_put_bank(bank);
++}
++
++static u64 of_get_phys_base(struct device_node *np)
++{
++	u64 size64;
++	const __be32 *regaddr_p;
++
++	regaddr_p = of_get_address(np, 0, &size64, NULL);
++	if (!regaddr_p)
++		return OF_BAD_ADDR;
++
++	return of_translate_address(np, regaddr_p);
++}
++
++static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
++{
++	int i;
++
++	if (!(buf[0] & CALIB_BUF0_VALID_V1))
++		return -EINVAL;
++
++	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
++
++	for (i = 0; i < mt->conf->num_sensors; i++) {
++		switch (mt->conf->vts_index[i]) {
++		case VTS1:
++			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
++			break;
++		case VTS2:
++			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
++			break;
++		case VTS3:
++			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
++			break;
++		case VTS4:
++			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
++			break;
++		case VTS5:
++			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
++			break;
++		case VTSABB:
++			mt->vts[VTSABB] =
++				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
++			break;
++		default:
++			break;
++		}
++	}
++
++	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
++	if (CALIB_BUF1_ID_V1(buf[1]) &
++	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
++		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
++	else
++		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
++
++	return 0;
++}
++
++static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
++{
++	if (!CALIB_BUF1_VALID_V2(buf[1]))
++		return -EINVAL;
++
++	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
++	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
++	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
++	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
++	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
++	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
++	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
++	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
++
++	return 0;
++}
++
++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
++{
++	if (!CALIB_BUF1_VALID_V3(buf[1]))
++		return -EINVAL;
++
++	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
++	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
++	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
++	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
++	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
++	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
++	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
++
++	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
++		mt->o_slope = 0;
++
++	return 0;
++}
++
++static int mtk_thermal_get_calibration_data(struct device *dev,
++					    struct mtk_thermal *mt)
++{
++	struct nvmem_cell *cell;
++	u32 *buf;
++	size_t len;
++	int i, ret = 0;
++
++	/* Start with default values */
++	mt->adc_ge = 512;
++	mt->adc_oe = 512;
++	for (i = 0; i < mt->conf->num_sensors; i++)
++		mt->vts[i] = 260;
++	mt->degc_cali = 40;
++	mt->o_slope = 0;
++
++	cell = nvmem_cell_get(dev, "calibration-data");
++	if (IS_ERR(cell)) {
++		if (PTR_ERR(cell) == -EPROBE_DEFER)
++			return PTR_ERR(cell);
++		return 0;
++	}
++
++	buf = (u32 *)nvmem_cell_read(cell, &len);
++
++	nvmem_cell_put(cell);
++
++	if (IS_ERR(buf))
++		return PTR_ERR(buf);
++
++	if (len < 3 * sizeof(u32)) {
++		dev_warn(dev, "invalid calibration data\n");
++		ret = -EINVAL;
++		goto out;
++	}
++
++	switch (mt->conf->version) {
++	case MTK_THERMAL_V1:
++		ret = mtk_thermal_extract_efuse_v1(mt, buf);
++		break;
++	case MTK_THERMAL_V2:
++		ret = mtk_thermal_extract_efuse_v2(mt, buf);
++		break;
++	case MTK_THERMAL_V3:
++		ret = mtk_thermal_extract_efuse_v3(mt, buf);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	if (ret) {
++		dev_info(dev, "Device not calibrated, using default calibration values\n");
++		ret = 0;
++	}
++
++out:
++	kfree(buf);
++
++	return ret;
++}
++
++static const struct of_device_id mtk_thermal_of_match[] = {
++	{
++		.compatible = "mediatek,mt8173-thermal",
++		.data = (void *)&mt8173_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt2701-thermal",
++		.data = (void *)&mt2701_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt2712-thermal",
++		.data = (void *)&mt2712_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt7622-thermal",
++		.data = (void *)&mt7622_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt7986-thermal",
++		.data = (void *)&mt7986_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt8183-thermal",
++		.data = (void *)&mt8183_thermal_data,
++	}, {
++	},
++};
++MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
++
++static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
++{
++	int tmp;
++
++	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
++	tmp &= ~(0x37);
++	tmp |= 0x1;
++	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
++	udelay(200);
++}
++
++static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
++					    void __iomem *auxadc_base)
++{
++	int tmp;
++
++	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
++	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
++	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
++	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
++}
++
++static int mtk_thermal_probe(struct platform_device *pdev)
++{
++	int ret, i, ctrl_id;
++	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
++	struct mtk_thermal *mt;
++	u64 auxadc_phys_base, apmixed_phys_base;
++	struct thermal_zone_device *tzdev;
++	void __iomem *apmixed_base, *auxadc_base;
++
++	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
++	if (!mt)
++		return -ENOMEM;
++
++	mt->conf = of_device_get_match_data(&pdev->dev);
++
++	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
++	if (IS_ERR(mt->clk_peri_therm))
++		return PTR_ERR(mt->clk_peri_therm);
++
++	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
++	if (IS_ERR(mt->clk_auxadc))
++		return PTR_ERR(mt->clk_auxadc);
++
++	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
++	if (IS_ERR(mt->thermal_base))
++		return PTR_ERR(mt->thermal_base);
++
++	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
++	if (ret)
++		return ret;
++
++	mutex_init(&mt->lock);
++
++	mt->dev = &pdev->dev;
++
++	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
++	if (!auxadc) {
++		dev_err(&pdev->dev, "missing auxadc node\n");
++		return -ENODEV;
++	}
++
++	auxadc_base = of_iomap(auxadc, 0);
++	auxadc_phys_base = of_get_phys_base(auxadc);
++
++	of_node_put(auxadc);
++
++	if (auxadc_phys_base == OF_BAD_ADDR) {
++		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
++		return -EINVAL;
++	}
++
++	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
++	if (!apmixedsys) {
++		dev_err(&pdev->dev, "missing apmixedsys node\n");
++		return -ENODEV;
++	}
++
++	apmixed_base = of_iomap(apmixedsys, 0);
++	apmixed_phys_base = of_get_phys_base(apmixedsys);
++
++	of_node_put(apmixedsys);
++
++	if (apmixed_phys_base == OF_BAD_ADDR) {
++		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
++		return -EINVAL;
++	}
++
++	ret = device_reset_optional(&pdev->dev);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(mt->clk_auxadc);
++	if (ret) {
++		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
++		return ret;
++	}
++
++	ret = clk_prepare_enable(mt->clk_peri_therm);
++	if (ret) {
++		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
++		goto err_disable_clk_auxadc;
++	}
++
++	if (mt->conf->version != MTK_THERMAL_V1) {
++		mtk_thermal_turn_on_buffer(apmixed_base);
++		mtk_thermal_release_periodic_ts(mt, auxadc_base);
++	}
++
++	if (mt->conf->version == MTK_THERMAL_V1)
++		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
++	else if (mt->conf->version == MTK_THERMAL_V2)
++		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
++	else
++		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
++
++	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
++		for (i = 0; i < mt->conf->num_banks; i++)
++			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
++					      auxadc_phys_base, ctrl_id);
++
++	platform_set_drvdata(pdev, mt);
++
++	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
++					      &mtk_thermal_ops);
++	if (IS_ERR(tzdev)) {
++		ret = PTR_ERR(tzdev);
++		goto err_disable_clk_peri_therm;
++	}
++
++	ret = devm_thermal_add_hwmon_sysfs(tzdev);
++	if (ret)
++		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
++
++	return 0;
++
++err_disable_clk_peri_therm:
++	clk_disable_unprepare(mt->clk_peri_therm);
++err_disable_clk_auxadc:
++	clk_disable_unprepare(mt->clk_auxadc);
++
++	return ret;
++}
++
++static int mtk_thermal_remove(struct platform_device *pdev)
++{
++	struct mtk_thermal *mt = platform_get_drvdata(pdev);
++
++	clk_disable_unprepare(mt->clk_peri_therm);
++	clk_disable_unprepare(mt->clk_auxadc);
++
++	return 0;
++}
++
++static struct platform_driver mtk_thermal_driver = {
++	.probe = mtk_thermal_probe,
++	.remove = mtk_thermal_remove,
++	.driver = {
++		.name = "mtk-thermal",
++		.of_match_table = mtk_thermal_of_match,
++	},
++};
++
++module_platform_driver(mtk_thermal_driver);
++
++MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
++MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
++MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
++MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
++MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
++MODULE_DESCRIPTION("Mediatek thermal driver");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch b/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch
new file mode 100644
index 0000000000..2ae3734e40
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch
@@ -0,0 +1,1298 @@
+From 325fadf27b21f7d79843c3cc282b7f3e6620ad3d Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Thu, 9 Feb 2023 11:56:26 +0100
+Subject: [PATCH 06/42] thermal/drivers/mediatek: Add the Low Voltage Thermal
+ Sensor driver
+
+The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi
+controllers contained in a thermal domain.
+
+A thermal domains can be the MCU or the AP.
+
+Each thermal domains contain up to seven controllers, each thermal
+controller handle up to four thermal sensors.
+
+The LVTS has two Finite State Machines (FSM), one to handle the
+functionin temperatures range like hot or cold temperature and another
+one to handle monitoring trip point. The FSM notifies via interrupts
+when a trip point is crossed.
+
+The interrupt is managed at the thermal controller level, so when an
+interrupt occurs, the driver has to find out which sensor triggered
+such an interrupt.
+
+The sampling of the thermal can be filtered or immediate. For the
+former, the LVTS measures several points and applies a low pass
+filter.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+On MT8195 Tomato Chromebook:
+
+Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230209105628.50294-5-bchihi@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/Kconfig        |   16 +
+ drivers/thermal/mediatek/Makefile       |    1 +
+ drivers/thermal/mediatek/lvts_thermal.c | 1224 +++++++++++++++++++++++
+ 3 files changed, 1241 insertions(+)
+ create mode 100644 drivers/thermal/mediatek/lvts_thermal.c
+
+--- a/drivers/thermal/mediatek/Kconfig
++++ b/drivers/thermal/mediatek/Kconfig
+@@ -18,4 +18,20 @@ config MTK_SOC_THERMAL
+ 	  This driver configures thermal controllers to collect
+ 	  temperature via AUXADC interface.
+ 
++config MTK_LVTS_THERMAL
++        tristate "LVTS Thermal Driver for MediaTek SoCs"
++        depends on HAS_IOMEM
++        help
++          Enable this option if you want to get SoC temperature
++          information for supported MediaTek platforms.
++          This driver configures LVTS (Low Voltage Thermal Sensor)
++          thermal controllers to collect temperatures via ASIF
++          (Analog Serial Interface).
++
++config MTK_LVTS_THERMAL_DEBUGFS
++       bool "LVTS thermal debugfs"
++       depends on MTK_LVTS_THERMAL && DEBUG_FS
++       help
++         Enable this option to debug the internals of the device driver.
++
+ endif
+--- a/drivers/thermal/mediatek/Makefile
++++ b/drivers/thermal/mediatek/Makefile
+@@ -1 +1,2 @@
+ obj-$(CONFIG_MTK_SOC_THERMAL)	+= auxadc_thermal.o
++obj-$(CONFIG_MTK_LVTS_THERMAL)	+= lvts_thermal.o
+--- /dev/null
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -0,0 +1,1224 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Balsam CHIHI <bchihi@baylibre.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/debugfs.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++#include <linux/thermal.h>
++#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
++
++#define LVTS_MONCTL0(__base)	(__base + 0x0000)
++#define LVTS_MONCTL1(__base)	(__base + 0x0004)
++#define LVTS_MONCTL2(__base)	(__base + 0x0008)
++#define LVTS_MONINT(__base)		(__base + 0x000C)
++#define LVTS_MONINTSTS(__base)	(__base + 0x0010)
++#define LVTS_MONIDET0(__base)	(__base + 0x0014)
++#define LVTS_MONIDET1(__base)	(__base + 0x0018)
++#define LVTS_MONIDET2(__base)	(__base + 0x001C)
++#define LVTS_MONIDET3(__base)	(__base + 0x0020)
++#define LVTS_H2NTHRE(__base)	(__base + 0x0024)
++#define LVTS_HTHRE(__base)		(__base + 0x0028)
++#define LVTS_OFFSETH(__base)	(__base + 0x0030)
++#define LVTS_OFFSETL(__base)	(__base + 0x0034)
++#define LVTS_MSRCTL0(__base)	(__base + 0x0038)
++#define LVTS_MSRCTL1(__base)	(__base + 0x003C)
++#define LVTS_TSSEL(__base)		(__base + 0x0040)
++#define LVTS_CALSCALE(__base)	(__base + 0x0048)
++#define LVTS_ID(__base)			(__base + 0x004C)
++#define LVTS_CONFIG(__base)		(__base + 0x0050)
++#define LVTS_EDATA00(__base)	(__base + 0x0054)
++#define LVTS_EDATA01(__base)	(__base + 0x0058)
++#define LVTS_EDATA02(__base)	(__base + 0x005C)
++#define LVTS_EDATA03(__base)	(__base + 0x0060)
++#define LVTS_MSR0(__base)		(__base + 0x0090)
++#define LVTS_MSR1(__base)		(__base + 0x0094)
++#define LVTS_MSR2(__base)		(__base + 0x0098)
++#define LVTS_MSR3(__base)		(__base + 0x009C)
++#define LVTS_IMMD0(__base)		(__base + 0x00A0)
++#define LVTS_IMMD1(__base)		(__base + 0x00A4)
++#define LVTS_IMMD2(__base)		(__base + 0x00A8)
++#define LVTS_IMMD3(__base)		(__base + 0x00AC)
++#define LVTS_PROTCTL(__base)	(__base + 0x00C0)
++#define LVTS_PROTTA(__base)		(__base + 0x00C4)
++#define LVTS_PROTTB(__base)		(__base + 0x00C8)
++#define LVTS_PROTTC(__base)		(__base + 0x00CC)
++#define LVTS_CLKEN(__base)		(__base + 0x00E4)
++
++#define LVTS_PERIOD_UNIT			((118 * 1000) / (256 * 38))
++#define LVTS_GROUP_INTERVAL			1
++#define LVTS_FILTER_INTERVAL		1
++#define LVTS_SENSOR_INTERVAL		1
++#define LVTS_HW_FILTER				0x2
++#define LVTS_TSSEL_CONF				0x13121110
++#define LVTS_CALSCALE_CONF			0x300
++#define LVTS_MONINT_CONF			0x9FBF7BDE
++
++#define LVTS_INT_SENSOR0			0x0009001F
++#define LVTS_INT_SENSOR1			0X000881F0
++#define LVTS_INT_SENSOR2			0x00247C00
++#define LVTS_INT_SENSOR3			0x1FC00000
++
++#define LVTS_SENSOR_MAX				4
++#define LVTS_GOLDEN_TEMP_MAX		62
++#define LVTS_GOLDEN_TEMP_DEFAULT	50
++#define LVTS_COEFF_A				-250460
++#define LVTS_COEFF_B				250460
++
++#define LVTS_MSR_IMMEDIATE_MODE		0
++#define LVTS_MSR_FILTERED_MODE		1
++
++#define LVTS_HW_SHUTDOWN_MT8195		105000
++
++static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
++static int coeff_b = LVTS_COEFF_B;
++
++struct lvts_sensor_data {
++	int dt_id;
++};
++
++struct lvts_ctrl_data {
++	struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
++	int cal_offset[LVTS_SENSOR_MAX];
++	int hw_tshut_temp;
++	int num_lvts_sensor;
++	int offset;
++	int mode;
++};
++
++struct lvts_data {
++	const struct lvts_ctrl_data *lvts_ctrl;
++	int num_lvts_ctrl;
++};
++
++struct lvts_sensor {
++	struct thermal_zone_device *tz;
++	void __iomem *msr;
++	void __iomem *base;
++	int id;
++	int dt_id;
++};
++
++struct lvts_ctrl {
++	struct lvts_sensor sensors[LVTS_SENSOR_MAX];
++	u32 calibration[LVTS_SENSOR_MAX];
++	u32 hw_tshut_raw_temp;
++	int num_lvts_sensor;
++	int mode;
++	void __iomem *base;
++};
++
++struct lvts_domain {
++	struct lvts_ctrl *lvts_ctrl;
++	struct reset_control *reset;
++	struct clk *clk;
++	int num_lvts_ctrl;
++	void __iomem *base;
++	size_t calib_len;
++	u8 *calib;
++#ifdef CONFIG_DEBUG_FS
++	struct dentry *dom_dentry;
++#endif
++};
++
++#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
++
++#define LVTS_DEBUG_FS_REGS(__reg)		\
++{						\
++	.name = __stringify(__reg),		\
++	.offset = __reg(0),			\
++}
++
++static const struct debugfs_reg32 lvts_regs[] = {
++	LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
++	LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
++	LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
++	LVTS_DEBUG_FS_REGS(LVTS_MONINT),
++	LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
++	LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
++	LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
++	LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
++	LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
++	LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
++	LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
++	LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
++	LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
++	LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
++	LVTS_DEBUG_FS_REGS(LVTS_ID),
++	LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
++	LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR0),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR1),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR2),
++	LVTS_DEBUG_FS_REGS(LVTS_MSR3),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
++	LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
++	LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
++	LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
++};
++
++static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
++{
++	struct debugfs_regset32 *regset;
++	struct lvts_ctrl *lvts_ctrl;
++	struct dentry *dentry;
++	char name[64];
++	int i;
++
++	lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
++	if (!lvts_td->dom_dentry)
++		return 0;
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
++
++		lvts_ctrl = &lvts_td->lvts_ctrl[i];
++
++		sprintf(name, "controller%d", i);
++		dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
++		if (!dentry)
++			continue;
++
++		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
++		if (!regset)
++			continue;
++
++		regset->base = lvts_ctrl->base;
++		regset->regs = lvts_regs;
++		regset->nregs = ARRAY_SIZE(lvts_regs);
++
++		debugfs_create_regset32("registers", 0400, dentry, regset);
++	}
++
++	return 0;
++}
++
++static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
++{
++	debugfs_remove_recursive(lvts_td->dom_dentry);
++}
++
++#else
++
++static inline int lvts_debugfs_init(struct device *dev,
++				    struct lvts_domain *lvts_td)
++{
++	return 0;
++}
++
++static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
++
++#endif
++
++static int lvts_raw_to_temp(u32 raw_temp)
++{
++	int temperature;
++
++	temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
++	temperature += coeff_b;
++
++	return temperature;
++}
++
++static u32 lvts_temp_to_raw(int temperature)
++{
++	u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
++
++	raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
++
++	return raw_temp;
++}
++
++static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
++{
++	struct lvts_sensor *lvts_sensor = tz->devdata;
++	void __iomem *msr = lvts_sensor->msr;
++	u32 value;
++
++	/*
++	 * Measurement registers:
++	 *
++	 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
++	 *
++	 * Bits:
++	 *
++	 * 32-17: Unused
++	 * 16	: Valid temperature
++	 * 15-0	: Raw temperature
++	 */
++	value = readl(msr);
++
++	/*
++	 * As the thermal zone temperature will read before the
++	 * hardware sensor is fully initialized, we have to check the
++	 * validity of the temperature returned when reading the
++	 * measurement register. The thermal controller will set the
++	 * valid bit temperature only when it is totally initialized.
++	 *
++	 * Otherwise, we may end up with garbage values out of the
++	 * functionning temperature and directly jump to a system
++	 * shutdown.
++	 */
++	if (!(value & BIT(16)))
++		return -EAGAIN;
++
++	*temp = lvts_raw_to_temp(value & 0xFFFF);
++
++	return 0;
++}
++
++static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
++{
++	struct lvts_sensor *lvts_sensor = tz->devdata;
++	void __iomem *base = lvts_sensor->base;
++	u32 raw_low = lvts_temp_to_raw(low);
++	u32 raw_high = lvts_temp_to_raw(high);
++
++	/*
++	 * Hot to normal temperature threshold
++	 *
++	 * LVTS_H2NTHRE
++	 *
++	 * Bits:
++	 *
++	 * 14-0 : Raw temperature for threshold
++	 */
++	if (low != -INT_MAX) {
++		dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
++		writel(raw_low, LVTS_H2NTHRE(base));
++	}
++
++	/*
++	 * Hot temperature threshold
++	 *
++	 * LVTS_HTHRE
++	 *
++	 * Bits:
++	 *
++	 * 14-0 : Raw temperature for threshold
++	 */
++	dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
++	writel(raw_high, LVTS_HTHRE(base));
++
++	return 0;
++}
++
++static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
++{
++	irqreturn_t iret = IRQ_NONE;
++	u32 value;
++	u32 masks[] = {
++		LVTS_INT_SENSOR0,
++		LVTS_INT_SENSOR1,
++		LVTS_INT_SENSOR2,
++		LVTS_INT_SENSOR3
++	};
++	int i;
++
++	/*
++	 * Interrupt monitoring status
++	 *
++	 * LVTS_MONINTST
++	 *
++	 * Bits:
++	 *
++	 * 31 : Interrupt for stage 3
++	 * 30 : Interrupt for stage 2
++	 * 29 : Interrupt for state 1
++	 * 28 : Interrupt using filter on sensor 3
++	 *
++	 * 27 : Interrupt using immediate on sensor 3
++	 * 26 : Interrupt normal to hot on sensor 3
++	 * 25 : Interrupt high offset on sensor 3
++	 * 24 : Interrupt low offset on sensor 3
++	 *
++	 * 23 : Interrupt hot threshold on sensor 3
++	 * 22 : Interrupt cold threshold on sensor 3
++	 * 21 : Interrupt using filter on sensor 2
++	 * 20 : Interrupt using filter on sensor 1
++	 *
++	 * 19 : Interrupt using filter on sensor 0
++	 * 18 : Interrupt using immediate on sensor 2
++	 * 17 : Interrupt using immediate on sensor 1
++	 * 16 : Interrupt using immediate on sensor 0
++	 *
++	 * 15 : Interrupt device access timeout interrupt
++	 * 14 : Interrupt normal to hot on sensor 2
++	 * 13 : Interrupt high offset interrupt on sensor 2
++	 * 12 : Interrupt low offset interrupt on sensor 2
++	 *
++	 * 11 : Interrupt hot threshold on sensor 2
++	 * 10 : Interrupt cold threshold on sensor 2
++	 *  9 : Interrupt normal to hot on sensor 1
++	 *  8 : Interrupt high offset interrupt on sensor 1
++	 *
++	 *  7 : Interrupt low offset interrupt on sensor 1
++	 *  6 : Interrupt hot threshold on sensor 1
++	 *  5 : Interrupt cold threshold on sensor 1
++	 *  4 : Interrupt normal to hot on sensor 0
++	 *
++	 *  3 : Interrupt high offset interrupt on sensor 0
++	 *  2 : Interrupt low offset interrupt on sensor 0
++	 *  1 : Interrupt hot threshold on sensor 0
++	 *  0 : Interrupt cold threshold on sensor 0
++	 *
++	 * We are interested in the sensor(s) responsible of the
++	 * interrupt event. We update the thermal framework with the
++	 * thermal zone associated with the sensor. The framework will
++	 * take care of the rest whatever the kind of interrupt, we
++	 * are only interested in which sensor raised the interrupt.
++	 *
++	 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
++	 *                  => 0x1FC00000
++	 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
++	 *                  => 0x00247C00
++	 * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
++	 *                  => 0X000881F0
++	 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
++	 *                  => 0x0009001F
++	 */
++	value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
++
++	/*
++	 * Let's figure out which sensors raised the interrupt
++	 *
++	 * NOTE: the masks array must be ordered with the index
++	 * corresponding to the sensor id eg. index=0, mask for
++	 * sensor0.
++	 */
++	for (i = 0; i < ARRAY_SIZE(masks); i++) {
++
++		if (!(value & masks[i]))
++			continue;
++
++		thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
++					   THERMAL_TRIP_VIOLATED);
++		iret = IRQ_HANDLED;
++	}
++
++	/*
++	 * Write back to clear the interrupt status (W1C)
++	 */
++	writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
++
++	return iret;
++}
++
++/*
++ * Temperature interrupt handler. Even if the driver supports more
++ * interrupt modes, we use the interrupt when the temperature crosses
++ * the hot threshold the way up and the way down (modulo the
++ * hysteresis).
++ *
++ * Each thermal domain has a couple of interrupts, one for hardware
++ * reset and another one for all the thermal events happening on the
++ * different sensors.
++ *
++ * The interrupt is configured for thermal events when crossing the
++ * hot temperature limit. At each interrupt, we check in every
++ * controller if there is an interrupt pending.
++ */
++static irqreturn_t lvts_irq_handler(int irq, void *data)
++{
++	struct lvts_domain *lvts_td = data;
++	irqreturn_t aux, iret = IRQ_NONE;
++	int i;
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
++
++		aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
++		if (aux != IRQ_HANDLED)
++			continue;
++
++		iret = IRQ_HANDLED;
++	}
++
++	return iret;
++}
++
++static struct thermal_zone_device_ops lvts_ops = {
++	.get_temp = lvts_get_temp,
++	.set_trips = lvts_set_trips,
++};
++
++static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
++					const struct lvts_ctrl_data *lvts_ctrl_data)
++{
++	struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
++	void __iomem *msr_regs[] = {
++		LVTS_MSR0(lvts_ctrl->base),
++		LVTS_MSR1(lvts_ctrl->base),
++		LVTS_MSR2(lvts_ctrl->base),
++		LVTS_MSR3(lvts_ctrl->base)
++	};
++
++	void __iomem *imm_regs[] = {
++		LVTS_IMMD0(lvts_ctrl->base),
++		LVTS_IMMD1(lvts_ctrl->base),
++		LVTS_IMMD2(lvts_ctrl->base),
++		LVTS_IMMD3(lvts_ctrl->base)
++	};
++
++	int i;
++
++	for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) {
++
++		int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
++
++		/*
++		 * At this point, we don't know which id matches which
++		 * sensor. Let's set arbitrally the id from the index.
++		 */
++		lvts_sensor[i].id = i;
++
++		/*
++		 * The thermal zone registration will set the trip
++		 * point interrupt in the thermal controller
++		 * register. But this one will be reset in the
++		 * initialization after. So we need to post pone the
++		 * thermal zone creation after the controller is
++		 * setup. For this reason, we store the device tree
++		 * node id from the data in the sensor structure
++		 */
++		lvts_sensor[i].dt_id = dt_id;
++
++		/*
++		 * We assign the base address of the thermal
++		 * controller as a back pointer. So it will be
++		 * accessible from the different thermal framework ops
++		 * as we pass the lvts_sensor pointer as thermal zone
++		 * private data.
++		 */
++		lvts_sensor[i].base = lvts_ctrl->base;
++
++		/*
++		 * Each sensor has its own register address to read from.
++		 */
++		lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
++			imm_regs[i] : msr_regs[i];
++	};
++
++	lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
++
++	return 0;
++}
++
++/*
++ * The efuse blob values follows the sensor enumeration per thermal
++ * controller. The decoding of the stream is as follow:
++ *
++ *                        <--?-> <----big0 ???---> <-sensor0-> <-0->
++ *                        ------------------------------------------
++ * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
++ *                        ------------------------------------------
++ *
++ *                        <--sensor1--><-0-> <----big1 ???---> <-sen
++ *                        ------------------------------------------
++ *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
++ *                        ------------------------------------------
++ *
++ *                        sor0-> <-0-> <-sensor1-> <-0-> ..........
++ *                        ------------------------------------------
++ *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
++ *                        ------------------------------------------
++ *
++ * And so on ...
++ *
++ * The data description gives the offset of the calibration data in
++ * this bytes stream for each sensor.
++ *
++ * Each thermal controller can handle up to 4 sensors max, we don't
++ * care if there are less as the array of calibration is sized to 4
++ * anyway. The unused sensor slot will be zeroed.
++ */
++static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
++					const struct lvts_ctrl_data *lvts_ctrl_data,
++					u8 *efuse_calibration)
++{
++	int i;
++
++	for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++)
++		memcpy(&lvts_ctrl->calibration[i],
++		       efuse_calibration + lvts_ctrl_data->cal_offset[i], 2);
++
++	return 0;
++}
++
++/*
++ * The efuse bytes stream can be split into different chunk of
++ * nvmems. This function reads and concatenate those into a single
++ * buffer so it can be read sequentially when initializing the
++ * calibration data.
++ */
++static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
++					const struct lvts_data *lvts_data)
++{
++	struct device_node *np = dev_of_node(dev);
++	struct nvmem_cell *cell;
++	struct property *prop;
++	const char *cell_name;
++
++	of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
++		size_t len;
++		u8 *efuse;
++
++		cell = of_nvmem_cell_get(np, cell_name);
++		if (IS_ERR(cell)) {
++			dev_err(dev, "Failed to get cell '%s'\n", cell_name);
++			return PTR_ERR(cell);
++		}
++
++		efuse = nvmem_cell_read(cell, &len);
++
++		nvmem_cell_put(cell);
++
++		if (IS_ERR(efuse)) {
++			dev_err(dev, "Failed to read cell '%s'\n", cell_name);
++			return PTR_ERR(efuse);
++		}
++
++		lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
++					       lvts_td->calib_len + len, GFP_KERNEL);
++		if (!lvts_td->calib)
++			return -ENOMEM;
++
++		memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
++
++		lvts_td->calib_len += len;
++
++		kfree(efuse);
++	}
++
++	return 0;
++}
++
++static int lvts_golden_temp_init(struct device *dev, u32 *value)
++{
++	u32 gt;
++
++	gt = (*value) >> 24;
++
++	if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
++		golden_temp = gt;
++
++	coeff_b = golden_temp * 500 + LVTS_COEFF_B;
++
++	return 0;
++}
++
++static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
++					const struct lvts_data *lvts_data)
++{
++	size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
++	struct lvts_ctrl *lvts_ctrl;
++	int i, ret;
++
++	/*
++	 * Create the calibration bytes stream from efuse data
++	 */
++	ret = lvts_calibration_read(dev, lvts_td, lvts_data);
++	if (ret)
++		return ret;
++
++	/*
++	 * The golden temp information is contained in the first chunk
++	 * of efuse data.
++	 */
++	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
++	if (ret)
++		return ret;
++
++	lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
++	if (!lvts_ctrl)
++		return -ENOMEM;
++
++	for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
++
++		lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
++
++		ret = lvts_sensor_init(dev, &lvts_ctrl[i],
++				       &lvts_data->lvts_ctrl[i]);
++		if (ret)
++			return ret;
++
++		ret = lvts_calibration_init(dev, &lvts_ctrl[i],
++					    &lvts_data->lvts_ctrl[i],
++					    lvts_td->calib);
++		if (ret)
++			return ret;
++
++		/*
++		 * The mode the ctrl will use to read the temperature
++		 * (filtered or immediate)
++		 */
++		lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
++
++		/*
++		 * The temperature to raw temperature must be done
++		 * after initializing the calibration.
++		 */
++		lvts_ctrl[i].hw_tshut_raw_temp =
++			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
++	}
++
++	/*
++	 * We no longer need the efuse bytes stream, let's free it
++	 */
++	devm_kfree(dev, lvts_td->calib);
++
++	lvts_td->lvts_ctrl = lvts_ctrl;
++	lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
++
++	return 0;
++}
++
++/*
++ * At this point the configuration register is the only place in the
++ * driver where we write multiple values. Per hardware constraint,
++ * each write in the configuration register must be separated by a
++ * delay of 2 us.
++ */
++static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
++{
++	int i;
++
++	/*
++	 * Configuration register
++	 */
++	for (i = 0; i < nr_cmds; i++) {
++		writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
++		usleep_range(2, 4);
++	}
++}
++
++static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
++{
++	/*
++	 * LVTS_PROTCTL : Thermal Protection Sensor Selection
++	 *
++	 * Bits:
++	 *
++	 * 19-18 : Sensor to base the protection on
++	 * 17-16 : Strategy:
++	 *         00 : Average of 4 sensors
++	 *         01 : Max of 4 sensors
++	 *         10 : Selected sensor with bits 19-18
++	 *         11 : Reserved
++	 */
++	writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base));
++
++	/*
++	 * LVTS_PROTTA : Stage 1 temperature threshold
++	 * LVTS_PROTTB : Stage 2 temperature threshold
++	 * LVTS_PROTTC : Stage 3 temperature threshold
++	 *
++	 * Bits:
++	 *
++	 * 14-0: Raw temperature threshold
++	 *
++	 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
++	 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
++	 */
++	writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base));
++
++	/*
++	 * LVTS_MONINT : Interrupt configuration register
++	 *
++	 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
++	 * register, except we set the bits to enable the interrupt.
++	 */
++	writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
++
++	return 0;
++}
++
++static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
++{
++	int ret;
++
++	ret = reset_control_assert(reset);
++	if (ret)
++		return ret;
++
++	return reset_control_deassert(reset);
++}
++
++/*
++ * Enable or disable the clocks of a specified thermal controller
++ */
++static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
++{
++	/*
++	 * LVTS_CLKEN : Internal LVTS clock
++	 *
++	 * Bits:
++	 *
++	 * 0 : enable / disable clock
++	 */
++	writel(enable, LVTS_CLKEN(lvts_ctrl->base));
++
++	return 0;
++}
++
++static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
++
++	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
++
++	/*
++	 * LVTS_ID : Get ID and status of the thermal controller
++	 *
++	 * Bits:
++	 *
++	 * 0-5	: thermal controller id
++	 *   7	: thermal controller connection is valid
++	 */
++	id = readl(LVTS_ID(lvts_ctrl->base));
++	if (!(id & BIT(7)))
++		return -EIO;
++
++	return 0;
++}
++
++static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	/*
++	 * Write device mask: 0xC1030000
++	 */
++	u32 cmds[] = {
++		0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
++		0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
++		0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
++		0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
++	};
++
++	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
++
++	return 0;
++}
++
++static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	int i;
++	void __iomem *lvts_edata[] = {
++		LVTS_EDATA00(lvts_ctrl->base),
++		LVTS_EDATA01(lvts_ctrl->base),
++		LVTS_EDATA02(lvts_ctrl->base),
++		LVTS_EDATA03(lvts_ctrl->base)
++	};
++
++	/*
++	 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
++	 *
++	 * Bits:
++	 *
++	 * 20-0 : Efuse value for normalization data
++	 */
++	for (i = 0; i < LVTS_SENSOR_MAX; i++)
++		writel(lvts_ctrl->calibration[i], lvts_edata[i]);
++
++	return 0;
++}
++
++static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	u32 value;
++
++	/*
++	 * LVTS_TSSEL : Sensing point index numbering
++	 *
++	 * Bits:
++	 *
++	 * 31-24: ADC Sense 3
++	 * 23-16: ADC Sense 2
++	 * 15-8	: ADC Sense 1
++	 * 7-0	: ADC Sense 0
++	 */
++	value = LVTS_TSSEL_CONF;
++	writel(value, LVTS_TSSEL(lvts_ctrl->base));
++
++	/*
++	 * LVTS_CALSCALE : ADC voltage round
++	 */
++	value = 0x300;
++	value = LVTS_CALSCALE_CONF;
++
++	/*
++	 * LVTS_MSRCTL0 : Sensor filtering strategy
++	 *
++	 * Filters:
++	 *
++	 * 000 : One sample
++	 * 001 : Avg 2 samples
++	 * 010 : 4 samples, drop min and max, avg 2 samples
++	 * 011 : 6 samples, drop min and max, avg 4 samples
++	 * 100 : 10 samples, drop min and max, avg 8 samples
++	 * 101 : 18 samples, drop min and max, avg 16 samples
++	 *
++	 * Bits:
++	 *
++	 * 0-2  : Sensor0 filter
++	 * 3-5  : Sensor1 filter
++	 * 6-8  : Sensor2 filter
++	 * 9-11 : Sensor3 filter
++	 */
++	value = LVTS_HW_FILTER << 9 |  LVTS_HW_FILTER << 6 |
++			LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
++	writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
++
++	/*
++	 * LVTS_MSRCTL1 : Measurement control
++	 *
++	 * Bits:
++	 *
++	 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
++	 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
++	 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
++	 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
++	 *
++	 * That configuration will ignore the filtering and the delays
++	 * introduced below in MONCTL1 and MONCTL2
++	 */
++	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
++		value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
++		writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
++	}
++
++	/*
++	 * LVTS_MONCTL1 : Period unit and group interval configuration
++	 *
++	 * The clock source of LVTS thermal controller is 26MHz.
++	 *
++	 * The period unit is a time base for all the interval delays
++	 * specified in the registers. By default we use 12. The time
++	 * conversion is done by multiplying by 256 and 1/26.10^6
++	 *
++	 * An interval delay multiplied by the period unit gives the
++	 * duration in seconds.
++	 *
++	 * - Filter interval delay is a delay between two samples of
++	 * the same sensor.
++	 *
++	 * - Sensor interval delay is a delay between two samples of
++	 * different sensors.
++	 *
++	 * - Group interval delay is a delay between different rounds.
++	 *
++	 * For example:
++	 *     If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
++	 *     and two sensors, TS1 and TS2, are in a LVTS thermal controller
++	 *     and then
++	 *     Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
++	 *     Filter interval delay = 1 * Period unit = 118.149us
++	 *     Sensor interval delay = 2 * Period unit = 236.298us
++	 *     Group interval delay = 1 * Period unit = 118.149us
++	 *
++	 *     TS1    TS1 ... TS1    TS2    TS2 ... TS2    TS1...
++	 *        <--> Filter interval delay
++	 *                       <--> Sensor interval delay
++	 *                                             <--> Group interval delay
++	 * Bits:
++	 *      29 - 20 : Group interval
++	 *      16 - 13 : Send a single interrupt when crossing the hot threshold (1)
++	 *                or an interrupt everytime the hot threshold is crossed (0)
++	 *       9 - 0  : Period unit
++	 *
++	 */
++	value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
++	writel(value, LVTS_MONCTL1(lvts_ctrl->base));
++
++	/*
++	 * LVTS_MONCTL2 : Filtering and sensor interval
++	 *
++	 * Bits:
++	 *
++	 *      25-16 : Interval unit in PERIOD_UNIT between sample on
++	 *              the same sensor, filter interval
++	 *       9-0  : Interval unit in PERIOD_UNIT between each sensor
++	 *
++	 */
++	value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
++	writel(value, LVTS_MONCTL2(lvts_ctrl->base));
++
++	return lvts_irq_init(lvts_ctrl);
++}
++
++static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
++{
++	struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
++	struct thermal_zone_device *tz;
++	u32 sensor_map = 0;
++	int i;
++
++	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
++
++		int dt_id = lvts_sensors[i].dt_id;
++
++		tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
++						   &lvts_ops);
++		if (IS_ERR(tz)) {
++			/*
++			 * This thermal zone is not described in the
++			 * device tree. It is not an error from the
++			 * thermal OF code POV, we just continue.
++			 */
++			if (PTR_ERR(tz) == -ENODEV)
++				continue;
++
++			return PTR_ERR(tz);
++		}
++
++		/*
++		 * The thermal zone pointer will be needed in the
++		 * interrupt handler, we store it in the sensor
++		 * structure. The thermal domain structure will be
++		 * passed to the interrupt handler private data as the
++		 * interrupt is shared for all the controller
++		 * belonging to the thermal domain.
++		 */
++		lvts_sensors[i].tz = tz;
++
++		/*
++		 * This sensor was correctly associated with a thermal
++		 * zone, let's set the corresponding bit in the sensor
++		 * map, so we can enable the temperature monitoring in
++		 * the hardware thermal controller.
++		 */
++		sensor_map |= BIT(i);
++	}
++
++	/*
++	 * Bits:
++	 *      9: Single point access flow
++	 *    0-3: Enable sensing point 0-3
++	 *
++	 * The initialization of the thermal zones give us
++	 * which sensor point to enable. If any thermal zone
++	 * was not described in the device tree, it won't be
++	 * enabled here in the sensor map.
++	 */
++	writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
++
++	return 0;
++}
++
++static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
++					const struct lvts_data *lvts_data)
++{
++	struct lvts_ctrl *lvts_ctrl;
++	int i, ret;
++
++	ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
++	if (ret)
++		return ret;
++
++	ret = lvts_domain_reset(dev, lvts_td->reset);
++	if (ret) {
++		dev_dbg(dev, "Failed to reset domain");
++		return ret;
++	}
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
++
++		lvts_ctrl = &lvts_td->lvts_ctrl[i];
++
++		/*
++		 * Initialization steps:
++		 *
++		 * - Enable the clock
++		 * - Connect to the LVTS
++		 * - Initialize the LVTS
++		 * - Prepare the calibration data
++		 * - Select monitored sensors
++		 * [ Configure sampling ]
++		 * [ Configure the interrupt ]
++		 * - Start measurement
++		 */
++		ret = lvts_ctrl_set_enable(lvts_ctrl, true);
++		if (ret) {
++			dev_dbg(dev, "Failed to enable LVTS clock");
++			return ret;
++		}
++
++		ret = lvts_ctrl_connect(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to connect to LVTS controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_initialize(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to initialize controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to calibrate controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_configure(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to configure controller");
++			return ret;
++		}
++
++		ret = lvts_ctrl_start(dev, lvts_ctrl);
++		if (ret) {
++			dev_dbg(dev, "Failed to start controller");
++			return ret;
++		}
++	}
++
++	return lvts_debugfs_init(dev, lvts_td);
++}
++
++static int lvts_probe(struct platform_device *pdev)
++{
++	const struct lvts_data *lvts_data;
++	struct lvts_domain *lvts_td;
++	struct device *dev = &pdev->dev;
++	struct resource *res;
++	int irq, ret;
++
++	lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
++	if (!lvts_td)
++		return -ENOMEM;
++
++	lvts_data = of_device_get_match_data(dev);
++
++	lvts_td->clk = devm_clk_get_enabled(dev, NULL);
++	if (IS_ERR(lvts_td->clk))
++		return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
++
++	res = platform_get_mem_or_io(pdev, 0);
++	if (!res)
++		return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
++
++	lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
++	if (IS_ERR(lvts_td->base))
++		return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
++
++	lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
++	if (IS_ERR(lvts_td->reset))
++		return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
++
++	irq = platform_get_irq(pdev, 0);
++	if (irq < 0)
++		return dev_err_probe(dev, irq, "No irq resource\n");
++
++	ret = lvts_domain_init(dev, lvts_td, lvts_data);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
++
++	/*
++	 * At this point the LVTS is initialized and enabled. We can
++	 * safely enable the interrupt.
++	 */
++	ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
++					IRQF_ONESHOT, dev_name(dev), lvts_td);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to request interrupt\n");
++
++	platform_set_drvdata(pdev, lvts_td);
++
++	return 0;
++}
++
++static int lvts_remove(struct platform_device *pdev)
++{
++	struct lvts_domain *lvts_td;
++	int i;
++
++	lvts_td = platform_get_drvdata(pdev);
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
++
++	lvts_debugfs_exit(lvts_td);
++
++	return 0;
++}
++
++static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
++	{
++		.cal_offset = { 0x04, 0x07 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_MCU_BIG_CPU0 },
++			{ .dt_id = MT8195_MCU_BIG_CPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x0d, 0x10 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_MCU_BIG_CPU2 },
++			{ .dt_id = MT8195_MCU_BIG_CPU3 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_MCU_LITTLE_CPU0 },
++			{ .dt_id = MT8195_MCU_LITTLE_CPU1 },
++			{ .dt_id = MT8195_MCU_LITTLE_CPU2 },
++			{ .dt_id = MT8195_MCU_LITTLE_CPU3 }
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	}
++};
++
++static const struct lvts_data mt8195_lvts_mcu_data = {
++	.lvts_ctrl	= mt8195_lvts_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_data_ctrl),
++};
++
++static const struct of_device_id lvts_of_match[] = {
++	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
++	{},
++};
++MODULE_DEVICE_TABLE(of, lvts_of_match);
++
++static struct platform_driver lvts_driver = {
++	.probe = lvts_probe,
++	.remove = lvts_remove,
++	.driver = {
++		.name = "mtk-lvts-thermal",
++		.of_match_table = lvts_of_match,
++	},
++};
++module_platform_driver(lvts_driver);
++
++MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
++MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
new file mode 100644
index 0000000000..b6a5f64090
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
@@ -0,0 +1,186 @@
+From 498e2f7a6e69dcbca24715de2b4b97569fdfeff4 Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Thu, 9 Feb 2023 11:56:24 +0100
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controllers
+
+Add LVTS thermal controllers dt-binding definition for mt8192 and mt8195.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230209105628.50294-3-bchihi@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ .../thermal/mediatek,lvts-thermal.yaml        | 142 ++++++++++++++++++
+ .../thermal/mediatek,lvts-thermal.h           |  19 +++
+ 2 files changed, 161 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
+ create mode 100644 include/dt-bindings/thermal/mediatek,lvts-thermal.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
+@@ -0,0 +1,142 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek SoC Low Voltage Thermal Sensor (LVTS)
++
++maintainers:
++  - Balsam CHIHI <bchihi@baylibre.com>
++
++description: |
++  LVTS is a thermal management architecture composed of three subsystems,
++  a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
++  a Converter - Low Voltage Thermal Sensor converter (LVTS), and
++  a Digital controller (LVTS_CTRL).
++
++properties:
++  compatible:
++    enum:
++      - mediatek,mt8192-lvts-ap
++      - mediatek,mt8192-lvts-mcu
++      - mediatek,mt8195-lvts-ap
++      - mediatek,mt8195-lvts-mcu
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    maxItems: 1
++
++  resets:
++    maxItems: 1
++    description: LVTS reset for clearing temporary data on AP/MCU.
++
++  nvmem-cells:
++    minItems: 1
++    items:
++      - description: Calibration eFuse data 1 for LVTS
++      - description: Calibration eFuse data 2 for LVTS
++
++  nvmem-cell-names:
++    minItems: 1
++    items:
++      - const: lvts-calib-data-1
++      - const: lvts-calib-data-2
++
++  "#thermal-sensor-cells":
++    const: 1
++
++allOf:
++  - $ref: thermal-sensor.yaml#
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - mediatek,mt8192-lvts-ap
++              - mediatek,mt8192-lvts-mcu
++    then:
++      properties:
++        nvmem-cells:
++          maxItems: 1
++
++        nvmem-cell-names:
++          maxItems: 1
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - mediatek,mt8195-lvts-ap
++              - mediatek,mt8195-lvts-mcu
++    then:
++      properties:
++        nvmem-cells:
++          minItems: 2
++
++        nvmem-cell-names:
++          minItems: 2
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - resets
++  - nvmem-cells
++  - nvmem-cell-names
++  - "#thermal-sensor-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/clock/mt8195-clk.h>
++    #include <dt-bindings/reset/mt8195-resets.h>
++    #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
++
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      lvts_mcu: thermal-sensor@11278000 {
++        compatible = "mediatek,mt8195-lvts-mcu";
++        reg = <0 0x11278000 0 0x1000>;
++        interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
++        clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
++        resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
++        nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
++        nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
++        #thermal-sensor-cells = <1>;
++      };
++    };
++
++    thermal_zones: thermal-zones {
++      cpu0-thermal {
++        polling-delay = <1000>;
++        polling-delay-passive = <250>;
++        thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
++
++        trips {
++          cpu0_alert: trip-alert {
++            temperature = <85000>;
++            hysteresis = <2000>;
++            type = "passive";
++          };
++
++          cpu0_crit: trip-crit {
++            temperature = <100000>;
++            hysteresis = <2000>;
++            type = "critical";
++          };
++        };
++      };
++    };
+--- /dev/null
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -0,0 +1,19 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Balsam CHIHI <bchihi@baylibre.com>
++ */
++
++#ifndef __MEDIATEK_LVTS_DT_H
++#define __MEDIATEK_LVTS_DT_H
++
++#define MT8195_MCU_BIG_CPU0     0
++#define MT8195_MCU_BIG_CPU1     1
++#define MT8195_MCU_BIG_CPU2     2
++#define MT8195_MCU_BIG_CPU3     3
++#define MT8195_MCU_LITTLE_CPU0  4
++#define MT8195_MCU_LITTLE_CPU1  5
++#define MT8195_MCU_LITTLE_CPU2  6
++#define MT8195_MCU_LITTLE_CPU3  7
++
++#endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch
new file mode 100644
index 0000000000..efb0d8b64f
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch
@@ -0,0 +1,35 @@
+From 05aaa7fdb0736262e224369b9b9f1410320fc71b Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 7 Mar 2023 16:45:21 +0100
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add AP domain to LVTS thermal
+ controllers for mt8195
+
+Add AP Domain to LVTS thermal controllers dt-binding definition for mt8195.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230307154524.118541-2-bchihi@baylibre.com
+---
+ include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -16,4 +16,14 @@
+ #define MT8195_MCU_LITTLE_CPU2  6
+ #define MT8195_MCU_LITTLE_CPU3  7
+ 
++#define MT8195_AP_VPU0  8
++#define MT8195_AP_VPU1  9
++#define MT8195_AP_GPU0  10
++#define MT8195_AP_GPU1  11
++#define MT8195_AP_VDEC  12
++#define MT8195_AP_IMG   13
++#define MT8195_AP_INFRA 14
++#define MT8195_AP_CAM0  15
++#define MT8195_AP_CAM1  16
++
+ #endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch
new file mode 100644
index 0000000000..c68969321e
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch
@@ -0,0 +1,65 @@
+From a6ff3c0021468721b96e84892a8cae24bde8d65f Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:29 +0100
+Subject: [PATCH] thermal/core: Add a thermal zone 'devdata' accessor
+
+The thermal zone device structure is exposed to the different drivers
+and obviously they access the internals while that should be
+restricted to the core thermal code.
+
+In order to self-encapsulate the thermal core code, we need to prevent
+the drivers accessing directly the thermal zone structure and provide
+accessor functions to deal with.
+
+Provide an accessor to the 'devdata' structure and make use of it in
+the different drivers.
+
+No functional changes intended.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/thermal_core.c | 6 ++++++
+ include/linux/thermal.h        | 7 +++++++
+ 2 files changed, 13 insertions(+)
+
+--- a/drivers/thermal/thermal_core.c
++++ b/drivers/thermal/thermal_core.c
+@@ -1346,6 +1346,12 @@ struct thermal_zone_device *thermal_zone
+ }
+ EXPORT_SYMBOL_GPL(thermal_zone_device_register);
+ 
++void *thermal_zone_device_priv(struct thermal_zone_device *tzd)
++{
++	return tzd->devdata;
++}
++EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
++
+ /**
+  * thermal_zone_device_unregister - removes the registered thermal zone device
+  * @tz: the thermal zone device to remove
+--- a/include/linux/thermal.h
++++ b/include/linux/thermal.h
+@@ -346,6 +346,8 @@ thermal_zone_device_register_with_trips(
+ 					void *, struct thermal_zone_device_ops *,
+ 					struct thermal_zone_params *, int, int);
+ 
++void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
++
+ int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
+ 				     struct thermal_cooling_device *,
+ 				     unsigned long, unsigned long,
+@@ -417,6 +419,11 @@ static inline int thermal_zone_get_offse
+ 		struct thermal_zone_device *tz)
+ { return -ENODEV; }
+ 
++static inline void *thermal_zone_device_priv(struct thermal_zone_device *tz)
++{
++	return NULL;
++}
++
+ static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
+ { return -ENODEV; }
+ 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch
new file mode 100644
index 0000000000..66d3c9e302
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch
@@ -0,0 +1,55 @@
+From 072e35c98806100182c0a7263cf4cba09ce43463 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:38 +0100
+Subject: [PATCH] thermal/core: Add thermal_zone_device structure 'type'
+ accessor
+
+The thermal zone device structure is exposed via the exported
+thermal.h header. This structure should stay private the thermal core
+code. In order to encapsulate the structure, let's add an accessor to
+get the 'type' of the thermal zone.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/thermal_core.c | 6 ++++++
+ include/linux/thermal.h        | 6 ++++++
+ 2 files changed, 12 insertions(+)
+
+--- a/drivers/thermal/thermal_core.c
++++ b/drivers/thermal/thermal_core.c
+@@ -1352,6 +1352,12 @@ void *thermal_zone_device_priv(struct th
+ }
+ EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
+ 
++const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
++{
++	return tzd->type;
++}
++EXPORT_SYMBOL_GPL(thermal_zone_device_type);
++
+ /**
+  * thermal_zone_device_unregister - removes the registered thermal zone device
+  * @tz: the thermal zone device to remove
+--- a/include/linux/thermal.h
++++ b/include/linux/thermal.h
+@@ -347,6 +347,7 @@ thermal_zone_device_register_with_trips(
+ 					struct thermal_zone_params *, int, int);
+ 
+ void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
++const char *thermal_zone_device_type(struct thermal_zone_device *tzd);
+ 
+ int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
+ 				     struct thermal_cooling_device *,
+@@ -423,6 +424,11 @@ static inline void *thermal_zone_device_
+ {
+ 	return NULL;
+ }
++
++static inline const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
++{
++	return NULL;
++}
+ 
+ static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
+ { return -ENODEV; }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch
new file mode 100644
index 0000000000..57bc910d3e
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch
@@ -0,0 +1,74 @@
+From 7d78bab533eb9aa0e5240e25a204e8f416723ed6 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:30 +0100
+Subject: [PATCH 07/42] thermal/core: Use the thermal zone 'devdata' accessor
+ in thermal located drivers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The thermal zone device structure is exposed to the different drivers
+and obviously they access the internals while that should be
+restricted to the core thermal code.
+
+In order to self-encapsulate the thermal core code, we need to prevent
+the drivers accessing directly the thermal zone structure and provide
+accessor functions to deal with.
+
+Use the devdata accessor introduced in the previous patch.
+
+No functional changes intended.
+
+[skipped drivers not relevant for mediatek target]
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> #R-Car
+Acked-by: Mark Brown <broonie@kernel.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc and lvts
+Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek lvts
+Reviewed-by: Adam Ward <DLG-Adam.Ward.opensource@dm.renesas.com> #da9062
+Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>  #spread
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com> #Broadcom
+Reviewed-by: Dhruva Gole <d-gole@ti.com> # K3 bandgap
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
+Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> #uniphier
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c           |  2 +-
+ drivers/thermal/mediatek/lvts_thermal.c             |  4 ++--
+ 43 files changed, 71 insertions(+), 73 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -763,7 +763,7 @@ static int mtk_thermal_bank_temperature(
+ 
+ static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
+ {
+-	struct mtk_thermal *mt = tz->devdata;
++	struct mtk_thermal *mt = thermal_zone_device_priv(tz);
+ 	int i;
+ 	int tempmax = INT_MIN;
+ 
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -252,7 +252,7 @@ static u32 lvts_temp_to_raw(int temperat
+ 
+ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
+ {
+-	struct lvts_sensor *lvts_sensor = tz->devdata;
++	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *msr = lvts_sensor->msr;
+ 	u32 value;
+ 
+@@ -290,7 +290,7 @@ static int lvts_get_temp(struct thermal_
+ 
+ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+-	struct lvts_sensor *lvts_sensor = tz->devdata;
++	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *base = lvts_sensor->base;
+ 	u32 raw_low = lvts_temp_to_raw(low);
+ 	u32 raw_high = lvts_temp_to_raw(high);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch
new file mode 100644
index 0000000000..647b3b0eca
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch
@@ -0,0 +1,201 @@
+From cc9c60e9cfeeac45d63361fa8c085c43c4bdfe3a Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:36 +0100
+Subject: [PATCH 08/42] thermal/hwmon: Use the right device for
+ devm_thermal_add_hwmon_sysfs()
+
+The devres variant of thermal_add_hwmon_sysfs() only takes the thermal
+zone structure pointer as parameter.
+
+Actually, it uses the tz->device to add it in the devres list.
+
+It is preferable to use the device registering the thermal zone
+instead of the thermal zone device itself. That prevents the driver
+accessing the thermal zone structure internals and it is from my POV
+more correct regarding how devm_ is used.
+
+[skipped imx thermal which did not apply cleanly and irrelevant on
+mediatek target]
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> #amlogic_thermal
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/amlogic_thermal.c                  | 2 +-
+ drivers/thermal/imx_sc_thermal.c                   | 2 +-
+ drivers/thermal/k3_bandgap.c                       | 2 +-
+ drivers/thermal/mediatek/auxadc_thermal.c          | 2 +-
+ drivers/thermal/qcom/qcom-spmi-adc-tm5.c           | 2 +-
+ drivers/thermal/qcom/qcom-spmi-temp-alarm.c        | 2 +-
+ drivers/thermal/qcom/tsens.c                       | 2 +-
+ drivers/thermal/qoriq_thermal.c                    | 2 +-
+ drivers/thermal/sun8i_thermal.c                    | 2 +-
+ drivers/thermal/tegra/tegra30-tsensor.c            | 2 +-
+ drivers/thermal/thermal_hwmon.c                    | 4 ++--
+ drivers/thermal/thermal_hwmon.h                    | 4 ++--
+ drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
+ 13 files changed, 15 insertions(+), 15 deletions(-)
+
+--- a/drivers/thermal/amlogic_thermal.c
++++ b/drivers/thermal/amlogic_thermal.c
+@@ -286,7 +286,7 @@ static int amlogic_thermal_probe(struct
+ 		return ret;
+ 	}
+ 
+-	if (devm_thermal_add_hwmon_sysfs(pdata->tzd))
++	if (devm_thermal_add_hwmon_sysfs(&pdev->dev, pdata->tzd))
+ 		dev_warn(&pdev->dev, "Failed to add hwmon sysfs attributes\n");
+ 
+ 	ret = amlogic_thermal_initialize(pdata);
+--- a/drivers/thermal/imx_sc_thermal.c
++++ b/drivers/thermal/imx_sc_thermal.c
+@@ -120,7 +120,7 @@ static int imx_sc_thermal_probe(struct p
+ 			return ret;
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(sensor->tzd))
++		if (devm_thermal_add_hwmon_sysfs(&pdev->dev, sensor->tzd))
+ 			dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n");
+ 	}
+ 
+--- a/drivers/thermal/k3_bandgap.c
++++ b/drivers/thermal/k3_bandgap.c
+@@ -222,7 +222,7 @@ static int k3_bandgap_probe(struct platf
+ 			goto err_alloc;
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(data[id].tzd))
++		if (devm_thermal_add_hwmon_sysfs(dev, data[id].tzd))
+ 			dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
+ 	}
+ 
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1210,7 +1210,7 @@ static int mtk_thermal_probe(struct plat
+ 		goto err_disable_clk_peri_therm;
+ 	}
+ 
+-	ret = devm_thermal_add_hwmon_sysfs(tzdev);
++	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
+ 	if (ret)
+ 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
+ 
+--- a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
++++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
+@@ -688,7 +688,7 @@ static int adc_tm5_register_tzd(struct a
+ 			return PTR_ERR(tzd);
+ 		}
+ 		adc_tm->channels[i].tzd = tzd;
+-		if (devm_thermal_add_hwmon_sysfs(tzd))
++		if (devm_thermal_add_hwmon_sysfs(adc_tm->dev, tzd))
+ 			dev_warn(adc_tm->dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 	}
+--- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
++++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
+@@ -460,7 +460,7 @@ static int qpnp_tm_probe(struct platform
+ 		return ret;
+ 	}
+ 
+-	if (devm_thermal_add_hwmon_sysfs(chip->tz_dev))
++	if (devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev))
+ 		dev_warn(&pdev->dev,
+ 			 "Failed to add hwmon sysfs attributes\n");
+ 
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -1056,7 +1056,7 @@ static int tsens_register(struct tsens_p
+ 		if (priv->ops->enable)
+ 			priv->ops->enable(priv, i);
+ 
+-		if (devm_thermal_add_hwmon_sysfs(tzd))
++		if (devm_thermal_add_hwmon_sysfs(priv->dev, tzd))
+ 			dev_warn(priv->dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 	}
+--- a/drivers/thermal/qoriq_thermal.c
++++ b/drivers/thermal/qoriq_thermal.c
+@@ -158,7 +158,7 @@ static int qoriq_tmu_register_tmu_zone(s
+ 			return ret;
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(tzd))
++		if (devm_thermal_add_hwmon_sysfs(dev, tzd))
+ 			dev_warn(dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -468,7 +468,7 @@ static int sun8i_ths_register(struct ths
+ 		if (IS_ERR(tmdev->sensor[i].tzd))
+ 			return PTR_ERR(tmdev->sensor[i].tzd);
+ 
+-		if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
++		if (devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd))
+ 			dev_warn(tmdev->dev,
+ 				 "Failed to add hwmon sysfs attributes\n");
+ 	}
+--- a/drivers/thermal/tegra/tegra30-tsensor.c
++++ b/drivers/thermal/tegra/tegra30-tsensor.c
+@@ -530,7 +530,7 @@ static int tegra_tsensor_register_channe
+ 		return 0;
+ 	}
+ 
+-	if (devm_thermal_add_hwmon_sysfs(tsc->tzd))
++	if (devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd))
+ 		dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n");
+ 
+ 	return 0;
+--- a/drivers/thermal/thermal_hwmon.c
++++ b/drivers/thermal/thermal_hwmon.c
+@@ -255,7 +255,7 @@ static void devm_thermal_hwmon_release(s
+ 	thermal_remove_hwmon_sysfs(*(struct thermal_zone_device **)res);
+ }
+ 
+-int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
++int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
+ {
+ 	struct thermal_zone_device **ptr;
+ 	int ret;
+@@ -272,7 +272,7 @@ int devm_thermal_add_hwmon_sysfs(struct
+ 	}
+ 
+ 	*ptr = tz;
+-	devres_add(&tz->device, ptr);
++	devres_add(dev, ptr);
+ 
+ 	return ret;
+ }
+--- a/drivers/thermal/thermal_hwmon.h
++++ b/drivers/thermal/thermal_hwmon.h
+@@ -17,7 +17,7 @@
+ 
+ #ifdef CONFIG_THERMAL_HWMON
+ int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
+-int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
++int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz);
+ void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz);
+ #else
+ static inline int
+@@ -27,7 +27,7 @@ thermal_add_hwmon_sysfs(struct thermal_z
+ }
+ 
+ static inline int
+-devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
++devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
+ {
+ 	return 0;
+ }
+--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+@@ -182,7 +182,7 @@ int ti_thermal_expose_sensor(struct ti_b
+ 	ti_bandgap_set_sensor_data(bgp, id, data);
+ 	ti_bandgap_write_update_interval(bgp, data->sensor_id, interval);
+ 
+-	if (devm_thermal_add_hwmon_sysfs(data->ti_thermal))
++	if (devm_thermal_add_hwmon_sysfs(bgp->dev, data->ti_thermal))
+ 		dev_warn(bgp->dev, "failed to add hwmon sysfs attributes\n");
+ 
+ 	return 0;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch b/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch
new file mode 100644
index 0000000000..9dedc2cb68
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch
@@ -0,0 +1,79 @@
+From 5a72b8e4bac753e4dc74dc0a1335d120f63df97a Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:37 +0100
+Subject: [PATCH 09/42] thermal: Don't use 'device' internal thermal zone
+ structure field
+
+Some drivers are directly using the thermal zone's 'device' structure
+field.
+
+Use the driver device pointer instead of the thermal zone device when
+it is available.
+
+Remove the traces when they are duplicate with the traces in the core
+code.
+
+[again skipped imx_thermal.c]
+
+Cc: Jean Delvare <jdelvare@suse.com>
+Cc: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek LVTS
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/lvts_thermal.c            | 4 ++--
+ drivers/thermal/thermal_hwmon.c                    | 4 ++--
+ drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -305,7 +305,7 @@ static int lvts_set_trips(struct thermal
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+ 	if (low != -INT_MAX) {
+-		dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
++		pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
+ 		writel(raw_low, LVTS_H2NTHRE(base));
+ 	}
+ 
+@@ -318,7 +318,7 @@ static int lvts_set_trips(struct thermal
+ 	 *
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+-	dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
++	pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
+ 	writel(raw_high, LVTS_HTHRE(base));
+ 
+ 	return 0;
+--- a/drivers/thermal/thermal_hwmon.c
++++ b/drivers/thermal/thermal_hwmon.c
+@@ -220,14 +220,14 @@ void thermal_remove_hwmon_sysfs(struct t
+ 	hwmon = thermal_hwmon_lookup_by_type(tz);
+ 	if (unlikely(!hwmon)) {
+ 		/* Should never happen... */
+-		dev_dbg(&tz->device, "hwmon device lookup failed!\n");
++		dev_dbg(hwmon->device, "hwmon device lookup failed!\n");
+ 		return;
+ 	}
+ 
+ 	temp = thermal_hwmon_lookup_temp(hwmon, tz);
+ 	if (unlikely(!temp)) {
+ 		/* Should never happen... */
+-		dev_dbg(&tz->device, "temperature input lookup failed!\n");
++		dev_dbg(hwmon->device, "temperature input lookup failed!\n");
+ 		return;
+ 	}
+ 
+--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+@@ -43,7 +43,7 @@ static void ti_thermal_work(struct work_
+ 
+ 	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
+ 
+-	dev_dbg(&data->ti_thermal->device, "updated thermal zone %s\n",
++	dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
+ 		data->ti_thermal->type);
+ }
+ 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch
new file mode 100644
index 0000000000..8cec9aba97
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch
@@ -0,0 +1,62 @@
+From 66b3a292d3fc749e8ec7ac5278a17e8a5757ecbc Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:41 +0100
+Subject: [PATCH 10/42] thermal: Use thermal_zone_device_type() accessor
+
+Replace the accesses to 'tz->type' by its accessor version in order to
+self-encapsulate the thermal_zone_device structure.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com> #mlxsw
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/net/ethernet/mellanox/mlxsw/core_thermal.c | 2 +-
+ drivers/thermal/mediatek/lvts_thermal.c            | 6 ++++--
+ drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
+ 3 files changed, 6 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
++++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
+@@ -168,7 +168,7 @@ mlxsw_thermal_module_trips_update(struct
+ 
+ 	if (crit_temp > emerg_temp) {
+ 		dev_warn(dev, "%s : Critical threshold %d is above emergency threshold %d\n",
+-			 tz->tzdev->type, crit_temp, emerg_temp);
++			 thermal_zone_device_type(tz->tzdev), crit_temp, emerg_temp);
+ 		return 0;
+ 	}
+ 
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -305,7 +305,8 @@ static int lvts_set_trips(struct thermal
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+ 	if (low != -INT_MAX) {
+-		pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
++		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
++			 thermal_zone_device_type(tz), low);
+ 		writel(raw_low, LVTS_H2NTHRE(base));
+ 	}
+ 
+@@ -318,7 +319,8 @@ static int lvts_set_trips(struct thermal
+ 	 *
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+-	pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
++	pr_debug("%s: Setting high limit temperature interrupt: %d\n",
++		 thermal_zone_device_type(tz), high);
+ 	writel(raw_high, LVTS_HTHRE(base));
+ 
+ 	return 0;
+--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+@@ -44,7 +44,7 @@ static void ti_thermal_work(struct work_
+ 	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
+ 
+ 	dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
+-		data->ti_thermal->type);
++		thermal_zone_device_type(data->ti_thermal));
+ }
+ 
+ /**
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch
new file mode 100644
index 0000000000..68f41fdd16
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch
@@ -0,0 +1,81 @@
+From f6658c1c4ae98477d6be00495226c0617354fe76 Mon Sep 17 00:00:00 2001
+From: Markus Schneider-Pargmann <msp@baylibre.com>
+Date: Fri, 27 Jan 2023 16:44:43 +0100
+Subject: [PATCH 11/42] thermal/drivers/mediatek: Control buffer enablement
+ tweaks
+
+Add logic in order to be able to turn on the control buffer on MT8365.
+This change now allows to have control buffer support for MTK_THERMAL_V1,
+and it allows to define the register offset, and mask used to enable it.
+
+Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Signed-off-by: Fabien Parent <fparent@baylibre.com>
+Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-2-55a1ae14af74@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 28 +++++++++++++++--------
+ 1 file changed, 19 insertions(+), 9 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -307,6 +307,9 @@ struct mtk_thermal_data {
+ 	bool need_switch_bank;
+ 	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
+ 	enum mtk_thermal_version version;
++	u32 apmixed_buffer_ctl_reg;
++	u32 apmixed_buffer_ctl_mask;
++	u32 apmixed_buffer_ctl_set;
+ };
+ 
+ struct mtk_thermal {
+@@ -560,6 +563,9 @@ static const struct mtk_thermal_data mt7
+ 	.adcpnp = mt7622_adcpnp,
+ 	.sensor_mux_values = mt7622_mux_values,
+ 	.version = MTK_THERMAL_V2,
++	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
++	.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
++	.apmixed_buffer_ctl_set = BIT(0),
+ };
+ 
+ /*
+@@ -1079,14 +1085,18 @@ static const struct of_device_id mtk_the
+ };
+ MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
+ 
+-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
++static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
++				       void __iomem *apmixed_base)
+ {
+-	int tmp;
++	u32 tmp;
++
++	if (!mt->conf->apmixed_buffer_ctl_reg)
++		return;
+ 
+-	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
+-	tmp &= ~(0x37);
+-	tmp |= 0x1;
+-	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
++	tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
++	tmp &= mt->conf->apmixed_buffer_ctl_mask;
++	tmp |= mt->conf->apmixed_buffer_ctl_set;
++	writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
+ 	udelay(200);
+ }
+ 
+@@ -1184,10 +1194,10 @@ static int mtk_thermal_probe(struct plat
+ 		goto err_disable_clk_auxadc;
+ 	}
+ 
+-	if (mt->conf->version != MTK_THERMAL_V1) {
+-		mtk_thermal_turn_on_buffer(apmixed_base);
++	mtk_thermal_turn_on_buffer(mt, apmixed_base);
++
++	if (mt->conf->version != MTK_THERMAL_V2)
+ 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+-	}
+ 
+ 	if (mt->conf->version == MTK_THERMAL_V1)
+ 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch b/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch
new file mode 100644
index 0000000000..285c6f6a7b
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch
@@ -0,0 +1,123 @@
+From c4eff784465f88218dc5eb51320320464db83d3f Mon Sep 17 00:00:00 2001
+From: Fabien Parent <fparent@baylibre.com>
+Date: Fri, 27 Jan 2023 16:44:44 +0100
+Subject: [PATCH 12/42] thermal/drivers/mediatek: Add support for MT8365 SoC
+
+MT8365 is similar to the other SoCs supported by the driver. It has only
+one bank and 3 actual sensors that can be multiplexed. There is another
+one sensor that does not have usable data.
+
+Signed-off-by: Fabien Parent <fparent@baylibre.com>
+Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-3-55a1ae14af74@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 68 +++++++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -31,6 +31,7 @@
+ #define AUXADC_CON2_V		0x010
+ #define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
+ 
++#define APMIXED_SYS_TS_CON0	0x600
+ #define APMIXED_SYS_TS_CON1	0x604
+ 
+ /* Thermal Controller Registers */
+@@ -281,6 +282,17 @@ enum mtk_thermal_version {
+ /* The calibration coefficient of sensor  */
+ #define MT7986_CALIBRATION		165
+ 
++/* MT8365 */
++#define MT8365_TEMP_AUXADC_CHANNEL 11
++#define MT8365_CALIBRATION 164
++#define MT8365_NUM_CONTROLLER 1
++#define MT8365_NUM_BANKS 1
++#define MT8365_NUM_SENSORS 3
++#define MT8365_NUM_SENSORS_PER_ZONE 3
++#define MT8365_TS1 0
++#define MT8365_TS2 1
++#define MT8365_TS3 2
++
+ struct mtk_thermal;
+ 
+ struct thermal_bank_cfg {
+@@ -435,6 +447,24 @@ static const int mt7986_mux_values[MT798
+ static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
+ static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
+ 
++/* MT8365 thermal sensor data */
++static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
++	MT8365_TS1, MT8365_TS2, MT8365_TS3
++};
++
++static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
++	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
++};
++
++static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
++	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
++};
++
++static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
++static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
++
++static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
++
+ /*
+  * The MT8173 thermal controller has four banks. Each bank can read up to
+  * four temperature sensors simultaneously. The MT8173 has a total of 5
+@@ -510,6 +540,40 @@ static const struct mtk_thermal_data mt2
+ };
+ 
+ /*
++ * The MT8365 thermal controller has one bank, which can read up to
++ * four temperature sensors simultaneously. The MT8365 has a total of 3
++ * temperature sensors.
++ *
++ * The thermal core only gets the maximum temperature of this one bank,
++ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
++ * Voltage Scaling) unit makes its decisions based on the same bank
++ * data.
++ */
++static const struct mtk_thermal_data mt8365_thermal_data = {
++	.auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
++	.num_banks = MT8365_NUM_BANKS,
++	.num_sensors = MT8365_NUM_SENSORS,
++	.vts_index = mt8365_vts_index,
++	.cali_val = MT8365_CALIBRATION,
++	.num_controller = MT8365_NUM_CONTROLLER,
++	.controller_offset = mt8365_tc_offset,
++	.need_switch_bank = false,
++	.bank_data = {
++		{
++			.num_sensors = MT8365_NUM_SENSORS,
++			.sensors = mt8365_bank_data
++		},
++	},
++	.msr = mt8365_msr,
++	.adcpnp = mt8365_adcpnp,
++	.sensor_mux_values = mt8365_mux_values,
++	.version = MTK_THERMAL_V1,
++	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
++	.apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
++	.apmixed_buffer_ctl_set = 0,
++};
++
++/*
+  * The MT2712 thermal controller has one bank, which can read up to
+  * four temperature sensors simultaneously. The MT2712 has a total of 4
+  * temperature sensors.
+@@ -1080,6 +1144,10 @@ static const struct of_device_id mtk_the
+ 	{
+ 		.compatible = "mediatek,mt8183-thermal",
+ 		.data = (void *)&mt8183_thermal_data,
++	},
++	{
++		.compatible = "mediatek,mt8365-thermal",
++		.data = (void *)&mt8365_thermal_data,
+ 	}, {
+ 	},
+ };
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch b/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch
new file mode 100644
index 0000000000..5c99aa80c1
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch
@@ -0,0 +1,50 @@
+From 4eead70db74922bc61e9d0b4591524369a335751 Mon Sep 17 00:00:00 2001
+From: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Date: Fri, 27 Jan 2023 16:44:46 +0100
+Subject: [PATCH 13/42] thermal/drivers/mediatek: Add delay after thermal banks
+ initialization
+
+Thermal sensor reads performed immediately after thermal bank
+initialization returns bogus values. This is currently tackled by returning
+0 if the temperature is bogus (exceeding 200000).
+
+Instead, add a delay between the bank init and the thermal zone device
+register to properly fix this.
+
+Signed-off-by: Michael Kao <michael.kao@mediatek.com>
+Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
+Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-5-55a1ae14af74@baylibre.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -816,14 +816,6 @@ static int mtk_thermal_bank_temperature(
+ 			mt, conf->bank_data[bank->id].sensors[i], raw);
+ 
+ 
+-		/*
+-		 * The first read of a sensor often contains very high bogus
+-		 * temperature value. Filter these out so that the system does
+-		 * not immediately shut down.
+-		 */
+-		if (temp > 200000)
+-			temp = 0;
+-
+ 		if (temp > max)
+ 			max = temp;
+ 	}
+@@ -1281,6 +1273,9 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	platform_set_drvdata(pdev, mt);
+ 
++	/* Delay for thermal banks to be ready */
++	msleep(30);
++
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+ 	if (IS_ERR(tzdev)) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch
new file mode 100644
index 0000000000..734f5c1e77
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch
@@ -0,0 +1,46 @@
+From ad9dc9e92367803a4f9576aea0dab110d03fc510 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wenst@chromium.org>
+Date: Tue, 28 Mar 2023 11:10:17 +0800
+Subject: [PATCH 14/42] thermal/drivers/mediatek/lvts_thermal: Fix sensor 1
+ interrupt status bitmask
+
+The binary representation for sensor 1 interrupt status was incorrectly
+assembled, when compared to the full table given in the same comment
+section. The conversion into hex was also incorrect, leading to
+incorrect interrupt status bitmask for sensor 1. This would cause the
+driver to incorrectly identify changes for sensor 1, when in fact it
+was sensor 0, or a sensor access time out.
+
+Fix the binary and hex representations in the comments, and the actual
+bitmask macro.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230328031017.1360976-1-wenst@chromium.org
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -66,7 +66,7 @@
+ #define LVTS_MONINT_CONF			0x9FBF7BDE
+ 
+ #define LVTS_INT_SENSOR0			0x0009001F
+-#define LVTS_INT_SENSOR1			0X000881F0
++#define LVTS_INT_SENSOR1			0x001203E0
+ #define LVTS_INT_SENSOR2			0x00247C00
+ #define LVTS_INT_SENSOR3			0x1FC00000
+ 
+@@ -395,8 +395,8 @@ static irqreturn_t lvts_ctrl_irq_handler
+ 	 *                  => 0x1FC00000
+ 	 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
+ 	 *                  => 0x00247C00
+-	 * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
+-	 *                  => 0X000881F0
++	 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
++	 *                  => 0X001203E0
+ 	 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
+ 	 *                  => 0x0009001F
+ 	 */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch
new file mode 100644
index 0000000000..d09c2055a3
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch
@@ -0,0 +1,149 @@
+From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 7 Mar 2023 16:45:22 +0100
+Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain
+ for mt8195
+
+Add MT8195 AP Domain support to LVTS Driver.
+
+Take the opportunity to update the comments to show calibration data
+information related to the new domain.
+
+[dlezcano]: Massaged a bit the changelog
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------
+ 1 file changed, 74 insertions(+), 20 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic
+  * The efuse blob values follows the sensor enumeration per thermal
+  * controller. The decoding of the stream is as follow:
+  *
+- *                        <--?-> <----big0 ???---> <-sensor0-> <-0->
+- *                        ------------------------------------------
+- * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
+- *                        ------------------------------------------
++ * stream index map for MCU Domain :
+  *
+- *                        <--sensor1--><-0-> <----big1 ???---> <-sen
+- *                        ------------------------------------------
+- *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
+- *                        ------------------------------------------
++ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
++ *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
+  *
+- *                        sor0-> <-0-> <-sensor1-> <-0-> ..........
+- *                        ------------------------------------------
+- *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
+- *                        ------------------------------------------
++ * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
++ *  0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
+  *
+- * And so on ...
++ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
++ *  0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
++ *
++ * stream index map for AP Domain :
++ *
++ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
++ *  0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
++ *
++ * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
++ *  0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
++ *
++ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
++ *  0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
++ *
++ * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
++ *  0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
+  *
+  * The data description gives the offset of the calibration data in
+  * this bytes stream for each sensor.
+- *
+- * Each thermal controller can handle up to 4 sensors max, we don't
+- * care if there are less as the array of calibration is sized to 4
+- * anyway. The unused sensor slot will be zeroed.
+  */
+ static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
+ 					const struct lvts_ctrl_data *lvts_ctrl_data,
+@@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d
+ 	return 0;
+ }
+ 
+-static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
++static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+ 		.lvts_sensor = {
+@@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819
+ 	}
+ };
+ 
++static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
++		{
++		.cal_offset = { 0x25, 0x28 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_VPU0 },
++			{ .dt_id = MT8195_AP_VPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x2e, 0x31 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_GPU0 },
++			{ .dt_id = MT8195_AP_GPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x37, 0x3a, 0x3d },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_VDEC },
++			{ .dt_id = MT8195_AP_IMG },
++			{ .dt_id = MT8195_AP_INFRA },
++		},
++		.num_lvts_sensor = 3,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	},
++	{
++		.cal_offset = { 0x43, 0x46 },
++		.lvts_sensor = {
++			{ .dt_id = MT8195_AP_CAM0 },
++			{ .dt_id = MT8195_AP_CAM1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x300,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
++	}
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+-	.lvts_ctrl	= mt8195_lvts_data_ctrl,
+-	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_data_ctrl),
++	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
++};
++
++static const struct lvts_data mt8195_lvts_ap_data = {
++	.lvts_ctrl	= mt8195_lvts_ap_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
+ };
+ 
+ static const struct of_device_id lvts_of_match[] = {
+ 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
++	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, lvts_of_match);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch b/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch
new file mode 100644
index 0000000000..a48ea3742b
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch
@@ -0,0 +1,53 @@
+From 7105a86760bd9e4d107075cefc75016b693a5542 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Wed, 19 Apr 2023 08:11:45 +0200
+Subject: [PATCH 16/42] Revert "thermal/drivers/mediatek: Add delay after
+ thermal banks initialization"
+
+Some more testing revealed that this commit introduces a regression on some
+MT8173 Chromebooks and at least on one MT6795 Sony Xperia M5 smartphone due
+to the delay being apparently variable and machine specific.
+
+Another solution would be to delay for a bit more (~70ms) but this is not
+feasible for two reasons: first of all, we're adding an even bigger delay
+in a probe function; second, some machines need less, some may need even
+more, making the msleep at probe solution highly suboptimal.
+
+This reverts commit 10debf8c2da8011c8009dd4b3f6d0ab85891c81b.
+
+Fixes: 10debf8c2da8 ("thermal/drivers/mediatek: Add delay after thermal banks initialization")
+Reported-by: "kernelci.org bot" <bot@kernelci.org>
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419061146.22246-2-angelogioacchino.delregno@collabora.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -816,6 +816,14 @@ static int mtk_thermal_bank_temperature(
+ 			mt, conf->bank_data[bank->id].sensors[i], raw);
+ 
+ 
++		/*
++		 * The first read of a sensor often contains very high bogus
++		 * temperature value. Filter these out so that the system does
++		 * not immediately shut down.
++		 */
++		if (temp > 200000)
++			temp = 0;
++
+ 		if (temp > max)
+ 			max = temp;
+ 	}
+@@ -1273,9 +1281,6 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	platform_set_drvdata(pdev, mt);
+ 
+-	/* Delay for thermal banks to be ready */
+-	msleep(30);
+-
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+ 	if (IS_ERR(tzdev)) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch b/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch
new file mode 100644
index 0000000000..aae87af5d1
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch
@@ -0,0 +1,78 @@
+From 681b652c9dfc4037d4a55b2733e091a4e1a5de18 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Wed, 19 Apr 2023 08:11:46 +0200
+Subject: [PATCH 17/42] thermal/drivers/mediatek: Add temperature constraints
+ to validate read
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The AUXADC thermal v1 allows reading temperature range between -20°C to
+150°C and any value out of this range is invalid.
+
+Add new definitions for MT8173_TEMP_{MIN_MAX} and a new small helper
+mtk_thermal_temp_is_valid() to check if new readings are in range: if
+not, we tell to the API that the reading is invalid by returning
+THERMAL_TEMP_INVALID.
+
+It was chosen to introduce the helper function because, even though this
+temperature range is realistically ok for all, it comes from a downstream
+kernel driver for version 1, but here we also support v2 and v3 which may
+may have wider constraints.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419061146.22246-3-angelogioacchino.delregno@collabora.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 24 +++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -116,6 +116,10 @@
+ /* The calibration coefficient of sensor  */
+ #define MT8173_CALIBRATION	165
+ 
++/* Valid temperatures range */
++#define MT8173_TEMP_MIN		-20000
++#define MT8173_TEMP_MAX		150000
++
+ /*
+  * Layout of the fuses providing the calibration data
+  * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
+@@ -689,6 +693,11 @@ static const struct mtk_thermal_data mt7
+ 	.version = MTK_THERMAL_V3,
+ };
+ 
++static bool mtk_thermal_temp_is_valid(int temp)
++{
++	return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX);
++}
++
+ /**
+  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
+  * @mt:	The thermal controller
+@@ -815,14 +824,17 @@ static int mtk_thermal_bank_temperature(
+ 		temp = mt->raw_to_mcelsius(
+ 			mt, conf->bank_data[bank->id].sensors[i], raw);
+ 
+-
+ 		/*
+-		 * The first read of a sensor often contains very high bogus
+-		 * temperature value. Filter these out so that the system does
+-		 * not immediately shut down.
++		 * Depending on the filt/sen intervals and ADC polling time,
++		 * we may need up to 60 milliseconds after initialization: this
++		 * will result in the first reading containing an out of range
++		 * temperature value.
++		 * Validate the reading to both address the aforementioned issue
++		 * and to eventually avoid bogus readings during runtime in the
++		 * event that the AUXADC gets unstable due to high EMI, etc.
+ 		 */
+-		if (temp > 200000)
+-			temp = 0;
++		if (!mtk_thermal_temp_is_valid(temp))
++			temp = THERMAL_TEMP_INVALID;
+ 
+ 		if (temp > max)
+ 			max = temp;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch
new file mode 100644
index 0000000000..782684aacc
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch
@@ -0,0 +1,53 @@
+From 458fa1d508de3f17e49d974a0158d9aeff273a58 Mon Sep 17 00:00:00 2001
+From: Kang Chen <void0red@hust.edu.cn>
+Date: Wed, 19 Apr 2023 10:07:48 +0800
+Subject: [PATCH 18/42] thermal/drivers/mediatek: Use devm_of_iomap to avoid
+ resource leak in mtk_thermal_probe
+
+Smatch reports:
+1. mtk_thermal_probe() warn: 'apmixed_base' from of_iomap() not released.
+2. mtk_thermal_probe() warn: 'auxadc_base' from of_iomap() not released.
+
+The original code forgets to release iomap resource when handling errors,
+fix it by switch to devm_of_iomap.
+
+Fixes: 89945047b166 ("thermal: mediatek: Add tsensor support for V2 thermal system")
+Signed-off-by: Kang Chen <void0red@hust.edu.cn>
+Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419020749.621257-1-void0red@hust.edu.cn
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1232,7 +1232,12 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	auxadc_base = of_iomap(auxadc, 0);
++	auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
++	if (IS_ERR(auxadc_base)) {
++		of_node_put(auxadc);
++		return PTR_ERR(auxadc_base);
++	}
++
+ 	auxadc_phys_base = of_get_phys_base(auxadc);
+ 
+ 	of_node_put(auxadc);
+@@ -1248,7 +1253,12 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	apmixed_base = of_iomap(apmixedsys, 0);
++	apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
++	if (IS_ERR(apmixed_base)) {
++		of_node_put(apmixedsys);
++		return PTR_ERR(apmixed_base);
++	}
++
+ 	apmixed_phys_base = of_get_phys_base(apmixedsys);
+ 
+ 	of_node_put(apmixedsys);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch
new file mode 100644
index 0000000000..d7896dbd60
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch
@@ -0,0 +1,100 @@
+From 227d1856924ec00a4f5bdf5afcf77bc7f3f04e86 Mon Sep 17 00:00:00 2001
+From: Kang Chen <void0red@hust.edu.cn>
+Date: Wed, 19 Apr 2023 10:07:49 +0800
+Subject: [PATCH 19/42] thermal/drivers/mediatek: Change clk_prepare_enable to
+ devm_clk_get_enabled in mtk_thermal_probe
+
+Use devm_clk_get_enabled to do automatic resource management.
+Meanwhile, remove error handling labels in the probe function and
+the whole remove function.
+
+Signed-off-by: Kang Chen <void0red@hust.edu.cn>
+Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419020749.621257-2-void0red@hust.edu.cn
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 44 +++++------------------
+ 1 file changed, 9 insertions(+), 35 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1206,14 +1206,6 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	mt->conf = of_device_get_match_data(&pdev->dev);
+ 
+-	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
+-	if (IS_ERR(mt->clk_peri_therm))
+-		return PTR_ERR(mt->clk_peri_therm);
+-
+-	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
+-	if (IS_ERR(mt->clk_auxadc))
+-		return PTR_ERR(mt->clk_auxadc);
+-
+ 	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ 	if (IS_ERR(mt->thermal_base))
+ 		return PTR_ERR(mt->thermal_base);
+@@ -1272,16 +1264,18 @@ static int mtk_thermal_probe(struct plat
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = clk_prepare_enable(mt->clk_auxadc);
+-	if (ret) {
++	mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");
++	if (IS_ERR(mt->clk_auxadc)) {
++		ret = PTR_ERR(mt->clk_auxadc);
+ 		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
+ 		return ret;
+ 	}
+ 
+-	ret = clk_prepare_enable(mt->clk_peri_therm);
+-	if (ret) {
++	mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");
++	if (IS_ERR(mt->clk_peri_therm)) {
++		ret = PTR_ERR(mt->clk_peri_therm);
+ 		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
+-		goto err_disable_clk_auxadc;
++		return ret;
+ 	}
+ 
+ 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
+@@ -1305,38 +1299,18 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+-	if (IS_ERR(tzdev)) {
+-		ret = PTR_ERR(tzdev);
+-		goto err_disable_clk_peri_therm;
+-	}
++	if (IS_ERR(tzdev))
++		return PTR_ERR(tzdev);
+ 
+ 	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
+ 	if (ret)
+ 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
+ 
+ 	return 0;
+-
+-err_disable_clk_peri_therm:
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-err_disable_clk_auxadc:
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return ret;
+-}
+-
+-static int mtk_thermal_remove(struct platform_device *pdev)
+-{
+-	struct mtk_thermal *mt = platform_get_drvdata(pdev);
+-
+-	clk_disable_unprepare(mt->clk_peri_therm);
+-	clk_disable_unprepare(mt->clk_auxadc);
+-
+-	return 0;
+ }
+ 
+ static struct platform_driver mtk_thermal_driver = {
+ 	.probe = mtk_thermal_probe,
+-	.remove = mtk_thermal_remove,
+ 	.driver = {
+ 		.name = "mtk-thermal",
+ 		.of_match_table = mtk_thermal_of_match,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch b/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch
new file mode 100644
index 0000000000..fd18a5365c
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch
@@ -0,0 +1,36 @@
+From 655fe2533ac05323a07c19ba079bf2064e7741af Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Sun, 19 Mar 2023 11:32:31 -0500
+Subject: [PATCH 20/42] thermal/drivers/mediatek: Use of_address_to_resource()
+
+Replace of_get_address() and of_translate_address() calls with single
+call to of_address_to_resource().
+
+Signed-off-by: Rob Herring <robh@kernel.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230319163231.226738-1-robh@kernel.org
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -979,14 +979,12 @@ static void mtk_thermal_init_bank(struct
+ 
+ static u64 of_get_phys_base(struct device_node *np)
+ {
+-	u64 size64;
+-	const __be32 *regaddr_p;
++	struct resource res;
+ 
+-	regaddr_p = of_get_address(np, 0, &size64, NULL);
+-	if (!regaddr_p)
++	if (of_address_to_resource(np, 0, &res))
+ 		return OF_BAD_ADDR;
+ 
+-	return of_translate_address(np, regaddr_p);
++	return res.start;
+ }
+ 
+ static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch b/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch
new file mode 100644
index 0000000000..c3ff17d517
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch
@@ -0,0 +1,57 @@
+From 2c380d07215e6fce3ac66cc5af059bc2c2a69f7a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= <ricardo.canuelo@collabora.com>
+Date: Thu, 25 May 2023 14:18:11 +0200
+Subject: [PATCH 21/42] Revert "thermal/drivers/mediatek: Use devm_of_iomap to
+ avoid resource leak in mtk_thermal_probe"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit f05c7b7d9ea9477fcc388476c6f4ade8c66d2d26.
+
+That change was causing a regression in the generic-adc-thermal-probed
+bootrr test as reported in the kernelci-results list [1].
+A proper rework will take longer, so revert it for now.
+
+[1] https://groups.io/g/kernelci-results/message/42660
+
+Fixes: f05c7b7d9ea9 ("thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak in mtk_thermal_probe")
+Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
+Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230525121811.3360268-1-ricardo.canuelo@collabora.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1222,12 +1222,7 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
+-	if (IS_ERR(auxadc_base)) {
+-		of_node_put(auxadc);
+-		return PTR_ERR(auxadc_base);
+-	}
+-
++	auxadc_base = of_iomap(auxadc, 0);
+ 	auxadc_phys_base = of_get_phys_base(auxadc);
+ 
+ 	of_node_put(auxadc);
+@@ -1243,12 +1238,7 @@ static int mtk_thermal_probe(struct plat
+ 		return -ENODEV;
+ 	}
+ 
+-	apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
+-	if (IS_ERR(apmixed_base)) {
+-		of_node_put(apmixedsys);
+-		return PTR_ERR(apmixed_base);
+-	}
+-
++	apmixed_base = of_iomap(apmixedsys, 0);
+ 	apmixed_phys_base = of_get_phys_base(apmixedsys);
+ 
+ 	of_node_put(apmixedsys);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch b/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch
new file mode 100644
index 0000000000..c4456529c1
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch
@@ -0,0 +1,37 @@
+From 496f4b08981d8a788ad5a2073fa1c65a2af1862b Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wenst@chromium.org>
+Date: Tue, 13 Jun 2023 17:13:16 +0800
+Subject: [PATCH 22/42] thermal/drivers/mediatek/lvts_thermal: Register thermal
+ zones as hwmon sensors
+
+Register thermal zones as hwmon sensors to let userspace read
+temperatures using standard hwmon interface.
+
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230613091317.1691247-1-wenst@chromium.org
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -19,6 +19,8 @@
+ #include <linux/thermal.h>
+ #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
+ 
++#include "../thermal_hwmon.h"
++
+ #define LVTS_MONCTL0(__base)	(__base + 0x0000)
+ #define LVTS_MONCTL1(__base)	(__base + 0x0004)
+ #define LVTS_MONCTL2(__base)	(__base + 0x0008)
+@@ -996,6 +998,9 @@ static int lvts_ctrl_start(struct device
+ 			return PTR_ERR(tz);
+ 		}
+ 
++		if (devm_thermal_add_hwmon_sysfs(dev, tz))
++			dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
++
+ 		/*
+ 		 * The thermal zone pointer will be needed in the
+ 		 * interrupt handler, we store it in the sensor
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch b/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch
new file mode 100644
index 0000000000..22e7a954ed
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch
@@ -0,0 +1,28 @@
+From 885b9768ce2a66ed5d250822aed53d5114c895da Mon Sep 17 00:00:00 2001
+From: Yangtao Li <frank.li@vivo.com>
+Date: Tue, 20 Jun 2023 17:07:31 +0800
+Subject: [PATCH 23/42] thermal/drivers/mediatek/lvts_thermal: Remove redundant
+ msg in lvts_ctrl_start()
+
+The upper-layer devm_thermal_add_hwmon_sysfs() function can directly
+print error information.
+
+Signed-off-by: Yangtao Li <frank.li@vivo.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230620090732.50025-10-frank.li@vivo.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -998,8 +998,7 @@ static int lvts_ctrl_start(struct device
+ 			return PTR_ERR(tz);
+ 		}
+ 
+-		if (devm_thermal_add_hwmon_sysfs(dev, tz))
+-			dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
++		devm_thermal_add_hwmon_sysfs(dev, tz);
+ 
+ 		/*
+ 		 * The thermal zone pointer will be needed in the
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch
new file mode 100644
index 0000000000..bc67727423
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch
@@ -0,0 +1,40 @@
+From 27b389d9f62c2174f95fe4002b11e77d4cb3ce80 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:32 -0400
+Subject: [PATCH 25/42] thermal/drivers/mediatek/lvts_thermal: Handle IRQ on
+ all controllers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is a single IRQ handler for each LVTS thermal domain, and it is
+supposed to check each of its underlying controllers for the origin of
+the interrupt and clear its status. However due to a typo, only the
+first controller was ever being handled, which resulted in the interrupt
+never being cleared when it happened on the other controllers. Add the
+missing index so interrupts are handled for all controllers.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-2-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -451,7 +451,7 @@ static irqreturn_t lvts_irq_handler(int
+ 
+ 	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
+ 
+-		aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
++		aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
+ 		if (aux != IRQ_HANDLED)
+ 			continue;
+ 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch
new file mode 100644
index 0000000000..51d119c05b
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch
@@ -0,0 +1,120 @@
+From 6d827142643ee10c13ff9a1d90f38fb399aa9fff Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:33 -0400
+Subject: [PATCH 26/42] thermal/drivers/mediatek/lvts_thermal: Honor sensors in
+ immediate mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Each controller can be configured to operate on immediate or filtered
+mode. On filtered mode, the sensors are enabled by setting the
+corresponding bits in MONCTL0, while on immediate mode, by setting
+MSRCTL1.
+
+Previously, the code would set MSRCTL1 for all four sensors when
+configured to immediate mode, but given that the controller might not
+have all four sensors connected, this would cause interrupts to trigger
+for non-existent sensors. Fix this by handling the MSRCTL1 register
+analogously to the MONCTL0: only enable the sensors that were declared.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-3-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 57 ++++++++++++++-----------
+ 1 file changed, 33 insertions(+), 24 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -897,24 +897,6 @@ static int lvts_ctrl_configure(struct de
+ 	writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
+ 
+ 	/*
+-	 * LVTS_MSRCTL1 : Measurement control
+-	 *
+-	 * Bits:
+-	 *
+-	 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
+-	 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
+-	 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
+-	 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
+-	 *
+-	 * That configuration will ignore the filtering and the delays
+-	 * introduced below in MONCTL1 and MONCTL2
+-	 */
+-	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
+-		value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
+-		writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
+-	}
+-
+-	/*
+ 	 * LVTS_MONCTL1 : Period unit and group interval configuration
+ 	 *
+ 	 * The clock source of LVTS thermal controller is 26MHz.
+@@ -979,6 +961,15 @@ static int lvts_ctrl_start(struct device
+ 	struct thermal_zone_device *tz;
+ 	u32 sensor_map = 0;
+ 	int i;
++	/*
++	 * Bitmaps to enable each sensor on immediate and filtered modes, as
++	 * described in MSRCTL1 and MONCTL0 registers below, respectively.
++	 */
++	u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
++	u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
++
++	u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
++			     sensor_imm_bitmap : sensor_filt_bitmap;
+ 
+ 	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
+ 
+@@ -1016,20 +1007,38 @@ static int lvts_ctrl_start(struct device
+ 		 * map, so we can enable the temperature monitoring in
+ 		 * the hardware thermal controller.
+ 		 */
+-		sensor_map |= BIT(i);
++		sensor_map |= sensor_bitmap[i];
+ 	}
+ 
+ 	/*
+-	 * Bits:
+-	 *      9: Single point access flow
+-	 *    0-3: Enable sensing point 0-3
+-	 *
+ 	 * The initialization of the thermal zones give us
+ 	 * which sensor point to enable. If any thermal zone
+ 	 * was not described in the device tree, it won't be
+ 	 * enabled here in the sensor map.
+ 	 */
+-	writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
++	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
++		/*
++		 * LVTS_MSRCTL1 : Measurement control
++		 *
++		 * Bits:
++		 *
++		 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
++		 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
++		 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
++		 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
++		 *
++		 * That configuration will ignore the filtering and the delays
++		 * introduced in MONCTL1 and MONCTL2
++		 */
++		writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
++	} else {
++		/*
++		 * Bits:
++		 *      9: Single point access flow
++		 *    0-3: Enable sensing point 0-3
++		 */
++		writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
++	}
+ 
+ 	return 0;
+ }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch b/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch
new file mode 100644
index 0000000000..bfbadee350
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch
@@ -0,0 +1,77 @@
+From 93bb11dd19bdcc1fc97c7ceababd0db9fde128ad Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:34 -0400
+Subject: [PATCH 27/42] thermal/drivers/mediatek/lvts_thermal: Use offset
+ threshold for IRQ
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are two kinds of temperature monitoring interrupts available:
+* High Offset, Low Offset
+* Hot, Hot to normal, Cold
+
+The code currently uses the hot/h2n/cold interrupts, however in a way
+that doesn't work: the cold threshold is left uninitialized, which
+prevents the other thresholds from ever triggering, and the h2n
+interrupt is used as the lower threshold, which prevents the hot
+interrupt from triggering again after the thresholds are updated by the
+thermal framework, since a hot interrupt can only trigger again after
+the hot to normal interrupt has been triggered.
+
+But better yet than addressing those issues, is to use the high/low
+offset interrupts instead. This way only two thresholds need to be
+managed, which have a simpler state machine, making them a better match
+to the thermal framework's high and low thresholds.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-4-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -298,9 +298,9 @@ static int lvts_set_trips(struct thermal
+ 	u32 raw_high = lvts_temp_to_raw(high);
+ 
+ 	/*
+-	 * Hot to normal temperature threshold
++	 * Low offset temperature threshold
+ 	 *
+-	 * LVTS_H2NTHRE
++	 * LVTS_OFFSETL
+ 	 *
+ 	 * Bits:
+ 	 *
+@@ -309,13 +309,13 @@ static int lvts_set_trips(struct thermal
+ 	if (low != -INT_MAX) {
+ 		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
+ 			 thermal_zone_device_type(tz), low);
+-		writel(raw_low, LVTS_H2NTHRE(base));
++		writel(raw_low, LVTS_OFFSETL(base));
+ 	}
+ 
+ 	/*
+-	 * Hot temperature threshold
++	 * High offset temperature threshold
+ 	 *
+-	 * LVTS_HTHRE
++	 * LVTS_OFFSETH
+ 	 *
+ 	 * Bits:
+ 	 *
+@@ -323,7 +323,7 @@ static int lvts_set_trips(struct thermal
+ 	 */
+ 	pr_debug("%s: Setting high limit temperature interrupt: %d\n",
+ 		 thermal_zone_device_type(tz), high);
+-	writel(raw_high, LVTS_HTHRE(base));
++	writel(raw_high, LVTS_OFFSETH(base));
+ 
+ 	return 0;
+ }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch b/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch
new file mode 100644
index 0000000000..1c35d0ad19
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch
@@ -0,0 +1,51 @@
+From 8f8cab9d3e90acf1db278ef44ad05f10aefb973f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:35 -0400
+Subject: [PATCH 28/42] thermal/drivers/mediatek/lvts_thermal: Disable
+ undesired interrupts
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Out of the many interrupts supported by the hardware, the only ones of
+interest to the driver currently are:
+* The temperature went over the high offset threshold, for any of the
+  sensors
+* The temperature went below the low offset threshold, for any of the
+  sensors
+* The temperature went over the stage3 threshold
+
+These are the only thresholds configured by the driver through the
+OFFSETH, OFFSETL, and PROTTC registers, respectively.
+
+The current interrupt mask in LVTS_MONINT_CONF, enables many more
+interrupts, including data ready on sensors for both filtered and
+immediate mode. These are not only not handled by the driver, but they
+are also triggered too often, causing unneeded overhead. Disable these
+unnecessary interrupts.
+
+The meaning of each bit can be seen in the comment describing
+LVTS_MONINTST in the IRQ handler.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-5-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -65,7 +65,7 @@
+ #define LVTS_HW_FILTER				0x2
+ #define LVTS_TSSEL_CONF				0x13121110
+ #define LVTS_CALSCALE_CONF			0x300
+-#define LVTS_MONINT_CONF			0x9FBF7BDE
++#define LVTS_MONINT_CONF			0x8300318C
+ 
+ #define LVTS_INT_SENSOR0			0x0009001F
+ #define LVTS_INT_SENSOR1			0x001203E0
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch b/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch
new file mode 100644
index 0000000000..60942fdb89
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch
@@ -0,0 +1,70 @@
+From bd1ccf9408e6155564530af5e09b53ae497fe332 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:36 -0400
+Subject: [PATCH 29/42] thermal/drivers/mediatek/lvts_thermal: Don't leave
+ threshold zeroed
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The thermal framework might leave the low threshold unset if there
+aren't any lower trip points. This leaves the register zeroed, which
+translates to a very high temperature for the low threshold. The
+interrupt for this threshold is then immediately triggered, and the
+state machine gets stuck, preventing any other temperature monitoring
+interrupts to ever trigger.
+
+(The same happens by not setting the Cold or Hot to Normal thresholds
+when using those)
+
+Set the unused threshold to a valid low value. This value was chosen so
+that for any valid golden temperature read from the efuse, when the
+value is converted to raw and back again to milliCelsius, the result
+doesn't underflow.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-6-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -83,6 +83,8 @@
+ 
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
++#define LVTS_MINIMUM_THRESHOLD		20000
++
+ static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
+ static int coeff_b = LVTS_COEFF_B;
+ 
+@@ -294,7 +296,7 @@ static int lvts_set_trips(struct thermal
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *base = lvts_sensor->base;
+-	u32 raw_low = lvts_temp_to_raw(low);
++	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
+ 	u32 raw_high = lvts_temp_to_raw(high);
+ 
+ 	/*
+@@ -306,11 +308,9 @@ static int lvts_set_trips(struct thermal
+ 	 *
+ 	 * 14-0 : Raw temperature for threshold
+ 	 */
+-	if (low != -INT_MAX) {
+-		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
+-			 thermal_zone_device_type(tz), low);
+-		writel(raw_low, LVTS_OFFSETL(base));
+-	}
++	pr_debug("%s: Setting low limit temperature interrupt: %d\n",
++		 thermal_zone_device_type(tz), low);
++	writel(raw_low, LVTS_OFFSETL(base));
+ 
+ 	/*
+ 	 * High offset temperature threshold
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch b/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch
new file mode 100644
index 0000000000..e99aa0cdfd
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch
@@ -0,0 +1,156 @@
+From d4dd09968cab3249e6148e1c3fccb51824edb411 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 6 Jul 2023 11:37:37 -0400
+Subject: [PATCH 30/42] thermal/drivers/mediatek/lvts_thermal: Manage threshold
+ between sensors
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Each LVTS thermal controller can have up to four sensors, each capable
+of triggering its own interrupt when its measured temperature crosses
+the configured threshold. The threshold for each sensor is handled
+separately by the thermal framework, since each one is registered with
+its own thermal zone and trips. However, the temperature thresholds are
+configured on the controller, and therefore are shared between all
+sensors on that controller.
+
+When the temperature measured by the sensors is different enough to
+cause the thermal framework to configure different thresholds for each
+one, interrupts start triggering on sensors outside the last threshold
+configured.
+
+To address the issue, track the thresholds required by each sensor and
+only actually set the highest one in the hardware, and disable
+interrupts for all sensors outside the current configured range.
+
+Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230706153823.201943-7-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 69 +++++++++++++++++++++++++
+ 1 file changed, 69 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -67,6 +67,11 @@
+ #define LVTS_CALSCALE_CONF			0x300
+ #define LVTS_MONINT_CONF			0x8300318C
+ 
++#define LVTS_MONINT_OFFSET_SENSOR0		0xC
++#define LVTS_MONINT_OFFSET_SENSOR1		0x180
++#define LVTS_MONINT_OFFSET_SENSOR2		0x3000
++#define LVTS_MONINT_OFFSET_SENSOR3		0x3000000
++
+ #define LVTS_INT_SENSOR0			0x0009001F
+ #define LVTS_INT_SENSOR1			0x001203E0
+ #define LVTS_INT_SENSOR2			0x00247C00
+@@ -112,6 +117,8 @@ struct lvts_sensor {
+ 	void __iomem *base;
+ 	int id;
+ 	int dt_id;
++	int low_thresh;
++	int high_thresh;
+ };
+ 
+ struct lvts_ctrl {
+@@ -121,6 +128,8 @@ struct lvts_ctrl {
+ 	int num_lvts_sensor;
+ 	int mode;
+ 	void __iomem *base;
++	int low_thresh;
++	int high_thresh;
+ };
+ 
+ struct lvts_domain {
+@@ -292,12 +301,66 @@ static int lvts_get_temp(struct thermal_
+ 	return 0;
+ }
+ 
++static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
++{
++	u32 masks[] = {
++		LVTS_MONINT_OFFSET_SENSOR0,
++		LVTS_MONINT_OFFSET_SENSOR1,
++		LVTS_MONINT_OFFSET_SENSOR2,
++		LVTS_MONINT_OFFSET_SENSOR3,
++	};
++	u32 value = 0;
++	int i;
++
++	value = readl(LVTS_MONINT(lvts_ctrl->base));
++
++	for (i = 0; i < ARRAY_SIZE(masks); i++) {
++		if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
++		    && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
++			value |= masks[i];
++		else
++			value &= ~masks[i];
++	}
++
++	writel(value, LVTS_MONINT(lvts_ctrl->base));
++}
++
++static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
++{
++	int i;
++
++	if (high > lvts_ctrl->high_thresh)
++		return true;
++
++	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++)
++		if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
++		    && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
++			return false;
++
++	return true;
++}
++
+ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
++	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
+ 	void __iomem *base = lvts_sensor->base;
+ 	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
+ 	u32 raw_high = lvts_temp_to_raw(high);
++	bool should_update_thresh;
++
++	lvts_sensor->low_thresh = low;
++	lvts_sensor->high_thresh = high;
++
++	should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
++	if (should_update_thresh) {
++		lvts_ctrl->high_thresh = high;
++		lvts_ctrl->low_thresh = low;
++	}
++	lvts_update_irq_mask(lvts_ctrl);
++
++	if (!should_update_thresh)
++		return 0;
+ 
+ 	/*
+ 	 * Low offset temperature threshold
+@@ -521,6 +584,9 @@ static int lvts_sensor_init(struct devic
+ 		 */
+ 		lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
+ 			imm_regs[i] : msr_regs[i];
++
++		lvts_sensor[i].low_thresh = INT_MIN;
++		lvts_sensor[i].high_thresh = INT_MIN;
+ 	};
+ 
+ 	lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
+@@ -688,6 +754,9 @@ static int lvts_ctrl_init(struct device
+ 		 */
+ 		lvts_ctrl[i].hw_tshut_raw_temp =
+ 			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
++
++		lvts_ctrl[i].low_thresh = INT_MIN;
++		lvts_ctrl[i].high_thresh = INT_MIN;
+ 	}
+ 
+ 	/*
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch b/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch
new file mode 100644
index 0000000000..9ce3eeb74b
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch
@@ -0,0 +1,29 @@
+From 5af4904adc8b840987000724977c13c706d3b7d8 Mon Sep 17 00:00:00 2001
+From: Minjie Du <duminjie@vivo.com>
+Date: Thu, 13 Jul 2023 12:24:12 +0800
+Subject: [PATCH 31/42] thermal/drivers/mediatek/lvts: Fix parameter check in
+ lvts_debugfs_init()
+
+The documentation says "If an error occurs, ERR_PTR(-ERROR) will be
+returned" but the current code checks against a NULL pointer returned.
+
+Fix this by checking if IS_ERR().
+
+Signed-off-by: Minjie Du <duminjie@vivo.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230713042413.2519-1-duminjie@vivo.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -201,7 +201,7 @@ static int lvts_debugfs_init(struct devi
+ 	int i;
+ 
+ 	lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
+-	if (!lvts_td->dom_dentry)
++	if (IS_ERR(lvts_td->dom_dentry))
+ 		return 0;
+ 
+ 	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch
new file mode 100644
index 0000000000..4841054917
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch
@@ -0,0 +1,33 @@
+From 6186be80317d1dbda34d35c06c084a083938f2d3 Mon Sep 17 00:00:00 2001
+From: Chen Jiahao <chenjiahao16@huawei.com>
+Date: Wed, 2 Aug 2023 17:45:27 +0800
+Subject: [PATCH 32/42] thermal/drivers/mediatek: Clean up redundant
+ dev_err_probe()
+
+Referring to platform_get_irq()'s definition, the return value has
+already been checked if ret < 0, and printed via dev_err_probe().
+Calling dev_err_probe() one more time outside platform_get_irq()
+is obviously redundant.
+
+Removing dev_err_probe() outside platform_get_irq() to clean up
+above problem.
+
+Signed-off-by: Chen Jiahao <chenjiahao16@huawei.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230802094527.988842-1-chenjiahao16@huawei.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1216,7 +1216,7 @@ static int lvts_probe(struct platform_de
+ 
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq < 0)
+-		return dev_err_probe(dev, irq, "No irq resource\n");
++		return irq;
+ 
+ 	ret = lvts_domain_init(dev, lvts_td, lvts_data);
+ 	if (ret)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch
new file mode 100644
index 0000000000..c88bf984fa
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch
@@ -0,0 +1,95 @@
+From c2ab54ab0425388e65901a7af2fbf69ead968708 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Thu, 13 Jul 2023 11:42:37 -0400
+Subject: [PATCH 33/42] thermal/drivers/mediatek/lvts_thermal: Make readings
+ valid in filtered mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, when a controller is configured to use filtered mode, thermal
+readings are valid only about 30% of the time.
+
+Upon testing, it was noticed that lowering any of the interval settings
+resulted in an improved rate of valid data. The same was observed when
+decreasing the number of samples for each sensor (which also results in
+quicker measurements).
+
+Retrying the read with a timeout longer than the time it takes to
+resample (about 344us with these settings and 4 sensors) also improves
+the rate.
+
+Lower all timing settings to the minimum, configure the filtering to
+single sample, and poll the measurement register for at least one period
+to improve the data validity on filtered mode.  With these changes in
+place, out of 100000 reads, a single one failed, ie 99.999% of the data
+was valid.
+
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230713154743.611870-1-nfraprado@collabora.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -58,11 +58,11 @@
+ #define LVTS_PROTTC(__base)		(__base + 0x00CC)
+ #define LVTS_CLKEN(__base)		(__base + 0x00E4)
+ 
+-#define LVTS_PERIOD_UNIT			((118 * 1000) / (256 * 38))
+-#define LVTS_GROUP_INTERVAL			1
+-#define LVTS_FILTER_INTERVAL		1
+-#define LVTS_SENSOR_INTERVAL		1
+-#define LVTS_HW_FILTER				0x2
++#define LVTS_PERIOD_UNIT			0
++#define LVTS_GROUP_INTERVAL			0
++#define LVTS_FILTER_INTERVAL		0
++#define LVTS_SENSOR_INTERVAL		0
++#define LVTS_HW_FILTER				0x0
+ #define LVTS_TSSEL_CONF				0x13121110
+ #define LVTS_CALSCALE_CONF			0x300
+ #define LVTS_MONINT_CONF			0x8300318C
+@@ -86,6 +86,9 @@
+ #define LVTS_MSR_IMMEDIATE_MODE		0
+ #define LVTS_MSR_FILTERED_MODE		1
+ 
++#define LVTS_MSR_READ_TIMEOUT_US	400
++#define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
++
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
+ #define LVTS_MINIMUM_THRESHOLD		20000
+@@ -268,6 +271,7 @@ static int lvts_get_temp(struct thermal_
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+ 	void __iomem *msr = lvts_sensor->msr;
+ 	u32 value;
++	int rc;
+ 
+ 	/*
+ 	 * Measurement registers:
+@@ -280,7 +284,8 @@ static int lvts_get_temp(struct thermal_
+ 	 * 16	: Valid temperature
+ 	 * 15-0	: Raw temperature
+ 	 */
+-	value = readl(msr);
++	rc = readl_poll_timeout(msr, value, value & BIT(16),
++				LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
+ 
+ 	/*
+ 	 * As the thermal zone temperature will read before the
+@@ -293,7 +298,7 @@ static int lvts_get_temp(struct thermal_
+ 	 * functionning temperature and directly jump to a system
+ 	 * shutdown.
+ 	 */
+-	if (!(value & BIT(16)))
++	if (rc)
+ 		return -EAGAIN;
+ 
+ 	*temp = lvts_raw_to_temp(value & 0xFFFF);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch b/target/linux/mediatek/patches-6.1/830-v6.4-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch
new file mode 100644
index 0000000000..994461cdb1
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch
@@ -0,0 +1,30 @@
+From c864ff9de3b225b43bb8e08dedb223632323e059 Mon Sep 17 00:00:00 2001
+From: Andrei Coardos <aboutphysycs@gmail.com>
+Date: Fri, 11 Aug 2023 22:28:47 +0300
+Subject: [PATCH 34/42] thermal/drivers/mediatek/auxadc_thermal: Removed call
+ to platform_set_drvdata()
+
+This function call was found to be unnecessary as there is no equivalent
+platform_get_drvdata() call to access the private data of the driver. Also,
+the private data is defined in this driver, so there is no risk of it being
+accessed outside of this driver file.
+
+Signed-off-by: Andrei Coardos <aboutphysycs@gmail.com>
+Reviewed-by: Alexandru Ardelean <alex@shruggie.ro>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230811192847.3838-1-aboutphysycs@gmail.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1283,8 +1283,6 @@ static int mtk_thermal_probe(struct plat
+ 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
+ 					      auxadc_phys_base, ctrl_id);
+ 
+-	platform_set_drvdata(pdev, mt);
+-
+ 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
+ 					      &mtk_thermal_ops);
+ 	if (IS_ERR(tzdev))
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch b/target/linux/mediatek/patches-6.1/830-v6.4-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch
new file mode 100644
index 0000000000..b3bfa37458
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch
@@ -0,0 +1,58 @@
+From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 27 Sep 2023 21:37:23 +0200
+Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback
+ returning void
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The .remove() callback for a platform driver returns an int which makes
+many driver authors wrongly assume it's possible to do error handling by
+returning an error code. However the value returned is ignored (apart
+from emitting a warning) and this typically results in resource leaks.
+
+To improve here there is a quest to make the remove callback return
+void. In the first step of this quest all drivers are converted to
+.remove_new(), which already returns void. Eventually after all drivers
+are converted, .remove_new() will be renamed to .remove().
+
+Trivially convert this driver from always returning zero in the remove
+callback to the void returning variant.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1241,7 +1241,7 @@ static int lvts_probe(struct platform_de
+ 	return 0;
+ }
+ 
+-static int lvts_remove(struct platform_device *pdev)
++static void lvts_remove(struct platform_device *pdev)
+ {
+ 	struct lvts_domain *lvts_td;
+ 	int i;
+@@ -1252,8 +1252,6 @@ static int lvts_remove(struct platform_d
+ 		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
+ 
+ 	lvts_debugfs_exit(lvts_td);
+-
+-	return 0;
+ }
+ 
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+@@ -1354,7 +1352,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
+ 
+ static struct platform_driver lvts_driver = {
+ 	.probe = lvts_probe,
+-	.remove = lvts_remove,
++	.remove_new = lvts_remove,
+ 	.driver = {
+ 		.name = "mtk-lvts-thermal",
+ 		.of_match_table = lvts_of_match,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch b/target/linux/mediatek/patches-6.1/830-v6.4-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch
new file mode 100644
index 0000000000..16a32f564b
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch
@@ -0,0 +1,198 @@
+From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:19 +0200
+Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff
+ configurable
+
+The upcoming mt7988 has different temperature coefficients so we
+cannot use constants in the functions lvts_golden_temp_init,
+lvts_golden_temp_init and lvts_raw_to_temp anymore.
+
+Add a field in the lvts_ctrl pointing to the lvts_data which now
+contains the soc-specific temperature coefficents.
+
+To make the code better readable, rename static int coeff_b to
+golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++---------
+ 1 file changed, 34 insertions(+), 17 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -80,8 +80,8 @@
+ #define LVTS_SENSOR_MAX				4
+ #define LVTS_GOLDEN_TEMP_MAX		62
+ #define LVTS_GOLDEN_TEMP_DEFAULT	50
+-#define LVTS_COEFF_A				-250460
+-#define LVTS_COEFF_B				250460
++#define LVTS_COEFF_A_MT8195			-250460
++#define LVTS_COEFF_B_MT8195			250460
+ 
+ #define LVTS_MSR_IMMEDIATE_MODE		0
+ #define LVTS_MSR_FILTERED_MODE		1
+@@ -94,7 +94,7 @@
+ #define LVTS_MINIMUM_THRESHOLD		20000
+ 
+ static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
+-static int coeff_b = LVTS_COEFF_B;
++static int golden_temp_offset;
+ 
+ struct lvts_sensor_data {
+ 	int dt_id;
+@@ -112,6 +112,8 @@ struct lvts_ctrl_data {
+ struct lvts_data {
+ 	const struct lvts_ctrl_data *lvts_ctrl;
+ 	int num_lvts_ctrl;
++	int temp_factor;
++	int temp_offset;
+ };
+ 
+ struct lvts_sensor {
+@@ -126,6 +128,7 @@ struct lvts_sensor {
+ 
+ struct lvts_ctrl {
+ 	struct lvts_sensor sensors[LVTS_SENSOR_MAX];
++	const struct lvts_data *lvts_data;
+ 	u32 calibration[LVTS_SENSOR_MAX];
+ 	u32 hw_tshut_raw_temp;
+ 	int num_lvts_sensor;
+@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt
+ 
+ #endif
+ 
+-static int lvts_raw_to_temp(u32 raw_temp)
++static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
+ {
+ 	int temperature;
+ 
+-	temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
+-	temperature += coeff_b;
++	temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
++	temperature += golden_temp_offset;
+ 
+ 	return temperature;
+ }
+ 
+-static u32 lvts_temp_to_raw(int temperature)
++static u32 lvts_temp_to_raw(int temperature, int temp_factor)
+ {
+-	u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
++	u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
+ 
+-	raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
++	raw_temp = div_s64(raw_temp, -temp_factor);
+ 
+ 	return raw_temp;
+ }
+@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat
+ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
++	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
++						   sensors[lvts_sensor->id]);
++	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
+ 	void __iomem *msr = lvts_sensor->msr;
+ 	u32 value;
+ 	int rc;
+@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_
+ 	if (rc)
+ 		return -EAGAIN;
+ 
+-	*temp = lvts_raw_to_temp(value & 0xFFFF);
++	*temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
+ 
+ 	return 0;
+ }
+@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st
+ static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+ 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
+-	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
++	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
++						   sensors[lvts_sensor->id]);
++	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
+ 	void __iomem *base = lvts_sensor->base;
+-	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
+-	u32 raw_high = lvts_temp_to_raw(high);
++	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
++				       lvts_data->temp_factor);
++	u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
+ 	bool should_update_thresh;
+ 
+ 	lvts_sensor->low_thresh = low;
+@@ -692,7 +701,7 @@ static int lvts_calibration_read(struct
+ 	return 0;
+ }
+ 
+-static int lvts_golden_temp_init(struct device *dev, u32 *value)
++static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
+ {
+ 	u32 gt;
+ 
+@@ -701,7 +710,7 @@ static int lvts_golden_temp_init(struct
+ 	if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
+ 		golden_temp = gt;
+ 
+-	coeff_b = golden_temp * 500 + LVTS_COEFF_B;
++	golden_temp_offset = golden_temp * 500 + temp_offset;
+ 
+ 	return 0;
+ }
+@@ -724,7 +733,7 @@ static int lvts_ctrl_init(struct device
+ 	 * The golden temp information is contained in the first chunk
+ 	 * of efuse data.
+ 	 */
+-	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
++	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -735,6 +744,7 @@ static int lvts_ctrl_init(struct device
+ 	for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
+ 
+ 		lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
++		lvts_ctrl[i].lvts_data = lvts_data;
+ 
+ 		ret = lvts_sensor_init(dev, &lvts_ctrl[i],
+ 				       &lvts_data->lvts_ctrl[i]);
+@@ -758,7 +768,8 @@ static int lvts_ctrl_init(struct device
+ 		 * after initializing the calibration.
+ 		 */
+ 		lvts_ctrl[i].hw_tshut_raw_temp =
+-			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
++			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
++					 lvts_data->temp_factor);
+ 
+ 		lvts_ctrl[i].low_thresh = INT_MIN;
+ 		lvts_ctrl[i].high_thresh = INT_MIN;
+@@ -1223,6 +1234,8 @@ static int lvts_probe(struct platform_de
+ 	if (irq < 0)
+ 		return irq;
+ 
++	golden_temp_offset = lvts_data->temp_offset;
++
+ 	ret = lvts_domain_init(dev, lvts_td, lvts_data);
+ 	if (ret)
+ 		return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
+@@ -1336,11 +1349,15 @@ static const struct lvts_ctrl_data mt819
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
++	.temp_factor	= LVTS_COEFF_A_MT8195,
++	.temp_offset	= LVTS_COEFF_B_MT8195,
+ };
+ 
+ static const struct lvts_data mt8195_lvts_ap_data = {
+ 	.lvts_ctrl	= mt8195_lvts_ap_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
++	.temp_factor	= LVTS_COEFF_A_MT8195,
++	.temp_offset	= LVTS_COEFF_B_MT8195,
+ };
+ 
+ static const struct of_device_id lvts_of_match[] = {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch
new file mode 100644
index 0000000000..1c2146f43f
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch
@@ -0,0 +1,35 @@
+From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:18 +0200
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for
+ mt7988
+
+Add sensor constants for MT7988.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de
+---
+ include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -7,6 +7,15 @@
+ #ifndef __MEDIATEK_LVTS_DT_H
+ #define __MEDIATEK_LVTS_DT_H
+ 
++#define MT7988_CPU_0		0
++#define MT7988_CPU_1		1
++#define MT7988_ETH2P5G_0	2
++#define MT7988_ETH2P5G_1	3
++#define MT7988_TOPS_0		4
++#define MT7988_TOPS_1		5
++#define MT7988_ETHWARP_0	6
++#define MT7988_ETHWARP_1	7
++
+ #define MT8195_MCU_BIG_CPU0     0
+ #define MT8195_MCU_BIG_CPU1     1
+ #define MT8195_MCU_BIG_CPU2     2
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.4-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch
new file mode 100644
index 0000000000..97c803a820
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch
@@ -0,0 +1,91 @@
+From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 22 Sep 2023 07:50:20 +0200
+Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
+ support
+
+Add Support for Mediatek Filogic 880/MT7988 LVTS.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -82,6 +82,8 @@
+ #define LVTS_GOLDEN_TEMP_DEFAULT	50
+ #define LVTS_COEFF_A_MT8195			-250460
+ #define LVTS_COEFF_B_MT8195			250460
++#define LVTS_COEFF_A_MT7988			-204650
++#define LVTS_COEFF_B_MT7988			204650
+ 
+ #define LVTS_MSR_IMMEDIATE_MODE		0
+ #define LVTS_MSR_FILTERED_MODE		1
+@@ -89,6 +91,7 @@
+ #define LVTS_MSR_READ_TIMEOUT_US	400
+ #define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
+ 
++#define LVTS_HW_SHUTDOWN_MT7988		105000
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
+ #define LVTS_MINIMUM_THRESHOLD		20000
+@@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_
+ 	lvts_debugfs_exit(lvts_td);
+ }
+ 
++static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
++	{
++		.cal_offset = { 0x00, 0x04, 0x08, 0x0c },
++		.lvts_sensor = {
++			{ .dt_id = MT7988_CPU_0 },
++			{ .dt_id = MT7988_CPU_1 },
++			{ .dt_id = MT7988_ETH2P5G_0 },
++			{ .dt_id = MT7988_ETH2P5G_1 }
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
++	},
++	{
++		.cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
++		.lvts_sensor = {
++			{ .dt_id = MT7988_TOPS_0},
++			{ .dt_id = MT7988_TOPS_1},
++			{ .dt_id = MT7988_ETHWARP_0},
++			{ .dt_id = MT7988_ETHWARP_1}
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
++	}
++};
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+@@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819
+ 	}
+ };
+ 
++static const struct lvts_data mt7988_lvts_ap_data = {
++	.lvts_ctrl	= mt7988_lvts_ap_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
++	.temp_factor	= LVTS_COEFF_A_MT7988,
++	.temp_offset	= LVTS_COEFF_B_MT7988,
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+@@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt
+ };
+ 
+ static const struct of_device_id lvts_of_match[] = {
++	{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ 	{},
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch b/target/linux/mediatek/patches-6.1/830-v6.4-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch
new file mode 100644
index 0000000000..5b212a2a37
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch
@@ -0,0 +1,30 @@
+From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001
+From: Minjie Du <duminjie@vivo.com>
+Date: Thu, 21 Sep 2023 17:10:50 +0800
+Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check
+ in lvts_debugfs_init()
+
+debugfs_create_dir() function returns an error value embedded in
+the pointer (PTR_ERR). Evaluate the return value using IS_ERR
+rather than checking for NULL.
+
+Signed-off-by: Minjie Du <duminjie@vivo.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi
+ 
+ 		sprintf(name, "controller%d", i);
+ 		dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
+-		if (!dentry)
++		if (IS_ERR(dentry))
+ 			continue;
+ 
+ 		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch b/target/linux/mediatek/patches-6.1/830-v6.4-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
new file mode 100644
index 0000000000..88f383c4ae
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
@@ -0,0 +1,33 @@
+From e6f43063f2fe9f08b34797bc6d223f7d63b01910 Mon Sep 17 00:00:00 2001
+From: Markus Schneider-Pargmann <msp@baylibre.com>
+Date: Mon, 18 Sep 2023 12:07:06 +0200
+Subject: [PATCH 39/42] thermal/drivers/mediatek: Fix probe for THERMAL_V2
+
+Fix the probe function to call mtk_thermal_release_periodic_ts for
+everything != MTK_THERMAL_V1. This was accidentally changed from V1
+to V2 in the original patch.
+
+Reported-by: Frank Wunderlich <frank-w@public-files.de>
+Closes: https://lore.kernel.org/lkml/B0B3775B-B8D1-4284-814F-4F41EC22F532@public-files.de/
+Reported-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Closes: https://lore.kernel.org/lkml/07a569b9-e691-64ea-dd65-3b49842af33d@linaro.org/
+Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
+Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230918100706.1229239-1-msp@baylibre.com
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -1268,7 +1268,7 @@ static int mtk_thermal_probe(struct plat
+ 
+ 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
+ 
+-	if (mt->conf->version != MTK_THERMAL_V2)
++	if (mt->conf->version != MTK_THERMAL_V1)
+ 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
+ 
+ 	if (mt->conf->version == MTK_THERMAL_V1)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch b/target/linux/mediatek/patches-6.1/830-v6.4-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch
new file mode 100644
index 0000000000..7b4b124b56
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.4-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch
@@ -0,0 +1,83 @@
+From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:42 +0200
+Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and
+ resume
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add suspend and resume support to LVTS driver.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+[bero@baylibre.com: suspend/resume in noirq phase]
+Co-developed-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -1297,6 +1297,38 @@ static const struct lvts_ctrl_data mt798
+ 	}
+ };
+ 
++static int lvts_suspend(struct device *dev)
++{
++	struct lvts_domain *lvts_td;
++	int i;
++
++	lvts_td = dev_get_drvdata(dev);
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
++
++	clk_disable_unprepare(lvts_td->clk);
++
++	return 0;
++}
++
++static int lvts_resume(struct device *dev)
++{
++	struct lvts_domain *lvts_td;
++	int i, ret;
++
++	lvts_td = dev_get_drvdata(dev);
++
++	ret = clk_prepare_enable(lvts_td->clk);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
++		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
++
++	return 0;
++}
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+@@ -1405,12 +1437,17 @@ static const struct of_device_id lvts_of
+ };
+ MODULE_DEVICE_TABLE(of, lvts_of_match);
+ 
++static const struct dev_pm_ops lvts_pm_ops = {
++	NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
++};
++
+ static struct platform_driver lvts_driver = {
+ 	.probe = lvts_probe,
+ 	.remove_new = lvts_remove,
+ 	.driver = {
+ 		.name = "mtk-lvts-thermal",
+ 		.of_match_table = lvts_of_match,
++		.pm = &lvts_pm_ops,
+ 	},
+ };
+ module_platform_driver(lvts_driver);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
new file mode 100644
index 0000000000..c278168610
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
@@ -0,0 +1,49 @@
+From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:41 +0200
+Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller
+ definition for mt8192
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add LVTS thermal controller definition for MT8192.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com
+---
+ .../thermal/mediatek,lvts-thermal.h           | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
++++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+@@ -35,4 +35,23 @@
+ #define MT8195_AP_CAM0  15
+ #define MT8195_AP_CAM1  16
+ 
++#define MT8192_MCU_BIG_CPU0     0
++#define MT8192_MCU_BIG_CPU1     1
++#define MT8192_MCU_BIG_CPU2     2
++#define MT8192_MCU_BIG_CPU3     3
++#define MT8192_MCU_LITTLE_CPU0  4
++#define MT8192_MCU_LITTLE_CPU1  5
++#define MT8192_MCU_LITTLE_CPU2  6
++#define MT8192_MCU_LITTLE_CPU3  7
++
++#define MT8192_AP_VPU0  8
++#define MT8192_AP_VPU1  9
++#define MT8192_AP_GPU0  10
++#define MT8192_AP_GPU1  11
++#define MT8192_AP_INFRA 12
++#define MT8192_AP_CAM   13
++#define MT8192_AP_MD0   14
++#define MT8192_AP_MD1   15
++#define MT8192_AP_MD2   16
++
+ #endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch
new file mode 100644
index 0000000000..6d68a6cd57
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch
@@ -0,0 +1,151 @@
+From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:43 +0200
+Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
+ support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add LVTS Driver support for MT8192.
+
+Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+[bero@baylibre.com: cosmetic changes, rebase]
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
+ 1 file changed, 95 insertions(+)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -92,6 +92,7 @@
+ #define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
+ 
+ #define LVTS_HW_SHUTDOWN_MT7988		105000
++#define LVTS_HW_SHUTDOWN_MT8192		105000
+ #define LVTS_HW_SHUTDOWN_MT8195		105000
+ 
+ #define LVTS_MINIMUM_THRESHOLD		20000
+@@ -1329,6 +1330,88 @@ static int lvts_resume(struct device *de
+ 	return 0;
+ }
+ 
++static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
++	{
++		.cal_offset = { 0x04, 0x08 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_MCU_BIG_CPU0 },
++			{ .dt_id = MT8192_MCU_BIG_CPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++		.mode = LVTS_MSR_FILTERED_MODE,
++	},
++	{
++		.cal_offset = { 0x0c, 0x10 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_MCU_BIG_CPU2 },
++			{ .dt_id = MT8192_MCU_BIG_CPU3 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++		.mode = LVTS_MSR_FILTERED_MODE,
++	},
++	{
++		.cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_MCU_LITTLE_CPU0 },
++			{ .dt_id = MT8192_MCU_LITTLE_CPU1 },
++			{ .dt_id = MT8192_MCU_LITTLE_CPU2 },
++			{ .dt_id = MT8192_MCU_LITTLE_CPU3 }
++		},
++		.num_lvts_sensor = 4,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++		.mode = LVTS_MSR_FILTERED_MODE,
++	}
++};
++
++static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
++		{
++		.cal_offset = { 0x24, 0x28 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_VPU0 },
++			{ .dt_id = MT8192_AP_VPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x0,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	},
++	{
++		.cal_offset = { 0x2c, 0x30 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_GPU0 },
++			{ .dt_id = MT8192_AP_GPU1 }
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x100,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	},
++	{
++		.cal_offset = { 0x34, 0x38 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_INFRA },
++			{ .dt_id = MT8192_AP_CAM },
++		},
++		.num_lvts_sensor = 2,
++		.offset = 0x200,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	},
++	{
++		.cal_offset = { 0x3c, 0x40, 0x44 },
++		.lvts_sensor = {
++			{ .dt_id = MT8192_AP_MD0 },
++			{ .dt_id = MT8192_AP_MD1 },
++			{ .dt_id = MT8192_AP_MD2 }
++		},
++		.num_lvts_sensor = 3,
++		.offset = 0x300,
++		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
++	}
++};
++
+ static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
+ 	{
+ 		.cal_offset = { 0x04, 0x07 },
+@@ -1415,6 +1498,16 @@ static const struct lvts_data mt7988_lvt
+ 	.temp_offset	= LVTS_COEFF_B_MT7988,
+ };
+ 
++static const struct lvts_data mt8192_lvts_mcu_data = {
++	.lvts_ctrl	= mt8192_lvts_mcu_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
++};
++
++static const struct lvts_data mt8192_lvts_ap_data = {
++	.lvts_ctrl	= mt8192_lvts_ap_data_ctrl,
++	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
++};
++
+ static const struct lvts_data mt8195_lvts_mcu_data = {
+ 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
+ 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
+@@ -1431,6 +1524,8 @@ static const struct lvts_data mt8195_lvt
+ 
+ static const struct of_device_id lvts_of_match[] = {
+ 	{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
++	{ .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
++	{ .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
+ 	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ 	{},
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch b/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch
new file mode 100644
index 0000000000..c20c0b5f2e
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch
@@ -0,0 +1,70 @@
+From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001
+From: Balsam CHIHI <bchihi@baylibre.com>
+Date: Tue, 17 Oct 2023 21:05:45 +0200
+Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update
+ calibration data documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Update LVTS calibration data documentation for mt8192 and mt8195.
+
+Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
+Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
+[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
+Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com
+---
+ drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
+ 1 file changed, 29 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/mediatek/lvts_thermal.c
++++ b/drivers/thermal/mediatek/lvts_thermal.c
+@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic
+  * The efuse blob values follows the sensor enumeration per thermal
+  * controller. The decoding of the stream is as follow:
+  *
+- * stream index map for MCU Domain :
++ * MT8192 :
++ * Stream index map for MCU Domain mt8192 :
++ *
++ * <-----mcu-tc#0-----> <-----sensor#0----->        <-----sensor#1----->
++ *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
++ *
++ * <-----sensor#2----->        <-----sensor#3----->
++ *  0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
++ *
++ * <-----sensor#4----->        <-----sensor#5----->        <-----sensor#6----->        <-----sensor#7----->
++ *  0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
++ *
++ * Stream index map for AP Domain mt8192 :
++ *
++ * <-----sensor#0----->        <-----sensor#1----->
++ *  0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
++ *
++ * <-----sensor#2----->        <-----sensor#3----->
++ *  0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
++ *
++ * <-----sensor#4----->        <-----sensor#5----->
++ *  0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
++ *
++ * <-----sensor#6----->        <-----sensor#7----->        <-----sensor#8----->
++ *  0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
++ *
++ * MT8195 :
++ * Stream index map for MCU Domain mt8195 :
+  *
+  * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+  *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
+@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic
+  * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
+  *  0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
+  *
+- * stream index map for AP Domain :
++ * Stream index map for AP Domain mt8195 :
+  *
+  * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+  *  0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
diff --git a/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch b/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch
new file mode 100644
index 0000000000..fc173646e0
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch
@@ -0,0 +1,59 @@
+From patchwork Thu Sep  7 11:20:18 2023
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
+X-Patchwork-Id: 13376356
+From: Frank Wunderlich <linux@fw-web.de>
+To: linux-mediatek@lists.infradead.org
+Subject: [PATCH] thermal/drivers/mediatek: Fix control buffer enablement on
+ MT7896
+Date: Thu,  7 Sep 2023 13:20:18 +0200
+Message-Id: <20230907112018.52811-1-linux@fw-web.de>
+X-Mailer: git-send-email 2.34.1
+MIME-Version: 1.0
+X-Mail-ID: e7eeb8e1-00de-41f6-a5df-ce2e9164136e
+X-BeenThere: linux-mediatek@lists.infradead.org
+X-Mailman-Version: 2.1.34
+Precedence: list
+List-Id: <linux-mediatek.lists.infradead.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
+ "Rafael J. Wysocki" <rafael@kernel.org>, linux-pm@vger.kernel.org,
+ Amit Kucheria <amitk@kernel.org>, Daniel Golle <daniel@makrotopia.org>,
+ stable@vger.kernel.org, linux-kernel@vger.kernel.org,
+ Matthias Brugger <matthias.bgg@gmail.com>, Zhang Rui <rui.zhang@intel.com>,
+ linux-arm-kernel@lists.infradead.org,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
+
+From: Frank Wunderlich <frank-w@public-files.de>
+
+Reading thermal sensor on mt7986 devices returns invalid temperature:
+
+bpi-r3 ~ # cat /sys/class/thermal/thermal_zone0/temp
+ -274000
+
+Fix this by adding missing members in mtk_thermal_data struct which were
+used in mtk_thermal_turn_on_buffer after commit 33140e668b10.
+
+Cc: stable@vger.kernel.org
+Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
+---
+ drivers/thermal/mediatek/auxadc_thermal.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/thermal/mediatek/auxadc_thermal.c
++++ b/drivers/thermal/mediatek/auxadc_thermal.c
+@@ -691,6 +691,9 @@ static const struct mtk_thermal_data mt7
+ 	.adcpnp = mt7986_adcpnp,
+ 	.sensor_mux_values = mt7986_mux_values,
+ 	.version = MTK_THERMAL_V3,
++	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
++	.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
++	.apmixed_buffer_ctl_set = BIT(0),
+ };
+ 
+ static bool mtk_thermal_temp_is_valid(int temp)
diff --git a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
index 8e56be9ff4..6dede02003 100644
--- a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
+++ b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -310,7 +310,7 @@
+@@ -312,7 +312,7 @@
  	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
  	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
  	 */
diff --git a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
index b6762e29ac..09ce417c35 100644
--- a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
+++ b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -637,5 +637,28 @@
+@@ -639,5 +639,28 @@
  };
  
  &wmac {
diff --git a/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch b/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch
new file mode 100644
index 0000000000..a141743194
--- /dev/null
+++ b/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch
@@ -0,0 +1,103 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -32,6 +32,9 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
++		rootdisk-emmc = <&emmc_rootfs>;
++		rootdisk-sd = <&sd_rootfs>;
++		rootdisk-snfi = <&ubi_rootfs>;
+ 	};
+ 
+ 	cpus {
+@@ -233,6 +236,26 @@
+ 	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+ 	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+ 	non-removable;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				block-partition-env {
++					partname = "ubootenv";
++					nvmem-layout {
++						compatible = "u-boot,env-layout";
++					};
++				};
++				emmc_rootfs: block-partition-production {
++					partname = "production";
++				};
++			};
++		};
++	};
+ };
+ 
+ &mmc1 {
+@@ -249,6 +272,26 @@
+ 	vqmmc-supply = <&reg_3p3v>;
+ 	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ 	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				block-partition-env {
++					partname = "ubootenv";
++					nvmem-layout {
++						compatible = "u-boot,env-layout";
++					};
++				};
++				sd_rootfs: block-partition-production {
++					partname = "production";
++				};
++			};
++		};
++	};
+ };
+ 
+ &nandc {
+@@ -283,14 +326,29 @@
+ 			};
+ 
+ 			partition@80000 {
+-				label = "fip";
+-				reg = <0x80000 0x200000>;
+-				read-only;
+-			};
+-
+-			partition@280000 {
+ 				label = "ubi";
+-				reg = <0x280000 0x7d80000>;
++				reg = <0x80000 0x7f80000>;
++				compatible = "linux,ubi";
++
++				volumes {
++					ubi-volume-ubootenv {
++						volname = "ubootenv";
++						nvmem-layout {
++							compatible = "u-boot,env-redundant-bool-layout";
++						};
++					};
++
++					ubi-volume-ubootenv2 {
++						volname = "ubootenv2";
++						nvmem-layout {
++							compatible = "u-boot,env-redundant-bool-layout";
++						};
++					};
++
++					ubi_rootfs: ubi-volume-fit {
++						volname = "fit";
++					};
++				};
+ 			};
+ 		};
+ 	};
diff --git a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
index b59ea02ae7..71cb3006ab 100644
--- a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
+++ b/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
@@ -15,7 +15,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1239,7 +1239,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1264,7 +1264,7 @@ static int mtk_init_fq_dma(struct mtk_et
  		eth->scratch_ring = eth->sram_base;
  	else
  		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
@@ -24,7 +24,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  						       &eth->phy_scratch_ring,
  						       GFP_KERNEL);
  	if (unlikely(!eth->scratch_ring))
-@@ -1255,16 +1255,16 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1280,16 +1280,16 @@ static int mtk_init_fq_dma(struct mtk_et
  	if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
  		return -ENOMEM;
  
@@ -44,7 +44,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  
  		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
  		txd->txd4 = 0;
-@@ -1513,7 +1513,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1538,7 +1538,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	if (itxd == ring->last_free)
  		return -ENOMEM;
  
@@ -53,7 +53,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	memset(itx_buf, 0, sizeof(*itx_buf));
  
  	txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1554,7 +1554,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1579,7 +1579,7 @@ static int mtk_tx_map(struct sk_buff *sk
  
  			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  			txd_info.size = min_t(unsigned int, frag_size,
@@ -62,7 +62,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			txd_info.qid = queue;
  			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
  					!(frag_size - txd_info.size);
-@@ -1567,7 +1567,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1592,7 +1592,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			mtk_tx_set_dma_desc(dev, txd, &txd_info);
  
  			tx_buf = mtk_desc_to_tx_buf(ring, txd,
@@ -71,7 +71,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			if (new_desc)
  				memset(tx_buf, 0, sizeof(*tx_buf));
  			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1610,7 +1610,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1635,7 +1635,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	} else {
  		int next_idx;
  
@@ -80,7 +80,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  					 ring->dma_size);
  		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
  	}
-@@ -1619,7 +1619,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1644,7 +1644,7 @@ static int mtk_tx_map(struct sk_buff *sk
  
  err_dma:
  	do {
@@ -89,7 +89,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  
  		/* unmap dma */
  		mtk_tx_unmap(eth, tx_buf, NULL, false);
-@@ -1644,7 +1644,7 @@ static int mtk_cal_txd_req(struct mtk_et
+@@ -1669,7 +1669,7 @@ static int mtk_cal_txd_req(struct mtk_et
  		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  			frag = &skb_shinfo(skb)->frags[i];
  			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
@@ -98,7 +98,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		}
  	} else {
  		nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1785,7 +1785,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
+@@ -1810,7 +1810,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
  
  		ring = &eth->rx_ring[i];
  		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
@@ -107,7 +107,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		if (rxd->rxd2 & RX_DMA_DONE) {
  			ring->calc_idx_update = true;
  			return ring;
-@@ -1953,7 +1953,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1978,7 +1978,7 @@ static int mtk_xdp_submit_frame(struct m
  	}
  	htxd = txd;
  
@@ -116,7 +116,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	memset(tx_buf, 0, sizeof(*tx_buf));
  	htx_buf = tx_buf;
  
-@@ -1972,7 +1972,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1997,7 +1997,7 @@ static int mtk_xdp_submit_frame(struct m
  				goto unmap;
  
  			tx_buf = mtk_desc_to_tx_buf(ring, txd,
@@ -125,7 +125,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			memset(tx_buf, 0, sizeof(*tx_buf));
  			n_desc++;
  		}
-@@ -2010,7 +2010,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -2035,7 +2035,7 @@ static int mtk_xdp_submit_frame(struct m
  	} else {
  		int idx;
  
@@ -134,7 +134,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
  			MT7628_TX_CTX_IDX0);
  	}
-@@ -2021,7 +2021,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -2046,7 +2046,7 @@ static int mtk_xdp_submit_frame(struct m
  
  unmap:
  	while (htxd != txd) {
@@ -143,7 +143,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		mtk_tx_unmap(eth, tx_buf, NULL, false);
  
  		htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2152,7 +2152,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2177,7 +2177,7 @@ static int mtk_poll_rx(struct napi_struc
  			goto rx_done;
  
  		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
@@ -152,7 +152,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		data = ring->data[idx];
  
  		if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2287,7 +2287,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2312,7 +2312,7 @@ static int mtk_poll_rx(struct napi_struc
  			rxdcsum = &trxd.rxd4;
  		}
  
@@ -161,7 +161,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			skb->ip_summed = CHECKSUM_UNNECESSARY;
  		else
  			skb_checksum_none_assert(skb);
-@@ -2411,7 +2411,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2436,7 +2436,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
  			break;
  
  		tx_buf = mtk_desc_to_tx_buf(ring, desc,
@@ -170,7 +170,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		if (!tx_buf->data)
  			break;
  
-@@ -2462,7 +2462,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
+@@ -2487,7 +2487,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
  
@@ -179,7 +179,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		ring->last_free = desc;
  		atomic_inc(&ring->free_count);
  
-@@ -2552,7 +2552,7 @@ static int mtk_napi_rx(struct napi_struc
+@@ -2577,7 +2577,7 @@ static int mtk_napi_rx(struct napi_struc
  	do {
  		int rx_done;
  
@@ -188,7 +188,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			reg_map->pdma.irq_status);
  		rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
  		rx_done_total += rx_done;
-@@ -2568,10 +2568,10 @@ static int mtk_napi_rx(struct napi_struc
+@@ -2593,10 +2593,10 @@ static int mtk_napi_rx(struct napi_struc
  			return budget;
  
  	} while (mtk_r32(eth, reg_map->pdma.irq_status) &
@@ -201,7 +201,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  
  	return rx_done_total;
  }
-@@ -2580,7 +2580,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2605,7 +2605,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  {
  	const struct mtk_soc_data *soc = eth->soc;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
@@ -210,7 +210,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	struct mtk_tx_dma_v2 *txd;
  	int ring_size;
  	u32 ofs, val;
-@@ -2703,14 +2703,14 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2728,14 +2728,14 @@ static void mtk_tx_clean(struct mtk_eth
  	}
  	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
  		dma_free_coherent(eth->dma_dev,
@@ -227,7 +227,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  				  ring->dma_pdma, ring->phys_pdma);
  		ring->dma_pdma = NULL;
  	}
-@@ -2765,15 +2765,15 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2790,15 +2790,15 @@ static int mtk_rx_alloc(struct mtk_eth *
  	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
  	    rx_flag != MTK_RX_FLAGS_NORMAL) {
  		ring->dma = dma_alloc_coherent(eth->dma_dev,
@@ -247,7 +247,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	}
  
  	if (!ring->dma)
-@@ -2784,7 +2784,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  		dma_addr_t dma_addr;
  		void *data;
  
@@ -256,7 +256,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		if (ring->page_pool) {
  			data = mtk_page_pool_get_buff(ring->page_pool,
  						      &dma_addr, GFP_KERNEL);
-@@ -2875,7 +2875,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2900,7 +2900,7 @@ static void mtk_rx_clean(struct mtk_eth
  			if (!ring->data[i])
  				continue;
  
@@ -265,7 +265,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			if (!rxd->rxd1)
  				continue;
  
-@@ -2892,7 +2892,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth
  
  	if (!in_sram && ring->dma) {
  		dma_free_coherent(eth->dma_dev,
@@ -274,7 +274,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  				  ring->dma, ring->phys);
  		ring->dma = NULL;
  	}
-@@ -3255,7 +3255,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3280,7 +3280,7 @@ static void mtk_dma_free(struct mtk_eth
  			netdev_reset_queue(eth->netdev[i]);
  	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
  		dma_free_coherent(eth->dma_dev,
@@ -283,7 +283,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  				  eth->scratch_ring, eth->phy_scratch_ring);
  		eth->scratch_ring = NULL;
  		eth->phy_scratch_ring = 0;
-@@ -3305,7 +3305,7 @@ static irqreturn_t mtk_handle_irq_rx(int
+@@ -3330,7 +3330,7 @@ static irqreturn_t mtk_handle_irq_rx(int
  
  	eth->rx_events++;
  	if (likely(napi_schedule_prep(&eth->rx_napi))) {
@@ -292,7 +292,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		__napi_schedule(&eth->rx_napi);
  	}
  
-@@ -3331,9 +3331,9 @@ static irqreturn_t mtk_handle_irq(int ir
+@@ -3356,9 +3356,9 @@ static irqreturn_t mtk_handle_irq(int ir
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  
  	if (mtk_r32(eth, reg_map->pdma.irq_mask) &
@@ -304,7 +304,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			mtk_handle_irq_rx(irq, _eth);
  	}
  	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3351,10 +3351,10 @@ static void mtk_poll_controller(struct n
+@@ -3376,10 +3376,10 @@ static void mtk_poll_controller(struct n
  	struct mtk_eth *eth = mac->hw;
  
  	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
@@ -317,7 +317,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  }
  #endif
  
-@@ -3517,7 +3517,7 @@ static int mtk_open(struct net_device *d
+@@ -3545,7 +3545,7 @@ static int mtk_open(struct net_device *d
  		napi_enable(&eth->tx_napi);
  		napi_enable(&eth->rx_napi);
  		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
@@ -326,7 +326,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		refcount_set(&eth->dma_refcnt, 1);
  	}
  	else
-@@ -3600,7 +3600,7 @@ static int mtk_stop(struct net_device *d
+@@ -3628,7 +3628,7 @@ static int mtk_stop(struct net_device *d
  	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
  
  	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
@@ -335,7 +335,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	napi_disable(&eth->tx_napi);
  	napi_disable(&eth->rx_napi);
  
-@@ -4076,9 +4076,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -4107,9 +4107,9 @@ static int mtk_hw_init(struct mtk_eth *e
  
  	/* FE int grouping */
  	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
@@ -347,7 +347,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
  	if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5176,11 +5176,15 @@ static const struct mtk_soc_data mt2701_
+@@ -5270,11 +5270,15 @@ static const struct mtk_soc_data mt2701_
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
  	.version = 1,
@@ -368,7 +368,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5196,11 +5200,15 @@ static const struct mtk_soc_data mt7621_
+@@ -5290,11 +5294,15 @@ static const struct mtk_soc_data mt7621_
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -389,7 +389,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5218,11 +5226,15 @@ static const struct mtk_soc_data mt7622_
+@@ -5312,11 +5320,15 @@ static const struct mtk_soc_data mt7622_
  	.hash_offset = 2,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@@ -410,7 +410,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5239,11 +5251,15 @@ static const struct mtk_soc_data mt7623_
+@@ -5333,11 +5345,15 @@ static const struct mtk_soc_data mt7623_
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
  	.disable_pll_modes = true,
@@ -431,7 +431,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5258,11 +5274,15 @@ static const struct mtk_soc_data mt7629_
+@@ -5352,11 +5368,15 @@ static const struct mtk_soc_data mt7629_
  	.required_pctl = false,
  	.has_accounting = true,
  	.version = 1,
@@ -452,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN,
  		.dma_len_offset = 16,
  	},
-@@ -5280,11 +5300,15 @@ static const struct mtk_soc_data mt7981_
+@@ -5374,11 +5394,15 @@ static const struct mtk_soc_data mt7981_
  	.hash_offset = 4,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -473,7 +473,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  		.dma_len_offset = 8,
  	},
-@@ -5302,11 +5326,15 @@ static const struct mtk_soc_data mt7986_
+@@ -5396,11 +5420,15 @@ static const struct mtk_soc_data mt7986_
  	.hash_offset = 4,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@@ -494,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  		.dma_len_offset = 8,
  	},
-@@ -5324,11 +5352,15 @@ static const struct mtk_soc_data mt7988_
+@@ -5418,11 +5446,15 @@ static const struct mtk_soc_data mt7988_
  	.hash_offset = 4,
  	.has_accounting = true,
  	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
@@ -515,7 +515,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  		.dma_len_offset = 8,
  	},
-@@ -5341,11 +5373,15 @@ static const struct mtk_soc_data rt5350_
+@@ -5435,11 +5467,15 @@ static const struct mtk_soc_data rt5350_
  	.required_clks = MT7628_CLKS_BITMAP,
  	.required_pctl = false,
  	.version = 1,
@@ -538,7 +538,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	},
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -326,8 +326,8 @@
+@@ -327,8 +327,8 @@
  /* QDMA descriptor txd3 */
  #define TX_DMA_OWNER_CPU	BIT(31)
  #define TX_DMA_LS0		BIT(30)
@@ -549,7 +549,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  #define TX_DMA_SWC		BIT(14)
  #define TX_DMA_PQID		GENMASK(3, 0)
  #define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
-@@ -347,8 +347,8 @@
+@@ -348,8 +348,8 @@
  /* QDMA descriptor rxd2 */
  #define RX_DMA_DONE		BIT(31)
  #define RX_DMA_LSO		BIT(30)
@@ -560,7 +560,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  #define RX_DMA_VTAG		BIT(15)
  #define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
  #if IS_ENABLED(CONFIG_64BIT)
-@@ -1279,10 +1279,9 @@ struct mtk_reg_map {
+@@ -1209,10 +1209,9 @@ struct mtk_reg_map {
   * @foe_entry_size		Foe table entry size.
   * @has_accounting		Bool indicating support for accounting of
   *				offloaded flows.
@@ -574,7 +574,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
   * @dma_max_len			Max DMA tx/rx buffer length.
   * @dma_len_offset		Tx/Rx DMA length field offset.
   */
-@@ -1300,13 +1299,17 @@ struct mtk_soc_data {
+@@ -1230,13 +1229,17 @@ struct mtk_soc_data {
  	bool		has_accounting;
  	bool		disable_pll_modes;
  	struct {
diff --git a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
index bebd7e870a..8b7d5c0a1c 100644
--- a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
+++ b/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
@@ -17,7 +17,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -108,16 +108,16 @@ static const struct mtk_reg_map mt7986_r
+@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
  	.tx_irq_mask		= 0x461c,
  	.tx_irq_status		= 0x4618,
  	.pdma = {
@@ -44,7 +44,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	},
  	.qdma = {
  		.qtx_cfg	= 0x4400,
-@@ -1207,7 +1207,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e
  	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
  	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
  	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
@@ -53,7 +53,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
  		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
  	}
-@@ -2159,7 +2159,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -62,7 +62,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
  
  			switch (val) {
-@@ -2271,7 +2271,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc
  		skb->dev = netdev;
  		bytes += skb->len;
  
@@ -71,7 +71,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
  			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
  			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2821,7 +2821,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
@@ -80,7 +80,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			rxd->rxd5 = 0;
  			rxd->rxd6 = 0;
  			rxd->rxd7 = 0;
-@@ -4022,7 +4022,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	else
  		mtk_hw_reset(eth);
  
@@ -89,7 +89,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		/* Set FE to PDMAv2 if necessary */
  		val = mtk_r32(eth, MTK_FE_GLO_MISC);
  		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5306,11 +5306,11 @@ static const struct mtk_soc_data mt7981_
+@@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_
  		.dma_len_offset = 8,
  	},
  	.rx = {
@@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	},
  };
  
-@@ -5332,11 +5332,11 @@ static const struct mtk_soc_data mt7986_
+@@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_
  		.dma_len_offset = 8,
  	},
  	.rx = {
diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile
index 9f5d374abd..316bf1dfa0 100644
--- a/target/linux/mvebu/Makefile
+++ b/target/linux/mvebu/Makefile
@@ -9,8 +9,7 @@ BOARDNAME:=Marvell EBU Armada
 FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard targz
 SUBTARGETS:=cortexa9 cortexa53 cortexa72
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/mvebu/config-5.15 b/target/linux/mvebu/config-5.15
deleted file mode 100644
index 0811ee6d4c..0000000000
--- a/target/linux/mvebu/config-5.15
+++ /dev/null
@@ -1,435 +0,0 @@
-CONFIG_AHCI_MVEBU=y
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARMADA_370_CLK=y
-CONFIG_ARMADA_370_XP_IRQ=y
-CONFIG_ARMADA_370_XP_TIMER=y
-# CONFIG_ARMADA_37XX_WATCHDOG is not set
-CONFIG_ARMADA_38X_CLK=y
-CONFIG_ARMADA_THERMAL=y
-CONFIG_ARMADA_XP_CLK=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
-# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_MVEBU_V7_CPUIDLE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_ATA_LEDS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_FEROCEON_L2 is not set
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_MARVELL=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRYPTO_ESSIV=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MVEBU_UART0=y
-# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
-# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xd0012000
-CONFIG_DEBUG_UART_VIRT=0xfec12000
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWBM=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-# CONFIG_I2C_PXA is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_JBD2=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PCA963X=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_ARMADA_370=y
-# CONFIG_MACH_ARMADA_375 is not set
-CONFIG_MACH_ARMADA_38X=y
-# CONFIG_MACH_ARMADA_39X is not set
-CONFIG_MACH_ARMADA_XP=y
-# CONFIG_MACH_DOVE is not set
-CONFIG_MACH_MVEBU_ANY=y
-CONFIG_MACH_MVEBU_V7=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MANGLE_BOOTARGS=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_I2C=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MVSDIO=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_PXAV3=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MARVELL=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVEBU_CLK_COMMON=y
-CONFIG_MVEBU_CLK_COREDIV=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_MVEBU_MBUS=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MVNETA_BM=y
-CONFIG_MVNETA_BM_ENABLE=y
-# CONFIG_MVPP2 is not set
-CONFIG_MV_XOR=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6XXX=y
-CONFIG_NET_DSA_TAG_DSA=y
-CONFIG_NET_DSA_TAG_DSA_COMMON=y
-CONFIG_NET_DSA_TAG_EDSA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_ORION_WATCHDOG=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PCI=y
-CONFIG_PCI_BRIDGE_EMUL=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
-# CONFIG_PHY_MVEBU_A3700_UTMI is not set
-# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_UTMI is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_38X=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_MVEBU=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PJ4B_ERRATA_4742=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PLAT_ORION=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_ARMADA38X=y
-# CONFIG_RTC_DRV_MV is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_MV=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SENSORS_PWM_FAN=y
-CONFIG_SENSORS_TMP421=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SFP=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_ARMADA_3700 is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ORION=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_ORION=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_LEDS_TRIGGER_USBPORT=y
-CONFIG_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MVEBU=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mvebu/cortexa53/config-5.15 b/target/linux/mvebu/cortexa53/config-5.15
deleted file mode 100644
index 27d410f68b..0000000000
--- a/target/linux/mvebu/cortexa53/config-5.15
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_37XX_RWTM_MBOX=y
-CONFIG_ARMADA_37XX_WATCHDOG=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_MHU_V2 is not set
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI_AARDVARK=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPI_ARMADA_3700=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TURRIS_MOX_RWTM=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/mvebu/cortexa72/config-5.15 b/target/linux/mvebu/cortexa72/config-5.15
deleted file mode 100644
index 978208f1cb..0000000000
--- a/target/linux/mvebu/cortexa72/config-5.15
+++ /dev/null
@@ -1,98 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_1742098=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_SVE=y
-# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CPU_CLK=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_8K_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_LEDS_IEI_WT61P803_PUZZLE=y
-CONFIG_LEDS_IS31FL319X=y
-CONFIG_MARVELL_10G_PHY=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_IEI_WT61P803_PUZZLE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_MVPP2=y
-CONFIG_MV_XOR_V2=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-# CONFIG_PCI_AARDVARK is not set
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_MVEBU_CP110_UTMI=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REGULATOR_GPIO=y
-# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
-CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/mvebu/cortexa9/config-5.15 b/target/linux/mvebu/cortexa9/config-5.15
deleted file mode 100644
index 266596d638..0000000000
--- a/target/linux/mvebu/cortexa9/config-5.15
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_MTD_SPLIT_SEIL_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_PHY_MVEBU_A38X_COMPHY=y
-CONFIG_POWER_RESET_QNAP=y
-CONFIG_RTC_DRV_MV=y
diff --git a/target/linux/mvebu/patches-5.15/100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch b/target/linux/mvebu/patches-5.15/100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch
deleted file mode 100644
index 67beb06541..0000000000
--- a/target/linux/mvebu/patches-5.15/100-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 81c0004a6433ff90fa6129418802c3c367e453c2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
-Date: Mon, 4 Jul 2022 13:36:21 +0200
-Subject: [PATCH 1/5] ARM: dts: turris-omnia: configure LED[0] pin function to
- link/activity
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The marvell PHY driver changes the LED[0] pin function to "On - 1000
-Mbps Link, Off - Else".
-
-Turris Omnia expects that the function is "On - Link, Blink - Activity,
-Off - No link".
-
-Use the `marvell,reg-init` DT property to change the function.
-
-In the future, once netdev trigger will support HW offloading, we will
-be able to have this configured via the combination of PHY driver and
-leds-turris-omnia driver.
-
-Signed-off-by: Marek Behún <kabel@kernel.org>
----
- arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
-+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
-@@ -396,7 +396,8 @@
- 	phy1: ethernet-phy@1 {
- 		compatible = "ethernet-phy-ieee802.3-c22";
- 		reg = <1>;
--		marvell,reg-init = <3 18 0 0x4985>;
-+		marvell,reg-init = <3 18 0 0x4985>,
-+				   <3 16 0xfff0 0x0001>;
- 
- 		/* irq is connected to &pcawan pin 7 */
- 	};
diff --git a/target/linux/mvebu/patches-5.15/100-aardvark-workaround-PCIe.patch b/target/linux/mvebu/patches-5.15/100-aardvark-workaround-PCIe.patch
deleted file mode 100644
index 975eadb80e..0000000000
--- a/target/linux/mvebu/patches-5.15/100-aardvark-workaround-PCIe.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
-Date:   Tue,  2 Aug 2022 14:38:16 +0200
-Message-Id: <20220802123816.21817-1-pali@kernel.org>
-X-Mailer: git-send-email 2.20.1
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-Precedence: bulk
-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci@vger.kernel.org
-
-Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
-document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
-that PCIe IP does not support a strong-ordered model for inbound posted vs.
-outbound completion.
-
-As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
-register must be set. It disables the ordering check in the core between
-Completions and Posted requests received from the link.
-
-Marvell also suggests to do full memory barrier at the beginning of
-aardvark summary interrupt handler before calling interrupt handlers of
-endpoint drivers in order to minimize the risk for the race condition
-documented in the Erratum between the DMA done status reading and the
-completion of writing to the host memory.
-
-More details about this issue and suggested workarounds are in discussion:
-https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
-
-It was reported that enabling this workaround fixes instability issues and
-"Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
-QCA6335 chip under significant load which were caused by interrupt status
-stuck in the outbound CMPLT queue traced back to this erratum.
-
-This workaround fixes also kernel panic triggered after some minutes of
-usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
-
-    Internal error: synchronous external abort: 96000210 [#1] SMP
-    Kernel panic - not syncing: Fatal exception in interrupt
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
-Cc: stable@vger.kernel.org
----
- drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/pci/controller/pci-aardvark.c
-+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -210,6 +210,8 @@ enum {
- };
- 
- #define VENDOR_ID_REG				(LMI_BASE_ADDR + 0x44)
-+#define DEBUG_MUX_CTRL_REG			(LMI_BASE_ADDR + 0x208)
-+#define     DIS_ORD_CHK				BIT(30)
- 
- /* PCIe core controller registers */
- #define CTRL_CORE_BASE_ADDR			0x18000
-@@ -558,6 +560,11 @@ static void advk_pcie_setup_hw(struct ad
- 		PCIE_CORE_CTRL2_TD_ENABLE;
- 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
- 
-+	/* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
-+	reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
-+	reg |= DIS_ORD_CHK;
-+	advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
-+
- 	/* Set lane X1 */
- 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- 	reg &= ~LANE_CNT_MSK;
-@@ -1580,6 +1587,9 @@ static irqreturn_t advk_pcie_irq_handler
- 	struct advk_pcie *pcie = arg;
- 	u32 status;
- 
-+	/* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
-+	mb();
-+
- 	status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
- 	if (!(status & PCIE_IRQ_CORE_INT))
- 		return IRQ_NONE;
diff --git a/target/linux/mvebu/patches-5.15/101-ARM-dts-turris-omnia-enable-LED-controller-node.patch b/target/linux/mvebu/patches-5.15/101-ARM-dts-turris-omnia-enable-LED-controller-node.patch
deleted file mode 100644
index ecfb43553f..0000000000
--- a/target/linux/mvebu/patches-5.15/101-ARM-dts-turris-omnia-enable-LED-controller-node.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From fed7cef5e4f2df8c6a79bebf5da1fdd3783ff6f3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
-Date: Mon, 4 Jul 2022 13:36:22 +0200
-Subject: [PATCH] ARM: dts: turris-omnia: enable LED controller node
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The LED controller node is disabled because the leds-turris-omnia driver
-does not support setting the LED blinking to be controlled by the MCU.
-
-The patches for that have now been sent [1], so let's enable the node.
-
-[1] https://lore.kernel.org/linux-leds/20220704105955.15474-1-kabel@kernel.org/T/
-
-Signed-off-by: Marek Behún <kabel@kernel.org>
----
- arch/arm/boot/dts/armada-385-turris-omnia.dts | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
-+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
-@@ -194,15 +194,13 @@
- 				reg = <0x2b>;
- 				#address-cells = <1>;
- 				#size-cells = <0>;
-+				status = "okay";
- 
- 				/*
- 				 * LEDs are controlled by MCU (STM32F0) at
- 				 * address 0x2b.
- 				 *
--				 * The driver does not support HW control mode
--				 * for the LEDs yet. Disable the LEDs for now.
--				 *
--				 * Also LED functions are not stable yet:
-+				 * LED functions are not stable yet:
- 				 * - there are 3 LEDs connected via MCU to PCIe
- 				 *   ports. One of these ports supports mSATA.
- 				 *   There is no mSATA nor PCIe function.
-@@ -213,7 +211,6 @@
- 				 *   B. Again there is no such function defined.
- 				 *   For now we use LED_FUNCTION_INDICATOR
- 				 */
--				status = "disabled";
- 
- 				multi-led@0 {
- 					reg = <0x0>;
diff --git a/target/linux/mvebu/patches-5.15/105-power-reset-linkstation-poweroff-add-ls220de.patch b/target/linux/mvebu/patches-5.15/105-power-reset-linkstation-poweroff-add-ls220de.patch
deleted file mode 100644
index 3223861234..0000000000
--- a/target/linux/mvebu/patches-5.15/105-power-reset-linkstation-poweroff-add-ls220de.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/drivers/power/reset/linkstation-poweroff.c
-+++ b/drivers/power/reset/linkstation-poweroff.c
-@@ -142,6 +142,12 @@ static void linkstation_poweroff(void)
- }
- 
- static const struct of_device_id ls_poweroff_of_match[] = {
-+	{ .compatible = "buffalo,ls220d",
-+	  .data = &linkstation_power_off_cfg,
-+	},
-+	{ .compatible = "buffalo,ls220de",
-+	  .data = &linkstation_power_off_cfg,
-+	},
- 	{ .compatible = "buffalo,ls421d",
- 	  .data = &linkstation_power_off_cfg,
- 	},
diff --git a/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
deleted file mode 100644
index bedeea4784..0000000000
--- a/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
+++ /dev/null
@@ -1,279 +0,0 @@
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-
-This patch has been modified to be mvebu specific. The original patch 
-did not pass the bootloader cmdline on if no append-rootblock stanza 
-was found, resulting in blank cmdline and failure to boot.
-
-Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
----
- arch/arm/Kconfig                        | 11 ++++
- arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-
- init/main.c                             | 16 +++++
- 3 files changed, 111 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1728,6 +1728,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 	  The command-line arguments provided by the boot loader will be
- 	  appended to the the device tree bootargs property.
- 
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+	bool "Append rootblock parsing bootloader's kernel arguments"
-+	help
-+	  The command-line arguments provided by the boot loader will be
-+	  appended to a new device tree property: bootloader-args.
-+	  If there is a property "append-rootblock" in DT under /chosen 
-+	  and a root= option in bootloaders command line it will be parsed 
-+	  and added to DT bootargs with the form: <append-rootblock>XX.
-+	  Only command line ATAG will be processed, the rest of the ATAGs
-+	  sent by bootloader will be ignored.
-+
- endchoice
- 
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
- 
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- 	return offset;
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- 		   void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- 		return offset;
- 	return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
- 
- static int setprop_string(void *fdt, const char *node_path,
- 			  const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- 	return fdt_setprop_string(fdt, offset, property, string);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- 			const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- 		return offset;
- 	return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
- 
- static const void *getprop(const void *fdt, const char *node_path,
- 			   const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- 	return fdt_getprop(fdt, offset, property, len);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- 	int len;
-@@ -69,6 +76,74 @@ static uint32_t get_cell_size(const void
- 	return cell_size;
- }
- 
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+	const char *ptr, *end;
-+	const char *root="root=";
-+	int i, l;
-+	const char *rootblock;
-+
-+	//ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
-+	ptr = str - 1;
-+
-+	do {
-+		//first find an 'r' at the begining or after a space
-+		do {
-+			ptr++;
-+			ptr = strchr(ptr, 'r');
-+			if (!ptr)
-+				goto no_append;
-+
-+		} while (ptr != str && *(ptr-1) != ' ');
-+
-+		//then check for the rest
-+		for(i = 1; i <= 4; i++)
-+			if(*(ptr+i) != *(root+i)) break;
-+
-+	} while (i != 5);
-+
-+	end = strchr(ptr, ' ');
-+	end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+	//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
-+	for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+	ptr = end + 1;
-+
-+	/* if append-rootblock property is set use it to append to command line */
-+	rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+	if (rootblock == NULL)
-+		goto no_append;
-+
-+	if (*dest != ' ') {
-+		*dest = ' ';
-+		dest++;
-+		len++;
-+	}
-+
-+	if (len + l + i <= COMMAND_LINE_SIZE) {
-+		memcpy(dest, rootblock, l);
-+		dest += l - 1;
-+		memcpy(dest, ptr, i);
-+		dest += i;
-+	}
-+
-+	return dest;
-+
-+no_append:
-+	len = strlen(str);
-+	if (len + 1 < COMMAND_LINE_SIZE) {
-+		memcpy(dest, str, len);
-+		dest += len;
-+	}
-+
-+	return dest;
-+}
-+#endif
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- 	char cmdline[COMMAND_LINE_SIZE];
-@@ -88,18 +163,28 @@ static void merge_fdt_bootargs(void *fdt
- 
- 	/* and append the ATAG_CMDLINE */
- 	if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+		//save original bootloader args
-+		//and append ubi.mtd with root partition number to current cmdline
-+		setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+		ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- 		len = strlen(fdt_cmdline);
- 		if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- 			*ptr++ = ' ';
- 			memcpy(ptr, fdt_cmdline, len);
- 			ptr += len;
- 		}
-+#endif
- 	}
- 	*ptr = '\0';
- 
- 	setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- 	uint32_t digit;
-@@ -117,6 +202,7 @@ static void hex_str(char *out, uint32_t
- 	}
- 	*out = '\0';
- }
-+#endif
- 
- /*
-  * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +217,11 @@ int atags_to_fdt(void *atag_list, void *
- 	struct tag *atag = atag_list;
- 	/* In the case of 64 bits memory size, need to reserve 2 cells for
- 	 * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- 	__be32 mem_reg_property[2 * 2 * NR_BANKS];
--	int memcount = 0;
--	int ret, memsize;
-+	int memsize, memcount = 0;
-+#endif
-+	int ret;
- 
- 	/* make sure we've got an aligned pointer */
- 	if ((u32)atag_list & 0x3)
-@@ -168,7 +256,9 @@ int atags_to_fdt(void *atag_list, void *
- 			else
- 				setprop_string(fdt, "/chosen", "bootargs",
- 					       atag->u.cmdline.cmdline);
--		} else if (atag->hdr.tag == ATAG_MEM) {
-+		}
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+		else if (atag->hdr.tag == ATAG_MEM) {
- 			if (memcount >= sizeof(mem_reg_property)/4)
- 				continue;
- 			if (!atag->u.mem.size)
-@@ -212,6 +302,10 @@ int atags_to_fdt(void *atag_list, void *
- 		setprop(fdt, "/memory", "reg", mem_reg_property,
- 			4 * memcount * memsize);
- 	}
-+#else
-+
-+	}
-+#endif
- 
- 	return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -112,6 +112,10 @@
- 
- #include <kunit/test.h>
- 
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
- 
- extern void init_IRQ(void);
-@@ -992,6 +996,18 @@ asmlinkage __visible void __init __no_sa
- 	page_alloc_init();
- 
- 	pr_notice("Kernel command line: %s\n", saved_command_line);
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+	//Show bootloader's original command line for reference
-+	if(of_chosen) {
-+		const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+		if(prop)
-+			pr_notice("Bootloader command line (ignored): %s\n", prop);
-+		else
-+			pr_notice("Bootloader command line not present\n");
-+	}
-+#endif
-+
- 	/* parameters may set static keys */
- 	jump_label_init();
- 	parse_early_param();
diff --git a/target/linux/mvebu/patches-5.15/301-mvebu-armada-38x-enable-libata-leds.patch b/target/linux/mvebu/patches-5.15/301-mvebu-armada-38x-enable-libata-leds.patch
deleted file mode 100644
index 615caac24f..0000000000
--- a/target/linux/mvebu/patches-5.15/301-mvebu-armada-38x-enable-libata-leds.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/mach-mvebu/Kconfig
-+++ b/arch/arm/mach-mvebu/Kconfig
-@@ -67,6 +67,7 @@ config MACH_ARMADA_38X
- 	select HAVE_ARM_TWD if SMP
- 	select MACH_MVEBU_V7
- 	select PINCTRL_ARMADA_38X
-+	select ARCH_WANT_LIBATA_LEDS
- 	help
- 	  Say 'Y' here if you want your kernel to support boards based
- 	  on the Marvell Armada 380/385 SoC with device tree.
diff --git a/target/linux/mvebu/patches-5.15/302-add_powertables.patch b/target/linux/mvebu/patches-5.15/302-add_powertables.patch
deleted file mode 100644
index 93ad5de2cc..0000000000
--- a/target/linux/mvebu/patches-5.15/302-add_powertables.patch
+++ /dev/null
@@ -1,770 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -214,11 +214,19 @@
- &pcie1 {
- 	/* Marvell 88W8864, 5GHz-only */
- 	status = "okay";
-+
-+	mwlwifi {
-+		marvell,2ghz = <0>;
-+	};
- };
- 
- &pcie2 {
- 	/* Marvell 88W8864, 2GHz-only */
- 	status = "okay";
-+
-+	mwlwifi {
-+		marvell,5ghz = <0>;
-+	};
- };
- 
- &pinctrl {
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <2 2>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
-+			CA =
-+				<36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+			CN =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
-+			ETSI =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
-+			FCC =
-+				<36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <2 2>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
-+				<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
-+			CN =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+			CA =
-+				<36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+			CN =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+			ETSI =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+			FCC =
-+				<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+			CN =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+			CA =
-+				<36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+			CN =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+			ETSI =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+			FCC =
-+				<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+			CN =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -157,6 +157,18 @@
- 	};
- };
- 
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+	};
-+};
-+
- &sdhci {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&sdhci_pins>;
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -225,12 +225,100 @@
- 	pcie@2,0 {
- 		/* Port 0, Lane 1 */
- 		status = "okay";
-+
-+		mwlwifi {
-+			marvell,5ghz = <0>;
-+			marvell,chainmask = <4 4>;
-+			marvell,powertable {
-+				FCC =
-+					<1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
-+					<2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
-+
-+				ETSI =
-+					<1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
-+			};
-+		};
- 	};
- 
- 	/* Second mini-PCIe port */
- 	pcie@3,0 {
- 		/* Port 0, Lane 3 */
- 		status = "okay";
-+
-+		mwlwifi {
-+			marvell,2ghz = <0>;
-+			marvell,chainmask = <4 4>;
-+			marvell,powertable {
-+				FCC =
-+					<36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
-+
-+				ETSI =
-+					<36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
-+			};
-+		};
- 	};
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/304-revert_i2c_delay.patch b/target/linux/mvebu/patches-5.15/304-revert_i2c_delay.patch
deleted file mode 100644
index 930c0f9494..0000000000
--- a/target/linux/mvebu/patches-5.15/304-revert_i2c_delay.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -237,12 +237,10 @@
- };
- 
- &i2c0 {
--	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- 	reg = <0x11000 0x100>;
- };
- 
- &i2c1 {
--	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- 	reg = <0x11100 0x100>;
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/305-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-5.15/305-armada-385-rd-mtd-partitions.patch
deleted file mode 100644
index 31bd53b1f3..0000000000
--- a/target/linux/mvebu/patches-5.15/305-armada-385-rd-mtd-partitions.patch
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/arch/arm/boot/dts/armada-388-rd.dts
-+++ b/arch/arm/boot/dts/armada-388-rd.dts
-@@ -103,6 +103,16 @@
- 		compatible = "st,m25p128", "jedec,spi-nor";
- 		reg = <0>; /* Chip select 0 */
- 		spi-max-frequency = <108000000>;
-+
-+		partition@0 {
-+			label = "uboot";
-+			reg = <0 0x400000>;
-+		};
-+
-+		partition@1 {
-+			label = "firmware";
-+			reg = <0x400000 0xc00000>;
-+		};
- 	};
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/306-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-5.15/306-ARM-mvebu-385-ap-Add-partitions.patch
deleted file mode 100644
index 2057e31c7e..0000000000
--- a/target/linux/mvebu/patches-5.15/306-ARM-mvebu-385-ap-Add-partitions.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 13 Jan 2015 11:14:09 +0100
-Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/arm/boot/dts/armada-385-db-ap.dts
-+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
-@@ -218,19 +218,19 @@
- 			#size-cells = <1>;
- 
- 			partition@0 {
--				label = "U-Boot";
-+				label = "u-boot";
- 				reg = <0x00000000 0x00800000>;
- 				read-only;
- 			};
- 
- 			partition@800000 {
--				label = "uImage";
-+				label = "kernel";
- 				reg = <0x00800000 0x00400000>;
- 				read-only;
- 			};
- 
- 			partition@c00000 {
--				label = "Root";
-+				label = "ubi";
- 				reg = <0x00c00000 0x3f400000>;
- 			};
- 		};
diff --git a/target/linux/mvebu/patches-5.15/307-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-5.15/307-armada-xp-linksys-mamba-broken-idle.patch
deleted file mode 100644
index 16112d53fc..0000000000
--- a/target/linux/mvebu/patches-5.15/307-armada-xp-linksys-mamba-broken-idle.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -485,3 +485,7 @@
- 		};
- 	};
- };
-+
-+&coherencyfab {
-+	broken-idle;
-+};
diff --git a/target/linux/mvebu/patches-5.15/308-armada-xp-linksys-mamba-wan.patch b/target/linux/mvebu/patches-5.15/308-armada-xp-linksys-mamba-wan.patch
deleted file mode 100644
index 4315abc7d2..0000000000
--- a/target/linux/mvebu/patches-5.15/308-armada-xp-linksys-mamba-wan.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -387,7 +387,7 @@
- 
- 			port@4 {
- 				reg = <4>;
--				label = "internet";
-+				label = "wan";
- 			};
- 
- 			port@5 {
diff --git a/target/linux/mvebu/patches-5.15/309-linksys-status-led.patch b/target/linux/mvebu/patches-5.15/309-linksys-status-led.patch
deleted file mode 100644
index e5e83572c9..0000000000
--- a/target/linux/mvebu/patches-5.15/309-linksys-status-led.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -14,6 +14,13 @@
- 	compatible = "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- 
-+	aliases {
-+		led-boot = &led_power;
-+		led-failsafe = &led_power;
-+		led-running = &led_power;
-+		led-upgrade = &led_power;
-+	};
-+
- 	chosen {
- 		stdout-path = "serial0:115200n8";
- 	};
-@@ -71,7 +78,7 @@
- 		pinctrl-0 = <&gpio_leds_pins>;
- 		pinctrl-names = "default";
- 
--		power {
-+		led_power: power {
- 			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- 			default-state = "on";
- 		};
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -26,6 +26,13 @@
- 	compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
- 		     "marvell,armadaxp", "marvell,armada-370-xp";
- 
-+	aliases {
-+		led-boot = &led_power;
-+		led-failsafe = &led_power;
-+		led-running = &led_power;
-+		led-upgrade = &led_power;
-+	};
-+
- 	chosen {
- 		bootargs = "console=ttyS0,115200";
- 		stdout-path = &uart0;
-@@ -197,7 +204,7 @@
- 		pinctrl-0 = <&power_led_pin>;
- 		pinctrl-names = "default";
- 
--		power {
-+		led_power: power {
- 			label = "mamba:white:power";
- 			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- 			default-state = "on";
diff --git a/target/linux/mvebu/patches-5.15/310-linksys-use-eth0-as-cpu-port.patch b/target/linux/mvebu/patches-5.15/310-linksys-use-eth0-as-cpu-port.patch
deleted file mode 100644
index 84d49a004b..0000000000
--- a/target/linux/mvebu/patches-5.15/310-linksys-use-eth0-as-cpu-port.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -116,7 +116,7 @@
- };
- 
- &eth2 {
--	status = "okay";
-+	status = "disabled";
- 	phy-mode = "sgmii";
- 	buffer-manager = <&bm>;
- 	bm,pool-long = <2>;
-@@ -200,10 +200,10 @@
- 				label = "wan";
- 			};
- 
--			port@5 {
--				reg = <5>;
-+			port@6 {
-+				reg = <6>;
- 				label = "cpu";
--				ethernet = <&eth2>;
-+				ethernet = <&eth0>;
- 
- 				fixed-link {
- 					speed = <1000>;
diff --git a/target/linux/mvebu/patches-5.15/311-adjust-compatible-for-linksys.patch b/target/linux/mvebu/patches-5.15/311-adjust-compatible-for-linksys.patch
deleted file mode 100644
index a5d3e63810..0000000000
--- a/target/linux/mvebu/patches-5.15/311-adjust-compatible-for-linksys.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -12,8 +12,8 @@
- 
- / {
- 	model = "Linksys WRT3200ACM";
--	compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
--		     "marvell,armada380";
-+	compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385",
-+		     "marvell,armada385", "marvell,armada380";
- };
- 
- &expander0 {
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -22,9 +22,10 @@
- #include "armada-xp-mv78230.dtsi"
- 
- / {
--	model = "Linksys WRT1900AC";
--	compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
--		     "marvell,armadaxp", "marvell,armada-370-xp";
-+	model = "Linksys WRT1900AC v1";
-+	compatible = "linksys,wrt1900ac-v1", "linksys,mamba",
-+		     "marvell,armadaxp-mv78230", "marvell,armadaxp",
-+		     "marvell,armada-370-xp";
- 
- 	aliases {
- 		led-boot = &led_power;
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -9,8 +9,9 @@
- #include "armada-385-linksys.dtsi"
- 
- / {
--	model = "Linksys WRT1900ACv2";
--	compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
-+	model = "Linksys WRT1900AC v2";
-+	compatible = "linksys,wrt1900ac-v2", "linksys,cobra",
-+		     "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- };
- 
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -10,8 +10,8 @@
- 
- / {
- 	model = "Linksys WRT1200AC";
--	compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
--		     "marvell,armada380";
-+	compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385",
-+		     "marvell,armada385", "marvell,armada380";
- };
- 
- &expander0 {
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -10,7 +10,8 @@
- 
- / {
- 	model = "Linksys WRT1900ACS";
--	compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
-+	compatible = "linksys,wrt1900acs", "linksys,shelby",
-+		     "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- };
- 
diff --git a/target/linux/mvebu/patches-5.15/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-5.15/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
deleted file mode 100644
index dd2bef7f63..0000000000
--- a/target/linux/mvebu/patches-5.15/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 29 Nov 2016 10:15:45 +0000
-Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- arch/arm/boot/dts/armada-388-clearfog-base.dts     |  1 +
- .../dts/armada-38x-solidrun-microsom-emmc.dtsi     | 62 ++++++++++++++++++++++
- 2 files changed, 63 insertions(+)
- create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-
---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
-+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
-@@ -7,6 +7,7 @@
- 
- /dts-v1/;
- #include "armada-388-clearfog.dtsi"
-+#include "armada-38x-solidrun-microsom-emmc.dtsi"
- 
- / {
- 	model = "SolidRun Clearfog Base A1";
---- /dev/null
-+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-@@ -0,0 +1,62 @@
-+/*
-+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
-+ *
-+ *  Copyright (C) 2015 Russell King
-+ *
-+ * This board is in development; the contents of this file work with
-+ * the A1 rev 2.0 of the board, which does not represent final
-+ * production board.  Things will change, don't expect this file to
-+ * remain compatible info the future.
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This file is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License
-+ *     version 2 as published by the Free Software Foundation.
-+ *
-+ *     This file is distributed in the hope that it will be useful
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/ {
-+	soc {
-+		internal-regs {
-+			sdhci@d8000 {
-+				bus-width = <4>;
-+				no-1-8-v;
-+				non-removable;
-+				pinctrl-0 = <&microsom_sdhci_pins>;
-+				pinctrl-names = "default";
-+				status = "okay";
-+				wp-inverted;
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/mvebu/patches-5.15/313-helios4-dts-status-led-alias.patch b/target/linux/mvebu/patches-5.15/313-helios4-dts-status-led-alias.patch
deleted file mode 100644
index 607f436297..0000000000
--- a/target/linux/mvebu/patches-5.15/313-helios4-dts-status-led-alias.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/arch/arm/boot/dts/armada-388-helios4.dts
-+++ b/arch/arm/boot/dts/armada-388-helios4.dts
-@@ -15,6 +15,13 @@
- 	model = "Helios4";
- 	compatible = "kobol,helios4", "marvell,armada388",
- 		"marvell,armada385", "marvell,armada380";
-+		
-+	aliases {
-+		led-boot = &led_status;
-+		led-failsafe = &led_status;
-+		led-running = &led_status;
-+		led-upgrade = &led_status;
-+	};
- 
- 	memory {
- 		device_type = "memory";
-@@ -73,10 +80,9 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&helios_system_led_pins>;
- 
--		status-led {
-+		led_status: status-led {
- 			label = "helios4:green:status";
- 			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
--			linux,default-trigger = "heartbeat";
- 			default-state = "on";
- 		};
- 
diff --git a/target/linux/mvebu/patches-5.15/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch b/target/linux/mvebu/patches-5.15/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch
deleted file mode 100644
index 7221e04de1..0000000000
--- a/target/linux/mvebu/patches-5.15/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From: Tomasz Maciej Nowak <tmn505@gmail.com>
-Date: Fri, 7 Jul 2023 19:06:05 +0200
-Subject: [PATCH] arm64: dts: marvell: enable heartbeat LED by default
-
-Some boards could be placed in an enclosure, so enable LED18 by default,
-since that'll be the only visible indicator that the board is operating.
-
-Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
----
- arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-@@ -25,6 +25,7 @@
- 			function = LED_FUNCTION_HEARTBEAT;
- 			color = <LED_COLOR_ID_GREEN>;
- 			linux,default-trigger = "heartbeat";
-+			default-state = "on";
- 		};
- 	};
- };
diff --git a/target/linux/mvebu/patches-5.15/315-armada-xp-linksys-mamba-resize-kernel.patch b/target/linux/mvebu/patches-5.15/315-armada-xp-linksys-mamba-resize-kernel.patch
deleted file mode 100644
index f1fddceff4..0000000000
--- a/target/linux/mvebu/patches-5.15/315-armada-xp-linksys-mamba-resize-kernel.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001
-From: Tad <tad@spotco.us>
-Date: Fri, 5 Feb 2021 22:32:11 -0500
-Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel
- partition to 4MB
-
-Signed-off-by: Tad Davanzo <tad@spotco.us>
----
- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -456,9 +456,9 @@
- 				reg = <0xa00000 0x2800000>;  /* 40MB */
- 			};
- 
--			partition@d00000 {
-+			partition@e00000 {
- 				label = "rootfs1";
--				reg = <0xd00000 0x2500000>;  /* 37MB */
-+				reg = <0xe00000 0x2400000>;  /* 36MB */
- 			};
- 
- 			/* kernel2 overlaps with rootfs2 by design */
-@@ -467,9 +467,9 @@
- 				reg = <0x3200000 0x2800000>; /* 40MB */
- 			};
- 
--			partition@3500000 {
-+			partition@3600000 {
- 				label = "rootfs2";
--				reg = <0x3500000 0x2500000>; /* 37MB */
-+				reg = <0x3600000 0x2400000>; /* 36MB */
- 			};
- 
- 			/*
diff --git a/target/linux/mvebu/patches-5.15/316-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.15/316-armada-370-dts-fix-crypto-engine.patch
deleted file mode 100644
index 19378870ef..0000000000
--- a/target/linux/mvebu/patches-5.15/316-armada-370-dts-fix-crypto-engine.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -234,7 +234,7 @@
- 				clocks = <&gateclk 23>;
- 				clock-names = "cesa0";
- 				marvell,crypto-srams = <&crypto_sram>;
--				marvell,crypto-sram-size = <0x7e0>;
-+				marvell,crypto-sram-size = <0x800>;
- 			};
- 		};
- 
-@@ -255,12 +255,17 @@
- 			 * cpuidle workaround.
- 			 */
- 			idle-sram@0 {
-+				status = "disabled";
- 				reg = <0x0 0x20>;
- 			};
- 		};
- 	};
- };
- 
-+&coherencyfab {
-+	broken-idle;
-+};
-+
- /*
-  * Default UART pinctrl setting without RTS/CTS, can be overwritten on
-  * board level if a different configuration is used.
diff --git a/target/linux/mvebu/patches-5.15/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch b/target/linux/mvebu/patches-5.15/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch
deleted file mode 100644
index 280fc5957e..0000000000
--- a/target/linux/mvebu/patches-5.15/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch
+++ /dev/null
@@ -1,134 +0,0 @@
---- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-@@ -31,6 +31,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
-+		append-rootblock = "nullparameter="; /* override the bootloader args */
- 	};
- 
- 	memory@0 {
-@@ -94,6 +95,8 @@
- 			       status = "okay";
- 			       phy = <&phy1>;
- 			       phy-mode = "sgmii";
-+		               nvmem-cells = <&macaddr_vendor_0>;
-+        		       nvmem-cell-names = "mac-address";
- 			};
- 
- 			sata@a0000 {
-@@ -175,6 +178,24 @@
- 			gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- 		};
- 	};
-+
-+	virtual_flash {
-+		compatible = "mtd-concat";
-+
-+		devices = <&mtd_kernel &mtd_gap &mtd_gap2>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				compatible = "openwrt,uimage", "denx,uimage";
-+				label = "firmware";
-+				reg = <0x0 0x0>;
-+			};
-+		};
-+	};
- };
- 
- &mdio {
-@@ -265,48 +286,52 @@
- 		reg = <0>; /* Chip select 0 */
- 		spi-max-frequency = <20000000>;
- 
--		/*
--		 * Warning!
--		 *
--		 * Synology u-boot uses its compiled-in environment
--		 * and it seems Synology did not care to change u-boot
--		 * default configuration in order to allow saving a
--		 * modified environment at a sensible location. So,
--		 * if you do a 'saveenv' under u-boot, your modified
--		 * environment will be saved at 1MB after the start
--		 * of the flash, i.e. in the middle of the uImage.
--		 * For that reason, it is strongly advised not to
--		 * change the default environment, unless you know
--		 * what you are doing.
--		 */
--		partition@0 { /* u-boot */
--			label = "RedBoot";
--			reg = <0x00000000 0x000c0000>; /* 768KB */
--		};
-+		partitions {
-+			compatible = "fixed-partitions";
- 
--		partition@c0000 { /* uImage */
--			label = "zImage";
--			reg = <0x000c0000 0x002d0000>; /* 2880KB */
--		};
-+			partition@0 { /* u-boot */
-+				label = "u-boot";
-+				reg = <0x00000000 0x000c0000>; /* 768KB */
-+				read-only;
-+			};
- 
--		partition@390000 { /* uInitramfs */
--			label = "rd.gz";
--			reg = <0x00390000 0x00440000>; /* 4250KB */
--		};
-+			mtd_gap: partition@c0000 { /* gap */
-+				label = "gap";
-+				reg = <0x000c0000 0x00040000>; /* 256KB */
-+			};
- 
--		partition@7d0000 { /* MAC address and serial number */
--			label = "vendor";
--			reg = <0x007d0000 0x00010000>; /* 64KB */
--		};
-+			partition@100000 { /* u-boot-env */
-+				label = "u-boot-env";
-+				reg = <0x00100000 0x00010000>; /* 64KB */
-+			};
- 
--		partition@7e0000 {
--			label = "RedBoot config";
--			reg = <0x007e0000 0x00010000>; /* 64KB */
--		};
-+			mtd_kernel: partition@110000 {
-+				label = "kernel";
-+				reg = <0x00110000 0x006c0000>; /* 6912KB */
-+			};
- 
--		partition@7f0000 {
--			label = "FIS directory";
--			reg = <0x007f0000 0x00010000>; /* 64KB */
-+			partition@7d0000 { /* MAC address and serial number */
-+				reg = <0x007d0000 0x00010000>; /* 64KB */
-+				label = "vendor";
-+				read-only;
-+
-+				compatible = "nvmem-cells";
-+
-+				nvmem-layout {
-+					compatible = "fixed-layout";
-+					#address-cells = <1>;
-+					#size-cells = <1>;
-+
-+					macaddr_vendor_0: macaddr@0 {
-+						reg = <0x0 0x6>;
-+					};
-+				};
-+			};
-+
-+			mtd_gap2: partition@7e0000 {
-+				label = "gap2";
-+				reg = <0x007e0000 0x00020000>; /* 128KB */
-+			};
- 		};
- 	};
- };
diff --git a/target/linux/mvebu/patches-5.15/400-find_active_root.patch b/target/linux/mvebu/patches-5.15/400-find_active_root.patch
deleted file mode 100644
index 5582d20c68..0000000000
--- a/target/linux/mvebu/patches-5.15/400-find_active_root.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-The WRT1900AC among other Linksys routers uses a dual-firmware layout.
-Dynamically rename the active partition to "ubi".
-
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-
---- a/drivers/mtd/parsers/ofpart_core.c
-+++ b/drivers/mtd/parsers/ofpart_core.c
-@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d
- 	return of_get_property(pp, "compatible", NULL);
- }
- 
-+static int mangled_rootblock;
-+
- static int parse_fixed_partitions(struct mtd_info *master,
- 				  const struct mtd_partition **pparts,
- 				  struct mtd_part_parser_data *data)
-@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct
- 	struct device_node *mtd_node;
- 	struct device_node *ofpart_node;
- 	const char *partname;
-+	const char *owrtpart = "ubi";
- 	struct device_node *pp;
- 	int nr_parts, i, ret = 0;
- 	bool dedicated = true;
-@@ -133,9 +136,13 @@ static int parse_fixed_partitions(struct
- 		parts[i].size = of_read_number(reg + a_cells, s_cells);
- 		parts[i].of_node = pp;
- 
--		partname = of_get_property(pp, "label", &len);
--		if (!partname)
--			partname = of_get_property(pp, "name", &len);
-+		if (mangled_rootblock && (i == mangled_rootblock)) {
-+			partname = owrtpart;
-+		} else {
-+			partname = of_get_property(pp, "label", &len);
-+			if (!partname)
-+				partname = of_get_property(pp, "name", &len);
-+		}
- 		parts[i].name = partname;
- 
- 		if (of_get_property(pp, "read-only", &len))
-@@ -252,6 +259,18 @@ static int __init ofpart_parser_init(voi
- 	return 0;
- }
- 
-+static int __init active_root(char *str)
-+{
-+	get_option(&str, &mangled_rootblock);
-+
-+	if (!mangled_rootblock)
-+		return 1;
-+
-+	return 1;
-+}
-+
-+__setup("mangled_rootblock=", active_root);
-+
- static void __exit ofpart_parser_exit(void)
- {
- 	deregister_mtd_parser(&ofpart_parser);
diff --git a/target/linux/mvebu/patches-5.15/700-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-5.15/700-mvneta-tx-queue-workaround.patch
deleted file mode 100644
index 32e8ef4b7d..0000000000
--- a/target/linux/mvebu/patches-5.15/700-mvneta-tx-queue-workaround.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-The hardware queue scheduling is apparently configured with fixed
-priorities, which creates a nasty fairness issue where traffic from one
-CPU can starve traffic from all other CPUs.
-
-Work around this issue by forcing all tx packets to go through one CPU,
-until this issue is fixed properly.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -5006,6 +5006,16 @@ static int mvneta_setup_tc(struct net_de
- 	}
- }
- 
-+#ifndef CONFIG_ARM64
-+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
-+			       struct net_device *sb_dev)
-+{
-+	/* XXX: hardware queue scheduling is broken,
-+	 * use only one queue until it is fixed */
-+	return 0;
-+}
-+#endif
-+
- static const struct net_device_ops mvneta_netdev_ops = {
- 	.ndo_open            = mvneta_open,
- 	.ndo_stop            = mvneta_stop,
-@@ -5016,6 +5026,9 @@ static const struct net_device_ops mvnet
- 	.ndo_fix_features    = mvneta_fix_features,
- 	.ndo_get_stats64     = mvneta_get_stats64,
- 	.ndo_eth_ioctl        = mvneta_ioctl,
-+#ifndef CONFIG_ARM64
-+	.ndo_select_queue    = mvneta_select_queue,
-+#endif
- 	.ndo_bpf	     = mvneta_xdp,
- 	.ndo_xdp_xmit        = mvneta_xdp_xmit,
- 	.ndo_setup_tc	     = mvneta_setup_tc,
diff --git a/target/linux/mvebu/patches-5.15/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch b/target/linux/mvebu/patches-5.15/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch
deleted file mode 100644
index 019b9528c3..0000000000
--- a/target/linux/mvebu/patches-5.15/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 75fa71e3acadbb4ab5eda18505277eb9a1f69b23 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:53 +0100
-Subject: net: mvneta: Use struct tc_mqprio_qopt_offload for MQPrio
- configuration
-
-The struct tc_mqprio_qopt_offload is a container for struct tc_mqprio_qopt,
-that allows passing extra parameters, such as traffic shaping. This commit
-converts the current mqprio code to that new struct.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 17 ++++++++++-------
- 1 file changed, 10 insertions(+), 7 deletions(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -38,6 +38,7 @@
- #include <net/ipv6.h>
- #include <net/tso.h>
- #include <net/page_pool.h>
-+#include <net/pkt_cls.h>
- #include <linux/bpf_trace.h>
- 
- /* Registers */
-@@ -4966,14 +4967,14 @@ static void mvneta_setup_rx_prio_map(str
- }
- 
- static int mvneta_setup_mqprio(struct net_device *dev,
--			       struct tc_mqprio_qopt *qopt)
-+			       struct tc_mqprio_qopt_offload *mqprio)
- {
- 	struct mvneta_port *pp = netdev_priv(dev);
- 	u8 num_tc;
- 	int i;
- 
--	qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
--	num_tc = qopt->num_tc;
-+	mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
-+	num_tc = mqprio->qopt.num_tc;
- 
- 	if (num_tc > rxq_number)
- 		return -EINVAL;
-@@ -4984,13 +4985,15 @@ static int mvneta_setup_mqprio(struct ne
- 		return 0;
- 	}
- 
--	memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map));
-+	memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
-+	       sizeof(pp->prio_tc_map));
- 
- 	mvneta_setup_rx_prio_map(pp);
- 
--	netdev_set_num_tc(dev, qopt->num_tc);
--	for (i = 0; i < qopt->num_tc; i++)
--		netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]);
-+	netdev_set_num_tc(dev, mqprio->qopt.num_tc);
-+	for (i = 0; i < mqprio->qopt.num_tc; i++)
-+		netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
-+				    mqprio->qopt.offset[i]);
- 
- 	return 0;
- }
diff --git a/target/linux/mvebu/patches-5.15/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch b/target/linux/mvebu/patches-5.15/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch
deleted file mode 100644
index c878a28843..0000000000
--- a/target/linux/mvebu/patches-5.15/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e7ca75fe6662f78bfeb0112671c812e4c7b8e214 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:54 +0100
-Subject: net: mvneta: Don't force-set the offloading flag
-
-The qopt->hw flag is set by the TC code according to the offloading mode
-asked by user. Don't force-set it in the driver, but instead read it to
-make sure we do what's asked.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -4973,7 +4973,9 @@ static int mvneta_setup_mqprio(struct ne
- 	u8 num_tc;
- 	int i;
- 
--	mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
-+	if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
-+		return 0;
-+
- 	num_tc = mqprio->qopt.num_tc;
- 
- 	if (num_tc > rxq_number)
diff --git a/target/linux/mvebu/patches-5.15/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch b/target/linux/mvebu/patches-5.15/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch
deleted file mode 100644
index 546a8486ef..0000000000
--- a/target/linux/mvebu/patches-5.15/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From e9f7099d0730341b24c057acbf545dd019581db6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:55 +0100
-Subject: net: mvneta: Allow having more than one queue per TC
-
-The current mqprio implementation assumed that we are only using one
-queue per TC. Use the offset and count parameters to allow using
-multiple queues per TC. In that case, the controller will use a standard
-round-robin algorithm to pick queues assigned to the same TC, with the
-same priority.
-
-This only applies to VLAN priorities in ingress traffic, each TC
-corresponding to a vlan priority.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 35 ++++++++++++++++++++---------------
- 1 file changed, 20 insertions(+), 15 deletions(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -498,7 +498,6 @@ struct mvneta_port {
- 	u8 mcast_count[256];
- 	u16 tx_ring_size;
- 	u16 rx_ring_size;
--	u8 prio_tc_map[8];
- 
- 	phy_interface_t phy_interface;
- 	struct device_node *dn;
-@@ -4955,13 +4954,12 @@ static void mvneta_clear_rx_prio_map(str
- 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);
- }
- 
--static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)
-+static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq)
- {
--	u32 val = 0;
--	int i;
-+	u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);
- 
--	for (i = 0; i < rxq_number; i++)
--		val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]);
-+	val &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7);
-+	val |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq);
- 
- 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
- }
-@@ -4970,8 +4968,8 @@ static int mvneta_setup_mqprio(struct ne
- 			       struct tc_mqprio_qopt_offload *mqprio)
- {
- 	struct mvneta_port *pp = netdev_priv(dev);
-+	int rxq, tc;
- 	u8 num_tc;
--	int i;
- 
- 	if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
- 		return 0;
-@@ -4981,21 +4979,28 @@ static int mvneta_setup_mqprio(struct ne
- 	if (num_tc > rxq_number)
- 		return -EINVAL;
- 
-+	mvneta_clear_rx_prio_map(pp);
-+
- 	if (!num_tc) {
--		mvneta_clear_rx_prio_map(pp);
- 		netdev_reset_tc(dev);
- 		return 0;
- 	}
- 
--	memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
--	       sizeof(pp->prio_tc_map));
-+	netdev_set_num_tc(dev, mqprio->qopt.num_tc);
- 
--	mvneta_setup_rx_prio_map(pp);
-+	for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
-+		netdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc],
-+				    mqprio->qopt.offset[tc]);
-+
-+		for (rxq = mqprio->qopt.offset[tc];
-+		     rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
-+		     rxq++) {
-+			if (rxq >= rxq_number)
-+				return -EINVAL;
- 
--	netdev_set_num_tc(dev, mqprio->qopt.num_tc);
--	for (i = 0; i < mqprio->qopt.num_tc; i++)
--		netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
--				    mqprio->qopt.offset[i]);
-+			mvneta_map_vlan_prio_to_rxq(pp, tc, rxq);
-+		}
-+	}
- 
- 	return 0;
- }
diff --git a/target/linux/mvebu/patches-5.15/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch b/target/linux/mvebu/patches-5.15/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch
deleted file mode 100644
index 1d4a055a71..0000000000
--- a/target/linux/mvebu/patches-5.15/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch
+++ /dev/null
@@ -1,182 +0,0 @@
-From 2551dc9e398c37a15e52122d385c29a8b06be45f Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 26 Nov 2021 12:20:56 +0100
-Subject: net: mvneta: Add TC traffic shaping offload
-
-The mvneta controller is able to do some tocken-bucket per-queue traffic
-shaping. This commit adds support for setting these using the TC mqprio
-interface.
-
-The token-bucket parameters are customisable, but the current
-implementation configures them to have a 10kbps resolution for the
-rate limitation, since it allows to cover the whole range of max_rate
-values from 10kbps to 5Gbps with 10kbps increments.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 120 +++++++++++++++++++++++++++++++++-
- 1 file changed, 119 insertions(+), 1 deletion(-)
-
-(limited to 'drivers/net/ethernet/marvell/mvneta.c')
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -248,12 +248,39 @@
- #define      MVNETA_TXQ_SENT_DESC_MASK           0x3fff0000
- #define MVNETA_PORT_TX_RESET                     0x3cf0
- #define      MVNETA_PORT_TX_DMA_RESET            BIT(0)
-+#define MVNETA_TXQ_CMD1_REG			 0x3e00
-+#define      MVNETA_TXQ_CMD1_BW_LIM_SEL_V1	 BIT(3)
-+#define      MVNETA_TXQ_CMD1_BW_LIM_EN		 BIT(0)
-+#define MVNETA_REFILL_NUM_CLK_REG		 0x3e08
-+#define      MVNETA_REFILL_MAX_NUM_CLK		 0x0000ffff
- #define MVNETA_TX_MTU                            0x3e0c
- #define MVNETA_TX_TOKEN_SIZE                     0x3e14
- #define      MVNETA_TX_TOKEN_SIZE_MAX            0xffffffff
-+#define MVNETA_TXQ_BUCKET_REFILL_REG(q)		 (0x3e20 + ((q) << 2))
-+#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK	0x3ff00000
-+#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT	20
-+#define      MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX	 0x0007ffff
- #define MVNETA_TXQ_TOKEN_SIZE_REG(q)             (0x3e40 + ((q) << 2))
- #define      MVNETA_TXQ_TOKEN_SIZE_MAX           0x7fffffff
- 
-+/* The values of the bucket refill base period and refill period are taken from
-+ * the reference manual, and adds up to a base resolution of 10Kbps. This allows
-+ * to cover all rate-limit values from 10Kbps up to 5Gbps
-+ */
-+
-+/* Base period for the rate limit algorithm */
-+#define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS	100
-+
-+/* Number of Base Period to wait between each bucket refill */
-+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD	1000
-+
-+/* The base resolution for rate limiting, in bps. Any max_rate value should be
-+ * a multiple of that value.
-+ */
-+#define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \
-+					 (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \
-+					  MVNETA_TXQ_BUCKET_REFILL_PERIOD))
-+
- #define MVNETA_LPI_CTRL_0                        0x2cc0
- #define MVNETA_LPI_CTRL_1                        0x2cc4
- #define      MVNETA_LPI_REQUEST_ENABLE           BIT(0)
-@@ -4964,11 +4991,74 @@ static void mvneta_map_vlan_prio_to_rxq(
- 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
- }
- 
-+static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp)
-+{
-+	unsigned long core_clk_rate;
-+	u32 refill_cycles;
-+	u32 val;
-+
-+	core_clk_rate = clk_get_rate(pp->clk);
-+	if (!core_clk_rate)
-+		return -EINVAL;
-+
-+	refill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS /
-+			(NSEC_PER_SEC / core_clk_rate);
-+
-+	if (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK)
-+		return -EINVAL;
-+
-+	/* Enable bw limit algorithm version 3 */
-+	val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
-+	val &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
-+	mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
-+
-+	/* Set the base refill rate */
-+	mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);
-+
-+	return 0;
-+}
-+
-+static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp)
-+{
-+	u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
-+
-+	val |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
-+	mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
-+}
-+
-+static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue,
-+				    u64 min_rate, u64 max_rate)
-+{
-+	u32 refill_val, rem;
-+	u32 val = 0;
-+
-+	/* Convert to from Bps to bps */
-+	max_rate *= 8;
-+
-+	if (min_rate)
-+		return -EINVAL;
-+
-+	refill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION,
-+				 &rem);
-+
-+	if (rem || !refill_val ||
-+	    refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX)
-+		return -EINVAL;
-+
-+	val = refill_val;
-+	val |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD <<
-+		MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT);
-+
-+	mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);
-+
-+	return 0;
-+}
-+
- static int mvneta_setup_mqprio(struct net_device *dev,
- 			       struct tc_mqprio_qopt_offload *mqprio)
- {
- 	struct mvneta_port *pp = netdev_priv(dev);
--	int rxq, tc;
-+	int rxq, txq, tc, ret;
- 	u8 num_tc;
- 
- 	if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
-@@ -4982,6 +5072,7 @@ static int mvneta_setup_mqprio(struct ne
- 	mvneta_clear_rx_prio_map(pp);
- 
- 	if (!num_tc) {
-+		mvneta_disable_per_queue_rate_limit(pp);
- 		netdev_reset_tc(dev);
- 		return 0;
- 	}
-@@ -5002,6 +5093,33 @@ static int mvneta_setup_mqprio(struct ne
- 		}
- 	}
- 
-+	if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) {
-+		mvneta_disable_per_queue_rate_limit(pp);
-+		return 0;
-+	}
-+
-+	if (mqprio->qopt.num_tc > txq_number)
-+		return -EINVAL;
-+
-+	ret = mvneta_enable_per_queue_rate_limit(pp);
-+	if (ret)
-+		return ret;
-+
-+	for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
-+		for (txq = mqprio->qopt.offset[tc];
-+		     txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
-+		     txq++) {
-+			if (txq >= txq_number)
-+				return -EINVAL;
-+
-+			ret = mvneta_setup_queue_rates(pp, txq,
-+						       mqprio->min_rate[tc],
-+						       mqprio->max_rate[tc]);
-+			if (ret)
-+				return ret;
-+		}
-+	}
-+
- 	return 0;
- }
- 
diff --git a/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch b/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch
deleted file mode 100644
index a852dc1fc1..0000000000
--- a/target/linux/mvebu/patches-5.15/710-v6.2-phy-marvell-phy-mvebu-a3700-comphy-Reset-COMPHY-regi.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From b01d622d76134e9401970ffd3fbbb9a7051f976a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
-Date: Tue, 20 Sep 2022 14:11:54 +0200
-Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Reset COMPHY registers
- before USB 3.0 power on
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Turris MOX board with older ARM Trusted Firmware version v1.5 is not able
-to detect any USB 3.0 device connected to USB-A port on Mox-A module after
-commit 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken
-reset support"). On the other hand USB 2.0 devices connected to the same
-USB-A port are working fine.
-
-It looks as if the older firmware configures COMPHY registers for USB 3.0
-somehow incompatibly for kernel driver. Experiments show that resetting
-COMPHY registers via setting SFT_RST auto-clearing bit in COMPHY_SFT_RESET
-register fixes this issue.
-
-Reset the COMPHY in mvebu_a3700_comphy_usb3_power_on() function as a first
-step after selecting COMPHY lane and USB 3.0 function. With this change
-Turris MOX board can successfully detect USB 3.0 devices again.
-
-Before the above mentioned commit this reset was implemented in PHY reset
-method, so this is the reason why there was no issue with older firmware
-version then.
-
-Fixes: 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset support")
-Reported-by: Marek Behún <kabel@kernel.org>
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Tested-by: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
-Link: https://lore.kernel.org/r/20220920121154.30115-1-pali@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
-+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
-@@ -826,6 +826,9 @@ mvebu_a3700_comphy_usb3_power_on(struct
- 	if (ret)
- 		return ret;
- 
-+	/* COMPHY register reset (cleared automatically) */
-+	comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
-+
- 	/*
- 	 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
- 	 * register belong to UTMI module, so it is set in UTMI phy driver.
diff --git a/target/linux/mvebu/patches-5.15/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-5.15/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
deleted file mode 100644
index 29f36be460..0000000000
--- a/target/linux/mvebu/patches-5.15/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@arm.linux.org.uk>
-Date: Sat, 3 Oct 2015 09:13:05 +0100
-Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
-
-The cpuidle ->enter method expects the return value to be the sleep
-state we entered.  Returning negative numbers or other codes is not
-permissible since coupled CPU idle was merged.
-
-At least some of the mvebu_v7_cpu_suspend() implementations return the
-value from cpu_suspend(), which returns zero if the CPU vectors back
-into the kernel via cpu_resume() (the success case), or the non-zero
-return value of the suspend actor, or one (failure cases).
-
-We do not want to be returning the failure case value back to CPU idle
-as that indicates that we successfully entered one of the deeper idle
-states.  Always return zero instead, indicating that we slept for the
-shortest amount of time.
-
-Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
----
- drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/cpuidle/cpuidle-mvebu-v7.c
-+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
-@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
- 	ret = mvebu_v7_cpu_suspend(deepidle);
- 	cpu_pm_exit();
- 
-+	/*
-+	 * If we failed to enter the desired state, indicate that we
-+	 * slept lightly.
-+	 */
- 	if (ret)
--		return ret;
-+		return 0;
- 
- 	return index;
- }
diff --git a/target/linux/mvebu/patches-5.15/801-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-5.15/801-pci-mvebu-time-out-reset-on-link-up.patch
deleted file mode 100644
index dba1253699..0000000000
--- a/target/linux/mvebu/patches-5.15/801-pci-mvebu-time-out-reset-on-link-up.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Sat, 9 Jul 2016 10:58:16 +0100
-Subject: pci: mvebu: time out reset on link up
-
-If the port reports that the link is up while we are resetting, there's
-little point in waiting for the full duration.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
- 1 file changed, 14 insertions(+), 6 deletions(-)
-
---- a/drivers/pci/controller/pci-mvebu.c
-+++ b/drivers/pci/controller/pci-mvebu.c
-@@ -1023,6 +1023,7 @@ static int mvebu_pcie_powerup(struct mve
- 
- 	if (port->reset_gpio) {
- 		u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
-+		unsigned int i;
- 
- 		of_property_read_u32(port->dn, "reset-delay-us",
- 				     &reset_udelay);
-@@ -1030,7 +1031,13 @@ static int mvebu_pcie_powerup(struct mve
- 		udelay(100);
- 
- 		gpiod_set_value_cansleep(port->reset_gpio, 0);
--		msleep(reset_udelay / 1000);
-+		for (i = 0; i < reset_udelay; i += 1000) {
-+			if (mvebu_pcie_link_up(port))
-+				break;
-+			msleep(1);
-+		}
-+
-+		printk("%s: reset completed in %dus\n", port->name, i);
- 	}
- 
- 	return 0;
-@@ -1190,15 +1197,16 @@ static int mvebu_pcie_probe(struct platf
- 		if (!child)
- 			continue;
- 
--		ret = mvebu_pcie_powerup(port);
--		if (ret < 0)
--			continue;
--
- 		port->base = mvebu_pcie_map_registers(pdev, child, port);
- 		if (IS_ERR(port->base)) {
- 			dev_err(dev, "%s: cannot map registers\n", port->name);
- 			port->base = NULL;
--			mvebu_pcie_powerdown(port);
-+			continue;
-+		}
-+
-+		ret = mvebu_pcie_powerup(port);
-+		if (ret < 0) {
-+			port->base = NULL;
- 			continue;
- 		}
- 
diff --git a/target/linux/mvebu/patches-5.15/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch b/target/linux/mvebu/patches-5.15/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
deleted file mode 100644
index 3446086cad..0000000000
--- a/target/linux/mvebu/patches-5.15/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
+++ /dev/null
@@ -1,218 +0,0 @@
-From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:32 +0000
-Subject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803
- PUZZLE driver bindings
-
-Add the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED
-drivers. A new vendor prefix is also added accordingly for
-IEI Integration Corp.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei,wt61p803-puzzle-hwmon.yaml      | 53 ++++++++++++
- .../leds/iei,wt61p803-puzzle-leds.yaml        | 39 +++++++++
- .../bindings/mfd/iei,wt61p803-puzzle.yaml     | 82 +++++++++++++++++++
- .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
- 4 files changed, 176 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
- create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
- create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-@@ -0,0 +1,53 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+  The HWMON module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle-hwmon
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 0
-+
-+patternProperties:
-+  "^fan-group@[0-1]$":
-+    type: object
-+    properties:
-+      reg:
-+        minimum: 0
-+        maximum: 1
-+        description:
-+          Fan group ID
-+
-+      cooling-levels:
-+        minItems: 1
-+        maxItems: 255
-+        description:
-+          Cooling levels for the fans (PWM value mapping)
-+    description: |
-+      Properties for each fan group.
-+    required:
-+      - reg
-+
-+required:
-+  - compatible
-+  - "#address-cells"
-+  - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-@@ -0,0 +1,39 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+  The LED module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle-leds
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 0
-+
-+  led@0:
-+    type: object
-+    $ref: common.yaml
-+    description: |
-+      Properties for a single LED.
-+
-+required:
-+  - compatible
-+  - "#address-cells"
-+  - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-@@ -0,0 +1,82 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards.
-+  It's used for controlling system power states, fans, LEDs and temperature
-+  sensors.
-+
-+  For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the
-+  binding documents under the respective subsystem directories.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle
-+
-+  current-speed:
-+    description:
-+      Serial bus speed in bps
-+    maxItems: 1
-+
-+  enable-beep: true
-+
-+  hwmon:
-+    $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+
-+  leds:
-+    $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml
-+
-+required:
-+  - compatible
-+  - current-speed
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/leds/common.h>
-+    serial {
-+        mcu {
-+            compatible = "iei,wt61p803-puzzle";
-+            current-speed = <115200>;
-+            enable-beep;
-+
-+            leds {
-+                compatible = "iei,wt61p803-puzzle-leds";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                led@0 {
-+                    reg = <0>;
-+                    function = LED_FUNCTION_POWER;
-+                    color = <LED_COLOR_ID_BLUE>;
-+                };
-+            };
-+
-+            hwmon {
-+                compatible = "iei,wt61p803-puzzle-hwmon";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                fan-group@0 {
-+                    #cooling-cells = <2>;
-+                    reg = <0x00>;
-+                    cooling-levels = <64 102 170 230 250>;
-+                };
-+
-+                fan-group@1 {
-+                    #cooling-cells = <2>;
-+                    reg = <0x01>;
-+                    cooling-levels = <64 102 170 230 250>;
-+                };
-+            };
-+        };
-+    };
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -519,6 +519,8 @@ patternProperties:
-     description: IC Plus Corp.
-   "^idt,.*":
-     description: Integrated Device Technologies, Inc.
-+  "^iei,.*":
-+    description: IEI Integration Corp.
-   "^ifi,.*":
-     description: Ingenieurburo Fur Ic-Technologie (I/F/I)
-   "^ilitek,.*":
diff --git a/target/linux/mvebu/patches-5.15/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch b/target/linux/mvebu/patches-5.15/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
deleted file mode 100644
index 0e546b426e..0000000000
--- a/target/linux/mvebu/patches-5.15/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
+++ /dev/null
@@ -1,1034 +0,0 @@
-From 692cfa85272dd12995b427c0a7a585ced5d54f32 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:33 +0000
-Subject: [PATCH 2/7] drivers: mfd: Add a driver for IEI WT61P803 PUZZLE MCU
-
-Add a driver for the IEI WT61P803 PUZZLE microcontroller, used in some
-IEI Puzzle series devices. The microcontroller controls system power,
-temperature sensors, fans and LEDs.
-
-This driver implements the core functionality for device communication
-over the system serial (serdev bus). It handles MCU messages and the
-internal MCU properties. Some properties can be managed over sysfs.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mfd/Kconfig                     |   8 +
- drivers/mfd/Makefile                    |   1 +
- drivers/mfd/iei-wt61p803-puzzle.c       | 908 ++++++++++++++++++++++++
- include/linux/mfd/iei-wt61p803-puzzle.h |  66 ++
- 4 files changed, 983 insertions(+)
- create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c
- create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h
-
---- a/drivers/mfd/Kconfig
-+++ b/drivers/mfd/Kconfig
-@@ -2189,6 +2189,15 @@ config SGI_MFD_IOC3
- 	  If you have an SGI Origin, Octane, or a PCI IOC3 card,
- 	  then say Y. Otherwise say N.
- 
-+config MFD_IEI_WT61P803_PUZZLE
-+	tristate "IEI WT61P803 PUZZLE MCU driver"
-+	depends on SERIAL_DEV_BUS
-+	select MFD_CORE
-+	help
-+	  IEI WT61P803 PUZZLE is a system power management microcontroller
-+	  used for fan control, temperature sensor reading, LED control
-+	  and system identification.
-+
- config MFD_INTEL_M10_BMC
- 	tristate "Intel MAX 10 Board Management Controller"
- 	depends on SPI_MASTER
---- a/drivers/mfd/Makefile
-+++ b/drivers/mfd/Makefile
-@@ -237,6 +237,7 @@ obj-$(CONFIG_MFD_DLN2)		+= dln2.o
- obj-$(CONFIG_MFD_RT4831)	+= rt4831.o
- obj-$(CONFIG_MFD_RT5033)	+= rt5033.o
- obj-$(CONFIG_MFD_SKY81452)	+= sky81452.o
-+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE)	+= iei-wt61p803-puzzle.o
- 
- intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
- obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
---- /dev/null
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -0,0 +1,908 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/atomic.h>
-+#include <linux/delay.h>
-+#include <linux/export.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/core.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/property.h>
-+#include <linux/sched.h>
-+#include <linux/serdev.h>
-+#include <linux/slab.h>
-+#include <linux/sysfs.h>
-+#include <asm/unaligned.h>
-+
-+/* start, payload and XOR checksum at end */
-+#define IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH	(1 + 20 + 1)
-+#define IEI_WT61P803_PUZZLE_RESP_BUF_SIZE	512
-+
-+#define IEI_WT61P803_PUZZLE_MAC_LENGTH			17
-+#define IEI_WT61P803_PUZZLE_SN_LENGTH			36
-+#define IEI_WT61P803_PUZZLE_VERSION_LENGTH		 6
-+#define IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH		16
-+#define IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH	 8
-+#define IEI_WT61P803_PUZZLE_NB_MAC			 8
-+
-+/* Use HZ as a timeout value throughout the driver */
-+#define IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT HZ
-+
-+enum iei_wt61p803_puzzle_attribute_type {
-+	IEI_WT61P803_PUZZLE_VERSION,
-+	IEI_WT61P803_PUZZLE_BUILD_INFO,
-+	IEI_WT61P803_PUZZLE_BOOTLOADER_MODE,
-+	IEI_WT61P803_PUZZLE_PROTOCOL_VERSION,
-+	IEI_WT61P803_PUZZLE_SERIAL_NUMBER,
-+	IEI_WT61P803_PUZZLE_MAC_ADDRESS,
-+	IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS,
-+	IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY,
-+	IEI_WT61P803_PUZZLE_POWER_STATUS,
-+};
-+
-+struct iei_wt61p803_puzzle_device_attribute {
-+	struct device_attribute dev_attr;
-+	enum iei_wt61p803_puzzle_attribute_type type;
-+	u8 index;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_status - MCU flags state
-+ * @ac_recovery_status_flag:	AC Recovery Status Flag
-+ * @power_loss_recovery:	System recovery after power loss
-+ * @power_status:		System Power-on Method
-+ */
-+struct iei_wt61p803_puzzle_mcu_status {
-+	u8 ac_recovery_status_flag;
-+	u8 power_loss_recovery;
-+	u8 power_status;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_reply - MCU reply
-+ * @size:	Size of the MCU reply
-+ * @data:	Full MCU reply buffer
-+ * @state:	Current state of the packet
-+ * @received:	Was the response fullfilled
-+ */
-+struct iei_wt61p803_puzzle_reply {
-+	size_t size;
-+	unsigned char data[IEI_WT61P803_PUZZLE_RESP_BUF_SIZE];
-+	struct completion received;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_version - MCU version status
-+ * @version:		Primary firmware version
-+ * @build_info:		Build date and time
-+ * @bootloader_mode:	Status of the MCU operation
-+ * @protocol_version:	MCU communication protocol version
-+ * @serial_number:	Device factory serial number
-+ * @mac_address:	Device factory MAC addresses
-+ *
-+ * Last element of arrays is reserved for '\0'.
-+ */
-+struct iei_wt61p803_puzzle_mcu_version {
-+	char version[IEI_WT61P803_PUZZLE_VERSION_LENGTH + 1];
-+	char build_info[IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH + 1];
-+	bool bootloader_mode;
-+	char protocol_version[IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH + 1];
-+	char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH + 1];
-+	char mac_address[IEI_WT61P803_PUZZLE_NB_MAC][IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle - IEI WT61P803 PUZZLE MCU Driver
-+ * @serdev:		Pointer to underlying serdev device
-+ * @dev:		Pointer to underlying dev device
-+ * @reply_lock:		Reply mutex lock
-+ * @reply:		Pointer to the iei_wt61p803_puzzle_reply struct
-+ * @version:		MCU version related data
-+ * @status:		MCU status related data
-+ * @response_buffer	Command response buffer allocation
-+ * @lock		General member mutex lock
-+ */
-+struct iei_wt61p803_puzzle {
-+	struct serdev_device *serdev;
-+	struct device *dev;
-+	struct mutex reply_lock; /* lock to prevent multiple firmware calls */
-+	struct iei_wt61p803_puzzle_reply *reply;
-+	struct iei_wt61p803_puzzle_mcu_version version;
-+	struct iei_wt61p803_puzzle_mcu_status status;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	struct mutex lock; /* lock to protect response buffer */
-+};
-+
-+static unsigned char iei_wt61p803_puzzle_checksum(unsigned char *buf, size_t len)
-+{
-+	unsigned char checksum = 0;
-+	size_t i;
-+
-+	for (i = 0; i < len; i++)
-+		checksum ^= buf[i];
-+	return checksum;
-+}
-+
-+static int iei_wt61p803_puzzle_process_resp(struct iei_wt61p803_puzzle *mcu,
-+					    const unsigned char *raw_resp_data, size_t size)
-+{
-+	unsigned char checksum;
-+
-+	/* Check the incoming frame header */
-+	if (!(raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START ||
-+	      raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER ||
-+	     (raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM &&
-+	      raw_resp_data[1] == IEI_WT61P803_PUZZLE_CMD_EEPROM_READ))) {
-+		if (mcu->reply->size + size >= sizeof(mcu->reply->data))
-+			return -EIO;
-+
-+		/* Append the frame to existing data */
-+		memcpy(mcu->reply->data + mcu->reply->size, raw_resp_data, size);
-+		mcu->reply->size += size;
-+	} else {
-+		if (size >= sizeof(mcu->reply->data))
-+			return -EIO;
-+
-+		/* Start processing a new frame */
-+		memcpy(mcu->reply->data, raw_resp_data, size);
-+		mcu->reply->size = size;
-+	}
-+
-+	checksum = iei_wt61p803_puzzle_checksum(mcu->reply->data, mcu->reply->size - 1);
-+	if (checksum != mcu->reply->data[mcu->reply->size - 1]) {
-+		/* The checksum isn't matched yet, wait for new frames */
-+		return size;
-+	}
-+
-+	/* Received all the data */
-+	complete(&mcu->reply->received);
-+
-+	return size;
-+}
-+
-+static int iei_wt61p803_puzzle_recv_buf(struct serdev_device *serdev,
-+					const unsigned char *data, size_t size)
-+{
-+	struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
-+	int ret;
-+
-+	ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
-+	/* Return the number of processed bytes if function returns error,
-+	 * discard the remaining incoming data, since the frame this data
-+	 * belongs to is broken anyway
-+	 */
-+	if (ret < 0)
-+		return size;
-+
-+	return ret;
-+}
-+
-+static const struct serdev_device_ops iei_wt61p803_puzzle_serdev_device_ops = {
-+	.receive_buf  = iei_wt61p803_puzzle_recv_buf,
-+	.write_wakeup = serdev_device_write_wakeup,
-+};
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command_watchdog() - Watchdog of the normal cmd
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ * @reply_size: Pointer to size_t (size of reply_data)
-+ * @retry_count: Number of times to retry sending the command to the MCU
-+ */
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+					       unsigned char *cmd, size_t size,
-+					       unsigned char *reply_data,
-+					       size_t *reply_size, int retry_count)
-+{
-+	struct device *dev = &mcu->serdev->dev;
-+	int ret, i;
-+
-+	for (i = 0; i < retry_count; i++) {
-+		ret = iei_wt61p803_puzzle_write_command(mcu, cmd, size,
-+							reply_data, reply_size);
-+		if (ret != -ETIMEDOUT)
-+			return ret;
-+	}
-+
-+	dev_err(dev, "Command response timed out. Retries: %d\n", retry_count);
-+
-+	return -ETIMEDOUT;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command_watchdog);
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command() - Send a structured command to the MCU
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ *
-+ * Sends a structured command to the MCU.
-+ */
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char *cmd, size_t size,
-+				      unsigned char *reply_data,
-+				      size_t *reply_size)
-+{
-+	struct device *dev = &mcu->serdev->dev;
-+	int ret;
-+
-+	if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
-+		return -EINVAL;
-+
-+	mutex_lock(&mcu->reply_lock);
-+
-+	cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
-+
-+	/* Initialize reply struct */
-+	reinit_completion(&mcu->reply->received);
-+	mcu->reply->size = 0;
-+	usleep_range(2000, 10000);
-+	serdev_device_write_flush(mcu->serdev);
-+	ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+	if (ret < 0)
-+		goto exit;
-+
-+	serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+	ret = wait_for_completion_timeout(&mcu->reply->received,
-+					  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+	if (ret == 0) {
-+		dev_err(dev, "Command reply receive timeout\n");
-+		ret = -ETIMEDOUT;
-+		goto exit;
-+	}
-+
-+	*reply_size = mcu->reply->size;
-+	/* Copy the received data, as it will not be available after a new frame is received */
-+	memcpy(reply_data, mcu->reply->data, mcu->reply->size);
-+	ret = 0;
-+exit:
-+	mutex_unlock(&mcu->reply_lock);
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command);
-+
-+static int iei_wt61p803_puzzle_buzzer(struct iei_wt61p803_puzzle *mcu, bool long_beep)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char buzzer_cmd[4] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	buzzer_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	buzzer_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE;
-+	buzzer_cmd[2] = long_beep ? '3' : '2'; /* Buzzer 1.5 / 0.5 second beep */
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, buzzer_cmd, sizeof(buzzer_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EPROTO;
-+		goto exit;
-+	}
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_version(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char version_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION,
-+	};
-+	unsigned char build_info_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD,
-+	};
-+	unsigned char bootloader_mode_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE,
-+	};
-+	unsigned char protocol_version_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION,
-+	};
-+	unsigned char *rb = mcu->response_buffer;
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, version_cmd, sizeof(version_cmd),
-+						rb, &reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 7) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.version, "v%c.%.3s", rb[2], &rb[3]);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, build_info_cmd,
-+						sizeof(build_info_cmd),	rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 15) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.build_info, "%c%c/%c%c/%.4s %c%c:%c%c",
-+		rb[8], rb[9], rb[6], rb[7], &rb[2], rb[10], rb[11],
-+		rb[12], rb[13]);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, bootloader_mode_cmd,
-+						sizeof(bootloader_mode_cmd), rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 4) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS)
-+		mcu->version.bootloader_mode = false;
-+	else if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER)
-+		mcu->version.bootloader_mode = true;
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, protocol_version_cmd,
-+						sizeof(protocol_version_cmd), rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 9) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.protocol_version, "v%c.%c%c%c%c%c",
-+		rb[7], rb[6], rb[5], rb[4], rb[3], rb[2]);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mcu_status(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char mcu_status_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+	};
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mcu_status_cmd, sizeof(mcu_status_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+	if (reply_size < 20) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	/* Response format:
-+	 * (IDX	RESPONSE)
-+	 * 0	@
-+	 * 1	O
-+	 * 2	S
-+	 * 3	S
-+	 * ...
-+	 * 5	AC Recovery Status Flag
-+	 * ...
-+	 * 10	Power Loss Recovery
-+	 * ...
-+	 * 19	Power Status (system power on method)
-+	 * 20	XOR checksum
-+	 */
-+	if (resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	    resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER &&
-+	    resp_buf[2] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS &&
-+	    resp_buf[3] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS) {
-+		mcu->status.ac_recovery_status_flag = resp_buf[5];
-+		mcu->status.power_loss_recovery = resp_buf[10];
-+		mcu->status.power_status = resp_buf[19];
-+	}
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_serial_number(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char serial_number_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+		0x00,	/* EEPROM read address */
-+		0x24,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+						sizeof(serial_number_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+
-+	if (reply_size < IEI_WT61P803_PUZZLE_SN_LENGTH + 4) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.serial_number, "%.*s",
-+		IEI_WT61P803_PUZZLE_SN_LENGTH, resp_buf + 4);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_serial_number(struct iei_wt61p803_puzzle *mcu,
-+						   unsigned char serial_number[36])
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char serial_number_header[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+		0x00,	/* EEPROM write address */
-+		0xC,	/* Data length */
-+	};
-+	unsigned char serial_number_cmd[4 + 12 + 1]; /* header, serial number, XOR checksum */
-+	int ret, sn_counter;
-+	size_t reply_size;
-+
-+	/* The MCU can only handle 22 byte messages, send the S/N in 12 byte chunks */
-+	mutex_lock(&mcu->lock);
-+	for (sn_counter = 0; sn_counter < 3; sn_counter++) {
-+		serial_number_header[2] = 0x0 + 0xC * sn_counter;
-+
-+		memcpy(serial_number_cmd, serial_number_header, sizeof(serial_number_header));
-+		memcpy(serial_number_cmd + sizeof(serial_number_header),
-+		       serial_number + 0xC * sn_counter, 0xC);
-+
-+		ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+							sizeof(serial_number_cmd),
-+							resp_buf, &reply_size);
-+		if (ret)
-+			goto err;
-+		if (reply_size != 3) {
-+			ret = -EIO;
-+			goto err;
-+		}
-+		if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+		      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+		      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+			ret = -EPROTO;
-+			goto err;
-+		}
-+	}
-+
-+	sprintf(mcu->version.serial_number, "%.*s",
-+		IEI_WT61P803_PUZZLE_SN_LENGTH, serial_number);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mac_address(struct iei_wt61p803_puzzle *mcu, int index)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char mac_address_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+		0x00,	/* EEPROM read address */
-+		0x11,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	mac_address_cmd[2] = 0x24 + 0x11 * index;
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+						sizeof(mac_address_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+
-+	if (reply_size < 22) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.mac_address[index], "%.*s",
-+		IEI_WT61P803_PUZZLE_MAC_LENGTH, resp_buf + 4);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int
-+iei_wt61p803_puzzle_write_mac_address(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH],
-+				      int mac_address_idx)
-+{
-+	unsigned char mac_address_cmd[4 + IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char mac_address_header[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+		0x00,	/* EEPROM write address */
-+		0x11,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	if (mac_address_idx < 0 || mac_address_idx >= IEI_WT61P803_PUZZLE_NB_MAC)
-+		return -EINVAL;
-+
-+	mac_address_header[2] = 0x24 + 0x11 * mac_address_idx;
-+
-+	/* Concat mac_address_header, mac_address to mac_address_cmd */
-+	memcpy(mac_address_cmd, mac_address_header, sizeof(mac_address_header));
-+	memcpy(mac_address_cmd + sizeof(mac_address_header), mac_address,
-+	       IEI_WT61P803_PUZZLE_MAC_LENGTH);
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+						sizeof(mac_address_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EPROTO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.mac_address[mac_address_idx], "%.*s",
-+		IEI_WT61P803_PUZZLE_MAC_LENGTH, mac_address);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_power_loss_recovery(struct iei_wt61p803_puzzle *mcu,
-+							 int power_loss_recovery_action)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char power_loss_recovery_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	if (power_loss_recovery_action < 0 || power_loss_recovery_action > 4)
-+		return -EINVAL;
-+
-+	power_loss_recovery_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	power_loss_recovery_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER;
-+	power_loss_recovery_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS;
-+	power_loss_recovery_cmd[3] = hex_asc[power_loss_recovery_action];
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, power_loss_recovery_cmd,
-+						sizeof(power_loss_recovery_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+	mcu->status.power_loss_recovery = power_loss_recovery_action;
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+#define to_puzzle_dev_attr(_attr) \
-+	container_of(_attr, struct iei_wt61p803_puzzle_device_attribute, dev_attr)
-+
-+static ssize_t show_output(struct device *dev,
-+			   struct device_attribute *attr, char *buf)
-+{
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+	struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+	int ret;
-+
-+	switch (pattr->type) {
-+	case IEI_WT61P803_PUZZLE_VERSION:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.version);
-+	case IEI_WT61P803_PUZZLE_BUILD_INFO:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.build_info);
-+	case IEI_WT61P803_PUZZLE_BOOTLOADER_MODE:
-+		return scnprintf(buf, PAGE_SIZE, "%d\n", mcu->version.bootloader_mode);
-+	case IEI_WT61P803_PUZZLE_PROTOCOL_VERSION:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.protocol_version);
-+	case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+		ret = iei_wt61p803_puzzle_get_serial_number(mcu);
-+		if (!ret)
-+			ret = scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.serial_number);
-+		else
-+			ret = 0;
-+		return ret;
-+	case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+		ret = iei_wt61p803_puzzle_get_mac_address(mcu, pattr->index);
-+		if (!ret)
-+			ret = scnprintf(buf, PAGE_SIZE, "%s\n",
-+					mcu->version.mac_address[pattr->index]);
-+		else
-+			ret = 0;
-+		return ret;
-+	case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+	case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+	case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+		ret = iei_wt61p803_puzzle_get_mcu_status(mcu);
-+		if (ret)
-+			return ret;
-+
-+		mutex_lock(&mcu->lock);
-+		switch (pattr->type) {
-+		case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n",
-+					mcu->status.ac_recovery_status_flag);
-+			break;
-+		case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_loss_recovery);
-+			break;
-+		case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_status);
-+			break;
-+		default:
-+			ret = 0;
-+			break;
-+		}
-+		mutex_unlock(&mcu->lock);
-+		return ret;
-+	default:
-+		return 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t store_output(struct device *dev,
-+			    struct device_attribute *attr,
-+			    const char *buf, size_t len)
-+{
-+	unsigned char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH];
-+	unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH];
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+	struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+	int power_loss_recovery_action = 0;
-+	int ret;
-+
-+	switch (pattr->type) {
-+	case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+		if (len != (size_t)(IEI_WT61P803_PUZZLE_SN_LENGTH + 1))
-+			return -EINVAL;
-+		memcpy(serial_number, buf, sizeof(serial_number));
-+		ret = iei_wt61p803_puzzle_write_serial_number(mcu, serial_number);
-+		if (ret)
-+			return ret;
-+		return len;
-+	case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+		if (len != (size_t)(IEI_WT61P803_PUZZLE_MAC_LENGTH + 1))
-+			return -EINVAL;
-+
-+		memcpy(mac_address, buf, sizeof(mac_address));
-+
-+		if (strlen(attr->attr.name) != 13)
-+			return -EIO;
-+
-+		ret = iei_wt61p803_puzzle_write_mac_address(mcu, mac_address, pattr->index);
-+		if (ret)
-+			return ret;
-+		return len;
-+	case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+		ret = kstrtoint(buf, 10, &power_loss_recovery_action);
-+		if (ret)
-+			return ret;
-+		ret = iei_wt61p803_puzzle_write_power_loss_recovery(mcu,
-+								    power_loss_recovery_action);
-+		if (ret)
-+			return ret;
-+		return len;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+#define IEI_WT61P803_PUZZLE_ATTR(_name, _mode, _show, _store, _type, _index) \
-+	struct iei_wt61p803_puzzle_device_attribute dev_attr_##_name = \
-+		{ .dev_attr	= __ATTR(_name, _mode, _show, _store), \
-+		  .type		= _type, \
-+		  .index	= _index }
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RO(_name, _type, _id) \
-+	IEI_WT61P803_PUZZLE_ATTR(_name, 0444, show_output, NULL, _type, _id)
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RW(_name, _type, _id) \
-+	IEI_WT61P803_PUZZLE_ATTR(_name, 0644, show_output, store_output, _type, _id)
-+
-+static IEI_WT61P803_PUZZLE_ATTR_RO(version, IEI_WT61P803_PUZZLE_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(build_info, IEI_WT61P803_PUZZLE_BUILD_INFO, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(bootloader_mode, IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(protocol_version, IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(serial_number, IEI_WT61P803_PUZZLE_SERIAL_NUMBER, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_0, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_1, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 1);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_2, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 2);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_3, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 3);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_4, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 4);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_5, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 5);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_6, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 6);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_7, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 7);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(ac_recovery_status, IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0);
-+
-+static struct attribute *iei_wt61p803_puzzle_attrs[] = {
-+	&dev_attr_version.dev_attr.attr,
-+	&dev_attr_build_info.dev_attr.attr,
-+	&dev_attr_bootloader_mode.dev_attr.attr,
-+	&dev_attr_protocol_version.dev_attr.attr,
-+	&dev_attr_serial_number.dev_attr.attr,
-+	&dev_attr_mac_address_0.dev_attr.attr,
-+	&dev_attr_mac_address_1.dev_attr.attr,
-+	&dev_attr_mac_address_2.dev_attr.attr,
-+	&dev_attr_mac_address_3.dev_attr.attr,
-+	&dev_attr_mac_address_4.dev_attr.attr,
-+	&dev_attr_mac_address_5.dev_attr.attr,
-+	&dev_attr_mac_address_6.dev_attr.attr,
-+	&dev_attr_mac_address_7.dev_attr.attr,
-+	&dev_attr_ac_recovery_status.dev_attr.attr,
-+	&dev_attr_power_loss_recovery.dev_attr.attr,
-+	&dev_attr_power_status.dev_attr.attr,
-+	NULL
-+};
-+ATTRIBUTE_GROUPS(iei_wt61p803_puzzle);
-+
-+static int iei_wt61p803_puzzle_sysfs_create(struct device *dev,
-+					    struct iei_wt61p803_puzzle *mcu)
-+{
-+	int ret;
-+
-+	ret = sysfs_create_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+	if (ret)
-+		mfd_remove_devices(mcu->dev);
-+
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_sysfs_remove(struct device *dev,
-+					    struct iei_wt61p803_puzzle *mcu)
-+{
-+	/* Remove sysfs groups */
-+	sysfs_remove_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+	mfd_remove_devices(mcu->dev);
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_probe(struct serdev_device *serdev)
-+{
-+	struct device *dev = &serdev->dev;
-+	struct iei_wt61p803_puzzle *mcu;
-+	u32 baud;
-+	int ret;
-+
-+	/* Read the baud rate from 'current-speed', because the MCU supports different rates */
-+	if (device_property_read_u32(dev, "current-speed", &baud)) {
-+		dev_err(dev,
-+			"'current-speed' is not specified in device node\n");
-+		return -EINVAL;
-+	}
-+	dev_dbg(dev, "Driver baud rate: %d\n", baud);
-+
-+	/* Allocate the memory */
-+	mcu = devm_kzalloc(dev, sizeof(*mcu), GFP_KERNEL);
-+	if (!mcu)
-+		return -ENOMEM;
-+
-+	mcu->reply = devm_kzalloc(dev, sizeof(*mcu->reply), GFP_KERNEL);
-+	if (!mcu->reply)
-+		return -ENOMEM;
-+
-+	/* Initialize device struct data */
-+	mcu->serdev = serdev;
-+	mcu->dev = dev;
-+	init_completion(&mcu->reply->received);
-+	mutex_init(&mcu->reply_lock);
-+	mutex_init(&mcu->lock);
-+
-+	/* Setup UART interface */
-+	serdev_device_set_drvdata(serdev, mcu);
-+	serdev_device_set_client_ops(serdev, &iei_wt61p803_puzzle_serdev_device_ops);
-+	ret = devm_serdev_device_open(dev, serdev);
-+	if (ret)
-+		return ret;
-+	serdev_device_set_baudrate(serdev, baud);
-+	serdev_device_set_flow_control(serdev, false);
-+	ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);
-+	if (ret) {
-+		dev_err(dev, "Failed to set parity\n");
-+		return ret;
-+	}
-+
-+	ret = iei_wt61p803_puzzle_get_version(mcu);
-+	if (ret)
-+		return ret;
-+
-+	dev_dbg(dev, "MCU version: %s\n", mcu->version.version);
-+	dev_dbg(dev, "MCU firmware build info: %s\n", mcu->version.build_info);
-+	dev_dbg(dev, "MCU in bootloader mode: %s\n",
-+		mcu->version.bootloader_mode ? "true" : "false");
-+	dev_dbg(dev, "MCU protocol version: %s\n", mcu->version.protocol_version);
-+
-+	if (device_property_read_bool(dev, "enable-beep")) {
-+		ret = iei_wt61p803_puzzle_buzzer(mcu, false);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	ret = iei_wt61p803_puzzle_sysfs_create(dev, mcu);
-+	if (ret)
-+		return ret;
-+
-+	return devm_of_platform_populate(dev);
-+}
-+
-+static void iei_wt61p803_puzzle_remove(struct serdev_device *serdev)
-+{
-+	struct device *dev = &serdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+
-+	iei_wt61p803_puzzle_sysfs_remove(dev, mcu);
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_dt_ids[] = {
-+	{ .compatible = "iei,wt61p803-puzzle" },
-+	{ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_dt_ids);
-+
-+static struct serdev_device_driver iei_wt61p803_puzzle_drv = {
-+	.probe			= iei_wt61p803_puzzle_probe,
-+	.remove			= iei_wt61p803_puzzle_remove,
-+	.driver = {
-+		.name		= "iei-wt61p803-puzzle",
-+		.of_match_table	= iei_wt61p803_puzzle_dt_ids,
-+	},
-+};
-+
-+module_serdev_device_driver(iei_wt61p803_puzzle_drv);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU Driver");
---- /dev/null
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -0,0 +1,66 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#ifndef _MFD_IEI_WT61P803_PUZZLE_H_
-+#define _MFD_IEI_WT61P803_PUZZLE_H_
-+
-+#define IEI_WT61P803_PUZZLE_BUF_SIZE 512
-+
-+/* Command magic numbers */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START		0x40 /* @ */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER	0x25 /* % */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM		0xF7
-+
-+#define IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK		0x30 /* 0 */
-+#define IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK	0x70
-+
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_READ		0xA1
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE		0xA0
-+
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION		0x56 /* V */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD		0x42 /* B */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE	0x4D /* M */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER	0x30
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS		0x31
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION	0x50 /* P */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE		0x43 /* C */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER		0x4F /* O */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS	0x53 /* S */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_LED			0x52 /* R */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_POWER		0x31 /* 1 */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP			0x54 /* T */
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL		0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN			0x46 /* F */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ		0x5A /* Z */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE		0x57 /* W */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE		0x30
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE		0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE + (x)) /* 0 - 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE + (x)) /* 0 - 5 */
-+
-+struct iei_wt61p803_puzzle_mcu_version;
-+struct iei_wt61p803_puzzle_reply;
-+struct iei_wt61p803_puzzle;
-+
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+					       unsigned char *cmd, size_t size,
-+					       unsigned char *reply_data, size_t *reply_size,
-+					       int retry_count);
-+
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char *cmd, size_t size,
-+				      unsigned char *reply_data, size_t *reply_size);
-+
-+#endif /* _MFD_IEI_WT61P803_PUZZLE_H_ */
diff --git a/target/linux/mvebu/patches-5.15/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch b/target/linux/mvebu/patches-5.15/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
deleted file mode 100644
index 023495373b..0000000000
--- a/target/linux/mvebu/patches-5.15/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
+++ /dev/null
@@ -1,501 +0,0 @@
-From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:34 +0000
-Subject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver
-
-Add the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed
-control via PWM, reading fan speed and reading on-board temperature
-sensors.
-
-The driver registers a HWMON device and a simple thermal cooling device to
-enable in-kernel fan management.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Acked-by: Guenter Roeck <linux@roeck-us.net>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/hwmon/Kconfig                     |   8 +
- drivers/hwmon/Makefile                    |   1 +
- drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 413 ++++++++++++++++++++++
- 3 files changed, 422 insertions(+)
- create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-
---- a/drivers/hwmon/Kconfig
-+++ b/drivers/hwmon/Kconfig
-@@ -732,6 +732,14 @@ config SENSORS_IBMPOWERNV
- 	  This driver can also be built as a module. If so, the module
- 	  will be called ibmpowernv.
- 
-+config SENSORS_IEI_WT61P803_PUZZLE_HWMON
-+	tristate "IEI WT61P803 PUZZLE MFD HWMON Driver"
-+	depends on MFD_IEI_WT61P803_PUZZLE
-+	help
-+	  The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed
-+	  and writing fan PWM values. It also supports reading on-board
-+	  temperature sensors.
-+
- config SENSORS_IIO_HWMON
- 	tristate "Hwmon driver that uses channels specified via iio maps"
- 	depends on IIO
---- a/drivers/hwmon/Makefile
-+++ b/drivers/hwmon/Makefile
-@@ -84,6 +84,7 @@ obj-$(CONFIG_SENSORS_HIH6130)	+= hih6130
- obj-$(CONFIG_SENSORS_ULTRA45)	+= ultra45_env.o
- obj-$(CONFIG_SENSORS_I5500)	+= i5500_temp.o
- obj-$(CONFIG_SENSORS_I5K_AMB)	+= i5k_amb.o
-+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o
- obj-$(CONFIG_SENSORS_IBMAEM)	+= ibmaem.o
- obj-$(CONFIG_SENSORS_IBMPEX)	+= ibmpex.o
- obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o
---- /dev/null
-+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-@@ -0,0 +1,445 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU HWMON Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/hwmon.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/math64.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+#include <linux/thermal.h>
-+
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM	2
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL	255
-+
-+/**
-+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance
-+ * @mcu_hwmon:		Parent driver struct pointer
-+ * @tcdev:		Thermal cooling device pointer
-+ * @name:		Thermal cooling device name
-+ * @pwm_channel:	Controlled PWM channel (0 or 1)
-+ * @cooling_levels:	Thermal cooling device cooling levels (DT)
-+ * @cur_level:		Current cooling level
-+ * @num_levels:	Number of cooling levels
-+ */
-+struct iei_wt61p803_puzzle_thermal_cooling_device {
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+	struct thermal_cooling_device *tcdev;
-+	char name[THERMAL_NAME_LENGTH];
-+	int pwm_channel;
-+	u32 *cooling_levels;
-+	int cur_level;
-+	u8 num_levels;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver
-+ * @mcu:				MCU struct pointer
-+ * @response_buffer			Global MCU response buffer
-+ * @thermal_cooling_dev_present:	Per-channel thermal cooling device control indicator
-+ * @cdev:				Per-channel thermal cooling device private structure
-+ */
-+struct iei_wt61p803_puzzle_hwmon {
-+	struct iei_wt61p803_puzzle *mcu;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	bool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+	struct iei_wt61p803_puzzle_thermal_cooling_device
-+		*cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+	struct mutex lock; /* mutex to protect response_buffer array */
-+};
-+
-+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000)
-+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char temp_sensor_ntc_cmd[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+		IEI_WT61P803_PUZZLE_CMD_TEMP,
-+		IEI_WT61P803_PUZZLE_CMD_TEMP_ALL,
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd,
-+						sizeof(temp_sensor_ntc_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 7) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	/* Check the number of NTC values */
-+	if (resp_buf[3] != '2') {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	*value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]);
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60)
-+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+					      int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char fan_speed_cmd[4] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	fan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	fan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	fan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel);
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd,
-+						sizeof(fan_speed_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 7) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	*value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]);
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						 int channel, long pwm_set_val)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char pwm_set_cmd[6] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	pwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	pwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	pwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE;
-+	pwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+	pwm_set_cmd[4] = pwm_set_val;
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd,
-+						sizeof(pwm_set_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char pwm_get_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	pwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	pwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	pwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ;
-+	pwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd,
-+						sizeof(pwm_get_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		return ret;
-+
-+	if (reply_size != 5)
-+		return -EIO;
-+
-+	if (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ)
-+		return -EIO;
-+
-+	*value = resp_buf[3];
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type,
-+				    u32 attr, int channel, long *val)
-+{
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+	switch (type) {
-+	case hwmon_pwm:
-+		return iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val);
-+	case hwmon_fan:
-+		return iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val);
-+	case hwmon_temp:
-+		return iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val);
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type,
-+				     u32 attr, int channel, long val)
-+{
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+	return iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val);
-+}
-+
-+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type,
-+					      u32 attr, int channel)
-+{
-+	const struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data;
-+
-+	switch (type) {
-+	case hwmon_pwm:
-+		if (mcu_hwmon->thermal_cooling_dev_present[channel])
-+			return 0444;
-+		if (attr == hwmon_pwm_input)
-+			return 0644;
-+		break;
-+	case hwmon_fan:
-+		if (attr == hwmon_fan_input)
-+			return 0444;
-+		break;
-+	case hwmon_temp:
-+		if (attr == hwmon_temp_input)
-+			return 0444;
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = {
-+	.is_visible = iei_wt61p803_puzzle_is_visible,
-+	.read = iei_wt61p803_puzzle_read,
-+	.write = iei_wt61p803_puzzle_write,
-+};
-+
-+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {
-+	HWMON_CHANNEL_INFO(pwm,
-+			   HWMON_PWM_INPUT,
-+			   HWMON_PWM_INPUT),
-+	HWMON_CHANNEL_INFO(fan,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT),
-+	HWMON_CHANNEL_INFO(temp,
-+			   HWMON_T_INPUT,
-+			   HWMON_T_INPUT),
-+	NULL
-+};
-+
-+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = {
-+	.ops = &iei_wt61p803_puzzle_hwmon_ops,
-+	.info = iei_wt61p803_puzzle_info,
-+};
-+
-+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long *state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	*state = cdev->num_levels - 1;
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long *state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	if (cdev->cur_level < 0)
-+		return -EAGAIN;
-+
-+	*state = cdev->cur_level;
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+	u8 pwm_level;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	if (state >= cdev->num_levels)
-+		return -EINVAL;
-+
-+	if (state == cdev->cur_level)
-+		return 0;
-+
-+	cdev->cur_level = state;
-+	pwm_level = cdev->cooling_levels[state];
-+
-+	return iei_wt61p803_puzzle_write_pwm_channel(cdev->mcu_hwmon, cdev->pwm_channel, pwm_level);
-+}
-+
-+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = {
-+	.get_max_state = iei_wt61p803_puzzle_get_max_state,
-+	.get_cur_state = iei_wt61p803_puzzle_get_cur_state,
-+	.set_cur_state = iei_wt61p803_puzzle_set_cur_state,
-+};
-+
-+static int
-+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev,
-+					       struct fwnode_handle *child,
-+					       struct iei_wt61p803_puzzle_hwmon *mcu_hwmon)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev;
-+	u32 pwm_channel;
-+	u8 num_levels;
-+	int i, ret;
-+
-+	ret = fwnode_property_read_u32(child, "reg", &pwm_channel);
-+	if (ret)
-+		return ret;
-+
-+	mcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true;
-+
-+	num_levels = fwnode_property_count_u32(child, "cooling-levels");
-+	if (!num_levels)
-+		return -EINVAL;
-+
-+	cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
-+	if (!cdev)
-+		return -ENOMEM;
-+
-+	cdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u32), GFP_KERNEL);
-+	if (!cdev->cooling_levels)
-+		return -ENOMEM;
-+
-+	ret = fwnode_property_read_u32_array(child, "cooling-levels",
-+					     cdev->cooling_levels,
-+					     num_levels);
-+	if (ret) {
-+		dev_err(dev, "Couldn't read property 'cooling-levels'\n");
-+		return ret;
-+	}
-+
-+	for (i = 0; i < num_levels; i++) {
-+		if (cdev->cooling_levels[i] >
-+		    IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL) {
-+			dev_err(dev, "iei_wt61p803_fan state[%d]:%d > %d\n", i,
-+				cdev->cooling_levels[i],
-+				IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL);
-+			return -EINVAL;
-+		}
-+	}
-+
-+	cdev->mcu_hwmon = mcu_hwmon;
-+	cdev->pwm_channel = pwm_channel;
-+	cdev->num_levels = num_levels;
-+	cdev->cur_level = -1;
-+	mcu_hwmon->cdev[pwm_channel] = cdev;
-+
-+	snprintf(cdev->name, THERMAL_NAME_LENGTH, "wt61p803_puzzle_%d", pwm_channel);
-+	cdev->tcdev = devm_thermal_of_cooling_device_register(dev, to_of_node(child), cdev->name,
-+							      cdev, &iei_wt61p803_puzzle_cooling_ops);
-+	if (IS_ERR(cdev->tcdev))
-+		return PTR_ERR(cdev->tcdev);
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+	struct fwnode_handle *child;
-+	struct device *hwmon_dev;
-+	int ret;
-+
-+	mcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL);
-+	if (!mcu_hwmon)
-+		return -ENOMEM;
-+
-+	mcu_hwmon->mcu = mcu;
-+	platform_set_drvdata(pdev, mcu_hwmon);
-+	mutex_init(&mcu_hwmon->lock);
-+
-+	hwmon_dev = devm_hwmon_device_register_with_info(dev, "iei_wt61p803_puzzle",
-+							 mcu_hwmon,
-+							 &iei_wt61p803_puzzle_chip_info,
-+							 NULL);
-+	if (IS_ERR(hwmon_dev))
-+		return PTR_ERR(hwmon_dev);
-+
-+	/* Control fans via PWM lines via Linux Kernel */
-+	if (IS_ENABLED(CONFIG_THERMAL)) {
-+		device_for_each_child_node(dev, child) {
-+			ret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon);
-+			if (ret) {
-+				dev_err(dev, "Enabling the PWM fan failed\n");
-+				fwnode_handle_put(child);
-+				return ret;
-+			}
-+		}
-+	}
-+	return 0;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = {
-+	{ .compatible = "iei,wt61p803-puzzle-hwmon" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table);
-+
-+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = {
-+	.driver = {
-+		.name = "iei-wt61p803-puzzle-hwmon",
-+		.of_match_table = iei_wt61p803_puzzle_hwmon_id_table,
-+	},
-+	.probe = iei_wt61p803_puzzle_hwmon_probe,
-+};
-+
-+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU HWMON Driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
deleted file mode 100644
index 8192d1998b..0000000000
--- a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:35 +0000
-Subject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver
-
-Add support for the IEI WT61P803 PUZZLE LED driver.
-Currently only the front panel power LED is supported,
-since it is the only LED on this board wired through the
-MCU.
-
-The LED is wired directly to the on-board MCU controller
-and is toggled using an MCU command.
-
-Support for more LEDs is going to be added in case more
-boards implement this microcontroller, as LEDs use many
-different GPIOs.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/leds/Kconfig                    |   8 ++
- drivers/leds/Makefile                   |   1 +
- drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++
- 3 files changed, 156 insertions(+)
- create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -307,6 +307,14 @@ config LEDS_IPAQ_MICRO
- 	  Choose this option if you want to use the notification LED on
- 	  Compaq/HP iPAQ h3100 and h3600.
- 
-+config LEDS_IEI_WT61P803_PUZZLE
-+	tristate "LED Support for the IEI WT61P803 PUZZLE MCU"
-+	depends on LEDS_CLASS
-+	depends on MFD_IEI_WT61P803_PUZZLE
-+	help
-+	  This option enables support for LEDs controlled by the IEI WT61P803
-+	  M801 MCU.
-+
- config LEDS_HP6XX
- 	tristate "LED Support for the HP Jornada 6xx"
- 	depends on LEDS_CLASS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_LEDS_HP6XX)		+= leds-hp6xx.
- obj-$(CONFIG_LEDS_INTEL_SS4200)		+= leds-ss4200.o
- obj-$(CONFIG_LEDS_IP30)			+= leds-ip30.o
- obj-$(CONFIG_LEDS_IPAQ_MICRO)		+= leds-ipaq-micro.o
-+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE)	+= leds-iei-wt61p803-puzzle.o
- obj-$(CONFIG_LEDS_IS31FL319X)		+= leds-is31fl319x.o
- obj-$(CONFIG_LEDS_IS31FL32XX)		+= leds-is31fl32xx.o
- obj-$(CONFIG_LEDS_LM3530)		+= leds-lm3530.o
---- /dev/null
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -0,0 +1,147 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU LED Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/leds.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+
-+enum iei_wt61p803_puzzle_led_state {
-+	IEI_LED_OFF = 0x30,
-+	IEI_LED_ON = 0x31,
-+	IEI_LED_BLINK_5HZ = 0x32,
-+	IEI_LED_BLINK_1HZ = 0x33,
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_led - MCU LED Driver
-+ * @cdev:		LED classdev
-+ * @mcu:		MCU struct pointer
-+ * @response_buffer	Global MCU response buffer
-+ * @lock:		General mutex lock to protect simultaneous R/W access to led_power_state
-+ * @led_power_state:	State of the front panel power LED
-+ */
-+struct iei_wt61p803_puzzle_led {
-+	struct led_classdev cdev;
-+	struct iei_wt61p803_puzzle *mcu;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	struct mutex lock; /* mutex to protect led_power_state */
-+	int led_power_state;
-+};
-+
-+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-+	(struct led_classdev *led_cdev)
-+{
-+	return container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev);
-+}
-+
-+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev,
-+							   enum led_brightness brightness)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	unsigned char *resp_buf = priv->response_buffer;
-+	unsigned char led_power_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
-+	led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+
-+	ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
-+						sizeof(led_power_cmd),
-+						resp_buf,
-+						&reply_size);
-+	if (ret)
-+		return ret;
-+
-+	if (reply_size != 3)
-+		return -EIO;
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK))
-+		return -EIO;
-+
-+	mutex_lock(&priv->lock);
-+	priv->led_power_state = brightness;
-+	mutex_unlock(&priv->lock);
-+
-+	return 0;
-+}
-+
-+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	int led_state;
-+
-+	mutex_lock(&priv->lock);
-+	led_state = priv->led_power_state;
-+	mutex_unlock(&priv->lock);
-+
-+	return led_state;
-+}
-+
-+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+	struct iei_wt61p803_puzzle_led *priv;
-+	struct led_init_data init_data = {};
-+	struct fwnode_handle *child;
-+	int ret;
-+
-+	if (device_get_child_node_count(dev) != 1)
-+		return -EINVAL;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->mcu = mcu;
-+	priv->led_power_state = 1;
-+	mutex_init(&priv->lock);
-+	dev_set_drvdata(dev, priv);
-+
-+	child = device_get_next_child_node(dev, NULL);
-+	init_data.fwnode = child;
-+
-+	priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+	priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+	priv->cdev.max_brightness = 1;
-+
-+	ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+	if (ret)
-+		dev_err(dev, "Could not register LED\n");
-+
-+	fwnode_handle_put(child);
-+	return ret;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = {
-+	{ .compatible = "iei,wt61p803-puzzle-leds" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match);
-+
-+static struct platform_driver iei_wt61p803_puzzle_led_driver = {
-+	.driver = {
-+		.name = "iei-wt61p803-puzzle-led",
-+		.of_match_table = iei_wt61p803_puzzle_led_of_match,
-+	},
-+	.probe = iei_wt61p803_puzzle_led_probe,
-+};
-+module_platform_driver(iei_wt61p803_puzzle_led_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE front panel LED driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:leds-iei-wt61p803-puzzle");
diff --git a/target/linux/mvebu/patches-5.15/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch b/target/linux/mvebu/patches-5.15/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch
deleted file mode 100644
index b1d420ef0a..0000000000
--- a/target/linux/mvebu/patches-5.15/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:36 +0000
-Subject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs
- interface documentation
-
-Add the iei-wt61p803-puzzle driver sysfs interface documentation to allow
-monitoring and control of the microcontroller from user space.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../testing/sysfs-driver-iei-wt61p803-puzzle  | 61 +++++++++++++++++++
- 1 file changed, 61 insertions(+)
- create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-
---- /dev/null
-+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-@@ -0,0 +1,61 @@
-+What:		/sys/bus/serial/devices/.../mac_address_*
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Internal factory assigned MAC address values
-+
-+What:		/sys/bus/serial/devices/.../serial_number
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Internal factory assigned serial number
-+
-+What:		/sys/bus/serial/devices/.../version
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU firmware version
-+
-+What:		/sys/bus/serial/devices/.../protocol_version
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU communication protocol version
-+
-+What:		/sys/bus/serial/devices/.../power_loss_recovery
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Host platform power loss recovery settings
-+		Value mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA
-+
-+What:		/sys/bus/serial/devices/.../bootloader_mode
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU bootloader mode status
-+		Value mapping:
-+		0 - normal mode
-+		1 - bootloader mode
-+
-+What:		/sys/bus/serial/devices/.../power_status
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Power status indicates the host platform power on method.
-+		Value mapping (bitwise list):
-+		0x80 - Null
-+		0x40 - Firmware flag
-+		0x20 - Power loss detection flag (powered off)
-+		0x10 - Power loss detection flag (AC mode)
-+		0x08 - Button power on
-+		0x04 - Wake-on-LAN power on
-+		0x02 - RTC alarm power on
-+		0x01 - AC recover power on
-+
-+What:		/sys/bus/serial/devices/.../build_info
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU firmware build date
-+		Format: yyyy/mm/dd hh:mm
-+
-+What:		/sys/bus/serial/devices/.../ac_recovery_status
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Host platform AC recovery status value
-+		Value mapping:
-+		0 - board has not been recovered from power down
-+		1 - board has been recovered from power down
diff --git a/target/linux/mvebu/patches-5.15/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch b/target/linux/mvebu/patches-5.15/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
deleted file mode 100644
index 9015436f6a..0000000000
--- a/target/linux/mvebu/patches-5.15/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:37 +0000
-Subject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver
- documentation
-
-Add the iei-wt61p803-puzzle driver hwmon driver interface documentation.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei-wt61p803-puzzle-hwmon.rst       | 43 +++++++++++++++++++
- Documentation/hwmon/index.rst                 |  1 +
- 2 files changed, 44 insertions(+)
- create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-
---- /dev/null
-+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-@@ -0,0 +1,43 @@
-+.. SPDX-License-Identifier: GPL-2.0-only
-+
-+Kernel driver iei-wt61p803-puzzle-hwmon
-+=======================================
-+
-+Supported chips:
-+ * IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+   Prefix: 'iei-wt61p803-puzzle-hwmon'
-+
-+Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+
-+Description
-+-----------
-+
-+This driver adds fan and temperature sensor reading for some IEI Puzzle
-+series boards.
-+
-+Sysfs attributes
-+----------------
-+
-+The following attributes are supported:
-+
-+- IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+/sys files in hwmon subsystem
-+-----------------------------
-+
-+================= == =====================================================
-+fan[1-5]_input    RO files for fan speed (in RPM)
-+pwm[1-2]          RW files for fan[1-2] target duty cycle (0..255)
-+temp[1-2]_input   RO files for temperature sensors, in millidegree Celsius
-+================= == =====================================================
-+
-+/sys files in thermal subsystem
-+-------------------------------
-+
-+================= == =====================================================
-+cur_state         RW file for current cooling state of the cooling device
-+                     (0..max_state)
-+max_state         RO file for maximum cooling state of the cooling device
-+================= == =====================================================
---- a/Documentation/hwmon/index.rst
-+++ b/Documentation/hwmon/index.rst
-@@ -74,6 +74,7 @@ Hardware Monitoring Kernel Drivers
-    ibmaem
-    ibm-cffps
-    ibmpowernv
-+   iei-wt61p803-puzzle-hwmon
-    ina209
-    ina2xx
-    ina3221
diff --git a/target/linux/mvebu/patches-5.15/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch b/target/linux/mvebu/patches-5.15/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
deleted file mode 100644
index 0b6891343d..0000000000
--- a/target/linux/mvebu/patches-5.15/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:38 +0000
-Subject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE
- driver
-
-Add an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers).
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- MAINTAINERS | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -9057,6 +9057,22 @@ F:	include/net/nl802154.h
- F:	net/ieee802154/
- F:	net/mac802154/
- 
-+IEI WT61P803 M801 MFD DRIVER
-+M:	Luka Kovacic <luka.kovacic@sartura.hr>
-+M:	Luka Perkov <luka.perkov@sartura.hr>
-+M:	Goran Medic <goran.medic@sartura.hr>
-+L:	linux-kernel@vger.kernel.org
-+S:	Maintained
-+F:	Documentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle
-+F:	Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+F:	Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-+F:	Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-+F:	Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-+F:	drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-+F:	drivers/leds/leds-iei-wt61p803-puzzle.c
-+F:	drivers/mfd/iei-wt61p803-puzzle.c
-+F:	include/linux/mfd/iei-wt61p803-puzzle.h
-+
- IFE PROTOCOL
- M:	Yotam Gigi <yotam.gi@gmail.com>
- M:	Jamal Hadi Salim <jhs@mojatatu.com>
diff --git a/target/linux/mvebu/patches-5.15/910-drivers-leds-wt61p803-puzzle-improvements.patch b/target/linux/mvebu/patches-5.15/910-drivers-leds-wt61p803-puzzle-improvements.patch
deleted file mode 100644
index 150a65498c..0000000000
--- a/target/linux/mvebu/patches-5.15/910-drivers-leds-wt61p803-puzzle-improvements.patch
+++ /dev/null
@@ -1,271 +0,0 @@
---- a/drivers/leds/leds-iei-wt61p803-puzzle.c
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -9,9 +9,13 @@
- #include <linux/mfd/iei-wt61p803-puzzle.h>
- #include <linux/mod_devicetable.h>
- #include <linux/module.h>
-+#include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/property.h>
- #include <linux/slab.h>
-+#include <linux/workqueue.h>
-+
-+#define IEI_LEDS_MAX		4
- 
- enum iei_wt61p803_puzzle_led_state {
- 	IEI_LED_OFF = 0x30,
-@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led {
- 	struct iei_wt61p803_puzzle *mcu;
- 	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
- 	struct mutex lock; /* mutex to protect led_power_state */
-+	struct work_struct work;
- 	int led_power_state;
-+	int id;
-+	u8 blinking;
-+	bool active_low;
- };
- 
- static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh
- 	size_t reply_size;
- 	int ret;
- 
-+	if (priv->blinking) {
-+		if (brightness == LED_OFF)
-+			priv->blinking = 0;
-+		else
-+			return 0;
-+	}
-+
- 	led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
- 	led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
--	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
--	led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+	led_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ?
-+				IEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON;
- 
- 	ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
- 						sizeof(led_power_cmd),
-@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_
- 	return led_state;
- }
- 
-+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work);
-+	unsigned char led_blink_cmd[5] = {};
-+	unsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	size_t reply_size;
-+
-+	led_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	led_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+	led_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+	led_blink_cmd[3] = priv->blinking;
-+
-+	iei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd,
-+					  sizeof(led_blink_cmd),
-+					  resp_buf,
-+					  &reply_size);
-+
-+	return;
-+}
-+
-+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev,
-+					     unsigned long *delay_on,
-+					     unsigned long *delay_off)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	u8 blink_mode = 0;
-+	int ret = 0;
-+
-+	/* set defaults */
-+	if (!*delay_on && !*delay_off) {
-+		*delay_on = 500;
-+		*delay_off = 500;
-+	}
-+
-+	/* minimum delay for soft-driven blinking is 100ms to keep load low */
-+	if (*delay_on < 100)
-+		*delay_on = 100;
-+
-+	if (*delay_off < 100)
-+		*delay_off = 100;
-+
-+	/* offload blinking to hardware, if possible */
-+	if (*delay_on != *delay_off) {
-+		ret = -EINVAL;
-+	} else if (*delay_on == 100) {
-+		blink_mode = IEI_LED_BLINK_5HZ;
-+		*delay_on = 100;
-+		*delay_off = 100;
-+	} else if (*delay_on <= 500) {
-+		blink_mode = IEI_LED_BLINK_1HZ;
-+		*delay_on = 500;
-+		*delay_off = 500;
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+	mutex_lock(&priv->lock);
-+	priv->blinking = blink_mode;
-+	mutex_unlock(&priv->lock);
-+
-+	if (blink_mode)
-+		schedule_work(&priv->work);
-+
-+	return ret;
-+}
-+
-+
-+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev,
-+				     struct device_node *np)
-+{
-+	const char *state;
-+	int ret = 0;
-+
-+	state = of_get_property(np, "default-state", NULL);
-+	if (state) {
-+		if (!strcmp(state, "on")) {
-+			ret =
-+			iei_wt61p803_puzzle_led_brightness_set_blocking(
-+				cdev, cdev->max_brightness);
-+		} else  {
-+			ret = iei_wt61p803_puzzle_led_brightness_set_blocking(
-+				cdev, LED_OFF);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
- static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev_of_node(dev);
-+	struct device_node *child;
- 	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
- 	struct iei_wt61p803_puzzle_led *priv;
--	struct led_init_data init_data = {};
--	struct fwnode_handle *child;
- 	int ret;
-+	u32 reg;
- 
--	if (device_get_child_node_count(dev) != 1)
-+	if (device_get_child_node_count(dev) > IEI_LEDS_MAX)
- 		return -EINVAL;
- 
--	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
--	if (!priv)
--		return -ENOMEM;
--
--	priv->mcu = mcu;
--	priv->led_power_state = 1;
--	mutex_init(&priv->lock);
--	dev_set_drvdata(dev, priv);
--
--	child = device_get_next_child_node(dev, NULL);
--	init_data.fwnode = child;
--
--	priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
--	priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
--	priv->cdev.max_brightness = 1;
-+	for_each_available_child_of_node(np, child) {
-+		struct led_init_data init_data = {};
- 
--	ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
--	if (ret)
--		dev_err(dev, "Could not register LED\n");
-+		ret = of_property_read_u32(child, "reg", &reg);
-+		if (ret) {
-+			dev_err(dev, "Failed to read led 'reg' property\n");
-+			goto put_child_node;
-+		}
-+
-+		if (reg > IEI_LEDS_MAX) {
-+			dev_err(dev, "Invalid led reg %u\n", reg);
-+			ret = -EINVAL;
-+			goto put_child_node;
-+		}
-+
-+		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+		if (!priv) {
-+			ret = -ENOMEM;
-+			goto put_child_node;
-+		}
-+
-+		mutex_init(&priv->lock);
-+
-+		dev_set_drvdata(dev, priv);
-+
-+		if (of_property_read_bool(child, "active-low"))
-+			priv->active_low = true;
-+
-+		priv->mcu = mcu;
-+		priv->id = reg;
-+		priv->led_power_state = 1;
-+		priv->blinking = 0;
-+		init_data.fwnode = of_fwnode_handle(child);
-+
-+		priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+		priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+		priv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink;
-+
-+		priv->cdev.max_brightness = 1;
-+
-+		INIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink);
-+
-+		ret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child);
-+		if (ret) {
-+			dev_err(dev, "Could apply default from DT\n");
-+			goto put_child_node;
-+		}
-+
-+		ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+		if (ret) {
-+			dev_err(dev, "Could not register LED\n");
-+			goto put_child_node;
-+		}
-+	}
-+
-+	return ret;
- 
--	fwnode_handle_put(child);
-+put_child_node:
-+	of_node_put(child);
- 	return ret;
- }
- 
---- a/include/linux/mfd/iei-wt61p803-puzzle.h
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -36,7 +36,7 @@
- #define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
- 
- #define IEI_WT61P803_PUZZLE_CMD_LED			0x52 /* R */
--#define IEI_WT61P803_PUZZLE_CMD_LED_POWER		0x31 /* 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n)		(0x30 | (n))
- 
- #define IEI_WT61P803_PUZZLE_CMD_TEMP			0x54 /* T */
- #define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL		0x41 /* A */
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf(
- 	struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
- 	int ret;
- 
-+	print_hex_dump_debug("puzzle-mcu rx: ", DUMP_PREFIX_NONE,
-+			     16, 1, data, size, false);
-+
- 	ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
- 	/* Return the number of processed bytes if function returns error,
- 	 * discard the remaining incoming data, since the frame this data
-@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st
- 
- 	cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
- 
-+	print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
-+			     16, 1, cmd, size, false);
-+
- 	/* Initialize reply struct */
- 	reinit_completion(&mcu->reply->received);
- 	mcu->reply->size = 0;
diff --git a/target/linux/mvebu/patches-5.15/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch b/target/linux/mvebu/patches-5.15/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch
deleted file mode 100644
index 2f0b1788ff..0000000000
--- a/target/linux/mvebu/patches-5.15/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch
+++ /dev/null
@@ -1,63 +0,0 @@
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -241,6 +241,7 @@ int iei_wt61p803_puzzle_write_command(st
- {
- 	struct device *dev = &mcu->serdev->dev;
- 	int ret;
-+	int retries;
- 
- 	if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
- 		return -EINVAL;
-@@ -252,24 +253,36 @@ int iei_wt61p803_puzzle_write_command(st
- 	print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
- 			     16, 1, cmd, size, false);
- 
-+	retries = 3;
- 	/* Initialize reply struct */
--	reinit_completion(&mcu->reply->received);
--	mcu->reply->size = 0;
--	usleep_range(2000, 10000);
--	serdev_device_write_flush(mcu->serdev);
--	ret = serdev_device_write_buf(mcu->serdev, cmd, size);
--	if (ret < 0)
--		goto exit;
--
--	serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
--	ret = wait_for_completion_timeout(&mcu->reply->received,
--					  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
--	if (ret == 0) {
--		dev_err(dev, "Command reply receive timeout\n");
--		ret = -ETIMEDOUT;
--		goto exit;
-+	while (retries) {
-+		reinit_completion(&mcu->reply->received);
-+		mcu->reply->size = 0;
-+		usleep_range(2000, 10000);
-+		serdev_device_write_flush(mcu->serdev);
-+		ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+		if (ret < 0)
-+			goto exit;
-+
-+		serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+		ret = wait_for_completion_timeout(&mcu->reply->received,
-+						  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+		retries--;
-+		if (ret == 0) {
-+			if (retries == 0) {
-+				dev_err(dev, "Command reply receive timeout\n");
-+				ret = -ETIMEDOUT;
-+				goto exit;
-+			}
-+		}
-+		else {
-+			if (mcu->reply->data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+				mcu->reply->data[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+				mcu->reply->data[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK) {
-+				break;
-+			}
-+		}
- 	}
--
- 	*reply_size = mcu->reply->size;
- 	/* Copy the received data, as it will not be available after a new frame is received */
- 	memcpy(reply_data, mcu->reply->data, mcu->reply->size);
diff --git a/target/linux/mvebu/patches-6.1/400-find_active_root.patch b/target/linux/mvebu/patches-6.1/400-find_active_root.patch
index 5582d20c68..90164adcd4 100644
--- a/target/linux/mvebu/patches-6.1/400-find_active_root.patch
+++ b/target/linux/mvebu/patches-6.1/400-find_active_root.patch
@@ -22,7 +22,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  	struct device_node *pp;
  	int nr_parts, i, ret = 0;
  	bool dedicated = true;
-@@ -133,9 +136,13 @@ static int parse_fixed_partitions(struct
+@@ -152,9 +155,13 @@ static int parse_fixed_partitions(struct
  		parts[i].size = of_read_number(reg + a_cells, s_cells);
  		parts[i].of_node = pp;
  
@@ -39,7 +39,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  		parts[i].name = partname;
  
  		if (of_get_property(pp, "read-only", &len))
-@@ -252,6 +259,18 @@ static int __init ofpart_parser_init(voi
+@@ -271,6 +278,18 @@ static int __init ofpart_parser_init(voi
  	return 0;
  }
  
diff --git a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
index 15762be81d..918132e293 100644
--- a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
+++ b/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
@@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 ---
 --- a/drivers/net/ethernet/marvell/mvneta.c
 +++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -5234,6 +5234,16 @@ static int mvneta_setup_tc(struct net_de
+@@ -5233,6 +5233,16 @@ static int mvneta_setup_tc(struct net_de
  	}
  }
  
@@ -26,7 +26,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static const struct net_device_ops mvneta_netdev_ops = {
  	.ndo_open            = mvneta_open,
  	.ndo_stop            = mvneta_stop,
-@@ -5244,6 +5254,9 @@ static const struct net_device_ops mvnet
+@@ -5243,6 +5253,9 @@ static const struct net_device_ops mvnet
  	.ndo_fix_features    = mvneta_fix_features,
  	.ndo_get_stats64     = mvneta_get_stats64,
  	.ndo_eth_ioctl        = mvneta_ioctl,
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts
new file mode 100644
index 0000000000..d935e19ad2
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-rm2-6.dts
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074-512m.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "CMCC RM2-6";
+	compatible = "cmcc,rm2-6", "qcom,ipq8074";
+
+	aliases {
+		serial0 = &blsp1_uart5;
+		serial1 = &blsp1_uart3;
+		led-boot = &led_status_red;
+		led-failsafe = &led_status_red;
+		led-running = &led_status_blue;
+		led-upgrade = &led_status_amber;
+		/*
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
+		ethernet0 = &dp4;
+		ethernet1 = &dp2;
+		ethernet2 = &dp5;
+		label-mac-device = &dp4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " root=/dev/ubiblock0_1";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+		};
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_amber: status-amber {
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_STATUS;
+			gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_blue: status-blue {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_red: status-red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	fan: gpio-fan {
+		#cooling-cells = <2>;
+		compatible = "gpio-fan";
+		gpio = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <0 0>, <1 1>;
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio-pins {
+		mdc {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&blsp1_uart3 {
+	status = "okay";
+};
+
+&blsp1_uart5 {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <8>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "qcom,smem-part";
+		};
+	};
+};
+
+&cpu0_thermal {
+	trips {
+		cpu0_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu0_trip_active>;
+		};
+	};
+};
+
+&cpu1_thermal {
+	trips {
+		cpu1_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu1_trip_active>;
+		};
+	};
+};
+
+&cpu2_thermal {
+	trips {
+		cpu2_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu2_trip_active>;
+		};
+	};
+};
+
+&cpu3_thermal {
+	trips {
+		cpu3_trip_active: cpu-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu3_trip_active>;
+		};
+	};
+};
+
+&cluster_thermal {
+	trips {
+		cluster_active: cluster-active {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cluster-active {
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cluster_active>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+	ethernet-phy-package@0 {
+		compatible = "qcom,qca8075-package";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_lan_bmp = <(ESS_PORT2 | ESS_PORT4)>;
+	switch_wan_bmp = <ESS_PORT5>;
+	switch_mac_mode = <MAC_MODE_PSGMII>;
+
+	qcom,port_phyinfo {
+		port@2 {
+			port_id = <2>;
+			phy_address = <1>;
+		};
+		port@4 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+		port@5 {
+			port_id = <5>;
+			phy_address = <4>;
+		};
+	};
+};
+
+&edma {
+	status = "okay";
+};
+
+/*
+ * Directly connect to the Hi5630
+ * PLC (Power Line Communication)
+ */
+&dp2 {
+	status = "okay";
+	phy-handle = <&qca8075_1>;
+	label = "plc";
+};
+
+&dp4 {
+	status = "okay";
+	phy-handle = <&qca8075_3>;
+	label = "lan";
+};
+
+&dp5 {
+	status = "okay";
+	phy-handle = <&qca8075_4>;
+	label = "wan";
+};
+
+&wifi {
+	status = "okay";
+
+	qcom,ath11k-calibration-variant = "CMCC-RM2-6";
+	qcom,ath11k-fw-memory-mode = <1>;
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
index 4dcacdf297..081e932b5c 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
@@ -414,7 +414,6 @@
 
 	switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT6)>; /* lan port bitmap */
 	switch_wan_bmp = <ESS_PORT5>; /* wan port bitmap */
-	malibu_first_phy_addr = <16>; /* PHY addr of the first malibu PHY */
 	switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
 	switch_mac_mode1 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance1*/
 	switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
@@ -486,12 +485,14 @@
 &dp5 {
 	status = "okay";
 	qcom,mactype = <1>;
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_8>;
 	label = "10g-1";
 };
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_0>;
 	label = "10g-2";
 };
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts
index 3f40c17ab4..c85e9f1993 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-aw1000.dts
@@ -246,24 +246,33 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_0: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
+	ethernet-phy-package@0 {
+		compatible = "qcom,qca8075-package";
+		#address-cells = <1>;
+		#size-cells = <0>;
 		reg = <0>;
-	};
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+		qcom,package-mode = "qsgmii";
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
 	};
 
 	qca8081: ethernet-phy@28 {
@@ -271,6 +280,19 @@
 		reg = <28>;
 		reset-deassert-us = <10000>;
 		reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@2 {
+				reg = <2>;
+				active-low;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_WAN;
+				default-state = "keep";
+			};
+		};
 	};
 };
 
@@ -313,24 +335,28 @@
 
 &dp1 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_0>;
 	label = "lan1";
 };
 
 &dp2 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_1>;
 	label = "lan2";
 };
 
 &dp3 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_2>;
 	label = "lan3";
 };
 
 &dp4 {
 	status = "okay";
+	phy-mode = "qsgmii";
 	phy-handle = <&qca8075_3>;
 	label = "lan4";
 };
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
index 70cc2921c7..289680d678 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
@@ -268,6 +268,7 @@
 &dp6_syn {
 	status = "okay";
 	qcom,mactype = <1>;
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c>;
 	label = "wan";
 };
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
index 6f98e01b9a..76838b86c5 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
@@ -23,24 +23,6 @@
 		switch_access_mode = "local bus";
 		switch_cpu_bmp = <ESS_PORT0>;  /* cpu port bitmap */
 		switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
-		/* This is a special binding that controls how the malibu PHY are
-		 * init. This value reflect the PHY addr of the first malibu PHY.
-		 * Malibu PHY are in a bundle of 5 PHY.
-		 * Some device might have some port not connected.
-		 * SSDK still needs the addrs of the first PHY (even if not connected)
-		 * to correctly setup the malibu PHY.
-		 *
-		 * This is needed as previously SSDK based this on the port bmp, but
-		 * this can be problematic now that we specify correct bmp.
-		 *
-		 * Most common configuration have the malibu PHY placed at 0.
-		 * But some device might have it placed at address 16.
-		 * To drive the correct value, check the port id of the malibu PHY
-		 * and try to understand what is the first one in devices where some
-		 * port are missing. port_phyinfo is normally the way to go to derive
-		 * this value in the few special cases.
-		 */
-		malibu_first_phy_addr = <0>;
 		clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
 			 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
 			 <&gcc GCC_UNIPHY0_AHB_CLK>,
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
index 5d7d84ac52..ac3077b29d 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
@@ -405,6 +405,7 @@
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c>;
 	label = "10g";
 	nvmem-cells = <&macaddr_lan 0>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
index 5b9a45e961..0be50603ba 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
@@ -274,6 +274,7 @@
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr111b0>;
 	label = "lan5";
 	nvmem-cells = <&macaddr_dp6_syn>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts
index 91561e5c2a..35f0c3e220 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wax630.dts
@@ -153,7 +153,7 @@
 
 	switch_lan_bmp = <(ESS_PORT4 | ESS_PORT6)>;
 	switch_mac_mode = <MAC_MODE_PSGMII>;
-	switch_mac_mode2 = <MAC_MODE_USXGMII>;
+	switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>;
 
 	qcom,port_phyinfo {
 		port@4 {
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
index a0631b3b71..d6411e4fa5 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
@@ -327,6 +327,7 @@
 
 &dp5_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_1>;
 	label = "wan";
 	nvmem-cells = <&macaddr_appsblenv_ethaddr>;
@@ -335,6 +336,7 @@
 
 &dp6_syn {
 	status = "okay";
+	phy-mode = "usxgmii";
 	phy-handle = <&aqr113c_2>;
 	label = "lan1";
 	nvmem-cells = <&macaddr_appsblenv_ethaddr>;
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi
index ef67742c03..13ce8d1601 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4200.dtsi
@@ -350,24 +350,31 @@
 	pinctrl-names = "default";
 	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
 
-	qca8075_1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
 
-	qca8075_2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <2>;
-	};
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
 
-	qca8075_3: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <3>;
-	};
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
 
-	qca8075_4: ethernet-phy@4 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <4>;
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
 	};
 };
 
diff --git a/target/linux/qualcommax/image/ipq807x.mk b/target/linux/qualcommax/image/ipq807x.mk
index 2616e5fbbc..109cb97c3a 100644
--- a/target/linux/qualcommax/image/ipq807x.mk
+++ b/target/linux/qualcommax/image/ipq807x.mk
@@ -36,6 +36,21 @@ define Device/buffalo_wxr-5950ax12
 endef
 TARGET_DEVICES += buffalo_wxr-5950ax12
 
+define Device/cmcc_rm2-6
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := CMCC
+	DEVICE_MODEL := RM2-6
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_DTS_CONFIG := config@ac02
+	SOC := ipq8070
+	IMAGES := factory.bin sysupgrade.bin
+	IMAGE/factory.bin := append-ubi | qsdk-ipq-factory-nand
+	DEVICE_PACKAGES := ipq-wifi-cmcc_rm2-6 kmod-hwmon-gpiofan
+endef
+TARGET_DEVICES += cmcc_rm2-6
+
 define Device/compex_wpq873
 	$(call Device/FitImage)
 	$(call Device/UbiFit)
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds
index ef984f7dda..bce4246bc9 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/01_leds
@@ -9,6 +9,7 @@ case "$board" in
 arcadyan,aw1000)
 	ucidef_set_led_netdev "5g" "5G" "green:5g" "wwan0"
 	ucidef_set_led_netdev "wan" "WAN" "green:internet" "wan"
+	ucidef_set_led_netdev "wan-port-link" "WAN-PORT-LINK" "90000.mdio-1:1c:green:wan" "wan" "tx rx link_10 link_100 link_1000 link_2500"
 	;;
 dynalink,dl-wrx36)
 	ucidef_set_led_netdev "wan-port-link-green" "WAN-PORT-LINK-GREEN" "90000.mdio-1:1c:green:wan" "wan" "link_2500"
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
index 5d3e419aa1..b7e4730695 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
@@ -17,6 +17,9 @@ ipq807x_setup_interfaces()
 	xiaomi,ax9000)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
 		;;
+	cmcc,rm2-6)
+		ucidef_set_interfaces_lan_wan "lan plc" "wan"
+		;;
 	compex,wpq873|\
 	linksys,mx4200v1|\
 	linksys,mx4200v2|\
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
index d5382be26f..21630224ce 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
@@ -11,6 +11,7 @@ case "$FIRMWARE" in
 	case "$board" in
 	arcadyan,aw1000|\
 	buffalo,wxr-5950ax12|\
+	cmcc,rm2-6|\
 	compex,wpq873|\
 	dynalink,dl-wrx36|\
 	edgecore,eap102|\
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
index b37650c4b2..6a8abff661 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
@@ -18,6 +18,11 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label)  8 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 16 > /sys${DEVPATH}/macaddress
 		;;
+	cmcc,rm2-6|\
+	zte,mf269)
+		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
+		;;
 	linksys,mx4200v1|\
 	linksys,mx4200v2)
 		label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
@@ -25,10 +30,6 @@ case "$board" in
 		[ "$PHYNBR" = "1" ] && macaddr_add $label_mac 1 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "2" ] && macaddr_add $label_mac 3 > /sys${DEVPATH}/macaddress
 		;;
-	zte,mf269)
-		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
-		;;
 	zte,mf269-stock)
 		mac_addr="$(mtd_get_mac_binary mac 0x0)"
 		[ "$mac_addr" != "00:00:00:00:00:00" ] || mac_addr="$(get_mac_binary "$(find_mtd_chardev mac)" 0x20000)"
diff --git a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
index 6d2b2316b9..b157700614 100644
--- a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
@@ -44,6 +44,7 @@ platform_pre_upgrade() {
 platform_do_upgrade() {
 	case "$(board_name)" in
 	arcadyan,aw1000|\
+	cmcc,rm2-6|\
 	compex,wpq873|\
 	dynalink,dl-wrx36|\
 	edimax,cax1800|\
diff --git a/target/linux/ramips/image/mt76x8.mk b/target/linux/ramips/image/mt76x8.mk
index 07a662b351..be83fb8885 100644
--- a/target/linux/ramips/image/mt76x8.mk
+++ b/target/linux/ramips/image/mt76x8.mk
@@ -494,7 +494,7 @@ define Device/ravpower_rp-wd009
   IMAGE_SIZE := 14272k
   DEVICE_VENDOR := RAVPower
   DEVICE_MODEL := RP-WD009
-  UBOOT_PATH := $(STAGING_DIR_IMAGE)/ravpower_rp-wd009-u-boot.bin
+  UBOOT_PATH := $(STAGING_DIR_IMAGE)/mt7628_ravpower_rp-wd009-u-boot.bin
   DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \
 	kmod-sdhci-mt7620 kmod-i2c-mt7628 ravpower-mcu
   IMAGES += factory.bin
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch b/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch
index 35a1c91f7c..361dc81df7 100644
--- a/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch
+++ b/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch
@@ -13,7 +13,7 @@ Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -13012,6 +13012,12 @@ S:	Maintained
+@@ -13014,6 +13014,12 @@ S:	Maintained
  F:	Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
  F:	drivers/clk/ralink/clk-mt7621.c
  
diff --git a/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch
index ac8585b74f..a6e2aa04ca 100644
--- a/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch
+++ b/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch
@@ -14,15 +14,15 @@ Signed-off-by: René van Dorst <opensource@vdorst.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4612,6 +4612,7 @@ static const struct net_device_ops mtk_n
+@@ -4643,6 +4643,7 @@ static const struct net_device_ops mtk_n
  
  static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
  {
 +	const char *name = of_get_property(np, "label", NULL);
  	const __be32 *_id = of_get_property(np, "reg", NULL);
+ 	struct device_node *pcs_np;
  	phy_interface_t phy_mode;
- 	struct phylink *phylink;
-@@ -4783,6 +4784,9 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4840,6 +4841,9 @@ static int mtk_add_mac(struct mtk_eth *e
  		register_netdevice_notifier(&mac->device_notifier);
  	}
  
diff --git a/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
index 73ed55a085..91159f2c63 100644
--- a/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
+++ b/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
@@ -71,7 +71,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
  		break;
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1039,14 +1039,16 @@ struct phy_device *phy_find_first(struct
+@@ -1037,14 +1037,16 @@ struct phy_device *phy_find_first(struct
  }
  EXPORT_SYMBOL(phy_find_first);
  
@@ -95,7 +95,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
  		phydev->mii_ts->link_state(phydev->mii_ts, phydev);
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -1602,7 +1602,8 @@ bool phylink_expects_phy(struct phylink
+@@ -1687,7 +1687,8 @@ bool phylink_expects_phy(struct phylink
  }
  EXPORT_SYMBOL_GPL(phylink_expects_phy);
  
diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk
index 60249ff2fd..19a40f1f61 100644
--- a/target/linux/realtek/image/rtl838x.mk
+++ b/target/linux/realtek/image/rtl838x.mk
@@ -168,6 +168,7 @@ define Device/netgear_nge
   SOC := rtl8380
   IMAGE_SIZE := 14848k
   UIMAGE_MAGIC := 0x4e474520
+  UIMAGE_NAME := 9.9.9.9
   DEVICE_VENDOR := NETGEAR
 endef
 
diff --git a/tools/expat/Makefile b/tools/expat/Makefile
index 5ee91bfc8a..1df6f8ec96 100644
--- a/tools/expat/Makefile
+++ b/tools/expat/Makefile
@@ -24,6 +24,7 @@ HOSTCC := $(HOSTCC_NOCACHE)
 HOST_CONFIGURE_ARGS += \
 	--disable-shared \
 	--without-docbook \
+	--without-tests \
 	--with-pic
 
 define Host/Uninstall