mediatek: add support for Winbond W25MxxGV W25NxxKV
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit b71e98d254)
This commit is contained in:
Chen Minqiang
Tianling Shen
parent
33f9a7be44
commit
d6187fb2e5
@ -0,0 +1,161 @@
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From 9471c6ebf176284108115f60e22a176e70b97c0b Mon Sep 17 00:00:00 2001
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From: Chen Minqiang <ptpt52@gmail.com>
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Date: Thu, 12 Oct 2023 06:51:40 +0800
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Subject: [PATCH] mtd: spinand: winbond: Support for W25MxxGV W25NxxKV series
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---
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drivers/mtd/nand/spi/winbond.c | 115 +++++++++++++++++++++++++++++++++
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1 file changed, 115 insertions(+)
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--- a/drivers/mtd/nand/spi/winbond.c
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+++ b/drivers/mtd/nand/spi/winbond.c
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@@ -15,6 +15,23 @@
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#define WINBOND_CFG_BUF_READ BIT(3)
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+#define W25N02_N04KV_STATUS_ECC_MASK (3 << 4)
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+#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
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+#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS (1 << 4)
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+#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
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+#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
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+
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+#define W25N01_M02GV_STATUS_ECC_MASK (3 << 4)
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+#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS (0 << 4)
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+#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4)
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+#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4)
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+
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+#define W25N01KV_STATUS_ECC_MASK (3 << 4)
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+#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
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+#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4)
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+#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4)
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+#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
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+
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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@@ -31,6 +48,29 @@ static SPINAND_OP_VARIANTS(update_cache_
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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+static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ return -ERANGE;
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+}
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+
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+static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section > 3)
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+ return -ERANGE;
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+
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+ region->offset = (16 * section) + 2;
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+ region->length = 14;
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+
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+ return 0;
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+}
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+
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+static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = {
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+ .ecc = w25n02kv_n04kv_ooblayout_ecc,
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+ .free = w25n02kv_n04kv_ooblayout_free,
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+};
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+
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static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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@@ -140,6 +180,58 @@ static int w25n02kv_ecc_get_status(struc
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return -EINVAL;
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}
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+static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ switch (status & W25N01KV_STATUS_ECC_MASK) {
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+ case W25N01KV_STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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+
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+ case W25N01KV_STATUS_ECC_1_3_BITFLIPS:
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+ return 3;
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+
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+ case W25N01KV_STATUS_ECC_4_BITFLIPS:
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+ return 4;
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+
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+ case W25N01KV_STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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+static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ switch (status & W25N02_N04KV_STATUS_ECC_MASK) {
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+ case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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+
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+ case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS:
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+ return 3;
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+
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+ case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS:
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+ return 4;
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+
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+ /* W25N02_N04KV_use internal 8bit ECC algorithm.
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+ * But the ECC strength is 4 bit requried.
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+ * Return 3 if the bit bit flip count less than 5.
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+ * Return 4 if the bit bit flip count more than 5 to 8.
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+ */
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+
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+ case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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static const struct spinand_info winbond_spinand_table[] = {
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SPINAND_INFO("W25M02GV",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
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@@ -151,6 +243,16 @@ static const struct spinand_info winbond
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0,
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SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
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SPINAND_SELECT_TARGET(w25m02gv_select_target)),
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+ SPINAND_INFO("W25N01KV",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
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+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
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+ w25n01kv_ecc_get_status)),
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SPINAND_INFO("W25N01GV",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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@@ -169,6 +271,19 @@ static const struct spinand_info winbond
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
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+ /* W25N04KV has 2-die(lun), however, it can select die automatically.
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+ * Treat it as single die here and double block size.
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+ */
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+ SPINAND_INFO("W25N04KV",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
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+ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
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+ w25n02kv_n04kv_ecc_get_status)),
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};
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static int winbond_spinand_init(struct spinand_device *spinand)
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