Merge Official Source

2020-11-14 13:17:40 +08:00 · 2020-11-14 13:17:40 +08:00 · dd07d73b73
commit dd07d73b73
parent 1cc893a8d6 95b0751d0f
100 changed files with 8196 additions and 1734 deletions
--- a/include/image.mk
+++ b/include/image.mk
@ -563,6 +563,7 @@ define Device/Build/image
 	@mkdir -p $$(shell dirname $$@)
 	DEVICE_ID="$(DEVICE_NAME)" \
 	BIN_DIR="$(BIN_DIR)" \
+	SOURCE_DATE_EPOCH=$(SOURCE_DATE_EPOCH) \
 	IMAGE_NAME="$(IMAGE_NAME)" \
 	IMAGE_TYPE=$(word 1,$(subst ., ,$(2))) \
 	IMAGE_PREFIX="$(IMAGE_PREFIX)" \
--- a/include/kernel-build.mk
+++ b/include/kernel-build.mk
@ -136,6 +136,7 @@ define BuildKernel
  $(LINUX_DIR)/.modules: export PKG_CONFIG_LIBDIR=$$(STAGING_DIR_HOST)/lib/pkgconfig
  $(LINUX_DIR)/.modules: $(STAMP_CONFIGURED) $(LINUX_DIR)/.config FORCE
 	$(Kernel/CompileModules)
+	mkdir -p $(PKG_SYMVERS_DIR)
 	touch $$@

  $(LINUX_DIR)/.image: export STAGING_PREFIX=$$(STAGING_DIR_HOST)
@ -169,9 +170,7 @@ define BuildKernel
 		) \
 		YACC=$(STAGING_DIR_HOST)/bin/bison \
 		$$@
-	$(LINUX_RECONF_DIFF) $(LINUX_DIR)/.config | \
-		grep -vE '(CONFIG_CC_(HAS_ASM_GOTO|IS_GCC|IS_CLANG)|GCC_VERSION)=' \
-		> $(LINUX_RECONFIG_TARGET)
+	$(call LINUX_RECONF_DIFF,$(LINUX_DIR)/.config) > $(LINUX_RECONFIG_TARGET)

  install: $(LINUX_DIR)/.image
 	+$(MAKE) -C image compile install TARGET_BUILD=
--- a/include/kernel.mk
+++ b/include/kernel.mk
@ -118,7 +118,8 @@ KERNEL_MAKE_FLAGS = \
 	CONFIG_SHELL="$(BASH)" \
 	$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \
 	$(if $(PKG_BUILD_ID),LDFLAGS_MODULE=--build-id=0x$(PKG_BUILD_ID)) \
-	cmd_syscalls=
+	cmd_syscalls= \
+	$(if $(__package_mk),KBUILD_EXTRA_SYMBOLS="$(wildcard $(PKG_SYMVERS_DIR)/*.symvers)")

 ifeq ($(call qstrip,$(CONFIG_EXTERNAL_KERNEL_TREE))$(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),)
  KERNEL_MAKE_FLAGS += \
@ -140,14 +141,6 @@ PKG_EXTMOD_SUBDIRS ?= .

 PKG_SYMVERS_DIR = $(KERNEL_BUILD_DIR)/symvers

-define populate_module_symvers
-	@mkdir -p $(PKG_SYMVERS_DIR)
-	cat /dev/null > $(PKG_SYMVERS_DIR)/$(PKG_NAME).symvers; \
-	for subdir in $(PKG_EXTMOD_SUBDIRS); do \
-		cat $(PKG_SYMVERS_DIR)/*.symvers 2>/dev/null > $(PKG_BUILD_DIR)/$$$$subdir/Module.symvers; \
-	done
-endef
-
 define collect_module_symvers
 	for subdir in $(PKG_EXTMOD_SUBDIRS); do \
 		realdir=$$$$(readlink -f $(PKG_BUILD_DIR)); \
@ -161,7 +154,6 @@ endef

 define KernelPackage/hooks
  ifneq ($(PKG_NAME),kernel)
-    Hooks/Compile/Pre += populate_module_symvers
    Hooks/Compile/Post += collect_module_symvers
  endif
  define KernelPackage/hooks
--- a/include/netfilter.mk
+++ b/include/netfilter.mk
@ -362,6 +362,7 @@ $(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB_INET, $(P_XT)nft_fib
 $(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB_IPV4, $(P_V4)nft_fib_ipv4),))
 $(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB_IPV6, $(P_V6)nft_fib_ipv6),))

+$(eval $(if $(NF_KMOD),$(call nf_add,NFT_QUEUE,CONFIG_NFT_QUEUE, $(P_XT)nft_queue),))

 # userland only
 IPT_BUILTIN += $(NF_IPT-y) $(NF_IPT-m)
--- a/include/target.mk
+++ b/include/target.mk
@ -200,11 +200,11 @@ ifeq ($(CONFIG_TARGET),env)
  LINUX_RECONFIG_TARGET = $(TOPDIR)/env/kernel-config
 endif

-__linux_confcmd = $(SCRIPT_DIR)/kconfig.pl $(2) $(patsubst %,+,$(wordlist 2,9999,$(1))) $(1)
+__linux_confcmd = $(2) $(patsubst %,+,$(wordlist 2,9999,$(1))) $(1)

-LINUX_CONF_CMD = $(call __linux_confcmd,$(LINUX_KCONFIG_LIST),)
-LINUX_RECONF_CMD = $(call __linux_confcmd,$(LINUX_RECONFIG_LIST),)
-LINUX_RECONF_DIFF = $(call __linux_confcmd,$(filter-out $(LINUX_RECONFIG_TARGET),$(LINUX_RECONFIG_LIST)),'>')
+LINUX_CONF_CMD = $(SCRIPT_DIR)/kconfig.pl $(call __linux_confcmd,$(LINUX_KCONFIG_LIST))
+LINUX_RECONF_CMD = $(SCRIPT_DIR)/kconfig.pl $(call __linux_confcmd,$(LINUX_RECONFIG_LIST))
+LINUX_RECONF_DIFF = $(SCRIPT_DIR)/kconfig.pl - '>' $(call __linux_confcmd,$(filter-out $(LINUX_RECONFIG_TARGET),$(LINUX_RECONFIG_LIST))) $(1) $(GENERIC_PLATFORM_DIR)/config-filter

 ifeq ($(DUMP),1)
  BuildTarget=$(BuildTargets/DumpCurrent)
--- a/package/boot/uboot-envtools/Makefile
+++ b/package/boot/uboot-envtools/Makefile
@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=uboot-envtools
 PKG_DISTNAME:=u-boot
 PKG_VERSION:=2020.04
-PKG_RELEASE:=4
+PKG_RELEASE:=5

 PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
--- a/package/boot/uboot-envtools/files/ramips
+++ b/package/boot/uboot-envtools/files/ramips
@ -29,6 +29,8 @@ buffalo,wsr-1166dhp|\
 buffalo,wsr-600dhp|\
 mediatek,linkit-smart-7688|\
 samknows,whitebox-v8|\
+xiaomi,mir3g-v2|\
+xiaomi,mi-router-4a-gigabit|\
 xiaomi,miwifi-nano|\
 zbtlink,zbt-wg2626)
 	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" "0x10000"
--- a/package/boot/uboot-sunxi/Makefile
+++ b/package/boot/uboot-sunxi/Makefile
@ -226,6 +226,14 @@ define U-Boot/pangolin
  UENV:=pangolin
 endef

+define U-Boot/libretech_all_h3_cc_h5
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Libre Computer ALL-H3-CC H5
+  BUILD_DEVICES:=libretech_all-h3-cc-h5
+  DEPENDS:=+PACKAGE_u-boot-libretech_all_h3_cc_h5:arm-trusted-firmware-sunxi
+  UENV:=a64
+endef
+
 define U-Boot/nanopi_neo_plus2
  BUILD_SUBTARGET:=cortexa53
  NAME:=NanoPi NEO Plus2 (H5)
@ -328,7 +336,8 @@ UBOOT_TARGETS := \
 	pangolin \
 	pine64_plus \
 	sopine_baseboard \
-	orangepi_zero_plus
+	orangepi_zero_plus \
+	libretech_all_h3_cc_h5

 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes

--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@ -1225,3 +1225,41 @@ define KernelPackage/igc/description
 endef

 $(eval $(call KernelPackage,igc))
+
+define KernelPackage/sfc
+  SUBMENU:=$(NETWORK_DEVICES_MENU)
+  TITLE:=Solarflare SFC9000/SFC9100/EF100-family support
+  DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-lib-crc32c +kmod-ptp +kmod-hwmon-core
+  KCONFIG:= \
+	CONFIG_SFC \
+	CONFIG_SFC_MTD \
+	CONFIG_SFC_MCDI_MON \
+	CONFIG_SFC_MCDI_LOGGING \
+	CONFIG_SFC_SRIOV
+  FILES:=$(LINUX_DIR)/drivers/net/ethernet/sfc/sfc.ko
+  AUTOLOAD:=$(call AutoProbe,sfc)
+endef
+
+define KernelPackage/sfc/description
+  Solarflare SFC9000/SFC9100/EF100-family support
+  Solarflare EF100 support requires at least kernel version 5.9
+endef
+
+$(eval $(call KernelPackage,sfc))
+
+define KernelPackage/sfc-falcon
+  SUBMENU:=$(NETWORK_DEVICES_MENU)
+  TITLE:=Solarflare SFC4000 support
+  DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-lib-crc32c +kmod-i2c-algo-bit
+  KCONFIG:= \
+	CONFIG_SFC_FALCON \
+	CONFIG_SFC_FALCON_MTD
+  FILES:=$(LINUX_DIR)/drivers/net/ethernet/sfc/falcon/sfc-falcon.ko
+  AUTOLOAD:=$(call AutoProbe,sfc-falcon)
+endef
+
+define KernelPackage/sfc-falcon/description
+  Solarflare SFC4000 support
+endef
+
+$(eval $(call KernelPackage,sfc-falcon))
--- a/package/kernel/linux/modules/netfilter.mk
+++ b/package/kernel/linux/modules/netfilter.mk
@ -1252,3 +1252,15 @@ define KernelPackage/nft-fib
 endef

 $(eval $(call KernelPackage,nft-fib))
+
+
+define KernelPackage/nft-queue
+  SUBMENU:=$(NF_MENU)
+  TITLE:=Netfilter nf_tables queue support
+  DEPENDS:=+kmod-nft-core +kmod-nfnetlink-queue
+  FILES:=$(foreach mod,$(NFT_QUEUE-m),$(LINUX_DIR)/net/$(mod).ko)
+  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_QUEUE-m)))
+  KCONFIG:=$(KCONFIG_NFT_QUEUE)
+endef
+
+$(eval $(call KernelPackage,nft-queue))
--- a/package/kernel/linux/modules/netsupport.mk
+++ b/package/kernel/linux/modules/netsupport.mk
@ -144,26 +144,6 @@ endef
 $(eval $(call KernelPackage,nsh))


-define KernelPackage/capi
-  SUBMENU:=$(NETWORK_SUPPORT_MENU)
-  TITLE:=CAPI (ISDN) Support
-  KCONFIG:= \
-	CONFIG_ISDN_CAPI \
-	CONFIG_ISDN_CAPI_CAPI20 \
-	CONFIG_ISDN_CAPIFS \
-	CONFIG_ISDN_CAPI_CAPIFS
-  FILES:= \
-	$(LINUX_DIR)/drivers/isdn/capi/kernelcapi.ko \
-	$(LINUX_DIR)/drivers/isdn/capi/capi.ko
-  AUTOLOAD:=$(call AutoLoad,30,kernelcapi capi)
-endef
-
-define KernelPackage/capi/description
- Kernel module for basic CAPI (ISDN) support
-endef
-
-$(eval $(call KernelPackage,capi))
-
 define KernelPackage/misdn
  SUBMENU:=$(NETWORK_SUPPORT_MENU)
  TITLE:=mISDN (ISDN) Support
--- a/package/kernel/mac80211/patches/subsys/073-backports-backport-tasklet_setup-from_tasklet.patch
+++ b/package/kernel/mac80211/patches/subsys/073-backports-backport-tasklet_setup-from_tasklet.patch
@ -0,0 +1,35 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 11 Nov 2020 13:34:26 +0100
+Subject: [PATCH] backports: backport tasklet_setup, from_tasklet
+
+Backport the new tasklet API
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/backport-include/linux/interrupt.h
+++ b/backport-include/linux/interrupt.h
+@@ -31,6 +31,23 @@ static inline void backport_hrtimer_star
+ 	hrtimer_start(timer, _time, mode);
+ }
+ #define hrtimer_start LINUX_BACKPORT(hrtimer_start)
+
+#endif
+
+#if LINUX_VERSION_IS_LESS(5,9,0)
+
+static inline void
+tasklet_setup(struct tasklet_struct *t,
+	      void (*callback)(struct tasklet_struct *))
+{
+	void (*cb)(unsigned long data) = (void *)callback;
+
+	tasklet_init(t, cb, (unsigned long)t);
+}
+
+#define from_tasklet(var, callback_tasklet, tasklet_fieldname) \
+	container_of(callback_tasklet, typeof(*var), tasklet_fieldname)
+
+ #endif
+ 
+ #endif /* _BP_LINUX_INTERRUPT_H */
--- a/package/kernel/mac80211/patches/subsys/334-mac80211-minstrel-remove-deferred-sampling-code.patch
+++ b/package/kernel/mac80211/patches/subsys/334-mac80211-minstrel-remove-deferred-sampling-code.patch
@ -0,0 +1,96 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 11 Nov 2020 19:17:44 +0100
+Subject: [PATCH] mac80211: minstrel: remove deferred sampling code
+
+Deferring sampling attempts to the second stage has some bad interactions
+with drivers that process the rate table in hardware and use the probe flag
+to indicate probing packets (e.g. most mt76 drivers). On affected drivers
+it can lead to probing not working at all.
+
+If the link conditions turn worse, it might not be such a good idea to
+do a lot of sampling for lower rates in this case.
+
+Fix this by simply skipping the sample attempt instead of deferring it,
+but keep the checks that would allow it to be sampled if it was skipped
+too often, but only if it has less than 95% success probability.
+
+Also ensure that IEEE80211_TX_CTL_RATE_CTRL_PROBE is set for all probing
+packets.
+
+Cc: stable@vger.kernel.org
+Fixes: cccf129f820e ("mac80211: add the 'minstrel' rate control algorithm")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/mac80211/rc80211_minstrel.c
+++ b/net/mac80211/rc80211_minstrel.c
+@@ -287,12 +287,6 @@ minstrel_tx_status(void *priv, struct ie
+ 			mi->r[ndx].stats.success += success;
+ 	}
+ 
+-	if ((info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) && (i >= 0))
+-		mi->sample_packets++;
+-
+-	if (mi->sample_deferred > 0)
+-		mi->sample_deferred--;
+-
+ 	if (time_after(jiffies, mi->last_stats_update +
+ 				mp->update_interval / (mp->new_avg ? 2 : 1)))
+ 		minstrel_update_stats(mp, mi);
+@@ -367,7 +361,7 @@ minstrel_get_rate(void *priv, struct iee
+ 		return;
+ 
+ 	delta = (mi->total_packets * sampling_ratio / 100) -
+-			(mi->sample_packets + mi->sample_deferred / 2);
+			mi->sample_packets;
+ 
+ 	/* delta < 0: no sampling required */
+ 	prev_sample = mi->prev_sample;
+@@ -376,7 +370,6 @@ minstrel_get_rate(void *priv, struct iee
+ 		return;
+ 
+ 	if (mi->total_packets >= 10000) {
+-		mi->sample_deferred = 0;
+ 		mi->sample_packets = 0;
+ 		mi->total_packets = 0;
+ 	} else if (delta > mi->n_rates * 2) {
+@@ -401,19 +394,8 @@ minstrel_get_rate(void *priv, struct iee
+ 	 * rate sampling method should be used.
+ 	 * Respect such rates that are not sampled for 20 interations.
+ 	 */
+-	if (mrr_capable &&
+-	    msr->perfect_tx_time > mr->perfect_tx_time &&
+-	    msr->stats.sample_skipped < 20) {
+-		/* Only use IEEE80211_TX_CTL_RATE_CTRL_PROBE to mark
+-		 * packets that have the sampling rate deferred to the
+-		 * second MRR stage. Increase the sample counter only
+-		 * if the deferred sample rate was actually used.
+-		 * Use the sample_deferred counter to make sure that
+-		 * the sampling is not done in large bursts */
+-		info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
+-		rate++;
+-		mi->sample_deferred++;
+-	} else {
+	if (msr->perfect_tx_time < mr->perfect_tx_time ||
+	    msr->stats.sample_skipped >= 20) {
+ 		if (!msr->sample_limit)
+ 			return;
+ 
+@@ -433,6 +415,7 @@ minstrel_get_rate(void *priv, struct iee
+ 
+ 	rate->idx = mi->r[ndx].rix;
+ 	rate->count = minstrel_get_retry_count(&mi->r[ndx], info);
+	info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
+ }
+ 
+ 
+--- a/net/mac80211/rc80211_minstrel.h
+++ b/net/mac80211/rc80211_minstrel.h
+@@ -126,7 +126,6 @@ struct minstrel_sta_info {
+ 	u8 max_prob_rate;
+ 	unsigned int total_packets;
+ 	unsigned int sample_packets;
+-	int sample_deferred;
+ 
+ 	unsigned int sample_row;
+ 	unsigned int sample_column;
--- a/package/kernel/mac80211/patches/subsys/335-mac80211-minstrel-fix-tx-status-processing-corner-ca.patch
+++ b/package/kernel/mac80211/patches/subsys/335-mac80211-minstrel-fix-tx-status-processing-corner-ca.patch
@ -0,0 +1,26 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 11 Nov 2020 19:25:39 +0100
+Subject: [PATCH] mac80211: minstrel: fix tx status processing corner case
+
+Some drivers fill the status rate list without setting the rate index after
+the final rate to -1. minstrel_ht already deals with this, but minstrel
+doesn't, which causes it to get stuck at the lowest rate on these drivers.
+
+Fix this by checking the count as well.
+
+Cc: stable@vger.kernel.org
+Fixes: cccf129f820e ("mac80211: add the 'minstrel' rate control algorithm")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/mac80211/rc80211_minstrel.c
+++ b/net/mac80211/rc80211_minstrel.c
+@@ -274,7 +274,7 @@ minstrel_tx_status(void *priv, struct ie
+ 	success = !!(info->flags & IEEE80211_TX_STAT_ACK);
+ 
+ 	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
+-		if (ar[i].idx < 0)
+		if (ar[i].idx < 0 || !ar[i].count)
+ 			break;
+ 
+ 		ndx = rix_to_ndx(mi, ar[i].idx);
--- a/package/libs/libnetfilter-log/Makefile
+++ b/package/libs/libnetfilter-log/Makefile
@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk

 PKG_NAME:=libnetfilter_log
 PKG_VERSION:=1.0.1
-PKG_RELEASE:=2
+PKG_RELEASE:=3

 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:= \
--- a/package/libs/libnetfilter-log/patches/0007-include-Sync-with-current-kernel-headers.patch
+++ b/package/libs/libnetfilter-log/patches/0007-include-Sync-with-current-kernel-headers.patch
@ -0,0 +1,108 @@
+From 614d8b6cfb969c6102ef320de22b1eb199efce2a Mon Sep 17 00:00:00 2001
+From: Felix Janda <felix.janda@posteo.de>
+Date: Sat, 16 May 2015 13:37:53 +0200
+Subject: include: Sync with current kernel headers
+
+Signed-off-by: Felix Janda <felix.janda@posteo.de>
+Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
+---
+ include/libnetfilter_log/linux_nfnetlink_log.h | 51 +++++++++++++-------------
+ 1 file changed, 25 insertions(+), 26 deletions(-)
+
+diff --git a/include/libnetfilter_log/linux_nfnetlink_log.h b/include/libnetfilter_log/linux_nfnetlink_log.h
+index 4c802c8..9f38277 100644
+--- a/include/libnetfilter_log/linux_nfnetlink_log.h
+++ b/include/libnetfilter_log/linux_nfnetlink_log.h
+@@ -20,33 +20,31 @@ enum nfulnl_msg_types {
+ };
+ 
+ struct nfulnl_msg_packet_hdr {
+-	u_int16_t	hw_protocol;	/* hw protocol (network order) */
+-	u_int8_t	hook;		/* netfilter hook */
+-	u_int8_t	_pad;
+-} __attribute__ ((packed));
+	__be16		hw_protocol;	/* hw protocol (network order) */
+	__u8	hook;		/* netfilter hook */
+	__u8	_pad;
+};
+ 
+ struct nfulnl_msg_packet_hw {
+-	u_int16_t	hw_addrlen;
+-	u_int16_t	_pad;
+-	u_int8_t	hw_addr[8];
+-} __attribute__ ((packed));
+	__be16		hw_addrlen;
+	__u16	_pad;
+	__u8	hw_addr[8];
+};
+ 
+ struct nfulnl_msg_packet_timestamp {
+-	aligned_u64	sec;
+-	aligned_u64	usec;
+-} __attribute__ ((packed));
+-
+-#define NFULNL_PREFIXLEN	30	/* just like old log target */
+	__aligned_be64	sec;
+	__aligned_be64	usec;
+};
+ 
+ enum nfulnl_attr_type {
+ 	NFULA_UNSPEC,
+ 	NFULA_PACKET_HDR,
+-	NFULA_MARK,			/* u_int32_t nfmark */
+	NFULA_MARK,			/* __u32 nfmark */
+ 	NFULA_TIMESTAMP,		/* nfulnl_msg_packet_timestamp */
+-	NFULA_IFINDEX_INDEV,		/* u_int32_t ifindex */
+-	NFULA_IFINDEX_OUTDEV,		/* u_int32_t ifindex */
+-	NFULA_IFINDEX_PHYSINDEV,	/* u_int32_t ifindex */
+-	NFULA_IFINDEX_PHYSOUTDEV,	/* u_int32_t ifindex */
+	NFULA_IFINDEX_INDEV,		/* __u32 ifindex */
+	NFULA_IFINDEX_OUTDEV,		/* __u32 ifindex */
+	NFULA_IFINDEX_PHYSINDEV,	/* __u32 ifindex */
+	NFULA_IFINDEX_PHYSOUTDEV,	/* __u32 ifindex */
+ 	NFULA_HWADDR,			/* nfulnl_msg_packet_hw */
+ 	NFULA_PAYLOAD,			/* opaque data payload */
+ 	NFULA_PREFIX,			/* string prefix */
+@@ -71,23 +69,23 @@ enum nfulnl_msg_config_cmds {
+ };
+ 
+ struct nfulnl_msg_config_cmd {
+-	u_int8_t	command;	/* nfulnl_msg_config_cmds */
+	__u8	command;	/* nfulnl_msg_config_cmds */
+ } __attribute__ ((packed));
+ 
+ struct nfulnl_msg_config_mode {
+-	u_int32_t	copy_range;
+-	u_int8_t	copy_mode;
+-	u_int8_t	_pad;
+	__be32		copy_range;
+	__u8	copy_mode;
+	__u8	_pad;
+ } __attribute__ ((packed));
+ 
+ enum nfulnl_attr_config {
+ 	NFULA_CFG_UNSPEC,
+ 	NFULA_CFG_CMD,			/* nfulnl_msg_config_cmd */
+ 	NFULA_CFG_MODE,			/* nfulnl_msg_config_mode */
+-	NFULA_CFG_NLBUFSIZ,		/* u_int32_t buffer size */
+-	NFULA_CFG_TIMEOUT,		/* u_int32_t in 1/100 s */
+-	NFULA_CFG_QTHRESH,		/* u_int32_t */
+-	NFULA_CFG_FLAGS,		/* u_int16_t */
+	NFULA_CFG_NLBUFSIZ,		/* __u32 buffer size */
+	NFULA_CFG_TIMEOUT,		/* __u32 in 1/100 s */
+	NFULA_CFG_QTHRESH,		/* __u32 */
+	NFULA_CFG_FLAGS,		/* __u16 */
+ 	__NFULA_CFG_MAX
+ };
+ #define NFULA_CFG_MAX (__NFULA_CFG_MAX -1)
+@@ -95,6 +93,7 @@ enum nfulnl_attr_config {
+ #define NFULNL_COPY_NONE	0x00
+ #define NFULNL_COPY_META	0x01
+ #define NFULNL_COPY_PACKET	0x02
+/* 0xff is reserved, don't use it for new copy modes. */
+ 
+ #define NFULNL_CFG_F_SEQ	0x0001
+ #define NFULNL_CFG_F_SEQ_GLOBAL	0x0002
+-- 
+2.11.0
+
--- a/package/libs/libnetfilter-log/patches/0008-include-Sync-with-current-kernel-headers.patch
+++ b/package/libs/libnetfilter-log/patches/0008-include-Sync-with-current-kernel-headers.patch
@ -0,0 +1,52 @@
+From 721ea5ec049e12afdd7c182f2899ab6d92914e68 Mon Sep 17 00:00:00 2001
+From: Ken-ichirou MATSUZAWA <chamaken@gmail.com>
+Date: Fri, 11 Sep 2015 12:12:11 +0900
+Subject: include: Sync with kernel headers
+
+Signed-off-by: Ken-ichirou MATSUZAWA <chamas@h4.dion.ne.jp>
+Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
+---
+ include/libnetfilter_log/linux_nfnetlink_log.h | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/include/libnetfilter_log/linux_nfnetlink_log.h b/include/libnetfilter_log/linux_nfnetlink_log.h
+index 9f38277..081e7f9 100644
+--- a/include/libnetfilter_log/linux_nfnetlink_log.h
+++ b/include/libnetfilter_log/linux_nfnetlink_log.h
+@@ -1,16 +1,12 @@
+ #ifndef _NFNETLINK_LOG_H
+ #define _NFNETLINK_LOG_H
+ 
+-#ifndef aligned_u64
+-#define aligned_u64 unsigned long long __attribute__((aligned(8)))
+-#endif
+-
+ /* This file describes the netlink messages (i.e. 'protocol packets'),
+  * and not any kind of function definitions.  It is shared between kernel and
+  * userspace.  Don't put kernel specific stuff in here */
+ 
+ #include <linux/types.h>
+-#include <libnfnetlink/linux_nfnetlink.h>
+#include <linux/netfilter/nfnetlink.h>
+ 
+ enum nfulnl_msg_types {
+ 	NFULNL_MSG_PACKET,		/* packet from kernel to userspace */
+@@ -55,6 +51,8 @@ enum nfulnl_attr_type {
+ 	NFULA_HWTYPE,			/* hardware type */
+ 	NFULA_HWHEADER,			/* hardware header */
+ 	NFULA_HWLEN,			/* hardware header length */
+	NFULA_CT,			/* nf_conntrack_netlink.h */
+	NFULA_CT_INFO,			/* enum ip_conntrack_info */
+ 
+ 	__NFULA_MAX
+ };
+@@ -97,5 +95,6 @@ enum nfulnl_attr_config {
+ 
+ #define NFULNL_CFG_F_SEQ	0x0001
+ #define NFULNL_CFG_F_SEQ_GLOBAL	0x0002
+#define NFULNL_CFG_F_CONNTRACK	0x0004
+ 
+ #endif /* _NFNETLINK_LOG_H */
+-- 
+2.11.0
+
--- a/package/libs/libnl-tiny/Makefile
+++ b/package/libs/libnl-tiny/Makefile
@ -12,9 +12,9 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/libnl-tiny.git
-PKG_SOURCE_DATE:=2019-10-29
-PKG_SOURCE_VERSION:=0219008cc8767655d7e747497e8e1133a3e8f840
-PKG_MIRROR_HASH:=b84fab21374c6ddbf992acc4ec1c9c6896b32af97603027ca5c866d69d95780f
+PKG_SOURCE_DATE:=2020-08-05
+PKG_SOURCE_VERSION:=c291088f631d1694f7ba0444b59677b194348da8
+PKG_MIRROR_HASH:=99bcce12701bb34dadb39689d95c2c5cf1e27719d0ecfd645d3957a8947025ac
 CMAKE_INSTALL:=1

 PKG_LICENSE:=LGPL-2.1
@ -27,6 +27,7 @@ define Package/libnl-tiny
  SECTION:=libs
  CATEGORY:=Libraries
  TITLE:=netlink socket library
+  ABI_VERSION:=1
 endef

 define Package/libnl-tiny/description
--- a/package/network/config/netifd/Makefile
+++ b/package/network/config/netifd/Makefile
@ -5,9 +5,9 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git
-PKG_SOURCE_DATE:=2020-10-22
-PKG_SOURCE_VERSION:=24ce1eab4910869576406bafd0489daf0d3e6e28
-PKG_MIRROR_HASH:=aa73b4e470e81165baba0262144f410bb05a3ff141cf72ad451914f033868ea1
+PKG_SOURCE_DATE:=2020-11-13
+PKG_SOURCE_VERSION:=4a41135750d97e06d1f6d808a9d24bb4b472aca4
+PKG_MIRROR_HASH:=2f58910f79c73209c20969ffa59ac5ccd4606f736993b207dccef6d42dab7880
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>

 PKG_LICENSE:=GPL-2.0
--- a/package/network/services/wireguard/Makefile
+++ b/package/network/services/wireguard/Makefile
@ -11,12 +11,12 @@ include $(INCLUDE_DIR)/kernel.mk

 PKG_NAME:=wireguard

-PKG_VERSION:=1.0.20200908
+PKG_VERSION:=1.0.20201112
 PKG_RELEASE:=1

 PKG_SOURCE:=wireguard-linux-compat-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://git.zx2c4.com/wireguard-linux-compat/snapshot/
-PKG_HASH:=ad33b2d2267a37e0f65c97e65e7d4d926d5aef7d530c251b63fbf919048eead9
+PKG_HASH:=89eae7f0c0bd6c8df3ba2e090984974ff68741a9f26aa0922890f8ca727897e1

 PKG_LICENSE:=GPL-2.0
 PKG_LICENSE_FILES:=COPYING
--- a/package/network/utils/layerscape/restool/Makefile
+++ b/package/network/utils/layerscape/restool/Makefile
@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk

 PKG_NAME:=restool
 PKG_VERSION:=LSDK-20.04
-PKG_RELEASE:=1
+PKG_RELEASE:=2

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/restool
@ -22,7 +22,7 @@ define Package/restool
  SECTION:=net
  CATEGORY:=Network
  TITLE:=Layerscape DPAA2 dynamical management tool
-  DEPENDS:=@TARGET_layerscape
+  DEPENDS:=@TARGET_layerscape_armv8_64b
 endef

 MAKE_FLAGS += \
--- a/package/system/ca-certificates/Makefile
+++ b/package/system/ca-certificates/Makefile
@ -14,7 +14,6 @@ PKG_MAINTAINER:=
 PKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=http://ftp.debian.org/debian/pool/main/c/ca-certificates
 PKG_HASH:=43766d5a436519503dfd65ab83488ae33ab4d4ca3d0993797b58c92eb9ed4e63
-PKG_BUILD_DIR:=$(BUILD_DIR)/work
 PKG_INSTALL:=1

 include $(INCLUDE_DIR)/package.mk
@ -35,6 +34,13 @@ define Package/ca-bundle
  PROVIDES:=ca-certs
 endef

+define Build/Prepare
+	$(DECOMPRESS_CMD) $(HOST_TAR) -C $(PKG_BUILD_DIR) $(TAR_OPTIONS)
+	$(Build/Patch)
+endef
+
+MAKE_PATH := work
+
 define Build/Install
 	mkdir -p \
 		$(PKG_INSTALL_DIR)/usr/sbin \
--- a/package/system/rpcd/Makefile
+++ b/package/system/rpcd/Makefile
@ -8,7 +8,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=rpcd
-PKG_RELEASE:=2
+PKG_RELEASE:=3

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/rpcd.git
--- a/package/system/rpcd/files/50-migrate-rpcd-ubus-sock.sh
+++ b/package/system/rpcd/files/50-migrate-rpcd-ubus-sock.sh
@ -1,6 +1,8 @@
 #!/bin/sh

-[ "$(uci get rpcd.@rpcd[0].socket)" = "/var/run/ubus.sock" ] && {
-	uci set rpcd.@rpcd[0].socket='/var/run/ubus/ubus.sock'
-	uci commit rpcd
-}
+[ "$(uci get rpcd.@rpcd[0].socket)" = "/var/run/ubus.sock" ] || exit 0
+
+uci set rpcd.@rpcd[0].socket='/var/run/ubus/ubus.sock'
+uci commit rpcd
+
+exit 0
--- a/package/utils/busybox/Makefile
+++ b/package/utils/busybox/Makefile
@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk

 PKG_NAME:=busybox
 PKG_VERSION:=1.31.1
-PKG_RELEASE:=5
+PKG_RELEASE:=6
 PKG_FLAGS:=essential

 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
--- a/package/utils/busybox/files/cron
+++ b/package/utils/busybox/files/cron
@ -32,6 +32,7 @@ start_service() {
 	for crontab in /etc/crontabs/*; do
 		 procd_set_param file "$crontab"
 	done
+	procd_set_param respawn
 	procd_close_instance
 }

--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
--- a/scripts/json_add_image_info.py
+++ b/scripts/json_add_image_info.py
@ -44,6 +44,7 @@ image_info = {
    "target": "{}/{}".format(getenv("TARGET"), getenv("SUBTARGET")),
    "version_code": getenv("VERSION_CODE"),
    "version_number": getenv("VERSION_NUMBER"),
+    "source_date_epoch": getenv("SOURCE_DATE_EPOCH"),
    "profiles": {
        device_id: {
            "image_prefix": getenv("IMAGE_PREFIX"),
--- a/scripts/kconfig.pl
+++ b/scripts/kconfig.pl
@ -102,8 +102,15 @@ sub config_sub($$) {
 	my $cfg1 = shift;
 	my $cfg2 = shift;
 	my %config = %{$cfg1};
-	
-	foreach my $config (keys %$cfg2) {
+	my @keys = map {
+		my $expr = $_;
+		$expr =~ /[?.*]/ ?
+			map {
+				/^$expr$/ ? $_ : ()
+			} keys %config : $expr;
+	} keys %$cfg2;
+
+	foreach my $config (@keys) {
 		delete $config{$config};
 	}
 	return \%config;
--- a/scripts/spelling.txt
+++ b/scripts/spelling.txt
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts
@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca9531_qxwlan_e600g.dtsi"
+
+/ {
+	model = "Qxwlan E600G v2 16M";
+	compatible = "qxwlan,e600g-v2-16m", "qca,qca9531";
+};
+
+&leds {
+	wlan {
+		label = "blue:wlan";
+		gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "phy0tpt";
+	};
+};
+
+&partitions {
+	partition@70000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x070000 0xf90000>;
+	};
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts
@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca9531_qxwlan_e600g.dtsi"
+
+/ {
+	model = "Qxwlan E600G v2 8M";
+	compatible = "qxwlan,e600g-v2-8m", "qca,qca9531";
+};
+
+&leds {
+	wlan {
+		label = "blue:wlan";
+		gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "phy0tpt";
+	};
+};
+
+&partitions {
+	partition@70000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x070000 0x790000>;
+	};
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca953x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	aliases {
+		label-mac-device = &eth0;
+		led-boot = &led_system;
+		led-failsafe = &led_system;
+		led-running = &led_system;
+		led-upgrade = &led_system;
+	};
+
+	keys: keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		led_system: system {
+			label = "blue:system";
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		wan {
+			label = "green:wan";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+		};
+
+		lan {
+			label = "green:lan";
+			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&spi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		partitions: partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x000000 0x040000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "u-boot-env";
+				reg = <0x040000 0x010000>;
+				read-only;
+			};
+
+			pridata: partition@50000 {
+				label = "pri-data";
+				reg = <0x050000 0x010000>;
+				read-only;
+			};
+
+			art: partition@60000 {
+				label = "art";
+				reg = <0x060000 0x010000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&swphy4>;
+
+	mtd-mac-address = <&pridata 0x400>;
+	mtd-mac-address-increment = <1>;
+};
+
+&eth1 {
+	mtd-mac-address = <&pridata 0x400>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&wmac {
+	status = "okay";
+
+	mtd-cal-data = <&art 0x1000>;
+};
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600gac-v2-16m.dts
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600gac-v2-16m.dts
@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca9531_qxwlan_e600g.dtsi"
+
+/ {
+	model = "Qxwlan E600GAC v2 16M";
+	compatible = "qxwlan,e600gac-v2-16m", "qca,qca9531";
+};
+
+&keys {
+	wps {
+		label = "wps";
+		linux,code = <KEY_WPS_BUTTON>;
+		gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+		debounce-interval = <60>;
+	};
+};
+
+&leds {
+	wlan2g {
+		label = "orange:wlan2g";
+		gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "phy1tpt";
+	};
+
+	control1 {
+		label = "green:control";
+		gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+	};
+
+	control2 {
+		label = "red:control";
+		gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+	};
+
+	control3 {
+		label = "blue:control";
+		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&partitions {
+	partition@70000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x070000 0xf90000>;
+	};
+};
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600gac-v2-8m.dts
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600gac-v2-8m.dts
@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca9531_qxwlan_e600g.dtsi"
+
+/ {
+	model = "Qxwlan E600GAC v2 8M";
+	compatible = "qxwlan,e600gac-v2-8m", "qca,qca9531";
+};
+
+&keys {
+	wps {
+		label = "wps";
+		linux,code = <KEY_WPS_BUTTON>;
+		gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+		debounce-interval = <60>;
+	};
+};
+
+&leds {
+	wlan2g {
+		label = "orange:wlan2g";
+		gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "phy1tpt";
+	};
+
+	control1 {
+		label = "green:control";
+		gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+	};
+
+	control2 {
+		label = "red:control";
+		gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+	};
+
+	control3 {
+		label = "blue:control";
+		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&partitions {
+	partition@70000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x070000 0x790000>;
+	};
+};
--- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds
+++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds
@ -195,6 +195,10 @@ etactica,eg200)
 	ucidef_set_led_oneshot "modbus" "Modbus" "red:modbus" "100" "33"
 	;;
 glinet,gl-mifi|\
+qxwlan,e600g-v2-8m|\
+qxwlan,e600g-v2-16m|\
+qxwlan,e600gac-v2-8m|\
+qxwlan,e600gac-v2-16m|\
 qxwlan,e750a-v4-8m|\
 qxwlan,e750a-v4-16m)
 	ucidef_set_led_switch "lan" "LAN" "green:lan" "switch0" "0x02"
--- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
@ -24,6 +24,8 @@ case "$FIRMWARE" in
 	devolo,magic-2-wifi|\
 	qxwlan,e1700ac-v2-8m|\
 	qxwlan,e1700ac-v2-16m|\
+	qxwlan,e600gac-v2-8m|\
+	qxwlan,e600gac-v2-16m|\
 	ubnt,unifiac-lite|\
 	ubnt,unifiac-lr|\
 	ubnt,unifiac-mesh|\
--- a/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration
+++ b/target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration
@ -24,6 +24,14 @@ qxwlan,e558-v2-16m|\
 qxwlan,e558-v2-8m)
 	migrate_leds ":qss=:sig2"
 	;;
+qxwlan,e600g-v2-16m|\
+qxwlan,e600g-v2-8m)
+	migrate_leds "blue:wan=blue:wlan"
+	;;
+qxwlan,e600gac-v2-16m|\
+qxwlan,e600gac-v2-8m)
+	migrate_leds "orange:wan=orange:wlan2g" "green:system=blue:system"
+	;;
 qxwlan,e750a-v4-16m|\
 qxwlan,e750a-v4-8m|\
 qxwlan,e750g-v8-16m|\
--- a/target/linux/ath79/image/generic.mk
+++ b/target/linux/ath79/image/generic.mk
@ -1540,6 +1540,50 @@ define Device/qxwlan_e558-v2-8m
 endef
 TARGET_DEVICES += qxwlan_e558-v2-8m

+define Device/qxwlan_e600g-v2
+  SOC := qca9531
+  DEVICE_VENDOR := Qxwlan
+  DEVICE_MODEL := E600G
+  DEVICE_PACKAGES := kmod-usb2
+  SUPPORTED_DEVICES += e600g-v2
+endef
+
+define Device/qxwlan_e600g-v2-16m
+  $(Device/qxwlan_e600g-v2)
+  DEVICE_VARIANT := v2 (16M)
+  IMAGE_SIZE := 15936k
+endef
+TARGET_DEVICES += qxwlan_e600g-v2-16m
+
+define Device/qxwlan_e600g-v2-8m
+  $(Device/qxwlan_e600g-v2)
+  DEVICE_VARIANT := v2 (8M)
+  IMAGE_SIZE := 7744k
+endef
+TARGET_DEVICES += qxwlan_e600g-v2-8m
+
+define Device/qxwlan_e600gac-v2
+  SOC := qca9531
+  DEVICE_VENDOR := Qxwlan
+  DEVICE_MODEL := E600GAC
+  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct
+  SUPPORTED_DEVICES += e600gac-v2
+endef
+
+define Device/qxwlan_e600gac-v2-16m
+  $(Device/qxwlan_e600gac-v2)
+  DEVICE_VARIANT := v2 (16M)
+  IMAGE_SIZE := 15936k
+endef
+TARGET_DEVICES += qxwlan_e600gac-v2-16m
+
+define Device/qxwlan_e600gac-v2-8m
+  $(Device/qxwlan_e600gac-v2)
+  DEVICE_VARIANT := v2 (8M)
+  IMAGE_SIZE := 7744k
+endef
+TARGET_DEVICES += qxwlan_e600gac-v2-8m
+
 define Device/qxwlan_e750a-v4
  SOC := ar9344
  DEVICE_VENDOR := Qxwlan
--- a/target/linux/generic/config-filter
+++ b/target/linux/generic/config-filter
@ -0,0 +1,7 @@
+# CONFIG_ARCH_(ENABLE|HAS|HAVE|INLINE|SUPPORTS|USE|WANT)_.* is not set
+# CONFIG_AS_.* is not set
+# CONFIG_CC_(CAN|HAS|IS|VERSION)_.* is not set
+# CONFIG_LD_.* is not set
+# CONFIG_GCC_VERSION is not set
+# CONFIG_INLINE_.* is not set
+# CONFIG_HAVE_(?!(ARCH_TIMER|TCM|SMP)).* is not set
--- a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_squashfs.c
+++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_squashfs.c
@ -36,7 +36,7 @@ mtdsplit_parse_squashfs(struct mtd_info *master,
 	if (err)
 		return err;

-	parent_mtd = mtdpart_get_master(master);
+	parent_mtd = mtd_get_master(master);
 	part_offset = mtdpart_get_offset(master);

 	part = kzalloc(sizeof(*part), GFP_KERNEL);
--- a/target/linux/generic/files/drivers/net/phy/ip17xx.c
+++ b/target/linux/generic/files/drivers/net/phy/ip17xx.c
@ -329,7 +329,7 @@ static int ip_phy_read(struct ip17xx_state *state, int port, int reg)
 {
 	int val = mdiobus_read(state->mii_bus, port, reg);
 	if (val < 0)
-		pr_warning("IP17xx: Unable to get MII register %d,%d: error %d\n", port, reg, -val);
+		pr_warn("IP17xx: Unable to get MII register %d,%d: error %d\n", port, reg, -val);
 #ifdef DUMP_MII_IO
 	else
 		pr_debug("IP17xx: Read MII(%d,%d) -> %04x\n", port, reg, val);
@ -346,7 +346,7 @@ static int ip_phy_write(struct ip17xx_state *state, int port, int reg, u16 val)
 #endif
 	err = mdiobus_write(state->mii_bus, port, reg, val);
 	if (err < 0)
-		pr_warning("IP17xx: Unable to write MII register %d,%d: error %d\n", port, reg, -err);
+		pr_warn("IP17xx: Unable to write MII register %d,%d: error %d\n", port, reg, -err);
 	return err;
 }

@ -451,7 +451,7 @@ static int get_model(struct ip17xx_state *state)
 			}
 		}
 	} else {
-		pr_warning("IP17xx: Found an unknown IC+ switch with model number %02x, revision %X.\n", model_no, rev_no);
+		pr_warn("IP17xx: Found an unknown IC+ switch with model number %02x, revision %X.\n", model_no, rev_no);
 		return -EPERM;
 	}
 	return 0;
--- a/target/linux/generic/files/drivers/platform/mikrotik/rb_hardconfig.c
+++ b/target/linux/generic/files/drivers/platform/mikrotik/rb_hardconfig.c
@ -39,7 +39,7 @@

 #include "routerboot.h"

-#define RB_HARDCONFIG_VER		"0.05"
+#define RB_HARDCONFIG_VER		"0.06"
 #define RB_HC_PR_PFX			"[rb_hardconfig] "

 /* ID values for hardware settings */
@ -76,6 +76,17 @@
 #define RB_HW_OPT_HAS_TS_FOR_ADC	BIT(22)
 #define RB_HW_OPT_HAS_PLC		BIT(29)

+/*
+ * Tag ID values for ERD data.
+ * Mikrotik used to pack all calibration data under a single tag id 0x1, but
+ * recently switched to a new scheme where each radio calibration gets a
+ * separate tag. The new scheme has tag id bit 15 always set and seems to be
+ * mutually exclusive with the old scheme.
+ */
+#define RB_WLAN_ERD_ID_SOLO		0x0001
+#define RB_WLAN_ERD_ID_MULTI_8001	0x8001
+#define RB_WLAN_ERD_ID_MULTI_8201	0x8201
+
 static struct kobject *hc_kobj;
 static u8 *hc_buf;		// ro buffer after init(): no locking required
 static size_t hc_buflen;
@ -351,10 +362,22 @@ static ssize_t hc_wlan_data_bin_read(struct file *filp, struct kobject *kobj,
 				     loff_t off, size_t count);

 static struct hc_wlan_attr {
+	const u16 erd_tag_id;
 	struct bin_attribute battr;
 	u16 pld_ofs;
 	u16 pld_len;
-} hc_wlandata_battr = {
+} hc_wd_multi_battrs[] = {
+	{
+		.erd_tag_id = RB_WLAN_ERD_ID_MULTI_8001,
+		.battr = __BIN_ATTR(data_0, S_IRUSR, hc_wlan_data_bin_read, NULL, 0),
+	}, {
+		.erd_tag_id = RB_WLAN_ERD_ID_MULTI_8201,
+		.battr = __BIN_ATTR(data_2, S_IRUSR, hc_wlan_data_bin_read, NULL, 0),
+	}
+};
+
+static struct hc_wlan_attr hc_wd_solo_battr = {
+	.erd_tag_id = RB_WLAN_ERD_ID_SOLO,
 	.battr = __BIN_ATTR(wlan_data, S_IRUSR, hc_wlan_data_bin_read, NULL, 0),
 };

@ -426,19 +449,19 @@ static struct hc_attr {
 /*
 * If the RB_ID_WLAN_DATA payload starts with RB_MAGIC_ERD, then past
 * that magic number the payload itself contains a routerboot tag node
- * locating the LZO-compressed calibration data at id 0x1.
+ * locating the LZO-compressed calibration data. So far this scheme is only
+ * known to use a single tag at id 0x1.
 */
-static int hc_wlan_data_unpack_erd(const u8 *inbuf, size_t inlen,
+static int hc_wlan_data_unpack_erd(const u16 tag_id, const u8 *inbuf, size_t inlen,
 				   void *outbuf, size_t *outlen)
 {
 	u16 lzo_ofs, lzo_len;
 	int ret;

 	/* Find embedded tag */
-	ret = routerboot_tag_find(inbuf, inlen, 0x1,	// always id 1
-				  &lzo_ofs, &lzo_len);
+	ret = routerboot_tag_find(inbuf, inlen, tag_id, &lzo_ofs, &lzo_len);
 	if (ret) {
-		pr_debug(RB_HC_PR_PFX "ERD data not found\n");
+		pr_debug(RB_HC_PR_PFX "no ERD data for id 0x%04x\n", tag_id);
 		goto fail;
 	}

@ -461,10 +484,10 @@ fail:
 * that magic number is a payload that must be appended to the hc_lzor_prefix,
 * the resulting blob is LZO-compressed. In the LZO decompression result,
 * the RB_MAGIC_ERD magic number (aligned) must be located. Following that
- * magic, there is a routerboot tag node (id 0x1) locating the RLE-encoded
+ * magic, there is one or more routerboot tag node(s) locating the RLE-encoded
 * calibration data payload.
 */
-static int hc_wlan_data_unpack_lzor(const u8 *inbuf, size_t inlen,
+static int hc_wlan_data_unpack_lzor(const u16 tag_id, const u8 *inbuf, size_t inlen,
 				    void *outbuf, size_t *outlen)
 {
 	u16 rle_ofs, rle_len;
@ -492,10 +515,8 @@ static int hc_wlan_data_unpack_lzor(const u8 *inbuf, size_t inlen,
 	if (ret) {
 		if (LZO_E_INPUT_NOT_CONSUMED == ret) {
 			/*
-			 * The tag length appears to always be aligned (probably
-			 * because it is the "root" RB_ID_WLAN_DATA tag), thus
-			 * the LZO payload may be padded, which can trigger a
-			 * spurious error which we ignore here.
+			 * The tag length is always aligned thus the LZO payload may be padded,
+			 * which can trigger a spurious error which we ignore here.
 			 */
 			pr_debug(RB_HC_PR_PFX "LZOR: LZO EOF before buffer end - this may be harmless\n");
 		} else {
@ -520,9 +541,9 @@ static int hc_wlan_data_unpack_lzor(const u8 *inbuf, size_t inlen,
 	templen -= (u8 *)needle - tempbuf;

 	/* Past magic. Look for tag node */
-	ret = routerboot_tag_find((u8 *)needle, templen, 0x1, &rle_ofs, &rle_len);
+	ret = routerboot_tag_find((u8 *)needle, templen, tag_id, &rle_ofs, &rle_len);
 	if (ret) {
-		pr_debug(RB_HC_PR_PFX "LZOR: RLE data not found\n");
+		pr_debug(RB_HC_PR_PFX "LZOR: no RLE data for id 0x%04x\n", tag_id);
 		goto fail;
 	}

@ -542,7 +563,7 @@ fail:
 	return ret;
 }

-static int hc_wlan_data_unpack(const size_t tofs, size_t tlen,
+static int hc_wlan_data_unpack(const u16 tag_id, const size_t tofs, size_t tlen,
 			       void *outbuf, size_t *outlen)
 {
 	const u8 *lbuf;
@ -562,23 +583,25 @@ static int hc_wlan_data_unpack(const size_t tofs, size_t tlen,
 		/* Skip magic */
 		lbuf += sizeof(magic);
 		tlen -= sizeof(magic);
-		ret = hc_wlan_data_unpack_lzor(lbuf, tlen, outbuf, outlen);
+		ret = hc_wlan_data_unpack_lzor(tag_id, lbuf, tlen, outbuf, outlen);
 		break;
 	case RB_MAGIC_ERD:
 		/* Skip magic */
 		lbuf += sizeof(magic);
 		tlen -= sizeof(magic);
-		ret = hc_wlan_data_unpack_erd(lbuf, tlen, outbuf, outlen);
+		ret = hc_wlan_data_unpack_erd(tag_id, lbuf, tlen, outbuf, outlen);
 		break;
 	default:
 		/*
 		 * If the RB_ID_WLAN_DATA payload doesn't start with a
 		 * magic number, the payload itself is the raw RLE-encoded
-		 * calibration data.
+		 * calibration data. Only RB_WLAN_ERD_ID_SOLO makes sense here.
 		 */
-		ret = routerboot_rle_decode(lbuf, tlen, outbuf, outlen);
-		if (ret)
-			pr_debug(RB_HC_PR_PFX "RLE decoding error (%d)\n", ret);
+		if (RB_WLAN_ERD_ID_SOLO == tag_id) {
+			ret = routerboot_rle_decode(lbuf, tlen, outbuf, outlen);
+			if (ret)
+				pr_debug(RB_HC_PR_PFX "RLE decoding error (%d)\n", ret);
+		}
 		break;
 	}

@ -633,7 +656,7 @@ static ssize_t hc_wlan_data_bin_read(struct file *filp, struct kobject *kobj,
 	if (!outbuf)
 		return -ENOMEM;

-	ret = hc_wlan_data_unpack(hc_wattr->pld_ofs, hc_wattr->pld_len, outbuf, &outlen);
+	ret = hc_wlan_data_unpack(hc_wattr->erd_tag_id, hc_wattr->pld_ofs, hc_wattr->pld_len, outbuf, &outlen);
 	if (ret) {
 		kfree(outbuf);
 		return ret;
@ -655,14 +678,17 @@ static ssize_t hc_wlan_data_bin_read(struct file *filp, struct kobject *kobj,

 int __init rb_hardconfig_init(struct kobject *rb_kobj)
 {
+	struct kobject *hc_wlan_kobj;
 	struct mtd_info *mtd;
-	size_t bytes_read, buflen;
+	size_t bytes_read, buflen, outlen;
 	const u8 *buf;
-	int i, ret;
+	void *outbuf;
+	int i, j, ret;
 	u32 magic;

 	hc_buf = NULL;
 	hc_kobj = NULL;
+	hc_wlan_kobj = NULL;

 	// TODO allow override
 	mtd = get_mtd_device_nm(RB_MTD_HARD_CONFIG);
@ -713,15 +739,62 @@ int __init rb_hardconfig_init(struct kobject *rb_kobj)
 		/* Account for skipped magic */
 		hc_attrs[i].pld_ofs += sizeof(magic);

-		/* Special case RB_ID_WLAN_DATA to prep and create the binary attribute */
+		/*
+		 * Special case RB_ID_WLAN_DATA to prep and create the binary attribute.
+		 * We first check if the data is "old style" within a single tag (or no tag at all):
+		 * If it is we publish this single blob as a binary attribute child of hc_kobj to
+		 * preserve backward compatibility.
+		 * If it isn't and instead uses multiple ERD tags, we create a subfolder and
+		 * publish the known ones there.
+		 */
 		if ((RB_ID_WLAN_DATA == hc_attrs[i].tag_id) && hc_attrs[i].pld_len) {
-			hc_wlandata_battr.pld_ofs = hc_attrs[i].pld_ofs;
-			hc_wlandata_battr.pld_len = hc_attrs[i].pld_len;
+			outlen = RB_ART_SIZE;
+			outbuf = kmalloc(outlen, GFP_KERNEL);
+			if (!outbuf) {
+				pr_warn(RB_HC_PR_PFX "Out of memory parsing WLAN tag\n");
+				continue;
+			}

-			ret = sysfs_create_bin_file(hc_kobj, &hc_wlandata_battr.battr);
-			if (ret)
-				pr_warn(RB_HC_PR_PFX "Could not create %s sysfs entry (%d)\n",
-				       hc_wlandata_battr.battr.attr.name, ret);
+			/* Test ID_SOLO first, if found: done */
+			ret = hc_wlan_data_unpack(RB_WLAN_ERD_ID_SOLO, hc_attrs[i].pld_ofs, hc_attrs[i].pld_len, outbuf, &outlen);
+			if (!ret) {
+				hc_wd_solo_battr.pld_ofs = hc_attrs[i].pld_ofs;
+				hc_wd_solo_battr.pld_len = hc_attrs[i].pld_len;
+
+				ret = sysfs_create_bin_file(hc_kobj, &hc_wd_solo_battr.battr);
+				if (ret)
+					pr_warn(RB_HC_PR_PFX "Could not create %s sysfs entry (%d)\n",
+						hc_wd_solo_battr.battr.attr.name, ret);
+			}
+			/* Otherwise, create "wlan_data" subtree and publish known data */
+			else {
+				hc_wlan_kobj = kobject_create_and_add("wlan_data", hc_kobj);
+				if (!hc_wlan_kobj) {
+					kfree(outbuf);
+					pr_warn(RB_HC_PR_PFX "Could not create wlan_data sysfs folder\n");
+					continue;
+				}
+
+				for (j = 0; j < ARRAY_SIZE(hc_wd_multi_battrs); j++) {
+					outlen = RB_ART_SIZE;
+					ret = hc_wlan_data_unpack(hc_wd_multi_battrs[j].erd_tag_id,
+								  hc_attrs[i].pld_ofs, hc_attrs[i].pld_len, outbuf, &outlen);
+					if (ret) {
+						hc_wd_multi_battrs[j].pld_ofs = hc_wd_multi_battrs[j].pld_len = 0;
+						continue;
+					}
+
+					hc_wd_multi_battrs[j].pld_ofs = hc_attrs[i].pld_ofs;
+					hc_wd_multi_battrs[j].pld_len = hc_attrs[i].pld_len;
+
+					ret = sysfs_create_bin_file(hc_wlan_kobj, &hc_wd_multi_battrs[j].battr);
+					if (ret)
+						pr_warn(RB_HC_PR_PFX "Could not create wlan_data/%s sysfs entry (%d)\n",
+							hc_wd_multi_battrs[j].battr.attr.name, ret);
+				}
+			}
+
+			kfree(outbuf);
 		}
 		/* All other tags are published via standard attributes */
 		else {
--- a/target/linux/generic/pending-5.4/404-mtd-add-more-helper-functions.patch
+++ b/target/linux/generic/pending-5.4/404-mtd-add-more-helper-functions.patch
@ -15,14 +15,14 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 }
 EXPORT_SYMBOL_GPL(mtd_is_partition);
 
-+struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd)
+struct mtd_info *mtd_get_master(const struct mtd_info *mtd)
 +{
 +	if (!mtd_is_partition(mtd))
 +		return (struct mtd_info *)mtd;
 +
 +	return mtd_to_part(mtd)->parent;
 +}
-+EXPORT_SYMBOL_GPL(mtdpart_get_master);
+EXPORT_SYMBOL_GPL(mtd_get_master);
 +
 +uint64_t mtdpart_get_offset(const struct mtd_info *mtd)
 +{
@ -69,7 +69,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 int mtd_add_partition(struct mtd_info *master, const char *name,
 		      long long offset, long long length);
 int mtd_del_partition(struct mtd_info *master, int partno);
-+struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd);
+struct mtd_info *mtd_get_master(const struct mtd_info *mtd);
 +uint64_t mtdpart_get_offset(const struct mtd_info *mtd);
 uint64_t mtd_get_device_size(const struct mtd_info *mtd);
 
--- a/target/linux/ipq40xx/patches-5.4/0001-v5.7-ARM-qcom-Add-support-for-IPQ40xx.patch
+++ b/target/linux/ipq40xx/patches-5.4/0001-v5.7-ARM-qcom-Add-support-for-IPQ40xx.patch
@ -0,0 +1,42 @@
+From f125e2d4339dda6937865f975470b29c84714c9b Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Mon, 6 Jan 2020 14:57:15 +0100
+Subject: [PATCH] ARM: qcom: Add support for IPQ40xx
+
+Add support for the Qualcomm IPQ40xx SoC in Kconfig.
+Also add its appropriate textofs.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+Tested-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ arch/arm/Makefile          | 1 +
+ arch/arm/mach-qcom/Kconfig | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
+@@ -152,6 +152,7 @@ textofs-$(CONFIG_PM_H1940)      := 0x001
+ ifeq ($(CONFIG_ARCH_SA1100),y)
+ textofs-$(CONFIG_SA1111) := 0x00208000
+ endif
+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
+ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
+ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+ textofs-$(CONFIG_ARCH_MESON) := 0x00208000
+--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
+@@ -12,6 +12,11 @@ menuconfig ARCH_QCOM
+ 
+ if ARCH_QCOM
+ 
+config ARCH_IPQ40XX
+	bool "Enable support for IPQ40XX"
+	select CLKSRC_QCOM
+	select HAVE_ARM_ARCH_TIMER
+
+ config ARCH_MSM8X60
+ 	bool "Enable support for MSM8X60"
+ 	select CLKSRC_QCOM
--- a/target/linux/ipq40xx/patches-5.4/0002-01-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch
+++ b/target/linux/ipq40xx/patches-5.4/0002-01-v5.6-regulator-add-IPQ4019-SDHCI-VQMMC-LDO-driver.patch
--- a/target/linux/ipq40xx/patches-5.4/0002-02-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch
+++ b/target/linux/ipq40xx/patches-5.4/0002-02-v5.5-ARM-dts-qcom-ipq4019-Add-SDHCI-controller-node.patch
@ -15,7 +15,7 @@ Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -209,6 +209,18 @@
+@@ -206,6 +206,18 @@
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
--- a/target/linux/ipq40xx/patches-5.4/0003-v5.6-ARM-dts-qcom-Add-nodes-for-SMP-boot-in-IPQ40xx.patch
+++ b/target/linux/ipq40xx/patches-5.4/0003-v5.6-ARM-dts-qcom-Add-nodes-for-SMP-boot-in-IPQ40xx.patch
@ -0,0 +1,71 @@
+From 5e4548922009870a38bcf1d887317676d4e08f54 Mon Sep 17 00:00:00 2001
+From: Damir Franusic <damir.franusic@sartura.hr>
+Date: Thu, 21 Nov 2019 16:29:02 +0100
+Subject: [PATCH] ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx
+
+Add missing nodes and properties to enable SMP
+support on IPQ40xx devices.
+
+Booting without "saw_l2" node:
+
+[    0.001400] CPU: Testing write buffer coherency: ok
+[    0.001856] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
+[    0.060163] Setting up static identity map for 0x80300000 - 0x80300060
+[    0.080140] rcu: Hierarchical SRCU implementation.
+[    0.120258] smp: Bringing up secondary CPUs ...
+[    0.200540] CPU1: failed to boot: -19
+[    0.280689] CPU2: failed to boot: -19
+[    0.360874] CPU3: failed to boot: -19
+[    0.360966] smp: Brought up 1 node, 1 CPU
+[    0.360979] SMP: Total of 1 processors activated (96.00 BogoMIPS).
+[    0.360988] CPU: All CPU(s) started in SVC mode.
+
+Then, booting with "saw_l2" node present (this patch applied):
+
+[    0.001450] CPU: Testing write buffer coherency: ok
+[    0.001904] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
+[    0.060161] Setting up static identity map for 0x80300000 - 0x80300060
+[    0.080137] rcu: Hierarchical SRCU implementation.
+[    0.120252] smp: Bringing up secondary CPUs ...
+[    0.200958] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
+[    0.281091] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
+[    0.361264] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
+[    0.361430] smp: Brought up 1 node, 4 CPUs
+[    0.361460] SMP: Total of 4 processors activated (384.00 BogoMIPS).
+[    0.361469] CPU: All CPU(s) started in SVC mode.
+
+Signed-off-by: Damir Franusic <damir.franusic@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Cc: Robert Marko <robert.marko@sartura.hr>
+Cc: Andy Gross <agross@kernel.org>
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: linux-arm-msm@vger.kernel.org
+Link: https://lore.kernel.org/r/20191121152902.21394-1-damir.franusic@gmail.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -102,6 +102,7 @@
+ 		L2: l2-cache {
+ 			compatible = "cache";
+ 			cache-level = <2>;
+			qcom,saw = <&saw_l2>;
+ 		};
+ 	};
+ 
+@@ -353,6 +354,12 @@
+ 			regulator;
+ 		};
+ 
+		saw_l2: regulator@b012000 {
+			compatible = "qcom,saw2";
+			reg = <0xb012000 0x1000>;
+			regulator;
+		};
+
+ 		blsp1_uart1: serial@78af000 {
+ 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ 			reg = <0x78af000 0x200>;
--- a/target/linux/ipq40xx/patches-5.4/0003-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch
+++ b/target/linux/ipq40xx/patches-5.4/0003-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch
@ -0,0 +1,119 @@
+From 8b99dc0922618062a1589ebd74df6108b4f9ac22 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Wed, 8 Jan 2020 13:54:55 +0100
+Subject: [PATCH] ARM: dts: qcom: add gpio-ranges property
+
+This patch adds the gpio-ranges property to almost all of
+the Qualcomm ARM platforms that utilize the pinctrl-msm
+framework.
+
+The gpio-ranges property is part of the gpiolib subsystem.
+As a result, the binding text is available in section
+"2.1 gpio- and pin-controller interaction" of
+Documentation/devicetree/bindings/gpio/gpio.txt
+
+For more information please see the patch titled:
+"pinctrl: msm: fix gpio-hog related boot issues" from
+this series.
+
+Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
+Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Tested-by: Robert Marko <robert.marko@sartura.hr> [ipq4019]
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Link: https://lore.kernel.org/r/20200108125455.308969-1-robert.marko@sartura.hr
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ arch/arm/boot/dts/qcom-apq8064.dtsi | 1 +
+ arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 +
+ arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
+ arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
+ arch/arm/boot/dts/qcom-msm8960.dtsi | 1 +
+ arch/arm/boot/dts/qcom-msm8974.dtsi | 1 +
+ 8 files changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
+@@ -350,6 +350,7 @@
+ 			reg = <0x800000 0x4000>;
+ 
+ 			gpio-controller;
+			gpio-ranges = <&tlmm_pinmux 0 0 90>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
+@@ -401,6 +401,7 @@
+ 			compatible = "qcom,apq8084-pinctrl";
+ 			reg = <0xfd510000 0x4000>;
+ 			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 147>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -201,6 +201,7 @@
+ 			compatible = "qcom,ipq4019-pinctrl";
+ 			reg = <0x01000000 0x300000>;
+ 			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 100>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -119,6 +119,7 @@
+ 			reg = <0x800000 0x4000>;
+ 
+ 			gpio-controller;
+			gpio-ranges = <&qcom_pinmux 0 0 69>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
+@@ -128,6 +128,7 @@
+ 		msmgpio: pinctrl@800000 {
+ 			compatible = "qcom,mdm9615-pinctrl";
+ 			gpio-controller;
+			gpio-ranges = <&msmgpio 0 0 88>;
+ 			#gpio-cells = <2>;
+ 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-controller;
+--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
+@@ -115,6 +115,7 @@
+ 			reg = <0x800000 0x4000>;
+ 
+ 			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 173>;
+ 			#gpio-cells = <2>;
+ 			interrupts = <0 16 0x4>;
+ 			interrupt-controller;
+--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
+@@ -107,6 +107,7 @@
+ 		msmgpio: pinctrl@800000 {
+ 			compatible = "qcom,msm8960-pinctrl";
+ 			gpio-controller;
+			gpio-ranges = <&msmgpio 0 0 152>;
+ 			#gpio-cells = <2>;
+ 			interrupts = <0 16 0x4>;
+ 			interrupt-controller;
+--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
+@@ -707,6 +707,7 @@
+ 			compatible = "qcom,msm8974-pinctrl";
+ 			reg = <0xfd510000 0x4000>;
+ 			gpio-controller;
+			gpio-ranges = <&msmgpio 0 0 146>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
--- a/target/linux/ipq40xx/patches-5.4/0004-v5.8-ARM-dts-qcom-ipq4019-fix-high-resolution-timer.patch
+++ b/target/linux/ipq40xx/patches-5.4/0004-v5.8-ARM-dts-qcom-ipq4019-fix-high-resolution-timer.patch
@ -1,7 +1,7 @@
-From 09f145f417a5d64d6b8d4476699dfb0eccc6c784 Mon Sep 17 00:00:00 2001
+From 8acc36189dcaf4487d8c6ba7445948f39b1d248a Mon Sep 17 00:00:00 2001
 From: Abhishek Sahu <absahu@codeaurora.org>
-Date: Tue, 7 May 2019 10:14:05 +0300
-Subject: [PATCH] ipq40xx: fix high resolution timer
+Date: Fri, 3 Apr 2020 13:40:40 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: fix high resolution timer

 Cherry-picked from CAF QSDK repo.
 Original commit message:
@ -10,9 +10,13 @@ mode and clock source operates in 10ms resolution. The always-on
 property needs to be given for timer device tree node to make
 clock source working in 1ns resolution.

-Change-Id: I7c00b3c74d97c2a30ac9f05e18b511a0550fd459
 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
 Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Tested-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Link: https://lore.kernel.org/r/20200403114040.349787-1-robert.marko@sartura.hr
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 ---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
 1 file changed, 1 insertion(+)
--- a/target/linux/ipq40xx/patches-5.4/0005-v5.8-02-ARM-dts-qcom-ipq4019-add-MDIO-node.patch
+++ b/target/linux/ipq40xx/patches-5.4/0005-v5.8-02-ARM-dts-qcom-ipq4019-add-MDIO-node.patch
@ -0,0 +1,57 @@
+From 9c8c0f70ec6fdac2398632c723c48277be09b7c0 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Thu, 30 Apr 2020 11:07:07 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add MDIO node
+
+This patch adds the necessary MDIO interface node
+to the Qualcomm IPQ4019 DTSI.
+
+Built-in QCA8337N switch is managed using it,
+and since we have a driver for it lets add it.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -577,5 +577,33 @@
+ 					  "legacy";
+ 			status = "disabled";
+ 		};
+
+		mdio: mdio@90000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,ipq4019-mdio";
+			reg = <0x90000 0x64>;
+			status = "disabled";
+
+			ethphy0: ethernet-phy@0 {
+				reg = <0>;
+			};
+
+			ethphy1: ethernet-phy@1 {
+				reg = <1>;
+			};
+
+			ethphy2: ethernet-phy@2 {
+				reg = <2>;
+			};
+
+			ethphy3: ethernet-phy@3 {
+				reg = <3>;
+			};
+
+			ethphy4: ethernet-phy@4 {
+				reg = <4>;
+			};
+		};
+ 	};
+ };
--- a/target/linux/ipq40xx/patches-5.4/0006-v5.5-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch
+++ b/target/linux/ipq40xx/patches-5.4/0006-v5.5-crypto-qce-add-CRYPTO_ALG_KERN_DRIVER_ONLY-flag.patch
--- a/target/linux/ipq40xx/patches-5.4/0007-v5.5-crypto-qce-switch-to-skcipher-API.patch
+++ b/target/linux/ipq40xx/patches-5.4/0007-v5.5-crypto-qce-switch-to-skcipher-API.patch
--- a/target/linux/ipq40xx/patches-5.4/0008-v5.6-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch
+++ b/target/linux/ipq40xx/patches-5.4/0008-v5.6-crypto-qce-fix-ctr-aes-qce-block-chunk-sizes.patch
--- a/target/linux/ipq40xx/patches-5.4/0009-v5.6-crypto-qce-fix-xts-aes-qce-key-sizes.patch
+++ b/target/linux/ipq40xx/patches-5.4/0009-v5.6-crypto-qce-fix-xts-aes-qce-key-sizes.patch
--- a/target/linux/ipq40xx/patches-5.4/0010-v5.6-crypto-qce-save-a-sg-table-slot-for-result-buf.patch
+++ b/target/linux/ipq40xx/patches-5.4/0010-v5.6-crypto-qce-save-a-sg-table-slot-for-result-buf.patch
--- a/target/linux/ipq40xx/patches-5.4/0011-v5.6-crypto-qce-update-the-skcipher-IV.patch
+++ b/target/linux/ipq40xx/patches-5.4/0011-v5.6-crypto-qce-update-the-skcipher-IV.patch
--- a/target/linux/ipq40xx/patches-5.4/0012-v5.6-crypto-qce-initialize-fallback-only-for-AES.patch
+++ b/target/linux/ipq40xx/patches-5.4/0012-v5.6-crypto-qce-initialize-fallback-only-for-AES.patch
--- a/target/linux/ipq40xx/patches-5.4/0013-v5.6-crypto-qce-allow-building-only-hashes-ciphers.patch
+++ b/target/linux/ipq40xx/patches-5.4/0013-v5.6-crypto-qce-allow-building-only-hashes-ciphers.patch
@ -94,8 +94,8 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
 +
 +endchoice
 
- config CRYPTO_DEV_QCE_SW_MAX_LEN
- 	int "Default maximum request size to use software for AES"
+ config CRYPTO_DEV_QCOM_RNG
+ 	tristate "Qualcomm Random Number Generator Driver"
 --- a/drivers/crypto/qce/Makefile
 +++ b/drivers/crypto/qce/Makefile
@@ -2,6 +2,7 @@
@ -111,7 +111,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
 +qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o
 --- a/drivers/crypto/qce/common.c
 +++ b/drivers/crypto/qce/common.c
-@@ -43,52 +43,56 @@ qce_clear_array(struct qce_device *qce,
+@@ -45,52 +45,56 @@ qce_clear_array(struct qce_device *qce,
 		qce_write(qce, offset + i * sizeof(u32), 0);
 }
 
@ -204,7 +204,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
 static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
 {
 	u32 cfg = 0;
-@@ -135,88 +139,6 @@ static u32 qce_auth_cfg(unsigned long fl
+@@ -137,88 +141,6 @@ static u32 qce_auth_cfg(unsigned long fl
 	return cfg;
 }
 
@ -293,7 +293,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
 static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
 				u32 totallen, u32 offset)
 {
-@@ -301,6 +223,87 @@ go_proc:
+@@ -303,6 +225,87 @@ go_proc:
 
 	return 0;
 }
@ -381,7 +381,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
 
 static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
 				     u32 totallen, u32 offset)
-@@ -382,15 +385,20 @@ static int qce_setup_regs_skcipher(struc
+@@ -384,15 +387,20 @@ static int qce_setup_regs_skcipher(struc
 
 	return 0;
 }
--- a/target/linux/ipq40xx/patches-5.4/0014-v5.7-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch
+++ b/target/linux/ipq40xx/patches-5.4/0014-v5.7-crypto-qce-use-cryptlen-when-adding-extra-sgl.patch
--- a/target/linux/ipq40xx/patches-5.4/0015-v5.7-crypto-qce-use-AES-fallback-for-small-requests.patch
+++ b/target/linux/ipq40xx/patches-5.4/0015-v5.7-crypto-qce-use-AES-fallback-for-small-requests.patch
@ -28,9 +28,9 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

 --- a/drivers/crypto/Kconfig
 +++ b/drivers/crypto/Kconfig
-@@ -628,6 +628,29 @@ config CRYPTO_DEV_QCE
- 	  hardware. To compile this driver as a module, choose M here. The
- 	  module will be called qcrypto.
+@@ -683,6 +683,29 @@ choice
+ 
+ endchoice
 
 +config CRYPTO_DEV_QCE_SW_MAX_LEN
 +	int "Default maximum request size to use software for AES"
--- a/target/linux/ipq40xx/patches-5.4/0016-v5.7-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch
+++ b/target/linux/ipq40xx/patches-5.4/0016-v5.7-crypto-qce-handle-AES-XTS-cases-that-qce-fails.patch
--- a/target/linux/ipq40xx/patches-5.4/0017-v5.8-phy-add-driver-for-Qualcomm-IPQ40xx-USB-PHY.patch
+++ b/target/linux/ipq40xx/patches-5.4/0017-v5.8-phy-add-driver-for-Qualcomm-IPQ40xx-USB-PHY.patch
@ -1,18 +1,21 @@
-From 633f0e08498aebfdb932bd71319b4cb136709499 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 24 Jul 2018 14:45:49 +0200
-Subject: [PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019
+From 3c9d8f6c03a2cda1849ec3c84f82ec030d1f49ef Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Sun, 3 May 2020 22:18:22 +0200
+Subject: [PATCH] phy: add driver for Qualcomm IPQ40xx USB PHY

-Add a driver to setup the USB phy on Qualcom Dakota SoCs.
-The driver sets up HS and SS phys. In case of HS some magic values need to
-be written to magic offsets. These were taken from the SDK driver.
+Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs.
+The driver sets up HS and SS phys.

 Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Link: https://lore.kernel.org/r/20200503201823.531757-1-robert.marko@sartura.hr
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
 ---
- drivers/phy/qualcomm/Kconfig                |   7 ++
+ drivers/phy/qualcomm/Kconfig                |   7 +
 drivers/phy/qualcomm/Makefile               |   1 +
- drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 188 ++++++++++++++++++++++++++++
- 3 files changed, 196 insertions(+)
+ drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 148 ++++++++++++++++++++
+ 3 files changed, 156 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c

 --- a/drivers/phy/qualcomm/Kconfig
@ -22,33 +25,35 @@ Signed-off-by: John Crispin <john@phrozen.org>
 	select GENERIC_PHY
 
 +config PHY_QCOM_IPQ4019_USB
-+	tristate "Qualcomm IPQ4019 USB PHY module"
-+	depends on OF && ARCH_QCOM
+	tristate "Qualcomm IPQ4019 USB PHY driver"
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
 +	select GENERIC_PHY
 +	help
-+	  Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
+	  Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
 +
 config PHY_QCOM_IPQ806X_SATA
 	tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
 	depends on ARCH_QCOM
+--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_PHY_ATH79_USB)		+= phy-ath79-usb.o
+ obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB)	+= phy-qcom-ipq4019-usb.o
+ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
+ obj-$(CONFIG_PHY_QCOM_PCIE2)		+= phy-qcom-pcie2.o
+ obj-$(CONFIG_PHY_QCOM_QMP)		+= phy-qcom-qmp.o
 --- /dev/null
 +++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
-@@ -0,0 +1,188 @@
+@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 +/*
 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
 + *
 + * Based on code from
 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 + *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
 + */
 +
 +#include <linux/delay.h>
@ -58,29 +63,11 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +#include <linux/module.h>
 +#include <linux/mutex.h>
 +#include <linux/of_platform.h>
+#include <linux/of_device.h>
 +#include <linux/phy/phy.h>
 +#include <linux/platform_device.h>
 +#include <linux/reset.h>
 +
-+/*
-+ * Magic registers copied from the SDK driver code
-+ */
-+#define PHY_CTRL0_ADDR	0x000
-+#define PHY_CTRL1_ADDR	0x004
-+#define PHY_CTRL2_ADDR	0x008
-+#define PHY_CTRL3_ADDR	0x00C
-+#define PHY_CTRL4_ADDR	0x010
-+#define PHY_MISC_ADDR	0x024
-+#define PHY_IPG_ADDR	0x030
-+
-+#define PHY_CTRL0_VAL	0xA4600015
-+#define PHY_CTRL1_VAL	0x09500000
-+#define PHY_CTRL2_VAL	0x00058180
-+#define PHY_CTRL3_VAL	0x6DB6DCD6
-+#define PHY_CTRL4_VAL	0x836DB6DB
-+#define PHY_MISC_VAL	0x3803FB0C
-+#define PHY_IPG_VAL	0x47323232
-+
 +struct ipq4019_usb_phy {
 +	struct device		*dev;
 +	struct phy		*phy;
@ -137,15 +124,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +	reset_control_deassert(phy->srif_rst);
 +	msleep(10);
 +
-+	writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
-+	writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
-+	writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
-+	writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
-+	writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
-+	writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
-+	writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
-+	msleep(10);
-+
 +	reset_control_deassert(phy->por_rst);
 +
 +	return 0;
@ -169,11 +147,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +	struct resource *res;
 +	struct phy_provider *phy_provider;
 +	struct ipq4019_usb_phy *phy;
-+	const struct of_device_id *match;
-+
-+	match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev);
-+	if (!match)
-+		return -ENODEV;
 +
 +	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 +	if (!phy)
@ -198,7 +171,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +	if (IS_ERR(phy->srif_rst))
 +		return PTR_ERR(phy->srif_rst);
 +
-+	phy->phy = devm_phy_create(dev, NULL, match->data);
+	phy->phy = devm_phy_create(dev, NULL, of_device_get_match_data(dev));
 +	if (IS_ERR(phy->phy)) {
 +		dev_err(dev, "failed to create PHY\n");
 +		return PTR_ERR(phy->phy);
@ -222,13 +195,3 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver");
 +MODULE_AUTHOR("John Crispin <john@phrozen.org>");
 +MODULE_LICENSE("GPL v2");
--- a/drivers/phy/qualcomm/Makefile
-+++ b/drivers/phy/qualcomm/Makefile
-@@ -1,6 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- obj-$(CONFIG_PHY_ATH79_USB)		+= phy-ath79-usb.o
- obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
-+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB)	+= phy-qcom-ipq4019-usb.o
- obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
- obj-$(CONFIG_PHY_QCOM_PCIE2)		+= phy-qcom-pcie2.o
- obj-$(CONFIG_PHY_QCOM_QMP)		+= phy-qcom-qmp.o
--- a/target/linux/ipq40xx/patches-5.4/0018-v5.9-pinctrl-msm-open-drain.patch
+++ b/target/linux/ipq40xx/patches-5.4/0018-v5.9-pinctrl-msm-open-drain.patch
--- a/target/linux/ipq40xx/patches-5.4/0019-v5.6-mtd-spi-nor-Add-support-for-mx25r3235f.patch
+++ b/target/linux/ipq40xx/patches-5.4/0019-v5.6-mtd-spi-nor-Add-support-for-mx25r3235f.patch
@ -1,6 +1,6 @@
-From 158acdbf0336f601971637f988b57a6a67a0869b Mon Sep 17 00:00:00 2001
+From 707745e8d4e75b638b990d67950ab292b3b8ea2a Mon Sep 17 00:00:00 2001
 From: David Bauer <mail@david-bauer.net>
-Date: Sun, 15 Dec 2019 13:10:50 +0100
+Date: Mon, 16 Dec 2019 01:36:46 +0100
 Subject: [PATCH] mtd: spi-nor: Add support for mx25r3235f

 Add MTD support for the Macronix MX25R3235F SPI NOR chip from Macronix.
@ -8,7 +8,10 @@ The chip has 4MB of total capacity, divided into a total of 64 sectors,
 each 64KB sized. The chip also supports 4KB large sectors.
 Additionally, it supports dual and quad read modes.

+Functionality was verified on an HPE/Aruba AP-303 board.
+
 Signed-off-by: David Bauer <mail@david-bauer.net>
+Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
 ---
 drivers/mtd/spi-nor/spi-nor.c | 2 ++
 1 file changed, 2 insertions(+)
--- a/target/linux/ipq40xx/patches-5.4/071-02-ipq40xx-Fix-booting-secondary-cores.patch
+++ b/target/linux/ipq40xx/patches-5.4/071-02-ipq40xx-Fix-booting-secondary-cores.patch
@ -1,38 +0,0 @@
-From 8a4540321e8bcf7a5b485c332a2e78f3501c78ed Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 29 Nov 2018 22:29:36 +0100
-Subject: [PATCH] ipq40xx: Fix booting secondary cores
-
-Add the second part of old 071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
-We dont modify the patch itself as its upstream and this change is not.
-
-Originally added by Mantas Pucka Mantas Pucka <mantas@8devices.com>
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
---
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -102,6 +102,7 @@
- 		L2: l2-cache {
- 			compatible = "cache";
- 			cache-level = <2>;
-+			qcom,saw = <&saw_l2>;
- 		};
- 	};
- 
-@@ -341,6 +342,12 @@
- 			regulator;
- 		};
- 
-+		saw_l2: regulator@b012000 {
-+			compatible = "qcom,saw2";
-+			reg = <0xb012000 0x1000>;
-+			regulator;
-+		};
-+
- 		blsp1_uart1: serial@78af000 {
- 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- 			reg = <0x78af000 0x200>;
--- a/target/linux/ipq40xx/patches-5.4/074-ARM-qcom-Add-IPQ4019-SoC-support.patch
+++ b/target/linux/ipq40xx/patches-5.4/074-ARM-qcom-Add-IPQ4019-SoC-support.patch
@ -1,36 +0,0 @@
-From 89b43d59ec8c9cda588555eb1f2754dd19ef5144 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 22 Jul 2018 12:07:57 +0200
-Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support
-
-Add support for the Qualcomm Atheros IPQ4019 SoC.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Signed-off-by: John Crispin <john@phrozen.org>
---
- arch/arm/Makefile          | 1 +
- arch/arm/mach-qcom/Kconfig | 5 +++++
- 2 files changed, 6 insertions(+)
-
--- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -156,6 +156,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x0020
- textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
- textofs-$(CONFIG_ARCH_MESON) := 0x00208000
- textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
-+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
- 
- # Machine directory name.  This list is sorted alphanumerically
- # by CONFIG_* macro name.
--- a/arch/arm/mach-qcom/Kconfig
-+++ b/arch/arm/mach-qcom/Kconfig
-@@ -28,4 +28,9 @@ config ARCH_MDM9615
- 	bool "Enable support for MDM9615"
- 	select CLKSRC_QCOM
- 
-+config ARCH_IPQ40XX
-+	bool "Enable support for IPQ40XX"
-+	select CLKSRC_QCOM
-+	select HAVE_ARM_ARCH_TIMER
-+
- endif
--- a/target/linux/ipq40xx/patches-5.4/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch
+++ b/target/linux/ipq40xx/patches-5.4/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch
@ -1,38 +0,0 @@
-From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 24 Jul 2018 15:09:36 +0200
-Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document
-
-This patch adds the binding documentation for the HS/SS USB PHY found
-inside Qualcom Dakota SoCs.
-
-Signed-off-by: John Crispin <john@phrozen.org>
---
- .../bindings/phy/phy-qcom-ipq4019-usb.txt           | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
-
--- /dev/null
-+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
-@@ -0,0 +1,21 @@
-+Qualcom Dakota HS/SS USB PHY
-+
-+Required properties:
-+ - compatible: "qcom,usb-ss-ipq4019-phy",
-+	       "qcom,usb-hs-ipq4019-phy"
-+ - reg: offset and length of the registers
-+ - #phy-cells: should be 0
-+ - resets: the reset controllers as listed below
-+ - reset-names: the names of the reset controllers
-+	"por_rst" - the POR reset line for SS and HS phys
-+	"srif_rst" - the SRIF reset line for HS phys
-+Example:
-+
-+hsphy@a8000 {
-+	compatible = "qcom,usb-hs-ipq4019-phy";
-+	phy-cells = <0>;
-+	reg = <0xa8000 0x40>;
-+	resets = <&gcc USB2_HSPHY_POR_ARES>,
-+		 <&gcc USB2_HSPHY_S_ARES>;
-+	reset-names = "por_rst", "srif_rst";
-+};
--- a/target/linux/ipq40xx/patches-5.4/080-ARM-dts-qcom-add-gpio-ranges-property.patch
+++ b/target/linux/ipq40xx/patches-5.4/080-ARM-dts-qcom-add-gpio-ranges-property.patch
@ -1,70 +0,0 @@
-From patchwork Mon May 21 20:57:38 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property
-X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com>
-X-Patchwork-Id: 917856
-Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com>
-To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
- linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
-Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
- Linus Walleij <linus.walleij@linaro.org>,
- Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>,
- Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
- Andy Gross <andy.gross@linaro.org>,
- Sven Eckelmann <sven.eckelmann@openmesh.com>
-Date: Mon, 21 May 2018 22:57:38 +0200
-From: Christian Lamparter <chunkeey@gmail.com>
-List-Id: <linux-gpio.vger.kernel.org>
-
-This patch adds the gpio-ranges property to almost all of
-the Qualcomm ARM platforms that utilize the pinctrl-msm
-framework.
-
-The gpio-ranges property is part of the gpiolib subsystem.
-As a result, the binding text is available in section
-"2.1 gpio- and pin-controller interaction" of
-Documentation/devicetree/bindings/gpio/gpio.txt
-
-For more information please see the patch titled:
-"pinctrl: msm: fix gpio-hog related boot issues" from
-this series.
-
-Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
-Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
-To help with git bisect, the DT update patch has been intentionally
-placed after the "pinctrl: msm: fix gpio-hog related boot issues".
-Otherwise - if the order was reveresed - and bisect decides to split
-between these two patches, the gpiochip_add_pin_ranges() function
-will be executed twice with the same parameters for the same pinctrl.
---
- arch/arm/boot/dts/qcom-apq8064.dtsi   | 1 +
- arch/arm/boot/dts/qcom-apq8084.dtsi   | 1 +
- arch/arm/boot/dts/qcom-ipq4019.dtsi   | 1 +
- arch/arm/boot/dts/qcom-ipq8064.dtsi   | 1 +
- arch/arm/boot/dts/qcom-mdm9615.dtsi   | 1 +
- arch/arm/boot/dts/qcom-msm8660.dtsi   | 1 +
- arch/arm/boot/dts/qcom-msm8960.dtsi   | 1 +
- arch/arm/boot/dts/qcom-msm8974.dtsi   | 1 +
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
- arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 +
- arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 +
- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
- 13 files changed, 14 insertions(+), 1 deletion(-)
-
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -201,6 +201,7 @@
- 			compatible = "qcom,ipq4019-pinctrl";
- 			reg = <0x01000000 0x300000>;
- 			gpio-controller;
-+			gpio-ranges = <&tlmm 0 0 100>;
- 			#gpio-cells = <2>;
- 			interrupt-controller;
- 			#interrupt-cells = <2>;
--- a/target/linux/ipq40xx/patches-5.4/101-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch
+++ b/target/linux/ipq40xx/patches-5.4/101-arm-dts-IPQ4019-add-SDHCI-VQMMC-LDO-node.patch
--- a/target/linux/ipq40xx/patches-5.4/102-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch
+++ b/target/linux/ipq40xx/patches-5.4/102-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch
@ -1,49 +1,23 @@
-From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001
+From 193856b5fe11c50a0b6ff22457dd674c1a45fec6 Mon Sep 17 00:00:00 2001
 From: John Crispin <john@phrozen.org>
-Date: Tue, 24 Jul 2018 14:47:55 +0200
-Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes
+Date: Wed, 9 Sep 2020 18:31:03 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes

-This patch makes USB work on the Dakota EVB.
+Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.

 Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Reviewed-by: Vinod Koul <vkoul@kernel.org>
 ---
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
- arch/arm/boot/dts/qcom-ipq4019.dtsi           | 74 +++++++++++++++++++++++++++
- 2 files changed, 94 insertions(+)
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
+ 1 file changed, 74 insertions(+)

--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -109,5 +109,25 @@
- 		wifi@a800000 {
- 			status = "ok";
- 		};
-+
-+		usb3_ss_phy: ssphy@9a000 {
-+			status = "okay";
-+		};
-+
-+		usb3_hs_phy: hsphy@a6000 {
-+			status = "okay";
-+		};
-+
-+		usb3: usb3@8af8800 {
-+			status = "okay";
-+		};
-+
-+		usb2_hs_phy: hsphy@a8000 {
-+			status = "okay";
-+		};
-+
-+		usb2: usb2@60f8800 {
-+			status = "okay";
-+		};
- 	};
- };
 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -563,5 +563,79 @@
- 					  "legacy";
- 			status = "disabled";
+@@ -615,5 +615,79 @@
+ 				reg = <4>;
+ 			};
 		};
 +
 +		usb3_ss_phy: ssphy@9a000 {
@ -66,7 +40,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +			status = "disabled";
 +		};
 +
-+		usb3@8af8800 {
+		usb3: usb3@8af8800 {
 +			compatible = "qcom,dwc3";
 +			reg = <0x8af8800 0x100>;
 +			#address-cells = <1>;
@ -98,7 +72,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +			status = "disabled";
 +		};
 +
-+		usb2@60f8800 {
+		usb2: usb2@60f8800 {
 +			compatible = "qcom,dwc3";
 +			reg = <0x60f8800 0x100>;
 +			#address-cells = <1>;
--- a/target/linux/ipq40xx/patches-5.4/103-arm-dts-qcom-ipq4019-add-more-labels.patch
+++ b/target/linux/ipq40xx/patches-5.4/103-arm-dts-qcom-ipq4019-add-more-labels.patch
@ -0,0 +1,42 @@
+From caa3ee6b094ee18021943504c938919fcac325ec Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Wed, 9 Sep 2020 20:40:33 +0200
+Subject: [PATCH] arm: dts: qcom: ipq4019: add more labels
+
+Lets add labels to more commonly used nodes for easier modification in board DTS files.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -190,7 +190,7 @@
+ 			reg = <0x1800000 0x60000>;
+ 		};
+ 
+-		rng@22000 {
+		prng: rng@22000 {
+ 			compatible = "qcom,prng";
+ 			reg = <0x22000 0x140>;
+ 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+@@ -310,7 +310,7 @@
+ 			status = "disabled";
+ 		};
+ 
+-		crypto@8e3a000 {
+		crypto: crypto@8e3a000 {
+ 			compatible = "qcom,crypto-v5.1";
+ 			reg = <0x08e3a000 0x6000>;
+ 			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+@@ -396,7 +396,7 @@
+ 			dma-names = "rx", "tx";
+ 		};
+ 
+-		watchdog@b017000 {
+		watchdog: watchdog@b017000 {
+ 			compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
+ 			reg = <0xb017000 0x40>;
+ 			clocks = <&sleep_clk>;
--- a/target/linux/ipq40xx/patches-5.4/104-clk-fix-apss-cpu-overclocking.patch
+++ b/target/linux/ipq40xx/patches-5.4/104-clk-fix-apss-cpu-overclocking.patch
--- a/target/linux/ipq40xx/patches-5.4/701-dts-ipq4019-add-mdio-node.patch
+++ b/target/linux/ipq40xx/patches-5.4/701-dts-ipq4019-add-mdio-node.patch
@ -1,52 +0,0 @@
-From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 20 Nov 2016 01:10:33 +0100
-Subject: [PATCH] dts: ipq4019: add mdio node for ethernet
-
-This patch adds the mdio device-tree node.
-This is where the switch is connected to, so it's needed
-for the ethernet interfaces.
-
-Note: The driver isn't anywhere close to be upstream,
-so the info might change.
---
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -588,6 +588,34 @@
- 			status = "disabled";
- 		};
- 
-+		mdio: mdio@90000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "qcom,ipq4019-mdio";
-+			reg = <0x90000 0x64>;
-+			status = "disabled";
-+
-+			ethphy0: ethernet-phy@0 {
-+				reg = <0>;
-+			};
-+
-+			ethphy1: ethernet-phy@1 {
-+				reg = <1>;
-+			};
-+
-+			ethphy2: ethernet-phy@2 {
-+				reg = <2>;
-+			};
-+
-+			ethphy3: ethernet-phy@3 {
-+				reg = <3>;
-+			};
-+
-+			ethphy4: ethernet-phy@4 {
-+				reg = <4>;
-+			};
-+		};
-+
- 		usb3_ss_phy: ssphy@9a000 {
- 			compatible = "qcom,usb-ss-ipq4019-phy";
- 			#phy-cells = <0>;
--- a/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch
+++ b/target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch
@ -8,7 +8,7 @@
 +	tristate "Driver for Qualcomm Atheros IPQ40XX switches"
 +	depends on HAS_IOMEM && OF
 +	select SWCONFIG
-+	---help---
+	help
 +	   This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
 +
 endif # PHYLIB
--- a/target/linux/ipq40xx/patches-5.4/721-dts-ipq4019-add-ethernet-essedma-node.patch
+++ b/target/linux/ipq40xx/patches-5.4/721-dts-ipq4019-add-ethernet-essedma-node.patch
@ -1,69 +0,0 @@
-From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 20 Nov 2016 01:01:10 +0100
-Subject: [PATCH] dts: ipq4019: add ethernet ipqess node
-
-This patch adds the device-tree node for the ipqess ethernet
-interfaces.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 60 insertions(+)
-
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -699,6 +699,53 @@
- 			};
- 		};
- 
-+		gmac: ethernet@c080000 {
-+			compatible = "qcom,ipq4019-ess-edma";
-+			reg = <0xc080000 0x8000>;
-+			interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
-+
-+			status = "disabled";
-+
-+			phy-mode = "internal";
-+			fixed-link {
-+				speed = <1000>;
-+				full-duplex;
-+				pause;
-+				asym-pause;
-+			};
-+		};
-+
- 		usb3_ss_phy: ssphy@9a000 {
- 			compatible = "qcom,usb-ss-ipq4019-phy";
- 			#phy-cells = <0>;
--- a/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch
+++ b/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch
@ -56,10 +56,11 @@
 		};
 
 		serial@78af000 {
-@@ -110,6 +129,22 @@
+@@ -109,5 +128,41 @@
+ 		wifi@a800000 {
 			status = "ok";
 		};
- 
+
 +		mdio@90000 {
 +			status = "okay";
 +		};
@ -76,9 +77,27 @@
 +			status = "okay";
 +		};
 +
- 		usb3_ss_phy: ssphy@9a000 {
- 			status = "okay";
- 		};
+		usb3_ss_phy: ssphy@9a000 {
+			status = "okay";
+		};
+
+		usb3_hs_phy: hsphy@a6000 {
+			status = "okay";
+		};
+
+		usb3: usb3@8af8800 {
+			status = "okay";
+		};
+
+		usb2_hs_phy: hsphy@a8000 {
+			status = "okay";
+		};
+
+		usb2: usb2@60f8800 {
+			status = "okay";
+		};
+ 	};
+ };
 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -18,5 +18,73 @@
--- a/target/linux/ipq40xx/patches-5.4/902-dts-ipq4019-ap-dk04.1.patch
+++ b/target/linux/ipq40xx/patches-5.4/902-dts-ipq4019-ap-dk04.1.patch
@ -102,7 +102,7 @@
 			};
 		};
 
-@@ -89,23 +115,57 @@
+@@ -89,11 +115,11 @@
 			status = "ok";
 			cs-gpios = <&tlmm 12 0>;
 
@ -116,17 +116,17 @@
 				spi-max-frequency = <24000000>;
 			};
 		};
+@@ -103,9 +129,48 @@
+ 			perst-gpio = <&tlmm 38 0x1>;
+ 		};
 
-		pci@40000000 {
-			status = "ok";
-			perst-gpio = <&tlmm 38 0x1>;
 +		i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
 +			pinctrl-0 = <&i2c_0_pins>;
 +			pinctrl-names = "default";
 +
 +			status = "okay";
- 		};
- 
+		};
+
 		qpic-nand@79b0000 {
 			pinctrl-0 = <&nand_pins>;
 			pinctrl-names = "default";
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	aliases {
+		led-boot = &led_status_yellow;
+		led-failsafe = &led_status_yellow;
+		led-running = &led_status_blue;
+		led-upgrade = &led_status_yellow;
+		label-mac-device = &wan;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_blue: status_blue {
+			label = "blue:status";
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+		};
+
+		led_status_yellow: status_yellow {
+			label = "yellow:status";
+			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x30000>;
+				read-only;
+			};
+
+			partition@30000 {
+				label = "u-boot-env";
+				reg = <0x30000 0x10000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "Bdata";
+				reg = <0x40000 0x10000>;
+				read-only;
+			};
+
+			factory: partition@50000 {
+				label = "factory";
+				reg = <0x50000 0x10000>;
+				read-only;
+			};
+
+			partition@60000 {
+				label = "crash";
+				reg = <0x60000 0x10000>;
+				read-only;
+			};
+
+			partition@70000 {
+				label = "cfg_bak";
+				reg = <0x70000 0x10000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "overlay";
+				reg = <0x80000 0x100000>;
+				read-only;
+			};
+
+			firmware: partition@180000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x180000 0xe80000>;
+			};
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	wifi@0,0 {
+		compatible = "pci14c3,7662";
+		reg = <0x0000 0 0 0 0>;
+		mediatek,mtd-eeprom = <&factory 0x8000>;
+		ieee80211-freq-limit = <5000000 6000000>;
+	};
+};
+
+&pcie1 {
+	wifi@0,0 {
+		compatible = "pci14c3,7603";
+		reg = <0x0000 0 0 0 0>;
+		mediatek,mtd-eeprom = <&factory 0x0000>;
+		ieee80211-freq-limit = <2400000 2500000>;
+	};
+};
+
+&gmac0 {
+	mtd-mac-address = <&factory 0xe000>;
+};
+
+&switch0 {
+	ports {
+		port@2 {
+			status = "okay";
+			label = "lan2";
+		};
+
+		port@3 {
+			status = "okay";
+			label = "lan1";
+		};
+
+		wan: port@4 {
+			status = "okay";
+			label = "wan";
+			mtd-mac-address = <&factory 0xe006>;
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "jtag", "uart2", "uart3", "wdt";
+		function = "gpio";
+	};
+};
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-gigabit.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-gigabit.dts
@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_xiaomi_mi-router-4a-3g-v2.dtsi"
+
+/ {
+	compatible = "xiaomi,mi-router-4a-gigabit", "mediatek,mt7621-soc";
+	model = "Xiaomi Mi Router 4A Gigabit Edition";
+};
--- a/target/linux/ramips/dts/mt7621_xiaomi_mir3g-v2.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mir3g-v2.dts
@ -1,163 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT

-#include "mt7621.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "mt7621_xiaomi_mi-router-4a-3g-v2.dtsi"

 / {
 	compatible = "xiaomi,mir3g-v2", "mediatek,mt7621-soc";
 	model = "Xiaomi Mi Router 3G v2";
-
-	aliases {
-		led-boot = &led_status_yellow;
-		led-failsafe = &led_status_yellow;
-		led-running = &led_status_blue;
-		led-upgrade = &led_status_yellow;
-		label-mac-device = &wan;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status_blue: status_blue {
-			label = "blue:status";
-			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
-		};
-
-		led_status_yellow: status_yellow {
-			label = "yellow:status";
-			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <80000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x0 0x30000>;
-				read-only;
-			};
-
-			partition@30000 {
-				label = "u-boot-env";
-				reg = <0x30000 0x10000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "Bdata";
-				reg = <0x40000 0x10000>;
-				read-only;
-			};
-
-			factory: partition@50000 {
-				label = "factory";
-				reg = <0x50000 0x10000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "crash";
-				reg = <0x60000 0x10000>;
-				read-only;
-			};
-
-			partition@70000 {
-				label = "cfg_bak";
-				reg = <0x70000 0x10000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "overlay";
-				reg = <0x80000 0x100000>;
-				read-only;
-			};
-
-			firmware: partition@180000 {
-				compatible = "denx,uimage";
-				label = "firmware";
-				reg = <0x180000 0xe80000>;
-			};
-		};
-	};
-};
-
-&pcie {
-	status = "okay";
-};
-
-&pcie0 {
-	wifi@0,0 {
-		compatible = "pci14c3,7662";
-		reg = <0x0000 0 0 0 0>;
-		mediatek,mtd-eeprom = <&factory 0x8000>;
-		ieee80211-freq-limit = <5000000 6000000>;
-	};
-};
-
-&pcie1 {
-	wifi@0,0 {
-		compatible = "pci14c3,7603";
-		reg = <0x0000 0 0 0 0>;
-		mediatek,mtd-eeprom = <&factory 0x0000>;
-		ieee80211-freq-limit = <2400000 2500000>;
-	};
-};
-
-&gmac0 {
-	mtd-mac-address = <&factory 0xe000>;
-};
-
-&switch0 {
-	ports {
-		port@2 {
-			status = "okay";
-			label = "lan2";
-		};
-
-		port@3 {
-			status = "okay";
-			label = "lan1";
-		};
-		wan: port@4 {
-			status = "okay";
-			label = "wan";
-			mtd-mac-address = <&factory 0xe006>;
-		};
-	};
-};
-
-&state_default {
-	gpio {
-		groups = "jtag", "uart2", "uart3", "wdt";
-		function = "gpio";
-	};
 };
--- a/target/linux/ramips/image/mt7621.mk
+++ b/target/linux/ramips/image/mt7621.mk
@ -1225,9 +1225,6 @@ define Device/xiaomi_mir3g-v2
  DEVICE_VENDOR := Xiaomi
  DEVICE_MODEL := Mi Router 3G
  DEVICE_VARIANT := v2
-  DEVICE_ALT0_VENDOR := Xiaomi
-  DEVICE_ALT0_MODEL := Mi Router 4A
-  DEVICE_ALT0_VARIANT := Gigabit Edition
  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2
 endef
 TARGET_DEVICES += xiaomi_mir3g-v2
@ -1251,6 +1248,17 @@ define Device/xiaomi_mir3p
 endef
 TARGET_DEVICES += xiaomi_mir3p

+define Device/xiaomi_mi-router-4a-gigabit
+  $(Device/dsa-migration)
+  $(Device/uimage-lzma-loader)
+  IMAGE_SIZE := 14848k
+  DEVICE_VENDOR := Xiaomi
+  DEVICE_MODEL := Mi Router 4A
+  DEVICE_VARIANT := Gigabit Edition
+  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2
+endef
+TARGET_DEVICES += xiaomi_mi-router-4a-gigabit
+
 define Device/xiaomi_redmi-router-ac2100
  $(Device/xiaomi-ac2100)
  DEVICE_MODEL := Redmi Router AC2100
--- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network
+++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network
@ -17,7 +17,8 @@ ramips_setup_interfaces()
 	lenovo,newifi-d1|\
 	mikrotik,routerboard-m33g|\
 	xiaomi,mir3g|\
-	xiaomi,mir3g-v2)
+	xiaomi,mir3g-v2|\
+	xiaomi,mi-router-4a-gigabit)
 		ucidef_set_interfaces_lan_wan "lan1 lan2" "wan"
 		;;
 	edimax,re23s|\
--- a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h
+++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h
@ -429,6 +429,9 @@ struct rtl838x_soc_info {
 	volatile void *icu_base;
 };

+extern struct rtl838x_soc_info soc_info;
+extern struct mutex smi_lock;
+
 void rtl838x_soc_detect(struct rtl838x_soc_info *i);

 #endif   /* _MACH_RTL838X_H_ */
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c
@ -20,8 +20,6 @@
 #include <asm/mipsregs.h>
 #include <mach-rtl838x.h>

-extern struct rtl838x_soc_info soc_info;
-
 #define icu_r32(reg)			rtl838x_r32(soc_info.icu_base + reg)
 #define icu_w32(val, reg)		rtl838x_w32(val, soc_info.icu_base + reg)
 #define icu_w32_mask(clear, set, reg)	rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c
@ -24,7 +24,6 @@
 extern char arcs_cmdline[];
 const void *fdt;
 extern const char __appended_dtb;
-//extern int __init rtl838x_serial_init(void);

 void prom_console_init(void)
 {
@ -67,8 +66,6 @@ char prom_getchar(void)
 }
 #endif

-struct rtl838x_soc_info soc_info;
-
 const char *get_system_type(void)
 {
 	return soc_info.name;
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c
@ -24,7 +24,6 @@
 #include <asm/mach-rtl838x/mach-rtl838x.h>

 extern char arcs_cmdline[];
-extern struct rtl838x_soc_info soc_info;

 int __init rtl838x_serial_init(void)
 {
--- a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c
+++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c
@ -28,7 +28,7 @@
 #include "mach-rtl838x.h"

 extern int rtl838x_serial_init(void);
-extern struct rtl838x_soc_info soc_info;
+struct rtl838x_soc_info soc_info;

 struct clk {
 	struct clk_lookup cl;
--- a/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c
+++ b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c
@ -38,8 +38,6 @@ struct rtl838x_gpios {
 	int i2c_sdc;
 };

-extern struct mutex smi_lock;
-
 u32 rtl838x_rtl8231_read(u8 bus_id, u32 reg)
 {
 	u32 t = 0;
--- a/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
+++ b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
@ -15,8 +15,6 @@
 #include "rtl838x-spi.h"
 #include <asm/mach-rtl838x/mach-rtl838x.h>

-extern struct rtl838x_soc_info soc_info;
-
 struct rtl838x_nor {
 	struct spi_nor nor;
 	struct device *dev;
--- a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h
+++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h
@ -54,20 +54,34 @@
 #define MAPLE_SDS4_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x880)
 #define MAPLE_SDS5_FIB_REG0r			(RTL838X_SDS4_REG28 + 0x980)

+/* Registers of the internal Serdes of the 8390 */
+#define RTL8390_SDS0_1_XSG0			(0xA000)
+#define RTL8390_SDS0_1_XSG1			(0xA100)
+#define RTL839X_SDS12_13_XSG0			(0xB800)
+#define RTL839X_SDS12_13_XSG1			(0xB900)
+#define RTL839X_SDS12_13_PWR0			(0xb880)
+#define RTL839X_SDS12_13_PWR1			(0xb980)
+
 /* VLAN registers */
-#define RTL838X_VLAN_PROFILE(idx)		(0x3A88 + ((idx) << 2))
+#define RTL838X_VLAN_PROFILE			(0x3A88)
 #define RTL838X_VLAN_PORT_EGR_FLTR		(0x3A84)
-#define RTL838X_VLAN_PORT_PB_VLAN(port)		(0x3C00 + ((port) << 2))
+#define RTL838X_VLAN_PORT_PB_VLAN		(0x3C00)
+#define RTL838X_VLAN_PORT_IGR_FLTR		(0x3A7C)
 #define RTL838X_VLAN_PORT_IGR_FLTR_0		(0x3A7C)
-#define RTL838X_VLAN_PORT_IGR_FLTR_1		(0x3A7C + 4)
+#define RTL838X_VLAN_PORT_IGR_FLTR_1		(0x3A80)
+#define RTL839X_VLAN_PROFILE			(0x25C0)
+#define RTL839X_VLAN_CTRL			(0x26D4)
+#define RTL839X_VLAN_PORT_PB_VLAN		(0x26D8)
+#define RTL839X_VLAN_PORT_IGR_FLTR		(0x27B4)
+#define RTL839X_VLAN_PORT_EGR_FLTR		(0x27C4)

 /* Table 0/1 access registers */
 #define RTL838X_TBL_ACCESS_CTRL_0		(0x6914)
-#define RTL838X_TBL_ACCESS_DATA_0(idx)		(0x6918 + ((idx) << 2))
+#define RTL838X_TBL_ACCESS_DATA_0		(0x6918)
 #define RTL838X_TBL_ACCESS_CTRL_1		(0xA4C8)
 #define RTL838X_TBL_ACCESS_DATA_1(idx)		(0xA4CC + ((idx) << 2))
 #define RTL839X_TBL_ACCESS_CTRL_0		(0x1190)
-#define RTL839X_TBL_ACCESS_DATA_0(idx)		(0x1194 + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_DATA_0		(0x1194)
 #define RTL839X_TBL_ACCESS_CTRL_1		(0x6b80)
 #define RTL839X_TBL_ACCESS_DATA_1(idx)		(0x6b84 + ((idx) << 2))

@ -75,12 +89,18 @@
 #define RTL838X_MAC_LINK_STS			(0xa188)
 #define RTL839X_MAC_LINK_STS			(0x0390)
 #define RTL838X_MAC_LINK_SPD_STS(port)		(0xa190 + (((port >> 4) << 2)))
+#define RTL839X_MAC_LINK_SPD_STS(port)		(0x03a0 + (((port >> 4) << 2)))
 #define RTL838X_MAC_LINK_DUP_STS		(0xa19c)
+#define RTL839X_MAC_LINK_DUP_STS		(0x03b0)
 #define RTL838X_MAC_TX_PAUSE_STS		(0xa1a0)
+#define RTL839X_MAC_TX_PAUSE_STS		(0x03b8)
 #define RTL838X_MAC_RX_PAUSE_STS		(0xa1a4)
+#define RTL839X_MAC_RX_PAUSE_STS		(0x03c0)
 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL		(0xaa04)
 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL	(0xaa08)

+#define RTL838X_DMA_IF_CTRL			(0x9f58)
+
 /* MAC link state bits */
 #define FORCE_EN				(1 << 0)
 #define FORCE_LINK_EN				(1 << 1)
@ -105,21 +125,31 @@
 #define RTL838X_TBL_ACCESS_L2_CTRL		(0x6900)
 #define RTL839X_TBL_ACCESS_L2_CTRL		(0x1180)
 #define RTL838X_TBL_ACCESS_L2_DATA(idx)		(0x6908 + ((idx) << 2))
-#define RTL838X_TBL_ACCESS_L2_DATA(idx)		(0x6908 + ((idx) << 2))
+#define RTL839X_TBL_ACCESS_L2_DATA(idx)		(0x1184 + ((idx) << 2))
 #define RTL838X_L2_TBL_FLUSH_CTRL		(0x3370)
 #define RTL839X_L2_TBL_FLUSH_CTRL		(0x3ba0)
+#define RTL838X_L2_PORT_NEW_SALRN(p)		(0x328c + (((p >> 4) << 2)))
+#define RTL839X_L2_PORT_NEW_SALRN(p)		(0x38F0 + (((p >> 4) << 2)))
+#define RTL838X_L2_PORT_NEW_SA_FWD(p)		(0x3294 + (((p >> 4) << 2)))
+#define RTL839X_L2_PORT_NEW_SA_FWD(p)		(0x3900 + (((p >> 4) << 2)))
+#define RTL838X_L2_PORT_SALRN(p)		(0x328c + (((p >> 4) << 2)))
+#define RTL839X_L2_PORT_SALRN(p)		(0x38F0 + (((p >> 4) << 2)))

 /* Port Mirroring */
 #define RTL838X_MIR_CTRL(grp)			(0x5D00 + (((grp) << 2)))
 #define RTL838X_MIR_DPM_CTRL(grp)		(0x5D20 + (((grp) << 2)))
 #define RTL838X_MIR_SPM_CTRL(grp)		(0x5D10 + (((grp) << 2)))
+#define RTL839X_MIR_CTRL(grp)			(0x2500 + (((grp) << 2)))
+#define RTL839X_MIR_DPM_CTRL(grp)		(0x2530 + (((grp) << 2)))
+#define RTL839X_MIR_SPM_CTRL(grp)		(0x2510 + (((grp) << 2)))

 enum phy_type {
 	PHY_NONE = 0,
 	PHY_RTL838X_SDS = 1,
 	PHY_RTL8218B_INT = 2,
 	PHY_RTL8218B_EXT = 3,
-	PHY_RTL8214FC = 4
+	PHY_RTL8214FC = 4,
+	PHY_RTL839X_SDS = 5,
 };

 struct rtl838x_port {
@ -133,20 +163,51 @@ struct rtl838x_port {
 struct rtl838x_vlan_info {
 	u64 untagged_ports;
 	u64 tagged_ports;
-	u32 vlan_conf;
+	u8 profile_id;
+	bool hash_mc;
+	bool hash_uc;
+	u8 fid;
+};
+
+enum l2_entry_type {
+	L2_INVALID = 0,
+	L2_UNICAST = 1,
+	L2_MULTICAST = 2,
+	IP4_MULTICAST = 3,
+	IP6_MULTICAST = 4,
+};
+
+struct rtl838x_l2_entry {
+	u8 mac[ETH_ALEN];
+	u16 vid;
+	u16 rvid;
+	u8 port;
+	bool valid;
+	enum l2_entry_type type;
+	bool is_static;
+	bool is_ip_mc;
+	bool is_ipv6_mc;
+	bool block_da;
+	bool block_sa;
+	bool suspended;
+	bool next_hop;
+	int age;
+	u16 mc_portmask_index;
 };

 struct rtl838x_switch_priv;

 struct rtl838x_reg {
-	void (*mask_port_reg)(u64 clear, u64 set, int reg);
-	void (*set_port_reg)(u64 set, int reg);
-	u64 (*get_port_reg)(int reg);
+	void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
+	void (*set_port_reg_be)(u64 set, int reg);
+	u64 (*get_port_reg_be)(int reg);
+	void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
+	void (*set_port_reg_le)(u64 set, int reg);
+	u64 (*get_port_reg_le)(int reg);
 	int stat_port_rst;
 	int stat_rst;
 	int (*stat_port_std_mib)(int p);
-	void (*mask_port_iso_ctrl)(u64 clear, u64 set, int port);
-	void (*set_port_iso_ctrl)(u64 set, int port);
+	int (*port_iso_ctrl)(int p);
 	int l2_ctrl_0;
 	int l2_ctrl_1;
 	int l2_port_aging_out;
@ -160,10 +221,26 @@ struct rtl838x_reg {
 	int imr_port_link_sts_chg;
 	int imr_glb;
 	void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
-	void (*vlan_set_tagged)(u32 vlan, u64 portmask, u32 conf);
+	void (*vlan_set_tagged)(u32 vlan, const struct rtl838x_vlan_info *info);
 	void (*vlan_set_untagged)(u32 vlan, u64 portmask);
 	int  (*mac_force_mode_ctrl)(int port);
-	int rst_glb_ctrl;
+	int  (*mac_port_ctrl)(int port);
+	int  (*l2_port_new_salrn)(int port);
+	int  (*l2_port_new_sa_fwd)(int port);
+	int  (*mir_ctrl)(int group);
+	int  (*mir_dpm)(int group);
+	int  (*mir_spm)(int group);
+	int mac_link_sts;
+	int mac_link_dup_sts;
+	int  (*mac_link_spd_sts)(int port);
+	int mac_rx_pause_sts;
+	int mac_tx_pause_sts;
+	u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
+	u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
+	int (*vlan_profile)(int profile);
+	int (*vlan_port_egr_filter)(int port);
+	int (*vlan_port_igr_filter)(int port);
+	int (*vlan_port_pb)(int port);
 };

 struct rtl838x_switch_priv {
@ -181,6 +258,7 @@ struct rtl838x_switch_priv {
 	const struct rtl838x_reg *r;
 	u8 cpu_port;
 	u8 port_mask;
+	u32 fib_entries;
 };

 extern struct rtl838x_soc_info soc_info;
--- a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c
+++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c
--- a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c
@ -17,12 +17,12 @@
 #include <linux/module.h>
 #include <linux/phylink.h>
 #include <net/dsa.h>
+#include <net/switchdev.h>
+#include <asm/cacheflush.h>

 #include <asm/mach-rtl838x/mach-rtl838x.h>
 #include "rtl838x_eth.h"

-extern struct rtl838x_soc_info soc_info;
-
 /*
 * Maximum number of RX rings is 8, assigned by switch based on
 * packet/port priortity (not implemented)
@ -30,10 +30,12 @@ extern struct rtl838x_soc_info soc_info;
 * RX ringlength needs to be at least 200, otherwise CPU and Switch
 * may gridlock.
 */
-#define RXRINGS		2
+#define RXRINGS		8
 #define RXRINGLEN	300
 #define TXRINGS		2
 #define TXRINGLEN	160
+#define NOTIFY_EVENTS	10
+#define NOTIFY_BLOCKS	10
 #define TX_EN		0x8
 #define RX_EN		0x4
 #define TX_DO		0x2
@ -51,6 +53,15 @@ struct p_hdr {
 	uint16_t	cpu_tag[5];
 } __packed __aligned(1);

+struct n_event {
+	uint32_t	type:2;
+	uint32_t	fidVid:12;
+	uint64_t	mac:48;
+	uint32_t	slp:6;
+	uint32_t	valid:1;
+	uint32_t	reserved:27;
+} __packed __aligned(1);
+
 struct ring_b {
 	uint32_t	rx_r[RXRINGS][RXRINGLEN];
 	uint32_t	tx_r[TXRINGS][TXRINGLEN];
@ -62,6 +73,53 @@ struct ring_b {
 	uint8_t		tx_space[TXRINGLEN*RING_BUFFER];
 };

+struct notify_block {
+	struct n_event	events[NOTIFY_EVENTS];
+};
+
+struct notify_b {
+	struct notify_block	blocks[NOTIFY_BLOCKS];
+	u32			reserved1[8];
+	u32			ring[NOTIFY_BLOCKS];
+	u32			reserved2[8];
+};
+
+inline void rtl838x_create_tx_header(struct p_hdr *h, int dest_port)
+{
+	if (dest_port > 0) {
+		h->cpu_tag[0] = 0x0400;
+		h->cpu_tag[1] = 0x0200;
+		h->cpu_tag[2] = 0x0000;
+		h->cpu_tag[3] = (1 << dest_port) >> 16;
+		h->cpu_tag[4] = (1 << dest_port) & 0xffff;
+	} else {
+		h->cpu_tag[0] = 0;
+		h->cpu_tag[1] = 0;
+		h->cpu_tag[2] = 0;
+		h->cpu_tag[3] = 0;
+		h->cpu_tag[4] = 0;
+	}
+}
+
+inline void rtl839x_create_tx_header(struct p_hdr *h, int dest_port)
+{
+	if (dest_port > 0) {
+		h->cpu_tag[0] = 0x0100;
+		h->cpu_tag[1] = ((1 << (dest_port - 32)) >> 16) | (1 << 21);
+		h->cpu_tag[2] = (1 << (dest_port - 32)) & 0xffff;
+		h->cpu_tag[3] = (1 << dest_port) >> 16;
+		h->cpu_tag[4] = (1 << dest_port) & 0xffff;
+	} else {
+		h->cpu_tag[0] = 0;
+		h->cpu_tag[1] = 0;
+		h->cpu_tag[2] = 0;
+		h->cpu_tag[3] = 0;
+		h->cpu_tag[4] = 0;
+	}
+}
+
+extern void rtl838x_fdb_sync(struct work_struct *work);
+
 struct rtl838x_eth_priv {
 	struct net_device *netdev;
 	struct platform_device *pdev;
@ -75,6 +133,8 @@ struct rtl838x_eth_priv {
 	u16 family_id;
 	const struct rtl838x_reg *r;
 	u8 cpu_port;
+	u8 port_mask;
+	u32 lastEvent;
 };

 static const struct rtl838x_reg rtl838x_reg = {
@ -119,6 +179,11 @@ static const struct rtl838x_reg rtl839x_reg = {
 	.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
 };

+extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
+extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
+extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
+extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
+
 /*
 * Discard the RX ring-buffers, called as part of the net-ISR
 * when the buffer runs over
@ -137,20 +202,64 @@ static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv)
 			if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
 				break;
 			h = &ring->rx_header[r][ring->c_rx[r]];
-			h->buf = (u8 *)CPHYSADDR(ring->rx_space
+			h->buf = (u8 *)KSEG1ADDR(ring->rx_space
 					+ r * ring->c_rx[r] * RING_BUFFER);
 			h->size = RING_BUFFER;
 			h->len = 0;
 			/* make sure the header is visible to the ASIC */
 			mb();

-			ring->rx_r[r][ring->c_rx[r]] = CPHYSADDR(h) | 0x1
-				| (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1);
+			ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
+				| (ring->c_rx[r] == (RXRINGLEN - 1) ? WRAP : 0x1);
 			ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN;
 		} while (&ring->rx_r[r][ring->c_rx[r]] != last);
 	}
 }

+struct fdb_update_work {
+	struct work_struct work;
+	struct net_device *ndev;
+	u64 macs[NOTIFY_EVENTS + 1];
+};
+
+static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
+{
+	struct notify_b *nb = priv->membase + sizeof(struct ring_b);
+	u32 e = priv->lastEvent;
+	struct n_event *event;
+	int i;
+	u64 mac;
+	struct fdb_update_work *w;
+
+	while (!(nb->ring[e] & 1)) {
+		w = kzalloc(sizeof(*w), GFP_ATOMIC);
+		if (!w) {
+			pr_err("Out of memory: %s", __func__);
+			return;
+		}
+		INIT_WORK(&w->work, rtl838x_fdb_sync);
+
+		for (i = 0; i < NOTIFY_EVENTS; i++) {
+			event = &nb->blocks[e].events[i];
+			if (!event->valid)
+				continue;
+			mac = event->mac;
+			if (event->type)
+				mac |= 1ULL << 63;
+			w->ndev = priv->netdev;
+			w->macs[i] = mac;
+		}
+
+		/* Hand the ring entry back to the switch */
+		nb->ring[e] = nb->ring[e] | 1;
+		e = (e + 1) % NOTIFY_BLOCKS;
+
+		w->macs[i] = 0ULL;
+		schedule_work(&w->work);
+	}
+	priv->lastEvent = e;
+}
+
 static irqreturn_t rtl838x_net_irq(int irq, void *dev_id)
 {
 	struct net_device *dev = dev_id;
@ -174,36 +283,69 @@ static irqreturn_t rtl838x_net_irq(int irq, void *dev_id)

 	/* RX buffer overrun */
 	if (status & 0x000ff) {
+		pr_debug("RX buffer overrun: status %x, mask: %x\n",
+			 status, sw_r32(priv->r->dma_if_intr_msk));
 		sw_w32(0x000000ff, priv->r->dma_if_intr_sts);
 		rtl838x_rb_cleanup(priv);
 	}

+	if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
+		sw_w32(0x00700000, priv->r->dma_if_intr_sts);
+		rtl839x_l2_notification_handler(priv);
+	}
+
 	spin_unlock(&priv->lock);
 	return IRQ_HANDLED;
 }

 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
 {
-	u32 int_saved;
+	u32 int_saved, nbuf;

 	pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
 	/* Stop TX/RX */
-	sw_w32(0x0, priv->r->mac_port_ctrl(priv->cpu_port));
+	sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
 	mdelay(500);

-	int_saved = sw_r32(priv->r->dma_if_intr_msk);
-	/* Reset NIC */
+	if (priv->family_id == RTL8390_FAMILY_ID) {
+		/* Preserve L2 notification and NBUF settings */
+		int_saved = sw_r32(priv->r->dma_if_intr_msk);
+		nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
+
+		/* Disable link change interrupt on RTL839x */
+		sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
+		sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
+
+		sw_w32(0x00000000, priv->r->dma_if_intr_msk);
+		sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
+	}
+
+	/* Reset NIC and Queue */
 	sw_w32(0x08, priv->r->rst_glb_ctrl);
-	do {
+	if (priv->family_id == RTL8390_FAMILY_ID)
+		sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
+	do { /* Reset NIC */
 		udelay(20);
 	} while (sw_r32(priv->r->rst_glb_ctrl) & 0x08);
+	do { /* Reset Queues */
+		udelay(20);
+	} while (sw_r32(priv->r->rst_glb_ctrl) & 0x04);
 	mdelay(100);

-	/* Restore notification settings: on RTL838x these bits are null */
-	sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
+	/* Re-enable link change interrupt */
+	if (priv->family_id == RTL8390_FAMILY_ID) {
+		sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
+		sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
+		sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
+		sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
+
+		/* Restore notification settings: on RTL838x these bits are null */
+		sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
+		sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
+	}

 	/* Restart TX/RX to CPU port */
-	sw_w32(0x03, priv->r->mac_port_ctrl(priv->cpu_port));
+	sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));

 	if (priv->family_id == RTL8380_FAMILY_ID) {
 		/* Set Speed, duplex, flow control
@ -215,6 +357,11 @@ static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
 		/* allow CRC errors on CPU-port */
 		sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(priv->cpu_port));
 	} else {
+		/* CPU port joins Lookup Miss Flooding Portmask */
+		sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
+		sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
+		sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
+
 		/* Force CPU port link up */
 		sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
 	}
@ -230,17 +377,14 @@ static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
 	struct ring_b *ring = priv->membase;

 	for (i = 0; i < RXRINGS; i++)
-		sw_w32(CPHYSADDR(&ring->rx_r[i]), priv->r->dma_rx_base(i));
+		sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base(i));

 	for (i = 0; i < TXRINGS; i++)
-		sw_w32(CPHYSADDR(&ring->tx_r[i]), priv->r->dma_tx_base(i));
+		sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base(i));
 }

 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
 {
-	u32 v;
-
-	pr_info("%s\n", __func__);
 	/* Disable Head of Line features for all RX rings */
 	sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));

@ -252,19 +396,18 @@ static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)

 	/* Enable traffic, engine expects empty FCS field */
 	sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
+}

-	/* Make sure to flood all traffic to CPU_PORT */
-	if (priv->family_id == RTL8390_FAMILY_ID) {
-		/* CPU port joins Lookup Miss Flooding Portmask */
-		/* Table access: CMD: read, table = 2 */
-		/* Sets MC_PMSK table port bit for port 52 to 1 */
-		sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
-		do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
-		v = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
-		sw_w32(v | 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
-		sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
-		do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
-	}
+static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
+{
+	/* Setup CPU-Port: RX Buffer */
+	sw_w32(0x0000c808, priv->r->dma_if_ctrl);
+
+	/* Enable Notify, RX done, RX overflow and TX done interrupts */
+	sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
+
+	/* Enable traffic */
+	sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
 }

 static void rtl838x_setup_ring_buffer(struct ring_b *ring)
@ -276,13 +419,14 @@ static void rtl838x_setup_ring_buffer(struct ring_b *ring)
 	for (i = 0; i < RXRINGS; i++) {
 		for (j = 0; j < RXRINGLEN; j++) {
 			h = &ring->rx_header[i][j];
-			h->buf = (u8 *)CPHYSADDR(ring->rx_space + i * j * RING_BUFFER);
+			h->buf = (u8 *)KSEG1ADDR(ring->rx_space + i * j * RING_BUFFER);
 			h->reserved = 0;
 			h->size = RING_BUFFER;
 			h->offset = 0;
 			h->len = 0;
+			memset(&h->cpu_tag, 0, sizeof(uint16_t[5]));
 			/* All rings owned by switch, last one wraps */
-			ring->rx_r[i][j] = CPHYSADDR(h) | 1 | (j == (RXRINGLEN - 1) ? WRAP : 0);
+			ring->rx_r[i][j] = KSEG1ADDR(h) | 1 | (j == (RXRINGLEN - 1) ? WRAP : 0);
 		}
 		ring->c_rx[i] = 0;
 	}
@ -290,19 +434,40 @@ static void rtl838x_setup_ring_buffer(struct ring_b *ring)
 	for (i = 0; i < TXRINGS; i++) {
 		for (j = 0; j < TXRINGLEN; j++) {
 			h = &ring->tx_header[i][j];
-			h->buf = (u8 *)CPHYSADDR(ring->tx_space + i * j * RING_BUFFER);
+			h->buf = (u8 *)KSEG1ADDR(ring->tx_space + i * j * RING_BUFFER);
 			h->reserved = 0;
 			h->size = RING_BUFFER;
 			h->offset = 0;
 			h->len = 0;
-			ring->tx_r[i][j] = CPHYSADDR(&ring->tx_header[i][j]);
+			memset(&h->cpu_tag, 0, sizeof(uint16_t[5]));
+			ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
 		}
 		/* Last header is wrapping around */
-		ring->tx_r[i][j-1] |= 2;
+		ring->tx_r[i][j-1] |= WRAP;
 		ring->c_tx[i] = 0;
 	}
 }

+static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
+{
+	int i;
+	struct notify_b *b = priv->membase + sizeof(struct ring_b);
+
+	for (i = 0; i < NOTIFY_BLOCKS; i++)
+		b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
+
+	sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
+	sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
+
+	/* Setup notification events */
+	sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
+	sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
+
+	/* Enable Notification */
+	sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
+	priv->lastEvent = 0;
+}
+
 static int rtl838x_eth_open(struct net_device *ndev)
 {
 	unsigned long flags;
@ -310,10 +475,18 @@ static int rtl838x_eth_open(struct net_device *ndev)
 	struct ring_b *ring = priv->membase;
 	int err;

-	pr_info("%s called %x, ring %x\n", __func__, (uint32_t)priv, (uint32_t)ring);
+	pr_info("%s called: RX rings %d, TX rings %d\n", __func__, RXRINGS, TXRINGS);
+
 	spin_lock_irqsave(&priv->lock, flags);
 	rtl838x_hw_reset(priv);
 	rtl838x_setup_ring_buffer(ring);
+	if (priv->family_id == RTL8390_FAMILY_ID) {
+		rtl839x_setup_notify_ring_buffer(priv);
+		/* Make sure the ring structure is visible to the ASIC */
+		mb();
+		flush_cache_all();
+	}
+
 	rtl838x_hw_ring_setup(priv);
 	err = request_irq(ndev->irq, rtl838x_net_irq, IRQF_SHARED,
 			ndev->name, ndev);
@ -327,7 +500,17 @@ static int rtl838x_eth_open(struct net_device *ndev)
 	napi_enable(&priv->napi);
 	netif_start_queue(ndev);

-	rtl838x_hw_en_rxtx(priv);
+	if (priv->family_id == RTL8380_FAMILY_ID) {
+		rtl838x_hw_en_rxtx(priv);
+		/* Trap IGMP traffic to CPU-Port */
+		sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
+		/* Flush learned FDB entries on link down of a port */
+		sw_w32_mask(0, 1 << 7, RTL838X_L2_CTRL_0);
+	} else {
+		rtl839x_hw_en_rxtx(priv);
+		sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
+		sw_w32_mask(0, 1 << 7, RTL839X_L2_CTRL_0);
+	}

 	spin_unlock_irqrestore(&priv->lock, flags);

@ -336,6 +519,8 @@ static int rtl838x_eth_open(struct net_device *ndev)

 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
 {
+	u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192D : 0x75;
+	u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
 	int i;

 	/* Block all ports */
@ -358,17 +543,19 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
 		}
 	}

-	/* CPU-Port: Link down BUG: Works only for RTL838x */
-	sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port));
+	/* CPU-Port: Link down */
+	sw_w32(force_mac, priv->r->mac_force_mode_ctrl(priv->cpu_port));
 	mdelay(100);

 	/* Disable traffic */
 	sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
-	mdelay(200);
+	mdelay(200); // Test, whether this is needed

 	/* Disable all TX/RX interrupts */
 	sw_w32(0x00000000, priv->r->dma_if_intr_msk);
-	sw_w32(0x000fffff, priv->r->dma_if_intr_sts);
+	sw_w32(clear_irq, priv->r->dma_if_intr_sts);
+
+	/* Disable TX/RX DMA */
 	sw_w32(0x00000000, priv->r->dma_if_ctrl);
 	mdelay(200);
 }
@ -387,12 +574,48 @@ static int rtl838x_eth_stop(struct net_device *ndev)
 	napi_disable(&priv->napi);
 	netif_stop_queue(ndev);
 	spin_unlock_irqrestore(&priv->lock, flags);
+
 	return 0;
 }

-static void rtl838x_eth_set_multicast_list(struct net_device *dev)
+static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
 {
+	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
+		sw_w32(0x0, RTL839X_RMA_CTRL_0);
+		sw_w32(0x0, RTL839X_RMA_CTRL_1);
+		sw_w32(0x0, RTL839X_RMA_CTRL_2);
+		sw_w32(0x0, RTL839X_RMA_CTRL_3);
+	}
+	if (ndev->flags & IFF_ALLMULTI) {
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
+	}
+	if (ndev->flags & IFF_PROMISC) {
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
+		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
+		sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
+	}
+}

+static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
+{
+	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
+
+	if (priv->family_id == RTL8390_FAMILY_ID)
+		return rtl839x_eth_set_multicast_list(ndev);
+
+	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
+		sw_w32(0x0, RTL838X_RMA_CTRL_0);
+		sw_w32(0x0, RTL838X_RMA_CTRL_1);
+	}
+	if (ndev->flags & IFF_ALLMULTI)
+		sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
+	if (ndev->flags & IFF_PROMISC) {
+		sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
+		sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
+	}
 }

 static void rtl838x_eth_tx_timeout(struct net_device *ndev)
@ -448,34 +671,27 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
 		/* Set descriptor for tx */
 		h = &ring->tx_header[0][ring->c_tx[0]];

-		h->buf = (u8 *)CPHYSADDR(ring->tx_space);
+		h->buf = (u8 *)KSEG1ADDR(ring->tx_space);
 		h->size = len;
 		h->len = len;

 		/* Create cpu_tag */
-		if (dest_port > 0) {
-			h->cpu_tag[0] = 0x0400;
-			h->cpu_tag[1] = 0x0200;
-			h->cpu_tag[2] = 0x0000;
-			h->cpu_tag[3] = (1 << dest_port) >> 16;
-			h->cpu_tag[4] = (1 << dest_port) & 0xffff;
-		} else {
-			h->cpu_tag[0] = 0;
-			h->cpu_tag[1] = 0;
-			h->cpu_tag[2] = 0;
-			h->cpu_tag[3] = 0;
-			h->cpu_tag[4] = 0;
-		}
+		if (priv->family_id == RTL8380_FAMILY_ID)
+			rtl838x_create_tx_header(h, dest_port);
+		else
+			rtl839x_create_tx_header(h, dest_port);

 		/* Copy packet data to tx buffer */
 		memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
 		/* Make sure packet data is visible to ASIC */
-		mb();
+		mb(); /* wmb() probably works, too */

 		/* Hand over to switch */
 		ring->tx_r[0][ring->c_tx[0]] = ring->tx_r[0][ring->c_tx[0]] | 0x1;

-		/* BUG: before tx fetch, need to make sure right data is accessed */
+		/* BUG: before tx fetch, need to make sure right data is accessed
+		 * This might not be necessary on newer RTL839x, though.
+		 */
 		for (i = 0; i < 10; i++) {
 			val = sw_r32(priv->r->dma_if_ctrl);
 			if ((val & 0xc) == 0xc)
@ -534,10 +750,6 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)

 		if (!len)
 			break;
-		h->buf = (u8 *)CPHYSADDR(ring->rx_space
-				+ r * ring->c_rx[r] * RING_BUFFER);
-		h->size = RING_BUFFER;
-		h->len = 0;
 		work_done++;

 		len -= 4; /* strip the CRC */
@ -549,12 +761,14 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
 		skb_reserve(skb, NET_IP_ALIGN);

 		if (likely(skb)) {
-			/* BUG: Prevent ASIC bug */
-			sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
-			for (i = 0; i < RXRINGS; i++) {
-				/* Update each ring cnt */
-				val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
-				sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
+			/* BUG: Prevent bug on RTL838x SoCs*/
+			if (priv->family_id == RTL8380_FAMILY_ID) {
+				sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
+				for (i = 0; i < RXRINGS; i++) {
+					/* Update each ring cnt */
+					val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
+					sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
+				}
 			}

 			skb_data = skb_put(skb, len);
@ -564,7 +778,7 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
 			/* Overwrite CRC with cpu_tag */
 			if (dsa) {
 				skb->data[len-4] = 0x80;
-				skb->data[len-3] = h->cpu_tag[0] & 0x1f;
+				skb->data[len-3] = h->cpu_tag[0] & priv->port_mask;
 				skb->data[len-2] = 0x10;
 				skb->data[len-1] = 0x00;
 			}
@ -579,8 +793,15 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
 				dev_warn(&dev->dev, "low on memory - packet dropped\n");
 			dev->stats.rx_dropped++;
 		}
+
+		h->buf = (u8 *)KSEG1ADDR(ring->rx_space
+				+ r * ring->c_rx[r] * RING_BUFFER);
+		h->size = RING_BUFFER;
+		h->len = 0;
+		memset(&h->cpu_tag, 0, sizeof(uint16_t[5]));
+
 		ring->rx_r[r][ring->c_rx[r]]
-			= CPHYSADDR(h) | 0x1 | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1);
+			= KSEG1ADDR(h) | 0x1 | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1);
 		ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN;
 	} while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);

@ -601,7 +822,7 @@ static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
 	if (work_done < budget) {
 		napi_complete_done(napi, work_done);
 		/* Enable RX interrupt */
-		sw_w32(0xfffff, priv->r->dma_if_intr_msk);
+		sw_w32_mask(0, 0xfffff, priv->r->dma_if_intr_msk);
 	}
 	return work_done;
 }
@ -660,7 +881,7 @@ static void rtl838x_mac_config(struct phylink_config *config,
 			       const struct phylink_link_state *state)
 {
 	/* This is only being called for the master device,
-	 * i.e. the CPU-Port
+	 * i.e. the CPU-Port. We don't need to do anything.
 	 */

 	pr_info("In %s, mode %x\n", __func__, mode);
@ -671,6 +892,10 @@ static void rtl838x_mac_an_restart(struct phylink_config *config)
 	struct net_device *dev = container_of(config->dev, struct net_device, dev);
 	struct rtl838x_eth_priv *priv = netdev_priv(dev);

+	/* This works only on RTL838x chips */
+	if (priv->family_id != RTL8380_FAMILY_ID)
+		return;
+
 	pr_info("In %s\n", __func__);
 	/* Restart by disabling and re-enabling link */
 	sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port));
@ -715,20 +940,6 @@ static int rtl838x_mac_pcs_get_state(struct phylink_config *config,
 	return 1;
 }

-static void dump_mac_conf(struct rtl838x_eth_priv *priv)
-{
-	int p;
-
-	for (p = 8; p < 16; p++) {
-		pr_debug("%d: %x, force %x\n", p, sw_r32(priv->r->mac_port_ctrl(p)),
-					     sw_r32(priv->r->mac_force_mode_ctrl(p))
-		);
-	}
-	pr_debug("CPU: %x, force %x\n", sw_r32(priv->r->mac_port_ctrl(priv->cpu_port)),
-					sw_r32(priv->r->mac_force_mode_ctrl(priv->cpu_port))
-		);
-}
-
 static void rtl838x_mac_link_down(struct phylink_config *config,
 				  unsigned int mode,
 				  phy_interface_t interface)
@ -794,14 +1005,7 @@ static int rtl838x_set_mac_address(struct net_device *dev, void *p)

 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
 {
-	pr_info("Configuring RTL8390 MAC\n");
-	// from mac_config_init
-	sw_w32(0x80,  RTL839X_MAC_EFUSE_CTRL);
-	sw_w32(0x4, RTL839X_RST_GLB_CTRL);
-	sw_w32(0x3c324f40, RTL839X_MAC_GLB_CTRL);
-	/* Unlimited egress rate */
-	sw_w32(0x1297b961, RTL839X_SCHED_LB_TICK_TKN_CTRL);
-
+	// We will need to set-up EEE and the egress-rate limitation
 	return 0;
 }

@ -812,9 +1016,6 @@ static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
 	if (priv->family_id == 0x8390)
 		return rtl8390_init_mac(priv);

-	if (priv->family_id != 0x8380)
-		return 0;
-
 	pr_info("%s\n", __func__);
 	/* fix timer for EEE */
 	sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
@ -850,20 +1051,14 @@ static int rtl838x_set_link_ksettings(struct net_device *ndev,
 	return phylink_ethtool_ksettings_set(priv->phylink, cmd);
 }

-
 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 {
 	u32 val;
-	u32 offset = 0;
 	int err;
 	struct rtl838x_eth_priv *priv = bus->priv;

-	if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
-		if (mii_id == 26)
-			offset = 0x100;
-		val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2)) & 0xffff;
-		return val;
-	}
+	if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
+		return rtl838x_read_sds_phy(mii_id, regnum);
 	err = rtl838x_read_phy(mii_id, 0, regnum, &val);
 	if (err)
 		return err;
@ -874,6 +1069,10 @@ static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 {
 	u32 val;
 	int err;
+	struct rtl838x_eth_priv *priv = bus->priv;
+
+	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+		return rtl839x_read_sds_phy(mii_id, regnum);

 	err = rtl839x_read_phy(mii_id, 0, regnum, &val);
 	if (err)
@ -899,6 +1098,11 @@ static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
 			      int regnum, u16 value)
 {
+	struct rtl838x_eth_priv *priv = bus->priv;
+
+	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+		return rtl839x_write_sds_phy(mii_id, regnum, value);
+
 	return rtl839x_write_phy(mii_id, 0, regnum, value);
 }

@ -911,18 +1115,23 @@ static int rtl838x_mdio_reset(struct mii_bus *bus)
 	/* Enable PHY control via SoC */
 	sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);

+	// Probably should reset all PHYs here...
 	return 0;
 }

 static int rtl839x_mdio_reset(struct mii_bus *bus)
 {
+	return 0;
+
 	pr_info("%s called\n", __func__);
+	/* BUG: The following does not work, but should! */
 	/* Disable MAC polling the PHY so that we can start configuration */
 	sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
 	sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
 	/* Disable PHY polling via SoC */
 	sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);

+	// Probably should reset all PHYs here...
 	return 0;
 }

@ -1057,8 +1266,8 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev)

 	/* Allocate buffer memory */
 	priv->membase = dmam_alloc_coherent(&pdev->dev,
-				sizeof(struct ring_b), (void *)&dev->mem_start,
-				GFP_KERNEL);
+				sizeof(struct ring_b) + sizeof(struct notify_b),
+				(void *)&dev->mem_start, GFP_KERNEL);
 	if (!priv->membase) {
 		dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
 		err = -ENOMEM;
@ -1090,9 +1299,11 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev)
 	if (priv->family_id == 0x8390) {
 		priv->cpu_port = RTL839X_CPU_PORT;
 		priv->r = &rtl839x_reg;
+		priv->port_mask = 0x3f;
 	} else {
 		priv->cpu_port = RTL838X_CPU_PORT;
 		priv->r = &rtl838x_reg;
+		priv->port_mask = 0x1f;
 	}

 	rtl8380_init_mac(priv);
@ -1157,6 +1368,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev)
 		goto err_free;
 	}
 	priv->phylink = phylink;
+
 	return 0;

 err_free:
--- a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h
+++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h
@ -100,6 +100,22 @@
 #define TX_PAUSE_EN				(1 << 6)
 #define RX_PAUSE_EN				(1 << 7)

+/* RTL839X L2 Notification DMA interface */
+#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL	(0x785C)
+#define RTL839X_L2_NOTIFICATION_CTRL		(0x7808)
+#define RTL838X_L2_CTRL_0			(0x3200)
+#define RTL839X_L2_CTRL_0			(0x3800)
+
+/* TRAPPING to CPU-PORT */
+#define RTL838X_SPCL_TRAP_IGMP_CTRL		(0x6984)
+#define RTL839X_SPCL_TRAP_IGMP_CTRL		(0x1058)
+#define RTL838X_RMA_CTRL_0			(0x4300)
+#define RTL838X_RMA_CTRL_1			(0x4304)
+#define RTL839X_RMA_CTRL_0			(0x1200)
+#define RTL839X_RMA_CTRL_1			(0x1204)
+#define RTL839X_RMA_CTRL_2			(0x1208)
+#define RTL839X_RMA_CTRL_3			(0x120C)
+
 inline int rtl838x_mac_port_ctrl(int p)
 {
 	return RTL838X_MAC_PORT_CTRL + (p << 7);
--- a/target/linux/sunxi/base-files/etc/board.d/01_leds
+++ b/target/linux/sunxi/base-files/etc/board.d/01_leds
@ -1,6 +1,5 @@
 #!/bin/sh

-. /lib/functions/leds.sh
 . /lib/functions/uci-defaults.sh

 board=$(board_name)
--- a/target/linux/sunxi/image/cortexa53.mk
+++ b/target/linux/sunxi/image/cortexa53.mk
@ -38,6 +38,15 @@ define Device/friendlyarm_nanopi-neo2
 endef
 TARGET_DEVICES += friendlyarm_nanopi-neo2

+define Device/libretech_all-h3-cc-h5
+  DEVICE_VENDOR := Libre Computer
+  DEVICE_MODEL := ALL-H3-CC
+  DEVICE_VARIANT := H5
+  $(Device/sun50i-h5)
+  SUNXI_DTS := $$(SUNXI_DTS_DIR)$$(SOC)-libretech-all-h3-cc
+endef
+TARGET_DEVICES += libretech_all-h3-cc-h5
+
 define Device/olimex_a64-olinuxino
  DEVICE_VENDOR := Olimex
  DEVICE_MODEL := A64-Olinuxino
--- a/target/linux/x86/generic/config-5.4
+++ b/target/linux/x86/generic/config-5.4
@ -126,7 +126,7 @@ CONFIG_EFI_RUNTIME_MAP=y
 CONFIG_EFI_RUNTIME_WRAPPERS=y
 CONFIG_EFI_STUB=y
 # CONFIG_EFI_TEST is not set
-CONFIG_EFI_VARS=y
+# CONFIG_EFI_VARS is not set
 # CONFIG_EISA is not set
 # CONFIG_EL3 is not set
 CONFIG_FAILOVER=y
--- a/toolchain/glibc/common.mk
+++ b/toolchain/glibc/common.mk
@ -12,8 +12,8 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=70ee5e8b573f76745760dd6b75f705590fc1923a
-PKG_MIRROR_HASH:=d816dc7658446c2969d307730b58df5f8a65853b4e57a655895feb685590d63b
+PKG_SOURCE_VERSION:=5c36293f067d2af16e4eb9f9465be36f346ea6d0
+PKG_MIRROR_HASH:=f01b467843af97fe29dd67d0dc52e8f2effc968258ae806af37be085239a3e4c
 PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz

--- a/tools/firmware-utils/Makefile
+++ b/tools/firmware-utils/Makefile
@ -7,7 +7,7 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME := firmware-utils
-PKG_RELEASE := 4
+PKG_RELEASE := 5

 include $(INCLUDE_DIR)/host-build.mk
 include $(INCLUDE_DIR)/kernel.mk
--- a/tools/firmware-utils/src/nec-enc.c
+++ b/tools/firmware-utils/src/nec-enc.c
@ -47,7 +47,7 @@ static unsigned char buf_pattern[4096], buf[4096];

 int main(int argc, char **argv)
 {
-	int k_off = 0, ptn = 0, c, ret = EXIT_SUCCESS;
+	int k_off = 0, ptn = 1, c, ret = EXIT_SUCCESS;
 	char *ifn = NULL, *ofn = NULL, *key = NULL;
 	size_t n, k_len;
 	FILE *out, *in;
@ -99,11 +99,11 @@ int main(int argc, char **argv)

 	while ((n = fread(buf, 1, sizeof(buf), in)) > 0) {
 		for (int i = 0; i < n; i++) {
-			buf_pattern[i] = ptn + 1;
+			buf_pattern[i] = ptn;
 			ptn++;

-			if (ptn > 250)
-				ptn = 0;
+			if (ptn > PATTERN_LEN)
+				ptn = 1;
 		}

 		k_off = xor_pattern(buf_pattern, n, key, k_len, k_off);