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rtl8192du: bump to latest git HEAD

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CN_SZTL 2020-01-22 11:42:01 +08:00
parent 4790884b4f
commit df7a10f50a
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GPG Key ID: 6850B6345C862176
161 changed files with 5 additions and 157054 deletions
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8
package/jsda/rtl8192du/Makefile
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@ -7,14 +7,16 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=rtl8192du
PKG_VERSION:=2018-11-10
PKG_VERSION:=2019-06-01
PKG_RELEASE:=$(PKG_SOURCE_VERSION)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/lwfinger/rtl8192du
PKG_SOURCE_VERSION:=d5056bd52d61abd88db987c8747ee06428df1c89
PKG_SOURCE_VERSION:=54c95aaa23fe332afaa1ed4aacbb0db43aa3c7dd
PKG_MIRROR_HASH:=9c21ca7b9115de8e711b38c3005fb22af5a9f392f801ac1f2383d82df789e81a
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz
PKG_MAINTAINER:=Javier Marcet <javier@keezel.co>
PKG_LICENSE:=GPLv2
@ -65,4 +67,4 @@ define KernelPackage/rtl8192du/install
$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtl8192dufw_wol.bin $(1)/lib/firmware/rtlwifi/
endef
$(eval $(call KernelPackage,rtl8192du))
$(eval $(call KernelPackage,rtl8192du))

4
package/jsda/rtl8192du/README.md
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@ -1,4 +0,0 @@
rtl8192du
=========
Source code for RTL8192DU device

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package/jsda/rtl8192du/core/rtw_ap.c
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package/jsda/rtl8192du/core/rtw_br_ext.c
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package/jsda/rtl8192du/core/rtw_cmd.c
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package/jsda/rtl8192du/core/rtw_debug.c
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package/jsda/rtl8192du/core/rtw_eeprom.c
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@ -1,378 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_EEPROM_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
void up_clk(_adapter* padapter, u16 *x)
{
_func_enter_;
*x = *x | _EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
}
void down_clk(_adapter * padapter, u16 *x )
{
_func_enter_;
*x = *x & ~_EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
}
void shift_out_bits(_adapter * padapter, u16 data, u16 count)
{
u16 x,mask;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
mask = 0x01 << (count - 1);
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDO | _EEDI);
do
{
x &= ~_EEDI;
if(data & mask)
x |= _EEDI;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
rtw_write8(padapter, EE_9346CR, (u8)x);
rtw_udelay_os(CLOCK_RATE);
up_clk(padapter, &x);
down_clk(padapter, &x);
mask = mask >> 1;
} while(mask);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~_EEDI;
rtw_write8(padapter, EE_9346CR, (u8)x);
out:
_func_exit_;
}
u16 shift_in_bits (_adapter * padapter)
{
u16 x,d=0,i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
x &= ~( _EEDO | _EEDI);
d = 0;
for(i=0; i<16; i++)
{
d = d << 1;
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDI);
if(x & _EEDO)
d |= 1;
down_clk(padapter, &x);
}
out:
_func_exit_;
return d;
}
void standby(_adapter * padapter )
{
u8 x;
_func_enter_;
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EECS | _EESK);
rtw_write8(padapter, EE_9346CR,x);
rtw_udelay_os(CLOCK_RATE);
x |= _EECS;
rtw_write8(padapter, EE_9346CR, x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
}
u16 wait_eeprom_cmd_done(_adapter* padapter)
{
u8 x;
u16 i,res=_FALSE;
_func_enter_;
standby(padapter );
for (i=0; i<200; i++)
{
x = rtw_read8(padapter, EE_9346CR);
if (x & _EEDO){
res=_TRUE;
goto exit;
}
rtw_udelay_os(CLOCK_RATE);
}
exit:
_func_exit_;
return res;
}
void eeprom_clean(_adapter * padapter)
{
u16 x;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EECS | _EEDI);
rtw_write8(padapter, EE_9346CR, (u8)x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
down_clk(padapter, &x);
out:
_func_exit_;
}
void eeprom_write16(_adapter * padapter, u16 reg, u16 data)
{
u8 x;
_func_enter_;
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
x |= _EEM1 | _EECS;
rtw_write8(padapter, EE_9346CR, x);
shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
if(padapter->EepromAddressSize==8) //CF+ and SDIO
shift_out_bits(padapter, 0, 6);
else //USB
shift_out_bits(padapter, 0, 4);
standby( padapter);
// Commented out by rcnjko, 2004.0
// // Erase this particular word. Write the erase opcode and register
// // number in that order. The opcode is 3bits in length; reg is 6 bits long.
// shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
// shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
//
// if (wait_eeprom_cmd_done(Adapter ) == FALSE)
// {
// return;
// }
standby(padapter );
// write the new word to the EEPROM
// send the write opcode the EEPORM
shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
// select which word in the EEPROM that we are writing to.
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
// write the data to the selected EEPROM word.
shift_out_bits(padapter, data, 16);
if (wait_eeprom_cmd_done(padapter ) == _FALSE)
{
goto exit;
}
standby(padapter );
shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
shift_out_bits(padapter, reg, 4);
eeprom_clean(padapter );
exit:
_func_exit_;
return;
}
u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
{
u16 x;
u16 data=0;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
x |= _EEM1 | _EECS;
rtw_write8(padapter, EE_9346CR, (unsigned char)x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
// Now read the data (16 bits) in from the selected EEPROM word
data = shift_in_bits(padapter);
eeprom_clean(padapter);
out:
_func_exit_;
return data;
}
//From even offset
void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz)
{
u16 x, data16;
u32 i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
x |= _EEM1 | _EECS;
rtw_write8(padapter, EE_9346CR, (unsigned char)x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
for(i=0; i<sz; i+=2)
{
data16 = shift_in_bits(padapter);
data[i] = data16 & 0xff;
data[i+1] = data16 >>8;
}
eeprom_clean(padapter);
out:
_func_exit_;
}
//addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg)
u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf)
{
u8 quotient, remainder, addr_2align_odd;
u16 reg, stmp , i=0, idx = 0;
_func_enter_;
reg = (u16)(addr_off >> 1);
addr_2align_odd = (u8)(addr_off & 0x1);
if(addr_2align_odd) //read that start at high part: e.g 1,3,5,7,9,...
{
stmp = eeprom_read16(padapter, reg);
rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short
reg++; sz--;
}
quotient = sz >> 1;
remainder = sz & 0x1;
for( i=0 ; i < quotient; i++)
{
stmp = eeprom_read16(padapter, reg+i);
rbuf[idx++] = (u8) (stmp&0xff);
rbuf[idx++] = (u8) ((stmp>>8)&0xff);
}
reg = reg+i;
if(remainder){ //end of read at lower part of short : 0,2,4,6,...
stmp = eeprom_read16(padapter, reg);
rbuf[idx] = (u8)(stmp & 0xff);
}
_func_exit_;
return _TRUE;
}
VOID read_eeprom_content(_adapter * padapter)
{
_func_enter_;
_func_exit_;
}

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package/jsda/rtl8192du/core/rtw_efuse.c
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package/jsda/rtl8192du/core/rtw_ieee80211.c
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package/jsda/rtl8192du/core/rtw_io.c
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@ -1,439 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*
The purpose of rtw_io.c
a. provides the API
b. provides the protocol engine
c. provides the software interface between caller and the hardware interface
Compiler Flag Option:
CONFIG_USB_HCI:
a. USE_ASYNC_IRP: Both sync/async operations are provided.
Only sync read/rtw_write_mem operations are provided.
jackson@realtek.com.tw
*/
#define _RTW_IO_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_io.h>
#include <osdep_intf.h>
#include <usb_ops.h>
u8 _rtw_read8(_adapter *adapter, u32 addr)
{
u8 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read8 = pintfhdl->io_ops._read8;
r_val = _read8(pintfhdl, addr);
_func_exit_;
return r_val;
}
u16 _rtw_read16(_adapter *adapter, u32 addr)
{
u16 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read16 = pintfhdl->io_ops._read16;
r_val = _read16(pintfhdl, addr);
_func_exit_;
return r_val;
}
u32 _rtw_read32(_adapter *adapter, u32 addr)
{
u32 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read32 = pintfhdl->io_ops._read32;
r_val = _read32(pintfhdl, addr);
_func_exit_;
return r_val;
}
int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
int ret;
_func_enter_;
_write8 = pintfhdl->io_ops._write8;
ret = _write8(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
int ret;
_func_enter_;
_write16 = pintfhdl->io_ops._write16;
ret = _write16(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
int ret;
_func_enter_;
_write32 = pintfhdl->io_ops._write32;
ret = _write32(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf));
int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata);
int ret;
_func_enter_;
_writeN = pintfhdl->io_ops._writeN;
ret = _writeN(pintfhdl, addr,length,pdata);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
int ret;
_func_enter_;
_write8_async = pintfhdl->io_ops._write8_async;
ret = _write8_async(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
int ret;
_func_enter_;
_write16_async = pintfhdl->io_ops._write16_async;
ret = _write16_async(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
int ret;
_func_enter_;
_write32_async = pintfhdl->io_ops._write32_async;
ret = _write32_async(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
}
_read_mem = pintfhdl->io_ops._read_mem;
_read_mem(pintfhdl, addr, cnt, pmem);
_func_exit_;
}
void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_func_enter_;
_write_mem = pintfhdl->io_ops._write_mem;
_write_mem(pintfhdl, addr, cnt, pmem);
_func_exit_;
}
void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
}
_read_port = pintfhdl->io_ops._read_port;
_read_port(pintfhdl, addr, cnt, pmem);
_func_exit_;
}
void _rtw_read_port_cancel(_adapter *adapter)
{
void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
if(_read_port_cancel)
_read_port_cancel(pintfhdl);
}
u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 ret = _SUCCESS;
_func_enter_;
_write_port = pintfhdl->io_ops._write_port;
ret = _write_port(pintfhdl, addr, cnt, pmem);
_func_exit_;
return ret;
}
u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
{
int ret = _SUCCESS;
struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;
struct submit_ctx sctx;
rtw_sctx_init(&sctx, timeout_ms);
pxmitbuf->sctx = &sctx;
ret = _rtw_write_port(adapter, addr, cnt, pmem);
if (ret == _SUCCESS)
ret = rtw_sctx_wait(&sctx);
return ret;
}
void _rtw_write_port_cancel(_adapter *adapter)
{
void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
if(_write_port_cancel)
_write_port_cancel(pintfhdl);
}
int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops))
{
struct io_priv *piopriv = &padapter->iopriv;
struct intf_hdl *pintf = &piopriv->intf;
if (set_intf_ops == NULL)
return _FAIL;
piopriv->padapter = padapter;
pintf->padapter = padapter;
pintf->pintf_dev = adapter_to_dvobj(padapter);
set_intf_ops(&pintf->io_ops);
return _SUCCESS;
}
#ifdef DBG_IO
u16 read_sniff_ranges[][2] = {
//{0x550, 0x551},
};
u16 write_sniff_ranges[][2] = {
//{0x550, 0x551},
//{0x4c, 0x4c},
};
int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u16)/2;
int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u16)/2;
bool match_read_sniff_ranges(u16 addr, u16 len)
{
int i;
for (i = 0; i<read_sniff_num; i++) {
if (addr + len > read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1])
return _TRUE;
}
return _FALSE;
}
bool match_write_sniff_ranges(u16 addr, u16 len)
{
int i;
for (i = 0; i<write_sniff_num; i++) {
if (addr + len > write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1])
return _TRUE;
}
return _FALSE;
}
u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u8 val = _rtw_read8(adapter, addr);
if (match_read_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n", caller, line, addr, val);
return val;
}
u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u16 val = _rtw_read16(adapter, addr);
if (match_read_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val);
return val;
}
u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u32 val = _rtw_read32(adapter, addr);
if (match_read_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val);
return val;
}
int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val);
return _rtw_write8(adapter, addr, val);
}
int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val);
return _rtw_write16(adapter, addr, val);
}
int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val);
return _rtw_write32(adapter, addr, val);
}
int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, length))
DBG_871X("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length);
return _rtw_writeN(adapter, addr, length, data);
}
#endif

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package/jsda/rtl8192du/core/rtw_ioctl_query.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_IOCTL_QUERY_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_ioctl_query.h>
#include <wifi.h>

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package/jsda/rtl8192du/core/rtw_ioctl_rtl.c
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package/jsda/rtl8192du/core/rtw_ioctl_set.c
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package/jsda/rtl8192du/core/rtw_iol.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include<rtw_iol.h>
#ifdef CONFIG_IOL
struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
{
struct xmit_frame *xmit_frame;
struct xmit_buf *xmitbuf;
struct pkt_attrib *pattrib;
struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
#if 1
if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL)
{
DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
goto exit;
}
if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL)
{
DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
rtw_free_xmitframe(pxmitpriv, xmit_frame);
xmit_frame=NULL;
goto exit;
}
xmit_frame->frame_tag = MGNT_FRAMETAG;
xmit_frame->pxmitbuf = xmitbuf;
xmit_frame->buf_addr = xmitbuf->pbuf;
xmitbuf->priv_data = xmit_frame;
pattrib = &xmit_frame->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = 0x10;
pattrib->pktlen = pattrib->last_txcmdsz = 0;
#else
if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL)
{
DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
}
else {
pattrib = &xmit_frame->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = 0x10;
pattrib->pktlen = pattrib->last_txcmdsz = 0;
}
#endif
exit:
return xmit_frame;
}
int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
{
struct pkt_attrib *pattrib = &xmit_frame->attrib;
u16 buf_offset;
u32 ori_len;
//Todo: bulkout without this offset
buf_offset = TXDESC_OFFSET;
ori_len = buf_offset+pattrib->pktlen;
//check if the io_buf can accommodate new cmds
if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
, ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
return _FAIL;
}
_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
pattrib->pktlen += cmd_len;
pattrib->last_txcmdsz += cmd_len;
//DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen);
return _SUCCESS;
}
int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
{
IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
u8* pos = (u8 *)&cmd;
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
#ifdef DBG_IO
int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value);
return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);
}
int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value);
return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);
}
int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value);
return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);
}
#endif
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
{
IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)us);
//DBG_871X("%s %u\n", __FUNCTION__, us);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
{
IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)ms);
//DBG_871X("%s %u\n", __FUNCTION__, ms);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
}
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
{
struct pkt_attrib *pattrib = &xmit_frame->attrib;
u16 buf_offset;
u32 ori_len;
IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
//Todo: bulkout without this offset
buf_offset = TXDESC_OFFSET;
ori_len = buf_offset+pattrib->pktlen;
//check if the io_buf can accommodate new cmds
if(ori_len + 8 > MAX_XMITBUF_SZ) {
DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate end cmd\n", __FUNCTION__
, ori_len + 8, MAX_XMITBUF_SZ);
return _FAIL;
}
_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, (u8*)&end_cmd, 8);
pattrib->pktlen += 8;
pattrib->last_txcmdsz += 8;
//DBG_871X("%s ori:%u + 8 = %u\n", __FUNCTION__ , ori_len, buf_offset+pattrib->pktlen);
return _SUCCESS;
}
int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms)
{
return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms);
}
int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)
{
struct xmit_frame *xmit_frame;
if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL)
return _FAIL;
if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL)
return _FAIL;
return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms);
}
int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
{
IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
return rtw_IOL_exec_cmd_array_sync(adapter, (u8*)&end_cmd, 1, max_wating_ms);
}
bool rtw_IOL_applied(ADAPTER *adapter)
{
if(adapter->registrypriv.force_iol)
return _TRUE;
if(!adapter_to_dvobj(adapter)->ishighspeed)
return _TRUE;
return _FALSE;
}
#endif //CONFIG_IOL

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package/jsda/rtl8192du/core/rtw_mlme.c
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package/jsda/rtl8192du/core/rtw_mlme_ext.c
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package/jsda/rtl8192du/core/rtw_mp.c
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package/jsda/rtl8192du/core/rtw_mp_ioctl.c
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package/jsda/rtl8192du/core/rtw_p2p.c
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package/jsda/rtl8192du/core/rtw_pwrctrl.c
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package/jsda/rtl8192du/core/rtw_recv.c
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package/jsda/rtl8192du/core/rtw_rf.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_RF_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <recv_osdep.h>
#include <xmit_osdep.h>
struct ch_freq {
u32 channel;
u32 frequency;
};
struct ch_freq ch_freq_map[] = {
{1, 2412},{2, 2417},{3, 2422},{4, 2427},{5, 2432},
{6, 2437},{7, 2442},{8, 2447},{9, 2452},{10, 2457},
{11, 2462},{12, 2467},{13, 2472},{14, 2484},
/* UNII */
{36, 5180},{40, 5200},{44, 5220},{48, 5240},{52, 5260},
{56, 5280},{60, 5300},{64, 5320},{149, 5745},{153, 5765},
{157, 5785},{161, 5805},{165, 5825},{167, 5835},{169, 5845},
{171, 5855},{173, 5865},
/* HiperLAN2 */
{100, 5500},{104, 5520},{108, 5540},{112, 5560},{116, 5580},
{120, 5600},{124, 5620},{128, 5640},{132, 5660},{136, 5680},
{140, 5700},
/* Japan MMAC */
{34, 5170},{38, 5190},{42, 5210},{46, 5230},
/* Japan */
{184, 4920},{188, 4940},{192, 4960},{196, 4980},
{208, 5040},/* Japan, means J08 */
{212, 5060},/* Japan, means J12 */
{216, 5080},/* Japan, means J16 */
};
int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq));
u32 rtw_ch2freq(u32 channel)
{
u8 i;
u32 freq = 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (channel == ch_freq_map[i].channel)
{
freq = ch_freq_map[i].frequency;
break;
}
}
if (i == ch_freq_map_num)
freq = 2412;
return freq;
}
u32 rtw_freq2ch(u32 freq)
{
u8 i;
u32 ch = 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (freq == ch_freq_map[i].frequency)
{
ch = ch_freq_map[i].channel;
break;
}
}
if (i == ch_freq_map_num)
ch = 1;
return ch;
}

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package/jsda/rtl8192du/core/rtw_security.c
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package/jsda/rtl8192du/core/rtw_sreset.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include<rtw_sreset.h>
void sreset_init_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
_rtw_mutex_init(&psrtpriv->silentreset_mutex);
psrtpriv->silent_reset_inprogress = _FALSE;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
void sreset_reset_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
psrtpriv->silent_reset_inprogress = _FALSE;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
u8 sreset_get_wifi_status(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u8 status = WIFI_STATUS_SUCCESS;
u32 val32 = 0;
_irqL irqL;
if(psrtpriv->silent_reset_inprogress == _TRUE)
{
return status;
}
val32 =rtw_read32(padapter,REG_TXDMA_STATUS);
if(val32==0xeaeaeaea){
psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
}
else if(val32!=0){
DBG_8192C("txdmastatu(%x)\n",val32);
psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
}
if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status)
{
DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status);
status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
}
DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status);
//status restore
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
return status;
#else
return WIFI_STATUS_SUCCESS;
#endif
}
void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.Wifi_Error_Status = status;
#endif
}
void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.dbg_trigger_point = tgp;
#endif
}
bool sreset_inprogress(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_RESET)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
return pHalData->srestpriv.silent_reset_inprogress;
#else
return _FALSE;
#endif
}
void sreset_restore_security_station(_adapter *padapter)
{
u8 EntryId = 0;
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct sta_priv * pstapriv = &padapter->stapriv;
struct sta_info *psta;
struct security_priv* psecuritypriv=&(padapter->securitypriv);
struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
{
u8 val8;
if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
val8 = 0xcc;
#ifdef CONFIG_WAPI_SUPPORT
} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
//Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey.
val8 = 0x4c;
#endif
} else {
val8 = 0xcf;
}
rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
}
if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
{
psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
if (psta == NULL) {
//DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
}
else
{
//pairwise key
rtw_setstakey_cmd(padapter, psta, _TRUE, _FALSE);
//group key
rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE);
}
}
}
void sreset_restore_network_station(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
#if 0
{
//=======================================================
// reset related register of Beacon control
//set MSR to nolink
Set_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
// disable update TSF
SetBcnCtrlReg(padapter, BIT(4), 0);
//=======================================================
}
#endif
rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, _FALSE);
{
u8 threshold;
// TH=1 => means that invalidate usb rx aggregation
// TH=0 => means that validate usb rx aggregation, use init value.
if(mlmepriv->htpriv.ht_option) {
if(padapter->registrypriv.wifi_spec==1)
threshold = 1;
else
threshold = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
} else {
threshold = 1;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
}
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
{
u8 join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
}
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
void sreset_restore_network_status(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
sreset_restore_network_station(padapter);
} else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
rtw_ap_restore_network(padapter);
} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
} else {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
}
}
void sreset_stop_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (!rtw_netif_queue_stopped(padapter->pnetdev))
rtw_netif_stop_queue(padapter->pnetdev);
rtw_cancel_all_timer(padapter);
tasklet_kill(&pxmitpriv->xmit_tasklet);
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
rtw_scan_abort(padapter);
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
{
rtw_set_to_roam(padapter, 0);
_rtw_join_timeout_handler(padapter);
}
}
void sreset_start_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
sreset_restore_network_status(padapter);
}
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
if (rtw_netif_queue_stopped(padapter->pnetdev))
rtw_netif_wake_queue(padapter->pnetdev);
}
void sreset_reset(_adapter *padapter)
{
#ifdef DBG_CONFIG_ERROR_RESET
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_irqL irqL;
u32 start = rtw_get_current_time();
DBG_871X("%s\n", __FUNCTION__);
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
_enter_pwrlock(&pwrpriv->lock);
psrtpriv->silent_reset_inprogress = _TRUE;
pwrpriv->change_rfpwrstate = rf_off;
sreset_stop_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_stop_adapter(padapter->pbuddy_adapter);
#endif
#ifdef CONFIG_IPS
_ips_enter(padapter);
_ips_leave(padapter);
#endif
sreset_start_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_start_adapter(padapter->pbuddy_adapter);
#endif
psrtpriv->silent_reset_inprogress = _FALSE;
_exit_pwrlock(&pwrpriv->lock);
DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
#endif
}

847
package/jsda/rtl8192du/core/rtw_sta_mgt.c
View File

@ -1,847 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTW_STA_MGT_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <recv_osdep.h>
#include <xmit_osdep.h>
#include <mlme_osdep.h>
#include <sta_info.h>
void _rtw_init_stainfo(struct sta_info *psta);
void _rtw_init_stainfo(struct sta_info *psta)
{
_func_enter_;
_rtw_memset((u8 *)psta, 0, sizeof (struct sta_info));
_rtw_spinlock_init(&psta->lock);
_rtw_init_listhead(&psta->list);
_rtw_init_listhead(&psta->hash_list);
//_rtw_init_listhead(&psta->asoc_list);
//_rtw_init_listhead(&psta->sleep_list);
//_rtw_init_listhead(&psta->wakeup_list);
_rtw_init_queue(&psta->sleep_q);
psta->sleepq_len = 0;
_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
#ifdef CONFIG_AP_MODE
_rtw_init_listhead(&psta->asoc_list);
_rtw_init_listhead(&psta->auth_list);
psta->expire_to = 0;
psta->flags = 0;
psta->capability = 0;
psta->bpairwise_key_installed = _FALSE;
#ifdef CONFIG_NATIVEAP_MLME
psta->nonerp_set = 0;
psta->no_short_slot_time_set = 0;
psta->no_short_preamble_set = 0;
psta->no_ht_gf_set = 0;
psta->no_ht_set = 0;
psta->ht_20mhz_set = 0;
#endif
#ifdef CONFIG_TX_MCAST2UNI
psta->under_exist_checking = 0;
#endif // CONFIG_TX_MCAST2UNI
psta->keep_alive_trycnt = 0;
#endif // CONFIG_AP_MODE
_func_exit_;
}
u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
{
struct sta_info *psta;
s32 i;
_func_enter_;
pstapriv->pallocated_stainfo_buf = rtw_zvmalloc (sizeof(struct sta_info) * NUM_STA+ 4);
if(!pstapriv->pallocated_stainfo_buf)
return _FAIL;
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3);
_rtw_init_queue(&pstapriv->free_sta_queue);
_rtw_spinlock_init(&pstapriv->sta_hash_lock);
//_rtw_init_queue(&pstapriv->asoc_q);
pstapriv->asoc_sta_count = 0;
_rtw_init_queue(&pstapriv->sleep_q);
_rtw_init_queue(&pstapriv->wakeup_q);
psta = (struct sta_info *)(pstapriv->pstainfo_buf);
for(i = 0; i < NUM_STA; i++)
{
_rtw_init_stainfo(psta);
_rtw_init_listhead(&(pstapriv->sta_hash[i]));
rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
psta++;
}
#ifdef CONFIG_AP_MODE
pstapriv->sta_dz_bitmap = 0;
pstapriv->tim_bitmap = 0;
_rtw_init_listhead(&pstapriv->asoc_list);
_rtw_init_listhead(&pstapriv->auth_list);
_rtw_spinlock_init(&pstapriv->asoc_list_lock);
_rtw_spinlock_init(&pstapriv->auth_list_lock);
pstapriv->asoc_list_cnt = 0;
pstapriv->auth_list_cnt = 0;
pstapriv->auth_to = 3; // 3*2 = 6 sec
pstapriv->assoc_to = 3;
//pstapriv->expire_to = 900;// 900*2 = 1800 sec = 30 min, expire after no any traffic.
//pstapriv->expire_to = 30;// 30*2 = 60 sec = 1 min, expire after no any traffic.
#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
pstapriv->expire_to = 3; // 3*2 = 6 sec
#else
pstapriv->expire_to = 60;// 60*2 = 120 sec = 2 min, expire after no any traffic.
#endif
pstapriv->max_num_sta = NUM_STA;
#endif
_func_exit_;
return _SUCCESS;
}
inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
{
int offset = (((u8 *)sta) - stapriv->pstainfo_buf)/sizeof(struct sta_info);
if (!stainfo_offset_valid(offset))
DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
return offset;
}
inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
{
if (!stainfo_offset_valid(offset))
DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
}
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
{
_func_enter_;
_rtw_spinlock_free(&psta_xmitpriv->lock);
_rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
_func_exit_;
}
static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
{
_func_enter_;
_rtw_spinlock_free(&psta_recvpriv->lock);
_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
_func_exit_;
}
void rtw_mfree_stainfo(struct sta_info *psta);
void rtw_mfree_stainfo(struct sta_info *psta)
{
_func_enter_;
if(&psta->lock != NULL)
_rtw_spinlock_free(&psta->lock);
_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
_func_exit_;
}
// this function is used to free the memory of lock || sema for all stainfos
void rtw_mfree_all_stainfo(struct sta_priv *pstapriv );
void rtw_mfree_all_stainfo(struct sta_priv *pstapriv )
{
_irqL irqL;
_list *plist, *phead;
struct sta_info *psta = NULL;
_func_enter_;
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
phead = get_list_head(&pstapriv->free_sta_queue);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
psta = LIST_CONTAINOR(plist, struct sta_info ,list);
plist = get_next(plist);
rtw_mfree_stainfo(psta);
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
_func_exit_;
}
void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv);
void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv)
{
#ifdef CONFIG_AP_MODE
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
#endif
rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock
_rtw_spinlock_free(&pstapriv->free_sta_queue.lock);
_rtw_spinlock_free(&pstapriv->sta_hash_lock);
_rtw_spinlock_free(&pstapriv->wakeup_q.lock);
_rtw_spinlock_free(&pstapriv->sleep_q.lock);
#ifdef CONFIG_AP_MODE
_rtw_spinlock_free(&pstapriv->asoc_list_lock);
_rtw_spinlock_free(&pstapriv->auth_list_lock);
_rtw_spinlock_free(&pacl_list->acl_node_q.lock);
#endif
}
u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
{
_irqL irqL;
_list *phead, *plist;
struct sta_info *psta = NULL;
struct recv_reorder_ctrl *preorder_ctrl;
int index;
_func_enter_;
if(pstapriv){
/* delete all reordering_ctrl_timer */
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(index = 0; index < NUM_STA; index++)
{
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
int i;
psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
plist = get_next(plist);
for(i=0; i < 16 ; i++)
{
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
}
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
/*===============================*/
rtw_mfree_sta_priv_lock(pstapriv);
if(pstapriv->pallocated_stainfo_buf) {
rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4);
}
}
_func_exit_;
return _SUCCESS;
}
//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr)
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
{
_irqL irqL, irqL2;
uint tmp_aid;
s32 index;
_list *phash_list;
struct sta_info *psta;
_queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
int i = 0;
u16 wRxSeqInitialValue = 0xffff;
_func_enter_;
pfree_sta_queue = &pstapriv->free_sta_queue;
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL);
_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
if (_rtw_queue_empty(pfree_sta_queue) == _TRUE)
{
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
psta = NULL;
}
else
{
psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
rtw_list_delete(&(psta->list));
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
tmp_aid = psta->aid;
_rtw_init_stainfo(psta);
_rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN);
index = wifi_mac_hash(hwaddr);
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("rtw_alloc_stainfo: index = %x", index));
if(index >= NUM_STA){
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("ERROR=> rtw_alloc_stainfo: index >= NUM_STA"));
psta= NULL;
goto exit;
}
phash_list = &(pstapriv->sta_hash[index]);
//_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
rtw_list_insert_tail(&psta->hash_list, phash_list);
pstapriv->asoc_sta_count ++ ;
//_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
// Commented by Albert 2009/08/13
// For the SMC router, the sequence number of first packet of WPS handshake will be 0.
// In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
// So, we initialize the tid_rxseq variable as the 0xffff.
for( i = 0; i < 16; i++ )
{
_rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 );
_rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i]));
}
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n",
pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5]));
init_addba_retry_timer(pstapriv->padapter, psta);
#ifdef CONFIG_TDLS
psta->padapter = pstapriv->padapter;
init_TPK_timer(pstapriv->padapter, psta);
init_ch_switch_timer(pstapriv->padapter, psta);
init_base_ch_timer(pstapriv->padapter, psta);
init_off_ch_timer(pstapriv->padapter, psta);
init_handshake_timer(pstapriv->padapter, psta);
init_tdls_alive_timer(pstapriv->padapter, psta);
#endif //CONFIG_TDLS
//for A-MPDU Rx reordering buffer control
for(i=0; i < 16 ; i++)
{
preorder_ctrl = &psta->recvreorder_ctrl[i];
preorder_ctrl->padapter = pstapriv->padapter;
preorder_ctrl->enable = _FALSE;
preorder_ctrl->indicate_seq = 0xffff;
#ifdef DBG_RX_SEQ
DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__,
preorder_ctrl->indicate_seq);
#endif
preorder_ctrl->wend_b= 0xffff;
//preorder_ctrl->wsize_b = (NR_RECVBUFF-2);
preorder_ctrl->wsize_b = 64;//64;
_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
rtw_init_recv_timer(preorder_ctrl);
}
//init for DM
psta->rssi_stat.UndecoratedSmoothedPWDB = 0;
psta->rssi_stat.UndecoratedSmoothedCCK = (-1);
/* init for the sequence number of received management frame */
psta->RxMgmtFrameSeqNum = 0xffff;
}
exit:
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
_func_exit_;
return psta;
}
// using pstapriv->sta_hash_lock to protect
u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
{
int i;
_irqL irqL0;
_queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
struct sta_xmit_priv *pstaxmitpriv;
struct xmit_priv *pxmitpriv= &padapter->xmitpriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct hw_xmit *phwxmit;
int pending_qcnt[4];
_func_enter_;
if (psta == NULL)
goto exit;
_enter_critical_bh(&psta->lock, &irqL0);
psta->state &= ~_FW_LINKED;
_exit_critical_bh(&psta->lock, &irqL0);
pfree_sta_queue = &pstapriv->free_sta_queue;
pstaxmitpriv = &psta->sta_xmitpriv;
//rtw_list_delete(&psta->sleep_list);
//rtw_list_delete(&psta->wakeup_list);
_enter_critical_bh(&pxmitpriv->lock, &irqL0);
rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
psta->sleepq_len = 0;
//vo
//_enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
phwxmit = pxmitpriv->hwxmits;
phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt;
pstaxmitpriv->vo_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
//vi
//_enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+1;
phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt;
pstaxmitpriv->vi_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0);
//be
//_enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+2;
phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
pending_qcnt[2] = pstaxmitpriv->be_q.qcnt;
pstaxmitpriv->be_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0);
//bk
//_enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+3;
phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt;
pstaxmitpriv->bk_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt);
_exit_critical_bh(&pxmitpriv->lock, &irqL0);
rtw_list_delete(&psta->hash_list);
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]));
pstapriv->asoc_sta_count --;
// re-init sta_info; 20061114 // will be init in alloc_stainfo
//_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
//_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
_cancel_timer_ex(&psta->addba_retry_timer);
#ifdef CONFIG_TDLS
_cancel_timer_ex(&psta->TPK_timer);
_cancel_timer_ex(&psta->option_timer);
_cancel_timer_ex(&psta->base_ch_timer);
_cancel_timer_ex(&psta->off_ch_timer);
_cancel_timer_ex(&psta->alive_timer1);
_cancel_timer_ex(&psta->alive_timer2);
#endif //CONFIG_TDLS
//for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer
for(i=0; i < 16 ; i++)
{
_irqL irqL;
_list *phead, *plist;
union recv_frame *prframe;
_queue *ppending_recvframe_queue;
_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
phead = get_list_head(ppending_recvframe_queue);
plist = get_next(phead);
while(!rtw_is_list_empty(phead))
{
prframe = LIST_CONTAINOR(plist, union recv_frame, u);
plist = get_next(plist);
rtw_list_delete(&(prframe->u.hdr.list));
rtw_free_recvframe(prframe, pfree_recv_queue);
}
_exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);
}
#ifdef CONFIG_AP_MODE
/*
_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
rtw_list_delete(&psta->asoc_list);
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
*/
_enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);
if (!rtw_is_list_empty(&psta->auth_list)) {
rtw_list_delete(&psta->auth_list);
pstapriv->auth_list_cnt--;
}
_exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);
psta->expire_to = 0;
psta->sleepq_ac_len = 0;
psta->qos_info = 0;
psta->max_sp_len = 0;
psta->uapsd_bk = 0;
psta->uapsd_be = 0;
psta->uapsd_vi = 0;
psta->uapsd_vo = 0;
psta->has_legacy_ac = 0;
#ifdef CONFIG_NATIVEAP_MLME
pstapriv->sta_dz_bitmap &=~BIT(psta->aid);
pstapriv->tim_bitmap &=~BIT(psta->aid);
//rtw_indicate_sta_disassoc_event(padapter, psta);
if ((psta->aid >0)&&(pstapriv->sta_aid[psta->aid - 1] == psta))
{
pstapriv->sta_aid[psta->aid - 1] = NULL;
psta->aid = 0;
}
#endif // CONFIG_NATIVEAP_MLME
#ifdef CONFIG_TX_MCAST2UNI
psta->under_exist_checking = 0;
#endif // CONFIG_TX_MCAST2UNI
#endif // CONFIG_AP_MODE
_rtw_spinlock_free(&psta->lock);
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0);
rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL0);
exit:
_func_exit_;
return _SUCCESS;
}
// free all stainfo which in sta_hash[all]
void rtw_free_all_stainfo(_adapter *padapter)
{
_irqL irqL;
_list *plist, *phead;
s32 index;
struct sta_info *psta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter);
_func_enter_;
if(pstapriv->asoc_sta_count==1)
goto exit;
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(index=0; index< NUM_STA; index++)
{
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
plist = get_next(plist);
if(pbcmc_stainfo!=psta)
rtw_free_stainfo(padapter , psta);
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
exit:
_func_exit_;
}
/* any station allocated can be searched by hash list */
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
{
_irqL irqL;
_list *plist, *phead;
struct sta_info *psta = NULL;
u32 index;
u8 *addr;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
if(hwaddr==NULL)
return NULL;
if(IS_MCAST(hwaddr))
{
addr = bc_addr;
}
else
{
addr = hwaddr;
}
index = wifi_mac_hash(addr);
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE)
{ // if found the matched address
break;
}
psta=NULL;
plist = get_next(plist);
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
_func_exit_;
return psta;
}
u32 rtw_init_bcmc_stainfo(_adapter* padapter)
{
struct sta_info *psta;
struct tx_servq *ptxservq;
u32 res=_SUCCESS;
NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff};
struct sta_priv *pstapriv = &padapter->stapriv;
//_queue *pstapending = &padapter->xmitpriv.bm_pending;
_func_enter_;
psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
if(psta==NULL){
res=_FAIL;
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail"));
goto exit;
}
// default broadcast & multicast use macid 1
psta->mac_id = 1;
ptxservq= &(psta->sta_xmitpriv.be_q);
/*
_enter_critical(&pstapending->lock, &irqL0);
if (rtw_is_list_empty(&ptxservq->tx_pending))
rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
_exit_critical(&pstapending->lock, &irqL0);
*/
exit:
_func_exit_;
return _SUCCESS;
}
struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter)
{
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
psta = rtw_get_stainfo(pstapriv, bc_addr);
_func_exit_;
return psta;
}
u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr)
{
u8 res = _TRUE;
#ifdef CONFIG_AP_MODE
_irqL irqL;
_list *plist, *phead;
struct rtw_wlan_acl_node *paclnode;
u8 match = _FALSE;
struct sta_priv *pstapriv = &padapter->stapriv;
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
_queue *pacl_node_q =&pacl_list->acl_node_q;
_enter_critical_bh(&(pacl_node_q->lock), &irqL);
phead = get_list_head(pacl_node_q);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
plist = get_next(plist);
if(_rtw_memcmp(paclnode->addr, mac_addr, ETH_ALEN))
{
if(paclnode->valid == _TRUE)
{
match = _TRUE;
break;
}
}
}
_exit_critical_bh(&(pacl_node_q->lock), &irqL);
if(pacl_list->mode == 1)//accept unless in deny list
{
res = (match == _TRUE) ? _FALSE:_TRUE;
}
else if(pacl_list->mode == 2)//deny unless in accept list
{
res = (match == _TRUE) ? _TRUE:_FALSE;
}
else
{
res = _TRUE;
}
#endif
return res;
}

2940
package/jsda/rtl8192du/core/rtw_tdls.c
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2585
package/jsda/rtl8192du/core/rtw_wlan_util.c
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4158
package/jsda/rtl8192du/core/rtw_xmit.c
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7
package/jsda/rtl8192du/dkms.conf
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MAKE="'make'"
BUILT_MODULE_NAME=8192du
BUILD_MODULE_NAME=8192du
DEST_MODULE_LOCATION=/kernel/drivers/net/wireless/
PACKAGE_NAME=8192du
PACKAGE_VERSION=1.0
REMAKE_INITRD=yes

3690
package/jsda/rtl8192du/hal/Hal8192DUHWImg.c
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1578
package/jsda/rtl8192du/hal/Hal8192DUHWImg_wowlan.c
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150
package/jsda/rtl8192du/hal/HalPwrSeqCmd.c
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@ -1,150 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
HalPwrSeqCmd.c
Abstract:
Implement HW Power sequence configuration CMD handling routine for Realtek devices.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
2011-07-07 Roger Create.
--*/
#include <HalPwrSeqCmd.h>
#include <sdio_ops.h>
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrSeqCmd[])
{
WLAN_PWR_CFG PwrCfgCmd = {0};
u8 bPollingBit = _FALSE;
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; // polling autoload done.
u32 maxPollingCnt = 5000;
do {
PwrCfgCmd = PwrSeqCmd[AryIdx];
RT_TRACE(_module_hal_init_c_ , _drv_info_,
("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
GET_PWR_CFG_OFFSET(PwrCfgCmd),
GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
GET_PWR_CFG_BASE(PwrCfgCmd),
GET_PWR_CFG_CMD(PwrCfgCmd),
GET_PWR_CFG_MASK(PwrCfgCmd),
GET_PWR_CFG_VALUE(PwrCfgCmd)));
//2 Only Handle the command whose FAB, CUT, and Interface are matched
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
{
switch (GET_PWR_CFG_CMD(PwrCfgCmd))
{
case PWR_CMD_READ:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
break;
case PWR_CMD_WRITE:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
// Read the value from system register
value = rtw_read8(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write the value back to sytem register
rtw_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
bPollingBit = _FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
do {
value = rtw_read8(padapter, offset);
value &= GET_PWR_CFG_MASK(PwrCfgCmd);
if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit = _TRUE;
else
rtw_udelay_os(10);
if (pollingCount++ > maxPollingCnt) {
RT_TRACE(_module_hal_init_c_ , _drv_err_, ("Fail to polling Offset[%#x]\n", offset));
return _FALSE;
}
} while (!bPollingBit);
break;
case PWR_CMD_DELAY:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
break;
case PWR_CMD_END:
// When this command is parsed, end the process
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
return _TRUE;
break;
default:
RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
break;
}
}
AryIdx++;//Add Array Index
}while(1);
return _TRUE;
}

856
package/jsda/rtl8192du/hal/dm.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8192d_hal.h>
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
typedef enum _ODM_RF_RADIO_PATH {
ODM_RF_PATH_A = 0, //Radio Path A
ODM_RF_PATH_B = 1, //Radio Path B
ODM_RF_PATH_C = 2, //Radio Path C
ODM_RF_PATH_D = 3, //Radio Path D
ODM_RF_PATH_AB,
ODM_RF_PATH_AC,
ODM_RF_PATH_AD,
ODM_RF_PATH_BC,
ODM_RF_PATH_BD,
ODM_RF_PATH_CD,
ODM_RF_PATH_ABC,
ODM_RF_PATH_ACD,
ODM_RF_PATH_BCD,
ODM_RF_PATH_ABCD,
// ODM_RF_PATH_MAX, //Max RF number 90 support
} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
#define ODM_AP 0x01 //BIT0
#define ODM_ADSL 0x02 //BIT1
#define ODM_CE 0x04 //BIT2
#define ODM_WIN 0x08 //BIT3
#define DM_ODM_SUPPORT_TYPE ODM_CE
typedef enum tag_ODM_Support_Interface_Definition
{
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
ODM_ITRF_SDIO = 0x4,
ODM_ITRF_ALL = 0x7,
}ODM_INTERFACE_E;
typedef enum tag_ODM_Support_IC_Type_Definition
{
ODM_RTL8192S = BIT0,
ODM_RTL8192C = BIT1,
ODM_RTL8192D = BIT2,
ODM_RTL8723A = BIT3,
ODM_RTL8188E = BIT4,
ODM_RTL8812 = BIT5,
ODM_RTL8821 = BIT6,
ODM_RTL8192E = BIT7,
ODM_RTL8723B = BIT8,
ODM_RTL8813A = BIT9,
ODM_RTL8881A = BIT10
}ODM_IC_TYPE_E;
#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8813A|ODM_RTL8881A)
u1Byte
ODM_Read1Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R8(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead1Byte(Adapter, RegAddr);
#endif
}
u2Byte
ODM_Read2Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R16(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read16(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead2Byte(Adapter, RegAddr);
#endif
}
u4Byte
ODM_Read4Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R32(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read32(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead4Byte(Adapter, RegAddr);
#endif
}
VOID
ODM_Write1Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u1Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W8(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write8(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite1Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_Write2Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u2Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W16(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_Write4Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W32(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write32(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite4Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_SetMACReg(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetMACReg(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryMacReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryMacReg(Adapter, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
return PHY_QueryBBReg(pDM_Odm->Adapter, RegAddr, BitMask);
#endif
}
VOID
ODM_SetBBReg(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetBBReg(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
#endif
}
VOID
ODM_SetRFReg(
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E eRFPath,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetRFReg(
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E eRFPath,
u4Byte RegAddr,
u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask);
#endif
}
#include "odm_RegDefine11N.h"
#include "odm_RegDefine11AC.h"
#include "odm_debug.h"
VOID
ODM_InitDebugSetting(
PDM_ODM_T pDM_Odm
)
{
pDM_Odm->DebugLevel = ODM_DBG_LOUD;
pDM_Odm->DebugComponents =
\
#if ODM_DBG
//BB Functions
// ODM_COMP_DIG |
// ODM_COMP_RA_MASK |
// ODM_COMP_DYNAMIC_TXPWR |
// ODM_COMP_FA_CNT |
// ODM_COMP_RSSI_MONITOR |
// ODM_COMP_CCK_PD |
// ODM_COMP_ANT_DIV |
// ODM_COMP_PWR_SAVE |
// ODM_COMP_PWR_TRAIN |
// ODM_COMP_RATE_ADAPTIVE |
// ODM_COMP_PATH_DIV |
// ODM_COMP_DYNAMIC_PRICCA |
// ODM_COMP_RXHP |
// ODM_COMP_MP |
// ODM_COMP_DYNAMIC_ATC |
//MAC Functions
// ODM_COMP_EDCA_TURBO |
// ODM_COMP_EARLY_MODE |
//RF Functions
// ODM_COMP_TX_PWR_TRACK |
// ODM_COMP_RX_GAIN_TRACK |
// ODM_COMP_CALIBRATION |
//Common
// ODM_COMP_COMMON |
// ODM_COMP_INIT |
// ODM_COMP_PSD |
#endif
0;
}
const char *odm_comp_str[] = {
/* BIT0 */"ODM_COMP_DIG",
/* BIT1 */"ODM_COMP_RA_MASK",
/* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
/* BIT3 */"ODM_COMP_FA_CNT",
/* BIT4 */"ODM_COMP_RSSI_MONITOR",
/* BIT5 */"ODM_COMP_CCK_PD",
/* BIT6 */"ODM_COMP_ANT_DIV",
/* BIT7 */"ODM_COMP_PWR_SAVE",
/* BIT8 */"ODM_COMP_PWR_TRAIN",
/* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
/* BIT10 */"ODM_COMP_PATH_DIV",
/* BIT11 */"ODM_COMP_PSD",
/* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
/* BIT13 */"ODM_COMP_RXHP",
/* BIT14 */"ODM_COMP_MP",
/* BIT15 */"ODM_COMP_DYNAMIC_ATC",
/* BIT16 */"ODM_COMP_EDCA_TURBO",
/* BIT17 */"ODM_COMP_EARLY_MODE",
/* BIT18 */NULL,
/* BIT19 */NULL,
/* BIT20 */NULL,
/* BIT21 */NULL,
/* BIT22 */NULL,
/* BIT23 */NULL,
/* BIT24 */"ODM_COMP_TX_PWR_TRACK",
/* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
/* BIT26 */"ODM_COMP_CALIBRATION",
/* BIT27 */NULL,
/* BIT28 */NULL,
/* BIT29 */NULL,
/* BIT30 */"ODM_COMP_COMMON",
/* BIT31 */"ODM_COMP_INIT",
};
#define RTW_ODM_COMP_MAX 32
const char *odm_dbg_level_str[] = {
NULL,
"ODM_DBG_OFF",
"ODM_DBG_SERIOUS",
"ODM_DBG_WARNING",
"ODM_DBG_LOUD",
"ODM_DBG_TRACE",
};
#define RTW_ODM_DBG_LEVEL_NUM 6
void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter)
{
DM_ODM_T *odm = adapter_to_odm(adapter);
int cnt = 0;
u64 dbg_comp;
int i;
dbg_comp = odm->DebugComponents;
DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx \n", dbg_comp);
for (i=0;i<RTW_ODM_COMP_MAX;i++) {
if (odm_comp_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
}
}
inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
{
DM_ODM_T *odm = adapter_to_odm(adapter);
odm->DebugComponents = comps;
}
void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
{
DM_ODM_T *odm = adapter_to_odm(adapter);
int cnt = 0;
u32 dbg_level;
int i;
dbg_level = odm->DebugLevel;
DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
if (odm_dbg_level_str[i])
DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
}
}
inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
{
DM_ODM_T *odm = adapter_to_odm(adapter);
odm->DebugLevel= level;
}
const char *dm_ability_str[] = {
/* BIT0 */"DYNAMIC_FUNC_DIG",
/* BIT1 */"DYNAMIC_FUNC_HP",
/* BIT2 */"DYNAMIC_FUNC_SS",
/* BIT3 */"DYNAMIC_FUNC_BT",
/* BIT4 */"DYNAMIC_FUNC_ANT_DIV",
#ifdef CONFIG_ODM_ADAPTIVITY
/* BIT5 */"DYNAMIC_FUNC_ADAPTIVITY",
#endif
};
#ifdef CONFIG_ODM_ADAPTIVITY
#define RTW_DM_ABILITY_MAX 6
#else
#define RTW_DM_ABILITY_MAX 5
#endif
void rtw_dm_check_rxfifo_full(_adapter *adapter)
{
struct dvobj_priv *psdpriv = adapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
//check RX fifo counter
rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0);
pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
}
void rtw_dm_ability_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
int cnt = 0;
u8 ability = 0;
int i;
rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
DBG_871X_SEL_NL(sel, "dm.DMFlag = 0x%02x\n", ability);
for (i=0;i<RTW_DM_ABILITY_MAX;i++) {
if (dm_ability_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & ability ? '+' : ' ', i, dm_ability_str[i]);
}
}
inline void rtw_dm_ability_set(_adapter *adapter, u8 ability)
{
rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
}
bool rtw_adapter_linked(_adapter *adapter)
{
bool linked = _FALSE;
struct mlme_priv *mlmepriv = &adapter->mlmepriv;
if( (check_fwstate(mlmepriv, WIFI_AP_STATE) == _TRUE) ||
(check_fwstate(mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE))
{
if(adapter->stapriv.asoc_sta_count > 2)
linked = _TRUE;
}
else{//Station mode
if(check_fwstate(mlmepriv, _FW_LINKED)== _TRUE)
linked = _TRUE;
}
return linked;
}
bool dm_linked(_adapter *adapter)
{
bool linked;
if ((linked = rtw_adapter_linked(adapter)))
goto exit;
#ifdef CONFIG_CONCURRENT_MODE
if ((adapter = adapter->pbuddy_adapter) == NULL)
goto exit;
linked = rtw_adapter_linked(adapter);
#endif
exit:
return linked;
}
/* v4 branch doesn't have common traffic_stat in dvobj */
u64 dev_tx_uncast_bytes(_adapter *adapter)
{
u64 tx_bytes = 0;
tx_bytes += adapter->xmitpriv.tx_bytes;
#ifdef CONFIG_CONCURRENT_MODE
if ((adapter = adapter->pbuddy_adapter) == NULL)
goto exit;
tx_bytes += adapter->xmitpriv.tx_bytes;
#endif
exit:
return tx_bytes;
}
u64 dev_rx_uncast_bytes(_adapter *adapter)
{
u64 rx_bytes = 0;
rx_bytes += adapter->recvpriv.rx_bytes;
#ifdef CONFIG_CONCURRENT_MODE
if ((adapter = adapter->pbuddy_adapter) == NULL)
goto exit;
rx_bytes += adapter->recvpriv.rx_bytes;
#endif
exit:
return rx_bytes;
}
void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
{
#ifdef CONFIG_ODM_ADAPTIVITY
DM_ODM_T *odm = adapter_to_odm(adapter);
DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
, "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
, (u8)odm->TH_L2H_ini
, odm->TH_EDCCA_HL_diff
, odm->IGI_Base
, odm->ForceEDCCA
, odm->AdapEn_RSSI
, odm->IGI_LowerBound
);
#endif /* CONFIG_ODM_ADAPTIVITY */
}
void rtw_odm_adaptivity_parm_set(_adapter *pAdapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
{
#ifdef CONFIG_ODM_ADAPTIVITY
DM_ODM_T *odm = adapter_to_odm(pAdapter);
odm->TH_L2H_ini = TH_L2H_ini;
odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
odm->IGI_Base = IGI_Base;
odm->ForceEDCCA = ForceEDCCA;
odm->AdapEn_RSSI = AdapEn_RSSI;
odm->IGI_LowerBound = IGI_LowerBound;
#endif /* CONFIG_ODM_ADAPTIVITY */
}
#ifdef CONFIG_ODM_ADAPTIVITY
VOID
ODM_Write_DIG(
PDM_ODM_T pDM_Odm,
u1Byte CurrentIGI
)
{
_adapter *adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
struct dm_priv *dmpriv = &pHalData->dmpriv;
DIG_T *pDigTable = &dmpriv->DM_DigTable;
if(pDigTable->CurIGValue != CurrentIGI) {
pDigTable->CurIGValue = CurrentIGI;
rtw_warn_on(!pDM_Odm->write_dig);
if (pDM_Odm->write_dig)
pDM_Odm->write_dig(adapter);
}
}
VOID
Phydm_SearchPwdBLowerBound(
PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 = 0;
u1Byte cnt, IGI = 0x50; /*IGI = 0x50 for cal EDCCA lower bound*/
u1Byte txEdcca1 = 0, txEdcca0 = 0;
BOOLEAN bAdjust = _TRUE;
s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
s1Byte Diff;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, 0x1); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, 0x1); /*set RXmod to standby mode to remove outside noise affect*/
if (pHalData->rf_type != RF_1T1R ) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, 0x1); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, 0x1); /*set RXmod to standby mode to remove outside noise affect*/
}
ODM_Write_DIG(pDM_Odm, 0x7e);
Diff = IGI_target - (s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if (TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
rtw_mdelay_os(5);
while (bAdjust) {
for (cnt = 0; cnt < 20; cnt++) {
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);
if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8723B | ODM_RTL8188E)))
txEdcca1 = txEdcca1 + 1;
else if (value32 & BIT29)
txEdcca1 = txEdcca1 + 1;
else
txEdcca0 = txEdcca0 + 1;
}
if (txEdcca1 > 1) {
IGI = IGI - 1;
TH_L2H_dmc = TH_L2H_dmc + 1;
if (TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
if (TH_L2H_dmc == 10) {
bAdjust = _FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
txEdcca1 = 0;
txEdcca0 = 0;
} else {
bAdjust = _FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
txEdcca1 = 0;
txEdcca0 = 0;
}
}
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, 0x2); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, 0x3); /*set RXmod to standby mode to remove outside noise affect*/
if (pHalData->rf_type != RF_1T1R ) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, 0x2); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, 0x3); /*set RXmod to standby mode to remove outside noise affect*/
}
ODM_Write_DIG(pDM_Odm, 0x20);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)0x7f);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)0x7f);
}
#endif /* CONFIG_ODM_ADAPTIVITY */
VOID
odm_AdaptivityInit(
PDM_ODM_T pDM_Odm
)
{
#ifdef CONFIG_ODM_ADAPTIVITY
pDM_Odm->TH_L2H_ini = 0xef; // -17
pDM_Odm->TH_EDCCA_HL_diff = 7;
pDM_Odm->IGI_Base = 0x32;
pDM_Odm->IGI_target = 0x1c;
pDM_Odm->ForceEDCCA = 0;
pDM_Odm->AdapEn_RSSI = 20;
pDM_Odm->NHM_disable = _FALSE;
pDM_Odm->TxHangFlg = _TRUE;
pDM_Odm->txEdcca0 = 0;
pDM_Odm->txEdcca1 = 0;
pDM_Odm->H2L_lb= 0;
pDM_Odm->L2H_lb= 0;
pDM_Odm->Adaptivity_IGI_upper = 0;
pDM_Odm->adaptivity_flag= _TRUE;
//Reg524[11]=0 is easily to transmit packets during adaptivity test
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0*/
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); /*reg524[11]=1 */
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
Phydm_SearchPwdBLowerBound(pDM_Odm);
#endif /* CONFIG_ODM_ADAPTIVITY */
}
VOID
odm_Adaptivity(
PDM_ODM_T pDM_Odm
)
{
#ifdef CONFIG_ODM_ADAPTIVITY
s1Byte TH_L2H_dmc, TH_H2L_dmc;
s1Byte Diff, IGI_target;
u32 value32;
BOOLEAN EDCCA_State = _TRUE;
_adapter *pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *dmpriv = &pHalData->dmpriv;
DIG_T *pDigTable = &dmpriv->DM_DigTable;
u8 IGI = pDigTable->CurIGValue;
u8 RSSI_Min = pDigTable->Rssi_val_min;
HT_CHANNEL_WIDTH BandWidth = rtw_get_oper_bw(pAdapter);
if (!(dmpriv->DMFlag & DYNAMIC_FUNC_ADAPTIVITY))
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
// Add by Neil Chen to enable edcca to MP Platform
return;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
IGI_target = pDM_Odm->IGI_Base;
pDM_Odm->IGI_target = (u1Byte) IGI_target;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
(BandWidth==HT_CHANNEL_WIDTH_40)?"40M":"20M", IGI_target, EDCCA_State));
if(EDCCA_State == _TRUE)
{
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10) TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
//replace lower bound to prevent EDCCA always equal 1
if(TH_H2L_dmc < pDM_Odm->H2L_lb)
TH_H2L_dmc = pDM_Odm->H2L_lb;
if(TH_L2H_dmc < pDM_Odm->L2H_lb)
TH_L2H_dmc = pDM_Odm->L2H_lb;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n",
IGI, TH_L2H_dmc, TH_H2L_dmc));
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
#endif /* CONFIG_ODM_ADAPTIVITY */
}
void rtw_odm_init(_adapter *adapter)
{
PDM_ODM_T odm = adapter_to_odm(adapter);
odm->Adapter = adapter;
rtw_warn_on(!odm->Adapter);
switch (adapter->chip_type) {
case RTL8188C_8192C:
odm->SupportICType = ODM_RTL8192C;
break;
case RTL8192D:
odm->SupportICType = ODM_RTL8192D;
break;
default:
odm->SupportICType = 0;
};
rtw_warn_on(!odm->SupportICType);
switch (adapter->interface_type) {
case RTW_USB:
odm->SupportInterface = ODM_ITRF_USB;
break;
case RTW_PCIE:
odm->SupportInterface = ODM_ITRF_PCIE;
break;
default:
odm->SupportInterface = 0;
};
rtw_warn_on(!odm->SupportInterface);
ODM_InitDebugSetting(odm);
}

94
package/jsda/rtl8192du/hal/dm.h
View File

@ -1,94 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DM_H__
#define __DM_H__
#define DYNAMIC_FUNC_DISABLE (0x0)
#define DYNAMIC_FUNC_DIG BIT(0)
#define DYNAMIC_FUNC_HP BIT(1)
#define DYNAMIC_FUNC_SS BIT(2) //Tx Power Tracking
#define DYNAMIC_FUNC_BT BIT(3)
#define DYNAMIC_FUNC_ANT_DIV BIT(4)
#define DYNAMIC_FUNC_ADAPTIVITY BIT(5)
void rtw_dm_ability_msg(void *sel, _adapter *adapter);
void rtw_dm_ability_set(_adapter *adapter, u8 ability);
void rtw_dm_check_rxfifo_full(_adapter *adapter);
void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter);
void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps);
void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter);
void rtw_odm_dbg_level_set(_adapter *adapter, u32 level);
void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter);
void rtw_odm_adaptivity_parm_set(_adapter *pAdapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound);
void rtw_odm_init(_adapter *adapter);
typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
{
_adapter *Adapter;
u32 SupportICType;
u8 SupportInterface;
u64 DebugComponents;
u32 DebugLevel;
void (*write_dig)(_adapter *adapter);
#ifdef CONFIG_ODM_ADAPTIVITY
/* Ported from ODM, for ESTI Adaptivity test */
s8 TH_L2H_ini;
s8 TH_EDCCA_HL_diff;
s8 IGI_Base;
u8 IGI_target;
bool ForceEDCCA;
u8 AdapEn_RSSI;
s8 Force_TH_H;
s8 Force_TH_L;
u8 IGI_LowerBound;
bool bPreEdccaEnable;
// add by Yu Cehn for adaptivtiy
bool adaptivity_flag;
bool NHM_disable;
bool TxHangFlg;
u8 tolerance_cnt;
u64 NHMCurTxOkcnt;
u64 NHMCurRxOkcnt;
u64 NHMLastTxOkcnt;
u64 NHMLastRxOkcnt;
u8 txEdcca1;
u8 txEdcca0;
s8 H2L_lb;
s8 L2H_lb;
u8 Adaptivity_IGI_upper;
#endif
} DM_ODM_T, *PDM_ODM_T; /* ODM structure for ease of partial porting */
void odm_AdaptivityInit(PDM_ODM_T pDM_Odm);
void odm_Adaptivity(PDM_ODM_T pDM_Odm);
#endif /* __DM_H__ */

593
package/jsda/rtl8192du/hal/hal_com.c
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@ -1,593 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_byteorder.h>
#include <hal_intf.h>
#include <hal_com.h>
#include <rtl8192d_hal.h>
#define _HAL_COM_C_
//============================================================
// Global var
//============================================================
u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
0x7f8001fe, // 0, +6.0dB
0x788001e2, // 1, +5.5dB
0x71c001c7, // 2, +5.0dB
0x6b8001ae, // 3, +4.5dB
0x65400195, // 4, +4.0dB
0x5fc0017f, // 5, +3.5dB
0x5a400169, // 6, +3.0dB
0x55400155, // 7, +2.5dB
0x50800142, // 8, +2.0dB
0x4c000130, // 9, +1.5dB
0x47c0011f, // 10, +1.0dB
0x43c0010f, // 11, +0.5dB
0x40000100, // 12, +0dB
0x3c8000f2, // 13, -0.5dB
0x390000e4, // 14, -1.0dB
0x35c000d7, // 15, -1.5dB
0x32c000cb, // 16, -2.0dB
0x300000c0, // 17, -2.5dB
0x2d4000b5, // 18, -3.0dB
0x2ac000ab, // 19, -3.5dB
0x288000a2, // 20, -4.0dB
0x26000098, // 21, -4.5dB
0x24000090, // 22, -5.0dB
0x22000088, // 23, -5.5dB
0x20000080, // 24, -6.0dB
0x1e400079, // 25, -6.5dB
0x1c800072, // 26, -7.0dB
0x1b00006c, // 27. -7.5dB
0x19800066, // 28, -8.0dB
0x18000060, // 29, -8.5dB
0x16c0005b, // 30, -9.0dB
0x15800056, // 31, -9.5dB
0x14400051, // 32, -10.0dB
0x1300004c, // 33, -10.5dB
0x12000048, // 34, -11.0dB
0x11000044, // 35, -11.5dB
0x10000040, // 36, -12.0dB
0x0f00003c,// 37, -12.5dB
0x0e400039,// 38, -13.0dB
0x0d800036,// 39, -13.5dB
0x0cc00033,// 40, -14.0dB
0x0c000030,// 41, -14.5dB
0x0b40002d,// 42, -15.0dB
};
u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB
};
u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB
};
#ifdef CONFIG_CHIP_VER_INTEGRATION
void dump_chip_info(HAL_VERSION ChipVersion)
{
if(IS_81XXC(ChipVersion)){
DBG_871X("Chip Version Info: %s_",IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
}
else if(IS_92D(ChipVersion)){
DBG_871X("Chip Version Info: CHIP_8192D_");
}
else if(IS_8723_SERIES(ChipVersion)){
DBG_871X("Chip Version Info: CHIP_8723A_");
}
else if(IS_8188E(ChipVersion)){
DBG_871X("Chip Version Info: CHIP_8188E_");
}
DBG_871X("%s_",IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip");
DBG_871X("%s_",IS_CHIP_VENDOR_TSMC(ChipVersion)?"TSMC":"UMC");
if(IS_A_CUT(ChipVersion)) DBG_871X("A_CUT_");
else if(IS_B_CUT(ChipVersion)) DBG_871X("B_CUT_");
else if(IS_C_CUT(ChipVersion)) DBG_871X("C_CUT_");
else if(IS_D_CUT(ChipVersion)) DBG_871X("D_CUT_");
else if(IS_E_CUT(ChipVersion)) DBG_871X("E_CUT_");
else DBG_871X("UNKNOWN_CUT(%d)_",ChipVersion.CUTVersion);
if(IS_1T1R(ChipVersion)) DBG_871X("1T1R_");
else if(IS_1T2R(ChipVersion)) DBG_871X("1T2R_");
else if(IS_2T2R(ChipVersion)) DBG_871X("2T2R_");
else DBG_871X("UNKNOWN_RFTYPE(%d)_",ChipVersion.RFType);
DBG_871X("RomVer(%d)\n",ChipVersion.ROMVer);
}
#endif
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
u8 //return the final channel plan decision
hal_com_get_channel_plan(
PADAPTER padapter,
u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
u8 sw_channel_plan, //channel plan from SW (registry/module param)
u8 def_channel_plan, //channel plan used when the former two is invalid
BOOLEAN AutoLoadFail
)
{
u8 swConfig;
u8 chnlPlan;
swConfig = _TRUE;
if (!AutoLoadFail)
{
if (!rtw_is_channel_plan_valid(sw_channel_plan))
swConfig = _FALSE;
if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
swConfig = _FALSE;
}
if (swConfig == _TRUE)
chnlPlan = sw_channel_plan;
else
chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
if (!rtw_is_channel_plan_valid(chnlPlan))
chnlPlan = def_channel_plan;
return chnlPlan;
}
u8 MRateToHwRate(u8 rate)
{
u8 ret = DESC_RATE1M;
switch(rate)
{
// CCK and OFDM non-HT rates
case IEEE80211_CCK_RATE_1MB: ret = DESC_RATE1M; break;
case IEEE80211_CCK_RATE_2MB: ret = DESC_RATE2M; break;
case IEEE80211_CCK_RATE_5MB: ret = DESC_RATE5_5M; break;
case IEEE80211_CCK_RATE_11MB: ret = DESC_RATE11M; break;
case IEEE80211_OFDM_RATE_6MB: ret = DESC_RATE6M; break;
case IEEE80211_OFDM_RATE_9MB: ret = DESC_RATE9M; break;
case IEEE80211_OFDM_RATE_12MB: ret = DESC_RATE12M; break;
case IEEE80211_OFDM_RATE_18MB: ret = DESC_RATE18M; break;
case IEEE80211_OFDM_RATE_24MB: ret = DESC_RATE24M; break;
case IEEE80211_OFDM_RATE_36MB: ret = DESC_RATE36M; break;
case IEEE80211_OFDM_RATE_48MB: ret = DESC_RATE48M; break;
case IEEE80211_OFDM_RATE_54MB: ret = DESC_RATE54M; break;
// HT rates since here
//case MGN_MCS0: ret = DESC_RATEMCS0; break;
//case MGN_MCS1: ret = DESC_RATEMCS1; break;
//case MGN_MCS2: ret = DESC_RATEMCS2; break;
//case MGN_MCS3: ret = DESC_RATEMCS3; break;
//case MGN_MCS4: ret = DESC_RATEMCS4; break;
//case MGN_MCS5: ret = DESC_RATEMCS5; break;
//case MGN_MCS6: ret = DESC_RATEMCS6; break;
//case MGN_MCS7: ret = DESC_RATEMCS7; break;
default: break;
}
return ret;
}
void HalSetBrateCfg(
PADAPTER Adapter,
u8 *mBratesOS,
u16 *pBrateCfg)
{
u8 i, is_brate, brate;
for(i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++)
{
is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
brate = mBratesOS[i] & 0x7f;
if( is_brate )
{
switch(brate)
{
case IEEE80211_CCK_RATE_1MB: *pBrateCfg |= RATE_1M; break;
case IEEE80211_CCK_RATE_2MB: *pBrateCfg |= RATE_2M; break;
case IEEE80211_CCK_RATE_5MB: *pBrateCfg |= RATE_5_5M;break;
case IEEE80211_CCK_RATE_11MB: *pBrateCfg |= RATE_11M; break;
case IEEE80211_OFDM_RATE_6MB: *pBrateCfg |= RATE_6M; break;
case IEEE80211_OFDM_RATE_9MB: *pBrateCfg |= RATE_9M; break;
case IEEE80211_OFDM_RATE_12MB: *pBrateCfg |= RATE_12M; break;
case IEEE80211_OFDM_RATE_18MB: *pBrateCfg |= RATE_18M; break;
case IEEE80211_OFDM_RATE_24MB: *pBrateCfg |= RATE_24M; break;
case IEEE80211_OFDM_RATE_36MB: *pBrateCfg |= RATE_36M; break;
case IEEE80211_OFDM_RATE_48MB: *pBrateCfg |= RATE_48M; break;
case IEEE80211_OFDM_RATE_54MB: *pBrateCfg |= RATE_54M; break;
}
}
}
}
void hal_init_macaddr(_adapter *adapter)
{
rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
#ifdef CONFIG_CONCURRENT_MODE
if (adapter->pbuddy_adapter)
rtw_hal_set_hwreg(adapter->pbuddy_adapter, HW_VAR_MAC_ADDR, adapter->pbuddy_adapter->eeprompriv.mac_addr);
#endif
}
/*
* C2H event format:
* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
*/
void c2h_evt_clear(_adapter *adapter)
{
rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
}
s32 c2h_evt_read(_adapter *adapter, u8 *buf)
{
s32 ret = _FAIL;
struct c2h_evt_hdr *c2h_evt;
int i;
u8 trigger;
if (buf == NULL)
goto exit;
trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
if (trigger == C2H_EVT_HOST_CLOSE) {
goto exit; /* Not ready */
} else if (trigger != C2H_EVT_FW_CLOSE) {
goto clear_evt; /* Not a valid value */
}
c2h_evt = (struct c2h_evt_hdr *)buf;
_rtw_memset(c2h_evt, 0, 16);
*buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
*(buf+1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);
RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ",
&c2h_evt , sizeof(c2h_evt));
if (0) {
DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
, c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
}
/* Read the content */
for (i = 0; i < c2h_evt->plen; i++)
c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
c2h_evt->payload, c2h_evt->plen);
ret = _SUCCESS;
clear_evt:
/*
* Clear event to notify FW we have read the command.
* If this field isn't clear, the FW won't update the next command message.
*/
c2h_evt_clear(adapter);
exit:
return ret;
}
void SetHwReg(_adapter *adapter, HW_VARIABLES variable, u8 *val)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct dm_priv *dm = &(hal_data->dmpriv);
switch (variable) {
case HW_VAR_SEC_CFG:
{
#if defined(CONFIG_CONCURRENT_MODE) && !defined(DYNAMIC_CAMID_ALLOC)
// enable tx enc and rx dec engine, and no key search for MC/BC
rtw_write8(adapter, REG_SECCFG, SCR_NoSKMC|SCR_RxDecEnable|SCR_TxEncEnable);
#elif defined(DYNAMIC_CAMID_ALLOC)
u16 reg_scr;
reg_scr = rtw_read16(adapter, REG_SECCFG);
rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
#else
rtw_write8(adapter, REG_SECCFG, *((u8*)val));
#endif
}
break;
case HW_VAR_SEC_DK_CFG:
{
struct security_priv *sec = &adapter->securitypriv;
u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
if (val) /* Enable default key related setting */
{
reg_scr |= SCR_TXBCUSEDK;
if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
}
else /* Disable default key related setting */
{
reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
}
rtw_write8(adapter, REG_SECCFG, reg_scr);
}
break;
case HW_VAR_DM_FLAG:
dm->DMFlag = *((u8*)val);
break;
case HW_VAR_ENC_BMC_ENABLE:
{
u8 seccfg;
struct security_priv *psecuritypriv = &adapter->securitypriv;
//enable MC/BC hw decrypt
seccfg = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf;
rtw_write8(adapter, REG_SECCFG, seccfg);
break;
}
case HW_VAR_ENC_BMC_DISABLE:
{
struct security_priv *psecuritypriv = &adapter->securitypriv;
rtw_write8(adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC
break;
}
case HW_VAR_CHECK_TXBUF:
{
u8 retry_limit;
u16 val16;
u32 reg_200 = 0, reg_204 = 0;
u32 init_reg_200 = 0, init_reg_204 = 0;
u32 start = rtw_get_current_time();
u32 pass_ms;
int i = 0;
retry_limit = 0x01;
val16 = retry_limit << RETRY_LIMIT_SHORT_SHIFT | retry_limit << RETRY_LIMIT_LONG_SHIFT;
rtw_write16(adapter, REG_RL, val16);
while (rtw_get_passing_time_ms(start) < 2000
&& !adapter->bDriverStopped && !adapter->bSurpriseRemoved
) {
reg_200 = rtw_read32(adapter, 0x200);
reg_204 = rtw_read32(adapter, 0x204);
if (i == 0) {
init_reg_200 = reg_200;
init_reg_204 = reg_204;
}
i++;
if ((reg_200 & 0x00ffffff) != (reg_204 & 0x00ffffff)) {
//DBG_871X("%s: (HW_VAR_CHECK_TXBUF)TXBUF NOT empty - 0x204=0x%x, 0x200=0x%x (%d)\n", __FUNCTION__, reg_204, reg_200, i);
rtw_msleep_os(10);
} else {
break;
}
}
pass_ms = rtw_get_passing_time_ms(start);
if (adapter->bDriverStopped || adapter->bSurpriseRemoved) {
} else if (pass_ms >= 2000 || (reg_200 & 0x00ffffff) != (reg_204 & 0x00ffffff)) {
DBG_871X_LEVEL(_drv_always_, "%s:(HW_VAR_CHECK_TXBUF)NOT empty(%d) in %d ms\n", __FUNCTION__, i, pass_ms);
DBG_871X_LEVEL(_drv_always_, "%s:(HW_VAR_CHECK_TXBUF)0x200=0x%08x, 0x204=0x%08x (0x%08x, 0x%08x)\n",
__FUNCTION__, reg_200, reg_204, init_reg_200, init_reg_204);
//rtw_warn_on(1);
} else {
DBG_871X("%s:(HW_VAR_CHECK_TXBUF)TXBUF Empty(%d) in %d ms\n", __FUNCTION__, i, pass_ms);
}
retry_limit = 0x30;
val16 = retry_limit << RETRY_LIMIT_SHORT_SHIFT | retry_limit << RETRY_LIMIT_LONG_SHIFT;
rtw_write16(adapter, REG_RL, val16);
}
break;
default:
if(0)
DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HW_VARIABLES(%d) not defined!\n", __FUNCTION__, variable);
break;
}
}
void GetHwReg(_adapter *adapter, HW_VARIABLES variable, u8 *val)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct dm_priv *dm = &(hal_data->dmpriv);
switch (variable) {
case HW_VAR_DM_FLAG:
*((u8*)val) = dm->DMFlag;
break;
default:
if(0)
DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HW_VARIABLES(%d) not defined!\n", __FUNCTION__, variable);
break;
}
}
u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct dm_priv *dm = &(hal_data->dmpriv);
u8 bResult = _SUCCESS;
switch(variable) {
case HAL_DEF_DBG_DM_FUNC:
{
u8 dm_func = *((u8*)val);
if (dm_func == 0){ //disable all dynamic func
dm->DMFlag = DYNAMIC_FUNC_DISABLE;
DBG_8192C("==> Disable all dynamic function...\n");
}
else if (dm_func == 1){//disable DIG
dm->DMFlag &= (~DYNAMIC_FUNC_DIG);
DBG_8192C("==> Disable DIG...\n");
}
else if (dm_func == 2){//disable High power
dm->DMFlag &= (~DYNAMIC_FUNC_HP);
}
else if (dm_func == 3){//disable tx power tracking
dm->DMFlag &= (~DYNAMIC_FUNC_SS);
DBG_8192C("==> Disable tx power tracking...\n");
}
else if (dm_func == 4){//disable BT coexistence
dm->DMFlag &= (~DYNAMIC_FUNC_BT);
}
else if (dm_func == 5){//disable antenna diversity
dm->DMFlag &= (~DYNAMIC_FUNC_ANT_DIV);
}
else if (dm_func == 6){//turn on all dynamic func
if (!(dm->DMFlag & DYNAMIC_FUNC_DIG)) {
DIG_T *pDigTable = &dm->DM_DigTable;
pDigTable->PreIGValue = rtw_read8(adapter, 0xc50);
}
dm->DMFlag |= (DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS|
DYNAMIC_FUNC_BT|DYNAMIC_FUNC_ANT_DIV) ;
DBG_8192C("==> Turn on all dynamic function...\n");
}
}
break;
default:
if(0)
DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
bResult = _FAIL;
break;
}
return bResult;
}
u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct dm_priv *dm = &(hal_data->dmpriv);
u8 bResult = _SUCCESS;
switch(variable) {
case HAL_DEF_DBG_DM_FUNC:
*((u8*)val) = dm->DMFlag;
break;
default:
if(0)
DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
bResult = _FAIL;
break;
}
return bResult;
}
//bus-agg check for SoftAP mode
inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter,u8 pre_qsel,u8 next_qsel)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
u8 chk_rst = _SUCCESS;
if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
return chk_rst;
//if((pre_qsel == 0xFF)||(next_qsel== 0xFF))
// return chk_rst;
if( ((pre_qsel == QSLT_HIGH)||((next_qsel== QSLT_HIGH)))
&& (pre_qsel != next_qsel )){
//DBG_871X("### bus-agg break cause of qsel misatch, pre_qsel=0x%02x,next_qsel=0x%02x ###\n",
// pre_qsel,next_qsel);
chk_rst = _FAIL;
}
return chk_rst;
}

545
package/jsda/rtl8192du/hal/hal_intf.c
View File

@ -1,545 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _HAL_INTF_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_byteorder.h>
#include <hal_intf.h>
#include <usb_hal.h>
void rtw_hal_chip_configure(_adapter *padapter)
{
if(padapter->HalFunc.intf_chip_configure)
padapter->HalFunc.intf_chip_configure(padapter);
}
void rtw_hal_read_chip_info(_adapter *padapter)
{
if(padapter->HalFunc.read_adapter_info)
padapter->HalFunc.read_adapter_info(padapter);
}
void rtw_hal_read_chip_version(_adapter *padapter)
{
if(padapter->HalFunc.read_chip_version)
padapter->HalFunc.read_chip_version(padapter);
}
void rtw_hal_def_value_init(_adapter *padapter)
{
if(padapter->HalFunc.init_default_value)
padapter->HalFunc.init_default_value(padapter);
}
void rtw_hal_free_data(_adapter *padapter)
{
if(padapter->HalFunc.free_hal_data)
padapter->HalFunc.free_hal_data(padapter);
}
void rtw_hal_dm_init(_adapter *padapter)
{
if(padapter->HalFunc.dm_init)
padapter->HalFunc.dm_init(padapter);
}
void rtw_hal_dm_deinit(_adapter *padapter)
{
// cancel dm timer
if(padapter->HalFunc.dm_deinit)
padapter->HalFunc.dm_deinit(padapter);
}
void rtw_hal_sw_led_init(_adapter *padapter)
{
if(padapter->HalFunc.InitSwLeds)
padapter->HalFunc.InitSwLeds(padapter);
}
void rtw_hal_sw_led_deinit(_adapter *padapter)
{
if(padapter->HalFunc.DeInitSwLeds)
padapter->HalFunc.DeInitSwLeds(padapter);
}
uint rtw_hal_init(_adapter *padapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
int i;
uint status = _SUCCESS;
if(padapter->hw_init_completed == _TRUE)
{
DBG_871X("rtw_hal_init: hw_init_completed == _TRUE\n");
goto success;
}
#ifdef CONFIG_DEINIT_BEFORE_INIT
status = padapter->HalFunc.hal_deinit(padapter);
if(status != _SUCCESS){
DBG_871X("rtw_hal_init: hal_deinit before hal_init FAIL !!\n");
goto fail;
}
#endif
#ifdef CONFIG_DUALMAC_CONCURRENT
// before init mac0, driver must init mac1 first to avoid usb rx error.
if((padapter->pbuddy_adapter != NULL) && (padapter->DualMacConcurrent == _TRUE)
&& (padapter->adapter_type == PRIMARY_ADAPTER))
{
if(padapter->pbuddy_adapter->hw_init_completed == _TRUE)
{
DBG_871X("rtw_hal_init: pbuddy_adapter hw_init_completed == _TRUE\n");
}
else
{
#ifdef CONFIG_DEINIT_BEFORE_INIT
status = padapter->HalFunc.hal_deinit(padapter->pbuddy_adapter);
if(status != _SUCCESS){
DBG_871X("rtw_hal_init: hal_deinit before hal_init FAIL !!(pbuddy_adapter)\n");
goto fail;
}
#endif
status = padapter->HalFunc.hal_init(padapter->pbuddy_adapter);
if(status == _SUCCESS){
padapter->pbuddy_adapter->hw_init_completed = _TRUE;
}
else{
padapter->pbuddy_adapter->hw_init_completed = _FALSE;
RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail(pbuddy_adapter)\n"));
goto fail;
}
}
}
#else
if(adapter_to_dvobj(padapter)->DualMacMode == _TRUE)
{
if(padapter->pbuddy_adapter != NULL) {
if(padapter->pbuddy_adapter->hw_init_completed == _FALSE)
{
#ifdef CONFIG_DEINIT_BEFORE_INIT
status = padapter->HalFunc.hal_deinit(padapter->pbuddy_adapter);
if(status != _SUCCESS){
DBG_871X("rtw_hal_init: hal_deinit before hal_init FAIL !!(pbuddy_adapter)\n");
goto fail;
}
#endif
status = padapter->HalFunc.hal_init(padapter->pbuddy_adapter);
if(status == _SUCCESS){
padapter->pbuddy_adapter->hw_init_completed = _TRUE;
}
else{
padapter->pbuddy_adapter->hw_init_completed = _FALSE;
RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail for another interface\n"));
}
}
}
}
#endif
padapter->hw_init_completed=_FALSE;
status = padapter->HalFunc.hal_init(padapter);
if(status == _SUCCESS){
padapter->hw_init_completed = _TRUE;
}
else{
padapter->hw_init_completed = _FALSE;
RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail\n"));
goto fail;
}
success:
if (padapter->registrypriv.notch_filter == 1)
rtw_hal_notch_filter(padapter, 1);
rtw_hal_reset_security_engine(padapter);
for (i = 0; i<dvobj->iface_nums; i++)
rtw_sec_restore_wep_key(dvobj->padapters[i]);
rtw_led_control(padapter, LED_CTL_POWER_ON);
init_hw_mlme_ext(padapter);
fail:
RT_TRACE(_module_hal_init_c_,_drv_err_,("-rtl871x_hal_init:status=0x%x\n",status));
return status;
}
uint rtw_hal_deinit(_adapter *padapter)
{
uint status = _SUCCESS;
_func_enter_;
status = padapter->HalFunc.hal_deinit(padapter);
if(status == _SUCCESS){
rtw_led_control(padapter, LED_CTL_POWER_OFF);
padapter->hw_init_completed = _FALSE;
}
else
{
RT_TRACE(_module_hal_init_c_,_drv_err_,("\n rtw_hal_deinit: hal_init fail\n"));
}
_func_exit_;
return status;
}
void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
{
if (padapter->HalFunc.SetHwRegHandler)
padapter->HalFunc.SetHwRegHandler(padapter, variable, val);
}
void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
{
if (padapter->HalFunc.GetHwRegHandler)
padapter->HalFunc.GetHwRegHandler(padapter, variable, val);
}
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
{
if(padapter->HalFunc.SetHalDefVarHandler)
return padapter->HalFunc.SetHalDefVarHandler(padapter,eVariable,pValue);
return _FAIL;
}
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
{
if(padapter->HalFunc.GetHalDefVarHandler)
return padapter->HalFunc.GetHalDefVarHandler(padapter,eVariable,pValue);
return _FAIL;
}
void rtw_hal_enable_interrupt(_adapter *padapter)
{
if (padapter->HalFunc.enable_interrupt)
padapter->HalFunc.enable_interrupt(padapter);
else
DBG_871X("%s: HalFunc.enable_interrupt is NULL!\n", __FUNCTION__);
}
void rtw_hal_disable_interrupt(_adapter *padapter)
{
if (padapter->HalFunc.disable_interrupt)
padapter->HalFunc.disable_interrupt(padapter);
else
DBG_871X("%s: HalFunc.disable_interrupt is NULL!\n", __FUNCTION__);
}
u32 rtw_hal_inirp_init(_adapter *padapter)
{
u32 rst = _FAIL;
if(padapter->HalFunc.inirp_init)
rst = padapter->HalFunc.inirp_init(padapter);
else
DBG_871X(" %s HalFunc.inirp_init is NULL!!!\n",__FUNCTION__);
return rst;
}
u32 rtw_hal_inirp_deinit(_adapter *padapter)
{
if(padapter->HalFunc.inirp_deinit)
return padapter->HalFunc.inirp_deinit(padapter);
return _FAIL;
}
u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val)
{
if(padapter->HalFunc.interface_ps_func)
return padapter->HalFunc.interface_ps_func(padapter,efunc_id,val);
return _FAIL;
}
s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
{
if(padapter->HalFunc.hal_xmitframe_enqueue)
return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe);
return _FALSE;
}
s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
{
if(padapter->HalFunc.hal_xmit)
return padapter->HalFunc.hal_xmit(padapter, pxmitframe);
return _FALSE;
}
s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
{
s32 ret = _FAIL;
unsigned char *pframe;
struct rtw_ieee80211_hdr *pwlanhdr;
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
_rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN);
#ifdef CONFIG_IEEE80211W
if(padapter->securitypriv.binstallBIPkey == _TRUE)
{
if(IS_MCAST(pmgntframe->attrib.ra))
{
pmgntframe->attrib.encrypt = _BIP_;
//pmgntframe->attrib.bswenc = _TRUE;
}
else
{
pmgntframe->attrib.encrypt = _AES_;
pmgntframe->attrib.bswenc = _TRUE;
}
rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
}
#endif //CONFIG_IEEE80211W
if(padapter->HalFunc.mgnt_xmit)
ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
return ret;
}
s32 rtw_hal_init_xmit_priv(_adapter *padapter)
{
if(padapter->HalFunc.init_xmit_priv != NULL)
return padapter->HalFunc.init_xmit_priv(padapter);
return _FAIL;
}
void rtw_hal_free_xmit_priv(_adapter *padapter)
{
if(padapter->HalFunc.free_xmit_priv != NULL)
padapter->HalFunc.free_xmit_priv(padapter);
}
s32 rtw_hal_init_recv_priv(_adapter *padapter)
{
if(padapter->HalFunc.init_recv_priv)
return padapter->HalFunc.init_recv_priv(padapter);
return _FAIL;
}
void rtw_hal_free_recv_priv(_adapter *padapter)
{
if(padapter->HalFunc.free_recv_priv)
padapter->HalFunc.free_recv_priv(padapter);
}
void rtw_hal_update_ra_mask(_adapter *padapter, u32 mac_id)
{
if(padapter->HalFunc.UpdateRAMaskHandler)
padapter->HalFunc.UpdateRAMaskHandler(padapter,mac_id);
}
void rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 arg)
{
if(padapter->HalFunc.Add_RateATid)
padapter->HalFunc.Add_RateATid(padapter, bitmap, arg);
}
u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
if (padapter->HalFunc.read_bbreg)
data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask);
return data;
}
void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
{
if (padapter->HalFunc.write_bbreg)
padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
}
u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
if (padapter->HalFunc.read_rfreg)
data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
return data;
}
void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
{
if (padapter->HalFunc.write_rfreg)
padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
}
s32 rtw_hal_interrupt_handler(_adapter *padapter)
{
if(padapter->HalFunc.interrupt_handler)
return padapter->HalFunc.interrupt_handler(padapter);
return _FAIL;
}
void rtw_hal_set_bwmode(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset)
{
if(padapter->HalFunc.set_bwmode_handler)
padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset);
}
void rtw_hal_set_chan(_adapter *padapter, u8 channel)
{
if(padapter->HalFunc.set_channel_handler)
padapter->HalFunc.set_channel_handler(padapter, channel);
}
void rtw_hal_dm_watchdog(_adapter *padapter)
{
if(padapter->HalFunc.hal_dm_watchdog)
padapter->HalFunc.hal_dm_watchdog(padapter);
}
void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
{
if(padapter->HalFunc.SetBeaconRelatedRegistersHandler)
padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter);
}
#ifdef CONFIG_ANTENNA_DIVERSITY
u8 rtw_hal_antdiv_before_linked(_adapter *padapter)
{
if (padapter->HalFunc.AntDivBeforeLinkHandler)
return padapter->HalFunc.AntDivBeforeLinkHandler(padapter);
return _FALSE;
}
void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
{
if (padapter->HalFunc.AntDivCompareHandler)
padapter->HalFunc.AntDivCompareHandler(padapter, dst, src);
}
#endif
#ifdef CONFIG_HOSTAPD_MLME
s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
{
if (padapter->HalFunc.hostap_mgnt_xmit_entry)
return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt);
return _FAIL;
}
#endif //CONFIG_HOSTAPD_MLME
#ifdef DBG_CONFIG_ERROR_DETECT
void rtw_hal_sreset_init(_adapter *padapter)
{
if(padapter->HalFunc.sreset_init_value)
padapter->HalFunc.sreset_init_value(padapter);
}
void rtw_hal_sreset_reset(_adapter *padapter)
{
padapter = GET_PRIMARY_ADAPTER(padapter);
if(padapter->HalFunc.silentreset)
padapter->HalFunc.silentreset(padapter);
}
void rtw_hal_sreset_reset_value(_adapter *padapter)
{
if(padapter->HalFunc.sreset_reset_value)
padapter->HalFunc.sreset_reset_value(padapter);
}
void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
{
#ifdef CONFIG_CONCURRENT_MODE
if (padapter->adapter_type != PRIMARY_ADAPTER)
return;
#endif
if(padapter->HalFunc.sreset_xmit_status_check)
padapter->HalFunc.sreset_xmit_status_check(padapter);
}
void rtw_hal_sreset_linked_status_check(_adapter *padapter)
{
if(padapter->HalFunc.sreset_linked_status_check)
padapter->HalFunc.sreset_linked_status_check(padapter);
}
u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
{
u8 status = 0;
if(padapter->HalFunc.sreset_get_wifi_status)
status = padapter->HalFunc.sreset_get_wifi_status(padapter);
return status;
}
bool rtw_hal_sreset_inprogress(_adapter *padapter)
{
bool inprogress = _FALSE;
padapter = GET_PRIMARY_ADAPTER(padapter);
if(padapter->HalFunc.sreset_inprogress)
inprogress = padapter->HalFunc.sreset_inprogress(padapter);
return inprogress;
}
#endif //DBG_CONFIG_ERROR_DETECT
#ifdef CONFIG_IOL
int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms)
{
if (adapter->HalFunc.IOL_exec_cmds_sync)
return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms);
return _FAIL;
}
#endif
void rtw_hal_notch_filter(_adapter *adapter, bool enable)
{
if(adapter->HalFunc.hal_notch_filter)
adapter->HalFunc.hal_notch_filter(adapter,enable);
}
void rtw_hal_reset_security_engine(_adapter * adapter)
{
if(adapter->HalFunc.hal_reset_security_engine)
adapter->HalFunc.hal_reset_security_engine(adapter);
}
s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt)
{
s32 ret = _FAIL;
if (adapter->HalFunc.c2h_handler)
ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt);
return ret;
}
c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter)
{
return adapter->HalFunc.c2h_id_filter_ccx;
}

69
package/jsda/rtl8192du/hal/odm_RegDefine11AC.h
View File

@ -1,69 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
//2 RF REG LIST
//2 BB REG LIST
//PAGE 8
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
#define ODM_REG_BB_RX_PATH_11AC 0x808
#define ODM_REG_DBG_RPT_11AC 0x8fc
//PAGE 9
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
#define ODM_REG_NHM_TIMER_11AC 0x990
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
#define ODM_REG_NHM_TH8_11AC 0x9a0
#define ODM_REG_NHM_9E8_11AC 0x9e8
//PAGE A
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
//PAGE C
#define ODM_REG_TRMUX_11AC 0xC08
#define ODM_REG_IGI_A_11AC 0xC50
//PAGE E
#define ODM_REG_IGI_B_11AC 0xE50
//PAGE F
#define ODM_REG_OFDM_FA_11AC 0xF48
#define ODM_REG_RPT_11AC 0xfa0
#define ODM_REG_NHM_CNT_11AC 0xfa8
//PAGE 18
#define ODM_REG_IGI_C_11AC 0x1850
//PAGE 1A
#define ODM_REG_IGI_D_11AC 0x1A50
//2 MAC REG LIST
#define ODM_REG_RESP_TX_11AC 0x6D8
//DIG Related
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
#define ODM_BIT_BB_RX_PATH_11AC 0xF
#endif

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package/jsda/rtl8192du/hal/odm_RegDefine11N.h
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@ -1,178 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
//2 RF REG LIST
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
//2 BB REG LIST
//PAGE 8
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_NHM_TIMER_11N 0x894
#define ODM_REG_NHM_TH9_TH10_11N 0x890
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
#define ODM_REG_NHM_CNT_11N 0x8d8
//PAGE 9
#define ODM_REG_DBG_RPT_11N 0x908
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
//PAGE A
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
//PAGE B
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
//PAGE C
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_BB_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
//PAGE D
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
#define ODM_REG_RPT_11N 0xDF4
//PAGE E
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
#define ODM_REG_IGI_C_11N 0xF84
#define ODM_REG_IGI_D_11N 0xF88
//2 MAC REG LIST
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
//DIG Related
#define ODM_BIT_IGI_11N 0x0000007F
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
#define ODM_BIT_BB_RX_PATH_11N 0xF
#endif

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package/jsda/rtl8192du/hal/odm_debug.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define ODM_DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
#define ODM_COMP_MP BIT14
#define ODM_COMP_DYNAMIC_ATC BIT15
//MAC Functions
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
//RF Functions
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define RT_PRINTK DbgPrint
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#define RT_DISP(dbgtype, dbgflag, printstr)
#else
#define DbgPrint panic_printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#define ODM_DBG 1
#if ODM_DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if(!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
RT_PRINTK fmt; \
ASSERT(FALSE); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#else
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
#define ODM_dbg_enter()
#define ODM_dbg_exit()
#define ODM_dbg_trace(str)
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID ODM_InitDebugSetting(PDM_ODM_T pDM_Odm);
#if 0
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif
#if 0
/* Define debug print header for every service module.*/
typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}ODM_DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_ODM_DBGP_Flag_Type_Definition
{
ODM_FTX = 0,
ODM_FRX ,
ODM_FPHY ,
ODM_FPWR ,
ODM_FDM ,
ODM_FC2H ,
ODM_FBT ,
ODM_DBGP_TYPE_MAX
}ODM_DBGP_FLAG_E;
// Define TX relative debug bit --> FTX
#define ODM_TX_DESC BIT0
#define ODM_TX_DESC_TID BIT1
#define ODM_TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define ODM_RX_DATA BIT0
#define ODM_RX_PHY_STS BIT1
#define ODM_RX_PHY_SS BIT2
#define ODM_RX_PHY_SQ BIT3
#define ODM_RX_PHY_ASTS BIT4
#define ODM_RX_ERR_LEN BIT5
#define ODM_RX_DEFRAG BIT6
#define ODM_RX_ERR_RATE BIT7
#define ODM_RX_PATH BIT8
#define ODM_RX_BEACON BIT9
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define ODM_PHY_BBR BIT0
#define ODM_PHY_BBW BIT1
#define ODM_PHY_RFR BIT2
#define ODM_PHY_RFW BIT3
#define ODM_PHY_MACR BIT4
#define ODM_PHY_MACW BIT5
#define ODM_PHY_ALLR BIT6
#define ODM_PHY_ALLW BIT7
#define ODM_PHY_TXPWR BIT8
#define ODM_PHY_PWRDIFF BIT9
#define ODM_PHY_SICR BIT10
#define ODM_PHY_SICW BIT11
extern u4Byte ODM_GlobalDebugLevel;
#if DBG
extern u8Byte ODM_GlobalDebugComponents;
#endif
#endif
#if 0
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
//
#define DBG_OFF 0
//
// Deprecated! Don't use it!
// TODO: fix related debug message!
//
//#define DBG_SEC 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
#define COMP_TRACE BIT0 // For function call tracing.
#define COMP_DBG BIT1 // Only for temporary debug message.
#define COMP_INIT BIT2 // during driver initialization / halt / reset.
#define COMP_OID_QUERY BIT3 // Query OID.
#define COMP_OID_SET BIT4 // Set OID.
#define COMP_RECV BIT5 // Reveive part data path.
#define COMP_SEND BIT6 // Send part path.
#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02.
#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related.
#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS.
#define COMP_SCAN BIT10 // For site survey.
#define COMP_SYSTEM BIT11 // For general platform function.
#define COMP_SEC BIT12 // For Security.
#define COMP_AP BIT13 // For AP mode related.
#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21.
#define COMP_QOS BIT15 // For QoS.
#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30.
#define COMP_BEACON BIT17 // For Beacon related, by rcnjko.
#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko.
#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
#define COMP_EVENTS BIT20 // Event handling
#define COMP_FPGA BIT21 // For FPGA verfication
#define COMP_RM BIT22 // For Radio Measurement.
#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13
#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko.
#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko.
#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko.
#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko.
#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW.
#define COMP_INDIC BIT31 // For link indication
#define COMP_LED BIT32 // For LED.
#define COMP_RF BIT33 // For RF.
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11
#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING
#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder
#define COMP_AMSDU BIT37 // For A-MSDU Debugging
#define COMP_WPS BIT38 //WPS Debug Message
#define COMP_RATR BIT39
#define COMP_RESET BIT40
// For debug command to print on dbgview!!
#define COMP_CMD BIT41
#define COMP_EFUSE BIT42
#define COMP_MESH_INTERWORKING BIT43
#define COMP_CCX BIT44 //CCX Debug Flag
#define COMP_IOCTL BIT45 // IO Control
#define COMP_GP BIT46 // For generic parser.
#define COMP_TXAGG BIT47
#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
#define COMP_TEST BIT49
#define COMP_BB_POWERSAVING BIT50
#define COMP_SWAS BIT51 // For SW Antenna Switch
#define COMP_P2P BIT52
#define COMP_MUX BIT53
#define COMP_FUNC BIT54
#define COMP_TDLS BIT55
#define COMP_OMNIPEEK BIT56
#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug
#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug
#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH
#define COMP_DFS BIT62
#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
// For debug print flag to use
/*------------------------------Define structure----------------------------*/
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/* Defnie structure to store different debug flag variable. Every debug flag
is a UINT32 integer and you can assign 32 different events. */
typedef struct tag_DBGP_Debug_Flag_Structure
{
u4Byte Mans; /* Main Scheduler module. */
u4Byte Rtos; /* RTOS module. */
u4Byte Alarm; /* Alarm module. */
u4Byte Pm; /* Performance monitor module. */
}DBGP_FLAG_T;
/* Define debug print header for every service module.*/
typedef struct tag_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_DBGP_Flag_Type_Definition
{
FQoS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBG_CTRL = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
FSHORT_CUT = 19,
DBGP_TYPE_MAX
}DBGP_FLAG_E;
// Define Qos Relative debug flag bit --> FQoS
#define QoS_INIT BIT0
#define QoS_VISTA BIT1
// Define TX relative debug bit --> FTX
#define TX_DESC BIT0
#define TX_DESC_TID BIT1
#define TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define RX_DATA BIT0
#define RX_PHY_STS BIT1
#define RX_PHY_SS BIT2
#define RX_PHY_SQ BIT3
#define RX_PHY_ASTS BIT4
#define RX_ERR_LEN BIT5
#define RX_DEFRAG BIT6
#define RX_ERR_RATE BIT7
#define RX_PATH BIT8
#define RX_BEACON BIT9
// Define Security relative debug bit --> FSEC
// Define MGNT relative debug bit --> FMGNT
// Define MLME relative debug bit --> FMLME
#define MEDIA_STS BIT0
#define LINK_STS BIT1
// Define OS resource check module bit --> FRESOURCE
#define OS_CHK BIT0
// Define beacon content check module bit --> FBEACON
#define BCN_SHOW BIT0
#define BCN_PEER BIT1
// Define ISR/IMR check module bit --> FISR
#define ISR_CHK BIT0
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define PHY_BBR BIT0
#define PHY_BBW BIT1
#define PHY_RFR BIT2
#define PHY_RFW BIT3
#define PHY_MACR BIT4
#define PHY_MACW BIT5
#define PHY_ALLR BIT6
#define PHY_ALLW BIT7
#define PHY_TXPWR BIT8
#define PHY_PWRDIFF BIT9
#define PHY_SICR BIT10
#define PHY_SICW BIT11
// Define MPT driver check module bit --> FMP
#define MP_RX BIT0
#define MP_SWICH_CH BIT1
// Define EEPROM and EFUSE check module bit --> FEEPROM
#define EEPROM_W BIT0
#define EFUSE_PG BIT1
#define EFUSE_READ_ALL BIT2
#define EFUSE_ANALYSIS BIT3
#define EFUSE_PG_DETAIL BIT4
// Define power save check module bit --> FPWR
#define LPS BIT0
#define IPS BIT1
#define PWRSW BIT2
#define PWRHW BIT3
#define PWRHAL BIT4
// Define Dynamic Mechanism check module bit --> FDM
#define WA_IOT BIT0
#define DM_PWDB BIT1
#define DM_Monitor BIT2
#define DM_DIG BIT3
#define DM_EDCA_Turbo BIT4
#define DM_BT30 BIT5
// Define Dbg Control module bit --> FDBG_CTRL
#define DBG_CTRL_TRACE BIT0
#define DBG_CTRL_INBAND_NOISE BIT1
// Define FW C2H Cmd check module bit --> FC2H
#define C2H_Summary BIT0
#define C2H_PacketData BIT1
#define C2H_ContentData BIT2
// Define BT Cmd check module bit --> FBT
#define BT_TRACE BIT0
#define BT_RFPoll BIT1
// Define init check for module bit --> FINIT
#define INIT_EEPROM BIT0
#define INIT_TxPower BIT1
#define INIT_IQK BIT2
#define INIT_RF BIT3
// Define IOCTL Cmd check module bit --> FIOCTL
// section 1 : IRP related
#define IOCTL_IRP BIT0
#define IOCTL_IRP_DETAIL BIT1
#define IOCTL_IRP_STATISTICS BIT2
#define IOCTL_IRP_HANDLE BIT3
// section 2 : HCI command/event
#define IOCTL_BT_HCICMD BIT8
#define IOCTL_BT_HCICMD_DETAIL BIT9
#define IOCTL_BT_HCICMD_EXT BIT10
#define IOCTL_BT_EVENT BIT11
#define IOCTL_BT_EVENT_DETAIL BIT12
#define IOCTL_BT_EVENT_PERIODICAL BIT13
// section 3 : BT tx/rx data and throughput
#define IOCTL_BT_TX_ACLDATA BIT16
#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17
#define IOCTL_BT_RX_ACLDATA BIT18
#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19
#define IOCTL_BT_TP BIT20
// section 4 : BT connection state machine.
#define IOCTL_STATE BIT21
#define IOCTL_BT_LOGO BIT22
// section 5 : BT function trace
#define IOCTL_CALLBACK_FUN BIT24
#define IOCTL_PARSE_BT_PKT BIT25
#define IOCTL_BT_TX_PKT BIT26
#define IOCTL_BT_FLAG_MON BIT27
//
// Define init check for module bit --> FSHORT_CUT
// 2011/07/20 MH Add for short but definition.
//
#define SHCUT_TX BIT0
#define SHCUT_RX BIT1
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args);
#if DBG
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_TRACE_F(comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_ASSERT(expr,fmt) \
if(!(expr)) { \
printk( "Assertion failed! %s at ......\n", #expr); \
printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
}
#define dbg_enter() { printk("==> %s\n", __FUNCTION__); }
#define dbg_exit() { printk("<== %s\n", __FUNCTION__); }
#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); }
#else
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
#define RT_TRACE_F(comp, level, fmt)
#define RT_ASSERT(expr, fmt)
#define dbg_enter()
#define dbg_exit()
#define dbg_trace(str)
#endif
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define DEBUG_PRINT 1
// Please add new OS's print API by yourself
#if (DEBUG_PRINT == 1) && DBG
#define RT_DISP(dbgtype, dbgflag, printstr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
DbgPrint printstr;\
}\
}
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint printstr; \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}\
}
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\
if (((__i + 1) % 16) == 0) DbgPrint("\n");\
} \
DbgPrint("\n"); \
}\
}
#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__))
#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__))
#else
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
#define FunctionIn(_comp)
#define FunctionOut(_comp)
#endif
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export global variable----------------------------*/
extern u4Byte DBGP_Type[DBGP_TYPE_MAX];
extern DBGP_HEAD_T DBGP_Head;
/*------------------------Export global variable----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
extern void DBGP_Flag_Init(void);
extern void DBG_PrintAllFlag(void);
extern void DBG_PrintAllComp(void);
extern void DBG_PrintFlagEvent(u1Byte DbgFlag);
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len);
/*--------------------------Exported Function prototype---------------------*/
extern u4Byte GlobalDebugLevel;
extern u8Byte GlobalDebugComponents;
#endif
#endif // __ODM_DBG_H__

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package/jsda/rtl8192du/hal/rtl8192d_cmd.c
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package/jsda/rtl8192du/hal/rtl8192d_dm.c
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package/jsda/rtl8192du/hal/rtl8192d_hal_init.c
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package/jsda/rtl8192du/hal/rtl8192d_mp.c
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package/jsda/rtl8192du/hal/rtl8192d_rxdesc.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8192C_REDESC_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8192d_hal.h>
static u8 evm_db2percentage(s8 value)
{
//
// -33dB~0dB to 0%~99%
//
s8 ret_val;
ret_val = value;
//ret_val /= 2;
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("EVMdbToPercentage92S Value=%d / %x \n", ret_val, ret_val));
if(ret_val >= 0)
ret_val = 0;
if(ret_val <= -33)
ret_val = -33;
ret_val = 0 - ret_val;
ret_val*=3;
if(ret_val == 99)
ret_val = 100;
return(ret_val);
}
static s32 signal_scale_mapping(_adapter *padapter, s32 cur_sig )
{
s32 ret_sig;
if(cur_sig >= 51 && cur_sig <= 100)
ret_sig = 100;
else if(cur_sig >= 41 && cur_sig <= 50)
ret_sig = 80 + ((cur_sig - 40)*2);
else if(cur_sig >= 31 && cur_sig <= 40)
ret_sig = 66 + (cur_sig - 30);
else if(cur_sig >= 21 && cur_sig <= 30)
ret_sig = 54 + (cur_sig - 20);
else if(cur_sig >= 10 && cur_sig <= 20)
ret_sig = 42 + (((cur_sig - 10) * 2) / 3);
else if(cur_sig >= 5 && cur_sig <= 9)
ret_sig = 22 + (((cur_sig - 5) * 3) / 2);
else if(cur_sig >= 1 && cur_sig <= 4)
ret_sig = 6 + (((cur_sig - 1) * 3) / 2);
else
ret_sig = cur_sig;
return ret_sig;
}
static s32 translate2dbm(u8 signal_strength_idx)
{
s32 signal_power; // in dBm.
// Translate to dBm (x=0.5y-95).
signal_power = (s32)((signal_strength_idx + 1) >> 1);
signal_power -= 95;
return signal_power;
}
static void query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat, BOOLEAN bPacketMatchBSSID)
{
PHY_STS_OFDM_8192CD_T *pOfdm_buf;
PHY_STS_CCK_8192CD_T *pCck_buf;
u8 i, max_spatial_stream, evm;
s8 rx_pwr[4], rx_pwr_all=0;
u8 pwdb_all;
u32 rssi,total_rssi=0;
u8 bcck_rate=0, rf_rx_num = 0, cck_highpwr = 0;
_adapter *padapter = prframe->u.hdr.adapter;
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
u8 tmp_rxsnr;
s8 rx_snrX;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
bcck_rate=(pattrib->mcs_rate<=3? 1:0);
// Record it for next packet processing
pattrib->rx_mimo_signal_qual[0]= -1;
pattrib->rx_mimo_signal_qual[1]= -1;
if(bcck_rate) //CCK
{
u8 report;
// CCK Driver info Structure is not the same as OFDM packet.
pCck_buf = (PHY_STS_CCK_8192CD_T *)pphy_stat;
//Adapter->RxStats.NumQryPhyStatusCCK++;
//
// (1)Hardware does not provide RSSI for CCK
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
if(padapter->pwrctrlpriv.rf_pwrstate == rf_on)
cck_highpwr = (u8)pHalData->bCckHighPower;
else
cck_highpwr = _FALSE;
if(!cck_highpwr)
{
report = pCck_buf->cck_agc_rpt&0xc0;
report = report>>6;
switch(report)
{
// 03312009 modified by cosa
// Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion
// Note: different RF with the different RNA gain.
case 0x3:
rx_pwr_all = (-46) - (pCck_buf->cck_agc_rpt & 0x3e);
break;
case 0x2:
rx_pwr_all = (-26) - (pCck_buf->cck_agc_rpt & 0x3e);
break;
case 0x1:
rx_pwr_all = (-12) - (pCck_buf->cck_agc_rpt & 0x3e);
break;
case 0x0:
rx_pwr_all = (16) - (pCck_buf->cck_agc_rpt & 0x3e);
break;
}
}
else
{
report = pCck_buf->cck_agc_rpt & 0x60;
report = report>>5;
switch(report)
{
case 0x3:
rx_pwr_all = (-46) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ;
break;
case 0x2:
rx_pwr_all = (-26)- ((pCck_buf->cck_agc_rpt & 0x1f)<<1);
break;
case 0x1:
rx_pwr_all = (-12) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ;
break;
case 0x0:
rx_pwr_all = (16) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ;
break;
}
}
pwdb_all= query_rx_pwr_percentage(rx_pwr_all);
//if(pHalData->CustomerID == RT_CID_819x_Lenovo)
{
// CCK gain is smaller than OFDM/MCS gain,
// so we add gain diff by experiences, the val is 6
pwdb_all+=6;
if(pwdb_all > 100)
pwdb_all = 100;
// modify the offset to make the same gain index with OFDM.
if(pwdb_all > 34 && pwdb_all <= 42)
pwdb_all -= 2;
else if(pwdb_all > 26 && pwdb_all <= 34)
pwdb_all -= 6;
else if(pwdb_all > 14 && pwdb_all <= 26)
pwdb_all -= 8;
else if(pwdb_all > 4 && pwdb_all <= 14)
pwdb_all -= 4;
}
pattrib->RxPWDBAll = pwdb_all;
pattrib->RecvSignalPower = rx_pwr_all;
padapter->recvpriv.rxpwdb = rx_pwr_all;
//
// (3) Get Signal Quality (EVM)
//
if(bPacketMatchBSSID)
{
u8 sq;
if(pHalData->CustomerID == RT_CID_819x_Lenovo)
{
// mapping to 5 bars for vista signal strength
// signal quality in driver will be displayed to signal strength
// in vista.
if(pwdb_all >= 50)
sq = 100;
else if(pwdb_all >= 35 && pwdb_all < 50)
sq = 80;
else if(pwdb_all >= 22 && pwdb_all < 35)
sq = 60;
else if(pwdb_all >= 18 && pwdb_all < 22)
sq = 40;
else
sq = 20;
}
else
{
if(pwdb_all> 40)
{
sq = 100;
}
else
{
sq = pCck_buf->SQ_rpt;
if(pCck_buf->SQ_rpt > 64)
sq = 0;
else if (pCck_buf->SQ_rpt < 20)
sq= 100;
else
sq = ((64-sq) * 100) / 44;
}
}
pattrib->signal_qual=sq;
pattrib->rx_mimo_signal_qual[0]=sq;
pattrib->rx_mimo_signal_qual[1]=(-1);
}
}
else //OFDM/HT
{
pOfdm_buf = (PHY_STS_OFDM_8192CD_T *)pphy_stat;
//
// (1)Get RSSI for HT rate
//
for(i=0; i<pHalData->NumTotalRFPath; i++)
{
// 2008/01/30 MH we will judge RF RX path now.
if (pHalData->bRFPathRxEnable[i])
rf_rx_num++;
//else
//continue;
rx_pwr[i] = ((pOfdm_buf->trsw_gain_X[+i]&0x3F)*2) - 110;
if(check_fwstate(pmlmepriv, WIFI_STATION_STATE))
{
if(bPacketMatchBSSID)
padapter->recvpriv.RxRssi[i] = rx_pwr[i];
}
else
padapter->recvpriv.RxRssi[i] = rx_pwr[i];
/* Translate DBM to percentage. */
pattrib->rx_rssi[i] = rssi = query_rx_pwr_percentage(rx_pwr[i]);
total_rssi += rssi;
RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], rssi));
//Get Rx snr value in DB
tmp_rxsnr = pOfdm_buf->rxsnr_X[i];
rx_snrX = (s8)(tmp_rxsnr);
rx_snrX >>= 1;
padapter->recvpriv.RxSNRdB[i] = (int)rx_snrX;
/* Record Signal Strength for next packet */
if(bPacketMatchBSSID)
{
//pRfd->Status.RxMIMOSignalStrength[i] =(u8) rssi;
//The following is for lenovo signal strength in vista
if(pHalData->CustomerID == RT_CID_819x_Lenovo)
{
u8 SQ;
if(i == 0)
{
// mapping to 5 bars for vista signal strength
// signal quality in driver will be displayed to signal strength
// in vista.
if(rssi >= 50)
SQ = 100;
else if(rssi >= 35 && rssi < 50)
SQ = 80;
else if(rssi >= 22 && rssi < 35)
SQ = 60;
else if(rssi >= 18 && rssi < 22)
SQ = 40;
else
SQ = 20;
//DbgPrint("ofdm/mcs RSSI=%d\n", RSSI);
pattrib->signal_qual = SQ;
//DbgPrint("ofdm/mcs SQ = %d\n", pRfd->Status.SignalQuality);
}
}
}
}
//
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
rx_pwr_all = (((pOfdm_buf->pwdb_all) >> 1 )& 0x7f) -106;
pwdb_all = query_rx_pwr_percentage(rx_pwr_all);
RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("PWDB_ALL=%d\n", pwdb_all));
pattrib->RxPWDBAll = pwdb_all; //for DIG/rate adaptive
pattrib->RecvSignalPower = rx_pwr_all;
padapter->recvpriv.rxpwdb = rx_pwr_all;
//
// (3)EVM of HT rate
//
if(pHalData->CustomerID != RT_CID_819x_Lenovo)
{
if(pattrib->rxht && pattrib->mcs_rate >=20 && pattrib->mcs_rate<=27)
max_spatial_stream = 2; //both spatial stream make sense
else
max_spatial_stream = 1; //only spatial stream 1 makes sense
for(i=0; i<max_spatial_stream; i++)
{
// Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
// fill most significant bit to "zero" when doing shifting operation which may change a negative
// value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
evm = evm_db2percentage( (pOfdm_buf->rxevm_X[i] /*/ 2*/));//dbm
RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",
pattrib->mcs_rate, pOfdm_buf->rxevm_X[i], "%",evm));
if(bPacketMatchBSSID)
{
if(i==0) // Fill value in RFD, Get the first spatial stream only
{
pattrib->signal_qual = (u8)(evm & 0xff);
}
pattrib->rx_mimo_signal_qual[i] = (u8)(evm & 0xff);
}
}
}
//
// 4. Record rx statistics for debug
//
}
//UI BSS List signal strength(in percentage), make it good looking, from 0~100.
//It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
if(bcck_rate)
{
pattrib->signal_strength=(u8)signal_scale_mapping(padapter, pwdb_all);
}
else
{
if (rf_rx_num != 0)
{
pattrib->signal_strength= (u8)(signal_scale_mapping(padapter, total_rssi/=rf_rx_num));
}
}
}
static void process_rssi(_adapter *padapter,union recv_frame *prframe)
{
u32 last_rssi, tmp_val;
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
//if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
{
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
if(signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
}
signal_stat->total_num++;
signal_stat->total_val += pattrib->signal_strength;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
//Adapter->RxStats.RssiCalculateCnt++; //For antenna Test
if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX)
{
padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
}
padapter->recvpriv.signal_strength_data.total_val +=pattrib->signal_strength;
padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->signal_strength;
if(padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
padapter->recvpriv.signal_strength_data.index = 0;
tmp_val = padapter->recvpriv.signal_strength_data.total_val/padapter->recvpriv.signal_strength_data.total_num;
padapter->recvpriv.signal_strength= tmp_val;
padapter->recvpriv.rssi=(s8)translate2dbm((u8)tmp_val);
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num));
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
}
}// Process_UI_RSSI_8192S
static void process_PWDB(_adapter *padapter, union recv_frame *prframe)
{
int UndecoratedSmoothedPWDB;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct rx_pkt_attrib *pattrib= &prframe->u.hdr.attrib;
struct sta_info *psta = prframe->u.hdr.psta;
if(psta)
{
UndecoratedSmoothedPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
}
//if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
{
if(UndecoratedSmoothedPWDB == 0) // initialize
{
UndecoratedSmoothedPWDB = pattrib->RxPWDBAll;
}
if(pattrib->RxPWDBAll > (u32)UndecoratedSmoothedPWDB)
{
UndecoratedSmoothedPWDB =
( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) +
(pattrib->RxPWDBAll)) /(Rx_Smooth_Factor);
UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB + 1;
}
else
{
UndecoratedSmoothedPWDB =
( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) +
(pattrib->RxPWDBAll)) /(Rx_Smooth_Factor);
}
if(psta)
{
psta->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
}
else
{
pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
}
//UpdateRxSignalStatistics8192C(Adapter, pRfd);
}
}
static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
{
u32 last_evm=0, tmpVal;
struct rx_pkt_attrib *pattrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
struct signal_stat * signal_stat;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
if(prframe == NULL || padapter==NULL){
return;
}
pattrib = &prframe->u.hdr.attrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
signal_stat = &padapter->recvpriv.signal_qual_data;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
if(signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
}
signal_stat->total_num++;
signal_stat->total_val += pattrib->signal_qual;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
if(pattrib->signal_qual != 0)
{
//
// 1. Record the general EVM to the sliding window.
//
if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
{
padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
padapter->recvpriv.signal_qual_data.total_val -= last_evm;
}
padapter->recvpriv.signal_qual_data.total_val += pattrib->signal_qual;
padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->signal_qual;
if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
padapter->recvpriv.signal_qual_data.index = 0;
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->signal_qual));
// <1> Showed on UI for user, in percentage.
tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
padapter->recvpriv.signal_qual=(u8)tmpVal;
}
else
{
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->signal_qual));
}
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
}// Process_UiLinkQuality8192S
static void process_phy_info(_adapter *padapter, union recv_frame *prframe)
{
union recv_frame *precvframe = (union recv_frame *)prframe;
//
// Check RSSI
//
process_rssi(padapter, precvframe);
//
// Check PWDB.
//
process_PWDB(padapter, precvframe);
//
// Check EVM
//
process_link_qual(padapter, precvframe);
}
void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_info)
{
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
_adapter *padapter = precvframe->u.hdr.adapter;
u8 bPacketMatchBSSID =_FALSE;
u8 bPacketToSelf = _FALSE;
u8 bPacketBeacon = _FALSE;
if((pattrib->physt) && (pphy_info != NULL))
{
bPacketMatchBSSID = ((!IsFrameTypeCtrl(precvframe->u.hdr.rx_data)) && !(pattrib->icv_err) && !(pattrib->crc_err) &&
_rtw_memcmp(get_hdr_bssid(precvframe->u.hdr.rx_data), get_my_bssid(&padapter->mlmeextpriv.mlmext_info.network), ETH_ALEN));
bPacketToSelf = bPacketMatchBSSID && (_rtw_memcmp(get_da(precvframe->u.hdr.rx_data), myid(&padapter->eeprompriv), ETH_ALEN));
bPacketBeacon =bPacketMatchBSSID && (GetFrameSubType(precvframe->u.hdr.rx_data) == WIFI_BEACON);
query_rx_phy_status(precvframe, pphy_info, bPacketMatchBSSID);
precvframe->u.hdr.psta = NULL;
if(bPacketMatchBSSID && check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
{
u8 *sa;
struct sta_info *psta=NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
sa = get_sa(precvframe->u.hdr.rx_data);
psta = rtw_get_stainfo(pstapriv, sa);
if(psta)
{
precvframe->u.hdr.psta = psta;
psta->rssi = pattrib->RecvSignalPower;
process_phy_info(padapter, precvframe);
}
}
else if(bPacketToSelf || bPacketBeacon)
{
if(check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
{
u8 *sa;
struct sta_info *psta=NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
sa = get_sa(precvframe->u.hdr.rx_data);
psta = rtw_get_stainfo(pstapriv, sa);
if(psta)
{
precvframe->u.hdr.psta = psta;
}
}
process_phy_info(padapter, precvframe);
}
}
}
void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc)
{
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
//Offset 0
pattrib->physt = (u8)((le32_to_cpu(pdesc->rxdw0) >> 26) & 0x1);
pattrib->pkt_len = (u16)(le32_to_cpu(pdesc->rxdw0)&0x00003fff);
pattrib->drvinfo_sz = (u8)((le32_to_cpu(pdesc->rxdw0) >> 16) & 0xf) * 8;//uint 2^3 = 8 bytes
pattrib->shift_sz = (u8)((le32_to_cpu(pdesc->rxdw0) >> 24) & 0x3);
pattrib->crc_err = (u8)((le32_to_cpu(pdesc->rxdw0) >> 14) & 0x1);
pattrib->icv_err = (u8)((le32_to_cpu(pdesc->rxdw0) >> 15) & 0x1);
pattrib->qos = (u8)(( le32_to_cpu( pdesc->rxdw0 ) >> 23) & 0x1);// Qos data, wireless lan header length is 26
pattrib->bdecrypted = (le32_to_cpu(pdesc->rxdw0) & BIT(27))? 0:1;
pattrib->encrypt = (u8)(( le32_to_cpu( pdesc->rxdw0 ) >> 20) & 0x7);
//Offset 4
pattrib->mfrag = (u8)((le32_to_cpu(pdesc->rxdw1) >> 27) & 0x1);//more fragment bit
//Offset 8
pattrib->frag_num = (u8)((le32_to_cpu(pdesc->rxdw2) >> 12) & 0xf);//fragmentation number
//Offset 12
#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
if ( le32_to_cpu(pdesc->rxdw3) & BIT(13)){
pattrib->tcpchk_valid = 1; // valid
if ( le32_to_cpu(pdesc->rxdw3) & BIT(11) ) {
pattrib->tcp_chkrpt = 1; // correct
//DBG_8192C("tcp csum ok\n");
}
else
pattrib->tcp_chkrpt = 0; // incorrect
if ( le32_to_cpu(pdesc->rxdw3) & BIT(12) )
pattrib->ip_chkrpt = 1; // correct
else
pattrib->ip_chkrpt = 0; // incorrect
}
else {
pattrib->tcpchk_valid = 0; // invalid
}
#endif
pattrib->mcs_rate=(u8)((le32_to_cpu(pdesc->rxdw3))&0x3f);
pattrib->rxht=(u8)((le32_to_cpu(pdesc->rxdw3) >>6)&0x1);
//Offset 16
//Offset 20
}

62
package/jsda/rtl8192du/hal/rtl8192d_xmit.c
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@ -1,62 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8192D_XMIT_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8192d_hal.h>
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_8192d(void *buf)
{
struct txrpt_ccx_8192d *txrpt_ccx = buf;
DBG_871X("%s:\n"
"retry_cnt:%u, rsvd_0:%u, rts_retry_cnt:%u, rsvd_1:%u\n"
"ccx_qtime:%u, missed_pkt_num:%u, rsvd_4:%u\n"
"mac_id:%u, des1_fragssn:%u\n"
"rpt_pkt_num:%u, pkt_drop:%u, lifetime_over:%u, retry_over:%u\n"
"edca_tx_queue:%u, rsvd_7:%u, bmc:%u, pkt_ok:%u, init_ccx:%u\n"
, __func__
, txrpt_ccx->retry_cnt, txrpt_ccx->rsvd_0, txrpt_ccx->rts_retry_cnt, txrpt_ccx->rsvd_1
, txrpt_ccx_qtime_8192d(txrpt_ccx), txrpt_ccx->missed_pkt_num, txrpt_ccx->rsvd_4
, txrpt_ccx->mac_id, txrpt_ccx->des1_fragssn
, txrpt_ccx->rpt_pkt_num, txrpt_ccx->pkt_drop, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over
, txrpt_ccx->edca_tx_queue, txrpt_ccx->rsvd_7, txrpt_ccx->bmc, txrpt_ccx->pkt_ok, txrpt_ccx->int_ccx
);
}
void handle_txrpt_ccx_8192d(_adapter *adapter, void *buf)
{
struct txrpt_ccx_8192d *txrpt_ccx = buf;
#ifdef DBG_CCX
dump_txrpt_ccx_8192d(buf);
#endif
//if (txrpt_ccx->int_ccx) {
if (txrpt_ccx->pkt_ok)
rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
else
rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
//}
}
#endif //CONFIG_XMIT_ACK

2678
package/jsda/rtl8192du/hal/rtl8192du_led.c
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218
package/jsda/rtl8192du/hal/rtl8192du_recv.c
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@ -1,218 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8192DU_RECV_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <recv_osdep.h>
#include <mlme_osdep.h>
#include <ip.h>
#include <if_ether.h>
#include <ethernet.h>
#include <usb_ops.h>
#include <wifi.h>
#include <circ_buf.h>
#include <rtl8192d_hal.h>
void rtl8192du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf)
{
precvbuf->transfer_len = 0;
precvbuf->len = 0;
precvbuf->ref_cnt = 0;
if(precvbuf->pbuf)
{
precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf;
precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ;
}
}
int rtl8192du_init_recv_priv(_adapter *padapter)
{
struct recv_priv *precvpriv = &padapter->recvpriv;
int i, res = _SUCCESS;
struct recv_buf *precvbuf;
#ifdef CONFIG_RECV_THREAD_MODE
_rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed
_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed
#endif //CONFIG_RECV_THREAD_MODE
#ifdef PLATFORM_LINUX
tasklet_init(&precvpriv->recv_tasklet,
(void(*)(unsigned long))rtl8192du_recv_tasklet,
(unsigned long)padapter);
_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
#endif // PLATFORM_LINUX
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
#ifdef PLATFORM_LINUX
precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
if(precvpriv->int_in_urb == NULL){
DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n");
}
#endif //PLATFORM_LINUX
precvpriv->int_in_buf = rtw_malloc(sizeof(INTERRUPT_MSG_FORMAT_EX));
if(precvpriv->int_in_buf == NULL){
DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n");
}
#endif //CONFIG_USB_INTERRUPT_IN_PIPE
//init recv_buf
_rtw_init_queue(&precvpriv->free_recv_buf_queue);
precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
if(precvpriv->pallocated_recv_buf==NULL){
res= _FAIL;
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n"));
goto exit;
}
precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
precvbuf = (struct recv_buf*)precvpriv->precv_buf;
for(i=0; i < NR_RECVBUFF ; i++)
{
_rtw_init_listhead(&precvbuf->list);
_rtw_spinlock_init(&precvbuf->recvbuf_lock);
precvbuf->alloc_sz = MAX_RECVBUF_SZ;
res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
if(res==_FAIL)
break;
precvbuf->ref_cnt = 0;
precvbuf->adapter =padapter;
//rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue));
precvbuf++;
}
precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF;
#if defined(PLATFORM_LINUX)
skb_queue_head_init(&precvpriv->rx_skb_queue);
#ifdef CONFIG_RX_INDICATE_QUEUE
memset(&precvpriv->rx_indicate_queue, 0, sizeof(struct ifqueue));
mtx_init(&precvpriv->rx_indicate_queue.ifq_mtx, "rx_indicate_queue", NULL, MTX_DEF);
#endif // CONFIG_RX_INDICATE_QUEUE
#ifdef CONFIG_PREALLOC_RECV_SKB
{
int i;
SIZE_PTR tmpaddr=0;
SIZE_PTR alignment=0;
struct sk_buff *pskb=NULL;
skb_queue_head_init(&precvpriv->free_recv_skb_queue);
for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
{
pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
if(pskb) {
pskb->dev = padapter->pnetdev;
tmpaddr = (SIZE_PTR)pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
}
pskb=NULL;
}
}
#endif
#endif
exit:
return res;
}
void rtl8192du_free_recv_priv (_adapter *padapter)
{
int i;
struct recv_buf *precvbuf;
struct recv_priv *precvpriv = &padapter->recvpriv;
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
for(i=0; i < NR_RECVBUFF ; i++)
{
rtw_os_recvbuf_resource_free(padapter, precvbuf);
precvbuf++;
}
if(precvpriv->pallocated_recv_buf)
rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
#ifdef PLATFORM_LINUX
if(precvpriv->int_in_urb)
{
usb_free_urb(precvpriv->int_in_urb);
}
#endif
if(precvpriv->int_in_buf)
rtw_mfree(precvpriv->int_in_buf, sizeof(INTERRUPT_MSG_FORMAT_EX));
#endif
#ifdef PLATFORM_LINUX
if (skb_queue_len(&precvpriv->rx_skb_queue)) {
DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n");
}
rtw_skb_queue_purge(&precvpriv->rx_skb_queue);
#ifdef CONFIG_PREALLOC_RECV_SKB
if (skb_queue_len(&precvpriv->free_recv_skb_queue)) {
DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue));
}
rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue);
#endif
#endif // PLATFORM_LINUX
}

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package/jsda/rtl8192du/hal/rtl8192du_xmit.c
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package/jsda/rtl8192du/hal/usb_halinit.c
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package/jsda/rtl8192du/hal/usb_ops_linux.c
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package/jsda/rtl8192du/include/Hal8192CEHWImg.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8192CE_FW_IMG_H
#define __INC_HAL8192CE_FW_IMG_H
#include <basic_types.h>
/*Created on 2011/ 6/15, 5:45*/
#ifdef CONFIG_BT_COEXISTENCE
#define TSMCImgArrayLength 15706 //v84 TSMC COMMON 2012-04-13
#else //#ifdef CONFIG_P2P
#define TSMCImgArrayLength 16126 //v88 TSMC P2PPS with CCX report C2H 2012-12-05
#endif
extern u8 Rtl8192CEFwTSMCImgArray[TSMCImgArrayLength];
#ifdef CONFIG_BT_COEXISTENCE
#define UMCACutImgArrayLength 16248 //v79 UMC A Cut COMMON 2011-10-06
#else //#ifdef CONFIG_P2P
#define UMCACutImgArrayLength 16126 //v88 UMC A Cut P2PPS with CCX report C2H 2012-12-05
#endif
extern u8 Rtl8192CEFwUMCACutImgArray[UMCACutImgArrayLength];
#ifdef CONFIG_BT_COEXISTENCE
#define UMCBCutImgArrayLength 15686 //v84 UMC B Cut COMMON 2012-04-13
#else //#ifdef CONFIG_P2P
#define UMCBCutImgArrayLength 16096 //v88 UMC B Cut P2PPS with CCX report C2H 2012-12-05
#endif
extern u8 Rtl8192CEFwUMCBCutImgArray[UMCBCutImgArrayLength];
//8192C_Formal_92CE_PHYforMP_110804 2011-11-23
//8188C_Formal_88CE_PHYforMP_111117 2011-11-23
#define PHY_REG_2TArrayLength 374
extern u32 Rtl8192CEPHY_REG_2TArray[PHY_REG_2TArrayLength];
#define PHY_REG_1TArrayLength 374
extern u32 Rtl8192CEPHY_REG_1TArray[PHY_REG_1TArrayLength];
#define PHY_ChangeTo_1T1RArrayLength 1
extern u32 Rtl8192CEPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength];
#define PHY_ChangeTo_1T2RArrayLength 1
extern u32 Rtl8192CEPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength];
#define PHY_ChangeTo_2T2RArrayLength 1
extern u32 Rtl8192CEPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength];
#define PHY_REG_Array_PGLength 336
extern u32 Rtl8192CEPHY_REG_Array_PG[PHY_REG_Array_PGLength];
#define PHY_REG_Array_MPLength 4
extern u32 Rtl8192CEPHY_REG_Array_MP[PHY_REG_Array_MPLength];
#define RadioA_2TArrayLength 282
extern u32 Rtl8192CERadioA_2TArray[RadioA_2TArrayLength];
#define RadioB_2TArrayLength 78
extern u32 Rtl8192CERadioB_2TArray[RadioB_2TArrayLength];
#define RadioA_1TArrayLength 282
extern u32 Rtl8192CERadioA_1TArray[RadioA_1TArrayLength];
#define RadioB_1TArrayLength 1
extern u32 Rtl8192CERadioB_1TArray[RadioB_1TArrayLength];
#define RadioB_GM_ArrayLength 1
extern u32 Rtl8192CERadioB_GM_Array[RadioB_GM_ArrayLength];
// MAC reg V14 - 2011-11-23
#define MAC_2T_ArrayLength 174
extern u32 Rtl8192CEMAC_2T_Array[MAC_2T_ArrayLength];
#define MACPHY_Array_PGLength 1
extern u32 Rtl8192CEMACPHY_Array_PG[MACPHY_Array_PGLength];
#define AGCTAB_2TArrayLength 320
extern u32 Rtl8192CEAGCTAB_2TArray[AGCTAB_2TArrayLength];
#define AGCTAB_1TArrayLength 320
extern u32 Rtl8192CEAGCTAB_1TArray[AGCTAB_1TArrayLength];
#endif //__INC_HAL8192CE_FW_IMG_H

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package/jsda/rtl8192du/include/Hal8192CPhyCfg.h
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@ -1,400 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*****************************************************************************
* Module: __INC_HAL8192CPHYCFG_H
*
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192CPHYCFG_H
#define __INC_HAL8192CPHYCFG_H
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#define MAX_AGGR_NUM 0x0909
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
}SwChnlCmdID;
/* 1. Switch channel related */
typedef struct _SwChnlCmd{
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
}SwChnlCmd;
typedef enum _HW90_BLOCK{
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this
}HW90_BLOCK_E, *PHW90_BLOCK_E;
#define RF_PATH_MAX 2
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
WIRELESS_MODE_B = 0x02,
WIRELESS_MODE_G = 0x04,
WIRELESS_MODE_AUTO = 0x08,
WIRELESS_MODE_N_24G = 0x10,
WIRELESS_MODE_N_5G = 0x20
} WIRELESS_MODE;
typedef enum _BaseBand_Config_Type{
BaseBand_Config_PHY_REG = 0, //Radio Path A
BaseBand_Config_AGC_TAB = 1, //Radio Path B
}BaseBand_Config_Type, *PBaseBand_Config_Type;
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
/* BB/RF related */
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
#ifdef CONFIG_MP_INCLUDED
typedef enum _ANTENNA_PATH{
ANTENNA_NONE = 0x00,
ANTENNA_D ,
ANTENNA_C ,
ANTENNA_CD ,
ANTENNA_B ,
ANTENNA_BD ,
ANTENNA_BC ,
ANTENNA_BCD ,
ANTENNA_A ,
ANTENNA_AD ,
ANTENNA_AC ,
ANTENNA_ACD ,
ANTENNA_AB ,
ANTENNA_ABD ,
ANTENNA_ABC ,
ANTENNA_ABCD
} ANTENNA_PATH;
#endif
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
u32 rtl8192c_PHY_QueryBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8192c_PHY_SetBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8192c_PHY_QueryRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8192c_PHY_SetRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8192C( IN PADAPTER Adapter );
int PHY_BBConfig8192C( IN PADAPTER Adapter );
int PHY_RFConfig8192C( IN PADAPTER Adapter );
/* RF config */
int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath);
/* BB/RF readback check for making sure init OK */
int rtl8192c_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
IN HW90_BLOCK_E CheckBlock,
IN RF_RADIO_PATH_E eRFPath );
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter,
IN int powerInDbm );
//
VOID
PHY_ScanOperationBackup8192C(IN PADAPTER Adapter,
IN u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8192C( IN PADAPTER pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8192C( IN PADAPTER pAdapter,
IN u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter,
IN u8 channel );
void ChkFwCmdIoDone( IN PADAPTER Adapter);
#ifdef USE_WORKITEM
//extern void SetIOWorkItemCallback( IN PVOID pContext );
#else
//extern void SetIOTimerCallback( IN PRT_TIMER pTimer);
#endif
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,
IN u32 eRFPath );
//
// IQ calibrate
//
VOID rtl8192c_PHY_IQCalibrate( IN PADAPTER pAdapter , IN BOOLEAN bReCovery);
//
// LC calibrate
//
VOID rtl8192c_PHY_LCCalibrate(IN PADAPTER pAdapter);
//
// AP calibrate
//
VOID rtl8192c_PHY_APCalibrate(IN PADAPTER pAdapter, IN char delta);
VOID rtl8192c_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
//
// Modify the value of the hw register when beacon interval be changed.
//
void
rtl8192c_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
IN u16 BeaconInterval );
extern VOID
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
);
extern VOID
PHY_EnableHostClkReq(
IN PADAPTER Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
);
/*--------------------------Exported Function prototype---------------------*/
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192c_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192c_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192c_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192c_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#define PHY_SetMacReg PHY_SetBBReg
#endif // __INC_HAL8192CPHYCFG_H

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package/jsda/rtl8192du/include/Hal8192CUHWImg.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8192CU_FW_IMG_H
#define __INC_HAL8192CU_FW_IMG_H
/*Created on 2011/ 6/15, 5:45*/
#ifdef CONFIG_BT_COEXISTENCE
#define TSMCImgArrayLength 15706 //v84 TSMC COMMON 2012-04-13
#else //#ifdef CONFIG_P2P
#define TSMCImgArrayLength 16126 //v88 TSMC P2PPS with CCX report C2H 2012-12-05
#endif
extern u8 Rtl8192CUFwTSMCImgArray[TSMCImgArrayLength];
#ifdef CONFIG_BT_COEXISTENCE
#define UMCACutImgArrayLength 16248 //v79 UMC A Cut COMMON 2011-10-06
#else //#ifdef CONFIG_P2P
#define UMCACutImgArrayLength 16126 //v88 UMC A Cut P2PPS with CCX report C2H 2012-12-05
#endif
extern u8 Rtl8192CUFwUMCACutImgArray[UMCACutImgArrayLength];
#ifdef CONFIG_BT_COEXISTENCE
#define UMCBCutImgArrayLength 15686 //v84 UMC B Cut COMMON 2012-04-13
#else //#ifdef CONFIG_P2P
#define UMCBCutImgArrayLength 16096 //v88 UMC B Cut P2PPS with CCX report C2H 2012-12-05
#endif
extern u8 Rtl8192CUFwUMCBCutImgArray[UMCBCutImgArrayLength];
//8188C_Formal_All_PHYforMP_111117 2011-11-23
//8192C_Formal_92CU_PHYforMP_110817 2011-11-23
#define PHY_REG_2TArrayLength 374
extern u32 Rtl8192CUPHY_REG_2TArray[PHY_REG_2TArrayLength];
#define PHY_REG_1TArrayLength 374
extern u32 Rtl8192CUPHY_REG_1TArray[PHY_REG_1TArrayLength];
#define PHY_ChangeTo_1T1RArrayLength 1
extern u32 Rtl8192CUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength];
#define PHY_ChangeTo_1T2RArrayLength 1
extern u32 Rtl8192CUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength];
#define PHY_ChangeTo_2T2RArrayLength 1
extern u32 Rtl8192CUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength];
#define PHY_REG_Array_PGLength 336
extern u32 Rtl8192CUPHY_REG_Array_PG[PHY_REG_Array_PGLength];
#define PHY_REG_Array_PG_mCardLength 336
extern u32 Rtl8192CUPHY_REG_Array_PG_mCard[PHY_REG_Array_PG_mCardLength];
#define PHY_REG_Array_MPLength 4
extern u32 Rtl8192CUPHY_REG_Array_MP[PHY_REG_Array_MPLength];
#define PHY_REG_1T_HPArrayLength 378
extern u32 Rtl8192CUPHY_REG_1T_HPArray[PHY_REG_1T_HPArrayLength];
#define PHY_REG_1T_mCardArrayLength 374
extern u32 Rtl8192CUPHY_REG_1T_mCardArray[PHY_REG_1T_mCardArrayLength];
#define PHY_REG_2T_mCardArrayLength 374
extern u32 Rtl8192CUPHY_REG_2T_mCardArray[PHY_REG_2T_mCardArrayLength];
#define PHY_REG_Array_PG_HPLength 336
extern u32 Rtl8192CUPHY_REG_Array_PG_HP[PHY_REG_Array_PG_HPLength];
#define RadioA_2TArrayLength 282
extern u32 Rtl8192CURadioA_2TArray[RadioA_2TArrayLength];
#define RadioB_2TArrayLength 78
extern u32 Rtl8192CURadioB_2TArray[RadioB_2TArrayLength];
#define RadioA_1TArrayLength 282
extern u32 Rtl8192CURadioA_1TArray[RadioA_1TArrayLength];
#define RadioB_1TArrayLength 1
extern u32 Rtl8192CURadioB_1TArray[RadioB_1TArrayLength];
#define RadioA_2T_mCardArrayLength 282
extern u32 Rtl8192CURadioA_2T_mCardArray[RadioA_2T_mCardArrayLength];
#define RadioB_2T_mCardArrayLength 78
extern u32 Rtl8192CURadioB_2T_mCardArray[RadioB_2T_mCardArrayLength];
#define RadioA_1T_mCardArrayLength 282
extern u32 Rtl8192CURadioA_1T_mCardArray[RadioA_1T_mCardArrayLength];
#define RadioB_1T_mCardArrayLength 1
extern u32 Rtl8192CURadioB_1T_mCardArray[RadioB_1T_mCardArrayLength];
#define RadioA_1T_HPArrayLength 282
extern u32 Rtl8192CURadioA_1T_HPArray[RadioA_1T_HPArrayLength];
#define RadioB_GM_ArrayLength 1
extern u32 Rtl8192CURadioB_GM_Array[RadioB_GM_ArrayLength];
// MAC reg V14 - 2011-11-23
#define MAC_2T_ArrayLength 174
extern u32 Rtl8192CUMAC_2T_Array[MAC_2T_ArrayLength];
#define MACPHY_Array_PGLength 1
extern u32 Rtl8192CUMACPHY_Array_PG[MACPHY_Array_PGLength];
#define AGCTAB_2TArrayLength 320
extern u32 Rtl8192CUAGCTAB_2TArray[AGCTAB_2TArrayLength];
#define AGCTAB_1TArrayLength 320
extern u32 Rtl8192CUAGCTAB_1TArray[AGCTAB_1TArrayLength];
#define AGCTAB_1T_HPArrayLength 320
extern u32 Rtl8192CUAGCTAB_1T_HPArray[AGCTAB_1T_HPArrayLength];
#endif //__INC_HAL8192CU_FW_IMG_H

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package/jsda/rtl8192du/include/Hal8192CUHWImg_wowlan.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8192CU_FW_IMG_WOWLAN_H
#define __INC_HAL8192CU_FW_IMG_WOWLAN_H
/*Created on 2011/11/ 8, 14:15*/
#define TSMCWWImgArrayLength 13458
extern u8 Rtl8192CUFwTSMCWWImgArray[TSMCWWImgArrayLength];
#define UMCACutWWImgArrayLength 13458
extern u8 Rtl8192CUFwUMCACutWWImgArray[UMCACutWWImgArrayLength];
#define UMCBCutWWImgArrayLength 13446
extern u8 Rtl8192CUFwUMCBCutWWImgArray[UMCBCutWWImgArrayLength];
#endif //__INC_HAL8192CU_FW_IMG_WOWLAN_H

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package/jsda/rtl8192du/include/Hal8192DEHWImg.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8192DE_FW_IMG_H
#define __INC_HAL8192DE_FW_IMG_H
#include <basic_types.h>
/*Created on 2011/11/11, 8: 8*/
#define Rtl8192DEImgArrayLength 32296
extern const u8 Rtl8192DEFwImgArray[Rtl8192DEImgArrayLength];
#define Rtl8192DEMainArrayLength 1
extern const u8 Rtl8192DEFwMainArray[Rtl8192DEMainArrayLength];
#define Rtl8192DEDataArrayLength 1
extern const u8 Rtl8192DEFwDataArray[Rtl8192DEDataArrayLength];
#define Rtl8192DEPHY_REG_2TArrayLength 372
extern const u32 Rtl8192DEPHY_REG_2TArray[Rtl8192DEPHY_REG_2TArrayLength];
#define Rtl8192DEPHY_REG_1TArrayLength 1
extern const u32 Rtl8192DEPHY_REG_1TArray[Rtl8192DEPHY_REG_1TArrayLength];
#define Rtl8192DEPHY_REG_Array_PGLength 624
extern const u32 Rtl8192DEPHY_REG_Array_PG[Rtl8192DEPHY_REG_Array_PGLength];
#define Rtl8192DEPHY_REG_Array_MPLength 12
extern const u32 Rtl8192DEPHY_REG_Array_MP[Rtl8192DEPHY_REG_Array_MPLength];
#define Rtl8192DERadioA_2TArrayLength 378
extern const u32 Rtl8192DERadioA_2TArray[Rtl8192DERadioA_2TArrayLength];
#define Rtl8192DERadioB_2TArrayLength 384
extern const u32 Rtl8192DERadioB_2TArray[Rtl8192DERadioB_2TArrayLength];
#define Rtl8192DERadioA_1TArrayLength 1
extern const u32 Rtl8192DERadioA_1TArray[Rtl8192DERadioA_1TArrayLength];
#define Rtl8192DERadioB_1TArrayLength 1
extern const u32 Rtl8192DERadioB_1TArray[Rtl8192DERadioB_1TArrayLength];
#define Rtl8192DERadioA_2T_intPAArrayLength 378
extern const u32 Rtl8192DERadioA_2T_intPAArray[Rtl8192DERadioA_2T_intPAArrayLength];
#define Rtl8192DERadioB_2T_intPAArrayLength 384
extern const u32 Rtl8192DERadioB_2T_intPAArray[Rtl8192DERadioB_2T_intPAArrayLength];
#define Rtl8192DEMAC_2T_ArrayLength 192
extern const u32 Rtl8192DEMAC_2T_Array[Rtl8192DEMAC_2T_ArrayLength];
#define Rtl8192DEAGCTAB_ArrayLength 386
extern const u32 Rtl8192DEAGCTAB_Array[Rtl8192DEAGCTAB_ArrayLength];
#define Rtl8192DEAGCTAB_5GArrayLength 194
extern const u32 Rtl8192DEAGCTAB_5GArray[Rtl8192DEAGCTAB_5GArrayLength];
#define Rtl8192DEAGCTAB_2GArrayLength 194
extern const u32 Rtl8192DEAGCTAB_2GArray[Rtl8192DEAGCTAB_2GArrayLength];
#define Rtl8192DEAGCTAB_2TArrayLength 1
extern const u32 Rtl8192DEAGCTAB_2TArray[Rtl8192DEAGCTAB_2TArrayLength];
#define Rtl8192DEAGCTAB_1TArrayLength 1
extern const u32 Rtl8192DEAGCTAB_1TArray[Rtl8192DEAGCTAB_1TArrayLength];
#endif //__INC_HAL8192CU_FW_IMG_H

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package/jsda/rtl8192du/include/Hal8192DPhyCfg.h
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@ -1,502 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*****************************************************************************
*
* Module: __INC_HAL8192DPHYCFG_H
*
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192DPHYCFG_H
#define __INC_HAL8192DPHYCFG_H
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 10
#define IQK_BB_REG_NUM_92C 9
#define IQK_BB_REG_NUM_92D 10
#define IQK_BB_REG_NUM_test 6
#define index_mapping_NUM 13
#define Rx_index_mapping_NUM 15
#define AVG_THERMAL_NUM 8
#define IQK_Matrix_REG_NUM 8
#define IQK_Matrix_Settings_NUM 1+24+21
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
}SwChnlCmdID;
/* 1. Switch channel related */
typedef struct _SwChnlCmd{
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
}SwChnlCmd;
typedef enum _HW90_BLOCK{
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this
}HW90_BLOCK_E, *PHW90_BLOCK_E;
//vivi added this for read parameter from header, 20100908
typedef enum _RF_CONTENT{
radioa_txt = 0x1000,
radiob_txt = 0x1001,
radioc_txt = 0x1002,
radiod_txt = 0x1003
} RF_CONTENT;
#define RF_PATH_MAX 2
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
WIRELESS_MODE_B = 0x02,
WIRELESS_MODE_G = 0x04,
WIRELESS_MODE_AUTO = 0x08,
WIRELESS_MODE_N_24G = 0x10,
WIRELESS_MODE_N_5G = 0x20
} WIRELESS_MODE;
#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number
#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups
#define MAX_PG_GROUP 13
#define CHANNEL_GROUP_MAX_2G 3
#define CHANNEL_GROUP_IDX_5GL 3
#define CHANNEL_GROUP_IDX_5GM 6
#define CHANNEL_GROUP_IDX_5GH 9
#define CHANNEL_GROUP_MAX_5G 9
#define CHANNEL_MAX_NUMBER_2G 14
typedef enum _BaseBand_Config_Type{
BaseBand_Config_PHY_REG = 0, //Radio Path A
BaseBand_Config_AGC_TAB = 1, //Radio Path B
}BaseBand_Config_Type, *PBaseBand_Config_Type;
typedef enum _MACPHY_MODE_8192D{
SINGLEMAC_SINGLEPHY,
DUALMAC_DUALPHY,
DUALMAC_SINGLEPHY,
}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
typedef enum _MACPHY_MODE_CHANGE_ACTION{
DMDP2DMSP = 0,
DMSP2DMDP = 1,
DMDP2SMSP = 2,
SMSP2DMDP = 3,
DMSP2SMSP = 4,
SMSP2DMSP = 5,
MAXACTION
}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
typedef enum _BAND_TYPE{
BAND_ON_2_4G = 0,
BAND_ON_5G,
BAND_ON_BOTH,
BANDMAX
}BAND_TYPE,*PBAND_TYPE;
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
/* BB/RF related */
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
#ifdef CONFIG_MP_INCLUDED
typedef enum _ANTENNA_PATH{
ANTENNA_NONE = 0x00,
ANTENNA_D ,
ANTENNA_C ,
ANTENNA_CD ,
ANTENNA_B ,
ANTENNA_BD ,
ANTENNA_BC ,
ANTENNA_BCD ,
ANTENNA_A ,
ANTENNA_AD ,
ANTENNA_AC ,
ANTENNA_ACD ,
ANTENNA_AB ,
ANTENNA_ABD ,
ANTENNA_ABC ,
ANTENNA_ABCD
} ANTENNA_PATH;
#endif
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
//Added for TX Power
//u8 GetRightChnlPlace(u8 chnl);
u8 rtl8192d_GetRightChnlPlaceforIQK(u8 chnl);
u8 rtl8192d_getChnlGroupfromArray(u8 chnl);
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
void rtl8192d_PHY_SetBBReg1Byte( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data );
u32 rtl8192d_PHY_QueryBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask );
void rtl8192d_PHY_SetBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data );
u32 rtl8192d_PHY_QueryRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask );
void rtl8192d_PHY_SetRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
extern int PHY_MACConfig8192D( PADAPTER Adapter );
extern int PHY_BBConfig8192D( PADAPTER Adapter );
extern int PHY_RFConfig8192D( PADAPTER Adapter );
/* RF config */
int rtl8192d_PHY_ConfigRFWithParaFile( PADAPTER Adapter,
u8* pFileName,
RF_RADIO_PATH_E eRFPath);
int rtl8192d_PHY_ConfigRFWithHeaderFile( PADAPTER Adapter,
RF_CONTENT Content,
RF_RADIO_PATH_E eRFPath);
/* BB/RF readback check for making sure init OK */
int rtl8192d_PHY_CheckBBAndRFOK( PADAPTER Adapter,
HW90_BLOCK_E CheckBlock,
RF_RADIO_PATH_E eRFPath );
/* Read initi reg value for tx power setting. */
void rtl8192d_PHY_GetHWRegOriginalValue(PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(PADAPTER Adapter,
// RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192D(PADAPTER Adapter,
u32* powerlevel );
void PHY_SetTxPowerLevel8192D(PADAPTER Adapter,
u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192D(PADAPTER Adapter,
int powerInDbm );
//
VOID
PHY_ScanOperationBackup8192D(PADAPTER Adapter,
u8 Operation );
//
// Switch bandwidth for 8192S
//
//void PHY_SetBWModeCallback8192C(PRT_TIMER pTimer );
void PHY_SetBWMode8192D(PADAPTER pAdapter,
HT_CHANNEL_WIDTH ChnlWidth,
unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( PADAPTER Adapter,
// IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C(PADAPTER Adapter,
u8 index,
u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C(PRT_TIMER pTimer );
void PHY_SwChnl8192D(PADAPTER pAdapter,
u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192D(PADAPTER pAdapter,
u8 channel );
extern void ChkFwCmdIoDone(PADAPTER Adapter);
#ifdef USE_WORKITEM
//extern void SetIOWorkItemCallback( IN PVOID pContext );
#else
//extern void SetIOTimerCallback( IN PRT_TIMER pTimer);
#endif
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192D(PADAPTER pAdapter,
BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192D(PADAPTER pAdapter,
u32 eRFPath );
//
// IQ calibrate
//
void rtl8192d_PHY_IQCalibrate(PADAPTER pAdapter, u8 FromPT);
//
// LC calibrate
//
void rtl8192d_PHY_LCCalibrate(PADAPTER pAdapter, BOOLEAN bInit);
//
// AP calibrate
//
void rtl8192d_PHY_APCalibrate(PADAPTER pAdapter, char delta);
//
// Modify the value of the hw register when beacon interval be changed.
//
void
rtl8192d_PHY_SetBeaconHwReg(PADAPTER Adapter,
u16 BeaconInterval );
extern VOID
PHY_SwitchEphyParameter(
PADAPTER Adapter
);
extern VOID
PHY_EnableHostClkReq(
PADAPTER Adapter
);
BOOLEAN
SetAntennaConfig92C(
PADAPTER Adapter,
u8 DefaultAnt
);
VOID
PHY_StopTRXBeforeChangeBand8192D(
PADAPTER Adapter
);
VOID
PHY_UpdateBBRFConfiguration8192D(
PADAPTER Adapter,
BOOLEAN bisBandSwitch
);
VOID PHY_ReadMacPhyMode92D(
PADAPTER Adapter,
BOOLEAN AutoloadFail
);
VOID PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
VOID PHY_ConfigMacPhyModeInfo92D(
PADAPTER Adapter
);
VOID PHY_ConfigMacCoexist_RFPage92D(
PADAPTER Adapter
);
VOID
rtl8192d_PHY_InitRxSetting(
PADAPTER Adapter
);
VOID
rtl8192d_PHY_ResetIQKResult(
PADAPTER Adapter
);
VOID
rtl8192d_PHY_SetRFPathSwitch(PADAPTER pAdapter, BOOLEAN bMain);
VOID
HalChangeCCKStatus8192D(
PADAPTER Adapter,
BOOLEAN bCCKDisable
);
VOID
PHY_InitPABias92D(PADAPTER Adapter);
/*--------------------------Exported Function prototype---------------------*/
#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#define PHY_SetMacReg PHY_SetBBReg
#endif // __INC_HAL8192SPHYCFG_H

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package/jsda/rtl8192du/include/Hal8192DPhyReg.h
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package/jsda/rtl8192du/include/Hal8192DUHWImg.h
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@ -1,66 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8192DU_FW_IMG_H
#define __INC_HAL8192DU_FW_IMG_H
#include <basic_types.h>
/*Created on 2011/11/11, 8: 8*/
#define Rtl8192DUImgArrayLength 31452
extern const u8 Rtl8192DUFwImgArray[Rtl8192DUImgArrayLength];
#define Rtl8192DUMainArrayLength 1
extern const u8 Rtl8192DUFwMainArray[Rtl8192DUMainArrayLength];
#define Rtl8192DUDataArrayLength 1
extern const u8 Rtl8192DUFwDataArray[Rtl8192DUDataArrayLength];
#define Rtl8192DUPHY_REG_2TArrayLength 372
extern const u32 Rtl8192DUPHY_REG_2TArray[Rtl8192DUPHY_REG_2TArrayLength];
#define Rtl8192DUPHY_REG_1TArrayLength 1
extern const u32 Rtl8192DUPHY_REG_1TArray[Rtl8192DUPHY_REG_1TArrayLength];
#define Rtl8192DUPHY_REG_Array_PGLength 624
extern const u32 Rtl8192DUPHY_REG_Array_PG[Rtl8192DUPHY_REG_Array_PGLength];
#define Rtl8192DUPHY_REG_Array_MPLength 14
extern const u32 Rtl8192DUPHY_REG_Array_MP[Rtl8192DUPHY_REG_Array_MPLength];
#define Rtl8192DURadioA_2TArrayLength 378
extern const u32 Rtl8192DURadioA_2TArray[Rtl8192DURadioA_2TArrayLength];
#define Rtl8192DURadioB_2TArrayLength 384
extern const u32 Rtl8192DURadioB_2TArray[Rtl8192DURadioB_2TArrayLength];
#define Rtl8192DURadioA_1TArrayLength 1
extern const u32 Rtl8192DURadioA_1TArray[Rtl8192DURadioA_1TArrayLength];
#define Rtl8192DURadioB_1TArrayLength 1
extern const u32 Rtl8192DURadioB_1TArray[Rtl8192DURadioB_1TArrayLength];
#define Rtl8192DURadioA_2T_intPAArrayLength 378
extern const u32 Rtl8192DURadioA_2T_intPAArray[Rtl8192DURadioA_2T_intPAArrayLength];
#define Rtl8192DURadioB_2T_intPAArrayLength 384
extern const u32 Rtl8192DURadioB_2T_intPAArray[Rtl8192DURadioB_2T_intPAArrayLength];
#define Rtl8192DUMAC_2T_ArrayLength 192
extern const u32 Rtl8192DUMAC_2T_Array[Rtl8192DUMAC_2T_ArrayLength];
#define Rtl8192DUAGCTAB_ArrayLength 386
extern const u32 Rtl8192DUAGCTAB_Array[Rtl8192DUAGCTAB_ArrayLength];
#define Rtl8192DUAGCTAB_5GArrayLength 194
extern const u32 Rtl8192DUAGCTAB_5GArray[Rtl8192DUAGCTAB_5GArrayLength];
#define Rtl8192DUAGCTAB_2GArrayLength 194
extern const u32 Rtl8192DUAGCTAB_2GArray[Rtl8192DUAGCTAB_2GArrayLength];
#define Rtl8192DUAGCTAB_2TArrayLength 1
extern const u32 Rtl8192DUAGCTAB_2TArray[Rtl8192DUAGCTAB_2TArrayLength];
#define Rtl8192DUAGCTAB_1TArrayLength 1
extern const u32 Rtl8192DUAGCTAB_1TArray[Rtl8192DUAGCTAB_1TArrayLength];
#endif //__INC_HAL8192CU_FW_IMG_H

29
package/jsda/rtl8192du/include/Hal8192DUHWImg_wowlan.h
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@ -1,29 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8192DU_FW_IMG_WOWLAN_H
#define __INC_HAL8192DU_FW_IMG_WOWLAN_H
/*Created on 2011/11/ 8, 14:15*/
#define DUWWImgArrayLength 24818
extern u8 Rtl8192DUFwWWImgArray[DUWWImgArrayLength];
#endif //__INC_HAL8192DU_FW_IMG_WOWLAN_H

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package/jsda/rtl8192du/include/HalPwrSeqCmd.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALPWRSEQCMD_H__
#define __HALPWRSEQCMD_H__
#include <drv_types.h>
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if( (Read(offset) & msk) == (value & msk) )
// break;
// } while(not timeout);
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/*---------------------------------------------*/
//3 The value of base: 4 bits
/*---------------------------------------------*/
// define the base address of each block
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of cut_msk: 8 bits
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//================================================================================
// Prototype of protected function.
//================================================================================
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrCfgCmd[]);
#endif

273
package/jsda/rtl8192du/include/autoconf.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*
* Public General Config
*/
#define AUTOCONF_INCLUDED
#define RTL871X_MODULE_NAME "92DU"
#define DRV_NAME "rtl8192du"
#define PLATFORM_LINUX 1
#ifdef CONFIG_IOCTL_CFG80211
#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
//#define CONFIG_DEBUG_CFG80211 1
#define CONFIG_SET_SCAN_DENY_TIMER
#endif
/*
* Internal General Config
*/
//#define CONFIG_PWRCTRL 1
//#define CONFIG_H2CLBK 1
#define CONFIG_EMBEDDED_FWIMG 1
//#define CONFIG_FILE_FWIMG
#ifdef CONFIG_WAKE_ON_WLAN
#define CONFIG_WOWLAN 1
#endif //CONFIG_WAKE_ON_WLAN
//#define CONFIG_WOWLAN_MANUAL /* manually use ioctl to enter suspend */
#define CONFIG_R871X_TEST 1
#define CONFIG_XMIT_ACK
#ifdef CONFIG_XMIT_ACK
#define CONFIG_XMIT_ACK_POLLING
#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
#endif
#define CONFIG_80211N_HT 1
#define CONFIG_RECV_REORDERING_CTRL 1
//#define CONFIG_TCP_CSUM_OFFLOAD_RX 1
//#define CONFIG_DRVEXT_MODULE 1
//#define CONFIG_DEINIT_BEFORE_INIT 1
#ifndef CONFIG_MP_INCLUDED
#define CONFIG_IPS 1
#define CONFIG_LPS 1
//#define CONFIG_BT_COEXIST 1
//#define SUPPORT_HW_RFOFF_DETECTED 1
#else
#define CONFIG_MP_IWPRIV_SUPPORT 1
#endif
#define CONFIG_AP_MODE 1
#ifdef CONFIG_AP_MODE
#define CONFIG_NATIVEAP_MLME 1
#ifndef CONFIG_NATIVEAP_MLME
#define CONFIG_HOSTAPD_MLME 1
#endif
#define CONFIG_FIND_BEST_CHANNEL 1
//#define CONFIG_NO_WIRELESS_HANDLERS 1
#endif
// Added by Albert 20110314
#define CONFIG_P2P 1
#ifdef CONFIG_P2P
//Added by Albert 20110812
//The CONFIG_WFD is for supporting the Wi-Fi display
#define CONFIG_WFD
#ifndef CONFIG_WIFI_TEST
#define CONFIG_P2P_REMOVE_GROUP_INFO
#endif
//#define CONFIG_DBG_P2P
//#define CONFIG_P2P_PS
//#define CONFIG_P2P_IPS
#define CONFIG_P2P_OP_CHK_SOCIAL_CH
// Added comment by Borg 2013/06/21
// Issue: Nexus 4 is hard to do miracast.
// Root Cause: After group formation,
// Nexus 4 is possible to be not at OP channel of Invitation Resp/Nego Confirm but at social channel.
// Patch: While scan OP channel,
// not only scan OP channel of Invitation Resp/Nego Confirm,
// but also scan social channel(1, 6, 11)
#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT
#define CONFIG_P2P_INVITE_IOT
#endif
// Added by Kurt 20110511
//#define CONFIG_TDLS 1
#ifdef CONFIG_TDLS
// #ifndef CONFIG_WFD
// #define CONFIG_WFD 1
// #endif
// #define CONFIG_TDLS_AUTOSETUP 1
// #define CONFIG_TDLS_AUTOCHECKALIVE 1
#endif
#define CONFIG_SKB_COPY 1//for amsdu
#define CONFIG_DFS 1
#define CONFIG_LED
#ifdef CONFIG_LED
#define CONFIG_SW_LED
#endif //CONFIG_LED
#define CONFIG_LAYER2_ROAMING
#define CONFIG_LAYER2_ROAMING_RESUME
//#define CONFIG_SET_SCAN_DENY_TIMER
#define CONFIG_NEW_SIGNAL_STAT_PROCESS
//#define CONFIG_SIGNAL_DISPLAY_DBM //display RX signal with dbm
#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable,*/
#define CONFIG_DEAUTH_BEFORE_CONNECT
#define CONFIG_BR_EXT 1 // Enable NAT2.5 support for STA mode interface with a L2 Bridge
#ifdef CONFIG_BR_EXT
#define CONFIG_BR_EXT_BRNAME "br0"
#endif // CONFIG_BR_EXT
#define CONFIG_TX_MCAST2UNI 1 // Support IP multicast->unicast
//#define CONFIG_CHECK_AC_LIFETIME 1 // Check packet lifetime of 4 ACs.
//#define CONFIG_DISABLE_MCS13TO15 1 // Disable MSC13-15 rates for more stable TX throughput with some 5G APs
//#define CONFIG_AVOID_ALLOC_MGNT_FAIL 1
#ifdef CONFIG_AVOID_ALLOC_MGNT_FAIL
#ifndef CONFIG_CHECK_AC_LIFETIME
#define CONFIG_CHECK_AC_LIFETIME 1 // Check packet lifetime of 4 ACs.
#endif
#endif
//#define CONFIG_DUALMAC_CONCURRENT 1 //for 92D dual mac concurrent ,DMSP DMDP SMSP switch
#define CONFIG_CONCURRENT_MODE 1
#ifdef CONFIG_CONCURRENT_MODE
#define CONFIG_TSF_RESET_OFFLOAD 1 // For 2 PORT TSF SYNC.
//#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri
#define CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
//#define CONFIG_MULTI_VIR_IFACES //besides primary&secondary interfaces, extend to support more interfaces
#undef CONFIG_DUALMAC_CONCURRENT //can not turn on CONFIG_CONCURRENT_MODE & CONFIG_DUALMAC_CONCURRENT at the same time
#endif // CONFIG_CONCURRENT_MODE
#define CONFIG_80211D
/*
* Interface Related Config
*/
//#define CONFIG_USB_INTERRUPT_IN_PIPE 1
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#define CONFIG_USB_TX_AGGREGATION 1
#define CONFIG_USB_RX_AGGREGATION 1
#endif
#define CONFIG_PREALLOC_RECV_SKB 1
//#define CONFIG_REDUCE_USB_TX_INT 1 // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms.
//#define CONFIG_EASY_REPLACEMENT 1
/*
* CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now!
*/
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX 1 // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX 1 // For RX path
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
#undef CONFIG_PREALLOC_RECV_SKB
#endif
/*
* USB VENDOR REQ BUFFER ALLOCATION METHOD
* if not set we'll use function local variable (stack memory)
*/
//#define CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
#define CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
#define CONFIG_USB_VENDOR_REQ_MUTEX
#define CONFIG_VENDOR_REQ_RETRY
//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ 1
/*
* HAL Related Config
*/
#define RTL8192C_RX_PACKET_NO_INCLUDE_CRC 1
#define CONFIG_ONLY_ONE_OUT_EP_TO_LOW 0
#define CONFIG_OUT_EP_WIFI_MODE 0
#define ENABLE_USB_DROP_INCORRECT_OUT
#define RTL8192CU_ASIC_VERIFICATION 0 // For ASIC verification.
#define RTL8192CU_ADHOC_WORKAROUND_SETTING 1
#define DISABLE_BB_RF 0
#define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0
#define ANTENNA_SELECTION_STATIC_SETTING 0
#define TX_POWER_FOR_5G_BAND 1 //For 5G band TX Power
#define RTL8192D_EASY_SMART_CONCURRENT 0
#define RTL8192D_DUAL_MAC_MODE_SWITCH 0
#define SWLCK 1
#define FW_PROCESS_VENDOR_CMD 1
#ifdef CONFIG_MP_INCLUDED
#define MP_DRIVER 1
#undef CONFIG_USB_TX_AGGREGATION
#undef CONFIG_USB_RX_AGGREGATION
#else
#define MP_DRIVER 0
#endif
/*
* Platform Related Config
*/
#ifndef CONFIG_WISTRON_PLATFORM
//#define CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE 1
#endif
#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR
/*
* Debug Related Config
*/
//#define CONFIG_DEBUG_RTL871X
#define DBG 0
#define CONFIG_DEBUG
#define CONFIG_PROC_DEBUG 1
//#define DBG_HAL_INIT_PROFILING
#define DBG_MEMORY_LEAK 1
//TX use 1 urb
//#define CONFIG_SINGLE_XMIT_BUF
//RX use 1 urb
//#define CONFIG_SINGLE_RECV_BUF

235
package/jsda/rtl8192du/include/basic_types.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __BASIC_TYPES_H__
#define __BASIC_TYPES_H__
#include <drv_conf.h>
#define SUCCESS 0
#define FAIL (-1)
#ifndef TRUE
#define _TRUE 1
#else
#define _TRUE TRUE
#endif
#ifndef FALSE
#define _FALSE 0
#else
#define _FALSE FALSE
#endif
#include <linux/version.h>
#include <linux/types.h>
#define VOID void
#define NDIS_OID uint
#define NDIS_STATUS uint
typedef signed int sint;
#ifndef PVOID
typedef void * PVOID;
//#define PVOID (void *)
#endif
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
typedef _Bool bool;
#endif
typedef void (*proc_t)(void*);
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1)
#define SIZE_PTR SIZE_T
#define SSIZE_PTR SSIZE_T
//port from fw by thomas
// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness
/*
* Call endian free function when
* 1. Read/write packet content.
* 2. Before write integer to IO.
* 3. After read integer from IO.
*/
//
// Byte Swapping routine.
//
#define EF1Byte
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
// Read LE format data from memory
//
#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr)))
#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr)))
#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr)))
//
// Write LE data to memory
//
#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
//
// Example:
// BIT_LEN_MASK_32(0) => 0x00000000
// BIT_LEN_MASK_32(1) => 0x00000001
// BIT_LEN_MASK_32(2) => 0x00000003
// BIT_LEN_MASK_32(32) => 0xFFFFFFFF
//
#define BIT_LEN_MASK_32(__BitLen) \
(0xFFFFFFFF >> (32 - (__BitLen)))
//
// Example:
// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
//
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
//
// Description:
// Return 4-byte value in host byte ordering from
// 4-byte pointer in litten-endian system.
//
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
(EF4Byte(*((u32 *)(__pStart))))
//
// Description:
// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
// 4-byte value in host byte ordering.
//
#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_32(__BitLen) \
)
//
// Description:
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// and return the result in 4-byte value in host byte ordering.
//
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
)
//
// Description:
// Set subfield of little-endian 4-byte value to specified value.
//
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u32 *)(__pStart)) = \
EF4Byte( \
LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_16(__BitLen) \
(0xFFFF >> (16 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
(EF2Byte(*((u16 *)(__pStart))))
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_16(__BitLen) \
)
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u16 *)(__pStart)) = \
EF2Byte( \
LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_8(__BitLen) \
(0xFF >> (8 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
(EF1Byte(*((u8 *)(__pStart))))
#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_8(__BitLen) \
)
#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u8 *)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
);
// Get the N-bytes aligment offset from the current length
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
typedef unsigned char BOOLEAN,*PBOOLEAN;
#endif //__BASIC_TYPES_H__

27
package/jsda/rtl8192du/include/circ_buf.h
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@ -1,27 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __CIRC_BUF_H_
#define __CIRC_BUF_H_ 1
#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
#endif //_CIRC_BUF_H_

35
package/jsda/rtl8192du/include/cmd_osdep.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __CMD_OSDEP_H_
#define __CMD_OSDEP_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
extern sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv);
extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
extern void _rtw_free_evt_priv (struct evt_priv *pevtpriv);
extern void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv);
extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj);
extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_CONF_H__
#define __DRV_CONF_H__
#include "autoconf.h"
//Older Android kernel doesn't has CONFIG_ANDROID defined,
//add this to force CONFIG_ANDROID defined
#ifdef CONFIG_PLATFORM_ANDROID
#define CONFIG_ANDROID
#endif
#ifdef CONFIG_ANDROID
//Some Android build will restart the UI while non-printable ascii is passed
//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
//for Android here. If you are sure there is no risk on your system about this,
//mask this macro define to support non-printable ascii ssid.
//#define CONFIG_VALIDATE_SSID
//Android expect dbm as the rx signal strength unit
#define CONFIG_SIGNAL_DISPLAY_DBM
#endif
#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE)
#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
#undef CONFIG_RESUME_IN_WORKQUEUE
#endif
#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE)
#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
#undef CONFIG_RESUME_IN_WORKQUEUE
#endif
#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this...
#if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
#endif
#endif
//About USB VENDOR REQ
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#define DYNAMIC_CAMID_ALLOC
#ifndef CONFIG_RTW_HIQ_FILTER
#define CONFIG_RTW_HIQ_FILTER 1
#endif
//#include <rtl871x_byteorder.h>
#endif // __DRV_CONF_H__

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*-------------------------------------------------------------------------------
For type defines and data structure defines
--------------------------------------------------------------------------------*/
#ifndef __DRV_TYPES_H__
#define __DRV_TYPES_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <wlan_bssdef.h>
#include <drv_types_linux.h>
enum _NIC_VERSION {
RTL8711_NIC,
RTL8712_NIC,
RTL8713_NIC,
RTL8716_NIC
};
enum{
UP_LINK,
DOWN_LINK,
};
typedef struct _ADAPTER _adapter, ADAPTER,*PADAPTER;
#ifdef CONFIG_80211N_HT
#include <rtw_ht.h>
#endif
#include <rtw_cmd.h>
#include <wlan_bssdef.h>
#include <rtw_security.h>
#include <rtw_xmit.h>
#include <rtw_recv.h>
#include <hal_intf.h>
#include <hal_com.h>
#include <rtw_qos.h>
#include <rtw_pwrctrl.h>
#include <rtw_io.h>
#include <rtw_eeprom.h>
#include <sta_info.h>
#include <rtw_mlme.h>
#include <rtw_debug.h>
#include <rtw_rf.h>
#include <rtw_event.h>
#include <rtw_led.h>
#include <rtw_mlme_ext.h>
#include <rtw_p2p.h>
#include <rtw_tdls.h>
#include <rtw_ap.h>
#include "../hal/dm.h"
#ifdef CONFIG_DRVEXT_MODULE
#include <drvext_api.h>
#endif
#ifdef CONFIG_MP_INCLUDED
#include <rtw_mp.h>
#endif
#ifdef CONFIG_BR_EXT
#include <rtw_br_ext.h>
#endif // CONFIG_BR_EXT
#ifdef CONFIG_IOCTL_CFG80211
#include "ioctl_cfg80211.h"
#endif //CONFIG_IOCTL_CFG80211
#define SPEC_DEV_ID_NONE BIT(0)
#define SPEC_DEV_ID_DISABLE_HT BIT(1)
#define SPEC_DEV_ID_ENABLE_PS BIT(2)
#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
struct specific_device_id{
u32 flags;
u16 idVendor;
u16 idProduct;
};
struct registry_priv
{
u8 chip_version;
u8 rfintfs;
u8 lbkmode;
u8 hci;
NDIS_802_11_SSID ssid;
u8 network_mode; //infra, ad-hoc, auto
u8 channel;//ad-hoc support requirement
u8 wireless_mode;//A, B, G, auto
u8 scan_mode;//active, passive
u8 radio_enable;
u8 preamble;//long, short, auto
u8 vrtl_carrier_sense;//Enable, Disable, Auto
u8 vcs_type;//RTS/CTS, CTS-to-self
u16 rts_thresh;
u16 frag_thresh;
u8 adhoc_tx_pwr;
u8 soft_ap;
u8 power_mgnt;
u8 ips_mode;
u8 smart_ps;
u8 long_retry_lmt;
u8 short_retry_lmt;
u16 busy_thresh;
u8 ack_policy;
u8 mp_mode;
u8 software_encrypt;
u8 software_decrypt;
u8 acm_method;
//UAPSD
u8 wmm_enable;
u8 uapsd_enable;
u8 uapsd_max_sp;
u8 uapsd_acbk_en;
u8 uapsd_acbe_en;
u8 uapsd_acvi_en;
u8 uapsd_acvo_en;
WLAN_BSSID_EX dev_network;
#ifdef CONFIG_80211N_HT
u8 ht_enable;
u8 cbw40_enable;
u8 ampdu_enable;//for tx
u8 rx_stbc;
u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted
#endif
u8 lowrate_two_xmit;
u8 rf_config ;
u8 low_power ;
u8 wifi_spec;// !turbo_mode
u8 channel_plan;
#ifdef CONFIG_BT_COEXIST
u8 bt_iso;
u8 bt_sco;
u8 bt_ampdu;
#endif
BOOLEAN bAcceptAddbaReq;
u8 antdiv_cfg;
u8 usbss_enable;//0:disable,1:enable
u8 hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config
u8 hwpwrp_detect;//0:disable,1:enable
u8 hw_wps_pbc;//0:disable,1:enable
#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
char adaptor_info_caching_file_path[PATH_LENGTH_MAX];
#endif
#ifdef CONFIG_LAYER2_ROAMING
u8 max_roaming_times; // the max number driver will try to roaming
#endif
#ifdef CONFIG_IOL
bool force_iol; //enable iol without other concern
#endif
u8 special_rf_path; //0: 2T2R ,1: only turn on path A 1T1R, 2: only turn on path B 1T1R
u8 mac_phy_mode; //0:by efuse, 1:smsp, 2:dmdp, 3:dmsp.
#ifdef CONFIG_80211D
u8 enable80211d;
#endif
u8 ifname[16];
u8 if2name[16];
u8 notch_filter;
#ifdef CONFIG_MULTI_VIR_IFACES
u8 ext_iface_num;//primary/secondary iface is excluded
#endif
u8 hiq_filter;
};
//For registry parameters
#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv,field))
#define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field)
#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX,field))
#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field)
#define MAX_CONTINUAL_URB_ERR 4
#ifdef CONFIG_CONCURRENT_MODE
#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
#define get_iface_type(adapter) (adapter->iface_type)
#else
#define is_primary_adapter(adapter) (1)
#define get_iface_type(adapter) (IFACE_PORT0)
#endif
#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->if1)
#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])
struct debug_priv {
u64 dbg_rx_fifo_last_overflow;
u64 dbg_rx_fifo_curr_overflow;
u64 dbg_rx_fifo_diff_overflow;
u64 dbg_rx_ampdu_drop_count;
u64 dbg_rx_ampdu_forced_indicate_count;
u64 dbg_rx_ampdu_loss_count;
u64 dbg_rx_ampdu_window_shift_cnt;
u64 dbg_rx_dup_mgt_frame_drop_count;};
enum _IFACE_ID {
IFACE_ID0, //maping to PRIMARY_ADAPTER
IFACE_ID1, //maping to SECONDARY_ADAPTER
IFACE_ID2,
IFACE_ID3,
IFACE_ID_MAX,
};
struct cam_ctl_t {
_lock lock;
u64 bitmap;
};
struct cam_entry_cache {
u16 ctrl;
u8 mac[ETH_ALEN];
u8 key[16];
};
#define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
#define KEY_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5], \
((u8*)(x))[6],((u8*)(x))[7],((u8*)(x))[8],((u8*)(x))[9],((u8*)(x))[10],((u8*)(x))[11], \
((u8*)(x))[12],((u8*)(x))[13],((u8*)(x))[14],((u8*)(x))[15]
struct dvobj_priv
{
_adapter *if1; //PRIMARY_ADAPTER
_adapter *if2; //SECONDARY_ADAPTER
s32 processing_dev_remove;
struct debug_priv drv_dbg;
//for local/global synchronization
_mutex hw_init_mutex;
_mutex h2c_fwcmd_mutex;
_mutex setch_mutex;
_mutex setbw_mutex;
unsigned char oper_channel; //saved channel info when call set_channel_bw
unsigned char oper_bwmode;
unsigned char oper_ch_offset;//PRIME_CHNL_OFFSET
u32 on_oper_ch_time;
//extend to support mulitu interface
//padapters[IFACE_ID0] == if1
//padapters[IFACE_ID1] == if2
_adapter *padapters[IFACE_ID_MAX];
u8 iface_nums; // total number of ifaces used runtime
struct cam_ctl_t cam_ctl;
struct cam_entry_cache cam_cache[32];
//For 92D, DMDP have 2 interface.
u8 InterfaceNumber;
u8 NumInterfaces;
u8 DualMacMode;
u8 irq_alloc;
/*-------- below is for SDIO INTERFACE --------*/
#ifdef INTF_DATA
INTF_DATA intf_data;
#endif
/*-------- below is for USB INTERFACE --------*/
u8 nr_endpoint;
u8 ishighspeed;
u8 RtNumInPipes;
u8 RtNumOutPipes;
int ep_num[5]; //endpoint number
int RegUsbSS;
_sema usb_suspend_sema;
#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
_mutex usb_vendor_req_mutex;
#endif
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
u8 * usb_alloc_vendor_req_buf;
u8 * usb_vendor_req_buf;
#endif
struct usb_interface *pusbintf;
struct usb_device *pusbdev;
ATOMIC_T continual_urb_error;
DM_ODM_T odmpriv;
};
static struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
{
/* todo: get interface type from dvobj and the return the dev accordingly */
return &dvobj->pusbintf->dev;
}
enum _IFACE_TYPE {
IFACE_PORT0, //mapping to port0 for C/D series chips
IFACE_PORT1, //mapping to port1 for C/D series chip
MAX_IFACE_PORT,
};
enum _ADAPTER_TYPE {
PRIMARY_ADAPTER,
SECONDARY_ADAPTER,
MAX_ADAPTER = 0xFF,
};
typedef enum _DRIVER_STATE{
DRIVER_NORMAL = 0,
DRIVER_DISAPPEAR = 1,
DRIVER_REPLACE_DONGLE = 2,
}DRIVER_STATE;
#ifdef CONFIG_INTEL_PROXIM
struct proxim {
bool proxim_support;
bool proxim_on;
void *proximity_priv;
int (*proxim_rx)(_adapter *padapter,
union recv_frame *precv_frame);
u8 (*proxim_get_var)(_adapter* padapter, u8 type);
};
#endif //CONFIG_INTEL_PROXIM
#ifdef RTL8723A_SDIO_LOOPBACK
typedef struct loopbackdata
{
_sema sema;
_thread_hdl_ lbkthread;
u8 bstop;
u32 cnt;
u16 size;
u16 txsize;
u8 txbuf[0x8000];
u16 rxsize;
u8 rxbuf[0x8000];
u8 msg[100];
}LOOPBACKDATA, *PLOOPBACKDATA;
#endif
struct _ADAPTER{
int DriverState;// for disable driver using module, use dongle to replace module.
int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd
int bDongle;//build-in module or external dongle
u16 chip_type;
u16 HardwareType;
u16 interface_type;//USB,SDIO,PCI
struct dvobj_priv *dvobj;
struct mlme_priv mlmepriv;
struct mlme_ext_priv mlmeextpriv;
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
//struct io_queue *pio_queue;
struct io_priv iopriv;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct security_priv securitypriv;
_lock security_key_mutex; // add for CONFIG_IEEE80211W, none 11w also can use
struct registry_priv registrypriv;
struct pwrctrl_priv pwrctrlpriv;
struct eeprom_priv eeprompriv;
struct led_priv ledpriv;
#ifdef CONFIG_MP_INCLUDED
struct mp_priv mppriv;
#endif
#ifdef CONFIG_DRVEXT_MODULE
struct drvext_priv drvextpriv;
#endif
#ifdef CONFIG_AP_MODE
struct hostapd_priv *phostapdpriv;
#endif
#ifdef CONFIG_IOCTL_CFG80211
#ifdef CONFIG_P2P
struct cfg80211_wifidirect_info cfg80211_wdinfo;
#endif //CONFIG_P2P
#endif //CONFIG_IOCTL_CFG80211
u32 setband;
#ifdef CONFIG_P2P
struct wifidirect_info wdinfo;
#endif //CONFIG_P2P
#ifdef CONFIG_TDLS
struct tdls_info tdlsinfo;
#endif //CONFIG_TDLS
#ifdef CONFIG_WFD
struct wifi_display_info wfd_info;
#endif //CONFIG_WFD
PVOID HalData;
u32 hal_data_sz;
struct hal_ops HalFunc;
#ifdef CONFIG_BT_COEXIST
//struct btcoexist_priv bt_coexist;
#endif
s32 bDriverStopped;
s32 bSurpriseRemoved;
s32 bCardDisableWOHSM;
u32 IsrContent;
u32 ImrContent;
u8 EepromAddressSize;
u8 hw_init_completed;
u8 bDriverIsGoingToUnload;
u8 init_adpt_in_progress;
u8 bHaltInProgress;
_thread_hdl_ cmdThread;
_thread_hdl_ evtThread;
_thread_hdl_ xmitThread;
_thread_hdl_ recvThread;
void (*intf_start)(_adapter * adapter);
void (*intf_stop)(_adapter * adapter);
_nic_hdl pnetdev;
char old_ifname[IFNAMSIZ];
// used by rtw_rereg_nd_name related function
struct rereg_nd_name_data {
_nic_hdl old_pnetdev;
char old_ifname[IFNAMSIZ];
u8 old_ips_mode;
u8 old_bRegUseLed;
} rereg_nd_name_priv;
int bup;
struct net_device_stats stats;
struct iw_statistics iwstats;
struct proc_dir_entry *dir_dev;// for proc directory
struct proc_dir_entry *dir_dm;
#ifdef CONFIG_IOCTL_CFG80211
struct wireless_dev *rtw_wdev;
struct rtw_wdev_priv wdev_data;
#endif //CONFIG_IOCTL_CFG80211
int net_closed;
u8 bFWReady;
u8 bReadPortCancel;
u8 bWritePortCancel;
u8 bRxRSSIDisplay;
// Added by Albert 2012/07/26
// The driver will write the initial gain everytime when running in the DM_Write_DIG function.
u8 bForceWriteInitGain;
// Added by Albert 2012/10/26
// The driver will show up the desired channel number when this flag is 1.
u8 bNotifyChannelChange;
#ifdef CONFIG_P2P
// Added by Albert 2012/12/06
// The driver will show the current P2P status when the upper application reads it.
u8 bShowGetP2PState;
#endif
#ifdef CONFIG_AUTOSUSPEND
u8 bDisableAutosuspend;
#endif
//pbuddy_adapter is used only in two inteface case, (iface_nums=2 in struct dvobj_priv)
//PRIMARY_ADAPTER's buddy is SECONDARY_ADAPTER
//SECONDARY_ADAPTER's buddy is PRIMARY_ADAPTER
//for iface_id > SECONDARY_ADAPTER(IFACE_ID1), refer to padapters[iface_id] in struct dvobj_priv
//and their pbuddy_adapter is PRIMARY_ADAPTER.
//for PRIMARY_ADAPTER(IFACE_ID0) can directly refer to if1 in struct dvobj_priv
_adapter *pbuddy_adapter;
#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT)
u8 isprimary; //is primary adapter or not
//notes:
// if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER
// if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for SECONDARY_ADAPTER
// refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.
u8 adapter_type;//used only in two inteface case(PRIMARY_ADAPTER and SECONDARY_ADAPTER) .
u8 iface_type; //interface port type, it depends on HW port
#endif
//extend to support multi interface
//IFACE_ID0 is equals to PRIMARY_ADAPTER
//IFACE_ID1 is equals to SECONDARY_ADAPTER
u8 iface_id;
#ifdef CONFIG_DUALMAC_CONCURRENT
u8 DualMacConcurrent; // 1: DMSP 0:DMDP
#endif
#ifdef CONFIG_BR_EXT
_lock br_ext_lock;
//unsigned int macclone_completed;
struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
int pppoe_connection_in_progress;
unsigned char pppoe_addr[MACADDRLEN];
unsigned char scdb_mac[MACADDRLEN];
unsigned char scdb_ip[4];
struct nat25_network_db_entry *scdb_entry;
unsigned char br_mac[MACADDRLEN];
unsigned char br_ip[4];
struct br_ext_info ethBrExtInfo;
#endif // CONFIG_BR_EXT
#ifdef CONFIG_INTEL_PROXIM
/* intel Proximity, should be alloc mem
* in intel Proximity module and can only
* be used in intel Proximity mode */
struct proxim proximity;
#endif //CONFIG_INTEL_PROXIM
#ifdef RTL8723A_SDIO_LOOPBACK
PLOOPBACKDATA ploopback;
#endif
u8 fix_rate;
};
#define adapter_to_dvobj(adapter) (adapter->dvobj)
#define adapter_to_odm(adapter) (&(adapter->dvobj->odmpriv))
#define adapter_wdev_data(adapter) (&((adapter)->wdev_data))
int rtw_handle_dualmac(_adapter *adapter, bool init);
__inline static u8 *myid(struct eeprom_priv *peepriv)
{
return (peepriv->mac_addr);
}
#endif //__DRV_TYPES_H__

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package/jsda/rtl8192du/include/drv_types_linux.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_LINUX_H__
#define __DRV_TYPES_LINUX_H__
#endif

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package/jsda/rtl8192du/include/ethernet.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*! \file */
#ifndef __INC_ETHERNET_H
#define __INC_ETHERNET_H
#define ETHERNET_ADDRESS_LENGTH 6 //!< Ethernet Address Length
#define ETHERNET_HEADER_SIZE 14 //!< Ethernet Header Length
#define LLC_HEADER_SIZE 6 //!< LLC Header Length
#define TYPE_LENGTH_FIELD_SIZE 2 //!< Type/Length Size
#define MINIMUM_ETHERNET_PACKET_SIZE 60 //!< Minimum Ethernet Packet Size
#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 //!< Maximum Ethernet Packet Size
#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address?
#define RT_ETH_IS_BROADCAST(_pAddr) ( \
((UCHAR *)(_pAddr))[0]==0xff && \
((UCHAR *)(_pAddr))[1]==0xff && \
((UCHAR *)(_pAddr))[2]==0xff && \
((UCHAR *)(_pAddr))[3]==0xff && \
((UCHAR *)(_pAddr))[4]==0xff && \
((UCHAR *)(_pAddr))[5]==0xff ) //!< Is Broadcast Address?
#endif // #ifndef __INC_ETHERNET_H

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _H2CLBK_H_
#include <rtl8711_spec.h>
#include <TypeDef.h>
void _lbk_cmd(PADAPTER Adapter);
void _lbk_rsp(PADAPTER Adapter);
void _lbk_evt(IN PADAPTER Adapter);
void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_COMMON_H__
#define __HAL_COMMON_H__
//CCK
#define RATE_1M BIT(0)
#define RATE_2M BIT(1)
#define RATE_5_5M BIT(2)
#define RATE_11M BIT(3)
//OFDM
#define RATE_6M BIT(4)
#define RATE_9M BIT(5)
#define RATE_12M BIT(6)
#define RATE_18M BIT(7)
#define RATE_24M BIT(8)
#define RATE_36M BIT(9)
#define RATE_48M BIT(10)
#define RATE_54M BIT(11)
//MCS 1 Spatial Stream
#define RATE_MCS0 BIT(12)
#define RATE_MCS1 BIT(13)
#define RATE_MCS2 BIT(14)
#define RATE_MCS3 BIT(15)
#define RATE_MCS4 BIT(16)
#define RATE_MCS5 BIT(17)
#define RATE_MCS6 BIT(18)
#define RATE_MCS7 BIT(19)
//MCS 2 Spatial Stream
#define RATE_MCS8 BIT(20)
#define RATE_MCS9 BIT(21)
#define RATE_MCS10 BIT(22)
#define RATE_MCS11 BIT(23)
#define RATE_MCS12 BIT(24)
#define RATE_MCS13 BIT(25)
#define RATE_MCS14 BIT(26)
#define RATE_MCS15 BIT(27)
// ALL CCK Rate
#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
RATR_36M|RATR_48M|RATR_54M
#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
/*------------------------------ Tx Desc definition Macro ------------------------*/
//#pragma mark -- Tx Desc related definition. --
//----------------------------------------------------------------------------
//-----------------------------------------------------------
// Rate
//-----------------------------------------------------------
// CCK Rates, TxHT = 0
#define DESC_RATE1M 0x00
#define DESC_RATE2M 0x01
#define DESC_RATE5_5M 0x02
#define DESC_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define DESC_RATE6M 0x04
#define DESC_RATE9M 0x05
#define DESC_RATE12M 0x06
#define DESC_RATE18M 0x07
#define DESC_RATE24M 0x08
#define DESC_RATE36M 0x09
#define DESC_RATE48M 0x0a
#define DESC_RATE54M 0x0b
// MCS Rates, TxHT = 1
#define DESC_RATEMCS0 0x0c
#define DESC_RATEMCS1 0x0d
#define DESC_RATEMCS2 0x0e
#define DESC_RATEMCS3 0x0f
#define DESC_RATEMCS4 0x10
#define DESC_RATEMCS5 0x11
#define DESC_RATEMCS6 0x12
#define DESC_RATEMCS7 0x13
#define DESC_RATEMCS8 0x14
#define DESC_RATEMCS9 0x15
#define DESC_RATEMCS10 0x16
#define DESC_RATEMCS11 0x17
#define DESC_RATEMCS12 0x18
#define DESC_RATEMCS13 0x19
#define DESC_RATEMCS14 0x1a
#define DESC_RATEMCS15 0x1b
#define DESC_RATEMCS15_SG 0x1c
#define DESC_RATEMCS32 0x20
#define HDATA_RATE(rate)\
(rate==DESC_RATE1M)?"CCK_1M":\
(rate==DESC_RATE2M)?"CCK_2M":\
(rate==DESC_RATE5_5M)?"CCK5_5M":\
(rate==DESC_RATE11M)?"CCK_11M":\
(rate==DESC_RATE6M)?"OFDM_6M":\
(rate==DESC_RATE9M)?"OFDM_9M":\
(rate==DESC_RATE12M)?"OFDM_12M":\
(rate==DESC_RATE18M)?"OFDM_18M":\
(rate==DESC_RATE24M)?"OFDM_24M":\
(rate==DESC_RATE36M)?"OFDM_36M":\
(rate==DESC_RATE48M)?"OFDM_48M":\
(rate==DESC_RATE54M)?"OFDM_54M":\
(rate==DESC_RATEMCS0)?"MCS0":\
(rate==DESC_RATEMCS1)?"MCS1":\
(rate==DESC_RATEMCS2)?"MCS2":\
(rate==DESC_RATEMCS3)?"MCS3":\
(rate==DESC_RATEMCS4)?"MCS4":\
(rate==DESC_RATEMCS5)?"MCS5":\
(rate==DESC_RATEMCS6)?"MCS6":\
(rate==DESC_RATEMCS7)?"MCS7":\
(rate==DESC_RATEMCS8)?"MCS8":\
(rate==DESC_RATEMCS9)?"MCS9":\
(rate==DESC_RATEMCS10)?"MCS10":\
(rate==DESC_RATEMCS11)?"MCS11":\
(rate==DESC_RATEMCS12)?"MCS12":\
(rate==DESC_RATEMCS13)?"MCS13":\
(rate==DESC_RATEMCS14)?"MCS14":\
(rate==DESC_RATEMCS15)?"MCS15":\
(rate==DESC_RATEMCS15_SG)?"MCS15_SG":\
(rate==DESC_RATEMCS32)?"MCS32":"UNKNOW"
//============================================================
// Global var
//============================================================
#define OFDM_TABLE_SIZE_92C 37
#define OFDM_TABLE_SIZE_92D 43
#define CCK_TABLE_SIZE 33
extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] ;
extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
#ifdef CONFIG_CHIP_VER_INTEGRATION
void dump_chip_info(HAL_VERSION ChipVersion);
#endif
u8 //return the final channel plan decision
hal_com_get_channel_plan(
PADAPTER padapter,
u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
u8 sw_channel_plan, //channel plan from SW (registry/module param)
u8 def_channel_plan, //channel plan used when the former two is invalid
BOOLEAN AutoLoadFail
);
void HalSetBrateCfg(
PADAPTER Adapter,
u8 *mBratesOS,
u16 *pBrateCfg);
u8 MRateToHwRate(u8 rate);
void hal_init_macaddr(_adapter *adapter);
void c2h_evt_clear(_adapter *adapter);
s32 c2h_evt_read(_adapter *adapter, u8 *buf);
void SetHwReg(_adapter *adapter, HW_VARIABLES variable, u8 *val);
void GetHwReg(_adapter *adapter, HW_VARIABLES variable, u8 *val);
u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val);
u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val);
u8 rtw_hal_busagg_qsel_check(_adapter *padapter,u8 pre_qsel,u8 next_qsel);
#endif //__HAL_COMMON_H__

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/******************************************************************************
*
* Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_COMMON_REG_H__
#define __HAL_COMMON_REG_H__
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
/* 92C, 92D */
#define REG_VOQ_INFO 0x0400
#define REG_VIQ_INFO 0x0404
#define REG_BEQ_INFO 0x0408
#define REG_BKQ_INFO 0x040C
#define REG_MGQ_INFO 0x0410
#define REG_HGQ_INFO 0x0414
#define REG_BCNQ_INFO 0x0418
// Security
#define REG_CAMCMD 0x0670
#define REG_CAMWRITE 0x0674
#define REG_CAMREAD 0x0678
#define REG_CAMDBG 0x067C
#define REG_SECCFG 0x0680
//----------------------------------------------------------------------------
// CAM Config Setting (offset 0x680, 1 byte)
//----------------------------------------------------------------------------
#define CAM_VALID BIT15
#define CAM_NOTVALID 0x0000
#define CAM_USEDK BIT5
#define CAM_CONTENT_COUNT 8
#define CAM_NONE 0x0
#define CAM_WEP40 0x01
#define CAM_TKIP 0x02
#define CAM_AES 0x04
#define CAM_WEP104 0x05
#define CAM_SMS4 0x6
#define TOTAL_CAM_ENTRY 32
#define HALF_CAM_ENTRY 16
#define CAM_CONFIG_USEDK _TRUE
#define CAM_CONFIG_NO_USEDK _FALSE
#define CAM_WRITE BIT16
#define CAM_READ 0x00000000
#define CAM_POLLINIG BIT31
//2 SECCFG
#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key
#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key
#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption
#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
#define SCR_SKByA2 BIT(4) //Search kEY BY A2
#define SCR_NoSKMC BIT(5) //No Key Search Multicast
#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
#define SCR_CHK_KEYID BIT(8)
#endif //__HAL_COMMON_H__

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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_INTF_H__
#define __HAL_INTF_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
enum RTL871X_HCI_TYPE {
RTW_SDIO,
RTW_USB,
RTW_PCIE
};
enum _CHIP_TYPE {
NULL_CHIP_TYPE,
RTL8712_8188S_8191S_8192S,
RTL8188C_8192C,
RTL8192D,
RTL8723A,
RTL8188E,
MAX_CHIP_TYPE
};
typedef enum _HW_VARIABLES{
HW_VAR_MEDIA_STATUS,
HW_VAR_MEDIA_STATUS1,
HW_VAR_SET_OPMODE,
HW_VAR_MAC_ADDR,
HW_VAR_BSSID,
HW_VAR_INIT_RTS_RATE,
HW_VAR_INIT_DATA_RATE,
HW_VAR_BASIC_RATE,
HW_VAR_TXPAUSE,
HW_VAR_BCN_FUNC,
HW_VAR_CORRECT_TSF,
HW_VAR_CHECK_BSSID,
HW_VAR_MLME_DISCONNECT,
HW_VAR_MLME_SITESURVEY,
HW_VAR_MLME_JOIN,
HW_VAR_ON_RCR_AM,
HW_VAR_OFF_RCR_AM,
HW_VAR_BEACON_INTERVAL,
HW_VAR_SLOT_TIME,
HW_VAR_RESP_SIFS,
HW_VAR_ACK_PREAMBLE,
HW_VAR_SEC_CFG,
HW_VAR_SEC_DK_CFG,
HW_VAR_BCN_VALID,
HW_VAR_RF_TYPE,
HW_VAR_DM_FLAG,
HW_VAR_DM_FUNC_OP,
HW_VAR_DM_FUNC_SET,
HW_VAR_DM_FUNC_CLR,
HW_VAR_DM_INIT_PWDB,
HW_VAR_CAM_EMPTY_ENTRY,
HW_VAR_CAM_INVALID_ALL,
HW_VAR_CAM_WRITE,
HW_VAR_CAM_READ,
HW_VAR_AC_PARAM_VO,
HW_VAR_AC_PARAM_VI,
HW_VAR_AC_PARAM_BE,
HW_VAR_AC_PARAM_BK,
HW_VAR_ACM_CTRL,
HW_VAR_AMPDU_MIN_SPACE,
HW_VAR_AMPDU_FACTOR,
HW_VAR_RXDMA_AGG_PG_TH,
HW_VAR_SET_RPWM,
HW_VAR_H2C_FW_PWRMODE,
HW_VAR_H2C_FW_JOINBSSRPT,
HW_VAR_FWLPS_RF_ON,
HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
HW_VAR_TDLS_WRCR,
HW_VAR_TDLS_INIT_CH_SEN,
HW_VAR_TDLS_RS_RCR,
HW_VAR_TDLS_DONE_CH_SEN,
HW_VAR_INITIAL_GAIN,
HW_VAR_TRIGGER_GPIO_0,
HW_VAR_BT_SET_COEXIST,
HW_VAR_BT_ISSUE_DELBA,
HW_VAR_CURRENT_ANTENNA,
HW_VAR_ANTENNA_DIVERSITY_LINK,
HW_VAR_ANTENNA_DIVERSITY_SELECT,
HW_VAR_SWITCH_EPHY_WoWLAN,
HW_VAR_EFUSE_BYTES,
HW_VAR_FIFO_CLEARN_UP,
HW_VAR_CHECK_TXBUF,
HW_VAR_APFM_ON_MAC, //Auto FSM to Turn On, include clock, isolation, power control for MAC only
HW_VAR_WOWLAN,
HW_VAR_VID,
HW_VAR_PID,
HW_VAR_MBSSID_CAM_WRITE,
HW_VAR_MBSSID_CAM_CLEAR,
HW_VAR_RCR_MBSSID_EN,
HW_VAR_USB_RXAGG_PAGE_TO,
HW_VAR_ENC_BMC_ENABLE,
HW_VAR_ENC_BMC_DISABLE,
HW_VAR_CHK_HI_QUEUE_EMPTY,
HW_VAR_DUMP_MAC_QUEUE_INFO,
}HW_VARIABLES;
typedef enum _HAL_DEF_VARIABLE{
HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
HAL_DEF_IS_SUPPORT_ANT_DIV,
HAL_DEF_CURRENT_ANTENNA,
HAL_DEF_DRVINFO_SZ,
HAL_DEF_MAX_RECVBUF_SZ,
HAL_DEF_RX_PACKET_OFFSET,
HAL_DEF_DBG_DUMP_RXPKT,//for dbg
HAL_DEF_DBG_DM_FUNC,//for dbg
HAL_DEF_DUAL_MAC_MODE,
}HAL_DEF_VARIABLE;
typedef enum _HAL_INTF_PS_FUNC{
HAL_USB_SELECT_SUSPEND,
HAL_MAX_ID,
}HAL_INTF_PS_FUNC;
typedef s32 (*c2h_id_filter)(u8 id);
struct hal_ops {
u32 (*hal_init)(PADAPTER Adapter);
u32 (*hal_deinit)(PADAPTER Adapter);
void (*free_hal_data)(PADAPTER Adapter);
u32 (*inirp_init)(PADAPTER Adapter);
u32 (*inirp_deinit)(PADAPTER Adapter);
s32 (*init_xmit_priv)(PADAPTER Adapter);
void (*free_xmit_priv)(PADAPTER Adapter);
s32 (*init_recv_priv)(PADAPTER Adapter);
void (*free_recv_priv)(PADAPTER Adapter);
void (*InitSwLeds)(PADAPTER Adapter);
void (*DeInitSwLeds)(PADAPTER Adapter);
void (*dm_init)(PADAPTER Adapter);
void (*dm_deinit)(PADAPTER Adapter);
void (*read_chip_version)(PADAPTER Adapter);
void (*init_default_value)(PADAPTER Adapter);
void (*intf_chip_configure)(PADAPTER Adapter);
void (*read_adapter_info)(PADAPTER Adapter);
void (*enable_interrupt)(PADAPTER Adapter);
void (*disable_interrupt)(PADAPTER Adapter);
s32 (*interrupt_handler)(PADAPTER Adapter);
void (*set_bwmode_handler)(PADAPTER Adapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
void (*set_channel_handler)(PADAPTER Adapter, u8 channel);
void (*hal_dm_watchdog)(PADAPTER Adapter);
void (*SetHwRegHandler)(PADAPTER Adapter, u8 variable,u8* val);
void (*GetHwRegHandler)(PADAPTER Adapter, u8 variable,u8* val);
u8 (*GetHalDefVarHandler)(PADAPTER Adapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
u8 (*SetHalDefVarHandler)(PADAPTER Adapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
void (*UpdateRAMaskHandler)(PADAPTER Adapter, u32 mac_id);
void (*SetBeaconRelatedRegistersHandler)(PADAPTER Adapter);
void (*Add_RateATid)(PADAPTER Adapter, u32 bitmap, u8 arg);
#ifdef CONFIG_ANTENNA_DIVERSITY
u8 (*AntDivBeforeLinkHandler)(PADAPTER Adapter);
void (*AntDivCompareHandler)(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
#endif
u8 (*interface_ps_func)(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8* val);
s32 (*hal_xmit)(PADAPTER Adapter, struct xmit_frame *pxmitframe);
s32 (*mgnt_xmit)(PADAPTER Adapter, struct xmit_frame *pmgntframe);
s32 (*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
u32 (*read_bbreg)(PADAPTER Adapter, u32 RegAddr, u32 BitMask);
void (*write_bbreg)(PADAPTER Adapter, u32 RegAddr, u32 BitMask, u32 Data);
u32 (*read_rfreg)(PADAPTER Adapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
void (*write_rfreg)(PADAPTER Adapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
#ifdef CONFIG_HOSTAPD_MLME
s32 (*hostap_mgnt_xmit_entry)(PADAPTER Adapter, _pkt *pkt);
#endif
void (*EfusePowerSwitch)(PADAPTER pAdapter, u8 bWrite, u8 PwrState);
void (*ReadEFuse)(PADAPTER Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
void (*EFUSEGetEfuseDefinition)(PADAPTER pAdapter, u8 efuseType, u8 type, PVOID *pOut, BOOLEAN bPseudoTest);
u16 (*EfuseGetCurrentSize)(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketRead)(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketWrite)(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
u8 (*Efuse_WordEnableDataWrite)(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
#ifdef DBG_CONFIG_ERROR_DETECT
void (*sreset_init_value)(_adapter *padapter);
void (*sreset_reset_value)(_adapter *padapter);
void (*silentreset)(_adapter *padapter);
void (*sreset_xmit_status_check)(_adapter *padapter);
void (*sreset_linked_status_check) (_adapter *padapter);
u8 (*sreset_get_wifi_status)(_adapter *padapter);
bool (*sreset_inprogress)(_adapter *padapter);
#endif
#ifdef CONFIG_IOL
int (*IOL_exec_cmds_sync)(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
#endif
void (*hal_notch_filter)(_adapter * adapter, bool enable);
void (*hal_reset_security_engine)(_adapter * adapter);
s32 (*c2h_handler)(_adapter *padapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter c2h_id_filter_ccx;
};
typedef enum _RT_EEPROM_TYPE{
EEPROM_93C46,
EEPROM_93C56,
EEPROM_BOOT_EFUSE,
}RT_EEPROM_TYPE,*PRT_EEPROM_TYPE;
#define USB_HIGH_SPEED_BULK_SIZE 512
#define USB_FULL_SPEED_BULK_SIZE 64
#define RF_CHANGE_BY_INIT 0
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
typedef enum _HARDWARE_TYPE{
HARDWARE_TYPE_RTL8180,
HARDWARE_TYPE_RTL8185,
HARDWARE_TYPE_RTL8187,
HARDWARE_TYPE_RTL8188,
HARDWARE_TYPE_RTL8190P,
HARDWARE_TYPE_RTL8192E,
HARDWARE_TYPE_RTL819xU,
HARDWARE_TYPE_RTL8192SE,
HARDWARE_TYPE_RTL8192SU,
HARDWARE_TYPE_RTL8192CE,
HARDWARE_TYPE_RTL8192CU,
HARDWARE_TYPE_RTL8192DE,
HARDWARE_TYPE_RTL8192DU,
HARDWARE_TYPE_RTL8723AE,
HARDWARE_TYPE_RTL8723AU,
HARDWARE_TYPE_RTL8723AS,
HARDWARE_TYPE_RTL8188EE,
HARDWARE_TYPE_RTL8188EU,
HARDWARE_TYPE_RTL8188ES,
HARDWARE_TYPE_MAX,
}HARDWARE_TYPE;
//
// RTL8192C Series
//
#define IS_HARDWARE_TYPE_8192CE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE)
#define IS_HARDWARE_TYPE_8192CU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU)
#define IS_HARDWARE_TYPE_8192C(_Adapter) \
(IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter))
//
// RTL8192D Series
//
#define IS_HARDWARE_TYPE_8192DE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE)
#define IS_HARDWARE_TYPE_8192DU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU)
#define IS_HARDWARE_TYPE_8192D(_Adapter) \
(IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter))
//
// RTL8723A Series
//
#define IS_HARDWARE_TYPE_8723AE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE)
#define IS_HARDWARE_TYPE_8723AU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU)
#define IS_HARDWARE_TYPE_8723AS(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS)
#define IS_HARDWARE_TYPE_8723A(_Adapter) \
(IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || IS_HARDWARE_TYPE_8723AS(_Adapter))
//
// RTL8188E Series
//
#define IS_HARDWARE_TYPE_8188EE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE)
#define IS_HARDWARE_TYPE_8188EU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU)
#define IS_HARDWARE_TYPE_8188ES(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES)
#define IS_HARDWARE_TYPE_8188E(_Adapter) \
(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
typedef struct eeprom_priv EEPROM_EFUSE_PRIV, *PEEPROM_EFUSE_PRIV;
#define GET_EEPROM_EFUSE_PRIV(priv) (&priv->eeprompriv)
#ifdef CONFIG_WOWLAN
typedef enum _wowlan_subcode{
WOWLAN_PATTERN_MATCH = 1,
WOWLAN_MAGIC_PACKET = 2,
WOWLAN_UNICAST = 3,
WOWLAN_SET_PATTERN = 4,
WOWLAN_DUMP_REG = 5,
WOWLAN_ENABLE = 6,
WOWLAN_DISABLE = 7,
WOWLAN_STATUS = 8,
WOWLAN_DEBUG_RELOAD_FW = 9,
WOWLAN_DEBUG_1 =10,
WOWLAN_DEBUG_2 =11
}wowlan_subcode;
struct wowlan_ioctl_param{
unsigned int subcode;
unsigned int subcode_value;
unsigned int wakeup_reason;
unsigned int len;
unsigned char pattern[0];
};
#define Rx_Pairwisekey BIT(0)
#define Rx_GTK BIT(1)
#define Rx_DisAssoc BIT(2)
#define Rx_DeAuth BIT(3)
#define FWDecisionDisconnect BIT(4)
#define Rx_MagicPkt BIT(5)
#define FinishBtFwPatch BIT(7)
#endif // CONFIG_WOWLAN
void rtw_hal_def_value_init(_adapter *padapter);
void rtw_hal_free_data(_adapter *padapter);
void rtw_hal_dm_init(_adapter *padapter);
void rtw_hal_dm_deinit(_adapter *padapter);
void rtw_hal_sw_led_init(_adapter *padapter);
void rtw_hal_sw_led_deinit(_adapter *padapter);
uint rtw_hal_init(_adapter *padapter);
uint rtw_hal_deinit(_adapter *padapter);
void rtw_hal_stop(_adapter *padapter);
void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
void rtw_hal_chip_configure(_adapter *padapter);
void rtw_hal_read_chip_info(_adapter *padapter);
void rtw_hal_read_chip_version(_adapter *padapter);
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
void rtw_hal_enable_interrupt(_adapter *padapter);
void rtw_hal_disable_interrupt(_adapter *padapter);
u32 rtw_hal_inirp_init(_adapter *padapter);
u32 rtw_hal_inirp_deinit(_adapter *padapter);
u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val);
s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtw_hal_init_xmit_priv(_adapter *padapter);
void rtw_hal_free_xmit_priv(_adapter *padapter);
s32 rtw_hal_init_recv_priv(_adapter *padapter);
void rtw_hal_free_recv_priv(_adapter *padapter);
void rtw_hal_update_ra_mask(_adapter *padapter, u32 mac_id);
void rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 arg);
void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
s32 rtw_hal_interrupt_handler(_adapter *padapter);
void rtw_hal_set_bwmode(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
void rtw_hal_set_chan(_adapter *padapter, u8 channel);
void rtw_hal_dm_watchdog(_adapter *padapter);
#ifdef CONFIG_ANTENNA_DIVERSITY
u8 rtw_hal_antdiv_before_linked(_adapter *padapter);
void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
#endif
#ifdef CONFIG_HOSTAPD_MLME
s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
#ifdef DBG_CONFIG_ERROR_DETECT
void rtw_hal_sreset_init(_adapter *padapter);
void rtw_hal_sreset_reset(_adapter *padapter);
void rtw_hal_sreset_reset_value(_adapter *padapter);
void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
void rtw_hal_sreset_linked_status_check(_adapter *padapter);
u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter);
bool rtw_hal_sreset_inprogress(_adapter *padapter);
#endif
#ifdef CONFIG_IOL
int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
#endif
void rtw_hal_notch_filter(_adapter * adapter, bool enable);
void rtw_hal_reset_security_engine(_adapter * adapter);
s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter);
#endif //__HAL_INTF_H__

1345
package/jsda/rtl8192du/include/ieee80211.h
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290
package/jsda/rtl8192du/include/ieee80211_ext.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IEEE80211_EXT_H
#define __IEEE80211_EXT_H
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#define WMM_OUI_TYPE 2
#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
#define WMM_VERSION 1
#define WPA_PROTO_WPA BIT(0)
#define WPA_PROTO_RSN BIT(1)
#define WPA_KEY_MGMT_IEEE8021X BIT(0)
#define WPA_KEY_MGMT_PSK BIT(1)
#define WPA_KEY_MGMT_NONE BIT(2)
#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
#define WPA_KEY_MGMT_WPA_NONE BIT(4)
#define WPA_CAPABILITY_PREAUTH BIT(0)
#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
#define PMKID_LEN 16
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct wme_ac_parameter {
#if defined(__LITTLE_ENDIAN)
/* byte 1 */
u8 aifsn:4,
acm:1,
aci:2,
reserved:1;
/* byte 2 */
u8 eCWmin:4,
eCWmax:4;
#else
/* byte 1 */
u8 reserved:1,
aci:2,
acm:1,
aifsn:4;
/* byte 2 */
u8 eCWmax:4,
eCWmin:4;
#endif
/* bytes 3 & 4 */
u16 txopLimit;
} __attribute__ ((packed));
struct wme_parameter_element {
/* required fields for WME version 1 */
u8 oui[3];
u8 oui_type;
u8 oui_subtype;
u8 version;
u8 acInfo;
u8 reserved;
struct wme_ac_parameter ac[4];
} __attribute__ ((packed));
#define WPA_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define WPA_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define WPA_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[0] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val))
/* Action category code */
enum ieee80211_category {
WLAN_CATEGORY_SPECTRUM_MGMT = 0,
WLAN_CATEGORY_QOS = 1,
WLAN_CATEGORY_DLS = 2,
WLAN_CATEGORY_BACK = 3,
WLAN_CATEGORY_HT = 7,
WLAN_CATEGORY_WMM = 17,
};
/* SPECTRUM_MGMT action code */
enum ieee80211_spectrum_mgmt_actioncode {
WLAN_ACTION_SPCT_MSR_REQ = 0,
WLAN_ACTION_SPCT_MSR_RPRT = 1,
WLAN_ACTION_SPCT_TPC_REQ = 2,
WLAN_ACTION_SPCT_TPC_RPRT = 3,
WLAN_ACTION_SPCT_CHL_SWITCH = 4,
WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
};
/* BACK action code */
enum ieee80211_back_actioncode {
WLAN_ACTION_ADDBA_REQ = 0,
WLAN_ACTION_ADDBA_RESP = 1,
WLAN_ACTION_DELBA = 2,
};
/* HT features action code */
enum ieee80211_ht_actioncode {
WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
WLAN_ACTION_SM_PS = 1,
WLAN_ACTION_PSPM = 2,
WLAN_ACTION_PCO_PHASE = 3,
WLAN_ACTION_MIMO_CSI_MX = 4,
WLAN_ACTION_MIMO_NONCP_BF = 5,
WLAN_ACTION_MIMP_CP_BF = 6,
WLAN_ACTION_ASEL_INDICATES_FB = 7,
WLAN_ACTION_HI_INFO_EXCHG = 8,
};
/* BACK (block-ack) parties */
enum ieee80211_back_parties {
WLAN_BACK_RECIPIENT = 0,
WLAN_BACK_INITIATOR = 1,
WLAN_BACK_TIMER = 2,
};
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} __attribute__ ((packed)) auth;
struct {
u16 reason_code;
} __attribute__ ((packed)) deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) reassoc_req;
struct {
u16 reason_code;
} __attribute__ ((packed)) disassoc;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params, TIM */
u8 variable[0];
} __attribute__ ((packed)) beacon;
struct {
/* only variable items: SSID, Supported rates */
u8 variable[0];
} __attribute__ ((packed)) probe_req;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params */
u8 variable[0];
} __attribute__ ((packed)) probe_resp;
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} __attribute__ ((packed)) wme_action;
struct{
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} __attribute__ ((packed)) addba_req;
struct{
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} __attribute__ ((packed)) addba_resp;
struct{
u8 action_code;
u16 params;
u16 reason_code;
} __attribute__ ((packed)) delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} __attribute__ ((packed)) plink_action;
struct{
u8 action_code;
u8 variable[0];
} __attribute__ ((packed)) mesh_action;
} __attribute__ ((packed)) u;
} __attribute__ ((packed)) action;
} __attribute__ ((packed)) u;
}__attribute__ ((packed));
/* mgmt header + 1 byte category code */
#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
#endif

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package/jsda/rtl8192du/include/if_ether.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _LINUX_IF_ETHER_H
#define _LINUX_IF_ETHER_H
/*
* IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble
* and FCS/CRC (frame check sequence).
*/
#define ETH_ALEN 6 /* Octets in one ethernet addr */
#define ETH_HLEN 14 /* Total octets in header. */
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
#define ETH_DATA_LEN 1500 /* Max. octets in payload */
#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
/*
* These are the defined Ethernet Protocol ID's.
*/
#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */
#define ETH_P_PUP 0x0200 /* Xerox PUP packet */
#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */
#define ETH_P_IP 0x0800 /* Internet Protocol packet */
#define ETH_P_X25 0x0805 /* CCITT X.25 */
#define ETH_P_ARP 0x0806 /* Address Resolution packet */
#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */
#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */
#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */
#define ETH_P_DEC 0x6000 /* DEC Assigned proto */
#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */
#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */
#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */
#define ETH_P_LAT 0x6004 /* DEC LAT */
#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */
#define ETH_P_CUST 0x6006 /* DEC Customer use */
#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */
#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */
#define ETH_P_ATALK 0x809B /* Appletalk DDP */
#define ETH_P_AARP 0x80F3 /* Appletalk AARP */
#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
#define ETH_P_IPX 0x8137 /* IPX over DIX */
#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */
#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */
#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */
#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */
#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport
* over Ethernet
*/
/*
* Non DIX types. Won't clash for 1500 types.
*/
#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */
#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */
#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */
#define ETH_P_802_2 0x0004 /* 802.2 frames */
#define ETH_P_SNAP 0x0005 /* Internal only */
#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */
#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/
#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */
#define ETH_P_CONTROL 0x0016 /* Card specific control frames */
#define ETH_P_IRDA 0x0017 /* Linux-IrDA */
#define ETH_P_ECONET 0x0018 /* Acorn Econet */
/*
* This is an Ethernet frame header.
*/
struct ethhdr
{
unsigned char h_dest[ETH_ALEN]; /* destination eth addr */
unsigned char h_source[ETH_ALEN]; /* source ether addr */
unsigned short h_proto; /* packet type ID field */
};
struct _vlan {
unsigned short h_vlan_TCI; // Encapsulates priority and VLAN ID
unsigned short h_vlan_encapsulated_proto;
};
#define get_vlan_id(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI)) & 0xfff)
#define get_vlan_priority(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI))>>13)
#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short )pvlan->h_vlan_encapsulated_proto))
#endif /* _LINUX_IF_ETHER_H */

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package/jsda/rtl8192du/include/ioctl_cfg80211.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IOCTL_CFG80211_H__
#define __IOCTL_CFG80211_H__
#if defined(CONFIG_IOCTL_CFG80211) && !defined(CONFIG_CFG80211) && !defined(CONFIG_CFG80211_MODULE)
#error "Can't define CONFIG_IOCTL_CFG80211 because neither CONFIG_CFG80211 nor CONFIG_CFG80211_MODULE is defined in kernel"
#endif
#if defined(CONFIG_IOCTL_CFG80211) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
#error "We haven't verify our cfg80211 solution below kernel version 2.6.35"
#endif
#if defined(RTW_USE_CFG80211_STA_EVENT)
#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
#endif
struct rtw_wdev_invit_info {
u8 state; /* 0: req, 1:rep */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 flags;
u8 status;
u8 req_op_ch;
u8 rsp_op_ch;
};
#define rtw_wdev_invit_info_init(invit_info) \
do { \
(invit_info)->state = 0xff; \
_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
(invit_info)->active = 0xff; \
(invit_info)->token = 0; \
(invit_info)->flags = 0x00; \
(invit_info)->status = 0xff; \
(invit_info)->req_op_ch = 0; \
(invit_info)->rsp_op_ch = 0; \
} while (0)
struct rtw_wdev_nego_info {
u8 state; /* 0: req, 1:rep, 2:conf */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 status;
u8 req_intent;
u8 req_op_ch;
u8 req_listen_ch;
u8 rsp_intent;
u8 rsp_op_ch;
u8 conf_op_ch;
};
#define rtw_wdev_nego_info_init(nego_info) \
do { \
(nego_info)->state = 0xff; \
_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
(nego_info)->active = 0xff; \
(nego_info)->token = 0; \
(nego_info)->status = 0xff; \
(nego_info)->req_intent = 0xff; \
(nego_info)->req_op_ch = 0; \
(nego_info)->req_listen_ch = 0; \
(nego_info)->rsp_intent = 0xff; \
(nego_info)->rsp_op_ch = 0; \
(nego_info)->conf_op_ch = 0; \
} while (0)
struct rtw_wdev_priv
{
struct wireless_dev *rtw_wdev;
_adapter *padapter;
struct cfg80211_scan_request *scan_request;
_lock scan_req_lock;
struct net_device *pmon_ndev;//for monitor interface
char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface
u8 p2p_enabled;
u8 provdisc_req_issued;
struct rtw_wdev_invit_info invit_info;
struct rtw_wdev_nego_info nego_info;
u8 bandroid_scan;
bool block;
bool power_mgmt;
#ifdef CONFIG_CONCURRENT_MODE
ATOMIC_T ro_ch_to;
ATOMIC_T switch_ch_to;
#endif
};
#define wiphy_to_adapter(x) (*((_adapter**)wiphy_priv(x)))
#define wdev_to_ndev(w) ((w)->netdev)
int rtw_wdev_alloc(_adapter *padapter, struct device *dev);
void rtw_wdev_free(struct wireless_dev *wdev);
void rtw_wdev_unregister(struct wireless_dev *wdev);
void rtw_cfg80211_init_wiphy(_adapter *padapter);
void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork);
int rtw_cfg80211_check_bss(_adapter *padapter);
void rtw_cfg80211_indicate_connect(_adapter *padapter);
void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated);
void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted);
#ifdef CONFIG_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason);
#endif //CONFIG_AP_MODE
void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg);
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,12,0))
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3 , 18 , 0))
#define rtw_cfg80211_rx_mgmt(adapter , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0, gfp)
#else
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
#else
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp)
#else
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp)
#else
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp)
#endif
#endif //__IOCTL_CFG80211_H__

139
package/jsda/rtl8192du/include/ip.h
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@ -1,139 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _LINUX_IP_H
#define _LINUX_IP_H
#include <rtw_byteorder.h>
/* SOL_IP socket options */
#define IPTOS_TOS_MASK 0x1E
#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK)
#define IPTOS_LOWDELAY 0x10
#define IPTOS_THROUGHPUT 0x08
#define IPTOS_RELIABILITY 0x04
#define IPTOS_MINCOST 0x02
#define IPTOS_PREC_MASK 0xE0
#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK)
#define IPTOS_PREC_NETCONTROL 0xe0
#define IPTOS_PREC_INTERNETCONTROL 0xc0
#define IPTOS_PREC_CRITIC_ECP 0xa0
#define IPTOS_PREC_FLASHOVERRIDE 0x80
#define IPTOS_PREC_FLASH 0x60
#define IPTOS_PREC_IMMEDIATE 0x40
#define IPTOS_PREC_PRIORITY 0x20
#define IPTOS_PREC_ROUTINE 0x00
/* IP options */
#define IPOPT_COPY 0x80
#define IPOPT_CLASS_MASK 0x60
#define IPOPT_NUMBER_MASK 0x1f
#define IPOPT_COPIED(o) ((o)&IPOPT_COPY)
#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK)
#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK)
#define IPOPT_CONTROL 0x00
#define IPOPT_RESERVED1 0x20
#define IPOPT_MEASUREMENT 0x40
#define IPOPT_RESERVED2 0x60
#define IPOPT_END (0 |IPOPT_CONTROL)
#define IPOPT_NOOP (1 |IPOPT_CONTROL)
#define IPOPT_SEC (2 |IPOPT_CONTROL|IPOPT_COPY)
#define IPOPT_LSRR (3 |IPOPT_CONTROL|IPOPT_COPY)
#define IPOPT_TIMESTAMP (4 |IPOPT_MEASUREMENT)
#define IPOPT_RR (7 |IPOPT_CONTROL)
#define IPOPT_SID (8 |IPOPT_CONTROL|IPOPT_COPY)
#define IPOPT_SSRR (9 |IPOPT_CONTROL|IPOPT_COPY)
#define IPOPT_RA (20|IPOPT_CONTROL|IPOPT_COPY)
#define IPVERSION 4
#define MAXTTL 255
#define IPDEFTTL 64
/* struct timestamp, struct route and MAX_ROUTES are removed.
REASONS: it is clear that nobody used them because:
- MAX_ROUTES value was wrong.
- "struct route" was wrong.
- "struct timestamp" had fatally misaligned bitfields and was completely unusable.
*/
#define IPOPT_OPTVAL 0
#define IPOPT_OLEN 1
#define IPOPT_OFFSET 2
#define IPOPT_MINOFF 4
#define MAX_IPOPTLEN 40
#define IPOPT_NOP IPOPT_NOOP
#define IPOPT_EOL IPOPT_END
#define IPOPT_TS IPOPT_TIMESTAMP
#define IPOPT_TS_TSONLY 0 /* timestamps only */
#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */
#define IPOPT_TS_PRESPEC 3 /* specified modules only */
#ifdef PLATFORM_LINUX
struct ip_options {
__u32 faddr; /* Saved first hop address */
unsigned char optlen;
unsigned char srr;
unsigned char rr;
unsigned char ts;
unsigned char is_setbyuser:1, /* Set by setsockopt? */
is_data:1, /* Options in __data, rather than skb */
is_strictroute:1, /* Strict source route */
srr_is_hit:1, /* Packet destination addr was our one */
is_changed:1, /* IP checksum more not valid */
rr_needaddr:1, /* Need to record addr of outgoing dev */
ts_needtime:1, /* Need to record timestamp */
ts_needaddr:1; /* Need to record addr of outgoing dev */
unsigned char router_alert;
unsigned char __pad1;
unsigned char __pad2;
unsigned char __data[0];
};
#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
#endif
struct iphdr {
#if defined(__LITTLE_ENDIAN)
__u8 ihl:4,
version:4;
#else
__u8 version:4,
ihl:4;
#endif
__u8 tos;
__u16 tot_len;
__u16 id;
__u16 frag_off;
__u8 ttl;
__u8 protocol;
__u16 check;
__u32 saddr;
__u32 daddr;
/*The options start here. */
};
#endif /* _LINUX_IP_H */

39
package/jsda/rtl8192du/include/mlme_osdep.h
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@ -1,39 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __MLME_OSDEP_H_
#define __MLME_OSDEP_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#if defined(PLATFORM_MPIXEL)
extern int time_after(u32 now, u32 old);
#endif
extern void rtw_init_mlme_timer(_adapter *padapter);
extern void rtw_os_indicate_disconnect( _adapter *adapter, u16 reason, u8 locally_generated);
extern void rtw_os_indicate_connect( _adapter *adapter );
void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted);
extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie);
void rtw_reset_securitypriv( _adapter *adapter );
#endif //_MLME_OSDEP_H_

353
package/jsda/rtl8192du/include/mp_custom_oid.h
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@ -1,353 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __CUSTOM_OID_H
#define __CUSTOM_OID_H
// by Owen
// 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit
// 0xFF818500 - 0xFF81850F RTL8185 Setup Utility
// 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility
//
// by Owen for Production Kit
// For Production Kit with Agilent Equipments
// in order to make our custom oids hopefully somewhat unique
// we will use 0xFF (indicating implementation specific OID)
// 81(first byte of non zero Realtek unique identifier)
// 80 (second byte of non zero Realtek unique identifier)
// XX (the custom OID number - providing 255 possible custom oids)
#define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
#define OID_RT_PRO_START_TEST 0xFF818002
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007
#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008
#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009
#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A
#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D
#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E
#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F
#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010
#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011
#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012
#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013
#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014
#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015
#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016
#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017
#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018
#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019
#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A
#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B
#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C
#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D
#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E
#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F
#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020
#define OID_RT_PRO_WRITE_EEPROM 0xFF818021
#define OID_RT_PRO_READ_EEPROM 0xFF818022
#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023
#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026
#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027
#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028
#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029
#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A
#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C
// added by Owen on 04/08/03 for Cameo's request
#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D
#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E
#define OID_RT_PRO_SET_MODULATION 0xFF81802F
//
//Sean
#define OID_RT_DRIVER_OPTION 0xFF818080
#define OID_RT_RF_OFF 0xFF818081
#define OID_RT_AUTH_STATUS 0xFF818082
//========================================================================
#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B
#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C
#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B
#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043
//========================================================================
// by Owen for RTL8185 Phy Status Report Utility
#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580
#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581
#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582
#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583
#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584
#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585
#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586
//
// by Owen on 03/09/19-03/09/22 for RTL8185
#define OID_RT_WIRELESS_MODE 0xFF818500
#define OID_RT_SUPPORTED_RATES 0xFF818501
#define OID_RT_DESIRED_RATES 0xFF818502
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
//
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_SET_KEY_LENGTH 0xFF030003
#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
#define OID_RT_SET_CHANNEL 0xFF010182
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
#define OID_RT_GET_TX_RETRY 0xFF010188
#define OID_RT_GET_RX_RETRY 0xFF010189
#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A//S
#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B//S
#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190
#define OID_RT_GET_TX_BEACON_OK 0xFF010191
#define OID_RT_GET_TX_BEACON_ERR 0xFF010192
#define OID_RT_GET_RX_ICV_ERR 0xFF010193
#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194
#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195
#define OID_RT_GET_PREAMBLE_MODE 0xFF010196
#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197
#define OID_RT_GET_AP_IP 0xFF010198
#define OID_RT_GET_CHANNELPLAN 0xFF010199
#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A
#define OID_RT_SET_BCN_INTVL 0xFF01019B
#define OID_RT_GET_RF_VENDER 0xFF01019C
#define OID_RT_DEDICATE_PROBE 0xFF01019D
#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E
#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F
#define OID_RT_GET_CCA_ERR 0xFF0101A0
#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1
#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2
#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3
#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4
// by Owen on 03/31/03 for Cameo's request
#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5
//
#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5
#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6
#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7
#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8
#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9
#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA
#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB
#define OID_RT_GET_CHANNEL 0xFF0101AC
#define OID_RT_SET_CHANNELPLAN 0xFF0101AD
#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE
#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF
#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0
#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1
#define OID_RT_GET_IS_ROAMING 0xFF0101B2
#define OID_RT_GET_IS_PRIVACY 0xFF0101B3
#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4
#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5
#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6
#define OID_RT_RESET_LOG 0xFF0101B7
#define OID_RT_GET_LOG 0xFF0101B8
#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9
#define OID_RT_GET_HEADER_FAIL 0xFF0101BA
#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB
#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC
#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD
#define OID_RT_GET_TX_INFO 0xFF0101BE
#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF
#define OID_RT_RF_READ_WRITE 0xFF0101C0
// For Netgear request. 2005.01.13, by rcnjko.
#define OID_RT_FORCED_DATA_RATE 0xFF0101C1
#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2
// For Netgear request. 2005.02.17, by rcnjko.
#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3
// For AZ project. 2005.06.27, by rcnjko.
#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4
// Vincent 8185MP
#define OID_RT_PRO_RX_FILTER 0xFF0111C0
//Andy TEST
//#define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1
//#define OID_RT_PRO_READ_REGISTRY 0xFF0111C2
#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1
#define OID_CE_USB_READ_REGISTRY 0xFF0111C2
#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3
#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4
#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5
#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6
#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7
#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8
#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9
#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA
// AP OID
#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300
#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301
#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302
#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303
#define OID_RT_AP_SUPPORTED 0xFF010304 // Determine if driver supports AP mode. 2004.08.27, by rcnjko.
#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 // Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko.
// 8187MP. 2004.09.06, by rcnjko.
#define OID_RT_PRO8187_WI_POLL 0xFF818780
#define OID_RT_PRO_WRITE_BB_REG 0xFF818781
#define OID_RT_PRO_READ_BB_REG 0xFF818782
#define OID_RT_PRO_WRITE_RF_REG 0xFF818783
#define OID_RT_PRO_READ_RF_REG 0xFF818784
// Meeting House. added by Annie, 2005-07-20.
#define OID_RT_MH_VENDER_ID 0xFFEDC100
//8711 MP OID added 20051230.
#define OID_RT_PRO8711_JOIN_BSS 0xFF871100//S
#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S
#define OID_RT_PRO_READ16_EEPROM 0xFF871106 //Q
#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 //S
#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 //S
#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 //Q
#define OID_RT_PRO8711_WI_POLL 0xFF87110A //Q
#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B //Q
#define OID_RT_RD_ATTRIB_MEM 0xFF87110C//Q
#define OID_RT_WR_ATTRIB_MEM 0xFF87110D//S
//Method 2 for H2C/C2H
#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 //S
#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 //Q
#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 //S
#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 //Q
#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114//Q
#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 //Q, S
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 //S
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 //Q,S
#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 //Q
#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 //Q
#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A //S
#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B //Q
#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C //S
#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D //Q
#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E //S
#define OID_RT_POLL_RX_STATUS 0xFF87111F //Q
#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 //Q,S
#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121//S
#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122//S
#define OID_RT_PRO_READ_TSSI 0xFF871123//S
#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S
#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S
//Method 2 , using workitem
#define OID_RT_SET_READ_REG 0xFF871181 //S
#define OID_RT_SET_WRITE_REG 0xFF871182 //S
#define OID_RT_SET_BURST_READ_REG 0xFF871183 //S
#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 //S
#define OID_RT_SET_WRITE_TXCMD 0xFF871185 //S
#define OID_RT_SET_READ16_EEPROM 0xFF871186 //S
#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 //S
#define OID_RT_QRY_POLL_WKITEM 0xFF871188 //Q
//For SDIO INTERFACE only
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
//For USB INTERFACE only
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S
#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 //S
#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 //S
#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 //Q
#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 //Q
#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB //S
#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC //S
#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S
#define OID_RT_PRO_READ_EFUSE 0xFF871205 //Q
#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 //S
#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 //Q, S
#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 //Q
#define OID_RT_SET_BANDWIDTH 0xFF871209 //S
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q
#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D //S
#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E //S
#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F //S
#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 //Q
#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 //S
#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 //Q
#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 //Q
#define OID_RT_SET_POWER_DOWN 0xFF871214 //S
#define OID_RT_GET_POWER_MODE 0xFF871215 //Q
#define OID_RT_PRO_EFUSE 0xFF871216 //Q, S
#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S
#endif //#ifndef __CUSTOM_OID_H

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package/jsda/rtl8192du/include/nic_spec.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __NIC_SPEC_H__
#define __NIC_SPEC_H__
#include <drv_conf.h>
#define RTL8711_MCTRL_ (0x20000)
#define RTL8711_UART_ (0x30000)
#define RTL8711_TIMER_ (0x40000)
#define RTL8711_FINT_ (0x50000)
#define RTL8711_HINT_ (0x50000)
#define RTL8711_GPIO_ (0x60000)
#define RTL8711_WLANCTRL_ (0x200000)
#define RTL8711_WLANFF_ (0xe00000)
#define RTL8711_HCICTRL_ (0x600000)
#define RTL8711_SYSCFG_ (0x620000)
#define RTL8711_SYSCTRL_ (0x620000)
#define RTL8711_MCCTRL_ (0x020000)
#include <rtl8711_regdef.h>
#include <rtl8711_bitdef.h>
#endif // __RTL8711_SPEC_H__

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package/jsda/rtl8192du/include/osdep_intf.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __OSDEP_INTF_H_
#define __OSDEP_INTF_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
struct intf_priv {
u8 *intf_dev;
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
u32 max_xmitsz; //USB2.0: unlimited, SDIO:512
u32 max_recvsz; //USB2.0: unlimited, SDIO:512
volatile u8 *io_rwmem;
volatile u8 *allocated_io_rwmem;
u32 io_wsz; //unit: 4bytes
u32 io_rsz;//unit: 4bytes
u8 intf_status;
void (*_bus_io)(u8 *priv);
/*
Under Sync. IRP (SDIO/USB)
A protection mechanism is necessary for the io_rwmem(read/write protocol)
Under Async. IRP (SDIO/USB)
The protection mechanism is through the pending queue.
*/
_mutex ioctl_mutex;
// when in USB, IO is through interrupt in/out endpoints
struct usb_device *udev;
PURB piorw_urb;
u8 io_irp_cnt;
u8 bio_irp_pending;
_sema io_retevt;
_timer io_timer;
u8 bio_irp_timeout;
u8 bio_timer_cancel;
};
#ifdef CONFIG_R871X_TEST
int rtw_start_pseudo_adhoc(_adapter *padapter);
int rtw_stop_pseudo_adhoc(_adapter *padapter);
#endif
struct dvobj_priv *devobj_init(void);
void devobj_deinit(struct dvobj_priv *pdvobj);
u8 rtw_init_drv_sw(_adapter *padapter);
u8 rtw_free_drv_sw(_adapter *padapter);
u8 rtw_reset_drv_sw(_adapter *padapter);
u32 rtw_start_drv_threads(_adapter *padapter);
void rtw_stop_drv_threads (_adapter *padapter);
void rtw_cancel_all_timer(_adapter *padapter);
#ifdef PLATFORM_LINUX
int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
struct net_device *rtw_init_netdev(_adapter *padapter);
void rtw_unregister_netdevs(struct dvobj_priv *dvobj);
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
u16 rtw_recv_select_queue(struct sk_buff *skb);
#endif //LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)
int rtw_ndev_notifier_register(void);
void rtw_ndev_notifier_unregister(void);
#include "../os_dep/rtw_proc.h"
#endif //PLATFORM_LINUX
void rtw_ips_dev_unload(_adapter *padapter);
#ifdef CONFIG_IPS
int rtw_ips_pwr_up(_adapter *padapter);
void rtw_ips_pwr_down(_adapter *padapter);
#endif
#ifdef CONFIG_CONCURRENT_MODE
struct _io_ops;
_adapter *rtw_drv_if2_init(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops));
void rtw_drv_if2_free(_adapter *if2);
void rtw_drv_if2_stop(_adapter *if2);
#ifdef CONFIG_MULTI_VIR_IFACES
struct dvobj_priv;
_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops));
void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj);
void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);
#endif //CONFIG_MULTI_VIR_IFACES
#endif
int rtw_drv_register_netdev(_adapter *padapter);
void rtw_ndev_destructor(_nic_hdl ndev);
#endif //_OSDEP_INTF_H_

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package/jsda/rtl8192du/include/osdep_service.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __OSDEP_SERVICE_H_
#define __OSDEP_SERVICE_H_
#include <drv_conf.h>
#include <basic_types.h>
//#include <rtl871x_byteorder.h>
#define _FAIL 0
#define _SUCCESS 1
#define RTW_RX_HANDLED 2
//#define RTW_STATUS_TIMEDOUT -110
#undef _TRUE
#define _TRUE 1
#undef _FALSE
#define _FALSE 0
#ifdef PLATFORM_LINUX
#include <linux/version.h>
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5))
#include <linux/kref.h>
#endif
//#include <linux/smp_lock.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/circ_buf.h>
#include <asm/uaccess.h>
#include <asm/byteorder.h>
#include <asm/atomic.h>
#include <asm/io.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
#include <asm/semaphore.h>
#else
#include <linux/semaphore.h>
#endif
#include <linux/sem.h>
#include <linux/sched.h>
#include <linux/etherdevice.h>
#include <net/iw_handler.h>
#include <linux/if_arp.h>
#include <linux/rtnetlink.h>
#include <linux/delay.h>
#include <linux/interrupt.h> // for struct tasklet_struct
#include <linux/ip.h>
#include <linux/kthread.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
#include <linux/sched/signal.h>
#endif
#ifdef CONFIG_NET_RADIO
#define CONFIG_WIRELESS_EXT
#endif
#ifdef CONFIG_IOCTL_CFG80211
// #include <linux/ieee80211.h>
#include <net/ieee80211_radiotap.h>
#include <net/cfg80211.h>
#endif //CONFIG_IOCTL_CFG80211
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
#include <linux/in.h>
#include <linux/udp.h>
#endif
#include <linux/usb.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
#include <linux/usb_ch9.h>
#else
#include <linux/usb/ch9.h>
#endif
typedef struct urb * PURB;
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22))
#ifdef CONFIG_USB_SUSPEND
#define CONFIG_AUTOSUSPEND 1
#endif
#endif
typedef struct semaphore _sema;
typedef spinlock_t _lock;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
typedef struct mutex _mutex;
#else
typedef struct semaphore _mutex;
#endif
typedef struct timer_list _timer;
struct __queue {
struct list_head queue;
_lock lock;
};
typedef struct sk_buff _pkt;
typedef unsigned char _buffer;
typedef struct __queue _queue;
typedef struct list_head _list;
typedef int _OS_STATUS;
//typedef u32 _irqL;
typedef unsigned long _irqL;
typedef struct net_device * _nic_hdl;
typedef void* _thread_hdl_;
typedef int thread_return;
typedef void* thread_context;
#define thread_exit() complete_and_exit(NULL, 0)
typedef void timer_hdl_return;
typedef void* timer_hdl_context;
typedef struct work_struct _workitem;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22))
// Porting from linux kernel, for compatible with old kernel.
static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)
{
return skb->tail;
}
static inline void skb_reset_tail_pointer(struct sk_buff *skb)
{
skb->tail = skb->data;
}
static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
{
skb->tail = skb->data + offset;
}
static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
{
return skb->end;
}
#endif
__inline static _list *get_next(_list *list)
{
return list->next;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
spin_lock_irqsave(plock, *pirqL);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
spin_unlock_irqrestore(plock, *pirqL);
}
__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
spin_lock_irqsave(plock, *pirqL);
}
__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
spin_unlock_irqrestore(plock, *pirqL);
}
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
{
spin_lock_bh(plock);
}
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
{
spin_unlock_bh(plock);
}
__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
mutex_lock(pmutex);
#else
down(pmutex);
#endif
}
__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
mutex_unlock(pmutex);
#else
up(pmutex);
#endif
}
__inline static void rtw_list_delete(_list *plist)
{
list_del_init(plist);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,void* cntx)
{
//setup_timer(ptimer, pfunc,(u32)cntx);
ptimer->function = pfunc;
ptimer->data = (unsigned long)cntx;
init_timer(ptimer);
}
#endif
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
del_timer_sync(ptimer);
*bcancelled= _TRUE;//TRUE ==1; FALSE==0
}
#ifdef PLATFORM_LINUX
#define RTW_TIMER_HDL_ARGS void *FunctionContext
#endif
#define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl
#define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS)
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
INIT_WORK(pwork, pfunc);
#else
INIT_WORK(pwork, pfunc,pwork);
#endif
}
__inline static void _set_workitem(_workitem *pwork)
{
schedule_work(pwork);
}
__inline static void _cancel_workitem_sync(_workitem *pwork)
{
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22))
cancel_work_sync(pwork);
#else
flush_scheduled_work();
#endif
}
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1)\
{ \
atomic_dec((atomic_t *)&(_MutexCounter)); \
msleep(10); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
atomic_dec((atomic_t *)&(_MutexCounter)); \
}
static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
{
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)) );
#else
return netif_queue_stopped(pnetdev);
#endif
}
static inline void rtw_netif_wake_queue(struct net_device *pnetdev)
{
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
netif_tx_wake_all_queues(pnetdev);
#else
netif_wake_queue(pnetdev);
#endif
}
static inline void rtw_netif_start_queue(struct net_device *pnetdev)
{
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
netif_tx_start_all_queues(pnetdev);
#else
netif_start_queue(pnetdev);
#endif
}
static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
{
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
netif_tx_stop_all_queues(pnetdev);
#else
netif_stop_queue(pnetdev);
#endif
}
#endif // PLATFORM_LINUX
#include <rtw_byteorder.h>
#ifndef BIT
#define BIT(x) ( 1 << (x))
#endif
extern int RTW_STATUS_CODE(int error_code);
#define CONFIG_USE_VMALLOC
/* flags used for rtw_mstat_update() */
enum mstat_f {
/* type: 0x00ff */
MSTAT_TYPE_VIR = 0x00,
MSTAT_TYPE_PHY= 0x01,
MSTAT_TYPE_SKB = 0x02,
MSTAT_TYPE_USB = 0x03,
MSTAT_TYPE_MAX = 0x04,
/* func: 0xff00 */
MSTAT_FUNC_UNSPECIFIED = 0x00<<8,
MSTAT_FUNC_IO = 0x01<<8,
MSTAT_FUNC_TX_IO = 0x02<<8,
MSTAT_FUNC_RX_IO = 0x03<<8,
MSTAT_FUNC_TX = 0x04<<8,
MSTAT_FUNC_RX = 0x05<<8,
MSTAT_FUNC_MAX = 0x06<<8,
};
#define mstat_tf_idx(flags) ((flags)&0xff)
#define mstat_ff_idx(flags) (((flags)&0xff00) >> 8)
typedef enum mstat_status{
MSTAT_ALLOC_SUCCESS = 0,
MSTAT_ALLOC_FAIL,
MSTAT_FREE
} MSTAT_STATUS;
#ifdef DBG_MEM_ALLOC
void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz);
void rtw_mstat_dump(void *sel);
u8* dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
u8* dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
u8* dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
struct sk_buff * dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line);
void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);
void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);
void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);
#ifdef CONFIG_USE_VMALLOC
#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
#else /* CONFIG_USE_VMALLOC */
#define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#endif /* CONFIG_USE_VMALLOC */
#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#else /* DBG_MEM_ALLOC */
#define rtw_mstat_update(flag, status, sz) do {} while(0)
#define rtw_mstat_dump(sel) do {} while(0)
u8* _rtw_vmalloc(u32 sz);
u8* _rtw_zvmalloc(u32 sz);
void _rtw_vmfree(u8 *pbuf, u32 sz);
u8* _rtw_zmalloc(u32 sz);
u8* _rtw_malloc(u32 sz);
void _rtw_mfree(u8 *pbuf, u32 sz);
struct sk_buff *_rtw_skb_alloc(u32 sz);
void _rtw_skb_free(struct sk_buff *skb);
struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb);
struct sk_buff *_rtw_skb_clone(struct sk_buff *skb);
int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);
void _rtw_skb_queue_purge(struct sk_buff_head *list);
void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);
void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);
#ifdef CONFIG_USE_VMALLOC
#define rtw_vmalloc(sz) _rtw_vmalloc((sz))
#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz))
#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz))
#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz))
#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz))
#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz))
#else /* CONFIG_USE_VMALLOC */
#define rtw_vmalloc(sz) _rtw_malloc((sz))
#define rtw_zvmalloc(sz) _rtw_zmalloc((sz))
#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz))
#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz))
#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz))
#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz))
#endif /* CONFIG_USE_VMALLOC */
#define rtw_malloc(sz) _rtw_malloc((sz))
#define rtw_zmalloc(sz) _rtw_zmalloc((sz))
#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz))
#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz))
#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz))
#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz))
#define rtw_skb_alloc(size) _rtw_skb_alloc((size))
#define rtw_skb_free(skb) _rtw_skb_free((skb))
#define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size))
#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb))
#define rtw_skb_copy(skb) _rtw_skb_copy((skb))
#define rtw_skb_clone(skb) _rtw_skb_clone((skb))
#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb))
#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb))
#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)
#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)
#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))
#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))
#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
#endif /* DBG_MEM_ALLOC */
extern void* rtw_malloc2d(int h, int w, int size);
extern void rtw_mfree2d(void *pbuf, int h, int w, int size);
extern void _rtw_memcpy(void* dec, void* sour, u32 sz);
extern int _rtw_memcmp(void *dst, void *src, u32 sz);
extern void _rtw_memset(void *pbuf, int c, u32 sz);
extern void _rtw_init_listhead(_list *list);
extern u32 rtw_is_list_empty(_list *phead);
extern void rtw_list_insert_head(_list *plist, _list *phead);
extern void rtw_list_insert_tail(_list *plist, _list *phead);
extern void rtw_list_delete(_list *plist);
extern void _rtw_init_sema(_sema *sema, int init_val);
extern void _rtw_free_sema(_sema *sema);
extern void _rtw_up_sema(_sema *sema);
extern u32 _rtw_down_sema(_sema *sema);
extern void _rtw_mutex_init(_mutex *pmutex);
extern void _rtw_mutex_free(_mutex *pmutex);
extern void _rtw_spinlock_init(_lock *plock);
extern void _rtw_spinlock_free(_lock *plock);
extern void _rtw_spinlock(_lock *plock);
extern void _rtw_spinunlock(_lock *plock);
extern void _rtw_spinlock_ex(_lock *plock);
extern void _rtw_spinunlock_ex(_lock *plock);
extern void _rtw_init_queue(_queue *pqueue);
extern u32 _rtw_queue_empty(_queue *pqueue);
extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement);
extern u32 rtw_get_current_time(void);
extern u32 rtw_systime_to_ms(u32 systime);
extern u32 rtw_ms_to_systime(u32 ms);
extern s32 rtw_get_passing_time_ms(u32 start);
extern s32 rtw_get_time_interval_ms(u32 start, u32 end);
extern void rtw_sleep_schedulable(int ms);
extern void rtw_msleep_os(int ms);
extern void rtw_usleep_os(int us);
extern u32 rtw_atoi(u8* s);
#ifdef DBG_DELAY_OS
#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)
#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)
extern void _rtw_mdelay_os(int ms, const char *func, const int line);
extern void _rtw_udelay_os(int us, const char *func, const int line);
#else
extern void rtw_mdelay_os(int ms);
extern void rtw_udelay_os(int us);
#endif
extern void rtw_yield_os(void);
__inline static unsigned char _cancel_timer_ex(_timer *ptimer)
{
#ifdef PLATFORM_LINUX
return del_timer_sync(ptimer);
#endif
}
static __inline void thread_enter(char *name)
{
#ifdef PLATFORM_LINUX
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
daemonize("%s", name);
#endif
allow_signal(SIGTERM);
#endif
}
__inline static void flush_signals_thread(void)
{
#ifdef PLATFORM_LINUX
if (signal_pending (current))
{
flush_signals(current);
}
#endif
}
__inline static _OS_STATUS res_to_status(sint res)
{
#if defined (PLATFORM_LINUX) || defined (PLATFORM_MPIXEL)
return res;
#endif
}
__inline static void rtw_dump_stack(void)
{
#ifdef PLATFORM_LINUX
dump_stack();
#endif
}
#ifdef PLATFORM_LINUX
#define rtw_warn_on(condition) WARN_ON(condition)
#else
#define rtw_warn_on(condition) do {} while (0)
#endif
#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2)
__inline static u32 _RND4(u32 sz)
{
u32 val;
val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2;
return val;
}
__inline static u32 _RND8(u32 sz)
{
u32 val;
val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3;
return val;
}
__inline static u32 _RND128(u32 sz)
{
u32 val;
val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7;
return val;
}
__inline static u32 _RND256(u32 sz)
{
u32 val;
val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8;
return val;
}
__inline static u32 _RND512(u32 sz)
{
u32 val;
val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9;
return val;
}
__inline static u32 bitshift(u32 bitmask)
{
u32 i;
for (i = 0; i <= 31; i++)
if (((bitmask>>i) & 0x1) == 1) break;
return i;
}
#ifndef MAC_FMT
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#ifndef MAC_ARG
#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
#endif
//#ifdef __GNUC__
#ifdef PLATFORM_LINUX
#define STRUCT_PACKED __attribute__ ((packed))
#else
#define STRUCT_PACKED
#endif
// limitation of path length
#ifdef PLATFORM_LINUX
#define PATH_LENGTH_MAX PATH_MAX
#endif
// Suspend lock prevent system from going suspend
#ifdef CONFIG_WAKELOCK
#include <linux/wakelock.h>
#elif defined(CONFIG_ANDROID_POWER)
#include <linux/android_power.h>
#endif
extern void rtw_suspend_lock_init(void);
extern void rtw_suspend_lock_uninit(void);
extern void rtw_lock_suspend(void);
extern void rtw_unlock_suspend(void);
extern void rtw_lock_suspend_timeout(u32 timeout_ms);
//Atomic integer operations
#ifdef PLATFORM_LINUX
#define ATOMIC_T atomic_t
#endif
extern void ATOMIC_SET(ATOMIC_T *v, int i);
extern int ATOMIC_READ(ATOMIC_T *v);
extern void ATOMIC_ADD(ATOMIC_T *v, int i);
extern void ATOMIC_SUB(ATOMIC_T *v, int i);
extern void ATOMIC_INC(ATOMIC_T *v);
extern void ATOMIC_DEC(ATOMIC_T *v);
extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
extern int ATOMIC_INC_RETURN(ATOMIC_T *v);
extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
//File operation APIs, just for linux now
extern int rtw_is_file_readable(char *path);
extern int rtw_retrive_from_file(char *path, u8* buf, u32 sz);
extern int rtw_store_to_file(char *path, u8* buf, u32 sz);
#if 1 //#ifdef MEM_ALLOC_REFINE_ADAPTOR
struct rtw_netdev_priv_indicator {
void *priv;
u32 sizeof_priv;
};
struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
extern struct net_device * rtw_alloc_etherdev(int sizeof_priv);
#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv )
extern void rtw_free_netdev(struct net_device * netdev);
#else //MEM_ALLOC_REFINE_ADAPTOR
#define rtw_alloc_etherdev(sizeof_priv) alloc_etherdev((sizeof_priv))
#define rtw_netdev_priv(netdev) netdev_priv((netdev))
#define rtw_free_netdev(netdev) free_netdev((netdev))
#endif
#ifdef PLATFORM_LINUX
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ndev->name
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) adapter->pnetdev->name
#define FUNC_NDEV_FMT "%s(%s)"
#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
#define FUNC_ADPT_FMT "%s(%s)"
#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name
#else
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#endif
#ifdef PLATFORM_LINUX
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27))
#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1)
#else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27))
#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27))
#endif //PLATFORM_LINUX
extern u64 rtw_modular64(u64 x, u64 y);
extern u64 rtw_division64(u64 x, u64 y);
/* Macros for handling unaligned memory accesses */
#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
#define RTW_PUT_BE16(a, val) \
do { \
(a)[0] = ((u16) (val)) >> 8; \
(a)[1] = ((u16) (val)) & 0xff; \
} while (0)
#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
#define RTW_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
((u32) (a)[2]))
#define RTW_PUT_BE24(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[2] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
(((u32) (a)[2]) << 8) | ((u32) (a)[3]))
#define RTW_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
(((u32) (a)[1]) << 8) | ((u32) (a)[0]))
#define RTW_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[0] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
(((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
(((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
(((u64) (a)[6]) << 8) | ((u64) (a)[7]))
#define RTW_PUT_BE64(a, val) \
do { \
(a)[0] = (u8) (((u64) (val)) >> 56); \
(a)[1] = (u8) (((u64) (val)) >> 48); \
(a)[2] = (u8) (((u64) (val)) >> 40); \
(a)[3] = (u8) (((u64) (val)) >> 32); \
(a)[4] = (u8) (((u64) (val)) >> 24); \
(a)[5] = (u8) (((u64) (val)) >> 16); \
(a)[6] = (u8) (((u64) (val)) >> 8); \
(a)[7] = (u8) (((u64) (val)) & 0xff); \
} while (0)
#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
(((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
(((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
(((u64) (a)[1]) << 8) | ((u64) (a)[0]))
void rtw_buf_free(u8 **buf, u32 *buf_len);
void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);
struct rtw_cbuf {
u32 write;
u32 read;
u32 size;
void *bufs[0];
};
bool rtw_cbuf_full(struct rtw_cbuf *cbuf);
bool rtw_cbuf_empty(struct rtw_cbuf *cbuf);
bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf);
void *rtw_cbuf_pop(struct rtw_cbuf *cbuf);
struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
void rtw_cbuf_free(struct rtw_cbuf *cbuf);
#endif

32
package/jsda/rtl8192du/include/platform_ops.h
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@ -1,32 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PLATFORM_OPS_H__
#define __PLATFORM_OPS_H__
/*
* Return:
* 0: power on successfully
* others: power on failed
*/
int platform_wifi_power_on(void);
void platform_wifi_power_off(void);
#endif // __PLATFORM_OPS_H__

57
package/jsda/rtl8192du/include/recv_osdep.h
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@ -1,57 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RECV_OSDEP_H_
#define __RECV_OSDEP_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
extern void _rtw_free_recv_priv (struct recv_priv *precvpriv);
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
extern void rtw_recv_returnpacket(_nic_hdl cnxt, _pkt *preturnedpkt);
extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup);
int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
void rtw_free_recv_priv (struct recv_priv *precvpriv);
int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);
int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);
void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf);
int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);
void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);
void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
#endif //

152
package/jsda/rtl8192du/include/rtl8192c_cmd.h
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@ -1,152 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_CMD_H_
#define __RTL8192C_CMD_H_
enum cmd_msg_element_id
{
NONE_CMDMSG_EID,
AP_OFFLOAD_EID=0,
SET_PWRMODE_EID=1,
JOINBSS_RPT_EID=2,
RSVD_PAGE_EID=3,
RSSI_4_EID = 4,
RSSI_SETTING_EID=5,
MACID_CONFIG_EID=6,
MACID_PS_MODE_EID=7,
P2P_PS_OFFLOAD_EID=8,
SELECTIVE_SUSPEND_ROF_CMD=9,
#ifdef CONFIG_WOWLAN
H2C_WO_WLAN_CMD = 26, // Wake on Wlan.
EXT_MACID_PERIOD_EID = 27, // support macid to 64
MACID64_CONFIG_EID = 28, // support macid to 64
#endif // CONFIG_WOWLAN
P2P_PS_CTW_CMD_EID=32,
H2C_92C_IO_OFFLOAD=44,
#ifdef CONFIG_WOWLAN
KEEP_ALIVE_CONTROL_CMD=48,
DISCONNECT_DECISION_CTRL_CMD=49,
REMOTE_WAKE_CTRL_CMD=60,
#endif // CONFIG_WOWLAN
H2C_92C_TSF_SYNC=67,
H2C_92C_DISABLE_BCN_FUNC=68,
H2C_92C_RESET_TSF = 75,
H2C_92C_CMD_MAX
};
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
u8 buf[6];
};
typedef struct _SETPWRMODE_PARM{
u8 Mode;
u8 SmartPS;
u8 BcnPassTime; // unit: 100ms
}SETPWRMODE_PARM, *PSETPWRMODE_PARM;
#ifdef CONFIG_WOWLAN
typedef struct _SETWOWLAN_PARM{
u8 mode;
u8 gpio_index;
u8 gpio_duration;
u8 second_mode;
u8 reserve;
}SETWOWLAN_PARM, *PSETWOWLAN_PARM;
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
#define FW_WOWLAN_MAGIC_PKT BIT(2)
#define FW_WOWLAN_UNICAST BIT(3)
#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
#define FW_FW_PARSE_MAGIC_PKT BIT(1)
#endif // CONFIG_WOWLAN
struct H2C_SS_RFOFF_PARAM{
u8 ROFOn; // 1: on, 0:off
u16 gpio_period; // unit: 1024 us
}__attribute__ ((packed));
typedef struct JOINBSSRPT_PARM{
u8 OpMode; // RT_MEDIA_STATUS
}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM;
typedef struct _RSVDPAGE_LOC{
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
}RSVDPAGE_LOC, *PRSVDPAGE_LOC;
struct P2P_PS_Offload_t {
unsigned char Offload_En:1;
unsigned char role:1; // 1: Owner, 0: Client
unsigned char CTWindow_En:1;
unsigned char NoA0_En:1;
unsigned char NoA1_En:1;
unsigned char AllStaSleep:1; // Only valid in Owner
unsigned char discovery:1;
unsigned char rsvd:1;
};
struct P2P_PS_CTWPeriod_t {
unsigned char CTWPeriod; //TU
};
// host message to firmware cmd
void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param);
u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg);
void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg);
u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter*padapter,u8 bfwpoll, u16 period);
#ifdef CONFIG_P2P
void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
#ifdef CONFIG_IOL
typedef struct _IO_OFFLOAD_LOC{
u8 LocCmd;
}IO_OFFLOAD_LOC, *PIO_OFFLOAD_LOC;
int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
#endif //CONFIG_IOL
#ifdef CONFIG_BEACON_DISABLE_OFFLOAD
u8 rtl8192c_dis_beacon_fun_cmd(_adapter* padapter);
#endif // CONFIG_BEACON_DISABLE_OFFLOAD
#ifdef CONFIG_TSF_RESET_OFFLOAD
int reset_tsf(PADAPTER Adapter, u8 reset_port );
#endif // CONFIG_TSF_RESET_OFFLOAD
#ifdef CONFIG_WOWLAN
void rtl8192c_set_wowlan_cmd(_adapter* padapter);
void SetFwRelatedForWoWLAN8192CU(_adapter* padapter,u8 bHostIsGoingtoSleep);
#endif // CONFIG_WOWLAN
#endif // __RTL8192C_CMD_H_

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package/jsda/rtl8192du/include/rtl8192c_dm.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_DM_H__
#define __RTL8192C_DM_H__
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
//
//
//============================================================
#define RSSI_CCK 0
#define RSSI_OFDM 1
#define RSSI_DEFAULT 2
//============================================================
// structure and define
//============================================================
typedef struct _FALSE_ALARM_STATISTICS{
u32 Cnt_Parity_Fail;
u32 Cnt_Rate_Illegal;
u32 Cnt_Crc8_fail;
u32 Cnt_Mcs_fail;
u32 Cnt_Ofdm_fail;
u32 Cnt_Cck_fail;
u32 Cnt_all;
u32 Cnt_Fast_Fsync;
u32 Cnt_SB_Search_fail;
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef struct _Dynamic_Power_Saving_
{
u8 PreCCAState;
u8 CurCCAState;
u8 PreRFState;
u8 CurRFState;
s32 Rssi_val_min;
}PS_T;
typedef struct _Dynamic_Initial_Gain_Threshold_
{
u8 Dig_Enable_Flag;
u8 Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u32 FALowThresh;
u32 FAHighThresh;
u8 CurSTAConnectState;
u8 PreSTAConnectState;
u8 CurMultiSTAConnectState;
u8 PreIGValue;
u8 CurIGValue;
u8 BackupIGValue;
char BackoffVal;
char BackoffVal_range_max;
char BackoffVal_range_min;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
u8 Rssi_val_min;
u8 PreCCKPDState;
u8 CurCCKPDState;
u8 PreCCKFAState;
u8 CurCCKFAState;
u8 PreCCAState;
u8 CurCCAState;
u8 LargeFAHit;
u8 ForbiddenIGI;
u32 Recover_cnt;
u8 rx_gain_range_min_nolink;
}DIG_T;
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
{
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_PD_STAGE_MAX = 3,
}DM_CCK_PDTH_E;
typedef enum tag_1R_CCA_Type_Definition
{
CCA_1R =0,
CCA_2R = 1,
CCA_MAX = 2,
}DM_1R_CCA_E;
typedef enum tag_RF_Type_Definition
{
RF_Save =0,
RF_Normal = 1,
RF_MAX = 2,
}DM_RF_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
}DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
typedef enum _BT_Ant_NUM{
Ant_x2 = 0,
Ant_x1 = 1
} BT_Ant_NUM, *PBT_Ant_NUM;
typedef enum _BT_CoType{
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR_BC4 = 3,
BT_CSR_BC8 = 4,
BT_RTL8756 = 5,
} BT_CoType, *PBT_CoType;
typedef enum _BT_CurState{
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
BT_Scan = 4,
BT_Idle = 5,
BT_OtherAction = 6,
BT_Busy = 7,
BT_OtherBusy = 8,
BT_PAN = 9,
} BT_ServiceType, *PBT_ServiceType;
typedef enum _BT_RadioShared{
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
} BT_RadioShared, *PBT_RadioShared;
struct btcoexist_priv {
u8 BT_Coexist;
u8 BT_Ant_Num;
u8 BT_CoexistType;
u8 BT_State;
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_Ampdu; // 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU.
u8 BT_RadioSharedType;
u32 Ratio_Tx;
u32 Ratio_PRI;
u8 BtRfRegOrigin1E;
u8 BtRfRegOrigin1F;
u8 BtRssiState;
u32 BtEdcaUL;
u32 BtEdcaDL;
u32 BT_EDCA[2];
u8 bCOBT;
u8 bInitSet;
u8 bBTBusyTraffic;
u8 bBTTrafficModeSet;
u8 bBTNonTrafficModeSet;
//BTTraffic BT21TrafficStatistics;
u32 CurrentState;
u32 PreviousState;
u8 BtPreRssiState;
u8 bFWCoexistAllOff;
u8 bSWCoexistAllOff;
};
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX 0x3e
#define DM_DIG_MIN 0x1e //0x22//0x1c
#define DM_DIG_FA_UPPER 0x3e
#define DM_DIG_FA_LOWER 0x20
#define DM_DIG_FA_TH0 0x20
#define DM_DIG_FA_TH1 0x100
#define DM_DIG_FA_TH2 0x200
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN (-4)
#define DM_DIG_BACKOFF_DEFAULT 10
#define RxPathSelection_SS_TH_low 30
#define RxPathSelection_diff_TH 18
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#define CTSToSelfTHVal 30
#define RegC38_TH 20
#define WAIotTHVal 25
//Dynamic Tx Power Control Threshold
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TxHighPwrLevel_Normal 0
#define TxHighPwrLevel_Level1 1
#define TxHighPwrLevel_Level2 2
#define TxHighPwrLevel_BT1 3
#define TxHighPwrLevel_BT2 4
#define TxHighPwrLevel_15 5
#define TxHighPwrLevel_35 6
#define TxHighPwrLevel_50 7
#define TxHighPwrLevel_70 8
#define TxHighPwrLevel_100 9
#define DM_Type_ByFW 0
#define DM_Type_ByDriver 1
typedef struct _RATE_ADAPTIVE
{
u8 RateAdaptiveDisabled;
u8 RATRState;
u16 reserve;
u32 HighRSSIThreshForRA;
u32 High2LowRSSIThreshForRA;
u8 Low2HighRSSIThreshForRA40M;
u32 LowRSSIThreshForRA40M;
u8 Low2HighRSSIThreshForRA20M;
u32 LowRSSIThreshForRA20M;
u32 UpperRSSIThresholdRATR;
u32 MiddleRSSIThresholdRATR;
u32 LowRSSIThresholdRATR;
u32 LowRSSIThresholdRATR40M;
u32 LowRSSIThresholdRATR20M;
u8 PingRSSIEnable; //cosa add for Netcore long range ping issue
u32 PingRSSIRATR; //cosa add for Netcore long range ping issue
u32 PingRSSIThreshForRA;//cosa add for Netcore long range ping issue
u32 LastRATR;
u8 PreRATRState;
} RATE_ADAPTIVE, *PRATE_ADAPTIVE;
typedef enum tag_SW_Antenna_Switch_Definition
{
Antenna_B = 1,
Antenna_A = 2,
Antenna_MAX = 3,
}DM_SWAS_E;
#ifdef CONFIG_ANTENNA_DIVERSITY
// This indicates two different the steps.
// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
// with original RSSI to determine if it is necessary to switch antenna.
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
#define TP_MODE 0
#define RSSI_MODE 1
#define TRAFFIC_LOW 0
#define TRAFFIC_HIGH 1
typedef struct _SW_Antenna_Switch_
{
u8 try_flag;
s32 PreRSSI;
u8 CurAntenna;
u8 PreAntenna;
u8 RSSI_Trying;
u8 TestMode;
u8 bTriggerAntennaSwitch;
u8 SelectAntennaMap;
// Before link Antenna Switch check
u8 SWAS_NoLink_State;
}SWAT_T;
#endif
struct dm_priv
{
u8 DM_Type;
u8 DMFlag, DMFlag_tmp;
//for DIG
u8 bDMInitialGainEnable;
u8 binitialized; // for dm_initial_gain_Multi_STA use.
DIG_T DM_DigTable;
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
//* Upper and Lower Signal threshold for Rate Adaptive*/
int UndecoratedSmoothedPWDB;
int UndecoratedSmoothedCCK;
int EntryMinUndecoratedSmoothedPWDB;
int EntryMaxUndecoratedSmoothedPWDB;
//for High Power
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
//for tx power tracking
//u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u8 ThermalValue;
u8 ThermalValue_LCK;
u8 ThermalValue_IQK;
u8 ThermalValue_DPK;
u8 bRfPiEnable;
//for APK
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
//for IQK
u32 RegC04;
u32 Reg874;
u32 RegC08;
u32 RegB68;
u32 RegB6C;
u32 Reg870;
u32 Reg860;
u32 Reg864;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u8 PowerIndex_backup[6];
u8 bCCKinCH14;
char CCK_index;
char OFDM_index[2];
BOOLEAN bDoneTxpower;
char CCK_index_HP;
char OFDM_index_HP[2];
u8 ThermalValue_HP[HP_THERMAL_NUM];
u8 ThermalValue_HP_index;
//for TxPwrTracking
int RegE94;
int RegE9C;
int RegEB4;
int RegEBC;
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
u32 prv_traffic_idx; // edca turbo
// for dm_RF_Saving
u8 initialize;
u32 rf_saving_Reg874;
u32 rf_saving_RegC70;
u32 rf_saving_Reg85C;
u32 rf_saving_RegA74;
//for Antenna diversity
#ifdef CONFIG_ANTENNA_DIVERSITY
SWAT_T DM_SWAT_Table;
#endif
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
_timer SwAntennaSwitchTimer;
u64 lastTxOkCnt;
u64 lastRxOkCnt;
u64 TXByteCnt_A;
u64 TXByteCnt_B;
u64 RXByteCnt_A;
u64 RXByteCnt_B;
u8 DoubleComfirm;
u8 TrafficLoad;
#endif
s32 OFDM_Pkt_Cnt;
u8 RSSI_Select;
u8 DIG_Dynamic_MIN ;
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
u8 INIDATA_RATE[32];
};
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
//============================================================
// function prototype
//============================================================
void rtl8192c_init_dm_priv(IN PADAPTER Adapter);
void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8192c_InitHalDm(IN PADAPTER Adapter);
void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter);
VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter);
void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal);
VOID DM_Write_DIG(IN PADAPTER pAdapter);
#ifdef CONFIG_BT_COEXIST
void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart);
void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir);
#endif
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
void SwAntDivRSSICheck8192C(_adapter *padapter ,u32 RxPWDBAll);
void SwAntDivRestAfterLink8192C(IN PADAPTER Adapter);
#endif
#ifdef CONFIG_ANTENNA_DIVERSITY
void SwAntDivCompare8192C(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
u8 SwAntDivBeforeLink8192C(IN PADAPTER Adapter);
#endif
#endif //__HAL8190PCIDM_H__

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package/jsda/rtl8192du/include/rtl8192c_event.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_EVENT_H_
#define _RTL8192C_EVENT_H_
#endif

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package/jsda/rtl8192du/include/rtl8192c_hal.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_HAL_H__
#define __RTL8192C_HAL_H__
#include "hal_com.h"
#include "rtl8192c_spec.h"
#include "Hal8192CPhyReg.h"
#include "Hal8192CPhyCfg.h"
#include "rtl8192c_rf.h"
#include "rtl8192c_dm.h"
#include "rtl8192c_recv.h"
#include "rtl8192c_xmit.h"
#include "rtl8192c_cmd.h"
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8192c_sreset.h"
#endif
#include "rtw_efuse.h"
#include "Hal8192CUHWImg.h"
#ifdef CONFIG_WOWLAN
#include "Hal8192CUHWImg_wowlan.h"
#endif //CONFIG_WOWLAN
//2TODO: We should define 8192S firmware related macro settings here!!
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
//TODO: The following need to check!!
#define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin"
#define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
#ifdef CONFIG_WOWLAN
#define RTL8192C_FW_TSMC_WW_IMG "rtl8192CU\\rtl8192cfwTww.bin"
#define RTL8192C_FW_UMC_WW_IMG "rtl8192CU\\rtl8192cfwUww.bin"
#define RTL8192C_FW_UMC_B_WW_IMG "rtl8192CU\\rtl8192cfwU_Bww.bin"
#endif // CONFIG_WOWLAN
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
//#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
//#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
#define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt"
#define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
#define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
#define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
#define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
#define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
#define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt"
#define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt"
#define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt"
#define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt"
#define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt"
#define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt"
//---------------------------------------------------------------------
// RTL8723U From file
//---------------------------------------------------------------------
#define RTL8723_FW_UMC_IMG "rtl8723U\\rtl8723fw.bin"
#define RTL8723_PHY_REG "rtl8723U\\PHY_REG_1T.txt"
#define RTL8723_PHY_RADIO_A "rtl8723U\\radio_a_1T.txt"
#define RTL8723_PHY_RADIO_B "rtl8723U\\radio_b_1T.txt"
#define RTL8723_AGC_TAB "rtl8723U\\AGC_TAB_1T.txt"
#define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt"
#define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt"
#define RTL8723_PHY_REG_PG "rtl8723U\\PHY_REG_PG.txt"
#define RTL8723_PHY_REG_MP "rtl8723U\\PHY_REG_MP.txt"
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
#define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray
#ifdef CONFIG_WOWLAN
#define Rtl8192C_FwTSMCWWImageArray Rtl8192CUFwTSMCWWImgArray
#define Rtl8192C_FwUMCWWImageArray Rtl8192CUFwUMCACutWWImgArray
#define Rtl8192C_FwUMCBCutWWImageArray Rtl8192CUFwUMCBCutWWImgArray
#endif //CONFIG_WOWLAN
#define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray
#define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
#define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
#define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define DRVINFO_SZ 4 // unit is 8bytes
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
#define FW_8192C_SIZE 16384+32//16k
#define FW_8192C_START_ADDRESS 0x1000
//#define FW_8192C_END_ADDRESS 0x3FFF //Filen said this is for test chip
#define FW_8192C_END_ADDRESS 0x1FFF
#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
typedef enum _FIRMWARE_SOURCE{
FW_SOURCE_IMG_FILE = 0,
FW_SOURCE_HEADER_FILE = 1, //from header file
}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
typedef struct _RT_FIRMWARE{
FIRMWARE_SOURCE eFWSource;
u8* szFwBuffer;
u32 ulFwLength;
#ifdef CONFIG_WOWLAN
u8* szWoWLANFwBuffer;
u32 ulWoWLANFwLength;
#endif //CONFIG_WOWLAN
}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92C, *PRT_FIRMWARE_92C;
//
// This structure must be cared byte-ordering
//
// Added by tynli. 2009.12.04.
typedef struct _RT_8192C_FIRMWARE_HDR {//8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
u8 Category; // AP/NIC and USB/PCI
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
u16 Version; // FW Version
u8 Subversion; // FW Subversion, default 0x00
u16 Rsvd1;
//--- LONG WORD 1 ----
u8 Month; // Release time Month field
u8 Date; // Release time Date field
u8 Hour; // Release time Hour field
u8 Minute; // Release time Minute field
u16 RamCodeSize; // The size of RAM code
u16 Rsvd2;
//--- LONG WORD 2 ----
u32 SvnIdx; // The SVN entry index
u32 Rsvd3;
//--- LONG WORD 3 ----
u32 Rsvd4;
u32 Rsvd5;
}RT_8192C_FIRMWARE_HDR, *PRT_8192C_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME 0x05
#define BCN_DMA_ATIME_INT_TIME 0x02
#ifdef CONFIG_USB_RX_AGGREGATION
typedef enum _USB_RX_AGG_MODE{
USB_RX_AGG_DISABLE,
USB_RX_AGG_DMA,
USB_RX_AGG_USB,
USB_RX_AGG_MIX
}USB_RX_AGG_MODE;
#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
#endif
#define TX_SELE_HQ BIT(0) // High Queue
#define TX_SELE_LQ BIT(1) // Low Queue
#define TX_SELE_NQ BIT(2) // Normal Queue
// Note: We will divide number of page equally for each queue other than public queue!
#define TX_TOTAL_PAGE_NUMBER 0xF8
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
#define NORMAL_PAGE_NUM_PUBQ 0xE7
#define NORMAL_PAGE_NUM_HPQ 0x0C
#define NORMAL_PAGE_NUM_LPQ 0x02
#define NORMAL_PAGE_NUM_NPQ 0x02
// For Test Chip Setting
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
#define TEST_PAGE_NUM_PUBQ 0x7E
// For Test Chip Setting
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
#define WMM_TEST_PAGE_NUM_HPQ 0x29
#define WMM_TEST_PAGE_NUM_LPQ 0x29
//Note: For Normal Chip Setting ,modify later
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_NORMAL_PAGE_NUM_PUBQ 0x65
#define WMM_NORMAL_PAGE_NUM_HPQ 0x30
#define WMM_NORMAL_PAGE_NUM_LPQ 0x30
#define WMM_NORMAL_PAGE_NUM_NPQ 0x30
//-------------------------------------------------------------------------
// Chip specific
//-------------------------------------------------------------------------
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_BONDING_88C_USB_MCARD 0x2
#define CHIP_BONDING_88C_USB_HP 0x1
//
// 2011.01.06. Define new structure of chip version for RTL8723 and so on. Added by tynli.
//
/*
| BIT15:12 | BIT11:8 | BIT 7 | BIT6:4 | BIT3 | BIT2:0 |
|-------------+-----------+-----------+-------+-----------+-------|
| IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Type |
| | | TSMC/UMC | | TEST/NORMAL| |
*/
// [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
// [7] Manufacturer: TSMC=0, UMC=1
// [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
// [3] Chip type: TEST=0, NORMAL=1
// [2:0] IC type: 81xxC=0, 8723=1, 92D=2
#define CHIP_8723 BIT(0)
#define CHIP_92D BIT(1)
#define NORMAL_CHIP BIT(3)
#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
#define RF_TYPE_1T2R BIT(4)
#define RF_TYPE_2T2R BIT(5)
#define CHIP_VENDOR_UMC BIT(7)
#define B_CUT_VERSION BIT(12)
#define C_CUT_VERSION BIT(13)
#define D_CUT_VERSION ((BIT(13)|BIT(14)))
// MASK
#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
#define CHIP_TYPE_MASK BIT(3)
#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
#define MANUFACTUER_MASK BIT(7)
#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
// Get element
#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? _TRUE : _FALSE)
#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723)? _TRUE : _FALSE)
#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? _TRUE : _FALSE)
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? _FALSE : _TRUE)
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? _TRUE : _FALSE)
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? _TRUE : _FALSE)
#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version))? _TRUE: _FALSE)
#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version))? _TRUE: _FALSE)
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE)
#define IS_92D_TEST_CHIP(version) ((IS_92D(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? _TRUE : _FALSE)
#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
// <tynli_Note> 88/92C UMC B-cut vendor is set to TSMC so we need to check CHIP_VENDOR_UMC bit is not 1.
#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? _TRUE : _FALSE):_FALSE)
#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? _TRUE: _FALSE) : _FALSE)
#define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x2) ? _TRUE : _FALSE) : _FALSE)
#define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x3) ? _TRUE : _FALSE) : _FALSE)
typedef enum _VERSION_8192C{
VERSION_TEST_CHIP_88C = 0x0000,
VERSION_TEST_CHIP_92C = 0x0020,
VERSION_TEST_UMC_CHIP_8723 = 0x0081,
VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
VERSION_TEST_CHIP_92D_SINGLEPHY= 0x0022,
VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
VERSION_NORMAL_CHIP_92D_SINGLEPHY= 0x002a,
VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
}VERSION_8192C,*PVERSION_8192C;
//-------------------------------------------------------------------------
// Channel Plan
//-------------------------------------------------------------------------
enum ChannelPlan{
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPAIN = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,
CHPL_ISRAEL = 7,
CHPL_TELEC = 8,
CHPL_GLOBAL = 9,
CHPL_WORLD = 10,
};
typedef struct _TxPowerInfo{
u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 TSSI_A;
u8 TSSI_B;
}TxPowerInfo, *PTxPowerInfo;
#define EFUSE_REAL_CONTENT_LEN 512
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
//
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 1byte|----8bytes----|1byte|--5bytes--|
// | | Reserved(14bytes) |
//
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
#define EFUSE_MAP_LEN_8723 256
#define EFUSE_MAX_SECTION_8723 32
//========================================================
// EFUSE for BT definition
//========================================================
#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
#define EFUSE_BT_MAX_SECTION 128 // 1024/8
#define EFUSE_PROTECT_BYTES_BANK 16
//
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
//
typedef enum _RT_MULTI_FUNC{
RT_MULTI_FUNC_NONE = 0x00,
RT_MULTI_FUNC_WIFI = 0x01,
RT_MULTI_FUNC_BT = 0x02,
RT_MULTI_FUNC_GPS = 0x04,
}RT_MULTI_FUNC,*PRT_MULTI_FUNC;
//
// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
//
typedef enum _RT_POLARITY_CTL{
RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1,
}RT_POLARITY_CTL,*PRT_POLARITY_CTL;
// For RTL8723 regulator mode. by tynli. 2011.01.14.
typedef enum _RT_REGULATOR_MODE{
RT_SWITCHING_REGULATOR = 0,
RT_LDO_REGULATOR = 1,
}RT_REGULATOR_MODE,*PRT_REGULATOR_MODE;
enum c2h_id_8192c {
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3,
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_EXT_RA_RPT = 6,
C2H_HW_INFO_EXCH = 10,
C2H_C2H_H2C_TEST = 11,
C2H_BT_INFO = 12,
C2H_BT_MP_INFO = 15,
MAX_C2HEVENT
};
struct hal_data_8192cu
{
VERSION_8192C VersionID;
RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
u16 CustomerID;
u16 FirmwareVersion;
u16 FirmwareVersionRev;
u16 FirmwareSubVersion;
//current WIFI_PHY values
u32 ReceiveConfig;
WIRELESS_MODE CurrentWirelessMode;
HT_CHANNEL_WIDTH CurrentChannelBW;
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
u16 BasicRateSet;
//rf_ctrl
u8 rf_chip;
u8 rf_type;
u8 NumTotalRFPath;
u8 BoardType;
//INTERFACE_SELECT_8192CUSB InterfaceSel;
//
// EEPROM setting.
//
u16 EEPROMVID;
u16 EEPROMPID;
u16 EEPROMSVID;
u16 EEPROMSDID;
u8 EEPROMCustomerID;
u8 EEPROMSubCustomerID;
u8 EEPROMVersion;
u8 EEPROMRegulatory;
u8 bTXPowerDataReadFromEEPORM;
u8 EEPROMThermalMeter;
u8 bIQKInitialized;
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
// Read/write are allow for following hardware information variables
u8 framesync;
u32 framesyncC34;
u8 framesyncMonitor;
u8 DefaultInitialGain[4];
u8 pwrGroupCnt;
u32 MCSTxPowerLevelOriginalOffset[7][16];
u32 CCKTxPowerLevelOriginalOffset;
u32 AntennaTxPath; // Antenna path Tx
u32 AntennaRxPath; // Antenna path Rx
u8 BluetoothCoexist;
u8 ExternalPA;
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
//u32 LedControlNum;
//u32 LedControlMode;
//u32 TxPowerTrackControl;
u8 b1x1RecvCombine; // for 1T1R receive combining
u8 bCurrentTurboEDCA;
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
//vivi, for tx power tracking, 20080407
//u16 TSSI_13dBm;
//u32 Pwr_Track;
// The current Tx Power Level
u8 CurrentCckTxPwrIdx;
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
u32 RfRegChnlVal[2];
u8 bCckHighPower;
//RDG enable
BOOLEAN bRDGEnable;
//for host message to fw
u8 LastHMEBoxNum;
u8 fw_ractrl;
u8 RegTxPause;
// Beacon function related global variable.
u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
struct dm_priv dmpriv;
#ifdef DBG_CONFIG_ERROR_DETECT
struct sreset_priv srestpriv;
#endif
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
u8 CurAntenna;
u8 AntDivCfg;
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//SW Antenna Switch
s32 RSSI_sum_A;
s32 RSSI_sum_B;
s32 RSSI_cnt_A;
s32 RSSI_cnt_B;
BOOLEAN RSSI_test;
#endif
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
u32 CCK_Ant1_Cnt;
u32 CCK_Ant2_Cnt;
u32 OFDM_Ant1_Cnt;
u32 OFDM_Ant2_Cnt;
#endif
u8 bDumpRxPkt;//for debug
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
// 2010/08/09 MH Add CU power down mode.
BOOLEAN pwrdown;
// For 92C USB endpoint setting
//
u32 UsbBulkOutSize;
int RtBulkOutPipe[3];
int RtBulkInPipe;
int RtIntInPipe;
// Add for dual MAC 0--Mac0 1--Mac1
u32 interfaceIndex;
u8 OutEpQueueSel;
u8 OutEpNumber;
u8 Queue2EPNum[8];//for out endpoint number mapping
#ifdef CONFIG_USB_TX_AGGREGATION
u8 UsbTxAggMode;
u8 UsbTxAggDescNum;
#endif
#ifdef CONFIG_USB_RX_AGGREGATION
u16 HwRxPageSize; // Hardware setting
u32 MaxUsbRxAggBlock;
USB_RX_AGG_MODE UsbRxAggMode;
u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
u8 UsbRxAggBlockTimeout;
u8 UsbRxAggPageCount; // 8192C DMA page count
u8 UsbRxAggPageTimeout;
#endif
// 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
BOOLEAN UsbRxHighSpeedMode;
// 2010/11/22 MH Add for slim combo debug mode selective.
// This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
BOOLEAN SlimComboDbg;
u16 EfuseUsedBytes;
EFUSE_HAL EfuseHal;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
#endif //CONFIG_P2P
};
typedef struct hal_data_8192cu HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
VOID rtl8192c_FirmwareSelfReset(IN PADAPTER Adapter);
int FirmwareDownload92C(IN PADAPTER Adapter,IN BOOLEAN bUsedWoWLANFw);
VOID InitializeFirmwareVars92C(PADAPTER Adapter);
u8 GetEEPROMSize8192C(PADAPTER Adapter);
void rtl8192c_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
VERSION_8192C rtl8192c_ReadChipVersion(IN PADAPTER Adapter);
void rtl8192c_ReadBluetoothCoexistInfo(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
//void rtl8192c_free_hal_data(_adapter * padapter);
VOID rtl8192c_EfuseParseIDCode(PADAPTER pAdapter, u8 *hwinfo);
void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc);
s32 c2h_id_filter_ccx_8192c(u8 id);
void SetHwReg8192C(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8192C(PADAPTER padapter, u8 variable, u8 *val);
u8 SetHalDefVar8192C(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val);
u8 GetHalDefVar8192C(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val);
#endif
#ifdef CONFIG_MP_INCLUDED
extern void Hal_SetAntenna(PADAPTER pAdapter);
extern void Hal_SetBandwidth(PADAPTER pAdapter);
extern void Hal_SetTxPower(PADAPTER pAdapter);
extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart );
extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart);
extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart);
extern void Hal_SetDataRate(PADAPTER pAdapter);
extern void Hal_SetChannel(PADAPTER pAdapter);
extern void Hal_SetAntennaPathPower(PADAPTER pAdapter);
extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable);
extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable);
extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value);
extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven);
extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower);
extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower);
extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter);
extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter);
extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart);
extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart);
#endif

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package/jsda/rtl8192du/include/rtl8192c_led.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_LED_H_
#define __RTL8192C_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
void rtl8192cu_InitSwLeds(_adapter *padapter);
void rtl8192cu_DeInitSwLeds(_adapter *padapter);
#endif

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package/jsda/rtl8192du/include/rtl8192c_recv.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_RECV_H_
#define _RTL8192C_RECV_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_SINGLE_RECV_BUF
#define NR_RECVBUFF (1)
#else
#define NR_RECVBUFF (4)
#endif //CONFIG_SINGLE_RECV_BUF
#define NR_PREALLOC_RECV_SKB (8)
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
//#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#endif
#define RECV_BULK_IN_ADDR 0x80
#define RECV_INT_IN_ADDR 0x81
#define PHY_RSSI_SLID_WIN_MAX 100
#define PHY_LINKQUALITY_SLID_WIN_MAX 20
struct phy_stat
{
unsigned int phydw0;
unsigned int phydw1;
unsigned int phydw2;
unsigned int phydw3;
unsigned int phydw4;
unsigned int phydw5;
unsigned int phydw6;
unsigned int phydw7;
};
typedef struct _Phy_OFDM_Rx_Status_Report_8192cd
{
unsigned char trsw_gain_X[4];
unsigned char pwdb_all;
unsigned char cfosho_X[4];
unsigned char cfotail_X[4];
unsigned char rxevm_X[2];
unsigned char rxsnr_X[4];
unsigned char pdsnr_X[2];
unsigned char csi_current_X[2];
unsigned char csi_target_X[2];
unsigned char sigevm;
unsigned char max_ex_pwr;
//#ifdef RTL8192SE
#ifdef __LITTLE_ENDIAN
unsigned char ex_intf_flg:1;
unsigned char sgi_en:1;
unsigned char rxsc:2;
//unsigned char rsvd:4;
unsigned char idle_long:1;
unsigned char r_ant_train_en:1;
unsigned char ANTSELB:1;
unsigned char ANTSEL:1;
#else // __BIG_ENDIAN_
//unsigned char rsvd:4;
unsigned char ANTSEL:1;
unsigned char ANTSELB:1;
unsigned char r_ant_train_en:1;
unsigned char idle_long:1;
unsigned char rxsc:2;
unsigned char sgi_en:1;
unsigned char ex_intf_flg:1;
#endif
//#else // RTL8190, RTL8192E
// unsigned char sgi_en;
// unsigned char rxsc_sgien_exflg;
//#endif
} __attribute__ ((packed))PHY_STS_OFDM_8192CD_T,PHY_RX_DRIVER_INFO_8192CD;
typedef struct _Phy_CCK_Rx_Status_Report_8192cd
{
/* For CCK rate descriptor. This is a signed 8:1 variable. LSB bit presend
0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
u8 adc_pwdb_X[4];
u8 SQ_rpt;
u8 cck_agc_rpt;
} PHY_STS_CCK_8192CD_T;
// Rx smooth factor
#define Rx_Smooth_Factor (20)
typedef struct _INTERRUPT_MSG_FORMAT_EX{
unsigned int C2H_MSG0;
unsigned int C2H_MSG1;
unsigned int C2H_MSG2;
unsigned int C2H_MSG3;
unsigned int HISR; // from HISR Reg0x124, read to clear
unsigned int HISRE;// from HISRE Reg0x12c, read to clear
unsigned int MSG_EX;
}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;
void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
int rtl8192cu_init_recv_priv(_adapter * padapter);
void rtl8192cu_free_recv_priv(_adapter * padapter);
void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_info);
void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
#endif

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package/jsda/rtl8192du/include/rtl8192c_rf.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192c_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192C_RF_H_
#define _RTL8192C_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192c_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192c_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
VOID rtl8192c_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192C( IN PADAPTER Adapter );
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */

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package/jsda/rtl8192du/include/rtl8192c_spec.h
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32
package/jsda/rtl8192du/include/rtl8192c_sreset.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_SRESET_C_
#define _RTL8192C_SRESET_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8192c_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8192c_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

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package/jsda/rtl8192du/include/rtl8192c_xmit.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_XMIT_H_
#define _RTL8192C_XMIT_H_
//
// Queue Select Value in TxDesc
//
#define QSLT_BK 0x2//0x01
#define QSLT_BE 0x0
#define QSLT_VI 0x5//0x4
#define QSLT_VO 0x7//0x6
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
struct txrpt_ccx_8192c {
/* offset 0 */
u8 retry_cnt:6;
u8 rsvd_0:2;
/* offset 1 */
u8 rts_retry_cnt:6;
u8 rsvd_1:2;
/* offset 2 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 4 */
u8 missed_pkt_num:5;
u8 rsvd_4:3;
/* offset 5 */
u8 mac_id:5;
u8 des1_fragssn:3;
/* offset 6 */
u8 rpt_pkt_num:5;
u8 pkt_drop:1;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 7*/
u8 edca_tx_queue:4;
u8 rsvd_7:1;
u8 bmc:1;
u8 pkt_ok:1;
u8 int_ccx:1;
};
#define txrpt_ccx_qtime_8192c(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_8192c(void *buf);
void handle_txrpt_ccx_8192c(_adapter *adapter, void *buf);
#else
#define dump_txrpt_ccx_8192c(buf) do {} while(0)
#define handle_txrpt_ccx_8192c(adapter, buf) do {} while(0)
#endif
#ifdef CONFIG_USB_TX_AGGREGATION
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
#endif
s32 rtl8192cu_init_xmit_priv(_adapter * padapter);
void rtl8192cu_free_xmit_priv(_adapter * padapter);
void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc);
s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
s32 rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8192cu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
#endif

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package/jsda/rtl8192du/include/rtl8192d_cmd.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_CMD_H_
#define __RTL8192D_CMD_H_
//--------------------------------------------
//3 Host Message Box
//--------------------------------------------
// User Define Message [31:8]
//_SETPWRMODE_PARM
#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
//JOINBSSRPT_PARM
#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
//_RSVDPAGE_LOC
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
//P2P_PS_OFFLOAD
struct P2P_PS_Offload_t {
unsigned char Offload_En:1;
unsigned char role:1; // 1: Owner, 0: Client
unsigned char CTWindow_En:1;
unsigned char NoA0_En:1;
unsigned char NoA1_En:1;
unsigned char AllStaSleep:1; // Only valid in Owner
unsigned char discovery:1;
unsigned char rsvd:1;
};
#define SET_H2CCMD_P2P_PS_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_CTW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
// Description: Determine the types of H2C commands that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _RTL8192D_H2C_CMD
{
H2C_AP_OFFLOAD = 0, /*0*/
H2C_SETPWRMODE = 1, /*1*/
H2C_JOINBSSRPT = 2, /*2*/
H2C_RSVDPAGE = 3,
H2C_RSSI_REPORT = 5,
H2C_RA_MASK = 6,
H2C_P2P_PS_OFFLOAD = 8,
H2C_MAC_MODE_SEL = 9,
H2C_PWRM=15,
#ifdef CONFIG_WOWLAN
H2C_WO_WLAN_CMD = 20, // Wake on Wlan.
#endif // CONFIG_WOWLAN
H2C_P2P_PS_CTW_CMD = 24,
H2C_PathDiv = 26, //PathDiv--NeilChen--2011.07.15
#ifdef CONFIG_WOWLAN
KEEP_ALIVE_CONTROL_CMD=31, //keep alive for wake on wlan
DISCONNECT_DECISION_CTRL_CMD=32,
REMOTE_WAKE_CTRL_CMD=34,
#endif // CONFIG_WOWLAN
H2C_92D_TSF_SYNC=36,
H2C_92D_RESET_TSF = 43,
H2C_CMD_MAX
}RTL8192D_H2C_CMD;
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
u8 buf[6];
};
void FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer);
// host message to firmware cmd
void rtl8192d_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
void rtl8192d_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
u8 rtl8192d_set_rssi_cmd(_adapter*padapter, u8 *param);
u8 rtl8192d_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg);
void rtl8192d_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg);
#ifdef CONFIG_P2P
void rtl8192d_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
#ifdef CONFIG_TSF_RESET_OFFLOAD
int reset_tsf(PADAPTER Adapter, u8 reset_port );
#endif // CONFIG_TSF_RESET_OFFLOAD
#ifdef CONFIG_WOWLAN
typedef struct _SETWOWLAN_PARM{
u8 mode;
u8 gpio_index;
u8 gpio_duration;
u8 second_mode;
u8 reserve;
}SETWOWLAN_PARM, *PSETWOWLAN_PARM;
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
#define FW_WOWLAN_MAGIC_PKT BIT(2)
#define FW_WOWLAN_UNICAST BIT(3)
#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
#define FW_FW_PARSE_MAGIC_PKT BIT(1)
void rtl8192d_set_wowlan_cmd(_adapter* padapter);
void SetFwRelatedForWoWLAN8192DU(_adapter* padapter,u8 bHostIsGoingtoSleep);
#endif // CONFIG_WOWLAN
#endif // __RTL8192D_CMD_H_

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package/jsda/rtl8192du/include/rtl8192d_dm.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_DM_H__
#define __RTL8192D_DM_H__
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
//
//
//============================================================
//============================================================
// Global var
//============================================================
extern u32 EDCAParam[maxAP][3] ;
//============================================================
// structure and define
//============================================================
typedef struct _FALSE_ALARM_STATISTICS{
u32 Cnt_Parity_Fail;
u32 Cnt_Rate_Illegal;
u32 Cnt_Crc8_fail;
u32 Cnt_Mcs_fail;
u32 Cnt_Ofdm_fail;
u32 Cnt_Cck_fail;
u32 Cnt_all;
u32 Cnt_Fast_Fsync;
u32 Cnt_SB_Search_fail;
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef struct _Dynamic_Power_Saving_
{
u8 PreCCAState;
u8 CurCCAState;
u8 PreRFState;
u8 CurRFState;
//int Rssi_val_min;
}PS_T,*pPS_T;
typedef struct _Dynamic_Initial_Gain_Threshold_
{
u8 Dig_Enable_Flag;
u8 Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u32 FALowThresh;
u32 FAHighThresh;
u8 CurSTAConnectState;
u8 PreSTAConnectState;
u8 CurMultiSTAConnectState;
u8 PreIGValue;
u8 CurIGValue;
u8 BackupIGValue;
char BackoffVal;
char BackoffVal_range_max;
char BackoffVal_range_min;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
u8 Rssi_val_min;
u8 PreCCKPDState;
u8 CurCCKPDState;
u8 LargeFAHit;
u8 ForbiddenIGI;
u32 Recover_cnt;
u8 rx_gain_range_min_nolink;
}DIG_T,*pDIG_T;
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
{
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_PD_STAGE_MAX = 3,
}DM_CCK_PDTH_E;
typedef enum tag_1R_CCA_Type_Definition
{
CCA_MIN = 0,
CCA_1R =1,
CCA_2R = 2,
CCA_MAX = 3,
}DM_1R_CCA_E;
typedef enum tag_RF_Type_Definition
{
RF_Save =0,
RF_Normal = 1,
RF_MAX = 2,
}DM_RF_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
}DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX 0x3e
#define DM_DIG_MIN 0x1e //0x22//0x1c
#define DM_DIG_FA_UPPER 0x32
#define DM_DIG_FA_LOWER 0x20
//vivi 92c&92d has different definition, 20110504
//this is for 92c
#define DM_DIG_FA_TH0 0x200//0x20
#define DM_DIG_FA_TH1 0x300//0x100
#define DM_DIG_FA_TH2 0x400//0x200
//this is for 92d
#define DM_DIG_FA_TH0_92D 0x100
#define DM_DIG_FA_TH1_92D 0x150
#define DM_DIG_FA_TH2_92D 0x250
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN (-4)
#define DM_DIG_BACKOFF_DEFAULT 10
#define RxPathSelection_SS_TH_low 30
#define RxPathSelection_diff_TH 18
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#define CTSToSelfTHVal 30
#define RegC38_TH 20
#define WAIotTHVal 25
//Dynamic Tx Power Control Threshold
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TxHighPwrLevel_Normal 0
#define TxHighPwrLevel_Level1 1
#define TxHighPwrLevel_Level2 2
#define TxHighPwrLevel_BT1 3
#define TxHighPwrLevel_BT2 4
#define TxHighPwrLevel_15 5
#define TxHighPwrLevel_35 6
#define TxHighPwrLevel_50 7
#define TxHighPwrLevel_70 8
#define TxHighPwrLevel_100 9
#define DM_Type_ByFW 0
#define DM_Type_ByDriver 1
typedef struct _RATE_ADAPTIVE
{
u8 RateAdaptiveDisabled;
u8 RATRState;
u16 reserve;
u32 HighRSSIThreshForRA;
u32 High2LowRSSIThreshForRA;
u8 Low2HighRSSIThreshForRA40M;
u32 LowRSSIThreshForRA40M;
u8 Low2HighRSSIThreshForRA20M;
u32 LowRSSIThreshForRA20M;
u32 UpperRSSIThresholdRATR;
u32 MiddleRSSIThresholdRATR;
u32 LowRSSIThresholdRATR;
u32 LowRSSIThresholdRATR40M;
u32 LowRSSIThresholdRATR20M;
u8 PingRSSIEnable; //cosa add for Netcore long range ping issue
u32 PingRSSIRATR; //cosa add for Netcore long range ping issue
u32 PingRSSIThreshForRA;//cosa add for Netcore long range ping issue
u32 LastRATR;
u8 PreRATRState;
} RATE_ADAPTIVE, *PRATE_ADAPTIVE;
typedef enum tag_SW_Antenna_Switch_Definition
{
Antenna_B = 1,
Antenna_A = 2,
Antenna_MAX = 3,
}DM_SWAS_E;
// 20100514 Joseph: Add definition for antenna switching test after link.
// This indicates two different the steps.
// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
// with original RSSI to determine if it is necessary to switch antenna.
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
#define TP_MODE 0
#define RSSI_MODE 1
#define TRAFFIC_LOW 0
#define TRAFFIC_HIGH 1
//=============================
//Neil Chen---2011--06--15--
//==============================
//3 PathDiv
typedef struct _SW_Antenna_Switch_
{
u8 try_flag;
s32 PreRSSI;
u8 CurAntenna;
u8 PreAntenna;
u8 RSSI_Trying;
u8 TestMode;
u8 bTriggerAntennaSwitch;
u8 SelectAntennaMap;
// Before link Antenna Switch check
u8 SWAS_NoLink_State;
u32 SWAS_NoLink_BK_Reg860;
}SWAT_T, *pSWAT_T;
//========================================
struct dm_priv
{
u8 DM_Type;
u8 DMFlag, DMFlag_tmp;
//for DIG
u8 bDMInitialGainEnable;
//u8 binitialized; // for dm_initial_gain_Multi_STA use.
DIG_T DM_DigTable;
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
//* Upper and Lower Signal threshold for Rate Adaptive*/
int UndecoratedSmoothedPWDB;
int EntryMinUndecoratedSmoothedPWDB;
int EntryMaxUndecoratedSmoothedPWDB;
int MinUndecoratedPWDBForDM;
int LastMinUndecoratedPWDBForDM;
#ifdef CONFIG_DUALMAC_CONCURRENT
int RssiValMinForAnotherMacOfDMSP;
u32 CurDigValueForAnotherMacOfDMSP;
BOOLEAN bWriteDigForAnotherMacOfDMSP;
BOOLEAN bChangeCCKPDStateForAnotherMacOfDMSP;
u8 CurCCKPDStateForAnotherMacOfDMSP;
BOOLEAN bChangeTxHighPowerLvlForAnotherMacOfDMSP;
u8 CurTxHighLvlForAnotherMacOfDMSP;
#endif
//for High Power
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u8 ThermalValue;
u8 ThermalValue_Variation; // 0: decrease 1:increase
u8 ThermalValue_LCK;
u8 ThermalValue_IQK;
u8 ThermalValue_AVG[AVG_THERMAL_NUM];
u8 ThermalValue_AVG_index;
u8 ThermalValue_RxGain;
u8 ThermalValue_Crystal;
u8 Delta_IQK;
u8 Delta_LCK;
u8 bRfPiEnable;
u8 bReloadtxpowerindex;
u8 bDoneTxpower;
//for APK
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
BOOLEAN bDPKdone[2];
BOOLEAN bDPKstore;
BOOLEAN bDPKworking;
u8 OFDM_min_index_internalPA_DPK[2];
u8 TxPowerLevelDPK[2];
u32 RegA24;
//for IQK
u32 Reg874;
u32 RegC08;
u32 Reg88C;
u8 Reg522;
u8 Reg550;
u8 Reg551;
u32 Reg870;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u8 bCCKinCH14;
char CCK_index;
//u8 Record_CCK_20Mindex;
//u8 Record_CCK_40Mindex;
char OFDM_index[2];
SWAT_T DM_SWAT_Table;
//for TxPwrTracking
int RegE94;
int RegE9C;
int RegEB4;
int RegEBC;
#if MP_DRIVER == 1
u8 RegC04_MP;
u32 RegD04_MP;
#endif
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
u32 prv_traffic_idx; // edca turbo
u32 RegRF3C[2]; //pathA / pathB
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
u8 INIDATA_RATE[32];
};
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
//============================================================
// function prototype
//============================================================
void rtl8192d_init_dm_priv(PADAPTER Adapter);
void rtl8192d_deinit_dm_priv(PADAPTER Adapter);
void rtl8192d_InitHalDm(PADAPTER Adapter);
void rtl8192d_HalDmWatchDog(PADAPTER Adapter);
VOID rtl8192d_dm_CheckTXPowerTracking(PADAPTER Adapter);
VOID DM_Write_DIG(PADAPTER pAdapter);
#endif //__HAL8190PCIDM_H__

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package/jsda/rtl8192du/include/rtl8192d_hal.h
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@ -1,872 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_HAL_H__
#define __RTL8192D_HAL_H__
#include "hal_com.h"
#include "rtl8192d_spec.h"
#include "Hal8192DPhyReg.h"
#include "Hal8192DPhyCfg.h"
#include "rtl8192d_rf.h"
#include "rtl8192d_dm.h"
#include "rtl8192d_recv.h"
#include "rtl8192d_xmit.h"
#include "rtl8192d_cmd.h"
#include "rtw_efuse.h"
/*---------------------------Define Local Constant---------------------------*/
/* Channel switch:The size of command tables for switch channel*/
#define MAX_PRECMD_CNT 16
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
#define MAX_DOZE_WAITING_TIMES_9x 64
#define MAX_RF_IMR_INDEX 12
#define MAX_RF_IMR_INDEX_NORMAL 13
#define RF_REG_NUM_for_C_CUT_5G 6
#define RF_REG_NUM_for_C_CUT_5G_internalPA 7
#define RF_REG_NUM_for_C_CUT_2G 5
#define RF_CHNL_NUM_5G 19
#define RF_CHNL_NUM_5G_40M 17
#define TARGET_CHNL_NUM_5G 221
#define TARGET_CHNL_NUM_2G 14
#define TARGET_CHNL_NUM_2G_5G 59
#define CV_CURVE_CNT 64
//static u32 RF_REG_FOR_5G_SWCHNL[MAX_RF_IMR_INDEX]={0,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x38,0x39,0x0};
static u32 RF_REG_FOR_5G_SWCHNL_NORMAL[MAX_RF_IMR_INDEX_NORMAL]={0,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x0};
static u8 RF_REG_for_C_CUT_5G[RF_REG_NUM_for_C_CUT_5G] =
{RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6};
static u8 RF_REG_for_C_CUT_5G_internalPA[RF_REG_NUM_for_C_CUT_5G_internalPA] =
{0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E};
static u8 RF_REG_for_C_CUT_2G[RF_REG_NUM_for_C_CUT_2G] =
{RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8};
#if DBG
static u32 RF_REG_MASK_for_C_CUT_2G[RF_REG_NUM_for_C_CUT_2G] =
{BIT19|BIT18|BIT17|BIT14|BIT1, BIT10|BIT9,
BIT18|BIT17|BIT16|BIT1, BIT2|BIT1,
BIT15|BIT14|BIT13|BIT12|BIT11};
#endif //amy, temp remove
static u8 RF_CHNL_5G[RF_CHNL_NUM_5G] =
{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140};
static u8 RF_CHNL_5G_40M[RF_CHNL_NUM_5G_40M] =
{38,42,46,50,54,58,62,102,106,110,114,118,122,126,130,134,138};
static u32 RF_REG_Param_for_C_CUT_5G[5][RF_REG_NUM_for_C_CUT_5G] = {
{0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
{0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
{0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
{0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
{0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}};
static u32 RF_REG_Param_for_C_CUT_2G[3][RF_REG_NUM_for_C_CUT_2G] = {
{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
{0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
{0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};
#if SWLCK == 1
static u32 RF_REG_SYN_G4_for_C_CUT_2G = 0xD1C31&0x7FF;
#endif
static u32 RF_REG_Param_for_C_CUT_5G_internalPA[3][RF_REG_NUM_for_C_CUT_5G_internalPA] = {
{0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}};
//[mode][patha+b][reg]
static u32 RF_IMR_Param_Normal[1][3][MAX_RF_IMR_INDEX_NORMAL]={{
{0x70000,0x00ff0,0x4400f,0x00ff0,0x0,0x0,0x0,0x0,0x0,0x64888,0xe266c,0x00090,0x22fff},// channel 1-14.
{0x70000,0x22880,0x4470f,0x55880,0x00070, 0x88000, 0x0,0x88080,0x70000,0x64a82,0xe466c,0x00090,0x32c9a}, //path 36-64
{0x70000,0x44880,0x4477f,0x77880,0x00070, 0x88000, 0x0,0x880b0,0x0,0x64b82,0xe466c,0x00090,0x32c9a} //100 -165
}
};
//static u32 CurveIndex_5G[TARGET_CHNL_NUM_5G]={0};
//static u32 CurveIndex_2G[TARGET_CHNL_NUM_2G]={0};
static u32 CurveIndex[TARGET_CHNL_NUM_2G_5G]={0};
static u32 TargetChnl_5G[TARGET_CHNL_NUM_5G] = {
25141, 25116, 25091, 25066, 25041,
25016, 24991, 24966, 24941, 24917,
24892, 24867, 24843, 24818, 24794,
24770, 24765, 24721, 24697, 24672,
24648, 24624, 24600, 24576, 24552,
24528, 24504, 24480, 24457, 24433,
24409, 24385, 24362, 24338, 24315,
24291, 24268, 24245, 24221, 24198,
24175, 24151, 24128, 24105, 24082,
24059, 24036, 24013, 23990, 23967,
23945, 23922, 23899, 23876, 23854,
23831, 23809, 23786, 23764, 23741,
23719, 23697, 23674, 23652, 23630,
23608, 23586, 23564, 23541, 23519,
23498, 23476, 23454, 23432, 23410,
23388, 23367, 23345, 23323, 23302,
23280, 23259, 23237, 23216, 23194,
23173, 23152, 23130, 23109, 23088,
23067, 23046, 23025, 23003, 22982,
22962, 22941, 22920, 22899, 22878,
22857, 22837, 22816, 22795, 22775,
22754, 22733, 22713, 22692, 22672,
22652, 22631, 22611, 22591, 22570,
22550, 22530, 22510, 22490, 22469,
22449, 22429, 22409, 22390, 22370,
22350, 22336, 22310, 22290, 22271,
22251, 22231, 22212, 22192, 22173,
22153, 22134, 22114, 22095, 22075,
22056, 22037, 22017, 21998, 21979,
21960, 21941, 21921, 21902, 21883,
21864, 21845, 21826, 21807, 21789,
21770, 21751, 21732, 21713, 21695,
21676, 21657, 21639, 21620, 21602,
21583, 21565, 21546, 21528, 21509,
21491, 21473, 21454, 21436, 21418,
21400, 21381, 21363, 21345, 21327,
21309, 21291, 21273, 21255, 21237,
21219, 21201, 21183, 21166, 21148,
21130, 21112, 21095, 21077, 21059,
21042, 21024, 21007, 20989, 20972,
25679, 25653, 25627, 25601, 25575,
25549, 25523, 25497, 25471, 25446,
25420, 25394, 25369, 25343, 25318,
25292, 25267, 25242, 25216, 25191,
25166 };
static u32 TargetChnl_2G[TARGET_CHNL_NUM_2G] = { // channel 1~14
26084, 26030, 25976, 25923, 25869, 25816, 25764,
25711, 25658, 25606, 25554, 25502, 25451, 25328
};
#include "Hal8192DUHWImg.h"
#ifdef CONFIG_WOWLAN
#include "Hal8192DUHWImg_wowlan.h"
#endif //CONFIG_WOWLAN
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
//---------------------------------------------------------------------
// RTL8192DU From file
//---------------------------------------------------------------------
#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
//---------------------------------------------------------------------
// RTL8192DU From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
#ifdef CONFIG_WOWLAN
#define Rtl8192D_FwWWImageArray Rtl8192DUFwWWImgArray
#endif //CONFIG_WOWLAN
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
#define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
#define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
#define DRVINFO_SZ 4 // unit is 8bytes
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
//
// Check if FW header exists. We do not consider the lower 4 bits in this case.
// By tynli. 2009.12.04.
//
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length).
#define FW_8192D_START_ADDRESS 0x1000
#define FW_8192D_END_ADDRESS 0x1FFF
#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
typedef enum _FIRMWARE_SOURCE{
FW_SOURCE_IMG_FILE = 0,
FW_SOURCE_HEADER_FILE = 1, //from header file
}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
typedef struct _RT_FIRMWARE{
FIRMWARE_SOURCE eFWSource;
u8* szFwBuffer;
u32 ulFwLength;
#ifdef CONFIG_WOWLAN
u8* szWoWLANFwBuffer;
u32 ulWoWLANFwLength;
#endif //CONFIG_WOWLAN
}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92D, *PRT_FIRMWARE_92D;
//
// This structure must be cared byte-ordering
//
// Added by tynli. 2009.12.04.
typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
u8 Category; // AP/NIC and USB/PCI
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
u16 Version; // FW Version
u8 Subversion; // FW Subversion, default 0x00
u8 Rsvd1;
//--- LONG WORD 1 ----
u8 Month; // Release time Month field
u8 Date; // Release time Date field
u8 Hour; // Release time Hour field
u8 Minute; // Release time Minute field
u16 RamCodeSize; // The size of RAM code
u16 Rsvd2;
//--- LONG WORD 2 ----
u32 SvnIdx; // The SVN entry index
u32 Rsvd3;
//--- LONG WORD 3 ----
u32 Rsvd4;
u32 Rsvd5;
}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME 0x05
#define BCN_DMA_ATIME_INT_TIME 0x02
typedef enum _BT_CoType{
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR = 3,
BT_CSR_ENHAN = 4,
BT_RTL8756 = 5,
} BT_CoType, *PBT_CoType;
typedef enum _BT_CurState{
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
BT_Scan = 4,
BT_Idle = 5,
BT_OtherAction = 6,
BT_Busy = 7,
BT_OtherBusy = 8,
} BT_ServiceType, *PBT_ServiceType;
typedef enum _BT_RadioShared{
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
} BT_RadioShared, *PBT_RadioShared;
typedef struct _BT_COEXIST_STR{
u8 BluetoothCoexist;
u8 BT_Ant_Num;
u8 BT_CoexistType;
u8 BT_State;
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_RadioSharedType;
u8 Ratio_Tx;
u8 Ratio_PRI;
}BT_COEXIST_STR, *PBT_COEXIST_STR;
//Added for 92D IQK setting.
typedef struct _IQK_MATRIX_REGS_SETTING{
BOOLEAN bIQKDone;
#if 1
int Value[1][IQK_Matrix_REG_NUM];
#else
u32 Mark[IQK_Matrix_REG_NUM];
u32 Value[IQK_Matrix_REG_NUM];
#endif
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
#ifdef CONFIG_USB_RX_AGGREGATION
typedef enum _USB_RX_AGG_MODE{
USB_RX_AGG_DISABLE,
USB_RX_AGG_DMA,
USB_RX_AGG_USB,
USB_RX_AGG_DMA_USB
}USB_RX_AGG_MODE;
#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
#endif
#define TX_SELE_HQ BIT(0) // High Queue
#define TX_SELE_LQ BIT(1) // Low Queue
#define TX_SELE_NQ BIT(2) // Normal Queue
// Note: We will divide number of page equally for each queue other than public queue!
#define TX_TOTAL_PAGE_NUMBER 0xF8
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
#define NORMAL_PAGE_NUM_PUBQ 0x56
// For Test Chip Setting
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
#define TEST_PAGE_NUM_PUBQ_92DU 0x89
#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
// For Test Chip Setting
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
#define WMM_TEST_PAGE_NUM_HPQ 0x29
#define WMM_TEST_PAGE_NUM_LPQ 0x29
//Note: For Normal Chip Setting ,modify later
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
#define WMM_NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0X32
#define WMM_NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0X18
#define WMM_NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0X18
#define WMM_NORMAL_PAGE_NUM_NPQ_92D_DUAL_MAC 0X18
//-------------------------------------------------------------------------
// Chip specific
//-------------------------------------------------------------------------
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_BONDING_88C_USB_MCARD 0x2
#define CHIP_BONDING_88C_USB_HP 0x1
//
// 2011.01.06. Define new structure of chip version for RTL8723 and so on. Added by tynli.
//
/*
| BIT15:12 | BIT11:8 | BIT 7 | BIT6:4 | BIT3 | BIT2:0 |
|-------------+-----------+-----------+-------+-----------+-------|
| IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Type |
| | | TSMC/UMC | | TEST/NORMAL| |
*/
// [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
// [7] Manufacturer: TSMC=0, UMC=1
// [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
// [3] Chip type: TEST=0, NORMAL=1
// [2:0] IC type: 81xxC=0, 8723=1, 92D=2
#define CHIP_8723 BIT(0)
#define CHIP_92D BIT(1)
#define NORMAL_CHIP BIT(3)
#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
#define RF_TYPE_1T2R BIT(4)
#define RF_TYPE_2T2R BIT(5)
#define CHIP_VENDOR_UMC BIT(7)
#define B_CUT_VERSION BIT(12)
#define C_CUT_VERSION BIT(13)
#define D_CUT_VERSION ((BIT(12)|BIT(13)))
#define E_CUT_VERSION BIT(14)
// MASK
#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
#define CHIP_TYPE_MASK BIT(3)
#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
#define MANUFACTUER_MASK BIT(7)
#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
// Get element
#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? _TRUE : _FALSE)
#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723)? _TRUE : _FALSE)
#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? _TRUE : _FALSE)
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? _FALSE : _TRUE)
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? _TRUE : _FALSE)
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? _TRUE : _FALSE)
#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version))? _TRUE: _FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? _TRUE : _FALSE)
#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
// <tynli_Note> 88/92C UMC B-cut vendor is set to TSMC so we need to check CHIP_VENDOR_UMC bit is not 1.
#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? _TRUE : _FALSE):_FALSE)
#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? _TRUE: _FALSE) : _FALSE)
#define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE)
#define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE)
#define IS_92D_E_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE)
#define IS_NORMAL_CHIP92D(version) ((GET_CVID_CHIP_TYPE(version))? _TRUE: _FALSE)
typedef enum _VERSION_8192D{
VERSION_TEST_CHIP_88C = 0x0000,
VERSION_TEST_CHIP_92C = 0x0020,
VERSION_TEST_UMC_CHIP_8723 = 0x0081,
VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
VERSION_TEST_CHIP_92D_SINGLEPHY= 0x0022,
VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
VERSION_NORMAL_CHIP_92D_SINGLEPHY= 0x002a,
VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a,
VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a,
}VERSION_8192D,*PVERSION_8192D;
//-------------------------------------------------------------------------
// Channel Plan
//-------------------------------------------------------------------------
enum ChannelPlan{
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPAIN = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,
CHPL_ISRAEL = 7,
CHPL_TELEC = 8,
CHPL_GLOBAL = 9,
CHPL_WORLD = 10,
};
typedef struct _TxPowerInfo{
u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
u8 TSSI_A[3];
u8 TSSI_B[3];
u8 TSSI_A_5G[3]; //5GL/5GM/5GH
u8 TSSI_B_5G[3];
}TxPowerInfo, *PTxPowerInfo;
#define EFUSE_REAL_CONTENT_LEN 1024
#define EFUSE_MAP_LEN 256
#define EFUSE_MAX_SECTION 32
#define EFUSE_MAX_SECTION_BASE 16
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 2byte|----8bytes----|1byte|--7bytes--| //92D
#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
typedef enum _PA_MODE {
PA_MODE_EXTERNAL = 0x00,
PA_MODE_INTERNAL_SP3T = 0x01,
PA_MODE_INTERNAL_SPDT = 0x02
} PA_MODE;
/* Copy from rtl8192c */
enum c2h_id_8192d {
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3,
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_EXT_RA_RPT = 6,
C2H_HW_INFO_EXCH = 10,
C2H_C2H_H2C_TEST = 11,
C2H_BT_INFO = 12,
C2H_BT_MP_INFO = 15,
MAX_C2HEVENT
};
//should be renamed and moved to another file
typedef enum _INTERFACE_SELECT_8192DUSB{
INTF_SEL0_USB = 0, // USB
INTF_SEL1_MINICARD = 1, // Minicard
INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary
INTF_SEL3_PRO = 3, // Customized proprietary
} INTERFACE_SELECT_8192DUSB, *PINTERFACE_SELECT_8192DUSB;
typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB;
struct hal_data_8192du
{
VERSION_8192D VersionID;
// add for 92D Phy mode/mac/Band mode
MACPHY_MODE_8192D MacPhyMode92D;
BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
BAND_TYPE BandSet92D;
BOOLEAN bIsVS;
BOOLEAN bNOPG;
BOOLEAN bSupportRemoteWakeUp;
BOOLEAN bMasterOfDMSP;
BOOLEAN bSlaveOfDMSP;
#ifdef CONFIG_DUALMAC_CONCURRENT
BOOLEAN bInModeSwitchProcess;
#endif
u16 CustomerID;
u16 FirmwareVersion;
u16 FirmwareVersionRev;
u16 FirmwareSubVersion;
//current WIFI_PHY values
u32 ReceiveConfig;
WIRELESS_MODE CurrentWirelessMode;
HT_CHANNEL_WIDTH CurrentChannelBW;
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
u16 BasicRateSet;
u8 BoardType;
//rf_ctrl
u8 rf_chip;
u8 rf_type;
u8 NumTotalRFPath;
//
// EEPROM setting.
//
u8 EEPROMVersion;
u16 EEPROMVID;
u16 EEPROMPID;
u16 EEPROMSVID;
u16 EEPROMSDID;
u8 EEPROMCustomerID;
u8 EEPROMSubCustomerID;
u8 EEPROMRegulatory;
u8 EEPROMThermalMeter;
u8 EEPROMC9;
u8 EEPROMCC;
u8 PAMode;
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
u8 CrystalCap; // CrystalCap.
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
// Read/write are allow for following hardware information variables
u8 framesync;
u32 framesyncC34;
u8 framesyncMonitor;
u8 DefaultInitialGain[4];
u8 pwrGroupCnt;
u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
u32 CCKTxPowerLevelOriginalOffset;
u32 AntennaTxPath; // Antenna path Tx
u32 AntennaRxPath; // Antenna path Rx
u8 BluetoothCoexist;
u8 ExternalPA;
u8 InternalPA5G[2]; //pathA / pathB
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
//u32 LedControlNum;
//u32 LedControlMode;
//u32 TxPowerTrackControl;
u8 b1x1RecvCombine; // for 1T1R receive combining
u8 bCurrentTurboEDCA;
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
//vivi, for tx power tracking, 20080407
//u16 TSSI_13dBm;
//u32 Pwr_Track;
// The current Tx Power Level
u8 CurrentCckTxPwrIdx;
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
u32 RfRegChnlVal[2];
u8 bCckHighPower;
BOOLEAN bPhyValueInitReady;
BOOLEAN bTXPowerDataReadFromEEPORM;
BOOLEAN bInSetPower;
//RDG enable
BOOLEAN bRDGEnable;
BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress
BOOLEAN bNeedIQK;
BOOLEAN bLCKInProgress;
BOOLEAN bEarlyModeEnable;
#if 1
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
#else
//regc80¡¢regc94¡¢regc4c¡¢regc88¡¢regc9c¡¢regc14¡¢regca0¡¢regc1c¡¢regc78
u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
#endif
//for host message to fw
u8 LastHMEBoxNum;
u8 fw_ractrl;
// Beacon function related global variable.
u32 RegBcnCtrlVal;
u8 RegTxPause;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 RegCR_1;
struct dm_priv dmpriv;
u8 bDumpRxPkt;//for debug
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
//Query RF by FW
BOOLEAN bReadRFbyFW;
// For 92C USB endpoint setting
//
u32 UsbBulkOutSize;
int RtBulkOutPipe[3];
int RtBulkInPipe;
int RtIntInPipe;
// Add for dual MAC 0--Mac0 1--Mac1
u32 interfaceIndex;
u8 OutEpQueueSel;
u8 OutEpNumber;
u8 Queue2EPNum[8];//for out endpoint number mapping
#ifdef CONFIG_USB_TX_AGGREGATION
u8 UsbTxAggMode;
u8 UsbTxAggDescNum;
#endif
#ifdef CONFIG_USB_RX_AGGREGATION
u16 HwRxPageSize; // Hardware setting
u32 MaxUsbRxAggBlock;
USB_RX_AGG_MODE UsbRxAggMode;
u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
u8 UsbRxAggBlockTimeout;
u8 UsbRxAggPageCount; // 8192C DMA page count
u8 UsbRxAggPageTimeout;
#endif
u16 RegRRSR;
u16 EfuseUsedBytes;
u8 RTSInitRate; // 2010.11.24.by tynli.
EFUSE_HAL EfuseHal;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
#endif //CONFIG_P2P
};
typedef struct hal_data_8192du HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
int FirmwareDownload92D(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
VOID rtl8192d_FirmwareSelfReset(PADAPTER Adapter);
void rtl8192d_ReadChipVersion(PADAPTER Adapter);
VOID rtl8192d_EfuseParseChnlPlan(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail);
VOID rtl8192d_ResetDualMacSwitchVariables(PADAPTER Adapter);
u8 GetEEPROMSize8192D(PADAPTER Adapter);
BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter);
VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter);
//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
void rtl8192d_free_hal_data(_adapter * padapter);
void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
void SetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);
void GetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);
u8 SetHalDefVar8192D(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val);
u8 GetHalDefVar8192D(_adapter *adapter, HAL_DEF_VARIABLE variable, void *val);
#endif
#ifdef CONFIG_MP_INCLUDED
extern void Hal_SetAntenna(PADAPTER pAdapter);
extern void Hal_SetBandwidth(PADAPTER pAdapter);
extern void Hal_SetTxPower(PADAPTER pAdapter);
extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart );
extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart);
extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart);
extern void Hal_SetBandwidth(PADAPTER pAdapter);
extern void Hal_SetDataRate(PADAPTER pAdapter);
extern void Hal_SetChannel(PADAPTER pAdapter);
extern void Hal_SetAntennaPathPower(PADAPTER pAdapter);
extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable);
extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable);
extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value);
extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven);
extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower);
extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower);
extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter);
extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter);
extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart);
extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart);
#endif //end CONFIG_MP_INCLUDED

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