From e1e44b79e0ded374c864d1b7c72c06b2ae1066a5 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 18 Dec 2023 16:05:35 +0800 Subject: [PATCH] sunxi: backport pending thermal support for H616 Signed-off-by: Tianling Shen --- ...lwinner-h616-Add-SID-controller-node.patch | 31 ++++ ...am-export-register-0-for-THS-on-H616.patch | 107 ++++++++++++ ...8i-explain-unknown-H6-register-value.patch | 93 +++++++++++ ...-H6-calibration-to-support-4-sensors.patch | 88 ++++++++++ ...-sun8i-add-SRAM-register-access-code.patch | 134 +++++++++++++++ ...-add-support-for-H616-THS-controller.patch | 67 ++++++++ ...er-h616-Add-thermal-sensor-and-zones.patch | 155 ++++++++++++++++++ 7 files changed, 675 insertions(+) create mode 100644 target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch create mode 100644 target/linux/sunxi/patches-6.1/110-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch create mode 100644 target/linux/sunxi/patches-6.1/111-thermal-sun8i-explain-unknown-H6-register-value.patch create mode 100644 target/linux/sunxi/patches-6.1/112-thermal-sun8i-extend-H6-calibration-to-support-4-sensors.patch create mode 100644 target/linux/sunxi/patches-6.1/113-thermal-sun8i-add-SRAM-register-access-code.patch create mode 100644 target/linux/sunxi/patches-6.1/114-thermal-sun8i-add-support-for-H616-THS-controller.patch create mode 100644 target/linux/sunxi/patches-6.1/115-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch diff --git a/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch b/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch new file mode 100644 index 0000000000..ce8add18ab --- /dev/null +++ b/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch @@ -0,0 +1,31 @@ +From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001 +From: Martin Botka +Date: Tue, 12 Sep 2023 14:25:13 +0200 +Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node + +Add node for the H616 SID controller + +Signed-off-by: Martin Botka +Acked-by: Jernej Skrabec +Link: https://lore.kernel.org/r/20230912-sid-h616-v3-2-ee18e1c5bbb5@somainline.org +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -133,6 +133,13 @@ + #reset-cells = <1>; + }; + ++ sid: efuse@3006000 { ++ compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; ++ reg = <0x03006000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ + watchdog: watchdog@30090a0 { + compatible = "allwinner,sun50i-h616-wdt", + "allwinner,sun6i-a31-wdt"; diff --git a/target/linux/sunxi/patches-6.1/110-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch b/target/linux/sunxi/patches-6.1/110-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch new file mode 100644 index 0000000000..5f5ef246f2 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/110-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch @@ -0,0 +1,107 @@ +From: Andre Przywara +To: Vasily Khoruzhick , + Yangtao Li , Chen-Yu Tsai , + Jernej Skrabec , + Samuel Holland +Cc: "Rafael J . Wysocki" , + Daniel Lezcano , + Zhang Rui , + Lukasz Luba , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Martin Botka , + Maksim Kiselev , + Bob McChesney , + linux-pm@vger.kernel.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-sunxi@lists.linux.dev +Subject: [PATCH v4 1/7] soc: sunxi: sram: export register 0 for THS on H616 +Date: Fri, 9 Feb 2024 14:42:15 +0000 [thread overview] +Message-ID: <20240209144221.3602382-2-andre.przywara@arm.com> (raw) +In-Reply-To: <20240209144221.3602382-1-andre.przywara@arm.com> + +The Allwinner H616 SoC contains a mysterious bit at register offset 0x0 +in the SRAM control block. If bit 16 is set (the reset value), the +temperature readings of the THS are way off, leading to reports about +200C, at normal ambient temperatures. Clearing this bits brings the +reported values down to reasonable ranges. +The BSP code clears this bit in firmware (U-Boot), and has an explicit +comment about this, but offers no real explanation. + +Since we should not rely on firmware settings, allow other code (the THS +driver) to access this register, by exporting it through the already +existing regmap. This mimics what we already do for the LDO control and +the EMAC register. + +Since this bit is in the very same register as the actual SRAM switch, +we need to change the regmap lock to the SRAM lock. Fortunately regmap +has provisions for that, so we just need to hook in there. + +Signed-off-by: Andre Przywara +--- + drivers/soc/sunxi/sunxi_sram.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -284,6 +284,7 @@ EXPORT_SYMBOL(sunxi_sram_release); + struct sunxi_sramc_variant { + int num_emac_clocks; + bool has_ldo_ctrl; ++ bool has_ths_offset; + }; + + static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { +@@ -305,8 +306,10 @@ static const struct sunxi_sramc_variant + + static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = { + .num_emac_clocks = 2, ++ .has_ths_offset = true, + }; + ++#define SUNXI_SRAM_THS_OFFSET_REG 0x0 + #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 + #define SUNXI_SYS_LDO_CTRL_REG 0x150 + +@@ -315,6 +318,8 @@ static bool sunxi_sram_regmap_accessible + { + const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev); + ++ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset) ++ return true; + if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG && + reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4) + return true; +@@ -324,6 +329,21 @@ static bool sunxi_sram_regmap_accessible + return false; + } + ++ ++static void sunxi_sram_lock(void *_lock) ++{ ++ spinlock_t *lock = _lock; ++ ++ spin_lock(lock); ++} ++ ++static void sunxi_sram_unlock(void *_lock) ++{ ++ spinlock_t *lock = _lock; ++ ++ spin_unlock(lock); ++} ++ + static struct regmap_config sunxi_sram_regmap_config = { + .reg_bits = 32, + .val_bits = 32, +@@ -333,6 +353,9 @@ static struct regmap_config sunxi_sram_r + /* other devices have no business accessing other registers */ + .readable_reg = sunxi_sram_regmap_accessible_reg, + .writeable_reg = sunxi_sram_regmap_accessible_reg, ++ .lock = sunxi_sram_lock, ++ .unlock = sunxi_sram_unlock, ++ .lock_arg = &sram_lock, + }; + + static int __init sunxi_sram_probe(struct platform_device *pdev) diff --git a/target/linux/sunxi/patches-6.1/111-thermal-sun8i-explain-unknown-H6-register-value.patch b/target/linux/sunxi/patches-6.1/111-thermal-sun8i-explain-unknown-H6-register-value.patch new file mode 100644 index 0000000000..4079e8ca08 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/111-thermal-sun8i-explain-unknown-H6-register-value.patch @@ -0,0 +1,93 @@ +From: Andre Przywara +To: Vasily Khoruzhick , + Yangtao Li , Chen-Yu Tsai , + Jernej Skrabec , + Samuel Holland +Cc: "Rafael J . Wysocki" , + Daniel Lezcano , + Zhang Rui , + Lukasz Luba , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Martin Botka , + Maksim Kiselev , + Bob McChesney , + linux-pm@vger.kernel.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-sunxi@lists.linux.dev +Subject: [PATCH v4 3/7] thermal: sun8i: explain unknown H6 register value +Date: Fri, 9 Feb 2024 14:42:17 +0000 [thread overview] +Message-ID: <20240209144221.3602382-4-andre.przywara@arm.com> (raw) +In-Reply-To: <20240209144221.3602382-1-andre.przywara@arm.com> + +So far we were ORing in some "unknown" value into the THS control +register on the Allwinner H6. This part of the register is not explained +in the H6 manual, but the H616 manual details those bits, and on closer +inspection the THS IP blocks in both SoCs seem very close: +- The BSP code for both SoCs writes the same values into THS_CTRL. +- The reset values of at least the first three registers are the same. + +Replace the "unknown" value with its proper meaning: "acquire time", +most probably the sample part of the sample & hold circuit of the ADC, +according to its explanation in the H616 manual. + +No functional change, just a macro rename and adjustment. + +Signed-off-by: Andre Przywara +--- + drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++------------- + 1 file changed, 16 insertions(+), 13 deletions(-) + +--- a/drivers/thermal/sun8i_thermal.c ++++ b/drivers/thermal/sun8i_thermal.c +@@ -50,7 +50,8 @@ + #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16) + #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8) + +-#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16) ++#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1)) ++#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16) + #define SUN50I_THS_FILTER_EN BIT(2) + #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) + #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) +@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct + return 0; + } + +-/* +- * Without this undocumented value, the returned temperatures would +- * be higher than real ones by about 20C. +- */ +-#define SUN50I_H6_CTRL0_UNK 0x0000002f +- + static int sun50i_h6_thermal_init(struct ths_device *tmdev) + { + int val; + + /* +- * T_acq = 20us +- * clkin = 24MHz +- * +- * x = T_acq * clkin - 1 +- * = 479 ++ * The manual recommends an overall sample frequency of 50 KHz (20us, ++ * 480 cycles at 24 MHz), which provides plenty of time for both the ++ * acquisition time (>24 cycles) and the actual conversion time ++ * (>14 cycles). ++ * The lower half of the CTRL register holds the "acquire time", in ++ * clock cycles, which the manual recommends to be 2us: ++ * 24MHz * 2us = 48 cycles. ++ * The high half of THS_CTRL encodes the sample frequency, in clock ++ * cycles: 24MHz * 20us = 480 cycles. ++ * This is explained in the H616 manual, but apparently wrongly ++ * described in the H6 manual, although the BSP code does the same ++ * for both SoCs. + */ + regmap_write(tmdev->regmap, SUN50I_THS_CTRL0, +- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479)); ++ SUN50I_THS_CTRL0_T_ACQ(48) | ++ SUN50I_THS_CTRL0_T_SAMPLE_PER(480)); + /* average over 4 samples */ + regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC, + SUN50I_THS_FILTER_EN | diff --git a/target/linux/sunxi/patches-6.1/112-thermal-sun8i-extend-H6-calibration-to-support-4-sensors.patch b/target/linux/sunxi/patches-6.1/112-thermal-sun8i-extend-H6-calibration-to-support-4-sensors.patch new file mode 100644 index 0000000000..0a48053711 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/112-thermal-sun8i-extend-H6-calibration-to-support-4-sensors.patch @@ -0,0 +1,88 @@ +From: Andre Przywara +To: Vasily Khoruzhick , + Yangtao Li , Chen-Yu Tsai , + Jernej Skrabec , + Samuel Holland +Cc: "Rafael J . Wysocki" , + Daniel Lezcano , + Zhang Rui , + Lukasz Luba , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Martin Botka , + Maksim Kiselev , + Bob McChesney , + linux-pm@vger.kernel.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-sunxi@lists.linux.dev +Subject: [PATCH v4 4/7] thermal: sun8i: extend H6 calibration to support 4 sensors +Date: Fri, 9 Feb 2024 14:42:18 +0000 [thread overview] +Message-ID: <20240209144221.3602382-5-andre.przywara@arm.com> (raw) +In-Reply-To: <20240209144221.3602382-1-andre.przywara@arm.com> + +From: Maksim Kiselev + +The H616 SoC resembles the H6 thermal sensor controller, with a few +changes like four sensors. + +Extend sun50i_h6_ths_calibrate() function to support calibration of +these sensors. + +Signed-off-by: Maksim Kiselev +Co-developed-by: Martin Botka +Reviewed-by: Andre Przywara +Signed-off-by: Andre Przywara +--- + drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++-------- + 1 file changed, 20 insertions(+), 8 deletions(-) + +--- a/drivers/thermal/sun8i_thermal.c ++++ b/drivers/thermal/sun8i_thermal.c +@@ -224,16 +224,21 @@ static int sun50i_h6_ths_calibrate(struc + struct device *dev = tmdev->dev; + int i, ft_temp; + +- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) ++ if (!caldata[0]) + return -EINVAL; + + /* + * efuse layout: + * +- * 0 11 16 32 +- * +-------+-------+-------+ +- * |temp| |sensor0|sensor1| +- * +-------+-------+-------+ ++ * 0 11 16 27 32 43 48 57 ++ * +----------+-----------+-----------+-----------+ ++ * | temp | |sensor0| |sensor1| |sensor2| | ++ * +----------+-----------+-----------+-----------+ ++ * ^ ^ ^ ++ * | | | ++ * | | sensor3[11:8] ++ * | sensor3[7:4] ++ * sensor3[3:0] + * + * The calibration data on the H6 is the ambient temperature and + * sensor values that are filled during the factory test stage. +@@ -246,9 +251,16 @@ static int sun50i_h6_ths_calibrate(struc + ft_temp = (caldata[0] & FT_TEMP_MASK) * 100; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { +- int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK; +- int cdata, offset; +- int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); ++ int sensor_reg, sensor_temp, cdata, offset; ++ ++ if (i == 3) ++ sensor_reg = (caldata[1] >> 12) ++ | ((caldata[2] >> 12) << 4) ++ | ((caldata[3] >> 12) << 8); ++ else ++ sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK; ++ ++ sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); + + /* + * Calibration data is CALIBRATE_DEFAULT - (calculated diff --git a/target/linux/sunxi/patches-6.1/113-thermal-sun8i-add-SRAM-register-access-code.patch b/target/linux/sunxi/patches-6.1/113-thermal-sun8i-add-SRAM-register-access-code.patch new file mode 100644 index 0000000000..d392d4efaa --- /dev/null +++ b/target/linux/sunxi/patches-6.1/113-thermal-sun8i-add-SRAM-register-access-code.patch @@ -0,0 +1,134 @@ +From: Andre Przywara +To: Vasily Khoruzhick , + Yangtao Li , Chen-Yu Tsai , + Jernej Skrabec , + Samuel Holland +Cc: "Rafael J . Wysocki" , + Daniel Lezcano , + Zhang Rui , + Lukasz Luba , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Martin Botka , + Maksim Kiselev , + Bob McChesney , + linux-pm@vger.kernel.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-sunxi@lists.linux.dev +Subject: [PATCH v4 5/7] thermal: sun8i: add SRAM register access code +Date: Fri, 9 Feb 2024 14:42:19 +0000 [thread overview] +Message-ID: <20240209144221.3602382-6-andre.przywara@arm.com> (raw) +In-Reply-To: <20240209144221.3602382-1-andre.przywara@arm.com> + +The Allwinner H616 SoC needs to clear a bit in one register in the SRAM +controller, to report reasonable temperature values. On reset, bit 16 in +register 0x3000000 is set, which leads to the driver reporting +temperatures around 200C. Clearing this bit brings the values down to the +expected range. The BSP code does a one-time write in U-Boot, with a +comment just mentioning the effect on the THS, but offering no further +explanation. + +To not rely on firmware to set things up for us, add code that queries +the SRAM controller device via a DT phandle link, then clear just this +single bit. + +Signed-off-by: Andre Przywara +--- + drivers/thermal/sun8i_thermal.c | 50 +++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/drivers/thermal/sun8i_thermal.c ++++ b/drivers/thermal/sun8i_thermal.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -68,6 +69,7 @@ struct tsensor { + struct ths_thermal_chip { + bool has_mod_clk; + bool has_bus_clk_reset; ++ bool needs_sram; + int sensor_num; + int offset; + int scale; +@@ -85,6 +87,7 @@ struct ths_device { + const struct ths_thermal_chip *chip; + struct device *dev; + struct regmap *regmap; ++ struct regmap_field *sram_regmap_field; + struct reset_control *reset; + struct clk *bus_clk; + struct clk *mod_clk; +@@ -337,6 +340,34 @@ static void sun8i_ths_reset_control_asse + reset_control_assert(data); + } + ++static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node) ++{ ++ struct device_node *sram_node; ++ struct platform_device *sram_pdev; ++ struct regmap *regmap = NULL; ++ ++ sram_node = of_parse_phandle(node, "allwinner,sram", 0); ++ if (!sram_node) ++ return ERR_PTR(-ENODEV); ++ ++ sram_pdev = of_find_device_by_node(sram_node); ++ if (!sram_pdev) { ++ /* platform device might not be probed yet */ ++ regmap = ERR_PTR(-EPROBE_DEFER); ++ goto out_put_node; ++ } ++ ++ /* If no regmap is found then the other device driver is at fault */ ++ regmap = dev_get_regmap(&sram_pdev->dev, NULL); ++ if (!regmap) ++ regmap = ERR_PTR(-EINVAL); ++ ++ platform_device_put(sram_pdev); ++out_put_node: ++ of_node_put(sram_node); ++ return regmap; ++} ++ + static int sun8i_ths_resource_init(struct ths_device *tmdev) + { + struct device *dev = tmdev->dev; +@@ -381,6 +412,21 @@ static int sun8i_ths_resource_init(struc + if (ret) + return ret; + ++ if (tmdev->chip->needs_sram) { ++ const struct reg_field sun8i_sram_reg_field = ++ REG_FIELD(0x0, 16, 16); ++ struct regmap *regmap; ++ ++ regmap = sun8i_ths_get_sram_regmap(dev->of_node); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ tmdev->sram_regmap_field = devm_regmap_field_alloc(dev, ++ regmap, ++ sun8i_sram_reg_field); ++ if (IS_ERR(tmdev->sram_regmap_field)) ++ return PTR_ERR(tmdev->sram_regmap_field); ++ } ++ + ret = sun8i_ths_calibrate(tmdev); + if (ret) + return ret; +@@ -427,6 +473,10 @@ static int sun50i_h6_thermal_init(struct + { + int val; + ++ /* The H616 needs to have a bit in the SRAM control register cleared. */ ++ if (tmdev->sram_regmap_field) ++ regmap_field_write(tmdev->sram_regmap_field, 0); ++ + /* + * The manual recommends an overall sample frequency of 50 KHz (20us, + * 480 cycles at 24 MHz), which provides plenty of time for both the diff --git a/target/linux/sunxi/patches-6.1/114-thermal-sun8i-add-support-for-H616-THS-controller.patch b/target/linux/sunxi/patches-6.1/114-thermal-sun8i-add-support-for-H616-THS-controller.patch new file mode 100644 index 0000000000..2b508eb1f2 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/114-thermal-sun8i-add-support-for-H616-THS-controller.patch @@ -0,0 +1,67 @@ +From: Andre Przywara +To: Vasily Khoruzhick , + Yangtao Li , Chen-Yu Tsai , + Jernej Skrabec , + Samuel Holland +Cc: "Rafael J . Wysocki" , + Daniel Lezcano , + Zhang Rui , + Lukasz Luba , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Martin Botka , + Maksim Kiselev , + Bob McChesney , + linux-pm@vger.kernel.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-sunxi@lists.linux.dev +Subject: [PATCH v4 6/7] thermal: sun8i: add support for H616 THS controller +Date: Fri, 9 Feb 2024 14:42:20 +0000 [thread overview] +Message-ID: <20240209144221.3602382-7-andre.przywara@arm.com> (raw) +In-Reply-To: <20240209144221.3602382-1-andre.przywara@arm.com> + +From: Martin Botka + +Add support for the thermal sensor found in H616 SoCs, is the same as +the H6 thermal sensor controller, but with four sensors. +Also the registers readings are wrong, unless a bit in the first SYS_CFG +register cleared, so set exercise the SRAM regmap to take care of that. + +Signed-off-by: Martin Botka +Signed-off-by: Andre Przywara +--- + drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/thermal/sun8i_thermal.c ++++ b/drivers/thermal/sun8i_thermal.c +@@ -675,6 +675,20 @@ static const struct ths_thermal_chip sun + .calc_temp = sun8i_ths_calc_temp, + }; + ++static const struct ths_thermal_chip sun50i_h616_ths = { ++ .sensor_num = 4, ++ .has_bus_clk_reset = true, ++ .needs_sram = true, ++ .ft_deviation = 8000, ++ .offset = 263655, ++ .scale = 810, ++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, ++ .calibrate = sun50i_h6_ths_calibrate, ++ .init = sun50i_h6_thermal_init, ++ .irq_ack = sun50i_h6_irq_ack, ++ .calc_temp = sun8i_ths_calc_temp, ++}; ++ + static const struct of_device_id of_ths_match[] = { + { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, + { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, +@@ -683,6 +697,7 @@ static const struct of_device_id of_ths_ + { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths }, + { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, + { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, ++ { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, of_ths_match); diff --git a/target/linux/sunxi/patches-6.1/115-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch b/target/linux/sunxi/patches-6.1/115-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch new file mode 100644 index 0000000000..60160c65d2 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/115-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch @@ -0,0 +1,155 @@ +From: Andre Przywara +To: Vasily Khoruzhick , + Yangtao Li , Chen-Yu Tsai , + Jernej Skrabec , + Samuel Holland +Cc: "Rafael J . Wysocki" , + Daniel Lezcano , + Zhang Rui , + Lukasz Luba , + Rob Herring , + Krzysztof Kozlowski , + Conor Dooley , + Martin Botka , + Maksim Kiselev , + Bob McChesney , + linux-pm@vger.kernel.org, devicetree@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, + linux-sunxi@lists.linux.dev +Subject: [PATCH v4 7/7] arm64: dts: allwinner: h616: Add thermal sensor and zones +Date: Fri, 9 Feb 2024 14:42:21 +0000 [thread overview] +Message-ID: <20240209144221.3602382-8-andre.przywara@arm.com> (raw) +In-Reply-To: <20240209144221.3602382-1-andre.przywara@arm.com> + +From: Martin Botka + +There are four thermal sensors: +- CPU +- GPU +- VE +- DRAM + +Add the thermal sensor configuration and the thermal zones. + +Signed-off-by: Martin Botka +Signed-off-by: Andre Przywara +--- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++ + 1 file changed, 88 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + + / { + interrupt-parent = <&gic>; +@@ -138,6 +139,10 @@ + reg = <0x03006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ ths_calibration: thermal-sensor-calibration@14 { ++ reg = <0x14 0x8>; ++ }; + }; + + watchdog: watchdog@30090a0 { +@@ -511,6 +516,19 @@ + }; + }; + ++ ths: thermal-sensor@5070400 { ++ compatible = "allwinner,sun50i-h616-ths"; ++ reg = <0x05070400 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_THS>; ++ clock-names = "bus"; ++ resets = <&ccu RST_BUS_THS>; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ allwinner,sram = <&syscon>; ++ #thermal-sensor-cells = <1>; ++ }; ++ + usbotg: usb@5100000 { + compatible = "allwinner,sun50i-h616-musb", + "allwinner,sun8i-h3-musb"; +@@ -755,4 +773,74 @@ + #size-cells = <0>; + }; + }; ++ ++ thermal-zones { ++ cpu-thermal { ++ polling-delay-passive = <500>; ++ polling-delay = <1000>; ++ thermal-sensors = <&ths 2>; ++ sustainable-power = <1000>; ++ ++ trips { ++ cpu_threshold: cpu-trip-0 { ++ temperature = <60000>; ++ type = "passive"; ++ hysteresis = <0>; ++ }; ++ cpu_target: cpu-trip-1 { ++ temperature = <70000>; ++ type = "passive"; ++ hysteresis = <0>; ++ }; ++ cpu_critical: cpu-trip-2 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; ++ }; ++ }; ++ ++ gpu-thermal { ++ polling-delay-passive = <500>; ++ polling-delay = <1000>; ++ thermal-sensors = <&ths 0>; ++ sustainable-power = <1100>; ++ ++ trips { ++ gpu_temp_critical: gpu-trip-0 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; ++ }; ++ }; ++ ++ ve-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 1>; ++ ++ trips { ++ ve_temp_critical: ve-trip-0 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; ++ }; ++ }; ++ ++ ddr-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 3>; ++ ++ trips { ++ ddr_temp_critical: ddr-trip-0 { ++ temperature = <110000>; ++ type = "critical"; ++ hysteresis = <0>; ++ }; ++ }; ++ }; ++ }; + };