diff --git a/target/linux/ipq40xx/patches-4.19/852-ARM-dts-qcom-ipq4019-Add-SDHCI-VQMMC-LDO-regulator-n.patch b/target/linux/ipq40xx/patches-4.19/852-ARM-dts-qcom-ipq4019-Add-SDHCI-VQMMC-LDO-regulator-n.patch new file mode 100644 index 0000000000..fdb3f8bbcc --- /dev/null +++ b/target/linux/ipq40xx/patches-4.19/852-ARM-dts-qcom-ipq4019-Add-SDHCI-VQMMC-LDO-regulator-n.patch @@ -0,0 +1,33 @@ +From beae4078c07d3cdc90473a2b35eb0d2b4f3c922c Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 14 Sep 2019 23:13:17 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI VQMMC LDO regulator node + +IPQ4019 has a built in SD/eMMC controller which depends on +VQMMC LDO regulator working. +Since we have a driver for it lets add the appropriate node for it. + +Signed-off-by: Robert Marko +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -216,6 +216,16 @@ + interrupts = ; + }; + ++ vqmmc: regulator@1948000 { ++ compatible = "qcom,ipq4019-vqmmc-regulator"; ++ reg = <0x01948000 0x4>; ++ regulator-name = "vqmmc"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ status = "disabled"; ++ }; ++ + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; diff --git a/target/linux/ipq40xx/patches-4.19/853-add-sdhci-msm-node-to-dts.patch b/target/linux/ipq40xx/patches-4.19/853-add-sdhci-msm-node-to-dts.patch new file mode 100644 index 0000000000..4450d48501 --- /dev/null +++ b/target/linux/ipq40xx/patches-4.19/853-add-sdhci-msm-node-to-dts.patch @@ -0,0 +1,41 @@ +Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node +Date: Thu, 15 Aug 2019 19:28:23 +0200 +Message-Id: <20190815172823.12028-1-robimarko@gmail.com> +X-Mailer: git-send-email 2.21.0 +MIME-Version: 1.0 +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org +X-Virus-Scanned: ClamAV using ClamSMTP + +IPQ4019 has a built in SD/eMMC controller which is supported by the +SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding. +So lets add the appropriate node for it. + +Signed-off-by: Robert Marko +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -226,6 +226,18 @@ + status = "disabled"; + }; + ++ sdhci: sdhci@7824900 { ++ compatible = "qcom,sdhci-msm-v4"; ++ reg = <0x7824900 0x11c>, <0x7824000 0x800>; ++ interrupts = , ; ++ interrupt-names = "hc_irq", "pwr_irq"; ++ bus-width = <8>; ++ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, ++ <&gcc GCC_DCD_XO_CLK>; ++ clock-names = "core", "iface", "xo"; ++ status = "disabled"; ++ }; ++ + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; diff --git a/target/linux/ipq40xx/patches-5.4/852-ARM-dts-qcom-ipq4019-Add-SDHCI-VQMMC-LDO-regulator.patch b/target/linux/ipq40xx/patches-5.4/852-ARM-dts-qcom-ipq4019-Add-SDHCI-VQMMC-LDO-regulator.patch new file mode 100644 index 0000000000..fdb3f8bbcc --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/852-ARM-dts-qcom-ipq4019-Add-SDHCI-VQMMC-LDO-regulator.patch @@ -0,0 +1,33 @@ +From beae4078c07d3cdc90473a2b35eb0d2b4f3c922c Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 14 Sep 2019 23:13:17 +0200 +Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI VQMMC LDO regulator node + +IPQ4019 has a built in SD/eMMC controller which depends on +VQMMC LDO regulator working. +Since we have a driver for it lets add the appropriate node for it. + +Signed-off-by: Robert Marko +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -216,6 +216,16 @@ + interrupts = ; + }; + ++ vqmmc: regulator@1948000 { ++ compatible = "qcom,ipq4019-vqmmc-regulator"; ++ reg = <0x01948000 0x4>; ++ regulator-name = "vqmmc"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ status = "disabled"; ++ }; ++ + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; diff --git a/target/linux/ipq40xx/patches-5.4/853-add-sdhci-msm-node-to-dts.patch b/target/linux/ipq40xx/patches-5.4/853-add-sdhci-msm-node-to-dts.patch new file mode 100644 index 0000000000..4450d48501 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/853-add-sdhci-msm-node-to-dts.patch @@ -0,0 +1,41 @@ +Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node +Date: Thu, 15 Aug 2019 19:28:23 +0200 +Message-Id: <20190815172823.12028-1-robimarko@gmail.com> +X-Mailer: git-send-email 2.21.0 +MIME-Version: 1.0 +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org +X-Virus-Scanned: ClamAV using ClamSMTP + +IPQ4019 has a built in SD/eMMC controller which is supported by the +SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding. +So lets add the appropriate node for it. + +Signed-off-by: Robert Marko +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -226,6 +226,18 @@ + status = "disabled"; + }; + ++ sdhci: sdhci@7824900 { ++ compatible = "qcom,sdhci-msm-v4"; ++ reg = <0x7824900 0x11c>, <0x7824000 0x800>; ++ interrupts = , ; ++ interrupt-names = "hc_irq", "pwr_irq"; ++ bus-width = <8>; ++ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, ++ <&gcc GCC_DCD_XO_CLK>; ++ clock-names = "core", "iface", "xo"; ++ status = "disabled"; ++ }; ++ + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; diff --git a/target/linux/ipq40xx/patches-5.4/854-add-sdhci-reset-implementation.patch b/target/linux/ipq40xx/patches-5.4/854-add-sdhci-reset-implementation.patch new file mode 100644 index 0000000000..58803df191 --- /dev/null +++ b/target/linux/ipq40xx/patches-5.4/854-add-sdhci-reset-implementation.patch @@ -0,0 +1,56 @@ +From: Georgi Djakov +Date: Mon, 28 Nov 2016 19:39:20 +0200 +Subject: [PATCH v2] mmc: sdhci-msm: Add sdhci_reset() implementation + +Signed-off-by: Georgi Djakov +--- + +drivers/mmc/host/sdhci-msm.c | 29 ++++++++++++++++++++++++++++- +1 file changed, 28 insertions(+), 1 deletion(-) + +diff -urN a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c +--- a/drivers/mmc/host/sdhci-msm.c 2020-01-23 15:20:37.000000000 +0800 ++++ b/drivers/mmc/host/sdhci-msm.c 2020-02-10 13:37:03.577363800 +0800 +@@ -1117,6 +1117,33 @@ + __sdhci_msm_set_clock(host, clock); + } + ++void sdhci_msm_reset(struct sdhci_host *host, u8 mask) ++{ ++ unsigned long timeout = 100; ++ ++ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); ++ ++ if (mask & SDHCI_RESET_ALL) { ++ host->clock = 0; ++ ++ /* ++ * SDHCI_RESET_ALL triggers the PWR IRQ ++ * and we need to handle it here. ++ */ ++ sdhci_msm_voltage_switch(host); ++ } ++ ++ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { ++ if (timeout == 0) { ++ pr_err("%s: Reset 0x%x never completed.\n", ++ mmc_hostname(host->mmc), (int)mask); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++} ++ + static void sdhci_msm_write_w(struct sdhci_host *host, u16 val, int reg) + { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); +@@ -1148,7 +1175,7 @@ + MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); + + static const struct sdhci_ops sdhci_msm_ops = { +- .reset = sdhci_reset, ++ .reset = sdhci_msm_reset, + .set_clock = sdhci_msm_set_clock, + .get_min_clock = sdhci_msm_get_min_clock, + .get_max_clock = sdhci_msm_get_max_clock,