diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c index 16af922b48..031efe6181 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.c +++ b/target/linux/generic/files/drivers/net/phy/ar8216.c @@ -23,12 +23,14 @@ #include #include #include +#include +#include +#include #include #include #include #include #include -#include #include #include #include @@ -40,100 +42,112 @@ extern const struct ar8xxx_chip ar8327_chip; extern const struct ar8xxx_chip ar8337_chip; -#define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */ +#define MIB_DESC_BASIC(_s , _o, _n) \ + { \ + .size = (_s), \ + .offset = (_o), \ + .name = (_n), \ + .type = AR8XXX_MIB_BASIC, \ + } -#define MIB_DESC(_s , _o, _n) \ - { \ - .size = (_s), \ - .offset = (_o), \ - .name = (_n), \ +#define MIB_DESC_EXT(_s , _o, _n) \ + { \ + .size = (_s), \ + .offset = (_o), \ + .name = (_n), \ + .type = AR8XXX_MIB_EXTENDED, \ } static const struct ar8xxx_mib_desc ar8216_mibs[] = { - MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"), - MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"), - MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"), - MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"), - MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"), - MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"), - MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"), - MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"), - MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"), - MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"), - MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"), - MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"), - MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"), - MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"), - MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"), - MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"), - MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"), - MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"), - MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"), - MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"), - MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"), - MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"), - MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"), - MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"), - MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"), - MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"), - MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"), - MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"), - MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"), - MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"), - MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"), - MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"), - MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"), - MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"), - MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"), - MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"), - MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"), + MIB_DESC_EXT(1, AR8216_STATS_RXBROAD, "RxBroad"), + MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, "RxPause"), + MIB_DESC_EXT(1, AR8216_STATS_RXMULTI, "RxMulti"), + MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, "RxFcsErr"), + MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"), + MIB_DESC_EXT(1, AR8216_STATS_RXRUNT, "RxRunt"), + MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, "RxFragment"), + MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, "Rx64Byte"), + MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, "Rx128Byte"), + MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, "Rx256Byte"), + MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, "Rx512Byte"), + MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"), + MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"), + MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, "RxTooLong"), + MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"), + MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, "RxBadByte"), + MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"), + MIB_DESC_EXT(1, AR8216_STATS_FILTERED, "Filtered"), + MIB_DESC_EXT(1, AR8216_STATS_TXBROAD, "TxBroad"), + MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, "TxPause"), + MIB_DESC_EXT(1, AR8216_STATS_TXMULTI, "TxMulti"), + MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"), + MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, "Tx64Byte"), + MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, "Tx128Byte"), + MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, "Tx256Byte"), + MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, "Tx512Byte"), + MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"), + MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"), + MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"), + MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, "TxByte"), + MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, "TxCollision"), + MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"), + MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"), + MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"), + MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"), + MIB_DESC_EXT(1, AR8216_STATS_TXDEFER, "TxDefer"), + MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, "TxLateCol"), }; const struct ar8xxx_mib_desc ar8236_mibs[39] = { - MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"), - MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"), - MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"), - MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"), - MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"), - MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"), - MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"), - MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"), - MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"), - MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"), - MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"), - MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"), - MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"), - MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"), - MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"), - MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"), - MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"), - MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"), - MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"), - MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"), - MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"), - MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"), - MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"), - MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"), - MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"), - MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"), - MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"), - MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"), - MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"), - MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"), - MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"), - MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"), - MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"), - MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"), - MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"), - MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"), - MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"), - MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"), - MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"), + MIB_DESC_EXT(1, AR8236_STATS_RXBROAD, "RxBroad"), + MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, "RxPause"), + MIB_DESC_EXT(1, AR8236_STATS_RXMULTI, "RxMulti"), + MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, "RxFcsErr"), + MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"), + MIB_DESC_EXT(1, AR8236_STATS_RXRUNT, "RxRunt"), + MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, "RxFragment"), + MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, "Rx64Byte"), + MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, "Rx128Byte"), + MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, "Rx256Byte"), + MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, "Rx512Byte"), + MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"), + MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"), + MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"), + MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, "RxTooLong"), + MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"), + MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, "RxBadByte"), + MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"), + MIB_DESC_EXT(1, AR8236_STATS_FILTERED, "Filtered"), + MIB_DESC_EXT(1, AR8236_STATS_TXBROAD, "TxBroad"), + MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, "TxPause"), + MIB_DESC_EXT(1, AR8236_STATS_TXMULTI, "TxMulti"), + MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"), + MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, "Tx64Byte"), + MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, "Tx128Byte"), + MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, "Tx256Byte"), + MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, "Tx512Byte"), + MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"), + MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"), + MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"), + MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"), + MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, "TxByte"), + MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, "TxCollision"), + MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"), + MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"), + MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"), + MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"), + MIB_DESC_EXT(1, AR8236_STATS_TXDEFER, "TxDefer"), + MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, "TxLateCol"), }; static DEFINE_MUTEX(ar8xxx_dev_list_lock); static LIST_HEAD(ar8xxx_dev_list); +static void +ar8xxx_mib_start(struct ar8xxx_priv *priv); +static void +ar8xxx_mib_stop(struct ar8xxx_priv *priv); + /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */ static int ar8xxx_phy_poll_reset(struct mii_bus *bus) @@ -188,7 +202,7 @@ ar8xxx_phy_init(struct ar8xxx_priv *priv) int i; struct mii_bus *bus; - bus = priv->mii_bus; + bus = priv->sw_mii_bus ?: priv->mii_bus; for (i = 0; i < AR8XXX_NUM_PHYS; i++) { if (priv->chip->phy_fixup) priv->chip->phy_fixup(priv, i); @@ -426,6 +440,8 @@ ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush) u64 t; mib = &priv->chip->mib_decs[i]; + if (mib->type > priv->mib_type) + continue; t = ar8xxx_read(priv, base + mib->offset); if (mib->size == 2) { u64 hi; @@ -651,7 +667,8 @@ ar8216_read_port_status(struct ar8xxx_priv *priv, int port) } static void -ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members) +__ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members, + bool ath_hdr_en) { u32 header; u32 egress, ingress; @@ -670,10 +687,7 @@ ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members) ingress = AR8216_IN_PORT_ONLY; } - if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU) - header = AR8216_PORT_CTRL_HEADER; - else - header = 0; + header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0; ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port), AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE | @@ -691,12 +705,23 @@ ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members) (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S)); } +static void +ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members) +{ + return __ar8216_setup_port(priv, port, members, + chip_is_ar8216(priv) && priv->vlan && + port == AR8216_PORT_CPU); +} + static int ar8216_hw_init(struct ar8xxx_priv *priv) { if (priv->initialized) return 0; + ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET); + ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000); + ar8xxx_phy_init(priv); priv->initialized = true; @@ -714,7 +739,8 @@ ar8216_init_globals(struct ar8xxx_priv *priv) } static void -ar8216_init_port(struct ar8xxx_priv *priv, int port) +__ar8216_init_port(struct ar8xxx_priv *priv, int port, + bool cpu_ge, bool flow_en) { /* Enable port learning and tx */ ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port), @@ -726,12 +752,11 @@ ar8216_init_port(struct ar8xxx_priv *priv, int port) if (port == AR8216_PORT_CPU) { ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port), AR8216_PORT_STATUS_LINK_UP | - (ar8xxx_has_gige(priv) ? - AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) | + (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) | AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC | - (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) | - (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) | + (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) | + (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) | AR8216_PORT_STATUS_DUPLEX); } else { ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port), @@ -739,6 +764,13 @@ ar8216_init_port(struct ar8xxx_priv *priv, int port) } } +static void +ar8216_init_port(struct ar8xxx_priv *priv, int port) +{ + __ar8216_init_port(priv, port, ar8xxx_has_gige(priv), + chip_is_ar8316(priv)); +} + static void ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1) { @@ -806,6 +838,193 @@ static void ar8216_get_arl_entry(struct ar8xxx_priv *priv, } } +static int +ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum) +{ + u32 t, val = 0xffff; + int err; + + if (addr >= AR8216_NUM_PORTS) + return 0xffff; + t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) | + (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) | + AR8216_MDIO_CTRL_MASTER_EN | + AR8216_MDIO_CTRL_BUSY | + AR8216_MDIO_CTRL_CMD_READ; + + ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t); + err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL, + AR8216_MDIO_CTRL_BUSY, 0, 5); + if (!err) + val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL); + + return val & AR8216_MDIO_CTRL_DATA_M; +} + +static int +ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val) +{ + u32 t; + int ret; + + if (addr >= AR8216_NUM_PORTS) + return -EINVAL; + + t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) | + (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) | + AR8216_MDIO_CTRL_MASTER_EN | + AR8216_MDIO_CTRL_BUSY | + AR8216_MDIO_CTRL_CMD_WRITE | + val; + + ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t); + ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL, + AR8216_MDIO_CTRL_BUSY, 0, 5); + + return ret; +} + +static int +ar8229_hw_init(struct ar8xxx_priv *priv) +{ + int phy_if_mode; + + if (priv->initialized) + return 0; + + ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET); + ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000); + + phy_if_mode = of_get_phy_mode(priv->pdev->of_node); + + if (phy_if_mode == PHY_INTERFACE_MODE_GMII) { + ar8xxx_write(priv, AR8229_REG_OPER_MODE0, + AR8229_OPER_MODE0_MAC_GMII_EN); + } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) { + ar8xxx_write(priv, AR8229_REG_OPER_MODE0, + AR8229_OPER_MODE0_PHY_MII_EN); + } else { + pr_err("ar8229: unsupported mii mode\n"); + return -EINVAL; + } + + if (priv->port4_phy) { + ar8xxx_write(priv, AR8229_REG_OPER_MODE1, + AR8229_REG_OPER_MODE1_PHY4_MII_EN); + /* disable port5 to prevent mii conflict */ + ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0); + } + + ar8xxx_phy_init(priv); + + priv->initialized = true; + return 0; +} + +static void +ar8229_init_globals(struct ar8xxx_priv *priv) +{ + + /* Enable CPU port, and disable mirror port */ + ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT, + AR8216_GLOBAL_CPUPORT_EN | + (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S)); + + /* Setup TAG priority mapping */ + ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50); + + /* Enable aging, MAC replacing */ + ar8xxx_write(priv, AR8216_REG_ATU_CTRL, + 0x2b /* 5 min age time */ | + AR8216_ATU_CTRL_AGE_EN | + AR8216_ATU_CTRL_LEARN_CHANGE); + + /* Enable ARP frame acknowledge */ + ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL, + AR8229_QM_CTRL_ARP_EN); + + /* Enable Broadcast/Multicast frames transmitted to the CPU */ + ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK, + AR8229_FLOOD_MASK_BC_DP(0) | + AR8229_FLOOD_MASK_MC_DP(0)); + + /* setup MTU */ + ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL, + AR8236_GCTRL_MTU, AR8236_GCTRL_MTU); + + /* Enable MIB counters */ + ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC, + AR8236_MIB_EN); + + /* setup Service TAG */ + ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0); +} + +static void +ar8229_init_port(struct ar8xxx_priv *priv, int port) +{ + __ar8216_init_port(priv, port, true, true); +} + + +static int +ar7240sw_hw_init(struct ar8xxx_priv *priv) +{ + if (priv->initialized) + return 0; + + ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET); + ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000); + + priv->port4_phy = 1; + /* disable port5 to prevent mii conflict */ + ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0); + + ar8xxx_phy_init(priv); + + priv->initialized = true; + return 0; +} + +static void +ar7240sw_init_globals(struct ar8xxx_priv *priv) +{ + + /* Enable CPU port, and disable mirror port */ + ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT, + AR8216_GLOBAL_CPUPORT_EN | + (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S)); + + /* Setup TAG priority mapping */ + ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50); + + /* Enable ARP frame acknowledge, aging, MAC replacing */ + ar8xxx_write(priv, AR8216_REG_ATU_CTRL, + AR8216_ATU_CTRL_RESERVED | + 0x2b /* 5 min age time */ | + AR8216_ATU_CTRL_AGE_EN | + AR8216_ATU_CTRL_ARP_EN | + AR8216_ATU_CTRL_LEARN_CHANGE); + + /* Enable Broadcast frames transmitted to the CPU */ + ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK, + AR8236_FM_CPU_BROADCAST_EN); + + /* setup MTU */ + ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL, + AR8216_GCTRL_MTU, + AR8216_GCTRL_MTU); + + /* setup Service TAG */ + ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0); +} + +static void +ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members) +{ + return __ar8216_setup_port(priv, port, members, false); +} + static void ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members) { @@ -1239,6 +1458,62 @@ unlock: return ret; } +int +ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + if (!ar8xxx_has_mib_counters(priv)) + return -EOPNOTSUPP; + + ar8xxx_mib_stop(priv); + priv->mib_poll_interval = val->value.i; + ar8xxx_mib_start(priv); + + return 0; +} + +int +ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + if (!ar8xxx_has_mib_counters(priv)) + return -EOPNOTSUPP; + val->value.i = priv->mib_poll_interval; + return 0; +} + +int +ar8xxx_sw_set_mib_type(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + if (!ar8xxx_has_mib_counters(priv)) + return -EOPNOTSUPP; + priv->mib_type = val->value.i; + return 0; +} + +int +ar8xxx_sw_get_mib_type(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + if (!ar8xxx_has_mib_counters(priv)) + return -EOPNOTSUPP; + val->value.i = priv->mib_type; + return 0; +} + int ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev, const struct switch_attr *attr, @@ -1410,7 +1685,7 @@ ar8xxx_sw_get_port_mib(struct switch_dev *dev, int i, len = 0; bool mib_stats_empty = true; - if (!ar8xxx_has_mib_counters(priv)) + if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval) return -EOPNOTSUPP; port = val->port_vlan; @@ -1429,6 +1704,8 @@ ar8xxx_sw_get_port_mib(struct switch_dev *dev, mib_stats = &priv->mib_stats[port * chip->num_mibs]; for (i = 0; i < chip->num_mibs; i++) { + if (chip->mib_decs[i].type > priv->mib_type) + continue; mib_name = chip->mib_decs[i].name; mib_data = mib_stats[i]; len += snprintf(buf + len, sizeof(priv->buf) - len, @@ -1595,6 +1872,48 @@ ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev, return ret; } +int +ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port, + struct switch_port_stats *stats) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + u64 *mib_stats; + + if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval) + return -EOPNOTSUPP; + + if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id)) + return -EOPNOTSUPP; + + if (port >= dev->ports) + return -EINVAL; + + mutex_lock(&priv->mib_lock); + + mib_stats = &priv->mib_stats[port * priv->chip->num_mibs]; + + stats->tx_bytes = mib_stats[priv->chip->mib_txb_id]; + stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id]; + + mutex_unlock(&priv->mib_lock); + return 0; +} + +static int +ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr) +{ + struct ar8xxx_priv *priv = bus->priv; + return priv->chip->phy_read(priv, phy_addr, reg_addr); +} + +static int +ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr, + u16 reg_val) +{ + struct ar8xxx_priv *priv = bus->priv; + return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val); +} + static const struct switch_attr ar8xxx_sw_attr_globals[] = { { .type = SWITCH_TYPE_INT, @@ -1610,6 +1929,20 @@ static const struct switch_attr ar8xxx_sw_attr_globals[] = { .description = "Reset all MIB counters", .set = ar8xxx_sw_set_reset_mibs, }, + { + .type = SWITCH_TYPE_INT, + .name = "ar8xxx_mib_poll_interval", + .description = "MIB polling interval in msecs (0 to disable)", + .set = ar8xxx_sw_set_mib_poll_interval, + .get = ar8xxx_sw_get_mib_poll_interval + }, + { + .type = SWITCH_TYPE_INT, + .name = "ar8xxx_mib_type", + .description = "MIB type (0=basic 1=extended)", + .set = ar8xxx_sw_set_mib_type, + .get = ar8xxx_sw_get_mib_type + }, { .type = SWITCH_TYPE_INT, .name = "enable_mirror_rx", @@ -1710,16 +2043,41 @@ static const struct switch_dev_ops ar8xxx_sw_ops = { .apply_config = ar8xxx_sw_hw_apply, .reset_switch = ar8xxx_sw_reset_switch, .get_port_link = ar8xxx_sw_get_port_link, -/* The following op is disabled as it hogs the CPU and degrades performance. - An implementation has been attempted in 4d8a66d but reading MIB data is slow - on ar8xxx switches. - - The high CPU load has been traced down to the ar8xxx_reg_wait() call in - ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by - the request to update the MIB counter is cleared. */ -#if 0 .get_port_stats = ar8xxx_sw_get_port_stats, -#endif +}; + +static const struct ar8xxx_chip ar7240sw_chip = { + .caps = AR8XXX_CAP_MIB_COUNTERS, + + .reg_port_stats_start = 0x20000, + .reg_port_stats_length = 0x100, + .reg_arl_ctrl = AR8216_REG_ATU_CTRL, + + .name = "Atheros AR724X/AR933X built-in", + .ports = AR7240SW_NUM_PORTS, + .vlans = AR8216_NUM_VLANS, + .swops = &ar8xxx_sw_ops, + + .hw_init = ar7240sw_hw_init, + .init_globals = ar7240sw_init_globals, + .init_port = ar8229_init_port, + .phy_read = ar8216_phy_read, + .phy_write = ar8216_phy_write, + .setup_port = ar7240sw_setup_port, + .read_port_status = ar8216_read_port_status, + .atu_flush = ar8216_atu_flush, + .atu_flush_port = ar8216_atu_flush_port, + .vtu_flush = ar8216_vtu_flush, + .vtu_load_vlan = ar8216_vtu_load_vlan, + .set_mirror_regs = ar8216_set_mirror_regs, + .get_arl_entry = ar8216_get_arl_entry, + .sw_hw_apply = ar8xxx_sw_hw_apply, + + .num_mibs = ARRAY_SIZE(ar8236_mibs), + .mib_decs = ar8236_mibs, + .mib_func = AR8216_REG_MIB_FUNC, + .mib_rxb_id = AR8236_MIB_RXB_ID, + .mib_txb_id = AR8236_MIB_TXB_ID, }; static const struct ar8xxx_chip ar8216_chip = { @@ -1749,7 +2107,43 @@ static const struct ar8xxx_chip ar8216_chip = { .num_mibs = ARRAY_SIZE(ar8216_mibs), .mib_decs = ar8216_mibs, - .mib_func = AR8216_REG_MIB_FUNC + .mib_func = AR8216_REG_MIB_FUNC, + .mib_rxb_id = AR8216_MIB_RXB_ID, + .mib_txb_id = AR8216_MIB_TXB_ID, +}; + +static const struct ar8xxx_chip ar8229_chip = { + .caps = AR8XXX_CAP_MIB_COUNTERS, + + .reg_port_stats_start = 0x20000, + .reg_port_stats_length = 0x100, + .reg_arl_ctrl = AR8216_REG_ATU_CTRL, + + .name = "Atheros AR8229", + .ports = AR8216_NUM_PORTS, + .vlans = AR8216_NUM_VLANS, + .swops = &ar8xxx_sw_ops, + + .hw_init = ar8229_hw_init, + .init_globals = ar8229_init_globals, + .init_port = ar8229_init_port, + .phy_read = ar8216_phy_read, + .phy_write = ar8216_phy_write, + .setup_port = ar8236_setup_port, + .read_port_status = ar8216_read_port_status, + .atu_flush = ar8216_atu_flush, + .atu_flush_port = ar8216_atu_flush_port, + .vtu_flush = ar8216_vtu_flush, + .vtu_load_vlan = ar8216_vtu_load_vlan, + .set_mirror_regs = ar8216_set_mirror_regs, + .get_arl_entry = ar8216_get_arl_entry, + .sw_hw_apply = ar8xxx_sw_hw_apply, + + .num_mibs = ARRAY_SIZE(ar8236_mibs), + .mib_decs = ar8236_mibs, + .mib_func = AR8216_REG_MIB_FUNC, + .mib_rxb_id = AR8236_MIB_RXB_ID, + .mib_txb_id = AR8236_MIB_TXB_ID, }; static const struct ar8xxx_chip ar8236_chip = { @@ -1779,7 +2173,9 @@ static const struct ar8xxx_chip ar8236_chip = { .num_mibs = ARRAY_SIZE(ar8236_mibs), .mib_decs = ar8236_mibs, - .mib_func = AR8216_REG_MIB_FUNC + .mib_func = AR8216_REG_MIB_FUNC, + .mib_rxb_id = AR8236_MIB_RXB_ID, + .mib_txb_id = AR8236_MIB_TXB_ID, }; static const struct ar8xxx_chip ar8316_chip = { @@ -1809,11 +2205,13 @@ static const struct ar8xxx_chip ar8316_chip = { .num_mibs = ARRAY_SIZE(ar8236_mibs), .mib_decs = ar8236_mibs, - .mib_func = AR8216_REG_MIB_FUNC + .mib_func = AR8216_REG_MIB_FUNC, + .mib_rxb_id = AR8236_MIB_RXB_ID, + .mib_txb_id = AR8236_MIB_TXB_ID, }; static int -ar8xxx_id_chip(struct ar8xxx_priv *priv) +ar8xxx_read_id(struct ar8xxx_priv *priv) { u32 val; u16 id; @@ -1838,6 +2236,17 @@ ar8xxx_id_chip(struct ar8xxx_priv *priv) priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S; priv->chip_rev = (id & AR8216_CTRL_REVISION); + return 0; +} + +static int +ar8xxx_id_chip(struct ar8xxx_priv *priv) +{ + int ret; + + ret = ar8xxx_read_id(priv); + if(ret) + return ret; switch (priv->chip_ver) { case AR8XXX_VER_AR8216: @@ -1869,7 +2278,7 @@ static void ar8xxx_mib_work_func(struct work_struct *work) { struct ar8xxx_priv *priv; - int err; + int err, i; priv = container_of(work, struct ar8xxx_priv, mib_work.work); @@ -1877,18 +2286,15 @@ ar8xxx_mib_work_func(struct work_struct *work) err = ar8xxx_mib_capture(priv); if (err) - goto next_port; + goto next_attempt; - ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false); - -next_port: - priv->mib_next_port++; - if (priv->mib_next_port >= priv->dev.ports) - priv->mib_next_port = 0; + for (i = 0; i < priv->dev.ports; i++) + ar8xxx_mib_fetch_port_stat(priv, i, false); +next_attempt: mutex_unlock(&priv->mib_lock); schedule_delayed_work(&priv->mib_work, - msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY)); + msecs_to_jiffies(priv->mib_poll_interval)); } static int @@ -1914,17 +2320,17 @@ ar8xxx_mib_init(struct ar8xxx_priv *priv) static void ar8xxx_mib_start(struct ar8xxx_priv *priv) { - if (!ar8xxx_has_mib_counters(priv)) + if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval) return; schedule_delayed_work(&priv->mib_work, - msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY)); + msecs_to_jiffies(priv->mib_poll_interval)); } static void ar8xxx_mib_stop(struct ar8xxx_priv *priv) { - if (!ar8xxx_has_mib_counters(priv)) + if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval) return; cancel_delayed_work_sync(&priv->mib_work); @@ -1964,10 +2370,6 @@ ar8xxx_probe_switch(struct ar8xxx_priv *priv) struct switch_dev *swdev; int ret; - ret = ar8xxx_id_chip(priv); - if (ret) - return ret; - chip = priv->chip; swdev = &priv->dev; @@ -2085,7 +2487,9 @@ ar8xxx_phy_read_status(struct phy_device *phydev) struct switch_port_link link; /* check for switch port link changes */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) if (phydev->state == PHY_CHANGELINK) +#endif ar8xxx_check_link_states(priv); if (phydev->mdio.addr != 0) @@ -2195,6 +2599,16 @@ ar8xxx_phy_probe(struct phy_device *phydev) } priv->mii_bus = phydev->mdio.bus; + priv->pdev = &phydev->mdio.dev; + + ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval", + &priv->mib_poll_interval); + if (ret) + priv->mib_poll_interval = 0; + + ret = ar8xxx_id_chip(priv); + if (ret) + goto free_priv; ret = ar8xxx_probe_switch(priv); if (ret) @@ -2216,6 +2630,14 @@ found: priv->use_count++; if (phydev->mdio.addr == 0) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) + linkmode_zero(phydev->supported); + if (ar8xxx_has_gige(priv)) + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported); + else + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported); + linkmode_copy(phydev->advertising, phydev->supported); +#else if (ar8xxx_has_gige(priv)) { phydev->supported = SUPPORTED_1000baseT_Full; phydev->advertising = ADVERTISED_1000baseT_Full; @@ -2223,6 +2645,7 @@ found: phydev->supported = SUPPORTED_100baseT_Full; phydev->advertising = ADVERTISED_100baseT_Full; } +#endif if (priv->chip->config_at_probe) { priv->phy = phydev; @@ -2233,8 +2656,14 @@ found: } } else { if (ar8xxx_has_gige(priv)) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) + linkmode_zero(phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported); + linkmode_copy(phydev->advertising, phydev->supported); +#else phydev->supported |= SUPPORTED_1000baseT_Full; phydev->advertising |= ADVERTISED_1000baseT_Full; +#endif } if (priv->chip->phy_rgmii_set) priv->chip->phy_rgmii_set(priv, phydev); @@ -2321,5 +2750,172 @@ static struct phy_driver ar8xxx_phy_driver[] = { } }; -module_phy_driver(ar8xxx_phy_driver); +static const struct of_device_id ar8xxx_mdiodev_of_match[] = { + { + .compatible = "qca,ar7240sw", + .data = &ar7240sw_chip, + }, { + .compatible = "qca,ar8229", + .data = &ar8229_chip, + }, { + .compatible = "qca,ar8236", + .data = &ar8236_chip, + }, { + .compatible = "qca,ar8327", + .data = &ar8327_chip, + }, + { /* sentinel */ }, +}; + +static int +ar8xxx_mdiodev_probe(struct mdio_device *mdiodev) +{ + const struct of_device_id *match; + struct ar8xxx_priv *priv; + struct switch_dev *swdev; + struct device_node *mdio_node; + int ret; + + match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev); + if (!match) + return -EINVAL; + + priv = ar8xxx_create(); + if (priv == NULL) + return -ENOMEM; + + priv->mii_bus = mdiodev->bus; + priv->pdev = &mdiodev->dev; + priv->chip = (const struct ar8xxx_chip *) match->data; + + ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval", + &priv->mib_poll_interval); + if (ret) + priv->mib_poll_interval = 0; + + ret = ar8xxx_read_id(priv); + if (ret) + goto free_priv; + + ret = ar8xxx_probe_switch(priv); + if (ret) + goto free_priv; + + if (priv->chip->phy_read && priv->chip->phy_write) { + priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev); + priv->sw_mii_bus->name = "ar8xxx-mdio"; + priv->sw_mii_bus->read = ar8xxx_phy_read; + priv->sw_mii_bus->write = ar8xxx_phy_write; + priv->sw_mii_bus->priv = priv; + priv->sw_mii_bus->parent = &mdiodev->dev; + snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s", + dev_name(&mdiodev->dev)); + mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus"); + ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node); + if (ret) + goto free_priv; + } + + swdev = &priv->dev; + swdev->alias = dev_name(&mdiodev->dev); + + if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) { + priv->port4_phy = true; + swdev->ports--; + } + + ret = register_switch(swdev, NULL); + if (ret) + goto free_priv; + + pr_info("%s: %s rev. %u switch registered on %s\n", + swdev->devname, swdev->name, priv->chip_rev, + dev_name(&priv->mii_bus->dev)); + + mutex_lock(&ar8xxx_dev_list_lock); + list_add(&priv->list, &ar8xxx_dev_list); + mutex_unlock(&ar8xxx_dev_list_lock); + + priv->use_count++; + + ret = ar8xxx_start(priv); + if (ret) + goto err_unregister_switch; + + dev_set_drvdata(&mdiodev->dev, priv); + + return 0; + +err_unregister_switch: + if (--priv->use_count) + return ret; + + unregister_switch(&priv->dev); + +free_priv: + ar8xxx_free(priv); + return ret; +} + +static void +ar8xxx_mdiodev_remove(struct mdio_device *mdiodev) +{ + struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev); + + if (WARN_ON(!priv)) + return; + + mutex_lock(&ar8xxx_dev_list_lock); + + if (--priv->use_count > 0) { + mutex_unlock(&ar8xxx_dev_list_lock); + return; + } + + list_del(&priv->list); + mutex_unlock(&ar8xxx_dev_list_lock); + + unregister_switch(&priv->dev); + ar8xxx_mib_stop(priv); + if(priv->sw_mii_bus) + mdiobus_unregister(priv->sw_mii_bus); + ar8xxx_free(priv); +} + +static struct mdio_driver ar8xxx_mdio_driver = { + .probe = ar8xxx_mdiodev_probe, + .remove = ar8xxx_mdiodev_remove, + .mdiodrv.driver = { + .name = "ar8xxx-switch", + .of_match_table = ar8xxx_mdiodev_of_match, + }, +}; + +static int __init ar8216_init(void) +{ + int ret; + + ret = phy_drivers_register(ar8xxx_phy_driver, + ARRAY_SIZE(ar8xxx_phy_driver), + THIS_MODULE); + if (ret) + return ret; + + ret = mdio_driver_register(&ar8xxx_mdio_driver); + if (ret) + phy_drivers_unregister(ar8xxx_phy_driver, + ARRAY_SIZE(ar8xxx_phy_driver)); + + return ret; +} +module_init(ar8216_init); + +static void __exit ar8216_exit(void) +{ + mdio_driver_unregister(&ar8xxx_mdio_driver); + phy_drivers_unregister(ar8xxx_phy_driver, + ARRAY_SIZE(ar8xxx_phy_driver)); +} +module_exit(ar8216_exit); + MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index 0a3e96dbef..bf34fdb775 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -26,6 +26,7 @@ #define AR8216_PORT_CPU 0 #define AR8216_NUM_PORTS 6 #define AR8216_NUM_VLANS 16 +#define AR7240SW_NUM_PORTS 5 #define AR8316_NUM_VLANS 4096 /* size of the vlan table */ @@ -55,6 +56,8 @@ #define AR8216_REG_FLOOD_MASK 0x002C #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6) #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6) +#define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p)) +#define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p)) #define AR8236_FM_CPU_BROADCAST_EN BIT(26) #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25) @@ -130,6 +133,14 @@ #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) #define AR8216_ATU_CTRL_AGE_TIME_S 0 #define AR8236_ATU_CTRL_RES BIT(20) +#define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18) +#define AR8216_ATU_CTRL_RESERVED BIT(19) +#define AR8216_ATU_CTRL_ARP_EN BIT(20) + +#define AR8216_REG_TAG_PRIORITY 0x0070 + +#define AR8216_REG_SERVICE_TAG 0x0074 +#define AR8216_SERVICE_TAG_M BITS(0, 16) #define AR8216_REG_MIB_FUNC 0x0080 #define AR8216_MIB_TIMER BITS(0, 16) @@ -145,6 +156,16 @@ #define AR8216_REG_GLOBAL_CPUPORT 0x0078 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4) #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4 +#define AR8216_GLOBAL_CPUPORT_EN BIT(8) + +#define AR8216_REG_MDIO_CTRL 0x98 +#define AR8216_MDIO_CTRL_DATA_M BITS(0, 16) +#define AR8216_MDIO_CTRL_REG_ADDR_S 16 +#define AR8216_MDIO_CTRL_PHY_ADDR_S 21 +#define AR8216_MDIO_CTRL_CMD_WRITE 0 +#define AR8216_MDIO_CTRL_CMD_READ BIT(27) +#define AR8216_MDIO_CTRL_MASTER_EN BIT(30) +#define AR8216_MDIO_CTRL_BUSY BIT(31) #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1)) #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000) @@ -240,6 +261,19 @@ #define AR8216_STATS_TXDEFER 0x98 #define AR8216_STATS_TXLATECOL 0x9c +#define AR8216_MIB_RXB_ID 14 /* RxGoodByte */ +#define AR8216_MIB_TXB_ID 29 /* TxByte */ + +#define AR8229_REG_OPER_MODE0 0x04 +#define AR8229_OPER_MODE0_MAC_GMII_EN BIT(6) +#define AR8229_OPER_MODE0_PHY_MII_EN BIT(10) + +#define AR8229_REG_OPER_MODE1 0x08 +#define AR8229_REG_OPER_MODE1_PHY4_MII_EN BIT(28) + +#define AR8229_REG_QM_CTRL 0x3c +#define AR8229_QM_CTRL_ARP_EN BIT(15) + #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008) #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12) #define AR8236_PORT_VLAN_DEFAULT_ID_S 16 @@ -293,6 +327,9 @@ #define AR8236_STATS_TXDEFER 0xa0 #define AR8236_STATS_TXLATECOL 0xa4 +#define AR8236_MIB_RXB_ID 15 /* RxGoodByte */ +#define AR8236_MIB_TXB_ID 31 /* TxByte */ + #define AR8316_REG_POSTRIP 0x0008 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0) #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1) @@ -355,6 +392,12 @@ enum { AR8216_PORT_STATE_FORWARD = 4 }; +/* mib counter type */ +enum { + AR8XXX_MIB_BASIC = 0, + AR8XXX_MIB_EXTENDED = 1 +}; + enum { AR8XXX_VER_AR8216 = 0x01, AR8XXX_VER_AR8236 = 0x03, @@ -381,6 +424,7 @@ struct ar8xxx_mib_desc { unsigned int size; unsigned int offset; const char *name; + u8 type; }; struct ar8xxx_chip { @@ -417,16 +461,22 @@ struct ar8xxx_chip { u32 *status, enum arl_op op); int (*sw_hw_apply)(struct switch_dev *dev); void (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev); + int (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum); + int (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val); const struct ar8xxx_mib_desc *mib_decs; unsigned num_mibs; unsigned mib_func; + int mib_rxb_id; + int mib_txb_id; }; struct ar8xxx_priv { struct switch_dev dev; struct mii_bus *mii_bus; + struct mii_bus *sw_mii_bus; struct phy_device *phy; + struct device *pdev; int (*get_port_link)(unsigned port); @@ -448,8 +498,9 @@ struct ar8xxx_priv { struct mutex mib_lock; struct delayed_work mib_work; - int mib_next_port; u64 *mib_stats; + u32 mib_poll_interval; + u8 mib_type; struct list_head list; unsigned int use_count; @@ -505,6 +556,22 @@ ar8xxx_sw_set_reset_mibs(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); int +ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mib_type(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mib_type(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); @@ -576,6 +643,9 @@ ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); int +ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port, + struct switch_port_stats *stats); +int ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val); static inline struct ar8xxx_priv * diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.c b/target/linux/generic/files/drivers/net/phy/ar8327.c index ad3f06597b..4cbfa4d234 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8327.c +++ b/target/linux/generic/files/drivers/net/phy/ar8327.c @@ -139,7 +139,7 @@ ar8327_phy_rgmii_set(struct ar8xxx_priv *priv, struct phy_device *phydev) if (!of_property_read_bool(np, "qca,phy-rgmii-en")) { pr_err("ar8327: qca,phy-rgmii-en is not specified\n"); - return -EINVAL; + return; } ar8xxx_phy_dbg_read(priv, phyaddr, AR8327_PHY_MODE_SEL, &phy_val); @@ -150,7 +150,7 @@ ar8327_phy_rgmii_set(struct ar8xxx_priv *priv, struct phy_device *phydev) /* set rgmii tx clock delay if needed */ if (!of_property_read_bool(np, "qca,txclk-delay-en")) { pr_err("ar8327: qca,txclk-delay-en is not specified\n"); - return -EINVAL; + return; } ar8xxx_phy_dbg_read(priv, phyaddr, AR8327_PHY_SYS_CTRL, &phy_val); @@ -161,7 +161,7 @@ ar8327_phy_rgmii_set(struct ar8xxx_priv *priv, struct phy_device *phydev) /* set rgmii rx clock delay if needed */ if (!of_property_read_bool(np, "qca,rxclk-delay-en")) { pr_err("ar8327: qca,rxclk-delay-en is not specified\n"); - return -EINVAL; + return; } ar8xxx_phy_dbg_read(priv, phyaddr, AR8327_PHY_TEST_CTRL, &phy_val); @@ -662,8 +662,8 @@ ar8327_hw_init(struct ar8xxx_priv *priv) if (!priv->chip_data) return -ENOMEM; - if (priv->phy->mdio.dev.of_node) - ret = ar8327_hw_config_of(priv, priv->phy->mdio.dev.of_node); + if (priv->pdev->of_node) + ret = ar8327_hw_config_of(priv, priv->pdev->of_node); else ret = ar8327_hw_config_pdata(priv, priv->phy->mdio.dev.platform_data); @@ -1321,6 +1321,20 @@ static const struct switch_attr ar8327_sw_attr_globals[] = { .description = "Reset all MIB counters", .set = ar8xxx_sw_set_reset_mibs, }, + { + .type = SWITCH_TYPE_INT, + .name = "ar8xxx_mib_poll_interval", + .description = "MIB polling interval in msecs (0 to disable)", + .set = ar8xxx_sw_set_mib_poll_interval, + .get = ar8xxx_sw_get_mib_poll_interval + }, + { + .type = SWITCH_TYPE_INT, + .name = "ar8xxx_mib_type", + .description = "MIB type (0=basic 1=extended)", + .set = ar8xxx_sw_set_mib_type, + .get = ar8xxx_sw_get_mib_type + }, { .type = SWITCH_TYPE_INT, .name = "enable_mirror_rx", @@ -1457,16 +1471,7 @@ static const struct switch_dev_ops ar8327_sw_ops = { .apply_config = ar8327_sw_hw_apply, .reset_switch = ar8xxx_sw_reset_switch, .get_port_link = ar8xxx_sw_get_port_link, -/* The following op is disabled as it hogs the CPU and degrades performance. - An implementation has been attempted in 4d8a66d but reading MIB data is slow - on ar8xxx switches. - - The high CPU load has been traced down to the ar8xxx_reg_wait() call in - ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by - the request to update the MIB counter is cleared. */ -#if 0 .get_port_stats = ar8xxx_sw_get_port_stats, -#endif }; const struct ar8xxx_chip ar8327_chip = { @@ -1501,7 +1506,9 @@ const struct ar8xxx_chip ar8327_chip = { .num_mibs = ARRAY_SIZE(ar8236_mibs), .mib_decs = ar8236_mibs, - .mib_func = AR8327_REG_MIB_FUNC + .mib_func = AR8327_REG_MIB_FUNC, + .mib_rxb_id = AR8236_MIB_RXB_ID, + .mib_txb_id = AR8236_MIB_TXB_ID, }; const struct ar8xxx_chip ar8337_chip = { @@ -1537,5 +1544,7 @@ const struct ar8xxx_chip ar8337_chip = { .num_mibs = ARRAY_SIZE(ar8236_mibs), .mib_decs = ar8236_mibs, - .mib_func = AR8327_REG_MIB_FUNC + .mib_func = AR8327_REG_MIB_FUNC, + .mib_rxb_id = AR8236_MIB_RXB_ID, + .mib_txb_id = AR8236_MIB_TXB_ID, }; diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c b/target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c index 5934befc9e..5675232bef 100644 --- a/target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c @@ -294,12 +294,22 @@ static int b53_phy_probe(struct phy_device *phydev) if (ret) return ret; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) + linkmode_zero(phydev->supported); + if (is5325(dev) || is5365(dev)) + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported); + else + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported); + + linkmode_copy(phydev->advertising, phydev->supported); +#else if (is5325(dev) || is5365(dev)) phydev->supported = SUPPORTED_100baseT_Full; else phydev->supported = SUPPORTED_1000baseT_Full; phydev->advertising = phydev->supported; +#endif ret = b53_switch_register(dev); if (ret) { @@ -360,6 +370,26 @@ static int b53_phy_read_status(struct phy_device *phydev) return 0; } +static const struct of_device_id b53_of_match_1[] = { + { .compatible = "brcm,bcm5325" }, + { .compatible = "brcm,bcm5395" }, + { .compatible = "brcm,bcm5397" }, + { .compatible = "brcm,bcm5398" }, + { /* sentinel */ }, +}; + +static const struct of_device_id b53_of_match_2[] = { + { .compatible = "brcm,bcm53115" }, + { .compatible = "brcm,bcm53125" }, + { .compatible = "brcm,bcm53128" }, + { /* sentinel */ }, +}; + +static const struct of_device_id b53_of_match_3[] = { + { .compatible = "brcm,bcm5365" }, + { /* sentinel */ }, +}; + /* BCM5325, BCM539x */ static struct phy_driver b53_phy_driver_id1 = { .phy_id = 0x0143bc00, @@ -371,6 +401,10 @@ static struct phy_driver b53_phy_driver_id1 = { .config_aneg = b53_phy_config_aneg, .config_init = b53_phy_config_init, .read_status = b53_phy_read_status, + .mdiodrv.driver = { + .name = "bcm539x", + .of_match_table = b53_of_match_1, + }, }; /* BCM53125, BCM53128 */ @@ -384,6 +418,10 @@ static struct phy_driver b53_phy_driver_id2 = { .config_aneg = b53_phy_config_aneg, .config_init = b53_phy_config_init, .read_status = b53_phy_read_status, + .mdiodrv.driver = { + .name = "bcm531xx", + .of_match_table = b53_of_match_2, + }, }; /* BCM5365 */ @@ -397,6 +435,10 @@ static struct phy_driver b53_phy_driver_id3 = { .config_aneg = b53_phy_config_aneg, .config_init = b53_phy_config_init, .read_status = b53_phy_read_status, + .mdiodrv.driver = { + .name = "bcm5365", + .of_match_table = b53_of_match_3, + }, }; int __init b53_phy_driver_register(void) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index be9f74f888..1b1d5001a3 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -133,23 +133,51 @@ #define RTL8367B_CHIP_MODE_MASK 0x7 #define RTL8367B_CHIP_DEBUG0_REG 0x1303 -#define RTL8367B_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x)) +#define RTL8367B_DEBUG0_SEL33(_x) BIT(8 + (_x)) +#define RTL8367B_DEBUG0_DRI_OTHER BIT(7) +#define RTL8367B_DEBUG0_DRI_RG(_x) BIT(5 + (_x)) +#define RTL8367B_DEBUG0_DRI(_x) BIT(3 + (_x)) +#define RTL8367B_DEBUG0_SLR_OTHER BIT(2) +#define RTL8367B_DEBUG0_SLR(_x) BIT(_x) #define RTL8367B_CHIP_DEBUG1_REG 0x1304 +#define RTL8367B_DEBUG1_DN_MASK(_x) \ + GENMASK(6 + (_x)*8, 4 + (_x)*8) +#define RTL8367B_DEBUG1_DN_SHIFT(_x) (4 + (_x) * 8) +#define RTL8367B_DEBUG1_DP_MASK(_x) \ + GENMASK(2 + (_x) * 8, (_x) * 8) +#define RTL8367B_DEBUG1_DP_SHIFT(_x) ((_x) * 8) + +#define RTL8367B_CHIP_DEBUG2_REG 0x13e2 +#define RTL8367B_DEBUG2_RG2_DN_MASK GENMASK(8, 6) +#define RTL8367B_DEBUG2_RG2_DN_SHIFT 6 +#define RTL8367B_DEBUG2_RG2_DP_MASK GENMASK(5, 3) +#define RTL8367B_DEBUG2_RG2_DP_SHIFT 3 +#define RTL8367B_DEBUG2_DRI_EXT2_RG BIT(2) +#define RTL8367B_DEBUG2_DRI_EXT2 BIT(1) +#define RTL8367B_DEBUG2_SLR_EXT2 BIT(0) #define RTL8367B_DIS_REG 0x1305 #define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x)) #define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x)) #define RTL8367B_DIS_RGMII_MASK 0x7 -#define RTL8367B_EXT_RGMXF_REG(_x) (0x1306 + (_x)) +#define RTL8367B_DIS2_REG 0x13c3 +#define RTL8367B_DIS2_SKIP_MII_RXER_SHIFT 4 +#define RTL8367B_DIS2_SKIP_MII_RXER 0x10 +#define RTL8367B_DIS2_RGMII_SHIFT 0 +#define RTL8367B_DIS2_RGMII_MASK 0xf + +#define RTL8367B_EXT_RGMXF_REG(_x) \ + ((_x) == 2 ? 0x13c5 : 0x1306 + (_x)) #define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5 #define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff #define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3 #define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1 #define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7 -#define RTL8367B_DI_FORCE_REG(_x) (0x1310 + (_x)) +#define RTL8367B_DI_FORCE_REG(_x) \ + ((_x) == 2 ? 0x13c4 : 0x1310 + (_x)) #define RTL8367B_DI_FORCE_MODE BIT(12) #define RTL8367B_DI_FORCE_NWAY BIT(7) #define RTL8367B_DI_FORCE_TXPAUSE BIT(6) @@ -754,28 +782,51 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id, switch (mode) { case RTL8367_EXTIF_MODE_RGMII: case RTL8367_EXTIF_MODE_RGMII_33V: - REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367); - REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777); + REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG, + RTL8367B_DEBUG0_SEL33(id), + RTL8367B_DEBUG0_SEL33(id)); + if (id <= 1) { + REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG, + RTL8367B_DEBUG0_DRI(id) | + RTL8367B_DEBUG0_DRI_RG(id) | + RTL8367B_DEBUG0_SLR(id), + RTL8367B_DEBUG0_DRI_RG(id) | + RTL8367B_DEBUG0_SLR(id)); + REG_RMW(smi, RTL8367B_CHIP_DEBUG1_REG, + RTL8367B_DEBUG1_DN_MASK(id) | + RTL8367B_DEBUG1_DP_MASK(id), + (7 << RTL8367B_DEBUG1_DN_SHIFT(id)) | + (7 << RTL8367B_DEBUG1_DP_SHIFT(id))); + } else { + REG_RMW(smi, RTL8367B_CHIP_DEBUG2_REG, + RTL8367B_DEBUG2_DRI_EXT2 | + RTL8367B_DEBUG2_DRI_EXT2_RG | + RTL8367B_DEBUG2_SLR_EXT2 | + RTL8367B_DEBUG2_RG2_DN_MASK | + RTL8367B_DEBUG2_RG2_DP_MASK, + RTL8367B_DEBUG2_DRI_EXT2_RG | + RTL8367B_DEBUG2_SLR_EXT2 | + (7 << RTL8367B_DEBUG2_RG2_DN_SHIFT) | + (7 << RTL8367B_DEBUG2_RG2_DP_SHIFT)); + } break; case RTL8367_EXTIF_MODE_TMII_MAC: case RTL8367_EXTIF_MODE_TMII_PHY: - REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, - BIT((id + 1) % 2), BIT((id + 1) % 2)); + REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, BIT(id), BIT(id)); break; case RTL8367_EXTIF_MODE_GMII: REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG, - RTL8367B_CHIP_DEBUG0_DUMMY0(id), - RTL8367B_CHIP_DEBUG0_DUMMY0(id)); + RTL8367B_DEBUG0_SEL33(id), + RTL8367B_DEBUG0_SEL33(id)); REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6)); break; case RTL8367_EXTIF_MODE_MII_MAC: case RTL8367_EXTIF_MODE_MII_PHY: case RTL8367_EXTIF_MODE_DISABLED: - REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, - BIT((id + 1) % 2), 0); + REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, BIT(id), 0); REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0); break; @@ -785,9 +836,14 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id, return -EINVAL; } - REG_RMW(smi, RTL8367B_DIS_REG, - RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id), - mode << RTL8367B_DIS_RGMII_SHIFT(id)); + if (id <= 1) + REG_RMW(smi, RTL8367B_DIS_REG, + RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id), + mode << RTL8367B_DIS_RGMII_SHIFT(id)); + else + REG_RMW(smi, RTL8367B_DIS2_REG, + RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT, + mode << RTL8367B_DIS2_RGMII_SHIFT); return 0; } @@ -931,6 +987,10 @@ static int rtl8367b_setup(struct rtl8366_smi *smi) err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1"); if (err) return err; + + err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2"); + if (err) + return err; } else { err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg); if (err) diff --git a/target/linux/generic/files/drivers/net/phy/swconfig.c b/target/linux/generic/files/drivers/net/phy/swconfig.c index 2f3a46ab07..e7da45d0f7 100644 --- a/target/linux/generic/files/drivers/net/phy/swconfig.c +++ b/target/linux/generic/files/drivers/net/phy/swconfig.c @@ -1291,6 +1291,7 @@ switch_generic_set_link(struct switch_dev *dev, int port, return 0; } +EXPORT_SYMBOL_GPL(switch_generic_set_link); static int __init swconfig_init(void)