diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
index f1953c24bd..73be747c04 100644
--- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
+++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
@@ -282,7 +282,9 @@
 		#size-cells = <2>;
 
 		rtl8125_1: pcie@30,0 {
+			compatible = "pci10ec,8125";
 			reg = <0x000000 0 0 0 0>;
+
 			realtek,led-data = <0x0 0x0 0x2b 0x200>;
 			label = "eth2";
 		};
@@ -300,7 +302,9 @@
 		#size-cells = <2>;
 
 		rtl8125_2: pcie@40,0 {
+			compatible = "pci10ec,8125";
 			reg = <0x000000 0 0 0 0>;
+
 			realtek,led-data = <0x0 0x0 0x2b 0x200>;
 			label = "eth1";
 		};
diff --git a/target/linux/rockchip/patches-6.6/610-arm64-rockchip-add-OF-node-for-eth.patch b/target/linux/rockchip/patches-6.6/610-arm64-rockchip-add-OF-node-for-eth.patch
index b47716bd6f..0e9bfafca2 100644
--- a/target/linux/rockchip/patches-6.6/610-arm64-rockchip-add-OF-node-for-eth.patch
+++ b/target/linux/rockchip/patches-6.6/610-arm64-rockchip-add-OF-node-for-eth.patch
@@ -193,6 +193,48 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  &sdhci {
  	bus-width = <8>;
  	max-frequency = <200000000>;
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+@@ -69,6 +69,19 @@
+ 	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x00100000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		rtl8125_1: pcie-eth@10,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++
++			realtek,led-data = <0x0 0x0 0x2b 0x200>;
++		};
++ 	};
+ };
+ 
+ &pcie3x2 {
+@@ -76,6 +89,19 @@
+ 	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x00200000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		rtl8125_2: pcie-eth@20,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++
++			realtek,led-data = <0x0 0x0 0x2b 0x200>;
++		};
++ 	};
+ };
+ 
+ &pinctrl {
 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
 @@ -78,6 +78,7 @@
@@ -203,6 +245,46 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	};
  };
  
+@@ -85,6 +86,19 @@
+ 	num-lanes = <1>;
+ 	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x00000000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		rtl8125_1: pcie@1,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++
++			realtek,led-data = <0x0 0x0 0x2b 0x200>;
++		};
++	};
+ };
+ 
+ &pcie30phy {
+@@ -97,6 +111,19 @@
+ 	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
+ 	status = "okay";
++
++	pcie@0,0 {
++		reg = <0x00100000 0 0 0 0>;
++		#address-cells = <3>;
++		#size-cells = <2>;
++
++		rtl8125_2: pcie@10,0 {
++			compatible = "pci10ec,8125";
++			reg = <0x000000 0 0 0 0>;
++
++			realtek,led-data = <0x0 0x0 0x2b 0x200>;
++		};
++	};
+ };
+ 
+ &pcie3x2 {
 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
 @@ -273,6 +273,10 @@
@@ -243,7 +325,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 +			compatible = "pci10ec,8125";
 +			reg = <0x000000 0 0 0 0>;
 +
-+			realtek,led-data = <0x0 0x0 0x200 0x2b>;
++			realtek,led-data = <0x0 0x0 0x2b 0x200>;
 +			label = "eth2";
 +		};
 +	};
@@ -264,7 +346,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 +			compatible = "pci10ec,8125";
 +			reg = <0x000000 0 0 0 0>;
 +
-+			realtek,led-data = <0x0 0x0 0x200 0x2b>;
++			realtek,led-data = <0x0 0x0 0x2b 0x200>;
 +			label = "eth1";
 +		};
 +	};