From eb0d7ca36cd0062d9205ad025c51439dcf297d5d Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Wed, 10 Feb 2021 12:20:21 +0800 Subject: [PATCH] sunxi: backport h5 cpufreq support from upstream linux (cherry picked from commit ecd317d8f4670f249e37ca6141d64701c646350e) --- ...s-allwinner-h5-unclock-CPU-OPP-table.patch | 27 ++++ ...-allwinner-h5-Add-clock-to-CPU-cores.patch | 54 ++++++++ ...4-dts-allwinner-h5-Add-CPU-OPP-table.patch | 128 ++++++++++++++++++ 3 files changed, 209 insertions(+) create mode 100644 target/linux/sunxi/patches-5.10/440-arm64-dts-allwinner-h5-unclock-CPU-OPP-table.patch create mode 100644 target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch create mode 100644 target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-OPP-table.patch diff --git a/target/linux/sunxi/patches-5.10/440-arm64-dts-allwinner-h5-unclock-CPU-OPP-table.patch b/target/linux/sunxi/patches-5.10/440-arm64-dts-allwinner-h5-unclock-CPU-OPP-table.patch new file mode 100644 index 0000000000..148825dd52 --- /dev/null +++ b/target/linux/sunxi/patches-5.10/440-arm64-dts-allwinner-h5-unclock-CPU-OPP-table.patch @@ -0,0 +1,27 @@ +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi +@@ -59,6 +59,24 @@ + opp-microvolt = <1300000 1300000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1248000000 { ++ opp-hz = /bits/ 64 <1248000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; + }; + }; + diff --git a/target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch b/target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch new file mode 100644 index 0000000000..1240ceb30f --- /dev/null +++ b/target/linux/sunxi/patches-5.4/016-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch @@ -0,0 +1,54 @@ +From 5fa21c1354c93cb9fe8239545b17eee46e39dd69 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Sat, 18 Jul 2020 00:00:49 +0800 +Subject: [PATCH] arm64: dts: allwinner: h5: Add clock to CPU cores + +The ARM CPU cores are fed by the CPU clock from the CCU. Add a +reference to the clock for each CPU core, along with the clock +transition latency. + +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Maxime Ripard +Link: https://lore.kernel.org/r/20200717160053.31191-5-wens@kernel.org +--- + arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +@@ -52,6 +52,8 @@ + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu1: cpu@1 { +@@ -59,6 +61,8 @@ + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu2: cpu@2 { +@@ -66,6 +70,8 @@ + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu3: cpu@3 { +@@ -73,6 +79,8 @@ + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + diff --git a/target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-OPP-table.patch b/target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-OPP-table.patch new file mode 100644 index 0000000000..982b29b1d3 --- /dev/null +++ b/target/linux/sunxi/patches-5.4/018-arm64-dts-allwinner-h5-Add-CPU-OPP-table.patch @@ -0,0 +1,128 @@ +From 7240598ba4e6c477c6809dc019505cf366fdb7c0 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Sat, 18 Jul 2020 00:00:51 +0800 +Subject: [PATCH] arm64: dts: allwinner: h5: Add CPU Operating Performance + Points table + +Add an OPP (Operating Performance Points) table for the CPU cores for +boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the +H5. The table originates from Armbian, but the maximum voltage is raised +slightly to account for boards using slightly higher voltages. + +The table and tie in to the CPU cores are put in a separate dtsi file +that board files can include to opt in. Or they can define their own +tables if the standard one does not fit. + +This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi +M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V +regulator, while the latter has a GPIO controlled regulator switchable +between 1.1V and 1.3V. + +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Maxime Ripard +Link: https://lore.kernel.org/r/20200717160053.31191-7-wens@kernel.org +--- + .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++ + 1 file changed, 79 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi +@@ -0,0 +1,97 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Chen-Yu Tsai ++ ++/ { ++ cpu_opp_table: cpu-opp-table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <1000000 1000000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-648000000 { ++ opp-hz = /bits/ 64 <648000000>; ++ opp-microvolt = <1040000 1040000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1080000 1080000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-912000000 { ++ opp-hz = /bits/ 64 <912000000>; ++ opp-microvolt = <1120000 1120000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-960000000 { ++ opp-hz = /bits/ 64 <960000000>; ++ opp-microvolt = <1160000 1160000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1200000 1200000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1240000 1240000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1260000 1260000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1248000000 { ++ opp-hz = /bits/ 64 <1248000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <1300000 1300000 1310000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu_opp_table>; ++};