Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
2021-04-12 20:19:36 +08:00 · 2021-04-12 20:19:36 +08:00 · ebe974970c
commit ebe974970c
parent bb80e686cc 9aa66b8ce7
39 changed files with 1115 additions and 60 deletions
--- a/package/boot/arm-trusted-firmware-sunxi/Makefile
+++ b/package/boot/arm-trusted-firmware-sunxi/Makefile
@ -12,40 +12,52 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=https://github.com/ARM-software/arm-trusted-firmware
-PKG_SOURCE_DATE:=2018-10-02
-PKG_SOURCE_VERSION:=dbc8d9496ead9ecdd7c2a276b542a4fbbbf64027
-PKG_MIRROR_HASH:=c81521a27b86f606e927b4e346286540b862828c8d49292eae1f5c6adfc24001
+PKG_SOURCE_DATE:=2020-11-17
+PKG_SOURCE_VERSION:=e2c509a39c6cc4dda8734e6509cdbe6e3603cdfc
+PKG_MIRROR_HASH:=b212d369a5286ebbf6a5616486efa05fa54d4294fd6e9ba2e54fdfae9eda918d

 PKG_LICENSE:=BSD-3-Clause
 PKG_LICENSE_FILES:=license.md

 PKG_MAINTAINER:=Hauke Mehrtens <hauke@hauke-m.de>

+include $(INCLUDE_DIR)/trusted-firmware-a.mk
 include $(INCLUDE_DIR)/package.mk


-define Package/arm-trusted-firmware-sunxi
+define Package/arm-trusted-firmware-sunxi/Default
    SECTION:=boot
    CATEGORY:=Boot Loaders
    TITLE:=ARM Trusted Firmware for Allwinner
    DEPENDS:=@TARGET_sunxi_cortexa53
 endef

+define Package/arm-trusted-firmware-sunxi-a64
+    $(call Package/arm-trusted-firmware-sunxi/Default)
+    VARIANT:=sun50i_a64
+endef
+
+define Package/arm-trusted-firmware-sunxi-h6
+    $(call Package/arm-trusted-firmware-sunxi/Default)
+    VARIANT:=sun50i_h6
+endef
+
 export GCC_HONOUR_COPTS=s

 MAKE_VARS = \
 	CROSS_COMPILE="$(TARGET_CROSS)"

 MAKE_FLAGS += \
-	PLAT=sun50i_a64 \
+	PLAT=$(BUILD_VARIANT) \
 	bl31

 define Build/InstallDev
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
-	$(CP) $(PKG_BUILD_DIR)/build/sun50i_a64/release/bl31.bin $(STAGING_DIR_IMAGE)/bl31.bin
+	$(CP) $(PKG_BUILD_DIR)/build/$(BUILD_VARIANT)/release/bl31.bin $(STAGING_DIR_IMAGE)/bl31_$(BUILD_VARIANT).bin
 endef

 define Package/arm-trusted-firmware-sunxi/install
 endef

-$(eval $(call BuildPackage,arm-trusted-firmware-sunxi))
+$(eval $(call BuildPackage,arm-trusted-firmware-sunxi-a64))
+$(eval $(call BuildPackage,arm-trusted-firmware-sunxi-h6))
--- a/package/boot/uboot-envtools/files/mediatek
+++ b/package/boot/uboot-envtools/files/mediatek
@ -20,9 +20,17 @@ bananapi,bpi-r64)
 	. /lib/upgrade/common.sh
 	export_bootdevice
 	export_partdevice rootdev 0
-	local envdev=/dev/$(get_partition_by_name $rootdev ubootenv)
-	ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
-	ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
+	case "$rootdev" in
+	mmc*)
+		local envdev=/dev/$(get_partition_by_name $rootdev ubootenv)
+		ubootenv_add_uci_config "$envdev" "0x0" "0x80000" "0x80000" "1"
+		ubootenv_add_uci_config "$envdev" "0x80000" "0x80000" "0x80000" "1"
+		;;
+	*)
+		ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1"
+		ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1"
+		;;
+	esac
 	;;
 buffalo,wsr-2533dhp2)
 	ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x1000" "0x20000"
--- a/package/boot/uboot-mediatek/Makefile
+++ b/package/boot/uboot-mediatek/Makefile
@ -54,6 +54,17 @@ define U-Boot/mt7622_bananapi_bpi-r64-sdmmc
  DEPENDS:=+trusted-firmware-a-mt7622-sdmmc-2ddr
 endef

+define U-Boot/mt7622_bananapi_bpi-r64-snand
+  NAME:=BananaPi R64 (SNAND)
+  UBOOT_CONFIG:=mt7622_bananapi_bpi-r64-snand
+  BUILD_DEVICES:=bananapi_bpi-r64
+  BUILD_SUBTARGET:=mt7622
+  UBOOT_IMAGE:=u-boot.fip
+  BL2_BOOTDEV:=snand
+  BL2_DDRBLOB:=2
+  DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr
+endef
+
 define U-Boot/mt7622_ubnt_unifi-6-lr
  NAME:=Ubiquiti UniFi 6 LR
  UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr
@ -90,6 +101,7 @@ endef
 UBOOT_TARGETS := \
 	mt7622_bananapi_bpi-r64-emmc \
 	mt7622_bananapi_bpi-r64-sdmmc \
+	mt7622_bananapi_bpi-r64-snand \
 	mt7622_linksys_e8450 \
 	mt7622_rfb1 \
 	mt7622_ubnt_unifi-6-lr \
--- a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
+++ b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch
@ -0,0 +1,33 @@
+--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+@@ -19,7 +19,7 @@
+ 	};
+ 
+ 	aliases {
+-		spi0 = &snfi;
+		spi0 = &snand;
+ 		ethernet0 = &eth;
+ 	};
+ 
+@@ -205,17 +205,11 @@
+ 	};
+ };
+ 
+-&snfi {
+-	pinctrl-names = "default", "snfi";
+-	pinctrl-0 = <&snor_pins>;
+-	pinctrl-1 = <&snfi_pins>;
+&snand {
+	pinctrl-names = "default";
+	pinctrl-0 = <&snfi_pins>;
+ 	status = "okay";
+-
+-	spi-flash@0{
+-		compatible = "jedec,spi-nor";
+-		reg = <0>;
+-		u-boot,dm-pre-reloc;
+-	};
+	quad-spi;
+ };
+ 
+ &uart0 {
--- a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
+++ b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch
@ -1,6 +1,6 @@
 --- /dev/null
 +++ b/configs/mt7622_bananapi_bpi-r64-sdmmc_defconfig
-@@ -0,0 +1,144 @@
+@@ -0,0 +1,157 @@
 +CONFIG_ARM=y
 +CONFIG_POSITION_INDEPENDENT=y
 +CONFIG_ARCH_MEDIATEK=y
@ -34,7 +34,7 @@
 +CONFIG_LED_GPIO=y
 +CONFIG_LOGLEVEL=7
 +CONFIG_LOG=y
-+CONFIG_DEFAULT_FDT_FILE="mt7622-bananapi-bpi-r64"
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7622-bananapi-bpi-r64.dtb"
 +CONFIG_SYS_PROMPT="MT7622> "
 +CONFIG_CMD_BOOTMENU=y
 +CONFIG_CMD_BOOTP=y
@ -42,6 +42,7 @@
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_CDP=y
 +CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
 +CONFIG_CMD_DNS=y
 +CONFIG_CMD_ECHO=y
 +CONFIG_CMD_ENV_READMEM=y
@ -59,6 +60,7 @@
 +CONFIG_CMD_LINK_LOCAL=y
 +# CONFIG_CMD_MBR is not set
 +CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 +CONFIG_CMD_PCI=y
 +CONFIG_CMD_SF_TEST=y
 +CONFIG_CMD_PING=y
@ -67,6 +69,9 @@
 +CONFIG_CMD_SMC=y
 +CONFIG_CMD_TFTPBOOT=y
 +CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
 +CONFIG_CMD_ASKENV=y
 +CONFIG_CMD_PART=y
 +# CONFIG_CMD_PSTORE is not set
@ -80,6 +85,7 @@
 +CONFIG_CMD_UUID=y
 +CONFIG_DISPLAY_CPUINFO=y
 +CONFIG_DM_MMC=y
+CONFIG_DM_MTD=y
 +CONFIG_DM_REGULATOR=y
 +CONFIG_DM_REGULATOR_FIXED=y
 +CONFIG_DM_REGULATOR_GPIO=y
@ -115,6 +121,9 @@
 +CONFIG_DM_ETH=y
 +CONFIG_MEDIATEK_ETH=y
 +CONFIG_PCI=y
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)"
 +CONFIG_DM_PCI=y
 +CONFIG_PCIE_MEDIATEK=y
 +CONFIG_PINCTRL=y
@ -133,6 +142,10 @@
 +CONFIG_MMC_MTK=y
 +CONFIG_MMC_SUPPORTS_TUNING=y
 +CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
 +CONFIG_SYSRESET_WATCHDOG=y
 +CONFIG_WDT_MTK=y
 +CONFIG_LZO=y
@ -147,20 +160,20 @@
 +CONFIG_USB_STORAGE=y
 --- /dev/null
 +++ b/bananapi_bpi-r64-sdmmc_env
-@@ -0,0 +1,60 @@
+@@ -0,0 +1,81 @@
 +ipaddr=192.168.1.1
 +serverip=192.168.1.254
 +loadaddr=0x4007ff28
-+bootcmd=run boot_sdmmc
 +bootargs=root=/dev/mmcblk1p65
+bootcmd=run boot_sdmmc
 +bootconf=config-mt7622-bananapi-bpi-r64-pcie1
 +bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1
 +bootconf_sata=config-mt7622-bananapi-bpi-r64-sata
 +bootdelay=0
 +bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb
 +bootfile_upg=openwrt-mediatek-mt7622-bananapi_bpi-r64-squashfs-sysupgrade.itb
-+bootfile_emmcbl3=openwrt-mediatek-mt7622-bananapi_bpi-r64-boot-emmc.img
-+bootfile_emmcbl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-bl2-emmc.bin
+bootfile_emmcbl3=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-bl31-uboot.fip
+bootfile_emmcbl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-preloader.bin
 +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
 +bootmenu_default=0
 +bootmenu_delay=0
@ -172,9 +185,10 @@
 +bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return
 +bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; run boot_tftp_production ; setenv noboot ; run bootmenu_confirm_return
 +bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; run boot_tftp_recovery ; setenv noboot ; run bootmenu_confirm_return
-+bootmenu_6=[31mInstall bootloader and recovery to eMMC.[0m=run emmc_init ; run bootmenu_confirm_return
-+bootmenu_7=Reboot.=reset
-+bootmenu_8=Reset all settings to factory defaults.=run reset_factory ; reset
+bootmenu_6=[31mInstall bootloader, recovery and production to eMMC.[0m=run emmc_init ; run bootmenu_confirm_return
+bootmenu_7=[31mInstall bootloader, recovery and production to NAND.[0m=run ubi_init ; run bootmenu_confirm_return
+bootmenu_8=Reboot.=reset
+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
 +boot_default=run bootcmd ; run boot_recovery ; run boot_tftp_forever
 +boot_first=if button reset ; then run boot_tftp_forever ; fi ; bootmenu
 +boot_production=led bpi-r64:pio:green on ; run sdmmc_read_production && bootm $loadaddr#$bootconf
@ -184,26 +198,46 @@
 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
-+emmc_write_bl2=mmc dev 0 1 && mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $loadaddr 0x0 0x100 ; mmc partconf 0 1 1 0
-+emmc_write_hdr=mmc dev 0 0 && mmc erase 0x0 0x40 && mmc write $loadaddr 0x0 0x40
-+emmc_write_bl3=mmc dev 0 0 && mmc erase 0x1000 0x1000 && mmc write $loadaddr 0x1000 0x1000 && mmc erase 0x2000 0x800
-+emmc_write_production=iminfo $loadaddr && mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
-+emmc_write_recovery=iminfo $loadaddr && mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
+boot_ubi=ubi part ubi && setenv bootargs && run boot_ubi_production ; run check_recovery
+boot_ubi_production=led bpi-r64:pio:green on ; run ubi_read_production && bootm $loadaddr
+boot_ubi_recovery=led bpi-r64:pio:green off ; run check_recovery
+check_recovery=run ubi_read_recovery ; if iminfo $loadaddr ; then bootm $loadaddr ; else ubi remove recovery ; fi
+check_ubi=ubi part ubi || run ubi_format
+emmc_init=run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
 +emmc_init_bl=run sdmmc_read_emmc_bl2 && run emmc_write_bl2 && run sdmmc_read_emmc_hdr && run emmc_write_hdr && run sdmmc_read_emmc_bl3 && run emmc_write_bl3
 +emmc_init_openwrt=run sdmmc_read_recovery && run emmc_write_recovery ; run sdmmc_read_production && run emmc_write_production
-+emmc_init=run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
-+sdmmc_write_production=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_write_vol
-+sdmmc_write_recovery=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol
-+sdmmc_read_production=mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_read_vol
-+sdmmc_read_recovery=mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_read_vol
-+sdmmc_read_emmc_hdr=mmc dev 1 && part start mmc 1 install part_addr && mmc read $loadaddr $part_addr 0x40
-+sdmmc_read_emmc_bl2=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x400 && mmc read $loadaddr $offset 0x400
-+sdmmc_read_emmc_bl3=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x1000 && mmc read $loadaddr $offset 0x1000
+emmc_write_bl2=mmc dev 0 1 && mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $loadaddr 0x0 0x100 ; mmc partconf 0 1 1 0
+emmc_write_bl3=mmc dev 0 0 && mmc erase 0x1000 0x1000 && mmc write $loadaddr 0x1000 0x1000 && mmc erase 0x2000 0x800
+emmc_write_hdr=mmc dev 0 0 && mmc erase 0x0 0x40 && mmc write $loadaddr 0x0 0x40
+emmc_write_production=iminfo $loadaddr && mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
+emmc_write_recovery=iminfo $loadaddr && mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
 +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size
-+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size
+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
 +part_default=production
 +part_recovery=recovery
 +reset_factory=eraseenv && reset
+sdmmc_read_emmc_hdr=mmc dev 1 && part start mmc 1 install part_addr && mmc read $loadaddr $part_addr 0x40
+sdmmc_read_emmc_bl2=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x400 && mmc read $loadaddr $offset 0x400
+sdmmc_read_emmc_bl3=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x1000 && mmc read $loadaddr $offset 0x1000
+sdmmc_read_production=mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_read_vol
+sdmmc_read_recovery=mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_read_vol
+sdmmc_read_snand_bl2=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x2000 && mmc read $loadaddr $offset 0x400
+sdmmc_read_snand_fip=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x2400 && mmc read $loadaddr $offset 0x1000
+sdmmc_write_production=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_write_vol
+sdmmc_write_recovery=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol
+snand_write_fip=mtd erase fip && mtd write fip $loadaddr
+snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
+ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3
+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
+ubi_init=run ubi_init_bl && ubi detach && mtd erase ubi && ubi part ubi && run ubi_create_env && run ubi_init_openwrt
+ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
+ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run snand_write_fip
+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
+ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
 +_firstboot=setenv _firstboot ; led bpi-r64:pio:blue on ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
@ -404,3 +438,204 @@
 +_firstboot=setenv _firstboot ; led bpi-r64:pio:blue on ; run _switch_to_menu ; run _init_env ; run boot_first
 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       [33m$ver[0m"
+--- /dev/null
+++ b/configs/mt7622_bananapi_bpi-r64-snand_defconfig
+@@ -0,0 +1,138 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-snand_env"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_BOOTDELAY=30
+CONFIG_AUTOBOOT_MENU_SHOW=y
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7622-bananapi-bpi-r64.dtb"
+CONFIG_SYS_PROMPT="MT7622> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_ENV_READMEM=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LINK_LOCAL=y
+# CONFIG_CMD_MBR is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_TFTPBOOT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_PART=y
+# CONFIG_CMD_PSTORE is not set
+CONFIG_CMD_RARP=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_UUID=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DM_MMC=y
+CONFIG_DM_MTD=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_USB=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_UBI_VOLUME="ubootenv"
+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_NETCONSOLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PCI=y
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)"
+CONFIG_DM_PCI=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7622=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_MMC=y
+CONFIG_MMC_DEFAULT_DEV=1
+CONFIG_MMC_MTK=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_MTK=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_RANDOM_UUID=y
+CONFIG_REGEX=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+--- /dev/null
+++ b/bananapi_bpi-r64-snand_env
+@@ -0,0 +1,57 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x4007ff28
+bootargs=root=/dev/ubiblock0_2p1
+bootcmd=run boot_ubi
+bootconf=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1
+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata
+bootdelay=0
+bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb
+bootfile_upg=openwrt-mediatek-mt7622-bananapi_bpi-r64-squashfs-sysupgrade.itb
+bootfile_fip=openwrt-mediatek-mt7622-bananapi_bpi-r64-snand-bl31-uboot.fip
+bootfile_bl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-snand-preloader.bin
+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
+bootmenu_default=0
+bootmenu_delay=0
+bootmenu_title=      [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) )  [0;36m[SPI-NAND][0m
+bootmenu_0=Initialize environment.=run _firstboot
+bootmenu_0d=Run default boot command.=run boot_default
+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
+bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
+bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
+bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; run boot_tftp_production ; setenv noboot ; run bootmenu_confirm_return
+bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; run boot_tftp_recovery ; setenv noboot ; run bootmenu_confirm_return
+bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
+bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
+bootmenu_8=Reboot.=reset
+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
+boot_default=run bootcmd ; run boot_recovery ; run boot_tftp_forever
+boot_first=if button reset ; then run boot_tftp_forever ; fi ; bootmenu
+boot_production=led bpi-r64:pio:green on ; run ubi_read_production && bootm $loadaddr#$bootconf
+boot_recovery=led bpi-r64:pio:green off ; run check_recovery
+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
+boot_tftp_forever=led bpi-r64:pio:blue on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
+boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2
+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
+boot_ubi=ubi part ubi && run boot_production ; run boot_recovery
+boot_write_fip=mtd erase fip && mtd write fip $loadaddr
+boot_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
+check_recovery=run ubi_read_recovery ; if iminfo $loadaddr ; then bootm $loadaddr#$bootconf; else ubi remove recovery ; fi
+check_ubi=ubi part ubi || run ubi_format
+part_default=production
+part_recovery=recovery
+reset_factory=ubi part ubi ; ubi write 0x0 ubootenv 0x0 ; ubi write 0x0 ubootenv2 0x0 ; ubi remove rootfs_data
+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
+ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
+_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3
+_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format
+_firstboot=setenv _firstboot ; led bpi-r64:pio:blue on ; run _switch_to_menu ; run check_ubi ; run _init_env ; run boot_first
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d
--- a/package/boot/uboot-sunxi/Makefile
+++ b/package/boot/uboot-sunxi/Makefile
@ -29,16 +29,18 @@ define U-Boot/a64-olinuxino
  BUILD_SUBTARGET:=cortexa53
  NAME:=Olimex A64-OLinuXino
  BUILD_DEVICES:=olimex_a64-olinuxino
-  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino:arm-trusted-firmware-sunxi
+  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino:arm-trusted-firmware-sunxi-a64
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/a64-olinuxino-emmc
  BUILD_SUBTARGET:=cortexa53
  NAME:=Olimex A64-OLinuXino eMMC
  BUILD_DEVICES:=olimex_a64-olinuxino-emmc
-  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino-emmc:arm-trusted-firmware-sunxi
+  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino-emmc:arm-trusted-firmware-sunxi-a64
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/A10-OLinuXino-Lime
@ -202,6 +204,15 @@ define U-Boot/orangepi_one
  BUILD_DEVICES:=xunlong_orangepi-one
 endef

+define U-Boot/orangepi_one_plus
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Orange Pi One Plus (H6)
+  DEPENDS:=+PACKAGE_u-boot-orangepi_one_plus:arm-trusted-firmware-sunxi-h6
+  BUILD_DEVICES:=xunlong_orangepi-one-plus
+  UENV:=h6
+  ATF:=h6
+endef
+
 define U-Boot/orangepi_pc
  BUILD_SUBTARGET:=cortexa7
  NAME:=Orange Pi PC (H3)
@ -236,8 +247,9 @@ define U-Boot/libretech_all_h3_cc_h5
  BUILD_SUBTARGET:=cortexa53
  NAME:=Libre Computer ALL-H3-CC H5
  BUILD_DEVICES:=libretech_all-h3-cc-h5
-  DEPENDS:=+PACKAGE_u-boot-libretech_all_h3_cc_h5:arm-trusted-firmware-sunxi
+  DEPENDS:=+PACKAGE_u-boot-libretech_all_h3_cc_h5:arm-trusted-firmware-sunxi-a64
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/nanopi_neo_plus2
@ -246,6 +258,7 @@ define U-Boot/nanopi_neo_plus2
  BUILD_DEVICES:=friendlyarm_nanopi-neo-plus2
  DEPENDS:=+PACKAGE_u-boot-nanopi_neo_plus2:arm-trusted-firmware-sunxi
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/nanopi_neo2
@ -254,6 +267,7 @@ define U-Boot/nanopi_neo2
  BUILD_DEVICES:=friendlyarm_nanopi-neo2
  DEPENDS:=+PACKAGE_u-boot-nanopi_neo2:arm-trusted-firmware-sunxi
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/pine64_plus
@ -262,6 +276,7 @@ define U-Boot/pine64_plus
  BUILD_DEVICES:=pine64_pine64-plus
  DEPENDS:=+PACKAGE_u-boot-pine64_plus:arm-trusted-firmware-sunxi
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/bananapi_m2_plus_h3
@ -274,8 +289,9 @@ define U-Boot/sopine_baseboard
  BUILD_SUBTARGET:=cortexa53
  NAME:=Sopine Baseboard
  BUILD_DEVICES:=pine64_sopine-baseboard
-  DEPENDS:=+PACKAGE_u-boot-sopine_baseboard:arm-trusted-firmware-sunxi
+  DEPENDS:=+PACKAGE_u-boot-sopine_baseboard:arm-trusted-firmware-sunxi-a64
  UENV:=a64
+  ATF:=a64
 endef


@ -283,16 +299,18 @@ define U-Boot/orangepi_zero_plus
  BUILD_SUBTARGET:=cortexa53
  NAME:=Xunlong Orange Pi Zero Plus
  BUILD_DEVICES:=xunlong_orangepi-zero-plus
-  DEPENDS:=+PACKAGE_u-boot-orangepi_zero_plus:arm-trusted-firmware-sunxi
+  DEPENDS:=+PACKAGE_u-boot-orangepi_zero_plus:arm-trusted-firmware-sunxi-a64
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/orangepi_pc2
  BUILD_SUBTARGET:=cortexa53
  NAME:=Xunlong Orange Pi PC2
  BUILD_DEVICES:=xunlong_orangepi-pc2
-  DEPENDS:=+PACKAGE_u-boot-orangepi_pc2:arm-trusted-firmware-sunxi
+  DEPENDS:=+PACKAGE_u-boot-orangepi_pc2:arm-trusted-firmware-sunxi-a64
  UENV:=a64
+  ATF:=a64
 endef

 define U-Boot/Bananapi_M2_Ultra
@ -301,6 +319,12 @@ define U-Boot/Bananapi_M2_Ultra
  BUILD_DEVICES:=sinovoip_bananapi-m2-ultra
 endef

+define U-Boot/bananapi_m2_berry
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapi M2 Berry
+  BUILD_DEVICES:=sinovoip_bananapi-m2-berry
+endef
+
 UBOOT_TARGETS := \
 	a64-olinuxino \
 	a64-olinuxino-emmc \
@ -312,6 +336,7 @@ UBOOT_TARGETS := \
 	A20-OLinuXino_MICRO \
 	bananapi_m2_plus_h3 \
 	Bananapi \
+	bananapi_m2_berry \
 	Bananapi_M2_Ultra \
 	Bananapro \
 	Cubieboard \
@ -335,6 +360,7 @@ UBOOT_TARGETS := \
 	orangepi_zero \
 	orangepi_r1 \
 	orangepi_one \
+	orangepi_one_plus \
 	orangepi_pc \
 	orangepi_pc_plus \
 	orangepi_plus \
@ -349,7 +375,7 @@ UBOOT_TARGETS := \
 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes

 UBOOT_MAKE_FLAGS += \
-	BL31=$(STAGING_DIR_IMAGE)/bl31.bin
+	BL31=$(STAGING_DIR_IMAGE)/bl31_sun50i_$(ATF).bin

 define Build/InstallDev
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
--- a/package/boot/uboot-sunxi/uEnv-h6.txt
+++ b/package/boot/uboot-sunxi/uEnv-h6.txt
@ -0,0 +1,7 @@
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd
--- a/package/devel/valgrind/patches/130-mips_fix_soft_float.patch
+++ b/package/devel/valgrind/patches/130-mips_fix_soft_float.patch
@ -0,0 +1,68 @@
+Disable the valgrind helpers which use MIPS floating point operations 
+when floating point support is deactivated in the toolchain.
+
+The fix from this commit is not sufficient any more:
+https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=869fcf2f6739f17b4eff36ec68f8dca826c8afeb
+
+This fixes the following error message when compiling with a GCC 10 MIPS BE 32:
+---------------------------------------------------------
+../VEX/priv/guest_mips_helpers.c: In function 'mips_dirtyhelper_calculate_FCSR_fp32':
+../VEX/priv/guest_mips_helpers.c:640:10: error: the register '$f21' cannot be clobbered in 'asm' for the current target
+  640 |          ASM_VOLATILE_UNARY32_DOUBLE(round.w.d)
+      |          ^
+---------------------------------------------------------
+
+--- a/VEX/priv/guest_mips_helpers.c
+++ b/VEX/priv/guest_mips_helpers.c
+@@ -617,6 +617,7 @@ extern UInt mips_dirtyhelper_calculate_F
+                                                    flt_op inst )
+ {
+    UInt ret = 0;
+#ifndef __mips_soft_float
+ #if defined(__mips__)
+    VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
+    UInt loFsVal, hiFsVal, loFtVal, hiFtVal;
+@@ -699,6 +700,7 @@ extern UInt mips_dirtyhelper_calculate_F
+          break;
+    }
+ #endif
+#endif
+    return ret;
+ }
+ 
+@@ -708,6 +710,7 @@ extern UInt mips_dirtyhelper_calculate_F
+                                                    flt_op inst )
+ {
+    UInt ret = 0;
+#ifndef __mips_soft_float
+ #if defined(__mips__) && ((__mips == 64) ||                                  \
+                           (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)))
+ #if defined(VGA_mips32)
+@@ -860,6 +863,7 @@ extern UInt mips_dirtyhelper_calculate_F
+          break;
+    }
+ #endif
+#endif
+    return ret;
+ }
+ 
+--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
+@@ -1828,6 +1828,7 @@ Bool VG_(machine_get_hwcaps)( void )
+            we are using alternative way to determine FP mode */
+         ULong result = 0;
+ 
+#ifndef __mips_soft_float
+         if (!VG_MINIMAL_SETJMP(env_unsup_insn)) {
+            __asm__ volatile (
+               ".set push\n\t"
+@@ -1845,6 +1846,9 @@ Bool VG_(machine_get_hwcaps)( void )
+ 
+            fpmode = (result != 0x3FF0000000000000ull);
+         }
+#else
+	fpmode = 0;
+#endif
+      }
+ 
+      if (fpmode != 0)
--- a/target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts
+++ b/target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts
@ -47,3 +47,11 @@
 &usb_phy0 {
 	status = "okay";
 };
+
+&usb1 {
+	status = "okay";
+};
+
+&usb_phy1 {
+	status = "okay";
+};
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@ -76,9 +76,11 @@ define Device/bananapi_bpi-r64
  DEVICE_DTS := mt7622-bananapi-bpi-r64
  DEVICE_DTS_OVERLAY := mt7622-bananapi-bpi-r64-pcie1 mt7622-bananapi-bpi-r64-sata
  DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3 e2fsprogs mkf2fs f2fsck
-  ARTIFACTS := sdcard.img.gz
+  ARTIFACTS := sdcard.img.gz snand-preloader.bin snand-bl31-uboot.fip
  IMAGES := sysupgrade.itb
  KERNEL_INITRAMFS_SUFFIX := -recovery.itb
+  ARTIFACT/snand-preloader.bin	:= bl2 snand-2ddr
+  ARTIFACT/snand-bl31-uboot.fip	:= bl31-uboot bananapi_bpi-r64-snand
  ARTIFACT/sdcard.img.gz	:= mt7622-gpt sdmmc |\
 				   pad-to 512k | bl2 sdmmc-2ddr |\
 				   pad-to 2048k | bl31-uboot bananapi_bpi-r64-sdmmc |\
@ -86,6 +88,8 @@ define Device/bananapi_bpi-r64
 				   pad-to 38912k | mt7622-gpt emmc |\
 				   pad-to 39424k | bl2 emmc-2ddr |\
 				   pad-to 40960k | bl31-uboot bananapi_bpi-r64-emmc |\
+				   pad-to 43008k | bl2 snand-2ddr |\
+				   pad-to 43520k | bl31-uboot bananapi_bpi-r64-snand |\
 				   pad-to 46080k | append-image squashfs-sysupgrade.itb | gzip
  KERNEL			:= kernel-bin | gzip
  KERNEL_INITRAMFS		:= kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd | pad-to 128k
--- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
@ -10,16 +10,24 @@ platform_do_upgrade() {
 	bananapi,bpi-r64)
 		export_bootdevice
 		export_partdevice rootdev 0
-		local fitpart=$(get_partition_by_name $rootdev "production")
-		[ "$fitpart" ] || return 1
-		dd if=/dev/zero of=/dev/$fitpart bs=4096 count=1 2>/dev/null
-		blockdev --rereadpt /dev/$rootdev
-		get_image "$1" | dd of=/dev/$fitpart
-		blockdev --rereadpt /dev/$rootdev
-		local datapart=$(get_partition_by_name $rootdev "rootfs_data")
-		[ "$datapart" ] || return 0
-		dd if=/dev/zero of=/dev/$datapart bs=4096 count=1 2>/dev/null
-		echo $datapart > /tmp/sysupgrade.datapart
+		case "$rootdev" in
+		mmc*)
+			local fitpart=$(get_partition_by_name $rootdev "production")
+			[ "$fitpart" ] || return 1
+			dd if=/dev/zero of=/dev/$fitpart bs=4096 count=1 2>/dev/null
+			blockdev --rereadpt /dev/$rootdev
+			get_image "$1" | dd of=/dev/$fitpart
+			blockdev --rereadpt /dev/$rootdev
+			local datapart=$(get_partition_by_name $rootdev "rootfs_data")
+			[ "$datapart" ] || return 0
+			dd if=/dev/zero of=/dev/$datapart bs=4096 count=1 2>/dev/null
+			echo $datapart > /tmp/sysupgrade.datapart
+			;;
+		*)
+			CI_KERNPART="fit"
+			nand_do_upgrade "$1"
+			;;
+		esac
 		;;
 	buffalo,wsr-2533dhp2)
 		local magic="$(get_magic_long "$1")"
@ -87,7 +95,11 @@ platform_copy_config_mmc() {
 platform_copy_config() {
 	case "$(board_name)" in
 	bananapi,bpi-r64)
-		platform_copy_config_mmc
+		export_bootdevice
+		export_partdevice rootdev 0
+		if echo $rootdev | grep -q mmc; then
+			platform_copy_config_mmc
+		fi
 		;;
 	esac
 }
--- a/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch
+++ b/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch
@ -0,0 +1,57 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts	2021-03-13 13:46:37.057936814 +0200
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts	2021-03-13 13:49:26.957481217 +0200
+@@ -114,7 +114,7 @@
+ };
+ 
+ &bch {
+-	status = "disabled";
+	status = "okay";
+ };
+ 
+ &btif {
+@@ -259,14 +259,40 @@
+ 	status = "disabled";
+ };
+ 
+-&nor_flash {
+&snfi {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&spi_nor_pins>;
+-	status = "disabled";
+	pinctrl-0 = <&serial_nand_pins>;
+	status = "okay";
+ 
+-	flash@0 {
+-		compatible = "jedec,spi-nor";
+	snand: spi_nand@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <104000000>;
+ 		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x0 0x80000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "fip";
+				reg = <0x80000 0x200000>;
+				read-only;
+			};
+
+			partition@280000 {
+				label = "ubi";
+				reg = <0x280000 0x7d80000>;
+			};
+		};
+ 	};
+ };
+ 
--- a/target/linux/mediatek/patches-5.4/115-dts-bpi64-add-snand-support.patch
+++ b/target/linux/mediatek/patches-5.4/115-dts-bpi64-add-snand-support.patch
@ -0,0 +1,57 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts	2021-03-13 13:46:37.057936814 +0200
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts	2021-03-13 13:49:26.957481217 +0200
+@@ -114,7 +114,7 @@
+ };
+ 
+ &bch {
+-	status = "disabled";
+	status = "okay";
+ };
+ 
+ &btif {
+@@ -259,14 +259,40 @@
+ 	status = "disabled";
+ };
+ 
+-&nor_flash {
+&snfi {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&spi_nor_pins>;
+-	status = "disabled";
+	pinctrl-0 = <&serial_nand_pins>;
+	status = "okay";
+ 
+-	flash@0 {
+-		compatible = "jedec,spi-nor";
+	snand: spi_nand@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <104000000>;
+ 		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x0 0x80000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "fip";
+				reg = <0x80000 0x200000>;
+				read-only;
+			};
+
+			partition@280000 {
+				label = "ubi";
+				reg = <0x280000 0x7d80000>;
+			};
+		};
+ 	};
+ };
+ 
--- a/target/linux/sunxi/image/cortexa53.mk
+++ b/target/linux/sunxi/image/cortexa53.mk
@ -9,13 +9,18 @@ define Device/sun50i
  KERNEL := kernel-bin
 endef

+define Device/sun50i-a64
+  SOC := sun50i-a64
+  $(Device/sun50i)
+endef
+
 define Device/sun50i-h5
  SOC := sun50i-h5
  $(Device/sun50i)
 endef

-define Device/sun50i-a64
-  SOC := sun50i-a64
+define Device/sun50i-h6
+  SOC := sun50i-h6
  $(Device/sun50i)
 endef

@ -79,6 +84,14 @@ define Device/pine64_sopine-baseboard
 endef
 TARGET_DEVICES += pine64_sopine-baseboard

+define Device/xunlong_orangepi-one-plus
+  $(Device/sun50i-h6)
+  DEVICE_VENDOR := Xunlong
+  DEVICE_MODEL := Orange Pi One Plus
+  SUNXI_DTS_DIR := allwinner/
+endef
+TARGET_DEVICES += xunlong_orangepi-one-plus
+
 define Device/xunlong_orangepi-pc2
  DEVICE_VENDOR := Xunlong
  DEVICE_MODEL := Orange Pi PC 2
--- a/target/linux/sunxi/image/cortexa7.mk
+++ b/target/linux/sunxi/image/cortexa7.mk
@ -77,6 +77,16 @@ define Device/lemaker_bananapi
 endef
 TARGET_DEVICES += lemaker_bananapi

+define Device/sinovoip_bananapi-m2-berry
+  DEVICE_VENDOR := Sinovoip
+  DEVICE_MODEL := Banana Pi M2 Berry
+  DEVICE_PACKAGES:=kmod-rtc-sunxi kmod-ata-sunxi kmod-brcmfmac \
+	brcmfmac-firmware-43430-sdio wpad-basic-wolfssl
+  SUPPORTED_DEVICES:=lemaker,bananapi-m2-berry
+  SOC := sun8i-v40
+endef
+TARGET_DEVICES += sinovoip_bananapi-m2-berry
+
 define Device/sinovoip_bananapi-m2-ultra
  DEVICE_VENDOR := Sinovoip
  DEVICE_MODEL := Banana Pi M2 Ultra
--- a/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch
+++ b/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch
@ -0,0 +1,400 @@
+diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
+index 581d23287333..487899d4cc3f 100644
+--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
+@@ -16,6 +16,7 @@
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/pwm.h>
+#include <linux/reset.h>
+ #include <linux/slab.h>
+ #include <linux/spinlock.h>
+ #include <linux/time.h>
+@@ -78,6 +79,7 @@ struct sun4i_pwm_data {
+ struct sun4i_pwm_chip {
+ 	struct pwm_chip chip;
+ 	struct clk *clk;
+	struct reset_control *rst;
+ 	void __iomem *base;
+ 	spinlock_t ctrl_lock;
+ 	const struct sun4i_pwm_data *data;
+@@ -364,6 +366,22 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
+ 	if (IS_ERR(pwm->clk))
+ 		return PTR_ERR(pwm->clk);
+ 
+	pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+	if (IS_ERR(pwm->rst)) {
+		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "get reset failed %pe\n",
+				pwm->rst);
+		return PTR_ERR(pwm->rst);
+	}
+
+	/* Deassert reset */
+	ret = reset_control_deassert(pwm->rst);
+	if (ret) {
+		dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
+			ERR_PTR(ret));
+		return ret;
+	}
+
+ 	pwm->chip.dev = &pdev->dev;
+ 	pwm->chip.ops = &sun4i_pwm_ops;
+ 	pwm->chip.base = -1;
+@@ -376,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
+ 	ret = pwmchip_add(&pwm->chip);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
+-		return ret;
+		goto err_pwm_add;
+ 	}
+ 
+ 	platform_set_drvdata(pdev, pwm);
+ 
+ 	return 0;
+
+err_pwm_add:
+	reset_control_assert(pwm->rst);
+
+	return ret;
+ }
+ 
+ static int sun4i_pwm_remove(struct platform_device *pdev)
+ {
+ 	struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = pwmchip_remove(&pwm->chip);
+	if (ret)
+		return ret;
+
+	reset_control_assert(pwm->rst);
+ 
+-	return pwmchip_remove(&pwm->chip);
+	return 0;
+ }
+ 
+ static struct platform_driver sun4i_pwm_driver = {
+
+diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
+index 487899d4cc3f..80026167044b 100644
+--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
+@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
+ 	if (IS_ERR(pwm->base))
+ 		return PTR_ERR(pwm->base);
+ 
+-	pwm->clk = devm_clk_get(&pdev->dev, NULL);
+-	if (IS_ERR(pwm->clk))
+	/*
+	 * All hardware variants need a source clock that is divided and
+	 * then feeds the counter that defines the output wave form. In the
+	 * device tree this clock is either unnamed or called "mod".
+	 * Some variants (e.g. H6) need another clock to access the
+	 * hardware registers; this is called "bus".
+	 * So we request "mod" first (and ignore the corner case that a
+	 * parent provides a "mod" clock while the right one would be the
+	 * unnamed one of the PWM device) and if this is not found we fall
+	 * back to the first clock of the PWM.
+	 */
+	pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+	if (IS_ERR(pwm->clk)) {
+		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "get mod clock failed %pe\n",
+				pwm->clk);
+ 		return PTR_ERR(pwm->clk);
+	}
+
+	if (!pwm->clk) {
+		pwm->clk = devm_clk_get(&pdev->dev, NULL);
+		if (IS_ERR(pwm->clk)) {
+			if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+				dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
+					pwm->clk);
+			return PTR_ERR(pwm->clk);
+		}
+	}
+ 
+ 	pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+ 	if (IS_ERR(pwm->rst)) {
+
+diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
+index 80026167044b..a6727dd89e28 100644
+--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
+@@ -78,6 +78,7 @@ struct sun4i_pwm_data {
+ 
+ struct sun4i_pwm_chip {
+ 	struct pwm_chip chip;
+	struct clk *bus_clk;
+ 	struct clk *clk;
+ 	struct reset_control *rst;
+ 	void __iomem *base;
+@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
+	pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+	if (IS_ERR(pwm->bus_clk)) {
+		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "get bus clock failed %pe\n",
+				pwm->bus_clk);
+		return PTR_ERR(pwm->bus_clk);
+	}
+
+ 	pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+ 	if (IS_ERR(pwm->rst)) {
+ 		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+@@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+	/*
+	 * We're keeping the bus clock on for the sake of simplicity.
+	 * Actually it only needs to be on for hardware register accesses.
+	 */
+	ret = clk_prepare_enable(pwm->bus_clk);
+	if (ret) {
+		dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
+			ERR_PTR(ret));
+		goto err_bus;
+	}
+
+ 	pwm->chip.dev = &pdev->dev;
+ 	pwm->chip.ops = &sun4i_pwm_ops;
+ 	pwm->chip.base = -1;
+@@ -427,6 +447,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
+ 	return 0;
+ 
+ err_pwm_add:
+	clk_disable_unprepare(pwm->bus_clk);
+err_bus:
+ 	reset_control_assert(pwm->rst);
+ 
+ 	return ret;
+@@ -441,6 +463,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
+	clk_disable_unprepare(pwm->bus_clk);
+ 	reset_control_assert(pwm->rst);
+ 
+ 	return 0;
+
+diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
+index a6727dd89e28..e369b5a398f4 100644
+--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
+@@ -202,9 +202,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ {
+ 	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
+ 	struct pwm_state cstate;
+-	u32 ctrl;
+	u32 ctrl, duty, period, val;
+ 	int ret;
+-	unsigned int delay_us;
+	unsigned int delay_us, prescaler;
+ 	unsigned long now;
+ 
+ 	pwm_get_state(pwm, &cstate);
+@@ -220,43 +220,37 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	spin_lock(&sun4i_pwm->ctrl_lock);
+ 	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ 
+-	if ((cstate.period != state->period) ||
+-	    (cstate.duty_cycle != state->duty_cycle)) {
+-		u32 period, duty, val;
+-		unsigned int prescaler;
+-
+-		ret = sun4i_pwm_calculate(sun4i_pwm, state,
+-					  &duty, &period, &prescaler);
+-		if (ret) {
+-			dev_err(chip->dev, "period exceeds the maximum value\n");
+-			spin_unlock(&sun4i_pwm->ctrl_lock);
+-			if (!cstate.enabled)
+-				clk_disable_unprepare(sun4i_pwm->clk);
+-			return ret;
+-		}
+-
+-		if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
+-			/* Prescaler changed, the clock has to be gated */
+-			ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+-			sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
+	if (ret) {
+		dev_err(chip->dev, "period exceeds the maximum value\n");
+		spin_unlock(&sun4i_pwm->ctrl_lock);
+		if (!cstate.enabled)
+			clk_disable_unprepare(sun4i_pwm->clk);
+		return ret;
+	}
+ 
+-			ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
+-			ctrl |= BIT_CH(prescaler, pwm->hwpwm);
+-		}
+	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
+		/* Prescaler changed, the clock has to be gated */
+		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+		sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ 
+-		val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
+-		sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
+-		sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
+-			usecs_to_jiffies(cstate.period / 1000 + 1);
+-		sun4i_pwm->needs_delay[pwm->hwpwm] = true;
+		ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
+		ctrl |= BIT_CH(prescaler, pwm->hwpwm);
+ 	}
+ 
+	val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
+	sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
+	sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
+		usecs_to_jiffies(cstate.period / 1000 + 1);
+	sun4i_pwm->needs_delay[pwm->hwpwm] = true;
+
+ 	if (state->polarity != PWM_POLARITY_NORMAL)
+ 		ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
+ 	else
+ 		ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
+ 
+ 	ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+
+ 	if (state->enabled) {
+ 		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
+ 	} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
+
+diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
+index e369b5a398f4..07bf7be6074b 100644
+--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
+@@ -3,6 +3,10 @@
+  * Driver for Allwinner sun4i Pulse Width Modulation Controller
+  *
+  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * Limitations:
+ * - When outputing the source clock directly, the PWM logic will be bypassed
+ *   and the currently running period is not guaranteed to be completed
+  */
+ 
+ #include <linux/bitops.h>
+@@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
+ 
+ struct sun4i_pwm_data {
+ 	bool has_prescaler_bypass;
+	bool has_direct_mod_clk_output;
+ 	unsigned int npwm;
+ };
+ 
+@@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
+ 
+ 	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ 
+	/*
+	 * PWM chapter in H6 manual has a diagram which explains that if bypass
+	 * bit is set, no other setting has any meaning. Even more, experiment
+	 * proved that also enable bit is ignored in this case.
+	 */
+	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
+	    sun4i_pwm->data->has_direct_mod_clk_output) {
+		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
+		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
+		state->polarity = PWM_POLARITY_NORMAL;
+		state->enabled = true;
+		return;
+	}
+
+ 	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
+ 	    sun4i_pwm->data->has_prescaler_bypass)
+ 		prescaler = 1;
+@@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
+ 
+ static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
+ 			       const struct pwm_state *state,
+-			       u32 *dty, u32 *prd, unsigned int *prsclr)
+			       u32 *dty, u32 *prd, unsigned int *prsclr,
+			       bool *bypass)
+ {
+ 	u64 clk_rate, div = 0;
+ 	unsigned int pval, prescaler = 0;
+ 
+ 	clk_rate = clk_get_rate(sun4i_pwm->clk);
+ 
+	*bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
+		  state->enabled &&
+		  (state->period * clk_rate >= NSEC_PER_SEC) &&
+		  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
+		  (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
+
+	/* Skip calculation of other parameters if we bypass them */
+	if (*bypass)
+		return 0;
+
+ 	if (sun4i_pwm->data->has_prescaler_bypass) {
+ 		/* First, test without any prescaler when available */
+ 		prescaler = PWM_PRESCAL_MASK;
+@@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	int ret;
+ 	unsigned int delay_us, prescaler;
+ 	unsigned long now;
+	bool bypass;
+ 
+ 	pwm_get_state(pwm, &cstate);
+ 
+@@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 	spin_lock(&sun4i_pwm->ctrl_lock);
+ 	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ 
+-	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
+	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
+				  &bypass);
+ 	if (ret) {
+ 		dev_err(chip->dev, "period exceeds the maximum value\n");
+ 		spin_unlock(&sun4i_pwm->ctrl_lock);
+@@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ 		return ret;
+ 	}
+ 
+	if (sun4i_pwm->data->has_direct_mod_clk_output) {
+		if (bypass) {
+			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+			/* We can skip other parameter */
+			sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+			spin_unlock(&sun4i_pwm->ctrl_lock);
+			return 0;
+		} else {
+			ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+		}
+	}
+
+ 	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
+ 		/* Prescaler changed, the clock has to be gated */
+ 		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+
+diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
+index 07bf7be6074b..c394878c7e5d 100644
+--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
+@@ -360,6 +360,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
+ 	.npwm = 1,
+ };
+ 
+static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
+	.has_prescaler_bypass = true,
+	.has_direct_mod_clk_output = true,
+	.npwm = 2,
+};
+
+ static const struct of_device_id sun4i_pwm_dt_ids[] = {
+ 	{
+ 		.compatible = "allwinner,sun4i-a10-pwm",
+@@ -376,6 +382,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
+ 	}, {
+ 		.compatible = "allwinner,sun8i-h3-pwm",
+ 		.data = &sun4i_pwm_single_bypass,
+	}, {
+		.compatible = "allwinner,sun50i-h6-pwm",
+		.data = &sun50i_h6_pwm_data,
+ 	}, {
+ 		/* sentinel */
+ 	},
--- a/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch
+++ b/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch
@ -0,0 +1,37 @@
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+
+Allwinner H6 PWM is similar to that in A20 except that it has additional
+bus clock and reset line.
+
+Note that first PWM channel is connected to output pin and second
+channel is used internally, as a clock source to AC200 co-packaged chip.
+This means that any combination of these two channels can be used and
+thus it doesn't make sense to add pinctrl nodes at this point.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Clément Péron <peron.clem@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 29824081b43b..6d4bde488f15 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -245,6 +245,16 @@
+ 			status = "disabled";
+ 		};
+ 
+		pwm: pwm@300a000 {
+			compatible = "allwinner,sun50i-h6-pwm";
+			reg = <0x0300a000 0x400>;
+			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+			clock-names = "mod", "bus";
+			resets = <&ccu RST_BUS_PWM>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+ 		pio: pinctrl@300b000 {
+ 			compatible = "allwinner,sun50i-h6-pinctrl";
+ 			reg = <0x0300b000 0x400>;
--- a/target/linux/sunxi/patches-5.4/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
+++ b/target/linux/sunxi/patches-5.4/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
@ -0,0 +1,12 @@
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+index f335f7482a73..cf684bc7374d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+@@ -45,3 +45,7 @@
+ 		reg = <1>;
+ 	};
+ };
+
+&pwm {
+	status = "okay";
+};
--- a/target/linux/sunxi/patches-5.4/443-board-h6-orangepioneplus-fix-missing-ethernet.patch
+++ b/target/linux/sunxi/patches-5.4/443-board-h6-orangepioneplus-fix-missing-ethernet.patch
@ -0,0 +1,44 @@
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+index 12e1756..79139f3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+@@ -9,4 +9,39 @@
+ / {
+ 	model = "OrangePi One Plus";
+ 	compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &emac;
+	};
+
+	reg_gmac_3v3: gmac-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc-gmac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <100000>;
+                enable-active-high;
+                gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+                vin-supply = <&reg_aldo2>;
+        };
+};
+
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ext_rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-handle = <&ext_rgmii_phy>;
+	phy-supply = <&reg_gmac_3v3>;
+	allwinner,rx-delay-ps = <200>;
+	allwinner,tx-delay-ps = <200>;
+	status = "okay";
+};
+
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+ };
--- a/toolchain/gcc/Config.version
+++ b/toolchain/gcc/Config.version
@ -14,7 +14,7 @@ config GCC_VERSION
 	string
 	default "7.5.0"		if GCC_VERSION_7
 	default "9.3.0"		if GCC_VERSION_9
-	default "10.2.0"	if GCC_VERSION_10
+	default "10.3.0"	if GCC_VERSION_10
 	default "8.4.0"

 config GCC_USE_IREMAP
--- a/toolchain/gcc/common.mk
+++ b/toolchain/gcc/common.mk
@ -40,8 +40,8 @@ ifeq ($(PKG_VERSION),9.3.0)
  PKG_HASH:=71e197867611f6054aa1119b13a0c0abac12834765fe2d81f35ac57f84f742d1
 endif

-ifeq ($(PKG_VERSION),10.2.0)
-  PKG_HASH:=b8dd4368bb9c7f0b98188317ee0254dd8cc99d1e3a18d0ff146c855fe16c1d8c
+ifeq ($(PKG_VERSION),10.3.0)
+  PKG_HASH:=64f404c1a650f27fc33da242e1f2df54952e3963a49e06e73f6940f3223ac344
 endif

 PATCH_DIR=../patches/$(GCC_VERSION)
--- a/toolchain/gcc/patches/10.3.0/002-case_insensitive.patch
+++ b/toolchain/gcc/patches/10.3.0/002-case_insensitive.patch
--- a/toolchain/gcc/patches/10.3.0/010-documentation.patch
+++ b/toolchain/gcc/patches/10.3.0/010-documentation.patch
--- a/toolchain/gcc/patches/10.3.0/110-Fix-MIPS-PR-84790.patch
+++ b/toolchain/gcc/patches/10.3.0/110-Fix-MIPS-PR-84790.patch
--- a/toolchain/gcc/patches/10.3.0/230-musl_libssp.patch
+++ b/toolchain/gcc/patches/10.3.0/230-musl_libssp.patch
--- a/toolchain/gcc/patches/10.3.0/300-mips_Os_cpu_rtx_cost_model.patch
+++ b/toolchain/gcc/patches/10.3.0/300-mips_Os_cpu_rtx_cost_model.patch
--- a/toolchain/gcc/patches/10.3.0/810-arm-softfloat-libgcc.patch
+++ b/toolchain/gcc/patches/10.3.0/810-arm-softfloat-libgcc.patch
--- a/toolchain/gcc/patches/10.3.0/820-libgcc_pic.patch
+++ b/toolchain/gcc/patches/10.3.0/820-libgcc_pic.patch
--- a/toolchain/gcc/patches/10.3.0/840-armv4_pass_fix-v4bx_to_ld.patch
+++ b/toolchain/gcc/patches/10.3.0/840-armv4_pass_fix-v4bx_to_ld.patch
--- a/toolchain/gcc/patches/10.3.0/850-use_shared_libgcc.patch
+++ b/toolchain/gcc/patches/10.3.0/850-use_shared_libgcc.patch
--- a/toolchain/gcc/patches/10.3.0/851-libgcc_no_compat.patch
+++ b/toolchain/gcc/patches/10.3.0/851-libgcc_no_compat.patch
--- a/toolchain/gcc/patches/10.3.0/870-ppc_no_crtsavres.patch
+++ b/toolchain/gcc/patches/10.3.0/870-ppc_no_crtsavres.patch
--- a/toolchain/gcc/patches/10.3.0/881-no_tm_section.patch
+++ b/toolchain/gcc/patches/10.3.0/881-no_tm_section.patch
--- a/toolchain/gcc/patches/10.3.0/900-bad-mips16-crt.patch
+++ b/toolchain/gcc/patches/10.3.0/900-bad-mips16-crt.patch
--- a/toolchain/gcc/patches/10.3.0/910-mbsd_multi.patch
+++ b/toolchain/gcc/patches/10.3.0/910-mbsd_multi.patch
@ -102,7 +102,7 @@ Date:   Tue Jul 31 00:52:27 2007 +0000
 Assume normal C execution environment.
 --- a/gcc/common.opt
 +++ b/gcc/common.opt
-@@ -1657,6 +1657,9 @@ fguess-branch-probability
+@@ -1660,6 +1660,9 @@ fguess-branch-probability
 Common Report Var(flag_guess_branch_prob) Optimization
 Enable guessing of branch probabilities.
 
@ -114,7 +114,7 @@ Date:   Tue Jul 31 00:52:27 2007 +0000
 ; On SVR4 targets, it also controls whether or not to emit a
 --- a/gcc/doc/invoke.texi
 +++ b/gcc/doc/invoke.texi
-@@ -8169,6 +8169,17 @@ This option is only supported for C and
+@@ -8171,6 +8171,17 @@ This option is only supported for C and
 @option{-Wall} and by @option{-Wpedantic}, which can be disabled with
 @option{-Wno-pointer-sign}.
 
@ -134,7 +134,7 @@ Date:   Tue Jul 31 00:52:27 2007 +0000
 @opindex Wno-stack-protector
 --- a/gcc/opts.c
 +++ b/gcc/opts.c
-@@ -2308,6 +2308,9 @@ common_handle_option (struct gcc_options
+@@ -2318,6 +2318,9 @@ common_handle_option (struct gcc_options
       /* Currently handled in a prescan.  */
       break;
 
--- a/toolchain/gcc/patches/10.3.0/920-specs_nonfatal_getenv.patch
+++ b/toolchain/gcc/patches/10.3.0/920-specs_nonfatal_getenv.patch
--- a/toolchain/gcc/patches/10.3.0/930-fix-mips-noexecstack.patch
+++ b/toolchain/gcc/patches/10.3.0/930-fix-mips-noexecstack.patch
--- a/toolchain/gcc/patches/10.3.0/931-libffi-fix-MIPS-softfloat-build-issue.patch
+++ b/toolchain/gcc/patches/10.3.0/931-libffi-fix-MIPS-softfloat-build-issue.patch
--- a/toolchain/gcc/patches/10.3.0/960-gotools-fix-compilation-when-making-cross-compiler.patch
+++ b/toolchain/gcc/patches/10.3.0/960-gotools-fix-compilation-when-making-cross-compiler.patch