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sunxi: backport h5 cpufreq support from upstream linux

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This commit is contained in:
AmadeusGhost 2021-02-10 12:20:21 +08:00
parent dcb54c420b
commit ecd317d8f4
10 changed files with 237 additions and 286 deletions
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66
target/linux/sunxi/patches-4.19/023-arm64-dts-allwinner-h5-Add-PMU-node.patch Normal file
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@ -0,0 +1,66 @@
From c35a516a46187c8eeb7a56c64505ec6f7e22a0c7 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Thu, 21 Nov 2019 01:18:34 +0000
Subject: [PATCH] arm64: dts: allwinner: H5: Add PMU node
Add the Performance Monitoring Unit (PMU) device tree node to the H5
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core.
As with the A64, the interrupt numbers from the manual were wrong (off
by 4), the actual SPI IDs have been gathered in U-Boot, and were
verified with perf in Linux.
Tested with perf record and taskset on an OrangePi PC2.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index e92c4de5bf3b4..7c775a918a4e7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -54,21 +54,21 @@
enable-method = "psci";
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
@@ -76,6 +76,16 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu",
+ "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";

21
target/linux/sunxi/patches-4.19/023-cpufreq-dt-platdev-Add-allwinner-sun50i-h5-compatible.patch
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@ -1,21 +0,0 @@
From 1d78fb6bf60b011bd60ebc9d6ef9499f91c29267 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 12:58:43 +0200
Subject: [PATCH 08/82] cpufreq: dt-platdev: Add allwinner,sun50i-h5 compatible
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57de6ca..afb511aa5050 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -29,6 +29,7 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "allwinner,sun8i-a23", },
{ .compatible = "allwinner,sun8i-a83t", },
{ .compatible = "allwinner,sun8i-h3", },
+ { .compatible = "allwinner,sun50i-h5", },
{ .compatible = "apm,xgene-shadowcat", },

56
target/linux/sunxi/patches-4.19/024-arm64-dts-allwinner-h5-Add-clock-to-CPU-cores.patch Normal file
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@ -0,0 +1,56 @@
From 5fa21c1354c93cb9fe8239545b17eee46e39dd69 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sat, 18 Jul 2020 00:00:49 +0800
Subject: [PATCH] arm64: dts: allwinner: h5: Add clock to CPU cores
The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-5-wens@kernel.org
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 4462a68c06815..09523f6011c5e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu1: cpu@1 {
@@ -59,6 +61,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu2: cpu@2 {
@@ -66,6 +70,8 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
cpu3: cpu@3 {
@@ -73,6 +79,8 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
};

113
target/linux/sunxi/patches-4.19/025-arm64-dts-allwinner-h5-Add-CPU-OPP-table.patch Normal file
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@ -0,0 +1,113 @@
From 7240598ba4e6c477c6809dc019505cf366fdb7c0 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sat, 18 Jul 2020 00:00:51 +0800
Subject: [PATCH] arm64: dts: allwinner: h5: Add CPU Operating Performance
Points table
Add an OPP (Operating Performance Points) table for the CPU cores for
boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the
H5. The table originates from Armbian, but the maximum voltage is raised
slightly to account for boards using slightly higher voltages.
The table and tie in to the CPU cores are put in a separate dtsi file
that board files can include to opt in. Or they can define their own
tables if the standard one does not fit.
This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi
M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V
regulator, while the latter has a GPIO controlled regulator switchable
between 1.1V and 1.3V.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-7-wens@kernel.org
---
.../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
new file mode 100644
index 0000000000000..b2657201957eb
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <1000000 1000000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1080000 1080000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <1120000 1120000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1160000 1160000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1240000 1240000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1260000 1260000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-microvolt = <1300000 1300000 1310000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};

3
target/linux/sunxi/patches-4.19/103-sunxi-h5-add-support-for-nanopi-r1s-h5.patch
View File

@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
@@ -0,0 +1,216 @@
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 AmadeusGhost <amadeus@jmu.edu.cn>
@ -21,6 +21,7 @@
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>

48
target/linux/sunxi/patches-4.19/321-ARM-dts-sun8i-h3-Add-clock-frequency.patch
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@ -1,48 +0,0 @@
From 0d1194aaf2b2ebc571cf01d2353d252c12146d2e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 27 Jun 2016 16:08:26 +0200
Subject: [PATCH 10/82] ARM: dts: sun8i-h3: Add clock-frequency
To avoid error messages during boot.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index f0096074a467..cb19ff797606 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -78,6 +78,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu1: cpu@1 {
@@ -88,6 +89,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu2: cpu@2 {
@@ -98,6 +100,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu3: cpu@3 {
@@ -108,6 +111,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
};

30
target/linux/sunxi/patches-4.19/322-arm64-dts-sun50i-h5-Add-clock-frequency.patch
View File

@ -1,30 +0,0 @@
From 6328da39df61f962190870089aaa171a7f8aab2c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 13:04:25 +0200
Subject: [PATCH 11/82] arm64: dts: sun50i-h5: Add clock-frequency
To avoid error messages during boot.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 62d646baac3c..4452ab873dec 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -76,6 +76,13 @@
};
};
+ reg_cpu_fallback: reg_cpu_fallback {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpux-dummy";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";

82
target/linux/sunxi/patches-4.19/323-arm-dts-sunxi-h3-h5-Move-CPU-OPP-table-to-dtsi-share.patch
View File

@ -1,82 +0,0 @@
From d4028daf51824eb792fb3c9cc77553ff1edc5d68 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 00:56:50 +0200
Subject: [PATCH 12/82] ARM: dts: sunxi-h3-h5: Move CPU OPP table to dtsi
shared by H3/H5
It is identical for H3 and H5, so it better live there.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 23 -----------------------
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 23 +++++++++++++++++++++++
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index cb19ff797606..261ca0356358 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -43,29 +43,6 @@
#include "sunxi-h3-h5.dtsi"
/ {
- cpu0_opp_table: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-648000000 {
- opp-hz = /bits/ 64 <648000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1100000 1100000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000 1200000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 13fe5e316136..539b69fecbe9 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -105,6 +105,29 @@
};
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000 1100000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
de: display-engine {
compatible = "allwinner,sun8i-h3-display-engine";
allwinner,pipelines = <&mixer0>;

54
target/linux/sunxi/patches-4.19/324-arm-dts-sunxi-h3-h5-Add-more-CPU-OPP-for-H3-H5.patch
View File

@ -1,54 +0,0 @@
From 9e05f3d014b05df39a55dfd6a08d4bd18a301307 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:13:01 +0200
Subject: [PATCH 13/82] ARM: dts: sunxi-h3-h5: Add more CPU OPP for H3/H5
These OPPs can be used with better cooling and/or thermal regulation.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 78 ++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 539b69fecbe9..f47c22b622f9 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -109,6 +109,24 @@
compatible = "operating-points-v2";
opp-shared;
+ opp@120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
opp@648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <1040000 1040000 1300000>;
@@ -121,6 +139,12 @@
clock-latency-ns = <244144>; /* 8 32k periods */
};
+ opp@960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1200000 1200000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000 1200000 1300000>;

50
target/linux/sunxi/patches-4.19/325-arm64-dts-sun50i-h5-Enable-cpufreq-dt-on-H5-CPU.patch
View File

@ -1,50 +0,0 @@
From 25be6ff78bebfd869a3be0017715f101bd75bb64 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:19:06 +0200
Subject: [PATCH 15/82] arm64: dts: sun50i-h5: Enable cpufreq-dt on H5 CPU
Uses OPPs shared with H3.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 60fc84a1fb44..acd90f390e88 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,9 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu@1 {
@@ -59,6 +62,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu@2 {
@@ -66,6 +70,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu@3 {
@@ -73,6 +78,7 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
};
};