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rockchip: backport latest rk3588 patches

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2024-05-04 20:36:34 +08:00
parent 67317ec075
commit f1ac8ecf1b
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GPG Key ID: 6850B6345C862176
10 changed files with 303 additions and 6 deletions
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24
target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch Normal file
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@ -0,0 +1,24 @@
From ca151fd56b5736a7adbdba5675b9d87d70f20b23 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Thu, 28 Mar 2024 04:20:52 +0530
Subject: [PATCH] dt-bindings: reset: Define reset id used for HDMI Receiver
Add reset id used for HDMI Receiver in RK3588 SoCs
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Link: https://lore.kernel.org/r/20240327225057.672304-2-shreeya.patel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 ++
1 file changed, 2 insertions(+)
--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
@@ -751,4 +751,6 @@
#define SRST_P_TRNG_CHK 658
#define SRST_TRNG_S 659
+#define SRST_A_HDMIRX_BIU 660
+
#endif

25
target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch Normal file
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@ -0,0 +1,25 @@
From 7af67019cd78d028ef377df689ac103d51905518 Mon Sep 17 00:00:00 2001
From: Shreeya Patel <shreeya.patel@collabora.com>
Date: Thu, 28 Mar 2024 04:20:53 +0530
Subject: [PATCH] clk: rockchip: rk3588: Add reset line for HDMI Receiver
Export hdmirx_biu reset line required by the Synopsys
DesignWare HDMIRX Controller.
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/rst-rk3588.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/clk/rockchip/rst-rk3588.c
+++ b/drivers/clk/rockchip/rst-rk3588.c
@@ -577,6 +577,7 @@ static const int rk3588_register_offset[
/* SOFTRST_CON59 */
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
+ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),

74
target/linux/rockchip/patches-6.6/050-21-v6.10-arm64-dts-rockchip-add-rk3588-pcie-and-php-IOMMUs.patch Normal file
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@ -0,0 +1,74 @@
From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001
From: Niklas Cassel <cassel@kernel.org>
Date: Thu, 2 May 2024 16:02:32 +0200
Subject: [PATCH] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
The mmu600_pcie is connected with the five PCIe controllers.
The mmu600_php is connected with the USB3 controller, the GMAC
controllers, and the SATA controllers.
See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).
The IOMMUs are disabled by default, as further patches are needed to
program the SID/SSIDs in to the IOMMUs.
iommu: Default domain type: Translated
iommu: DMA domain TLB invalidation policy: strict mode
arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf)
arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq
arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq
arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs
Additionally, the IOMMU correctly triggers an IOMMU fault when
a PCIe device performs a write (since the device hasn't been
assigned a SID/SSID):
arm-smmu-v3 fc900000.iommu: event 0x02 received:
arm-smmu-v3 fc900000.iommu: 0x0000010000000002
arm-smmu-v3 fc900000.iommu: 0x0000000000000000
arm-smmu-v3 fc900000.iommu: 0x0000000000000000
arm-smmu-v3 fc900000.iommu: 0x0000000000000000
While this doesn't provide much value as is, having the devices as
disabled in the device tree will allow developers to see that the rk3588
actually has IOMMUs on the SoC.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -558,6 +558,30 @@
status = "disabled";
};
+ mmu600_pcie: iommu@fc900000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfc900000 0x0 0x200000>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ mmu600_php: iommu@fcb00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfcb00000 0x0 0x200000>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x10000>;

28
target/linux/rockchip/patches-6.6/055-04-v6.10-arm64-dts-rockchip-Enable-GPU-on-Orange-Pi-5.patch Normal file
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@ -0,0 +1,28 @@
From 8beafb228f2be5de03e73178ac1081847d0d411f Mon Sep 17 00:00:00 2001
From: Jimmy Hon <honyuenkwun@gmail.com>
Date: Thu, 25 Apr 2024 17:29:13 -0500
Subject: [PATCH] arm64: dts: rockchip: Enable GPU on Orange Pi 5
Enable the Mali GPU in the Orange Pi 5
Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com>
Link: https://lore.kernel.org/r/20240425222913.1760-1-honyuenkwun@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
@@ -146,6 +146,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;

146
target/linux/rockchip/patches-6.6/055-05-v6.10-arm64-dts-rockchip-add-USB-C-support-to-rk3588s-orangepi-.patch Normal file
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@ -0,0 +1,146 @@
From c57d1a970275aabfbfab4c56001394ada3456d8e Mon Sep 17 00:00:00 2001
From: Jimmy Hon <honyuenkwun@gmail.com>
Date: Wed, 17 Apr 2024 22:52:33 -0500
Subject: [PATCH] arm64: dts: rockchip: add USB-C support to rk3588s-orangepi-5
Add support for using the Orange Pi 5 USB-C port for USB in OHCI, EHCI
or XHCI mode. Displayport AltMode is not yet supported.
Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com>
Link: https://lore.kernel.org/r/20240418035232.35344-2-honyuenkwun@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../boot/dts/rockchip/rk3588s-orangepi-5.dts | 94 +++++++++++++++++++
1 file changed, 94 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
@@ -6,6 +6,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
#include "rk3588s.dtsi"
/ {
@@ -217,6 +218,56 @@
pinctrl-0 = <&i2c6m3_xfer>;
status = "okay";
+ usbc0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus_typec>;
+ status = "okay";
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ op-sink-microwatt = <1000000>;
+ power-role = "dual";
+ sink-pdos =
+ <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "source";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_hs: endpoint {
+ remote-endpoint = <&usb_host0_xhci_drd_sw>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usbc0_ss: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ usbc0_sbu: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_sbu>;
+ };
+ };
+ };
+ };
+ };
+
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
@@ -630,6 +681,14 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -651,6 +710,29 @@
status = "okay";
};
+&usbdp_phy0 {
+ mode-switch;
+ orientation-switch;
+ sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_typec_ss: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_ss>;
+ };
+
+ usbdp_phy0_typec_sbu: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usbc0_sbu>;
+ };
+ };
+};
+
&usb_host0_ehci {
status = "okay";
};
@@ -659,6 +741,18 @@
status = "okay";
};
+&usb_host0_xhci {
+ dr_mode = "otg";
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb_host0_xhci_drd_sw: endpoint {
+ remote-endpoint = <&usbc0_hs>;
+ };
+ };
+};
+
&usb_host1_ehci {
status = "okay";
};

4
target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch
View File

@ -449,7 +449,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
@@ -10,11 +10,16 @@
@@ -11,11 +11,16 @@
/ {
model = "Xunlong Orange Pi 5";
@ -467,7 +467,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
};
chosen {
@@ -40,10 +45,9 @@
@@ -41,10 +46,9 @@
pinctrl-names = "default";
pinctrl-0 =<&leds_gpio>;

2
target/linux/rockchip/patches-6.6/120-01-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling.patch
View File

@ -536,7 +536,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -611,6 +1053,16 @@
@@ -635,6 +1077,16 @@
reg = <0x0 0xfd5ac000 0x0 0x4000>;
};

2
target/linux/rockchip/patches-6.6/120-06-arm64-dts-rockchip-enable-RK3588-tsadc-by-default.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2813,7 +2813,6 @@
@@ -2837,7 +2837,6 @@
pinctrl-1 = <&tsadc_shut>;
pinctrl-names = "gpio", "otpout";
#thermal-sensor-cells = <1>;

2
target/linux/rockchip/patches-6.6/801-05-arm64-dts-rockchip-rk3588s-add-rng-node.patch
View File

@ -11,7 +11,7 @@ Change-Id: Ifb8964053daa6b593dd2c2c6a3b8caab8526e56d
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2228,6 +2228,16 @@
@@ -2252,6 +2252,16 @@
status = "disabled";
};

2
target/linux/rockchip/patches-6.6/801-06-arm64-dts-rockchip-rk3588s-rng-use-scmi_clk.patch
View File

@ -14,7 +14,7 @@ Change-Id: I49994529fcc209c2bc173c1abc497536fb920302
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2232,7 +2232,7 @@
@@ -2256,7 +2256,7 @@
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;