diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1 index cd64ae1c8f..8e7e27d022 100644 --- a/target/linux/rockchip/armv8/config-6.1 +++ b/target/linux/rockchip/armv8/config-6.1 @@ -117,6 +117,7 @@ CONFIG_CLK_RK3328=y CONFIG_CLK_RK3368=y CONFIG_CLK_RK3399=y CONFIG_CLK_RK3568=y +CONFIG_CLK_RK3588=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMA=y CONFIG_CMA_ALIGNMENT=8 @@ -382,7 +383,9 @@ CONFIG_MEMFD_CREATE=y CONFIG_MEMORY_ISOLATION=y CONFIG_MFD_CORE=y # CONFIG_MFD_KHADAS_MCU is not set -CONFIG_MFD_RK808=y +CONFIG_MFD_RK8XX=y +CONFIG_MFD_RK8XX_I2C=y +CONFIG_MFD_RK8XX_SPI=y CONFIG_MFD_SYSCON=y CONFIG_MIGRATION=y CONFIG_MMC=y @@ -545,6 +548,7 @@ CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y CONFIG_REGULATOR=y # CONFIG_REGULATOR_ARM_SCMI is not set CONFIG_REGULATOR_FAN53555=y diff --git a/target/linux/rockchip/patches-6.1/030-01-v6.2-dt-bindings-clock-add-rk3588-clock-definitions.patch b/target/linux/rockchip/patches-6.1/030-01-v6.2-dt-bindings-clock-add-rk3588-clock-definitions.patch new file mode 100644 index 0000000000..1d0d2404b3 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-01-v6.2-dt-bindings-clock-add-rk3588-clock-definitions.patch @@ -0,0 +1,792 @@ +From f204a60e545ccd4bc28939054389690fd194cb5e Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 18 Oct 2022 17:13:59 +0200 +Subject: [PATCH] dt-bindings: clock: add rk3588 clock definitions + +Add clock ID defines for rk3588. + +Compared to the downstream bindings written by Elaine, this uses +continous gapless clock IDs starting at 0. Thus all numbers are +different between downstream and upstream, but I kept exactly the +same names. + +Co-Developed-by: Elaine Zhang +Signed-off-by: Elaine Zhang +Acked-by: Rob Herring +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-2-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ++++++++++++++++++ + 1 file changed, 766 insertions(+) + create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h + +--- /dev/null ++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h +@@ -0,0 +1,766 @@ ++/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2022 Collabora Ltd. ++ * ++ * Author: Elaine Zhang ++ * Author: Sebastian Reichel ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H ++#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H ++ ++/* cru-clocks indices */ ++ ++#define PLL_B0PLL 0 ++#define PLL_B1PLL 1 ++#define PLL_LPLL 2 ++#define PLL_V0PLL 3 ++#define PLL_AUPLL 4 ++#define PLL_CPLL 5 ++#define PLL_GPLL 6 ++#define PLL_NPLL 7 ++#define PLL_PPLL 8 ++#define ARMCLK_L 9 ++#define ARMCLK_B01 10 ++#define ARMCLK_B23 11 ++#define PCLK_BIGCORE0_ROOT 12 ++#define PCLK_BIGCORE0_PVTM 13 ++#define PCLK_BIGCORE1_ROOT 14 ++#define PCLK_BIGCORE1_PVTM 15 ++#define PCLK_DSU_S_ROOT 16 ++#define PCLK_DSU_ROOT 17 ++#define PCLK_DSU_NS_ROOT 18 ++#define PCLK_LITCORE_PVTM 19 ++#define PCLK_DBG 20 ++#define PCLK_DSU 21 ++#define PCLK_S_DAPLITE 22 ++#define PCLK_M_DAPLITE 23 ++#define MBIST_MCLK_PDM1 24 ++#define MBIST_CLK_ACDCDIG 25 ++#define HCLK_I2S2_2CH 26 ++#define HCLK_I2S3_2CH 27 ++#define CLK_I2S2_2CH_SRC 28 ++#define CLK_I2S2_2CH_FRAC 29 ++#define CLK_I2S2_2CH 30 ++#define MCLK_I2S2_2CH 31 ++#define I2S2_2CH_MCLKOUT 32 ++#define CLK_DAC_ACDCDIG 33 ++#define CLK_I2S3_2CH_SRC 34 ++#define CLK_I2S3_2CH_FRAC 35 ++#define CLK_I2S3_2CH 36 ++#define MCLK_I2S3_2CH 37 ++#define I2S3_2CH_MCLKOUT 38 ++#define PCLK_ACDCDIG 39 ++#define HCLK_I2S0_8CH 40 ++#define CLK_I2S0_8CH_TX_SRC 41 ++#define CLK_I2S0_8CH_TX_FRAC 42 ++#define MCLK_I2S0_8CH_TX 43 ++#define CLK_I2S0_8CH_TX 44 ++#define CLK_I2S0_8CH_RX_SRC 45 ++#define CLK_I2S0_8CH_RX_FRAC 46 ++#define MCLK_I2S0_8CH_RX 47 ++#define CLK_I2S0_8CH_RX 48 ++#define I2S0_8CH_MCLKOUT 49 ++#define HCLK_PDM1 50 ++#define MCLK_PDM1 51 ++#define HCLK_AUDIO_ROOT 52 ++#define PCLK_AUDIO_ROOT 53 ++#define HCLK_SPDIF0 54 ++#define CLK_SPDIF0_SRC 55 ++#define CLK_SPDIF0_FRAC 56 ++#define MCLK_SPDIF0 57 ++#define CLK_SPDIF0 58 ++#define CLK_SPDIF1 59 ++#define HCLK_SPDIF1 60 ++#define CLK_SPDIF1_SRC 61 ++#define CLK_SPDIF1_FRAC 62 ++#define MCLK_SPDIF1 63 ++#define ACLK_AV1_ROOT 64 ++#define ACLK_AV1 65 ++#define PCLK_AV1_ROOT 66 ++#define PCLK_AV1 67 ++#define PCLK_MAILBOX0 68 ++#define PCLK_MAILBOX1 69 ++#define PCLK_MAILBOX2 70 ++#define PCLK_PMU2 71 ++#define PCLK_PMUCM0_INTMUX 72 ++#define PCLK_DDRCM0_INTMUX 73 ++#define PCLK_TOP 74 ++#define PCLK_PWM1 75 ++#define CLK_PWM1 76 ++#define CLK_PWM1_CAPTURE 77 ++#define PCLK_PWM2 78 ++#define CLK_PWM2 79 ++#define CLK_PWM2_CAPTURE 80 ++#define PCLK_PWM3 81 ++#define CLK_PWM3 82 ++#define CLK_PWM3_CAPTURE 83 ++#define PCLK_BUSTIMER0 84 ++#define PCLK_BUSTIMER1 85 ++#define CLK_BUS_TIMER_ROOT 86 ++#define CLK_BUSTIMER0 87 ++#define CLK_BUSTIMER1 88 ++#define CLK_BUSTIMER2 89 ++#define CLK_BUSTIMER3 90 ++#define CLK_BUSTIMER4 91 ++#define CLK_BUSTIMER5 92 ++#define CLK_BUSTIMER6 93 ++#define CLK_BUSTIMER7 94 ++#define CLK_BUSTIMER8 95 ++#define CLK_BUSTIMER9 96 ++#define CLK_BUSTIMER10 97 ++#define CLK_BUSTIMER11 98 ++#define PCLK_WDT0 99 ++#define TCLK_WDT0 100 ++#define PCLK_CAN0 101 ++#define CLK_CAN0 102 ++#define PCLK_CAN1 103 ++#define CLK_CAN1 104 ++#define PCLK_CAN2 105 ++#define CLK_CAN2 106 ++#define ACLK_DECOM 107 ++#define PCLK_DECOM 108 ++#define DCLK_DECOM 109 ++#define ACLK_DMAC0 110 ++#define ACLK_DMAC1 111 ++#define ACLK_DMAC2 112 ++#define ACLK_BUS_ROOT 113 ++#define ACLK_GIC 114 ++#define PCLK_GPIO1 115 ++#define DBCLK_GPIO1 116 ++#define PCLK_GPIO2 117 ++#define DBCLK_GPIO2 118 ++#define PCLK_GPIO3 119 ++#define DBCLK_GPIO3 120 ++#define PCLK_GPIO4 121 ++#define DBCLK_GPIO4 122 ++#define PCLK_I2C1 123 ++#define PCLK_I2C2 124 ++#define PCLK_I2C3 125 ++#define PCLK_I2C4 126 ++#define PCLK_I2C5 127 ++#define PCLK_I2C6 128 ++#define PCLK_I2C7 129 ++#define PCLK_I2C8 130 ++#define CLK_I2C1 131 ++#define CLK_I2C2 132 ++#define CLK_I2C3 133 ++#define CLK_I2C4 134 ++#define CLK_I2C5 135 ++#define CLK_I2C6 136 ++#define CLK_I2C7 137 ++#define CLK_I2C8 138 ++#define PCLK_OTPC_NS 139 ++#define CLK_OTPC_NS 140 ++#define CLK_OTPC_ARB 141 ++#define CLK_OTPC_AUTO_RD_G 142 ++#define CLK_OTP_PHY_G 143 ++#define PCLK_SARADC 144 ++#define CLK_SARADC 145 ++#define PCLK_SPI0 146 ++#define PCLK_SPI1 147 ++#define PCLK_SPI2 148 ++#define PCLK_SPI3 149 ++#define PCLK_SPI4 150 ++#define CLK_SPI0 151 ++#define CLK_SPI1 152 ++#define CLK_SPI2 153 ++#define CLK_SPI3 154 ++#define CLK_SPI4 155 ++#define ACLK_SPINLOCK 156 ++#define PCLK_TSADC 157 ++#define CLK_TSADC 158 ++#define PCLK_UART1 159 ++#define PCLK_UART2 160 ++#define PCLK_UART3 161 ++#define PCLK_UART4 162 ++#define PCLK_UART5 163 ++#define PCLK_UART6 164 ++#define PCLK_UART7 165 ++#define PCLK_UART8 166 ++#define PCLK_UART9 167 ++#define CLK_UART1_SRC 168 ++#define CLK_UART1_FRAC 169 ++#define CLK_UART1 170 ++#define SCLK_UART1 171 ++#define CLK_UART2_SRC 172 ++#define CLK_UART2_FRAC 173 ++#define CLK_UART2 174 ++#define SCLK_UART2 175 ++#define CLK_UART3_SRC 176 ++#define CLK_UART3_FRAC 177 ++#define CLK_UART3 178 ++#define SCLK_UART3 179 ++#define CLK_UART4_SRC 180 ++#define CLK_UART4_FRAC 181 ++#define CLK_UART4 182 ++#define SCLK_UART4 183 ++#define CLK_UART5_SRC 184 ++#define CLK_UART5_FRAC 185 ++#define CLK_UART5 186 ++#define SCLK_UART5 187 ++#define CLK_UART6_SRC 188 ++#define CLK_UART6_FRAC 189 ++#define CLK_UART6 190 ++#define SCLK_UART6 191 ++#define CLK_UART7_SRC 192 ++#define CLK_UART7_FRAC 193 ++#define CLK_UART7 194 ++#define SCLK_UART7 195 ++#define CLK_UART8_SRC 196 ++#define CLK_UART8_FRAC 197 ++#define CLK_UART8 198 ++#define SCLK_UART8 199 ++#define CLK_UART9_SRC 200 ++#define CLK_UART9_FRAC 201 ++#define CLK_UART9 202 ++#define SCLK_UART9 203 ++#define ACLK_CENTER_ROOT 204 ++#define ACLK_CENTER_LOW_ROOT 205 ++#define HCLK_CENTER_ROOT 206 ++#define PCLK_CENTER_ROOT 207 ++#define ACLK_DMA2DDR 208 ++#define ACLK_DDR_SHAREMEM 209 ++#define ACLK_CENTER_S200_ROOT 210 ++#define ACLK_CENTER_S400_ROOT 211 ++#define FCLK_DDR_CM0_CORE 212 ++#define CLK_DDR_TIMER_ROOT 213 ++#define CLK_DDR_TIMER0 214 ++#define CLK_DDR_TIMER1 215 ++#define TCLK_WDT_DDR 216 ++#define CLK_DDR_CM0_RTC 217 ++#define PCLK_WDT 218 ++#define PCLK_TIMER 219 ++#define PCLK_DMA2DDR 220 ++#define PCLK_SHAREMEM 221 ++#define CLK_50M_SRC 222 ++#define CLK_100M_SRC 223 ++#define CLK_150M_SRC 224 ++#define CLK_200M_SRC 225 ++#define CLK_250M_SRC 226 ++#define CLK_300M_SRC 227 ++#define CLK_350M_SRC 228 ++#define CLK_400M_SRC 229 ++#define CLK_450M_SRC 230 ++#define CLK_500M_SRC 231 ++#define CLK_600M_SRC 232 ++#define CLK_650M_SRC 233 ++#define CLK_700M_SRC 234 ++#define CLK_800M_SRC 235 ++#define CLK_1000M_SRC 236 ++#define CLK_1200M_SRC 237 ++#define ACLK_TOP_M300_ROOT 238 ++#define ACLK_TOP_M500_ROOT 239 ++#define ACLK_TOP_M400_ROOT 240 ++#define ACLK_TOP_S200_ROOT 241 ++#define ACLK_TOP_S400_ROOT 242 ++#define CLK_MIPI_CAMARAOUT_M0 243 ++#define CLK_MIPI_CAMARAOUT_M1 244 ++#define CLK_MIPI_CAMARAOUT_M2 245 ++#define CLK_MIPI_CAMARAOUT_M3 246 ++#define CLK_MIPI_CAMARAOUT_M4 247 ++#define MCLK_GMAC0_OUT 248 ++#define REFCLKO25M_ETH0_OUT 249 ++#define REFCLKO25M_ETH1_OUT 250 ++#define CLK_CIFOUT_OUT 251 ++#define PCLK_MIPI_DCPHY0 252 ++#define PCLK_MIPI_DCPHY1 253 ++#define PCLK_CSIPHY0 254 ++#define PCLK_CSIPHY1 255 ++#define ACLK_TOP_ROOT 256 ++#define PCLK_TOP_ROOT 257 ++#define ACLK_LOW_TOP_ROOT 258 ++#define PCLK_CRU 259 ++#define PCLK_GPU_ROOT 260 ++#define CLK_GPU_SRC 261 ++#define CLK_GPU 262 ++#define CLK_GPU_COREGROUP 263 ++#define CLK_GPU_STACKS 264 ++#define PCLK_GPU_PVTM 265 ++#define CLK_GPU_PVTM 266 ++#define CLK_CORE_GPU_PVTM 267 ++#define PCLK_GPU_GRF 268 ++#define ACLK_ISP1_ROOT 269 ++#define HCLK_ISP1_ROOT 270 ++#define CLK_ISP1_CORE 271 ++#define CLK_ISP1_CORE_MARVIN 272 ++#define CLK_ISP1_CORE_VICAP 273 ++#define ACLK_ISP1 274 ++#define HCLK_ISP1 275 ++#define ACLK_NPU1 276 ++#define HCLK_NPU1 277 ++#define ACLK_NPU2 278 ++#define HCLK_NPU2 279 ++#define HCLK_NPU_CM0_ROOT 280 ++#define FCLK_NPU_CM0_CORE 281 ++#define CLK_NPU_CM0_RTC 282 ++#define PCLK_NPU_PVTM 283 ++#define PCLK_NPU_GRF 284 ++#define CLK_NPU_PVTM 285 ++#define CLK_CORE_NPU_PVTM 286 ++#define ACLK_NPU0 287 ++#define HCLK_NPU0 288 ++#define HCLK_NPU_ROOT 289 ++#define CLK_NPU_DSU0 290 ++#define PCLK_NPU_ROOT 291 ++#define PCLK_NPU_TIMER 292 ++#define CLK_NPUTIMER_ROOT 293 ++#define CLK_NPUTIMER0 294 ++#define CLK_NPUTIMER1 295 ++#define PCLK_NPU_WDT 296 ++#define TCLK_NPU_WDT 297 ++#define HCLK_EMMC 298 ++#define ACLK_EMMC 299 ++#define CCLK_EMMC 300 ++#define BCLK_EMMC 301 ++#define TMCLK_EMMC 302 ++#define SCLK_SFC 303 ++#define HCLK_SFC 304 ++#define HCLK_SFC_XIP 305 ++#define HCLK_NVM_ROOT 306 ++#define ACLK_NVM_ROOT 307 ++#define CLK_GMAC0_PTP_REF 308 ++#define CLK_GMAC1_PTP_REF 309 ++#define CLK_GMAC_125M 310 ++#define CLK_GMAC_50M 311 ++#define ACLK_PHP_GIC_ITS 312 ++#define ACLK_MMU_PCIE 313 ++#define ACLK_MMU_PHP 314 ++#define ACLK_PCIE_4L_DBI 315 ++#define ACLK_PCIE_2L_DBI 316 ++#define ACLK_PCIE_1L0_DBI 317 ++#define ACLK_PCIE_1L1_DBI 318 ++#define ACLK_PCIE_1L2_DBI 319 ++#define ACLK_PCIE_4L_MSTR 320 ++#define ACLK_PCIE_2L_MSTR 321 ++#define ACLK_PCIE_1L0_MSTR 322 ++#define ACLK_PCIE_1L1_MSTR 323 ++#define ACLK_PCIE_1L2_MSTR 324 ++#define ACLK_PCIE_4L_SLV 325 ++#define ACLK_PCIE_2L_SLV 326 ++#define ACLK_PCIE_1L0_SLV 327 ++#define ACLK_PCIE_1L1_SLV 328 ++#define ACLK_PCIE_1L2_SLV 329 ++#define PCLK_PCIE_4L 330 ++#define PCLK_PCIE_2L 331 ++#define PCLK_PCIE_1L0 332 ++#define PCLK_PCIE_1L1 333 ++#define PCLK_PCIE_1L2 334 ++#define CLK_PCIE_AUX0 335 ++#define CLK_PCIE_AUX1 336 ++#define CLK_PCIE_AUX2 337 ++#define CLK_PCIE_AUX3 338 ++#define CLK_PCIE_AUX4 339 ++#define CLK_PIPEPHY0_REF 340 ++#define CLK_PIPEPHY1_REF 341 ++#define CLK_PIPEPHY2_REF 342 ++#define PCLK_PHP_ROOT 343 ++#define PCLK_GMAC0 344 ++#define PCLK_GMAC1 345 ++#define ACLK_PCIE_ROOT 346 ++#define ACLK_PHP_ROOT 347 ++#define ACLK_PCIE_BRIDGE 348 ++#define ACLK_GMAC0 349 ++#define ACLK_GMAC1 350 ++#define CLK_PMALIVE0 351 ++#define CLK_PMALIVE1 352 ++#define CLK_PMALIVE2 353 ++#define ACLK_SATA0 354 ++#define ACLK_SATA1 355 ++#define ACLK_SATA2 356 ++#define CLK_RXOOB0 357 ++#define CLK_RXOOB1 358 ++#define CLK_RXOOB2 359 ++#define ACLK_USB3OTG2 360 ++#define SUSPEND_CLK_USB3OTG2 361 ++#define REF_CLK_USB3OTG2 362 ++#define CLK_UTMI_OTG2 363 ++#define CLK_PIPEPHY0_PIPE_G 364 ++#define CLK_PIPEPHY1_PIPE_G 365 ++#define CLK_PIPEPHY2_PIPE_G 366 ++#define CLK_PIPEPHY0_PIPE_ASIC_G 367 ++#define CLK_PIPEPHY1_PIPE_ASIC_G 368 ++#define CLK_PIPEPHY2_PIPE_ASIC_G 369 ++#define CLK_PIPEPHY2_PIPE_U3_G 370 ++#define CLK_PCIE1L2_PIPE 371 ++#define CLK_PCIE4L_PIPE 372 ++#define CLK_PCIE2L_PIPE 373 ++#define PCLK_PCIE_COMBO_PIPE_PHY0 374 ++#define PCLK_PCIE_COMBO_PIPE_PHY1 375 ++#define PCLK_PCIE_COMBO_PIPE_PHY2 376 ++#define PCLK_PCIE_COMBO_PIPE_PHY 377 ++#define HCLK_RGA3_1 378 ++#define ACLK_RGA3_1 379 ++#define CLK_RGA3_1_CORE 380 ++#define ACLK_RGA3_ROOT 381 ++#define HCLK_RGA3_ROOT 382 ++#define ACLK_RKVDEC_CCU 383 ++#define HCLK_RKVDEC0 384 ++#define ACLK_RKVDEC0 385 ++#define CLK_RKVDEC0_CA 386 ++#define CLK_RKVDEC0_HEVC_CA 387 ++#define CLK_RKVDEC0_CORE 388 ++#define HCLK_RKVDEC1 389 ++#define ACLK_RKVDEC1 390 ++#define CLK_RKVDEC1_CA 391 ++#define CLK_RKVDEC1_HEVC_CA 392 ++#define CLK_RKVDEC1_CORE 393 ++#define HCLK_SDIO 394 ++#define CCLK_SRC_SDIO 395 ++#define ACLK_USB_ROOT 396 ++#define HCLK_USB_ROOT 397 ++#define HCLK_HOST0 398 ++#define HCLK_HOST_ARB0 399 ++#define HCLK_HOST1 400 ++#define HCLK_HOST_ARB1 401 ++#define ACLK_USB3OTG0 402 ++#define SUSPEND_CLK_USB3OTG0 403 ++#define REF_CLK_USB3OTG0 404 ++#define ACLK_USB3OTG1 405 ++#define SUSPEND_CLK_USB3OTG1 406 ++#define REF_CLK_USB3OTG1 407 ++#define UTMI_OHCI_CLK48_HOST0 408 ++#define UTMI_OHCI_CLK48_HOST1 409 ++#define HCLK_IEP2P0 410 ++#define ACLK_IEP2P0 411 ++#define CLK_IEP2P0_CORE 412 ++#define ACLK_JPEG_ENCODER0 413 ++#define HCLK_JPEG_ENCODER0 414 ++#define ACLK_JPEG_ENCODER1 415 ++#define HCLK_JPEG_ENCODER1 416 ++#define ACLK_JPEG_ENCODER2 417 ++#define HCLK_JPEG_ENCODER2 418 ++#define ACLK_JPEG_ENCODER3 419 ++#define HCLK_JPEG_ENCODER3 420 ++#define ACLK_JPEG_DECODER 421 ++#define HCLK_JPEG_DECODER 422 ++#define HCLK_RGA2 423 ++#define ACLK_RGA2 424 ++#define CLK_RGA2_CORE 425 ++#define HCLK_RGA3_0 426 ++#define ACLK_RGA3_0 427 ++#define CLK_RGA3_0_CORE 428 ++#define ACLK_VDPU_ROOT 429 ++#define ACLK_VDPU_LOW_ROOT 430 ++#define HCLK_VDPU_ROOT 431 ++#define ACLK_JPEG_DECODER_ROOT 432 ++#define ACLK_VPU 433 ++#define HCLK_VPU 434 ++#define HCLK_RKVENC0_ROOT 435 ++#define ACLK_RKVENC0_ROOT 436 ++#define HCLK_RKVENC0 437 ++#define ACLK_RKVENC0 438 ++#define CLK_RKVENC0_CORE 439 ++#define HCLK_RKVENC1_ROOT 440 ++#define ACLK_RKVENC1_ROOT 441 ++#define HCLK_RKVENC1 442 ++#define ACLK_RKVENC1 443 ++#define CLK_RKVENC1_CORE 444 ++#define ICLK_CSIHOST01 445 ++#define ICLK_CSIHOST0 446 ++#define ICLK_CSIHOST1 447 ++#define PCLK_CSI_HOST_0 448 ++#define PCLK_CSI_HOST_1 449 ++#define PCLK_CSI_HOST_2 450 ++#define PCLK_CSI_HOST_3 451 ++#define PCLK_CSI_HOST_4 452 ++#define PCLK_CSI_HOST_5 453 ++#define ACLK_FISHEYE0 454 ++#define HCLK_FISHEYE0 455 ++#define CLK_FISHEYE0_CORE 456 ++#define ACLK_FISHEYE1 457 ++#define HCLK_FISHEYE1 458 ++#define CLK_FISHEYE1_CORE 459 ++#define CLK_ISP0_CORE 460 ++#define CLK_ISP0_CORE_MARVIN 461 ++#define CLK_ISP0_CORE_VICAP 462 ++#define ACLK_ISP0 463 ++#define HCLK_ISP0 464 ++#define ACLK_VI_ROOT 465 ++#define HCLK_VI_ROOT 466 ++#define PCLK_VI_ROOT 467 ++#define DCLK_VICAP 468 ++#define ACLK_VICAP 469 ++#define HCLK_VICAP 470 ++#define PCLK_DP0 471 ++#define PCLK_DP1 472 ++#define PCLK_S_DP0 473 ++#define PCLK_S_DP1 474 ++#define CLK_DP0 475 ++#define CLK_DP1 476 ++#define HCLK_HDCP_KEY0 477 ++#define ACLK_HDCP0 478 ++#define HCLK_HDCP0 479 ++#define PCLK_HDCP0 480 ++#define HCLK_I2S4_8CH 481 ++#define ACLK_TRNG0 482 ++#define PCLK_TRNG0 483 ++#define ACLK_VO0_ROOT 484 ++#define HCLK_VO0_ROOT 485 ++#define HCLK_VO0_S_ROOT 486 ++#define PCLK_VO0_ROOT 487 ++#define PCLK_VO0_S_ROOT 488 ++#define PCLK_VO0GRF 489 ++#define CLK_I2S4_8CH_TX_SRC 490 ++#define CLK_I2S4_8CH_TX_FRAC 491 ++#define MCLK_I2S4_8CH_TX 492 ++#define CLK_I2S4_8CH_TX 493 ++#define HCLK_I2S8_8CH 494 ++#define CLK_I2S8_8CH_TX_SRC 495 ++#define CLK_I2S8_8CH_TX_FRAC 496 ++#define MCLK_I2S8_8CH_TX 497 ++#define CLK_I2S8_8CH_TX 498 ++#define HCLK_SPDIF2_DP0 499 ++#define CLK_SPDIF2_DP0_SRC 500 ++#define CLK_SPDIF2_DP0_FRAC 501 ++#define MCLK_SPDIF2_DP0 502 ++#define CLK_SPDIF2_DP0 503 ++#define MCLK_SPDIF2 504 ++#define HCLK_SPDIF5_DP1 505 ++#define CLK_SPDIF5_DP1_SRC 506 ++#define CLK_SPDIF5_DP1_FRAC 507 ++#define MCLK_SPDIF5_DP1 508 ++#define CLK_SPDIF5_DP1 509 ++#define MCLK_SPDIF5 510 ++#define PCLK_EDP0 511 ++#define CLK_EDP0_24M 512 ++#define CLK_EDP0_200M 513 ++#define PCLK_EDP1 514 ++#define CLK_EDP1_24M 515 ++#define CLK_EDP1_200M 516 ++#define HCLK_HDCP_KEY1 517 ++#define ACLK_HDCP1 518 ++#define HCLK_HDCP1 519 ++#define PCLK_HDCP1 520 ++#define ACLK_HDMIRX 521 ++#define PCLK_HDMIRX 522 ++#define CLK_HDMIRX_REF 523 ++#define CLK_HDMIRX_AUD_SRC 524 ++#define CLK_HDMIRX_AUD_FRAC 525 ++#define CLK_HDMIRX_AUD 526 ++#define CLK_HDMIRX_AUD_P_MUX 527 ++#define PCLK_HDMITX0 528 ++#define CLK_HDMITX0_EARC 529 ++#define CLK_HDMITX0_REF 530 ++#define PCLK_HDMITX1 531 ++#define CLK_HDMITX1_EARC 532 ++#define CLK_HDMITX1_REF 533 ++#define CLK_HDMITRX_REFSRC 534 ++#define ACLK_TRNG1 535 ++#define PCLK_TRNG1 536 ++#define ACLK_HDCP1_ROOT 537 ++#define ACLK_HDMIRX_ROOT 538 ++#define HCLK_VO1_ROOT 539 ++#define HCLK_VO1_S_ROOT 540 ++#define PCLK_VO1_ROOT 541 ++#define PCLK_VO1_S_ROOT 542 ++#define PCLK_S_EDP0 543 ++#define PCLK_S_EDP1 544 ++#define PCLK_S_HDMIRX 545 ++#define HCLK_I2S10_8CH 546 ++#define CLK_I2S10_8CH_RX_SRC 547 ++#define CLK_I2S10_8CH_RX_FRAC 548 ++#define CLK_I2S10_8CH_RX 549 ++#define MCLK_I2S10_8CH_RX 550 ++#define HCLK_I2S7_8CH 551 ++#define CLK_I2S7_8CH_RX_SRC 552 ++#define CLK_I2S7_8CH_RX_FRAC 553 ++#define CLK_I2S7_8CH_RX 554 ++#define MCLK_I2S7_8CH_RX 555 ++#define HCLK_I2S9_8CH 556 ++#define CLK_I2S9_8CH_RX_SRC 557 ++#define CLK_I2S9_8CH_RX_FRAC 558 ++#define CLK_I2S9_8CH_RX 559 ++#define MCLK_I2S9_8CH_RX 560 ++#define CLK_I2S5_8CH_TX_SRC 561 ++#define CLK_I2S5_8CH_TX_FRAC 562 ++#define CLK_I2S5_8CH_TX 563 ++#define MCLK_I2S5_8CH_TX 564 ++#define HCLK_I2S5_8CH 565 ++#define CLK_I2S6_8CH_TX_SRC 566 ++#define CLK_I2S6_8CH_TX_FRAC 567 ++#define CLK_I2S6_8CH_TX 568 ++#define MCLK_I2S6_8CH_TX 569 ++#define CLK_I2S6_8CH_RX_SRC 570 ++#define CLK_I2S6_8CH_RX_FRAC 571 ++#define CLK_I2S6_8CH_RX 572 ++#define MCLK_I2S6_8CH_RX 573 ++#define I2S6_8CH_MCLKOUT 574 ++#define HCLK_I2S6_8CH 575 ++#define HCLK_SPDIF3 576 ++#define CLK_SPDIF3_SRC 577 ++#define CLK_SPDIF3_FRAC 578 ++#define CLK_SPDIF3 579 ++#define MCLK_SPDIF3 580 ++#define HCLK_SPDIF4 581 ++#define CLK_SPDIF4_SRC 582 ++#define CLK_SPDIF4_FRAC 583 ++#define CLK_SPDIF4 584 ++#define MCLK_SPDIF4 585 ++#define HCLK_SPDIFRX0 586 ++#define MCLK_SPDIFRX0 587 ++#define HCLK_SPDIFRX1 588 ++#define MCLK_SPDIFRX1 589 ++#define HCLK_SPDIFRX2 590 ++#define MCLK_SPDIFRX2 591 ++#define ACLK_VO1USB_TOP_ROOT 592 ++#define HCLK_VO1USB_TOP_ROOT 593 ++#define CLK_HDMIHDP0 594 ++#define CLK_HDMIHDP1 595 ++#define PCLK_HDPTX0 596 ++#define PCLK_HDPTX1 597 ++#define PCLK_USBDPPHY0 598 ++#define PCLK_USBDPPHY1 599 ++#define ACLK_VOP_ROOT 600 ++#define ACLK_VOP_LOW_ROOT 601 ++#define HCLK_VOP_ROOT 602 ++#define PCLK_VOP_ROOT 603 ++#define HCLK_VOP 604 ++#define ACLK_VOP 605 ++#define DCLK_VOP0_SRC 606 ++#define DCLK_VOP1_SRC 607 ++#define DCLK_VOP2_SRC 608 ++#define DCLK_VOP0 609 ++#define DCLK_VOP1 610 ++#define DCLK_VOP2 611 ++#define DCLK_VOP3 612 ++#define PCLK_DSIHOST0 613 ++#define PCLK_DSIHOST1 614 ++#define CLK_DSIHOST0 615 ++#define CLK_DSIHOST1 616 ++#define CLK_VOP_PMU 617 ++#define ACLK_VOP_DOBY 618 ++#define ACLK_VOP_SUB_SRC 619 ++#define CLK_USBDP_PHY0_IMMORTAL 620 ++#define CLK_USBDP_PHY1_IMMORTAL 621 ++#define CLK_PMU0 622 ++#define PCLK_PMU0 623 ++#define PCLK_PMU0IOC 624 ++#define PCLK_GPIO0 625 ++#define DBCLK_GPIO0 626 ++#define PCLK_I2C0 627 ++#define CLK_I2C0 628 ++#define HCLK_I2S1_8CH 629 ++#define CLK_I2S1_8CH_TX_SRC 630 ++#define CLK_I2S1_8CH_TX_FRAC 631 ++#define CLK_I2S1_8CH_TX 632 ++#define MCLK_I2S1_8CH_TX 633 ++#define CLK_I2S1_8CH_RX_SRC 634 ++#define CLK_I2S1_8CH_RX_FRAC 635 ++#define CLK_I2S1_8CH_RX 636 ++#define MCLK_I2S1_8CH_RX 637 ++#define I2S1_8CH_MCLKOUT 638 ++#define CLK_PMU1_50M_SRC 639 ++#define CLK_PMU1_100M_SRC 640 ++#define CLK_PMU1_200M_SRC 641 ++#define CLK_PMU1_300M_SRC 642 ++#define CLK_PMU1_400M_SRC 643 ++#define HCLK_PMU1_ROOT 644 ++#define PCLK_PMU1_ROOT 645 ++#define PCLK_PMU0_ROOT 646 ++#define HCLK_PMU_CM0_ROOT 647 ++#define PCLK_PMU1 648 ++#define CLK_DDR_FAIL_SAFE 649 ++#define CLK_PMU1 650 ++#define HCLK_PDM0 651 ++#define MCLK_PDM0 652 ++#define HCLK_VAD 653 ++#define FCLK_PMU_CM0_CORE 654 ++#define CLK_PMU_CM0_RTC 655 ++#define PCLK_PMU1_IOC 656 ++#define PCLK_PMU1PWM 657 ++#define CLK_PMU1PWM 658 ++#define CLK_PMU1PWM_CAPTURE 659 ++#define PCLK_PMU1TIMER 660 ++#define CLK_PMU1TIMER_ROOT 661 ++#define CLK_PMU1TIMER0 662 ++#define CLK_PMU1TIMER1 663 ++#define CLK_UART0_SRC 664 ++#define CLK_UART0_FRAC 665 ++#define CLK_UART0 666 ++#define SCLK_UART0 667 ++#define PCLK_UART0 668 ++#define PCLK_PMU1WDT 669 ++#define TCLK_PMU1WDT 670 ++#define CLK_CR_PARA 671 ++#define CLK_USB2PHY_HDPTXRXPHY_REF 672 ++#define CLK_USBDPPHY_MIPIDCPPHY_REF 673 ++#define CLK_REF_PIPE_PHY0_OSC_SRC 674 ++#define CLK_REF_PIPE_PHY1_OSC_SRC 675 ++#define CLK_REF_PIPE_PHY2_OSC_SRC 676 ++#define CLK_REF_PIPE_PHY0_PLL_SRC 677 ++#define CLK_REF_PIPE_PHY1_PLL_SRC 678 ++#define CLK_REF_PIPE_PHY2_PLL_SRC 679 ++#define CLK_REF_PIPE_PHY0 680 ++#define CLK_REF_PIPE_PHY1 681 ++#define CLK_REF_PIPE_PHY2 682 ++#define SCLK_SDIO_DRV 683 ++#define SCLK_SDIO_SAMPLE 684 ++#define SCLK_SDMMC_DRV 685 ++#define SCLK_SDMMC_SAMPLE 686 ++#define CLK_PCIE1L0_PIPE 687 ++#define CLK_PCIE1L1_PIPE 688 ++#define CLK_BIGCORE0_PVTM 689 ++#define CLK_CORE_BIGCORE0_PVTM 690 ++#define CLK_BIGCORE1_PVTM 691 ++#define CLK_CORE_BIGCORE1_PVTM 692 ++#define CLK_LITCORE_PVTM 693 ++#define CLK_CORE_LITCORE_PVTM 694 ++#define CLK_AUX16M_0 695 ++#define CLK_AUX16M_1 696 ++#define CLK_PHY0_REF_ALT_P 697 ++#define CLK_PHY0_REF_ALT_M 698 ++#define CLK_PHY1_REF_ALT_P 699 ++#define CLK_PHY1_REF_ALT_M 700 ++#define ACLK_ISP1_PRE 701 ++#define HCLK_ISP1_PRE 702 ++#define HCLK_NVM 703 ++#define ACLK_USB 704 ++#define HCLK_USB 705 ++#define ACLK_JPEG_DECODER_PRE 706 ++#define ACLK_VDPU_LOW_PRE 707 ++#define ACLK_RKVENC1_PRE 708 ++#define HCLK_RKVENC1_PRE 709 ++#define HCLK_RKVDEC0_PRE 710 ++#define ACLK_RKVDEC0_PRE 711 ++#define HCLK_RKVDEC1_PRE 712 ++#define ACLK_RKVDEC1_PRE 713 ++#define ACLK_HDCP0_PRE 714 ++#define HCLK_VO0 715 ++#define ACLK_HDCP1_PRE 716 ++#define HCLK_VO1 717 ++#define ACLK_AV1_PRE 718 ++#define PCLK_AV1_PRE 719 ++#define HCLK_SDIO_PRE 720 ++ ++#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) ++ ++/* scmi-clocks indices */ ++ ++#define SCMI_CLK_CPUL 0 ++#define SCMI_CLK_DSU 1 ++#define SCMI_CLK_CPUB01 2 ++#define SCMI_CLK_CPUB23 3 ++#define SCMI_CLK_DDR 4 ++#define SCMI_CLK_GPU 5 ++#define SCMI_CLK_NPU 6 ++#define SCMI_CLK_SBUS 7 ++#define SCMI_PCLK_SBUS 8 ++#define SCMI_CCLK_SD 9 ++#define SCMI_DCLK_SD 10 ++#define SCMI_ACLK_SECURE_NS 11 ++#define SCMI_HCLK_SECURE_NS 12 ++#define SCMI_TCLK_WDT 13 ++#define SCMI_KEYLADDER_CORE 14 ++#define SCMI_KEYLADDER_RNG 15 ++#define SCMI_ACLK_SECURE_S 16 ++#define SCMI_HCLK_SECURE_S 17 ++#define SCMI_PCLK_SECURE_S 18 ++#define SCMI_CRYPTO_RNG 19 ++#define SCMI_CRYPTO_CORE 20 ++#define SCMI_CRYPTO_PKA 21 ++#define SCMI_SPLL 22 ++#define SCMI_HCLK_SD 23 ++ ++#endif diff --git a/target/linux/rockchip/patches-6.1/030-02-v6.2-dt-bindings-reset-add-rk3588-reset-definitions.patch b/target/linux/rockchip/patches-6.1/030-02-v6.2-dt-bindings-reset-add-rk3588-reset-definitions.patch new file mode 100644 index 0000000000..a620d50e50 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-02-v6.2-dt-bindings-reset-add-rk3588-reset-definitions.patch @@ -0,0 +1,781 @@ +From 0a8eb7dae617a9537b9a64a6b14e63415c279eb5 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 18 Oct 2022 17:14:00 +0200 +Subject: [PATCH] dt-bindings: reset: add rk3588 reset definitions + +Add reset ID defines for rk3588. + +Compared to the downstream bindings and previous rockchip +generations this uses continous gapless reset IDs starting +at 0 instead of register offsets as IDs. Thus all numbers +are different between upstream and downstream, but I kept +the names exactly the same. + +Co-Developed-by: Elaine Zhang +Signed-off-by: Elaine Zhang +Acked-by: Rob Herring +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-3-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++++++++++++++++ + 1 file changed, 754 insertions(+) + create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h + +--- /dev/null ++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h +@@ -0,0 +1,754 @@ ++/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. ++ * Copyright (c) 2022 Collabora Ltd. ++ * ++ * Author: Elaine Zhang ++ * Author: Sebastian Reichel ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H ++#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H ++ ++#define SRST_A_TOP_BIU 0 ++#define SRST_P_TOP_BIU 1 ++#define SRST_P_CSIPHY0 2 ++#define SRST_CSIPHY0 3 ++#define SRST_P_CSIPHY1 4 ++#define SRST_CSIPHY1 5 ++#define SRST_A_TOP_M500_BIU 6 ++ ++#define SRST_A_TOP_M400_BIU 7 ++#define SRST_A_TOP_S200_BIU 8 ++#define SRST_A_TOP_S400_BIU 9 ++#define SRST_A_TOP_M300_BIU 10 ++#define SRST_USBDP_COMBO_PHY0_INIT 11 ++#define SRST_USBDP_COMBO_PHY0_CMN 12 ++#define SRST_USBDP_COMBO_PHY0_LANE 13 ++#define SRST_USBDP_COMBO_PHY0_PCS 14 ++#define SRST_USBDP_COMBO_PHY1_INIT 15 ++ ++#define SRST_USBDP_COMBO_PHY1_CMN 16 ++#define SRST_USBDP_COMBO_PHY1_LANE 17 ++#define SRST_USBDP_COMBO_PHY1_PCS 18 ++#define SRST_DCPHY0 19 ++#define SRST_P_MIPI_DCPHY0 20 ++#define SRST_P_MIPI_DCPHY0_GRF 21 ++ ++#define SRST_DCPHY1 22 ++#define SRST_P_MIPI_DCPHY1 23 ++#define SRST_P_MIPI_DCPHY1_GRF 24 ++#define SRST_P_APB2ASB_SLV_CDPHY 25 ++#define SRST_P_APB2ASB_SLV_CSIPHY 26 ++#define SRST_P_APB2ASB_SLV_VCCIO3_5 27 ++#define SRST_P_APB2ASB_SLV_VCCIO6 28 ++#define SRST_P_APB2ASB_SLV_EMMCIO 29 ++#define SRST_P_APB2ASB_SLV_IOC_TOP 30 ++#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31 ++ ++#define SRST_P_CRU 32 ++#define SRST_A_CHANNEL_SECURE2VO1USB 33 ++#define SRST_A_CHANNEL_SECURE2CENTER 34 ++#define SRST_H_CHANNEL_SECURE2VO1USB 35 ++#define SRST_H_CHANNEL_SECURE2CENTER 36 ++ ++#define SRST_P_CHANNEL_SECURE2VO1USB 37 ++#define SRST_P_CHANNEL_SECURE2CENTER 38 ++ ++#define SRST_H_AUDIO_BIU 39 ++#define SRST_P_AUDIO_BIU 40 ++#define SRST_H_I2S0_8CH 41 ++#define SRST_M_I2S0_8CH_TX 42 ++#define SRST_M_I2S0_8CH_RX 43 ++#define SRST_P_ACDCDIG 44 ++#define SRST_H_I2S2_2CH 45 ++#define SRST_H_I2S3_2CH 46 ++ ++#define SRST_M_I2S2_2CH 47 ++#define SRST_M_I2S3_2CH 48 ++#define SRST_DAC_ACDCDIG 49 ++#define SRST_H_SPDIF0 50 ++ ++#define SRST_M_SPDIF0 51 ++#define SRST_H_SPDIF1 52 ++#define SRST_M_SPDIF1 53 ++#define SRST_H_PDM1 54 ++#define SRST_PDM1 55 ++ ++#define SRST_A_BUS_BIU 56 ++#define SRST_P_BUS_BIU 57 ++#define SRST_A_GIC 58 ++#define SRST_A_GIC_DBG 59 ++#define SRST_A_DMAC0 60 ++#define SRST_A_DMAC1 61 ++#define SRST_A_DMAC2 62 ++#define SRST_P_I2C1 63 ++#define SRST_P_I2C2 64 ++#define SRST_P_I2C3 65 ++#define SRST_P_I2C4 66 ++#define SRST_P_I2C5 67 ++#define SRST_P_I2C6 68 ++#define SRST_P_I2C7 69 ++#define SRST_P_I2C8 70 ++ ++#define SRST_I2C1 71 ++#define SRST_I2C2 72 ++#define SRST_I2C3 73 ++#define SRST_I2C4 74 ++#define SRST_I2C5 75 ++#define SRST_I2C6 76 ++#define SRST_I2C7 77 ++#define SRST_I2C8 78 ++#define SRST_P_CAN0 79 ++#define SRST_CAN0 80 ++#define SRST_P_CAN1 81 ++#define SRST_CAN1 82 ++#define SRST_P_CAN2 83 ++#define SRST_CAN2 84 ++#define SRST_P_SARADC 85 ++ ++#define SRST_P_TSADC 86 ++#define SRST_TSADC 87 ++#define SRST_P_UART1 88 ++#define SRST_P_UART2 89 ++#define SRST_P_UART3 90 ++#define SRST_P_UART4 91 ++#define SRST_P_UART5 92 ++#define SRST_P_UART6 93 ++#define SRST_P_UART7 94 ++#define SRST_P_UART8 95 ++#define SRST_P_UART9 96 ++#define SRST_S_UART1 97 ++ ++#define SRST_S_UART2 98 ++#define SRST_S_UART3 99 ++#define SRST_S_UART4 100 ++#define SRST_S_UART5 101 ++#define SRST_S_UART6 102 ++#define SRST_S_UART7 103 ++ ++#define SRST_S_UART8 104 ++#define SRST_S_UART9 105 ++#define SRST_P_SPI0 106 ++#define SRST_P_SPI1 107 ++#define SRST_P_SPI2 108 ++#define SRST_P_SPI3 109 ++#define SRST_P_SPI4 110 ++#define SRST_SPI0 111 ++#define SRST_SPI1 112 ++#define SRST_SPI2 113 ++#define SRST_SPI3 114 ++#define SRST_SPI4 115 ++ ++#define SRST_P_WDT0 116 ++#define SRST_T_WDT0 117 ++#define SRST_P_SYS_GRF 118 ++#define SRST_P_PWM1 119 ++#define SRST_PWM1 120 ++#define SRST_P_PWM2 121 ++#define SRST_PWM2 122 ++#define SRST_P_PWM3 123 ++#define SRST_PWM3 124 ++#define SRST_P_BUSTIMER0 125 ++#define SRST_P_BUSTIMER1 126 ++#define SRST_BUSTIMER0 127 ++ ++#define SRST_BUSTIMER1 128 ++#define SRST_BUSTIMER2 129 ++#define SRST_BUSTIMER3 130 ++#define SRST_BUSTIMER4 131 ++#define SRST_BUSTIMER5 132 ++#define SRST_BUSTIMER6 133 ++#define SRST_BUSTIMER7 134 ++#define SRST_BUSTIMER8 135 ++#define SRST_BUSTIMER9 136 ++#define SRST_BUSTIMER10 137 ++#define SRST_BUSTIMER11 138 ++#define SRST_P_MAILBOX0 139 ++#define SRST_P_MAILBOX1 140 ++#define SRST_P_MAILBOX2 141 ++#define SRST_P_GPIO1 142 ++#define SRST_GPIO1 143 ++ ++#define SRST_P_GPIO2 144 ++#define SRST_GPIO2 145 ++#define SRST_P_GPIO3 146 ++#define SRST_GPIO3 147 ++#define SRST_P_GPIO4 148 ++#define SRST_GPIO4 149 ++#define SRST_A_DECOM 150 ++#define SRST_P_DECOM 151 ++#define SRST_D_DECOM 152 ++#define SRST_P_TOP 153 ++#define SRST_A_GICADB_GIC2CORE_BUS 154 ++#define SRST_P_DFT2APB 155 ++#define SRST_P_APB2ASB_MST_TOP 156 ++#define SRST_P_APB2ASB_MST_CDPHY 157 ++#define SRST_P_APB2ASB_MST_BOT_RIGHT 158 ++ ++#define SRST_P_APB2ASB_MST_IOC_TOP 159 ++#define SRST_P_APB2ASB_MST_IOC_RIGHT 160 ++#define SRST_P_APB2ASB_MST_CSIPHY 161 ++#define SRST_P_APB2ASB_MST_VCCIO3_5 162 ++#define SRST_P_APB2ASB_MST_VCCIO6 163 ++#define SRST_P_APB2ASB_MST_EMMCIO 164 ++#define SRST_A_SPINLOCK 165 ++#define SRST_P_OTPC_NS 166 ++#define SRST_OTPC_NS 167 ++#define SRST_OTPC_ARB 168 ++ ++#define SRST_P_BUSIOC 169 ++#define SRST_P_PMUCM0_INTMUX 170 ++#define SRST_P_DDRCM0_INTMUX 171 ++ ++#define SRST_P_DDR_DFICTL_CH0 172 ++#define SRST_P_DDR_MON_CH0 173 ++#define SRST_P_DDR_STANDBY_CH0 174 ++#define SRST_P_DDR_UPCTL_CH0 175 ++#define SRST_TM_DDR_MON_CH0 176 ++#define SRST_P_DDR_GRF_CH01 177 ++#define SRST_DFI_CH0 178 ++#define SRST_SBR_CH0 179 ++#define SRST_DDR_UPCTL_CH0 180 ++#define SRST_DDR_DFICTL_CH0 181 ++#define SRST_DDR_MON_CH0 182 ++#define SRST_DDR_STANDBY_CH0 183 ++#define SRST_A_DDR_UPCTL_CH0 184 ++#define SRST_P_DDR_DFICTL_CH1 185 ++#define SRST_P_DDR_MON_CH1 186 ++#define SRST_P_DDR_STANDBY_CH1 187 ++ ++#define SRST_P_DDR_UPCTL_CH1 188 ++#define SRST_TM_DDR_MON_CH1 189 ++#define SRST_DFI_CH1 190 ++#define SRST_SBR_CH1 191 ++#define SRST_DDR_UPCTL_CH1 192 ++#define SRST_DDR_DFICTL_CH1 193 ++#define SRST_DDR_MON_CH1 194 ++#define SRST_DDR_STANDBY_CH1 195 ++#define SRST_A_DDR_UPCTL_CH1 196 ++#define SRST_A_DDR01_MSCH0 197 ++#define SRST_A_DDR01_RS_MSCH0 198 ++#define SRST_A_DDR01_FRS_MSCH0 199 ++ ++#define SRST_A_DDR01_SCRAMBLE0 200 ++#define SRST_A_DDR01_FRS_SCRAMBLE0 201 ++#define SRST_A_DDR01_MSCH1 202 ++#define SRST_A_DDR01_RS_MSCH1 203 ++#define SRST_A_DDR01_FRS_MSCH1 204 ++#define SRST_A_DDR01_SCRAMBLE1 205 ++#define SRST_A_DDR01_FRS_SCRAMBLE1 206 ++#define SRST_P_DDR01_MSCH0 207 ++#define SRST_P_DDR01_MSCH1 208 ++ ++#define SRST_P_DDR_DFICTL_CH2 209 ++#define SRST_P_DDR_MON_CH2 210 ++#define SRST_P_DDR_STANDBY_CH2 211 ++#define SRST_P_DDR_UPCTL_CH2 212 ++#define SRST_TM_DDR_MON_CH2 213 ++#define SRST_P_DDR_GRF_CH23 214 ++#define SRST_DFI_CH2 215 ++#define SRST_SBR_CH2 216 ++#define SRST_DDR_UPCTL_CH2 217 ++#define SRST_DDR_DFICTL_CH2 218 ++#define SRST_DDR_MON_CH2 219 ++#define SRST_DDR_STANDBY_CH2 220 ++#define SRST_A_DDR_UPCTL_CH2 221 ++#define SRST_P_DDR_DFICTL_CH3 222 ++#define SRST_P_DDR_MON_CH3 223 ++#define SRST_P_DDR_STANDBY_CH3 224 ++ ++#define SRST_P_DDR_UPCTL_CH3 225 ++#define SRST_TM_DDR_MON_CH3 226 ++#define SRST_DFI_CH3 227 ++#define SRST_SBR_CH3 228 ++#define SRST_DDR_UPCTL_CH3 229 ++#define SRST_DDR_DFICTL_CH3 230 ++#define SRST_DDR_MON_CH3 231 ++#define SRST_DDR_STANDBY_CH3 232 ++#define SRST_A_DDR_UPCTL_CH3 233 ++#define SRST_A_DDR23_MSCH2 234 ++#define SRST_A_DDR23_RS_MSCH2 235 ++#define SRST_A_DDR23_FRS_MSCH2 236 ++ ++#define SRST_A_DDR23_SCRAMBLE2 237 ++#define SRST_A_DDR23_FRS_SCRAMBLE2 238 ++#define SRST_A_DDR23_MSCH3 239 ++#define SRST_A_DDR23_RS_MSCH3 240 ++#define SRST_A_DDR23_FRS_MSCH3 241 ++#define SRST_A_DDR23_SCRAMBLE3 242 ++#define SRST_A_DDR23_FRS_SCRAMBLE3 243 ++#define SRST_P_DDR23_MSCH2 244 ++#define SRST_P_DDR23_MSCH3 245 ++ ++#define SRST_ISP1 246 ++#define SRST_ISP1_VICAP 247 ++#define SRST_A_ISP1_BIU 248 ++#define SRST_H_ISP1_BIU 249 ++ ++#define SRST_A_RKNN1 250 ++#define SRST_A_RKNN1_BIU 251 ++#define SRST_H_RKNN1 252 ++#define SRST_H_RKNN1_BIU 253 ++ ++#define SRST_A_RKNN2 254 ++#define SRST_A_RKNN2_BIU 255 ++#define SRST_H_RKNN2 256 ++#define SRST_H_RKNN2_BIU 257 ++ ++#define SRST_A_RKNN_DSU0 258 ++#define SRST_P_NPUTOP_BIU 259 ++#define SRST_P_NPU_TIMER 260 ++#define SRST_NPUTIMER0 261 ++#define SRST_NPUTIMER1 262 ++#define SRST_P_NPU_WDT 263 ++#define SRST_T_NPU_WDT 264 ++#define SRST_P_NPU_PVTM 265 ++#define SRST_P_NPU_GRF 266 ++#define SRST_NPU_PVTM 267 ++ ++#define SRST_NPU_PVTPLL 268 ++#define SRST_H_NPU_CM0_BIU 269 ++#define SRST_F_NPU_CM0_CORE 270 ++#define SRST_T_NPU_CM0_JTAG 271 ++#define SRST_A_RKNN0 272 ++#define SRST_A_RKNN0_BIU 273 ++#define SRST_H_RKNN0 274 ++#define SRST_H_RKNN0_BIU 275 ++ ++#define SRST_H_NVM_BIU 276 ++#define SRST_A_NVM_BIU 277 ++#define SRST_H_EMMC 278 ++#define SRST_A_EMMC 279 ++#define SRST_C_EMMC 280 ++#define SRST_B_EMMC 281 ++#define SRST_T_EMMC 282 ++#define SRST_S_SFC 283 ++#define SRST_H_SFC 284 ++#define SRST_H_SFC_XIP 285 ++ ++#define SRST_P_GRF 286 ++#define SRST_P_DEC_BIU 287 ++#define SRST_P_PHP_BIU 288 ++#define SRST_A_PCIE_GRIDGE 289 ++#define SRST_A_PHP_BIU 290 ++#define SRST_A_GMAC0 291 ++#define SRST_A_GMAC1 292 ++#define SRST_A_PCIE_BIU 293 ++#define SRST_PCIE0_POWER_UP 294 ++#define SRST_PCIE1_POWER_UP 295 ++#define SRST_PCIE2_POWER_UP 296 ++ ++#define SRST_PCIE3_POWER_UP 297 ++#define SRST_PCIE4_POWER_UP 298 ++#define SRST_P_PCIE0 299 ++#define SRST_P_PCIE1 300 ++#define SRST_P_PCIE2 301 ++#define SRST_P_PCIE3 302 ++ ++#define SRST_P_PCIE4 303 ++#define SRST_A_PHP_GIC_ITS 304 ++#define SRST_A_MMU_PCIE 305 ++#define SRST_A_MMU_PHP 306 ++#define SRST_A_MMU_BIU 307 ++ ++#define SRST_A_USB3OTG2 308 ++ ++#define SRST_PMALIVE0 309 ++#define SRST_PMALIVE1 310 ++#define SRST_PMALIVE2 311 ++#define SRST_A_SATA0 312 ++#define SRST_A_SATA1 313 ++#define SRST_A_SATA2 314 ++#define SRST_RXOOB0 315 ++#define SRST_RXOOB1 316 ++#define SRST_RXOOB2 317 ++#define SRST_ASIC0 318 ++#define SRST_ASIC1 319 ++#define SRST_ASIC2 320 ++ ++#define SRST_A_RKVDEC_CCU 321 ++#define SRST_H_RKVDEC0 322 ++#define SRST_A_RKVDEC0 323 ++#define SRST_H_RKVDEC0_BIU 324 ++#define SRST_A_RKVDEC0_BIU 325 ++#define SRST_RKVDEC0_CA 326 ++#define SRST_RKVDEC0_HEVC_CA 327 ++#define SRST_RKVDEC0_CORE 328 ++ ++#define SRST_H_RKVDEC1 329 ++#define SRST_A_RKVDEC1 330 ++#define SRST_H_RKVDEC1_BIU 331 ++#define SRST_A_RKVDEC1_BIU 332 ++#define SRST_RKVDEC1_CA 333 ++#define SRST_RKVDEC1_HEVC_CA 334 ++#define SRST_RKVDEC1_CORE 335 ++ ++#define SRST_A_USB_BIU 336 ++#define SRST_H_USB_BIU 337 ++#define SRST_A_USB3OTG0 338 ++#define SRST_A_USB3OTG1 339 ++#define SRST_H_HOST0 340 ++#define SRST_H_HOST_ARB0 341 ++#define SRST_H_HOST1 342 ++#define SRST_H_HOST_ARB1 343 ++#define SRST_A_USB_GRF 344 ++#define SRST_C_USB2P0_HOST0 345 ++ ++#define SRST_C_USB2P0_HOST1 346 ++#define SRST_HOST_UTMI0 347 ++#define SRST_HOST_UTMI1 348 ++ ++#define SRST_A_VDPU_BIU 349 ++#define SRST_A_VDPU_LOW_BIU 350 ++#define SRST_H_VDPU_BIU 351 ++#define SRST_A_JPEG_DECODER_BIU 352 ++#define SRST_A_VPU 353 ++#define SRST_H_VPU 354 ++#define SRST_A_JPEG_ENCODER0 355 ++#define SRST_H_JPEG_ENCODER0 356 ++#define SRST_A_JPEG_ENCODER1 357 ++#define SRST_H_JPEG_ENCODER1 358 ++#define SRST_A_JPEG_ENCODER2 359 ++#define SRST_H_JPEG_ENCODER2 360 ++ ++#define SRST_A_JPEG_ENCODER3 361 ++#define SRST_H_JPEG_ENCODER3 362 ++#define SRST_A_JPEG_DECODER 363 ++#define SRST_H_JPEG_DECODER 364 ++#define SRST_H_IEP2P0 365 ++#define SRST_A_IEP2P0 366 ++#define SRST_IEP2P0_CORE 367 ++#define SRST_H_RGA2 368 ++#define SRST_A_RGA2 369 ++#define SRST_RGA2_CORE 370 ++#define SRST_H_RGA3_0 371 ++#define SRST_A_RGA3_0 372 ++#define SRST_RGA3_0_CORE 373 ++ ++#define SRST_H_RKVENC0_BIU 374 ++#define SRST_A_RKVENC0_BIU 375 ++#define SRST_H_RKVENC0 376 ++#define SRST_A_RKVENC0 377 ++#define SRST_RKVENC0_CORE 378 ++ ++#define SRST_H_RKVENC1_BIU 379 ++#define SRST_A_RKVENC1_BIU 380 ++#define SRST_H_RKVENC1 381 ++#define SRST_A_RKVENC1 382 ++#define SRST_RKVENC1_CORE 383 ++ ++#define SRST_A_VI_BIU 384 ++#define SRST_H_VI_BIU 385 ++#define SRST_P_VI_BIU 386 ++#define SRST_D_VICAP 387 ++#define SRST_A_VICAP 388 ++#define SRST_H_VICAP 389 ++#define SRST_ISP0 390 ++#define SRST_ISP0_VICAP 391 ++ ++#define SRST_FISHEYE0 392 ++#define SRST_FISHEYE1 393 ++#define SRST_P_CSI_HOST_0 394 ++#define SRST_P_CSI_HOST_1 395 ++#define SRST_P_CSI_HOST_2 396 ++#define SRST_P_CSI_HOST_3 397 ++#define SRST_P_CSI_HOST_4 398 ++#define SRST_P_CSI_HOST_5 399 ++ ++#define SRST_CSIHOST0_VICAP 400 ++#define SRST_CSIHOST1_VICAP 401 ++#define SRST_CSIHOST2_VICAP 402 ++#define SRST_CSIHOST3_VICAP 403 ++#define SRST_CSIHOST4_VICAP 404 ++#define SRST_CSIHOST5_VICAP 405 ++#define SRST_CIFIN 406 ++ ++#define SRST_A_VOP_BIU 407 ++#define SRST_A_VOP_LOW_BIU 408 ++#define SRST_H_VOP_BIU 409 ++#define SRST_P_VOP_BIU 410 ++#define SRST_H_VOP 411 ++#define SRST_A_VOP 412 ++#define SRST_D_VOP0 413 ++#define SRST_D_VOP2HDMI_BRIDGE0 414 ++#define SRST_D_VOP2HDMI_BRIDGE1 415 ++ ++#define SRST_D_VOP1 416 ++#define SRST_D_VOP2 417 ++#define SRST_D_VOP3 418 ++#define SRST_P_VOPGRF 419 ++#define SRST_P_DSIHOST0 420 ++#define SRST_P_DSIHOST1 421 ++#define SRST_DSIHOST0 422 ++#define SRST_DSIHOST1 423 ++#define SRST_VOP_PMU 424 ++#define SRST_P_VOP_CHANNEL_BIU 425 ++ ++#define SRST_H_VO0_BIU 426 ++#define SRST_H_VO0_S_BIU 427 ++#define SRST_P_VO0_BIU 428 ++#define SRST_P_VO0_S_BIU 429 ++#define SRST_A_HDCP0_BIU 430 ++#define SRST_P_VO0GRF 431 ++#define SRST_H_HDCP_KEY0 432 ++#define SRST_A_HDCP0 433 ++#define SRST_H_HDCP0 434 ++#define SRST_HDCP0 435 ++ ++#define SRST_P_TRNG0 436 ++#define SRST_DP0 437 ++#define SRST_DP1 438 ++#define SRST_H_I2S4_8CH 439 ++#define SRST_M_I2S4_8CH_TX 440 ++#define SRST_H_I2S8_8CH 441 ++ ++#define SRST_M_I2S8_8CH_TX 442 ++#define SRST_H_SPDIF2_DP0 443 ++#define SRST_M_SPDIF2_DP0 444 ++#define SRST_H_SPDIF5_DP1 445 ++#define SRST_M_SPDIF5_DP1 446 ++ ++#define SRST_A_HDCP1_BIU 447 ++#define SRST_A_VO1_BIU 448 ++#define SRST_H_VOP1_BIU 449 ++#define SRST_H_VOP1_S_BIU 450 ++#define SRST_P_VOP1_BIU 451 ++#define SRST_P_VO1GRF 452 ++#define SRST_P_VO1_S_BIU 453 ++ ++#define SRST_H_I2S7_8CH 454 ++#define SRST_M_I2S7_8CH_RX 455 ++#define SRST_H_HDCP_KEY1 456 ++#define SRST_A_HDCP1 457 ++#define SRST_H_HDCP1 458 ++#define SRST_HDCP1 459 ++#define SRST_P_TRNG1 460 ++#define SRST_P_HDMITX0 461 ++ ++#define SRST_HDMITX0_REF 462 ++#define SRST_P_HDMITX1 463 ++#define SRST_HDMITX1_REF 464 ++#define SRST_A_HDMIRX 465 ++#define SRST_P_HDMIRX 466 ++#define SRST_HDMIRX_REF 467 ++ ++#define SRST_P_EDP0 468 ++#define SRST_EDP0_24M 469 ++#define SRST_P_EDP1 470 ++#define SRST_EDP1_24M 471 ++#define SRST_M_I2S5_8CH_TX 472 ++#define SRST_H_I2S5_8CH 473 ++#define SRST_M_I2S6_8CH_TX 474 ++ ++#define SRST_M_I2S6_8CH_RX 475 ++#define SRST_H_I2S6_8CH 476 ++#define SRST_H_SPDIF3 477 ++#define SRST_M_SPDIF3 478 ++#define SRST_H_SPDIF4 479 ++#define SRST_M_SPDIF4 480 ++#define SRST_H_SPDIFRX0 481 ++#define SRST_M_SPDIFRX0 482 ++#define SRST_H_SPDIFRX1 483 ++#define SRST_M_SPDIFRX1 484 ++ ++#define SRST_H_SPDIFRX2 485 ++#define SRST_M_SPDIFRX2 486 ++#define SRST_LINKSYM_HDMITXPHY0 487 ++#define SRST_LINKSYM_HDMITXPHY1 488 ++#define SRST_VO1_BRIDGE0 489 ++#define SRST_VO1_BRIDGE1 490 ++ ++#define SRST_H_I2S9_8CH 491 ++#define SRST_M_I2S9_8CH_RX 492 ++#define SRST_H_I2S10_8CH 493 ++#define SRST_M_I2S10_8CH_RX 494 ++#define SRST_P_S_HDMIRX 495 ++ ++#define SRST_GPU 496 ++#define SRST_SYS_GPU 497 ++#define SRST_A_S_GPU_BIU 498 ++#define SRST_A_M0_GPU_BIU 499 ++#define SRST_A_M1_GPU_BIU 500 ++#define SRST_A_M2_GPU_BIU 501 ++#define SRST_A_M3_GPU_BIU 502 ++#define SRST_P_GPU_BIU 503 ++#define SRST_P_GPU_PVTM 504 ++ ++#define SRST_GPU_PVTM 505 ++#define SRST_P_GPU_GRF 506 ++#define SRST_GPU_PVTPLL 507 ++#define SRST_GPU_JTAG 508 ++ ++#define SRST_A_AV1_BIU 509 ++#define SRST_A_AV1 510 ++#define SRST_P_AV1_BIU 511 ++#define SRST_P_AV1 512 ++ ++#define SRST_A_DDR_BIU 513 ++#define SRST_A_DMA2DDR 514 ++#define SRST_A_DDR_SHAREMEM 515 ++#define SRST_A_DDR_SHAREMEM_BIU 516 ++#define SRST_A_CENTER_S200_BIU 517 ++#define SRST_A_CENTER_S400_BIU 518 ++#define SRST_H_AHB2APB 519 ++#define SRST_H_CENTER_BIU 520 ++#define SRST_F_DDR_CM0_CORE 521 ++ ++#define SRST_DDR_TIMER0 522 ++#define SRST_DDR_TIMER1 523 ++#define SRST_T_WDT_DDR 524 ++#define SRST_T_DDR_CM0_JTAG 525 ++#define SRST_P_CENTER_GRF 526 ++#define SRST_P_AHB2APB 527 ++#define SRST_P_WDT 528 ++#define SRST_P_TIMER 529 ++#define SRST_P_DMA2DDR 530 ++#define SRST_P_SHAREMEM 531 ++#define SRST_P_CENTER_BIU 532 ++#define SRST_P_CENTER_CHANNEL_BIU 533 ++ ++#define SRST_P_USBDPGRF0 534 ++#define SRST_P_USBDPPHY0 535 ++#define SRST_P_USBDPGRF1 536 ++#define SRST_P_USBDPPHY1 537 ++#define SRST_P_HDPTX0 538 ++#define SRST_P_HDPTX1 539 ++#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540 ++#define SRST_P_USB2PHY_U3_0_GRF0 541 ++#define SRST_P_USB2PHY_U3_1_GRF0 542 ++#define SRST_P_USB2PHY_U2_0_GRF0 543 ++#define SRST_P_USB2PHY_U2_1_GRF0 544 ++#define SRST_HDPTX0_ROPLL 545 ++#define SRST_HDPTX0_LCPLL 546 ++#define SRST_HDPTX0 547 ++#define SRST_HDPTX1_ROPLL 548 ++ ++#define SRST_HDPTX1_LCPLL 549 ++#define SRST_HDPTX1 550 ++#define SRST_HDPTX0_HDMIRXPHY_SET 551 ++#define SRST_USBDP_COMBO_PHY0 552 ++#define SRST_USBDP_COMBO_PHY0_LCPLL 553 ++#define SRST_USBDP_COMBO_PHY0_ROPLL 554 ++#define SRST_USBDP_COMBO_PHY0_PCS_HS 555 ++#define SRST_USBDP_COMBO_PHY1 556 ++#define SRST_USBDP_COMBO_PHY1_LCPLL 557 ++#define SRST_USBDP_COMBO_PHY1_ROPLL 558 ++#define SRST_USBDP_COMBO_PHY1_PCS_HS 559 ++#define SRST_HDMIHDP0 560 ++#define SRST_HDMIHDP1 561 ++ ++#define SRST_A_VO1USB_TOP_BIU 562 ++#define SRST_H_VO1USB_TOP_BIU 563 ++ ++#define SRST_H_SDIO_BIU 564 ++#define SRST_H_SDIO 565 ++#define SRST_SDIO 566 ++ ++#define SRST_H_RGA3_BIU 567 ++#define SRST_A_RGA3_BIU 568 ++#define SRST_H_RGA3_1 569 ++#define SRST_A_RGA3_1 570 ++#define SRST_RGA3_1_CORE 571 ++ ++#define SRST_REF_PIPE_PHY0 572 ++#define SRST_REF_PIPE_PHY1 573 ++#define SRST_REF_PIPE_PHY2 574 ++ ++#define SRST_P_PHPTOP_CRU 575 ++#define SRST_P_PCIE2_GRF0 576 ++#define SRST_P_PCIE2_GRF1 577 ++#define SRST_P_PCIE2_GRF2 578 ++#define SRST_P_PCIE2_PHY0 579 ++#define SRST_P_PCIE2_PHY1 580 ++#define SRST_P_PCIE2_PHY2 581 ++#define SRST_P_PCIE3_PHY 582 ++#define SRST_P_APB2ASB_SLV_CHIP_TOP 583 ++#define SRST_PCIE30_PHY 584 ++ ++#define SRST_H_PMU1_BIU 585 ++#define SRST_P_PMU1_BIU 586 ++#define SRST_H_PMU_CM0_BIU 587 ++#define SRST_F_PMU_CM0_CORE 588 ++#define SRST_T_PMU1_CM0_JTAG 589 ++ ++#define SRST_DDR_FAIL_SAFE 590 ++#define SRST_P_CRU_PMU1 591 ++#define SRST_P_PMU1_GRF 592 ++#define SRST_P_PMU1_IOC 593 ++#define SRST_P_PMU1WDT 594 ++#define SRST_T_PMU1WDT 595 ++#define SRST_P_PMU1TIMER 596 ++#define SRST_PMU1TIMER0 597 ++#define SRST_PMU1TIMER1 598 ++#define SRST_P_PMU1PWM 599 ++#define SRST_PMU1PWM 600 ++ ++#define SRST_P_I2C0 601 ++#define SRST_I2C0 602 ++#define SRST_S_UART0 603 ++#define SRST_P_UART0 604 ++#define SRST_H_I2S1_8CH 605 ++#define SRST_M_I2S1_8CH_TX 606 ++#define SRST_M_I2S1_8CH_RX 607 ++#define SRST_H_PDM0 608 ++#define SRST_PDM0 609 ++ ++#define SRST_H_VAD 610 ++#define SRST_HDPTX0_INIT 611 ++#define SRST_HDPTX0_CMN 612 ++#define SRST_HDPTX0_LANE 613 ++#define SRST_HDPTX1_INIT 614 ++ ++#define SRST_HDPTX1_CMN 615 ++#define SRST_HDPTX1_LANE 616 ++#define SRST_M_MIPI_DCPHY0 617 ++#define SRST_S_MIPI_DCPHY0 618 ++#define SRST_M_MIPI_DCPHY1 619 ++#define SRST_S_MIPI_DCPHY1 620 ++#define SRST_OTGPHY_U3_0 621 ++#define SRST_OTGPHY_U3_1 622 ++#define SRST_OTGPHY_U2_0 623 ++#define SRST_OTGPHY_U2_1 624 ++ ++#define SRST_P_PMU0GRF 625 ++#define SRST_P_PMU0IOC 626 ++#define SRST_P_GPIO0 627 ++#define SRST_GPIO0 628 ++ ++#define SRST_A_SECURE_NS_BIU 629 ++#define SRST_H_SECURE_NS_BIU 630 ++#define SRST_A_SECURE_S_BIU 631 ++#define SRST_H_SECURE_S_BIU 632 ++#define SRST_P_SECURE_S_BIU 633 ++#define SRST_CRYPTO_CORE 634 ++ ++#define SRST_CRYPTO_PKA 635 ++#define SRST_CRYPTO_RNG 636 ++#define SRST_A_CRYPTO 637 ++#define SRST_H_CRYPTO 638 ++#define SRST_KEYLADDER_CORE 639 ++#define SRST_KEYLADDER_RNG 640 ++#define SRST_A_KEYLADDER 641 ++#define SRST_H_KEYLADDER 642 ++#define SRST_P_OTPC_S 643 ++#define SRST_OTPC_S 644 ++#define SRST_WDT_S 645 ++ ++#define SRST_T_WDT_S 646 ++#define SRST_H_BOOTROM 647 ++#define SRST_A_DCF 648 ++#define SRST_P_DCF 649 ++#define SRST_H_BOOTROM_NS 650 ++#define SRST_P_KEYLADDER 651 ++#define SRST_H_TRNG_S 652 ++ ++#define SRST_H_TRNG_NS 653 ++#define SRST_D_SDMMC_BUFFER 654 ++#define SRST_H_SDMMC 655 ++#define SRST_H_SDMMC_BUFFER 656 ++#define SRST_SDMMC 657 ++#define SRST_P_TRNG_CHK 658 ++#define SRST_TRNG_S 659 ++ ++#endif diff --git a/target/linux/rockchip/patches-6.1/030-03-v6.2-clk-rockchip-add-register-offset-of-the-cores-select-pare.patch b/target/linux/rockchip/patches-6.1/030-03-v6.2-clk-rockchip-add-register-offset-of-the-cores-select-pare.patch new file mode 100644 index 0000000000..d5de4df0ab --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-03-v6.2-clk-rockchip-add-register-offset-of-the-cores-select-pare.patch @@ -0,0 +1,79 @@ +From cf87691f143e6cc5727767b02ec2be3725534a5d Mon Sep 17 00:00:00 2001 +From: Elaine Zhang +Date: Tue, 18 Oct 2022 17:14:02 +0200 +Subject: [PATCH] clk: rockchip: add register offset of the cores select parent + +The cores select parent register is special on RK3588. + +Signed-off-by: Elaine Zhang +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-cpu.c | 28 ++++++++++++++++++++-------- + drivers/clk/rockchip/clk.h | 3 +++ + 2 files changed, 23 insertions(+), 8 deletions(-) + +--- a/drivers/clk/rockchip/clk-cpu.c ++++ b/drivers/clk/rockchip/clk-cpu.c +@@ -166,10 +166,16 @@ static int rockchip_cpuclk_pre_rate_chan + } + } + /* select alternate parent */ +- writel(HIWORD_UPDATE(reg_data->mux_core_alt, +- reg_data->mux_core_mask, +- reg_data->mux_core_shift), +- cpuclk->reg_base + reg_data->core_reg[0]); ++ if (reg_data->mux_core_reg) ++ writel(HIWORD_UPDATE(reg_data->mux_core_alt, ++ reg_data->mux_core_mask, ++ reg_data->mux_core_shift), ++ cpuclk->reg_base + reg_data->mux_core_reg); ++ else ++ writel(HIWORD_UPDATE(reg_data->mux_core_alt, ++ reg_data->mux_core_mask, ++ reg_data->mux_core_shift), ++ cpuclk->reg_base + reg_data->core_reg[0]); + + spin_unlock_irqrestore(cpuclk->lock, flags); + return 0; +@@ -202,10 +208,16 @@ static int rockchip_cpuclk_post_rate_cha + * primary parent by the extra dividers that were needed for the alt. + */ + +- writel(HIWORD_UPDATE(reg_data->mux_core_main, +- reg_data->mux_core_mask, +- reg_data->mux_core_shift), +- cpuclk->reg_base + reg_data->core_reg[0]); ++ if (reg_data->mux_core_reg) ++ writel(HIWORD_UPDATE(reg_data->mux_core_main, ++ reg_data->mux_core_mask, ++ reg_data->mux_core_shift), ++ cpuclk->reg_base + reg_data->mux_core_reg); ++ else ++ writel(HIWORD_UPDATE(reg_data->mux_core_main, ++ reg_data->mux_core_mask, ++ reg_data->mux_core_shift), ++ cpuclk->reg_base + reg_data->core_reg[0]); + + /* remove dividers */ + for (i = 0; i < reg_data->num_cores; i++) { +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -389,6 +389,8 @@ struct rockchip_cpuclk_rate_table { + * @div_core_shift[]: cores divider offset used to divide the pll value + * @div_core_mask[]: cores divider mask + * @num_cores: number of cpu cores ++ * @mux_core_reg: register offset of the cores select parent ++ * @mux_core_alt: mux value to select alternate parent + * @mux_core_main: mux value to select main parent of core + * @mux_core_shift: offset of the core multiplexer + * @mux_core_mask: core multiplexer mask +@@ -398,6 +400,7 @@ struct rockchip_cpuclk_reg_data { + u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; + u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; + int num_cores; ++ int mux_core_reg; + u8 mux_core_alt; + u8 mux_core_main; + u8 mux_core_shift; diff --git a/target/linux/rockchip/patches-6.1/030-04-v6.2-clk-rockchip-add-pll-type-for-RK3588.patch b/target/linux/rockchip/patches-6.1/030-04-v6.2-clk-rockchip-add-pll-type-for-RK3588.patch new file mode 100644 index 0000000000..5603dbcbad --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-04-v6.2-clk-rockchip-add-pll-type-for-RK3588.patch @@ -0,0 +1,300 @@ +From 8f6594494b1cb0ad14493795b436413cfe64a0f8 Mon Sep 17 00:00:00 2001 +From: Elaine Zhang +Date: Tue, 18 Oct 2022 17:14:03 +0200 +Subject: [PATCH] clk: rockchip: add pll type for RK3588 + +Add RK3588 PLL support fully relying on lookup tables like +the other upstream supported rockchip platforms. + +Signed-off-by: Elaine Zhang +[rebase and modify code to avoid PLL parameter calculation] +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-pll.c | 218 ++++++++++++++++++++++++++++++++- + drivers/clk/rockchip/clk.h | 18 +++ + 2 files changed, 235 insertions(+), 1 deletion(-) + +--- a/drivers/clk/rockchip/clk-pll.c ++++ b/drivers/clk/rockchip/clk-pll.c +@@ -843,6 +843,213 @@ static const struct clk_ops rockchip_rk3 + }; + + /* ++ * PLL used in RK3588 ++ */ ++ ++#define RK3588_PLLCON(i) (i * 0x4) ++#define RK3588_PLLCON0_M_MASK 0x3ff ++#define RK3588_PLLCON0_M_SHIFT 0 ++#define RK3588_PLLCON1_P_MASK 0x3f ++#define RK3588_PLLCON1_P_SHIFT 0 ++#define RK3588_PLLCON1_S_MASK 0x7 ++#define RK3588_PLLCON1_S_SHIFT 6 ++#define RK3588_PLLCON2_K_MASK 0xffff ++#define RK3588_PLLCON2_K_SHIFT 0 ++#define RK3588_PLLCON1_PWRDOWN BIT(13) ++#define RK3588_PLLCON6_LOCK_STATUS BIT(15) ++ ++static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) ++{ ++ u32 pllcon; ++ int ret; ++ ++ /* ++ * Lock time typical 250, max 500 input clock cycles @24MHz ++ * So define a very safe maximum of 1000us, meaning 24000 cycles. ++ */ ++ ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), ++ pllcon, ++ pllcon & RK3588_PLLCON6_LOCK_STATUS, ++ 0, 1000); ++ if (ret) ++ pr_err("%s: timeout waiting for pll to lock\n", __func__); ++ ++ return ret; ++} ++ ++static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, ++ struct rockchip_pll_rate_table *rate) ++{ ++ u32 pllcon; ++ ++ pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); ++ rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK); ++ ++ pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); ++ rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK); ++ rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK); ++ ++ pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); ++ rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK); ++} ++ ++static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) ++{ ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ struct rockchip_pll_rate_table cur; ++ u64 rate64 = prate, postdiv; ++ ++ rockchip_rk3588_pll_get_params(pll, &cur); ++ ++ rate64 *= cur.m; ++ do_div(rate64, cur.p); ++ ++ if (cur.k) { ++ /* fractional mode */ ++ u64 frac_rate64 = prate * cur.k; ++ ++ postdiv = cur.p * 65535; ++ do_div(frac_rate64, postdiv); ++ rate64 += frac_rate64; ++ } ++ rate64 = rate64 >> cur.s; ++ ++ return (unsigned long)rate64; ++} ++ ++static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, ++ const struct rockchip_pll_rate_table *rate) ++{ ++ const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; ++ struct clk_mux *pll_mux = &pll->pll_mux; ++ struct rockchip_pll_rate_table cur; ++ int rate_change_remuxed = 0; ++ int cur_parent; ++ int ret; ++ ++ pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", ++ __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); ++ ++ rockchip_rk3588_pll_get_params(pll, &cur); ++ cur.rate = 0; ++ ++ if (pll->type == pll_rk3588) { ++ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); ++ if (cur_parent == PLL_MODE_NORM) { ++ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); ++ rate_change_remuxed = 1; ++ } ++ } ++ ++ /* set pll power down */ ++ writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, ++ RK3588_PLLCON1_PWRDOWN, 0), ++ pll->reg_base + RK3399_PLLCON(1)); ++ ++ /* update pll values */ ++ writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), ++ pll->reg_base + RK3399_PLLCON(0)); ++ ++ writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | ++ HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), ++ pll->reg_base + RK3399_PLLCON(1)); ++ ++ writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), ++ pll->reg_base + RK3399_PLLCON(2)); ++ ++ /* set pll power up */ ++ writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), ++ pll->reg_base + RK3588_PLLCON(1)); ++ ++ /* wait for the pll to lock */ ++ ret = rockchip_rk3588_pll_wait_lock(pll); ++ if (ret) { ++ pr_warn("%s: pll update unsuccessful, trying to restore old params\n", ++ __func__); ++ rockchip_rk3588_pll_set_params(pll, &cur); ++ } ++ ++ if ((pll->type == pll_rk3588) && rate_change_remuxed) ++ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); ++ ++ return ret; ++} ++ ++static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate, ++ unsigned long prate) ++{ ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ const struct rockchip_pll_rate_table *rate; ++ ++ pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", ++ __func__, __clk_get_name(hw->clk), drate, prate); ++ ++ /* Get required rate settings from table */ ++ rate = rockchip_get_pll_settings(pll, drate); ++ if (!rate) { ++ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, ++ drate, __clk_get_name(hw->clk)); ++ return -EINVAL; ++ } ++ ++ return rockchip_rk3588_pll_set_params(pll, rate); ++} ++ ++static int rockchip_rk3588_pll_enable(struct clk_hw *hw) ++{ ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ ++ writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), ++ pll->reg_base + RK3588_PLLCON(1)); ++ rockchip_rk3588_pll_wait_lock(pll); ++ ++ return 0; ++} ++ ++static void rockchip_rk3588_pll_disable(struct clk_hw *hw) ++{ ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ ++ writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0), ++ pll->reg_base + RK3588_PLLCON(1)); ++} ++ ++static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw) ++{ ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); ++ ++ return !(pllcon & RK3588_PLLCON1_PWRDOWN); ++} ++ ++static int rockchip_rk3588_pll_init(struct clk_hw *hw) ++{ ++ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); ++ ++ if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) ++ return 0; ++ ++ return 0; ++} ++ ++static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = { ++ .recalc_rate = rockchip_rk3588_pll_recalc_rate, ++ .enable = rockchip_rk3588_pll_enable, ++ .disable = rockchip_rk3588_pll_disable, ++ .is_enabled = rockchip_rk3588_pll_is_enabled, ++}; ++ ++static const struct clk_ops rockchip_rk3588_pll_clk_ops = { ++ .recalc_rate = rockchip_rk3588_pll_recalc_rate, ++ .round_rate = rockchip_pll_round_rate, ++ .set_rate = rockchip_rk3588_pll_set_rate, ++ .enable = rockchip_rk3588_pll_enable, ++ .disable = rockchip_rk3588_pll_disable, ++ .is_enabled = rockchip_rk3588_pll_is_enabled, ++ .init = rockchip_rk3588_pll_init, ++}; ++ ++/* + * Common registering of pll clocks + */ + +@@ -890,7 +1097,8 @@ struct clk *rockchip_clk_register_pll(st + if (pll_type == pll_rk3036 || + pll_type == pll_rk3066 || + pll_type == pll_rk3328 || +- pll_type == pll_rk3399) ++ pll_type == pll_rk3399 || ++ pll_type == pll_rk3588) + pll_mux->flags |= CLK_MUX_HIWORD_MASK; + + /* the actual muxing is xin24m, pll-output, xin32k */ +@@ -957,6 +1165,14 @@ struct clk *rockchip_clk_register_pll(st + else + init.ops = &rockchip_rk3399_pll_clk_ops; + break; ++ case pll_rk3588: ++ case pll_rk3588_core: ++ if (!pll->rate_table) ++ init.ops = &rockchip_rk3588_pll_clk_norate_ops; ++ else ++ init.ops = &rockchip_rk3588_pll_clk_ops; ++ init.flags = flags; ++ break; + default: + pr_warn("%s: Unknown pll type for pll clk %s\n", + __func__, name); +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -240,6 +240,8 @@ enum rockchip_pll_type { + pll_rk3066, + pll_rk3328, + pll_rk3399, ++ pll_rk3588, ++ pll_rk3588_core, + }; + + #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ +@@ -272,6 +274,15 @@ enum rockchip_pll_type { + .nb = _nb, \ + } + ++#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ ++{ \ ++ .rate = _rate##U, \ ++ .p = _p, \ ++ .m = _m, \ ++ .s = _s, \ ++ .k = _k, \ ++} ++ + /** + * struct rockchip_clk_provider - information about clock provider + * @reg_base: virtual address for the register base. +@@ -307,6 +318,13 @@ struct rockchip_pll_rate_table { + unsigned int dsmpd; + unsigned int frac; + }; ++ struct { ++ /* for RK3588 */ ++ unsigned int m; ++ unsigned int p; ++ unsigned int s; ++ unsigned int k; ++ }; + }; + }; + diff --git a/target/linux/rockchip/patches-6.1/030-05-v6.2-clk-rockchip-allow-additional-mux-options-for-cpu-clock.patch b/target/linux/rockchip/patches-6.1/030-05-v6.2-clk-rockchip-allow-additional-mux-options-for-cpu-clock.patch new file mode 100644 index 0000000000..788b1bb2a3 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-05-v6.2-clk-rockchip-allow-additional-mux-options-for-cpu-clock.patch @@ -0,0 +1,122 @@ +From 2004b7b1803719eaaaee5fa6b089b1699a65d31d Mon Sep 17 00:00:00 2001 +From: Elaine Zhang +Date: Tue, 18 Oct 2022 17:14:04 +0200 +Subject: [PATCH] clk: rockchip: allow additional mux options for cpu-clock + frequency changes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +In order to improve the main frequency of CPU, the clock path of CPU is +simplified as follows: + |--\ + | \ |--\ + --apll--|\ | \ | \ + | |--apll_core--| \ | \ + --24M---|/ |mux1 |--[gate]--|mux2|---clk_core + | / | / + --gpll--|\ | / |------| / + | |--gpll_core--| / | |--/ + --24M---|/ |--/ | + | + -------apll_directly--------------| + +When the CPU requests high frequency, we want to use MUX2 select the +"apll_directly". +At low frequencies use MUX1 to select “apll_core" and then MUX2 to +select "apll_core_gate". + +However, in this way, the CPU frequency conversion needs to be +in the following order: +1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core" +2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL +sets normal_mode +3. MUX1 select "apll_core", MUX2 select "apll_directly" + +So add pre_mux and post_mux options to cover this special requirements. + +Signed-off-by: Elaine Zhang +[rebase] +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-cpu.c | 41 ++++++++++++++++++++++++++++++++++ + drivers/clk/rockchip/clk.h | 2 ++ + 2 files changed, 43 insertions(+) + +--- a/drivers/clk/rockchip/clk-cpu.c ++++ b/drivers/clk/rockchip/clk-cpu.c +@@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers + } + } + ++static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk, ++ const struct rockchip_cpuclk_rate_table *rate) ++{ ++ int i; ++ ++ /* alternate parent is active now. set the pre_muxs */ ++ for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) { ++ const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; ++ ++ if (!clksel->reg) ++ break; ++ ++ pr_debug("%s: setting reg 0x%x to 0x%x\n", ++ __func__, clksel->reg, clksel->val); ++ writel(clksel->val, cpuclk->reg_base + clksel->reg); ++ } ++} ++ ++static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk, ++ const struct rockchip_cpuclk_rate_table *rate) ++{ ++ int i; ++ ++ /* alternate parent is active now. set the muxs */ ++ for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) { ++ const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; ++ ++ if (!clksel->reg) ++ break; ++ ++ pr_debug("%s: setting reg 0x%x to 0x%x\n", ++ __func__, clksel->reg, clksel->val); ++ writel(clksel->val, cpuclk->reg_base + clksel->reg); ++ } ++} ++ + static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, + struct clk_notifier_data *ndata) + { +@@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_chan + cpuclk->reg_base + reg_data->core_reg[i]); + } + } ++ ++ rockchip_cpuclk_set_pre_muxs(cpuclk, rate); ++ + /* select alternate parent */ + if (reg_data->mux_core_reg) + writel(HIWORD_UPDATE(reg_data->mux_core_alt, +@@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_cha + reg_data->mux_core_shift), + cpuclk->reg_base + reg_data->core_reg[0]); + ++ rockchip_cpuclk_set_post_muxs(cpuclk, rate); ++ + /* remove dividers */ + for (i = 0; i < reg_data->num_cores; i++) { + writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i], +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -399,6 +399,8 @@ struct rockchip_cpuclk_clksel { + struct rockchip_cpuclk_rate_table { + unsigned long prate; + struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; ++ struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; ++ struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; + }; + + /** diff --git a/target/linux/rockchip/patches-6.1/030-06-v6.2-clk-rockchip-simplify-rockchip_clk_add_lookup.patch b/target/linux/rockchip/patches-6.1/030-06-v6.2-clk-rockchip-simplify-rockchip_clk_add_lookup.patch new file mode 100644 index 0000000000..c9fcd10c58 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-06-v6.2-clk-rockchip-simplify-rockchip_clk_add_lookup.patch @@ -0,0 +1,72 @@ +From ff94c8660dac444081f2f650fae36a283c55b117 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 18 Oct 2022 17:14:05 +0200 +Subject: [PATCH] clk: rockchip: simplify rockchip_clk_add_lookup + +rockchip_clk_add_lookup is only called from within the file, +so it can be made static. The additional checks are removed +with the following reasoning: + +1. The data structure is initialized by rockchip_clk_init(), + which is called by all rockchip platforms before the clocks + are registered. Not doing so would result in an incomplete + clock tree at the moment, which is a fatal error. In other + parts of the kernel these kind of checks are usually + omitted, so this was done here. The alternative is adding + a pr_err to inform the kernel programmer adding a new platform + about his incorrect code. Apart from that we are also not + checking if the clock id is within the array boundings. + +2. While not used so far by any rockchip platform, 0 is a valid + clock identifier. To align rockchip closer to other ARM + platforms we will start using it with rk3588. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk.c | 14 ++++++-------- + drivers/clk/rockchip/clk.h | 2 -- + 2 files changed, 6 insertions(+), 10 deletions(-) + +--- a/drivers/clk/rockchip/clk.c ++++ b/drivers/clk/rockchip/clk.c +@@ -198,6 +198,12 @@ static void rockchip_fractional_approxim + clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n); + } + ++static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, ++ struct clk *clk, unsigned int id) ++{ ++ ctx->clk_data.clks[id] = clk; ++} ++ + static struct clk *rockchip_clk_register_frac_branch( + struct rockchip_clk_provider *ctx, const char *name, + const char *const *parent_names, u8 num_parents, +@@ -401,14 +407,6 @@ void rockchip_clk_of_add_provider(struct + } + EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider); + +-void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, +- struct clk *clk, unsigned int id) +-{ +- if (ctx->clk_data.clks && id) +- ctx->clk_data.clks[id] = clk; +-} +-EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup); +- + void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, + struct rockchip_pll_clock *list, + unsigned int nr_pll, int grf_lock_offset) +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -928,8 +928,6 @@ struct rockchip_clk_provider *rockchip_c + void __iomem *base, unsigned long nr_clks); + void rockchip_clk_of_add_provider(struct device_node *np, + struct rockchip_clk_provider *ctx); +-void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, +- struct clk *clk, unsigned int id); + void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk); diff --git a/target/linux/rockchip/patches-6.1/030-07-v6.2-clk-rockchip-add-lookup-table-support.patch b/target/linux/rockchip/patches-6.1/030-07-v6.2-clk-rockchip-add-lookup-table-support.patch new file mode 100644 index 0000000000..7373380847 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-07-v6.2-clk-rockchip-add-lookup-table-support.patch @@ -0,0 +1,130 @@ +From ada8f95ba04e8fe07289b7de157ae99bb96bc8cb Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 18 Oct 2022 17:14:06 +0200 +Subject: [PATCH] clk: rockchip: add lookup table support + +Add support for mapping reset IDs to register offsets +to support gapless continous platform reset IDs. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk.h | 21 +++++++++++++++------ + drivers/clk/rockchip/softrst.c | 34 +++++++++++++++++++++++++--------- + 2 files changed, 40 insertions(+), 15 deletions(-) + +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -958,15 +958,24 @@ struct clk *rockchip_clk_register_halfdi + spinlock_t *lock); + + #ifdef CONFIG_RESET_CONTROLLER +-void rockchip_register_softrst(struct device_node *np, +- unsigned int num_regs, +- void __iomem *base, u8 flags); ++void rockchip_register_softrst_lut(struct device_node *np, ++ const int *lookup_table, ++ unsigned int num_regs, ++ void __iomem *base, u8 flags); + #else +-static inline void rockchip_register_softrst(struct device_node *np, +- unsigned int num_regs, +- void __iomem *base, u8 flags) ++static inline void rockchip_register_softrst_lut(struct device_node *np, ++ const int *lookup_table, ++ unsigned int num_regs, ++ void __iomem *base, u8 flags) + { + } + #endif + ++static inline void rockchip_register_softrst(struct device_node *np, ++ unsigned int num_regs, ++ void __iomem *base, u8 flags) ++{ ++ return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); ++} ++ + #endif +--- a/drivers/clk/rockchip/softrst.c ++++ b/drivers/clk/rockchip/softrst.c +@@ -12,6 +12,7 @@ + + struct rockchip_softrst { + struct reset_controller_dev rcdev; ++ const int *lut; + void __iomem *reg_base; + int num_regs; + int num_per_reg; +@@ -25,8 +26,13 @@ static int rockchip_softrst_assert(struc + struct rockchip_softrst *softrst = container_of(rcdev, + struct rockchip_softrst, + rcdev); +- int bank = id / softrst->num_per_reg; +- int offset = id % softrst->num_per_reg; ++ int bank, offset; ++ ++ if (softrst->lut) ++ id = softrst->lut[id]; ++ ++ bank = id / softrst->num_per_reg; ++ offset = id % softrst->num_per_reg; + + if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { + writel(BIT(offset) | (BIT(offset) << 16), +@@ -52,8 +58,13 @@ static int rockchip_softrst_deassert(str + struct rockchip_softrst *softrst = container_of(rcdev, + struct rockchip_softrst, + rcdev); +- int bank = id / softrst->num_per_reg; +- int offset = id % softrst->num_per_reg; ++ int bank, offset; ++ ++ if (softrst->lut) ++ id = softrst->lut[id]; ++ ++ bank = id / softrst->num_per_reg; ++ offset = id % softrst->num_per_reg; + + if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { + writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); +@@ -77,9 +88,10 @@ static const struct reset_control_ops ro + .deassert = rockchip_softrst_deassert, + }; + +-void rockchip_register_softrst(struct device_node *np, +- unsigned int num_regs, +- void __iomem *base, u8 flags) ++void rockchip_register_softrst_lut(struct device_node *np, ++ const int *lookup_table, ++ unsigned int num_regs, ++ void __iomem *base, u8 flags) + { + struct rockchip_softrst *softrst; + int ret; +@@ -91,13 +103,17 @@ void rockchip_register_softrst(struct de + spin_lock_init(&softrst->lock); + + softrst->reg_base = base; ++ softrst->lut = lookup_table; + softrst->flags = flags; + softrst->num_regs = num_regs; + softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16 + : 32; + + softrst->rcdev.owner = THIS_MODULE; +- softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; ++ if (lookup_table) ++ softrst->rcdev.nr_resets = num_regs; ++ else ++ softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; + softrst->rcdev.ops = &rockchip_softrst_ops; + softrst->rcdev.of_node = np; + ret = reset_controller_register(&softrst->rcdev); +@@ -107,4 +123,4 @@ void rockchip_register_softrst(struct de + kfree(softrst); + } + }; +-EXPORT_SYMBOL_GPL(rockchip_register_softrst); ++EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut); diff --git a/target/linux/rockchip/patches-6.1/030-08-v6.2-clk-rockchip-add-clock-controller-for-the-RK3588.patch b/target/linux/rockchip/patches-6.1/030-08-v6.2-clk-rockchip-add-clock-controller-for-the-RK3588.patch new file mode 100644 index 0000000000..958a0d2cd9 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-08-v6.2-clk-rockchip-add-clock-controller-for-the-RK3588.patch @@ -0,0 +1,3516 @@ +From f1c506d152ff235ad621d3c25d061cb16da67214 Mon Sep 17 00:00:00 2001 +From: Elaine Zhang +Date: Tue, 18 Oct 2022 17:14:07 +0200 +Subject: [PATCH] clk: rockchip: add clock controller for the RK3588 + +Add full clock controller support RK3588. + +[rebase, integrate fixes from Wyon and Finley, add missing frequencies + to PLL lookup table, update commit message, add GATE_LINK clocks which + downstream handles in its own driver with one DT node per clock] + +Signed-off-by: Wyon Bi +Signed-off-by: Finley Xiao +Signed-off-by: Elaine Zhang +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com +[dropped module stuff after talking to Sebastian] +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/Kconfig | 8 + + drivers/clk/rockchip/Makefile | 1 + + drivers/clk/rockchip/clk-rk3588.c | 2533 +++++++++++++++++++++++++++++ + drivers/clk/rockchip/clk.h | 49 +- + drivers/clk/rockchip/rst-rk3588.c | 857 ++++++++++ + 5 files changed, 3447 insertions(+), 1 deletion(-) + create mode 100644 drivers/clk/rockchip/clk-rk3588.c + create mode 100644 drivers/clk/rockchip/rst-rk3588.c + +--- a/drivers/clk/rockchip/Kconfig ++++ b/drivers/clk/rockchip/Kconfig +@@ -99,4 +99,12 @@ config CLK_RK3568 + default y + help + Build the driver for RK3568 Clock Driver. ++ ++config CLK_RK3588 ++ bool "Rockchip RK3588 clock controller support" ++ depends on ARM64 || COMPILE_TEST ++ default y ++ help ++ Build the driver for RK3588 Clock Driver. ++ + endif +--- a/drivers/clk/rockchip/Makefile ++++ b/drivers/clk/rockchip/Makefile +@@ -28,3 +28,4 @@ obj-$(CONFIG_CLK_RK3328) += clk-r + obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o + obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o + obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o ++obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o +--- /dev/null ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -0,0 +1,2533 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. ++ * Author: Elaine Zhang ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "clk.h" ++ ++/* ++ * GATE with additional linked clock. Downstream enables the linked clock ++ * (via runtime PM) whenever the gate is enabled. The downstream implementation ++ * does this via separate clock nodes for each of the linked gate clocks, ++ * which leaks parts of the clock tree into DT. It is unclear why this is ++ * actually needed and things work without it for simple use cases. Thus ++ * the linked clock is ignored for now. ++ */ ++#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ ++ GATE(_id, cname, pname, f, o, b, gf) ++ ++ ++#define RK3588_GRF_SOC_STATUS0 0x600 ++#define RK3588_PHYREF_ALT_GATE 0xc38 ++ ++enum rk3588_plls { ++ b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, ++}; ++ ++static struct rockchip_pll_rate_table rk3588_pll_rates[] = { ++ /* _mhz, _p, _m, _s, _k */ ++ RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), ++ RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), ++ RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), ++ RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), ++ RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), ++ RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), ++ RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), ++ RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), ++ RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), ++ RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), ++ RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), ++ RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), ++ RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), ++ RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), ++ RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), ++ RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), ++ RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), ++ RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), ++ RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), ++ RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), ++ RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), ++ RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), ++ RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), ++ RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), ++ RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), ++ RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), ++ RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), ++ RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), ++ RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), ++ RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), ++ RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), ++ RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), ++ RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), ++ RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), ++ RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), ++ RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), ++ RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), ++ RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), ++ RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), ++ RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), ++ RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), ++ RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), ++ RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), ++ RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), ++ RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), ++ RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), ++ RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), ++ RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), ++ RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), ++ RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), ++ RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), ++ RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), ++ RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), ++ RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), ++ RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), ++ RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), ++ RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), ++ RK3588_PLL_RATE(900000000, 2, 300, 2, 0), ++ RK3588_PLL_RATE(850000000, 3, 425, 2, 0), ++ RK3588_PLL_RATE(816000000, 2, 272, 2, 0), ++ RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), ++ RK3588_PLL_RATE(786000000, 1, 131, 2, 0), ++ RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), ++ RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), ++ RK3588_PLL_RATE(600000000, 2, 200, 2, 0), ++ RK3588_PLL_RATE(594000000, 2, 198, 2, 0), ++ RK3588_PLL_RATE(408000000, 2, 272, 3, 0), ++ RK3588_PLL_RATE(312000000, 2, 208, 3, 0), ++ RK3588_PLL_RATE(216000000, 2, 288, 4, 0), ++ RK3588_PLL_RATE(100000000, 3, 400, 5, 0), ++ RK3588_PLL_RATE(96000000, 2, 256, 5, 0), ++ { /* sentinel */ }, ++}; ++ ++#define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3 ++#define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13 ++#define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3 ++#define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5 ++#define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f ++#define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 ++#define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 ++#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 ++#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 ++#define RK3588_CLK_DSU_SEL_DF_MASK 0x1 ++#define RK3588_CLK_DSU_SEL_DF_SHIFT 15 ++#define RK3588_CLK_DSU_DF_SRC_MASK 0x3 ++#define RK3588_CLK_DSU_DF_SRC_SHIFT 12 ++#define RK3588_CLK_DSU_DF_DIV_MASK 0x1f ++#define RK3588_CLK_DSU_DF_DIV_SHIFT 7 ++#define RK3588_ACLKM_DSU_DIV_MASK 0x1f ++#define RK3588_ACLKM_DSU_DIV_SHIFT 1 ++#define RK3588_ACLKS_DSU_DIV_MASK 0x1f ++#define RK3588_ACLKS_DSU_DIV_SHIFT 6 ++#define RK3588_ACLKMP_DSU_DIV_MASK 0x1f ++#define RK3588_ACLKMP_DSU_DIV_SHIFT 11 ++#define RK3588_PERIPH_DSU_DIV_MASK 0x1f ++#define RK3588_PERIPH_DSU_DIV_SHIFT 0 ++#define RK3588_ATCLK_DSU_DIV_MASK 0x1f ++#define RK3588_ATCLK_DSU_DIV_SHIFT 0 ++#define RK3588_GICCLK_DSU_DIV_MASK 0x1f ++#define RK3588_GICCLK_DSU_DIV_SHIFT 5 ++ ++#define RK3588_CORE_B0_SEL(_apllcore) \ ++{ \ ++ .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \ ++ .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ ++ RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ ++ HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ ++ RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ ++} ++ ++#define RK3588_CORE_B1_SEL(_apllcore) \ ++{ \ ++ .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \ ++ .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ ++ RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ ++} ++ ++#define RK3588_CORE_B2_SEL(_apllcore) \ ++{ \ ++ .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \ ++ .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ ++ RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ ++ HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ ++ RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ ++} ++ ++#define RK3588_CORE_B3_SEL(_apllcore) \ ++{ \ ++ .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \ ++ .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ ++ RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ ++} ++ ++#define RK3588_CORE_L_SEL0(_offs, _apllcore) \ ++{ \ ++ .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ ++ .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ ++ RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ ++ HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ ++ RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ ++} ++ ++#define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ ++{ \ ++ .reg = RK3588_DSU_CLKSEL_CON(0), \ ++ .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ ++ RK3588_CLK_DSU_DF_SRC_SHIFT) | \ ++ HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ ++ RK3588_CLK_DSU_DF_DIV_SHIFT), \ ++} ++ ++#define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ ++{ \ ++ .reg = RK3588_DSU_CLKSEL_CON(1), \ ++ .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \ ++ RK3588_ACLKM_DSU_DIV_SHIFT) | \ ++ HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \ ++ RK3588_ACLKMP_DSU_DIV_SHIFT) | \ ++ HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \ ++ RK3588_ACLKS_DSU_DIV_SHIFT), \ ++} ++ ++#define RK3588_CORE_L_SEL3(_periph) \ ++{ \ ++ .reg = RK3588_DSU_CLKSEL_CON(2), \ ++ .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \ ++ RK3588_PERIPH_DSU_DIV_SHIFT), \ ++} ++ ++#define RK3588_CORE_L_SEL4(_gicclk, _atclk) \ ++{ \ ++ .reg = RK3588_DSU_CLKSEL_CON(3), \ ++ .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \ ++ RK3588_GICCLK_DSU_DIV_SHIFT) | \ ++ HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \ ++ RK3588_ATCLK_DSU_DIV_SHIFT), \ ++} ++ ++#define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \ ++{ \ ++ .prate = _prate##U, \ ++ .pre_muxs = { \ ++ RK3588_CORE_B0_SEL(0), \ ++ RK3588_CORE_B1_SEL(0), \ ++ }, \ ++ .post_muxs = { \ ++ RK3588_CORE_B0_SEL(_apllcore), \ ++ RK3588_CORE_B1_SEL(_apllcore), \ ++ }, \ ++} ++ ++#define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \ ++{ \ ++ .prate = _prate##U, \ ++ .pre_muxs = { \ ++ RK3588_CORE_B2_SEL(0), \ ++ RK3588_CORE_B3_SEL(0), \ ++ }, \ ++ .post_muxs = { \ ++ RK3588_CORE_B2_SEL(_apllcore), \ ++ RK3588_CORE_B3_SEL(_apllcore), \ ++ }, \ ++} ++ ++#define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \ ++{ \ ++ .prate = _prate##U, \ ++ .pre_muxs = { \ ++ RK3588_CORE_L_SEL0(0, 0), \ ++ RK3588_CORE_L_SEL0(1, 0), \ ++ RK3588_CORE_L_SEL1(3, 2), \ ++ RK3588_CORE_L_SEL2(2, 3, 3), \ ++ RK3588_CORE_L_SEL3(4), \ ++ RK3588_CORE_L_SEL4(4, 4), \ ++ }, \ ++ .post_muxs = { \ ++ RK3588_CORE_L_SEL0(0, _apllcore), \ ++ RK3588_CORE_L_SEL0(1, _apllcore), \ ++ RK3588_CORE_L_SEL1(_seldsu, _divdsu), \ ++ }, \ ++} ++ ++static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { ++ RK3588_CPUB01CLK_RATE(2496000000, 1), ++ RK3588_CPUB01CLK_RATE(2400000000, 1), ++ RK3588_CPUB01CLK_RATE(2304000000, 1), ++ RK3588_CPUB01CLK_RATE(2208000000, 1), ++ RK3588_CPUB01CLK_RATE(2184000000, 1), ++ RK3588_CPUB01CLK_RATE(2088000000, 1), ++ RK3588_CPUB01CLK_RATE(2040000000, 1), ++ RK3588_CPUB01CLK_RATE(2016000000, 1), ++ RK3588_CPUB01CLK_RATE(1992000000, 1), ++ RK3588_CPUB01CLK_RATE(1896000000, 1), ++ RK3588_CPUB01CLK_RATE(1800000000, 1), ++ RK3588_CPUB01CLK_RATE(1704000000, 0), ++ RK3588_CPUB01CLK_RATE(1608000000, 0), ++ RK3588_CPUB01CLK_RATE(1584000000, 0), ++ RK3588_CPUB01CLK_RATE(1560000000, 0), ++ RK3588_CPUB01CLK_RATE(1536000000, 0), ++ RK3588_CPUB01CLK_RATE(1512000000, 0), ++ RK3588_CPUB01CLK_RATE(1488000000, 0), ++ RK3588_CPUB01CLK_RATE(1464000000, 0), ++ RK3588_CPUB01CLK_RATE(1440000000, 0), ++ RK3588_CPUB01CLK_RATE(1416000000, 0), ++ RK3588_CPUB01CLK_RATE(1392000000, 0), ++ RK3588_CPUB01CLK_RATE(1368000000, 0), ++ RK3588_CPUB01CLK_RATE(1344000000, 0), ++ RK3588_CPUB01CLK_RATE(1320000000, 0), ++ RK3588_CPUB01CLK_RATE(1296000000, 0), ++ RK3588_CPUB01CLK_RATE(1272000000, 0), ++ RK3588_CPUB01CLK_RATE(1248000000, 0), ++ RK3588_CPUB01CLK_RATE(1224000000, 0), ++ RK3588_CPUB01CLK_RATE(1200000000, 0), ++ RK3588_CPUB01CLK_RATE(1104000000, 0), ++ RK3588_CPUB01CLK_RATE(1008000000, 0), ++ RK3588_CPUB01CLK_RATE(912000000, 0), ++ RK3588_CPUB01CLK_RATE(816000000, 0), ++ RK3588_CPUB01CLK_RATE(696000000, 0), ++ RK3588_CPUB01CLK_RATE(600000000, 0), ++ RK3588_CPUB01CLK_RATE(408000000, 0), ++ RK3588_CPUB01CLK_RATE(312000000, 0), ++ RK3588_CPUB01CLK_RATE(216000000, 0), ++ RK3588_CPUB01CLK_RATE(96000000, 0), ++}; ++ ++static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = { ++ .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0), ++ .div_core_shift[0] = 8, ++ .div_core_mask[0] = 0x1f, ++ .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1), ++ .div_core_shift[1] = 0, ++ .div_core_mask[1] = 0x1f, ++ .num_cores = 2, ++ .mux_core_alt = 1, ++ .mux_core_main = 2, ++ .mux_core_shift = 6, ++ .mux_core_mask = 0x3, ++}; ++ ++static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = { ++ RK3588_CPUB23CLK_RATE(2496000000, 1), ++ RK3588_CPUB23CLK_RATE(2400000000, 1), ++ RK3588_CPUB23CLK_RATE(2304000000, 1), ++ RK3588_CPUB23CLK_RATE(2208000000, 1), ++ RK3588_CPUB23CLK_RATE(2184000000, 1), ++ RK3588_CPUB23CLK_RATE(2088000000, 1), ++ RK3588_CPUB23CLK_RATE(2040000000, 1), ++ RK3588_CPUB23CLK_RATE(2016000000, 1), ++ RK3588_CPUB23CLK_RATE(1992000000, 1), ++ RK3588_CPUB23CLK_RATE(1896000000, 1), ++ RK3588_CPUB23CLK_RATE(1800000000, 1), ++ RK3588_CPUB23CLK_RATE(1704000000, 0), ++ RK3588_CPUB23CLK_RATE(1608000000, 0), ++ RK3588_CPUB23CLK_RATE(1584000000, 0), ++ RK3588_CPUB23CLK_RATE(1560000000, 0), ++ RK3588_CPUB23CLK_RATE(1536000000, 0), ++ RK3588_CPUB23CLK_RATE(1512000000, 0), ++ RK3588_CPUB23CLK_RATE(1488000000, 0), ++ RK3588_CPUB23CLK_RATE(1464000000, 0), ++ RK3588_CPUB23CLK_RATE(1440000000, 0), ++ RK3588_CPUB23CLK_RATE(1416000000, 0), ++ RK3588_CPUB23CLK_RATE(1392000000, 0), ++ RK3588_CPUB23CLK_RATE(1368000000, 0), ++ RK3588_CPUB23CLK_RATE(1344000000, 0), ++ RK3588_CPUB23CLK_RATE(1320000000, 0), ++ RK3588_CPUB23CLK_RATE(1296000000, 0), ++ RK3588_CPUB23CLK_RATE(1272000000, 0), ++ RK3588_CPUB23CLK_RATE(1248000000, 0), ++ RK3588_CPUB23CLK_RATE(1224000000, 0), ++ RK3588_CPUB23CLK_RATE(1200000000, 0), ++ RK3588_CPUB23CLK_RATE(1104000000, 0), ++ RK3588_CPUB23CLK_RATE(1008000000, 0), ++ RK3588_CPUB23CLK_RATE(912000000, 0), ++ RK3588_CPUB23CLK_RATE(816000000, 0), ++ RK3588_CPUB23CLK_RATE(696000000, 0), ++ RK3588_CPUB23CLK_RATE(600000000, 0), ++ RK3588_CPUB23CLK_RATE(408000000, 0), ++ RK3588_CPUB23CLK_RATE(312000000, 0), ++ RK3588_CPUB23CLK_RATE(216000000, 0), ++ RK3588_CPUB23CLK_RATE(96000000, 0), ++}; ++ ++static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { ++ .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0), ++ .div_core_shift[0] = 8, ++ .div_core_mask[0] = 0x1f, ++ .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1), ++ .div_core_shift[1] = 0, ++ .div_core_mask[1] = 0x1f, ++ .num_cores = 2, ++ .mux_core_alt = 1, ++ .mux_core_main = 2, ++ .mux_core_shift = 6, ++ .mux_core_mask = 0x3, ++}; ++ ++static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { ++ RK3588_CPULCLK_RATE(2208000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(2184000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(2088000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(2040000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(2016000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(1992000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(1896000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(1800000000, 1, 3, 1), ++ RK3588_CPULCLK_RATE(1704000000, 0, 3, 1), ++ RK3588_CPULCLK_RATE(1608000000, 0, 3, 1), ++ RK3588_CPULCLK_RATE(1584000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1560000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1536000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1512000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1488000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1464000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1440000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1416000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1392000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1368000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1344000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1320000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1296000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1272000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1248000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1224000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1200000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1104000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(1008000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(912000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(816000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(696000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(600000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(408000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(312000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(216000000, 0, 2, 1), ++ RK3588_CPULCLK_RATE(96000000, 0, 2, 1), ++}; ++ ++static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = { ++ .core_reg[0] = RK3588_DSU_CLKSEL_CON(6), ++ .div_core_shift[0] = 0, ++ .div_core_mask[0] = 0x1f, ++ .core_reg[1] = RK3588_DSU_CLKSEL_CON(6), ++ .div_core_shift[1] = 7, ++ .div_core_mask[1] = 0x1f, ++ .core_reg[2] = RK3588_DSU_CLKSEL_CON(7), ++ .div_core_shift[2] = 0, ++ .div_core_mask[2] = 0x1f, ++ .core_reg[3] = RK3588_DSU_CLKSEL_CON(7), ++ .div_core_shift[3] = 7, ++ .div_core_mask[3] = 0x1f, ++ .num_cores = 4, ++ .mux_core_reg = RK3588_DSU_CLKSEL_CON(5), ++ .mux_core_alt = 1, ++ .mux_core_main = 2, ++ .mux_core_shift = 14, ++ .mux_core_mask = 0x3, ++}; ++ ++PNAME(mux_pll_p) = { "xin24m", "xin32k" }; ++PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" }; ++PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",}; ++PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",}; ++PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" }; ++PNAME(gpll_24m_p) = { "gpll", "xin24m" }; ++PNAME(gpll_aupll_p) = { "gpll", "aupll" }; ++PNAME(gpll_lpll_p) = { "gpll", "lpll" }; ++PNAME(gpll_cpll_p) = { "gpll", "cpll" }; ++PNAME(gpll_spll_p) = { "gpll", "spll" }; ++PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"}; ++PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"}; ++PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"}; ++PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"}; ++PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; ++PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; ++PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" }; ++PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" }; ++PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" }; ++PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" }; ++PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; ++PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" }; ++PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" }; ++PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" }; ++PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" }; ++PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" }; ++PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" }; ++PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; ++PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" }; ++PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; ++PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" }; ++PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; ++PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; ++PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; ++PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" }; ++PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" }; ++PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; ++PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; ++PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; ++PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" }; ++PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; ++PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" }; ++PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; ++PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; ++PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; ++PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; ++PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; ++PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; ++PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; ++PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; ++PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; ++PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; ++PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; ++PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; ++PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; ++PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; ++PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; ++PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; ++PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; ++PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; ++PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; ++PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; ++PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; ++PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; ++PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; ++PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; ++PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; ++PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; ++PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; ++PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; ++PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; ++PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; ++PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; ++PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" }; ++PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" }; ++PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" }; ++PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" }; ++PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" }; ++PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; ++PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; ++PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; ++PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; ++PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" }; ++PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" }; ++PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; ++PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" }; ++PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; ++PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; ++PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; ++PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" }; ++PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; ++PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; ++PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; ++PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; ++ ++#define MFLAGS CLK_MUX_HIWORD_MASK ++#define DFLAGS CLK_DIVIDER_HIWORD_MASK ++#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) ++ ++static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = ++ MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = ++ MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = ++ MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, ++ RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = ++ MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, ++ RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = ++ MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = ++ MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = ++ MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = ++ MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = ++ MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = ++ MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = ++ MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = ++ MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = ++ MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = ++ MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = ++ MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = ++ MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = ++ MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = ++ MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = ++ MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = ++ MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = ++ MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, ++ RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata = ++ MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(43), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata = ++ MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(45), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata = ++ MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(47), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata = ++ MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(49), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata = ++ MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(51), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata = ++ MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(53), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata = ++ MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(55), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata = ++ MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(57), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata = ++ MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(59), 0, 2, MFLAGS); ++ ++static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = ++ MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(140), 0, 1, MFLAGS); ++ ++static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { ++ [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), ++ RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), ++ [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), ++ RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), ++ [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), ++ RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), ++ [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, ++ 0, RK3588_PLL_CON(88), ++ RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates), ++ [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, ++ 0, RK3588_PLL_CON(96), ++ RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), ++ [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), ++ RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), ++ [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), ++ RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), ++ [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, ++ 0, RK3588_PLL_CON(120), ++ RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), ++ [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, ++ CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), ++ RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), ++}; ++ ++static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { ++ /* ++ * CRU Clock-Architecture ++ */ ++ /* fixed */ ++ FACTOR(0, "xin12m", "xin24m", 0, 1, 2), ++ ++ /* top */ ++ COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 0, GFLAGS), ++ COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 1, GFLAGS), ++ COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 2, GFLAGS), ++ COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 3, GFLAGS), ++ COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 4, GFLAGS), ++ COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 5, GFLAGS), ++ COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 6, GFLAGS), ++ COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 7, GFLAGS), ++ COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 8, GFLAGS), ++ COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 9, GFLAGS), ++ COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 10, GFLAGS), ++ COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0, ++ RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 11, GFLAGS), ++ COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 12, GFLAGS), ++ COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 13, GFLAGS), ++ COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 14, GFLAGS), ++ COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3588_CLKGATE_CON(0), 15, GFLAGS), ++ COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(1), 10, GFLAGS), ++ COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, ++ RK3588_CLKGATE_CON(1), 11, GFLAGS), ++ COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, ++ RK3588_CLKGATE_CON(1), 12, GFLAGS), ++ COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, ++ RK3588_CLKGATE_CON(1), 13, GFLAGS), ++ COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, ++ RK3588_CLKGATE_CON(1), 14, GFLAGS), ++ COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(1), 0, GFLAGS), ++ COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, ++ RK3588_CLKGATE_CON(1), 1, GFLAGS), ++ COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(1), 2, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(5), 9, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(5), 10, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(5), 11, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(5), 12, GFLAGS), ++ COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(5), 13, GFLAGS), ++ COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(5), 3, GFLAGS), ++ COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, ++ RK3588_CLKGATE_CON(5), 4, GFLAGS), ++ COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(5), 5, GFLAGS), ++ COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, ++ RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(5), 6, GFLAGS), ++ GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(3), 14, GFLAGS), ++ GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(4), 3, GFLAGS), ++ GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(1), 6, GFLAGS), ++ GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(1), 8, GFLAGS), ++ GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(5), 0, GFLAGS), ++ ++ /* bigcore0 */ ++ COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, ++ RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS), ++ GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0, ++ RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS), ++ GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0, ++ RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS), ++ GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0, ++ RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS), ++ ++ /* bigcore1 */ ++ COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS, ++ RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS), ++ GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0, ++ RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS), ++ GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0, ++ RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS), ++ GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0, ++ RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS), ++ ++ /* dsu */ ++ COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS), ++ COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS), ++ COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS), ++ COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS), ++ COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS), ++ COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS), ++ COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS), ++ COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS), ++ COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, ++ RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS), ++ COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS, ++ RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS), ++ COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS), ++ COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS, ++ RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS), ++ GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0, ++ RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS), ++ GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS), ++ GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL, ++ RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS), ++ GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED, ++ RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS), ++ GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED, ++ RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS), ++ GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0, ++ RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS), ++ GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0, ++ RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), ++ ++ /* audio */ ++ COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(7), 0, GFLAGS), ++ COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, ++ RK3588_CLKGATE_CON(7), 1, GFLAGS), ++ GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, ++ RK3588_CLKGATE_CON(7), 12, GFLAGS), ++ GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, ++ RK3588_CLKGATE_CON(7), 13, GFLAGS), ++ COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, ++ RK3588_CLKGATE_CON(7), 14, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(29), 0, ++ RK3588_CLKGATE_CON(7), 15, GFLAGS, ++ &rk3588_i2s2_2ch_fracmux), ++ GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, ++ RK3588_CLKGATE_CON(8), 0, GFLAGS), ++ MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), ++ ++ COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, ++ RK3588_CLKGATE_CON(8), 1, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(31), 0, ++ RK3588_CLKGATE_CON(8), 2, GFLAGS, ++ &rk3588_i2s3_2ch_fracmux), ++ GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, ++ RK3588_CLKGATE_CON(8), 3, GFLAGS), ++ GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0, ++ RK3588_CLKGATE_CON(8), 4, GFLAGS), ++ MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), ++ GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, ++ RK3588_CLKGATE_CON(7), 11, GFLAGS), ++ GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, ++ RK3588_CLKGATE_CON(7), 4, GFLAGS), ++ ++ COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, ++ RK3588_CLKGATE_CON(7), 5, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(25), 0, ++ RK3588_CLKGATE_CON(7), 6, GFLAGS, ++ &rk3588_i2s0_8ch_tx_fracmux), ++ GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, ++ RK3588_CLKGATE_CON(7), 7, GFLAGS), ++ ++ COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(7), 8, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(27), 0, ++ RK3588_CLKGATE_CON(7), 9, GFLAGS, ++ &rk3588_i2s0_8ch_rx_fracmux), ++ GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, ++ RK3588_CLKGATE_CON(7), 10, GFLAGS), ++ MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), ++ ++ GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, ++ RK3588_CLKGATE_CON(9), 6, GFLAGS), ++ COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(9), 7, GFLAGS), ++ ++ GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, ++ RK3588_CLKGATE_CON(8), 14, GFLAGS), ++ COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, ++ RK3588_CLKGATE_CON(8), 15, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(33), 0, ++ RK3588_CLKGATE_CON(9), 0, GFLAGS, ++ &rk3588_spdif0_fracmux), ++ GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, ++ RK3588_CLKGATE_CON(9), 1, GFLAGS), ++ ++ GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0, ++ RK3588_CLKGATE_CON(9), 2, GFLAGS), ++ COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(9), 3, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(35), 0, ++ RK3588_CLKGATE_CON(9), 4, GFLAGS, ++ &rk3588_spdif1_fracmux), ++ GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, ++ RK3588_CLKGATE_CON(9), 5, GFLAGS), ++ ++ COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(68), 0, GFLAGS), ++ COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, ++ RK3588_CLKGATE_CON(68), 3, GFLAGS), ++ ++ /* bus */ ++ COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(10), 0, GFLAGS), ++ ++ GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(16), 11, GFLAGS), ++ GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(16), 12, GFLAGS), ++ GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(16), 13, GFLAGS), ++ GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(19), 3, GFLAGS), ++ GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(19), 4, GFLAGS), ++ GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(19), 5, GFLAGS), ++ ++ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(15), 3, GFLAGS), ++ COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(59), 12, 2, MFLAGS, ++ RK3588_CLKGATE_CON(15), 4, GFLAGS), ++ GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, ++ RK3588_CLKGATE_CON(15), 5, GFLAGS), ++ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(15), 6, GFLAGS), ++ COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(59), 14, 2, MFLAGS, ++ RK3588_CLKGATE_CON(15), 7, GFLAGS), ++ GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, ++ RK3588_CLKGATE_CON(15), 8, GFLAGS), ++ GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(15), 9, GFLAGS), ++ COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(60), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(15), 10, GFLAGS), ++ GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, ++ RK3588_CLKGATE_CON(15), 11, GFLAGS), ++ ++ GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(15), 12, GFLAGS), ++ GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(15), 13, GFLAGS), ++ COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0, ++ RK3588_CLKSEL_CON(60), 2, 1, MFLAGS, ++ RK3588_CLKGATE_CON(15), 14, GFLAGS), ++ GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(15), 15, GFLAGS), ++ GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 0, GFLAGS), ++ GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 1, GFLAGS), ++ GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 2, GFLAGS), ++ GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 3, GFLAGS), ++ GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 4, GFLAGS), ++ GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 5, GFLAGS), ++ GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 6, GFLAGS), ++ GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 7, GFLAGS), ++ GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 8, GFLAGS), ++ GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 9, GFLAGS), ++ GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0, ++ RK3588_CLKGATE_CON(16), 10, GFLAGS), ++ ++ GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(15), 0, GFLAGS), ++ GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, ++ RK3588_CLKGATE_CON(15), 1, GFLAGS), ++ ++ GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(11), 8, GFLAGS), ++ COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(11), 9, GFLAGS), ++ GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(11), 10, GFLAGS), ++ COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(11), 11, GFLAGS), ++ GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(11), 12, GFLAGS), ++ COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(11), 13, GFLAGS), ++ ++ GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, ++ RK3588_CLKGATE_CON(17), 6, GFLAGS), ++ GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(17), 7, GFLAGS), ++ COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, ++ RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(17), 8, GFLAGS), ++ GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, ++ RK3588_CLKGATE_CON(10), 5, GFLAGS), ++ GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, ++ RK3588_CLKGATE_CON(10), 6, GFLAGS), ++ GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, ++ RK3588_CLKGATE_CON(10), 7, GFLAGS), ++ GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(10), 3, GFLAGS), ++ ++ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(16), 14, GFLAGS), ++ COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0, ++ RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS, ++ RK3588_CLKGATE_CON(16), 15, GFLAGS), ++ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(17), 0, GFLAGS), ++ COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0, ++ RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(17), 1, GFLAGS), ++ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(17), 2, GFLAGS), ++ COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0, ++ RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(17), 3, GFLAGS), ++ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(17), 4, GFLAGS), ++ COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0, ++ RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(17), 5, GFLAGS), ++ ++ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 8, GFLAGS), ++ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 9, GFLAGS), ++ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 10, GFLAGS), ++ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 11, GFLAGS), ++ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 12, GFLAGS), ++ GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 13, GFLAGS), ++ GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 14, GFLAGS), ++ GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(10), 15, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 6, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 0, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 7, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 1, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 8, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 2, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 9, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 3, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 10, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 4, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 11, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 5, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 12, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 6, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0, ++ RK3588_CLKSEL_CON(38), 13, 1, MFLAGS, ++ RK3588_CLKGATE_CON(11), 7, GFLAGS), ++ ++ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(18), 9, GFLAGS), ++ GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, ++ RK3588_CLKGATE_CON(18), 10, GFLAGS), ++ GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, ++ RK3588_CLKGATE_CON(18), 11, GFLAGS), ++ GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, ++ RK3588_CLKGATE_CON(18), 13, GFLAGS), ++ GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, ++ RK3588_CLKGATE_CON(18), 12, GFLAGS), ++ ++ GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(11), 14, GFLAGS), ++ COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, ++ RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS, ++ RK3588_CLKGATE_CON(11), 15, GFLAGS), ++ ++ GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(14), 6, GFLAGS), ++ GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(14), 7, GFLAGS), ++ GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(14), 8, GFLAGS), ++ GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(14), 9, GFLAGS), ++ GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(14), 10, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0, ++ RK3588_CLKSEL_CON(59), 2, 2, MFLAGS, ++ RK3588_CLKGATE_CON(14), 11, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0, ++ RK3588_CLKSEL_CON(59), 4, 2, MFLAGS, ++ RK3588_CLKGATE_CON(14), 12, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0, ++ RK3588_CLKSEL_CON(59), 6, 2, MFLAGS, ++ RK3588_CLKGATE_CON(14), 13, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0, ++ RK3588_CLKSEL_CON(59), 8, 2, MFLAGS, ++ RK3588_CLKGATE_CON(14), 14, GFLAGS), ++ COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0, ++ RK3588_CLKSEL_CON(59), 10, 2, MFLAGS, ++ RK3588_CLKGATE_CON(14), 15, GFLAGS), ++ ++ GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED, ++ RK3588_CLKGATE_CON(18), 6, GFLAGS), ++ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 0, GFLAGS), ++ COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0, ++ RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(12), 1, GFLAGS), ++ ++ GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 2, GFLAGS), ++ GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 3, GFLAGS), ++ GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 4, GFLAGS), ++ GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 5, GFLAGS), ++ GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 6, GFLAGS), ++ GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 7, GFLAGS), ++ GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 8, GFLAGS), ++ GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 9, GFLAGS), ++ GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(12), 10, GFLAGS), ++ ++ COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(12), 11, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(42), 0, ++ RK3588_CLKGATE_CON(12), 12, GFLAGS, ++ &rk3588_uart1_fracmux), ++ GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, ++ RK3588_CLKGATE_CON(12), 13, GFLAGS), ++ COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(12), 14, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(44), 0, ++ RK3588_CLKGATE_CON(12), 15, GFLAGS, ++ &rk3588_uart2_fracmux), ++ GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, ++ RK3588_CLKGATE_CON(13), 0, GFLAGS), ++ COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(13), 1, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(46), 0, ++ RK3588_CLKGATE_CON(13), 2, GFLAGS, ++ &rk3588_uart3_fracmux), ++ GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, ++ RK3588_CLKGATE_CON(13), 3, GFLAGS), ++ COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(13), 4, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(48), 0, ++ RK3588_CLKGATE_CON(13), 5, GFLAGS, ++ &rk3588_uart4_fracmux), ++ GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, ++ RK3588_CLKGATE_CON(13), 6, GFLAGS), ++ COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(13), 7, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(50), 0, ++ RK3588_CLKGATE_CON(13), 8, GFLAGS, ++ &rk3588_uart5_fracmux), ++ GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, ++ RK3588_CLKGATE_CON(13), 9, GFLAGS), ++ COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(13), 10, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(52), 0, ++ RK3588_CLKGATE_CON(13), 11, GFLAGS, ++ &rk3588_uart6_fracmux), ++ GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, ++ RK3588_CLKGATE_CON(13), 12, GFLAGS), ++ COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(13), 13, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(54), 0, ++ RK3588_CLKGATE_CON(13), 14, GFLAGS, ++ &rk3588_uart7_fracmux), ++ GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, ++ RK3588_CLKGATE_CON(13), 15, GFLAGS), ++ COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(14), 0, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(56), 0, ++ RK3588_CLKGATE_CON(14), 1, GFLAGS, ++ &rk3588_uart8_fracmux), ++ GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, ++ RK3588_CLKGATE_CON(14), 2, GFLAGS), ++ COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(14), 3, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(58), 0, ++ RK3588_CLKGATE_CON(14), 4, GFLAGS, ++ &rk3588_uart9_fracmux), ++ GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, ++ RK3588_CLKGATE_CON(14), 5, GFLAGS), ++ ++ /* center */ ++ COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(165), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(69), 0, GFLAGS), ++ COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(165), 2, 2, MFLAGS, ++ RK3588_CLKGATE_CON(69), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(165), 4, 2, MFLAGS, ++ RK3588_CLKGATE_CON(69), 2, GFLAGS), ++ COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, ++ RK3588_CLKGATE_CON(69), 3, GFLAGS), ++ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(69), 5, GFLAGS), ++ GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(69), 6, GFLAGS), ++ COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(165), 8, 2, MFLAGS, ++ RK3588_CLKGATE_CON(69), 8, GFLAGS), ++ COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, ++ CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(165), 10, 2, MFLAGS, ++ RK3588_CLKGATE_CON(69), 9, GFLAGS), ++ GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(69), 14, GFLAGS), ++ COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED, ++ RK3588_CLKSEL_CON(165), 12, 1, MFLAGS, ++ RK3588_CLKGATE_CON(69), 15, GFLAGS), ++ GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, ++ RK3588_CLKGATE_CON(70), 0, GFLAGS), ++ GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, ++ RK3588_CLKGATE_CON(70), 1, GFLAGS), ++ GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, ++ RK3588_CLKGATE_CON(70), 2, GFLAGS), ++ COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(70), 4, GFLAGS), ++ GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, ++ RK3588_CLKGATE_CON(70), 7, GFLAGS), ++ GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, ++ RK3588_CLKGATE_CON(70), 8, GFLAGS), ++ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(70), 9, GFLAGS), ++ GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(70), 10, GFLAGS), ++ ++ /* gpu */ ++ COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0, ++ RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(66), 1, GFLAGS), ++ GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0, ++ RK3588_CLKGATE_CON(66), 4, GFLAGS), ++ GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0, ++ RK3588_CLKGATE_CON(66), 6, GFLAGS), ++ COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0, ++ RK3588_CLKSEL_CON(159), 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(66), 7, GFLAGS), ++ GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, ++ RK3588_CLKGATE_CON(67), 0, GFLAGS), ++ GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0, ++ RK3588_CLKGATE_CON(67), 1, GFLAGS), ++ ++ /* isp1 */ ++ COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(26), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(67), 7, 2, MFLAGS, ++ RK3588_CLKGATE_CON(26), 1, GFLAGS), ++ COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(26), 2, GFLAGS), ++ GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0, ++ RK3588_CLKGATE_CON(26), 3, GFLAGS), ++ GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, ++ RK3588_CLKGATE_CON(26), 4, GFLAGS), ++ ++ /* npu */ ++ COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(29), 0, GFLAGS), ++ COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, ++ RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(29), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, ++ RK3588_CLKGATE_CON(29), 4, GFLAGS), ++ GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, ++ RK3588_CLKGATE_CON(27), 0, GFLAGS), ++ GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, ++ RK3588_CLKGATE_CON(27), 2, GFLAGS), ++ GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0, ++ RK3588_CLKGATE_CON(28), 0, GFLAGS), ++ GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0, ++ RK3588_CLKGATE_CON(28), 2, GFLAGS), ++ COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, ++ RK3588_CLKSEL_CON(74), 5, 2, MFLAGS, ++ RK3588_CLKGATE_CON(30), 1, GFLAGS), ++ GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, ++ RK3588_CLKGATE_CON(30), 3, GFLAGS), ++ COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, ++ RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3588_CLKGATE_CON(30), 5, GFLAGS), ++ GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0, ++ RK3588_CLKGATE_CON(29), 12, GFLAGS), ++ GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED, ++ RK3588_CLKGATE_CON(29), 13, GFLAGS), ++ GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, ++ RK3588_CLKGATE_CON(29), 14, GFLAGS), ++ GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0, ++ RK3588_CLKGATE_CON(29), 15, GFLAGS), ++ GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0, ++ RK3588_CLKGATE_CON(30), 6, GFLAGS), ++ GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, ++ RK3588_CLKGATE_CON(30), 8, GFLAGS), ++ GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, ++ RK3588_CLKGATE_CON(29), 6, GFLAGS), ++ COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, ++ RK3588_CLKSEL_CON(74), 3, 1, MFLAGS, ++ RK3588_CLKGATE_CON(29), 7, GFLAGS), ++ GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, ++ RK3588_CLKGATE_CON(29), 8, GFLAGS), ++ GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, ++ RK3588_CLKGATE_CON(29), 9, GFLAGS), ++ GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0, ++ RK3588_CLKGATE_CON(29), 10, GFLAGS), ++ GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, ++ RK3588_CLKGATE_CON(29), 11, GFLAGS), ++ ++ /* nvm */ ++ COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(31), 0, GFLAGS), ++ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(31), 1, GFLAGS), ++ GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, ++ RK3588_CLKGATE_CON(31), 5, GFLAGS), ++ COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, ++ RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS, ++ RK3588_CLKGATE_CON(31), 6, GFLAGS), ++ COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(31), 7, GFLAGS), ++ GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, ++ RK3588_CLKGATE_CON(31), 8, GFLAGS), ++ ++ COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, ++ RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, ++ RK3588_CLKGATE_CON(31), 9, GFLAGS), ++ ++ /* php */ ++ COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, ++ RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, ++ RK3588_CLKGATE_CON(34), 10, GFLAGS), ++ COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0, ++ RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, ++ RK3588_CLKGATE_CON(34), 11, GFLAGS), ++ COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS, ++ RK3588_CLKGATE_CON(35), 5, GFLAGS), ++ COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(35), 6, GFLAGS), ++ ++ COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(32), 6, GFLAGS), ++ COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, ++ RK3588_CLKGATE_CON(32), 7, GFLAGS), ++ COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(32), 0, GFLAGS), ++ GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, ++ RK3588_CLKGATE_CON(34), 6, GFLAGS), ++ GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, ++ RK3588_CLKGATE_CON(32), 8, GFLAGS), ++ GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, ++ RK3588_CLKGATE_CON(34), 7, GFLAGS), ++ GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(34), 8, GFLAGS), ++ GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(32), 13, GFLAGS), ++ GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(32), 14, GFLAGS), ++ GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(32), 15, GFLAGS), ++ GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 0, GFLAGS), ++ GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 1, GFLAGS), ++ GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, ++ RK3588_CLKGATE_CON(33), 2, GFLAGS), ++ GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, ++ RK3588_CLKGATE_CON(33), 3, GFLAGS), ++ GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, ++ RK3588_CLKGATE_CON(33), 4, GFLAGS), ++ GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, ++ RK3588_CLKGATE_CON(33), 5, GFLAGS), ++ GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, ++ RK3588_CLKGATE_CON(33), 6, GFLAGS), ++ GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 7, GFLAGS), ++ GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 8, GFLAGS), ++ GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 9, GFLAGS), ++ GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 10, GFLAGS), ++ GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 11, GFLAGS), ++ GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 12, GFLAGS), ++ GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 13, GFLAGS), ++ GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 14, GFLAGS), ++ GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0, ++ RK3588_CLKGATE_CON(33), 15, GFLAGS), ++ GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0, ++ RK3588_CLKGATE_CON(34), 0, GFLAGS), ++ GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0, ++ RK3588_CLKGATE_CON(34), 1, GFLAGS), ++ GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0, ++ RK3588_CLKGATE_CON(34), 2, GFLAGS), ++ GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0, ++ RK3588_CLKGATE_CON(34), 3, GFLAGS), ++ GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0, ++ RK3588_CLKGATE_CON(34), 4, GFLAGS), ++ GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0, ++ RK3588_CLKGATE_CON(34), 5, GFLAGS), ++ GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0, ++ RK3588_CLKGATE_CON(37), 0, GFLAGS), ++ GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0, ++ RK3588_CLKGATE_CON(37), 1, GFLAGS), ++ GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, ++ RK3588_CLKGATE_CON(37), 2, GFLAGS), ++ GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, ++ RK3588_CLKGATE_CON(32), 3, GFLAGS), ++ GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, ++ RK3588_CLKGATE_CON(32), 4, GFLAGS), ++ GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, ++ RK3588_CLKGATE_CON(32), 10, GFLAGS), ++ GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, ++ RK3588_CLKGATE_CON(32), 11, GFLAGS), ++ GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, ++ RK3588_CLKGATE_CON(37), 4, GFLAGS), ++ GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0, ++ RK3588_CLKGATE_CON(37), 5, GFLAGS), ++ GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, ++ RK3588_CLKGATE_CON(37), 6, GFLAGS), ++ GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, ++ RK3588_CLKGATE_CON(37), 7, GFLAGS), ++ GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, ++ RK3588_CLKGATE_CON(37), 8, GFLAGS), ++ GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, ++ RK3588_CLKGATE_CON(37), 9, GFLAGS), ++ COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(37), 10, GFLAGS), ++ COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS, ++ RK3588_CLKGATE_CON(37), 11, GFLAGS), ++ COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(37), 12, GFLAGS), ++ GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, ++ RK3588_CLKGATE_CON(35), 7, GFLAGS), ++ GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, ++ RK3588_CLKGATE_CON(35), 8, GFLAGS), ++ GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0, ++ RK3588_CLKGATE_CON(35), 9, GFLAGS), ++ COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, ++ RK3588_CLKGATE_CON(35), 10, GFLAGS), ++ GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, ++ RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), ++ GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, ++ RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS), ++ GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0, ++ RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS), ++ GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0, ++ RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), ++ ++ /* rga */ ++ COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(76), 6, GFLAGS), ++ COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(76), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, ++ RK3588_CLKGATE_CON(76), 1, GFLAGS), ++ GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, ++ RK3588_CLKGATE_CON(76), 4, GFLAGS), ++ GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, ++ RK3588_CLKGATE_CON(76), 5, GFLAGS), ++ ++ /* vdec */ ++ COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(89), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(40), 0, GFLAGS), ++ COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(40), 1, GFLAGS), ++ COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(40), 2, GFLAGS), ++ COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(40), 7, GFLAGS), ++ COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0, ++ RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(40), 8, GFLAGS), ++ COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(40), 9, GFLAGS), ++ COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(93), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(41), 0, GFLAGS), ++ COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, ++ RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(41), 1, GFLAGS), ++ COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(41), 6, GFLAGS), ++ COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0, ++ RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(41), 7, GFLAGS), ++ COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3588_CLKGATE_CON(41), 8, GFLAGS), ++ ++ /* sdio */ ++ COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(75), 0, GFLAGS), ++ COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, ++ RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, ++ RK3588_CLKGATE_CON(75), 3, GFLAGS), ++ MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), ++ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), ++ ++ /* usb */ ++ COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(42), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, ++ RK3588_CLKGATE_CON(42), 1, GFLAGS), ++ GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, ++ RK3588_CLKGATE_CON(42), 5, GFLAGS), ++ GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, ++ RK3588_CLKGATE_CON(42), 6, GFLAGS), ++ GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, ++ RK3588_CLKGATE_CON(42), 8, GFLAGS), ++ GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, ++ RK3588_CLKGATE_CON(42), 9, GFLAGS), ++ ++ /* vdpu */ ++ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(44), 0, GFLAGS), ++ COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, ++ RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, ++ RK3588_CLKGATE_CON(44), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, ++ RK3588_CLKGATE_CON(44), 2, GFLAGS), ++ COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(44), 3, GFLAGS), ++ GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(45), 4, GFLAGS), ++ COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3588_CLKGATE_CON(45), 6, GFLAGS), ++ GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(44), 11, GFLAGS), ++ GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(44), 13, GFLAGS), ++ GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(44), 15, GFLAGS), ++ GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(45), 1, GFLAGS), ++ GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(45), 3, GFLAGS), ++ GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(45), 7, GFLAGS), ++ GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(45), 8, GFLAGS), ++ COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(45), 9, GFLAGS), ++ GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(45), 10, GFLAGS), ++ GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(45), 11, GFLAGS), ++ COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, ++ RK3588_CLKGATE_CON(45), 12, GFLAGS), ++ GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, ++ RK3588_CLKGATE_CON(44), 9, GFLAGS), ++ ++ /* venc */ ++ COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(48), 0, GFLAGS), ++ COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, ++ RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(48), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(47), 0, GFLAGS), ++ COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, ++ RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(47), 1, GFLAGS), ++ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, ++ RK3588_CLKGATE_CON(47), 4, GFLAGS), ++ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, ++ RK3588_CLKGATE_CON(47), 5, GFLAGS), ++ COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, ++ RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(47), 6, GFLAGS), ++ COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, ++ RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(48), 6, GFLAGS), ++ ++ /* vi */ ++ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(49), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, ++ RK3588_CLKGATE_CON(49), 1, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, ++ RK3588_CLKGATE_CON(49), 2, GFLAGS), ++ COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, ++ RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, ++ RK3588_CLKGATE_CON(51), 10, GFLAGS), ++ GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, ++ RK3588_CLKGATE_CON(51), 11, GFLAGS), ++ GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0, ++ RK3588_CLKGATE_CON(51), 12, GFLAGS), ++ GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 4, GFLAGS), ++ GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 5, GFLAGS), ++ GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 6, GFLAGS), ++ GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 7, GFLAGS), ++ GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 8, GFLAGS), ++ GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 9, GFLAGS), ++ GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0, ++ RK3588_CLKGATE_CON(49), 14, GFLAGS), ++ GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0, ++ RK3588_CLKGATE_CON(49), 15, GFLAGS), ++ COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(50), 0, GFLAGS), ++ GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 1, GFLAGS), ++ GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0, ++ RK3588_CLKGATE_CON(50), 2, GFLAGS), ++ COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS, ++ RK3588_CLKGATE_CON(50), 3, GFLAGS), ++ COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0, ++ RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(49), 9, GFLAGS), ++ GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0, ++ RK3588_CLKGATE_CON(49), 10, GFLAGS), ++ GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0, ++ RK3588_CLKGATE_CON(49), 11, GFLAGS), ++ GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0, ++ RK3588_CLKGATE_CON(49), 12, GFLAGS), ++ GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, ++ RK3588_CLKGATE_CON(49), 13, GFLAGS), ++ COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(49), 6, GFLAGS), ++ GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, ++ RK3588_CLKGATE_CON(49), 7, GFLAGS), ++ GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, ++ RK3588_CLKGATE_CON(49), 8, GFLAGS), ++ ++ /* vo0 */ ++ COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(55), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(116), 6, 2, MFLAGS, ++ RK3588_CLKGATE_CON(55), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(116), 8, 2, MFLAGS, ++ RK3588_CLKGATE_CON(55), 2, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(116), 10, 2, MFLAGS, ++ RK3588_CLKGATE_CON(55), 3, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, ++ RK3588_CLKGATE_CON(55), 4, GFLAGS), ++ GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, ++ RK3588_CLKGATE_CON(56), 4, GFLAGS), ++ GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, ++ RK3588_CLKGATE_CON(56), 5, GFLAGS), ++ GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, ++ RK3588_CLKGATE_CON(56), 6, GFLAGS), ++ GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, ++ RK3588_CLKGATE_CON(56), 7, GFLAGS), ++ GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, ++ RK3588_CLKGATE_CON(56), 8, GFLAGS), ++ GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, ++ RK3588_CLKGATE_CON(56), 9, GFLAGS), ++ GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, ++ RK3588_CLKGATE_CON(55), 11, GFLAGS), ++ GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, ++ RK3588_CLKGATE_CON(55), 14, GFLAGS), ++ GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, ++ RK3588_CLKGATE_CON(56), 0, GFLAGS), ++ GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, ++ RK3588_CLKGATE_CON(56), 1, GFLAGS), ++ GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, ++ RK3588_CLKGATE_CON(55), 10, GFLAGS), ++ COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(56), 11, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(119), 0, ++ RK3588_CLKGATE_CON(56), 12, GFLAGS, ++ &rk3588_i2s4_8ch_tx_fracmux), ++ GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, ++ RK3588_CLKGATE_CON(56), 13, GFLAGS), ++ COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, ++ RK3588_CLKGATE_CON(56), 15, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(121), 0, ++ RK3588_CLKGATE_CON(57), 0, GFLAGS, ++ &rk3588_i2s8_8ch_tx_fracmux), ++ GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, ++ RK3588_CLKGATE_CON(57), 1, GFLAGS), ++ COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, ++ RK3588_CLKGATE_CON(57), 3, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(123), 0, ++ RK3588_CLKGATE_CON(57), 4, GFLAGS, ++ &rk3588_spdif2_dp0_fracmux), ++ GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, ++ RK3588_CLKGATE_CON(57), 5, GFLAGS), ++ GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, ++ RK3588_CLKGATE_CON(57), 6, GFLAGS), ++ COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(57), 8, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(125), 0, ++ RK3588_CLKGATE_CON(57), 9, GFLAGS, ++ &rk3588_spdif5_dp1_fracmux), ++ GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, ++ RK3588_CLKGATE_CON(57), 10, GFLAGS), ++ GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0, ++ RK3588_CLKGATE_CON(57), 11, GFLAGS), ++ COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0, ++ RK3588_CLKSEL_CON(117), 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(56), 2, GFLAGS), ++ COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0, ++ RK3588_CLKSEL_CON(117), 8, 8, DFLAGS, ++ RK3588_CLKGATE_CON(56), 3, GFLAGS), ++ ++ /* vo1 */ ++ COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(65), 9, GFLAGS), ++ COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, ++ RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(59), 0, GFLAGS), ++ COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3588_CLKGATE_CON(59), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, ++ RK3588_CLKGATE_CON(59), 2, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, ++ RK3588_CLKGATE_CON(59), 3, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, ++ RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, ++ RK3588_CLKGATE_CON(59), 4, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, ++ RK3588_CLKGATE_CON(59), 5, GFLAGS), ++ COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, ++ RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(52), 0, GFLAGS), ++ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, ++ RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, ++ RK3588_CLKGATE_CON(52), 1, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, ++ RK3588_CLKGATE_CON(52), 2, GFLAGS), ++ COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, ++ RK3588_CLKGATE_CON(52), 3, GFLAGS), ++ COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(74), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, ++ RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, ++ RK3588_CLKGATE_CON(74), 2, GFLAGS), ++ MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), ++ GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, ++ RK3588_CLKGATE_CON(62), 0, GFLAGS), ++ GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, ++ RK3588_CLKGATE_CON(62), 1, GFLAGS), ++ COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(140), 1, 2, MFLAGS, ++ RK3588_CLKGATE_CON(62), 2, GFLAGS), ++ GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0, ++ RK3588_CLKGATE_CON(62), 3, GFLAGS), ++ GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0, ++ RK3588_CLKGATE_CON(62), 4, GFLAGS), ++ COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0, ++ RK3588_CLKSEL_CON(140), 3, 2, MFLAGS, ++ RK3588_CLKGATE_CON(62), 5, GFLAGS), ++ GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, ++ RK3588_CLKGATE_CON(60), 4, GFLAGS), ++ GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, ++ RK3588_CLKGATE_CON(60), 7, GFLAGS), ++ GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, ++ RK3588_CLKGATE_CON(61), 9, GFLAGS), ++ GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0, ++ RK3588_CLKGATE_CON(61), 10, GFLAGS), ++ GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0, ++ RK3588_CLKGATE_CON(61), 11, GFLAGS), ++ COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS, ++ RK3588_CLKGATE_CON(61), 12, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(139), 0, ++ RK3588_CLKGATE_CON(61), 13, GFLAGS, ++ &rk3588_hdmirx_aud_fracmux), ++ GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0, ++ RK3588_CLKGATE_CON(61), 14, GFLAGS), ++ GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0, ++ RK3588_CLKGATE_CON(60), 11, GFLAGS), ++ COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS, ++ RK3588_CLKGATE_CON(60), 15, GFLAGS), ++ GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0, ++ RK3588_CLKGATE_CON(61), 0, GFLAGS), ++ GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0, ++ RK3588_CLKGATE_CON(61), 2, GFLAGS), ++ COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0, ++ RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS, ++ RK3588_CLKGATE_CON(61), 6, GFLAGS), ++ GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, ++ RK3588_CLKGATE_CON(61), 7, GFLAGS), ++ GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, ++ RK3588_CLKGATE_CON(60), 9, GFLAGS), ++ GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, ++ RK3588_CLKGATE_CON(60), 10, GFLAGS), ++ GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, ++ RK3588_CLKGATE_CON(59), 12, GFLAGS), ++ GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, ++ RK3588_CLKGATE_CON(59), 14, GFLAGS), ++ GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, ++ RK3588_CLKGATE_CON(59), 15, GFLAGS), ++ GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, ++ RK3588_CLKGATE_CON(65), 8, GFLAGS), ++ COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, ++ RK3588_CLKGATE_CON(65), 5, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(156), 0, ++ RK3588_CLKGATE_CON(65), 6, GFLAGS, ++ &rk3588_i2s10_8ch_rx_fracmux), ++ GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, ++ RK3588_CLKGATE_CON(65), 7, GFLAGS), ++ COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, ++ RK3588_CLKGATE_CON(60), 1, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(130), 0, ++ RK3588_CLKGATE_CON(60), 2, GFLAGS, ++ &rk3588_i2s7_8ch_rx_fracmux), ++ GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, ++ RK3588_CLKGATE_CON(60), 3, GFLAGS), ++ COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, ++ RK3588_CLKGATE_CON(65), 1, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(154), 0, ++ RK3588_CLKGATE_CON(65), 2, GFLAGS, ++ &rk3588_i2s9_8ch_rx_fracmux), ++ GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, ++ RK3588_CLKGATE_CON(65), 3, GFLAGS), ++ COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, ++ RK3588_CLKGATE_CON(62), 6, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, ++ RK3588_CLKSEL_CON(141), 0, ++ RK3588_CLKGATE_CON(62), 7, GFLAGS, ++ &rk3588_i2s5_8ch_tx_fracmux), ++ GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, ++ RK3588_CLKGATE_CON(62), 8, GFLAGS), ++ COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, ++ RK3588_CLKGATE_CON(62), 13, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(145), 0, ++ RK3588_CLKGATE_CON(62), 14, GFLAGS, ++ &rk3588_i2s6_8ch_tx_fracmux), ++ GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, ++ RK3588_CLKGATE_CON(62), 15, GFLAGS), ++ COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(63), 0, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, ++ RK3588_CLKSEL_CON(147), 0, ++ RK3588_CLKGATE_CON(63), 1, GFLAGS, ++ &rk3588_i2s6_8ch_rx_fracmux), ++ GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, ++ RK3588_CLKGATE_CON(63), 2, GFLAGS), ++ MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), ++ COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, ++ RK3588_CLKGATE_CON(63), 5, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(149), 0, ++ RK3588_CLKGATE_CON(63), 6, GFLAGS, ++ &rk3588_spdif3_fracmux), ++ GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, ++ RK3588_CLKGATE_CON(63), 7, GFLAGS), ++ COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(63), 9, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(151), 0, ++ RK3588_CLKGATE_CON(63), 10, GFLAGS, ++ &rk3588_spdif4_fracmux), ++ GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, ++ RK3588_CLKGATE_CON(63), 11, GFLAGS), ++ COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, ++ RK3588_CLKGATE_CON(63), 13, GFLAGS), ++ COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(63), 15, GFLAGS), ++ COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, ++ RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(64), 1, GFLAGS), ++ GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, ++ RK3588_CLKGATE_CON(73), 12, GFLAGS), ++ GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, ++ RK3588_CLKGATE_CON(73), 13, GFLAGS), ++ GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(72), 5, GFLAGS), ++ GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(72), 6, GFLAGS), ++ GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(72), 2, GFLAGS), ++ GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, ++ RK3588_CLKGATE_CON(72), 4, GFLAGS), ++ GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, ++ RK3588_CLKGATE_CON(52), 8, GFLAGS), ++ GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, ++ RK3588_CLKGATE_CON(52), 9, GFLAGS), ++ COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0, ++ RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(52), 10, GFLAGS), ++ COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, ++ RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, ++ RK3588_CLKGATE_CON(52), 11, GFLAGS), ++ COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_CLKGATE_CON(52), 12, GFLAGS), ++ COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, ++ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, ++ RK3588_CLKGATE_CON(52), 13, GFLAGS), ++ COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, ++ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3588_CLKSEL_CON(112), 9, 2, MFLAGS, ++ RK3588_CLKGATE_CON(53), 0, GFLAGS), ++ COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, ++ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, ++ RK3588_CLKSEL_CON(112), 11, 2, MFLAGS, ++ RK3588_CLKGATE_CON(53), 1, GFLAGS), ++ COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0, ++ RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(53), 2, GFLAGS), ++ GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0, ++ RK3588_CLKGATE_CON(53), 4, GFLAGS), ++ GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0, ++ RK3588_CLKGATE_CON(53), 5, GFLAGS), ++ COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0, ++ RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(53), 6, GFLAGS), ++ COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0, ++ RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS, ++ RK3588_CLKGATE_CON(53), 7, GFLAGS), ++ GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED, ++ RK3588_CLKGATE_CON(53), 8, GFLAGS), ++ GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, ++ RK3588_CLKGATE_CON(53), 10, GFLAGS), ++ GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, ++ RK3588_CLKGATE_CON(2), 8, GFLAGS), ++ GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, ++ RK3588_CLKGATE_CON(2), 15, GFLAGS), ++ ++ GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0, ++ RK3588_CLKGATE_CON(77), 0, GFLAGS), ++ GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0, ++ RK3588_CLKGATE_CON(77), 1, GFLAGS), ++ GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0, ++ RK3588_CLKGATE_CON(77), 2, GFLAGS), ++ COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0, ++ RK3588_CLKSEL_CON(176), 0, 6, DFLAGS, ++ RK3588_CLKGATE_CON(77), 3, GFLAGS), ++ COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0, ++ RK3588_CLKSEL_CON(176), 6, 6, DFLAGS, ++ RK3588_CLKGATE_CON(77), 4, GFLAGS), ++ COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0, ++ RK3588_CLKSEL_CON(177), 0, 6, DFLAGS, ++ RK3588_CLKGATE_CON(77), 5, GFLAGS), ++ MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(177), 6, 1, MFLAGS), ++ MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(177), 7, 1, MFLAGS), ++ MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT, ++ RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), ++ ++ /* pmu */ ++ COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, ++ RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), ++ COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, ++ RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, ++ RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, ++ RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), ++ COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, ++ RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), ++ COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, ++ RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), ++ COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, ++ RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), ++ GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, ++ RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), ++ COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, ++ RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), ++ GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, ++ RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), ++ GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, ++ RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS), ++ GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL, ++ RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS), ++ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, ++ RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS), ++ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, ++ RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS), ++ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0, ++ RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS), ++ COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0, ++ RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS), ++ GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0, ++ RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS), ++ COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0, ++ RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_PMU_CLKSEL_CON(6), 0, ++ RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, ++ &rk3588_i2s1_8ch_tx_fracmux), ++ GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, ++ RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS), ++ COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0, ++ RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", ++ CLK_SET_RATE_PARENT, ++ RK3588_PMU_CLKSEL_CON(8), 0, ++ RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, ++ &rk3588_i2s1_8ch_rx_fracmux), ++ GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, ++ RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), ++ MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, ++ RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), ++ GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, ++ RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), ++ GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, ++ RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS), ++ GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL, ++ RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS), ++ GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, ++ RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS), ++ COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0, ++ RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS), ++ GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, ++ RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS), ++ GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL, ++ RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS), ++ COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, ++ RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS), ++ GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED, ++ RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS), ++ GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0, ++ RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS), ++ COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0, ++ RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS), ++ GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0, ++ RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS), ++ GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0, ++ RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS), ++ COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0, ++ RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS), ++ GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0, ++ RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS), ++ GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0, ++ RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS), ++ COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0, ++ RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS), ++ COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, ++ RK3588_PMU_CLKSEL_CON(4), 0, ++ RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS, ++ &rk3588_uart0_fracmux), ++ GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, ++ RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS), ++ GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0, ++ RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS), ++ GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0, ++ RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS), ++ COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, ++ RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, ++ RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS), ++ COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0, ++ RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS), ++ COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, ++ CLK_IS_CRITICAL, ++ RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS), ++ COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, ++ CLK_IS_CRITICAL, ++ RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, ++ RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), ++ ++ GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0, ++ RK3588_PHYREF_ALT_GATE, 0, GFLAGS), ++ GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0, ++ RK3588_PHYREF_ALT_GATE, 1, GFLAGS), ++ GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0, ++ RK3588_PHYREF_ALT_GATE, 2, GFLAGS), ++ GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0, ++ RK3588_PHYREF_ALT_GATE, 3, GFLAGS), ++ ++ GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(63), 12, GFLAGS), ++ GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(63), 14, GFLAGS), ++ GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(64), 0, GFLAGS), ++ GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(63), 8, GFLAGS), ++ GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(63), 4, GFLAGS), ++ GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(63), 3, GFLAGS), ++ GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(62), 12, GFLAGS), ++ GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(65), 0, GFLAGS), ++ GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(60), 0, GFLAGS), ++ GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(65), 4, GFLAGS), ++ GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, ++ RK3588_CLKGATE_CON(60), 5, GFLAGS), ++ GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, ++ RK3588_CLKGATE_CON(60), 6, GFLAGS), ++ GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, ++ RK3588_CLKGATE_CON(57), 7, GFLAGS), ++ GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, ++ RK3588_CLKGATE_CON(57), 2, GFLAGS), ++ GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, ++ RK3588_CLKGATE_CON(56), 14, GFLAGS), ++ GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, ++ RK3588_CLKGATE_CON(56), 10, GFLAGS), ++ GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, ++ RK3588_CLKGATE_CON(55), 12, GFLAGS), ++ GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, ++ RK3588_CLKGATE_CON(55), 13, GFLAGS), ++ GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, ++ RK3588_CLKGATE_CON(48), 4, GFLAGS), ++ GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, ++ RK3588_CLKGATE_CON(48), 5, GFLAGS), ++ GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, ++ RK3588_CLKGATE_CON(44), 8, GFLAGS), ++ GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, ++ RK3588_CLKGATE_CON(45), 5, GFLAGS), ++ GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, ++ RK3588_CLKGATE_CON(44), 10, GFLAGS), ++ GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, ++ RK3588_CLKGATE_CON(44), 12, GFLAGS), ++ GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, ++ RK3588_CLKGATE_CON(44), 14, GFLAGS), ++ GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, ++ RK3588_CLKGATE_CON(45), 0, GFLAGS), ++ GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, ++ RK3588_CLKGATE_CON(45), 2, GFLAGS), ++ GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, ++ RK3588_CLKGATE_CON(42), 7, GFLAGS), ++ GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, ++ RK3588_CLKGATE_CON(42), 10, GFLAGS), ++ GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, ++ RK3588_CLKGATE_CON(42), 11, GFLAGS), ++ GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, ++ RK3588_CLKGATE_CON(42), 12, GFLAGS), ++ GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, ++ RK3588_CLKGATE_CON(42), 13, GFLAGS), ++ GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, ++ RK3588_CLKGATE_CON(42), 4, GFLAGS), ++ MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), ++ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), ++ GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, ++ RK3588_CLKGATE_CON(75), 2, GFLAGS), ++ GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, ++ RK3588_CLKGATE_CON(41), 2, GFLAGS), ++ GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, ++ RK3588_CLKGATE_CON(41), 3, GFLAGS), ++ GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, ++ RK3588_CLKGATE_CON(40), 3, GFLAGS), ++ GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, ++ RK3588_CLKGATE_CON(40), 4, GFLAGS), ++ GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, ++ RK3588_CLKGATE_CON(39), 0, GFLAGS), ++ GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, ++ RK3588_CLKGATE_CON(39), 1, GFLAGS), ++ GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, ++ RK3588_CLKGATE_CON(38), 3, GFLAGS), ++ GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, ++ RK3588_CLKGATE_CON(38), 4, GFLAGS), ++ GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, ++ RK3588_CLKGATE_CON(38), 5, GFLAGS), ++ GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, ++ RK3588_CLKGATE_CON(38), 6, GFLAGS), ++ GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, ++ RK3588_CLKGATE_CON(38), 7, GFLAGS), ++ GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, ++ RK3588_CLKGATE_CON(38), 8, GFLAGS), ++ GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, ++ RK3588_CLKGATE_CON(38), 9, GFLAGS), ++ GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, ++ RK3588_CLKGATE_CON(38), 13, GFLAGS), ++ GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, ++ RK3588_CLKGATE_CON(38), 14, GFLAGS), ++ GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, ++ RK3588_CLKGATE_CON(38), 15, GFLAGS), ++ GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, ++ RK3588_CLKGATE_CON(31), 10, GFLAGS), ++ GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, ++ RK3588_CLKGATE_CON(31), 11, GFLAGS), ++ GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, ++ RK3588_CLKGATE_CON(31), 4, GFLAGS), ++ GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, ++ RK3588_CLKGATE_CON(26), 5, GFLAGS), ++ GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, ++ RK3588_CLKGATE_CON(26), 7, GFLAGS), ++ GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, ++ RK3588_CLKGATE_CON(68), 5, GFLAGS), ++ GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, ++ RK3588_CLKGATE_CON(68), 2, GFLAGS), ++ ++ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), ++ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), ++ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), ++ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), ++ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), ++ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), ++ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), ++ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), ++ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), ++ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), ++ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), ++ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), ++ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), ++ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), ++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), ++ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), ++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), ++ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), ++ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), ++ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), ++}; ++ ++static void __init rk3588_clk_init(struct device_node *np) ++{ ++ struct rockchip_clk_provider *ctx; ++ void __iomem *reg_base; ++ ++ reg_base = of_iomap(np, 0); ++ if (!reg_base) { ++ pr_err("%s: could not map cru region\n", __func__); ++ return; ++ } ++ ++ ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); ++ if (IS_ERR(ctx)) { ++ pr_err("%s: rockchip clk init failed\n", __func__); ++ iounmap(reg_base); ++ return; ++ } ++ ++ rockchip_clk_register_plls(ctx, rk3588_pll_clks, ++ ARRAY_SIZE(rk3588_pll_clks), ++ RK3588_GRF_SOC_STATUS0); ++ ++ rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", ++ mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), ++ &rk3588_cpulclk_data, rk3588_cpulclk_rates, ++ ARRAY_SIZE(rk3588_cpulclk_rates)); ++ rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", ++ mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), ++ &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, ++ ARRAY_SIZE(rk3588_cpub0clk_rates)); ++ rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", ++ mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), ++ &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, ++ ARRAY_SIZE(rk3588_cpub1clk_rates)); ++ ++ rockchip_clk_register_branches(ctx, rk3588_clk_branches, ++ ARRAY_SIZE(rk3588_clk_branches)); ++ ++ rk3588_rst_init(np, reg_base); ++ ++ rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); ++ ++ rockchip_clk_of_add_provider(np, ctx); ++} ++ ++CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); ++ ++struct clk_rk3588_inits { ++ void (*inits)(struct device_node *np); ++}; ++ ++static const struct clk_rk3588_inits clk_3588_cru_init = { ++ .inits = rk3588_clk_init, ++}; ++ ++static const struct of_device_id clk_rk3588_match_table[] = { ++ { ++ .compatible = "rockchip,rk3588-cru", ++ .data = &clk_3588_cru_init, ++ }, ++ { } ++}; ++ ++static int __init clk_rk3588_probe(struct platform_device *pdev) ++{ ++ const struct clk_rk3588_inits *init_data; ++ struct device *dev = &pdev->dev; ++ ++ init_data = device_get_match_data(dev); ++ if (!init_data) ++ return -EINVAL; ++ ++ if (init_data->inits) ++ init_data->inits(dev->of_node); ++ ++ return 0; ++} ++ ++static struct platform_driver clk_rk3588_driver = { ++ .driver = { ++ .name = "clk-rk3588", ++ .of_match_table = clk_rk3588_match_table, ++ .suppress_bind_attrs = true, ++ }, ++}; ++builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe); +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -235,6 +235,51 @@ struct clk; + #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) + #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) + ++#define RK3588_PHP_CRU_BASE 0x8000 ++#define RK3588_PMU_CRU_BASE 0x30000 ++#define RK3588_BIGCORE0_CRU_BASE 0x50000 ++#define RK3588_BIGCORE1_CRU_BASE 0x52000 ++#define RK3588_DSU_CRU_BASE 0x58000 ++ ++#define RK3588_PLL_CON(x) RK2928_PLL_CON(x) ++#define RK3588_MODE_CON0 0x280 ++#define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280) ++#define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280) ++#define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280) ++#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) ++#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) ++#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) ++#define RK3588_GLB_CNT_TH 0xc00 ++#define RK3588_GLB_SRST_FST 0xc08 ++#define RK3588_GLB_SRST_SND 0xc0c ++#define RK3588_GLB_RST_CON 0xc10 ++#define RK3588_GLB_RST_ST 0xc04 ++#define RK3588_SDIO_CON0 0xC24 ++#define RK3588_SDIO_CON1 0xC28 ++#define RK3588_SDMMC_CON0 0xC30 ++#define RK3588_SDMMC_CON1 0xC34 ++ ++#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) ++#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) ++ ++#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) ++#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) ++#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) ++#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) ++ ++#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) ++#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) ++#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) ++#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) ++#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) ++#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) ++#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) ++#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) ++#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) ++#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) ++#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) ++#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) ++ + enum rockchip_pll_type { + pll_rk3036, + pll_rk3066, +@@ -394,7 +439,7 @@ struct rockchip_cpuclk_clksel { + u32 val; + }; + +-#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5 ++#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6 + #define ROCKCHIP_CPUCLK_MAX_CORES 4 + struct rockchip_cpuclk_rate_table { + unsigned long prate; +@@ -978,4 +1023,6 @@ static inline void rockchip_register_sof + return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); + } + ++void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); ++ + #endif +--- /dev/null ++++ b/drivers/clk/rockchip/rst-rk3588.c +@@ -0,0 +1,857 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2022 Collabora Ltd. ++ * Author: Sebastian Reichel ++ */ ++ ++#include ++#include ++#include ++#include "clk.h" ++ ++/* 0xFD7C0000 + 0x0A00 */ ++#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) ++ ++/* 0xFD7C8000 + 0x0A00 */ ++#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) ++ ++/* 0xFD7D0000 + 0x0A00 */ ++#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) ++ ++/* 0xFD7F0000 + 0x0A00 */ ++#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) ++ ++/* mapping table for reset ID to register offset */ ++static const int rk3588_register_offset[] = { ++ /* SOFTRST_CON01 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15), ++ ++ /* SOFTRST_CON02 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15), ++ ++ /* SOFTRST_CON03 */ ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15), ++ ++ /* SOFTRST_CON04 */ ++ RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11), ++ ++ /* SOFTRST_CON05 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15), ++ ++ /* SOFTRST_CON06 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1), ++ ++ /* SOFTRST_CON07 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13), ++ ++ /* SOFTRST_CON08 */ ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14), ++ ++ /* SOFTRST_CON09 */ ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7), ++ ++ /* SOFTRST_CON10 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15), ++ ++ /* SOFTRST_CON11 */ ++ RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14), ++ ++ /* SOFTRST_CON12 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13), ++ ++ /* SOFTRST_CON13 */ ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15), ++ ++ /* SOFTRST_CON14 */ ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15), ++ ++ /* SOFTRST_CON15 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15), ++ ++ /* SOFTRST_CON16 */ ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15), ++ ++ /* SOFTRST_CON17 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15), ++ ++ /* SOFTRST_CON18 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11), ++ ++ /* SOFTRST_CON19 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5), ++ ++ /* SOFTRST_CON20 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15), ++ ++ /* SOFTRST_CON21 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15), ++ ++ /* SOFTRST_CON22 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8), ++ ++ /* SOFTRST_CON23 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15), ++ ++ /* SOFTRST_CON24 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15), ++ ++ /* SOFTRST_CON25 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8), ++ ++ /* SOFTRST_CON26 */ ++ RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8), ++ ++ /* SOFTRST_CON27 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3), ++ ++ /* SOFTRST_CON28 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3), ++ ++ /* SOFTRST_CON29 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14), ++ ++ /* SOFTRST_CON30 */ ++ RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9), ++ ++ /* SOFTRST_CON31 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11), ++ ++ /* SOFTRST_CON32 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15), ++ ++ /* SOFTRST_CON33 */ ++ RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15), ++ ++ /* SOFTRST_CON34 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9), ++ ++ /* SOFTRST_CON35 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7), ++ ++ /* SOFTRST_CON37 */ ++ RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15), ++ ++ /* SOFTRST_CON40 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9), ++ ++ /* SOFTRST_CON41 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8), ++ ++ /* SOFTRST_CON42 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15), ++ ++ /* SOFTRST_CON43 */ ++ RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2), ++ ++ /* SOFTRST_CON44 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15), ++ ++ /* SOFTRST_CON45 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12), ++ ++ /* SOFTRST_CON47 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6), ++ ++ /* SOFTRST_CON48 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6), ++ ++ /* SOFTRST_CON49 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11), ++ ++ /* SOFTRST_CON50 */ ++ RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9), ++ ++ /* SOFTRST_CON51 */ ++ RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13), ++ ++ /* SOFTRST_CON52 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15), ++ ++ /* SOFTRST_CON53 */ ++ RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9), ++ ++ /* SOFTRST_CON55 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15), ++ ++ /* SOFTRST_CON56 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14), ++ ++ /* SOFTRST_CON57 */ ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11), ++ ++ /* SOFTRST_CON59 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13), ++ ++ /* SOFTRST_CON60 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11), ++ ++ /* SOFTRST_CON61 */ ++ RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11), ++ ++ /* SOFTRST_CON62 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15), ++ ++ /* SOFTRST_CON63 */ ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15), ++ ++ /* SOFTRST_CON64 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15), ++ ++ /* SOFTRST_CON65 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8), ++ ++ /* SOFTRST_CON66 */ ++ RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14), ++ RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15), ++ ++ /* SOFTRST_CON67 */ ++ RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4), ++ ++ /* SOFTRST_CON68 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5), ++ ++ /* SOFTRST_CON69 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13), ++ RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14), ++ ++ /* SOFTRST_CON70 */ ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0), ++ RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12), ++ ++ /* SOFTRST_CON72 */ ++ RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8), ++ RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9), ++ RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10), ++ RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11), ++ RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM ++ ++ /* SOFTRST_CON73 */ ++ RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM ++ RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12), ++ RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13), ++ ++ /* SOFTRST_CON74 */ ++ RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3), ++ ++ /* SOFTRST_CON75 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1), ++ RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3), ++ ++ /* SOFTRST_CON76 */ ++ RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3), ++ RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4), ++ RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5), ++ RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6), ++ ++ /* SOFTRST_CON77 */ ++ RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6), ++ RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7), ++ RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8), ++ ++ /* PHPTOPCRU_SOFTRST_CON00 */ ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9), ++ RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10), ++ ++ /* PMU1CRU_SOFTRST_CON00 */ ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14), ++ ++ /* PMU1CRU_SOFTRST_CON01 */ ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13), ++ ++ /* PMU1CRU_SOFTRST_CON02 */ ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15), ++ ++ /* PMU1CRU_SOFTRST_CON03 */ ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15), ++ ++ /* PMU1CRU_SOFTRST_CON04 */ ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10), ++ ++ /* PMU1CRU_SOFTRST_CON05 */ ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), ++ RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), ++ ++ /* SECURECRU_SOFTRST_CON00 */ ++ RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), ++ ++ /* SECURECRU_SOFTRST_CON01 */ ++ RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), ++ ++ /* SECURECRU_SOFTRST_CON02 */ ++ RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), ++ ++ /* SECURECRU_SOFTRST_CON03 */ ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), ++ RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), ++}; ++ ++void rk3588_rst_init(struct device_node *np, void __iomem *reg_base) ++{ ++ rockchip_register_softrst_lut(np, ++ rk3588_register_offset, ++ ARRAY_SIZE(rk3588_register_offset), ++ reg_base + RK3588_SOFTRST_CON(0), ++ ROCKCHIP_SOFTRST_HIWORD_MASK); ++} diff --git a/target/linux/rockchip/patches-6.1/030-09-v6.4-clk-rockchip-Remove-values-for-mmask-and-nmask-in-struct.patch b/target/linux/rockchip/patches-6.1/030-09-v6.4-clk-rockchip-Remove-values-for-mmask-and-nmask-in-struct.patch new file mode 100644 index 0000000000..ca0305ef75 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-09-v6.4-clk-rockchip-Remove-values-for-mmask-and-nmask-in-struct.patch @@ -0,0 +1,30 @@ +From 645a5198ddba6d6b2dea8346ca796064e931a0c3 Mon Sep 17 00:00:00 2001 +From: Christophe JAILLET +Date: Sun, 2 Apr 2023 11:42:06 +0200 +Subject: [PATCH] clk: rockchip: Remove values for mmask and nmask in struct + clk_fractional_divider + +Now that fractional_divider clk computes mmask and nmask when needed, there +is no more need to provide them explicitly anymore. + +Signed-off-by: Christophe JAILLET +Link: https://lore.kernel.org/r/58e1950566e40e2fbb31004baee57a164ca6a390.1680423909.git.christophe.jaillet@wanadoo.fr +Reviewed-by: Heiko Stuebner +Signed-off-by: Stephen Boyd +--- + drivers/clk/rockchip/clk.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/clk/rockchip/clk.c ++++ b/drivers/clk/rockchip/clk.c +@@ -245,10 +245,8 @@ static struct clk *rockchip_clk_register + div->reg = base + muxdiv_offset; + div->mshift = 16; + div->mwidth = 16; +- div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift; + div->nshift = 0; + div->nwidth = 16; +- div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift; + div->lock = lock; + div->approximation = rockchip_fractional_approximation; + div_ops = &clk_fractional_divider_ops; diff --git a/target/linux/rockchip/patches-6.1/030-10-v6.4-clk-rockchip-rk3588-make-gate-linked-clocks-critical.patch b/target/linux/rockchip/patches-6.1/030-10-v6.4-clk-rockchip-rk3588-make-gate-linked-clocks-critical.patch new file mode 100644 index 0000000000..6d984f1efc --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-10-v6.4-clk-rockchip-rk3588-make-gate-linked-clocks-critical.patch @@ -0,0 +1,148 @@ +From 64042c28c3bb6729df8e2fda89bc7ebbe3790907 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Mon, 3 Apr 2023 21:32:49 +0200 +Subject: [PATCH] clk: rockchip: rk3588: make gate linked clocks critical + +RK3588 has a couple of hardware blocks called Native Interface Unit +(NIU) that gate the clocks to devices behind them. Effectively this +means that some clocks require two parent clocks being enabled. +Downstream implemented this by using a separate clock driver +("clk-link") for them, which enables the second clock using PM +framework. + +In the upstream kernel we are currently missing support for the second +parent. The information about it is in the GATE_LINK() macro as +linkname, but that is not used. Thus the second parent clock is not +properly enabled. So far this did not really matter, since these clocks +are mostly required for the more advanced IP blocks, that are not yet +supported upstream. As this is about to change we need a fix. There +are three options available: + +1. Properly implement support for having two parent clocks in the + clock framework. +2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not + disabled. This wastes some power, but keeps the hack contained + within the clock driver. Going from this to the first solution + is easy once that has been implemented. +3. Enabling the extra clock in the consumer driver. This leaks some + implementation details into DT. + +This patch implements the second option as an intermediate solution +until the first one is available. I used an alias for CLK_IS_CRITICAL, +so that it's easy to see which clocks are not really critical once +the clock framework supports a better way to implement this. + +Tested-by: Vincent Legoll +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230403193250.108693-2-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------ + 1 file changed, 26 insertions(+), 16 deletions(-) + +--- a/drivers/clk/rockchip/clk-rk3588.c ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -13,15 +13,25 @@ + #include "clk.h" + + /* +- * GATE with additional linked clock. Downstream enables the linked clock +- * (via runtime PM) whenever the gate is enabled. The downstream implementation +- * does this via separate clock nodes for each of the linked gate clocks, +- * which leaks parts of the clock tree into DT. It is unclear why this is +- * actually needed and things work without it for simple use cases. Thus +- * the linked clock is ignored for now. ++ * Recent Rockchip SoCs have a new hardware block called Native Interface ++ * Unit (NIU), which gates clocks to devices behind them. These effectively ++ * need two parent clocks. ++ * ++ * Downstream enables the linked clock via runtime PM whenever the gate is ++ * enabled. This implementation uses separate clock nodes for each of the ++ * linked gate clocks, which leaks parts of the clock tree into DT. ++ * ++ * The GATE_LINK macro instead takes the second parent via 'linkname', but ++ * ignores the information. Once the clock framework is ready to handle it, the ++ * information should be passed on here. But since these clocks are required to ++ * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked ++ * clocks critical until a better solution is available. This will waste some ++ * power, but avoids leaking implementation details into DT or hanging the ++ * system. + */ + #define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ + GATE(_id, cname, pname, f, o, b, gf) ++#define RK3588_LINKED_CLK CLK_IS_CRITICAL + + + #define RK3588_GRF_SOC_STATUS0 0x600 +@@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588 + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, + RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, + RK3588_CLKGATE_CON(31), 0, GFLAGS), +- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, ++ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, + RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(31), 1, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, +@@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(42), 9, GFLAGS), + + /* vdpu */ +- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, ++ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, + RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(44), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, + RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 1, GFLAGS), +- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, ++ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, + RK3588_CLKGATE_CON(44), 2, GFLAGS), + COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, +@@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588 + COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, + RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3588_CLKGATE_CON(47), 1, GFLAGS), +- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, ++ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, + RK3588_CLKGATE_CON(47), 4, GFLAGS), +- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, ++ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, + RK3588_CLKGATE_CON(47), 5, GFLAGS), + COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, + RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, +@@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(48), 6, GFLAGS), + + /* vi */ +- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, ++ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, + RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(49), 0, GFLAGS), +- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, ++ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(49), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, +@@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588 + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, + RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(52), 0, GFLAGS), +- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, ++ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, + RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 1, GFLAGS), +- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, ++ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, + RK3588_CLKGATE_CON(52), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, +@@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588 + + GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), + GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), +- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), ++ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), + GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), + GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), diff --git a/target/linux/rockchip/patches-6.1/031-01-v6.2-mfd-rk808-Convert-to-i2c-s-.probe_new.patch b/target/linux/rockchip/patches-6.1/031-01-v6.2-mfd-rk808-Convert-to-i2c-s-.probe_new.patch new file mode 100644 index 0000000000..8072e6b47d --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-01-v6.2-mfd-rk808-Convert-to-i2c-s-.probe_new.patch @@ -0,0 +1,39 @@ +From 8416360935b9b632a517503eac6e320cbd5f310a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Fri, 18 Nov 2022 23:43:07 +0100 +Subject: [PATCH] mfd: rk808: Convert to i2c's .probe_new() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The probe function doesn't make use of the i2c_device_id * parameter so it +can be trivially converted. + +Signed-off-by: Uwe Kleine-König +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/20221118224540.619276-454-uwe@kleine-koenig.org +--- + drivers/mfd/rk808.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/drivers/mfd/rk808.c ++++ b/drivers/mfd/rk808.c +@@ -640,8 +640,7 @@ static const struct of_device_id rk808_o + }; + MODULE_DEVICE_TABLE(of, rk808_of_match); + +-static int rk808_probe(struct i2c_client *client, +- const struct i2c_device_id *id) ++static int rk808_probe(struct i2c_client *client) + { + struct device_node *np = client->dev.of_node; + struct rk808 *rk808; +@@ -861,7 +860,7 @@ static struct i2c_driver rk808_i2c_drive + .of_match_table = rk808_of_match, + .pm = &rk8xx_pm_ops, + }, +- .probe = rk808_probe, ++ .probe_new = rk808_probe, + .remove = rk808_remove, + .shutdown = rk8xx_shutdown, + }; diff --git a/target/linux/rockchip/patches-6.1/031-02-v6.2-mfd-rk808-Permit-having-multiple-PMIC-instances.patch b/target/linux/rockchip/patches-6.1/031-02-v6.2-mfd-rk808-Permit-having-multiple-PMIC-instances.patch new file mode 100644 index 0000000000..b99f17c053 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-02-v6.2-mfd-rk808-Permit-having-multiple-PMIC-instances.patch @@ -0,0 +1,96 @@ +From 3633daacea2e54bf991d2f6b871efe9f83a0cac8 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Mon, 31 Oct 2022 17:05:07 +0100 +Subject: [PATCH] mfd: rk808: Permit having multiple PMIC instances + +This set each cells id to PLATFORM_DEVID_NONE to allow multiple +instances of each cell in case multiple PMICs handled by the rk808 +driver are probed. + +This fixes probing a RK818 and a RK817 on the Odroid Go Ultra +devices. + +Signed-off-by: Neil Armstrong +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/20221025-rk808-multi-v2-0-d292d51ada81@linaro.org +--- + drivers/mfd/rk808.c | 26 ++++++++++++++++---------- + 1 file changed, 16 insertions(+), 10 deletions(-) + +--- a/drivers/mfd/rk808.c ++++ b/drivers/mfd/rk808.c +@@ -137,58 +137,64 @@ static const struct resource rk817_charg + }; + + static const struct mfd_cell rk805s[] = { +- { .name = "rk808-clkout", }, +- { .name = "rk808-regulator", }, +- { .name = "rk805-pinctrl", }, ++ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, }, + { + .name = "rk808-rtc", + .num_resources = ARRAY_SIZE(rtc_resources), + .resources = &rtc_resources[0], ++ .id = PLATFORM_DEVID_NONE, + }, + { .name = "rk805-pwrkey", + .num_resources = ARRAY_SIZE(rk805_key_resources), + .resources = &rk805_key_resources[0], ++ .id = PLATFORM_DEVID_NONE, + }, + }; + + static const struct mfd_cell rk808s[] = { +- { .name = "rk808-clkout", }, +- { .name = "rk808-regulator", }, ++ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, + { + .name = "rk808-rtc", + .num_resources = ARRAY_SIZE(rtc_resources), + .resources = rtc_resources, ++ .id = PLATFORM_DEVID_NONE, + }, + }; + + static const struct mfd_cell rk817s[] = { +- { .name = "rk808-clkout",}, +- { .name = "rk808-regulator",}, ++ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, + { + .name = "rk805-pwrkey", + .num_resources = ARRAY_SIZE(rk817_pwrkey_resources), + .resources = &rk817_pwrkey_resources[0], ++ .id = PLATFORM_DEVID_NONE, + }, + { + .name = "rk808-rtc", + .num_resources = ARRAY_SIZE(rk817_rtc_resources), + .resources = &rk817_rtc_resources[0], ++ .id = PLATFORM_DEVID_NONE, + }, +- { .name = "rk817-codec",}, ++ { .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, }, + { + .name = "rk817-charger", + .num_resources = ARRAY_SIZE(rk817_charger_resources), + .resources = &rk817_charger_resources[0], ++ .id = PLATFORM_DEVID_NONE, + }, + }; + + static const struct mfd_cell rk818s[] = { +- { .name = "rk808-clkout", }, +- { .name = "rk808-regulator", }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, + { + .name = "rk808-rtc", + .num_resources = ARRAY_SIZE(rtc_resources), + .resources = rtc_resources, ++ .id = PLATFORM_DEVID_NONE, + }, + }; + diff --git a/target/linux/rockchip/patches-6.1/031-03-v6.2-rtc-rk808-reduce-struct-rk808-usage.patch b/target/linux/rockchip/patches-6.1/031-03-v6.2-rtc-rk808-reduce-struct-rk808-usage.patch new file mode 100644 index 0000000000..dac104f31e --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-03-v6.2-rtc-rk808-reduce-struct-rk808-usage.patch @@ -0,0 +1,215 @@ +From 2e830ccc21eb67a4c2490279d907e5e9199e5156 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Oct 2022 22:42:41 +0200 +Subject: [PATCH] rtc: rk808: reduce 'struct rk808' usage + +Reduce usage of 'struct rk808' (driver data of the parent MFD), so +that only the chip variant field is still being accessed directly. +This allows restructuring the MFD driver to support SPI based +PMICs. + +Acked-by: Alexandre Belloni +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221020204251.108565-4-sebastian.reichel@collabora.com +Signed-off-by: Alexandre Belloni +--- + drivers/rtc/rtc-rk808.c | 47 ++++++++++++++++++----------------------- + 1 file changed, 20 insertions(+), 27 deletions(-) + +--- a/drivers/rtc/rtc-rk808.c ++++ b/drivers/rtc/rtc-rk808.c +@@ -14,7 +14,6 @@ + #include + #include + #include +-#include + + /* RTC_CTRL_REG bitfields */ + #define BIT_RTC_CTRL_REG_STOP_RTC_M BIT(0) +@@ -51,7 +50,7 @@ struct rk_rtc_compat_reg { + }; + + struct rk808_rtc { +- struct rk808 *rk808; ++ struct regmap *regmap; + struct rtc_device *rtc; + struct rk_rtc_compat_reg *creg; + int irq; +@@ -97,12 +96,11 @@ static void gregorian_to_rockchip(struct + static int rk808_rtc_readtime(struct device *dev, struct rtc_time *tm) + { + struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev); +- struct rk808 *rk808 = rk808_rtc->rk808; + u8 rtc_data[NUM_TIME_REGS]; + int ret; + + /* Force an update of the shadowed registers right now */ +- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, ++ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, + BIT_RTC_CTRL_REG_RTC_GET_TIME, + BIT_RTC_CTRL_REG_RTC_GET_TIME); + if (ret) { +@@ -116,7 +114,7 @@ static int rk808_rtc_readtime(struct dev + * 32khz. If we clear the GET_TIME bit here, the time of i2c transfer + * certainly more than 31.25us: 16 * 2.5us at 400kHz bus frequency. + */ +- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, ++ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, + BIT_RTC_CTRL_REG_RTC_GET_TIME, + 0); + if (ret) { +@@ -124,7 +122,7 @@ static int rk808_rtc_readtime(struct dev + return ret; + } + +- ret = regmap_bulk_read(rk808->regmap, rk808_rtc->creg->seconds_reg, ++ ret = regmap_bulk_read(rk808_rtc->regmap, rk808_rtc->creg->seconds_reg, + rtc_data, NUM_TIME_REGS); + if (ret) { + dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret); +@@ -148,7 +146,6 @@ static int rk808_rtc_readtime(struct dev + static int rk808_rtc_set_time(struct device *dev, struct rtc_time *tm) + { + struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev); +- struct rk808 *rk808 = rk808_rtc->rk808; + u8 rtc_data[NUM_TIME_REGS]; + int ret; + +@@ -163,7 +160,7 @@ static int rk808_rtc_set_time(struct dev + rtc_data[6] = bin2bcd(tm->tm_wday); + + /* Stop RTC while updating the RTC registers */ +- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, ++ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, + BIT_RTC_CTRL_REG_STOP_RTC_M, + BIT_RTC_CTRL_REG_STOP_RTC_M); + if (ret) { +@@ -171,14 +168,14 @@ static int rk808_rtc_set_time(struct dev + return ret; + } + +- ret = regmap_bulk_write(rk808->regmap, rk808_rtc->creg->seconds_reg, ++ ret = regmap_bulk_write(rk808_rtc->regmap, rk808_rtc->creg->seconds_reg, + rtc_data, NUM_TIME_REGS); + if (ret) { + dev_err(dev, "Failed to bull write rtc_data: %d\n", ret); + return ret; + } + /* Start RTC again */ +- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, ++ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, + BIT_RTC_CTRL_REG_STOP_RTC_M, 0); + if (ret) { + dev_err(dev, "Failed to update RTC control: %d\n", ret); +@@ -191,12 +188,11 @@ static int rk808_rtc_set_time(struct dev + static int rk808_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) + { + struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev); +- struct rk808 *rk808 = rk808_rtc->rk808; + u8 alrm_data[NUM_ALARM_REGS]; + uint32_t int_reg; + int ret; + +- ret = regmap_bulk_read(rk808->regmap, ++ ret = regmap_bulk_read(rk808_rtc->regmap, + rk808_rtc->creg->alarm_seconds_reg, + alrm_data, NUM_ALARM_REGS); + if (ret) { +@@ -212,7 +208,7 @@ static int rk808_rtc_readalarm(struct de + alrm->time.tm_year = (bcd2bin(alrm_data[5] & YEARS_REG_MSK)) + 100; + rockchip_to_gregorian(&alrm->time); + +- ret = regmap_read(rk808->regmap, rk808_rtc->creg->int_reg, &int_reg); ++ ret = regmap_read(rk808_rtc->regmap, rk808_rtc->creg->int_reg, &int_reg); + if (ret) { + dev_err(dev, "Failed to read RTC INT REG: %d\n", ret); + return ret; +@@ -228,10 +224,9 @@ static int rk808_rtc_readalarm(struct de + + static int rk808_rtc_stop_alarm(struct rk808_rtc *rk808_rtc) + { +- struct rk808 *rk808 = rk808_rtc->rk808; + int ret; + +- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg, ++ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->int_reg, + BIT_RTC_INTERRUPTS_REG_IT_ALARM_M, 0); + + return ret; +@@ -239,10 +234,9 @@ static int rk808_rtc_stop_alarm(struct r + + static int rk808_rtc_start_alarm(struct rk808_rtc *rk808_rtc) + { +- struct rk808 *rk808 = rk808_rtc->rk808; + int ret; + +- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg, ++ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->int_reg, + BIT_RTC_INTERRUPTS_REG_IT_ALARM_M, + BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); + +@@ -252,7 +246,6 @@ static int rk808_rtc_start_alarm(struct + static int rk808_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) + { + struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev); +- struct rk808 *rk808 = rk808_rtc->rk808; + u8 alrm_data[NUM_ALARM_REGS]; + int ret; + +@@ -272,7 +265,7 @@ static int rk808_rtc_setalarm(struct dev + alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1); + alrm_data[5] = bin2bcd(alrm->time.tm_year - 100); + +- ret = regmap_bulk_write(rk808->regmap, ++ ret = regmap_bulk_write(rk808_rtc->regmap, + rk808_rtc->creg->alarm_seconds_reg, + alrm_data, NUM_ALARM_REGS); + if (ret) { +@@ -313,20 +306,18 @@ static int rk808_rtc_alarm_irq_enable(st + static irqreturn_t rk808_alarm_irq(int irq, void *data) + { + struct rk808_rtc *rk808_rtc = data; +- struct rk808 *rk808 = rk808_rtc->rk808; +- struct i2c_client *client = rk808->i2c; + int ret; + +- ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg, ++ ret = regmap_write(rk808_rtc->regmap, rk808_rtc->creg->status_reg, + RTC_STATUS_MASK); + if (ret) { +- dev_err(&client->dev, ++ dev_err(&rk808_rtc->rtc->dev, + "%s:Failed to update RTC status: %d\n", __func__, ret); + return ret; + } + + rtc_update_irq(rk808_rtc->rtc, 1, RTC_IRQF | RTC_AF); +- dev_dbg(&client->dev, ++ dev_dbg(&rk808_rtc->rtc->dev, + "%s:irq=%d\n", __func__, irq); + return IRQ_HANDLED; + } +@@ -404,10 +395,12 @@ static int rk808_rtc_probe(struct platfo + break; + } + platform_set_drvdata(pdev, rk808_rtc); +- rk808_rtc->rk808 = rk808; ++ rk808_rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (!rk808_rtc->regmap) ++ return -ENODEV; + + /* start rtc running by default, and use shadowed timer. */ +- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, ++ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, + BIT_RTC_CTRL_REG_STOP_RTC_M | + BIT_RTC_CTRL_REG_RTC_READSEL_M, + BIT_RTC_CTRL_REG_RTC_READSEL_M); +@@ -417,7 +410,7 @@ static int rk808_rtc_probe(struct platfo + return ret; + } + +- ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg, ++ ret = regmap_write(rk808_rtc->regmap, rk808_rtc->creg->status_reg, + RTC_STATUS_MASK); + if (ret) { + dev_err(&pdev->dev, diff --git a/target/linux/rockchip/patches-6.1/031-04-v6.5-clk-RK808-Reduce-struct-rk808-usage.patch b/target/linux/rockchip/patches-6.1/031-04-v6.5-clk-RK808-Reduce-struct-rk808-usage.patch new file mode 100644 index 0000000000..85758ab368 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-04-v6.5-clk-RK808-Reduce-struct-rk808-usage.patch @@ -0,0 +1,132 @@ +From 2dc51ca822e4633e244e7f7bdc51e76a77dca939 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:05 +0200 +Subject: [PATCH] clk: RK808: Reduce 'struct rk808' usage + +Reduce usage of 'struct rk808' (driver data of the parent MFD), so +that only the chip variant field is still being accessed directly. +This allows restructuring the MFD driver to support SPI based +PMICs. + +Acked-by: Stephen Boyd +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-2-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/clk/clk-rk808.c | 34 ++++++++++++++++------------------ + 1 file changed, 16 insertions(+), 18 deletions(-) + +--- a/drivers/clk/clk-rk808.c ++++ b/drivers/clk/clk-rk808.c +@@ -12,10 +12,9 @@ + #include + #include + #include +-#include + + struct rk808_clkout { +- struct rk808 *rk808; ++ struct regmap *regmap; + struct clk_hw clkout1_hw; + struct clk_hw clkout2_hw; + }; +@@ -31,9 +30,8 @@ static int rk808_clkout2_enable(struct c + struct rk808_clkout *rk808_clkout = container_of(hw, + struct rk808_clkout, + clkout2_hw); +- struct rk808 *rk808 = rk808_clkout->rk808; + +- return regmap_update_bits(rk808->regmap, RK808_CLK32OUT_REG, ++ return regmap_update_bits(rk808_clkout->regmap, RK808_CLK32OUT_REG, + CLK32KOUT2_EN, enable ? CLK32KOUT2_EN : 0); + } + +@@ -52,10 +50,9 @@ static int rk808_clkout2_is_prepared(str + struct rk808_clkout *rk808_clkout = container_of(hw, + struct rk808_clkout, + clkout2_hw); +- struct rk808 *rk808 = rk808_clkout->rk808; + uint32_t val; + +- int ret = regmap_read(rk808->regmap, RK808_CLK32OUT_REG, &val); ++ int ret = regmap_read(rk808_clkout->regmap, RK808_CLK32OUT_REG, &val); + + if (ret < 0) + return ret; +@@ -93,9 +90,8 @@ static int rk817_clkout2_enable(struct c + struct rk808_clkout *rk808_clkout = container_of(hw, + struct rk808_clkout, + clkout2_hw); +- struct rk808 *rk808 = rk808_clkout->rk808; + +- return regmap_update_bits(rk808->regmap, RK817_SYS_CFG(1), ++ return regmap_update_bits(rk808_clkout->regmap, RK817_SYS_CFG(1), + RK817_CLK32KOUT2_EN, + enable ? RK817_CLK32KOUT2_EN : 0); + } +@@ -115,10 +111,9 @@ static int rk817_clkout2_is_prepared(str + struct rk808_clkout *rk808_clkout = container_of(hw, + struct rk808_clkout, + clkout2_hw); +- struct rk808 *rk808 = rk808_clkout->rk808; + unsigned int val; + +- int ret = regmap_read(rk808->regmap, RK817_SYS_CFG(1), &val); ++ int ret = regmap_read(rk808_clkout->regmap, RK817_SYS_CFG(1), &val); + + if (ret < 0) + return 0; +@@ -153,18 +148,21 @@ static const struct clk_ops *rkpmic_get_ + static int rk808_clkout_probe(struct platform_device *pdev) + { + struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent); +- struct i2c_client *client = rk808->i2c; +- struct device_node *node = client->dev.of_node; ++ struct device *dev = &pdev->dev; + struct clk_init_data init = {}; + struct rk808_clkout *rk808_clkout; + int ret; + +- rk808_clkout = devm_kzalloc(&client->dev, ++ dev->of_node = pdev->dev.parent->of_node; ++ ++ rk808_clkout = devm_kzalloc(dev, + sizeof(*rk808_clkout), GFP_KERNEL); + if (!rk808_clkout) + return -ENOMEM; + +- rk808_clkout->rk808 = rk808; ++ rk808_clkout->regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (!rk808_clkout->regmap) ++ return -ENODEV; + + init.parent_names = NULL; + init.num_parents = 0; +@@ -173,10 +171,10 @@ static int rk808_clkout_probe(struct pla + rk808_clkout->clkout1_hw.init = &init; + + /* optional override of the clockname */ +- of_property_read_string_index(node, "clock-output-names", ++ of_property_read_string_index(dev->of_node, "clock-output-names", + 0, &init.name); + +- ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout1_hw); ++ ret = devm_clk_hw_register(dev, &rk808_clkout->clkout1_hw); + if (ret) + return ret; + +@@ -185,10 +183,10 @@ static int rk808_clkout_probe(struct pla + rk808_clkout->clkout2_hw.init = &init; + + /* optional override of the clockname */ +- of_property_read_string_index(node, "clock-output-names", ++ of_property_read_string_index(dev->of_node, "clock-output-names", + 1, &init.name); + +- ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout2_hw); ++ ret = devm_clk_hw_register(dev, &rk808_clkout->clkout2_hw); + if (ret) + return ret; + diff --git a/target/linux/rockchip/patches-6.1/031-05-v6.5-mfd-rk808-Convert-to-device-managed-resources.patch b/target/linux/rockchip/patches-6.1/031-05-v6.5-mfd-rk808-Convert-to-device-managed-resources.patch new file mode 100644 index 0000000000..8d79166fa7 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-05-v6.5-mfd-rk808-Convert-to-device-managed-resources.patch @@ -0,0 +1,151 @@ +From 4fec8a5a85c495851007084e632b7f3f87cb7bdb Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:06 +0200 +Subject: [PATCH] mfd: rk808: Convert to device managed resources + +Fully convert the driver to device managed resources. + +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-3-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/mfd/rk808.c | 64 ++++++++++++++++----------------------------- + 1 file changed, 22 insertions(+), 42 deletions(-) + +--- a/drivers/mfd/rk808.c ++++ b/drivers/mfd/rk808.c +@@ -547,13 +547,11 @@ static const struct regmap_irq_chip rk81 + .init_ack_masked = true, + }; + +-static struct i2c_client *rk808_i2c_client; +- +-static void rk808_pm_power_off(void) ++static int rk808_power_off(struct sys_off_data *data) + { ++ struct rk808 *rk808 = data->cb_data; + int ret; + unsigned int reg, bit; +- struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); + + switch (rk808->variant) { + case RK805_ID: +@@ -574,16 +572,18 @@ static void rk808_pm_power_off(void) + bit = DEV_OFF; + break; + default: +- return; ++ return NOTIFY_DONE; + } + ret = regmap_update_bits(rk808->regmap, reg, bit, bit); + if (ret) +- dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); ++ dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n"); ++ ++ return NOTIFY_DONE; + } + +-static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd) ++static int rk808_restart(struct sys_off_data *data) + { +- struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); ++ struct rk808 *rk808 = data->cb_data; + unsigned int reg, bit; + int ret; + +@@ -599,16 +599,11 @@ static int rk808_restart_notify(struct n + } + ret = regmap_update_bits(rk808->regmap, reg, bit, bit); + if (ret) +- dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n"); ++ dev_err(&rk808->i2c->dev, "Failed to restart device!\n"); + + return NOTIFY_DONE; + } + +-static struct notifier_block rk808_restart_handler = { +- .notifier_call = rk808_restart_notify, +- .priority = 192, +-}; +- + static void rk8xx_shutdown(struct i2c_client *client) + { + struct rk808 *rk808 = i2c_get_clientdata(client); +@@ -744,9 +739,9 @@ static int rk808_probe(struct i2c_client + return -EINVAL; + } + +- ret = regmap_add_irq_chip(rk808->regmap, client->irq, +- IRQF_ONESHOT, -1, +- rk808->regmap_irq_chip, &rk808->irq_data); ++ ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq, ++ IRQF_ONESHOT, -1, ++ rk808->regmap_irq_chip, &rk808->irq_data); + if (ret) { + dev_err(&client->dev, "Failed to add irq_chip %d\n", ret); + return ret; +@@ -770,17 +765,23 @@ static int rk808_probe(struct i2c_client + regmap_irq_get_domain(rk808->irq_data)); + if (ret) { + dev_err(&client->dev, "failed to add MFD devices %d\n", ret); +- goto err_irq; ++ return ret; + } + + if (of_property_read_bool(np, "rockchip,system-power-controller")) { +- rk808_i2c_client = client; +- pm_power_off = rk808_pm_power_off; ++ ret = devm_register_sys_off_handler(&client->dev, ++ SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH, ++ &rk808_power_off, rk808); ++ if (ret) ++ return dev_err_probe(&client->dev, ret, ++ "failed to register poweroff handler\n"); + + switch (rk808->variant) { + case RK809_ID: + case RK817_ID: +- ret = register_restart_handler(&rk808_restart_handler); ++ ret = devm_register_sys_off_handler(&client->dev, ++ SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH, ++ &rk808_restart, rk808); + if (ret) + dev_warn(&client->dev, "failed to register rst handler, %d\n", ret); + break; +@@ -791,26 +792,6 @@ static int rk808_probe(struct i2c_client + } + + return 0; +- +-err_irq: +- regmap_del_irq_chip(client->irq, rk808->irq_data); +- return ret; +-} +- +-static void rk808_remove(struct i2c_client *client) +-{ +- struct rk808 *rk808 = i2c_get_clientdata(client); +- +- regmap_del_irq_chip(client->irq, rk808->irq_data); +- +- /** +- * pm_power_off may points to a function from another module. +- * Check if the pointer is set by us and only then overwrite it. +- */ +- if (pm_power_off == rk808_pm_power_off) +- pm_power_off = NULL; +- +- unregister_restart_handler(&rk808_restart_handler); + } + + static int __maybe_unused rk8xx_suspend(struct device *dev) +@@ -867,7 +848,6 @@ static struct i2c_driver rk808_i2c_drive + .pm = &rk8xx_pm_ops, + }, + .probe_new = rk808_probe, +- .remove = rk808_remove, + .shutdown = rk8xx_shutdown, + }; + diff --git a/target/linux/rockchip/patches-6.1/031-06-v6.5-mfd-rk808-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/031-06-v6.5-mfd-rk808-Use-dev_err_probe.patch new file mode 100644 index 0000000000..a096e7f783 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-06-v6.5-mfd-rk808-Use-dev_err_probe.patch @@ -0,0 +1,103 @@ +From e714b50bdf3cf45076c601276e9e3da00ea05319 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:07 +0200 +Subject: [PATCH] mfd: rk808: Use dev_err_probe + +Use dev_err_probe instead of dev_err in probe function, +which simplifies code a little bit and prints the error +code. + +Also drop possibly incorrect printing of chip id registers +while touching the error message. + +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-4-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/mfd/rk808.c | 48 +++++++++++++++------------------------------ + 1 file changed, 16 insertions(+), 32 deletions(-) + +--- a/drivers/mfd/rk808.c ++++ b/drivers/mfd/rk808.c +@@ -669,18 +669,12 @@ static int rk808_probe(struct i2c_client + + /* Read chip variant */ + msb = i2c_smbus_read_byte_data(client, pmic_id_msb); +- if (msb < 0) { +- dev_err(&client->dev, "failed to read the chip id at 0x%x\n", +- RK808_ID_MSB); +- return msb; +- } ++ if (msb < 0) ++ return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); + + lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); +- if (lsb < 0) { +- dev_err(&client->dev, "failed to read the chip id at 0x%x\n", +- RK808_ID_LSB); +- return lsb; +- } ++ if (lsb < 0) ++ return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); + + rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; + dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); +@@ -729,44 +723,34 @@ static int rk808_probe(struct i2c_client + i2c_set_clientdata(client, rk808); + + rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg); +- if (IS_ERR(rk808->regmap)) { +- dev_err(&client->dev, "regmap initialization failed\n"); +- return PTR_ERR(rk808->regmap); +- } ++ if (IS_ERR(rk808->regmap)) ++ return dev_err_probe(&client->dev, PTR_ERR(rk808->regmap), ++ "regmap initialization failed\n"); + +- if (!client->irq) { +- dev_err(&client->dev, "No interrupt support, no core IRQ\n"); +- return -EINVAL; +- } ++ if (!client->irq) ++ return dev_err_probe(&client->dev, -EINVAL, "No interrupt support, no core IRQ\n"); + + ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq, + IRQF_ONESHOT, -1, + rk808->regmap_irq_chip, &rk808->irq_data); +- if (ret) { +- dev_err(&client->dev, "Failed to add irq_chip %d\n", ret); +- return ret; +- } ++ if (ret) ++ return dev_err_probe(&client->dev, ret, "Failed to add irq_chip\n"); + + for (i = 0; i < nr_pre_init_regs; i++) { + ret = regmap_update_bits(rk808->regmap, + pre_init_reg[i].addr, + pre_init_reg[i].mask, + pre_init_reg[i].value); +- if (ret) { +- dev_err(&client->dev, +- "0x%x write err\n", +- pre_init_reg[i].addr); +- return ret; +- } ++ if (ret) ++ return dev_err_probe(&client->dev, ret, "0x%x write err\n", ++ pre_init_reg[i].addr); + } + + ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE, + cells, nr_cells, NULL, 0, + regmap_irq_get_domain(rk808->irq_data)); +- if (ret) { +- dev_err(&client->dev, "failed to add MFD devices %d\n", ret); +- return ret; +- } ++ if (ret) ++ return dev_err_probe(&client->dev, ret, "failed to add MFD devices\n"); + + if (of_property_read_bool(np, "rockchip,system-power-controller")) { + ret = devm_register_sys_off_handler(&client->dev, diff --git a/target/linux/rockchip/patches-6.1/031-07-v6.5-mfd-rk808-Replace-struct-i2c_client-with-struct-device-.patch b/target/linux/rockchip/patches-6.1/031-07-v6.5-mfd-rk808-Replace-struct-i2c_client-with-struct-device-.patch new file mode 100644 index 0000000000..c457a79d96 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-07-v6.5-mfd-rk808-Replace-struct-i2c_client-with-struct-device-.patch @@ -0,0 +1,59 @@ +From 049449976f549605a6913d468b61356a9950a6a2 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:08 +0200 +Subject: [PATCH] mfd: rk808: Replace 'struct i2c_client' with 'struct device' + +Put 'struct device' pointer into the MFD platform_data instead +of the 'struct i2c_client' pointer. This simplifies the code +and prepares the MFD for SPI support. + +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-5-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/mfd/rk808.c | 6 +++--- + include/linux/mfd/rk808.h | 2 +- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/mfd/rk808.c ++++ b/drivers/mfd/rk808.c +@@ -576,7 +576,7 @@ static int rk808_power_off(struct sys_of + } + ret = regmap_update_bits(rk808->regmap, reg, bit, bit); + if (ret) +- dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n"); ++ dev_err(rk808->dev, "Failed to shutdown device!\n"); + + return NOTIFY_DONE; + } +@@ -599,7 +599,7 @@ static int rk808_restart(struct sys_off_ + } + ret = regmap_update_bits(rk808->regmap, reg, bit, bit); + if (ret) +- dev_err(&rk808->i2c->dev, "Failed to restart device!\n"); ++ dev_err(rk808->dev, "Failed to restart device!\n"); + + return NOTIFY_DONE; + } +@@ -719,7 +719,7 @@ static int rk808_probe(struct i2c_client + return -EINVAL; + } + +- rk808->i2c = client; ++ rk808->dev = &client->dev; + i2c_set_clientdata(client, rk808); + + rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg); +--- a/include/linux/mfd/rk808.h ++++ b/include/linux/mfd/rk808.h +@@ -787,7 +787,7 @@ enum { + }; + + struct rk808 { +- struct i2c_client *i2c; ++ struct device *dev; + struct regmap_irq_chip_data *irq_data; + struct regmap *regmap; + long variant; diff --git a/target/linux/rockchip/patches-6.1/031-08-v6.5-mfd-rk808-Split-into-core-and-i2c.patch b/target/linux/rockchip/patches-6.1/031-08-v6.5-mfd-rk808-Split-into-core-and-i2c.patch new file mode 100644 index 0000000000..b24a5c5a32 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-08-v6.5-mfd-rk808-Split-into-core-and-i2c.patch @@ -0,0 +1,1912 @@ +From c20e8c5b1203af3726561ee5649b147194e0618e Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:09 +0200 +Subject: [PATCH] mfd: rk808: Split into core and i2c + +Split rk808 into a core and an i2c part in preparation for +SPI support. + +Acked-by: Alexandre Belloni # for RTC +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-6-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/clk/Kconfig | 2 +- + drivers/input/misc/Kconfig | 2 +- + drivers/mfd/Kconfig | 7 +- + drivers/mfd/Makefile | 3 +- + drivers/mfd/{rk808.c => rk8xx-core.c} | 209 +++++--------------------- + drivers/mfd/rk8xx-i2c.c | 200 ++++++++++++++++++++++++ + drivers/pinctrl/Kconfig | 2 +- + drivers/power/supply/Kconfig | 2 +- + drivers/regulator/Kconfig | 2 +- + drivers/rtc/Kconfig | 2 +- + include/linux/mfd/rk808.h | 6 + + sound/soc/codecs/Kconfig | 2 +- + 12 files changed, 256 insertions(+), 183 deletions(-) + rename drivers/mfd/{rk808.c => rk8xx-core.c} (76%) + create mode 100644 drivers/mfd/rk8xx-i2c.c + +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -83,7 +83,7 @@ config COMMON_CLK_MAX9485 + + config COMMON_CLK_RK808 + tristate "Clock driver for RK805/RK808/RK809/RK817/RK818" +- depends on MFD_RK808 ++ depends on MFD_RK8XX + help + This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock. + These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. +--- a/drivers/input/misc/Kconfig ++++ b/drivers/input/misc/Kconfig +@@ -588,7 +588,7 @@ config INPUT_PWM_VIBRA + + config INPUT_RK805_PWRKEY + tristate "Rockchip RK805 PMIC power key support" +- depends on MFD_RK808 ++ depends on MFD_RK8XX + help + Select this option to enable power key driver for RK805. + +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -1202,12 +1202,17 @@ config MFD_RC5T583 + Additional drivers must be enabled in order to use the + different functionality of the device. + +-config MFD_RK808 ++config MFD_RK8XX ++ bool ++ select MFD_CORE ++ ++config MFD_RK8XX_I2C + tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power Management Chip" + depends on I2C && OF + select MFD_CORE + select REGMAP_I2C + select REGMAP_IRQ ++ select MFD_RK8XX + help + If you say yes here you get support for the RK805, RK808, RK809, + RK817 and RK818 Power Management chips. +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -223,7 +223,8 @@ obj-$(CONFIG_MFD_PALMAS) += palmas.o + obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o + obj-$(CONFIG_MFD_NTXEC) += ntxec.o + obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o +-obj-$(CONFIG_MFD_RK808) += rk808.o ++obj-$(CONFIG_MFD_RK8XX) += rk8xx-core.o ++obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o + obj-$(CONFIG_MFD_RN5T618) += rn5t618.o + obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o + obj-$(CONFIG_MFD_SYSCON) += syscon.o +--- a/drivers/mfd/rk808.c ++++ /dev/null +@@ -1,844 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0-only +-/* +- * MFD core driver for Rockchip RK808/RK818 +- * +- * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd +- * +- * Author: Chris Zhong +- * Author: Zhang Qing +- * +- * Copyright (C) 2016 PHYTEC Messtechnik GmbH +- * +- * Author: Wadim Egorov +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-struct rk808_reg_data { +- int addr; +- int mask; +- int value; +-}; +- +-static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) +-{ +- /* +- * Notes: +- * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but +- * we don't use that feature. It's better to cache. +- * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since +- * bits are cleared in case when we shutoff anyway, but better safe. +- */ +- +- switch (reg) { +- case RK808_SECONDS_REG ... RK808_WEEKS_REG: +- case RK808_RTC_STATUS_REG: +- case RK808_VB_MON_REG: +- case RK808_THERMAL_REG: +- case RK808_DCDC_UV_STS_REG: +- case RK808_LDO_UV_STS_REG: +- case RK808_DCDC_PG_REG: +- case RK808_LDO_PG_REG: +- case RK808_DEVCTRL_REG: +- case RK808_INT_STS_REG1: +- case RK808_INT_STS_REG2: +- return true; +- } +- +- return false; +-} +- +-static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg) +-{ +- /* +- * Notes: +- * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but +- * we don't use that feature. It's better to cache. +- */ +- +- switch (reg) { +- case RK817_SECONDS_REG ... RK817_WEEKS_REG: +- case RK817_RTC_STATUS_REG: +- case RK817_CODEC_DTOP_LPT_SRST: +- case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0: +- case RK817_PMIC_CHRG_STS: +- case RK817_PMIC_CHRG_OUT: +- case RK817_PMIC_CHRG_IN: +- case RK817_INT_STS_REG0: +- case RK817_INT_STS_REG1: +- case RK817_INT_STS_REG2: +- case RK817_SYS_STS: +- return true; +- } +- +- return false; +-} +- +-static const struct regmap_config rk818_regmap_config = { +- .reg_bits = 8, +- .val_bits = 8, +- .max_register = RK818_USB_CTRL_REG, +- .cache_type = REGCACHE_RBTREE, +- .volatile_reg = rk808_is_volatile_reg, +-}; +- +-static const struct regmap_config rk805_regmap_config = { +- .reg_bits = 8, +- .val_bits = 8, +- .max_register = RK805_OFF_SOURCE_REG, +- .cache_type = REGCACHE_RBTREE, +- .volatile_reg = rk808_is_volatile_reg, +-}; +- +-static const struct regmap_config rk808_regmap_config = { +- .reg_bits = 8, +- .val_bits = 8, +- .max_register = RK808_IO_POL_REG, +- .cache_type = REGCACHE_RBTREE, +- .volatile_reg = rk808_is_volatile_reg, +-}; +- +-static const struct regmap_config rk817_regmap_config = { +- .reg_bits = 8, +- .val_bits = 8, +- .max_register = RK817_GPIO_INT_CFG, +- .cache_type = REGCACHE_NONE, +- .volatile_reg = rk817_is_volatile_reg, +-}; +- +-static const struct resource rtc_resources[] = { +- DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM), +-}; +- +-static const struct resource rk817_rtc_resources[] = { +- DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM), +-}; +- +-static const struct resource rk805_key_resources[] = { +- DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE), +- DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL), +-}; +- +-static const struct resource rk817_pwrkey_resources[] = { +- DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), +- DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL), +-}; +- +-static const struct resource rk817_charger_resources[] = { +- DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN), +- DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT), +-}; +- +-static const struct mfd_cell rk805s[] = { +- { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, +- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, +- { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, }, +- { +- .name = "rk808-rtc", +- .num_resources = ARRAY_SIZE(rtc_resources), +- .resources = &rtc_resources[0], +- .id = PLATFORM_DEVID_NONE, +- }, +- { .name = "rk805-pwrkey", +- .num_resources = ARRAY_SIZE(rk805_key_resources), +- .resources = &rk805_key_resources[0], +- .id = PLATFORM_DEVID_NONE, +- }, +-}; +- +-static const struct mfd_cell rk808s[] = { +- { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, +- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, +- { +- .name = "rk808-rtc", +- .num_resources = ARRAY_SIZE(rtc_resources), +- .resources = rtc_resources, +- .id = PLATFORM_DEVID_NONE, +- }, +-}; +- +-static const struct mfd_cell rk817s[] = { +- { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, +- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, +- { +- .name = "rk805-pwrkey", +- .num_resources = ARRAY_SIZE(rk817_pwrkey_resources), +- .resources = &rk817_pwrkey_resources[0], +- .id = PLATFORM_DEVID_NONE, +- }, +- { +- .name = "rk808-rtc", +- .num_resources = ARRAY_SIZE(rk817_rtc_resources), +- .resources = &rk817_rtc_resources[0], +- .id = PLATFORM_DEVID_NONE, +- }, +- { .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, }, +- { +- .name = "rk817-charger", +- .num_resources = ARRAY_SIZE(rk817_charger_resources), +- .resources = &rk817_charger_resources[0], +- .id = PLATFORM_DEVID_NONE, +- }, +-}; +- +-static const struct mfd_cell rk818s[] = { +- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, +- { +- .name = "rk808-rtc", +- .num_resources = ARRAY_SIZE(rtc_resources), +- .resources = rtc_resources, +- .id = PLATFORM_DEVID_NONE, +- }, +-}; +- +-static const struct rk808_reg_data rk805_pre_init_reg[] = { +- {RK805_BUCK1_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK, +- RK805_BUCK1_2_ILMAX_4000MA}, +- {RK805_BUCK2_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK, +- RK805_BUCK1_2_ILMAX_4000MA}, +- {RK805_BUCK3_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK, +- RK805_BUCK3_ILMAX_3000MA}, +- {RK805_BUCK4_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK, +- RK805_BUCK4_ILMAX_3500MA}, +- {RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA}, +- {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C}, +-}; +- +-static const struct rk808_reg_data rk808_pre_init_reg[] = { +- { RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA }, +- { RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA }, +- { RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA }, +- { RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK, BUCK_ILMIN_200MA }, +- { RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_200MA }, +- { RK808_DCDC_UV_ACT_REG, BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE}, +- { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT | +- VB_LO_SEL_3500MV }, +-}; +- +-static const struct rk808_reg_data rk817_pre_init_reg[] = { +- {RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP}, +- /* Codec specific registers */ +- { RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 }, +- { RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 }, +- { RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 }, +- { RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 }, +- /* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */ +- { RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 }, +- { RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 }, +- { RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 }, +- /* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */ +- { RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_NG, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 }, +- { RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff }, +- { RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff }, +- { RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 }, +- { RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 }, +- { RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 }, +- /* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */ +- { RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 }, +- { RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 }, +- { RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 }, +- { RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 }, +- { RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff }, +- { RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff }, +- { RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 }, +- { RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 }, +- { RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 }, +- /* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */ +- { RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 }, +- { RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 }, +- { RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 }, +- { RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 }, +- { RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 }, +- { RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff }, +- { RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff }, +- { RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 }, +- { RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 }, +- { RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 }, +- { RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f }, +- { RK817_CODEC_AHP_CP, MASK_ALL, 0x09 }, +- { RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 }, +- { RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 }, +- { RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 }, +- { RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 }, +- { RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 }, +- { RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 }, +- { RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 }, +- { RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 }, +- { RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 }, +- { RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 }, +- { RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 }, +- { RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 }, +- { RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 }, +- { RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 }, +- { RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 }, +- {RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L}, +- {RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK, +- RK817_HOTDIE_105 | RK817_TSD_140}, +-}; +- +-static const struct rk808_reg_data rk818_pre_init_reg[] = { +- /* improve efficiency */ +- { RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_250MA }, +- { RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_250MA }, +- { RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA }, +- { RK818_USB_CTRL_REG, RK818_USB_ILIM_SEL_MASK, +- RK818_USB_ILMIN_2000MA }, +- /* close charger when usb lower then 3.4V */ +- { RK818_USB_CTRL_REG, RK818_USB_CHG_SD_VSEL_MASK, +- (0x7 << 4) }, +- /* no action when vref */ +- { RK818_H5V_EN_REG, BIT(1), RK818_REF_RDY_CTRL }, +- /* enable HDMI 5V */ +- { RK818_H5V_EN_REG, BIT(0), RK818_H5V_EN }, +- { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT | +- VB_LO_SEL_3500MV }, +-}; +- +-static const struct regmap_irq rk805_irqs[] = { +- [RK805_IRQ_PWRON_RISE] = { +- .mask = RK805_IRQ_PWRON_RISE_MSK, +- .reg_offset = 0, +- }, +- [RK805_IRQ_VB_LOW] = { +- .mask = RK805_IRQ_VB_LOW_MSK, +- .reg_offset = 0, +- }, +- [RK805_IRQ_PWRON] = { +- .mask = RK805_IRQ_PWRON_MSK, +- .reg_offset = 0, +- }, +- [RK805_IRQ_PWRON_LP] = { +- .mask = RK805_IRQ_PWRON_LP_MSK, +- .reg_offset = 0, +- }, +- [RK805_IRQ_HOTDIE] = { +- .mask = RK805_IRQ_HOTDIE_MSK, +- .reg_offset = 0, +- }, +- [RK805_IRQ_RTC_ALARM] = { +- .mask = RK805_IRQ_RTC_ALARM_MSK, +- .reg_offset = 0, +- }, +- [RK805_IRQ_RTC_PERIOD] = { +- .mask = RK805_IRQ_RTC_PERIOD_MSK, +- .reg_offset = 0, +- }, +- [RK805_IRQ_PWRON_FALL] = { +- .mask = RK805_IRQ_PWRON_FALL_MSK, +- .reg_offset = 0, +- }, +-}; +- +-static const struct regmap_irq rk808_irqs[] = { +- /* INT_STS */ +- [RK808_IRQ_VOUT_LO] = { +- .mask = RK808_IRQ_VOUT_LO_MSK, +- .reg_offset = 0, +- }, +- [RK808_IRQ_VB_LO] = { +- .mask = RK808_IRQ_VB_LO_MSK, +- .reg_offset = 0, +- }, +- [RK808_IRQ_PWRON] = { +- .mask = RK808_IRQ_PWRON_MSK, +- .reg_offset = 0, +- }, +- [RK808_IRQ_PWRON_LP] = { +- .mask = RK808_IRQ_PWRON_LP_MSK, +- .reg_offset = 0, +- }, +- [RK808_IRQ_HOTDIE] = { +- .mask = RK808_IRQ_HOTDIE_MSK, +- .reg_offset = 0, +- }, +- [RK808_IRQ_RTC_ALARM] = { +- .mask = RK808_IRQ_RTC_ALARM_MSK, +- .reg_offset = 0, +- }, +- [RK808_IRQ_RTC_PERIOD] = { +- .mask = RK808_IRQ_RTC_PERIOD_MSK, +- .reg_offset = 0, +- }, +- +- /* INT_STS2 */ +- [RK808_IRQ_PLUG_IN_INT] = { +- .mask = RK808_IRQ_PLUG_IN_INT_MSK, +- .reg_offset = 1, +- }, +- [RK808_IRQ_PLUG_OUT_INT] = { +- .mask = RK808_IRQ_PLUG_OUT_INT_MSK, +- .reg_offset = 1, +- }, +-}; +- +-static const struct regmap_irq rk818_irqs[] = { +- /* INT_STS */ +- [RK818_IRQ_VOUT_LO] = { +- .mask = RK818_IRQ_VOUT_LO_MSK, +- .reg_offset = 0, +- }, +- [RK818_IRQ_VB_LO] = { +- .mask = RK818_IRQ_VB_LO_MSK, +- .reg_offset = 0, +- }, +- [RK818_IRQ_PWRON] = { +- .mask = RK818_IRQ_PWRON_MSK, +- .reg_offset = 0, +- }, +- [RK818_IRQ_PWRON_LP] = { +- .mask = RK818_IRQ_PWRON_LP_MSK, +- .reg_offset = 0, +- }, +- [RK818_IRQ_HOTDIE] = { +- .mask = RK818_IRQ_HOTDIE_MSK, +- .reg_offset = 0, +- }, +- [RK818_IRQ_RTC_ALARM] = { +- .mask = RK818_IRQ_RTC_ALARM_MSK, +- .reg_offset = 0, +- }, +- [RK818_IRQ_RTC_PERIOD] = { +- .mask = RK818_IRQ_RTC_PERIOD_MSK, +- .reg_offset = 0, +- }, +- [RK818_IRQ_USB_OV] = { +- .mask = RK818_IRQ_USB_OV_MSK, +- .reg_offset = 0, +- }, +- +- /* INT_STS2 */ +- [RK818_IRQ_PLUG_IN] = { +- .mask = RK818_IRQ_PLUG_IN_MSK, +- .reg_offset = 1, +- }, +- [RK818_IRQ_PLUG_OUT] = { +- .mask = RK818_IRQ_PLUG_OUT_MSK, +- .reg_offset = 1, +- }, +- [RK818_IRQ_CHG_OK] = { +- .mask = RK818_IRQ_CHG_OK_MSK, +- .reg_offset = 1, +- }, +- [RK818_IRQ_CHG_TE] = { +- .mask = RK818_IRQ_CHG_TE_MSK, +- .reg_offset = 1, +- }, +- [RK818_IRQ_CHG_TS1] = { +- .mask = RK818_IRQ_CHG_TS1_MSK, +- .reg_offset = 1, +- }, +- [RK818_IRQ_TS2] = { +- .mask = RK818_IRQ_TS2_MSK, +- .reg_offset = 1, +- }, +- [RK818_IRQ_CHG_CVTLIM] = { +- .mask = RK818_IRQ_CHG_CVTLIM_MSK, +- .reg_offset = 1, +- }, +- [RK818_IRQ_DISCHG_ILIM] = { +- .mask = RK818_IRQ_DISCHG_ILIM_MSK, +- .reg_offset = 1, +- }, +-}; +- +-static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = { +- REGMAP_IRQ_REG_LINE(0, 8), +- REGMAP_IRQ_REG_LINE(1, 8), +- REGMAP_IRQ_REG_LINE(2, 8), +- REGMAP_IRQ_REG_LINE(3, 8), +- REGMAP_IRQ_REG_LINE(4, 8), +- REGMAP_IRQ_REG_LINE(5, 8), +- REGMAP_IRQ_REG_LINE(6, 8), +- REGMAP_IRQ_REG_LINE(7, 8), +- REGMAP_IRQ_REG_LINE(8, 8), +- REGMAP_IRQ_REG_LINE(9, 8), +- REGMAP_IRQ_REG_LINE(10, 8), +- REGMAP_IRQ_REG_LINE(11, 8), +- REGMAP_IRQ_REG_LINE(12, 8), +- REGMAP_IRQ_REG_LINE(13, 8), +- REGMAP_IRQ_REG_LINE(14, 8), +- REGMAP_IRQ_REG_LINE(15, 8), +- REGMAP_IRQ_REG_LINE(16, 8), +- REGMAP_IRQ_REG_LINE(17, 8), +- REGMAP_IRQ_REG_LINE(18, 8), +- REGMAP_IRQ_REG_LINE(19, 8), +- REGMAP_IRQ_REG_LINE(20, 8), +- REGMAP_IRQ_REG_LINE(21, 8), +- REGMAP_IRQ_REG_LINE(22, 8), +- REGMAP_IRQ_REG_LINE(23, 8) +-}; +- +-static struct regmap_irq_chip rk805_irq_chip = { +- .name = "rk805", +- .irqs = rk805_irqs, +- .num_irqs = ARRAY_SIZE(rk805_irqs), +- .num_regs = 1, +- .status_base = RK805_INT_STS_REG, +- .mask_base = RK805_INT_STS_MSK_REG, +- .ack_base = RK805_INT_STS_REG, +- .init_ack_masked = true, +-}; +- +-static const struct regmap_irq_chip rk808_irq_chip = { +- .name = "rk808", +- .irqs = rk808_irqs, +- .num_irqs = ARRAY_SIZE(rk808_irqs), +- .num_regs = 2, +- .irq_reg_stride = 2, +- .status_base = RK808_INT_STS_REG1, +- .mask_base = RK808_INT_STS_MSK_REG1, +- .ack_base = RK808_INT_STS_REG1, +- .init_ack_masked = true, +-}; +- +-static struct regmap_irq_chip rk817_irq_chip = { +- .name = "rk817", +- .irqs = rk817_irqs, +- .num_irqs = ARRAY_SIZE(rk817_irqs), +- .num_regs = 3, +- .irq_reg_stride = 2, +- .status_base = RK817_INT_STS_REG0, +- .mask_base = RK817_INT_STS_MSK_REG0, +- .ack_base = RK817_INT_STS_REG0, +- .init_ack_masked = true, +-}; +- +-static const struct regmap_irq_chip rk818_irq_chip = { +- .name = "rk818", +- .irqs = rk818_irqs, +- .num_irqs = ARRAY_SIZE(rk818_irqs), +- .num_regs = 2, +- .irq_reg_stride = 2, +- .status_base = RK818_INT_STS_REG1, +- .mask_base = RK818_INT_STS_MSK_REG1, +- .ack_base = RK818_INT_STS_REG1, +- .init_ack_masked = true, +-}; +- +-static int rk808_power_off(struct sys_off_data *data) +-{ +- struct rk808 *rk808 = data->cb_data; +- int ret; +- unsigned int reg, bit; +- +- switch (rk808->variant) { +- case RK805_ID: +- reg = RK805_DEV_CTRL_REG; +- bit = DEV_OFF; +- break; +- case RK808_ID: +- reg = RK808_DEVCTRL_REG, +- bit = DEV_OFF_RST; +- break; +- case RK809_ID: +- case RK817_ID: +- reg = RK817_SYS_CFG(3); +- bit = DEV_OFF; +- break; +- case RK818_ID: +- reg = RK818_DEVCTRL_REG; +- bit = DEV_OFF; +- break; +- default: +- return NOTIFY_DONE; +- } +- ret = regmap_update_bits(rk808->regmap, reg, bit, bit); +- if (ret) +- dev_err(rk808->dev, "Failed to shutdown device!\n"); +- +- return NOTIFY_DONE; +-} +- +-static int rk808_restart(struct sys_off_data *data) +-{ +- struct rk808 *rk808 = data->cb_data; +- unsigned int reg, bit; +- int ret; +- +- switch (rk808->variant) { +- case RK809_ID: +- case RK817_ID: +- reg = RK817_SYS_CFG(3); +- bit = DEV_RST; +- break; +- +- default: +- return NOTIFY_DONE; +- } +- ret = regmap_update_bits(rk808->regmap, reg, bit, bit); +- if (ret) +- dev_err(rk808->dev, "Failed to restart device!\n"); +- +- return NOTIFY_DONE; +-} +- +-static void rk8xx_shutdown(struct i2c_client *client) +-{ +- struct rk808 *rk808 = i2c_get_clientdata(client); +- int ret; +- +- switch (rk808->variant) { +- case RK805_ID: +- ret = regmap_update_bits(rk808->regmap, +- RK805_GPIO_IO_POL_REG, +- SLP_SD_MSK, +- SHUTDOWN_FUN); +- break; +- case RK809_ID: +- case RK817_ID: +- ret = regmap_update_bits(rk808->regmap, +- RK817_SYS_CFG(3), +- RK817_SLPPIN_FUNC_MSK, +- SLPPIN_DN_FUN); +- break; +- default: +- return; +- } +- if (ret) +- dev_warn(&client->dev, +- "Cannot switch to power down function\n"); +-} +- +-static const struct of_device_id rk808_of_match[] = { +- { .compatible = "rockchip,rk805" }, +- { .compatible = "rockchip,rk808" }, +- { .compatible = "rockchip,rk809" }, +- { .compatible = "rockchip,rk817" }, +- { .compatible = "rockchip,rk818" }, +- { }, +-}; +-MODULE_DEVICE_TABLE(of, rk808_of_match); +- +-static int rk808_probe(struct i2c_client *client) +-{ +- struct device_node *np = client->dev.of_node; +- struct rk808 *rk808; +- const struct rk808_reg_data *pre_init_reg; +- const struct mfd_cell *cells; +- int nr_pre_init_regs; +- int nr_cells; +- int msb, lsb; +- unsigned char pmic_id_msb, pmic_id_lsb; +- int ret; +- int i; +- +- rk808 = devm_kzalloc(&client->dev, sizeof(*rk808), GFP_KERNEL); +- if (!rk808) +- return -ENOMEM; +- +- if (of_device_is_compatible(np, "rockchip,rk817") || +- of_device_is_compatible(np, "rockchip,rk809")) { +- pmic_id_msb = RK817_ID_MSB; +- pmic_id_lsb = RK817_ID_LSB; +- } else { +- pmic_id_msb = RK808_ID_MSB; +- pmic_id_lsb = RK808_ID_LSB; +- } +- +- /* Read chip variant */ +- msb = i2c_smbus_read_byte_data(client, pmic_id_msb); +- if (msb < 0) +- return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); +- +- lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); +- if (lsb < 0) +- return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); +- +- rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; +- dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); +- +- switch (rk808->variant) { +- case RK805_ID: +- rk808->regmap_cfg = &rk805_regmap_config; +- rk808->regmap_irq_chip = &rk805_irq_chip; +- pre_init_reg = rk805_pre_init_reg; +- nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg); +- cells = rk805s; +- nr_cells = ARRAY_SIZE(rk805s); +- break; +- case RK808_ID: +- rk808->regmap_cfg = &rk808_regmap_config; +- rk808->regmap_irq_chip = &rk808_irq_chip; +- pre_init_reg = rk808_pre_init_reg; +- nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg); +- cells = rk808s; +- nr_cells = ARRAY_SIZE(rk808s); +- break; +- case RK818_ID: +- rk808->regmap_cfg = &rk818_regmap_config; +- rk808->regmap_irq_chip = &rk818_irq_chip; +- pre_init_reg = rk818_pre_init_reg; +- nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg); +- cells = rk818s; +- nr_cells = ARRAY_SIZE(rk818s); +- break; +- case RK809_ID: +- case RK817_ID: +- rk808->regmap_cfg = &rk817_regmap_config; +- rk808->regmap_irq_chip = &rk817_irq_chip; +- pre_init_reg = rk817_pre_init_reg; +- nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg); +- cells = rk817s; +- nr_cells = ARRAY_SIZE(rk817s); +- break; +- default: +- dev_err(&client->dev, "Unsupported RK8XX ID %lu\n", +- rk808->variant); +- return -EINVAL; +- } +- +- rk808->dev = &client->dev; +- i2c_set_clientdata(client, rk808); +- +- rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg); +- if (IS_ERR(rk808->regmap)) +- return dev_err_probe(&client->dev, PTR_ERR(rk808->regmap), +- "regmap initialization failed\n"); +- +- if (!client->irq) +- return dev_err_probe(&client->dev, -EINVAL, "No interrupt support, no core IRQ\n"); +- +- ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq, +- IRQF_ONESHOT, -1, +- rk808->regmap_irq_chip, &rk808->irq_data); +- if (ret) +- return dev_err_probe(&client->dev, ret, "Failed to add irq_chip\n"); +- +- for (i = 0; i < nr_pre_init_regs; i++) { +- ret = regmap_update_bits(rk808->regmap, +- pre_init_reg[i].addr, +- pre_init_reg[i].mask, +- pre_init_reg[i].value); +- if (ret) +- return dev_err_probe(&client->dev, ret, "0x%x write err\n", +- pre_init_reg[i].addr); +- } +- +- ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE, +- cells, nr_cells, NULL, 0, +- regmap_irq_get_domain(rk808->irq_data)); +- if (ret) +- return dev_err_probe(&client->dev, ret, "failed to add MFD devices\n"); +- +- if (of_property_read_bool(np, "rockchip,system-power-controller")) { +- ret = devm_register_sys_off_handler(&client->dev, +- SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH, +- &rk808_power_off, rk808); +- if (ret) +- return dev_err_probe(&client->dev, ret, +- "failed to register poweroff handler\n"); +- +- switch (rk808->variant) { +- case RK809_ID: +- case RK817_ID: +- ret = devm_register_sys_off_handler(&client->dev, +- SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH, +- &rk808_restart, rk808); +- if (ret) +- dev_warn(&client->dev, "failed to register rst handler, %d\n", ret); +- break; +- default: +- dev_dbg(&client->dev, "pmic controlled board reset not supported\n"); +- break; +- } +- } +- +- return 0; +-} +- +-static int __maybe_unused rk8xx_suspend(struct device *dev) +-{ +- struct rk808 *rk808 = i2c_get_clientdata(to_i2c_client(dev)); +- int ret = 0; +- +- switch (rk808->variant) { +- case RK805_ID: +- ret = regmap_update_bits(rk808->regmap, +- RK805_GPIO_IO_POL_REG, +- SLP_SD_MSK, +- SLEEP_FUN); +- break; +- case RK809_ID: +- case RK817_ID: +- ret = regmap_update_bits(rk808->regmap, +- RK817_SYS_CFG(3), +- RK817_SLPPIN_FUNC_MSK, +- SLPPIN_SLP_FUN); +- break; +- default: +- break; +- } +- +- return ret; +-} +- +-static int __maybe_unused rk8xx_resume(struct device *dev) +-{ +- struct rk808 *rk808 = i2c_get_clientdata(to_i2c_client(dev)); +- int ret = 0; +- +- switch (rk808->variant) { +- case RK809_ID: +- case RK817_ID: +- ret = regmap_update_bits(rk808->regmap, +- RK817_SYS_CFG(3), +- RK817_SLPPIN_FUNC_MSK, +- SLPPIN_NULL_FUN); +- break; +- default: +- break; +- } +- +- return ret; +-} +-static SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume); +- +-static struct i2c_driver rk808_i2c_driver = { +- .driver = { +- .name = "rk808", +- .of_match_table = rk808_of_match, +- .pm = &rk8xx_pm_ops, +- }, +- .probe_new = rk808_probe, +- .shutdown = rk8xx_shutdown, +-}; +- +-module_i2c_driver(rk808_i2c_driver); +- +-MODULE_LICENSE("GPL"); +-MODULE_AUTHOR("Chris Zhong "); +-MODULE_AUTHOR("Zhang Qing "); +-MODULE_AUTHOR("Wadim Egorov "); +-MODULE_DESCRIPTION("RK808/RK818 PMIC driver"); +--- /dev/null ++++ b/drivers/mfd/rk8xx-core.c +@@ -0,0 +1,705 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * MFD core driver for Rockchip RK8XX ++ * ++ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (C) 2016 PHYTEC Messtechnik GmbH ++ * ++ * Author: Chris Zhong ++ * Author: Zhang Qing ++ * Author: Wadim Egorov ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct rk808_reg_data { ++ int addr; ++ int mask; ++ int value; ++}; ++ ++static const struct resource rtc_resources[] = { ++ DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM), ++}; ++ ++static const struct resource rk817_rtc_resources[] = { ++ DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM), ++}; ++ ++static const struct resource rk805_key_resources[] = { ++ DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE), ++ DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL), ++}; ++ ++static const struct resource rk817_pwrkey_resources[] = { ++ DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), ++ DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL), ++}; ++ ++static const struct resource rk817_charger_resources[] = { ++ DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN), ++ DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT), ++}; ++ ++static const struct mfd_cell rk805s[] = { ++ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, }, ++ { ++ .name = "rk808-rtc", ++ .num_resources = ARRAY_SIZE(rtc_resources), ++ .resources = &rtc_resources[0], ++ .id = PLATFORM_DEVID_NONE, ++ }, ++ { .name = "rk805-pwrkey", ++ .num_resources = ARRAY_SIZE(rk805_key_resources), ++ .resources = &rk805_key_resources[0], ++ .id = PLATFORM_DEVID_NONE, ++ }, ++}; ++ ++static const struct mfd_cell rk808s[] = { ++ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, ++ { ++ .name = "rk808-rtc", ++ .num_resources = ARRAY_SIZE(rtc_resources), ++ .resources = rtc_resources, ++ .id = PLATFORM_DEVID_NONE, ++ }, ++}; ++ ++static const struct mfd_cell rk817s[] = { ++ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, ++ { ++ .name = "rk805-pwrkey", ++ .num_resources = ARRAY_SIZE(rk817_pwrkey_resources), ++ .resources = &rk817_pwrkey_resources[0], ++ .id = PLATFORM_DEVID_NONE, ++ }, ++ { ++ .name = "rk808-rtc", ++ .num_resources = ARRAY_SIZE(rk817_rtc_resources), ++ .resources = &rk817_rtc_resources[0], ++ .id = PLATFORM_DEVID_NONE, ++ }, ++ { .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, }, ++ { ++ .name = "rk817-charger", ++ .num_resources = ARRAY_SIZE(rk817_charger_resources), ++ .resources = &rk817_charger_resources[0], ++ .id = PLATFORM_DEVID_NONE, ++ }, ++}; ++ ++static const struct mfd_cell rk818s[] = { ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, ++ { ++ .name = "rk808-rtc", ++ .num_resources = ARRAY_SIZE(rtc_resources), ++ .resources = rtc_resources, ++ .id = PLATFORM_DEVID_NONE, ++ }, ++}; ++ ++static const struct rk808_reg_data rk805_pre_init_reg[] = { ++ {RK805_BUCK1_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK, ++ RK805_BUCK1_2_ILMAX_4000MA}, ++ {RK805_BUCK2_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK, ++ RK805_BUCK1_2_ILMAX_4000MA}, ++ {RK805_BUCK3_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK, ++ RK805_BUCK3_ILMAX_3000MA}, ++ {RK805_BUCK4_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK, ++ RK805_BUCK4_ILMAX_3500MA}, ++ {RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA}, ++ {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C}, ++}; ++ ++static const struct rk808_reg_data rk808_pre_init_reg[] = { ++ { RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA }, ++ { RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA }, ++ { RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA }, ++ { RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK, BUCK_ILMIN_200MA }, ++ { RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_200MA }, ++ { RK808_DCDC_UV_ACT_REG, BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE}, ++ { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT | ++ VB_LO_SEL_3500MV }, ++}; ++ ++static const struct rk808_reg_data rk817_pre_init_reg[] = { ++ {RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP}, ++ /* Codec specific registers */ ++ { RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 }, ++ { RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 }, ++ /* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */ ++ { RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 }, ++ { RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 }, ++ { RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 }, ++ /* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */ ++ { RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_NG, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff }, ++ { RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff }, ++ { RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 }, ++ { RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 }, ++ { RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 }, ++ /* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */ ++ { RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 }, ++ { RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 }, ++ { RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 }, ++ { RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 }, ++ { RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff }, ++ { RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff }, ++ { RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 }, ++ { RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 }, ++ { RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 }, ++ /* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */ ++ { RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 }, ++ { RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 }, ++ { RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 }, ++ { RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 }, ++ { RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff }, ++ { RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff }, ++ { RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 }, ++ { RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 }, ++ { RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f }, ++ { RK817_CODEC_AHP_CP, MASK_ALL, 0x09 }, ++ { RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 }, ++ { RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 }, ++ { RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 }, ++ { RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 }, ++ { RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 }, ++ { RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 }, ++ { RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 }, ++ { RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 }, ++ { RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 }, ++ { RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 }, ++ { RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 }, ++ { RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 }, ++ {RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L}, ++ {RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK, ++ RK817_HOTDIE_105 | RK817_TSD_140}, ++}; ++ ++static const struct rk808_reg_data rk818_pre_init_reg[] = { ++ /* improve efficiency */ ++ { RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_250MA }, ++ { RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_250MA }, ++ { RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA }, ++ { RK818_USB_CTRL_REG, RK818_USB_ILIM_SEL_MASK, ++ RK818_USB_ILMIN_2000MA }, ++ /* close charger when usb lower then 3.4V */ ++ { RK818_USB_CTRL_REG, RK818_USB_CHG_SD_VSEL_MASK, ++ (0x7 << 4) }, ++ /* no action when vref */ ++ { RK818_H5V_EN_REG, BIT(1), RK818_REF_RDY_CTRL }, ++ /* enable HDMI 5V */ ++ { RK818_H5V_EN_REG, BIT(0), RK818_H5V_EN }, ++ { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT | ++ VB_LO_SEL_3500MV }, ++}; ++ ++static const struct regmap_irq rk805_irqs[] = { ++ [RK805_IRQ_PWRON_RISE] = { ++ .mask = RK805_IRQ_PWRON_RISE_MSK, ++ .reg_offset = 0, ++ }, ++ [RK805_IRQ_VB_LOW] = { ++ .mask = RK805_IRQ_VB_LOW_MSK, ++ .reg_offset = 0, ++ }, ++ [RK805_IRQ_PWRON] = { ++ .mask = RK805_IRQ_PWRON_MSK, ++ .reg_offset = 0, ++ }, ++ [RK805_IRQ_PWRON_LP] = { ++ .mask = RK805_IRQ_PWRON_LP_MSK, ++ .reg_offset = 0, ++ }, ++ [RK805_IRQ_HOTDIE] = { ++ .mask = RK805_IRQ_HOTDIE_MSK, ++ .reg_offset = 0, ++ }, ++ [RK805_IRQ_RTC_ALARM] = { ++ .mask = RK805_IRQ_RTC_ALARM_MSK, ++ .reg_offset = 0, ++ }, ++ [RK805_IRQ_RTC_PERIOD] = { ++ .mask = RK805_IRQ_RTC_PERIOD_MSK, ++ .reg_offset = 0, ++ }, ++ [RK805_IRQ_PWRON_FALL] = { ++ .mask = RK805_IRQ_PWRON_FALL_MSK, ++ .reg_offset = 0, ++ }, ++}; ++ ++static const struct regmap_irq rk808_irqs[] = { ++ /* INT_STS */ ++ [RK808_IRQ_VOUT_LO] = { ++ .mask = RK808_IRQ_VOUT_LO_MSK, ++ .reg_offset = 0, ++ }, ++ [RK808_IRQ_VB_LO] = { ++ .mask = RK808_IRQ_VB_LO_MSK, ++ .reg_offset = 0, ++ }, ++ [RK808_IRQ_PWRON] = { ++ .mask = RK808_IRQ_PWRON_MSK, ++ .reg_offset = 0, ++ }, ++ [RK808_IRQ_PWRON_LP] = { ++ .mask = RK808_IRQ_PWRON_LP_MSK, ++ .reg_offset = 0, ++ }, ++ [RK808_IRQ_HOTDIE] = { ++ .mask = RK808_IRQ_HOTDIE_MSK, ++ .reg_offset = 0, ++ }, ++ [RK808_IRQ_RTC_ALARM] = { ++ .mask = RK808_IRQ_RTC_ALARM_MSK, ++ .reg_offset = 0, ++ }, ++ [RK808_IRQ_RTC_PERIOD] = { ++ .mask = RK808_IRQ_RTC_PERIOD_MSK, ++ .reg_offset = 0, ++ }, ++ ++ /* INT_STS2 */ ++ [RK808_IRQ_PLUG_IN_INT] = { ++ .mask = RK808_IRQ_PLUG_IN_INT_MSK, ++ .reg_offset = 1, ++ }, ++ [RK808_IRQ_PLUG_OUT_INT] = { ++ .mask = RK808_IRQ_PLUG_OUT_INT_MSK, ++ .reg_offset = 1, ++ }, ++}; ++ ++static const struct regmap_irq rk818_irqs[] = { ++ /* INT_STS */ ++ [RK818_IRQ_VOUT_LO] = { ++ .mask = RK818_IRQ_VOUT_LO_MSK, ++ .reg_offset = 0, ++ }, ++ [RK818_IRQ_VB_LO] = { ++ .mask = RK818_IRQ_VB_LO_MSK, ++ .reg_offset = 0, ++ }, ++ [RK818_IRQ_PWRON] = { ++ .mask = RK818_IRQ_PWRON_MSK, ++ .reg_offset = 0, ++ }, ++ [RK818_IRQ_PWRON_LP] = { ++ .mask = RK818_IRQ_PWRON_LP_MSK, ++ .reg_offset = 0, ++ }, ++ [RK818_IRQ_HOTDIE] = { ++ .mask = RK818_IRQ_HOTDIE_MSK, ++ .reg_offset = 0, ++ }, ++ [RK818_IRQ_RTC_ALARM] = { ++ .mask = RK818_IRQ_RTC_ALARM_MSK, ++ .reg_offset = 0, ++ }, ++ [RK818_IRQ_RTC_PERIOD] = { ++ .mask = RK818_IRQ_RTC_PERIOD_MSK, ++ .reg_offset = 0, ++ }, ++ [RK818_IRQ_USB_OV] = { ++ .mask = RK818_IRQ_USB_OV_MSK, ++ .reg_offset = 0, ++ }, ++ ++ /* INT_STS2 */ ++ [RK818_IRQ_PLUG_IN] = { ++ .mask = RK818_IRQ_PLUG_IN_MSK, ++ .reg_offset = 1, ++ }, ++ [RK818_IRQ_PLUG_OUT] = { ++ .mask = RK818_IRQ_PLUG_OUT_MSK, ++ .reg_offset = 1, ++ }, ++ [RK818_IRQ_CHG_OK] = { ++ .mask = RK818_IRQ_CHG_OK_MSK, ++ .reg_offset = 1, ++ }, ++ [RK818_IRQ_CHG_TE] = { ++ .mask = RK818_IRQ_CHG_TE_MSK, ++ .reg_offset = 1, ++ }, ++ [RK818_IRQ_CHG_TS1] = { ++ .mask = RK818_IRQ_CHG_TS1_MSK, ++ .reg_offset = 1, ++ }, ++ [RK818_IRQ_TS2] = { ++ .mask = RK818_IRQ_TS2_MSK, ++ .reg_offset = 1, ++ }, ++ [RK818_IRQ_CHG_CVTLIM] = { ++ .mask = RK818_IRQ_CHG_CVTLIM_MSK, ++ .reg_offset = 1, ++ }, ++ [RK818_IRQ_DISCHG_ILIM] = { ++ .mask = RK818_IRQ_DISCHG_ILIM_MSK, ++ .reg_offset = 1, ++ }, ++}; ++ ++static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = { ++ REGMAP_IRQ_REG_LINE(0, 8), ++ REGMAP_IRQ_REG_LINE(1, 8), ++ REGMAP_IRQ_REG_LINE(2, 8), ++ REGMAP_IRQ_REG_LINE(3, 8), ++ REGMAP_IRQ_REG_LINE(4, 8), ++ REGMAP_IRQ_REG_LINE(5, 8), ++ REGMAP_IRQ_REG_LINE(6, 8), ++ REGMAP_IRQ_REG_LINE(7, 8), ++ REGMAP_IRQ_REG_LINE(8, 8), ++ REGMAP_IRQ_REG_LINE(9, 8), ++ REGMAP_IRQ_REG_LINE(10, 8), ++ REGMAP_IRQ_REG_LINE(11, 8), ++ REGMAP_IRQ_REG_LINE(12, 8), ++ REGMAP_IRQ_REG_LINE(13, 8), ++ REGMAP_IRQ_REG_LINE(14, 8), ++ REGMAP_IRQ_REG_LINE(15, 8), ++ REGMAP_IRQ_REG_LINE(16, 8), ++ REGMAP_IRQ_REG_LINE(17, 8), ++ REGMAP_IRQ_REG_LINE(18, 8), ++ REGMAP_IRQ_REG_LINE(19, 8), ++ REGMAP_IRQ_REG_LINE(20, 8), ++ REGMAP_IRQ_REG_LINE(21, 8), ++ REGMAP_IRQ_REG_LINE(22, 8), ++ REGMAP_IRQ_REG_LINE(23, 8) ++}; ++ ++static struct regmap_irq_chip rk805_irq_chip = { ++ .name = "rk805", ++ .irqs = rk805_irqs, ++ .num_irqs = ARRAY_SIZE(rk805_irqs), ++ .num_regs = 1, ++ .status_base = RK805_INT_STS_REG, ++ .mask_base = RK805_INT_STS_MSK_REG, ++ .ack_base = RK805_INT_STS_REG, ++ .init_ack_masked = true, ++}; ++ ++static const struct regmap_irq_chip rk808_irq_chip = { ++ .name = "rk808", ++ .irqs = rk808_irqs, ++ .num_irqs = ARRAY_SIZE(rk808_irqs), ++ .num_regs = 2, ++ .irq_reg_stride = 2, ++ .status_base = RK808_INT_STS_REG1, ++ .mask_base = RK808_INT_STS_MSK_REG1, ++ .ack_base = RK808_INT_STS_REG1, ++ .init_ack_masked = true, ++}; ++ ++static struct regmap_irq_chip rk817_irq_chip = { ++ .name = "rk817", ++ .irqs = rk817_irqs, ++ .num_irqs = ARRAY_SIZE(rk817_irqs), ++ .num_regs = 3, ++ .irq_reg_stride = 2, ++ .status_base = RK817_INT_STS_REG0, ++ .mask_base = RK817_INT_STS_MSK_REG0, ++ .ack_base = RK817_INT_STS_REG0, ++ .init_ack_masked = true, ++}; ++ ++static const struct regmap_irq_chip rk818_irq_chip = { ++ .name = "rk818", ++ .irqs = rk818_irqs, ++ .num_irqs = ARRAY_SIZE(rk818_irqs), ++ .num_regs = 2, ++ .irq_reg_stride = 2, ++ .status_base = RK818_INT_STS_REG1, ++ .mask_base = RK818_INT_STS_MSK_REG1, ++ .ack_base = RK818_INT_STS_REG1, ++ .init_ack_masked = true, ++}; ++ ++static int rk808_power_off(struct sys_off_data *data) ++{ ++ struct rk808 *rk808 = data->cb_data; ++ int ret; ++ unsigned int reg, bit; ++ ++ switch (rk808->variant) { ++ case RK805_ID: ++ reg = RK805_DEV_CTRL_REG; ++ bit = DEV_OFF; ++ break; ++ case RK808_ID: ++ reg = RK808_DEVCTRL_REG, ++ bit = DEV_OFF_RST; ++ break; ++ case RK809_ID: ++ case RK817_ID: ++ reg = RK817_SYS_CFG(3); ++ bit = DEV_OFF; ++ break; ++ case RK818_ID: ++ reg = RK818_DEVCTRL_REG; ++ bit = DEV_OFF; ++ break; ++ default: ++ return NOTIFY_DONE; ++ } ++ ret = regmap_update_bits(rk808->regmap, reg, bit, bit); ++ if (ret) ++ dev_err(rk808->dev, "Failed to shutdown device!\n"); ++ ++ return NOTIFY_DONE; ++} ++ ++static int rk808_restart(struct sys_off_data *data) ++{ ++ struct rk808 *rk808 = data->cb_data; ++ unsigned int reg, bit; ++ int ret; ++ ++ switch (rk808->variant) { ++ case RK809_ID: ++ case RK817_ID: ++ reg = RK817_SYS_CFG(3); ++ bit = DEV_RST; ++ break; ++ ++ default: ++ return NOTIFY_DONE; ++ } ++ ret = regmap_update_bits(rk808->regmap, reg, bit, bit); ++ if (ret) ++ dev_err(rk808->dev, "Failed to restart device!\n"); ++ ++ return NOTIFY_DONE; ++} ++ ++void rk8xx_shutdown(struct device *dev) ++{ ++ struct rk808 *rk808 = dev_get_drvdata(dev); ++ int ret; ++ ++ switch (rk808->variant) { ++ case RK805_ID: ++ ret = regmap_update_bits(rk808->regmap, ++ RK805_GPIO_IO_POL_REG, ++ SLP_SD_MSK, ++ SHUTDOWN_FUN); ++ break; ++ case RK809_ID: ++ case RK817_ID: ++ ret = regmap_update_bits(rk808->regmap, ++ RK817_SYS_CFG(3), ++ RK817_SLPPIN_FUNC_MSK, ++ SLPPIN_DN_FUN); ++ break; ++ default: ++ return; ++ } ++ if (ret) ++ dev_warn(dev, ++ "Cannot switch to power down function\n"); ++} ++EXPORT_SYMBOL_GPL(rk8xx_shutdown); ++ ++int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap) ++{ ++ struct rk808 *rk808; ++ const struct rk808_reg_data *pre_init_reg; ++ const struct mfd_cell *cells; ++ int nr_pre_init_regs; ++ int nr_cells; ++ int ret; ++ int i; ++ ++ rk808 = devm_kzalloc(dev, sizeof(*rk808), GFP_KERNEL); ++ if (!rk808) ++ return -ENOMEM; ++ rk808->dev = dev; ++ rk808->variant = variant; ++ rk808->regmap = regmap; ++ dev_set_drvdata(dev, rk808); ++ ++ switch (rk808->variant) { ++ case RK805_ID: ++ rk808->regmap_irq_chip = &rk805_irq_chip; ++ pre_init_reg = rk805_pre_init_reg; ++ nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg); ++ cells = rk805s; ++ nr_cells = ARRAY_SIZE(rk805s); ++ break; ++ case RK808_ID: ++ rk808->regmap_irq_chip = &rk808_irq_chip; ++ pre_init_reg = rk808_pre_init_reg; ++ nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg); ++ cells = rk808s; ++ nr_cells = ARRAY_SIZE(rk808s); ++ break; ++ case RK818_ID: ++ rk808->regmap_irq_chip = &rk818_irq_chip; ++ pre_init_reg = rk818_pre_init_reg; ++ nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg); ++ cells = rk818s; ++ nr_cells = ARRAY_SIZE(rk818s); ++ break; ++ case RK809_ID: ++ case RK817_ID: ++ rk808->regmap_irq_chip = &rk817_irq_chip; ++ pre_init_reg = rk817_pre_init_reg; ++ nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg); ++ cells = rk817s; ++ nr_cells = ARRAY_SIZE(rk817s); ++ break; ++ default: ++ dev_err(dev, "Unsupported RK8XX ID %lu\n", rk808->variant); ++ return -EINVAL; ++ } ++ ++ dev_info(dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); ++ ++ if (!irq) ++ return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n"); ++ ++ ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq, ++ IRQF_ONESHOT, -1, ++ rk808->regmap_irq_chip, &rk808->irq_data); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to add irq_chip\n"); ++ ++ for (i = 0; i < nr_pre_init_regs; i++) { ++ ret = regmap_update_bits(rk808->regmap, ++ pre_init_reg[i].addr, ++ pre_init_reg[i].mask, ++ pre_init_reg[i].value); ++ if (ret) ++ return dev_err_probe(dev, ret, "0x%x write err\n", ++ pre_init_reg[i].addr); ++ } ++ ++ ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ++ cells, nr_cells, NULL, 0, ++ regmap_irq_get_domain(rk808->irq_data)); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to add MFD devices\n"); ++ ++ if (device_property_read_bool(dev, "rockchip,system-power-controller")) { ++ ret = devm_register_sys_off_handler(dev, ++ SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH, ++ &rk808_power_off, rk808); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to register poweroff handler\n"); ++ ++ switch (rk808->variant) { ++ case RK809_ID: ++ case RK817_ID: ++ ret = devm_register_sys_off_handler(dev, ++ SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH, ++ &rk808_restart, rk808); ++ if (ret) ++ dev_warn(dev, "failed to register rst handler, %d\n", ret); ++ break; ++ default: ++ dev_dbg(dev, "pmic controlled board reset not supported\n"); ++ break; ++ } ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(rk8xx_probe); ++ ++int rk8xx_suspend(struct device *dev) ++{ ++ struct rk808 *rk808 = dev_get_drvdata(dev); ++ int ret = 0; ++ ++ switch (rk808->variant) { ++ case RK805_ID: ++ ret = regmap_update_bits(rk808->regmap, ++ RK805_GPIO_IO_POL_REG, ++ SLP_SD_MSK, ++ SLEEP_FUN); ++ break; ++ case RK809_ID: ++ case RK817_ID: ++ ret = regmap_update_bits(rk808->regmap, ++ RK817_SYS_CFG(3), ++ RK817_SLPPIN_FUNC_MSK, ++ SLPPIN_SLP_FUN); ++ break; ++ default: ++ break; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rk8xx_suspend); ++ ++int rk8xx_resume(struct device *dev) ++{ ++ struct rk808 *rk808 = dev_get_drvdata(dev); ++ int ret = 0; ++ ++ switch (rk808->variant) { ++ case RK809_ID: ++ case RK817_ID: ++ ret = regmap_update_bits(rk808->regmap, ++ RK817_SYS_CFG(3), ++ RK817_SLPPIN_FUNC_MSK, ++ SLPPIN_NULL_FUN); ++ break; ++ default: ++ break; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rk8xx_resume); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chris Zhong "); ++MODULE_AUTHOR("Zhang Qing "); ++MODULE_AUTHOR("Wadim Egorov "); ++MODULE_DESCRIPTION("RK8xx PMIC core"); +--- /dev/null ++++ b/drivers/mfd/rk8xx-i2c.c +@@ -0,0 +1,200 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip RK808/RK818 Core (I2C) driver ++ * ++ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (C) 2016 PHYTEC Messtechnik GmbH ++ * ++ * Author: Chris Zhong ++ * Author: Zhang Qing ++ * Author: Wadim Egorov ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ /* ++ * Notes: ++ * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but ++ * we don't use that feature. It's better to cache. ++ * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since ++ * bits are cleared in case when we shutoff anyway, but better safe. ++ */ ++ ++ switch (reg) { ++ case RK808_SECONDS_REG ... RK808_WEEKS_REG: ++ case RK808_RTC_STATUS_REG: ++ case RK808_VB_MON_REG: ++ case RK808_THERMAL_REG: ++ case RK808_DCDC_UV_STS_REG: ++ case RK808_LDO_UV_STS_REG: ++ case RK808_DCDC_PG_REG: ++ case RK808_LDO_PG_REG: ++ case RK808_DEVCTRL_REG: ++ case RK808_INT_STS_REG1: ++ case RK808_INT_STS_REG2: ++ return true; ++ } ++ ++ return false; ++} ++ ++static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ /* ++ * Notes: ++ * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but ++ * we don't use that feature. It's better to cache. ++ */ ++ ++ switch (reg) { ++ case RK817_SECONDS_REG ... RK817_WEEKS_REG: ++ case RK817_RTC_STATUS_REG: ++ case RK817_CODEC_DTOP_LPT_SRST: ++ case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0: ++ case RK817_PMIC_CHRG_STS: ++ case RK817_PMIC_CHRG_OUT: ++ case RK817_PMIC_CHRG_IN: ++ case RK817_INT_STS_REG0: ++ case RK817_INT_STS_REG1: ++ case RK817_INT_STS_REG2: ++ case RK817_SYS_STS: ++ return true; ++ } ++ ++ return false; ++} ++ ++ ++static const struct regmap_config rk818_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = RK818_USB_CTRL_REG, ++ .cache_type = REGCACHE_RBTREE, ++ .volatile_reg = rk808_is_volatile_reg, ++}; ++ ++static const struct regmap_config rk805_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = RK805_OFF_SOURCE_REG, ++ .cache_type = REGCACHE_RBTREE, ++ .volatile_reg = rk808_is_volatile_reg, ++}; ++ ++static const struct regmap_config rk808_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = RK808_IO_POL_REG, ++ .cache_type = REGCACHE_RBTREE, ++ .volatile_reg = rk808_is_volatile_reg, ++}; ++ ++static const struct regmap_config rk817_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = RK817_GPIO_INT_CFG, ++ .cache_type = REGCACHE_NONE, ++ .volatile_reg = rk817_is_volatile_reg, ++}; ++ ++static int rk8xx_i2c_get_variant(struct i2c_client *client) ++{ ++ u8 pmic_id_msb, pmic_id_lsb; ++ int msb, lsb; ++ ++ if (of_device_is_compatible(client->dev.of_node, "rockchip,rk817") || ++ of_device_is_compatible(client->dev.of_node, "rockchip,rk809")) { ++ pmic_id_msb = RK817_ID_MSB; ++ pmic_id_lsb = RK817_ID_LSB; ++ } else { ++ pmic_id_msb = RK808_ID_MSB; ++ pmic_id_lsb = RK808_ID_LSB; ++ } ++ ++ /* Read chip variant */ ++ msb = i2c_smbus_read_byte_data(client, pmic_id_msb); ++ if (msb < 0) ++ return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); ++ ++ lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); ++ if (lsb < 0) ++ return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); ++ ++ return ((msb << 8) | lsb) & RK8XX_ID_MSK; ++} ++ ++static int rk8xx_i2c_probe(struct i2c_client *client) ++{ ++ const struct regmap_config *regmap_cfg; ++ struct regmap *regmap; ++ int variant; ++ ++ variant = rk8xx_i2c_get_variant(client); ++ if (variant < 0) ++ return variant; ++ ++ switch (variant) { ++ case RK805_ID: ++ regmap_cfg = &rk805_regmap_config; ++ break; ++ case RK808_ID: ++ regmap_cfg = &rk808_regmap_config; ++ break; ++ case RK818_ID: ++ regmap_cfg = &rk818_regmap_config; ++ break; ++ case RK809_ID: ++ case RK817_ID: ++ regmap_cfg = &rk817_regmap_config; ++ break; ++ default: ++ return dev_err_probe(&client->dev, -EINVAL, "Unsupported RK8XX ID %x\n", variant); ++ } ++ ++ regmap = devm_regmap_init_i2c(client, regmap_cfg); ++ if (IS_ERR(regmap)) ++ return dev_err_probe(&client->dev, PTR_ERR(regmap), ++ "regmap initialization failed\n"); ++ ++ return rk8xx_probe(&client->dev, variant, client->irq, regmap); ++} ++ ++static void rk8xx_i2c_shutdown(struct i2c_client *client) ++{ ++ rk8xx_shutdown(&client->dev); ++} ++ ++static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume); ++ ++static const struct of_device_id rk8xx_i2c_of_match[] = { ++ { .compatible = "rockchip,rk805" }, ++ { .compatible = "rockchip,rk808" }, ++ { .compatible = "rockchip,rk809" }, ++ { .compatible = "rockchip,rk817" }, ++ { .compatible = "rockchip,rk818" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match); ++ ++static struct i2c_driver rk8xx_i2c_driver = { ++ .driver = { ++ .name = "rk8xx-i2c", ++ .of_match_table = rk8xx_i2c_of_match, ++ .pm = &rk8xx_i2c_pm_ops, ++ }, ++ .probe_new = rk8xx_i2c_probe, ++ .shutdown = rk8xx_i2c_shutdown, ++}; ++module_i2c_driver(rk8xx_i2c_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chris Zhong "); ++MODULE_AUTHOR("Zhang Qing "); ++MODULE_AUTHOR("Wadim Egorov "); ++MODULE_DESCRIPTION("RK8xx I2C PMIC driver"); +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -396,7 +396,7 @@ config PINCTRL_PISTACHIO + + config PINCTRL_RK805 + tristate "Pinctrl and GPIO driver for RK805 PMIC" +- depends on MFD_RK808 ++ depends on MFD_RK8XX + select GPIOLIB + select PINMUX + select GENERIC_PINCONF +--- a/drivers/power/supply/Kconfig ++++ b/drivers/power/supply/Kconfig +@@ -725,7 +725,7 @@ config CHARGER_BQ256XX + + config CHARGER_RK817 + tristate "Rockchip RK817 PMIC Battery Charger" +- depends on MFD_RK808 ++ depends on MFD_RK8XX + help + Say Y to include support for Rockchip RK817 Battery Charger. + +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -1039,7 +1039,7 @@ config REGULATOR_RC5T583 + + config REGULATOR_RK808 + tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power regulators" +- depends on MFD_RK808 ++ depends on MFD_RK8XX + help + Select this option to enable the power regulator of ROCKCHIP + PMIC RK805,RK809&RK817,RK808 and RK818. +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -395,7 +395,7 @@ config RTC_DRV_NCT3018Y + + config RTC_DRV_RK808 + tristate "Rockchip RK805/RK808/RK809/RK817/RK818 RTC" +- depends on MFD_RK808 ++ depends on MFD_RK8XX + help + If you say yes here you will get support for the + RTC of RK805, RK809 and RK817, RK808 and RK818 PMIC. +--- a/include/linux/mfd/rk808.h ++++ b/include/linux/mfd/rk808.h +@@ -794,4 +794,10 @@ struct rk808 { + const struct regmap_config *regmap_cfg; + const struct regmap_irq_chip *regmap_irq_chip; + }; ++ ++void rk8xx_shutdown(struct device *dev); ++int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap); ++int rk8xx_suspend(struct device *dev); ++int rk8xx_resume(struct device *dev); ++ + #endif /* __LINUX_REGULATOR_RK808_H */ +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -1211,7 +1211,7 @@ config SND_SOC_RK3328 + + config SND_SOC_RK817 + tristate "Rockchip RK817 audio CODEC" +- depends on MFD_RK808 || COMPILE_TEST ++ depends on MFD_RK8XX || COMPILE_TEST + + config SND_SOC_RL6231 + tristate diff --git a/target/linux/rockchip/patches-6.1/031-09-v6.5-mfd-rk8xx-i2c-Use-device_get_match_data.patch b/target/linux/rockchip/patches-6.1/031-09-v6.5-mfd-rk8xx-i2c-Use-device_get_match_data.patch new file mode 100644 index 0000000000..5873038a52 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-09-v6.5-mfd-rk8xx-i2c-Use-device_get_match_data.patch @@ -0,0 +1,158 @@ +From 74413bd611b4fd21fdf90e369780b2f8543447a4 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:10 +0200 +Subject: [PATCH] mfd: rk8xx-i2c: Use device_get_match_data + +Simplify the device identification logic by supplying the relevant +information via of_match_data. This also removes the dev_info() +printing the chip version, since that's supplied by the match data +now. + +Due to lack of hardware this change is compile-tested only. + +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-7-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/mfd/rk8xx-core.c | 2 - + drivers/mfd/rk8xx-i2c.c | 89 +++++++++++++++++----------------------- + 2 files changed, 37 insertions(+), 54 deletions(-) + +--- a/drivers/mfd/rk8xx-core.c ++++ b/drivers/mfd/rk8xx-core.c +@@ -596,8 +596,6 @@ int rk8xx_probe(struct device *dev, int + return -EINVAL; + } + +- dev_info(dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); +- + if (!irq) + return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n"); + +--- a/drivers/mfd/rk8xx-i2c.c ++++ b/drivers/mfd/rk8xx-i2c.c +@@ -16,6 +16,11 @@ + #include + #include + ++struct rk8xx_i2c_platform_data { ++ const struct regmap_config *regmap_cfg; ++ int variant; ++}; ++ + static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) + { + /* +@@ -103,66 +108,46 @@ static const struct regmap_config rk817_ + .volatile_reg = rk817_is_volatile_reg, + }; + +-static int rk8xx_i2c_get_variant(struct i2c_client *client) +-{ +- u8 pmic_id_msb, pmic_id_lsb; +- int msb, lsb; ++static const struct rk8xx_i2c_platform_data rk805_data = { ++ .regmap_cfg = &rk805_regmap_config, ++ .variant = RK805_ID, ++}; + +- if (of_device_is_compatible(client->dev.of_node, "rockchip,rk817") || +- of_device_is_compatible(client->dev.of_node, "rockchip,rk809")) { +- pmic_id_msb = RK817_ID_MSB; +- pmic_id_lsb = RK817_ID_LSB; +- } else { +- pmic_id_msb = RK808_ID_MSB; +- pmic_id_lsb = RK808_ID_LSB; +- } ++static const struct rk8xx_i2c_platform_data rk808_data = { ++ .regmap_cfg = &rk808_regmap_config, ++ .variant = RK808_ID, ++}; + +- /* Read chip variant */ +- msb = i2c_smbus_read_byte_data(client, pmic_id_msb); +- if (msb < 0) +- return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); +- +- lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); +- if (lsb < 0) +- return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); ++static const struct rk8xx_i2c_platform_data rk809_data = { ++ .regmap_cfg = &rk817_regmap_config, ++ .variant = RK809_ID, ++}; + +- return ((msb << 8) | lsb) & RK8XX_ID_MSK; +-} ++static const struct rk8xx_i2c_platform_data rk817_data = { ++ .regmap_cfg = &rk817_regmap_config, ++ .variant = RK817_ID, ++}; ++ ++static const struct rk8xx_i2c_platform_data rk818_data = { ++ .regmap_cfg = &rk818_regmap_config, ++ .variant = RK818_ID, ++}; + + static int rk8xx_i2c_probe(struct i2c_client *client) + { +- const struct regmap_config *regmap_cfg; ++ const struct rk8xx_i2c_platform_data *data; + struct regmap *regmap; +- int variant; + +- variant = rk8xx_i2c_get_variant(client); +- if (variant < 0) +- return variant; +- +- switch (variant) { +- case RK805_ID: +- regmap_cfg = &rk805_regmap_config; +- break; +- case RK808_ID: +- regmap_cfg = &rk808_regmap_config; +- break; +- case RK818_ID: +- regmap_cfg = &rk818_regmap_config; +- break; +- case RK809_ID: +- case RK817_ID: +- regmap_cfg = &rk817_regmap_config; +- break; +- default: +- return dev_err_probe(&client->dev, -EINVAL, "Unsupported RK8XX ID %x\n", variant); +- } ++ data = device_get_match_data(&client->dev); ++ if (!data) ++ return -ENODEV; + +- regmap = devm_regmap_init_i2c(client, regmap_cfg); ++ regmap = devm_regmap_init_i2c(client, data->regmap_cfg); + if (IS_ERR(regmap)) + return dev_err_probe(&client->dev, PTR_ERR(regmap), + "regmap initialization failed\n"); + +- return rk8xx_probe(&client->dev, variant, client->irq, regmap); ++ return rk8xx_probe(&client->dev, data->variant, client->irq, regmap); + } + + static void rk8xx_i2c_shutdown(struct i2c_client *client) +@@ -173,11 +158,11 @@ static void rk8xx_i2c_shutdown(struct i2 + static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume); + + static const struct of_device_id rk8xx_i2c_of_match[] = { +- { .compatible = "rockchip,rk805" }, +- { .compatible = "rockchip,rk808" }, +- { .compatible = "rockchip,rk809" }, +- { .compatible = "rockchip,rk817" }, +- { .compatible = "rockchip,rk818" }, ++ { .compatible = "rockchip,rk805", .data = &rk805_data }, ++ { .compatible = "rockchip,rk808", .data = &rk808_data }, ++ { .compatible = "rockchip,rk809", .data = &rk809_data }, ++ { .compatible = "rockchip,rk817", .data = &rk817_data }, ++ { .compatible = "rockchip,rk818", .data = &rk818_data }, + { }, + }; + MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match); diff --git a/target/linux/rockchip/patches-6.1/031-10-v6.5-mfd-rk8xx-Add-rk806-support.patch b/target/linux/rockchip/patches-6.1/031-10-v6.5-mfd-rk8xx-Add-rk806-support.patch new file mode 100644 index 0000000000..14d952c240 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-10-v6.5-mfd-rk8xx-Add-rk806-support.patch @@ -0,0 +1,743 @@ +From 210f418f8ace9f056c337f7945e0ae3e242b3389 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:12 +0200 +Subject: [PATCH] mfd: rk8xx: Add rk806 support + +Add support for SPI connected rk806, which is used by the RK3588 +evaluation boards. The PMIC is advertised to support I2C and SPI, +but the evaluation boards all use SPI. Thus only SPI support is +added here. + +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-9-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/mfd/Kconfig | 14 ++ + drivers/mfd/Makefile | 1 + + drivers/mfd/rk8xx-core.c | 69 ++++++- + drivers/mfd/rk8xx-spi.c | 124 ++++++++++++ + include/linux/mfd/rk808.h | 409 ++++++++++++++++++++++++++++++++++++++ + 5 files changed, 614 insertions(+), 3 deletions(-) + create mode 100644 drivers/mfd/rk8xx-spi.c + +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -1220,6 +1220,20 @@ config MFD_RK8XX_I2C + through I2C interface. The device supports multiple sub-devices + including interrupts, RTC, LDO & DCDC regulators, and onkey. + ++config MFD_RK8XX_SPI ++ tristate "Rockchip RK806 Power Management Chip" ++ depends on SPI && OF ++ select MFD_CORE ++ select REGMAP_SPI ++ select REGMAP_IRQ ++ select MFD_RK8XX ++ help ++ If you say yes here you get support for the RK806 Power Management ++ chip. ++ This driver provides common support for accessing the device ++ through an SPI interface. The device supports multiple sub-devices ++ including interrupts, LDO & DCDC regulators, and power on-key. ++ + config MFD_RN5T618 + tristate "Ricoh RN5T567/618 PMIC" + depends on I2C +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -225,6 +225,7 @@ obj-$(CONFIG_MFD_NTXEC) += ntxec.o + obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o + obj-$(CONFIG_MFD_RK8XX) += rk8xx-core.o + obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o ++obj-$(CONFIG_MFD_RK8XX_SPI) += rk8xx-spi.o + obj-$(CONFIG_MFD_RN5T618) += rn5t618.o + obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o + obj-$(CONFIG_MFD_SYSCON) += syscon.o +--- a/drivers/mfd/rk8xx-core.c ++++ b/drivers/mfd/rk8xx-core.c +@@ -37,6 +37,11 @@ static const struct resource rk805_key_r + DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL), + }; + ++static struct resource rk806_pwrkey_resources[] = { ++ DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL), ++ DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE), ++}; ++ + static const struct resource rk817_pwrkey_resources[] = { + DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), + DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL), +@@ -64,6 +69,17 @@ static const struct mfd_cell rk805s[] = + }, + }; + ++static const struct mfd_cell rk806s[] = { ++ { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, }, ++ { .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, }, ++ { ++ .name = "rk805-pwrkey", ++ .resources = rk806_pwrkey_resources, ++ .num_resources = ARRAY_SIZE(rk806_pwrkey_resources), ++ .id = PLATFORM_DEVID_AUTO, ++ }, ++}; ++ + static const struct mfd_cell rk808s[] = { + { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, + { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, +@@ -122,6 +138,12 @@ static const struct rk808_reg_data rk805 + {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C}, + }; + ++static const struct rk808_reg_data rk806_pre_init_reg[] = { ++ { RK806_GPIO_INT_CONFIG, RK806_INT_POL_MSK, RK806_INT_POL_L }, ++ { RK806_SYS_CFG3, RK806_SLAVE_RESTART_FUN_MSK, RK806_SLAVE_RESTART_FUN_EN }, ++ { RK806_SYS_OPTION, RK806_SYS_ENB2_2M_MSK, RK806_SYS_ENB2_2M_EN }, ++}; ++ + static const struct rk808_reg_data rk808_pre_init_reg[] = { + { RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA }, + { RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA }, +@@ -272,6 +294,27 @@ static const struct regmap_irq rk805_irq + }, + }; + ++static const struct regmap_irq rk806_irqs[] = { ++ /* INT_STS0 IRQs */ ++ REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL), ++ REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE), ++ REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON), ++ REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP), ++ REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE), ++ REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE), ++ REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL), ++ REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO), ++ /* INT_STS1 IRQs */ ++ REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0), ++ REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1), ++ REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2), ++ REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR), ++ REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO), ++ REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO), ++ REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO), ++ REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT), ++}; ++ + static const struct regmap_irq rk808_irqs[] = { + /* INT_STS */ + [RK808_IRQ_VOUT_LO] = { +@@ -422,6 +465,18 @@ static struct regmap_irq_chip rk805_irq_ + .init_ack_masked = true, + }; + ++static struct regmap_irq_chip rk806_irq_chip = { ++ .name = "rk806", ++ .irqs = rk806_irqs, ++ .num_irqs = ARRAY_SIZE(rk806_irqs), ++ .num_regs = 2, ++ .irq_reg_stride = 2, ++ .mask_base = RK806_INT_MSK0, ++ .status_base = RK806_INT_STS0, ++ .ack_base = RK806_INT_STS0, ++ .init_ack_masked = true, ++}; ++ + static const struct regmap_irq_chip rk808_irq_chip = { + .name = "rk808", + .irqs = rk808_irqs, +@@ -548,6 +603,7 @@ int rk8xx_probe(struct device *dev, int + struct rk808 *rk808; + const struct rk808_reg_data *pre_init_reg; + const struct mfd_cell *cells; ++ int dual_support = 0; + int nr_pre_init_regs; + int nr_cells; + int ret; +@@ -569,6 +625,14 @@ int rk8xx_probe(struct device *dev, int + cells = rk805s; + nr_cells = ARRAY_SIZE(rk805s); + break; ++ case RK806_ID: ++ rk808->regmap_irq_chip = &rk806_irq_chip; ++ pre_init_reg = rk806_pre_init_reg; ++ nr_pre_init_regs = ARRAY_SIZE(rk806_pre_init_reg); ++ cells = rk806s; ++ nr_cells = ARRAY_SIZE(rk806s); ++ dual_support = IRQF_SHARED; ++ break; + case RK808_ID: + rk808->regmap_irq_chip = &rk808_irq_chip; + pre_init_reg = rk808_pre_init_reg; +@@ -600,7 +664,7 @@ int rk8xx_probe(struct device *dev, int + return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n"); + + ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq, +- IRQF_ONESHOT, -1, ++ IRQF_ONESHOT | dual_support, -1, + rk808->regmap_irq_chip, &rk808->irq_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to add irq_chip\n"); +@@ -615,8 +679,7 @@ int rk8xx_probe(struct device *dev, int + pre_init_reg[i].addr); + } + +- ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, +- cells, nr_cells, NULL, 0, ++ ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0, + regmap_irq_get_domain(rk808->irq_data)); + if (ret) + return dev_err_probe(dev, ret, "failed to add MFD devices\n"); +--- /dev/null ++++ b/drivers/mfd/rk8xx-spi.c +@@ -0,0 +1,124 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip RK806 Core (SPI) driver ++ * ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2023 Collabora Ltd. ++ * ++ * Author: Xu Shengfei ++ * Author: Sebastian Reichel ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RK806_ADDR_SIZE 2 ++#define RK806_CMD_WITH_SIZE(CMD, VALUE_BYTES) \ ++ (RK806_CMD_##CMD | RK806_CMD_CRC_DIS | (VALUE_BYTES - 1)) ++ ++static const struct regmap_range rk806_volatile_ranges[] = { ++ regmap_reg_range(RK806_POWER_EN0, RK806_POWER_EN5), ++ regmap_reg_range(RK806_DVS_START_CTRL, RK806_INT_MSK1), ++}; ++ ++static const struct regmap_access_table rk806_volatile_table = { ++ .yes_ranges = rk806_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(rk806_volatile_ranges), ++}; ++ ++static const struct regmap_config rk806_regmap_config_spi = { ++ .reg_bits = 16, ++ .val_bits = 8, ++ .max_register = RK806_BUCK_RSERVE_REG5, ++ .cache_type = REGCACHE_RBTREE, ++ .volatile_table = &rk806_volatile_table, ++}; ++ ++static int rk806_spi_bus_write(void *context, const void *vdata, size_t count) ++{ ++ struct device *dev = context; ++ struct spi_device *spi = to_spi_device(dev); ++ struct spi_transfer xfer[2] = { 0 }; ++ /* data and thus count includes the register address */ ++ size_t val_size = count - RK806_ADDR_SIZE; ++ char cmd; ++ ++ if (val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1)) ++ return -EINVAL; ++ ++ cmd = RK806_CMD_WITH_SIZE(WRITE, val_size); ++ ++ xfer[0].tx_buf = &cmd; ++ xfer[0].len = sizeof(cmd); ++ xfer[1].tx_buf = vdata; ++ xfer[1].len = count; ++ ++ return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); ++} ++ ++static int rk806_spi_bus_read(void *context, const void *vreg, size_t reg_size, ++ void *val, size_t val_size) ++{ ++ struct device *dev = context; ++ struct spi_device *spi = to_spi_device(dev); ++ char txbuf[3] = { 0 }; ++ ++ if (reg_size != RK806_ADDR_SIZE || ++ val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1)) ++ return -EINVAL; ++ ++ /* TX buffer contains command byte followed by two address bytes */ ++ txbuf[0] = RK806_CMD_WITH_SIZE(READ, val_size); ++ memcpy(txbuf+1, vreg, reg_size); ++ ++ return spi_write_then_read(spi, txbuf, sizeof(txbuf), val, val_size); ++} ++ ++static const struct regmap_bus rk806_regmap_bus_spi = { ++ .write = rk806_spi_bus_write, ++ .read = rk806_spi_bus_read, ++ .reg_format_endian_default = REGMAP_ENDIAN_LITTLE, ++}; ++ ++static int rk8xx_spi_probe(struct spi_device *spi) ++{ ++ struct regmap *regmap; ++ ++ regmap = devm_regmap_init(&spi->dev, &rk806_regmap_bus_spi, ++ &spi->dev, &rk806_regmap_config_spi); ++ if (IS_ERR(regmap)) ++ return dev_err_probe(&spi->dev, PTR_ERR(regmap), ++ "Failed to init regmap\n"); ++ ++ return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap); ++} ++ ++static const struct of_device_id rk8xx_spi_of_match[] = { ++ { .compatible = "rockchip,rk806", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, rk8xx_spi_of_match); ++ ++static const struct spi_device_id rk8xx_spi_id_table[] = { ++ { "rk806", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(spi, rk8xx_spi_id_table); ++ ++static struct spi_driver rk8xx_spi_driver = { ++ .driver = { ++ .name = "rk8xx-spi", ++ .of_match_table = rk8xx_spi_of_match, ++ }, ++ .probe = rk8xx_spi_probe, ++ .id_table = rk8xx_spi_id_table, ++}; ++module_spi_driver(rk8xx_spi_driver); ++ ++MODULE_AUTHOR("Xu Shengfei "); ++MODULE_DESCRIPTION("RK8xx SPI PMIC driver"); ++MODULE_LICENSE("GPL"); +--- a/include/linux/mfd/rk808.h ++++ b/include/linux/mfd/rk808.h +@@ -289,6 +289,414 @@ enum rk805_reg { + #define RK805_INT_ALARM_EN (1 << 3) + #define RK805_INT_TIMER_EN (1 << 2) + ++/* RK806 */ ++#define RK806_POWER_EN0 0x0 ++#define RK806_POWER_EN1 0x1 ++#define RK806_POWER_EN2 0x2 ++#define RK806_POWER_EN3 0x3 ++#define RK806_POWER_EN4 0x4 ++#define RK806_POWER_EN5 0x5 ++#define RK806_POWER_SLP_EN0 0x6 ++#define RK806_POWER_SLP_EN1 0x7 ++#define RK806_POWER_SLP_EN2 0x8 ++#define RK806_POWER_DISCHRG_EN0 0x9 ++#define RK806_POWER_DISCHRG_EN1 0xA ++#define RK806_POWER_DISCHRG_EN2 0xB ++#define RK806_BUCK_FB_CONFIG 0xC ++#define RK806_SLP_LP_CONFIG 0xD ++#define RK806_POWER_FPWM_EN0 0xE ++#define RK806_POWER_FPWM_EN1 0xF ++#define RK806_BUCK1_CONFIG 0x10 ++#define RK806_BUCK2_CONFIG 0x11 ++#define RK806_BUCK3_CONFIG 0x12 ++#define RK806_BUCK4_CONFIG 0x13 ++#define RK806_BUCK5_CONFIG 0x14 ++#define RK806_BUCK6_CONFIG 0x15 ++#define RK806_BUCK7_CONFIG 0x16 ++#define RK806_BUCK8_CONFIG 0x17 ++#define RK806_BUCK9_CONFIG 0x18 ++#define RK806_BUCK10_CONFIG 0x19 ++#define RK806_BUCK1_ON_VSEL 0x1A ++#define RK806_BUCK2_ON_VSEL 0x1B ++#define RK806_BUCK3_ON_VSEL 0x1C ++#define RK806_BUCK4_ON_VSEL 0x1D ++#define RK806_BUCK5_ON_VSEL 0x1E ++#define RK806_BUCK6_ON_VSEL 0x1F ++#define RK806_BUCK7_ON_VSEL 0x20 ++#define RK806_BUCK8_ON_VSEL 0x21 ++#define RK806_BUCK9_ON_VSEL 0x22 ++#define RK806_BUCK10_ON_VSEL 0x23 ++#define RK806_BUCK1_SLP_VSEL 0x24 ++#define RK806_BUCK2_SLP_VSEL 0x25 ++#define RK806_BUCK3_SLP_VSEL 0x26 ++#define RK806_BUCK4_SLP_VSEL 0x27 ++#define RK806_BUCK5_SLP_VSEL 0x28 ++#define RK806_BUCK6_SLP_VSEL 0x29 ++#define RK806_BUCK7_SLP_VSEL 0x2A ++#define RK806_BUCK8_SLP_VSEL 0x2B ++#define RK806_BUCK9_SLP_VSEL 0x2D ++#define RK806_BUCK10_SLP_VSEL 0x2E ++#define RK806_BUCK_DEBUG1 0x30 ++#define RK806_BUCK_DEBUG2 0x31 ++#define RK806_BUCK_DEBUG3 0x32 ++#define RK806_BUCK_DEBUG4 0x33 ++#define RK806_BUCK_DEBUG5 0x34 ++#define RK806_BUCK_DEBUG6 0x35 ++#define RK806_BUCK_DEBUG7 0x36 ++#define RK806_BUCK_DEBUG8 0x37 ++#define RK806_BUCK_DEBUG9 0x38 ++#define RK806_BUCK_DEBUG10 0x39 ++#define RK806_BUCK_DEBUG11 0x3A ++#define RK806_BUCK_DEBUG12 0x3B ++#define RK806_BUCK_DEBUG13 0x3C ++#define RK806_BUCK_DEBUG14 0x3D ++#define RK806_BUCK_DEBUG15 0x3E ++#define RK806_BUCK_DEBUG16 0x3F ++#define RK806_BUCK_DEBUG17 0x40 ++#define RK806_BUCK_DEBUG18 0x41 ++#define RK806_NLDO_IMAX 0x42 ++#define RK806_NLDO1_ON_VSEL 0x43 ++#define RK806_NLDO2_ON_VSEL 0x44 ++#define RK806_NLDO3_ON_VSEL 0x45 ++#define RK806_NLDO4_ON_VSEL 0x46 ++#define RK806_NLDO5_ON_VSEL 0x47 ++#define RK806_NLDO1_SLP_VSEL 0x48 ++#define RK806_NLDO2_SLP_VSEL 0x49 ++#define RK806_NLDO3_SLP_VSEL 0x4A ++#define RK806_NLDO4_SLP_VSEL 0x4B ++#define RK806_NLDO5_SLP_VSEL 0x4C ++#define RK806_PLDO_IMAX 0x4D ++#define RK806_PLDO1_ON_VSEL 0x4E ++#define RK806_PLDO2_ON_VSEL 0x4F ++#define RK806_PLDO3_ON_VSEL 0x50 ++#define RK806_PLDO4_ON_VSEL 0x51 ++#define RK806_PLDO5_ON_VSEL 0x52 ++#define RK806_PLDO6_ON_VSEL 0x53 ++#define RK806_PLDO1_SLP_VSEL 0x54 ++#define RK806_PLDO2_SLP_VSEL 0x55 ++#define RK806_PLDO3_SLP_VSEL 0x56 ++#define RK806_PLDO4_SLP_VSEL 0x57 ++#define RK806_PLDO5_SLP_VSEL 0x58 ++#define RK806_PLDO6_SLP_VSEL 0x59 ++#define RK806_CHIP_NAME 0x5A ++#define RK806_CHIP_VER 0x5B ++#define RK806_OTP_VER 0x5C ++#define RK806_SYS_STS 0x5D ++#define RK806_SYS_CFG0 0x5E ++#define RK806_SYS_CFG1 0x5F ++#define RK806_SYS_OPTION 0x61 ++#define RK806_SLEEP_CONFIG0 0x62 ++#define RK806_SLEEP_CONFIG1 0x63 ++#define RK806_SLEEP_CTR_SEL0 0x64 ++#define RK806_SLEEP_CTR_SEL1 0x65 ++#define RK806_SLEEP_CTR_SEL2 0x66 ++#define RK806_SLEEP_CTR_SEL3 0x67 ++#define RK806_SLEEP_CTR_SEL4 0x68 ++#define RK806_SLEEP_CTR_SEL5 0x69 ++#define RK806_DVS_CTRL_SEL0 0x6A ++#define RK806_DVS_CTRL_SEL1 0x6B ++#define RK806_DVS_CTRL_SEL2 0x6C ++#define RK806_DVS_CTRL_SEL3 0x6D ++#define RK806_DVS_CTRL_SEL4 0x6E ++#define RK806_DVS_CTRL_SEL5 0x6F ++#define RK806_DVS_START_CTRL 0x70 ++#define RK806_SLEEP_GPIO 0x71 ++#define RK806_SYS_CFG3 0x72 ++#define RK806_ON_SOURCE 0x74 ++#define RK806_OFF_SOURCE 0x75 ++#define RK806_PWRON_KEY 0x76 ++#define RK806_INT_STS0 0x77 ++#define RK806_INT_MSK0 0x78 ++#define RK806_INT_STS1 0x79 ++#define RK806_INT_MSK1 0x7A ++#define RK806_GPIO_INT_CONFIG 0x7B ++#define RK806_DATA_REG0 0x7C ++#define RK806_DATA_REG1 0x7D ++#define RK806_DATA_REG2 0x7E ++#define RK806_DATA_REG3 0x7F ++#define RK806_DATA_REG4 0x80 ++#define RK806_DATA_REG5 0x81 ++#define RK806_DATA_REG6 0x82 ++#define RK806_DATA_REG7 0x83 ++#define RK806_DATA_REG8 0x84 ++#define RK806_DATA_REG9 0x85 ++#define RK806_DATA_REG10 0x86 ++#define RK806_DATA_REG11 0x87 ++#define RK806_DATA_REG12 0x88 ++#define RK806_DATA_REG13 0x89 ++#define RK806_DATA_REG14 0x8A ++#define RK806_DATA_REG15 0x8B ++#define RK806_TM_REG 0x8C ++#define RK806_OTP_EN_REG 0x8D ++#define RK806_FUNC_OTP_EN_REG 0x8E ++#define RK806_TEST_REG1 0x8F ++#define RK806_TEST_REG2 0x90 ++#define RK806_TEST_REG3 0x91 ++#define RK806_TEST_REG4 0x92 ++#define RK806_TEST_REG5 0x93 ++#define RK806_BUCK_VSEL_OTP_REG0 0x94 ++#define RK806_BUCK_VSEL_OTP_REG1 0x95 ++#define RK806_BUCK_VSEL_OTP_REG2 0x96 ++#define RK806_BUCK_VSEL_OTP_REG3 0x97 ++#define RK806_BUCK_VSEL_OTP_REG4 0x98 ++#define RK806_BUCK_VSEL_OTP_REG5 0x99 ++#define RK806_BUCK_VSEL_OTP_REG6 0x9A ++#define RK806_BUCK_VSEL_OTP_REG7 0x9B ++#define RK806_BUCK_VSEL_OTP_REG8 0x9C ++#define RK806_BUCK_VSEL_OTP_REG9 0x9D ++#define RK806_NLDO1_VSEL_OTP_REG0 0x9E ++#define RK806_NLDO1_VSEL_OTP_REG1 0x9F ++#define RK806_NLDO1_VSEL_OTP_REG2 0xA0 ++#define RK806_NLDO1_VSEL_OTP_REG3 0xA1 ++#define RK806_NLDO1_VSEL_OTP_REG4 0xA2 ++#define RK806_PLDO_VSEL_OTP_REG0 0xA3 ++#define RK806_PLDO_VSEL_OTP_REG1 0xA4 ++#define RK806_PLDO_VSEL_OTP_REG2 0xA5 ++#define RK806_PLDO_VSEL_OTP_REG3 0xA6 ++#define RK806_PLDO_VSEL_OTP_REG4 0xA7 ++#define RK806_PLDO_VSEL_OTP_REG5 0xA8 ++#define RK806_BUCK_EN_OTP_REG1 0xA9 ++#define RK806_NLDO_EN_OTP_REG1 0xAA ++#define RK806_PLDO_EN_OTP_REG1 0xAB ++#define RK806_BUCK_FB_RES_OTP_REG1 0xAC ++#define RK806_OTP_RESEV_REG0 0xAD ++#define RK806_OTP_RESEV_REG1 0xAE ++#define RK806_OTP_RESEV_REG2 0xAF ++#define RK806_OTP_RESEV_REG3 0xB0 ++#define RK806_OTP_RESEV_REG4 0xB1 ++#define RK806_BUCK_SEQ_REG0 0xB2 ++#define RK806_BUCK_SEQ_REG1 0xB3 ++#define RK806_BUCK_SEQ_REG2 0xB4 ++#define RK806_BUCK_SEQ_REG3 0xB5 ++#define RK806_BUCK_SEQ_REG4 0xB6 ++#define RK806_BUCK_SEQ_REG5 0xB7 ++#define RK806_BUCK_SEQ_REG6 0xB8 ++#define RK806_BUCK_SEQ_REG7 0xB9 ++#define RK806_BUCK_SEQ_REG8 0xBA ++#define RK806_BUCK_SEQ_REG9 0xBB ++#define RK806_BUCK_SEQ_REG10 0xBC ++#define RK806_BUCK_SEQ_REG11 0xBD ++#define RK806_BUCK_SEQ_REG12 0xBE ++#define RK806_BUCK_SEQ_REG13 0xBF ++#define RK806_BUCK_SEQ_REG14 0xC0 ++#define RK806_BUCK_SEQ_REG15 0xC1 ++#define RK806_BUCK_SEQ_REG16 0xC2 ++#define RK806_BUCK_SEQ_REG17 0xC3 ++#define RK806_HK_TRIM_REG1 0xC4 ++#define RK806_HK_TRIM_REG2 0xC5 ++#define RK806_BUCK_REF_TRIM_REG1 0xC6 ++#define RK806_BUCK_REF_TRIM_REG2 0xC7 ++#define RK806_BUCK_REF_TRIM_REG3 0xC8 ++#define RK806_BUCK_REF_TRIM_REG4 0xC9 ++#define RK806_BUCK_REF_TRIM_REG5 0xCA ++#define RK806_BUCK_OSC_TRIM_REG1 0xCB ++#define RK806_BUCK_OSC_TRIM_REG2 0xCC ++#define RK806_BUCK_OSC_TRIM_REG3 0xCD ++#define RK806_BUCK_OSC_TRIM_REG4 0xCE ++#define RK806_BUCK_OSC_TRIM_REG5 0xCF ++#define RK806_BUCK_TRIM_ZCDIOS_REG1 0xD0 ++#define RK806_BUCK_TRIM_ZCDIOS_REG2 0xD1 ++#define RK806_NLDO_TRIM_REG1 0xD2 ++#define RK806_NLDO_TRIM_REG2 0xD3 ++#define RK806_NLDO_TRIM_REG3 0xD4 ++#define RK806_PLDO_TRIM_REG1 0xD5 ++#define RK806_PLDO_TRIM_REG2 0xD6 ++#define RK806_PLDO_TRIM_REG3 0xD7 ++#define RK806_TRIM_ICOMP_REG1 0xD8 ++#define RK806_TRIM_ICOMP_REG2 0xD9 ++#define RK806_EFUSE_CONTROL_REGH 0xDA ++#define RK806_FUSE_PROG_REG 0xDB ++#define RK806_MAIN_FSM_STS_REG 0xDD ++#define RK806_FSM_REG 0xDE ++#define RK806_TOP_RESEV_OFFR 0xEC ++#define RK806_TOP_RESEV_POR 0xED ++#define RK806_BUCK_VRSN_REG1 0xEE ++#define RK806_BUCK_VRSN_REG2 0xEF ++#define RK806_NLDO_RLOAD_SEL_REG1 0xF0 ++#define RK806_PLDO_RLOAD_SEL_REG1 0xF1 ++#define RK806_PLDO_RLOAD_SEL_REG2 0xF2 ++#define RK806_BUCK_CMIN_MX_REG1 0xF3 ++#define RK806_BUCK_CMIN_MX_REG2 0xF4 ++#define RK806_BUCK_FREQ_SET_REG1 0xF5 ++#define RK806_BUCK_FREQ_SET_REG2 0xF6 ++#define RK806_BUCK_RS_MEABS_REG1 0xF7 ++#define RK806_BUCK_RS_MEABS_REG2 0xF8 ++#define RK806_BUCK_RS_ZDLEB_REG1 0xF9 ++#define RK806_BUCK_RS_ZDLEB_REG2 0xFA ++#define RK806_BUCK_RSERVE_REG1 0xFB ++#define RK806_BUCK_RSERVE_REG2 0xFC ++#define RK806_BUCK_RSERVE_REG3 0xFD ++#define RK806_BUCK_RSERVE_REG4 0xFE ++#define RK806_BUCK_RSERVE_REG5 0xFF ++ ++/* INT_STS Register field definitions */ ++#define RK806_INT_STS_PWRON_FALL BIT(0) ++#define RK806_INT_STS_PWRON_RISE BIT(1) ++#define RK806_INT_STS_PWRON BIT(2) ++#define RK806_INT_STS_PWRON_LP BIT(3) ++#define RK806_INT_STS_HOTDIE BIT(4) ++#define RK806_INT_STS_VDC_RISE BIT(5) ++#define RK806_INT_STS_VDC_FALL BIT(6) ++#define RK806_INT_STS_VB_LO BIT(7) ++#define RK806_INT_STS_REV0 BIT(0) ++#define RK806_INT_STS_REV1 BIT(1) ++#define RK806_INT_STS_REV2 BIT(2) ++#define RK806_INT_STS_CRC_ERROR BIT(3) ++#define RK806_INT_STS_SLP3_GPIO BIT(4) ++#define RK806_INT_STS_SLP2_GPIO BIT(5) ++#define RK806_INT_STS_SLP1_GPIO BIT(6) ++#define RK806_INT_STS_WDT BIT(7) ++ ++/* SPI command */ ++#define RK806_CMD_READ 0 ++#define RK806_CMD_WRITE BIT(7) ++#define RK806_CMD_CRC_EN BIT(6) ++#define RK806_CMD_CRC_DIS 0 ++#define RK806_CMD_LEN_MSK 0x0f ++#define RK806_REG_H 0x00 ++ ++#define VERSION_AB 0x01 ++ ++enum rk806_reg_id { ++ RK806_ID_DCDC1 = 0, ++ RK806_ID_DCDC2, ++ RK806_ID_DCDC3, ++ RK806_ID_DCDC4, ++ RK806_ID_DCDC5, ++ RK806_ID_DCDC6, ++ RK806_ID_DCDC7, ++ RK806_ID_DCDC8, ++ RK806_ID_DCDC9, ++ RK806_ID_DCDC10, ++ ++ RK806_ID_NLDO1, ++ RK806_ID_NLDO2, ++ RK806_ID_NLDO3, ++ RK806_ID_NLDO4, ++ RK806_ID_NLDO5, ++ ++ RK806_ID_PLDO1, ++ RK806_ID_PLDO2, ++ RK806_ID_PLDO3, ++ RK806_ID_PLDO4, ++ RK806_ID_PLDO5, ++ RK806_ID_PLDO6, ++ RK806_ID_END, ++}; ++ ++/* Define the RK806 IRQ numbers */ ++enum rk806_irqs { ++ /* INT_STS0 registers */ ++ RK806_IRQ_PWRON_FALL, ++ RK806_IRQ_PWRON_RISE, ++ RK806_IRQ_PWRON, ++ RK806_IRQ_PWRON_LP, ++ RK806_IRQ_HOTDIE, ++ RK806_IRQ_VDC_RISE, ++ RK806_IRQ_VDC_FALL, ++ RK806_IRQ_VB_LO, ++ ++ /* INT_STS0 registers */ ++ RK806_IRQ_REV0, ++ RK806_IRQ_REV1, ++ RK806_IRQ_REV2, ++ RK806_IRQ_CRC_ERROR, ++ RK806_IRQ_SLP3_GPIO, ++ RK806_IRQ_SLP2_GPIO, ++ RK806_IRQ_SLP1_GPIO, ++ RK806_IRQ_WDT, ++}; ++ ++/* VCC1 Low Voltage Threshold */ ++enum rk806_lv_sel { ++ VB_LO_SEL_2800, ++ VB_LO_SEL_2900, ++ VB_LO_SEL_3000, ++ VB_LO_SEL_3100, ++ VB_LO_SEL_3200, ++ VB_LO_SEL_3300, ++ VB_LO_SEL_3400, ++ VB_LO_SEL_3500, ++}; ++ ++/* System Shutdown Voltage Select */ ++enum rk806_uv_sel { ++ VB_UV_SEL_2700, ++ VB_UV_SEL_2800, ++ VB_UV_SEL_2900, ++ VB_UV_SEL_3000, ++ VB_UV_SEL_3100, ++ VB_UV_SEL_3200, ++ VB_UV_SEL_3300, ++ VB_UV_SEL_3400, ++}; ++ ++/* Pin Function */ ++enum rk806_pwrctrl_fun { ++ PWRCTRL_NULL_FUN, ++ PWRCTRL_SLP_FUN, ++ PWRCTRL_POWOFF_FUN, ++ PWRCTRL_RST_FUN, ++ PWRCTRL_DVS_FUN, ++ PWRCTRL_GPIO_FUN, ++}; ++ ++/* Pin Polarity */ ++enum rk806_pin_level { ++ POL_LOW, ++ POL_HIGH, ++}; ++ ++enum rk806_vsel_ctr_sel { ++ CTR_BY_NO_EFFECT, ++ CTR_BY_PWRCTRL1, ++ CTR_BY_PWRCTRL2, ++ CTR_BY_PWRCTRL3, ++}; ++ ++enum rk806_dvs_ctr_sel { ++ CTR_SEL_NO_EFFECT, ++ CTR_SEL_DVS_START1, ++ CTR_SEL_DVS_START2, ++ CTR_SEL_DVS_START3, ++}; ++ ++enum rk806_pin_dr_sel { ++ RK806_PIN_INPUT, ++ RK806_PIN_OUTPUT, ++}; ++ ++#define RK806_INT_POL_MSK BIT(1) ++#define RK806_INT_POL_H BIT(1) ++#define RK806_INT_POL_L 0 ++ ++#define RK806_SLAVE_RESTART_FUN_MSK BIT(1) ++#define RK806_SLAVE_RESTART_FUN_EN BIT(1) ++#define RK806_SLAVE_RESTART_FUN_OFF 0 ++ ++#define RK806_SYS_ENB2_2M_MSK BIT(1) ++#define RK806_SYS_ENB2_2M_EN BIT(1) ++#define RK806_SYS_ENB2_2M_OFF 0 ++ ++enum rk806_int_fun { ++ RK806_INT_ONLY, ++ RK806_INT_ADN_WKUP, ++}; ++ ++enum rk806_dvs_mode { ++ RK806_DVS_NOT_SUPPORT, ++ RK806_DVS_START1, ++ RK806_DVS_START2, ++ RK806_DVS_START3, ++ RK806_DVS_PWRCTRL1, ++ RK806_DVS_PWRCTRL2, ++ RK806_DVS_PWRCTRL3, ++ RK806_DVS_START_PWRCTR1, ++ RK806_DVS_START_PWRCTR2, ++ RK806_DVS_START_PWRCTR3, ++ RK806_DVS_END, ++}; ++ + /* RK808 IRQ Definitions */ + #define RK808_IRQ_VOUT_LO 0 + #define RK808_IRQ_VB_LO 1 +@@ -780,6 +1188,7 @@ enum { + + enum { + RK805_ID = 0x8050, ++ RK806_ID = 0x8060, + RK808_ID = 0x0000, + RK809_ID = 0x8090, + RK817_ID = 0x8170, diff --git a/target/linux/rockchip/patches-6.1/031-11-v6.5-pinctrl-rk805-Add-rk806-pinctrl-support.patch b/target/linux/rockchip/patches-6.1/031-11-v6.5-pinctrl-rk805-Add-rk806-pinctrl-support.patch new file mode 100644 index 0000000000..165bd939b6 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-11-v6.5-pinctrl-rk805-Add-rk806-pinctrl-support.patch @@ -0,0 +1,338 @@ +From 924764aa5f2e705f46f548611e6a9d6b986ae880 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:13 +0200 +Subject: [PATCH] pinctrl: rk805: Add rk806 pinctrl support + +Add support for rk806 dvs pinctrl to the existing rk805 +driver. + +This has been implemented using shengfei Xu's rk806 +specific driver from the vendor tree as reference. + +Co-developed-by: shengfei Xu +Signed-off-by: shengfei Xu +Reviewed-by: Linus Walleij +Acked-by: Linus Walleij +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-10-sebastian.reichel@collabora.com +Signed-off-by: Lee Jones +--- + drivers/pinctrl/pinctrl-rk805.c | 189 ++++++++++++++++++++++++++++---- + 1 file changed, 168 insertions(+), 21 deletions(-) + +--- a/drivers/pinctrl/pinctrl-rk805.c ++++ b/drivers/pinctrl/pinctrl-rk805.c +@@ -1,10 +1,12 @@ + // SPDX-License-Identifier: GPL-2.0-or-later + /* +- * Pinctrl driver for Rockchip RK805 PMIC ++ * Pinctrl driver for Rockchip RK805/RK806 PMIC + * + * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * Author: Joseph Chen ++ * Author: Xu Shengfei + * + * Based on the pinctrl-as3722 driver + */ +@@ -44,6 +46,7 @@ struct rk805_pin_group { + + /* + * @reg: gpio setting register; ++ * @fun_reg: functions select register; + * @fun_mask: functions select mask value, when set is gpio; + * @dir_mask: input or output mask value, when set is output, otherwise input; + * @val_mask: gpio set value, when set is level high, otherwise low; +@@ -56,6 +59,7 @@ struct rk805_pin_group { + */ + struct rk805_pin_config { + u8 reg; ++ u8 fun_reg; + u8 fun_msk; + u8 dir_msk; + u8 val_msk; +@@ -80,22 +84,50 @@ enum rk805_pinmux_option { + RK805_PINMUX_GPIO, + }; + ++enum rk806_pinmux_option { ++ RK806_PINMUX_FUN0 = 0, ++ RK806_PINMUX_FUN1, ++ RK806_PINMUX_FUN2, ++ RK806_PINMUX_FUN3, ++ RK806_PINMUX_FUN4, ++ RK806_PINMUX_FUN5, ++}; ++ + enum { + RK805_GPIO0, + RK805_GPIO1, + }; + ++enum { ++ RK806_GPIO_DVS1, ++ RK806_GPIO_DVS2, ++ RK806_GPIO_DVS3 ++}; ++ + static const char *const rk805_gpio_groups[] = { + "gpio0", + "gpio1", + }; + ++static const char *const rk806_gpio_groups[] = { ++ "gpio_pwrctrl1", ++ "gpio_pwrctrl2", ++ "gpio_pwrctrl3", ++}; ++ + /* RK805: 2 output only GPIOs */ + static const struct pinctrl_pin_desc rk805_pins_desc[] = { + PINCTRL_PIN(RK805_GPIO0, "gpio0"), + PINCTRL_PIN(RK805_GPIO1, "gpio1"), + }; + ++/* RK806 */ ++static const struct pinctrl_pin_desc rk806_pins_desc[] = { ++ PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"), ++ PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"), ++ PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"), ++}; ++ + static const struct rk805_pin_function rk805_pin_functions[] = { + { + .name = "gpio", +@@ -105,6 +137,45 @@ static const struct rk805_pin_function r + }, + }; + ++static const struct rk805_pin_function rk806_pin_functions[] = { ++ { ++ .name = "pin_fun0", ++ .groups = rk806_gpio_groups, ++ .ngroups = ARRAY_SIZE(rk806_gpio_groups), ++ .mux_option = RK806_PINMUX_FUN0, ++ }, ++ { ++ .name = "pin_fun1", ++ .groups = rk806_gpio_groups, ++ .ngroups = ARRAY_SIZE(rk806_gpio_groups), ++ .mux_option = RK806_PINMUX_FUN1, ++ }, ++ { ++ .name = "pin_fun2", ++ .groups = rk806_gpio_groups, ++ .ngroups = ARRAY_SIZE(rk806_gpio_groups), ++ .mux_option = RK806_PINMUX_FUN2, ++ }, ++ { ++ .name = "pin_fun3", ++ .groups = rk806_gpio_groups, ++ .ngroups = ARRAY_SIZE(rk806_gpio_groups), ++ .mux_option = RK806_PINMUX_FUN3, ++ }, ++ { ++ .name = "pin_fun4", ++ .groups = rk806_gpio_groups, ++ .ngroups = ARRAY_SIZE(rk806_gpio_groups), ++ .mux_option = RK806_PINMUX_FUN4, ++ }, ++ { ++ .name = "pin_fun5", ++ .groups = rk806_gpio_groups, ++ .ngroups = ARRAY_SIZE(rk806_gpio_groups), ++ .mux_option = RK806_PINMUX_FUN5, ++ }, ++}; ++ + static const struct rk805_pin_group rk805_pin_groups[] = { + { + .name = "gpio0", +@@ -118,6 +189,24 @@ static const struct rk805_pin_group rk80 + }, + }; + ++static const struct rk805_pin_group rk806_pin_groups[] = { ++ { ++ .name = "gpio_pwrctrl1", ++ .pins = { RK806_GPIO_DVS1 }, ++ .npins = 1, ++ }, ++ { ++ .name = "gpio_pwrctrl2", ++ .pins = { RK806_GPIO_DVS2 }, ++ .npins = 1, ++ }, ++ { ++ .name = "gpio_pwrctrl3", ++ .pins = { RK806_GPIO_DVS3 }, ++ .npins = 1, ++ } ++}; ++ + #define RK805_GPIO0_VAL_MSK BIT(0) + #define RK805_GPIO1_VAL_MSK BIT(1) + +@@ -132,6 +221,40 @@ static const struct rk805_pin_config rk8 + }, + }; + ++#define RK806_PWRCTRL1_DR BIT(0) ++#define RK806_PWRCTRL2_DR BIT(1) ++#define RK806_PWRCTRL3_DR BIT(2) ++#define RK806_PWRCTRL1_DATA BIT(4) ++#define RK806_PWRCTRL2_DATA BIT(5) ++#define RK806_PWRCTRL3_DATA BIT(6) ++#define RK806_PWRCTRL1_FUN GENMASK(2, 0) ++#define RK806_PWRCTRL2_FUN GENMASK(6, 4) ++#define RK806_PWRCTRL3_FUN GENMASK(2, 0) ++ ++static struct rk805_pin_config rk806_gpio_cfgs[] = { ++ { ++ .fun_reg = RK806_SLEEP_CONFIG0, ++ .fun_msk = RK806_PWRCTRL1_FUN, ++ .reg = RK806_SLEEP_GPIO, ++ .val_msk = RK806_PWRCTRL1_DATA, ++ .dir_msk = RK806_PWRCTRL1_DR, ++ }, ++ { ++ .fun_reg = RK806_SLEEP_CONFIG0, ++ .fun_msk = RK806_PWRCTRL2_FUN, ++ .reg = RK806_SLEEP_GPIO, ++ .val_msk = RK806_PWRCTRL2_DATA, ++ .dir_msk = RK806_PWRCTRL2_DR, ++ }, ++ { ++ .fun_reg = RK806_SLEEP_CONFIG1, ++ .fun_msk = RK806_PWRCTRL3_FUN, ++ .reg = RK806_SLEEP_GPIO, ++ .val_msk = RK806_PWRCTRL3_DATA, ++ .dir_msk = RK806_PWRCTRL3_DR, ++ } ++}; ++ + /* generic gpio chip */ + static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset) + { +@@ -289,19 +412,13 @@ static int _rk805_pinctrl_set_mux(struct + if (!pci->pin_cfg[offset].fun_msk) + return 0; + +- if (mux == RK805_PINMUX_GPIO) { +- ret = regmap_update_bits(pci->rk808->regmap, +- pci->pin_cfg[offset].reg, +- pci->pin_cfg[offset].fun_msk, +- pci->pin_cfg[offset].fun_msk); +- if (ret) { +- dev_err(pci->dev, "set gpio%d GPIO failed\n", offset); +- return ret; +- } +- } else { +- dev_err(pci->dev, "Couldn't find function mux %d\n", mux); +- return -EINVAL; +- } ++ mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1; ++ ret = regmap_update_bits(pci->rk808->regmap, ++ pci->pin_cfg[offset].fun_reg, ++ pci->pin_cfg[offset].fun_msk, mux); ++ ++ if (ret) ++ dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux); + + return 0; + } +@@ -317,6 +434,22 @@ static int rk805_pinctrl_set_mux(struct + return _rk805_pinctrl_set_mux(pctldev, offset, mux); + } + ++static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int offset) ++{ ++ struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); ++ ++ switch (pci->rk808->variant) { ++ case RK805_ID: ++ return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); ++ case RK806_ID: ++ return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5); ++ } ++ ++ return -ENOTSUPP; ++} ++ + static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +@@ -324,13 +457,6 @@ static int rk805_pmx_gpio_set_direction( + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + int ret; + +- /* switch to gpio function */ +- ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); +- if (ret) { +- dev_err(pci->dev, "set gpio%d mux failed\n", offset); +- return ret; +- } +- + /* set direction */ + if (!pci->pin_cfg[offset].dir_msk) + return 0; +@@ -352,6 +478,7 @@ static const struct pinmux_ops rk805_pin + .get_function_name = rk805_pinctrl_get_func_name, + .get_function_groups = rk805_pinctrl_get_func_groups, + .set_mux = rk805_pinctrl_set_mux, ++ .gpio_request_enable = rk805_pinctrl_gpio_request_enable, + .gpio_set_direction = rk805_pmx_gpio_set_direction, + }; + +@@ -364,6 +491,7 @@ static int rk805_pinconf_get(struct pinc + + switch (param) { + case PIN_CONFIG_OUTPUT: ++ case PIN_CONFIG_INPUT_ENABLE: + arg = rk805_gpio_get(&pci->gpio_chip, pin); + break; + default: +@@ -393,6 +521,12 @@ static int rk805_pinconf_set(struct pinc + rk805_gpio_set(&pci->gpio_chip, pin, arg); + rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false); + break; ++ case PIN_CONFIG_INPUT_ENABLE: ++ if (pci->rk808->variant != RK805_ID && arg) { ++ rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true); ++ break; ++ } ++ fallthrough; + default: + dev_err(pci->dev, "Properties not supported\n"); + return -ENOTSUPP; +@@ -448,6 +582,18 @@ static int rk805_pinctrl_probe(struct pl + pci->pin_cfg = rk805_gpio_cfgs; + pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs); + break; ++ case RK806_ID: ++ pci->pins = rk806_pins_desc; ++ pci->num_pins = ARRAY_SIZE(rk806_pins_desc); ++ pci->functions = rk806_pin_functions; ++ pci->num_functions = ARRAY_SIZE(rk806_pin_functions); ++ pci->groups = rk806_pin_groups; ++ pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups); ++ pci->pinctrl_desc.pins = rk806_pins_desc; ++ pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc); ++ pci->pin_cfg = rk806_gpio_cfgs; ++ pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs); ++ break; + default: + dev_err(&pdev->dev, "unsupported RK805 ID %lu\n", + pci->rk808->variant); +@@ -488,5 +634,6 @@ static struct platform_driver rk805_pinc + module_platform_driver(rk805_pinctrl_driver); + + MODULE_DESCRIPTION("RK805 pin control and GPIO driver"); ++MODULE_AUTHOR("Xu Shengfei "); + MODULE_AUTHOR("Joseph Chen "); + MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/patches-6.1/032-01-v6.2-regulator-rk808-reduce-struct-rk808-usage.patch b/target/linux/rockchip/patches-6.1/032-01-v6.2-regulator-rk808-reduce-struct-rk808-usage.patch new file mode 100644 index 0000000000..8fe5bd0c42 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-01-v6.2-regulator-rk808-reduce-struct-rk808-usage.patch @@ -0,0 +1,82 @@ +From 647e57351f8ebc37d8e12cbc0f4bf7471754a0cc Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Oct 2022 22:42:40 +0200 +Subject: [PATCH] regulator: rk808: reduce 'struct rk808' usage + +Reduce usage of 'struct rk808' (driver data of the parent MFD), so +that only the chip variant field is still being accessed directly. +This allows restructuring the MFD driver to support SPI based +PMICs. + +Acked-by: Mark Brown +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221020204251.108565-3-sebastian.reichel@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/rk808-regulator.c | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + +--- a/drivers/regulator/rk808-regulator.c ++++ b/drivers/regulator/rk808-regulator.c +@@ -14,7 +14,6 @@ + + #include + #include +-#include + #include + #include + #include +@@ -1286,19 +1285,23 @@ dt_parse_end: + static int rk808_regulator_probe(struct platform_device *pdev) + { + struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent); +- struct i2c_client *client = rk808->i2c; + struct regulator_config config = {}; + struct regulator_dev *rk808_rdev; + struct rk808_regulator_data *pdata; + const struct regulator_desc *regulators; ++ struct regmap *regmap; + int ret, i, nregulators; + ++ regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (!regmap) ++ return -ENODEV; ++ + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + +- ret = rk808_regulator_dt_parse_pdata(&pdev->dev, &client->dev, +- rk808->regmap, pdata); ++ ret = rk808_regulator_dt_parse_pdata(&pdev->dev, pdev->dev.parent, ++ regmap, pdata); + if (ret < 0) + return ret; + +@@ -1326,21 +1329,22 @@ static int rk808_regulator_probe(struct + nregulators = RK818_NUM_REGULATORS; + break; + default: +- dev_err(&client->dev, "unsupported RK8XX ID %lu\n", ++ dev_err(&pdev->dev, "unsupported RK8XX ID %lu\n", + rk808->variant); + return -EINVAL; + } + +- config.dev = &client->dev; ++ config.dev = &pdev->dev; ++ config.dev->of_node = pdev->dev.parent->of_node; + config.driver_data = pdata; +- config.regmap = rk808->regmap; ++ config.regmap = regmap; + + /* Instantiate the regulators */ + for (i = 0; i < nregulators; i++) { + rk808_rdev = devm_regulator_register(&pdev->dev, + ®ulators[i], &config); + if (IS_ERR(rk808_rdev)) { +- dev_err(&client->dev, ++ dev_err(&pdev->dev, + "failed to register %d regulator\n", i); + return PTR_ERR(rk808_rdev); + } diff --git a/target/linux/rockchip/patches-6.1/032-02-v6.2-regulator-rk808-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/032-02-v6.2-regulator-rk808-Use-dev_err_probe.patch new file mode 100644 index 0000000000..22d085ee20 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-02-v6.2-regulator-rk808-Use-dev_err_probe.patch @@ -0,0 +1,34 @@ +From f39f8709c217d82aabbf51d8669731137ce09aea Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Oct 2022 22:42:49 +0200 +Subject: [PATCH] regulator: rk808: Use dev_err_probe + +Print error message for potential EPROBE_DEFER error using +dev_err_probe, which captures the reason in +/sys/kernel/debug/devices_deferred and otherwise silences +the message. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20221020204251.108565-12-sebastian.reichel@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/rk808-regulator.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/drivers/regulator/rk808-regulator.c ++++ b/drivers/regulator/rk808-regulator.c +@@ -1343,11 +1343,9 @@ static int rk808_regulator_probe(struct + for (i = 0; i < nregulators; i++) { + rk808_rdev = devm_regulator_register(&pdev->dev, + ®ulators[i], &config); +- if (IS_ERR(rk808_rdev)) { +- dev_err(&pdev->dev, +- "failed to register %d regulator\n", i); +- return PTR_ERR(rk808_rdev); +- } ++ if (IS_ERR(rk808_rdev)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(rk808_rdev), ++ "failed to register %d regulator\n", i); + } + + return 0; diff --git a/target/linux/rockchip/patches-6.1/032-03-v6.5-regulator-expose-regulator_find_closest_bigger.patch b/target/linux/rockchip/patches-6.1/032-03-v6.5-regulator-expose-regulator_find_closest_bigger.patch new file mode 100644 index 0000000000..2d7595c53c --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-03-v6.5-regulator-expose-regulator_find_closest_bigger.patch @@ -0,0 +1,76 @@ +From 431cb97b763133fba8b1c68c1ed089315f25e4dd Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:14 +0200 +Subject: [PATCH] regulator: expose regulator_find_closest_bigger + +Expose and document the table lookup logic used by +regulator_set_ramp_delay_regmap, so that it can be +reused for devices that cannot be configured via +regulator_set_ramp_delay_regmap. + +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-11-sebastian.reichel@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/helpers.c | 22 ++++++++++++++++++---- + include/linux/regulator/driver.h | 2 ++ + 2 files changed, 20 insertions(+), 4 deletions(-) + +--- a/drivers/regulator/helpers.c ++++ b/drivers/regulator/helpers.c +@@ -902,8 +902,21 @@ bool regulator_is_equal(struct regulator + } + EXPORT_SYMBOL_GPL(regulator_is_equal); + +-static int find_closest_bigger(unsigned int target, const unsigned int *table, +- unsigned int num_sel, unsigned int *sel) ++/** ++ * regulator_find_closest_bigger - helper to find offset in ramp delay table ++ * ++ * @target: targeted ramp_delay ++ * @table: table with supported ramp delays ++ * @num_sel: number of entries in the table ++ * @sel: Pointer to store table offset ++ * ++ * This is the internal helper used by regulator_set_ramp_delay_regmap to ++ * map ramp delay to register value. It should only be used directly if ++ * regulator_set_ramp_delay_regmap cannot handle a specific device setup ++ * (e.g. because the value is split over multiple registers). ++ */ ++int regulator_find_closest_bigger(unsigned int target, const unsigned int *table, ++ unsigned int num_sel, unsigned int *sel) + { + unsigned int s, tmp, max, maxsel = 0; + bool found = false; +@@ -933,6 +946,7 @@ static int find_closest_bigger(unsigned + + return 0; + } ++EXPORT_SYMBOL_GPL(regulator_find_closest_bigger); + + /** + * regulator_set_ramp_delay_regmap - set_ramp_delay() helper +@@ -951,8 +965,8 @@ int regulator_set_ramp_delay_regmap(stru + if (WARN_ON(!rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table)) + return -EINVAL; + +- ret = find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, +- rdev->desc->n_ramp_values, &sel); ++ ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, ++ rdev->desc->n_ramp_values, &sel); + + if (ret) { + dev_warn(rdev_get_dev(rdev), +--- a/include/linux/regulator/driver.h ++++ b/include/linux/regulator/driver.h +@@ -758,6 +758,8 @@ int regulator_set_current_limit_regmap(s + int min_uA, int max_uA); + int regulator_get_current_limit_regmap(struct regulator_dev *rdev); + void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data); ++int regulator_find_closest_bigger(unsigned int target, const unsigned int *table, ++ unsigned int num_sel, unsigned int *sel); + int regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay); + int regulator_sync_voltage_rdev(struct regulator_dev *rdev); + diff --git a/target/linux/rockchip/patches-6.1/032-04-v6.5-regulator-rk808-fix-asynchronous-probing.patch b/target/linux/rockchip/patches-6.1/032-04-v6.5-regulator-rk808-fix-asynchronous-probing.patch new file mode 100644 index 0000000000..d7190f2260 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-04-v6.5-regulator-rk808-fix-asynchronous-probing.patch @@ -0,0 +1,31 @@ +From 1b9e86d445a0f5c6d8dcbaf11508cb5dfb5848a8 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:15 +0200 +Subject: [PATCH] regulator: rk808: fix asynchronous probing + +If the probe routine fails with -EPROBE_DEFER after taking over the +OF node from its parent driver, reprobing triggers pinctrl_bind_pins() +and that will fail. Fix this by setting of_node_reused, so that the +device does not try to setup pin muxing. + +For me this always happens once the driver is marked to prefer async +probing and never happens without that flag. + +Fixes: 259b93b21a9f ("regulator: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in 4.14") +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-12-sebastian.reichel@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/rk808-regulator.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/regulator/rk808-regulator.c ++++ b/drivers/regulator/rk808-regulator.c +@@ -1336,6 +1336,7 @@ static int rk808_regulator_probe(struct + + config.dev = &pdev->dev; + config.dev->of_node = pdev->dev.parent->of_node; ++ config.dev->of_node_reused = true; + config.driver_data = pdata; + config.regmap = regmap; + diff --git a/target/linux/rockchip/patches-6.1/032-05-v6.5-regulator-rk808-cleanup-parent-device-usage.patch b/target/linux/rockchip/patches-6.1/032-05-v6.5-regulator-rk808-cleanup-parent-device-usage.patch new file mode 100644 index 0000000000..f14860a08f --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-05-v6.5-regulator-rk808-cleanup-parent-device-usage.patch @@ -0,0 +1,70 @@ +From 5111c931f36cebe77d4ce66964c348e6eb4afca0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:16 +0200 +Subject: [PATCH] regulator: rk808: cleanup parent device usage + +By overridering the device's of_node a bit earlier we can +get the GPIOs and any other DT properties from our own +device instead of relying on the parent device. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-13-sebastian.reichel@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/rk808-regulator.c | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +--- a/drivers/regulator/rk808-regulator.c ++++ b/drivers/regulator/rk808-regulator.c +@@ -1245,20 +1245,19 @@ static const struct regulator_desc rk818 + }; + + static int rk808_regulator_dt_parse_pdata(struct device *dev, +- struct device *client_dev, + struct regmap *map, + struct rk808_regulator_data *pdata) + { + struct device_node *np; + int tmp, ret = 0, i; + +- np = of_get_child_by_name(client_dev->of_node, "regulators"); ++ np = of_get_child_by_name(dev->of_node, "regulators"); + if (!np) + return -ENXIO; + + for (i = 0; i < ARRAY_SIZE(pdata->dvs_gpio); i++) { + pdata->dvs_gpio[i] = +- devm_gpiod_get_index_optional(client_dev, "dvs", i, ++ devm_gpiod_get_index_optional(dev, "dvs", i, + GPIOD_OUT_LOW); + if (IS_ERR(pdata->dvs_gpio[i])) { + ret = PTR_ERR(pdata->dvs_gpio[i]); +@@ -1292,6 +1291,9 @@ static int rk808_regulator_probe(struct + struct regmap *regmap; + int ret, i, nregulators; + ++ pdev->dev.of_node = pdev->dev.parent->of_node; ++ pdev->dev.of_node_reused = true; ++ + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; +@@ -1300,8 +1302,7 @@ static int rk808_regulator_probe(struct + if (!pdata) + return -ENOMEM; + +- ret = rk808_regulator_dt_parse_pdata(&pdev->dev, pdev->dev.parent, +- regmap, pdata); ++ ret = rk808_regulator_dt_parse_pdata(&pdev->dev, regmap, pdata); + if (ret < 0) + return ret; + +@@ -1335,8 +1336,6 @@ static int rk808_regulator_probe(struct + } + + config.dev = &pdev->dev; +- config.dev->of_node = pdev->dev.parent->of_node; +- config.dev->of_node_reused = true; + config.driver_data = pdata; + config.regmap = regmap; + diff --git a/target/linux/rockchip/patches-6.1/032-06-v6.5-regulator-rk808-add-rk806-support.patch b/target/linux/rockchip/patches-6.1/032-06-v6.5-regulator-rk808-add-rk806-support.patch new file mode 100644 index 0000000000..940a5ef08e --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-06-v6.5-regulator-rk808-add-rk806-support.patch @@ -0,0 +1,482 @@ +From f991a220a44726c54c2332569a2a80bf074aa775 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 4 May 2023 19:36:18 +0200 +Subject: [PATCH] regulator: rk808: add rk806 support + +Add rk806 support to the existing rk808 regulator +driver. + +This has been implemented using shengfei Xu's rk806 +specific driver from the vendor tree as reference. + +Co-developed-by: shengfei Xu +Signed-off-by: shengfei Xu +Reviewed-by: Matti Vaittinen +Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B +Tested-by: Vincent Legoll # Pine64 QuartzPro64 +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230504173618.142075-15-sebastian.reichel@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/rk808-regulator.c | 385 ++++++++++++++++++++++++++++ + 1 file changed, 385 insertions(+) + +--- a/drivers/regulator/rk808-regulator.c ++++ b/drivers/regulator/rk808-regulator.c +@@ -3,9 +3,11 @@ + * Regulator driver for Rockchip RK805/RK808/RK818 + * + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * Author: Chris Zhong + * Author: Zhang Qing ++ * Author: Xu Shengfei + * + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * +@@ -39,6 +41,13 @@ + #define RK818_LDO3_ON_VSEL_MASK 0xf + #define RK818_BOOST_ON_VSEL_MASK 0xe0 + ++#define RK806_DCDC_SLP_REG_OFFSET 0x0A ++#define RK806_NLDO_SLP_REG_OFFSET 0x05 ++#define RK806_PLDO_SLP_REG_OFFSET 0x06 ++ ++#define RK806_BUCK_SEL_CNT 0xff ++#define RK806_LDO_SEL_CNT 0xff ++ + /* Ramp rate definitions for buck1 / buck2 only */ + #define RK808_RAMP_RATE_OFFSET 3 + #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) +@@ -117,6 +126,34 @@ + RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ + _vmask, _ereg, _emask, 0, 0, _etime, &rk805_reg_ops) + ++#define RK806_REGULATOR(_name, _supply_name, _id, _ops,\ ++ _n_voltages, _vr, _er, _lr, ctrl_bit,\ ++ _rr, _rm, _rt)\ ++[_id] = {\ ++ .name = _name,\ ++ .supply_name = _supply_name,\ ++ .of_match = of_match_ptr(_name),\ ++ .regulators_node = of_match_ptr("regulators"),\ ++ .id = _id,\ ++ .ops = &_ops,\ ++ .type = REGULATOR_VOLTAGE,\ ++ .n_voltages = _n_voltages,\ ++ .linear_ranges = _lr,\ ++ .n_linear_ranges = ARRAY_SIZE(_lr),\ ++ .vsel_reg = _vr,\ ++ .vsel_mask = 0xff,\ ++ .enable_reg = _er,\ ++ .enable_mask = ENABLE_MASK(ctrl_bit),\ ++ .enable_val = ENABLE_MASK(ctrl_bit),\ ++ .disable_val = DISABLE_VAL(ctrl_bit),\ ++ .of_map_mode = rk8xx_regulator_of_map_mode,\ ++ .ramp_reg = _rr,\ ++ .ramp_mask = _rm,\ ++ .ramp_delay_table = _rt, \ ++ .n_ramp_values = ARRAY_SIZE(_rt), \ ++ .owner = THIS_MODULE,\ ++ } ++ + #define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ + _vmask, _ereg, _emask, _etime) \ + RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ +@@ -153,6 +190,17 @@ + RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \ + 0, 0, &rk808_switch_ops) + ++struct rk8xx_register_bit { ++ u8 reg; ++ u8 bit; ++}; ++ ++#define RK8XX_REG_BIT(_reg, _bit) \ ++ { \ ++ .reg = _reg, \ ++ .bit = BIT(_bit), \ ++ } ++ + struct rk808_regulator_data { + struct gpio_desc *dvs_gpio[2]; + }; +@@ -216,6 +264,133 @@ static const unsigned int rk817_buck1_4_ + 3000, 6300, 12500, 25000 + }; + ++static int rk806_set_mode_dcdc(struct regulator_dev *rdev, unsigned int mode) ++{ ++ int rid = rdev_get_id(rdev); ++ int ctr_bit, reg; ++ ++ reg = RK806_POWER_FPWM_EN0 + rid / 8; ++ ctr_bit = rid % 8; ++ ++ switch (mode) { ++ case REGULATOR_MODE_FAST: ++ return regmap_update_bits(rdev->regmap, reg, ++ PWM_MODE_MSK << ctr_bit, ++ FPWM_MODE << ctr_bit); ++ case REGULATOR_MODE_NORMAL: ++ return regmap_update_bits(rdev->regmap, reg, ++ PWM_MODE_MSK << ctr_bit, ++ AUTO_PWM_MODE << ctr_bit); ++ default: ++ dev_err(rdev_get_dev(rdev), "mode unsupported: %u\n", mode); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static unsigned int rk806_get_mode_dcdc(struct regulator_dev *rdev) ++{ ++ int rid = rdev_get_id(rdev); ++ int ctr_bit, reg; ++ unsigned int val; ++ int err; ++ ++ reg = RK806_POWER_FPWM_EN0 + rid / 8; ++ ctr_bit = rid % 8; ++ ++ err = regmap_read(rdev->regmap, reg, &val); ++ if (err) ++ return err; ++ ++ if ((val >> ctr_bit) & FPWM_MODE) ++ return REGULATOR_MODE_FAST; ++ else ++ return REGULATOR_MODE_NORMAL; ++} ++ ++static const struct rk8xx_register_bit rk806_dcdc_rate2[] = { ++ RK8XX_REG_BIT(0xEB, 0), ++ RK8XX_REG_BIT(0xEB, 1), ++ RK8XX_REG_BIT(0xEB, 2), ++ RK8XX_REG_BIT(0xEB, 3), ++ RK8XX_REG_BIT(0xEB, 4), ++ RK8XX_REG_BIT(0xEB, 5), ++ RK8XX_REG_BIT(0xEB, 6), ++ RK8XX_REG_BIT(0xEB, 7), ++ RK8XX_REG_BIT(0xEA, 0), ++ RK8XX_REG_BIT(0xEA, 1), ++}; ++ ++static const unsigned int rk806_ramp_delay_table_dcdc[] = { ++ 50000, 25000, 12500, 6250, 3125, 1560, 961, 390 ++}; ++ ++static int rk806_set_ramp_delay_dcdc(struct regulator_dev *rdev, int ramp_delay) ++{ ++ int rid = rdev_get_id(rdev); ++ int regval, ramp_value, ret; ++ ++ ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, ++ rdev->desc->n_ramp_values, &ramp_value); ++ if (ret) { ++ dev_warn(rdev_get_dev(rdev), ++ "Can't set ramp-delay %u, setting %u\n", ramp_delay, ++ rdev->desc->ramp_delay_table[ramp_value]); ++ } ++ ++ regval = ramp_value << (ffs(rdev->desc->ramp_mask) - 1); ++ ++ ret = regmap_update_bits(rdev->regmap, rdev->desc->ramp_reg, ++ rdev->desc->ramp_mask, regval); ++ if (ret) ++ return ret; ++ ++ /* ++ * The above is effectively a copy of regulator_set_ramp_delay_regmap(), ++ * but that only stores the lower 2 bits for rk806 DCDC ramp. The MSB must ++ * be stored in a separate register, so this open codes the implementation ++ * to have access to the ramp_value. ++ */ ++ ++ regval = (ramp_value >> 2) & 0x1 ? rk806_dcdc_rate2[rid].bit : 0; ++ return regmap_update_bits(rdev->regmap, rk806_dcdc_rate2[rid].reg, ++ rk806_dcdc_rate2[rid].bit, ++ regval); ++} ++ ++static const unsigned int rk806_ramp_delay_table_ldo[] = { ++ 100000, 50000, 25000, 12500, 6280, 3120, 1900, 780 ++}; ++ ++static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int reg_offset, int uv) ++{ ++ int sel = regulator_map_voltage_linear_range(rdev, uv, uv); ++ unsigned int reg; ++ ++ if (sel < 0) ++ return -EINVAL; ++ ++ reg = rdev->desc->vsel_reg + reg_offset; ++ ++ return regmap_update_bits(rdev->regmap, reg, rdev->desc->vsel_mask, sel); ++} ++ ++static int rk806_set_suspend_voltage_range_dcdc(struct regulator_dev *rdev, int uv) ++{ ++ return rk806_set_suspend_voltage_range(rdev, RK806_DCDC_SLP_REG_OFFSET, uv); ++} ++ ++static int rk806_set_suspend_voltage_range_nldo(struct regulator_dev *rdev, int uv) ++{ ++ return rk806_set_suspend_voltage_range(rdev, RK806_NLDO_SLP_REG_OFFSET, uv); ++} ++ ++static int rk806_set_suspend_voltage_range_pldo(struct regulator_dev *rdev, int uv) ++{ ++ return rk806_set_suspend_voltage_range(rdev, RK806_PLDO_SLP_REG_OFFSET, uv); ++} ++ + static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev) + { + struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev); +@@ -393,6 +568,47 @@ static int rk805_set_suspend_disable(str + 0); + } + ++static const struct rk8xx_register_bit rk806_suspend_bits[] = { ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 0), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 1), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 2), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 3), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 4), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 5), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 6), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 7), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 6), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 7), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 0), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 1), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 2), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 3), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 4), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 1), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 2), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 3), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 4), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 5), ++ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 0), ++}; ++ ++static int rk806_set_suspend_enable(struct regulator_dev *rdev) ++{ ++ int rid = rdev_get_id(rdev); ++ ++ return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg, ++ rk806_suspend_bits[rid].bit, ++ rk806_suspend_bits[rid].bit); ++} ++ ++static int rk806_set_suspend_disable(struct regulator_dev *rdev) ++{ ++ int rid = rdev_get_id(rdev); ++ ++ return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg, ++ rk806_suspend_bits[rid].bit, 0); ++} ++ + static int rk808_set_suspend_enable(struct regulator_dev *rdev) + { + unsigned int reg; +@@ -561,6 +777,64 @@ static const struct regulator_ops rk805_ + .set_suspend_disable = rk805_set_suspend_disable, + }; + ++static const struct regulator_ops rk806_ops_dcdc = { ++ .list_voltage = regulator_list_voltage_linear_range, ++ .map_voltage = regulator_map_voltage_linear_range, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++ .set_mode = rk806_set_mode_dcdc, ++ .get_mode = rk806_get_mode_dcdc, ++ ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = rk8xx_is_enabled_wmsk_regmap, ++ ++ .set_suspend_mode = rk806_set_mode_dcdc, ++ .set_ramp_delay = rk806_set_ramp_delay_dcdc, ++ ++ .set_suspend_voltage = rk806_set_suspend_voltage_range_dcdc, ++ .set_suspend_enable = rk806_set_suspend_enable, ++ .set_suspend_disable = rk806_set_suspend_disable, ++}; ++ ++static const struct regulator_ops rk806_ops_nldo = { ++ .list_voltage = regulator_list_voltage_linear_range, ++ .map_voltage = regulator_map_voltage_linear_range, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++ ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ ++ .set_ramp_delay = regulator_set_ramp_delay_regmap, ++ ++ .set_suspend_voltage = rk806_set_suspend_voltage_range_nldo, ++ .set_suspend_enable = rk806_set_suspend_enable, ++ .set_suspend_disable = rk806_set_suspend_disable, ++}; ++ ++static const struct regulator_ops rk806_ops_pldo = { ++ .list_voltage = regulator_list_voltage_linear_range, ++ .map_voltage = regulator_map_voltage_linear_range, ++ ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++ ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ ++ .set_ramp_delay = regulator_set_ramp_delay_regmap, ++ ++ .set_suspend_voltage = rk806_set_suspend_voltage_range_pldo, ++ .set_suspend_enable = rk806_set_suspend_enable, ++ .set_suspend_disable = rk806_set_suspend_disable, ++}; ++ + static const struct regulator_ops rk808_buck1_2_ops = { + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, +@@ -743,6 +1017,112 @@ static const struct regulator_desc rk805 + BIT(2), 400), + }; + ++static const struct linear_range rk806_buck_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(500000, 0, 160, 6250), /* 500mV ~ 1500mV */ ++ REGULATOR_LINEAR_RANGE(1500000, 161, 237, 25000), /* 1500mV ~ 3400mV */ ++ REGULATOR_LINEAR_RANGE(3400000, 238, 255, 0), ++}; ++ ++static const struct linear_range rk806_ldo_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(500000, 0, 232, 12500), /* 500mV ~ 3400mV */ ++ REGULATOR_LINEAR_RANGE(3400000, 233, 255, 0), /* 500mV ~ 3400mV */ ++}; ++ ++static const struct regulator_desc rk806_reg[] = { ++ RK806_REGULATOR("dcdc-reg1", "vcc1", RK806_ID_DCDC1, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK1_ON_VSEL, ++ RK806_POWER_EN0, rk806_buck_voltage_ranges, 0, ++ RK806_BUCK1_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ RK806_REGULATOR("dcdc-reg2", "vcc2", RK806_ID_DCDC2, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK2_ON_VSEL, ++ RK806_POWER_EN0, rk806_buck_voltage_ranges, 1, ++ RK806_BUCK2_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ RK806_REGULATOR("dcdc-reg3", "vcc3", RK806_ID_DCDC3, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK3_ON_VSEL, ++ RK806_POWER_EN0, rk806_buck_voltage_ranges, 2, ++ RK806_BUCK3_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ RK806_REGULATOR("dcdc-reg4", "vcc4", RK806_ID_DCDC4, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK4_ON_VSEL, ++ RK806_POWER_EN0, rk806_buck_voltage_ranges, 3, ++ RK806_BUCK4_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ ++ RK806_REGULATOR("dcdc-reg5", "vcc5", RK806_ID_DCDC5, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK5_ON_VSEL, ++ RK806_POWER_EN1, rk806_buck_voltage_ranges, 0, ++ RK806_BUCK5_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ RK806_REGULATOR("dcdc-reg6", "vcc6", RK806_ID_DCDC6, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK6_ON_VSEL, ++ RK806_POWER_EN1, rk806_buck_voltage_ranges, 1, ++ RK806_BUCK6_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ RK806_REGULATOR("dcdc-reg7", "vcc7", RK806_ID_DCDC7, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK7_ON_VSEL, ++ RK806_POWER_EN1, rk806_buck_voltage_ranges, 2, ++ RK806_BUCK7_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ RK806_REGULATOR("dcdc-reg8", "vcc8", RK806_ID_DCDC8, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK8_ON_VSEL, ++ RK806_POWER_EN1, rk806_buck_voltage_ranges, 3, ++ RK806_BUCK8_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ ++ RK806_REGULATOR("dcdc-reg9", "vcc9", RK806_ID_DCDC9, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK9_ON_VSEL, ++ RK806_POWER_EN2, rk806_buck_voltage_ranges, 0, ++ RK806_BUCK9_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ RK806_REGULATOR("dcdc-reg10", "vcc10", RK806_ID_DCDC10, rk806_ops_dcdc, ++ RK806_BUCK_SEL_CNT, RK806_BUCK10_ON_VSEL, ++ RK806_POWER_EN2, rk806_buck_voltage_ranges, 1, ++ RK806_BUCK10_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), ++ ++ RK806_REGULATOR("nldo-reg1", "vcc13", RK806_ID_NLDO1, rk806_ops_nldo, ++ RK806_LDO_SEL_CNT, RK806_NLDO1_ON_VSEL, ++ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 0, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ RK806_REGULATOR("nldo-reg2", "vcc13", RK806_ID_NLDO2, rk806_ops_nldo, ++ RK806_LDO_SEL_CNT, RK806_NLDO2_ON_VSEL, ++ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 1, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ RK806_REGULATOR("nldo-reg3", "vcc13", RK806_ID_NLDO3, rk806_ops_nldo, ++ RK806_LDO_SEL_CNT, RK806_NLDO3_ON_VSEL, ++ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 2, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ RK806_REGULATOR("nldo-reg4", "vcc14", RK806_ID_NLDO4, rk806_ops_nldo, ++ RK806_LDO_SEL_CNT, RK806_NLDO4_ON_VSEL, ++ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 3, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ ++ RK806_REGULATOR("nldo-reg5", "vcc14", RK806_ID_NLDO5, rk806_ops_nldo, ++ RK806_LDO_SEL_CNT, RK806_NLDO5_ON_VSEL, ++ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 2, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ ++ RK806_REGULATOR("pldo-reg1", "vcc11", RK806_ID_PLDO1, rk806_ops_pldo, ++ RK806_LDO_SEL_CNT, RK806_PLDO1_ON_VSEL, ++ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 1, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ RK806_REGULATOR("pldo-reg2", "vcc11", RK806_ID_PLDO2, rk806_ops_pldo, ++ RK806_LDO_SEL_CNT, RK806_PLDO2_ON_VSEL, ++ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 2, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ RK806_REGULATOR("pldo-reg3", "vcc11", RK806_ID_PLDO3, rk806_ops_pldo, ++ RK806_LDO_SEL_CNT, RK806_PLDO3_ON_VSEL, ++ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 3, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ ++ RK806_REGULATOR("pldo-reg4", "vcc12", RK806_ID_PLDO4, rk806_ops_pldo, ++ RK806_LDO_SEL_CNT, RK806_PLDO4_ON_VSEL, ++ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 0, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ RK806_REGULATOR("pldo-reg5", "vcc12", RK806_ID_PLDO5, rk806_ops_pldo, ++ RK806_LDO_SEL_CNT, RK806_PLDO5_ON_VSEL, ++ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 1, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++ ++ RK806_REGULATOR("pldo-reg6", "vcca", RK806_ID_PLDO6, rk806_ops_pldo, ++ RK806_LDO_SEL_CNT, RK806_PLDO6_ON_VSEL, ++ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 0, ++ 0xEA, 0x38, rk806_ramp_delay_table_ldo), ++}; ++ ++ + static const struct regulator_desc rk808_reg[] = { + { + .name = "DCDC_REG1", +@@ -1313,6 +1693,10 @@ static int rk808_regulator_probe(struct + regulators = rk805_reg; + nregulators = RK805_NUM_REGULATORS; + break; ++ case RK806_ID: ++ regulators = rk806_reg; ++ nregulators = ARRAY_SIZE(rk806_reg); ++ break; + case RK808_ID: + regulators = rk808_reg; + nregulators = RK808_NUM_REGULATORS; +@@ -1365,5 +1749,6 @@ MODULE_AUTHOR("Tony xie "); + MODULE_AUTHOR("Zhang Qing "); + MODULE_AUTHOR("Wadim Egorov "); ++MODULE_AUTHOR("Xu Shengfei "); + MODULE_LICENSE("GPL"); + MODULE_ALIAS("platform:rk808-regulator"); diff --git a/target/linux/rockchip/patches-6.1/032-07-v6.4-regulator-fan53555-Remove-unused-SLEW_SHIFT-definitions.patch b/target/linux/rockchip/patches-6.1/032-07-v6.4-regulator-fan53555-Remove-unused-SLEW_SHIFT-definitions.patch new file mode 100644 index 0000000000..64d2db7330 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-07-v6.4-regulator-fan53555-Remove-unused-SLEW_SHIFT-definitions.patch @@ -0,0 +1,35 @@ +From d5edc0e36bb1657d2c46b7521010d4f0894a5c74 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 6 Apr 2023 22:41:54 +0300 +Subject: [PATCH] regulator: fan53555: Remove unused *_SLEW_SHIFT definitions + +Commit b61ac767db4d ("regulator: fan53555: Convert to use +regulator_set_ramp_delay_regmap") removed the slew_shift member from +struct fan53555_device_info, hence the {CTL,TCS}_SLEW_SHIFT definitions +remained unused. Drop them. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230406194158.963352-5-cristian.ciocaltea@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/fan53555.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/regulator/fan53555.c ++++ b/drivers/regulator/fan53555.c +@@ -49,7 +49,6 @@ + /* Control bit definitions */ + #define CTL_OUTPUT_DISCHG (1 << 7) + #define CTL_SLEW_MASK (0x7 << 4) +-#define CTL_SLEW_SHIFT 4 + #define CTL_RESET (1 << 2) + #define CTL_MODE_VSEL0_MODE BIT(0) + #define CTL_MODE_VSEL1_MODE BIT(1) +@@ -60,7 +59,6 @@ + #define TCS_VSEL0_MODE (1 << 7) + #define TCS_VSEL1_MODE (1 << 6) + +-#define TCS_SLEW_SHIFT 3 + #define TCS_SLEW_MASK GENMASK(4, 3) + + enum fan53555_vendor { diff --git a/target/linux/rockchip/patches-6.1/032-08-v6.4-regulator-fan53555-Make-use-of-the-bit-macros.patch b/target/linux/rockchip/patches-6.1/032-08-v6.4-regulator-fan53555-Make-use-of-the-bit-macros.patch new file mode 100644 index 0000000000..62ce4f4e93 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-08-v6.4-regulator-fan53555-Make-use-of-the-bit-macros.patch @@ -0,0 +1,53 @@ +From d25016618c0845b2a0f9ae64d084a66efd39b03c Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 6 Apr 2023 22:41:55 +0300 +Subject: [PATCH] regulator: fan53555: Make use of the bit macros + +For consistency and improved clarity, use BIT() and GENMASK() macros for +defining the bitfields inside the registers. No functional changes +intended. + +While here, also fix DIE_{ID,REV} inconsistent indentation. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230406194158.963352-6-cristian.ciocaltea@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/fan53555.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/drivers/regulator/fan53555.c ++++ b/drivers/regulator/fan53555.c +@@ -41,23 +41,23 @@ + #define FAN53555_MONITOR 0x05 + + /* VSEL bit definitions */ +-#define VSEL_BUCK_EN (1 << 7) +-#define VSEL_MODE (1 << 6) ++#define VSEL_BUCK_EN BIT(7) ++#define VSEL_MODE BIT(6) + /* Chip ID and Verison */ +-#define DIE_ID 0x0F /* ID1 */ +-#define DIE_REV 0x0F /* ID2 */ ++#define DIE_ID 0x0F /* ID1 */ ++#define DIE_REV 0x0F /* ID2 */ + /* Control bit definitions */ +-#define CTL_OUTPUT_DISCHG (1 << 7) +-#define CTL_SLEW_MASK (0x7 << 4) +-#define CTL_RESET (1 << 2) ++#define CTL_OUTPUT_DISCHG BIT(7) ++#define CTL_SLEW_MASK GENMASK(6, 4) ++#define CTL_RESET BIT(2) + #define CTL_MODE_VSEL0_MODE BIT(0) + #define CTL_MODE_VSEL1_MODE BIT(1) + + #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ + #define FAN53526_NVOLTAGES 128 + +-#define TCS_VSEL0_MODE (1 << 7) +-#define TCS_VSEL1_MODE (1 << 6) ++#define TCS_VSEL0_MODE BIT(7) ++#define TCS_VSEL1_MODE BIT(6) + + #define TCS_SLEW_MASK GENMASK(4, 3) + diff --git a/target/linux/rockchip/patches-6.1/032-09-v6.4-regulator-fan53555-Improve-vsel_mask-computation.patch b/target/linux/rockchip/patches-6.1/032-09-v6.4-regulator-fan53555-Improve-vsel_mask-computation.patch new file mode 100644 index 0000000000..a001a7cc59 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-09-v6.4-regulator-fan53555-Improve-vsel_mask-computation.patch @@ -0,0 +1,39 @@ +From 6bb18339c6b54e0241344280fe4d14909db9356c Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 6 Apr 2023 22:41:56 +0300 +Subject: [PATCH] regulator: fan53555: Improve vsel_mask computation + +In preparation for introducing support for additional regulators which +do not use the maximum number of voltage selectors available for a given +mask, improve the mask computation formula by using fls(). + +Note fls() requires the bitops header, hence include it explicitly and +drop bits.h which is already pulled by bitops.h. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230406194158.963352-7-cristian.ciocaltea@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/fan53555.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/regulator/fan53555.c ++++ b/drivers/regulator/fan53555.c +@@ -8,7 +8,7 @@ + // Copyright (c) 2012 Marvell Technology Ltd. + // Yunfan Zhang + +-#include ++#include + #include + #include + #include +@@ -486,7 +486,7 @@ static int fan53555_regulator_register(s + rdesc->min_uV = di->vsel_min; + rdesc->uV_step = di->vsel_step; + rdesc->vsel_reg = di->vol_reg; +- rdesc->vsel_mask = di->vsel_count - 1; ++ rdesc->vsel_mask = BIT(fls(di->vsel_count - 1)) - 1; + rdesc->ramp_reg = di->slew_reg; + rdesc->ramp_mask = di->slew_mask; + rdesc->ramp_delay_table = di->ramp_delay_table; diff --git a/target/linux/rockchip/patches-6.1/032-10-v6.4-regulator-fan53555-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/032-10-v6.4-regulator-fan53555-Use-dev_err_probe.patch new file mode 100644 index 0000000000..b0fba84204 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-10-v6.4-regulator-fan53555-Use-dev_err_probe.patch @@ -0,0 +1,106 @@ +From 2c82f5b8ae6d0b5bbac1526021d9c3120d183555 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 6 Apr 2023 22:41:57 +0300 +Subject: [PATCH] regulator: fan53555: Use dev_err_probe + +Use dev_err_probe() instead of dev_err() in the probe function, which +ensures the error code is always printed and, additionally, simplifies +the code a bit. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230406194158.963352-8-cristian.ciocaltea@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/fan53555.c | 47 ++++++++++++++++-------------------- + 1 file changed, 21 insertions(+), 26 deletions(-) + +--- a/drivers/regulator/fan53555.c ++++ b/drivers/regulator/fan53555.c +@@ -568,10 +568,9 @@ static int fan53555_regulator_probe(stru + if (!pdata) + pdata = fan53555_parse_dt(&client->dev, np, &di->desc); + +- if (!pdata || !pdata->regulator) { +- dev_err(&client->dev, "Platform data not found!\n"); +- return -ENODEV; +- } ++ if (!pdata || !pdata->regulator) ++ return dev_err_probe(&client->dev, -ENODEV, ++ "Platform data not found!\n"); + + di->regulator = pdata->regulator; + if (client->dev.of_node) { +@@ -580,10 +579,9 @@ static int fan53555_regulator_probe(stru + } else { + /* if no ramp constraint set, get the pdata ramp_delay */ + if (!di->regulator->constraints.ramp_delay) { +- if (pdata->slew_rate >= ARRAY_SIZE(slew_rates)) { +- dev_err(&client->dev, "Invalid slew_rate\n"); +- return -EINVAL; +- } ++ if (pdata->slew_rate >= ARRAY_SIZE(slew_rates)) ++ return dev_err_probe(&client->dev, -EINVAL, ++ "Invalid slew_rate\n"); + + di->regulator->constraints.ramp_delay + = slew_rates[pdata->slew_rate]; +@@ -593,34 +591,31 @@ static int fan53555_regulator_probe(stru + } + + regmap = devm_regmap_init_i2c(client, &fan53555_regmap_config); +- if (IS_ERR(regmap)) { +- dev_err(&client->dev, "Failed to allocate regmap!\n"); +- return PTR_ERR(regmap); +- } ++ if (IS_ERR(regmap)) ++ return dev_err_probe(&client->dev, PTR_ERR(regmap), ++ "Failed to allocate regmap!\n"); ++ + di->dev = &client->dev; + i2c_set_clientdata(client, di); + /* Get chip ID */ + ret = regmap_read(regmap, FAN53555_ID1, &val); +- if (ret < 0) { +- dev_err(&client->dev, "Failed to get chip ID!\n"); +- return ret; +- } ++ if (ret < 0) ++ return dev_err_probe(&client->dev, ret, "Failed to get chip ID!\n"); ++ + di->chip_id = val & DIE_ID; + /* Get chip revision */ + ret = regmap_read(regmap, FAN53555_ID2, &val); +- if (ret < 0) { +- dev_err(&client->dev, "Failed to get chip Rev!\n"); +- return ret; +- } ++ if (ret < 0) ++ return dev_err_probe(&client->dev, ret, "Failed to get chip Rev!\n"); ++ + di->chip_rev = val & DIE_REV; + dev_info(&client->dev, "FAN53555 Option[%d] Rev[%d] Detected!\n", + di->chip_id, di->chip_rev); + /* Device init */ + ret = fan53555_device_setup(di, pdata); +- if (ret < 0) { +- dev_err(&client->dev, "Failed to setup device!\n"); +- return ret; +- } ++ if (ret < 0) ++ return dev_err_probe(&client->dev, ret, "Failed to setup device!\n"); ++ + /* Register regulator */ + config.dev = di->dev; + config.init_data = di->regulator; +@@ -630,9 +625,9 @@ static int fan53555_regulator_probe(stru + + ret = fan53555_regulator_register(di, &config); + if (ret < 0) +- dev_err(&client->dev, "Failed to register regulator!\n"); +- return ret; ++ dev_err_probe(&client->dev, ret, "Failed to register regulator!\n"); + ++ return ret; + } + + static const struct i2c_device_id fan53555_id[] = { diff --git a/target/linux/rockchip/patches-6.1/032-11-v6.4-regulator-fan53555-Add-support-for-RK860X.patch b/target/linux/rockchip/patches-6.1/032-11-v6.4-regulator-fan53555-Add-support-for-RK860X.patch new file mode 100644 index 0000000000..f8fbd8378f --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-11-v6.4-regulator-fan53555-Add-support-for-RK860X.patch @@ -0,0 +1,263 @@ +From a27e71a66ee0f887fefcc31b85a804b0905fa865 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 6 Apr 2023 22:41:58 +0300 +Subject: [PATCH] regulator: fan53555: Add support for RK860X + +Extend the existing fan53555 driver to support the Rockchip RK860X +regulators. + +RK8600/RK8601 are pretty similar to the FAN53555 regulators. + +RK8602/RK8603 are a bit different, having a wider output voltage +selection range, from 0.5 V to 1.5 V in 6.25 mV steps. They also use +additional VSEL0/VSEL1 registers for the voltage selector, but the +enable and mode bits are still located in the original FAN53555 specific +VSEL0/VSEL1 registers. + +Signed-off-by: Cristian Ciocaltea +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20230406194158.963352-9-cristian.ciocaltea@collabora.com +Signed-off-by: Mark Brown +--- + drivers/regulator/fan53555.c | 121 ++++++++++++++++++++++++++++++++++- + 1 file changed, 118 insertions(+), 3 deletions(-) + +--- a/drivers/regulator/fan53555.c ++++ b/drivers/regulator/fan53555.c +@@ -26,6 +26,9 @@ + #define FAN53555_VSEL0 0x00 + #define FAN53555_VSEL1 0x01 + ++#define RK8602_VSEL0 0x06 ++#define RK8602_VSEL1 0x07 ++ + #define TCS4525_VSEL0 0x11 + #define TCS4525_VSEL1 0x10 + #define TCS4525_TIME 0x13 +@@ -55,6 +58,7 @@ + + #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ + #define FAN53526_NVOLTAGES 128 ++#define RK8602_NVOLTAGES 160 + + #define TCS_VSEL0_MODE BIT(7) + #define TCS_VSEL1_MODE BIT(6) +@@ -64,6 +68,8 @@ + enum fan53555_vendor { + FAN53526_VENDOR_FAIRCHILD = 0, + FAN53555_VENDOR_FAIRCHILD, ++ FAN53555_VENDOR_ROCKCHIP, /* RK8600, RK8601 */ ++ RK8602_VENDOR_ROCKCHIP, /* RK8602, RK8603 */ + FAN53555_VENDOR_SILERGY, + FAN53526_VENDOR_TCS, + }; +@@ -88,6 +94,14 @@ enum { + }; + + enum { ++ RK8600_CHIP_ID_08 = 8, /* RK8600, RK8601 */ ++}; ++ ++enum { ++ RK8602_CHIP_ID_10 = 10, /* RK8602, RK8603 */ ++}; ++ ++enum { + TCS4525_CHIP_ID_12 = 12, + }; + +@@ -117,6 +131,8 @@ struct fan53555_device_info { + /* Voltage setting register */ + unsigned int vol_reg; + unsigned int sleep_reg; ++ unsigned int en_reg; ++ unsigned int sleep_en_reg; + /* Voltage range and step(linear) */ + unsigned int vsel_min; + unsigned int vsel_step; +@@ -159,7 +175,7 @@ static int fan53555_set_suspend_enable(s + { + struct fan53555_device_info *di = rdev_get_drvdata(rdev); + +- return regmap_update_bits(rdev->regmap, di->sleep_reg, ++ return regmap_update_bits(rdev->regmap, di->sleep_en_reg, + VSEL_BUCK_EN, VSEL_BUCK_EN); + } + +@@ -167,7 +183,7 @@ static int fan53555_set_suspend_disable( + { + struct fan53555_device_info *di = rdev_get_drvdata(rdev); + +- return regmap_update_bits(rdev->regmap, di->sleep_reg, ++ return regmap_update_bits(rdev->regmap, di->sleep_en_reg, + VSEL_BUCK_EN, 0); + } + +@@ -317,6 +333,50 @@ static int fan53555_voltages_setup_fairc + return 0; + } + ++static int fan53555_voltages_setup_rockchip(struct fan53555_device_info *di) ++{ ++ /* Init voltage range and step */ ++ switch (di->chip_id) { ++ case RK8600_CHIP_ID_08: ++ di->vsel_min = 712500; ++ di->vsel_step = 12500; ++ break; ++ default: ++ dev_err(di->dev, ++ "Chip ID %d not supported!\n", di->chip_id); ++ return -EINVAL; ++ } ++ di->slew_reg = FAN53555_CONTROL; ++ di->slew_mask = CTL_SLEW_MASK; ++ di->ramp_delay_table = slew_rates; ++ di->n_ramp_values = ARRAY_SIZE(slew_rates); ++ di->vsel_count = FAN53555_NVOLTAGES; ++ ++ return 0; ++} ++ ++static int rk8602_voltages_setup_rockchip(struct fan53555_device_info *di) ++{ ++ /* Init voltage range and step */ ++ switch (di->chip_id) { ++ case RK8602_CHIP_ID_10: ++ di->vsel_min = 500000; ++ di->vsel_step = 6250; ++ break; ++ default: ++ dev_err(di->dev, ++ "Chip ID %d not supported!\n", di->chip_id); ++ return -EINVAL; ++ } ++ di->slew_reg = FAN53555_CONTROL; ++ di->slew_mask = CTL_SLEW_MASK; ++ di->ramp_delay_table = slew_rates; ++ di->n_ramp_values = ARRAY_SIZE(slew_rates); ++ di->vsel_count = RK8602_NVOLTAGES; ++ ++ return 0; ++} ++ + static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) + { + /* Init voltage range and step */ +@@ -377,6 +437,7 @@ static int fan53555_device_setup(struct + switch (di->vendor) { + case FAN53526_VENDOR_FAIRCHILD: + case FAN53555_VENDOR_FAIRCHILD: ++ case FAN53555_VENDOR_ROCKCHIP: + case FAN53555_VENDOR_SILERGY: + switch (pdata->sleep_vsel_id) { + case FAN53555_VSEL_ID_0: +@@ -391,6 +452,27 @@ static int fan53555_device_setup(struct + dev_err(di->dev, "Invalid VSEL ID!\n"); + return -EINVAL; + } ++ di->sleep_en_reg = di->sleep_reg; ++ di->en_reg = di->vol_reg; ++ break; ++ case RK8602_VENDOR_ROCKCHIP: ++ switch (pdata->sleep_vsel_id) { ++ case FAN53555_VSEL_ID_0: ++ di->sleep_reg = RK8602_VSEL0; ++ di->vol_reg = RK8602_VSEL1; ++ di->sleep_en_reg = FAN53555_VSEL0; ++ di->en_reg = FAN53555_VSEL1; ++ break; ++ case FAN53555_VSEL_ID_1: ++ di->sleep_reg = RK8602_VSEL1; ++ di->vol_reg = RK8602_VSEL0; ++ di->sleep_en_reg = FAN53555_VSEL1; ++ di->en_reg = FAN53555_VSEL0; ++ break; ++ default: ++ dev_err(di->dev, "Invalid VSEL ID!\n"); ++ return -EINVAL; ++ } + break; + case FAN53526_VENDOR_TCS: + switch (pdata->sleep_vsel_id) { +@@ -406,6 +488,8 @@ static int fan53555_device_setup(struct + dev_err(di->dev, "Invalid VSEL ID!\n"); + return -EINVAL; + } ++ di->sleep_en_reg = di->sleep_reg; ++ di->en_reg = di->vol_reg; + break; + default: + dev_err(di->dev, "vendor %d not supported!\n", di->vendor); +@@ -427,10 +511,23 @@ static int fan53555_device_setup(struct + } + break; + case FAN53555_VENDOR_FAIRCHILD: ++ case FAN53555_VENDOR_ROCKCHIP: + case FAN53555_VENDOR_SILERGY: + di->mode_reg = di->vol_reg; + di->mode_mask = VSEL_MODE; + break; ++ case RK8602_VENDOR_ROCKCHIP: ++ di->mode_mask = VSEL_MODE; ++ ++ switch (pdata->sleep_vsel_id) { ++ case FAN53555_VSEL_ID_0: ++ di->mode_reg = FAN53555_VSEL1; ++ break; ++ case FAN53555_VSEL_ID_1: ++ di->mode_reg = FAN53555_VSEL0; ++ break; ++ } ++ break; + case FAN53526_VENDOR_TCS: + di->mode_reg = TCS4525_COMMAND; + +@@ -456,6 +553,12 @@ static int fan53555_device_setup(struct + case FAN53555_VENDOR_FAIRCHILD: + ret = fan53555_voltages_setup_fairchild(di); + break; ++ case FAN53555_VENDOR_ROCKCHIP: ++ ret = fan53555_voltages_setup_rockchip(di); ++ break; ++ case RK8602_VENDOR_ROCKCHIP: ++ ret = rk8602_voltages_setup_rockchip(di); ++ break; + case FAN53555_VENDOR_SILERGY: + ret = fan53555_voltages_setup_silergy(di); + break; +@@ -481,7 +584,7 @@ static int fan53555_regulator_register(s + rdesc->ops = &fan53555_regulator_ops; + rdesc->type = REGULATOR_VOLTAGE; + rdesc->n_voltages = di->vsel_count; +- rdesc->enable_reg = di->vol_reg; ++ rdesc->enable_reg = di->en_reg; + rdesc->enable_mask = VSEL_BUCK_EN; + rdesc->min_uV = di->vsel_min; + rdesc->uV_step = di->vsel_step; +@@ -532,6 +635,12 @@ static const struct of_device_id __maybe + .compatible = "fcs,fan53555", + .data = (void *)FAN53555_VENDOR_FAIRCHILD + }, { ++ .compatible = "rockchip,rk8600", ++ .data = (void *)FAN53555_VENDOR_ROCKCHIP ++ }, { ++ .compatible = "rockchip,rk8602", ++ .data = (void *)RK8602_VENDOR_ROCKCHIP ++ }, { + .compatible = "silergy,syr827", + .data = (void *)FAN53555_VENDOR_SILERGY, + }, { +@@ -638,6 +747,12 @@ static const struct i2c_device_id fan535 + .name = "fan53555", + .driver_data = FAN53555_VENDOR_FAIRCHILD + }, { ++ .name = "rk8600", ++ .driver_data = FAN53555_VENDOR_ROCKCHIP ++ }, { ++ .name = "rk8602", ++ .driver_data = RK8602_VENDOR_ROCKCHIP ++ }, { + .name = "syr827", + .driver_data = FAN53555_VENDOR_SILERGY + }, { diff --git a/target/linux/rockchip/patches-6.1/033-01-v6.4-thermal-drivers-rockchip-Simplify-getting-match-data.patch b/target/linux/rockchip/patches-6.1/033-01-v6.4-thermal-drivers-rockchip-Simplify-getting-match-data.patch new file mode 100644 index 0000000000..25ffb411bf --- /dev/null +++ b/target/linux/rockchip/patches-6.1/033-01-v6.4-thermal-drivers-rockchip-Simplify-getting-match-data.patch @@ -0,0 +1,44 @@ +From f1d2427cb458fd8ecb709c27f43088d6e250a7aa Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 8 Mar 2023 12:22:47 +0100 +Subject: [PATCH] thermal/drivers/rockchip: Simplify getting match data + +It's possible to directly get the match data in a generic +way nowadays. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Sebastian Reichel +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230308112253.15659-2-sebastian.reichel@collabora.com +--- + drivers/thermal/rockchip_thermal.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -1353,16 +1353,11 @@ static int rockchip_thermal_probe(struct + { + struct device_node *np = pdev->dev.of_node; + struct rockchip_thermal_data *thermal; +- const struct of_device_id *match; + struct resource *res; + int irq; + int i; + int error; + +- match = of_match_node(of_rockchip_thermal_match, np); +- if (!match) +- return -ENXIO; +- + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -EINVAL; +@@ -1374,7 +1369,7 @@ static int rockchip_thermal_probe(struct + + thermal->pdev = pdev; + +- thermal->chip = (const struct rockchip_tsadc_chip *)match->data; ++ thermal->chip = device_get_match_data(&pdev->dev); + if (!thermal->chip) + return -EINVAL; + diff --git a/target/linux/rockchip/patches-6.1/033-02-v6.4-thermal-drivers-rockchip-Simplify-clock-logic.patch b/target/linux/rockchip/patches-6.1/033-02-v6.4-thermal-drivers-rockchip-Simplify-clock-logic.patch new file mode 100644 index 0000000000..f7fe4a7695 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/033-02-v6.4-thermal-drivers-rockchip-Simplify-clock-logic.patch @@ -0,0 +1,106 @@ +From 2f6916f12c0e46ecd4c2b793a014132140730560 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 8 Mar 2023 12:22:48 +0100 +Subject: [PATCH] thermal/drivers/rockchip: Simplify clock logic + +By using devm_clk_get_enabled() the clock acquisition and +enabling can be done in one step with automatic error +handling. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Sebastian Reichel +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230308112253.15659-3-sebastian.reichel@collabora.com +--- + drivers/thermal/rockchip_thermal.c | 33 +++++------------------------- + 1 file changed, 5 insertions(+), 28 deletions(-) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -1385,14 +1385,14 @@ static int rockchip_thermal_probe(struct + return error; + } + +- thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); ++ thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc"); + if (IS_ERR(thermal->clk)) { + error = PTR_ERR(thermal->clk); + dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); + return error; + } + +- thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); ++ thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); + if (IS_ERR(thermal->pclk)) { + error = PTR_ERR(thermal->pclk); + dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", +@@ -1400,26 +1400,13 @@ static int rockchip_thermal_probe(struct + return error; + } + +- error = clk_prepare_enable(thermal->clk); +- if (error) { +- dev_err(&pdev->dev, "failed to enable converter clock: %d\n", +- error); +- return error; +- } +- +- error = clk_prepare_enable(thermal->pclk); +- if (error) { +- dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); +- goto err_disable_clk; +- } +- + rockchip_thermal_reset_controller(thermal->reset); + + error = rockchip_configure_from_dt(&pdev->dev, np, thermal); + if (error) { + dev_err(&pdev->dev, "failed to parse device tree data: %d\n", + error); +- goto err_disable_pclk; ++ return error; + } + + thermal->chip->initialize(thermal->grf, thermal->regs, +@@ -1433,7 +1420,7 @@ static int rockchip_thermal_probe(struct + dev_err(&pdev->dev, + "failed to register sensor[%d] : error = %d\n", + i, error); +- goto err_disable_pclk; ++ return error; + } + } + +@@ -1444,7 +1431,7 @@ static int rockchip_thermal_probe(struct + if (error) { + dev_err(&pdev->dev, + "failed to request tsadc irq: %d\n", error); +- goto err_disable_pclk; ++ return error; + } + + thermal->chip->control(thermal->regs, true); +@@ -1462,13 +1449,6 @@ static int rockchip_thermal_probe(struct + platform_set_drvdata(pdev, thermal); + + return 0; +- +-err_disable_pclk: +- clk_disable_unprepare(thermal->pclk); +-err_disable_clk: +- clk_disable_unprepare(thermal->clk); +- +- return error; + } + + static int rockchip_thermal_remove(struct platform_device *pdev) +@@ -1485,9 +1465,6 @@ static int rockchip_thermal_remove(struc + + thermal->chip->control(thermal->regs, false); + +- clk_disable_unprepare(thermal->pclk); +- clk_disable_unprepare(thermal->clk); +- + return 0; + } + diff --git a/target/linux/rockchip/patches-6.1/033-03-v6.4-thermal-drivers-rockchip-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/033-03-v6.4-thermal-drivers-rockchip-Use-dev_err_probe.patch new file mode 100644 index 0000000000..fb628bf85d --- /dev/null +++ b/target/linux/rockchip/patches-6.1/033-03-v6.4-thermal-drivers-rockchip-Use-dev_err_probe.patch @@ -0,0 +1,96 @@ +From cb71c5f904c5b7e84d770c87bebc5df0bec200a4 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 8 Mar 2023 12:22:49 +0100 +Subject: [PATCH] thermal/drivers/rockchip: Use dev_err_probe + +Use dev_err_probe to simplify error printing in the driver's probe +routine. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Sebastian Reichel +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230308112253.15659-4-sebastian.reichel@collabora.com +--- + drivers/thermal/rockchip_thermal.c | 50 +++++++++++------------------- + 1 file changed, 18 insertions(+), 32 deletions(-) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -1379,35 +1379,26 @@ static int rockchip_thermal_probe(struct + return PTR_ERR(thermal->regs); + + thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); +- if (IS_ERR(thermal->reset)) { +- error = PTR_ERR(thermal->reset); +- dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); +- return error; +- } ++ if (IS_ERR(thermal->reset)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset), ++ "failed to get tsadc reset.\n"); + + thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc"); +- if (IS_ERR(thermal->clk)) { +- error = PTR_ERR(thermal->clk); +- dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); +- return error; +- } ++ if (IS_ERR(thermal->clk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk), ++ "failed to get tsadc clock.\n"); + + thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); +- if (IS_ERR(thermal->pclk)) { +- error = PTR_ERR(thermal->pclk); +- dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", +- error); +- return error; +- } ++ if (IS_ERR(thermal->pclk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk), ++ "failed to get apb_pclk clock.\n"); + + rockchip_thermal_reset_controller(thermal->reset); + + error = rockchip_configure_from_dt(&pdev->dev, np, thermal); +- if (error) { +- dev_err(&pdev->dev, "failed to parse device tree data: %d\n", +- error); +- return error; +- } ++ if (error) ++ return dev_err_probe(&pdev->dev, error, ++ "failed to parse device tree data\n"); + + thermal->chip->initialize(thermal->grf, thermal->regs, + thermal->tshut_polarity); +@@ -1416,23 +1407,18 @@ static int rockchip_thermal_probe(struct + error = rockchip_thermal_register_sensor(pdev, thermal, + &thermal->sensors[i], + thermal->chip->chn_id[i]); +- if (error) { +- dev_err(&pdev->dev, +- "failed to register sensor[%d] : error = %d\n", +- i, error); +- return error; +- } ++ if (error) ++ return dev_err_probe(&pdev->dev, error, ++ "failed to register sensor[%d].\n", i); + } + + error = devm_request_threaded_irq(&pdev->dev, irq, NULL, + &rockchip_thermal_alarm_irq_thread, + IRQF_ONESHOT, + "rockchip_thermal", thermal); +- if (error) { +- dev_err(&pdev->dev, +- "failed to request tsadc irq: %d\n", error); +- return error; +- } ++ if (error) ++ return dev_err_probe(&pdev->dev, error, ++ "failed to request tsadc irq.\n"); + + thermal->chip->control(thermal->regs, true); + diff --git a/target/linux/rockchip/patches-6.1/033-04-v6.4-thermal-drivers-rockchip-Simplify-channel-id-logic.patch b/target/linux/rockchip/patches-6.1/033-04-v6.4-thermal-drivers-rockchip-Simplify-channel-id-logic.patch new file mode 100644 index 0000000000..94735918ab --- /dev/null +++ b/target/linux/rockchip/patches-6.1/033-04-v6.4-thermal-drivers-rockchip-Simplify-channel-id-logic.patch @@ -0,0 +1,157 @@ +From f7cef1b743e84bdc7b1f2e5711615aaddf101ca8 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 8 Mar 2023 12:22:50 +0100 +Subject: [PATCH] thermal/drivers/rockchip: Simplify channel id logic + +Replace the channel ID lookup table by a simple offset, since +the channel IDs are consecutive. + +Signed-off-by: Sebastian Reichel +Signed-off-by: Daniel Lezcano +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20230308112253.15659-5-sebastian.reichel@collabora.com +--- + drivers/thermal/rockchip_thermal.c | 48 +++++++++++++----------------- + 1 file changed, 21 insertions(+), 27 deletions(-) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -40,15 +40,6 @@ enum tshut_polarity { + }; + + /* +- * The system has two Temperature Sensors. +- * sensor0 is for CPU, and sensor1 is for GPU. +- */ +-enum sensor_id { +- SENSOR_CPU = 0, +- SENSOR_GPU, +-}; +- +-/* + * The conversion table has the adc value and temperature. + * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) + * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) +@@ -82,7 +73,7 @@ struct chip_tsadc_table { + + /** + * struct rockchip_tsadc_chip - hold the private data of tsadc chip +- * @chn_id: array of sensor ids of chip corresponding to the channel ++ * @chn_offset: the channel offset of the first channel + * @chn_num: the channel number of tsadc chip + * @tshut_temp: the hardware-controlled shutdown temperature value + * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) +@@ -98,7 +89,7 @@ struct chip_tsadc_table { + */ + struct rockchip_tsadc_chip { + /* The sensor id of chip correspond to the ADC channel */ +- int chn_id[SOC_MAX_SENSORS]; ++ int chn_offset; + int chn_num; + + /* The hardware-controlled tshut property */ +@@ -925,8 +916,8 @@ static void rk_tsadcv2_tshut_mode(int ch + } + + static const struct rockchip_tsadc_chip px30_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ +- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ ++ /* cpu, gpu */ ++ .chn_offset = 0, + .chn_num = 2, /* 2 channels for tsadc */ + + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ +@@ -949,7 +940,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rv1108_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ ++ /* cpu */ ++ .chn_offset = 0, + .chn_num = 1, /* one channel for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ +@@ -973,7 +965,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rk3228_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ ++ /* cpu */ ++ .chn_offset = 0, + .chn_num = 1, /* one channel for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ +@@ -997,8 +990,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rk3288_tsadc_data = { +- .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ +- .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ ++ /* cpu, gpu */ ++ .chn_offset = 1, + .chn_num = 2, /* two channels for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ +@@ -1022,7 +1015,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rk3328_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ ++ /* cpu */ ++ .chn_offset = 0, + .chn_num = 1, /* one channels for tsadc */ + + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ +@@ -1045,8 +1039,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rk3366_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ +- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ ++ /* cpu, gpu */ ++ .chn_offset = 0, + .chn_num = 2, /* two channels for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ +@@ -1070,8 +1064,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rk3368_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ +- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ ++ /* cpu, gpu */ ++ .chn_offset = 0, + .chn_num = 2, /* two channels for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ +@@ -1095,8 +1089,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rk3399_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ +- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ ++ /* cpu, gpu */ ++ .chn_offset = 0, + .chn_num = 2, /* two channels for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ +@@ -1120,8 +1114,8 @@ static const struct rockchip_tsadc_chip + }; + + static const struct rockchip_tsadc_chip rk3568_tsadc_data = { +- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ +- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ ++ /* cpu, gpu */ ++ .chn_offset = 0, + .chn_num = 2, /* two channels for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ +@@ -1406,7 +1400,7 @@ static int rockchip_thermal_probe(struct + for (i = 0; i < thermal->chip->chn_num; i++) { + error = rockchip_thermal_register_sensor(pdev, thermal, + &thermal->sensors[i], +- thermal->chip->chn_id[i]); ++ thermal->chip->chn_offset + i); + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to register sensor[%d].\n", i); diff --git a/target/linux/rockchip/patches-6.1/033-05-v6.4-thermal-drivers-rockchip-Support-dynamic-sized-sensor-arr.patch b/target/linux/rockchip/patches-6.1/033-05-v6.4-thermal-drivers-rockchip-Support-dynamic-sized-sensor-arr.patch new file mode 100644 index 0000000000..b5324c1d4b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/033-05-v6.4-thermal-drivers-rockchip-Support-dynamic-sized-sensor-arr.patch @@ -0,0 +1,53 @@ +From 267f596585abc78efbdda51a80dd36c65c0f6ad0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 8 Mar 2023 12:22:51 +0100 +Subject: [PATCH] thermal/drivers/rockchip: Support dynamic sized sensor array + +Dynamically allocate the sensors array based on the amount +of platform sensors in preparation for rk3588 support, which +needs 7 sensors. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Sebastian Reichel +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230308112253.15659-6-sebastian.reichel@collabora.com +--- + drivers/thermal/rockchip_thermal.c | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -52,12 +52,6 @@ enum adc_sort_mode { + #include "thermal_hwmon.h" + + /** +- * The max sensors is two in rockchip SoCs. +- * Two sensors: CPU and GPU sensor. +- */ +-#define SOC_MAX_SENSORS 2 +- +-/** + * struct chip_tsadc_table - hold information about chip-specific differences + * @id: conversion table + * @length: size of conversion table +@@ -147,7 +141,7 @@ struct rockchip_thermal_data { + struct platform_device *pdev; + struct reset_control *reset; + +- struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; ++ struct rockchip_thermal_sensor *sensors; + + struct clk *clk; + struct clk *pclk; +@@ -1367,6 +1361,11 @@ static int rockchip_thermal_probe(struct + if (!thermal->chip) + return -EINVAL; + ++ thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num, ++ sizeof(*thermal->sensors), GFP_KERNEL); ++ if (!thermal->sensors) ++ return -ENOMEM; ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + thermal->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(thermal->regs)) diff --git a/target/linux/rockchip/patches-6.1/033-06-v6.4-thermal-drivers-rockchip-Support-RK3588-SoC-in-the-therma.patch b/target/linux/rockchip/patches-6.1/033-06-v6.4-thermal-drivers-rockchip-Support-RK3588-SoC-in-the-therma.patch new file mode 100644 index 0000000000..c071a1a908 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/033-06-v6.4-thermal-drivers-rockchip-Support-RK3588-SoC-in-the-therma.patch @@ -0,0 +1,319 @@ +From 45d7b3867a5cabb97fc31f16122cda8540c3a30c Mon Sep 17 00:00:00 2001 +From: Finley Xiao +Date: Wed, 8 Mar 2023 12:22:52 +0100 +Subject: [PATCH] thermal/drivers/rockchip: Support RK3588 SoC in the thermal + driver + +The RK3588 SoC has seven temperature sensor ADC channels: + +- Chip Center +- CPU Cluster 1 (Dual A76 "Big" Cores) +- CPU Cluster 2 (Dual A76 "Big" Cores) +- CPU Cluster 0 (Quad A55 "Little" Cores) +- Power Domain Center +- Graphics Processing Unit +- Neural Processing Unit + +Signed-off-by: Finley Xiao +[rebase, squash fixes] +Reviewed-by: Heiko Stuebner +Signed-off-by: Sebastian Reichel +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20230308112253.15659-7-sebastian.reichel@collabora.com +--- + drivers/thermal/rockchip_thermal.c | 177 +++++++++++++++++++++++++++++ + 1 file changed, 177 insertions(+) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -165,29 +165,49 @@ struct rockchip_thermal_data { + #define TSADCV2_AUTO_CON 0x04 + #define TSADCV2_INT_EN 0x08 + #define TSADCV2_INT_PD 0x0c ++#define TSADCV3_AUTO_SRC_CON 0x0c ++#define TSADCV3_HT_INT_EN 0x14 ++#define TSADCV3_HSHUT_GPIO_INT_EN 0x18 ++#define TSADCV3_HSHUT_CRU_INT_EN 0x1c ++#define TSADCV3_INT_PD 0x24 ++#define TSADCV3_HSHUT_PD 0x28 + #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) + #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) + #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) ++#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) ++#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) ++#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) + #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 + #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 ++#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c ++#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 + #define TSADCV2_AUTO_PERIOD 0x68 + #define TSADCV2_AUTO_PERIOD_HT 0x6c ++#define TSADCV3_AUTO_PERIOD 0x154 ++#define TSADCV3_AUTO_PERIOD_HT 0x158 + + #define TSADCV2_AUTO_EN BIT(0) ++#define TSADCV2_AUTO_EN_MASK BIT(16) + #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) ++#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) ++#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn) + #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) ++#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) + + #define TSADCV3_AUTO_Q_SEL_EN BIT(1) + + #define TSADCV2_INT_SRC_EN(chn) BIT(chn) ++#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) + #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) + #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) + + #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) + #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) ++#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff + + #define TSADCV2_DATA_MASK 0xfff + #define TSADCV3_DATA_MASK 0x3ff ++#define TSADCV4_DATA_MASK 0x1ff + + #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 + #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 +@@ -198,6 +218,8 @@ struct rockchip_thermal_data { + + #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ + #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ ++#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ ++#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ + + #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ + #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ +@@ -214,6 +236,12 @@ struct rockchip_thermal_data { + #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) + #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) + ++#define RK3588_GRF0_TSADC_CON 0x0100 ++ ++#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0) ++#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10) ++#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12) ++ + #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) + #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) + #define GRF_TSADC_VCM_EN_L (0x10001 << 7) +@@ -508,6 +536,15 @@ static const struct tsadc_table rk3568_c + {TSADCV2_DATA_MASK, 125000}, + }; + ++static const struct tsadc_table rk3588_code_table[] = { ++ {0, -40000}, ++ {215, -40000}, ++ {285, 25000}, ++ {350, 85000}, ++ {395, 125000}, ++ {TSADCV4_DATA_MASK, 125000}, ++}; ++ + static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, + int temp) + { +@@ -778,6 +815,25 @@ static void rk_tsadcv7_initialize(struct + } + } + ++static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs, ++ enum tshut_polarity tshut_polarity) ++{ ++ writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); ++ writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME, ++ regs + TSADCV3_AUTO_PERIOD_HT); ++ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, ++ regs + TSADCV3_HIGHT_INT_DEBOUNCE); ++ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, ++ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); ++ if (tshut_polarity == TSHUT_HIGH_ACTIVE) ++ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | ++ TSADCV2_AUTO_TSHUT_POLARITY_MASK, ++ regs + TSADCV2_AUTO_CON); ++ else ++ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, ++ regs + TSADCV2_AUTO_CON); ++} ++ + static void rk_tsadcv2_irq_ack(void __iomem *regs) + { + u32 val; +@@ -794,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __io + writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); + } + ++static void rk_tsadcv4_irq_ack(void __iomem *regs) ++{ ++ u32 val; ++ ++ val = readl_relaxed(regs + TSADCV3_INT_PD); ++ writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD); ++ val = readl_relaxed(regs + TSADCV3_HSHUT_PD); ++ writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, ++ regs + TSADCV3_HSHUT_PD); ++} ++ + static void rk_tsadcv2_control(void __iomem *regs, bool enable) + { + u32 val; +@@ -829,6 +896,18 @@ static void rk_tsadcv3_control(void __io + writel_relaxed(val, regs + TSADCV2_AUTO_CON); + } + ++static void rk_tsadcv4_control(void __iomem *regs, bool enable) ++{ ++ u32 val; ++ ++ if (enable) ++ val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; ++ else ++ val = TSADCV2_AUTO_EN_MASK; ++ ++ writel_relaxed(val, regs + TSADCV2_AUTO_CON); ++} ++ + static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int *temp) + { +@@ -839,6 +918,16 @@ static int rk_tsadcv2_get_temp(const str + return rk_tsadcv2_code_to_temp(table, val, temp); + } + ++static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table, ++ int chn, void __iomem *regs, int *temp) ++{ ++ u32 val; ++ ++ val = readl_relaxed(regs + TSADCV3_DATA(chn)); ++ ++ return rk_tsadcv2_code_to_temp(table, val, temp); ++} ++ + static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) + { +@@ -873,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const s + return 0; + } + ++static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table, ++ int chn, void __iomem *regs, int temp) ++{ ++ u32 alarm_value; ++ ++ /* ++ * In some cases, some sensors didn't need the trip points, the ++ * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm ++ * in the end, ignore this case and disable the high temperature ++ * interrupt. ++ */ ++ if (temp == INT_MAX) { ++ writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn), ++ regs + TSADCV3_HT_INT_EN); ++ return 0; ++ } ++ /* Make sure the value is valid */ ++ alarm_value = rk_tsadcv2_temp_to_code(table, temp); ++ if (alarm_value == table->data_mask) ++ return -ERANGE; ++ writel_relaxed(alarm_value & table->data_mask, ++ regs + TSADCV3_COMP_INT(chn)); ++ writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), ++ regs + TSADCV3_HT_INT_EN); ++ return 0; ++} ++ + static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) + { +@@ -892,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const s + return 0; + } + ++static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table, ++ int chn, void __iomem *regs, int temp) ++{ ++ u32 tshut_value; ++ ++ /* Make sure the value is valid */ ++ tshut_value = rk_tsadcv2_temp_to_code(table, temp); ++ if (tshut_value == table->data_mask) ++ return -ERANGE; ++ ++ writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn)); ++ ++ /* TSHUT will be valid */ ++ writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), ++ regs + TSADCV3_AUTO_SRC_CON); ++ ++ return 0; ++} ++ + static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, + enum tshut_mode mode) + { +@@ -909,6 +1044,22 @@ static void rk_tsadcv2_tshut_mode(int ch + writel_relaxed(val, regs + TSADCV2_INT_EN); + } + ++static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, ++ enum tshut_mode mode) ++{ ++ u32 val_gpio, val_cru; ++ ++ if (mode == TSHUT_MODE_GPIO) { ++ val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); ++ val_cru = TSADCV2_INT_SRC_EN_MASK(chn); ++ } else { ++ val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); ++ val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); ++ } ++ writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); ++ writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); ++} ++ + static const struct rockchip_tsadc_chip px30_tsadc_data = { + /* cpu, gpu */ + .chn_offset = 0, +@@ -1132,6 +1283,28 @@ static const struct rockchip_tsadc_chip + }, + }; + ++static const struct rockchip_tsadc_chip rk3588_tsadc_data = { ++ /* top, big_core0, big_core1, little_core, center, gpu, npu */ ++ .chn_offset = 0, ++ .chn_num = 7, /* seven channels for tsadc */ ++ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ ++ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ ++ .tshut_temp = 95000, ++ .initialize = rk_tsadcv8_initialize, ++ .irq_ack = rk_tsadcv4_irq_ack, ++ .control = rk_tsadcv4_control, ++ .get_temp = rk_tsadcv4_get_temp, ++ .set_alarm_temp = rk_tsadcv3_alarm_temp, ++ .set_tshut_temp = rk_tsadcv3_tshut_temp, ++ .set_tshut_mode = rk_tsadcv3_tshut_mode, ++ .table = { ++ .id = rk3588_code_table, ++ .length = ARRAY_SIZE(rk3588_code_table), ++ .data_mask = TSADCV4_DATA_MASK, ++ .mode = ADC_INCREMENT, ++ }, ++}; ++ + static const struct of_device_id of_rockchip_thermal_match[] = { + { .compatible = "rockchip,px30-tsadc", + .data = (void *)&px30_tsadc_data, +@@ -1168,6 +1341,10 @@ static const struct of_device_id of_rock + .compatible = "rockchip,rk3568-tsadc", + .data = (void *)&rk3568_tsadc_data, + }, ++ { ++ .compatible = "rockchip,rk3588-tsadc", ++ .data = (void *)&rk3588_tsadc_data, ++ }, + { /* end */ }, + }; + MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); diff --git a/target/linux/rockchip/patches-6.1/033-07-v6.4-thermal-drivers-rockchip-use.patch b/target/linux/rockchip/patches-6.1/033-07-v6.4-thermal-drivers-rockchip-use.patch new file mode 100644 index 0000000000..7f381e3a4b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/033-07-v6.4-thermal-drivers-rockchip-use.patch @@ -0,0 +1,28 @@ +From fee5caec88b3d1948453c55474cf16b81026a1b2 Mon Sep 17 00:00:00 2001 +From: Ye Xingchen +Date: Fri, 24 Mar 2023 11:08:55 +0800 +Subject: [PATCH] thermal/drivers/rockchip: use + devm_reset_control_array_get_exclusive() + +Switch devm_reset_control_array_get() to +devm_reset_control_array_get_exclusive(). + +Signed-off-by: Ye Xingchen +Reviewed-by: Philipp Zabel +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/202303241108553006227@zte.com.cn +--- + drivers/thermal/rockchip_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -1548,7 +1548,7 @@ static int rockchip_thermal_probe(struct + if (IS_ERR(thermal->regs)) + return PTR_ERR(thermal->regs); + +- thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); ++ thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(thermal->reset)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset), + "failed to get tsadc reset.\n"); diff --git a/target/linux/rockchip/patches-6.1/034-v6.4-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/034-v6.4-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch new file mode 100644 index 0000000000..ceab9d1d0d --- /dev/null +++ b/target/linux/rockchip/patches-6.1/034-v6.4-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch @@ -0,0 +1,232 @@ +From a03c4427725301328ccbe414d0a19ad39e90d008 Mon Sep 17 00:00:00 2001 +From: Lucas Tanure +Date: Tue, 14 Mar 2023 13:55:55 +0000 +Subject: [PATCH] phy: rockchip: Add naneng combo phy support for RK3588 + +Add support for RK3588 combo phy + +This is based on prior work from XiaoDong Huang and +Peter Geis fixing this issue specifically for Rockchip 356x. + +Co-developed-by: Andrew Powers-Holmes +Signed-off-by: Andrew Powers-Holmes +Signed-off-by: Lucas Tanure +Link: https://lore.kernel.org/r/20230314135555.44162-4-lucas.tanure@collabora.com +Signed-off-by: Vinod Koul +--- + .../rockchip/phy-rockchip-naneng-combphy.c | 184 ++++++++++++++++++ + 1 file changed, 184 insertions(+) + +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -63,6 +63,9 @@ + #define PHYREG18 0x44 + #define PHYREG18_PLL_LOOP 0x32 + ++#define PHYREG27 0x6C ++#define PHYREG27_RX_TRIM_RK3588 0x4C ++ + #define PHYREG32 0x7C + #define PHYREG32_SSC_MASK GENMASK(7, 4) + #define PHYREG32_SSC_DIR_SHIFT 4 +@@ -114,7 +117,10 @@ struct rockchip_combphy_grfcfg { + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; ++ struct combphy_reg pipe_con1_for_sata; + struct combphy_reg pipe_xpcs_phy_ready; ++ struct combphy_reg pipe_pcie1l0_sel; ++ struct combphy_reg pipe_pcie1l1_sel; + }; + + struct rockchip_combphy_cfg { +@@ -559,11 +565,189 @@ static const struct rockchip_combphy_cfg + .combphy_cfg = rk3568_combphy_cfg, + }; + ++static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) ++{ ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ unsigned long rate; ++ u32 val; ++ ++ switch (priv->type) { ++ case PHY_TYPE_PCIE: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); ++ break; ++ case PHY_TYPE_USB3: ++ /* Set SSC downward spread spectrum */ ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, ++ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, ++ PHYREG32); ++ ++ /* Enable adaptive CTLE for USB3.0 Rx. */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ ++ /* Set PLL KVCO fine tuning signals. */ ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, ++ PHYREG33); ++ ++ /* Enable controlling random jitter. */ ++ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ ++ /* Set PLL input clock divider 1/2. */ ++ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, ++ PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, ++ PHYREG6); ++ ++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); ++ break; ++ case PHY_TYPE_SATA: ++ /* Enable adaptive CTLE for SATA Rx. */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ /* ++ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. ++ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) ++ */ ++ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; ++ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; ++ writel(val, priv->mmio + PHYREG7); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); ++ break; ++ case PHY_TYPE_SGMII: ++ case PHY_TYPE_QSGMII: ++ default: ++ dev_err(priv->dev, "incompatible PHY type\n"); ++ return -EINVAL; ++ } ++ ++ rate = clk_get_rate(priv->refclk); ++ ++ switch (rate) { ++ case REF_CLOCK_24MHz: ++ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { ++ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ ++ val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; ++ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, ++ val, PHYREG15); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ } ++ break; ++ ++ case REF_CLOCK_25MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); ++ break; ++ case REF_CLOCK_100MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); ++ if (priv->type == PHY_TYPE_PCIE) { ++ /* PLL KVCO fine tuning. */ ++ val = 4 << PHYREG33_PLL_KVCO_SHIFT; ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Enable controlling random jitter. */ ++ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ ++ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ ++ writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); ++ ++ /* Set up su_trim: */ ++ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ } else if (priv->type == PHY_TYPE_SATA) { ++ /* downward spread spectrum +500ppm */ ++ val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; ++ val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ } ++ break; ++ default: ++ dev_err(priv->dev, "Unsupported rate: %lu\n", rate); ++ return -EINVAL; ++ } ++ ++ if (priv->ext_refclk) { ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); ++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { ++ val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; ++ val |= PHYREG13_CKRCV_AMP0; ++ rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); ++ ++ val = readl(priv->mmio + PHYREG14); ++ val |= PHYREG14_CKRCV_AMP1; ++ writel(val, priv->mmio + PHYREG14); ++ } ++ } ++ ++ if (priv->enable_ssc) { ++ val = readl(priv->mmio + PHYREG8); ++ val |= PHYREG8_SSC_EN; ++ writel(val, priv->mmio + PHYREG8); ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { ++ /* pipe-phy-grf */ ++ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, ++ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, ++ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, ++ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, ++ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, ++ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, ++ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, ++ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, ++ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, ++ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, ++ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, ++ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, ++ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, ++ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, ++ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, ++ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, ++ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, ++ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, ++ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, ++ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, ++ /* pipe-grf */ ++ .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, ++ .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, ++ .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 }, ++ .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 }, ++}; ++ ++static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { ++ .grfcfg = &rk3588_combphy_grfcfgs, ++ .combphy_cfg = rk3588_combphy_cfg, ++}; ++ + static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, ++ { ++ .compatible = "rockchip,rk3588-naneng-combphy", ++ .data = &rk3588_combphy_cfgs, ++ }, + { }, + }; + MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); diff --git a/target/linux/rockchip/patches-6.1/035-01-v6.2-ASoC-rockchip-i2s_tdm-Make-the-grf-property-optional.patch b/target/linux/rockchip/patches-6.1/035-01-v6.2-ASoC-rockchip-i2s_tdm-Make-the-grf-property-optional.patch new file mode 100644 index 0000000000..0cb3951aba --- /dev/null +++ b/target/linux/rockchip/patches-6.1/035-01-v6.2-ASoC-rockchip-i2s_tdm-Make-the-grf-property-optional.patch @@ -0,0 +1,55 @@ +From d980004e349049a3fcbffc6096d14896f6a122ed Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 25 Oct 2022 14:41:30 +0200 +Subject: [PATCH] ASoC: rockchip: i2s_tdm: Make the grf property optional + +Only IO Multiplex and two TRCM modes need access to the GRF, so +making it a hard requirement is not a wise idea, as it complicates +support for newer SoCs which do not do these things. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20221025124132.399729-3-frattaroli.nicolas@gmail.com +Signed-off-by: Mark Brown +--- + sound/soc/rockchip/rockchip_i2s_tdm.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +--- a/sound/soc/rockchip/rockchip_i2s_tdm.c ++++ b/sound/soc/rockchip/rockchip_i2s_tdm.c +@@ -756,6 +756,12 @@ static int rockchip_i2s_io_multiplex(str + if (!i2s_tdm->io_multiplex) + return 0; + ++ if (IS_ERR_OR_NULL(i2s_tdm->grf)) { ++ dev_err(i2s_tdm->dev, ++ "io multiplex not supported for this device\n"); ++ return -EINVAL; ++ } ++ + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + struct snd_pcm_str *playback_str = + &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; +@@ -1222,6 +1228,12 @@ static int common_soc_init(struct device + if (trcm == TRCM_TXRX) + return 0; + ++ if (IS_ERR_OR_NULL(i2s_tdm->grf)) { ++ dev_err(i2s_tdm->dev, ++ "no grf present but non-txrx TRCM specified\n"); ++ return -EINVAL; ++ } ++ + for (i = 0; i < i2s_tdm->soc_data->config_count; i++) { + if (addr != configs[i].addr) + continue; +@@ -1568,10 +1580,6 @@ static int rockchip_i2s_tdm_probe(struct + return ret; + + i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); +- if (IS_ERR(i2s_tdm->grf)) +- return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf), +- "Error in rockchip,grf\n"); +- + i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, + "tx-m"); + if (IS_ERR(i2s_tdm->tx_reset)) { diff --git a/target/linux/rockchip/patches-6.1/035-02-v6.2-ASoC-rockchip-i2s_tdm-Add-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/035-02-v6.2-ASoC-rockchip-i2s_tdm-Add-support-for-RK3588.patch new file mode 100644 index 0000000000..42ee51a561 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/035-02-v6.2-ASoC-rockchip-i2s_tdm-Add-support-for-RK3588.patch @@ -0,0 +1,33 @@ +From c619bd4268ff9895760dab303b4eb15ed3d0f7e9 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Tue, 25 Oct 2022 14:41:32 +0200 +Subject: [PATCH] ASoC: rockchip: i2s_tdm: Add support for RK3588 + +This adds support for the RK3588 SoC to the I2S/TDM driver. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20221025124132.399729-5-frattaroli.nicolas@gmail.com +Signed-off-by: Mark Brown +--- + sound/soc/rockchip/rockchip_i2s_tdm.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/sound/soc/rockchip/rockchip_i2s_tdm.c ++++ b/sound/soc/rockchip/rockchip_i2s_tdm.c +@@ -1318,6 +1318,7 @@ static const struct of_device_id rockchi + { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data }, + { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data }, + { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data }, ++ { .compatible = "rockchip,rk3588-i2s-tdm" }, + { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data }, + {}, + }; +@@ -1556,7 +1557,7 @@ static int rockchip_i2s_tdm_probe(struct + i2s_tdm->dev = &pdev->dev; + + of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev); +- if (!of_id || !of_id->data) ++ if (!of_id) + return -EINVAL; + + spin_lock_init(&i2s_tdm->lock); diff --git a/target/linux/rockchip/patches-6.1/035-03-v6.4-ASoC-rockchip-i2s-Add-compatible-for-RK3588.patch b/target/linux/rockchip/patches-6.1/035-03-v6.4-ASoC-rockchip-i2s-Add-compatible-for-RK3588.patch new file mode 100644 index 0000000000..fb711feba3 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/035-03-v6.4-ASoC-rockchip-i2s-Add-compatible-for-RK3588.patch @@ -0,0 +1,25 @@ +From 0e6c37610934e9b91f6f5f2599de5e2f1ab59e72 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Wed, 15 Mar 2023 13:48:03 +0200 +Subject: [PATCH] ASoC: rockchip: i2s: Add compatible for RK3588 + +The Rockchip I2S driver supports the RK3588/RK3588S SoCs, hence add the +corresponding compatible string. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230315114806.3819515-9-cristian.ciocaltea@collabora.com +Signed-off-by: Mark Brown +--- + sound/soc/rockchip/rockchip_i2s.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/sound/soc/rockchip/rockchip_i2s.c ++++ b/sound/soc/rockchip/rockchip_i2s.c +@@ -659,6 +659,7 @@ static const struct of_device_id rockchi + { .compatible = "rockchip,rk3366-i2s", }, + { .compatible = "rockchip,rk3368-i2s", }, + { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, ++ { .compatible = "rockchip,rk3588-i2s", }, + { .compatible = "rockchip,rv1126-i2s", }, + {}, + }; diff --git a/target/linux/rockchip/patches-6.1/036-01-v6.5-nvmem-rockchip-otp-Add-clks-and-reg_read-to-rockchip_data.patch b/target/linux/rockchip/patches-6.1/036-01-v6.5-nvmem-rockchip-otp-Add-clks-and-reg_read-to-rockchip_data.patch new file mode 100644 index 0000000000..a8d3daff78 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/036-01-v6.5-nvmem-rockchip-otp-Add-clks-and-reg_read-to-rockchip_data.patch @@ -0,0 +1,177 @@ +From: Cristian Ciocaltea +To: Srinivas Kandagatla , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Sebastian Reichel , + Shreeya Patel , + Kever Yang , + Finley Xiao , + Vincent Legoll +Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, + kernel@collabora.com +Subject: [PATCH v2 3/8] nvmem: rockchip-otp: Add clks and reg_read to rockchip_data +Date: Thu, 4 May 2023 23:06:43 +0300 [thread overview] +Message-ID: <20230504200648.1119866-4-cristian.ciocaltea@collabora.com> (raw) +In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> + +In preparation to support new Rockchip OTP memory devices with different +clock configurations and register layout, extend rockchip_data struct +with the related members: clks, num_clks, reg_read. + +Additionally, to avoid managing redundant driver data, drop num_clks +member from rockchip_otp struct and update all references to point to +the equivalent member in rockchip_data. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +--- + drivers/nvmem/rockchip-otp.c | 79 ++++++++++++++++++++++-------------- + 1 file changed, 49 insertions(+), 30 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -54,21 +54,19 @@ + + #define OTPC_TIMEOUT 10000 + ++struct rockchip_data { ++ int size; ++ const char * const *clks; ++ int num_clks; ++ nvmem_reg_read_t reg_read; ++}; ++ + struct rockchip_otp { + struct device *dev; + void __iomem *base; +- struct clk_bulk_data *clks; +- int num_clks; ++ struct clk_bulk_data *clks; + struct reset_control *rst; +-}; +- +-/* list of required clocks */ +-static const char * const rockchip_otp_clocks[] = { +- "otp", "apb_pclk", "phy", +-}; +- +-struct rockchip_data { +- int size; ++ const struct rockchip_data *data; + }; + + static int rockchip_otp_reset(struct rockchip_otp *otp) +@@ -132,29 +130,23 @@ static int rockchip_otp_ecc_enable(struc + return ret; + } + +-static int rockchip_otp_read(void *context, unsigned int offset, +- void *val, size_t bytes) ++static int px30_otp_read(void *context, unsigned int offset, ++ void *val, size_t bytes) + { + struct rockchip_otp *otp = context; + u8 *buf = val; +- int ret = 0; +- +- ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); +- if (ret < 0) { +- dev_err(otp->dev, "failed to prepare/enable clks\n"); +- return ret; +- } ++ int ret; + + ret = rockchip_otp_reset(otp); + if (ret) { + dev_err(otp->dev, "failed to reset otp phy\n"); +- goto disable_clks; ++ return ret; + } + + ret = rockchip_otp_ecc_enable(otp, false); + if (ret < 0) { + dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); +- goto disable_clks; ++ return ret; + } + + writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); +@@ -174,8 +166,28 @@ static int rockchip_otp_read(void *conte + + read_end: + writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); +-disable_clks: +- clk_bulk_disable_unprepare(otp->num_clks, otp->clks); ++ ++ return ret; ++} ++ ++static int rockchip_otp_read(void *context, unsigned int offset, ++ void *val, size_t bytes) ++{ ++ struct rockchip_otp *otp = context; ++ int ret; ++ ++ if (!otp->data || !otp->data->reg_read) ++ return -EINVAL; ++ ++ ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks); ++ if (ret < 0) { ++ dev_err(otp->dev, "failed to prepare/enable clks\n"); ++ return ret; ++ } ++ ++ ret = otp->data->reg_read(context, offset, val, bytes); ++ ++ clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks); + + return ret; + } +@@ -189,8 +201,15 @@ static struct nvmem_config otp_config = + .reg_read = rockchip_otp_read, + }; + ++static const char * const px30_otp_clocks[] = { ++ "otp", "apb_pclk", "phy", ++}; ++ + static const struct rockchip_data px30_data = { + .size = 0x40, ++ .clks = px30_otp_clocks, ++ .num_clks = ARRAY_SIZE(px30_otp_clocks), ++ .reg_read = px30_otp_read, + }; + + static const struct of_device_id rockchip_otp_match[] = { +@@ -225,21 +244,21 @@ static int rockchip_otp_probe(struct pla + if (!otp) + return -ENOMEM; + ++ otp->data = data; + otp->dev = dev; + otp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(otp->base)) + return PTR_ERR(otp->base); + +- otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks); +- otp->clks = devm_kcalloc(dev, otp->num_clks, +- sizeof(*otp->clks), GFP_KERNEL); ++ otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), ++ GFP_KERNEL); + if (!otp->clks) + return -ENOMEM; + +- for (i = 0; i < otp->num_clks; ++i) +- otp->clks[i].id = rockchip_otp_clocks[i]; ++ for (i = 0; i < data->num_clks; ++i) ++ otp->clks[i].id = data->clks[i]; + +- ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks); ++ ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); + if (ret) + return ret; + diff --git a/target/linux/rockchip/patches-6.1/036-02-v6.5-nvmem-rockchip-otp-Generalize-rockchip_otp_wait_status.patch b/target/linux/rockchip/patches-6.1/036-02-v6.5-nvmem-rockchip-otp-Generalize-rockchip_otp_wait_status.patch new file mode 100644 index 0000000000..5128bbed41 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/036-02-v6.5-nvmem-rockchip-otp-Generalize-rockchip_otp_wait_status.patch @@ -0,0 +1,73 @@ +From: Cristian Ciocaltea +To: Srinivas Kandagatla , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Sebastian Reichel , + Shreeya Patel , + Kever Yang , + Finley Xiao , + Vincent Legoll +Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, + kernel@collabora.com +Subject: [PATCH v2 4/8] nvmem: rockchip-otp: Generalize rockchip_otp_wait_status() +Date: Thu, 4 May 2023 23:06:44 +0300 [thread overview] +Message-ID: <20230504200648.1119866-5-cristian.ciocaltea@collabora.com> (raw) +In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> + +In preparation to support additional Rockchip OTP memory devices with +different register layout, generalize rockchip_otp_wait_status() to +accept a new parameter for specifying the offset of the status register. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +--- + drivers/nvmem/rockchip-otp.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -90,18 +90,19 @@ static int rockchip_otp_reset(struct roc + return 0; + } + +-static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag) ++static int rockchip_otp_wait_status(struct rockchip_otp *otp, ++ unsigned int reg, u32 flag) + { + u32 status = 0; + int ret; + +- ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status, ++ ret = readl_poll_timeout_atomic(otp->base + reg, status, + (status & flag), 1, OTPC_TIMEOUT); + if (ret) + return ret; + + /* clean int status */ +- writel(flag, otp->base + OTPC_INT_STATUS); ++ writel(flag, otp->base + reg); + + return 0; + } +@@ -123,7 +124,7 @@ static int rockchip_otp_ecc_enable(struc + + writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); + +- ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE); ++ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE); + if (ret < 0) + dev_err(otp->dev, "timeout during ecc_enable\n"); + +@@ -156,7 +157,7 @@ static int px30_otp_read(void *context, + otp->base + OTPC_USER_ADDR); + writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, + otp->base + OTPC_USER_ENABLE); +- ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE); ++ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); + if (ret < 0) { + dev_err(otp->dev, "timeout during read setup\n"); + goto read_end; diff --git a/target/linux/rockchip/patches-6.1/036-03-v6.5-nvmem-rockchip-otp-Use-devm_reset_control_array_get_exclu.patch b/target/linux/rockchip/patches-6.1/036-03-v6.5-nvmem-rockchip-otp-Use-devm_reset_control_array_get_exclu.patch new file mode 100644 index 0000000000..bb81dec65b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/036-03-v6.5-nvmem-rockchip-otp-Use-devm_reset_control_array_get_exclu.patch @@ -0,0 +1,41 @@ +From: Cristian Ciocaltea +To: Srinivas Kandagatla , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Sebastian Reichel , + Shreeya Patel , + Kever Yang , + Finley Xiao , + Vincent Legoll +Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, + kernel@collabora.com +Subject: [PATCH v2 5/8] nvmem: rockchip-otp: Use devm_reset_control_array_get_exclusive() +Date: Thu, 4 May 2023 23:06:45 +0300 [thread overview] +Message-ID: <20230504200648.1119866-6-cristian.ciocaltea@collabora.com> (raw) +In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> + +In preparation to support new Rockchip OTP memory devices having +specific reset configurations, switch devm_reset_control_get() to +devm_reset_control_array_get_exclusive(). + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +--- + drivers/nvmem/rockchip-otp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -263,7 +263,7 @@ static int rockchip_otp_probe(struct pla + if (ret) + return ret; + +- otp->rst = devm_reset_control_get(dev, "phy"); ++ otp->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(otp->rst)) + return PTR_ERR(otp->rst); + diff --git a/target/linux/rockchip/patches-6.1/036-04-v6.5-nvmem-rockchip-otp-Improve-probe-error-handling.patch b/target/linux/rockchip/patches-6.1/036-04-v6.5-nvmem-rockchip-otp-Improve-probe-error-handling.patch new file mode 100644 index 0000000000..aae51abf09 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/036-04-v6.5-nvmem-rockchip-otp-Improve-probe-error-handling.patch @@ -0,0 +1,82 @@ +From: Cristian Ciocaltea +To: Srinivas Kandagatla , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Sebastian Reichel , + Shreeya Patel , + Kever Yang , + Finley Xiao , + Vincent Legoll +Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, + kernel@collabora.com +Subject: [PATCH v2 6/8] nvmem: rockchip-otp: Improve probe error handling +Date: Thu, 4 May 2023 23:06:46 +0300 [thread overview] +Message-ID: <20230504200648.1119866-7-cristian.ciocaltea@collabora.com> (raw) +In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> + +Enhance error handling in the probe function by making use of +dev_err_probe(), which ensures the error code is always printed, in +addition to the specified error message. + +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +--- + drivers/nvmem/rockchip-otp.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -235,10 +235,8 @@ static int rockchip_otp_probe(struct pla + int ret, i; + + data = of_device_get_match_data(dev); +- if (!data) { +- dev_err(dev, "failed to get match data\n"); +- return -EINVAL; +- } ++ if (!data) ++ return dev_err_probe(dev, -EINVAL, "failed to get match data\n"); + + otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp), + GFP_KERNEL); +@@ -249,7 +247,8 @@ static int rockchip_otp_probe(struct pla + otp->dev = dev; + otp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(otp->base)) +- return PTR_ERR(otp->base); ++ return dev_err_probe(dev, PTR_ERR(otp->base), ++ "failed to ioremap resource\n"); + + otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), + GFP_KERNEL); +@@ -261,18 +260,22 @@ static int rockchip_otp_probe(struct pla + + ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); + if (ret) +- return ret; ++ return dev_err_probe(dev, ret, "failed to get clocks\n"); + + otp->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(otp->rst)) +- return PTR_ERR(otp->rst); ++ return dev_err_probe(dev, PTR_ERR(otp->rst), ++ "failed to get resets\n"); + + otp_config.size = data->size; + otp_config.priv = otp; + otp_config.dev = dev; +- nvmem = devm_nvmem_register(dev, &otp_config); + +- return PTR_ERR_OR_ZERO(nvmem); ++ nvmem = devm_nvmem_register(dev, &otp_config); ++ if (IS_ERR(nvmem)) ++ return dev_err_probe(dev, PTR_ERR(nvmem), ++ "failed to register nvmem device\n"); ++ return 0; + } + + static struct platform_driver rockchip_otp_driver = { diff --git a/target/linux/rockchip/patches-6.1/036-05-v6.5-nvmem-rockchip-otp-Add-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/036-05-v6.5-nvmem-rockchip-otp-Add-support-for-RK3588.patch new file mode 100644 index 0000000000..a4a494c1a5 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/036-05-v6.5-nvmem-rockchip-otp-Add-support-for-RK3588.patch @@ -0,0 +1,140 @@ +From: Cristian Ciocaltea +To: Srinivas Kandagatla , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Sebastian Reichel , + Shreeya Patel , + Kever Yang , + Finley Xiao , + Vincent Legoll +Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, + kernel@collabora.com +Subject: [PATCH v2 7/8] nvmem: rockchip-otp: Add support for RK3588 +Date: Thu, 4 May 2023 23:06:47 +0300 [thread overview] +Message-ID: <20230504200648.1119866-8-cristian.ciocaltea@collabora.com> (raw) +In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> + +Add support for the OTP memory device found on the Rockchip RK3588 SoC. + +While here, remove the unnecessary 'void *' casts in the OF device ID +table. + +Co-developed-by: Finley Xiao +Signed-off-by: Finley Xiao +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +Reviewed-by: Heiko Stuebner +--- + drivers/nvmem/rockchip-otp.c | 78 +++++++++++++++++++++++++++++++++++- + 1 file changed, 76 insertions(+), 2 deletions(-) + +--- a/drivers/nvmem/rockchip-otp.c ++++ b/drivers/nvmem/rockchip-otp.c +@@ -54,6 +54,19 @@ + + #define OTPC_TIMEOUT 10000 + ++/* RK3588 Register */ ++#define RK3588_OTPC_AUTO_CTRL 0x04 ++#define RK3588_OTPC_AUTO_EN 0x08 ++#define RK3588_OTPC_INT_ST 0x84 ++#define RK3588_OTPC_DOUT0 0x20 ++#define RK3588_NO_SECURE_OFFSET 0x300 ++#define RK3588_NBYTES 4 ++#define RK3588_BURST_NUM 1 ++#define RK3588_BURST_SHIFT 8 ++#define RK3588_ADDR_SHIFT 16 ++#define RK3588_AUTO_EN BIT(0) ++#define RK3588_RD_DONE BIT(1) ++ + struct rockchip_data { + int size; + const char * const *clks; +@@ -171,6 +184,52 @@ read_end: + return ret; + } + ++static int rk3588_otp_read(void *context, unsigned int offset, ++ void *val, size_t bytes) ++{ ++ struct rockchip_otp *otp = context; ++ unsigned int addr_start, addr_end, addr_len; ++ int ret, i = 0; ++ u32 data; ++ u8 *buf; ++ ++ addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES; ++ addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES; ++ addr_len = addr_end - addr_start; ++ addr_start += RK3588_NO_SECURE_OFFSET; ++ ++ buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ while (addr_len--) { ++ writel((addr_start << RK3588_ADDR_SHIFT) | ++ (RK3588_BURST_NUM << RK3588_BURST_SHIFT), ++ otp->base + RK3588_OTPC_AUTO_CTRL); ++ writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN); ++ ++ ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST, ++ RK3588_RD_DONE); ++ if (ret < 0) { ++ dev_err(otp->dev, "timeout during read setup\n"); ++ goto read_end; ++ } ++ ++ data = readl(otp->base + RK3588_OTPC_DOUT0); ++ memcpy(&buf[i], &data, RK3588_NBYTES); ++ ++ i += RK3588_NBYTES; ++ addr_start++; ++ } ++ ++ memcpy(val, buf + offset % RK3588_NBYTES, bytes); ++ ++read_end: ++ kfree(buf); ++ ++ return ret; ++} ++ + static int rockchip_otp_read(void *context, unsigned int offset, + void *val, size_t bytes) + { +@@ -213,14 +272,29 @@ static const struct rockchip_data px30_d + .reg_read = px30_otp_read, + }; + ++static const char * const rk3588_otp_clocks[] = { ++ "otp", "apb_pclk", "phy", "arb", ++}; ++ ++static const struct rockchip_data rk3588_data = { ++ .size = 0x400, ++ .clks = rk3588_otp_clocks, ++ .num_clks = ARRAY_SIZE(rk3588_otp_clocks), ++ .reg_read = rk3588_otp_read, ++}; ++ + static const struct of_device_id rockchip_otp_match[] = { + { + .compatible = "rockchip,px30-otp", +- .data = (void *)&px30_data, ++ .data = &px30_data, + }, + { + .compatible = "rockchip,rk3308-otp", +- .data = (void *)&px30_data, ++ .data = &px30_data, ++ }, ++ { ++ .compatible = "rockchip,rk3588-otp", ++ .data = &rk3588_data, + }, + { /* sentinel */ }, + }; diff --git a/target/linux/rockchip/patches-6.1/050-01-v6.3-arm64-dts-rockchip-Add-rk3588-pinctrl-data.patch b/target/linux/rockchip/patches-6.1/050-01-v6.3-arm64-dts-rockchip-Add-rk3588-pinctrl-data.patch new file mode 100644 index 0000000000..55587e3201 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-01-v6.3-arm64-dts-rockchip-Add-rk3588-pinctrl-data.patch @@ -0,0 +1,3957 @@ +From d85f8a5c798d593366d0e0acdb6a547591a7aaff Mon Sep 17 00:00:00 2001 +From: Jianqun Xu +Date: Mon, 9 Jan 2023 16:57:56 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add rk3588 pinctrl data + +This adds the pin controller data for rk3588 and rk3588s. + +Co-Developed-by: Shengfei Xu +Signed-off-by: Shengfei Xu +Co-Developed-by: Damon Ding +Signed-off-by: Damon Ding +Co-Developed-by: Steven Liu +Signed-off-by: Steven Liu +Co-Developed-by: Jon Lin +Signed-off-by: Jon Lin +Co-Developed-by: Finley Xiao +Signed-off-by: Finley Xiao +Signed-off-by: Jianqun Xu +[port from vendor tree merging all fixes] +Reviewed-by: Linus Walleij +Signed-off-by: Sebastian Reichel +Acked-by: Jagan Teki +Tested-by: Jagan Teki # edgeble-neu6a +Link: https://lore.kernel.org/r/20230109155801.51642-3-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3588-pinctrl.dtsi | 516 +++ + .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++ + 2 files changed, 3919 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi +@@ -0,0 +1,516 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include "rockchip-pinconf.dtsi" ++ ++/* ++ * This file is auto generated by pin2dts tool, please keep these code ++ * by adding changes at end of this file. ++ */ ++&pinctrl { ++ clk32k { ++ /omit-if-no-ref/ ++ clk32k_out1: clk32k-out1 { ++ rockchip,pins = ++ /* clk32k_out1 */ ++ <2 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ eth0 { ++ /omit-if-no-ref/ ++ eth0_pins: eth0-pins { ++ rockchip,pins = ++ /* eth0_refclko_25m */ ++ <2 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ fspi { ++ /omit-if-no-ref/ ++ fspim1_pins: fspim1-pins { ++ rockchip,pins = ++ /* fspi_clk_m1 */ ++ <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_cs0n_m1 */ ++ <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d0_m1 */ ++ <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d1_m1 */ ++ <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d2_m1 */ ++ <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d3_m1 */ ++ <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim1_cs1: fspim1-cs1 { ++ rockchip,pins = ++ /* fspi_cs1n_m1 */ ++ <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; ++ }; ++ }; ++ ++ gmac0 { ++ /omit-if-no-ref/ ++ gmac0_miim: gmac0-miim { ++ rockchip,pins = ++ /* gmac0_mdc */ ++ <4 RK_PC4 1 &pcfg_pull_none>, ++ /* gmac0_mdio */ ++ <4 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_clkinout: gmac0-clkinout { ++ rockchip,pins = ++ /* gmac0_mclkinout */ ++ <4 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_rx_bus2: gmac0-rx-bus2 { ++ rockchip,pins = ++ /* gmac0_rxd0 */ ++ <2 RK_PC1 1 &pcfg_pull_none>, ++ /* gmac0_rxd1 */ ++ <2 RK_PC2 1 &pcfg_pull_none>, ++ /* gmac0_rxdv_crs */ ++ <4 RK_PC2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_tx_bus2: gmac0-tx-bus2 { ++ rockchip,pins = ++ /* gmac0_txd0 */ ++ <2 RK_PB6 1 &pcfg_pull_none>, ++ /* gmac0_txd1 */ ++ <2 RK_PB7 1 &pcfg_pull_none>, ++ /* gmac0_txen */ ++ <2 RK_PC0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_rgmii_clk: gmac0-rgmii-clk { ++ rockchip,pins = ++ /* gmac0_rxclk */ ++ <2 RK_PB0 1 &pcfg_pull_none>, ++ /* gmac0_txclk */ ++ <2 RK_PB3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_rgmii_bus: gmac0-rgmii-bus { ++ rockchip,pins = ++ /* gmac0_rxd2 */ ++ <2 RK_PA6 1 &pcfg_pull_none>, ++ /* gmac0_rxd3 */ ++ <2 RK_PA7 1 &pcfg_pull_none>, ++ /* gmac0_txd2 */ ++ <2 RK_PB1 1 &pcfg_pull_none>, ++ /* gmac0_txd3 */ ++ <2 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_ppsclk: gmac0-ppsclk { ++ rockchip,pins = ++ /* gmac0_ppsclk */ ++ <2 RK_PC4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_ppstring: gmac0-ppstring { ++ rockchip,pins = ++ /* gmac0_ppstring */ ++ <2 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_ptp_refclk: gmac0-ptp-refclk { ++ rockchip,pins = ++ /* gmac0_ptp_refclk */ ++ <2 RK_PB4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac0_txer: gmac0-txer { ++ rockchip,pins = ++ /* gmac0_txer */ ++ <4 RK_PC6 1 &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ hdmi { ++ /omit-if-no-ref/ ++ hdmim0_tx1_cec: hdmim0-tx1-cec { ++ rockchip,pins = ++ /* hdmim0_tx1_cec */ ++ <2 RK_PC4 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx1_scl: hdmim0-tx1-scl { ++ rockchip,pins = ++ /* hdmim0_tx1_scl */ ++ <2 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx1_sda: hdmim0-tx1-sda { ++ rockchip,pins = ++ /* hdmim0_tx1_sda */ ++ <2 RK_PB4 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2c0 { ++ /omit-if-no-ref/ ++ i2c0m1_xfer: i2c0m1-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m1 */ ++ <4 RK_PC5 9 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m1 */ ++ <4 RK_PC6 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c2 { ++ /omit-if-no-ref/ ++ i2c2m1_xfer: i2c2m1-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m1 */ ++ <2 RK_PC1 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m1 */ ++ <2 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c3 { ++ /omit-if-no-ref/ ++ i2c3m3_xfer: i2c3m3-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m3 */ ++ <2 RK_PB2 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m3 */ ++ <2 RK_PB3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c4 { ++ /omit-if-no-ref/ ++ i2c4m1_xfer: i2c4m1-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m1 */ ++ <2 RK_PB5 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m1 */ ++ <2 RK_PB4 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c5 { ++ /omit-if-no-ref/ ++ i2c5m4_xfer: i2c5m4-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m4 */ ++ <2 RK_PB6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m4 */ ++ <2 RK_PB7 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c6 { ++ /omit-if-no-ref/ ++ i2c6m2_xfer: i2c6m2-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m2 */ ++ <2 RK_PC3 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m2 */ ++ <2 RK_PC2 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c7 { ++ /omit-if-no-ref/ ++ i2c7m1_xfer: i2c7m1-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m1 */ ++ <4 RK_PC3 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m1 */ ++ <4 RK_PC4 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c8 { ++ /omit-if-no-ref/ ++ i2c8m1_xfer: i2c8m1-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m1 */ ++ <2 RK_PB0 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m1 */ ++ <2 RK_PB1 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2s2 { ++ /omit-if-no-ref/ ++ i2s2m0_lrck: i2s2m0-lrck { ++ rockchip,pins = ++ /* i2s2m0_lrck */ ++ <2 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_mclk: i2s2m0-mclk { ++ rockchip,pins = ++ /* i2s2m0_mclk */ ++ <2 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sclk: i2s2m0-sclk { ++ rockchip,pins = ++ /* i2s2m0_sclk */ ++ <2 RK_PB7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdi: i2s2m0-sdi { ++ rockchip,pins = ++ /* i2s2m0_sdi */ ++ <2 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdo: i2s2m0-sdo { ++ rockchip,pins = ++ /* i2s2m0_sdo */ ++ <4 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm2 { ++ /omit-if-no-ref/ ++ pwm2m2_pins: pwm2m2-pins { ++ rockchip,pins = ++ /* pwm2_m2 */ ++ <4 RK_PC2 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm4 { ++ /omit-if-no-ref/ ++ pwm4m1_pins: pwm4m1-pins { ++ rockchip,pins = ++ /* pwm4_m1 */ ++ <4 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm5 { ++ /omit-if-no-ref/ ++ pwm5m2_pins: pwm5m2-pins { ++ rockchip,pins = ++ /* pwm5_m2 */ ++ <4 RK_PC4 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm6 { ++ /omit-if-no-ref/ ++ pwm6m2_pins: pwm6m2-pins { ++ rockchip,pins = ++ /* pwm6_m2 */ ++ <4 RK_PC5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm7 { ++ /omit-if-no-ref/ ++ pwm7m3_pins: pwm7m3-pins { ++ rockchip,pins = ++ /* pwm7_ir_m3 */ ++ <4 RK_PC6 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdio { ++ /omit-if-no-ref/ ++ sdiom0_pins: sdiom0-pins { ++ rockchip,pins = ++ /* sdio_clk_m0 */ ++ <2 RK_PB3 2 &pcfg_pull_none>, ++ /* sdio_cmd_m0 */ ++ <2 RK_PB2 2 &pcfg_pull_none>, ++ /* sdio_d0_m0 */ ++ <2 RK_PA6 2 &pcfg_pull_none>, ++ /* sdio_d1_m0 */ ++ <2 RK_PA7 2 &pcfg_pull_none>, ++ /* sdio_d2_m0 */ ++ <2 RK_PB0 2 &pcfg_pull_none>, ++ /* sdio_d3_m0 */ ++ <2 RK_PB1 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi1 { ++ /omit-if-no-ref/ ++ spi1m0_pins: spi1m0-pins { ++ rockchip,pins = ++ /* spi1_clk_m0 */ ++ <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_miso_m0 */ ++ <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_mosi_m0 */ ++ <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m0_cs0: spi1m0-cs0 { ++ rockchip,pins = ++ /* spi1_cs0_m0 */ ++ <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m0_cs1: spi1m0-cs1 { ++ rockchip,pins = ++ /* spi1_cs1_m0 */ ++ <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi3 { ++ /omit-if-no-ref/ ++ spi3m0_pins: spi3m0-pins { ++ rockchip,pins = ++ /* spi3_clk_m0 */ ++ <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m0 */ ++ <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m0 */ ++ <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m0_cs0: spi3m0-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m0 */ ++ <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m0_cs1: spi3m0-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m0 */ ++ <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ uart1 { ++ /omit-if-no-ref/ ++ uart1m0_xfer: uart1m0-xfer { ++ rockchip,pins = ++ /* uart1_rx_m0 */ ++ <2 RK_PB6 10 &pcfg_pull_up>, ++ /* uart1_tx_m0 */ ++ <2 RK_PB7 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m0_ctsn: uart1m0-ctsn { ++ rockchip,pins = ++ /* uart1m0_ctsn */ ++ <2 RK_PC1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m0_rtsn: uart1m0-rtsn { ++ rockchip,pins = ++ /* uart1m0_rtsn */ ++ <2 RK_PC0 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart6 { ++ /omit-if-no-ref/ ++ uart6m0_xfer: uart6m0-xfer { ++ rockchip,pins = ++ /* uart6_rx_m0 */ ++ <2 RK_PA6 10 &pcfg_pull_up>, ++ /* uart6_tx_m0 */ ++ <2 RK_PA7 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m0_ctsn: uart6m0-ctsn { ++ rockchip,pins = ++ /* uart6m0_ctsn */ ++ <2 RK_PB1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m0_rtsn: uart6m0-rtsn { ++ rockchip,pins = ++ /* uart6m0_rtsn */ ++ <2 RK_PB0 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart7 { ++ /omit-if-no-ref/ ++ uart7m0_xfer: uart7m0-xfer { ++ rockchip,pins = ++ /* uart7_rx_m0 */ ++ <2 RK_PB4 10 &pcfg_pull_up>, ++ /* uart7_tx_m0 */ ++ <2 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m0_ctsn: uart7m0-ctsn { ++ rockchip,pins = ++ /* uart7m0_ctsn */ ++ <4 RK_PC6 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m0_rtsn: uart7m0-rtsn { ++ rockchip,pins = ++ /* uart7m0_rtsn */ ++ <4 RK_PC2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart9 { ++ /omit-if-no-ref/ ++ uart9m0_xfer: uart9m0-xfer { ++ rockchip,pins = ++ /* uart9_rx_m0 */ ++ <2 RK_PC4 10 &pcfg_pull_up>, ++ /* uart9_tx_m0 */ ++ <2 RK_PC2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m0_ctsn: uart9m0-ctsn { ++ rockchip,pins = ++ /* uart9m0_ctsn */ ++ <4 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m0_rtsn: uart9m0-rtsn { ++ rockchip,pins = ++ /* uart9m0_rtsn */ ++ <4 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +@@ -0,0 +1,3403 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include "rockchip-pinconf.dtsi" ++ ++/* ++ * This file is auto generated by pin2dts tool, please keep these code ++ * by adding changes at end of this file. ++ */ ++&pinctrl { ++ auddsm { ++ /omit-if-no-ref/ ++ auddsm_pins: auddsm-pins { ++ rockchip,pins = ++ /* auddsm_ln */ ++ <3 RK_PA1 4 &pcfg_pull_none>, ++ /* auddsm_lp */ ++ <3 RK_PA2 4 &pcfg_pull_none>, ++ /* auddsm_rn */ ++ <3 RK_PA3 4 &pcfg_pull_none>, ++ /* auddsm_rp */ ++ <3 RK_PA4 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ bt1120 { ++ /omit-if-no-ref/ ++ bt1120_pins: bt1120-pins { ++ rockchip,pins = ++ /* bt1120_clkout */ ++ <4 RK_PB0 2 &pcfg_pull_none>, ++ /* bt1120_d0 */ ++ <4 RK_PA0 2 &pcfg_pull_none>, ++ /* bt1120_d1 */ ++ <4 RK_PA1 2 &pcfg_pull_none>, ++ /* bt1120_d2 */ ++ <4 RK_PA2 2 &pcfg_pull_none>, ++ /* bt1120_d3 */ ++ <4 RK_PA3 2 &pcfg_pull_none>, ++ /* bt1120_d4 */ ++ <4 RK_PA4 2 &pcfg_pull_none>, ++ /* bt1120_d5 */ ++ <4 RK_PA5 2 &pcfg_pull_none>, ++ /* bt1120_d6 */ ++ <4 RK_PA6 2 &pcfg_pull_none>, ++ /* bt1120_d7 */ ++ <4 RK_PA7 2 &pcfg_pull_none>, ++ /* bt1120_d8 */ ++ <4 RK_PB2 2 &pcfg_pull_none>, ++ /* bt1120_d9 */ ++ <4 RK_PB3 2 &pcfg_pull_none>, ++ /* bt1120_d10 */ ++ <4 RK_PB4 2 &pcfg_pull_none>, ++ /* bt1120_d11 */ ++ <4 RK_PB5 2 &pcfg_pull_none>, ++ /* bt1120_d12 */ ++ <4 RK_PB6 2 &pcfg_pull_none>, ++ /* bt1120_d13 */ ++ <4 RK_PB7 2 &pcfg_pull_none>, ++ /* bt1120_d14 */ ++ <4 RK_PC0 2 &pcfg_pull_none>, ++ /* bt1120_d15 */ ++ <4 RK_PC1 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can0 { ++ /omit-if-no-ref/ ++ can0m0_pins: can0m0-pins { ++ rockchip,pins = ++ /* can0_rx_m0 */ ++ <0 RK_PC0 11 &pcfg_pull_none>, ++ /* can0_tx_m0 */ ++ <0 RK_PB7 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can0m1_pins: can0m1-pins { ++ rockchip,pins = ++ /* can0_rx_m1 */ ++ <4 RK_PD5 9 &pcfg_pull_none>, ++ /* can0_tx_m1 */ ++ <4 RK_PD4 9 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can1 { ++ /omit-if-no-ref/ ++ can1m0_pins: can1m0-pins { ++ rockchip,pins = ++ /* can1_rx_m0 */ ++ <3 RK_PB5 9 &pcfg_pull_none>, ++ /* can1_tx_m0 */ ++ <3 RK_PB6 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can1m1_pins: can1m1-pins { ++ rockchip,pins = ++ /* can1_rx_m1 */ ++ <4 RK_PB2 12 &pcfg_pull_none>, ++ /* can1_tx_m1 */ ++ <4 RK_PB3 12 &pcfg_pull_none>; ++ }; ++ }; ++ ++ can2 { ++ /omit-if-no-ref/ ++ can2m0_pins: can2m0-pins { ++ rockchip,pins = ++ /* can2_rx_m0 */ ++ <3 RK_PC4 9 &pcfg_pull_none>, ++ /* can2_tx_m0 */ ++ <3 RK_PC5 9 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ can2m1_pins: can2m1-pins { ++ rockchip,pins = ++ /* can2_rx_m1 */ ++ <0 RK_PD4 10 &pcfg_pull_none>, ++ /* can2_tx_m1 */ ++ <0 RK_PD5 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cif { ++ /omit-if-no-ref/ ++ cif_clk: cif-clk { ++ rockchip,pins = ++ /* cif_clkout */ ++ <4 RK_PB4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cif_dvp_clk: cif-dvp-clk { ++ rockchip,pins = ++ /* cif_clkin */ ++ <4 RK_PB0 1 &pcfg_pull_none>, ++ /* cif_href */ ++ <4 RK_PB2 1 &pcfg_pull_none>, ++ /* cif_vsync */ ++ <4 RK_PB3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cif_dvp_bus16: cif-dvp-bus16 { ++ rockchip,pins = ++ /* cif_d8 */ ++ <3 RK_PC4 1 &pcfg_pull_none>, ++ /* cif_d9 */ ++ <3 RK_PC5 1 &pcfg_pull_none>, ++ /* cif_d10 */ ++ <3 RK_PC6 1 &pcfg_pull_none>, ++ /* cif_d11 */ ++ <3 RK_PC7 1 &pcfg_pull_none>, ++ /* cif_d12 */ ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ /* cif_d13 */ ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ /* cif_d14 */ ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ /* cif_d15 */ ++ <3 RK_PD3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ cif_dvp_bus8: cif-dvp-bus8 { ++ rockchip,pins = ++ /* cif_d0 */ ++ <4 RK_PA0 1 &pcfg_pull_none>, ++ /* cif_d1 */ ++ <4 RK_PA1 1 &pcfg_pull_none>, ++ /* cif_d2 */ ++ <4 RK_PA2 1 &pcfg_pull_none>, ++ /* cif_d3 */ ++ <4 RK_PA3 1 &pcfg_pull_none>, ++ /* cif_d4 */ ++ <4 RK_PA4 1 &pcfg_pull_none>, ++ /* cif_d5 */ ++ <4 RK_PA5 1 &pcfg_pull_none>, ++ /* cif_d6 */ ++ <4 RK_PA6 1 &pcfg_pull_none>, ++ /* cif_d7 */ ++ <4 RK_PA7 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ clk32k { ++ /omit-if-no-ref/ ++ clk32k_in: clk32k-in { ++ rockchip,pins = ++ /* clk32k_in */ ++ <0 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ clk32k_out0: clk32k-out0 { ++ rockchip,pins = ++ /* clk32k_out0 */ ++ <0 RK_PB2 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ cpu { ++ /omit-if-no-ref/ ++ cpu_pins: cpu-pins { ++ rockchip,pins = ++ /* cpu_big0_avs */ ++ <0 RK_PD1 2 &pcfg_pull_none>, ++ /* cpu_big1_avs */ ++ <0 RK_PD5 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych0 { ++ /omit-if-no-ref/ ++ ddrphych0_pins: ddrphych0-pins { ++ rockchip,pins = ++ /* ddrphych0_dtb0 */ ++ <4 RK_PA0 7 &pcfg_pull_none>, ++ /* ddrphych0_dtb1 */ ++ <4 RK_PA1 7 &pcfg_pull_none>, ++ /* ddrphych0_dtb2 */ ++ <4 RK_PA2 7 &pcfg_pull_none>, ++ /* ddrphych0_dtb3 */ ++ <4 RK_PA3 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych1 { ++ /omit-if-no-ref/ ++ ddrphych1_pins: ddrphych1-pins { ++ rockchip,pins = ++ /* ddrphych1_dtb0 */ ++ <4 RK_PA4 7 &pcfg_pull_none>, ++ /* ddrphych1_dtb1 */ ++ <4 RK_PA5 7 &pcfg_pull_none>, ++ /* ddrphych1_dtb2 */ ++ <4 RK_PA6 7 &pcfg_pull_none>, ++ /* ddrphych1_dtb3 */ ++ <4 RK_PA7 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych2 { ++ /omit-if-no-ref/ ++ ddrphych2_pins: ddrphych2-pins { ++ rockchip,pins = ++ /* ddrphych2_dtb0 */ ++ <4 RK_PB0 7 &pcfg_pull_none>, ++ /* ddrphych2_dtb1 */ ++ <4 RK_PB1 7 &pcfg_pull_none>, ++ /* ddrphych2_dtb2 */ ++ <4 RK_PB2 7 &pcfg_pull_none>, ++ /* ddrphych2_dtb3 */ ++ <4 RK_PB3 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ ddrphych3 { ++ /omit-if-no-ref/ ++ ddrphych3_pins: ddrphych3-pins { ++ rockchip,pins = ++ /* ddrphych3_dtb0 */ ++ <4 RK_PB4 7 &pcfg_pull_none>, ++ /* ddrphych3_dtb1 */ ++ <4 RK_PB5 7 &pcfg_pull_none>, ++ /* ddrphych3_dtb2 */ ++ <4 RK_PB6 7 &pcfg_pull_none>, ++ /* ddrphych3_dtb3 */ ++ <4 RK_PB7 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dp0 { ++ /omit-if-no-ref/ ++ dp0m0_pins: dp0m0-pins { ++ rockchip,pins = ++ /* dp0_hpdin_m0 */ ++ <4 RK_PB4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp0m1_pins: dp0m1-pins { ++ rockchip,pins = ++ /* dp0_hpdin_m1 */ ++ <0 RK_PC4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp0m2_pins: dp0m2-pins { ++ rockchip,pins = ++ /* dp0_hpdin_m2 */ ++ <1 RK_PA0 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ dp1 { ++ /omit-if-no-ref/ ++ dp1m0_pins: dp1m0-pins { ++ rockchip,pins = ++ /* dp1_hpdin_m0 */ ++ <3 RK_PD5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp1m1_pins: dp1m1-pins { ++ rockchip,pins = ++ /* dp1_hpdin_m1 */ ++ <0 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ dp1m2_pins: dp1m2-pins { ++ rockchip,pins = ++ /* dp1_hpdin_m2 */ ++ <1 RK_PA1 5 &pcfg_pull_none>; ++ }; ++ }; ++ ++ emmc { ++ /omit-if-no-ref/ ++ emmc_rstnout: emmc-rstnout { ++ rockchip,pins = ++ /* emmc_rstn */ ++ <2 RK_PA3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_bus8: emmc-bus8 { ++ rockchip,pins = ++ /* emmc_d0 */ ++ <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d1 */ ++ <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d2 */ ++ <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d3 */ ++ <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d4 */ ++ <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d5 */ ++ <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d6 */ ++ <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, ++ /* emmc_d7 */ ++ <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_clk: emmc-clk { ++ rockchip,pins = ++ /* emmc_clkout */ ++ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_cmd: emmc-cmd { ++ rockchip,pins = ++ /* emmc_cmd */ ++ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ emmc_data_strobe: emmc-data-strobe { ++ rockchip,pins = ++ /* emmc_data_strobe */ ++ <2 RK_PA2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth1 { ++ /omit-if-no-ref/ ++ eth1_pins: eth1-pins { ++ rockchip,pins = ++ /* eth1_refclko_25m */ ++ <3 RK_PA6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ fspi { ++ /omit-if-no-ref/ ++ fspim0_pins: fspim0-pins { ++ rockchip,pins = ++ /* fspi_clk_m0 */ ++ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_cs0n_m0 */ ++ <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d0_m0 */ ++ <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d1_m0 */ ++ <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d2_m0 */ ++ <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d3_m0 */ ++ <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim0_cs1: fspim0-cs1 { ++ rockchip,pins = ++ /* fspi_cs1n_m0 */ ++ <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim2_pins: fspim2-pins { ++ rockchip,pins = ++ /* fspi_clk_m2 */ ++ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_cs0n_m2 */ ++ <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d0_m2 */ ++ <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d1_m2 */ ++ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d2_m2 */ ++ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, ++ /* fspi_d3_m2 */ ++ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ fspim2_cs1: fspim2-cs1 { ++ rockchip,pins = ++ /* fspi_cs1n_m2 */ ++ <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; ++ }; ++ }; ++ ++ gmac1 { ++ /omit-if-no-ref/ ++ gmac1_miim: gmac1-miim { ++ rockchip,pins = ++ /* gmac1_mdc */ ++ <3 RK_PC2 1 &pcfg_pull_none>, ++ /* gmac1_mdio */ ++ <3 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_clkinout: gmac1-clkinout { ++ rockchip,pins = ++ /* gmac1_mclkinout */ ++ <3 RK_PB6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_rx_bus2: gmac1-rx-bus2 { ++ rockchip,pins = ++ /* gmac1_rxd0 */ ++ <3 RK_PA7 1 &pcfg_pull_none>, ++ /* gmac1_rxd1 */ ++ <3 RK_PB0 1 &pcfg_pull_none>, ++ /* gmac1_rxdv_crs */ ++ <3 RK_PB1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_tx_bus2: gmac1-tx-bus2 { ++ rockchip,pins = ++ /* gmac1_txd0 */ ++ <3 RK_PB3 1 &pcfg_pull_none>, ++ /* gmac1_txd1 */ ++ <3 RK_PB4 1 &pcfg_pull_none>, ++ /* gmac1_txen */ ++ <3 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_rgmii_clk: gmac1-rgmii-clk { ++ rockchip,pins = ++ /* gmac1_rxclk */ ++ <3 RK_PA5 1 &pcfg_pull_none>, ++ /* gmac1_txclk */ ++ <3 RK_PA4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_rgmii_bus: gmac1-rgmii-bus { ++ rockchip,pins = ++ /* gmac1_rxd2 */ ++ <3 RK_PA2 1 &pcfg_pull_none>, ++ /* gmac1_rxd3 */ ++ <3 RK_PA3 1 &pcfg_pull_none>, ++ /* gmac1_txd2 */ ++ <3 RK_PA0 1 &pcfg_pull_none>, ++ /* gmac1_txd3 */ ++ <3 RK_PA1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_ppsclk: gmac1-ppsclk { ++ rockchip,pins = ++ /* gmac1_ppsclk */ ++ <3 RK_PC1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_ppstrig: gmac1-ppstrig { ++ rockchip,pins = ++ /* gmac1_ppstrig */ ++ <3 RK_PC0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { ++ rockchip,pins = ++ /* gmac1_ptp_ref_clk */ ++ <3 RK_PB7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ gmac1_txer: gmac1-txer { ++ rockchip,pins = ++ /* gmac1_txer */ ++ <3 RK_PB2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ gpu { ++ /omit-if-no-ref/ ++ gpu_pins: gpu-pins { ++ rockchip,pins = ++ /* gpu_avs */ ++ <0 RK_PC5 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ hdmi { ++ /omit-if-no-ref/ ++ hdmim0_rx_cec: hdmim0-rx-cec { ++ rockchip,pins = ++ /* hdmim0_rx_cec */ ++ <4 RK_PB5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_rx_hpdin: hdmim0-rx-hpdin { ++ rockchip,pins = ++ /* hdmim0_rx_hpdin */ ++ <4 RK_PB6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_rx_scl: hdmim0-rx-scl { ++ rockchip,pins = ++ /* hdmim0_rx_scl */ ++ <0 RK_PD2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_rx_sda: hdmim0-rx-sda { ++ rockchip,pins = ++ /* hdmim0_rx_sda */ ++ <0 RK_PD1 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_cec: hdmim0-tx0-cec { ++ rockchip,pins = ++ /* hdmim0_tx0_cec */ ++ <4 RK_PC1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_hpd: hdmim0-tx0-hpd { ++ rockchip,pins = ++ /* hdmim0_tx0_hpd */ ++ <1 RK_PA5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_scl: hdmim0-tx0-scl { ++ rockchip,pins = ++ /* hdmim0_tx0_scl */ ++ <4 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx0_sda: hdmim0-tx0-sda { ++ rockchip,pins = ++ /* hdmim0_tx0_sda */ ++ <4 RK_PC0 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim0_tx1_hpd: hdmim0-tx1-hpd { ++ rockchip,pins = ++ /* hdmim0_tx1_hpd */ ++ <1 RK_PA6 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ hdmim1_rx_cec: hdmim1-rx-cec { ++ rockchip,pins = ++ /* hdmim1_rx_cec */ ++ <3 RK_PD1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_rx_hpdin: hdmim1-rx-hpdin { ++ rockchip,pins = ++ /* hdmim1_rx_hpdin */ ++ <3 RK_PD4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_rx_scl: hdmim1-rx-scl { ++ rockchip,pins = ++ /* hdmim1_rx_scl */ ++ <3 RK_PD2 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_rx_sda: hdmim1-rx-sda { ++ rockchip,pins = ++ /* hdmim1_rx_sda */ ++ <3 RK_PD3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_cec: hdmim1-tx0-cec { ++ rockchip,pins = ++ /* hdmim1_tx0_cec */ ++ <0 RK_PD1 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_hpd: hdmim1-tx0-hpd { ++ rockchip,pins = ++ /* hdmim1_tx0_hpd */ ++ <3 RK_PD4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_scl: hdmim1-tx0-scl { ++ rockchip,pins = ++ /* hdmim1_tx0_scl */ ++ <0 RK_PD5 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx0_sda: hdmim1-tx0-sda { ++ rockchip,pins = ++ /* hdmim1_tx0_sda */ ++ <0 RK_PD4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_cec: hdmim1-tx1-cec { ++ rockchip,pins = ++ /* hdmim1_tx1_cec */ ++ <0 RK_PD2 13 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_hpd: hdmim1-tx1-hpd { ++ rockchip,pins = ++ /* hdmim1_tx1_hpd */ ++ <3 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_scl: hdmim1-tx1-scl { ++ rockchip,pins = ++ /* hdmim1_tx1_scl */ ++ <3 RK_PC6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim1_tx1_sda: hdmim1-tx1-sda { ++ rockchip,pins = ++ /* hdmim1_tx1_sda */ ++ <3 RK_PC5 5 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ hdmim2_rx_cec: hdmim2-rx-cec { ++ rockchip,pins = ++ /* hdmim2_rx_cec */ ++ <1 RK_PB7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_rx_hpdin: hdmim2-rx-hpdin { ++ rockchip,pins = ++ /* hdmim2_rx_hpdin */ ++ <1 RK_PB6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_rx_scl: hdmim2-rx-scl { ++ rockchip,pins = ++ /* hdmim2_rx_scl */ ++ <1 RK_PD6 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_rx_sda: hdmim2-rx-sda { ++ rockchip,pins = ++ /* hdmim2_rx_sda */ ++ <1 RK_PD7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx0_scl: hdmim2-tx0-scl { ++ rockchip,pins = ++ /* hdmim2_tx0_scl */ ++ <3 RK_PC7 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx0_sda: hdmim2-tx0-sda { ++ rockchip,pins = ++ /* hdmim2_tx0_sda */ ++ <3 RK_PD0 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx1_cec: hdmim2-tx1-cec { ++ rockchip,pins = ++ /* hdmim2_tx1_cec */ ++ <3 RK_PC4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx1_scl: hdmim2-tx1-scl { ++ rockchip,pins = ++ /* hdmim2_tx1_scl */ ++ <1 RK_PA4 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmim2_tx1_sda: hdmim2-tx1-sda { ++ rockchip,pins = ++ /* hdmim2_tx1_sda */ ++ <1 RK_PA3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug0: hdmi-debug0 { ++ rockchip,pins = ++ /* hdmi_debug0 */ ++ <1 RK_PA7 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug1: hdmi-debug1 { ++ rockchip,pins = ++ /* hdmi_debug1 */ ++ <1 RK_PB0 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug2: hdmi-debug2 { ++ rockchip,pins = ++ /* hdmi_debug2 */ ++ <1 RK_PB1 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug3: hdmi-debug3 { ++ rockchip,pins = ++ /* hdmi_debug3 */ ++ <1 RK_PB2 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug4: hdmi-debug4 { ++ rockchip,pins = ++ /* hdmi_debug4 */ ++ <1 RK_PB3 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug5: hdmi-debug5 { ++ rockchip,pins = ++ /* hdmi_debug5 */ ++ <1 RK_PB4 7 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ hdmi_debug6: hdmi-debug6 { ++ rockchip,pins = ++ /* hdmi_debug6 */ ++ <1 RK_PA0 7 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2c0 { ++ /omit-if-no-ref/ ++ i2c0m0_xfer: i2c0m0-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m0 */ ++ <0 RK_PB3 2 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m0 */ ++ <0 RK_PA6 2 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c0m2_xfer: i2c0m2-xfer { ++ rockchip,pins = ++ /* i2c0_scl_m2 */ ++ <0 RK_PD1 3 &pcfg_pull_none_smt>, ++ /* i2c0_sda_m2 */ ++ <0 RK_PD2 3 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c1 { ++ /omit-if-no-ref/ ++ i2c1m0_xfer: i2c1m0-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m0 */ ++ <0 RK_PB5 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m0 */ ++ <0 RK_PB6 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m1_xfer: i2c1m1-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m1 */ ++ <0 RK_PB0 2 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m1 */ ++ <0 RK_PB1 2 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m2_xfer: i2c1m2-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m2 */ ++ <0 RK_PD4 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m2 */ ++ <0 RK_PD5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m3_xfer: i2c1m3-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m3 */ ++ <2 RK_PD4 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m3 */ ++ <2 RK_PD5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c1m4_xfer: i2c1m4-xfer { ++ rockchip,pins = ++ /* i2c1_scl_m4 */ ++ <1 RK_PD2 9 &pcfg_pull_none_smt>, ++ /* i2c1_sda_m4 */ ++ <1 RK_PD3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c2 { ++ /omit-if-no-ref/ ++ i2c2m0_xfer: i2c2m0-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m0 */ ++ <0 RK_PB7 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m0 */ ++ <0 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m2_xfer: i2c2m2-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m2 */ ++ <2 RK_PA3 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m2 */ ++ <2 RK_PA2 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m3_xfer: i2c2m3-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m3 */ ++ <1 RK_PC5 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m3 */ ++ <1 RK_PC4 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2m4_xfer: i2c2m4-xfer { ++ rockchip,pins = ++ /* i2c2_scl_m4 */ ++ <1 RK_PA1 9 &pcfg_pull_none_smt>, ++ /* i2c2_sda_m4 */ ++ <1 RK_PA0 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c3 { ++ /omit-if-no-ref/ ++ i2c3m0_xfer: i2c3m0-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m0 */ ++ <1 RK_PC1 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m0 */ ++ <1 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m1_xfer: i2c3m1-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m1 */ ++ <3 RK_PB7 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m1 */ ++ <3 RK_PC0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m2_xfer: i2c3m2-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m2 */ ++ <4 RK_PA4 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m2 */ ++ <4 RK_PA5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3m4_xfer: i2c3m4-xfer { ++ rockchip,pins = ++ /* i2c3_scl_m4 */ ++ <4 RK_PD0 9 &pcfg_pull_none_smt>, ++ /* i2c3_sda_m4 */ ++ <4 RK_PD1 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c4 { ++ /omit-if-no-ref/ ++ i2c4m0_xfer: i2c4m0-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m0 */ ++ <3 RK_PA6 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m0 */ ++ <3 RK_PA5 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m2_xfer: i2c4m2-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m2 */ ++ <0 RK_PC5 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m2 */ ++ <0 RK_PC4 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m3_xfer: i2c4m3-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m3 */ ++ <1 RK_PA3 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m3 */ ++ <1 RK_PA2 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4m4_xfer: i2c4m4-xfer { ++ rockchip,pins = ++ /* i2c4_scl_m4 */ ++ <1 RK_PC7 9 &pcfg_pull_none_smt>, ++ /* i2c4_sda_m4 */ ++ <1 RK_PC6 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c5 { ++ /omit-if-no-ref/ ++ i2c5m0_xfer: i2c5m0-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m0 */ ++ <3 RK_PC7 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m0 */ ++ <3 RK_PD0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m1_xfer: i2c5m1-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m1 */ ++ <4 RK_PB6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m1 */ ++ <4 RK_PB7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m2_xfer: i2c5m2-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m2 */ ++ <4 RK_PA6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m2 */ ++ <4 RK_PA7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c5m3_xfer: i2c5m3-xfer { ++ rockchip,pins = ++ /* i2c5_scl_m3 */ ++ <1 RK_PB6 9 &pcfg_pull_none_smt>, ++ /* i2c5_sda_m3 */ ++ <1 RK_PB7 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c6 { ++ /omit-if-no-ref/ ++ i2c6m0_xfer: i2c6m0-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m0 */ ++ <0 RK_PD0 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m0 */ ++ <0 RK_PC7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m1_xfer: i2c6m1-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m1 */ ++ <1 RK_PC3 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m1 */ ++ <1 RK_PC2 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m3_xfer: i2c6m3-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m3 */ ++ <4 RK_PB1 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m3 */ ++ <4 RK_PB0 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c6m4_xfer: i2c6m4-xfer { ++ rockchip,pins = ++ /* i2c6_scl_m4 */ ++ <3 RK_PA1 9 &pcfg_pull_none_smt>, ++ /* i2c6_sda_m4 */ ++ <3 RK_PA0 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c7 { ++ /omit-if-no-ref/ ++ i2c7m0_xfer: i2c7m0-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m0 */ ++ <1 RK_PD0 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m0 */ ++ <1 RK_PD1 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c7m2_xfer: i2c7m2-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m2 */ ++ <3 RK_PD2 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m2 */ ++ <3 RK_PD3 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c7m3_xfer: i2c7m3-xfer { ++ rockchip,pins = ++ /* i2c7_scl_m3 */ ++ <4 RK_PB2 9 &pcfg_pull_none_smt>, ++ /* i2c7_sda_m3 */ ++ <4 RK_PB3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2c8 { ++ /omit-if-no-ref/ ++ i2c8m0_xfer: i2c8m0-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m0 */ ++ <4 RK_PD2 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m0 */ ++ <4 RK_PD3 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m2_xfer: i2c8m2-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m2 */ ++ <1 RK_PD6 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m2 */ ++ <1 RK_PD7 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m3_xfer: i2c8m3-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m3 */ ++ <4 RK_PC0 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m3 */ ++ <4 RK_PC1 9 &pcfg_pull_none_smt>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c8m4_xfer: i2c8m4-xfer { ++ rockchip,pins = ++ /* i2c8_scl_m4 */ ++ <3 RK_PC2 9 &pcfg_pull_none_smt>, ++ /* i2c8_sda_m4 */ ++ <3 RK_PC3 9 &pcfg_pull_none_smt>; ++ }; ++ }; ++ ++ i2s0 { ++ /omit-if-no-ref/ ++ i2s0_lrck: i2s0-lrck { ++ rockchip,pins = ++ /* i2s0_lrck */ ++ <1 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_mclk: i2s0-mclk { ++ rockchip,pins = ++ /* i2s0_mclk */ ++ <1 RK_PC2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sclk: i2s0-sclk { ++ rockchip,pins = ++ /* i2s0_sclk */ ++ <1 RK_PC3 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi0: i2s0-sdi0 { ++ rockchip,pins = ++ /* i2s0_sdi0 */ ++ <1 RK_PD4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi1: i2s0-sdi1 { ++ rockchip,pins = ++ /* i2s0_sdi1 */ ++ <1 RK_PD3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi2: i2s0-sdi2 { ++ rockchip,pins = ++ /* i2s0_sdi2 */ ++ <1 RK_PD2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdi3: i2s0-sdi3 { ++ rockchip,pins = ++ /* i2s0_sdi3 */ ++ <1 RK_PD1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo0: i2s0-sdo0 { ++ rockchip,pins = ++ /* i2s0_sdo0 */ ++ <1 RK_PC7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo1: i2s0-sdo1 { ++ rockchip,pins = ++ /* i2s0_sdo1 */ ++ <1 RK_PD0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo2: i2s0-sdo2 { ++ rockchip,pins = ++ /* i2s0_sdo2 */ ++ <1 RK_PD1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s0_sdo3: i2s0-sdo3 { ++ rockchip,pins = ++ /* i2s0_sdo3 */ ++ <1 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2s1 { ++ /omit-if-no-ref/ ++ i2s1m0_lrck: i2s1m0-lrck { ++ rockchip,pins = ++ /* i2s1m0_lrck */ ++ <4 RK_PA2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_mclk: i2s1m0-mclk { ++ rockchip,pins = ++ /* i2s1m0_mclk */ ++ <4 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sclk: i2s1m0-sclk { ++ rockchip,pins = ++ /* i2s1m0_sclk */ ++ <4 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi0: i2s1m0-sdi0 { ++ rockchip,pins = ++ /* i2s1m0_sdi0 */ ++ <4 RK_PA5 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi1: i2s1m0-sdi1 { ++ rockchip,pins = ++ /* i2s1m0_sdi1 */ ++ <4 RK_PA6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi2: i2s1m0-sdi2 { ++ rockchip,pins = ++ /* i2s1m0_sdi2 */ ++ <4 RK_PA7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdi3: i2s1m0-sdi3 { ++ rockchip,pins = ++ /* i2s1m0_sdi3 */ ++ <4 RK_PB0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo0: i2s1m0-sdo0 { ++ rockchip,pins = ++ /* i2s1m0_sdo0 */ ++ <4 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo1: i2s1m0-sdo1 { ++ rockchip,pins = ++ /* i2s1m0_sdo1 */ ++ <4 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo2: i2s1m0-sdo2 { ++ rockchip,pins = ++ /* i2s1m0_sdo2 */ ++ <4 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m0_sdo3: i2s1m0-sdo3 { ++ rockchip,pins = ++ /* i2s1m0_sdo3 */ ++ <4 RK_PB4 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ i2s1m1_lrck: i2s1m1-lrck { ++ rockchip,pins = ++ /* i2s1m1_lrck */ ++ <0 RK_PB7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_mclk: i2s1m1-mclk { ++ rockchip,pins = ++ /* i2s1m1_mclk */ ++ <0 RK_PB5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sclk: i2s1m1-sclk { ++ rockchip,pins = ++ /* i2s1m1_sclk */ ++ <0 RK_PB6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi0: i2s1m1-sdi0 { ++ rockchip,pins = ++ /* i2s1m1_sdi0 */ ++ <0 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi1: i2s1m1-sdi1 { ++ rockchip,pins = ++ /* i2s1m1_sdi1 */ ++ <0 RK_PC6 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi2: i2s1m1-sdi2 { ++ rockchip,pins = ++ /* i2s1m1_sdi2 */ ++ <0 RK_PC7 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdi3: i2s1m1-sdi3 { ++ rockchip,pins = ++ /* i2s1m1_sdi3 */ ++ <0 RK_PD0 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo0: i2s1m1-sdo0 { ++ rockchip,pins = ++ /* i2s1m1_sdo0 */ ++ <0 RK_PD1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo1: i2s1m1-sdo1 { ++ rockchip,pins = ++ /* i2s1m1_sdo1 */ ++ <0 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo2: i2s1m1-sdo2 { ++ rockchip,pins = ++ /* i2s1m1_sdo2 */ ++ <0 RK_PD4 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s1m1_sdo3: i2s1m1-sdo3 { ++ rockchip,pins = ++ /* i2s1m1_sdo3 */ ++ <0 RK_PD5 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2s2 { ++ /omit-if-no-ref/ ++ i2s2m1_lrck: i2s2m1-lrck { ++ rockchip,pins = ++ /* i2s2m1_lrck */ ++ <3 RK_PB6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_mclk: i2s2m1-mclk { ++ rockchip,pins = ++ /* i2s2m1_mclk */ ++ <3 RK_PB4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_sclk: i2s2m1-sclk { ++ rockchip,pins = ++ /* i2s2m1_sclk */ ++ <3 RK_PB5 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_sdi: i2s2m1-sdi { ++ rockchip,pins = ++ /* i2s2m1_sdi */ ++ <3 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m1_sdo: i2s2m1-sdo { ++ rockchip,pins = ++ /* i2s2m1_sdo */ ++ <3 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ i2s3 { ++ /omit-if-no-ref/ ++ i2s3_lrck: i2s3-lrck { ++ rockchip,pins = ++ /* i2s3_lrck */ ++ <3 RK_PA2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_mclk: i2s3-mclk { ++ rockchip,pins = ++ /* i2s3_mclk */ ++ <3 RK_PA0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_sclk: i2s3-sclk { ++ rockchip,pins = ++ /* i2s3_sclk */ ++ <3 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_sdi: i2s3-sdi { ++ rockchip,pins = ++ /* i2s3_sdi */ ++ <3 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s3_sdo: i2s3-sdo { ++ rockchip,pins = ++ /* i2s3_sdo */ ++ <3 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ jtag { ++ /omit-if-no-ref/ ++ jtagm0_pins: jtagm0-pins { ++ rockchip,pins = ++ /* jtag_tck_m0 */ ++ <4 RK_PD2 5 &pcfg_pull_none>, ++ /* jtag_tms_m0 */ ++ <4 RK_PD3 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ jtagm1_pins: jtagm1-pins { ++ rockchip,pins = ++ /* jtag_tck_m1 */ ++ <4 RK_PD0 5 &pcfg_pull_none>, ++ /* jtag_tms_m1 */ ++ <4 RK_PD1 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ jtagm2_pins: jtagm2-pins { ++ rockchip,pins = ++ /* jtag_tck_m2 */ ++ <0 RK_PB5 2 &pcfg_pull_none>, ++ /* jtag_tms_m2 */ ++ <0 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ litcpu { ++ /omit-if-no-ref/ ++ litcpu_pins: litcpu-pins { ++ rockchip,pins = ++ /* litcpu_avs */ ++ <0 RK_PD3 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ mcu { ++ /omit-if-no-ref/ ++ mcum0_pins: mcum0-pins { ++ rockchip,pins = ++ /* mcu_jtag_tck_m0 */ ++ <4 RK_PD4 5 &pcfg_pull_none>, ++ /* mcu_jtag_tms_m0 */ ++ <4 RK_PD5 5 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mcum1_pins: mcum1-pins { ++ rockchip,pins = ++ /* mcu_jtag_tck_m1 */ ++ <3 RK_PD4 6 &pcfg_pull_none>, ++ /* mcu_jtag_tms_m1 */ ++ <3 RK_PD5 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ mipi { ++ /omit-if-no-ref/ ++ mipim0_camera0_clk: mipim0-camera0-clk { ++ rockchip,pins = ++ /* mipim0_camera0_clk */ ++ <4 RK_PB1 1 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera1_clk: mipim0-camera1-clk { ++ rockchip,pins = ++ /* mipim0_camera1_clk */ ++ <1 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera2_clk: mipim0-camera2-clk { ++ rockchip,pins = ++ /* mipim0_camera2_clk */ ++ <1 RK_PB7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera3_clk: mipim0-camera3-clk { ++ rockchip,pins = ++ /* mipim0_camera3_clk */ ++ <1 RK_PD6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim0_camera4_clk: mipim0-camera4-clk { ++ rockchip,pins = ++ /* mipim0_camera4_clk */ ++ <1 RK_PD7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera0_clk: mipim1-camera0-clk { ++ rockchip,pins = ++ /* mipim1_camera0_clk */ ++ <3 RK_PA5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera1_clk: mipim1-camera1-clk { ++ rockchip,pins = ++ /* mipim1_camera1_clk */ ++ <3 RK_PA6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera2_clk: mipim1-camera2-clk { ++ rockchip,pins = ++ /* mipim1_camera2_clk */ ++ <3 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera3_clk: mipim1-camera3-clk { ++ rockchip,pins = ++ /* mipim1_camera3_clk */ ++ <3 RK_PB0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipim1_camera4_clk: mipim1-camera4-clk { ++ rockchip,pins = ++ /* mipim1_camera4_clk */ ++ <3 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipi_te0: mipi-te0 { ++ rockchip,pins = ++ /* mipi_te0 */ ++ <3 RK_PC2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ mipi_te1: mipi-te1 { ++ rockchip,pins = ++ /* mipi_te1 */ ++ <3 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ npu { ++ /omit-if-no-ref/ ++ npu_pins: npu-pins { ++ rockchip,pins = ++ /* npu_avs */ ++ <0 RK_PC6 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie20x1 { ++ /omit-if-no-ref/ ++ pcie20x1m0_pins: pcie20x1m0-pins { ++ rockchip,pins = ++ /* pcie20x1_2_clkreqn_m0 */ ++ <3 RK_PC7 4 &pcfg_pull_none>, ++ /* pcie20x1_2_perstn_m0 */ ++ <3 RK_PD1 4 &pcfg_pull_none>, ++ /* pcie20x1_2_waken_m0 */ ++ <3 RK_PD0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1m1_pins: pcie20x1m1-pins { ++ rockchip,pins = ++ /* pcie20x1_2_clkreqn_m1 */ ++ <4 RK_PB7 4 &pcfg_pull_none>, ++ /* pcie20x1_2_perstn_m1 */ ++ <4 RK_PC1 4 &pcfg_pull_none>, ++ /* pcie20x1_2_waken_m1 */ ++ <4 RK_PC0 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { ++ rockchip,pins = ++ /* pcie20x1_2_button_rstn */ ++ <4 RK_PB3 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30phy { ++ /omit-if-no-ref/ ++ pcie30phy_pins: pcie30phy-pins { ++ rockchip,pins = ++ /* pcie30phy_dtb0 */ ++ <1 RK_PC4 4 &pcfg_pull_none>, ++ /* pcie30phy_dtb1 */ ++ <1 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x1 { ++ /omit-if-no-ref/ ++ pcie30x1m0_pins: pcie30x1m0-pins { ++ rockchip,pins = ++ /* pcie30x1_0_clkreqn_m0 */ ++ <0 RK_PC0 12 &pcfg_pull_none>, ++ /* pcie30x1_0_perstn_m0 */ ++ <0 RK_PC5 12 &pcfg_pull_none>, ++ /* pcie30x1_0_waken_m0 */ ++ <0 RK_PC4 12 &pcfg_pull_none>, ++ /* pcie30x1_1_clkreqn_m0 */ ++ <0 RK_PB5 12 &pcfg_pull_none>, ++ /* pcie30x1_1_perstn_m0 */ ++ <0 RK_PB7 12 &pcfg_pull_none>, ++ /* pcie30x1_1_waken_m0 */ ++ <0 RK_PB6 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m1_pins: pcie30x1m1-pins { ++ rockchip,pins = ++ /* pcie30x1_0_clkreqn_m1 */ ++ <4 RK_PA3 4 &pcfg_pull_none>, ++ /* pcie30x1_0_perstn_m1 */ ++ <4 RK_PA5 4 &pcfg_pull_none>, ++ /* pcie30x1_0_waken_m1 */ ++ <4 RK_PA4 4 &pcfg_pull_none>, ++ /* pcie30x1_1_clkreqn_m1 */ ++ <4 RK_PA0 4 &pcfg_pull_none>, ++ /* pcie30x1_1_perstn_m1 */ ++ <4 RK_PA2 4 &pcfg_pull_none>, ++ /* pcie30x1_1_waken_m1 */ ++ <4 RK_PA1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1m2_pins: pcie30x1m2-pins { ++ rockchip,pins = ++ /* pcie30x1_0_clkreqn_m2 */ ++ <1 RK_PB5 4 &pcfg_pull_none>, ++ /* pcie30x1_0_perstn_m2 */ ++ <1 RK_PB4 4 &pcfg_pull_none>, ++ /* pcie30x1_0_waken_m2 */ ++ <1 RK_PB3 4 &pcfg_pull_none>, ++ /* pcie30x1_1_clkreqn_m2 */ ++ <1 RK_PA0 4 &pcfg_pull_none>, ++ /* pcie30x1_1_perstn_m2 */ ++ <1 RK_PA7 4 &pcfg_pull_none>, ++ /* pcie30x1_1_waken_m2 */ ++ <1 RK_PA1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { ++ rockchip,pins = ++ /* pcie30x1_0_button_rstn */ ++ <4 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { ++ rockchip,pins = ++ /* pcie30x1_1_button_rstn */ ++ <4 RK_PB2 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x2 { ++ /omit-if-no-ref/ ++ pcie30x2m0_pins: pcie30x2m0-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m0 */ ++ <0 RK_PD1 12 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m0 */ ++ <0 RK_PD4 12 &pcfg_pull_none>, ++ /* pcie30x2_waken_m0 */ ++ <0 RK_PD2 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m1_pins: pcie30x2m1-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m1 */ ++ <4 RK_PA6 4 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m1 */ ++ <4 RK_PB0 4 &pcfg_pull_none>, ++ /* pcie30x2_waken_m1 */ ++ <4 RK_PA7 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m2_pins: pcie30x2m2-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m2 */ ++ <3 RK_PD2 4 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m2 */ ++ <3 RK_PD4 4 &pcfg_pull_none>, ++ /* pcie30x2_waken_m2 */ ++ <3 RK_PD3 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2m3_pins: pcie30x2m3-pins { ++ rockchip,pins = ++ /* pcie30x2_clkreqn_m3 */ ++ <1 RK_PD7 4 &pcfg_pull_none>, ++ /* pcie30x2_perstn_m3 */ ++ <1 RK_PB7 4 &pcfg_pull_none>, ++ /* pcie30x2_waken_m3 */ ++ <1 RK_PB6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x2_button_rstn: pcie30x2-button-rstn { ++ rockchip,pins = ++ /* pcie30x2_button_rstn */ ++ <3 RK_PC1 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie30x4 { ++ /omit-if-no-ref/ ++ pcie30x4m0_pins: pcie30x4m0-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m0 */ ++ <0 RK_PC6 12 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m0 */ ++ <0 RK_PD0 12 &pcfg_pull_none>, ++ /* pcie30x4_waken_m0 */ ++ <0 RK_PC7 12 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m1_pins: pcie30x4m1-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m1 */ ++ <4 RK_PB4 4 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m1 */ ++ <4 RK_PB6 4 &pcfg_pull_none>, ++ /* pcie30x4_waken_m1 */ ++ <4 RK_PB5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m2_pins: pcie30x4m2-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m2 */ ++ <3 RK_PC4 4 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m2 */ ++ <3 RK_PC6 4 &pcfg_pull_none>, ++ /* pcie30x4_waken_m2 */ ++ <3 RK_PC5 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4m3_pins: pcie30x4m3-pins { ++ rockchip,pins = ++ /* pcie30x4_clkreqn_m3 */ ++ <1 RK_PB0 4 &pcfg_pull_none>, ++ /* pcie30x4_perstn_m3 */ ++ <1 RK_PB2 4 &pcfg_pull_none>, ++ /* pcie30x4_waken_m3 */ ++ <1 RK_PB1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4_button_rstn: pcie30x4-button-rstn { ++ rockchip,pins = ++ /* pcie30x4_button_rstn */ ++ <3 RK_PD5 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pdm0 { ++ /omit-if-no-ref/ ++ pdm0m0_clk: pdm0m0-clk { ++ rockchip,pins = ++ /* pdm0_clk0_m0 */ ++ <1 RK_PC6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_clk1: pdm0m0-clk1 { ++ rockchip,pins = ++ /* pdm0m0_clk1 */ ++ <1 RK_PC4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi0: pdm0m0-sdi0 { ++ rockchip,pins = ++ /* pdm0m0_sdi0 */ ++ <1 RK_PD5 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi1: pdm0m0-sdi1 { ++ rockchip,pins = ++ /* pdm0m0_sdi1 */ ++ <1 RK_PD1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi2: pdm0m0-sdi2 { ++ rockchip,pins = ++ /* pdm0m0_sdi2 */ ++ <1 RK_PD2 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m0_sdi3: pdm0m0-sdi3 { ++ rockchip,pins = ++ /* pdm0m0_sdi3 */ ++ <1 RK_PD3 3 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ pdm0m1_clk: pdm0m1-clk { ++ rockchip,pins = ++ /* pdm0_clk0_m1 */ ++ <0 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_clk1: pdm0m1-clk1 { ++ rockchip,pins = ++ /* pdm0m1_clk1 */ ++ <0 RK_PC4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi0: pdm0m1-sdi0 { ++ rockchip,pins = ++ /* pdm0m1_sdi0 */ ++ <0 RK_PC7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi1: pdm0m1-sdi1 { ++ rockchip,pins = ++ /* pdm0m1_sdi1 */ ++ <0 RK_PD0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi2: pdm0m1-sdi2 { ++ rockchip,pins = ++ /* pdm0m1_sdi2 */ ++ <0 RK_PD4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm0m1_sdi3: pdm0m1-sdi3 { ++ rockchip,pins = ++ /* pdm0m1_sdi3 */ ++ <0 RK_PD6 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pdm1 { ++ /omit-if-no-ref/ ++ pdm1m0_clk: pdm1m0-clk { ++ rockchip,pins = ++ /* pdm1_clk0_m0 */ ++ <4 RK_PD5 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_clk1: pdm1m0-clk1 { ++ rockchip,pins = ++ /* pdm1m0_clk1 */ ++ <4 RK_PD4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi0: pdm1m0-sdi0 { ++ rockchip,pins = ++ /* pdm1m0_sdi0 */ ++ <4 RK_PD3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi1: pdm1m0-sdi1 { ++ rockchip,pins = ++ /* pdm1m0_sdi1 */ ++ <4 RK_PD2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi2: pdm1m0-sdi2 { ++ rockchip,pins = ++ /* pdm1m0_sdi2 */ ++ <4 RK_PD1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m0_sdi3: pdm1m0-sdi3 { ++ rockchip,pins = ++ /* pdm1m0_sdi3 */ ++ <4 RK_PD0 2 &pcfg_pull_none>; ++ }; ++ /omit-if-no-ref/ ++ pdm1m1_clk: pdm1m1-clk { ++ rockchip,pins = ++ /* pdm1_clk0_m1 */ ++ <1 RK_PB4 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_clk1: pdm1m1-clk1 { ++ rockchip,pins = ++ /* pdm1m1_clk1 */ ++ <1 RK_PB3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi0: pdm1m1-sdi0 { ++ rockchip,pins = ++ /* pdm1m1_sdi0 */ ++ <1 RK_PA7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi1: pdm1m1-sdi1 { ++ rockchip,pins = ++ /* pdm1m1_sdi1 */ ++ <1 RK_PB0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi2: pdm1m1-sdi2 { ++ rockchip,pins = ++ /* pdm1m1_sdi2 */ ++ <1 RK_PB1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pdm1m1_sdi3: pdm1m1-sdi3 { ++ rockchip,pins = ++ /* pdm1m1_sdi3 */ ++ <1 RK_PB2 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ /omit-if-no-ref/ ++ pmic_pins: pmic-pins { ++ rockchip,pins = ++ /* pmic_int_l */ ++ <0 RK_PA7 0 &pcfg_pull_up>, ++ /* pmic_sleep1 */ ++ <0 RK_PA2 1 &pcfg_pull_none>, ++ /* pmic_sleep2 */ ++ <0 RK_PA3 1 &pcfg_pull_none>, ++ /* pmic_sleep3 */ ++ <0 RK_PC1 1 &pcfg_pull_none>, ++ /* pmic_sleep4 */ ++ <0 RK_PC2 1 &pcfg_pull_none>, ++ /* pmic_sleep5 */ ++ <0 RK_PC3 1 &pcfg_pull_none>, ++ /* pmic_sleep6 */ ++ <0 RK_PD6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmu { ++ /omit-if-no-ref/ ++ pmu_pins: pmu-pins { ++ rockchip,pins = ++ /* pmu_debug */ ++ <0 RK_PA5 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm0 { ++ /omit-if-no-ref/ ++ pwm0m0_pins: pwm0m0-pins { ++ rockchip,pins = ++ /* pwm0_m0 */ ++ <0 RK_PB7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m1_pins: pwm0m1-pins { ++ rockchip,pins = ++ /* pwm0_m1 */ ++ <1 RK_PD2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0m2_pins: pwm0m2-pins { ++ rockchip,pins = ++ /* pwm0_m2 */ ++ <1 RK_PA2 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm1 { ++ /omit-if-no-ref/ ++ pwm1m0_pins: pwm1m0-pins { ++ rockchip,pins = ++ /* pwm1_m0 */ ++ <0 RK_PC0 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m1_pins: pwm1m1-pins { ++ rockchip,pins = ++ /* pwm1_m1 */ ++ <1 RK_PD3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1m2_pins: pwm1m2-pins { ++ rockchip,pins = ++ /* pwm1_m2 */ ++ <1 RK_PA3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm2 { ++ /omit-if-no-ref/ ++ pwm2m0_pins: pwm2m0-pins { ++ rockchip,pins = ++ /* pwm2_m0 */ ++ <0 RK_PC4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2m1_pins: pwm2m1-pins { ++ rockchip,pins = ++ /* pwm2_m1 */ ++ <3 RK_PB1 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm3 { ++ /omit-if-no-ref/ ++ pwm3m0_pins: pwm3m0-pins { ++ rockchip,pins = ++ /* pwm3_ir_m0 */ ++ <0 RK_PD4 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3m1_pins: pwm3m1-pins { ++ rockchip,pins = ++ /* pwm3_ir_m1 */ ++ <3 RK_PB2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3m2_pins: pwm3m2-pins { ++ rockchip,pins = ++ /* pwm3_ir_m2 */ ++ <1 RK_PC2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3m3_pins: pwm3m3-pins { ++ rockchip,pins = ++ /* pwm3_ir_m3 */ ++ <1 RK_PA7 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm4 { ++ /omit-if-no-ref/ ++ pwm4m0_pins: pwm4m0-pins { ++ rockchip,pins = ++ /* pwm4_m0 */ ++ <0 RK_PC5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm5 { ++ /omit-if-no-ref/ ++ pwm5m0_pins: pwm5m0-pins { ++ rockchip,pins = ++ /* pwm5_m0 */ ++ <0 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5m1_pins: pwm5m1-pins { ++ rockchip,pins = ++ /* pwm5_m1 */ ++ <0 RK_PC6 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm6 { ++ /omit-if-no-ref/ ++ pwm6m0_pins: pwm6m0-pins { ++ rockchip,pins = ++ /* pwm6_m0 */ ++ <0 RK_PC7 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6m1_pins: pwm6m1-pins { ++ rockchip,pins = ++ /* pwm6_m1 */ ++ <4 RK_PC1 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm7 { ++ /omit-if-no-ref/ ++ pwm7m0_pins: pwm7m0-pins { ++ rockchip,pins = ++ /* pwm7_ir_m0 */ ++ <0 RK_PD0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7m1_pins: pwm7m1-pins { ++ rockchip,pins = ++ /* pwm7_ir_m1 */ ++ <4 RK_PD4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7m2_pins: pwm7m2-pins { ++ rockchip,pins = ++ /* pwm7_ir_m2 */ ++ <1 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm8 { ++ /omit-if-no-ref/ ++ pwm8m0_pins: pwm8m0-pins { ++ rockchip,pins = ++ /* pwm8_m0 */ ++ <3 RK_PA7 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8m1_pins: pwm8m1-pins { ++ rockchip,pins = ++ /* pwm8_m1 */ ++ <4 RK_PD0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8m2_pins: pwm8m2-pins { ++ rockchip,pins = ++ /* pwm8_m2 */ ++ <3 RK_PD0 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm9 { ++ /omit-if-no-ref/ ++ pwm9m0_pins: pwm9m0-pins { ++ rockchip,pins = ++ /* pwm9_m0 */ ++ <3 RK_PB0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9m1_pins: pwm9m1-pins { ++ rockchip,pins = ++ /* pwm9_m1 */ ++ <4 RK_PD1 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9m2_pins: pwm9m2-pins { ++ rockchip,pins = ++ /* pwm9_m2 */ ++ <3 RK_PD1 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm10 { ++ /omit-if-no-ref/ ++ pwm10m0_pins: pwm10m0-pins { ++ rockchip,pins = ++ /* pwm10_m0 */ ++ <3 RK_PA0 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10m1_pins: pwm10m1-pins { ++ rockchip,pins = ++ /* pwm10_m1 */ ++ <4 RK_PD3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10m2_pins: pwm10m2-pins { ++ rockchip,pins = ++ /* pwm10_m2 */ ++ <3 RK_PD3 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm11 { ++ /omit-if-no-ref/ ++ pwm11m0_pins: pwm11m0-pins { ++ rockchip,pins = ++ /* pwm11_ir_m0 */ ++ <3 RK_PA1 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11m1_pins: pwm11m1-pins { ++ rockchip,pins = ++ /* pwm11_ir_m1 */ ++ <4 RK_PB4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11m2_pins: pwm11m2-pins { ++ rockchip,pins = ++ /* pwm11_ir_m2 */ ++ <1 RK_PC4 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11m3_pins: pwm11m3-pins { ++ rockchip,pins = ++ /* pwm11_ir_m3 */ ++ <3 RK_PD5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm12 { ++ /omit-if-no-ref/ ++ pwm12m0_pins: pwm12m0-pins { ++ rockchip,pins = ++ /* pwm12_m0 */ ++ <3 RK_PB5 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12m1_pins: pwm12m1-pins { ++ rockchip,pins = ++ /* pwm12_m1 */ ++ <4 RK_PB5 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm13 { ++ /omit-if-no-ref/ ++ pwm13m0_pins: pwm13m0-pins { ++ rockchip,pins = ++ /* pwm13_m0 */ ++ <3 RK_PB6 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13m1_pins: pwm13m1-pins { ++ rockchip,pins = ++ /* pwm13_m1 */ ++ <4 RK_PB6 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13m2_pins: pwm13m2-pins { ++ rockchip,pins = ++ /* pwm13_m2 */ ++ <1 RK_PB7 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm14 { ++ /omit-if-no-ref/ ++ pwm14m0_pins: pwm14m0-pins { ++ rockchip,pins = ++ /* pwm14_m0 */ ++ <3 RK_PC2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14m1_pins: pwm14m1-pins { ++ rockchip,pins = ++ /* pwm14_m1 */ ++ <4 RK_PB2 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14m2_pins: pwm14m2-pins { ++ rockchip,pins = ++ /* pwm14_m2 */ ++ <1 RK_PD6 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pwm15 { ++ /omit-if-no-ref/ ++ pwm15m0_pins: pwm15m0-pins { ++ rockchip,pins = ++ /* pwm15_ir_m0 */ ++ <3 RK_PC3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15m1_pins: pwm15m1-pins { ++ rockchip,pins = ++ /* pwm15_ir_m1 */ ++ <4 RK_PB3 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15m2_pins: pwm15m2-pins { ++ rockchip,pins = ++ /* pwm15_ir_m2 */ ++ <1 RK_PC6 11 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15m3_pins: pwm15m3-pins { ++ rockchip,pins = ++ /* pwm15_ir_m3 */ ++ <1 RK_PD7 11 &pcfg_pull_none>; ++ }; ++ }; ++ ++ refclk { ++ /omit-if-no-ref/ ++ refclk_pins: refclk-pins { ++ rockchip,pins = ++ /* refclk_out */ ++ <0 RK_PA0 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata { ++ /omit-if-no-ref/ ++ sata_pins: sata-pins { ++ rockchip,pins = ++ /* sata_cp_pod */ ++ <0 RK_PC6 13 &pcfg_pull_none>, ++ /* sata_cpdet */ ++ <0 RK_PD4 13 &pcfg_pull_none>, ++ /* sata_mp_switch */ ++ <0 RK_PD5 13 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata0 { ++ /omit-if-no-ref/ ++ sata0m0_pins: sata0m0-pins { ++ rockchip,pins = ++ /* sata0_act_led_m0 */ ++ <4 RK_PB6 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata0m1_pins: sata0m1-pins { ++ rockchip,pins = ++ /* sata0_act_led_m1 */ ++ <1 RK_PB3 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata1 { ++ /omit-if-no-ref/ ++ sata1m0_pins: sata1m0-pins { ++ rockchip,pins = ++ /* sata1_act_led_m0 */ ++ <4 RK_PB5 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata1m1_pins: sata1m1-pins { ++ rockchip,pins = ++ /* sata1_act_led_m1 */ ++ <1 RK_PA1 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sata2 { ++ /omit-if-no-ref/ ++ sata2m0_pins: sata2m0-pins { ++ rockchip,pins = ++ /* sata2_act_led_m0 */ ++ <4 RK_PB1 6 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ sata2m1_pins: sata2m1-pins { ++ rockchip,pins = ++ /* sata2_act_led_m1 */ ++ <1 RK_PB7 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdio { ++ /omit-if-no-ref/ ++ sdiom1_pins: sdiom1-pins { ++ rockchip,pins = ++ /* sdio_clk_m1 */ ++ <3 RK_PA5 2 &pcfg_pull_none>, ++ /* sdio_cmd_m1 */ ++ <3 RK_PA4 2 &pcfg_pull_none>, ++ /* sdio_d0_m1 */ ++ <3 RK_PA0 2 &pcfg_pull_none>, ++ /* sdio_d1_m1 */ ++ <3 RK_PA1 2 &pcfg_pull_none>, ++ /* sdio_d2_m1 */ ++ <3 RK_PA2 2 &pcfg_pull_none>, ++ /* sdio_d3_m1 */ ++ <3 RK_PA3 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc { ++ /omit-if-no-ref/ ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = ++ /* sdmmc_d0 */ ++ <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc_d1 */ ++ <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc_d2 */ ++ <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, ++ /* sdmmc_d3 */ ++ <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = ++ /* sdmmc_clk */ ++ <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = ++ /* sdmmc_cmd */ ++ <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_det: sdmmc-det { ++ rockchip,pins = ++ /* sdmmc_det */ ++ <0 RK_PA4 1 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ sdmmc_pwren: sdmmc-pwren { ++ rockchip,pins = ++ /* sdmmc_pwren */ ++ <0 RK_PA5 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spdif0 { ++ /omit-if-no-ref/ ++ spdif0m0_tx: spdif0m0-tx { ++ rockchip,pins = ++ /* spdif0m0_tx */ ++ <1 RK_PB6 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdif0m1_tx: spdif0m1-tx { ++ rockchip,pins = ++ /* spdif0m1_tx */ ++ <4 RK_PB4 6 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spdif1 { ++ /omit-if-no-ref/ ++ spdif1m0_tx: spdif1m0-tx { ++ rockchip,pins = ++ /* spdif1m0_tx */ ++ <1 RK_PB7 3 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdif1m1_tx: spdif1m1-tx { ++ rockchip,pins = ++ /* spdif1m1_tx */ ++ <4 RK_PB1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ spdif1m2_tx: spdif1m2-tx { ++ rockchip,pins = ++ /* spdif1m2_tx */ ++ <4 RK_PC1 3 &pcfg_pull_none>; ++ }; ++ }; ++ ++ spi0 { ++ /omit-if-no-ref/ ++ spi0m0_pins: spi0m0-pins { ++ rockchip,pins = ++ /* spi0_clk_m0 */ ++ <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m0 */ ++ <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m0 */ ++ <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m0_cs0: spi0m0-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m0 */ ++ <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m0_cs1: spi0m0-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m0 */ ++ <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ /omit-if-no-ref/ ++ spi0m1_pins: spi0m1-pins { ++ rockchip,pins = ++ /* spi0_clk_m1 */ ++ <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m1 */ ++ <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m1 */ ++ <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m1_cs0: spi0m1-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m1 */ ++ <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m1_cs1: spi0m1-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m1 */ ++ <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ /omit-if-no-ref/ ++ spi0m2_pins: spi0m2-pins { ++ rockchip,pins = ++ /* spi0_clk_m2 */ ++ <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m2 */ ++ <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m2 */ ++ <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m2_cs0: spi0m2-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m2 */ ++ <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m2_cs1: spi0m2-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m2 */ ++ <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ /omit-if-no-ref/ ++ spi0m3_pins: spi0m3-pins { ++ rockchip,pins = ++ /* spi0_clk_m3 */ ++ <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_miso_m3 */ ++ <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi0_mosi_m3 */ ++ <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m3_cs0: spi0m3-cs0 { ++ rockchip,pins = ++ /* spi0_cs0_m3 */ ++ <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi0m3_cs1: spi0m3-cs1 { ++ rockchip,pins = ++ /* spi0_cs1_m3 */ ++ <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi1 { ++ /omit-if-no-ref/ ++ spi1m1_pins: spi1m1-pins { ++ rockchip,pins = ++ /* spi1_clk_m1 */ ++ <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_miso_m1 */ ++ <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_mosi_m1 */ ++ <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m1_cs0: spi1m1-cs0 { ++ rockchip,pins = ++ /* spi1_cs0_m1 */ ++ <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m1_cs1: spi1m1-cs1 { ++ rockchip,pins = ++ /* spi1_cs1_m1 */ ++ <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_pins: spi1m2-pins { ++ rockchip,pins = ++ /* spi1_clk_m2 */ ++ <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_miso_m2 */ ++ <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi1_mosi_m2 */ ++ <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_cs0: spi1m2-cs0 { ++ rockchip,pins = ++ /* spi1_cs0_m2 */ ++ <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi1m2_cs1: spi1m2-cs1 { ++ rockchip,pins = ++ /* spi1_cs1_m2 */ ++ <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi2 { ++ /omit-if-no-ref/ ++ spi2m0_pins: spi2m0-pins { ++ rockchip,pins = ++ /* spi2_clk_m0 */ ++ <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_miso_m0 */ ++ <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_mosi_m0 */ ++ <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m0_cs0: spi2m0-cs0 { ++ rockchip,pins = ++ /* spi2_cs0_m0 */ ++ <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m0_cs1: spi2m0-cs1 { ++ rockchip,pins = ++ /* spi2_cs1_m0 */ ++ <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_pins: spi2m1-pins { ++ rockchip,pins = ++ /* spi2_clk_m1 */ ++ <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_miso_m1 */ ++ <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, ++ /* spi2_mosi_m1 */ ++ <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_cs0: spi2m1-cs0 { ++ rockchip,pins = ++ /* spi2_cs0_m1 */ ++ <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m1_cs1: spi2m1-cs1 { ++ rockchip,pins = ++ /* spi2_cs1_m1 */ ++ <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_pins: spi2m2-pins { ++ rockchip,pins = ++ /* spi2_clk_m2 */ ++ <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, ++ /* spi2_miso_m2 */ ++ <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, ++ /* spi2_mosi_m2 */ ++ <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_cs0: spi2m2-cs0 { ++ rockchip,pins = ++ /* spi2_cs0_m2 */ ++ <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi2m2_cs1: spi2m2-cs1 { ++ rockchip,pins = ++ /* spi2_cs1_m2 */ ++ <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi3 { ++ /omit-if-no-ref/ ++ spi3m1_pins: spi3m1-pins { ++ rockchip,pins = ++ /* spi3_clk_m1 */ ++ <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m1 */ ++ <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m1 */ ++ <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m1_cs0: spi3m1-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m1 */ ++ <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m1_cs1: spi3m1-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m1 */ ++ <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_pins: spi3m2-pins { ++ rockchip,pins = ++ /* spi3_clk_m2 */ ++ <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m2 */ ++ <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m2 */ ++ <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_cs0: spi3m2-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m2 */ ++ <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m2_cs1: spi3m2-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m2 */ ++ <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m3_pins: spi3m3-pins { ++ rockchip,pins = ++ /* spi3_clk_m3 */ ++ <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_miso_m3 */ ++ <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, ++ /* spi3_mosi_m3 */ ++ <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m3_cs0: spi3m3-cs0 { ++ rockchip,pins = ++ /* spi3_cs0_m3 */ ++ <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi3m3_cs1: spi3m3-cs1 { ++ rockchip,pins = ++ /* spi3_cs1_m3 */ ++ <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ spi4 { ++ /omit-if-no-ref/ ++ spi4m0_pins: spi4m0-pins { ++ rockchip,pins = ++ /* spi4_clk_m0 */ ++ <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_miso_m0 */ ++ <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_mosi_m0 */ ++ <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m0_cs0: spi4m0-cs0 { ++ rockchip,pins = ++ /* spi4_cs0_m0 */ ++ <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m0_cs1: spi4m0-cs1 { ++ rockchip,pins = ++ /* spi4_cs1_m0 */ ++ <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_pins: spi4m1-pins { ++ rockchip,pins = ++ /* spi4_clk_m1 */ ++ <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_miso_m1 */ ++ <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_mosi_m1 */ ++ <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_cs0: spi4m1-cs0 { ++ rockchip,pins = ++ /* spi4_cs0_m1 */ ++ <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m1_cs1: spi4m1-cs1 { ++ rockchip,pins = ++ /* spi4_cs1_m1 */ ++ <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m2_pins: spi4m2-pins { ++ rockchip,pins = ++ /* spi4_clk_m2 */ ++ <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_miso_m2 */ ++ <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, ++ /* spi4_mosi_m2 */ ++ <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ ++ /omit-if-no-ref/ ++ spi4m2_cs0: spi4m2-cs0 { ++ rockchip,pins = ++ /* spi4_cs0_m2 */ ++ <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; ++ }; ++ }; ++ ++ tsadc { ++ /omit-if-no-ref/ ++ tsadcm1_shut: tsadcm1-shut { ++ rockchip,pins = ++ /* tsadcm1_shut */ ++ <0 RK_PA2 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ tsadc_shut: tsadc-shut { ++ rockchip,pins = ++ /* tsadc_shut */ ++ <0 RK_PA1 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ tsadc_shut_org: tsadc-shut-org { ++ rockchip,pins = ++ /* tsadc_shut_org */ ++ <0 RK_PA1 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart0 { ++ /omit-if-no-ref/ ++ uart0m0_xfer: uart0m0-xfer { ++ rockchip,pins = ++ /* uart0_rx_m0 */ ++ <0 RK_PC4 4 &pcfg_pull_up>, ++ /* uart0_tx_m0 */ ++ <0 RK_PC5 4 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0m1_xfer: uart0m1-xfer { ++ rockchip,pins = ++ /* uart0_rx_m1 */ ++ <0 RK_PB0 4 &pcfg_pull_up>, ++ /* uart0_tx_m1 */ ++ <0 RK_PB1 4 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0m2_xfer: uart0m2-xfer { ++ rockchip,pins = ++ /* uart0_rx_m2 */ ++ <4 RK_PA4 10 &pcfg_pull_up>, ++ /* uart0_tx_m2 */ ++ <4 RK_PA3 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0_ctsn: uart0-ctsn { ++ rockchip,pins = ++ /* uart0_ctsn */ ++ <0 RK_PD1 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0_rtsn: uart0-rtsn { ++ rockchip,pins = ++ /* uart0_rtsn */ ++ <0 RK_PC6 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart1 { ++ /omit-if-no-ref/ ++ uart1m1_xfer: uart1m1-xfer { ++ rockchip,pins = ++ /* uart1_rx_m1 */ ++ <1 RK_PB7 10 &pcfg_pull_up>, ++ /* uart1_tx_m1 */ ++ <1 RK_PB6 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m1_ctsn: uart1m1-ctsn { ++ rockchip,pins = ++ /* uart1m1_ctsn */ ++ <1 RK_PD7 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m1_rtsn: uart1m1-rtsn { ++ rockchip,pins = ++ /* uart1m1_rtsn */ ++ <1 RK_PD6 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_xfer: uart1m2-xfer { ++ rockchip,pins = ++ /* uart1_rx_m2 */ ++ <0 RK_PD2 10 &pcfg_pull_up>, ++ /* uart1_tx_m2 */ ++ <0 RK_PD1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_ctsn: uart1m2-ctsn { ++ rockchip,pins = ++ /* uart1m2_ctsn */ ++ <0 RK_PD0 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart1m2_rtsn: uart1m2-rtsn { ++ rockchip,pins = ++ /* uart1m2_rtsn */ ++ <0 RK_PC7 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart2 { ++ /omit-if-no-ref/ ++ uart2m0_xfer: uart2m0-xfer { ++ rockchip,pins = ++ /* uart2_rx_m0 */ ++ <0 RK_PB6 10 &pcfg_pull_up>, ++ /* uart2_tx_m0 */ ++ <0 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m1_xfer: uart2m1-xfer { ++ rockchip,pins = ++ /* uart2_rx_m1 */ ++ <4 RK_PD1 10 &pcfg_pull_up>, ++ /* uart2_tx_m1 */ ++ <4 RK_PD0 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2m2_xfer: uart2m2-xfer { ++ rockchip,pins = ++ /* uart2_rx_m2 */ ++ <3 RK_PB2 10 &pcfg_pull_up>, ++ /* uart2_tx_m2 */ ++ <3 RK_PB1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_ctsn: uart2-ctsn { ++ rockchip,pins = ++ /* uart2_ctsn */ ++ <3 RK_PB4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_rtsn: uart2-rtsn { ++ rockchip,pins = ++ /* uart2_rtsn */ ++ <3 RK_PB3 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart3 { ++ /omit-if-no-ref/ ++ uart3m0_xfer: uart3m0-xfer { ++ rockchip,pins = ++ /* uart3_rx_m0 */ ++ <1 RK_PC0 10 &pcfg_pull_up>, ++ /* uart3_tx_m0 */ ++ <1 RK_PC1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m1_xfer: uart3m1-xfer { ++ rockchip,pins = ++ /* uart3_rx_m1 */ ++ <3 RK_PB6 10 &pcfg_pull_up>, ++ /* uart3_tx_m1 */ ++ <3 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3m2_xfer: uart3m2-xfer { ++ rockchip,pins = ++ /* uart3_rx_m2 */ ++ <4 RK_PA6 10 &pcfg_pull_up>, ++ /* uart3_tx_m2 */ ++ <4 RK_PA5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_ctsn: uart3-ctsn { ++ rockchip,pins = ++ /* uart3_ctsn */ ++ <1 RK_PC3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_rtsn: uart3-rtsn { ++ rockchip,pins = ++ /* uart3_rtsn */ ++ <1 RK_PC2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart4 { ++ /omit-if-no-ref/ ++ uart4m0_xfer: uart4m0-xfer { ++ rockchip,pins = ++ /* uart4_rx_m0 */ ++ <1 RK_PD3 10 &pcfg_pull_up>, ++ /* uart4_tx_m0 */ ++ <1 RK_PD2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m1_xfer: uart4m1-xfer { ++ rockchip,pins = ++ /* uart4_rx_m1 */ ++ <3 RK_PD0 10 &pcfg_pull_up>, ++ /* uart4_tx_m1 */ ++ <3 RK_PD1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4m2_xfer: uart4m2-xfer { ++ rockchip,pins = ++ /* uart4_rx_m2 */ ++ <1 RK_PB2 10 &pcfg_pull_up>, ++ /* uart4_tx_m2 */ ++ <1 RK_PB3 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_ctsn: uart4-ctsn { ++ rockchip,pins = ++ /* uart4_ctsn */ ++ <1 RK_PC7 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_rtsn: uart4-rtsn { ++ rockchip,pins = ++ /* uart4_rtsn */ ++ <1 RK_PC5 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ uart5 { ++ /omit-if-no-ref/ ++ uart5m0_xfer: uart5m0-xfer { ++ rockchip,pins = ++ /* uart5_rx_m0 */ ++ <4 RK_PD4 10 &pcfg_pull_up>, ++ /* uart5_tx_m0 */ ++ <4 RK_PD5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m0_ctsn: uart5m0-ctsn { ++ rockchip,pins = ++ /* uart5m0_ctsn */ ++ <4 RK_PD2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m0_rtsn: uart5m0-rtsn { ++ rockchip,pins = ++ /* uart5m0_rtsn */ ++ <4 RK_PD3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_xfer: uart5m1-xfer { ++ rockchip,pins = ++ /* uart5_rx_m1 */ ++ <3 RK_PC5 10 &pcfg_pull_up>, ++ /* uart5_tx_m1 */ ++ <3 RK_PC4 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_ctsn: uart5m1-ctsn { ++ rockchip,pins = ++ /* uart5m1_ctsn */ ++ <2 RK_PA2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m1_rtsn: uart5m1-rtsn { ++ rockchip,pins = ++ /* uart5m1_rtsn */ ++ <2 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5m2_xfer: uart5m2-xfer { ++ rockchip,pins = ++ /* uart5_rx_m2 */ ++ <2 RK_PD4 10 &pcfg_pull_up>, ++ /* uart5_tx_m2 */ ++ <2 RK_PD5 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart6 { ++ /omit-if-no-ref/ ++ uart6m1_xfer: uart6m1-xfer { ++ rockchip,pins = ++ /* uart6_rx_m1 */ ++ <1 RK_PA0 10 &pcfg_pull_up>, ++ /* uart6_tx_m1 */ ++ <1 RK_PA1 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m1_ctsn: uart6m1-ctsn { ++ rockchip,pins = ++ /* uart6m1_ctsn */ ++ <1 RK_PA3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m1_rtsn: uart6m1-rtsn { ++ rockchip,pins = ++ /* uart6m1_rtsn */ ++ <1 RK_PA2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6m2_xfer: uart6m2-xfer { ++ rockchip,pins = ++ /* uart6_rx_m2 */ ++ <1 RK_PD1 10 &pcfg_pull_up>, ++ /* uart6_tx_m2 */ ++ <1 RK_PD0 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart7 { ++ /omit-if-no-ref/ ++ uart7m1_xfer: uart7m1-xfer { ++ rockchip,pins = ++ /* uart7_rx_m1 */ ++ <3 RK_PC1 10 &pcfg_pull_up>, ++ /* uart7_tx_m1 */ ++ <3 RK_PC0 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m1_ctsn: uart7m1-ctsn { ++ rockchip,pins = ++ /* uart7m1_ctsn */ ++ <3 RK_PC3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m1_rtsn: uart7m1-rtsn { ++ rockchip,pins = ++ /* uart7m1_rtsn */ ++ <3 RK_PC2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7m2_xfer: uart7m2-xfer { ++ rockchip,pins = ++ /* uart7_rx_m2 */ ++ <1 RK_PB4 10 &pcfg_pull_up>, ++ /* uart7_tx_m2 */ ++ <1 RK_PB5 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart8 { ++ /omit-if-no-ref/ ++ uart8m0_xfer: uart8m0-xfer { ++ rockchip,pins = ++ /* uart8_rx_m0 */ ++ <4 RK_PB1 10 &pcfg_pull_up>, ++ /* uart8_tx_m0 */ ++ <4 RK_PB0 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m0_ctsn: uart8m0-ctsn { ++ rockchip,pins = ++ /* uart8m0_ctsn */ ++ <4 RK_PB3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m0_rtsn: uart8m0-rtsn { ++ rockchip,pins = ++ /* uart8m0_rtsn */ ++ <4 RK_PB2 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_xfer: uart8m1-xfer { ++ rockchip,pins = ++ /* uart8_rx_m1 */ ++ <3 RK_PA3 10 &pcfg_pull_up>, ++ /* uart8_tx_m1 */ ++ <3 RK_PA2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_ctsn: uart8m1-ctsn { ++ rockchip,pins = ++ /* uart8m1_ctsn */ ++ <3 RK_PA5 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8m1_rtsn: uart8m1-rtsn { ++ rockchip,pins = ++ /* uart8m1_rtsn */ ++ <3 RK_PA4 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8_xfer: uart8-xfer { ++ rockchip,pins = ++ /* uart8_rx_ */ ++ <4 RK_PB1 10 &pcfg_pull_up>; ++ }; ++ }; ++ ++ uart9 { ++ /omit-if-no-ref/ ++ uart9m1_xfer: uart9m1-xfer { ++ rockchip,pins = ++ /* uart9_rx_m1 */ ++ <4 RK_PB5 10 &pcfg_pull_up>, ++ /* uart9_tx_m1 */ ++ <4 RK_PB4 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m1_ctsn: uart9m1-ctsn { ++ rockchip,pins = ++ /* uart9m1_ctsn */ ++ <4 RK_PA1 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m1_rtsn: uart9m1-rtsn { ++ rockchip,pins = ++ /* uart9m1_rtsn */ ++ <4 RK_PA0 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m2_xfer: uart9m2-xfer { ++ rockchip,pins = ++ /* uart9_rx_m2 */ ++ <3 RK_PD4 10 &pcfg_pull_up>, ++ /* uart9_tx_m2 */ ++ <3 RK_PD5 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m2_ctsn: uart9m2-ctsn { ++ rockchip,pins = ++ /* uart9m2_ctsn */ ++ <3 RK_PD3 10 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9m2_rtsn: uart9m2-rtsn { ++ rockchip,pins = ++ /* uart9m2_rtsn */ ++ <3 RK_PD2 10 &pcfg_pull_none>; ++ }; ++ }; ++ ++ vop { ++ /omit-if-no-ref/ ++ vop_pins: vop-pins { ++ rockchip,pins = ++ /* vop_post_empty */ ++ <1 RK_PA2 1 &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++/* ++ * This part is edited handly. ++ */ ++&pinctrl { ++ bt656 { ++ /omit-if-no-ref/ ++ bt656_pins: bt656-pins { ++ rockchip,pins = ++ /* bt1120_clkout */ ++ <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d0 */ ++ <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d1 */ ++ <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d2 */ ++ <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d3 */ ++ <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d4 */ ++ <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d5 */ ++ <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d6 */ ++ <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, ++ /* bt1120_d7 */ ++ <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; ++ }; ++ }; ++ ++ gpio-func { ++ /omit-if-no-ref/ ++ tsadc_gpio_func: tsadc-gpio-func { ++ rockchip,pins = ++ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.1/050-02-v6.3-arm64-dts-rockchip-Add-base-DT-for-rk3588-SoC.patch b/target/linux/rockchip/patches-6.1/050-02-v6.3-arm64-dts-rockchip-Add-base-DT-for-rk3588-SoC.patch new file mode 100644 index 0000000000..069bee37fb --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-02-v6.3-arm64-dts-rockchip-Add-base-DT-for-rk3588-SoC.patch @@ -0,0 +1,1799 @@ +From c9211fa2602b87849086dd061da78b5e2dee1f3c Mon Sep 17 00:00:00 2001 +From: Kever Yang +Date: Mon, 9 Jan 2023 16:57:57 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add base DT for rk3588 SoC + +This initial version supports CPU, dma, interrupts, timers, UART and +SDHCI (everything necessary to boot Linux on this system on chip) as +well as Ethernet, I2C, PWM and SPI. + +The DT is split into rk3588 and rk3588s, which is a reduced version +(i.e. with less peripherals) of the former. + +Co-Developed-by: Yifeng Zhao +Signed-off-by: Yifeng Zhao +Co-Developed-by: Elaine Zhang +Signed-off-by: Elaine Zhang +Co-Developed-by: Sugar Zhang +Signed-off-by: Sugar Zhang +Signed-off-by: Kever Yang +[rebase, squash and reword commit message] +Signed-off-by: Sebastian Reichel +Acked-by: Jagan Teki +Tested-by: Jagan Teki # edgeble-neu6a +Link: https://lore.kernel.org/r/20230109155801.51642-4-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 58 + + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1703 +++++++++++++++++++++ + 2 files changed, 1761 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -0,0 +1,58 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include "rk3588s.dtsi" ++#include "rk3588-pinctrl.dtsi" ++ ++/ { ++ gmac0: ethernet@fe1b0000 { ++ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe1b0000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, ++ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, ++ <&cru CLK_GMAC0_PTP_REF>; ++ clock-names = "stmmaceth", "clk_mac_ref", ++ "pclk_mac", "aclk_mac", ++ "ptp_ref"; ++ power-domains = <&power RK3588_PD_GMAC>; ++ resets = <&cru SRST_A_GMAC0>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,php-grf = <&php_grf>; ++ snps,axi-config = <&gmac0_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio0: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac0_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,wr_osr_lmt = <4>; ++ snps,rd_osr_lmt = <8>; ++ }; ++ ++ gmac0_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ ++ gmac0_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -0,0 +1,1703 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/ { ++ compatible = "rockchip,rk3588"; ++ ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu_l0>; ++ }; ++ core1 { ++ cpu = <&cpu_l1>; ++ }; ++ core2 { ++ cpu = <&cpu_l2>; ++ }; ++ core3 { ++ cpu = <&cpu_l3>; ++ }; ++ }; ++ cluster1 { ++ core0 { ++ cpu = <&cpu_b0>; ++ }; ++ core1 { ++ cpu = <&cpu_b1>; ++ }; ++ }; ++ cluster2 { ++ core0 { ++ cpu = <&cpu_b2>; ++ }; ++ core1 { ++ cpu = <&cpu_b3>; ++ }; ++ }; ++ }; ++ ++ cpu_l0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x0>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l0>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_l1: cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l1>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_l2: cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l2>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_l3: cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x300>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <530>; ++ clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <32768>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <128>; ++ d-cache-size = <32768>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <128>; ++ next-level-cache = <&l2_cache_l3>; ++ dynamic-power-coefficient = <228>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b0: cpu@400 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x400>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b0>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b1: cpu@500 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x500>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b1>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b2: cpu@600 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x600>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b2>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ cpu_b3: cpu@700 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x700>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <1024>; ++ clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ cpu-idle-states = <&CPU_SLEEP>; ++ i-cache-size = <65536>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <65536>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache_b3>; ++ dynamic-power-coefficient = <416>; ++ #cooling-cells = <2>; ++ }; ++ ++ idle-states { ++ entry-method = "psci"; ++ CPU_SLEEP: cpu-sleep { ++ compatible = "arm,idle-state"; ++ local-timer-stop; ++ arm,psci-suspend-param = <0x0010000>; ++ entry-latency-us = <100>; ++ exit-latency-us = <120>; ++ min-residency-us = <1000>; ++ }; ++ }; ++ ++ l2_cache_l0: l2-cache-l0 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l1: l2-cache-l1 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l2: l2-cache-l2 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l3: l2-cache-l3 { ++ compatible = "cache"; ++ cache-size = <131072>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b0: l2-cache-b0 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b1: l2-cache-b1 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b2: l2-cache-b2 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_b3: l2-cache-b3 { ++ compatible = "cache"; ++ cache-size = <524288>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l3_cache: l3-cache { ++ compatible = "cache"; ++ cache-size = <3145728>; ++ cache-line-size = <64>; ++ cache-sets = <4096>; ++ }; ++ }; ++ ++ firmware { ++ optee: optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ ++ scmi: scmi { ++ compatible = "arm,scmi-smc"; ++ arm,smc-id = <0x82000010>; ++ shmem = <&scmi_shmem>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ scmi_clk: protocol@14 { ++ reg = <0x14>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, ++ <&scmi_clk SCMI_CLK_CPUB23>; ++ assigned-clock-rates = <1200000000>, ++ <1200000000>; ++ #clock-cells = <1>; ++ }; ++ ++ scmi_reset: protocol@16 { ++ reg = <0x16>; ++ #reset-cells = <1>; ++ }; ++ }; ++ }; ++ ++ pmu-a55 { ++ compatible = "arm,cortex-a55-pmu"; ++ interrupts = ; ++ }; ++ ++ pmu-a76 { ++ compatible = "arm,cortex-a76-pmu"; ++ interrupts = ; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ spll: clock-0 { ++ compatible = "fixed-clock"; ++ clock-frequency = <702000000>; ++ clock-output-names = "spll"; ++ #clock-cells = <0>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; ++ }; ++ ++ xin24m: clock-1 { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "xin24m"; ++ #clock-cells = <0>; ++ }; ++ ++ xin32k: clock-2 { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ #clock-cells = <0>; ++ }; ++ ++ pmu_sram: sram@10f000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0x0010f000 0x0 0x100>; ++ ranges = <0 0x0 0x0010f000 0x100>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ scmi_shmem: sram@0 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x0 0x100>; ++ }; ++ }; ++ ++ sys_grf: syscon@fd58c000 { ++ compatible = "rockchip,rk3588-sys-grf", "syscon"; ++ reg = <0x0 0xfd58c000 0x0 0x1000>; ++ }; ++ ++ php_grf: syscon@fd5b0000 { ++ compatible = "rockchip,rk3588-php-grf", "syscon"; ++ reg = <0x0 0xfd5b0000 0x0 0x1000>; ++ }; ++ ++ ioc: syscon@fd5f0000 { ++ compatible = "rockchip,rk3588-ioc", "syscon"; ++ reg = <0x0 0xfd5f0000 0x0 0x10000>; ++ }; ++ ++ system_sram1: sram@fd600000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0xfd600000 0x0 0x100000>; ++ ranges = <0x0 0x0 0xfd600000 0x100000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ ++ cru: clock-controller@fd7c0000 { ++ compatible = "rockchip,rk3588-cru"; ++ reg = <0x0 0xfd7c0000 0x0 0x5c000>; ++ assigned-clocks = ++ <&cru PLL_PPLL>, <&cru PLL_AUPLL>, ++ <&cru PLL_NPLL>, <&cru PLL_GPLL>, ++ <&cru ACLK_CENTER_ROOT>, ++ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, ++ <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, ++ <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, ++ <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, ++ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, ++ <&cru CLK_GPU>; ++ assigned-clock-rates = ++ <100000000>, <786432000>, ++ <850000000>, <1188000000>, ++ <702000000>, ++ <400000000>, <500000000>, ++ <800000000>, <100000000>, ++ <400000000>, <100000000>, ++ <200000000>, <500000000>, ++ <375000000>, <150000000>, ++ <200000000>; ++ rockchip,grf = <&php_grf>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ i2c0: i2c@fd880000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfd880000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; ++ clock-names = "i2c", "pclk"; ++ pinctrl-0 = <&i2c0m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart0: serial@fd890000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfd890000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 6>, <&dmac0 7>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart0m1_xfer>; ++ pinctrl-names = "default"; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ pwm0: pwm@fd8b0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0000 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm0m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@fd8b0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0010 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm1m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@fd8b0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0020 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm2m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@fd8b0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfd8b0030 0x0 0x10>; ++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm3m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pmu: power-management@fd8d8000 { ++ compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; ++ reg = <0x0 0xfd8d8000 0x0 0x400>; ++ ++ power: power-controller { ++ compatible = "rockchip,rk3588-power-controller"; ++ #address-cells = <1>; ++ #power-domain-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ /* These power domains are grouped by VD_NPU */ ++ power-domain@RK3588_PD_NPU { ++ reg = ; ++ #power-domain-cells = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3588_PD_NPUTOP { ++ reg = ; ++ clocks = <&cru HCLK_NPU_ROOT>, ++ <&cru PCLK_NPU_ROOT>, ++ <&cru CLK_NPU_DSU0>, ++ <&cru HCLK_NPU_CM0_ROOT>; ++ pm_qos = <&qos_npu0_mwr>, ++ <&qos_npu0_mro>, ++ <&qos_mcu_npu>; ++ #power-domain-cells = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power-domain@RK3588_PD_NPU1 { ++ reg = ; ++ clocks = <&cru HCLK_NPU_ROOT>, ++ <&cru PCLK_NPU_ROOT>, ++ <&cru CLK_NPU_DSU0>; ++ pm_qos = <&qos_npu1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_NPU2 { ++ reg = ; ++ clocks = <&cru HCLK_NPU_ROOT>, ++ <&cru PCLK_NPU_ROOT>, ++ <&cru CLK_NPU_DSU0>; ++ pm_qos = <&qos_npu2>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ /* These power domains are grouped by VD_GPU */ ++ power-domain@RK3588_PD_GPU { ++ reg = ; ++ clocks = <&cru CLK_GPU>, ++ <&cru CLK_GPU_COREGROUP>, ++ <&cru CLK_GPU_STACKS>; ++ pm_qos = <&qos_gpu_m0>, ++ <&qos_gpu_m1>, ++ <&qos_gpu_m2>, ++ <&qos_gpu_m3>; ++ #power-domain-cells = <0>; ++ }; ++ /* These power domains are grouped by VD_VCODEC */ ++ power-domain@RK3588_PD_VCODEC { ++ reg = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_RKVDEC0 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC0>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_RKVDEC0>, ++ <&cru ACLK_RKVDEC_CCU>; ++ pm_qos = <&qos_rkvdec0>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RKVDEC1 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC1>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_RKVDEC1>; ++ pm_qos = <&qos_rkvdec1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_VENC0 { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC0>, ++ <&cru ACLK_RKVENC0>; ++ pm_qos = <&qos_rkvenc0_m0ro>, ++ <&qos_rkvenc0_m1ro>, ++ <&qos_rkvenc0_m2wo>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_VENC1 { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC1>, ++ <&cru HCLK_RKVENC0>, ++ <&cru ACLK_RKVENC0>, ++ <&cru ACLK_RKVENC1>; ++ pm_qos = <&qos_rkvenc1_m0ro>, ++ <&qos_rkvenc1_m1ro>, ++ <&qos_rkvenc1_m2wo>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ /* These power domains are grouped by VD_LOGIC */ ++ power-domain@RK3588_PD_VDPU { ++ reg = ; ++ clocks = <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_LOW_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_JPEG_DECODER_ROOT>, ++ <&cru ACLK_IEP2P0>, ++ <&cru HCLK_IEP2P0>, ++ <&cru ACLK_JPEG_ENCODER0>, ++ <&cru HCLK_JPEG_ENCODER0>, ++ <&cru ACLK_JPEG_ENCODER1>, ++ <&cru HCLK_JPEG_ENCODER1>, ++ <&cru ACLK_JPEG_ENCODER2>, ++ <&cru HCLK_JPEG_ENCODER2>, ++ <&cru ACLK_JPEG_ENCODER3>, ++ <&cru HCLK_JPEG_ENCODER3>, ++ <&cru ACLK_JPEG_DECODER>, ++ <&cru HCLK_JPEG_DECODER>, ++ <&cru ACLK_RGA2>, ++ <&cru HCLK_RGA2>; ++ pm_qos = <&qos_iep>, ++ <&qos_jpeg_dec>, ++ <&qos_jpeg_enc0>, ++ <&qos_jpeg_enc1>, ++ <&qos_jpeg_enc2>, ++ <&qos_jpeg_enc3>, ++ <&qos_rga2_mro>, ++ <&qos_rga2_mwo>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ ++ power-domain@RK3588_PD_AV1 { ++ reg = ; ++ clocks = <&cru PCLK_AV1>, ++ <&cru ACLK_AV1>, ++ <&cru HCLK_VDPU_ROOT>; ++ pm_qos = <&qos_av1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RKVDEC0 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC0>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>, ++ <&cru ACLK_RKVDEC0>; ++ pm_qos = <&qos_rkvdec0>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RKVDEC1 { ++ reg = ; ++ clocks = <&cru HCLK_RKVDEC1>, ++ <&cru HCLK_VDPU_ROOT>, ++ <&cru ACLK_VDPU_ROOT>; ++ pm_qos = <&qos_rkvdec1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_RGA30 { ++ reg = ; ++ clocks = <&cru ACLK_RGA3_0>, ++ <&cru HCLK_RGA3_0>; ++ pm_qos = <&qos_rga3_0>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ power-domain@RK3588_PD_VOP { ++ reg = ; ++ clocks = <&cru PCLK_VOP_ROOT>, ++ <&cru HCLK_VOP_ROOT>, ++ <&cru ACLK_VOP>; ++ pm_qos = <&qos_vop_m0>, ++ <&qos_vop_m1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_VO0 { ++ reg = ; ++ clocks = <&cru PCLK_VO0_ROOT>, ++ <&cru PCLK_VO0_S_ROOT>, ++ <&cru HCLK_VO0_S_ROOT>, ++ <&cru ACLK_VO0_ROOT>, ++ <&cru HCLK_HDCP0>, ++ <&cru ACLK_HDCP0>, ++ <&cru HCLK_VOP_ROOT>; ++ pm_qos = <&qos_hdcp0>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ power-domain@RK3588_PD_VO1 { ++ reg = ; ++ clocks = <&cru PCLK_VO1_ROOT>, ++ <&cru PCLK_VO1_S_ROOT>, ++ <&cru HCLK_VO1_S_ROOT>, ++ <&cru HCLK_HDCP1>, ++ <&cru ACLK_HDCP1>, ++ <&cru ACLK_HDMIRX_ROOT>, ++ <&cru HCLK_VO1USB_TOP_ROOT>; ++ pm_qos = <&qos_hdcp1>, ++ <&qos_hdmirx>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_VI { ++ reg = ; ++ clocks = <&cru HCLK_VI_ROOT>, ++ <&cru PCLK_VI_ROOT>, ++ <&cru HCLK_ISP0>, ++ <&cru ACLK_ISP0>, ++ <&cru HCLK_VICAP>, ++ <&cru ACLK_VICAP>; ++ pm_qos = <&qos_isp0_mro>, ++ <&qos_isp0_mwo>, ++ <&qos_vicap_m0>, ++ <&qos_vicap_m1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #power-domain-cells = <0>; ++ ++ power-domain@RK3588_PD_ISP1 { ++ reg = ; ++ clocks = <&cru HCLK_ISP1>, ++ <&cru ACLK_ISP1>, ++ <&cru HCLK_VI_ROOT>, ++ <&cru PCLK_VI_ROOT>; ++ pm_qos = <&qos_isp1_mwo>, ++ <&qos_isp1_mro>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_FEC { ++ reg = ; ++ clocks = <&cru HCLK_FISHEYE0>, ++ <&cru ACLK_FISHEYE0>, ++ <&cru HCLK_FISHEYE1>, ++ <&cru ACLK_FISHEYE1>, ++ <&cru PCLK_VI_ROOT>; ++ pm_qos = <&qos_fisheye0>, ++ <&qos_fisheye1>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ power-domain@RK3588_PD_RGA31 { ++ reg = ; ++ clocks = <&cru HCLK_RGA3_1>, ++ <&cru ACLK_RGA3_1>; ++ pm_qos = <&qos_rga3_1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_USB { ++ reg = ; ++ clocks = <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_USB_ROOT>, ++ <&cru HCLK_USB_ROOT>, ++ <&cru HCLK_HOST0>, ++ <&cru HCLK_HOST_ARB0>, ++ <&cru HCLK_HOST1>, ++ <&cru HCLK_HOST_ARB1>; ++ pm_qos = <&qos_usb3_0>, ++ <&qos_usb3_1>, ++ <&qos_usb2host_0>, ++ <&qos_usb2host_1>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_GMAC { ++ reg = ; ++ clocks = <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_PCIE_ROOT>, ++ <&cru ACLK_PHP_ROOT>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_PCIE { ++ reg = ; ++ clocks = <&cru PCLK_PHP_ROOT>, ++ <&cru ACLK_PCIE_ROOT>, ++ <&cru ACLK_PHP_ROOT>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_SDIO { ++ reg = ; ++ clocks = <&cru HCLK_SDIO>, ++ <&cru HCLK_NVM_ROOT>; ++ pm_qos = <&qos_sdio>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_AUDIO { ++ reg = ; ++ clocks = <&cru HCLK_AUDIO_ROOT>, ++ <&cru PCLK_AUDIO_ROOT>; ++ #power-domain-cells = <0>; ++ }; ++ power-domain@RK3588_PD_SDMMC { ++ reg = ; ++ pm_qos = <&qos_sdmmc>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ ++ qos_gpu_m0: qos@fdf35000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35000 0x0 0x20>; ++ }; ++ ++ qos_gpu_m1: qos@fdf35200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35200 0x0 0x20>; ++ }; ++ ++ qos_gpu_m2: qos@fdf35400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35400 0x0 0x20>; ++ }; ++ ++ qos_gpu_m3: qos@fdf35600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf35600 0x0 0x20>; ++ }; ++ ++ qos_rga3_1: qos@fdf36000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf36000 0x0 0x20>; ++ }; ++ ++ qos_sdio: qos@fdf39000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf39000 0x0 0x20>; ++ }; ++ ++ qos_sdmmc: qos@fdf3d800 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3d800 0x0 0x20>; ++ }; ++ ++ qos_usb3_1: qos@fdf3e000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e000 0x0 0x20>; ++ }; ++ ++ qos_usb3_0: qos@fdf3e200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e200 0x0 0x20>; ++ }; ++ ++ qos_usb2host_0: qos@fdf3e400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e400 0x0 0x20>; ++ }; ++ ++ qos_usb2host_1: qos@fdf3e600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf3e600 0x0 0x20>; ++ }; ++ ++ qos_fisheye0: qos@fdf40000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40000 0x0 0x20>; ++ }; ++ ++ qos_fisheye1: qos@fdf40200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40200 0x0 0x20>; ++ }; ++ ++ qos_isp0_mro: qos@fdf40400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40400 0x0 0x20>; ++ }; ++ ++ qos_isp0_mwo: qos@fdf40500 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40500 0x0 0x20>; ++ }; ++ ++ qos_vicap_m0: qos@fdf40600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40600 0x0 0x20>; ++ }; ++ ++ qos_vicap_m1: qos@fdf40800 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf40800 0x0 0x20>; ++ }; ++ ++ qos_isp1_mwo: qos@fdf41000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf41000 0x0 0x20>; ++ }; ++ ++ qos_isp1_mro: qos@fdf41100 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf41100 0x0 0x20>; ++ }; ++ ++ qos_rkvenc0_m0ro: qos@fdf60000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf60000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc0_m1ro: qos@fdf60200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf60200 0x0 0x20>; ++ }; ++ ++ qos_rkvenc0_m2wo: qos@fdf60400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf60400 0x0 0x20>; ++ }; ++ ++ qos_rkvenc1_m0ro: qos@fdf61000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf61000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc1_m1ro: qos@fdf61200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf61200 0x0 0x20>; ++ }; ++ ++ qos_rkvenc1_m2wo: qos@fdf61400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf61400 0x0 0x20>; ++ }; ++ ++ qos_rkvdec0: qos@fdf62000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf62000 0x0 0x20>; ++ }; ++ ++ qos_rkvdec1: qos@fdf63000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf63000 0x0 0x20>; ++ }; ++ ++ qos_av1: qos@fdf64000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf64000 0x0 0x20>; ++ }; ++ ++ qos_iep: qos@fdf66000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66000 0x0 0x20>; ++ }; ++ ++ qos_jpeg_dec: qos@fdf66200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66200 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc0: qos@fdf66400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66400 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc1: qos@fdf66600 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66600 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc2: qos@fdf66800 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66800 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc3: qos@fdf66a00 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66a00 0x0 0x20>; ++ }; ++ ++ qos_rga2_mro: qos@fdf66c00 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66c00 0x0 0x20>; ++ }; ++ ++ qos_rga2_mwo: qos@fdf66e00 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf66e00 0x0 0x20>; ++ }; ++ ++ qos_rga3_0: qos@fdf67000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf67000 0x0 0x20>; ++ }; ++ ++ qos_vdpu: qos@fdf67200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf67200 0x0 0x20>; ++ }; ++ ++ qos_npu1: qos@fdf70000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf70000 0x0 0x20>; ++ }; ++ ++ qos_npu2: qos@fdf71000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf71000 0x0 0x20>; ++ }; ++ ++ qos_npu0_mwr: qos@fdf72000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf72000 0x0 0x20>; ++ }; ++ ++ qos_npu0_mro: qos@fdf72200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf72200 0x0 0x20>; ++ }; ++ ++ qos_mcu_npu: qos@fdf72400 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf72400 0x0 0x20>; ++ }; ++ ++ qos_hdcp0: qos@fdf80000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf80000 0x0 0x20>; ++ }; ++ ++ qos_hdcp1: qos@fdf81000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf81000 0x0 0x20>; ++ }; ++ ++ qos_hdmirx: qos@fdf81200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf81200 0x0 0x20>; ++ }; ++ ++ qos_vop_m0: qos@fdf82000 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf82000 0x0 0x20>; ++ }; ++ ++ qos_vop_m1: qos@fdf82200 { ++ compatible = "rockchip,rk3588-qos", "syscon"; ++ reg = <0x0 0xfdf82200 0x0 0x20>; ++ }; ++ ++ gmac1: ethernet@fe1c0000 { ++ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe1c0000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, ++ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, ++ <&cru CLK_GMAC1_PTP_REF>; ++ clock-names = "stmmaceth", "clk_mac_ref", ++ "pclk_mac", "aclk_mac", ++ "ptp_ref"; ++ power-domains = <&power RK3588_PD_GMAC>; ++ resets = <&cru SRST_A_GMAC1>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,php-grf = <&php_grf>; ++ snps,axi-config = <&gmac1_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac1_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,wr_osr_lmt = <4>; ++ snps,rd_osr_lmt = <8>; ++ }; ++ ++ gmac1_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ ++ gmac1_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <2>; ++ queue0 {}; ++ queue1 {}; ++ }; ++ }; ++ ++ sdhci: mmc@fe2e0000 { ++ compatible = "rockchip,rk3588-dwcmshc"; ++ reg = <0x0 0xfe2e0000 0x0 0x10000>; ++ interrupts = ; ++ assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; ++ assigned-clock-rates = <200000000>, <24000000>, <200000000>; ++ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, ++ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, ++ <&cru TMCLK_EMMC>; ++ clock-names = "core", "bus", "axi", "block", "timer"; ++ max-frequency = <200000000>; ++ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, ++ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, ++ <&cru SRST_T_EMMC>; ++ reset-names = "core", "bus", "axi", "block", "timer"; ++ status = "disabled"; ++ }; ++ ++ gic: interrupt-controller@fe600000 { ++ compatible = "arm,gic-v3"; ++ reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ ++ <0x0 0xfe680000 0 0x100000>; /* GICR */ ++ interrupts = ; ++ interrupt-controller; ++ mbi-alias = <0x0 0xfe610000>; ++ mbi-ranges = <424 56>; ++ msi-controller; ++ #interrupt-cells = <4>; ++ ++ ppi-partitions { ++ ppi_partition0: interrupt-partition-0 { ++ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; ++ }; ++ ++ ppi_partition1: interrupt-partition-1 { ++ affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; ++ }; ++ }; ++ }; ++ ++ dmac0: dma-controller@fea10000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfea10000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC0>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ dmac1: dma-controller@fea30000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfea30000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC1>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ i2c1: i2c@fea90000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfea90000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c1m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@feaa0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeaa0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c2m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@feab0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeab0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c3m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@feac0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeac0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c4m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@fead0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfead0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c5m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@feb00000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb00000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 14>, <&dmac0 15>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@feb10000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb10000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 16>, <&dmac0 17>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@feb20000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb20000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac1 15>, <&dmac1 16>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@feb30000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfeb30000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac1 17>, <&dmac1 18>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@feb40000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb40000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 8>, <&dmac0 9>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart1m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@feb50000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb50000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 10>, <&dmac0 11>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart2m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@feb60000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb60000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac0 12>, <&dmac0 13>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart3m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@feb70000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb70000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 9>, <&dmac1 10>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart4m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@feb80000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb80000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 11>, <&dmac1 12>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart5m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart6: serial@feb90000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeb90000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac1 13>, <&dmac1 14>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart6m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart7: serial@feba0000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfeba0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 7>, <&dmac2 8>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart7m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart8: serial@febb0000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfebb0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 9>, <&dmac2 10>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart8m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart9: serial@febc0000 { ++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xfebc0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; ++ clock-names = "baudclk", "apb_pclk"; ++ dmas = <&dmac2 11>, <&dmac2 12>; ++ dma-names = "tx", "rx"; ++ pinctrl-0 = <&uart9m1_xfer>; ++ pinctrl-names = "default"; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@febd0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm4m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@febd0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm5m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@febd0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm6m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@febd0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebd0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm7m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm8: pwm@febe0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm8m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm9: pwm@febe0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm9m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm10: pwm@febe0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm10m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm11: pwm@febe0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebe0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm11m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm12: pwm@febf0000 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm12m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm13: pwm@febf0010 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm13m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm14: pwm@febf0020 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm14m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm15: pwm@febf0030 { ++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfebf0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm15m0_pins>; ++ pinctrl-names = "default"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ i2c6: i2c@fec80000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfec80000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c6m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c7: i2c@fec90000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfec90000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c7m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c8: i2c@feca0000 { ++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; ++ reg = <0x0 0xfeca0000 0x0 0x1000>; ++ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; ++ clock-names = "i2c", "pclk"; ++ interrupts = ; ++ pinctrl-0 = <&i2c8m0_xfer>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi4: spi@fecb0000 { ++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfecb0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac2 13>, <&dmac2 14>; ++ dma-names = "tx", "rx"; ++ num-cs = <2>; ++ pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ dmac2: dma-controller@fed10000 { ++ compatible = "arm,pl330", "arm,primecell"; ++ reg = <0x0 0xfed10000 0x0 0x4000>; ++ interrupts = , ++ ; ++ arm,pl330-periph-burst; ++ clocks = <&cru ACLK_DMAC2>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <1>; ++ }; ++ ++ system_sram2: sram@ff001000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0xff001000 0x0 0xef000>; ++ ranges = <0x0 0x0 0xff001000 0xef000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ ++ pinctrl: pinctrl { ++ compatible = "rockchip,rk3588-pinctrl"; ++ ranges; ++ rockchip,grf = <&ioc>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ gpio0: gpio@fd8a0000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfd8a0000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 0 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio1: gpio@fec20000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec20000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 32 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio2: gpio@fec30000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec30000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 64 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio3: gpio@fec40000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec40000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 96 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio4: gpio@fec50000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x0 0xfec50000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; ++ gpio-controller; ++ gpio-ranges = <&pinctrl 0 128 32>; ++ interrupt-controller; ++ #gpio-cells = <2>; ++ #interrupt-cells = <2>; ++ }; ++ }; ++}; ++ ++#include "rk3588s-pinctrl.dtsi" diff --git a/target/linux/rockchip/patches-6.1/050-03-v6.4-arm64-dts-rockchip-Add-sdmmc-node-to-rk3588.patch b/target/linux/rockchip/patches-6.1/050-03-v6.4-arm64-dts-rockchip-Add-sdmmc-node-to-rk3588.patch new file mode 100644 index 0000000000..c785f4d862 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-03-v6.4-arm64-dts-rockchip-Add-sdmmc-node-to-rk3588.patch @@ -0,0 +1,40 @@ +From dbe406d1397ffccd4a0f85daef456291f265505a Mon Sep 17 00:00:00 2001 +From: Lucas Tanure +Date: Tue, 28 Feb 2023 10:36:10 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add sdmmc node to rk3588 + +Add SD Card node for RK3588s and RK3588. + +Co-developed-by: Shawn Lin +Signed-off-by: Shawn Lin +Signed-off-by: Lucas Tanure +Link: https://lore.kernel.org/r/20230228103610.25108-1-lucas.tanure@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1099,6 +1099,21 @@ + }; + }; + ++ sdmmc: mmc@fe2c0000 { ++ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xfe2c0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, ++ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; ++ power-domains = <&power RK3588_PD_SDMMC>; ++ status = "disabled"; ++ }; ++ + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.1/050-04-v6.4-arm64-dts-rockchip-add-rk3588-cache-level-information.patch b/target/linux/rockchip/patches-6.1/050-04-v6.4-arm64-dts-rockchip-add-rk3588-cache-level-information.patch new file mode 100644 index 0000000000..a93a4df3d1 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-04-v6.4-arm64-dts-rockchip-add-rk3588-cache-level-information.patch @@ -0,0 +1,88 @@ +From b37115b6534c4027df75854a44b485596d368171 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 17 Mar 2023 18:41:02 +0100 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 cache level information + +Add missing, mandatory cache-level information for RK3588. + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230317174102.61209-1-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -222,6 +222,7 @@ + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -230,6 +231,7 @@ + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -238,6 +240,7 @@ + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -246,6 +249,7 @@ + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -254,6 +258,7 @@ + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -262,6 +267,7 @@ + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -270,6 +276,7 @@ + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -278,6 +285,7 @@ + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; ++ cache-level = <2>; + next-level-cache = <&l3_cache>; + }; + +@@ -286,6 +294,7 @@ + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; ++ cache-level = <3>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.1/050-05-v6.4-arm64-dts-rockchip-Enable-watchdog-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/050-05-v6.4-arm64-dts-rockchip-Enable-watchdog-support-for-RK3588.patch new file mode 100644 index 0000000000..a5a75fd4b0 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-05-v6.4-arm64-dts-rockchip-Enable-watchdog-support-for-RK3588.patch @@ -0,0 +1,31 @@ +From 932d139e4db18d535dea271df51db5216b8787b3 Mon Sep 17 00:00:00 2001 +From: Shreeya Patel +Date: Wed, 29 Mar 2023 02:30:47 +0530 +Subject: [PATCH] arm64: dts: rockchip: Enable watchdog support for RK3588 + +Add DT node for watchdog support in RK3588. + +Signed-off-by: Shreeya Patel +Link: https://lore.kernel.org/r/20230328210048.195124-2-shreeya.patel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1250,6 +1250,14 @@ + status = "disabled"; + }; + ++ wdt: watchdog@feaf0000 { ++ compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; ++ reg = <0x0 0xfeaf0000 0x0 0x100>; ++ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; ++ clock-names = "tclk", "pclk"; ++ interrupts = ; ++ }; ++ + spi0: spi@feb00000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.1/050-06-v6.4-arm64-dts-rockchip-add-rk3588-thermal-sensor.patch b/target/linux/rockchip/patches-6.1/050-06-v6.4-arm64-dts-rockchip-add-rk3588-thermal-sensor.patch new file mode 100644 index 0000000000..ce2c73e816 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-06-v6.4-arm64-dts-rockchip-add-rk3588-thermal-sensor.patch @@ -0,0 +1,52 @@ +From 32641b8ab1a5bd08e898cec3d46a8ecb4b4e895e Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 4 Apr 2023 17:44:29 +0200 +Subject: [PATCH] arm64: dts: rockchip: add rk3588 thermal sensor + +Add thermal sensor IP, which allows monitoring temperatures at +seven different places in the SoC: + +* Chip Center +* CPU Cluster 1 (Dual A76 "Big" Cores) +* CPU Cluster 2 (Dual A76 "Big" Cores) +* CPU Cluster 0 (Quad A55 "Little" Cores) +* Power Domain Center +* Graphics Processing Unit +* Neural Processing Unit + +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230404154429.51601-1-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1589,6 +1589,26 @@ + status = "disabled"; + }; + ++ tsadc: tsadc@fec00000 { ++ compatible = "rockchip,rk3588-tsadc"; ++ reg = <0x0 0xfec00000 0x0 0x400>; ++ interrupts = ; ++ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; ++ clock-names = "tsadc", "apb_pclk"; ++ assigned-clocks = <&cru CLK_TSADC>; ++ assigned-clock-rates = <2000000>; ++ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; ++ reset-names = "tsadc-apb", "tsadc"; ++ rockchip,hw-tshut-temp = <120000>; ++ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ ++ pinctrl-0 = <&tsadc_gpio_func>; ++ pinctrl-1 = <&tsadc_shut>; ++ pinctrl-names = "gpio", "otpout"; ++ #thermal-sensor-cells = <1>; ++ status = "disabled"; ++ }; ++ + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.1/050-07-v6.4-arm64-dts-rockchip-Fix-SCMI-assigned-clocks-on-rk3588s.patch b/target/linux/rockchip/patches-6.1/050-07-v6.4-arm64-dts-rockchip-Fix-SCMI-assigned-clocks-on-rk3588s.patch new file mode 100644 index 0000000000..08ec456c64 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-07-v6.4-arm64-dts-rockchip-Fix-SCMI-assigned-clocks-on-rk3588s.patch @@ -0,0 +1,68 @@ +From 87810bda8a8472a9a106c6de34a032fb6a4b425b Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 2 Apr 2023 12:50:50 +0300 +Subject: [PATCH] arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s + +Since commit df4fdd0db475 ("dt-bindings: firmware: arm,scmi: Restrict +protocol child node properties") the following dtbs_check warning is +shown: + + rk3588-rock-5b.dtb: scmi: protocol@14: Unevaluated properties are not + allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) + +Because adding the missing properties to firmware/arm,scmi.yaml binding +document was not an acceptable solution, move SCMI_CLK_CPUB01 and +SCMI_CLK_CPUB23 assigned clocks to the related CPU nodes and also add +the missing SCMI_CLK_CPUL. + +Additionally, adjust frequency to 816 MHz for all the above mentioned +assigned clocks, in order to match the firmware defaults. + +Suggested-by: Sebastian Reichel +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230402095054.384739-2-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -60,6 +60,8 @@ + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -136,6 +138,8 @@ + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -174,6 +178,8 @@ + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -313,10 +319,6 @@ + + scmi_clk: protocol@14 { + reg = <0x14>; +- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, +- <&scmi_clk SCMI_CLK_CPUB23>; +- assigned-clock-rates = <1200000000>, +- <1200000000>; + #clock-cells = <1>; + }; + diff --git a/target/linux/rockchip/patches-6.1/050-08-v6.4-arm64-dts-rockchip-Assign-PLL_PPLL-clock-rate-to-1.1-GHz.patch b/target/linux/rockchip/patches-6.1/050-08-v6.4-arm64-dts-rockchip-Assign-PLL_PPLL-clock-rate-to-1.1-GHz.patch new file mode 100644 index 0000000000..067ccc66b1 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-08-v6.4-arm64-dts-rockchip-Assign-PLL_PPLL-clock-rate-to-1.1-GHz.patch @@ -0,0 +1,29 @@ +From b46a22dea7530cf530a45c6b84c03300083b813d Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 2 Apr 2023 12:50:51 +0300 +Subject: [PATCH] arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz + on rk3588s + +The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz +instead of 1.1 GHz. Fix it. + +Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC") +Reported-by: Sebastian Reichel +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -425,7 +425,7 @@ + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>; + assigned-clock-rates = +- <100000000>, <786432000>, ++ <1100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, diff --git a/target/linux/rockchip/patches-6.1/050-09-v6.4-arm64-dts-rockchip-Add-rk3588s-I2S-nodes.patch b/target/linux/rockchip/patches-6.1/050-09-v6.4-arm64-dts-rockchip-Add-rk3588s-I2S-nodes.patch new file mode 100644 index 0000000000..2637b9c0fd --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-09-v6.4-arm64-dts-rockchip-Add-rk3588s-I2S-nodes.patch @@ -0,0 +1,185 @@ +From 8ae112a5554fb1580fc5564f8610cef85f2e3f7b Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 2 Apr 2023 12:50:52 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add rk3588s I2S nodes + +There are five I2S/PCM/TDM controllers and two I2S/PCM controllers +embedded in the RK3588 and RK3588S SoCs. + +Add the DT nodes corresponding to the above mentioned Rockchip +controllers. + +Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers, +which are handled via a separate patch. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230402095054.384739-4-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 148 ++++++++++++++++++++++ + 1 file changed, 148 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -821,6 +821,57 @@ + }; + }; + ++ i2s4_8ch: i2s@fddc0000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddc0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 0>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO0>; ++ resets = <&cru SRST_M_I2S4_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s5_8ch: i2s@fddf0000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddf0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 2>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S5_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s9_8ch: i2s@fddfc000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddfc000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 23>; ++ dma-names = "rx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S9_8CH_RX>; ++ reset-names = "rx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + qos_gpu_m0: qos@fdf35000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; +@@ -1143,6 +1194,103 @@ + status = "disabled"; + }; + ++ i2s0_8ch: i2s@fe470000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfe470000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; ++ dmas = <&dmac0 0>, <&dmac0 1>; ++ dma-names = "tx", "rx"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,trcm-sync-tx-only; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdi1 ++ &i2s0_sdi2 ++ &i2s0_sdi3 ++ &i2s0_sdo0 ++ &i2s0_sdo1 ++ &i2s0_sdo2 ++ &i2s0_sdo3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s1_8ch: i2s@fe480000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfe480000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac0 2>, <&dmac0 3>; ++ dma-names = "tx", "rx"; ++ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,trcm-sync-tx-only; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_lrck ++ &i2s1m0_sclk ++ &i2s1m0_sdi0 ++ &i2s1m0_sdi1 ++ &i2s1m0_sdi2 ++ &i2s1m0_sdi3 ++ &i2s1m0_sdo0 ++ &i2s1m0_sdo1 ++ &i2s1m0_sdo2 ++ &i2s1m0_sdo3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s2_2ch: i2s@fe490000 { ++ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; ++ reg = <0x0 0xfe490000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; ++ clock-names = "i2s_clk", "i2s_hclk"; ++ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac1 0>, <&dmac1 1>; ++ dma-names = "tx", "rx"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ rockchip,trcm-sync-tx-only; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s2m1_lrck ++ &i2s2m1_sclk ++ &i2s2m1_sdi ++ &i2s2m1_sdo>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s3_2ch: i2s@fe4a0000 { ++ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; ++ reg = <0x0 0xfe4a0000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; ++ clock-names = "i2s_clk", "i2s_hclk"; ++ assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac1 2>, <&dmac1 3>; ++ dma-names = "tx", "rx"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ rockchip,trcm-sync-tx-only; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s3_lrck ++ &i2s3_sclk ++ &i2s3_sdi ++ &i2s3_sdo>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ diff --git a/target/linux/rockchip/patches-6.1/050-10-v6.4-arm64-dts-rockchip-Add-I2S-rk3588-nodes.patch b/target/linux/rockchip/patches-6.1/050-10-v6.4-arm64-dts-rockchip-Add-I2S-rk3588-nodes.patch new file mode 100644 index 0000000000..156c306d27 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-10-v6.4-arm64-dts-rockchip-Add-I2S-rk3588-nodes.patch @@ -0,0 +1,95 @@ +From 6f48c6f5859296eaf54a55f436db3a248f772e4d Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 2 Apr 2023 12:50:53 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add I2S rk3588 nodes + +In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM +controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides +another group of four I2S/PCM/TDM controllers. + +Add the DT nodes corresponding to the additional controllers. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230402095054.384739-5-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 68 ++++++++++++++++++++++++ + 1 file changed, 68 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -7,6 +7,74 @@ + #include "rk3588-pinctrl.dtsi" + + / { ++ i2s8_8ch: i2s@fddc8000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddc8000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 22>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO0>; ++ resets = <&cru SRST_M_I2S8_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s6_8ch: i2s@fddf4000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddf4000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 4>; ++ dma-names = "tx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S6_8CH_TX>; ++ reset-names = "tx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s7_8ch: i2s@fddf8000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfddf8000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 21>; ++ dma-names = "rx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S7_8CH_RX>; ++ reset-names = "rx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2s10_8ch: i2s@fde00000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x0 0xfde00000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ dmas = <&dmac2 24>; ++ dma-names = "rx"; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_M_I2S10_8CH_RX>; ++ reset-names = "rx-m"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-6.1/050-11-v6.5-arm64-dts-rockchip-add-GIC-ITS-support-to-rk3588.patch b/target/linux/rockchip/patches-6.1/050-11-v6.5-arm64-dts-rockchip-add-GIC-ITS-support-to-rk3588.patch new file mode 100644 index 0000000000..f6cff0954b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-11-v6.5-arm64-dts-rockchip-add-GIC-ITS-support-to-rk3588.patch @@ -0,0 +1,45 @@ +From 06cdac8e840767f801bbd94ed991354a206adf1f Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 18 Apr 2023 16:21:09 +0200 +Subject: [PATCH] arm64: dts: rockchip: add GIC ITS support to rk3588 + +Add the two Interrupt Translation Service (ITS) IPs that are part of the +GIC-600. They are mainly required for PCIe Message Signalled Interrupts +(MSI). + +Co-developed-by: Kever Yang +Signed-off-by: Kever Yang +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230418142109.49762-3-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1300,7 +1300,24 @@ + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; ++ ranges; ++ #address-cells = <2>; + #interrupt-cells = <4>; ++ #size-cells = <2>; ++ ++ its0: msi-controller@fe640000 { ++ compatible = "arm,gic-v3-its"; ++ reg = <0x0 0xfe640000 0x0 0x20000>; ++ msi-controller; ++ #msi-cells = <1>; ++ }; ++ ++ its1: msi-controller@fe660000 { ++ compatible = "arm,gic-v3-its"; ++ reg = <0x0 0xfe660000 0x0 0x20000>; ++ msi-controller; ++ #msi-cells = <1>; ++ }; + + ppi-partitions { + ppi_partition0: interrupt-partition-0 { diff --git a/target/linux/rockchip/patches-6.1/050-12-v6.5-arm64-dts-rockchip-Add-rk3588-timer.patch b/target/linux/rockchip/patches-6.1/050-12-v6.5-arm64-dts-rockchip-Add-rk3588-timer.patch new file mode 100644 index 0000000000..d0dac55911 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-12-v6.5-arm64-dts-rockchip-Add-rk3588-timer.patch @@ -0,0 +1,31 @@ +From 09d5fef31f9058e3b39e3a6b8870b6fb9f28091d Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Wed, 19 Apr 2023 21:13:09 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add rk3588 timer + +Add DT node for Rockchip RK3588/RK3588S SoC timer. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230419181309.338354-4-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1417,6 +1417,14 @@ + status = "disabled"; + }; + ++ timer0: timer@feae0000 { ++ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; ++ reg = <0x0 0xfeae0000 0x0 0x20>; ++ interrupts = ; ++ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; ++ clock-names = "pclk", "timer"; ++ }; ++ + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.1/050-13-v6.5-arm64-dts-rockchip-Add-rk3588-OTP-node.patch b/target/linux/rockchip/patches-6.1/050-13-v6.5-arm64-dts-rockchip-Add-rk3588-OTP-node.patch new file mode 100644 index 0000000000..63ba42b4a4 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/050-13-v6.5-arm64-dts-rockchip-Add-rk3588-OTP-node.patch @@ -0,0 +1,81 @@ +From bcac467b7ca045224bd0f35e245b8edfcb1c452e Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Thu, 4 May 2023 23:06:48 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add rk3588 OTP node + +Add DT node for Rockchip RK3588/RK3588S OTP memory. + +Co-developed-by: Finley Xiao +Signed-off-by: Finley Xiao +Signed-off-by: Cristian Ciocaltea +Tested-by: Vincent Legoll +[moved cpu-version subnode down, to be sorted by address] +Link: https://lore.kernel.org/r/20230504200648.1119866-9-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -1839,6 +1839,60 @@ + status = "disabled"; + }; + ++ otp: efuse@fecc0000 { ++ compatible = "rockchip,rk3588-otp"; ++ reg = <0x0 0xfecc0000 0x0 0x400>; ++ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, ++ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; ++ clock-names = "otp", "apb_pclk", "phy", "arb"; ++ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, ++ <&cru SRST_OTPC_ARB>; ++ reset-names = "otp", "apb", "arb"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpu_code: cpu-code@2 { ++ reg = <0x02 0x2>; ++ }; ++ ++ otp_id: id@7 { ++ reg = <0x07 0x10>; ++ }; ++ ++ cpub0_leakage: cpu-leakage@17 { ++ reg = <0x17 0x1>; ++ }; ++ ++ cpub1_leakage: cpu-leakage@18 { ++ reg = <0x18 0x1>; ++ }; ++ ++ cpul_leakage: cpu-leakage@19 { ++ reg = <0x19 0x1>; ++ }; ++ ++ log_leakage: log-leakage@1a { ++ reg = <0x1a 0x1>; ++ }; ++ ++ gpu_leakage: gpu-leakage@1b { ++ reg = <0x1b 0x1>; ++ }; ++ ++ otp_cpu_version: cpu-version@1c { ++ reg = <0x1c 0x1>; ++ bits = <3 3>; ++ }; ++ ++ npu_leakage: npu-leakage@28 { ++ reg = <0x28 0x1>; ++ }; ++ ++ codec_leakage: codec-leakage@29 { ++ reg = <0x29 0x1>; ++ }; ++ }; ++ + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-6.1/051-01-v6.3-arm64-dts-rockchip-Add-rk3588-evb1-board.patch b/target/linux/rockchip/patches-6.1/051-01-v6.3-arm64-dts-rockchip-Add-rk3588-evb1-board.patch new file mode 100644 index 0000000000..46e1e6ea13 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/051-01-v6.3-arm64-dts-rockchip-Add-rk3588-evb1-board.patch @@ -0,0 +1,162 @@ +From e904ca928a3f6d73df062da63a91e346e084a63a Mon Sep 17 00:00:00 2001 +From: Kever Yang +Date: Mon, 9 Jan 2023 16:57:59 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add rk3588-evb1 board + +Add board file for the RK3588 evaluation board. While the hardware +offers plenty of peripherals and connectivity this basic implementation +just handles things required to successfully boot Linux from eMMC, +connect via UART or Ethernet. + +Signed-off-by: Kever Yang +[rebase, update commit message, use EVB1 for SoC bringup] +Reviewed-by: Michael Riesch +Signed-off-by: Sebastian Reichel +Reviewed-by: Jagan Teki +Link: https://lore.kernel.org/r/20230109155801.51642-6-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 129 ++++++++++++++++++ + 2 files changed, 130 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -80,3 +80,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fa + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -0,0 +1,129 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ model = "Rockchip RK3588 EVB1 V10 Board"; ++ compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ power-supply = <&vcc12v_dcin>; ++ pwms = <&pwm2 0 25000 0>; ++ }; ++ ++ vcc12v_dcin: vcc12v-dcin-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++}; ++ ++&gmac0 { ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy>; ++ phy-mode = "rgmii-rxid"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ pinctrl-names = "default"; ++ rx_delay = <0x00>; ++ tx_delay = <0x43>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&mdio0 { ++ rgmii_phy: ethernet-phy@1 { ++ /* RTL8211F */ ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <0x1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8211f_rst>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ rtl8211f { ++ rtl8211f_rst: rtl8211f-rst { ++ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ max-frequency = <200000000>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.1/052-01-v6.3-arm64-dts-rockchip-Add-rock-5a-board.patch b/target/linux/rockchip/patches-6.1/052-01-v6.3-arm64-dts-rockchip-Add-rock-5a-board.patch new file mode 100644 index 0000000000..a3e1db1e4d --- /dev/null +++ b/target/linux/rockchip/patches-6.1/052-01-v6.3-arm64-dts-rockchip-Add-rock-5a-board.patch @@ -0,0 +1,104 @@ +From d1824cf9579924737da64b3eba5ad3129ad67f28 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Mon, 9 Jan 2023 16:58:00 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add rock-5a board + +Add board file for the RK3588s Rock 5A board. While the hardware +offers plenty of peripherals and connectivity this basic implementation +just handles things required to access eMMC, UART and Ethernet (i.e. +enough to successfully boot Linux). + +Reviewed-by: Michael Riesch +Tested-by: Benjamin Gaignard +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230109155801.51642-7-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3588s-rock-5a.dts | 73 +++++++++++++++++++ + 2 files changed, 74 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -81,3 +81,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-na + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -0,0 +1,73 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3588s.dtsi" ++ ++/ { ++ model = "Radxa ROCK 5 Model A"; ++ compatible = "radxa,rock-5a", "rockchip,rk3588s"; ++ ++ aliases { ++ mmc1 = &sdhci; ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++}; ++ ++&gmac1 { ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-rxid"; ++ pinctrl-0 = <&gmac1_miim ++ &gmac1_tx_bus2 ++ &gmac1_rx_bus2 ++ &gmac1_rgmii_clk ++ &gmac1_rgmii_bus>; ++ pinctrl-names = "default"; ++ tx_delay = <0x3a>; ++ status = "okay"; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ /* RTL8211F */ ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <0x1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8211f_rst>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ rtl8211f { ++ rtl8211f_rst: rtl8211f-rst { ++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ max-frequency = <200000000>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.1/052-02-v6.3-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5a.patch b/target/linux/rockchip/patches-6.1/052-02-v6.3-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5a.patch new file mode 100644 index 0000000000..917b846088 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/052-02-v6.3-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5a.patch @@ -0,0 +1,28 @@ +From 991f136c9f8de181b25cef056ab5fe7f49413919 Mon Sep 17 00:00:00 2001 +From: Christopher Obbard +Date: Tue, 10 Jan 2023 19:53:50 +0000 +Subject: [PATCH] arm64: dts: rockchip: Update sdhci alias for rock-5a + +In the previous version, the sdhci alias was set to mmc1: an artifact +leftover from the port from vendor kernel. Update the alias to mmc0 to +match the device's boot order. + +Fixes: a4a8f1afb360 ("arm64: dts: rockchip: Add rock-5a board") +Signed-off-by: Christopher Obbard +Link: https://lore.kernel.org/r/20230110195352.272360-2-chris.obbard@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -11,7 +11,7 @@ + compatible = "radxa,rock-5a", "rockchip,rk3588s"; + + aliases { +- mmc1 = &sdhci; ++ mmc0 = &sdhci; + serial2 = &uart2; + }; + diff --git a/target/linux/rockchip/patches-6.1/052-03-v6.3-arm64-dts-rockchip-Fix-RX-delay-for-ethernet-phy-on.patch b/target/linux/rockchip/patches-6.1/052-03-v6.3-arm64-dts-rockchip-Fix-RX-delay-for-ethernet-phy-on.patch new file mode 100644 index 0000000000..40d11bada3 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/052-03-v6.3-arm64-dts-rockchip-Fix-RX-delay-for-ethernet-phy-on.patch @@ -0,0 +1,37 @@ +From cda0c2ea65a0ffbe75caae9acbf78b2bb825a6bd Mon Sep 17 00:00:00 2001 +From: Lucas Tanure +Date: Fri, 13 Jan 2023 13:02:20 +0000 +Subject: [PATCH] arm64: dts: rockchip: Fix RX delay for ethernet phy on + rk3588s-rock5a + +Add network PHY rx delay and change type to rgmii, so +that it is applied. This fixes packet loss when more +than a few packets are exchanged. + +Fixes: d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board") +Signed-off-by: Lucas Tanure +Link: https://lore.kernel.org/r/20230113130220.662194-1-lucas.tanure@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -23,7 +23,7 @@ + &gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; +- phy-mode = "rgmii-rxid"; ++ phy-mode = "rgmii"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 +@@ -31,6 +31,7 @@ + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x3a>; ++ rx_delay = <0x3e>; + status = "okay"; + }; + diff --git a/target/linux/rockchip/patches-6.1/053-01-v6.3-arm64-dts-rockchip-Add-rock-5b-board.patch b/target/linux/rockchip/patches-6.1/053-01-v6.3-arm64-dts-rockchip-Add-rock-5b-board.patch new file mode 100644 index 0000000000..a311c90134 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-01-v6.3-arm64-dts-rockchip-Add-rock-5b-board.patch @@ -0,0 +1,78 @@ +From a1d3281450ab24108631a8b0f7cd9f27de717e0e Mon Sep 17 00:00:00 2001 +From: Christopher Obbard +Date: Mon, 9 Jan 2023 16:58:01 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add rock-5b board + +Add board file for the RK3588 Rock 5B board. This is a basic +implementation which just brings up the eMMC and UART which is +enough to successfully boot Linux. + +The ethernet controller is connected via PCIe so support will +come in a follow-up patch. + +Signed-off-by: Christopher Obbard +Reviewed-by: Michael Riesch +Signed-off-by: Sebastian Reichel +Link: https://lore.kernel.org/r/20230109155801.51642-8-sebastian.reichel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3588-rock-5b.dts | 44 +++++++++++++++++++ + 2 files changed, 45 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -81,4 +81,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-na + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -0,0 +1,44 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3588.dtsi" ++ ++/ { ++ model = "Radxa ROCK 5 Model B"; ++ compatible = "radxa,rock-5b", "rockchip,rk3588"; ++ ++ aliases { ++ mmc1 = &sdhci; ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ max-frequency = <200000000>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.1/053-02-v6.3-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5b.patch b/target/linux/rockchip/patches-6.1/053-02-v6.3-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5b.patch new file mode 100644 index 0000000000..a73cf43c37 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-02-v6.3-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5b.patch @@ -0,0 +1,28 @@ +From 6fb13f888f2a6155fe4c19d14721e8909eda9b52 Mon Sep 17 00:00:00 2001 +From: Christopher Obbard +Date: Tue, 10 Jan 2023 19:53:52 +0000 +Subject: [PATCH] arm64: dts: rockchip: Update sdhci alias for rock-5b + +In the previous version, the sdhci alias was set to mmc1: an artifact +leftover from the port from vendor kernel. Update the alias to mmc0 to +match the device's boot order. + +Fixes: 6fb2d1549786 ("arm64: dts: rockchip: Add rock-5b board") +Signed-off-by: Christopher Obbard +Link: https://lore.kernel.org/r/20230110195352.272360-4-chris.obbard@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -9,7 +9,7 @@ + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + aliases { +- mmc1 = &sdhci; ++ mmc0 = &sdhci; + serial2 = &uart2; + }; + diff --git a/target/linux/rockchip/patches-6.1/053-03-v6.4-arm64-dts-rockchip-Enable-RTC-support-for-Rock-5B.patch b/target/linux/rockchip/patches-6.1/053-03-v6.4-arm64-dts-rockchip-Enable-RTC-support-for-Rock-5B.patch new file mode 100644 index 0000000000..2ba21a1203 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-03-v6.4-arm64-dts-rockchip-Enable-RTC-support-for-Rock-5B.patch @@ -0,0 +1,49 @@ +From 1e9c2404d8870ec08bfc338ae7113c3f7fe0b171 Mon Sep 17 00:00:00 2001 +From: Shreeya Patel +Date: Wed, 5 Apr 2023 13:57:11 +0530 +Subject: [PATCH] arm64: dts: rockchip: Enable RTC support for Rock 5B + +Add DT node to enable RTC support for Rock 5B board. + +Signed-off-by: Shreeya Patel +Reviewed-by: Christopher Obbard +Link: https://lore.kernel.org/r/20230405082711.46303-1-shreeya.patel@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -27,6 +27,31 @@ + }; + }; + ++&i2c6 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ + &sdhci { + bus-width = <8>; + no-sdio; diff --git a/target/linux/rockchip/patches-6.1/053-04-v6.4-arm64-dts-rockchip-Add-pwm-fan-to-rk3588-rock-5b.patch b/target/linux/rockchip/patches-6.1/053-04-v6.4-arm64-dts-rockchip-Add-pwm-fan-to-rk3588-rock-5b.patch new file mode 100644 index 0000000000..5caffba95b --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-04-v6.4-arm64-dts-rockchip-Add-pwm-fan-to-rk3588-rock-5b.patch @@ -0,0 +1,44 @@ +From f36bb17653e4b9e26bbdb1224027d20614e77636 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Tue, 4 Apr 2023 20:38:07 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add pwm-fan to rk3588-rock-5b + +Add the necessary DT changes for the Rock 5B board to enable support for +the PWM controlled heat sink fan. + +Signed-off-by: Cristian Ciocaltea +Reviewed-by: Christopher Obbard +Link: https://lore.kernel.org/r/20230404173807.490520-3-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -17,6 +17,14 @@ + stdout-path = "serial2:1500000n8"; + }; + ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 95 145 195 255>; ++ fan-supply = <&vcc5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ #cooling-cells = <2>; ++ }; ++ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -52,6 +60,10 @@ + }; + }; + ++&pwm1 { ++ status = "okay"; ++}; ++ + &sdhci { + bus-width = <8>; + no-sdio; diff --git a/target/linux/rockchip/patches-6.1/053-05-v6.4-arm64-dts-rockchip-Add-rk3588-rock-5b-analog-audio.patch b/target/linux/rockchip/patches-6.1/053-05-v6.4-arm64-dts-rockchip-Add-rk3588-rock-5b-analog-audio.patch new file mode 100644 index 0000000000..c50dfc185f --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-05-v6.4-arm64-dts-rockchip-Add-rk3588-rock-5b-analog-audio.patch @@ -0,0 +1,106 @@ +From 55529fe3f32d8c2fdb70981f2e151735e090a1e0 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Sun, 2 Apr 2023 12:50:54 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add rk3588-rock-5b analog audio + +Add the necessary DT nodes for the Rock 5B board to enable the analog +audio support provided by the Everest Semi ES8316 codec. + +Signed-off-by: Cristian Ciocaltea +Reviewed-by: Christopher Obbard +Link: https://lore.kernel.org/r/20230402095054.384739-6-cristian.ciocaltea@collabora.com +[adapted to the fan addition I applied slightly earlier] +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 60 +++++++++++++++++++ + 1 file changed, 60 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -2,6 +2,7 @@ + + /dts-v1/; + ++#include + #include "rk3588.dtsi" + + / { +@@ -25,6 +26,23 @@ + #cooling-cells = <2>; + }; + ++ sound { ++ compatible = "audio-graph-card"; ++ label = "Analog"; ++ ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ dais = <&i2s0_8ch_p0>; ++ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ }; ++ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -52,12 +70,54 @@ + }; + }; + ++&i2c7 { ++ status = "okay"; ++ ++ es8316: es8316@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &pwm1 { diff --git a/target/linux/rockchip/patches-6.1/053-06-v6.4-arm64-dts-rockchip-Drop-RTC-clock-frequency-on.patch b/target/linux/rockchip/patches-6.1/053-06-v6.4-arm64-dts-rockchip-Drop-RTC-clock-frequency-on.patch new file mode 100644 index 0000000000..51ac86ad23 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-06-v6.4-arm64-dts-rockchip-Drop-RTC-clock-frequency-on.patch @@ -0,0 +1,32 @@ +From d7f5e83913d1bcd50968972a7b50e49c9a14b2af Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Fri, 14 Apr 2023 15:54:23 +0300 +Subject: [PATCH] arm64: dts: rockchip: Drop RTC clock-frequency on + rk3588-rock-5b + +The hym8563 RTC driver doesn't handle the 'clock-frequency' property, +which is also indicated by the following dtbs_check warning: + + rk3588-rock-5b.dtb: rtc@51: Unevaluated properties are not allowed ('clock-frequency' was unexpected) + From schema: Documentation/devicetree/bindings/rtc/haoyu,hym8563.yaml + +Drop the unsupported property. + +Fixes: 1e9c2404d887 ("arm64: dts: rockchip: Enable RTC support for Rock 5B") +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230414125425.124994-2-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -60,7 +60,6 @@ + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; +- clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; diff --git a/target/linux/rockchip/patches-6.1/053-07-v6.4-arm64-dts-rockchip-Use-generic-name-for-es8316-on-Pineboo.patch b/target/linux/rockchip/patches-6.1/053-07-v6.4-arm64-dts-rockchip-Use-generic-name-for-es8316-on-Pineboo.patch new file mode 100644 index 0000000000..1c7dd407ea --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-07-v6.4-arm64-dts-rockchip-Use-generic-name-for-es8316-on-Pineboo.patch @@ -0,0 +1,39 @@ +From 0af7164cb0e076dbfeed28956658a1ad94bd5927 Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Fri, 14 Apr 2023 15:54:24 +0300 +Subject: [PATCH] arm64: dts: rockchip: Use generic name for es8316 on Pinebook + Pro and Rock 5B + +Use generic 'audio-codec' name for es8316 node on Pinebook Pro and Rock +5B boards. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230414125425.124994-3-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -675,7 +675,7 @@ + i2c-scl-rising-time-ns = <168>; + status = "okay"; + +- es8316: es8316@11 { ++ es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -72,7 +72,7 @@ + &i2c7 { + status = "okay"; + +- es8316: es8316@11 { ++ es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; diff --git a/target/linux/rockchip/patches-6.1/053-08-v6.4-arm64-dts-rockchip-Add-vdd_cpu_big-regulators-to.patch b/target/linux/rockchip/patches-6.1/053-08-v6.4-arm64-dts-rockchip-Add-vdd_cpu_big-regulators-to.patch new file mode 100644 index 0000000000..3aff5a2f29 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/053-08-v6.4-arm64-dts-rockchip-Add-vdd_cpu_big-regulators-to.patch @@ -0,0 +1,84 @@ +From 1bb69cd4a344299a382695a2de1a84c0b23fe6da Mon Sep 17 00:00:00 2001 +From: Cristian Ciocaltea +Date: Fri, 14 Apr 2023 15:54:25 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add vdd_cpu_big regulators to + rk3588-rock-5b + +The RK8602 and RK8603 voltage regulators on the Rock 5B board provide +the power lines vdd_cpu_big0 and vdd_cpu_big1, respectively. + +Add the necessary device tree nodes and bind them to the corresponding +CPU big core nodes. + +Signed-off-by: Cristian Ciocaltea +Link: https://lore.kernel.org/r/20230414125425.124994-4-cristian.ciocaltea@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 56 +++++++++++++++++++ + 1 file changed, 56 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -53,6 +53,62 @@ + }; + }; + ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ + &i2c6 { + status = "okay"; + diff --git a/target/linux/rockchip/patches-6.1/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch b/target/linux/rockchip/patches-6.1/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch index 9527d80716..e9e7dd54ea 100644 --- a/target/linux/rockchip/patches-6.1/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch +++ b/target/linux/rockchip/patches-6.1/802-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch @@ -180,7 +180,7 @@ Signed-off-by: hmz007 GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h -@@ -418,7 +418,8 @@ struct clk *rockchip_clk_register_mmc(co +@@ -486,7 +486,8 @@ struct clk *rockchip_clk_register_mmc(co * DDRCLK flags, including method of setting the rate * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. */