From f450acefb00c699ff5cda26d6611277838eca9bc Mon Sep 17 00:00:00 2001 From: Marty Jones Date: Mon, 11 Jan 2021 18:35:29 -0500 Subject: [PATCH] uboot-rockchip: update to v2021.01 Update the U-Boot to version v2021.01. Run-tested: FriendlyARM NanoPi R2S Radxa Rock Pi 4 Pine64 RockPro64 Signed-off-by: Marty Jones [format commit message] Signed-off-by: David Bauer Signed-off-by: CN_SZTL --- package/boot/uboot-rockchip/Makefile | 4 +- ...-spl-remove-dtoc-of-pdata-generation.patch | 2 +- ...Add-support-for-FriendlyARM-NanoPi-R.patch | 15 +- .../nanopi-r2s-rk3328/dt-platdata.c | 222 +++++++++--------- .../nanopi-r2s-rk3328/dt-structs-gen.h | 6 - 5 files changed, 127 insertions(+), 122 deletions(-) diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 31299e9da0..6253679834 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2020.10 +PKG_VERSION:=2021.01 PKG_RELEASE:=1 -PKG_HASH:=0d481bbdc05c0ee74908ec2f56a6daa53166cc6a78a0e4fac2ac5d025770a622 +PKG_HASH:=b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454 PKG_MAINTAINER:=Tobias Maedel diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch index 4161c46ce2..bd401103ea 100644 --- a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch +++ b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch @@ -17,7 +17,7 @@ Signed-off-by: David Bauer --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl -@@ -320,12 +320,6 @@ PHONY += dts_dir +@@ -321,12 +321,6 @@ PHONY += dts_dir dts_dir: $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index e8b1c9b67d..60416a6880 100644 --- a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -1,6 +1,6 @@ -From 82cab423557470769a14fd3d1258cb02ec5b052b Mon Sep 17 00:00:00 2001 +From 4189a8db90ca7edc16cf9509576ca2e74f028c1c Mon Sep 17 00:00:00 2001 From: David Bauer -Date: Fri, 10 Jul 2020 14:58:30 +0200 +Date: Thu, 7 Jan 2021 00:05:46 +0100 Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S This adds support for the NanoPi R2S from FriendlyArm. @@ -20,15 +20,15 @@ Signed-off-by: David Bauer arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 40 +++ arch/arm/dts/rk3328-nanopi-r2s.dts | 370 +++++++++++++++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 7 + - configs/nanopi-r2s-rk3328_defconfig | 99 ++++++ - 5 files changed, 517 insertions(+) + configs/nanopi-r2s-rk3328_defconfig | 98 ++++++ + 5 files changed, 516 insertions(+) create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts create mode 100644 configs/nanopi-r2s-rk3328_defconfig --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ +@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ @@ -470,7 +470,7 @@ Signed-off-by: David Bauer M: Chen-Yu Tsai --- /dev/null +++ b/configs/nanopi-r2s-rk3328_defconfig -@@ -0,0 +1,99 @@ +@@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 @@ -485,7 +485,7 @@ Signed-off-by: David Bauer +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SMBIOS_PRODUCT_NAME="nanopi_r2s_rk3328" ++CONFIG_SYSINFO=y +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set @@ -569,4 +569,3 @@ Signed-off-by: David Bauer +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -+CONFIG_SMBIOS_MANUFACTURER="pine64" diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c index a931ab7924..17e1e302a5 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c @@ -4,19 +4,14 @@ * This file was generated by dtoc from a .dtb (device tree binary) file. */ +/* Allow use of U_BOOT_DEVICE() in this file */ +#define DT_PLATDATA_C + #include #include #include -static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DEVICE(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .platdata = &dtv_syscon_at_ff100000, - .platdata_size = sizeof(dtv_syscon_at_ff100000), -}; - +/* Node /clock-controller@ff440000 index 0 */ static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { .reg = {0xff440000, 0x1000}, .rockchip_grf = 0x3a, @@ -25,97 +20,10 @@ U_BOOT_DEVICE(clock_controller_at_ff440000) = { .name = "rockchip_rk3328_cru", .platdata = &dtv_clock_controller_at_ff440000, .platdata_size = sizeof(dtv_clock_controller_at_ff440000), + .parent_idx = -1, }; -static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {NULL, {40}}, - {NULL, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DEVICE(serial_at_ff130000) = { - .name = "ns16550_serial", - .platdata = &dtv_serial_at_ff130000, - .platdata_size = sizeof(dtv_serial_at_ff130000), -}; - -static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_sd_highspeed = true, - .clocks = { - {NULL, {317}}, - {NULL, {33}}, - {NULL, {74}}, - {NULL, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .sd_uhs_sdr104 = true, - .sd_uhs_sdr12 = true, - .sd_uhs_sdr25 = true, - .sd_uhs_sdr50 = true, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DEVICE(mmc_at_ff500000) = { - .name = "rockchip_rk3288_dw_mshc", - .platdata = &dtv_mmc_at_ff500000, - .platdata_size = sizeof(dtv_mmc_at_ff500000), -}; - -static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { - .ranges = true, - .rockchip_grf = 0x3a, -}; -U_BOOT_DEVICE(pinctrl) = { - .name = "rockchip_rk3328_pinctrl", - .platdata = &dtv_pinctrl, - .platdata_size = sizeof(dtv_pinctrl), -}; - -static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { - .clocks = { - {NULL, {200}},}, - .gpio_controller = true, - .interrupt_controller = true, - .interrupts = {0x0, 0x33, 0x4}, - .reg = {0xff210000, 0x100}, -}; -U_BOOT_DEVICE(gpio0_at_ff210000) = { - .name = "rockchip_gpio_bank", - .platdata = &dtv_gpio0_at_ff210000, - .platdata_size = sizeof(dtv_gpio0_at_ff210000), -}; - -static struct dtd_regulator_fixed dtv_sdmmc_regulator = { - .gpio = {0x61, 0x1e, 0x1}, - .pinctrl_0 = 0x67, - .pinctrl_names = "default", - .regulator_boot_on = true, - .regulator_max_microvolt = 0x325aa0, - .regulator_min_microvolt = 0x325aa0, - .regulator_name = "vcc_sd", - .vin_supply = 0x1c, -}; -U_BOOT_DEVICE(sdmmc_regulator) = { - .name = "regulator_fixed", - .platdata = &dtv_sdmmc_regulator, - .platdata_size = sizeof(dtv_sdmmc_regulator), -}; - +/* Node /dmc index 1 */ static struct dtd_rockchip_rk3328_dmc dtv_dmc = { .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, 0xff720000, 0x1000, 0xff798000, 0x1000}, @@ -149,14 +57,118 @@ U_BOOT_DEVICE(dmc) = { .name = "rockchip_rk3328_dmc", .platdata = &dtv_dmc, .platdata_size = sizeof(dtv_dmc), + .parent_idx = -1, +}; + +/* Node /pinctrl/gpio0@ff210000 index 2 */ +static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { + .clocks = { + {0, {200}},}, + .gpio_controller = true, + .interrupt_controller = true, + .interrupts = {0x0, 0x33, 0x4}, + .reg = {0xff210000, 0x100}, +}; +U_BOOT_DEVICE(gpio0_at_ff210000) = { + .name = "rockchip_gpio_bank", + .platdata = &dtv_gpio0_at_ff210000, + .platdata_size = sizeof(dtv_gpio0_at_ff210000), + .parent_idx = 4, +}; + +/* Node /mmc@ff500000 index 3 */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_sd_highspeed = true, + .clocks = { + {0, {317}}, + {0, {33}}, + {0, {74}}, + {0, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .sd_uhs_sdr104 = true, + .sd_uhs_sdr12 = true, + .sd_uhs_sdr25 = true, + .sd_uhs_sdr50 = true, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x4b, + .vqmmc_supply = 0x1e, +}; +U_BOOT_DEVICE(mmc_at_ff500000) = { + .name = "rockchip_rk3288_dw_mshc", + .platdata = &dtv_mmc_at_ff500000, + .platdata_size = sizeof(dtv_mmc_at_ff500000), + .parent_idx = -1, +}; + +/* Node /pinctrl index 4 */ +static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { + .ranges = true, + .rockchip_grf = 0x3a, +}; +U_BOOT_DEVICE(pinctrl) = { + .name = "rockchip_rk3328_pinctrl", + .platdata = &dtv_pinctrl, + .platdata_size = sizeof(dtv_pinctrl), + .parent_idx = -1, +}; + +/* Node /sdmmc-regulator index 5 */ +static struct dtd_regulator_fixed dtv_sdmmc_regulator = { + .gpio = {0x61, 0x1e, 0x1}, + .pinctrl_0 = 0x67, + .pinctrl_names = "default", + .regulator_boot_on = true, + .regulator_max_microvolt = 0x325aa0, + .regulator_min_microvolt = 0x325aa0, + .regulator_name = "vcc_sd", + .vin_supply = 0x1c, +}; +U_BOOT_DEVICE(sdmmc_regulator) = { + .name = "regulator_fixed", + .platdata = &dtv_sdmmc_regulator, + .platdata_size = sizeof(dtv_sdmmc_regulator), + .parent_idx = -1, +}; + +/* Node /serial@ff130000 index 6 */ +static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {0, {40}}, + {0, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x26, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DEVICE(serial_at_ff130000) = { + .name = "ns16550_serial", + .platdata = &dtv_serial_at_ff130000, + .platdata_size = sizeof(dtv_serial_at_ff130000), + .parent_idx = -1, +}; + +/* Node /syscon@ff100000 index 7 */ +static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DEVICE(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .platdata = &dtv_syscon_at_ff100000, + .platdata_size = sizeof(dtv_syscon_at_ff100000), + .parent_idx = -1, }; void dm_populate_phandle_data(void) { - dtv_serial_at_ff130000.clocks[0].node = DM_GET_DEVICE(clock_controller_at_ff440000); - dtv_serial_at_ff130000.clocks[1].node = DM_GET_DEVICE(clock_controller_at_ff440000); - dtv_mmc_at_ff500000.clocks[0].node = DM_GET_DEVICE(clock_controller_at_ff440000); - dtv_mmc_at_ff500000.clocks[1].node = DM_GET_DEVICE(clock_controller_at_ff440000); - dtv_mmc_at_ff500000.clocks[2].node = DM_GET_DEVICE(clock_controller_at_ff440000); - dtv_mmc_at_ff500000.clocks[3].node = DM_GET_DEVICE(clock_controller_at_ff440000); - dtv_gpio0_at_ff210000.clocks[0].node = DM_GET_DEVICE(clock_controller_at_ff440000); } diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h index 22efe0d247..847b121a34 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h @@ -69,9 +69,3 @@ struct dtd_rockchip_rk3328_pinctrl { bool ranges; fdt32_t rockchip_grf; }; -#define dtd_syscon dtd_rockchip_rk3328_cru -#define dtd_simple_mfd dtd_rockchip_rk3328_grf -#define dtd_rockchip_rk3328_uart dtd_ns16550_serial -#define dtd_snps_dw_apb_uart dtd_ns16550_serial -#define dtd_rockchip_cru dtd_rockchip_rk3328_cru -#define dtd_rockchip_rk3328_dw_mshc dtd_rockchip_rk3288_dw_mshc