diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 63497ccaf3..d8b1109f2d 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -184,6 +184,13 @@ define U-Boot/nanopi-r5s-rk3568 friendlyarm_nanopi-r5s endef +define U-Boot/photonicat-rk3568 + $(U-Boot/Default/rk3568) + NAME:=Ariaboard Photonicat + BUILD_DEVICES:= \ + ariaboard_photonicat +endef + define U-Boot/roc-pc-rk3568 $(U-Boot/Default/rk3568) NAME:=Station P2 @@ -211,6 +218,7 @@ UBOOT_TARGETS := \ mrkaio-m68s-rk3568 \ nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 \ + photonicat-rk3568 \ roc-pc-rk3568 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch b/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch index 7d2161ae42..b467f48f72 100644 --- a/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch +++ b/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch @@ -12,8 +12,6 @@ Signed-off-by: Lu jicong arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi -index 17201bcf41..8b6c9059ab 100644 --- a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi @@ -4,4 +4,4 @@ diff --git a/package/boot/uboot-rockchip/patches/200-add-photonicat-board-watchdog-support.patch b/package/boot/uboot-rockchip/patches/200-add-photonicat-board-watchdog-support.patch new file mode 100644 index 0000000000..204e82010b --- /dev/null +++ b/package/boot/uboot-rockchip/patches/200-add-photonicat-board-watchdog-support.patch @@ -0,0 +1,20 @@ +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -47,3 +47,4 @@ obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt + obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o + obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o + obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o ++obj-$(CONFIG_WDT_PCAT) += pcat_wdt.o +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -399,4 +399,10 @@ config WDT_FTWDT010 + help + Faraday Technology ftwdt010 watchdog is an architecture independent + watchdog. It is usually used in SoC chip design. ++ ++config WDT_PCAT ++ bool "photonicat board watchdog support" ++ depends on WDT && SERIAL && DM ++ help ++ Select this to enable watchdog timer on photonicat board. + endmenu diff --git a/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch b/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch index ae633e8758..d141752dda 100644 --- a/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch +++ b/package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch @@ -28,7 +28,7 @@ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ rk3399-pinephone-pro.dtb \ -@@ -169,6 +175,12 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ +@@ -169,6 +175,13 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ @@ -37,6 +37,7 @@ + rk3568-mrkaio-m68s.dtb \ + rk3568-nanopi-r5c.dtb \ + rk3568-nanopi-r5s.dtb \ ++ rk3568-photonicat.dtb \ + rk3568-roc-pc.dtb \ rk3568-rock-3a.dtb diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat-u-boot.dtsi new file mode 100644 index 0000000000..c43b03fe70 --- /dev/null +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&gpio0 { + bootph-pre-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + clock-frequency = <24000000>; + bootph-all; + status = "okay"; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat.dts new file mode 100644 index 0000000000..126835bac0 --- /dev/null +++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-photonicat.dts @@ -0,0 +1,572 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Ariaboard Photonicat"; + compatible = "ariaboard,photonicat", "rockchip,rk3568"; + + aliases { + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + timeout-ms = <3000>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + modem-rfkill { + compatible = "rfkill-gpio"; + label = "modem-rfkill"; + radio-type = "wwan"; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + pcat-wdt { + compatible = "linux,wdt-pcat"; + port = <&uart4>; + status = "okay"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &clk32k_out1>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + vcc_sysin: vcc-sysin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_syson: vcc-syson-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_syson"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcc_1v8: vcc-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c: vcc3v3-pi6c-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pi6c"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + /* actually fed by vcc_syson, dependent on pi6c clock generator */ + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c>; + }; + + vcc3v3_sd: vcc3v3-sd-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc5v0_boost: vcc5v0-boost-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_boost_en>; + regulator-name = "vcc5v0_boost"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcca_1v8: vcca-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdda_0v9: vdda-0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_gpu: vdd-gpu-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_syson>; + }; + + vdd_logic: vdd-logic-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_syson>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_syson>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&pcie30phy { + phy-supply = <&vcc3v3_pi6c>; + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_boost_en: vcc5v0-boost-en { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc-sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = ; + interrupt-names = "host-wake"; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "qcom,qca9377-bt"; + enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "lpo"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&xin32k { + pinctrl-names = "default"; + pinctrl-0 = <&clk32k_out1>; +}; diff --git a/package/boot/uboot-rockchip/src/configs/photonicat-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/photonicat-rk3568_defconfig new file mode 100644 index 0000000000..cdcb98b3f5 --- /dev/null +++ b/package/boot/uboot-rockchip/src/configs/photonicat-rk3568_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-photonicat" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-photonicat.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_WARN=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_RESET_SCMI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_PCAT=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/src/drivers/watchdog/pcat_wdt.c b/package/boot/uboot-rockchip/src/drivers/watchdog/pcat_wdt.c new file mode 100644 index 0000000000..292b9d4b8b --- /dev/null +++ b/package/boot/uboot-rockchip/src/drivers/watchdog/pcat_wdt.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include + +struct pcat_wdt_priv { + struct udevice *serial_dev; + struct dm_serial_ops *serial_ops; + uint16_t packet_count; +}; + +static uint16_t pcat_pmu_serial_compute_crc16(const uint8_t *data, + size_t len) +{ + uint16_t crc = 0xFFFF; + size_t i; + unsigned int j; + + for(i=0;i> 1) ^ 0xA001; + } else { + crc >>= 1; + } + } + } + + return crc; +} + +static int pcat_wdt_reset(struct udevice *dev) +{ + struct pcat_wdt_priv *priv = dev_get_priv(dev); + uint8_t packet[13] = "\xA5\x01\x81\x00\x00\x03\x00\x01\x00" + "\x00\x00\x00\x5A"; + uint16_t crc; + int err = 0; + unsigned int i; + + packet[3] = priv->packet_count & 0xFF; + packet[4] = (priv->packet_count >> 8) & 0xFF; + priv->packet_count++; + + crc = pcat_pmu_serial_compute_crc16(packet+1, 9); + packet[10] = crc & 0xFF; + packet[11] = (crc >> 8)& 0xFF; + + i = 0; + while(i < 13) { + err = priv->serial_ops->putc( + priv->serial_dev, ((const char *)packet)[i]); + if(!err) { + i++; + } else if(err==-EAGAIN) { + ; + } else { + pr_err("%s: unable to send watchdog setup " + "request: %d\n", __func__, err); + break; + } + } + + return err; +} + +static int pcat_wdt_setup(struct pcat_wdt_priv *priv, u64 timeout) { + uint8_t packet[16] = "\xA5\x01\x81\x00\x00\x06\x00\x13\x00" + "\x3C\x3C\x00\x00\x00\x00\x5A"; + uint16_t crc; + int err = 0; + unsigned int i; + + if(timeout > 255) { + pr_warn("%s: timeout cannot be more than 255s\n", + __func__); + timeout = 255; + } + + packet[3] = priv->packet_count & 0xFF; + packet[4] = (priv->packet_count >> 8) & 0xFF; + priv->packet_count++; + packet[11] = timeout & 0xFF; + + crc = pcat_pmu_serial_compute_crc16(packet+1, 12); + packet[13] = crc & 0xFF; + packet[14] = (crc >> 8)& 0xFF; + + i = 0; + while(i < 16) { + err = priv->serial_ops->putc( + priv->serial_dev, ((const char *)packet)[i]); + if(!err) { + i++; + } else if(err==-EAGAIN) { + ; + } else { + pr_err("%s: unable to send watchdog setup " + "request: %d\n", __func__, err); + break; + } + } + + return err; +} + +static int pcat_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct pcat_wdt_priv *priv = dev_get_priv(dev); + + pcat_wdt_setup(priv, timeout); + + return 0; +} + +static int pcat_wdt_stop(struct udevice *dev) +{ + struct pcat_wdt_priv *priv = dev_get_priv(dev); + + pcat_wdt_setup(priv, 0); + + return 0; +} + +static int dm_probe(struct udevice *dev) +{ + struct pcat_wdt_priv *priv = dev_get_priv(dev); + struct udevice *serial_dev = NULL; + struct dm_serial_ops *ops; + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_SERIAL, dev, "port", + &serial_dev); + if(ret) { + pr_err("%s: unable to find serial port device: %d\n", + __func__, ret); + return ret; + } + + ret = device_probe(serial_dev); + if(ret) { + pr_err("%s: unable to probe serial port device: %d\n", + __func__, ret); + return ret; + } + + ops = serial_get_ops(serial_dev); + if(!ops) { + printf("Cannot get ops for PMU serial port!\n"); + return -EINVAL; + } + + if(ops->setconfig) { + ops->setconfig(serial_dev, SERIAL_DEFAULT_CONFIG); + } + if(ops->setbrg) { + ops->setbrg(serial_dev, 115200); + } + + priv->serial_dev = serial_dev; + priv->serial_ops = ops; + priv->packet_count = 0; + + pcat_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops pcat_wdt_ops = { + .start = pcat_wdt_start, + .reset = pcat_wdt_reset, + .stop = pcat_wdt_stop, +}; + +static const struct udevice_id pcat_wdt_ids[] = { + { .compatible = "linux,wdt-pcat" }, + {} +}; + +U_BOOT_DRIVER(wdt_pcat) = { + .name = "wdt_pcat", + .id = UCLASS_WDT, + .of_match = pcat_wdt_ids, + .ops = &pcat_wdt_ops, + .probe = dm_probe, + .priv_auto = sizeof(struct pcat_wdt_priv), +};