Will be used for conversions in later commits and is a requirement for
PHY backports.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
[rmilecki: update commit message for 23.05]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
(cherry picked from commit 511c7ff032)
Ubiquiti Rocket M XW is a single-band, 2x2:2 external Wi-Fi AP, with optional
GPS receiver, with two external RP-SMA antenna connections, based on
AR9342 SoC. Two band variants exists, for 2.4GHz and 5GHz band, usable
with the same image.
Specs:
- CPU: Atheros AR9342 MIPS SoC at 535MHz
- RAM: 64MB DDR400
- ROM: 8MB SPI-NOR in SO16W package, MX25L6408E
- Wi-Fi Atheros AR9342 built-in 2x2:2 radio
- Ethernet: Atheros AR8035 PHY, limited to 100Mbps speeds due to
magnetics
- Power: 24V passive PoE input.
Installation: please refer to Ubiquiti Bullet M2HP for documentation.
The device runs with exactly same image as the Bullet, and after fixes
in preceding commit, is fully functional again. Add the alternative name
to the build system.
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit 54387fddead1094774187cedfe07cc8a47f5fe2c)
Since commit 6f2e1b7485 ("ath79: disable delays on AT803X config init")
Ubiquiti XW boards equipped with AR8035 PHY suffered from lack of
outbound traffic on the Ethernet port. This was caused by the fact, the
U-boot has set this during boot and it wasn't reset by the PHY driver,
and the corresponding setting in device tree was wrong.
Set the 'phy-mode = "rgmii-txid"' at the ð0, and drop this property
from PHY node, as it is not parsed there. This causes the device to
connect using Ethernet once again.
Fixes: db4b6535f8 ("ath79: Add support for Ubiquity Bullet M (XW)")
Fixes: 6f2e1b7485 ("ath79: disable delays on AT803X config init")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit a9b2ba4d7ba06e1ac4ff7da3eb9b4038b94d9fbb)
Onboard AR8035 PHY supports 1000Base-T operation, but onboard
Ethernet magnetics do not. Reduce advertised link speeds to 100Mbps and
lower.
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit d406777fb14c84e82f51bab059631af70cf6d5c9)
While flashing sysupgrade image from U-Boot, then the rootfs_data
overlay filesystem formatting is left for the fstools during firstboot,
but that wont work as mkfs.f2fs is missing in the sysupgrade image:
mount_root: overlay filesystem in /dev/loop0 has not been formatted yet
mount_root: no usable overlay filesystem found, using tmpfs overlay
sh: mkfs.f2fs: not found
Filesystem Size Used Available Use% Mounted on
/dev/loop0 139.6M 46.9M 92.6M 34% /overlay
Number Start (sector) End (sector) Size Code Name
20 98850 406349 150.1 MiB FFFF rootfs
So lets fix it by adding f2fs support to the sysupgrade image.
Signed-off-by: Petr Štetiar <ynezz@true.cz>
(cherry picked from commit ba415af570)
The original configuration might be copied from bcm2710 which uses
cortex A53 rather than A72 in BCM2711, without errata might be harmful
to system stability and security.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
(cherry picked from commit d549809c05)
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
The documentation links have changed and are no longer valid.
(cherry picked from commit 189838517e)
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Booting from non-MMC devices on Rockchip targets without this
change results in a boot failure:
Model: FriendlyElec NanoPi R5S
Net: eth0: ethernet@fe2a0000
Hit any key to stop autoboot: 0
** Booting bootflow 'nvme#0.blk#1.bootdev.part_1' with script
** No partition table - mmc 0 **
** No partition table - mmc 0 **
Couldn't find partition mmc 0:1
Can't set block device
Wrong Image Type for bootm command
ERROR -91: Protocol wrong type for socket: can't get kernel image!
Boot failed (err=1)
This change fixes the default boot script for Rockchip targets to
support booting from non-MMC devices such as NVMe or USB drives.
Some targets with only a boot rom (e.g. NanoPi R5S) may require u-boot
to be installed on the eMMC or a MicroSD card in order to boot from
non-MMC devices.
Fixes: #14420
Reviewed-by: Tianling Shen <cnsztl@immortalwrt.org>
Signed-off-by: Justin Klaassen <justin@tidylabs.app>
(cherry picked from commit 4d49ce1bde)
Kernel 5.15 introduced a significant change to spi-nor subsystem [1],
which would the SPI-NOR core to no longer unprotect the Flash chips if
their protection bits are non-volatile, which is the case for MX25L6405D
and MX25L12805D, used in Ubiquiti XW and WA lines of devices [2].
However, their bootloader forcibly enables this protection before
continuing to boot, making the kernel not unprotect the flash upon boot,
causing JFFS2 to be unable write to the filesystem. Because sysupgrade
seems to unlock the flash explicitly, the upgrade will work, but the
system will be unable to save configrationm showing the following symptom
in the kernel log:
[ 86.168016] jffs2_scan_eraseblock(): End of filesystem marker found at 0x0
[ 86.192344] jffs2_build_filesystem(): unlocking the mtd device...
[ 86.192443] done.
[ 86.200669] jffs2_build_filesystem(): erasing all blocks after the end marker...
[ 86.220646] jffs2: Newly-erased block contained word 0x19852003 at offset 0x001e0000
[ 86.292388] jffs2: Newly-erased block contained word 0x19852003 at offset 0x001d0000
[ 86.324867] jffs2: Newly-erased block contained word 0x19852003 at offset 0x001c0000
[ 86.355316] jffs2: Newly-erased block contained word 0x19852003 at offset 0x001b0000
[ 86.402855] jffs2: Newly-erased block contained word 0x19852003 at offset 0x001a0000
Disable the write protection unconditionally for ath79/generic subtarget,
so the XW and WA devices can function again. However, this is only a
stopgap solution - it probably should be investigated if there is a way
to selectively unlock the area used by rootfs_data - but given the lock
granularity, this seems unlikely.
With this patch in place, rootfs_data partition on my Nanostation Loco
M5 XW is writable again.
Fixes: #12882Fixes: #13750
Fixes: 579703f38c ("ath79: switch to 5.15 as default kernel")
Link: http://www.infradead.org/pipermail/linux-mtd/2020-October/082805.html
Link: https://forum.openwrt.org/t/powerbeam-m5-xw-configuration-loss-after-reboot/141925
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit f024f4b1b0)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
The current dts file of dgs-1210-10p doesn't support link states
for the sfp ports (they are always up).
This patch tries to give better support for this and was run tested
on dgs-1210-10p.
It was already commited to the main branch.
Signed-off-by: Michel Thill <jmthill@gmail.com>
(cherry picked from commit 135e107620)
This wireless driver seems broken and causes kernel hang up.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit ef03ac6684)
(based on support for ASUS RT-AX59U by liushiyou006)
SOC: MediaTek MT7986
RAM: 512MB DDR4
FLASH: 128MB SPI-NAND (Winbond W25N01GV)
WIFI: Mediatek MT7986 DBDC 802.11ax 2.4/5 GHz
ETH: MediaTek MT7531 Switch
UART: 3V3 115200 8N1 (Pinout silkscreened / Do not connect VCC)
Upgrade from AsusWRT to OpenWRT using UART
Download the OpenWrt initramfs image.
Copy the image to a TFTP server reachable at 192.168.1.70/24. Rename the image to rtax59u.bin.
Connect the PC with TFTP server to the RT-AX59U.
Set a static ip on the ethernet interface of your PC.
(ip address: 192.168.1.70, subnet mask:255.255.255.0)
Conect to the serial console, interrupt the autoboot process by pressing '4' when prompted.
Download & Boot the OpenWrt initramfs image.
$ setenv ipaddr 192.168.1.1
$ setenv serverip 192.168.1.70
$ tftpboot 0x46000000 rtax59u.bin
$ bootm 0x46000000
Wait for OpenWrt to boot. Transfer the sysupgrade image to the device using scp and install using sysupgrade.
$ sysupgrade -n <path-to-sysupgrade.bin>
Upgrade from AsusWRT to OpenWRT using WebUI
Download transit TRX file from https://drive.google.com/drive/folders/1A20QdjK7Udagu31FSszpWAk8-cGlCwsq
Upgrade firmware from WebUI (192.168.50.1) using downloaded TRX file
Wait for OpenWRT to boot (192.168.1.1).
Upgrade system with sysupgrade image using luci or uploading it through scp and executing sysupgrade command
MAC Address for WLAN 5g is not following the same algorithm as in AsusWRT.
We have increased by one the WLAN 5g to avoid collisions with other networks from WLAN 2g
when bit 28 is already set.
: Stock : OpenWrt
WLAN 2g (1) : C8:xx:xx:0D:xx:D4 : C8:xx:xx:0D:xx:D4
WLAN 2g (2) : : CA:xx:xx:0D:xx:D4
WLAN 2g (3) : : CE:xx:xx:0D:xx:D4
WLAN 5g (1) : CA:xx:xx:1D:xx:D4 : CA:xx:xx:1D:xx:D5
WLAN 5g (2) : : CE:xx:xx:1D:xx:D5
WLAN 5g (3) : : C2:xx:xx:1D:xx:D5
WLAN 2g (1) : 08:xx:xx:76:xx:BE : 08:xx:xx:76:xx:BE
WLAN 2g (2) : : 0A:xx:xx:76:xx:BE
WLAN 2g (3) : : 0E:xx:xx:76:xx:BE
WLAN 5g (1) : 0A:xx:xx:76:xx:BE : 0A:xx:xx:76:xx:BF
WLAN 5g (2) : : 0E:xx:xx:76:xx:BF
WLAN 5g (3) : : 02:xx:xx:76:xx:BF
Signed-off-by: Xavier Franquet <xavier@franquet.es>
(cherry picked from commit 782eb05008)
Enabling SMP on the xway target results in two issues:
* some danube chipset-based devices fail on boot,
* on devices based on the arx100 chipset, enabling smp
results in a degradation of NAT performance.
After these two issues are fixed, SMP can be re-enabled.
This reverts commit 084c20f6c5.
Fixes: #13934Fixes: #14283
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Fine tuning PR: openwrt/openwrt#14355 Ref: 5a82bb909b
("mediatek: GL-MT6000: Add missing LED state definitions")
As the only LED is using white in the stock firmware when the device is
running and blue for the bootloader I suggest following changes:
- Using blue for the BL and preinit+failsafe
- White for normal operation (like the original FW) and sysupgrade
With this changes it's clear by looking to the LED in which operation
mode the device is and a possible BL stuck can be seen easily.
Tested with [GL-MT6000](https://openwrt.org/toh/gl.inet/gl-mt6000).
Signed-off-by: Thomas Schröder <tschroeder_github@outlook.com>
Tested-by: Hannu Nyman <hannu.nyman@iki.fi>
(cherry picked from commit 4d7bac1dca)
Router Asus TUF AX6000 have second MaxLinear GPY211 PHY controller for 2.5Gb LAN port.
The 5'th LAN port have inverted status of the LED.
Based on the commit from main branch 90fbec8 we could set proper status of the LED.
Signed-off-by: Patryk Kowalczyk <patryk@kowalczyk.ws>
(cherry picked from commit b22539b5fe)
(based on support for ASUS RT-AX59U by liushiyou006)
SOC: MediaTek MT7986
RAM: 512MB DDR4
FLASH: 128MB SPI-NAND (Winbond W25N01GV)
WIFI: Mediatek MT7986 DBDC 802.11ax 2.4/5 GHz
ETH: MediaTek MT7531 Switch
UART: 3V3 115200 8N1 (Pinout silkscreened / Do not connect VCC)
Upgrade from AsusWRT to OpenWRT using UART
Download the OpenWrt initramfs image.
Copy the image to a TFTP server reachable at 192.168.1.70/24. Rename the image to rtax59u.bin.
Connect the PC with TFTP server to the RT-AX59U.
Set a static ip on the ethernet interface of your PC.
(ip address: 192.168.1.70, subnet mask:255.255.255.0)
Conect to the serial console, interrupt the autoboot process by pressing '4' when prompted.
Download & Boot the OpenWrt initramfs image.
$ setenv ipaddr 192.168.1.1
$ setenv serverip 192.168.1.70
$ tftpboot 0x46000000 rtax59u.bin
$ bootm 0x46000000
Wait for OpenWrt to boot. Transfer the sysupgrade image to the device using scp and install using sysupgrade.
$ sysupgrade -n <path-to-sysupgrade.bin>
Upgrade from AsusWRT to OpenWRT using WebUI
Download transit TRX file from https://drive.google.com/drive/folders/1A20QdjK7Udagu31FSszpWAk8-cGlCwsq
Upgrade firmware from WebUI (192.168.50.1) using downloaded TRX file
Wait for OpenWRT to boot (192.168.1.1).
Upgrade system with sysupgrade image using luci or uploading it through scp and executing sysupgrade command
MAC Address for WLAN 5g is not following the same algorithm as in AsusWRT.
We have increased by one the WLAN 5g to avoid collisions with other networks from WLAN 2g
when bit 28 is already set.
: Stock : OpenWrt
WLAN 2g (1) : C8:xx:xx:0D:xx:D4 : C8:xx:xx:0D:xx:D4
WLAN 2g (2) : : CA:xx:xx:0D:xx:D4
WLAN 2g (3) : : CE:xx:xx:0D:xx:D4
WLAN 5g (1) : CA:xx:xx:1D:xx:D4 : CA:xx:xx:1D:xx:D5
WLAN 5g (2) : : CE:xx:xx:1D:xx:D5
WLAN 5g (3) : : C2:xx:xx:1D:xx:D5
WLAN 2g (1) : 08:xx:xx:76:xx:BE : 08:xx:xx:76:xx:BE
WLAN 2g (2) : : 0A:xx:xx:76:xx:BE
WLAN 2g (3) : : 0E:xx:xx:76:xx:BE
WLAN 5g (1) : 0A:xx:xx:76:xx:BE : 0A:xx:xx:76:xx:BF
WLAN 5g (2) : : 0E:xx:xx:76:xx:BF
WLAN 5g (3) : : 02:xx:xx:76:xx:BF
Signed-off-by: Xavier Franquet <xavier@franquet.es>
(cherry picked from commit 782eb05008)
Read back the reset register in order to flush the cache. This fixes
spurious reboot hangs on TP-Link TL-WDR3600 and TL-WDR4300 with Zentel
DRAM chips.
This issue was fixed in the past, but switching to the reset-driver
specific implementation removed the cache barrier which was previously
implicitly added by reading back the register in question.
Link: https://github.com/freifunk-gluon/gluon/issues/2904
Link: https://github.com/openwrt/openwrt/issues/13043
Link: https://dev.archive.openwrt.org/ticket/17839
Link: f8a7bfe1cb2c ("MIPS: ath79: fix system restart")
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit 2fe8ecd880)
Hardware
--------
CPU: Qualcomm Atheros QCA9563
RAM: 128M DDR2
FLASH: 16MB SPI-NOR
WiFi: Qualcomm Atheros QCA9563 2x2:2 802.11n 2.4GHz
Qualcomm Atheros QCA9880 2x2:2 802.11ac 5GHz
Antennas
--------
The device features internal antennas as well as external antenna
connectors. By default, the internal antennas are used.
Two GPIOs are exported by name, which can be used to control the
antenna-path mux. Writing a logical 0 enables the external antenna
connectors.
Installation
------------
1. Download the OpenWrt sysupgrade image to the device. You can use scp
for this task. The default username and password are "ubnt" and the
device is reachable at 192.168.1.20.
$ scp -O openwrt-sysupgrade.bin ubnt@192.168.1.20:/tmp/firmware.bin
2. Connect to the device using SSH.
$ ssh ubnt@192.168.1.20
3. Disable the write-protect
$ echo "5edfacbf" > /proc/ubnthal/.uf
4. Verify kernel0 and kernel1 match mtd2 and mtd3
$ cat /proc/mtd
5. Write the sysupgrade image to kernel0 and kernel1
$ dd if=/tmp/firmware.bin of=/dev/mtdblock2
$ dd if=/tmp/firmware.bin of=/dev/mtdblock3
6. Write the bootselect flag to boot from kernel0
$ dd if=/dev/zero bs=1 count=1 of=/dev/mtd4
7. Reboot the device
$ reboot
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit bf94e0a383)
This allows us to embrace alphabetical sorting for the UK-Ultra.
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit c9e58f85f6)
Setting/clearing bits on the first byte of the mac address causes collisions
when using multiple SSIDs on both PHYs. Change the allocation to alter the
last byte instead.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
(cherry picked from commit 38bec08e87)
Adjust LED names and provide the OpenWrt status indicator aliases
to actually use LEDs by the OpenWrt boot & sysupgrade processes.
* Name both LEDs clearly by the color
* Add the missing OpenWrt LED status indicator aliases and
remove the now unnecessary default status from blue LED
After this commit, the LEDs are used as:
* bootloader, really early Linux boot: blue LED is on
* preinit/failsafe: white LED blinks rapidly
* late boot: white LED blinks slowly
* boot completed, running normally: blue LED is on
* sysupgrade: white LED blinks
Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
(cherry picked from commit 5a82bb909b)
The COVR-X1860 are MT7621-based AX1800 devices (similar to DAP-X1860, but
with two Ethernet ports and external power supply) that are sold in sets
of two (COVR-X1862) and three (COVR-X1863).
Specification:
- MT7621
- MT7915 + MT7975 2x2 802.11ax (DBDC)
- 256MB RAM
- 128 MB flash
- 3 LEDs (red, orange, white), routed to one indicator in the top of the device
- 2 buttons (WPS in the back and Reset at the bottom of the device)
MAC addresses:
- LAN MAC (printed on the device) is stored in config2 partition as ASCII (entry factory_mac=xx:xx:xx:xx:xx:xx)
- WAN MAC: LAN MAC + 3
- 2.4G MAC: LAN MAC + 1
- 5G MAC: LAN MAC + 2
The pins for the serial console are already labeled on the board (VCC, TX, RX, GND). Serial settings: 3.3V, 115200,8n1
Flashing via OEM Web Interface:
- Download openwrt-ramips-mt7621-dlink_covr-x1860-a1-squashfs-factory.bin via the OEM web interface firmware update
- The configuration wizard can be skipped by directly going to http://192.168.0.1/UpdateFirmware_Simple.html
Flashing via Recovery Web Interface:
- Set your IP address to 192.168.0.10, subnetmask 255.255.255.0
- Press the reset button while powering on the deivce
- Keep the reset button pressed until the status LED blinks red
- Open a Chromium based browser and goto http://192.168.0.1
- Download openwrt-ramips-mt7621-dlink_covr-x1860-a1-squashfs-recovery.bin
Revert back to stock using the Recovery Web Interface:
- Set your IP address to 192.168.0.10, subnetmask 255.255.255.25
- Press the reset button while powering on the deivce
- Keep the reset button pressed until the status LED blinks red
- Open a Chromium based browser and goto http://192.168.0.1
- Flash a decrypted firmware image from D-Link. Decrypting an firmware image is described below.
Decrypting a D-Link firmware image:
- Download https://github.com/openwrt/firmware-utils/blob/master/src/dlink-sge-image.c and https://raw.githubusercontent.com/openwrt/firmware-utils/master/src/dlink-sge-image.h
- Compile a binary from the downloaded file, e.g. gcc dlink-sge-image.c -lcrypto -o dlink-sge-image
- Run ./dlink-sge-image COVR-X1860 <OriginalFirmware> <OutputFile> -d
- Example for firmware 102b01: ./dlink-sge-image COVR-X1860 COVR-X1860_RevA_Firmware_102b01.bin COVR-X1860_RevA_Firmware_102b01_Decrypted.bin -d
The pull request is based on the discussion in https://forum.openwrt.org/t/add-support-for-d-link-covr-x1860
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Signed-off-by: Roland Reinl <reinlroland+github@gmail.com>
(cherry picked from commit 0a18259e4a)
Signed-off-by: Florian Maurer <f.maurer@outlook.de>
MT7621 gets a new PCIe driver in the 5.15+ kernel. Allocating wrong PCIe
port will cause the PCIe NIC to not work properly. This commit fixes
the wrong port numbers on Unielec u7621-01.
According to the bootlog, MT7612E (5 GHz) is connected to pcie2, and
MT7603E (2 GHz) is connected to pcie1:
[ 1.294844] mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
[ 1.308635] mt7621-pci 1e140000.pcie: PCIE1 enabled
[ 1.318277] mt7621-pci 1e140000.pcie: PCIE2 enabled
Also correct the led activity for the MT7603e - not used on the MT7612e
Signed-off-by: David Bentham <db260179@gmail.com>
(cherry picked from commit 39e55bdbe2)
Signed-off-by: David Bentham <db260179@gmail.com>
The default strength is not enough to provide stable connection
under 3.3v LDO voltage.
Fixes: 3f3586a06d ("rockchip: add Orange Pi R1 Plus LTS support")
Fixes: #13117Fixes: #13759
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 3645ac8a10)
[rebased onto openwrt-23.05 branch]
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
The rt305x series SOC have two UART devices,
and the one at bus address 0x500 is disabled by default.
Some boards do not even have a pinout for the first one,
so use the same one that the kernel uses at 0xc00 instead.
This allows the lzma-loader printing to be visible
alongside the kernel log in the same console.
Tested-by: Lech Perczak <lech.perczak@gmail.com> # zte,mf283plus
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit bc00c78b43)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Before this was reworked, in the file for mt7621 subtarget
(target/linux/ramips/image/lzma-loader/src/board-mt7621.c)
the "Transmitter shift register empty" bit TEMT was used instead of
the "Transmitter holding register empty" bit THRE,
but after the rework, this value was labeled as the THRE bit instead.
Functionally there is no difference, but this is confusing to read,
as it suggests that the subtargets have different bits for the same
register in UART when in reality they are exactly the same.
One can use either bit, or both, at user's descretion
in order to determine whether the UART TX buffer is ready.
The generic kernel early-printk uses both,
(arch/mips/kernel/early_printk_8250.c)
while the ralink-specific early-printk uses only THRE,
(arch/mips/ralink/early_printk.c).
Define both bits and rewrite macros for readability,
keep the same values, as changing which to use should be tested first.
Ref: c31319b66 ("ramips: lzma-loader: Refactor loader")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 2e47913c64)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
The native bus address for UART was entered for rt305x UART_BASE,
but the bootloaders have memory space remapped with the same
virtual memory map the kernel uses for program addressing at boot time.
In UBoot, the remapped address is often defined as TEXT_BASE.
In the kernel, for rt305x this remapped address is RT305X_SYSC_BASE.
(arch/mips/include/asm/mach-ralink/rt305x.h)
Because the ralink I/O busses begin at a low address of 0x10000000,
they are remapped using KSEG0 or KSEG1, which for all 32-bit MIPS SOCs
(arch/mips/include/asm/addrspace.h)
are offsets of 0x80000000 and 0xa0000000 respectively.
This is consistent with the other UART_BASE macros here
and with MIPS memory map documentation.
Before the recent rework of the lzma-loader for ramips,
the original board-$(PLATFORM).c files also did not
use KSEG1ADDR for UART_BASE despite being defined,
which made this mistake easier to occur.
Fix this by defining KSEG1ADDR again and actually use it.
Copy and paste from the kernel's macros for consistency.
Link: https://training.mips.com/basic_mips/PDF/Memory_Map.pdf
Fixes: c31319b66 ("ramips: lzma-loader: Refactor loader")
Reported-by: Lech Perczak <lech.perczak@gmail.com>
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 4c1e9bd858)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
The ESW core needs to be reset together with FE core, so after the
relevant reset controller lines are moved under FE, drop rst_esw and all
related code, which would not execute anyway, because rst_esw would be
NULL. While at that, ensure that if reset line for EPHY cannot be
claimed, a proper error message is reported.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Co-developed-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split out of the bigger commit, provide commit mesage, refactor error
handling]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit f393ffcac1)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Provide commit description, split into logical changes]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit f87b66507e)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: #9284
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit fc92fecfc7)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
