501 lines
12 KiB
C
501 lines
12 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __RTL8192C_DM_H__
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#define __RTL8192C_DM_H__
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//============================================================
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// Description:
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//
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// This file is for 92CE/92CU dynamic mechanism only
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//
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//
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//============================================================
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#define RSSI_CCK 0
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#define RSSI_OFDM 1
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#define RSSI_DEFAULT 2
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//============================================================
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// structure and define
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//============================================================
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typedef struct _FALSE_ALARM_STATISTICS{
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u32 Cnt_Parity_Fail;
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u32 Cnt_Rate_Illegal;
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u32 Cnt_Crc8_fail;
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u32 Cnt_Mcs_fail;
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u32 Cnt_Ofdm_fail;
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u32 Cnt_Cck_fail;
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u32 Cnt_all;
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u32 Cnt_Fast_Fsync;
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u32 Cnt_SB_Search_fail;
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}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
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typedef struct _Dynamic_Power_Saving_
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{
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u8 PreCCAState;
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u8 CurCCAState;
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u8 PreRFState;
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u8 CurRFState;
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s32 Rssi_val_min;
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}PS_T;
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typedef struct _Dynamic_Initial_Gain_Threshold_
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{
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u8 Dig_Enable_Flag;
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u8 Dig_Ext_Port_Stage;
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int RssiLowThresh;
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int RssiHighThresh;
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u32 FALowThresh;
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u32 FAHighThresh;
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u8 CurSTAConnectState;
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u8 PreSTAConnectState;
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u8 CurMultiSTAConnectState;
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u8 PreIGValue;
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u8 CurIGValue;
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u8 BackupIGValue;
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char BackoffVal;
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char BackoffVal_range_max;
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char BackoffVal_range_min;
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u8 rx_gain_range_max;
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u8 rx_gain_range_min;
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u8 Rssi_val_min;
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u8 PreCCKPDState;
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u8 CurCCKPDState;
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u8 PreCCKFAState;
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u8 CurCCKFAState;
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u8 PreCCAState;
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u8 CurCCAState;
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u8 LargeFAHit;
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u8 ForbiddenIGI;
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u32 Recover_cnt;
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u8 rx_gain_range_min_nolink;
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}DIG_T;
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typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
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{
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DIG_TYPE_THRESH_HIGH = 0,
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DIG_TYPE_THRESH_LOW = 1,
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DIG_TYPE_BACKOFF = 2,
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DIG_TYPE_RX_GAIN_MIN = 3,
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DIG_TYPE_RX_GAIN_MAX = 4,
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DIG_TYPE_ENABLE = 5,
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DIG_TYPE_DISABLE = 6,
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DIG_OP_TYPE_MAX
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}DM_DIG_OP_E;
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typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
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{
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CCK_PD_STAGE_LowRssi = 0,
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CCK_PD_STAGE_HighRssi = 1,
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CCK_PD_STAGE_MAX = 3,
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}DM_CCK_PDTH_E;
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typedef enum tag_1R_CCA_Type_Definition
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{
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CCA_1R =0,
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CCA_2R = 1,
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CCA_MAX = 2,
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}DM_1R_CCA_E;
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typedef enum tag_RF_Type_Definition
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{
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RF_Save =0,
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RF_Normal = 1,
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RF_MAX = 2,
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}DM_RF_E;
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typedef enum tag_DIG_EXT_PORT_ALGO_Definition
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{
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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}DM_DIG_EXT_PORT_ALG_E;
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typedef enum tag_DIG_Connect_Definition
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{
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DIG_STA_DISCONNECT = 0,
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DIG_STA_CONNECT = 1,
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DIG_STA_BEFORE_CONNECT = 2,
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DIG_MultiSTA_DISCONNECT = 3,
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DIG_MultiSTA_CONNECT = 4,
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DIG_CONNECT_MAX
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}DM_DIG_CONNECT_E;
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typedef enum _BT_Ant_NUM{
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Ant_x2 = 0,
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Ant_x1 = 1
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} BT_Ant_NUM, *PBT_Ant_NUM;
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typedef enum _BT_CoType{
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BT_2Wire = 0,
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BT_ISSC_3Wire = 1,
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BT_Accel = 2,
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BT_CSR_BC4 = 3,
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BT_CSR_BC8 = 4,
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BT_RTL8756 = 5,
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} BT_CoType, *PBT_CoType;
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typedef enum _BT_CurState{
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BT_OFF = 0,
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BT_ON = 1,
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} BT_CurState, *PBT_CurState;
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typedef enum _BT_ServiceType{
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BT_SCO = 0,
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BT_A2DP = 1,
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BT_HID = 2,
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BT_HID_Idle = 3,
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BT_Scan = 4,
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BT_Idle = 5,
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BT_OtherAction = 6,
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BT_Busy = 7,
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BT_OtherBusy = 8,
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BT_PAN = 9,
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} BT_ServiceType, *PBT_ServiceType;
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typedef enum _BT_RadioShared{
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BT_Radio_Shared = 0,
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BT_Radio_Individual = 1,
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} BT_RadioShared, *PBT_RadioShared;
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struct btcoexist_priv {
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u8 BT_Coexist;
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u8 BT_Ant_Num;
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u8 BT_CoexistType;
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u8 BT_State;
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u8 BT_CUR_State; //0:on, 1:off
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u8 BT_Ant_isolation; //0:good, 1:bad
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u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
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u8 BT_Service;
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u8 BT_Ampdu; // 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU.
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u8 BT_RadioSharedType;
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u32 Ratio_Tx;
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u32 Ratio_PRI;
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u8 BtRfRegOrigin1E;
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u8 BtRfRegOrigin1F;
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u8 BtRssiState;
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u32 BtEdcaUL;
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u32 BtEdcaDL;
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u32 BT_EDCA[2];
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u8 bCOBT;
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u8 bInitSet;
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u8 bBTBusyTraffic;
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u8 bBTTrafficModeSet;
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u8 bBTNonTrafficModeSet;
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//BTTraffic BT21TrafficStatistics;
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u32 CurrentState;
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u32 PreviousState;
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u8 BtPreRssiState;
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u8 bFWCoexistAllOff;
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u8 bSWCoexistAllOff;
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};
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#define BW_AUTO_SWITCH_HIGH_LOW 25
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#define BW_AUTO_SWITCH_LOW_HIGH 30
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#define DM_DIG_THRESH_HIGH 40
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#define DM_DIG_THRESH_LOW 35
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#define DM_FALSEALARM_THRESH_LOW 400
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#define DM_FALSEALARM_THRESH_HIGH 1000
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#define DM_DIG_MAX 0x3e
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#define DM_DIG_MIN 0x1e //0x22//0x1c
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#define DM_DIG_FA_UPPER 0x3e
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#define DM_DIG_FA_LOWER 0x20
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#define DM_DIG_FA_TH0 0x20
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#define DM_DIG_FA_TH1 0x100
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#define DM_DIG_FA_TH2 0x200
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#define DM_DIG_BACKOFF_MAX 12
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#define DM_DIG_BACKOFF_MIN (-4)
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#define DM_DIG_BACKOFF_DEFAULT 10
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#define RxPathSelection_SS_TH_low 30
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#define RxPathSelection_diff_TH 18
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#define DM_RATR_STA_INIT 0
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#define DM_RATR_STA_HIGH 1
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#define DM_RATR_STA_MIDDLE 2
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#define DM_RATR_STA_LOW 3
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#define CTSToSelfTHVal 30
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#define RegC38_TH 20
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#define WAIotTHVal 25
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//Dynamic Tx Power Control Threshold
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#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
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#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
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#define TxHighPwrLevel_Normal 0
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#define TxHighPwrLevel_Level1 1
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#define TxHighPwrLevel_Level2 2
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#define TxHighPwrLevel_BT1 3
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#define TxHighPwrLevel_BT2 4
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#define TxHighPwrLevel_15 5
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#define TxHighPwrLevel_35 6
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#define TxHighPwrLevel_50 7
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#define TxHighPwrLevel_70 8
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#define TxHighPwrLevel_100 9
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#define DM_Type_ByFW 0
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#define DM_Type_ByDriver 1
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typedef struct _RATE_ADAPTIVE
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{
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u8 RateAdaptiveDisabled;
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u8 RATRState;
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u16 reserve;
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u32 HighRSSIThreshForRA;
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u32 High2LowRSSIThreshForRA;
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u8 Low2HighRSSIThreshForRA40M;
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u32 LowRSSIThreshForRA40M;
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u8 Low2HighRSSIThreshForRA20M;
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u32 LowRSSIThreshForRA20M;
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u32 UpperRSSIThresholdRATR;
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u32 MiddleRSSIThresholdRATR;
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u32 LowRSSIThresholdRATR;
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u32 LowRSSIThresholdRATR40M;
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u32 LowRSSIThresholdRATR20M;
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u8 PingRSSIEnable; //cosa add for Netcore long range ping issue
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u32 PingRSSIRATR; //cosa add for Netcore long range ping issue
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u32 PingRSSIThreshForRA;//cosa add for Netcore long range ping issue
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u32 LastRATR;
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u8 PreRATRState;
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} RATE_ADAPTIVE, *PRATE_ADAPTIVE;
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typedef enum tag_SW_Antenna_Switch_Definition
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{
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Antenna_B = 1,
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Antenna_A = 2,
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Antenna_MAX = 3,
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}DM_SWAS_E;
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#ifdef CONFIG_ANTENNA_DIVERSITY
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// This indicates two different the steps.
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// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
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// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
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// with original RSSI to determine if it is necessary to switch antenna.
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#define SWAW_STEP_PEAK 0
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#define SWAW_STEP_DETERMINE 1
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#define TP_MODE 0
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#define RSSI_MODE 1
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#define TRAFFIC_LOW 0
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#define TRAFFIC_HIGH 1
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typedef struct _SW_Antenna_Switch_
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{
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u8 try_flag;
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s32 PreRSSI;
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u8 CurAntenna;
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u8 PreAntenna;
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u8 RSSI_Trying;
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u8 TestMode;
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u8 bTriggerAntennaSwitch;
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u8 SelectAntennaMap;
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// Before link Antenna Switch check
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u8 SWAS_NoLink_State;
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}SWAT_T;
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#endif
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struct dm_priv
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{
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u8 DM_Type;
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u8 DMFlag, DMFlag_tmp;
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//for DIG
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u8 bDMInitialGainEnable;
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u8 binitialized; // for dm_initial_gain_Multi_STA use.
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DIG_T DM_DigTable;
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PS_T DM_PSTable;
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FALSE_ALARM_STATISTICS FalseAlmCnt;
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//for rate adaptive, in fact, 88c/92c fw will handle this
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u8 bUseRAMask;
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RATE_ADAPTIVE RateAdaptive;
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//* Upper and Lower Signal threshold for Rate Adaptive*/
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int UndecoratedSmoothedPWDB;
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int UndecoratedSmoothedCCK;
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int EntryMinUndecoratedSmoothedPWDB;
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int EntryMaxUndecoratedSmoothedPWDB;
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//for High Power
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u8 bDynamicTxPowerEnable;
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u8 LastDTPLvl;
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u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
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//for tx power tracking
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//u8 bTXPowerTracking;
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u8 TXPowercount;
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u8 bTXPowerTrackingInit;
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u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
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u8 TM_Trigger;
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u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
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u8 ThermalValue;
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u8 ThermalValue_LCK;
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u8 ThermalValue_IQK;
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u8 ThermalValue_DPK;
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u8 bRfPiEnable;
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//for APK
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u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
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u8 bAPKdone;
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u8 bAPKThermalMeterIgnore;
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u8 bDPdone;
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u8 bDPPathAOK;
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u8 bDPPathBOK;
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//for IQK
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u32 RegC04;
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u32 Reg874;
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u32 RegC08;
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u32 RegB68;
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u32 RegB6C;
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u32 Reg870;
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u32 Reg860;
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u32 Reg864;
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u32 ADDA_backup[IQK_ADDA_REG_NUM];
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u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
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u32 IQK_BB_backup_recover[9];
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u32 IQK_BB_backup[IQK_BB_REG_NUM];
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u8 PowerIndex_backup[6];
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u8 bCCKinCH14;
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char CCK_index;
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char OFDM_index[2];
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BOOLEAN bDoneTxpower;
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char CCK_index_HP;
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char OFDM_index_HP[2];
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u8 ThermalValue_HP[HP_THERMAL_NUM];
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u8 ThermalValue_HP_index;
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//for TxPwrTracking
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int RegE94;
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int RegE9C;
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int RegEB4;
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int RegEBC;
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u32 TXPowerTrackingCallbackCnt; //cosa add for debug
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u32 prv_traffic_idx; // edca turbo
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// for dm_RF_Saving
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u8 initialize;
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u32 rf_saving_Reg874;
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u32 rf_saving_RegC70;
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u32 rf_saving_Reg85C;
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u32 rf_saving_RegA74;
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//for Antenna diversity
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#ifdef CONFIG_ANTENNA_DIVERSITY
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SWAT_T DM_SWAT_Table;
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#endif
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#ifdef CONFIG_SW_ANTENNA_DIVERSITY
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_timer SwAntennaSwitchTimer;
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u64 lastTxOkCnt;
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u64 lastRxOkCnt;
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u64 TXByteCnt_A;
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u64 TXByteCnt_B;
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u64 RXByteCnt_A;
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u64 RXByteCnt_B;
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u8 DoubleComfirm;
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u8 TrafficLoad;
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#endif
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s32 OFDM_Pkt_Cnt;
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u8 RSSI_Select;
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u8 DIG_Dynamic_MIN ;
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// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
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u8 INIDATA_RATE[32];
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};
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
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//============================================================
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// function prototype
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//============================================================
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void rtl8192c_init_dm_priv(IN PADAPTER Adapter);
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void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter);
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void rtl8192c_InitHalDm(IN PADAPTER Adapter);
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void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter);
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VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter);
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void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal);
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VOID DM_Write_DIG(IN PADAPTER pAdapter);
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#ifdef CONFIG_BT_COEXIST
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void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart);
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void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir);
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#endif
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#ifdef CONFIG_SW_ANTENNA_DIVERSITY
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void SwAntDivRSSICheck8192C(_adapter *padapter ,u32 RxPWDBAll);
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void SwAntDivRestAfterLink8192C(IN PADAPTER Adapter);
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#endif
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#ifdef CONFIG_ANTENNA_DIVERSITY
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void SwAntDivCompare8192C(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
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u8 SwAntDivBeforeLink8192C(IN PADAPTER Adapter);
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#endif
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#endif //__HAL8190PCIDM_H__
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