Fix PCIe initialization on AR934x by clearing PLL_PWD bit in addition to PPL(PLL?)_RESET bit of AR724x. Refresh patches by `make target/linux/refresh`. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Link: https://github.com/openwrt/openwrt/pull/15432 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
21 lines
736 B
Diff
21 lines
736 B
Diff
From: Christian Lamparter <chunkeey@gmail.com>
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Subject: [PATCH] ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for
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ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -1233,6 +1233,10 @@
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#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
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#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
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#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
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+#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
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+#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
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/*
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* QCA953X GMAC Interface
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