142 lines
3.3 KiB
Diff
142 lines
3.3 KiB
Diff
From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Sun, 26 Jul 2020 13:32:59 +0200
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Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
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This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
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NanoPi R2S. Add the correct value for the RTL8153 LED configuration
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register to match the blink behavior of the other port on the device.
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Signed-off-by: David Bauer <mail@david-bauer.net>
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---
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arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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@@ -38,3 +38,7 @@
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};
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};
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};
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+
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+&rtl8153 {
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+ realtek,led-data = <0x78>;
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
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@@ -405,9 +405,11 @@
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#size-cells = <0>;
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/* Second port is for USB 3.0 */
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- rtl8153: device@2 {
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- compatible = "usbbda,8153";
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+ rtl8153: usb-eth@2 {
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+ compatible = "realtek,rtl8153";
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reg = <2>;
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+
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+ realtek,led-data = <0x87>;
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};
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};
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--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
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@@ -359,9 +359,11 @@
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#size-cells = <0>;
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/* Second port is for USB 3.0 */
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- rtl8153: device@2 {
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- compatible = "usbbda,8153";
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+ rtl8153: usb-eth@2 {
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+ compatible = "realtek,rtl8153";
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reg = <2>;
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+
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+ realtek,led-data = <0x87>;
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};
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};
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--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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@@ -38,3 +38,7 @@
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};
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};
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};
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+
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+&rtl8153 {
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+ realtek,led-data = <0x78>;
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
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@@ -83,6 +83,19 @@
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max-link-speed = <1>;
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num-lanes = <1>;
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vpcie3v3-supply = <&vcc3v3_sys>;
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+
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+ pcie@0 {
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+ reg = <0x00000000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ pcie-eth@0,0 {
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+ compatible = "pci10ec,8168";
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+ reg = <0x000000 0 0 0 0>;
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+
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+ realtek,led-data = <0x870>;
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+ };
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+ };
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};
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&pinctrl {
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--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
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@@ -31,6 +31,7 @@
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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+ label = "eth0";
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phy-handle = <&rgmii_phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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@@ -53,6 +54,7 @@
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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+ label = "eth1";
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phy-handle = <&rgmii_phy1>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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@@ -88,6 +90,34 @@
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};
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};
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+&pcie3x1 {
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+ pcie@0,0 {
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+ reg = <0x00100000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ pcie-eth@10,0 {
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+ compatible = "pci10ec,8125";
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+ reg = <0x000000 0 0 0 0>;
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+ label = "eth3";
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+ };
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+ };
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+};
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+
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+&pcie3x2 {
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+ pcie@0,0 {
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+ reg = <0x00100000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ pcie-eth@20,0 {
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+ compatible = "pci10ec,8125";
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+ reg = <0x000000 0 0 0 0>;
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+ label = "eth2";
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+ };
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+ };
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+};
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+
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&pinctrl {
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gmac0 {
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eth_phy0_reset_pin: eth-phy0-reset-pin {
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