4d5fe0a362
Move kernel config and patches to kernel 6.6. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
123 lines
4.1 KiB
Diff
123 lines
4.1 KiB
Diff
From 2004b7b1803719eaaaee5fa6b089b1699a65d31d Mon Sep 17 00:00:00 2001
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From: Elaine Zhang <zhangqing@rock-chips.com>
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Date: Tue, 18 Oct 2022 17:14:04 +0200
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Subject: [PATCH] clk: rockchip: allow additional mux options for cpu-clock
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frequency changes
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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In order to improve the main frequency of CPU, the clock path of CPU is
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simplified as follows:
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|--\
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| \ |--\
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--apll--|\ | \ | \
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| |--apll_core--| \ | \
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--24M---|/ |mux1 |--[gate]--|mux2|---clk_core
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| / | /
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--gpll--|\ | / |------| /
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| |--gpll_core--| / | |--/
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--24M---|/ |--/ |
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-------apll_directly--------------|
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When the CPU requests high frequency, we want to use MUX2 select the
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"apll_directly".
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At low frequencies use MUX1 to select “apll_core" and then MUX2 to
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select "apll_core_gate".
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However, in this way, the CPU frequency conversion needs to be
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in the following order:
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1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
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2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
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sets normal_mode
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3. MUX1 select "apll_core", MUX2 select "apll_directly"
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So add pre_mux and post_mux options to cover this special requirements.
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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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[rebase]
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-cpu.c | 41 ++++++++++++++++++++++++++++++++++
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drivers/clk/rockchip/clk.h | 2 ++
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2 files changed, 43 insertions(+)
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--- a/drivers/clk/rockchip/clk-cpu.c
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+++ b/drivers/clk/rockchip/clk-cpu.c
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@@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers
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}
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}
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+static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
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+ const struct rockchip_cpuclk_rate_table *rate)
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+{
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+ int i;
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+
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+ /* alternate parent is active now. set the pre_muxs */
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+ for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
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+ const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
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+
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+ if (!clksel->reg)
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+ break;
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+
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+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
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+ __func__, clksel->reg, clksel->val);
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+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
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+ }
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+}
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+
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+static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
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+ const struct rockchip_cpuclk_rate_table *rate)
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+{
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+ int i;
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+
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+ /* alternate parent is active now. set the muxs */
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+ for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
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+ const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
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+
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+ if (!clksel->reg)
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+ break;
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+
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+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
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+ __func__, clksel->reg, clksel->val);
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+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
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+ }
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+}
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+
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static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
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struct clk_notifier_data *ndata)
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{
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@@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_chan
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cpuclk->reg_base + reg_data->core_reg[i]);
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}
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}
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+
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+ rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
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+
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/* select alternate parent */
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if (reg_data->mux_core_reg)
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writel(HIWORD_UPDATE(reg_data->mux_core_alt,
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@@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_cha
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reg_data->mux_core_shift),
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cpuclk->reg_base + reg_data->core_reg[0]);
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+ rockchip_cpuclk_set_post_muxs(cpuclk, rate);
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+
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/* remove dividers */
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for (i = 0; i < reg_data->num_cores; i++) {
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writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
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--- a/drivers/clk/rockchip/clk.h
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+++ b/drivers/clk/rockchip/clk.h
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@@ -399,6 +399,8 @@ struct rockchip_cpuclk_clksel {
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struct rockchip_cpuclk_rate_table {
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unsigned long prate;
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struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
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+ struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
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+ struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
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};
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/**
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