Lech Perczak 4e1bf2a50c ramips: dts: rt3050: reset FE and ESW cores together ... Failing to do so will cause the DMA engine to not initialize properly and fail to forward packets between them, and in some cases will cause spurious transmission with size exceeding allowed packet size, causing a kernel panic. This is behaviour of downstream driver as well, however I haven't observed bug reports about this SoC in the wild, so this commit's purpose is to align this chip with all other SoC's - MT7620 were already using this arrangement. Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Signed-off-by: Lech Perczak <lech.perczak@gmail.com> (cherry picked from commit c5a399f372) Signed-off-by: Lech Perczak <lech.perczak@gmail.com>		2024-01-05 23:32:59 +01:00
..
imagebuilder	ib: split out processing user provided packages	2023-07-15 22:24:50 +02:00
linux	ramips: dts: rt3050: reset FE and ESW cores together	2024-01-05 23:32:59 +01:00
llvm-bpf
sdk	sdk: rename README + update Makefile	2023-07-15 22:24:50 +02:00
toolchain	treewide: add ORIG_PATH variable	2023-06-12 22:10:20 +02:00
Config.in	generic: groundwork for RISC-V	2023-06-14 09:22:08 +02:00
Makefile