60e6e250cb
- Added PCIe3/USB3 support for Rock 5B - Updated sdmmc properties for Rock 5A/5B Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
142 lines
4.3 KiB
Diff
142 lines
4.3 KiB
Diff
From c062260a0e652da798f7130ec25c6452957456d5 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Tue, 25 Apr 2023 18:17:19 +0200
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Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 controllers
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Add all USB3 controllers.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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arch/arm64/boot/dts/rockchip/rk3588.dtsi | 29 ++++++++++-
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 60 ++++++++++++++++++++++-
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2 files changed, 87 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -7,6 +7,34 @@
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#include "rk3588-pinctrl.dtsi"
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/ {
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+ usbdrd3_1: usb@fc400000 {
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+ compatible = "rockchip,rk3588-dwc3-otg", "rockchip,rk3399-dwc3";
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+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
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+ <&cru ACLK_USB3OTG1>;
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+ clock-names = "ref", "suspend", "bus";
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+ ranges;
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+ resets = <&cru SRST_A_USB3OTG1>;
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+ reset-names = "usb3-otg";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ status = "disabled";
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+
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+ usbdrd_dwc3_1: usb@fc400000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0xfc400000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
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+ power-domains = <&power RK3588_PD_USB>;
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+ dr_mode = "host";
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+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ };
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+ };
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+
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pcie30_phy_grf: syscon@fd5b8000 {
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compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
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reg = <0x0 0xfd5b8000 0x0 0x10000>;
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@@ -39,7 +67,6 @@
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy1";
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#clock-cells = <0>;
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- rockchip,usbctrl-grf = <&usb_grf>;
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status = "disabled";
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u2phy1_otg: otg-port {
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -832,6 +832,36 @@
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};
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};
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+ usbdrd3_0: usb@fc000000 {
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+ compatible = "rockchip,rk3588-dwc3-otg", "rockchip,rk3399-dwc3";
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+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
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+ <&cru ACLK_USB3OTG0>;
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+ clock-names = "ref", "suspend", "bus";
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+ ranges;
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+ resets = <&cru SRST_A_USB3OTG0>;
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+ reset-names = "usb3-otg";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ status = "disabled";
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+
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+ usbdrd_dwc3_0: usb@fc000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0xfc000000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
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+ power-domains = <&power RK3588_PD_USB>;
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+ dr_mode = "otg";
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+ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u1-entry-quirk;
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+ snps,dis-u2-entry-quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ };
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+ };
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+
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usb_host0_ehci: usb@fc800000 {
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compatible = "rockchip,rk3588-ehci", "generic-ehci";
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reg = <0x0 0xfc800000 0x0 0x40000>;
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@@ -876,6 +906,35 @@
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status = "disabled";
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};
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+ usbhost3_0: usb@fcd00000 {
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+ compatible = "rockchip,rk3588-dwc3-host", "rockchip,rk3399-dwc3";
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+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
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+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
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+ <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>;
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+ clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
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+ ranges;
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+ resets = <&cru SRST_A_USB3OTG2>;
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+ reset-names = "usb3-host";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ status = "disabled";
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+
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+ usbhost_dwc3_0: usb@fcd00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0xfcd00000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
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+ dr_mode = "host";
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+ phys = <&combphy2_psu PHY_TYPE_USB3>;
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+ phy-names = "usb3-phy";
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ snps,dis_rxdet_inp3_quirk;
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+ };
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+ };
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+
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sys_grf: syscon@fd58c000 {
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compatible = "rockchip,rk3588-sys-grf", "syscon";
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reg = <0x0 0xfd58c000 0x0 0x1000>;
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@@ -923,7 +982,6 @@
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy0";
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#clock-cells = <0>;
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- rockchip,usbctrl-grf = <&usb_grf>;
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status = "disabled";
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u2phy0_otg: otg-port {
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