187 lines
5.6 KiB
Diff
187 lines
5.6 KiB
Diff
From: Martin Botka <martin.botka@somainline.org>
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To: Mark Rutland <mark.rutland@arm.com>,
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Lorenzo Pieralisi <lpieralisi@kernel.org>,
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Sudeep Holla <sudeep.holla@arm.com>,
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"Rafael J. Wysocki" <rafael@kernel.org>,
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Viresh Kumar <viresh.kumar@linaro.org>,
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Yangtao Li <tiny.windzz@gmail.com>, Chen-Yu Tsai <wens@csie.org>,
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Jernej Skrabec <jernej.skrabec@gmail.com>,
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Samuel Holland <samuel@sholland.org>,
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Rob Herring <robh+dt@kernel.org>,
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Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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Conor Dooley <conor+dt@kernel.org>
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Cc: linux-arm-kernel@lists.infradead.org,
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linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
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linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org,
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Andre Przywara <andre.przywara@arm.com>,
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Alan Ma <tech@biqu3d.com>,
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Luke Harrison <bttuniversity@biqu3d.com>,
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Marijn Suijten <marijn.suijten@somainline.org>,
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AngeloGioacchino Del Regno
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<angelogioacchino.delregno@somainline.org>,
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Konrad Dybcio <konrad.dybcio@somainline.org>,
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Rogerio Goncalves <rogerlz@gmail.com>,
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Martin Botka <martin@biqu3d.com>,
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Martin Botka <martin.botka@somainline.org>
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Subject: [PATCH 5/6] arm64: dts: allwinner: h616: Add CPU Operating Performance Points table
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Date: Mon, 04 Sep 2023 17:57:05 +0200 [thread overview]
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Message-ID: <20230904-cpufreq-h616-v1-5-b8842e525c43@somainline.org> (raw)
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In-Reply-To: <20230904-cpufreq-h616-v1-0-b8842e525c43@somainline.org>
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Add an Operating Performance Points table for the CPU cores to
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enable Dynamic Voltage & Frequency Scaling on the H616.
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Also add the needed cpu_speed_grade nvmem cell.
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Signed-off-by: Martin Botka <martin.botka@somainline.org>
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---
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.../boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi | 129 +++++++++++++++++++++
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arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 4 +
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2 files changed, 133 insertions(+)
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
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@@ -0,0 +1,129 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2023 Martin Botka <martin@somainline.org>
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+
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+/ {
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+ cpu_opp_table: cpu-opp-table {
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+ compatible = "allwinner,sun50i-h616-operating-points";
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+ nvmem-cells = <&cpu_speed_grade>;
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+ opp-shared;
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+
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+ opp-480000000 {
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+ opp-hz = /bits/ 64 <480000000>;
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+ opp-microvolt-speed0 = <900000>;
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+ opp-microvolt-speed1 = <900000>;
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+ opp-microvolt-speed2 = <900000>;
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+ opp-microvolt-speed3 = <900000>;
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+ opp-microvolt-speed4 = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1f>;
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+ };
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+
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt-speed1 = <900000>;
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+ opp-microvolt-speed4 = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x12>;
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+ };
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+
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+ opp-720000000 {
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+ opp-hz = /bits/ 64 <720000000>;
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+ opp-microvolt-speed0 = <900000>;
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+ opp-microvolt-speed2 = <900000>;
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+ opp-microvolt-speed3 = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0xd>;
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+ };
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+
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+ opp-792000000 {
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+ opp-hz = /bits/ 64 <792000000>;
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+ opp-microvolt-speed1 = <900000>;
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+ opp-microvolt-speed4 = <940000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x12>;
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+ };
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+
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+ opp-936000000 {
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+ opp-hz = /bits/ 64 <936000000>;
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+ opp-microvolt-speed0 = <900000>;
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+ opp-microvolt-speed2 = <900000>;
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+ opp-microvolt-speed3 = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0xd>;
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt-speed0 = <950000>;
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+ opp-microvolt-speed1 = <940000>;
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+ opp-microvolt-speed2 = <950000>;
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+ opp-microvolt-speed3 = <950000>;
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+ opp-microvolt-speed4 = <1020000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1f>;
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt-speed0 = <1000000>;
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+ opp-microvolt-speed2 = <1000000>;
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+ opp-microvolt-speed3 = <1000000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0xd>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt-speed0 = <1050000>;
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+ opp-microvolt-speed1 = <1020000>;
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+ opp-microvolt-speed2 = <1050000>;
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+ opp-microvolt-speed3 = <1050000>;
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+ opp-microvolt-speed4 = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1f>;
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+ };
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+
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+ opp-1320000000 {
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+ opp-hz = /bits/ 64 <1320000000>;
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+ opp-microvolt-speed0 = <1100000>;
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+ opp-microvolt-speed2 = <1100000>;
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+ opp-microvolt-speed3 = <1100000>;
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+ opp-microvolt-speed4 = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1d>;
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+ };
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+
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt-speed0 = <1100000>;
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+ opp-microvolt-speed2 = <1100000>;
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+ opp-microvolt-speed3 = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0xd>;
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+ };
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+
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+ opp-1512000000 {
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+ opp-hz = /bits/ 64 <1512000000>;
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+ opp-microvolt-speed1 = <1100000>;
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+ opp-microvolt-speed3 = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0xa>;
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu1 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu2 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu3 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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@@ -143,6 +143,10 @@
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ths_calibration: thermal-sensor-calibration@14 {
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reg = <0x14 0x8>;
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};
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+
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+ cpu_speed_grade: cpu_speed_grade@0 {
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+ reg = <0x0 2>;
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+ };
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};
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watchdog: watchdog@30090a0 {
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