a2f87aaf53
0. Added rk356x support to existing drivers (PCIe v2 / usb) (upstreamed) 1. Added rk356x dtsi (upstreamed) 2. Added combo phy driver (upstreamed) 3. Added hwRNG support (vendor) 4. Added PCIe v3 driver (under review) 5. Added VOP2 driver (upstreamed) 6. Added 1992 MHz to cpu opp-table (local) Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
45 lines
1.6 KiB
Diff
45 lines
1.6 KiB
Diff
From 842f4cb7263953020f4e2f2f0005fc3e6fc56144 Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Wed, 26 Jan 2022 15:55:33 +0100
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Subject: [PATCH] clk: rockchip: Add more PLL rates for rk3568
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This adds a few more PLL settings needed for some standard resolutions:
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297MHz 3840x2160-30.00
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241.5MHz 2560x1440-59.95
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135MHz 1280x1024-75.02
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119MHz 1680x1050-59.88
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108MHz 1280x1024-60.02
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78.75MHz 1024x768-75.03
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Changes since v3:
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- new patch
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3568.c | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/drivers/clk/rockchip/clk-rk3568.c
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+++ b/drivers/clk/rockchip/clk-rk3568.c
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@@ -71,11 +71,17 @@ static struct rockchip_pll_rate_table rk
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RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
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RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
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RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
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+ RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
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+ RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
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RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
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RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
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RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
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+ RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
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+ RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
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+ RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
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RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
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RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
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+ RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
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RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
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{ /* sentinel */ },
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};
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