383 lines
11 KiB
C
383 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 - 2021
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*
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* Richard van Schagen <vschagen@icloud.com>
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*/
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#ifndef REG_EIP93_H
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#define REG_EIP93_H
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#define EIP93_REG_WIDTH 4
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/*-----------------------------------------------------------------------------
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* Register Map
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*/
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#define DESP_BASE 0x0000000
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#define EIP93_REG_PE_CTRL_STAT ((DESP_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_SOURCE_ADDR ((DESP_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_DEST_ADDR ((DESP_BASE)+(0x02 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_SA_ADDR ((DESP_BASE)+(0x03 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_ADDR ((DESP_BASE)+(0x04 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_USER_ID ((DESP_BASE)+(0x06 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_LENGTH ((DESP_BASE)+(0x07 * EIP93_REG_WIDTH))
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//PACKET ENGINE RING configuration registers
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#define PE_RNG_BASE 0x0000080
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#define EIP93_REG_PE_CDR_BASE ((PE_RNG_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_RDR_BASE ((PE_RNG_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_RING_CONFIG ((PE_RNG_BASE)+(0x02 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_RING_THRESH ((PE_RNG_BASE)+(0x03 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_CD_COUNT ((PE_RNG_BASE)+(0x04 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_RD_COUNT ((PE_RNG_BASE)+(0x05 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_RING_RW_PNTR ((PE_RNG_BASE)+(0x06 * EIP93_REG_WIDTH))
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//PACKET ENGINE configuration registers
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#define PE_CFG_BASE 0x0000100
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#define EIP93_REG_PE_CONFIG ((PE_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_STATUS ((PE_CFG_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_BUF_THRESH ((PE_CFG_BASE)+(0x03 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_INBUF_COUNT ((PE_CFG_BASE)+(0x04 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_OUTBUF_COUNT ((PE_CFG_BASE)+(0x05 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_BUF_RW_PNTR ((PE_CFG_BASE)+(0x06 * EIP93_REG_WIDTH))
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//PACKET ENGINE endian config
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#define EN_CFG_BASE 0x00001CC
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#define EIP93_REG_PE_ENDIAN_CONFIG ((EN_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
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//EIP93 CLOCK control registers
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#define CLOCK_BASE 0x01E8
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#define EIP93_REG_PE_CLOCK_CTRL ((CLOCK_BASE)+(0x00 * EIP93_REG_WIDTH))
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//EIP93 Device Option and Revision Register
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#define REV_BASE 0x01F4
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#define EIP93_REG_PE_OPTION_1 ((REV_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_OPTION_0 ((REV_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_REG_PE_REVISION ((REV_BASE)+(0x02 * EIP93_REG_WIDTH))
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//EIP93 Interrupt Control Register
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#define INT_BASE 0x0200
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#define EIP93_REG_INT_UNMASK_STAT ((INT_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_INT_MASK_STAT ((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_REG_INT_CLR ((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_REG_INT_MASK ((INT_BASE)+(0x02 * EIP93_REG_WIDTH))
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#define EIP93_REG_INT_CFG ((INT_BASE)+(0x03 * EIP93_REG_WIDTH))
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#define EIP93_REG_MASK_ENABLE ((INT_BASE)+(0X04 * EIP93_REG_WIDTH))
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#define EIP93_REG_MASK_DISABLE ((INT_BASE)+(0X05 * EIP93_REG_WIDTH))
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//EIP93 SA Record register
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#define SA_BASE 0x0400
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#define EIP93_REG_SA_CMD_0 ((SA_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_SA_CMD_1 ((SA_BASE)+(0x01 * EIP93_REG_WIDTH))
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//#define EIP93_REG_SA_READY ((SA_BASE)+(31 * EIP93_REG_WIDTH))
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//State save register
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#define STATE_BASE 0x0500
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#define EIP93_REG_STATE_IV_0 ((STATE_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_STATE_IV_1 ((STATE_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_PE_ARC4STATE_BASEADDR_REG 0x0700
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//RAM buffer start address
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#define EIP93_INPUT_BUFFER 0x0800
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#define EIP93_OUTPUT_BUFFER 0x0800
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//EIP93 PRNG Configuration Register
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#define PRNG_BASE 0x0300
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#define EIP93_REG_PRNG_STAT ((PRNG_BASE)+(0x00 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_CTRL ((PRNG_BASE)+(0x01 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_SEED_0 ((PRNG_BASE)+(0x02 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_SEED_1 ((PRNG_BASE)+(0x03 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_SEED_2 ((PRNG_BASE)+(0x04 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_SEED_3 ((PRNG_BASE)+(0x05 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_KEY_0 ((PRNG_BASE)+(0x06 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_KEY_1 ((PRNG_BASE)+(0x07 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_KEY_2 ((PRNG_BASE)+(0x08 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_KEY_3 ((PRNG_BASE)+(0x09 * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_RES_0 ((PRNG_BASE)+(0x0A * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_RES_1 ((PRNG_BASE)+(0x0B * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_RES_2 ((PRNG_BASE)+(0x0C * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_RES_3 ((PRNG_BASE)+(0x0D * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_LFSR_0 ((PRNG_BASE)+(0x0E * EIP93_REG_WIDTH))
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#define EIP93_REG_PRNG_LFSR_1 ((PRNG_BASE)+(0x0F * EIP93_REG_WIDTH))
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/*-----------------------------------------------------------------------------
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* Constants & masks
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*/
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#define EIP93_SUPPORTED_INTERRUPTS_MASK 0xffff7f00
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#define EIP93_PRNG_DT_TEXT_LOWERHALF 0xDEAD
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#define EIP93_PRNG_DT_TEXT_UPPERHALF 0xC0DE
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#define EIP93_10BITS_MASK 0X3FF
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#define EIP93_12BITS_MASK 0XFFF
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#define EIP93_4BITS_MASK 0X04
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#define EIP93_20BITS_MASK 0xFFFFF
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#define EIP93_MIN_DESC_DONE_COUNT 0
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#define EIP93_MAX_DESC_DONE_COUNT 15
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#define EIP93_MIN_DESC_PENDING_COUNT 0
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#define EIP93_MAX_DESC_PENDING_COUNT 1023
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#define EIP93_MIN_TIMEOUT_COUNT 0
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#define EIP93_MAX_TIMEOUT_COUNT 15
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#define EIP93_MIN_PE_INPUT_THRESHOLD 1
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#define EIP93_MAX_PE_INPUT_THRESHOLD 511
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#define EIP93_MIN_PE_OUTPUT_THRESHOLD 1
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#define EIP93_MAX_PE_OUTPUT_THRESHOLD 432
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#define EIP93_MIN_PE_RING_SIZE 1
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#define EIP93_MAX_PE_RING_SIZE 1023
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#define EIP93_MIN_PE_DESCRIPTOR_SIZE 7
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#define EIP93_MAX_PE_DESCRIPTOR_SIZE 15
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//3DES keys,seed,known data and its result
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#define EIP93_KEY_0 0x133b3454
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#define EIP93_KEY_1 0x5e5b890b
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#define EIP93_KEY_2 0x5eb30757
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#define EIP93_KEY_3 0x93ab15f7
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#define EIP93_SEED_0 0x62c4bf5e
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#define EIP93_SEED_1 0x972667c8
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#define EIP93_SEED_2 0x6345bf67
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#define EIP93_SEED_3 0xcb3482bf
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#define EIP93_LFSR_0 0xDEADC0DE
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#define EIP93_LFSR_1 0xBEEFF00D
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/*-----------------------------------------------------------------------------
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* EIP93 device initialization specifics
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*/
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/*----------------------------------------------------------------------------
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* Byte Order Reversal Mechanisms Supported in EIP93
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* EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
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* EIP93_BO_REVERSE_WORD : reverse the byte order within a word
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* EIP93_BO_REVERSE_DUAL_WORD : reverse the byte order within a dual-word
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* EIP93_BO_REVERSE_QUAD_WORD : reverse the byte order within a quad-word
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*/
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enum EIP93_Byte_Order_Value_t {
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EIP93_BO_REVERSE_HALF_WORD = 1,
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EIP93_BO_REVERSE_WORD = 2,
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EIP93_BO_REVERSE_DUAL_WORD = 4,
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EIP93_BO_REVERSE_QUAD_WORD = 8,
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};
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/*----------------------------------------------------------------------------
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* Byte Order Reversal Mechanisms Supported in EIP93 for Target Data
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* EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
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* EIP93_BO_REVERSE_WORD : reverse the byte order within a word
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*/
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enum EIP93_Byte_Order_Value_TD_t {
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EIP93_BO_REVERSE_HALF_WORD_TD = 1,
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EIP93_BO_REVERSE_WORD_TD = 2,
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};
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// BYTE_ORDER_CFG register values
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#define EIP93_BYTE_ORDER_PD EIP93_BO_REVERSE_WORD
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#define EIP93_BYTE_ORDER_SA EIP93_BO_REVERSE_WORD
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#define EIP93_BYTE_ORDER_DATA EIP93_BO_REVERSE_WORD
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#define EIP93_BYTE_ORDER_TD EIP93_BO_REVERSE_WORD_TD
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// INT_CFG register values
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#define EIP93_INT_HOST_OUTPUT_TYPE 0
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#define EIP93_INT_PULSE_CLEAR 0
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/*
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* Interrupts of EIP93
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*/
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enum EIP93_InterruptSource_t {
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EIP93_INT_PE_CDRTHRESH_REQ = BIT(0),
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EIP93_INT_PE_RDRTHRESH_REQ = BIT(1),
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EIP93_INT_PE_OPERATION_DONE = BIT(9),
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EIP93_INT_PE_INBUFTHRESH_REQ = BIT(10),
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EIP93_INT_PE_OUTBURTHRSH_REQ = BIT(11),
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EIP93_INT_PE_PRNG_IRQ = BIT(12),
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EIP93_INT_PE_ERR_REG = BIT(13),
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EIP93_INT_PE_RD_DONE_IRQ = BIT(16),
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};
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union peConfig_w {
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u32 word;
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struct {
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u32 resetPE :1;
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u32 resetRing :1;
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u32 reserved :6;
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u32 peMode :2;
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u32 enCDRupdate :1;
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u32 reserved2 :5;
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u32 swapCDRD :1;
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u32 swapSA :1;
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u32 swapData :1;
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u32 reserved3 :13;
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} bits;
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} __packed;
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union peEndianCfg_w {
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u32 word;
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struct {
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u32 masterByteSwap :8;
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u32 reserved :8;
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u32 targetByteSwap :8;
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u32 reserved2 :8;
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} bits;
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} __packed;
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union peIntCfg_w {
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u32 word;
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struct {
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u32 PulseClear :1;
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u32 IntType :1;
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u32 reserved :30;
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} bits;
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} __packed;
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union peClockCfg_w {
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u32 word;
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struct {
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u32 enPEclk :1;
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u32 enDESclk :1;
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u32 enAESclk :1;
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u32 reserved :1;
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u32 enHASHclk :1;
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u32 reserved2 :27;
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} bits;
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} __packed;
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union peBufThresh_w {
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u32 word;
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struct {
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u32 inputBuffer :8;
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u32 reserved :8;
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u32 outputBuffer :8;
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u32 reserved2 :8;
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} bits;
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} __packed;
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union peRingThresh_w {
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u32 word;
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struct {
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u32 CDRThresh :10;
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u32 reserved :6;
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u32 RDRThresh :10;
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u32 RDTimeout :4;
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u32 reserved2 :1;
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u32 enTimeout :1;
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} bits;
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} __packed;
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union peRingCfg_w {
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u32 word;
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struct {
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u32 ringSize :10;
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u32 reserved :6;
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u32 ringOffset :8;
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u32 reserved2 :8;
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} bits;
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} __packed;
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union saCmd0 {
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u32 word;
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struct {
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u32 opCode :3;
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u32 direction :1;
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u32 opGroup :2;
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u32 padType :2;
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u32 cipher :4;
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u32 hash :4;
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u32 reserved2 :1;
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u32 scPad :1;
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u32 extPad :1;
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u32 hdrProc :1;
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u32 digestLength :4;
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u32 ivSource :2;
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u32 hashSource :2;
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u32 saveIv :1;
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u32 saveHash :1;
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u32 reserved1 :2;
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} bits;
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} __packed;
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union saCmd1 {
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u32 word;
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struct {
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u32 copyDigest :1;
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u32 copyHeader :1;
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u32 copyPayload :1;
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u32 copyPad :1;
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u32 reserved4 :4;
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u32 cipherMode :2;
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u32 reserved3 :1;
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u32 sslMac :1;
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u32 hmac :1;
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u32 byteOffset :1;
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u32 reserved2 :2;
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u32 hashCryptOffset :8;
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u32 aesKeyLen :3;
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u32 reserved1 :1;
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u32 aesDecKey :1;
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u32 seqNumCheck :1;
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u32 reserved0 :2;
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} bits;
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} __packed;
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struct saRecord_s {
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union saCmd0 saCmd0;
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union saCmd1 saCmd1;
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u32 saKey[8];
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u32 saIDigest[8];
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u32 saODigest[8];
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u32 saSpi;
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u32 saSeqNum[2];
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u32 saSeqNumMask[2];
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u32 saNonce;
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} __packed;
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struct saState_s {
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u32 stateIv[4];
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u32 stateByteCnt[2];
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u32 stateIDigest[8];
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} __packed;
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union peCrtlStat_w {
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u32 word;
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struct {
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u32 hostReady :1;
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u32 peReady :1;
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u32 reserved :1;
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u32 initArc4 :1;
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u32 hashFinal :1;
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u32 haltMode :1;
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u32 prngMode :2;
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u32 padValue :8;
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u32 errStatus :8;
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u32 padCrtlStat :8;
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} bits;
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} __packed;
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union peLength_w {
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u32 word;
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struct {
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u32 length :20;
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u32 reserved :2;
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u32 hostReady :1;
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u32 peReady :1;
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u32 byPass :8;
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} bits;
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} __packed;
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struct eip93_descriptor_s {
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union peCrtlStat_w peCrtlStat;
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u32 srcAddr;
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u32 dstAddr;
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u32 saAddr;
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u32 stateAddr;
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u32 arc4Addr;
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u32 userId;
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union peLength_w peLength;
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} __packed;
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#endif
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