4465dc87d8
Fixes: a09aab301f ("rockchip: update rk3588 gate link patches")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
From 81f3db1af2934b19df3dd6a7103db558ce6281da Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Tue, 24 Oct 2023 16:13:50 +0200
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Subject: [PATCH] clk: divider: Fix divisor masking on 64 bit platforms
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The clock framework handles clock rates as "unsigned long", so u32 on
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32-bit architectures and u64 on 64-bit architectures.
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The current code casts the dividend to u64 on 32-bit to avoid a
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potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000)
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= (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been
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introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow
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when dividing large clock rates").
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On 64 bit platforms this masks the divisor, so that only the lower
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32 bit are used. Thus requesting a frequency >= 4.3GHz results
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in incorrect values. For example requesting 4300000000 (4.3 GHz) will
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effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
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is a bit of a special case, since that still returns correct values as
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long as the parent clock is below 8.5 GHz.
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Fix this by switching to DIV_ROUND_UP_NO_OVERFLOW, which cannot
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overflow. This avoids any requirements on the arguments (except
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that divisor should not be 0 obviously).
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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drivers/clk/clk-divider.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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--- a/drivers/clk/clk-divider.c
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+++ b/drivers/clk/clk-divider.c
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@@ -220,7 +220,7 @@ static int _div_round_up(const struct cl
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unsigned long parent_rate, unsigned long rate,
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unsigned long flags)
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{
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- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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+ int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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div = __roundup_pow_of_two(div);
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@@ -237,7 +237,7 @@ static int _div_round_closest(const stru
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int up, down;
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unsigned long up_rate, down_rate;
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- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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+ up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
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down = parent_rate / rate;
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if (flags & CLK_DIVIDER_POWER_OF_TWO) {
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@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate,
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{
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unsigned int div, value;
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- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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+ div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
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if (!_is_valid_div(table, div, flags))
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return -EINVAL;
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