Tomasz Maciej Nowak 598bcdddfb mvebu: limit mvneta tx queue workaround to 32 bit SoC ... This patch has been carried since introduction throughout every kernel major bump and no one has tested if the later kernels improved the situation. The Armada 3720 SoC can only process GbE interrupts on Core 0 and this is already limited in all stable kernels, so ditch this workaround for 64 bit SoCs. Ref: https://git.kernel.org/torvalds/c/cf9bf871280d Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>		2021-07-26 12:15:45 +08:00
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base-files/lib	Merge Mainline	2021-06-17 20:47:12 +08:00
cortexa9	target: use SPDX license identifiers on Makefiles	2021-02-11 12:05:39 +08:00
cortexa53	mvebu: Fix sysupgrade for GL.iNet GL-MV1000	2021-04-18 23:44:18 +08:00
cortexa72	kernel: move some disabled symbols to generic	2021-03-20 11:19:57 +08:00
files/arch	mvebu: convert mtd-mac-address to nvmem implementation	2021-07-20 12:27:06 +08:00
files-5.4/arch/arm64/boot/dts/marvell	mvebu: remove upstreamed DTS files in 5.10	2021-02-24 12:15:07 +08:00
image	mvebu: enable WRT1900AC v1 and WRT32X for buildbots	2021-03-20 11:47:12 +08:00
patches-5.4	mvebu: limit mvneta tx queue workaround to 32 bit SoC	2021-07-26 12:15:45 +08:00
patches-5.10	mvebu: limit mvneta tx queue workaround to 32 bit SoC	2021-07-26 12:15:45 +08:00
config-5.4	treewide: switch the timer frequency to 100 Hz	2021-04-22 23:12:24 +08:00
config-5.10	treewide: switch the timer frequency to 100 Hz	2021-04-22 23:12:24 +08:00
Makefile	mvebu: add 5.10 as a testing kernel	2021-02-24 12:17:02 +08:00
modules.mk	mvebu: sync with upstream source	2020-08-29 01:35:33 +08:00