Daniel González Cabanelas ddd3c99ca1 mvebu: LS421DE: improve pin configuration ... The CLK125 output pin at the ethernet PHY is connected via capacitor to GND and nowhere else. Disable it. Also tune the LED masks. The MPP56 and MPP60 pins at the SoC are conected to the μPD720202 USB3.0 chip: - MPP56: wired to PCIe CLKREQ# (out) - MPP60: wired to PCIe RESET# (in) Configure the pcie pinmux for these pins. Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>		2021-05-01 11:37:11 +08:00
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base-files/lib	mvebu: base-files: Update Turris Omnia U-Boot environment	2020-11-28 19:07:25 +08:00
cortexa9	target: use SPDX license identifiers on Makefiles	2021-02-11 12:05:39 +08:00
cortexa53	mvebu: Fix sysupgrade for GL.iNet GL-MV1000	2021-04-18 23:44:18 +08:00
cortexa72	kernel: move some disabled symbols to generic	2021-03-20 11:19:57 +08:00
files/arch	mvebu: LS421DE: improve pin configuration	2021-05-01 11:37:11 +08:00
files-5.4/arch/arm64/boot/dts/marvell	mvebu: remove upstreamed DTS files in 5.10	2021-02-24 12:15:07 +08:00
image	mvebu: enable WRT1900AC v1 and WRT32X for buildbots	2021-03-20 11:47:12 +08:00
patches-5.4	mvebu: armada 370: dts: fix the crypto engine	2021-04-18 23:43:57 +08:00
patches-5.10	mvebu: armada 370: dts: fix the crypto engine	2021-04-18 23:43:57 +08:00
config-5.4	treewide: switch the timer frequency to 100 Hz	2021-04-22 23:12:24 +08:00
config-5.10	treewide: switch the timer frequency to 100 Hz	2021-04-22 23:12:24 +08:00
Makefile	mvebu: add 5.10 as a testing kernel	2021-02-24 12:17:02 +08:00
modules.mk	mvebu: sync with upstream source	2020-08-29 01:35:33 +08:00