immortalwrt/target/linux/rockchip/patches-6.1/610-arm64-rockchip-add-OF-node-for-eth.patch

From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Sun, 26 Jul 2020 13:32:59 +0200
Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S

This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
NanoPi R2S. Add the correct value for the RTL8153 LED configuration
register to match the blink behavior of the other port on the device.

Signed-off-by: David Bauer <mail@david-bauer.net>
---
 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
 1 file changed, 7 insertions(+)

--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -38,3 +38,7 @@
 		};
 	};
 };
+
+&rtl8153 {
+	realtek,led-data = <0x78>;
+};
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -405,9 +405,11 @@
 	#size-cells = <0>;
 
 	/* Second port is for USB 3.0 */
-	rtl8153: device@2 {
-		compatible = "usbbda,8153";
+	rtl8153: usb-eth@2 {
+		compatible = "realtek,rtl8153";
 		reg = <2>;
+
+		realtek,led-data = <0x87>;
 	};
 };
 
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
@@ -359,9 +359,11 @@
 	#size-cells = <0>;
 
 	/* Second port is for USB 3.0 */
-	rtl8153: device@2 {
-		compatible = "usbbda,8153";
+	rtl8153: usb-eth@2 {
+		compatible = "realtek,rtl8153";
 		reg = <2>;
+
+		realtek,led-data = <0x87>;
 	};
 };
 
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -38,3 +38,7 @@
 		};
 	};
 };
+
+&rtl8153 {
+	realtek,led-data = <0x78>;
+};
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -83,6 +83,19 @@
 	max-link-speed = <1>;
 	num-lanes = <1>;
 	vpcie3v3-supply = <&vcc3v3_sys>;
+
+	pcie@0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@0,0 {
+			compatible = "pci10ec,8168";
+			reg = <0x000000 0 0 0 0>;
+
+			realtek,led-data = <0x870>;
+		};
+	};
 };
 
 &pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
@@ -31,6 +31,7 @@
 	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
 	assigned-clock-rates = <0>, <125000000>;
 	clock_in_out = "output";
+	label = "eth0";
 	phy-handle = <&rgmii_phy0>;
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
@@ -53,6 +54,7 @@
 	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
 	assigned-clock-rates = <0>, <125000000>;
 	clock_in_out = "output";
+	label = "eth1";
 	phy-handle = <&rgmii_phy1>;
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
@@ -88,6 +90,34 @@
 	};
 };
 
+&pcie3x1 {
+	pcie@0,0 {
+		reg = <0x00100000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@10,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x000000 0 0 0 0>;
+			label = "eth3";
+		};
+	};
+};
+
+&pcie3x2 {
+	pcie@0,0 {
+		reg = <0x00100000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@20,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x000000 0 0 0 0>;
+			label = "eth2";
+		};
+	};
+};
+
 &pinctrl {
 	gmac0 {
 		eth_phy0_reset_pin: eth-phy0-reset-pin {