rockchip: 6.1: copy patches, config from 5.15
Copy patches and config from 5.15 kernel version. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
parent
d42a0b57db
commit
496436c0e0
672
target/linux/rockchip/armv8/config-6.1
Normal file
672
target/linux/rockchip/armv8/config-6.1
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@ -0,0 +1,672 @@
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CONFIG_64BIT=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
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CONFIG_ARCH_MMAP_RND_BITS=18
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CONFIG_ARCH_MMAP_RND_BITS_MAX=33
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CONFIG_ARCH_MMAP_RND_BITS_MIN=18
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
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CONFIG_ARCH_PROC_KCORE_TEXT=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_STACKWALK=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_WANTS_NO_INSTR=y
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CONFIG_ARCH_WANTS_THP_SWAP=y
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CONFIG_ARC_EMAC_CORE=y
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CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_CNP=y
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CONFIG_ARM64_CRYPTO=y
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CONFIG_ARM64_EPAN=y
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CONFIG_ARM64_ERRATUM_1742098=y
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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CONFIG_ARM64_ERRATUM_827319=y
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CONFIG_ARM64_ERRATUM_832075=y
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CONFIG_ARM64_ERRATUM_843419=y
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CONFIG_ARM64_ERRATUM_845719=y
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CONFIG_ARM64_ERRATUM_858921=y
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CONFIG_ARM64_HW_AFDBM=y
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CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
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CONFIG_ARM64_MODULE_PLTS=y
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CONFIG_ARM64_PAGE_SHIFT=12
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CONFIG_ARM64_PAN=y
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CONFIG_ARM64_PA_BITS=48
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CONFIG_ARM64_PA_BITS_48=y
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CONFIG_ARM64_PTR_AUTH=y
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CONFIG_ARM64_PTR_AUTH_KERNEL=y
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CONFIG_ARM64_RAS_EXTN=y
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CONFIG_ARM64_SVE=y
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CONFIG_ARM64_TAGGED_ADDR_ABI=y
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CONFIG_ARM64_VA_BITS=48
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# CONFIG_ARM64_VA_BITS_39 is not set
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CONFIG_ARM64_VA_BITS_48=y
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CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
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# CONFIG_ARMV8_DEPRECATED is not set
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_GIC_V2M=y
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_GIC_V3_ITS_PCI=y
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CONFIG_ARM_MHU=y
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CONFIG_ARM_MHU_V2=y
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CONFIG_ARM_PSCI_CPUIDLE=y
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CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
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CONFIG_ARM_PSCI_FW=y
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CONFIG_ARM_RK3328_DMC_DEVFREQ=y
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# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
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CONFIG_ARM_SCMI_CPUFREQ=y
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CONFIG_ARM_SCMI_HAVE_SHMEM=y
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CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
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CONFIG_ARM_SCMI_POWER_DOMAIN=y
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CONFIG_ARM_SCMI_PROTOCOL=y
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CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
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CONFIG_ARM_SCMI_TRANSPORT_SMC=y
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CONFIG_ARM_SCPI_CPUFREQ=y
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CONFIG_ARM_SCPI_POWER_DOMAIN=y
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CONFIG_ARM_SCPI_PROTOCOL=y
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CONFIG_ARM_SMMU=y
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CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
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# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
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CONFIG_ARM_SMMU_V3=y
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# CONFIG_ARM_SMMU_V3_SVA is not set
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CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_GPIO=y
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CONFIG_BACKLIGHT_PWM=y
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CONFIG_BLK_DEV_BSG=y
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CONFIG_BLK_DEV_BSGLIB=y
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CONFIG_BLK_DEV_BSG_COMMON=y
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# CONFIG_BLK_DEV_INITRD is not set
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CONFIG_BLK_DEV_INTEGRITY=y
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CONFIG_BLK_DEV_INTEGRITY_T10=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_NVME=y
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CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_PM=y
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CONFIG_BLOCK_COMPAT=y
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
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CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
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CONFIG_CHARGER_GPIO=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLK_PX30=y
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CONFIG_CLK_RK3308=y
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CONFIG_CLK_RK3328=y
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CONFIG_CLK_RK3368=y
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CONFIG_CLK_RK3399=y
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CONFIG_CLK_RK3568=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMA=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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CONFIG_CMA_SIZE_MBYTES=16
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# CONFIG_CMA_SIZE_SEL_MAX is not set
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CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_MIN is not set
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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# CONFIG_CMA_SYSFS is not set
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_RK808=y
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CONFIG_COMMON_CLK_ROCKCHIP=y
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CONFIG_COMMON_CLK_SCMI=y
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CONFIG_COMMON_CLK_SCPI=y
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CONFIGFS_FS=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTIG_ALLOC=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_FREQ=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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CONFIG_CPU_FREQ_GOV_COMMON=y
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# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
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CONFIG_CPU_ISOLATION=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CRASH_CORE=y
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CONFIG_CRASH_DUMP=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CRC_T10DIF=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_AES_ARM64=y
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CONFIG_CRYPTO_AES_ARM64_CE=y
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CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
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CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_CRCT10DIF=y
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CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
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CONFIG_CRYPTO_CRYPTD=y
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# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
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CONFIG_CRYPTO_DRBG=y
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CONFIG_CRYPTO_DRBG_HMAC=y
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CONFIG_CRYPTO_DRBG_MENU=y
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CONFIG_CRYPTO_GHASH_ARM64_CE=y
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CONFIG_CRYPTO_HMAC=y
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CONFIG_CRYPTO_JITTERENTROPY=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_RNG=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_SHA512=y
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CONFIG_CRYPTO_SIMD=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
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# CONFIG_DEVFREQ_GOV_PASSIVE is not set
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CONFIG_DEVFREQ_GOV_PERFORMANCE=y
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CONFIG_DEVFREQ_GOV_POWERSAVE=y
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CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
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CONFIG_DEVFREQ_GOV_USERSPACE=y
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# CONFIG_DEVFREQ_THERMAL is not set
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CONFIG_DEVMEM=y
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# CONFIG_DEVPORT is not set
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CONFIG_DMADEVICES=y
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CONFIG_DMA_CMA=y
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CONFIG_DMA_DIRECT_REMAP=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DMA_OPS=y
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CONFIG_DMA_REMAP=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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CONFIG_DWMAC_DWC_QOS_ETH=y
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CONFIG_DWMAC_GENERIC=y
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CONFIG_DWMAC_ROCKCHIP=y
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CONFIG_DW_WATCHDOG=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EMAC_ROCKCHIP=y
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CONFIG_ENERGY_MODEL=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXTCON=y
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CONFIG_F2FS_FS=y
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CONFIG_FANOTIFY=y
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CONFIG_FHANDLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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# CONFIG_FORTIFY_SOURCE is not set
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CONFIG_FRAME_POINTER=y
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CONFIG_FRAME_WARN=2048
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_CPU_VULNERABILITIES=y
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CONFIG_GENERIC_CSUM=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_FIND_FIRST_BIT=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_MIGRATION=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_DWAPB=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_GENERIC_PLATFORM=y
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CONFIG_GPIO_ROCKCHIP=y
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CONFIG_GPIO_SYSCON=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HID=y
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CONFIG_HID_GENERIC=y
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CONFIG_HOTPLUG_CPU=y
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CONFIG_HOTPLUG_PCI=y
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# CONFIG_HOTPLUG_PCI_PCIE is not set
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CONFIG_HUGETLBFS=y
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CONFIG_HUGETLB_PAGE=y
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CONFIG_HWMON=y
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CONFIG_HWSPINLOCK=y
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CONFIG_HW_CONSOLE=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_ROCKCHIP=y
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CONFIG_HZ=250
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_COMPAT=y
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CONFIG_I2C_HELPER_AUTO=y
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CONFIG_I2C_RK3X=y
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# CONFIG_IIO_SCMI is not set
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CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
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CONFIG_INDIRECT_PIO=y
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CONFIG_INPUT=y
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CONFIG_INPUT_EVDEV=y
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CONFIG_INPUT_FF_MEMLESS=y
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CONFIG_INPUT_KEYBOARD=y
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CONFIG_INPUT_LEDS=y
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CONFIG_INPUT_MATRIXKMAP=y
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CONFIG_INPUT_RK805_PWRKEY=y
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CONFIG_IOMMU_API=y
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# CONFIG_IOMMU_DEBUGFS is not set
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CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
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CONFIG_IOMMU_DMA=y
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CONFIG_IOMMU_IOVA=y
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CONFIG_IOMMU_IO_PGTABLE=y
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# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
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CONFIG_IOMMU_IO_PGTABLE_LPAE=y
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# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
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CONFIG_IOMMU_SUPPORT=y
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# CONFIG_IO_STRICT_DEVMEM is not set
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_MSI_IOMMU=y
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CONFIG_IRQ_TIME_ACCOUNTING=y
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CONFIG_IRQ_WORK=y
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CONFIG_JBD2=y
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CONFIG_JFFS2_ZLIB=y
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CONFIG_JUMP_LABEL=y
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CONFIG_KALLSYMS=y
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CONFIG_KEXEC_CORE=y
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CONFIG_KEXEC_FILE=y
|
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CONFIG_KSM=y
|
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# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
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CONFIG_LEDS_GPIO=y
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CONFIG_LEDS_PWM=y
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CONFIG_LEDS_SYSCON=y
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CONFIG_LEDS_TRIGGER_CPU=y
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CONFIG_LEDS_TRIGGER_DISK=y
|
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CONFIG_LEDS_TRIGGER_PANIC=y
|
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CONFIG_LIBCRC32C=y
|
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CONFIG_LIBFDT=y
|
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CONFIG_LOCALVERSION_AUTO=y
|
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
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CONFIG_LOCK_SPIN_ON_OWNER=y
|
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CONFIG_LOG_BUF_SHIFT=19
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CONFIG_MAGIC_SYSRQ=y
|
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CONFIG_MAGIC_SYSRQ_SERIAL=y
|
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CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
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CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_KHADAS_MCU is not set
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
|
||||
# CONFIG_NVMEM_ROCKCHIP_OTP is not set
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PCS_XPCS=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_RK805=y
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
CONFIG_PM_DEVFREQ_EVENT=y
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
# CONFIG_REGULATOR_ARM_SCMI is not set
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SENSORS_ARM_SCMI is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_ROCKCHIP_SFC=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UACCE is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
@ -0,0 +1,25 @@
|
||||
From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Mon, 28 Sep 2020 22:54:52 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY
|
||||
|
||||
This adds the compatible property to the NanoPi R2S ethernet PHY node.
|
||||
Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff
|
||||
when it is still in reset.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -156,6 +156,8 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-id001c.c915",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
pinctrl-0 = <ð_phy_reset_pin>;
|
||||
pinctrl-names = "default";
|
||||
@ -0,0 +1,60 @@
|
||||
From fd573b2bf2d2cf61e835ea68bbaa34c71d4a70d7 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Thu, 15 Sep 2022 10:25:11 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise
|
||||
Edition
|
||||
|
||||
The only diffrence against the standrard edition is that the enterprise
|
||||
one has a built-in EEPROM chip which stores a globally unique MAC address.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220915022511.4267-2-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../rockchip/rk3399-nanopi-r4s-enterprise.dts | 29 +++++++++++++++++++
|
||||
2 files changed, 30 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-na
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts
|
||||
@@ -0,0 +1,29 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3399-nanopi-r4s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R4S Enterprise Edition";
|
||||
+ compatible = "friendlyarm,nanopi-r4s-enterprise", "rockchip,rk3399";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ nvmem-cells = <&mac_address>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
+ eeprom@51 {
|
||||
+ compatible = "microchip,24c02", "atmel,24c02";
|
||||
+ reg = <0x51>;
|
||||
+ pagesize = <16>;
|
||||
+ size = <256>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ mac_address: mac-address@fa {
|
||||
+ reg = <0xfa 0x06>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -0,0 +1,155 @@
|
||||
From d269aa2ab975807764dc2509e4156bb9b6bd0d34 Mon Sep 17 00:00:00 2001
|
||||
From: Sugar Zhang <sugar.zhang@rock-chips.com>
|
||||
Date: Fri, 3 Sep 2021 21:23:24 +0800
|
||||
Subject: [PATCH] ASoC: rockchip: Add support for rv1126 pdm
|
||||
|
||||
This patch adds support for rv1126 pdm controller which
|
||||
redesign cic filiter for better performance.
|
||||
|
||||
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/1630675410-3354-1-git-send-email-sugar.zhang@rock-chips.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/rockchip/rockchip_pdm.c | 76 ++++++++++++++++++++++++++++---
|
||||
sound/soc/rockchip/rockchip_pdm.h | 3 ++
|
||||
2 files changed, 73 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/sound/soc/rockchip/rockchip_pdm.c
|
||||
+++ b/sound/soc/rockchip/rockchip_pdm.c
|
||||
@@ -24,6 +24,7 @@
|
||||
enum rk_pdm_version {
|
||||
RK_PDM_RK3229,
|
||||
RK_PDM_RK3308,
|
||||
+ RK_PDM_RV1126,
|
||||
};
|
||||
|
||||
struct rk_pdm_dev {
|
||||
@@ -121,6 +122,55 @@ static unsigned int get_pdm_ds_ratio(uns
|
||||
return ratio;
|
||||
}
|
||||
|
||||
+static unsigned int get_pdm_cic_ratio(unsigned int clk)
|
||||
+{
|
||||
+ switch (clk) {
|
||||
+ case 4096000:
|
||||
+ case 5644800:
|
||||
+ case 6144000:
|
||||
+ return 0;
|
||||
+ case 2048000:
|
||||
+ case 2822400:
|
||||
+ case 3072000:
|
||||
+ return 1;
|
||||
+ case 1024000:
|
||||
+ case 1411200:
|
||||
+ case 1536000:
|
||||
+ return 2;
|
||||
+ default:
|
||||
+ return 1;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static unsigned int samplerate_to_bit(unsigned int samplerate)
|
||||
+{
|
||||
+ switch (samplerate) {
|
||||
+ case 8000:
|
||||
+ case 11025:
|
||||
+ case 12000:
|
||||
+ return 0;
|
||||
+ case 16000:
|
||||
+ case 22050:
|
||||
+ case 24000:
|
||||
+ return 1;
|
||||
+ case 32000:
|
||||
+ return 2;
|
||||
+ case 44100:
|
||||
+ case 48000:
|
||||
+ return 3;
|
||||
+ case 64000:
|
||||
+ case 88200:
|
||||
+ case 96000:
|
||||
+ return 4;
|
||||
+ case 128000:
|
||||
+ case 176400:
|
||||
+ case 192000:
|
||||
+ return 5;
|
||||
+ default:
|
||||
+ return 1;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai)
|
||||
{
|
||||
return snd_soc_dai_get_drvdata(dai);
|
||||
@@ -166,7 +216,8 @@ static int rockchip_pdm_hw_params(struct
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
- if (pdm->version == RK_PDM_RK3308) {
|
||||
+ if (pdm->version == RK_PDM_RK3308 ||
|
||||
+ pdm->version == RK_PDM_RV1126) {
|
||||
rational_best_approximation(clk_out, clk_src,
|
||||
GENMASK(16 - 1, 0),
|
||||
GENMASK(16 - 1, 0),
|
||||
@@ -194,8 +245,18 @@ static int rockchip_pdm_hw_params(struct
|
||||
PDM_CLK_FD_RATIO_MSK,
|
||||
val);
|
||||
}
|
||||
- val = get_pdm_ds_ratio(samplerate);
|
||||
- regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
|
||||
+
|
||||
+ if (pdm->version == RK_PDM_RV1126) {
|
||||
+ val = get_pdm_cic_ratio(clk_out);
|
||||
+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CIC_RATIO_MSK, val);
|
||||
+ val = samplerate_to_bit(samplerate);
|
||||
+ regmap_update_bits(pdm->regmap, PDM_CTRL0,
|
||||
+ PDM_SAMPLERATE_MSK, PDM_SAMPLERATE(val));
|
||||
+ } else {
|
||||
+ val = get_pdm_ds_ratio(samplerate);
|
||||
+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
|
||||
+ }
|
||||
+
|
||||
regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
|
||||
PDM_HPF_CF_MSK, PDM_HPF_60HZ);
|
||||
regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
|
||||
@@ -442,9 +503,10 @@ static bool rockchip_pdm_precious_reg(st
|
||||
}
|
||||
|
||||
static const struct reg_default rockchip_pdm_reg_defaults[] = {
|
||||
- {0x04, 0x78000017},
|
||||
- {0x08, 0x0bb8ea60},
|
||||
- {0x18, 0x0000001f},
|
||||
+ { PDM_CTRL0, 0x78000017 },
|
||||
+ { PDM_CTRL1, 0x0bb8ea60 },
|
||||
+ { PDM_CLK_CTRL, 0x0000e401 },
|
||||
+ { PDM_DMA_CTRL, 0x0000001f },
|
||||
};
|
||||
|
||||
static const struct regmap_config rockchip_pdm_regmap_config = {
|
||||
@@ -470,6 +532,8 @@ static const struct of_device_id rockchi
|
||||
.data = (void *)RK_PDM_RK3308 },
|
||||
{ .compatible = "rockchip,rk3308-pdm",
|
||||
.data = (void *)RK_PDM_RK3308 },
|
||||
+ { .compatible = "rockchip,rv1126-pdm",
|
||||
+ .data = (void *)RK_PDM_RV1126 },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
|
||||
--- a/sound/soc/rockchip/rockchip_pdm.h
|
||||
+++ b/sound/soc/rockchip/rockchip_pdm.h
|
||||
@@ -41,6 +41,8 @@
|
||||
#define PDM_PATH1_EN BIT(28)
|
||||
#define PDM_PATH0_EN BIT(27)
|
||||
#define PDM_HWT_EN BIT(26)
|
||||
+#define PDM_SAMPLERATE_MSK GENMASK(7, 5)
|
||||
+#define PDM_SAMPLERATE(x) ((x) << 5)
|
||||
#define PDM_VDW_MSK (0x1f << 0)
|
||||
#define PDM_VDW(X) ((X - 1) << 0)
|
||||
|
||||
@@ -66,6 +68,7 @@
|
||||
#define PDM_CLK_1280FS (0x2 << 0)
|
||||
#define PDM_CLK_2560FS (0x3 << 0)
|
||||
#define PDM_CLK_5120FS (0x4 << 0)
|
||||
+#define PDM_CIC_RATIO_MSK (0x3 << 0)
|
||||
|
||||
/* PDM HPF CTRL */
|
||||
#define PDM_HPF_LE BIT(3)
|
||||
@ -0,0 +1,26 @@
|
||||
From d00d1cd4ab42f92d4d871deb9cdea1d7c262a213 Mon Sep 17 00:00:00 2001
|
||||
From: Sugar Zhang <sugar.zhang@rock-chips.com>
|
||||
Date: Fri, 3 Sep 2021 21:23:26 +0800
|
||||
Subject: [PATCH] ASoC: rockchip: pdm: Add support for rk3568 pdm
|
||||
|
||||
This patch adds compatible for rk3568 which is the same
|
||||
with rv1126.
|
||||
|
||||
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/1630675410-3354-3-git-send-email-sugar.zhang@rock-chips.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/rockchip/rockchip_pdm.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/sound/soc/rockchip/rockchip_pdm.c
|
||||
+++ b/sound/soc/rockchip/rockchip_pdm.c
|
||||
@@ -532,6 +532,8 @@ static const struct of_device_id rockchi
|
||||
.data = (void *)RK_PDM_RK3308 },
|
||||
{ .compatible = "rockchip,rk3308-pdm",
|
||||
.data = (void *)RK_PDM_RK3308 },
|
||||
+ { .compatible = "rockchip,rk3568-pdm",
|
||||
+ .data = (void *)RK_PDM_RV1126 },
|
||||
{ .compatible = "rockchip,rv1126-pdm",
|
||||
.data = (void *)RK_PDM_RV1126 },
|
||||
{},
|
||||
@ -0,0 +1,95 @@
|
||||
From 13e6e042a6f9c2be676f421935e026308de3303c Mon Sep 17 00:00:00 2001
|
||||
From: Sugar Zhang <sugar.zhang@rock-chips.com>
|
||||
Date: Fri, 3 Sep 2021 21:23:28 +0800
|
||||
Subject: [PATCH] ASoC: rockchip: pdm: Add support for path map
|
||||
|
||||
This patch adds property 'rockchip,path-map' for path mapping.
|
||||
|
||||
e.g.
|
||||
|
||||
"rockchip,path-map = <3 2 1 0>" means the mapping as follows:
|
||||
|
||||
path0 <-- sdi3
|
||||
path1 <-- sdi2
|
||||
path2 <-- sdi1
|
||||
path3 <-- sdi0
|
||||
|
||||
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/1630675410-3354-5-git-send-email-sugar.zhang@rock-chips.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/rockchip/rockchip_pdm.c | 34 +++++++++++++++++++++++++++++++
|
||||
sound/soc/rockchip/rockchip_pdm.h | 3 +++
|
||||
2 files changed, 37 insertions(+)
|
||||
|
||||
--- a/sound/soc/rockchip/rockchip_pdm.c
|
||||
+++ b/sound/soc/rockchip/rockchip_pdm.c
|
||||
@@ -20,6 +20,7 @@
|
||||
|
||||
#define PDM_DMA_BURST_SIZE (8) /* size * width: 8*4 = 32 bytes */
|
||||
#define PDM_SIGNOFF_CLK_RATE (100000000)
|
||||
+#define PDM_PATH_MAX (4)
|
||||
|
||||
enum rk_pdm_version {
|
||||
RK_PDM_RK3229,
|
||||
@@ -540,8 +541,36 @@ static const struct of_device_id rockchi
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
|
||||
|
||||
+static int rockchip_pdm_path_parse(struct rk_pdm_dev *pdm, struct device_node *node)
|
||||
+{
|
||||
+ unsigned int path[PDM_PATH_MAX];
|
||||
+ int cnt = 0, ret = 0, i = 0, val = 0, msk = 0;
|
||||
+
|
||||
+ cnt = of_count_phandle_with_args(node, "rockchip,path-map",
|
||||
+ NULL);
|
||||
+ if (cnt != PDM_PATH_MAX)
|
||||
+ return cnt;
|
||||
+
|
||||
+ ret = of_property_read_u32_array(node, "rockchip,path-map",
|
||||
+ path, cnt);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ for (i = 0; i < cnt; i++) {
|
||||
+ if (path[i] >= PDM_PATH_MAX)
|
||||
+ return -EINVAL;
|
||||
+ msk |= PDM_PATH_MASK(i);
|
||||
+ val |= PDM_PATH(i, path[i]);
|
||||
+ }
|
||||
+
|
||||
+ regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, msk, val);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rockchip_pdm_probe(struct platform_device *pdev)
|
||||
{
|
||||
+ struct device_node *node = pdev->dev.of_node;
|
||||
const struct of_device_id *match;
|
||||
struct rk_pdm_dev *pdm;
|
||||
struct resource *res;
|
||||
@@ -607,6 +636,11 @@ static int rockchip_pdm_probe(struct pla
|
||||
}
|
||||
|
||||
rockchip_pdm_rxctrl(pdm, 0);
|
||||
+
|
||||
+ ret = rockchip_pdm_path_parse(pdm, node);
|
||||
+ if (ret != 0 && ret != -ENOENT)
|
||||
+ goto err_suspend;
|
||||
+
|
||||
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "could not register pcm: %d\n", ret);
|
||||
--- a/sound/soc/rockchip/rockchip_pdm.h
|
||||
+++ b/sound/soc/rockchip/rockchip_pdm.h
|
||||
@@ -53,6 +53,9 @@
|
||||
#define PDM_FD_DENOMINATOR_MSK GENMASK(15, 0)
|
||||
|
||||
/* PDM CLK CTRL */
|
||||
+#define PDM_PATH_SHIFT(x) (8 + (x) * 2)
|
||||
+#define PDM_PATH_MASK(x) (0x3 << PDM_PATH_SHIFT(x))
|
||||
+#define PDM_PATH(x, v) ((v) << PDM_PATH_SHIFT(x))
|
||||
#define PDM_CLK_FD_RATIO_MSK BIT(6)
|
||||
#define PDM_CLK_FD_RATIO_40 (0X0 << 6)
|
||||
#define PDM_CLK_FD_RATIO_35 BIT(6)
|
||||
@ -0,0 +1,32 @@
|
||||
From 1330875dc2a3742fd41127e78d5036f2d8f261da Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 28 Jul 2021 14:00:31 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3568 tsadc nodes
|
||||
|
||||
Add the thermal and tsadc nodes to the rk3568 device tree.
|
||||
There are two sensors, one for the cpu, one for the gpu.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 9 +++
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++
|
||||
2 files changed, 79 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
|
||||
@@ -3108,4 +3108,13 @@
|
||||
<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ tsadc {
|
||||
+ /omit-if-no-ref/
|
||||
+ tsadc_pin: tsadc-pin {
|
||||
+ rockchip,pins =
|
||||
+ /* tsadc_pin */
|
||||
+ <0 RK_PA1 0 &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
@ -0,0 +1,28 @@
|
||||
From 02832ed8ae2c8b130efea4e43d3ecac50b4b7933 Mon Sep 17 00:00:00 2001
|
||||
From: Johan Jonker <jbx6244@gmail.com>
|
||||
Date: Thu, 30 Sep 2021 13:05:16 +0200
|
||||
Subject: [PATCH] thermal/drivers/rockchip_thermal: Allow more resets for tsadc
|
||||
node
|
||||
|
||||
The tsadc node in rk356x.dtsi has more resets then currently supported
|
||||
by the rockchip_thermal.c driver, so use
|
||||
devm_reset_control_array_get() to reset them all.
|
||||
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210930110517.14323-3-jbx6244@gmail.com
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -1383,7 +1383,7 @@ static int rockchip_thermal_probe(struct
|
||||
if (IS_ERR(thermal->regs))
|
||||
return PTR_ERR(thermal->regs);
|
||||
|
||||
- thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
|
||||
+ thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
|
||||
if (IS_ERR(thermal->reset)) {
|
||||
error = PTR_ERR(thermal->reset);
|
||||
dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
|
||||
@ -0,0 +1,27 @@
|
||||
From 4d94b98f2e2407e3f053b2546f86c76179fea644 Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megous@megous.com>
|
||||
Date: Sun, 29 Aug 2021 04:51:53 +0200
|
||||
Subject: [PATCH] mfd: rk808: Add support for power off on RK817
|
||||
|
||||
RK817 has a power-off bit in SYS_CFG3. Add support for powering
|
||||
off the PMIC.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megous@megous.com>
|
||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
||||
---
|
||||
drivers/mfd/rk808.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -543,6 +543,10 @@ static void rk808_pm_power_off(void)
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
break;
|
||||
+ case RK817_ID:
|
||||
+ reg = RK817_SYS_CFG(3);
|
||||
+ bit = DEV_OFF;
|
||||
+ break;
|
||||
case RK818_ID:
|
||||
reg = RK818_DEVCTRL_REG;
|
||||
bit = DEV_OFF;
|
||||
@ -0,0 +1,45 @@
|
||||
From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:47 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2
|
||||
|
||||
New Rockchip devices have the usb phy nodes as standalone devices.
|
||||
These nodes have register nodes with #address_cells = 2, but only use 32
|
||||
bit addresses.
|
||||
|
||||
Adjust the driver to check if the returned address is "0", and adjust
|
||||
the index in that case.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++-
|
||||
1 file changed, 10 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1100,12 +1100,21 @@ static int rockchip_usb2phy_probe(struct
|
||||
rphy->usbgrf = NULL;
|
||||
}
|
||||
|
||||
- if (of_property_read_u32(np, "reg", ®)) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 0, ®)) {
|
||||
dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
+ /* support address_cells=2 */
|
||||
+ if (reg == 0) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 1, ®)) {
|
||||
+ dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
+ np);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
rphy->dev = dev;
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
@ -0,0 +1,237 @@
|
||||
From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:49 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts
|
||||
|
||||
The rk3568 usb2phy has a single muxed interrupt that handles all
|
||||
interrupts.
|
||||
Allow the driver to plug in only a single interrupt as necessary.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++-----
|
||||
1 file changed, 119 insertions(+), 49 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port {
|
||||
* @dcd_retries: The retry count used to track Data contact
|
||||
* detection process.
|
||||
* @edev: extcon device for notification registration
|
||||
+ * @irq: muxed interrupt for single irq configuration
|
||||
* @phy_cfg: phy register configuration, assigned by driver data.
|
||||
* @ports: phy port instance.
|
||||
*/
|
||||
@@ -218,6 +219,7 @@ struct rockchip_usb2phy {
|
||||
enum power_supply_type chg_type;
|
||||
u8 dcd_retries;
|
||||
struct extcon_dev *edev;
|
||||
+ int irq;
|
||||
const struct rockchip_usb2phy_cfg *phy_cfg;
|
||||
struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
|
||||
};
|
||||
@@ -936,6 +938,102 @@ static irqreturn_t rockchip_usb2phy_otg_
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
|
||||
+{
|
||||
+ struct rockchip_usb2phy *rphy = data;
|
||||
+ struct rockchip_usb2phy_port *rport;
|
||||
+ irqreturn_t ret = IRQ_NONE;
|
||||
+ unsigned int index;
|
||||
+
|
||||
+ for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
|
||||
+ rport = &rphy->ports[index];
|
||||
+ if (!rport->phy)
|
||||
+ continue;
|
||||
+
|
||||
+ /* Handle linestate irq for both otg port and host port */
|
||||
+ ret = rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
|
||||
+ struct rockchip_usb2phy_port *rport,
|
||||
+ struct device_node *child_np)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ /*
|
||||
+ * If the usb2 phy used combined irq for otg and host port,
|
||||
+ * don't need to init otg and host port irq separately.
|
||||
+ */
|
||||
+ if (rphy->irq > 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ switch (rport->port_id) {
|
||||
+ case USB2PHY_PORT_HOST:
|
||||
+ rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
+ if (rport->ls_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
+ return rport->ls_irq;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
+ rockchip_usb2phy_linestate_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy", rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ break;
|
||||
+ case USB2PHY_PORT_OTG:
|
||||
+ /*
|
||||
+ * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
+ * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
+ * if not found, then look for the regular interrupts one by one.
|
||||
+ */
|
||||
+ rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
+ if (rport->otg_mux_irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_otg_mux_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_otg",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-mux irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ } else {
|
||||
+ rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
+ if (rport->bvalid_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
+ ret = rport->bvalid_irq;
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_bvalid_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_bvalid",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-bvalid irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
@@ -949,18 +1047,9 @@ static int rockchip_usb2phy_host_port_in
|
||||
mutex_init(&rport->mutex);
|
||||
INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
|
||||
|
||||
- rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
- if (rport->ls_irq < 0) {
|
||||
- dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
- return rport->ls_irq;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
- rockchip_usb2phy_linestate_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy", rport);
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
if (ret) {
|
||||
- dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ dev_err(rphy->dev, "failed to setup host irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -1009,44 +1098,10 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
|
||||
INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
|
||||
|
||||
- /*
|
||||
- * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
- * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
- * if not found, then look for the regular interrupts one by one.
|
||||
- */
|
||||
- rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
- if (rport->otg_mux_irq > 0) {
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_otg_mux_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_otg",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-mux irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- } else {
|
||||
- rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
- if (rport->bvalid_irq < 0) {
|
||||
- dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
- ret = rport->bvalid_irq;
|
||||
- goto out;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_bvalid_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_bvalid",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-bvalid irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- }
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
+ goto out;
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1119,6 +1174,7 @@ static int rockchip_usb2phy_probe(struct
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
|
||||
+ rphy->irq = platform_get_irq_optional(pdev, 0);
|
||||
platform_set_drvdata(pdev, rphy);
|
||||
|
||||
ret = rockchip_usb2phy_extcon_register(rphy);
|
||||
@@ -1198,6 +1254,20 @@ next_child:
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+
|
||||
+ if (rphy->irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
|
||||
+ rockchip_usb2phy_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy",
|
||||
+ rphy);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request usb2phy irq handle\n");
|
||||
+ goto put_child;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
return PTR_ERR_OR_ZERO(provider);
|
||||
|
||||
put_child:
|
||||
@ -0,0 +1,44 @@
|
||||
From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:48 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes
|
||||
|
||||
New Rockchip devices have the usb2 phy devices as standalone nodes
|
||||
instead of children of the grf node.
|
||||
Allow the driver to find the grf node from a phandle.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++-----
|
||||
1 file changed, 12 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1138,12 +1138,19 @@ static int rockchip_usb2phy_probe(struct
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- if (!dev->parent || !dev->parent->of_node)
|
||||
- return -EINVAL;
|
||||
+ if (!dev->parent || !dev->parent->of_node) {
|
||||
+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
|
||||
+ if (IS_ERR(rphy->grf)) {
|
||||
+ dev_err(dev, "failed to locate usbgrf\n");
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
+ }
|
||||
|
||||
- rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
- if (IS_ERR(rphy->grf))
|
||||
- return PTR_ERR(rphy->grf);
|
||||
+ else {
|
||||
+ rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(rphy->grf))
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
|
||||
if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
|
||||
rphy->usbgrf =
|
||||
@ -0,0 +1,104 @@
|
||||
From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:50 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support
|
||||
|
||||
The rk3568 usb2phy is a standalone device with a single muxed interrupt.
|
||||
Add support for the registers to the usb2phy driver.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++
|
||||
1 file changed, 65 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1102,6 +1102,7 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
if (ret) {
|
||||
dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
goto out;
|
||||
+ }
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1513,6 +1514,69 @@ static const struct rockchip_usb2phy_cfg
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
|
||||
+ {
|
||||
+ .reg = 0xfe8a0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
|
||||
+ .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
|
||||
+ .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
|
||||
+ .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ /* Select suspend control from controller */
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ .chg_det = {
|
||||
+ .opmode = { 0x0000, 3, 0, 5, 1 },
|
||||
+ .cp_det = { 0x00c0, 24, 24, 0, 1 },
|
||||
+ .dcp_det = { 0x00c0, 23, 23, 0, 1 },
|
||||
+ .dp_det = { 0x00c0, 25, 25, 0, 1 },
|
||||
+ .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
|
||||
+ .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
|
||||
+ .idp_src_en = { 0x0008, 9, 9, 0, 1 },
|
||||
+ .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
|
||||
+ .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
|
||||
+ .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .reg = 0xfe8b0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x100,
|
||||
@@ -1562,6 +1626,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
|
||||
+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
|
||||
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
|
||||
{}
|
||||
};
|
||||
@ -0,0 +1,44 @@
|
||||
From 842f4cb7263953020f4e2f2f0005fc3e6fc56144 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Wed, 26 Jan 2022 15:55:33 +0100
|
||||
Subject: [PATCH] clk: rockchip: Add more PLL rates for rk3568
|
||||
|
||||
This adds a few more PLL settings needed for some standard resolutions:
|
||||
|
||||
297MHz 3840x2160-30.00
|
||||
241.5MHz 2560x1440-59.95
|
||||
135MHz 1280x1024-75.02
|
||||
119MHz 1680x1050-59.88
|
||||
108MHz 1280x1024-60.02
|
||||
78.75MHz 1024x768-75.03
|
||||
|
||||
Changes since v3:
|
||||
- new patch
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3568.c | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3568.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3568.c
|
||||
@@ -71,11 +71,17 @@ static struct rockchip_pll_rate_table rk
|
||||
RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
|
||||
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
|
||||
RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
|
||||
+ RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
|
||||
+ RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
|
||||
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
|
||||
RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
|
||||
RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
|
||||
+ RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
|
||||
+ RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
|
||||
+ RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
|
||||
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
|
||||
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
|
||||
+ RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
|
||||
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
@ -0,0 +1,52 @@
|
||||
From 6e69052f01d9131388cfcfaee929120118a267f4 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Wed, 26 Jan 2022 15:55:47 +0100
|
||||
Subject: [PATCH] clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference
|
||||
clock on rk3568
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
On the rk3568 we have this (simplified) situation:
|
||||
|
||||
.--------. .-----. .---------.
|
||||
-| hpll |--.--| /n |----|dclk_vop0|-
|
||||
`--------´ | `-----´ `---------´
|
||||
| .-----. .---------.
|
||||
`--| /m |----|dclk_vop1|-
|
||||
| `-----´ `---------´
|
||||
| .---------.
|
||||
`-------------|hdmi_ref |-
|
||||
`---------´
|
||||
|
||||
For the HDMI to work the HDMI reference clock needs to be the same as the
|
||||
pixel clock which means the dividers have be set to one. The last patch removed
|
||||
the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not
|
||||
changed on pixel clock changes. In order to allow the HDMI controller to
|
||||
set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the
|
||||
HDMI reference clock. With this the flow becomes:
|
||||
|
||||
1) HDMI controller driver sets the rate to its pixel clock which means
|
||||
hpll is set to the pixel clock
|
||||
2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change
|
||||
the hpll clock anymore this means only the divider is adjusted to the
|
||||
desired value of dividing by one.
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Link: https://lore.kernel.org/r/20220126145549.617165-26-s.hauer@pengutronix.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3568.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3568.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3568.c
|
||||
@@ -1568,7 +1568,7 @@ static struct rockchip_clk_branch rk3568
|
||||
RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
|
||||
GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
|
||||
RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
|
||||
- MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0,
|
||||
+ MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
|
||||
RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
|
||||
};
|
||||
|
||||
@ -0,0 +1,49 @@
|
||||
From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001
|
||||
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Date: Tue, 8 Feb 2022 17:13:25 +0800
|
||||
Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568
|
||||
|
||||
This patch implements a combo phy driver for Rockchip SoCs
|
||||
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
|
||||
sata-phy or sgmii-phy.
|
||||
|
||||
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Tested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 8 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++
|
||||
3 files changed, 590 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
|
||||
Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
|
||||
Innosilicon IP block.
|
||||
|
||||
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
|
||||
+ tristate "Rockchip NANENG COMBO PHY Driver"
|
||||
+ depends on ARCH_ROCKCHIP && OF
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
|
||||
+ combo PHY with NaNeng IP block.
|
||||
+
|
||||
config PHY_ROCKCHIP_PCIE
|
||||
tristate "Rockchip PCIe PHY Driver"
|
||||
depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
@ -0,0 +1,54 @@
|
||||
From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:34 -0500
|
||||
Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers
|
||||
|
||||
Host drivers may not be able to support frequencies as low as dw-mmc
|
||||
supports. Unfortunately f_min isn't available when the drv_data->init
|
||||
function is called, as the mmc_host struct hasn't been set up yet.
|
||||
|
||||
Support the host drivers saving the requested minimum frequency, so we
|
||||
can later set f_min when it is available.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc.c | 7 ++++++-
|
||||
drivers/mmc/host/dw_mmc.h | 2 ++
|
||||
2 files changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.c
|
||||
+++ b/drivers/mmc/host/dw_mmc.c
|
||||
@@ -2853,7 +2853,12 @@ static int dw_mci_init_slot_caps(struct
|
||||
if (host->pdata->caps2)
|
||||
mmc->caps2 = host->pdata->caps2;
|
||||
|
||||
- mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+ /* if host has set a minimum_freq, we should respect it */
|
||||
+ if (host->minimum_speed)
|
||||
+ mmc->f_min = host->minimum_speed;
|
||||
+ else
|
||||
+ mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+
|
||||
if (!mmc->f_max)
|
||||
mmc->f_max = DW_MCI_FREQ_MAX;
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.h
|
||||
+++ b/drivers/mmc/host/dw_mmc.h
|
||||
@@ -99,6 +99,7 @@ struct dw_mci_dma_slave {
|
||||
* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
|
||||
* rate and timeout calculations.
|
||||
* @current_speed: Configured rate of the controller.
|
||||
+ * @minimum_speed: Stored minimum rate of the controller.
|
||||
* @fifoth_val: The value of FIFOTH register.
|
||||
* @verid: Denote Version ID.
|
||||
* @dev: Device associated with the MMC controller.
|
||||
@@ -200,6 +201,7 @@ struct dw_mci {
|
||||
|
||||
u32 bus_hz;
|
||||
u32 current_speed;
|
||||
+ u32 minimum_speed;
|
||||
u32 fifoth_val;
|
||||
u16 verid;
|
||||
struct device *dev;
|
||||
@ -0,0 +1,79 @@
|
||||
From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:35 -0500
|
||||
Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates
|
||||
|
||||
The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc
|
||||
hardware supports. This leads to a situation during card initialization
|
||||
where the clock is set lower than the clock driver can support. The
|
||||
dw-mmc-rockchip driver spews errors when this happens.
|
||||
For normal operation this only happens a few times during boot, but when
|
||||
cd-broken is enabled (in cases such as the SoQuartz module) this fires
|
||||
multiple times each poll cycle.
|
||||
|
||||
Fix this by testing the lowest possible frequency that the clock driver
|
||||
can support which is within the mmc specification. Divide that rate by
|
||||
the internal divider and set f_min to this.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++----
|
||||
1 file changed, 23 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
@@ -15,7 +15,9 @@
|
||||
#include "dw_mmc.h"
|
||||
#include "dw_mmc-pltfm.h"
|
||||
|
||||
-#define RK3288_CLKGEN_DIV 2
|
||||
+#define RK3288_CLKGEN_DIV 2
|
||||
+
|
||||
+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
|
||||
|
||||
struct dw_mci_rockchip_priv_data {
|
||||
struct clk *drv_clk;
|
||||
@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct
|
||||
|
||||
ret = clk_set_rate(host->ciu_clk, cclkin);
|
||||
if (ret)
|
||||
- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
|
||||
+ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
|
||||
|
||||
bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
|
||||
if (bus_hz != host->bus_hz) {
|
||||
@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct
|
||||
|
||||
static int dw_mci_rockchip_init(struct dw_mci *host)
|
||||
{
|
||||
+ int ret, i;
|
||||
+
|
||||
/* It is slot 8 on Rockchip SoCs */
|
||||
host->sdio_id0 = 8;
|
||||
|
||||
- if (of_device_is_compatible(host->dev->of_node,
|
||||
- "rockchip,rk3288-dw-mshc"))
|
||||
+ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
|
||||
host->bus_hz /= RK3288_CLKGEN_DIV;
|
||||
|
||||
+ /* clock driver will fail if the clock is less than the lowest source clock
|
||||
+ * divided by the internal clock divider. Test for the lowest available
|
||||
+ * clock and set the minimum freq to clock / clock divider.
|
||||
+ */
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(freqs); i++) {
|
||||
+ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
|
||||
+ if (ret > 0) {
|
||||
+ host->minimum_speed = ret / RK3288_CLKGEN_DIV;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ if (ret < 0)
|
||||
+ dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -0,0 +1,110 @@
|
||||
From 56f216d8efbc1212bf5ff8a6ff5e29927965e8db Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Tue, 8 Feb 2022 14:40:23 -0500
|
||||
Subject: [PATCH] mfd: rk808: Add reboot support to rk808.c
|
||||
|
||||
This adds reboot support to the rk808 pmic driver and enables it for
|
||||
the rk809 and rk817 devices.
|
||||
This only enables if the rockchip,system-power-controller flag is set.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
|
||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20220208194023.929720-1-pgwipeout@gmail.com
|
||||
---
|
||||
drivers/mfd/rk808.c | 44 +++++++++++++++++++++++++++++++++++++++
|
||||
include/linux/mfd/rk808.h | 1 +
|
||||
2 files changed, 45 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/regmap.h>
|
||||
+#include <linux/reboot.h>
|
||||
|
||||
struct rk808_reg_data {
|
||||
int addr;
|
||||
@@ -543,6 +544,7 @@ static void rk808_pm_power_off(void)
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
break;
|
||||
+ case RK809_ID:
|
||||
case RK817_ID:
|
||||
reg = RK817_SYS_CFG(3);
|
||||
bit = DEV_OFF;
|
||||
@@ -559,6 +561,34 @@ static void rk808_pm_power_off(void)
|
||||
dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
|
||||
}
|
||||
|
||||
+static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd)
|
||||
+{
|
||||
+ struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
|
||||
+ unsigned int reg, bit;
|
||||
+ int ret;
|
||||
+
|
||||
+ switch (rk808->variant) {
|
||||
+ case RK809_ID:
|
||||
+ case RK817_ID:
|
||||
+ reg = RK817_SYS_CFG(3);
|
||||
+ bit = DEV_RST;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ return NOTIFY_DONE;
|
||||
+ }
|
||||
+ ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
|
||||
+ if (ret)
|
||||
+ dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n");
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
+}
|
||||
+
|
||||
+static struct notifier_block rk808_restart_handler = {
|
||||
+ .notifier_call = rk808_restart_notify,
|
||||
+ .priority = 192,
|
||||
+};
|
||||
+
|
||||
static void rk8xx_shutdown(struct i2c_client *client)
|
||||
{
|
||||
struct rk808 *rk808 = i2c_get_clientdata(client);
|
||||
@@ -727,6 +757,18 @@ static int rk808_probe(struct i2c_client
|
||||
if (of_property_read_bool(np, "rockchip,system-power-controller")) {
|
||||
rk808_i2c_client = client;
|
||||
pm_power_off = rk808_pm_power_off;
|
||||
+
|
||||
+ switch (rk808->variant) {
|
||||
+ case RK809_ID:
|
||||
+ case RK817_ID:
|
||||
+ ret = register_restart_handler(&rk808_restart_handler);
|
||||
+ if (ret)
|
||||
+ dev_warn(&client->dev, "failed to register rst handler, %d\n", ret);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_dbg(&client->dev, "pmic controlled board reset not supported\n");
|
||||
+ break;
|
||||
+ }
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -749,6 +791,8 @@ static int rk808_remove(struct i2c_clien
|
||||
if (pm_power_off == rk808_pm_power_off)
|
||||
pm_power_off = NULL;
|
||||
|
||||
+ unregister_restart_handler(&rk808_restart_handler);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/include/linux/mfd/rk808.h
|
||||
+++ b/include/linux/mfd/rk808.h
|
||||
@@ -373,6 +373,7 @@ enum rk805_reg {
|
||||
#define SWITCH2_EN BIT(6)
|
||||
#define SWITCH1_EN BIT(5)
|
||||
#define DEV_OFF_RST BIT(3)
|
||||
+#define DEV_RST BIT(2)
|
||||
#define DEV_OFF BIT(0)
|
||||
#define RTC_STOP BIT(0)
|
||||
|
||||
@ -0,0 +1,46 @@
|
||||
From 62b20e6e0dde8d5633e3d94b028f86fb24b31d22 Mon Sep 17 00:00:00 2001
|
||||
From: Bin Yang <yangbin@rock-chips.com>
|
||||
Date: Mon, 28 Feb 2022 08:56:56 -0500
|
||||
Subject: [PATCH] usb: dwc3: core: do not use 3.0 clock when operating in 2.0
|
||||
mode
|
||||
|
||||
In the 3.0 device core, if the core is programmed to operate in
|
||||
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
|
||||
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
|
||||
clock. Enabling this feature allows the pipe3 clock to be not-running
|
||||
when forcibly operating in 2.0 device mode.
|
||||
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220228135700.1089526-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/usb/dwc3/core.c | 5 +++++
|
||||
drivers/usb/dwc3/core.h | 1 +
|
||||
2 files changed, 6 insertions(+)
|
||||
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -1090,6 +1090,11 @@ static int dwc3_core_init(struct dwc3 *d
|
||||
if (dwc->parkmode_disable_ss_quirk)
|
||||
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
|
||||
|
||||
+ if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
|
||||
+ (dwc->maximum_speed == USB_SPEED_HIGH ||
|
||||
+ dwc->maximum_speed == USB_SPEED_FULL))
|
||||
+ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
|
||||
+
|
||||
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
||||
}
|
||||
|
||||
--- a/drivers/usb/dwc3/core.h
|
||||
+++ b/drivers/usb/dwc3/core.h
|
||||
@@ -258,6 +258,7 @@
|
||||
/* Global User Control 1 Register */
|
||||
#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
|
||||
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
|
||||
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
|
||||
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
|
||||
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
|
||||
#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
|
||||
@ -0,0 +1,51 @@
|
||||
From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 8 Apr 2022 11:12:34 -0400
|
||||
Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566
|
||||
|
||||
The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to
|
||||
the combophy as the clock source. As combophy0 doesn't exist on rk3566,
|
||||
we need to set the clock source to the usb2 phy instead.
|
||||
|
||||
Add handling to the grf driver to handle this on boot.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/soc/rockchip/grf.c | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/drivers/soc/rockchip/grf.c
|
||||
+++ b/drivers/soc/rockchip/grf.c
|
||||
@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk
|
||||
.num_values = ARRAY_SIZE(rk3399_defaults),
|
||||
};
|
||||
|
||||
+#define RK3566_GRF_USB3OTG0_CON1 0x0104
|
||||
+
|
||||
+static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
|
||||
+ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
|
||||
+ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
|
||||
+ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
|
||||
+ .values = rk3566_defaults,
|
||||
+ .num_values = ARRAY_SIZE(rk3566_defaults),
|
||||
+};
|
||||
+
|
||||
+
|
||||
static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
|
||||
{
|
||||
.compatible = "rockchip,rk3036-grf",
|
||||
@@ -130,6 +144,9 @@ static const struct of_device_id rockchi
|
||||
}, {
|
||||
.compatible = "rockchip,rk3399-grf",
|
||||
.data = (void *)&rk3399_grf,
|
||||
+ }, {
|
||||
+ .compatible = "rockchip,rk3566-pipe-grf",
|
||||
+ .data = (void *)&rk3566_pipegrf,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
@ -0,0 +1,71 @@
|
||||
From 5f6bfab6da6531238e899fdf29efd6d0185adc3e Mon Sep 17 00:00:00 2001
|
||||
From: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
|
||||
Date: Mon, 14 Feb 2022 21:29:53 +0000
|
||||
Subject: [PATCH] media: hantro: Add support for Hantro G1 on RK356x
|
||||
|
||||
RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8
|
||||
video formats.
|
||||
|
||||
This patch adds support for RK356x family in existing Hantro
|
||||
video decoder kernel driver.
|
||||
|
||||
Tested on [1] with FFmpeg v4l2_request code taken from [2]
|
||||
with MPEG2, H.642 and VP8 samples with results [3].
|
||||
|
||||
[1] https://github.com/warpme/minimyth2
|
||||
[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
|
||||
[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt
|
||||
|
||||
Signed-off-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
|
||||
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
|
||||
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
---
|
||||
drivers/staging/media/hantro/hantro_drv.c | 1 +
|
||||
drivers/staging/media/hantro/hantro_hw.h | 1 +
|
||||
drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 ++++++++++++++
|
||||
3 files changed, 16 insertions(+)
|
||||
|
||||
--- a/drivers/staging/media/hantro/hantro_drv.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_drv.c
|
||||
@@ -588,6 +588,7 @@ static const struct of_device_id of_hant
|
||||
{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
|
||||
{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
|
||||
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
|
||||
+ { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
|
||||
#endif
|
||||
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
|
||||
{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
|
||||
--- a/drivers/staging/media/hantro/hantro_hw.h
|
||||
+++ b/drivers/staging/media/hantro/hantro_hw.h
|
||||
@@ -215,6 +215,7 @@ extern const struct hantro_variant rk306
|
||||
extern const struct hantro_variant rk3288_vpu_variant;
|
||||
extern const struct hantro_variant rk3328_vpu_variant;
|
||||
extern const struct hantro_variant rk3399_vpu_variant;
|
||||
+extern const struct hantro_variant rk3568_vpu_variant;
|
||||
extern const struct hantro_variant sama5d4_vdec_variant;
|
||||
|
||||
extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
|
||||
--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
@@ -551,6 +551,20 @@ const struct hantro_variant rk3399_vpu_v
|
||||
.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
|
||||
};
|
||||
|
||||
+const struct hantro_variant rk3568_vpu_variant = {
|
||||
+ .dec_offset = 0x400,
|
||||
+ .dec_fmts = rk3399_vpu_dec_fmts,
|
||||
+ .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
|
||||
+ .codec = HANTRO_MPEG2_DECODER |
|
||||
+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
|
||||
+ .codec_ops = rk3399_vpu_codec_ops,
|
||||
+ .irqs = rockchip_vdpu2_irqs,
|
||||
+ .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
|
||||
+ .init = rockchip_vpu_hw_init,
|
||||
+ .clk_names = rockchip_vpu_clk_names,
|
||||
+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
|
||||
+};
|
||||
+
|
||||
const struct hantro_variant px30_vpu_variant = {
|
||||
.enc_offset = 0x0,
|
||||
.enc_fmts = rockchip_vpu_enc_fmts,
|
||||
@ -0,0 +1,42 @@
|
||||
From 6a98df08ccd55e87947d253b19925691763e755c Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
Date: Wed, 13 Apr 2022 22:22:52 -0500
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Fix muxed interrupt support
|
||||
|
||||
This commit fixes two issues with the muxed interrupt handler. First,
|
||||
the OTG port has the "bvalid" interrupt enabled, not "linestate". Since
|
||||
only the linestate interrupt was handled, and not the bvalid interrupt,
|
||||
plugging in a cable to the OTG port caused an interrupt storm.
|
||||
|
||||
Second, the return values from the individual port IRQ handlers need to
|
||||
be OR-ed together. Otherwise, the lack of an interrupt from the last
|
||||
port would cause the handler to erroneously return IRQ_NONE.
|
||||
|
||||
Fixes: ed2b5a8e6b98 ("phy: phy-rockchip-inno-usb2: support muxed interrupts")
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220414032258.40984-2-samuel@sholland.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++++++--
|
||||
1 file changed, 8 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -950,8 +950,14 @@ static irqreturn_t rockchip_usb2phy_irq(
|
||||
if (!rport->phy)
|
||||
continue;
|
||||
|
||||
- /* Handle linestate irq for both otg port and host port */
|
||||
- ret = rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
+ switch (rport->port_id) {
|
||||
+ case USB2PHY_PORT_OTG:
|
||||
+ ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
|
||||
+ break;
|
||||
+ case USB2PHY_PORT_HOST:
|
||||
+ ret |= rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
+ break;
|
||||
+ }
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -0,0 +1,37 @@
|
||||
From 656f7fcb1272df590e10cb82e07cd2b79bbf60d1 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
Date: Wed, 13 Apr 2022 22:22:53 -0500
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Do not check bvalid twice
|
||||
|
||||
The bvalid interrupt handler already checks bvalid status. The muxed IRQ
|
||||
handler just needs to call the other handler (plus any other handlers
|
||||
that will be added).
|
||||
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220414032258.40984-3-samuel@sholland.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++------
|
||||
1 file changed, 4 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -929,13 +929,11 @@ static irqreturn_t rockchip_usb2phy_bval
|
||||
|
||||
static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
|
||||
{
|
||||
- struct rockchip_usb2phy_port *rport = data;
|
||||
- struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
|
||||
+ irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
- if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
|
||||
- return rockchip_usb2phy_bvalid_irq(irq, data);
|
||||
- else
|
||||
- return IRQ_NONE;
|
||||
+ ret |= rockchip_usb2phy_bvalid_irq(irq, data);
|
||||
+
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
|
||||
@ -0,0 +1,31 @@
|
||||
From 5a709a46e4270a6130877c052260d9a6d14ac685 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
Date: Wed, 13 Apr 2022 22:22:54 -0500
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Do not lock in bvalid IRQ handler
|
||||
|
||||
Clearing the IRQ is atomic, so there is no need to hold the mutex.
|
||||
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220414032258.40984-4-samuel@sholland.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 ----
|
||||
1 file changed, 4 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -915,13 +915,9 @@ static irqreturn_t rockchip_usb2phy_bval
|
||||
if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
|
||||
return IRQ_NONE;
|
||||
|
||||
- mutex_lock(&rport->mutex);
|
||||
-
|
||||
/* clear bvalid detect irq pending status */
|
||||
property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
|
||||
|
||||
- mutex_unlock(&rport->mutex);
|
||||
-
|
||||
rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
@ -0,0 +1,29 @@
|
||||
From ffe597d04db2b75d9c547a2d2e07c268c2a33117 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
Date: Wed, 13 Apr 2022 22:22:55 -0500
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Support multi-bit mask properties
|
||||
|
||||
The "bvalid" and "id" interrupts can trigger on either the rising edge
|
||||
or the falling edge, so each interrupt has two enable bits and two
|
||||
status bits. This change allows using a single property for both bits,
|
||||
checking whether either bit is set.
|
||||
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220414032258.40984-5-samuel@sholland.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -253,7 +253,7 @@ static inline bool property_enabled(stru
|
||||
return false;
|
||||
|
||||
tmp = (orig & mask) >> reg->bitstart;
|
||||
- return tmp == reg->enable;
|
||||
+ return tmp != reg->disable;
|
||||
}
|
||||
|
||||
static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
|
||||
@ -0,0 +1,58 @@
|
||||
From 21a470606ed5e8b14980f34cd360595d1cba737f Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
Date: Wed, 13 Apr 2022 22:22:56 -0500
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Handle bvalid falling
|
||||
|
||||
Some SoCs have a bvalid falling interrupt, in addition to bvalid rising.
|
||||
This interrupt can detect OTG cable plugout immediately, so it can avoid
|
||||
the delay until the next scheduled work.
|
||||
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220414032258.40984-6-samuel@sholland.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 18 +++++++++---------
|
||||
1 file changed, 9 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1355,9 +1355,9 @@ static const struct rockchip_usb2phy_cfg
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
|
||||
- .bvalid_det_en = { 0x3020, 2, 2, 0, 1 },
|
||||
- .bvalid_det_st = { 0x3024, 2, 2, 0, 1 },
|
||||
- .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_en = { 0x3020, 3, 2, 0, 3 },
|
||||
+ .bvalid_det_st = { 0x3024, 3, 2, 0, 3 },
|
||||
+ .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
|
||||
.ls_det_en = { 0x3020, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x3024, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x3028, 0, 0, 0, 1 },
|
||||
@@ -1398,9 +1398,9 @@ static const struct rockchip_usb2phy_cfg
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
|
||||
- .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
|
||||
- .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
|
||||
- .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
|
||||
+ .bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
|
||||
+ .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
|
||||
.ls_det_en = { 0x0110, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x0114, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x0118, 0, 0, 0, 1 },
|
||||
@@ -1522,9 +1522,9 @@ static const struct rockchip_usb2phy_cfg
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
|
||||
- .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
|
||||
- .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
|
||||
- .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_en = { 0x0080, 3, 2, 0, 3 },
|
||||
+ .bvalid_det_st = { 0x0084, 3, 2, 0, 3 },
|
||||
+ .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
|
||||
.utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
|
||||
.utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
|
||||
},
|
||||
@ -0,0 +1,230 @@
|
||||
From 51a9b2c03dd3fddc56c2f68740fade2e38a066d0 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
Date: Wed, 13 Apr 2022 22:22:57 -0500
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Handle ID IRQ
|
||||
|
||||
This supports detecting host mode for the OTG port without an extcon.
|
||||
|
||||
The rv1108 properties are not updated due to lack of documentation.
|
||||
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220414032258.40984-7-samuel@sholland.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 85 +++++++++++++++++++
|
||||
1 file changed, 85 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -116,11 +116,15 @@ struct rockchip_chg_det_reg {
|
||||
* @bvalid_det_en: vbus valid rise detection enable register.
|
||||
* @bvalid_det_st: vbus valid rise detection status register.
|
||||
* @bvalid_det_clr: vbus valid rise detection clear register.
|
||||
+ * @id_det_en: id detection enable register.
|
||||
+ * @id_det_st: id detection state register.
|
||||
+ * @id_det_clr: id detection clear register.
|
||||
* @ls_det_en: linestate detection enable register.
|
||||
* @ls_det_st: linestate detection state register.
|
||||
* @ls_det_clr: linestate detection clear register.
|
||||
* @utmi_avalid: utmi vbus avalid status register.
|
||||
* @utmi_bvalid: utmi vbus bvalid status register.
|
||||
+ * @utmi_id: utmi id state register.
|
||||
* @utmi_ls: utmi linestate state register.
|
||||
* @utmi_hstdet: utmi host disconnect register.
|
||||
*/
|
||||
@@ -129,11 +133,15 @@ struct rockchip_usb2phy_port_cfg {
|
||||
struct usb2phy_reg bvalid_det_en;
|
||||
struct usb2phy_reg bvalid_det_st;
|
||||
struct usb2phy_reg bvalid_det_clr;
|
||||
+ struct usb2phy_reg id_det_en;
|
||||
+ struct usb2phy_reg id_det_st;
|
||||
+ struct usb2phy_reg id_det_clr;
|
||||
struct usb2phy_reg ls_det_en;
|
||||
struct usb2phy_reg ls_det_st;
|
||||
struct usb2phy_reg ls_det_clr;
|
||||
struct usb2phy_reg utmi_avalid;
|
||||
struct usb2phy_reg utmi_bvalid;
|
||||
+ struct usb2phy_reg utmi_id;
|
||||
struct usb2phy_reg utmi_ls;
|
||||
struct usb2phy_reg utmi_hstdet;
|
||||
};
|
||||
@@ -161,6 +169,7 @@ struct rockchip_usb2phy_cfg {
|
||||
* @suspended: phy suspended flag.
|
||||
* @vbus_attached: otg device vbus status.
|
||||
* @bvalid_irq: IRQ number assigned for vbus valid rise detection.
|
||||
+ * @id_irq: IRQ number assigned for ID pin detection.
|
||||
* @ls_irq: IRQ number assigned for linestate detection.
|
||||
* @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
|
||||
* irqs to one irq in otg-port.
|
||||
@@ -179,6 +188,7 @@ struct rockchip_usb2phy_port {
|
||||
bool suspended;
|
||||
bool vbus_attached;
|
||||
int bvalid_irq;
|
||||
+ int id_irq;
|
||||
int ls_irq;
|
||||
int otg_mux_irq;
|
||||
struct mutex mutex;
|
||||
@@ -426,6 +436,19 @@ static int rockchip_usb2phy_init(struct
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
+ /* clear id status and enable id detect irq */
|
||||
+ ret = property_enable(rphy->grf,
|
||||
+ &rport->port_cfg->id_det_clr,
|
||||
+ true);
|
||||
+ if (ret)
|
||||
+ goto out;
|
||||
+
|
||||
+ ret = property_enable(rphy->grf,
|
||||
+ &rport->port_cfg->id_det_en,
|
||||
+ true);
|
||||
+ if (ret)
|
||||
+ goto out;
|
||||
+
|
||||
schedule_delayed_work(&rport->otg_sm_work,
|
||||
OTG_SCHEDULE_DELAY * 3);
|
||||
} else {
|
||||
@@ -923,11 +946,30 @@ static irqreturn_t rockchip_usb2phy_bval
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
+static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
|
||||
+{
|
||||
+ struct rockchip_usb2phy_port *rport = data;
|
||||
+ struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
|
||||
+ bool id;
|
||||
+
|
||||
+ if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st))
|
||||
+ return IRQ_NONE;
|
||||
+
|
||||
+ /* clear id detect irq pending status */
|
||||
+ property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true);
|
||||
+
|
||||
+ id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
|
||||
+ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
|
||||
{
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
ret |= rockchip_usb2phy_bvalid_irq(irq, data);
|
||||
+ ret |= rockchip_usb2phy_id_irq(irq, data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -1025,6 +1067,25 @@ static int rockchip_usb2phy_port_irq_ini
|
||||
"failed to request otg-bvalid irq handle\n");
|
||||
return ret;
|
||||
}
|
||||
+
|
||||
+ rport->id_irq = of_irq_get_byname(child_np, "otg-id");
|
||||
+ if (rport->id_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no otg-id irq provided\n");
|
||||
+ ret = rport->id_irq;
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->id_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_id_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_id",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-id irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@@ -1299,10 +1360,14 @@ static const struct rockchip_usb2phy_cfg
|
||||
.bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
|
||||
.bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
|
||||
.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
|
||||
+ .id_det_en = { 0x0680, 6, 5, 0, 3 },
|
||||
+ .id_det_st = { 0x0690, 6, 5, 0, 3 },
|
||||
+ .id_det_clr = { 0x06a0, 6, 5, 0, 3 },
|
||||
.ls_det_en = { 0x0680, 2, 2, 0, 1 },
|
||||
.ls_det_st = { 0x0690, 2, 2, 0, 1 },
|
||||
.ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
|
||||
.utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
|
||||
+ .utmi_id = { 0x0480, 1, 1, 0, 1 },
|
||||
.utmi_ls = { 0x0480, 3, 2, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
@@ -1358,11 +1423,15 @@ static const struct rockchip_usb2phy_cfg
|
||||
.bvalid_det_en = { 0x3020, 3, 2, 0, 3 },
|
||||
.bvalid_det_st = { 0x3024, 3, 2, 0, 3 },
|
||||
.bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
|
||||
+ .id_det_en = { 0x3020, 5, 4, 0, 3 },
|
||||
+ .id_det_st = { 0x3024, 5, 4, 0, 3 },
|
||||
+ .id_det_clr = { 0x3028, 5, 4, 0, 3 },
|
||||
.ls_det_en = { 0x3020, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x3024, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x3028, 0, 0, 0, 1 },
|
||||
.utmi_avalid = { 0x0120, 10, 10, 0, 1 },
|
||||
.utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
|
||||
+ .utmi_id = { 0x0120, 6, 6, 0, 1 },
|
||||
.utmi_ls = { 0x0120, 5, 4, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
@@ -1401,11 +1470,15 @@ static const struct rockchip_usb2phy_cfg
|
||||
.bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
|
||||
.bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
|
||||
.bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
|
||||
+ .id_det_en = { 0x0110, 5, 4, 0, 3 },
|
||||
+ .id_det_st = { 0x0114, 5, 4, 0, 3 },
|
||||
+ .id_det_clr = { 0x0118, 5, 4, 0, 3 },
|
||||
.ls_det_en = { 0x0110, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x0114, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x0118, 0, 0, 0, 1 },
|
||||
.utmi_avalid = { 0x0120, 10, 10, 0, 1 },
|
||||
.utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
|
||||
+ .utmi_id = { 0x0120, 6, 6, 0, 1 },
|
||||
.utmi_ls = { 0x0120, 5, 4, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
@@ -1463,8 +1536,12 @@ static const struct rockchip_usb2phy_cfg
|
||||
.bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
|
||||
.bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
|
||||
.bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
|
||||
+ .id_det_en = { 0xe3c0, 5, 4, 0, 3 },
|
||||
+ .id_det_st = { 0xe3e0, 5, 4, 0, 3 },
|
||||
+ .id_det_clr = { 0xe3d0, 5, 4, 0, 3 },
|
||||
.utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
|
||||
.utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
|
||||
+ .utmi_id = { 0xe2ac, 8, 8, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
|
||||
@@ -1498,8 +1575,12 @@ static const struct rockchip_usb2phy_cfg
|
||||
.bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
|
||||
.bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
|
||||
.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
|
||||
+ .id_det_en = { 0xe3c0, 10, 9, 0, 3 },
|
||||
+ .id_det_st = { 0xe3e0, 10, 9, 0, 3 },
|
||||
+ .id_det_clr = { 0xe3d0, 10, 9, 0, 3 },
|
||||
.utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
|
||||
.utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
|
||||
+ .utmi_id = { 0xe2ac, 11, 11, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
|
||||
@@ -1525,8 +1606,12 @@ static const struct rockchip_usb2phy_cfg
|
||||
.bvalid_det_en = { 0x0080, 3, 2, 0, 3 },
|
||||
.bvalid_det_st = { 0x0084, 3, 2, 0, 3 },
|
||||
.bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
|
||||
+ .id_det_en = { 0x0080, 5, 4, 0, 3 },
|
||||
+ .id_det_st = { 0x0084, 5, 4, 0, 3 },
|
||||
+ .id_det_clr = { 0x0088, 5, 4, 0, 3 },
|
||||
.utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
|
||||
.utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
|
||||
+ .utmi_id = { 0x00c0, 6, 6, 0, 1 },
|
||||
},
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
/* Select suspend control from controller */
|
||||
@ -0,0 +1,66 @@
|
||||
From 6931f85c29d5a0261219cf8a73773d3165806d84 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Fri, 22 Apr 2022 09:28:18 +0200
|
||||
Subject: [PATCH] clk: rockchip: Mark hclk_vo as critical on rk3568
|
||||
|
||||
Whenever pclk_vo is enabled hclk_vo must be enabled as well. This is
|
||||
described in the Reference Manual as:
|
||||
|
||||
| 2.8.6 NIU Clock gating reliance
|
||||
|
|
||||
| A part of niu clocks have a dependence on another niu clock in order to
|
||||
| sharing the internal bus. When these clocks are in use, another niu
|
||||
| clock must be opened, and cannot be gated. These clocks and the special
|
||||
| clock on which they are relied are as following:
|
||||
|
|
||||
| Clocks which have dependency The clock which can not be gated
|
||||
| -----------------------------------------------------------------
|
||||
| ...
|
||||
| pclk_vo_niu, hclk_vo_s_niu hclk_vo_niu
|
||||
| ...
|
||||
|
||||
The clock framework doesn't offer a way to enable clock B whenever clock A is
|
||||
enabled, at least not when B is not an ancestor of A. Workaround this by
|
||||
marking hclk_vo as critical so it is never disabled. This is suboptimal in
|
||||
terms of power consumption, but a stop gap solution until the clock framework
|
||||
has a way to deal with this.
|
||||
|
||||
We have this clock tree:
|
||||
|
||||
| aclk_vo 2 2 0 300000000 0 0 50000 Y
|
||||
| aclk_hdcp 0 0 0 300000000 0 0 50000 N
|
||||
| pclk_vo 2 3 0 75000000 0 0 50000 Y
|
||||
| pclk_edp_ctrl 0 0 0 75000000 0 0 50000 N
|
||||
| pclk_dsitx_1 0 0 0 75000000 0 0 50000 N
|
||||
| pclk_dsitx_0 1 2 0 75000000 0 0 50000 Y
|
||||
| pclk_hdmi_host 1 2 0 75000000 0 0 50000 Y
|
||||
| pclk_hdcp 0 0 0 75000000 0 0 50000 N
|
||||
| hclk_vo 2 5 0 150000000 0 0 50000 Y
|
||||
| hclk_hdcp 0 0 0 150000000 0 0 50000 N
|
||||
| hclk_vop 0 2 0 150000000 0 0 50000 N
|
||||
|
||||
Without this patch the edp, dsitx, hdmi and hdcp driver would enable their
|
||||
clocks which then enables pclk_vo, but hclk_vo stays disabled and register
|
||||
accesses just hang. hclk_vo is enabled by the VOP2 driver, so reproducibility
|
||||
of this issue depends on the probe order.
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220422072841.2206452-2-s.hauer@pengutronix.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3568.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3568.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3568.c
|
||||
@@ -1591,6 +1591,7 @@ static const char *const rk3568_cru_crit
|
||||
"hclk_php",
|
||||
"pclk_php",
|
||||
"hclk_usb",
|
||||
+ "hclk_vo",
|
||||
};
|
||||
|
||||
static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
|
||||
@ -0,0 +1,203 @@
|
||||
From 421be3ee36a497949a4b564cd1e4f7f9fe755f57 Mon Sep 17 00:00:00 2001
|
||||
From: Robin Murphy <robin.murphy@arm.com>
|
||||
Date: Tue, 5 Apr 2022 15:32:50 +0100
|
||||
Subject: [PATCH] drm/rockchip: Refactor IOMMU initialisation
|
||||
|
||||
Defer the IOMMU domain setup until after successfully binding
|
||||
components, so we can figure out IOMMU support directly from the VOP
|
||||
devices themselves, rather than manually inferring it from the DT (which
|
||||
also fails to account for whether the IOMMU driver is actually loaded).
|
||||
Although this is somewhat of a logical cleanup, the main motivation is
|
||||
to prepare for a change in the iommu_domain_alloc() interface.
|
||||
|
||||
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/94eee7ab434fe11eb0787f691e9f1ab03a2e91be.1649168685.git.robin.murphy@arm.com
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 60 +++++++++------------
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 3 ++
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +
|
||||
3 files changed, 31 insertions(+), 34 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
@@ -7,7 +7,6 @@
|
||||
*/
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
-#include <linux/dma-iommu.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_graph.h>
|
||||
@@ -35,7 +34,6 @@
|
||||
#define DRIVER_MAJOR 1
|
||||
#define DRIVER_MINOR 0
|
||||
|
||||
-static bool is_support_iommu = true;
|
||||
static const struct drm_driver rockchip_drm_driver;
|
||||
|
||||
/*
|
||||
@@ -49,7 +47,7 @@ int rockchip_drm_dma_attach_device(struc
|
||||
struct rockchip_drm_private *private = drm_dev->dev_private;
|
||||
int ret;
|
||||
|
||||
- if (!is_support_iommu)
|
||||
+ if (!private->domain)
|
||||
return 0;
|
||||
|
||||
ret = iommu_attach_device(private->domain, dev);
|
||||
@@ -65,12 +63,22 @@ void rockchip_drm_dma_detach_device(stru
|
||||
struct device *dev)
|
||||
{
|
||||
struct rockchip_drm_private *private = drm_dev->dev_private;
|
||||
- struct iommu_domain *domain = private->domain;
|
||||
|
||||
- if (!is_support_iommu)
|
||||
+ if (!private->domain)
|
||||
return;
|
||||
|
||||
- iommu_detach_device(domain, dev);
|
||||
+ iommu_detach_device(private->domain, dev);
|
||||
+}
|
||||
+
|
||||
+void rockchip_drm_dma_init_device(struct drm_device *drm_dev,
|
||||
+ struct device *dev)
|
||||
+{
|
||||
+ struct rockchip_drm_private *private = drm_dev->dev_private;
|
||||
+
|
||||
+ if (!device_iommu_mapped(dev))
|
||||
+ private->iommu_dev = ERR_PTR(-ENODEV);
|
||||
+ else if (!private->iommu_dev)
|
||||
+ private->iommu_dev = dev;
|
||||
}
|
||||
|
||||
static int rockchip_drm_init_iommu(struct drm_device *drm_dev)
|
||||
@@ -79,10 +87,10 @@ static int rockchip_drm_init_iommu(struc
|
||||
struct iommu_domain_geometry *geometry;
|
||||
u64 start, end;
|
||||
|
||||
- if (!is_support_iommu)
|
||||
+ if (IS_ERR_OR_NULL(private->iommu_dev))
|
||||
return 0;
|
||||
|
||||
- private->domain = iommu_domain_alloc(&platform_bus_type);
|
||||
+ private->domain = iommu_domain_alloc(private->iommu_dev->bus);
|
||||
if (!private->domain)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -102,7 +110,7 @@ static void rockchip_iommu_cleanup(struc
|
||||
{
|
||||
struct rockchip_drm_private *private = drm_dev->dev_private;
|
||||
|
||||
- if (!is_support_iommu)
|
||||
+ if (!private->domain)
|
||||
return;
|
||||
|
||||
drm_mm_takedown(&private->mm);
|
||||
@@ -141,25 +149,25 @@ static int rockchip_drm_bind(struct devi
|
||||
INIT_LIST_HEAD(&private->psr_list);
|
||||
mutex_init(&private->psr_list_lock);
|
||||
|
||||
- ret = rockchip_drm_init_iommu(drm_dev);
|
||||
- if (ret)
|
||||
- goto err_free;
|
||||
-
|
||||
ret = drmm_mode_config_init(drm_dev);
|
||||
if (ret)
|
||||
- goto err_iommu_cleanup;
|
||||
+ goto err_free;
|
||||
|
||||
rockchip_drm_mode_config_init(drm_dev);
|
||||
|
||||
/* Try to bind all sub drivers. */
|
||||
ret = component_bind_all(dev, drm_dev);
|
||||
if (ret)
|
||||
- goto err_iommu_cleanup;
|
||||
+ goto err_free;
|
||||
|
||||
- ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc);
|
||||
+ ret = rockchip_drm_init_iommu(drm_dev);
|
||||
if (ret)
|
||||
goto err_unbind_all;
|
||||
|
||||
+ ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc);
|
||||
+ if (ret)
|
||||
+ goto err_iommu_cleanup;
|
||||
+
|
||||
drm_mode_config_reset(drm_dev);
|
||||
|
||||
ret = rockchip_drm_fbdev_init(drm_dev);
|
||||
@@ -177,10 +185,10 @@ static int rockchip_drm_bind(struct devi
|
||||
err_kms_helper_poll_fini:
|
||||
drm_kms_helper_poll_fini(drm_dev);
|
||||
rockchip_drm_fbdev_fini(drm_dev);
|
||||
-err_unbind_all:
|
||||
- component_unbind_all(dev, drm_dev);
|
||||
err_iommu_cleanup:
|
||||
rockchip_iommu_cleanup(drm_dev);
|
||||
+err_unbind_all:
|
||||
+ component_unbind_all(dev, drm_dev);
|
||||
err_free:
|
||||
drm_dev_put(drm_dev);
|
||||
return ret;
|
||||
@@ -358,8 +366,6 @@ static int rockchip_drm_platform_of_prob
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0;; i++) {
|
||||
- struct device_node *iommu;
|
||||
-
|
||||
port = of_parse_phandle(np, "ports", i);
|
||||
if (!port)
|
||||
break;
|
||||
@@ -369,21 +375,7 @@ static int rockchip_drm_platform_of_prob
|
||||
continue;
|
||||
}
|
||||
|
||||
- iommu = of_parse_phandle(port->parent, "iommus", 0);
|
||||
- if (!iommu || !of_device_is_available(iommu->parent)) {
|
||||
- DRM_DEV_DEBUG(dev,
|
||||
- "no iommu attached for %pOF, using non-iommu buffers\n",
|
||||
- port->parent);
|
||||
- /*
|
||||
- * if there is a crtc not support iommu, force set all
|
||||
- * crtc use non-iommu buffer.
|
||||
- */
|
||||
- is_support_iommu = false;
|
||||
- }
|
||||
-
|
||||
found = true;
|
||||
-
|
||||
- of_node_put(iommu);
|
||||
of_node_put(port);
|
||||
}
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
@@ -46,6 +46,7 @@ struct rockchip_drm_private {
|
||||
struct drm_fb_helper fbdev_helper;
|
||||
struct drm_gem_object *fbdev_bo;
|
||||
struct iommu_domain *domain;
|
||||
+ struct device *iommu_dev;
|
||||
struct mutex mm_lock;
|
||||
struct drm_mm mm;
|
||||
struct list_head psr_list;
|
||||
@@ -56,6 +57,8 @@ int rockchip_drm_dma_attach_device(struc
|
||||
struct device *dev);
|
||||
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
|
||||
struct device *dev);
|
||||
+void rockchip_drm_dma_init_device(struct drm_device *drm_dev,
|
||||
+ struct device *dev);
|
||||
int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
|
||||
|
||||
int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
@@ -2176,6 +2176,8 @@ static int vop_bind(struct device *dev,
|
||||
}
|
||||
}
|
||||
|
||||
+ rockchip_drm_dma_init_device(drm_dev, dev);
|
||||
+
|
||||
return 0;
|
||||
|
||||
err_disable_pm_runtime:
|
||||
@ -0,0 +1,601 @@
|
||||
From 540b8f271e53362a308f6bf288d38b630cf3fbd2 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Fri, 22 Apr 2022 09:28:19 +0200
|
||||
Subject: [PATCH] drm/rockchip: Embed drm_encoder into rockchip_decoder
|
||||
|
||||
The VOP2 driver needs rockchip specific information for a drm_encoder.
|
||||
|
||||
This patch creates a struct rockchip_encoder with a struct drm_encoder
|
||||
embedded in it. This is used throughout the rockchip driver instead of
|
||||
struct drm_encoder directly.
|
||||
|
||||
The information the VOP2 drivers needs is the of_graph endpoint node
|
||||
of the encoder. To ease bisectability this is added here.
|
||||
|
||||
While at it convert the different encoder-to-driverdata macros to
|
||||
static inline functions in order to gain type safety and readability.
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-3-s.hauer@pengutronix.de
|
||||
---
|
||||
.../gpu/drm/rockchip/analogix_dp-rockchip.c | 32 +++++++++++------
|
||||
drivers/gpu/drm/rockchip/cdn-dp-core.c | 18 ++++++----
|
||||
drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +-
|
||||
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 17 ++++++----
|
||||
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 11 ++++--
|
||||
drivers/gpu/drm/rockchip/inno_hdmi.c | 32 +++++++++++------
|
||||
drivers/gpu/drm/rockchip/rk3066_hdmi.c | 34 ++++++++++++-------
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 10 ++++++
|
||||
drivers/gpu/drm/rockchip/rockchip_lvds.c | 26 ++++++++------
|
||||
9 files changed, 122 insertions(+), 60 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
|
||||
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
|
||||
@@ -40,8 +40,6 @@
|
||||
|
||||
#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
|
||||
|
||||
-#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
|
||||
-
|
||||
/**
|
||||
* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
|
||||
* @lcdsel_grf_reg: grf register offset of lcdc select
|
||||
@@ -59,7 +57,7 @@ struct rockchip_dp_chip_data {
|
||||
struct rockchip_dp_device {
|
||||
struct drm_device *drm_dev;
|
||||
struct device *dev;
|
||||
- struct drm_encoder encoder;
|
||||
+ struct rockchip_encoder encoder;
|
||||
struct drm_display_mode mode;
|
||||
|
||||
struct clk *pclk;
|
||||
@@ -73,6 +71,18 @@ struct rockchip_dp_device {
|
||||
struct analogix_dp_plat_data plat_data;
|
||||
};
|
||||
|
||||
+static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
|
||||
+
|
||||
+ return container_of(rkencoder, struct rockchip_dp_device, encoder);
|
||||
+}
|
||||
+
|
||||
+static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
|
||||
+{
|
||||
+ return container_of(plat_data, struct rockchip_dp_device, plat_data);
|
||||
+}
|
||||
+
|
||||
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
|
||||
{
|
||||
reset_control_assert(dp->rst);
|
||||
@@ -84,7 +94,7 @@ static int rockchip_dp_pre_init(struct r
|
||||
|
||||
static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
|
||||
{
|
||||
- struct rockchip_dp_device *dp = to_dp(plat_data);
|
||||
+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(dp->pclk);
|
||||
@@ -105,7 +115,7 @@ static int rockchip_dp_poweron_start(str
|
||||
|
||||
static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
|
||||
{
|
||||
- struct rockchip_dp_device *dp = to_dp(plat_data);
|
||||
+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
|
||||
|
||||
clk_disable_unprepare(dp->pclk);
|
||||
|
||||
@@ -166,7 +176,7 @@ struct drm_crtc *rockchip_dp_drm_get_new
|
||||
static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
|
||||
struct drm_atomic_state *state)
|
||||
{
|
||||
- struct rockchip_dp_device *dp = to_dp(encoder);
|
||||
+ struct rockchip_dp_device *dp = encoder_to_dp(encoder);
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_crtc_state *old_crtc_state;
|
||||
int ret;
|
||||
@@ -208,7 +218,7 @@ static void rockchip_dp_drm_encoder_enab
|
||||
static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
|
||||
struct drm_atomic_state *state)
|
||||
{
|
||||
- struct rockchip_dp_device *dp = to_dp(encoder);
|
||||
+ struct rockchip_dp_device *dp = encoder_to_dp(encoder);
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_crtc_state *new_crtc_state = NULL;
|
||||
int ret;
|
||||
@@ -297,7 +307,7 @@ static int rockchip_dp_of_probe(struct r
|
||||
|
||||
static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
|
||||
{
|
||||
- struct drm_encoder *encoder = &dp->encoder;
|
||||
+ struct drm_encoder *encoder = &dp->encoder.encoder;
|
||||
struct drm_device *drm_dev = dp->drm_dev;
|
||||
struct device *dev = dp->dev;
|
||||
int ret;
|
||||
@@ -333,7 +343,7 @@ static int rockchip_dp_bind(struct devic
|
||||
return ret;
|
||||
}
|
||||
|
||||
- dp->plat_data.encoder = &dp->encoder;
|
||||
+ dp->plat_data.encoder = &dp->encoder.encoder;
|
||||
|
||||
ret = analogix_dp_bind(dp->adp, drm_dev);
|
||||
if (ret)
|
||||
@@ -341,7 +351,7 @@ static int rockchip_dp_bind(struct devic
|
||||
|
||||
return 0;
|
||||
err_cleanup_encoder:
|
||||
- dp->encoder.funcs->destroy(&dp->encoder);
|
||||
+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -351,7 +361,7 @@ static void rockchip_dp_unbind(struct de
|
||||
struct rockchip_dp_device *dp = dev_get_drvdata(dev);
|
||||
|
||||
analogix_dp_unbind(dp->adp);
|
||||
- dp->encoder.funcs->destroy(&dp->encoder);
|
||||
+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
|
||||
}
|
||||
|
||||
static const struct component_ops rockchip_dp_component_ops = {
|
||||
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
@@ -26,11 +26,17 @@
|
||||
#include "cdn-dp-reg.h"
|
||||
#include "rockchip_drm_vop.h"
|
||||
|
||||
-#define connector_to_dp(c) \
|
||||
- container_of(c, struct cdn_dp_device, connector)
|
||||
+static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector)
|
||||
+{
|
||||
+ return container_of(connector, struct cdn_dp_device, connector);
|
||||
+}
|
||||
|
||||
-#define encoder_to_dp(c) \
|
||||
- container_of(c, struct cdn_dp_device, encoder)
|
||||
+static inline struct cdn_dp_device *encoder_to_dp(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
|
||||
+
|
||||
+ return container_of(rkencoder, struct cdn_dp_device, encoder);
|
||||
+}
|
||||
|
||||
#define GRF_SOC_CON9 0x6224
|
||||
#define DP_SEL_VOP_LIT BIT(12)
|
||||
@@ -1025,7 +1031,7 @@ static int cdn_dp_bind(struct device *de
|
||||
|
||||
INIT_WORK(&dp->event_work, cdn_dp_pd_event_work);
|
||||
|
||||
- encoder = &dp->encoder;
|
||||
+ encoder = &dp->encoder.encoder;
|
||||
|
||||
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
|
||||
dev->of_node);
|
||||
@@ -1090,7 +1096,7 @@ err_free_encoder:
|
||||
static void cdn_dp_unbind(struct device *dev, struct device *master, void *data)
|
||||
{
|
||||
struct cdn_dp_device *dp = dev_get_drvdata(dev);
|
||||
- struct drm_encoder *encoder = &dp->encoder;
|
||||
+ struct drm_encoder *encoder = &dp->encoder.encoder;
|
||||
struct drm_connector *connector = &dp->connector;
|
||||
|
||||
cancel_work_sync(&dp->event_work);
|
||||
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.h
|
||||
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h
|
||||
@@ -65,7 +65,7 @@ struct cdn_dp_device {
|
||||
struct device *dev;
|
||||
struct drm_device *drm_dev;
|
||||
struct drm_connector connector;
|
||||
- struct drm_encoder encoder;
|
||||
+ struct rockchip_encoder encoder;
|
||||
struct drm_display_mode mode;
|
||||
struct platform_device *audio_pdev;
|
||||
struct work_struct event_work;
|
||||
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
|
||||
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
|
||||
@@ -182,8 +182,6 @@
|
||||
|
||||
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
|
||||
|
||||
-#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
|
||||
-
|
||||
enum {
|
||||
DW_DSI_USAGE_IDLE,
|
||||
DW_DSI_USAGE_DSI,
|
||||
@@ -237,7 +235,7 @@ struct rockchip_dw_dsi_chip_data {
|
||||
|
||||
struct dw_mipi_dsi_rockchip {
|
||||
struct device *dev;
|
||||
- struct drm_encoder encoder;
|
||||
+ struct rockchip_encoder encoder;
|
||||
void __iomem *base;
|
||||
|
||||
struct regmap *grf_regmap;
|
||||
@@ -272,6 +270,13 @@ struct dw_mipi_dsi_rockchip {
|
||||
bool dsi_bound;
|
||||
};
|
||||
|
||||
+static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
|
||||
+
|
||||
+ return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder);
|
||||
+}
|
||||
+
|
||||
struct dphy_pll_parameter_map {
|
||||
unsigned int max_mbps;
|
||||
u8 hsfreqrange;
|
||||
@@ -771,7 +776,7 @@ static void dw_mipi_dsi_encoder_enable(s
|
||||
int ret, mux;
|
||||
|
||||
mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
|
||||
- &dsi->encoder);
|
||||
+ &dsi->encoder.encoder);
|
||||
if (mux < 0)
|
||||
return;
|
||||
|
||||
@@ -802,7 +807,7 @@ dw_mipi_dsi_encoder_helper_funcs = {
|
||||
static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
|
||||
struct drm_device *drm_dev)
|
||||
{
|
||||
- struct drm_encoder *encoder = &dsi->encoder;
|
||||
+ struct drm_encoder *encoder = &dsi->encoder.encoder;
|
||||
int ret;
|
||||
|
||||
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
|
||||
@@ -960,7 +965,7 @@ static int dw_mipi_dsi_rockchip_bind(str
|
||||
goto out_pll_clk;
|
||||
}
|
||||
|
||||
- ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
|
||||
+ ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
|
||||
goto out_pll_clk;
|
||||
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
@@ -67,7 +67,7 @@ struct rockchip_hdmi_chip_data {
|
||||
struct rockchip_hdmi {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
- struct drm_encoder encoder;
|
||||
+ struct rockchip_encoder encoder;
|
||||
const struct rockchip_hdmi_chip_data *chip_data;
|
||||
struct clk *vpll_clk;
|
||||
struct clk *grf_clk;
|
||||
@@ -75,7 +75,12 @@ struct rockchip_hdmi {
|
||||
struct phy *phy;
|
||||
};
|
||||
|
||||
-#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
|
||||
+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
|
||||
+
|
||||
+ return container_of(rkencoder, struct rockchip_hdmi, encoder);
|
||||
+}
|
||||
|
||||
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
|
||||
{
|
||||
@@ -511,7 +516,7 @@ static int dw_hdmi_rockchip_bind(struct
|
||||
hdmi->dev = &pdev->dev;
|
||||
hdmi->chip_data = plat_data->phy_data;
|
||||
plat_data->phy_data = hdmi;
|
||||
- encoder = &hdmi->encoder;
|
||||
+ encoder = &hdmi->encoder.encoder;
|
||||
|
||||
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
|
||||
/*
|
||||
--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
|
||||
+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c
|
||||
@@ -26,8 +26,6 @@
|
||||
|
||||
#include "inno_hdmi.h"
|
||||
|
||||
-#define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x)
|
||||
-
|
||||
struct hdmi_data_info {
|
||||
int vic;
|
||||
bool sink_is_hdmi;
|
||||
@@ -56,7 +54,7 @@ struct inno_hdmi {
|
||||
void __iomem *regs;
|
||||
|
||||
struct drm_connector connector;
|
||||
- struct drm_encoder encoder;
|
||||
+ struct rockchip_encoder encoder;
|
||||
|
||||
struct inno_hdmi_i2c *i2c;
|
||||
struct i2c_adapter *ddc;
|
||||
@@ -67,6 +65,18 @@ struct inno_hdmi {
|
||||
struct drm_display_mode previous_mode;
|
||||
};
|
||||
|
||||
+static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
|
||||
+
|
||||
+ return container_of(rkencoder, struct inno_hdmi, encoder);
|
||||
+}
|
||||
+
|
||||
+static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
|
||||
+{
|
||||
+ return container_of(connector, struct inno_hdmi, connector);
|
||||
+}
|
||||
+
|
||||
enum {
|
||||
CSC_ITU601_16_235_TO_RGB_0_255_8BIT,
|
||||
CSC_ITU601_0_255_TO_RGB_0_255_8BIT,
|
||||
@@ -483,7 +493,7 @@ static void inno_hdmi_encoder_mode_set(s
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adj_mode)
|
||||
{
|
||||
- struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
|
||||
+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
|
||||
|
||||
inno_hdmi_setup(hdmi, adj_mode);
|
||||
|
||||
@@ -493,14 +503,14 @@ static void inno_hdmi_encoder_mode_set(s
|
||||
|
||||
static void inno_hdmi_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
- struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
|
||||
+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
|
||||
|
||||
inno_hdmi_set_pwr_mode(hdmi, NORMAL);
|
||||
}
|
||||
|
||||
static void inno_hdmi_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
- struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
|
||||
+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
|
||||
|
||||
inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
|
||||
}
|
||||
@@ -536,7 +546,7 @@ static struct drm_encoder_helper_funcs i
|
||||
static enum drm_connector_status
|
||||
inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
|
||||
{
|
||||
- struct inno_hdmi *hdmi = to_inno_hdmi(connector);
|
||||
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
|
||||
|
||||
return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
|
||||
connector_status_connected : connector_status_disconnected;
|
||||
@@ -544,7 +554,7 @@ inno_hdmi_connector_detect(struct drm_co
|
||||
|
||||
static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
- struct inno_hdmi *hdmi = to_inno_hdmi(connector);
|
||||
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
|
||||
struct edid *edid;
|
||||
int ret = 0;
|
||||
|
||||
@@ -599,7 +609,7 @@ static struct drm_connector_helper_funcs
|
||||
|
||||
static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
|
||||
{
|
||||
- struct drm_encoder *encoder = &hdmi->encoder;
|
||||
+ struct drm_encoder *encoder = &hdmi->encoder.encoder;
|
||||
struct device *dev = hdmi->dev;
|
||||
|
||||
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
|
||||
@@ -881,7 +891,7 @@ static int inno_hdmi_bind(struct device
|
||||
return 0;
|
||||
err_cleanup_hdmi:
|
||||
hdmi->connector.funcs->destroy(&hdmi->connector);
|
||||
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
|
||||
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
|
||||
err_put_adapter:
|
||||
i2c_put_adapter(hdmi->ddc);
|
||||
err_disable_clk:
|
||||
@@ -895,7 +905,7 @@ static void inno_hdmi_unbind(struct devi
|
||||
struct inno_hdmi *hdmi = dev_get_drvdata(dev);
|
||||
|
||||
hdmi->connector.funcs->destroy(&hdmi->connector);
|
||||
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
|
||||
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
|
||||
|
||||
i2c_put_adapter(hdmi->ddc);
|
||||
clk_disable_unprepare(hdmi->pclk);
|
||||
--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
|
||||
@@ -47,7 +47,7 @@ struct rk3066_hdmi {
|
||||
void __iomem *regs;
|
||||
|
||||
struct drm_connector connector;
|
||||
- struct drm_encoder encoder;
|
||||
+ struct rockchip_encoder encoder;
|
||||
|
||||
struct rk3066_hdmi_i2c *i2c;
|
||||
struct i2c_adapter *ddc;
|
||||
@@ -58,7 +58,17 @@ struct rk3066_hdmi {
|
||||
struct drm_display_mode previous_mode;
|
||||
};
|
||||
|
||||
-#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
|
||||
+static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
|
||||
+
|
||||
+ return container_of(rkencoder, struct rk3066_hdmi, encoder);
|
||||
+}
|
||||
+
|
||||
+static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector)
|
||||
+{
|
||||
+ return container_of(connector, struct rk3066_hdmi, connector);
|
||||
+}
|
||||
|
||||
static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
|
||||
{
|
||||
@@ -380,7 +390,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adj_mode)
|
||||
{
|
||||
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
|
||||
+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
|
||||
|
||||
/* Store the display mode for plugin/DPMS poweron events. */
|
||||
drm_mode_copy(&hdmi->previous_mode, adj_mode);
|
||||
@@ -388,7 +398,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_
|
||||
|
||||
static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
|
||||
+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
|
||||
int mux, val;
|
||||
|
||||
mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
|
||||
@@ -407,7 +417,7 @@ static void rk3066_hdmi_encoder_enable(s
|
||||
|
||||
static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
|
||||
+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
|
||||
|
||||
DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
|
||||
|
||||
@@ -455,7 +465,7 @@ struct drm_encoder_helper_funcs rk3066_h
|
||||
static enum drm_connector_status
|
||||
rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
|
||||
{
|
||||
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
|
||||
+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
|
||||
|
||||
return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
|
||||
connector_status_connected : connector_status_disconnected;
|
||||
@@ -463,7 +473,7 @@ rk3066_hdmi_connector_detect(struct drm_
|
||||
|
||||
static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
|
||||
+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
|
||||
struct edid *edid;
|
||||
int ret = 0;
|
||||
|
||||
@@ -496,9 +506,9 @@ rk3066_hdmi_connector_mode_valid(struct
|
||||
static struct drm_encoder *
|
||||
rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
|
||||
{
|
||||
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
|
||||
+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
|
||||
|
||||
- return &hdmi->encoder;
|
||||
+ return &hdmi->encoder.encoder;
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -538,7 +548,7 @@ struct drm_connector_helper_funcs rk3066
|
||||
static int
|
||||
rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
|
||||
{
|
||||
- struct drm_encoder *encoder = &hdmi->encoder;
|
||||
+ struct drm_encoder *encoder = &hdmi->encoder.encoder;
|
||||
struct device *dev = hdmi->dev;
|
||||
|
||||
encoder->possible_crtcs =
|
||||
@@ -816,7 +826,7 @@ static int rk3066_hdmi_bind(struct devic
|
||||
|
||||
err_cleanup_hdmi:
|
||||
hdmi->connector.funcs->destroy(&hdmi->connector);
|
||||
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
|
||||
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
|
||||
err_disable_i2c:
|
||||
i2c_put_adapter(hdmi->ddc);
|
||||
err_disable_hclk:
|
||||
@@ -831,7 +841,7 @@ static void rk3066_hdmi_unbind(struct de
|
||||
struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
|
||||
|
||||
hdmi->connector.funcs->destroy(&hdmi->connector);
|
||||
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
|
||||
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
|
||||
|
||||
i2c_put_adapter(hdmi->ddc);
|
||||
clk_disable_unprepare(hdmi->hclk);
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
@@ -53,6 +53,10 @@ struct rockchip_drm_private {
|
||||
struct mutex psr_list_lock;
|
||||
};
|
||||
|
||||
+struct rockchip_encoder {
|
||||
+ struct drm_encoder encoder;
|
||||
+};
|
||||
+
|
||||
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
|
||||
struct device *dev);
|
||||
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
|
||||
@@ -70,4 +74,10 @@ extern struct platform_driver rockchip_d
|
||||
extern struct platform_driver rockchip_lvds_driver;
|
||||
extern struct platform_driver vop_platform_driver;
|
||||
extern struct platform_driver rk3066_hdmi_driver;
|
||||
+
|
||||
+static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ return container_of(encoder, struct rockchip_encoder, encoder);
|
||||
+}
|
||||
+
|
||||
#endif /* _ROCKCHIP_DRM_DRV_H_ */
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
@@ -35,12 +35,6 @@
|
||||
|
||||
struct rockchip_lvds;
|
||||
|
||||
-#define connector_to_lvds(c) \
|
||||
- container_of(c, struct rockchip_lvds, connector)
|
||||
-
|
||||
-#define encoder_to_lvds(c) \
|
||||
- container_of(c, struct rockchip_lvds, encoder)
|
||||
-
|
||||
/**
|
||||
* struct rockchip_lvds_soc_data - rockchip lvds Soc private data
|
||||
* @probe: LVDS platform probe function
|
||||
@@ -64,10 +58,22 @@ struct rockchip_lvds {
|
||||
struct drm_panel *panel;
|
||||
struct drm_bridge *bridge;
|
||||
struct drm_connector connector;
|
||||
- struct drm_encoder encoder;
|
||||
+ struct rockchip_encoder encoder;
|
||||
struct dev_pin_info *pins;
|
||||
};
|
||||
|
||||
+static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *connector)
|
||||
+{
|
||||
+ return container_of(connector, struct rockchip_lvds, connector);
|
||||
+}
|
||||
+
|
||||
+static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *encoder)
|
||||
+{
|
||||
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
|
||||
+
|
||||
+ return container_of(rkencoder, struct rockchip_lvds, encoder);
|
||||
+}
|
||||
+
|
||||
static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset,
|
||||
u32 val)
|
||||
{
|
||||
@@ -604,7 +610,7 @@ static int rockchip_lvds_bind(struct dev
|
||||
goto err_put_remote;
|
||||
}
|
||||
|
||||
- encoder = &lvds->encoder;
|
||||
+ encoder = &lvds->encoder.encoder;
|
||||
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
|
||||
dev->of_node);
|
||||
|
||||
@@ -669,10 +675,10 @@ static void rockchip_lvds_unbind(struct
|
||||
const struct drm_encoder_helper_funcs *encoder_funcs;
|
||||
|
||||
encoder_funcs = lvds->soc_data->helper_funcs;
|
||||
- encoder_funcs->disable(&lvds->encoder);
|
||||
+ encoder_funcs->disable(&lvds->encoder.encoder);
|
||||
pm_runtime_disable(dev);
|
||||
drm_connector_cleanup(&lvds->connector);
|
||||
- drm_encoder_cleanup(&lvds->encoder);
|
||||
+ drm_encoder_cleanup(&lvds->encoder.encoder);
|
||||
}
|
||||
|
||||
static const struct component_ops rockchip_lvds_component_ops = {
|
||||
@ -0,0 +1,88 @@
|
||||
From cf544c6a885c52d79e4d8bf139fb8cb63a878512 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Fri, 22 Apr 2022 09:28:20 +0200
|
||||
Subject: [PATCH] drm/rockchip: Add crtc_endpoint_id to rockchip_encoder
|
||||
|
||||
The VOP2 has an interface mux which decides to which encoder(s) a CRTC
|
||||
is routed to. The encoders and CRTCs are connected via of_graphs in the
|
||||
device tree. When given an encoder the VOP2 driver needs to know to
|
||||
which internal register setting this encoder matches. For this the VOP2
|
||||
binding offers different endpoints, one for each possible encoder. The
|
||||
endpoint ids of these endpoints are used as a key from an encoders
|
||||
device tree description to the internal register setting.
|
||||
|
||||
This patch adds the key aka endpoint id to struct rockchip_encoder plus
|
||||
a function to read the endpoint id starting from the encoders device
|
||||
node.
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-4-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 33 +++++++++++++++++++++
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 4 ++-
|
||||
2 files changed, 36 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
@@ -263,6 +263,39 @@ static struct platform_driver *rockchip_
|
||||
static int num_rockchip_sub_drivers;
|
||||
|
||||
/*
|
||||
+ * Get the endpoint id of the remote endpoint of the given encoder. This
|
||||
+ * information is used by the VOP2 driver to identify the encoder.
|
||||
+ *
|
||||
+ * @rkencoder: The encoder to get the remote endpoint id from
|
||||
+ * @np: The encoder device node
|
||||
+ * @port: The number of the port leading to the VOP2
|
||||
+ * @reg: The endpoint number leading to the VOP2
|
||||
+ */
|
||||
+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rkencoder,
|
||||
+ struct device_node *np, int port, int reg)
|
||||
+{
|
||||
+ struct of_endpoint ep;
|
||||
+ struct device_node *en, *ren;
|
||||
+ int ret;
|
||||
+
|
||||
+ en = of_graph_get_endpoint_by_regs(np, port, reg);
|
||||
+ if (!en)
|
||||
+ return -ENOENT;
|
||||
+
|
||||
+ ren = of_graph_get_remote_endpoint(en);
|
||||
+ if (!ren)
|
||||
+ return -ENOENT;
|
||||
+
|
||||
+ ret = of_graph_parse_endpoint(ren, &ep);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ rkencoder->crtc_endpoint_id = ep.id;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
* Check if a vop endpoint is leading to a rockchip subdriver or bridge.
|
||||
* Should be called from the component bind stage of the drivers
|
||||
* to ensure that all subdrivers are probed.
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
@@ -54,6 +54,7 @@ struct rockchip_drm_private {
|
||||
};
|
||||
|
||||
struct rockchip_encoder {
|
||||
+ int crtc_endpoint_id;
|
||||
struct drm_encoder encoder;
|
||||
};
|
||||
|
||||
@@ -64,7 +65,8 @@ void rockchip_drm_dma_detach_device(stru
|
||||
void rockchip_drm_dma_init_device(struct drm_device *drm_dev,
|
||||
struct device *dev);
|
||||
int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
|
||||
-
|
||||
+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder,
|
||||
+ struct device_node *np, int port, int reg);
|
||||
int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
|
||||
extern struct platform_driver cdn_dp_driver;
|
||||
extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
|
||||
@ -0,0 +1,93 @@
|
||||
From a9d37e684492ab5db1cce28b655e20c01191873f Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Fri, 22 Apr 2022 09:28:21 +0200
|
||||
Subject: [PATCH] drm/rockchip: dw_hdmi: rename vpll clock to reference clock
|
||||
|
||||
"vpll" is a misnomer. A clock input to a device should be named after
|
||||
the usage in the device, not after the clock that drives it. On the
|
||||
rk3568 the same clock is driven by the HPLL.
|
||||
To fix that, this patch renames the vpll clock to ref clock. The clock
|
||||
name "vpll" is left for compatibility to old device trees.
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-5-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 27 +++++++++++----------
|
||||
1 file changed, 14 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
@@ -69,7 +69,7 @@ struct rockchip_hdmi {
|
||||
struct regmap *regmap;
|
||||
struct rockchip_encoder encoder;
|
||||
const struct rockchip_hdmi_chip_data *chip_data;
|
||||
- struct clk *vpll_clk;
|
||||
+ struct clk *ref_clk;
|
||||
struct clk *grf_clk;
|
||||
struct dw_hdmi *hdmi;
|
||||
struct phy *phy;
|
||||
@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct
|
||||
return PTR_ERR(hdmi->regmap);
|
||||
}
|
||||
|
||||
- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
|
||||
- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
|
||||
- hdmi->vpll_clk = NULL;
|
||||
- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
|
||||
+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref");
|
||||
+ if (!hdmi->ref_clk)
|
||||
+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll");
|
||||
+
|
||||
+ if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
|
||||
return -EPROBE_DEFER;
|
||||
- } else if (IS_ERR(hdmi->vpll_clk)) {
|
||||
- DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n");
|
||||
- return PTR_ERR(hdmi->vpll_clk);
|
||||
+ } else if (IS_ERR(hdmi->ref_clk)) {
|
||||
+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
|
||||
+ return PTR_ERR(hdmi->ref_clk);
|
||||
}
|
||||
|
||||
hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
|
||||
@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mod
|
||||
{
|
||||
struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
|
||||
|
||||
- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
|
||||
+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
|
||||
}
|
||||
|
||||
static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
|
||||
@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
- ret = clk_prepare_enable(hdmi->vpll_clk);
|
||||
+ ret = clk_prepare_enable(hdmi->ref_clk);
|
||||
if (ret) {
|
||||
- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
|
||||
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct
|
||||
if (IS_ERR(hdmi->hdmi)) {
|
||||
ret = PTR_ERR(hdmi->hdmi);
|
||||
drm_encoder_cleanup(encoder);
|
||||
- clk_disable_unprepare(hdmi->vpll_clk);
|
||||
+ clk_disable_unprepare(hdmi->ref_clk);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(stru
|
||||
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
|
||||
|
||||
dw_hdmi_unbind(hdmi->hdmi);
|
||||
- clk_disable_unprepare(hdmi->vpll_clk);
|
||||
+ clk_disable_unprepare(hdmi->ref_clk);
|
||||
}
|
||||
|
||||
static const struct component_ops dw_hdmi_rockchip_ops = {
|
||||
@ -0,0 +1,84 @@
|
||||
From 28bbb5ffbe32741e65d798070986d212cc11e1bb Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Fri, 22 Apr 2022 09:28:24 +0200
|
||||
Subject: [PATCH] drm/rockchip: dw_hdmi: add rk3568 support
|
||||
|
||||
Add a new dw_hdmi_plat_data struct and new compatible for rk3568.
|
||||
|
||||
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-8-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 31 +++++++++++++++++++++
|
||||
1 file changed, 31 insertions(+)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
@@ -50,6 +50,10 @@
|
||||
#define RK3399_GRF_SOC_CON20 0x6250
|
||||
#define RK3399_HDMI_LCDC_SEL BIT(6)
|
||||
|
||||
+#define RK3568_GRF_VO_CON1 0x0364
|
||||
+#define RK3568_HDMI_SDAIN_MSK BIT(15)
|
||||
+#define RK3568_HDMI_SCLIN_MSK BIT(14)
|
||||
+
|
||||
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
|
||||
|
||||
/**
|
||||
@@ -473,6 +477,19 @@ static const struct dw_hdmi_plat_data rk
|
||||
.use_drm_infoframe = true,
|
||||
};
|
||||
|
||||
+static struct rockchip_hdmi_chip_data rk3568_chip_data = {
|
||||
+ .lcdsel_grf_reg = -1,
|
||||
+};
|
||||
+
|
||||
+static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
|
||||
+ .mode_valid = dw_hdmi_rockchip_mode_valid,
|
||||
+ .mpll_cfg = rockchip_mpll_cfg,
|
||||
+ .cur_ctr = rockchip_cur_ctr,
|
||||
+ .phy_config = rockchip_phy_config,
|
||||
+ .phy_data = &rk3568_chip_data,
|
||||
+ .use_drm_infoframe = true,
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
|
||||
{ .compatible = "rockchip,rk3228-dw-hdmi",
|
||||
.data = &rk3228_hdmi_drv_data
|
||||
@@ -486,6 +503,9 @@ static const struct of_device_id dw_hdmi
|
||||
{ .compatible = "rockchip,rk3399-dw-hdmi",
|
||||
.data = &rk3399_hdmi_drv_data
|
||||
},
|
||||
+ { .compatible = "rockchip,rk3568-dw-hdmi",
|
||||
+ .data = &rk3568_hdmi_drv_data
|
||||
+ },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
|
||||
@@ -520,6 +540,9 @@ static int dw_hdmi_rockchip_bind(struct
|
||||
encoder = &hdmi->encoder.encoder;
|
||||
|
||||
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
|
||||
+ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
|
||||
+ dev->of_node, 0, 0);
|
||||
+
|
||||
/*
|
||||
* If we failed to find the CRTC(s) which this encoder is
|
||||
* supposed to be connected to, it's because the CRTC has
|
||||
@@ -550,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ if (hdmi->chip_data == &rk3568_chip_data) {
|
||||
+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
|
||||
+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
|
||||
+ RK3568_HDMI_SCLIN_MSK,
|
||||
+ RK3568_HDMI_SDAIN_MSK |
|
||||
+ RK3568_HDMI_SCLIN_MSK));
|
||||
+ }
|
||||
+
|
||||
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
|
||||
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
|
||||
|
||||
@ -0,0 +1,109 @@
|
||||
From ca80c4eb4b01a7f1c2f333d0a329937ef9c7f03a Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Fri, 22 Apr 2022 09:28:26 +0200
|
||||
Subject: [PATCH] drm/rockchip: dw_hdmi: add regulator support
|
||||
|
||||
The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed
|
||||
for the HDMI port. add support for these to the driver for boards which
|
||||
have them supplied by switchable regulators.
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-10-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++--
|
||||
1 file changed, 38 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
||||
@@ -9,6 +9,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/regmap.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
|
||||
#include <drm/bridge/dw_hdmi.h>
|
||||
#include <drm/drm_edid.h>
|
||||
@@ -76,6 +77,8 @@ struct rockchip_hdmi {
|
||||
struct clk *ref_clk;
|
||||
struct clk *grf_clk;
|
||||
struct dw_hdmi *hdmi;
|
||||
+ struct regulator *avdd_0v9;
|
||||
+ struct regulator *avdd_1v8;
|
||||
struct phy *phy;
|
||||
};
|
||||
|
||||
@@ -226,6 +229,14 @@ static int rockchip_hdmi_parse_dt(struct
|
||||
return PTR_ERR(hdmi->grf_clk);
|
||||
}
|
||||
|
||||
+ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
|
||||
+ if (IS_ERR(hdmi->avdd_0v9))
|
||||
+ return PTR_ERR(hdmi->avdd_0v9);
|
||||
+
|
||||
+ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8");
|
||||
+ if (IS_ERR(hdmi->avdd_1v8))
|
||||
+ return PTR_ERR(hdmi->avdd_1v8);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -566,11 +577,23 @@ static int dw_hdmi_rockchip_bind(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ ret = regulator_enable(hdmi->avdd_0v9);
|
||||
+ if (ret) {
|
||||
+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret);
|
||||
+ goto err_avdd_0v9;
|
||||
+ }
|
||||
+
|
||||
+ ret = regulator_enable(hdmi->avdd_1v8);
|
||||
+ if (ret) {
|
||||
+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret);
|
||||
+ goto err_avdd_1v8;
|
||||
+ }
|
||||
+
|
||||
ret = clk_prepare_enable(hdmi->ref_clk);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
|
||||
ret);
|
||||
- return ret;
|
||||
+ goto err_clk;
|
||||
}
|
||||
|
||||
if (hdmi->chip_data == &rk3568_chip_data) {
|
||||
@@ -594,10 +617,19 @@ static int dw_hdmi_rockchip_bind(struct
|
||||
*/
|
||||
if (IS_ERR(hdmi->hdmi)) {
|
||||
ret = PTR_ERR(hdmi->hdmi);
|
||||
- drm_encoder_cleanup(encoder);
|
||||
- clk_disable_unprepare(hdmi->ref_clk);
|
||||
+ goto err_bind;
|
||||
}
|
||||
|
||||
+ return 0;
|
||||
+
|
||||
+err_bind:
|
||||
+ drm_encoder_cleanup(encoder);
|
||||
+ clk_disable_unprepare(hdmi->ref_clk);
|
||||
+err_clk:
|
||||
+ regulator_disable(hdmi->avdd_1v8);
|
||||
+err_avdd_1v8:
|
||||
+ regulator_disable(hdmi->avdd_0v9);
|
||||
+err_avdd_0v9:
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -608,6 +640,9 @@ static void dw_hdmi_rockchip_unbind(stru
|
||||
|
||||
dw_hdmi_unbind(hdmi->hdmi);
|
||||
clk_disable_unprepare(hdmi->ref_clk);
|
||||
+
|
||||
+ regulator_disable(hdmi->avdd_1v8);
|
||||
+ regulator_disable(hdmi->avdd_0v9);
|
||||
}
|
||||
|
||||
static const struct component_ops dw_hdmi_rockchip_ops = {
|
||||
@ -0,0 +1,65 @@
|
||||
From b382406a2cf4afaa7320a7ad4b298ed6e2675437 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Fri, 22 Apr 2022 09:28:38 +0200
|
||||
Subject: [PATCH] drm/rockchip: Make VOP driver optional
|
||||
|
||||
With upcoming VOP2 support VOP won't be the only choice anymore, so make
|
||||
the VOP driver optional.
|
||||
|
||||
This also adds a dependency from ROCKCHIP_ANALOGIX_DP to ROCKCHIP_VOP,
|
||||
because that driver currently only links and works with the VOP driver.
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-22-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/Kconfig | 8 ++++++++
|
||||
drivers/gpu/drm/rockchip/Makefile | 3 ++-
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +-
|
||||
3 files changed, 11 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/Kconfig
|
||||
+++ b/drivers/gpu/drm/rockchip/Kconfig
|
||||
@@ -22,8 +22,16 @@ config DRM_ROCKCHIP
|
||||
|
||||
if DRM_ROCKCHIP
|
||||
|
||||
+config ROCKCHIP_VOP
|
||||
+ bool "Rockchip VOP driver"
|
||||
+ default y
|
||||
+ help
|
||||
+ This selects support for the VOP driver. You should enable it
|
||||
+ on older SoCs.
|
||||
+
|
||||
config ROCKCHIP_ANALOGIX_DP
|
||||
bool "Rockchip specific extensions for Analogix DP driver"
|
||||
+ depends on ROCKCHIP_VOP
|
||||
help
|
||||
This selects support for Rockchip SoC specific extensions
|
||||
for the Analogix Core DP driver. If you want to enable DP
|
||||
--- a/drivers/gpu/drm/rockchip/Makefile
|
||||
+++ b/drivers/gpu/drm/rockchip/Makefile
|
||||
@@ -4,9 +4,10 @@
|
||||
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
|
||||
|
||||
rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
|
||||
- rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o
|
||||
+ rockchip_drm_gem.o
|
||||
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
|
||||
|
||||
+rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
|
||||
rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
|
||||
rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
|
||||
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
@@ -494,7 +494,7 @@ static int __init rockchip_drm_init(void
|
||||
int ret;
|
||||
|
||||
num_rockchip_sub_drivers = 0;
|
||||
- ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP);
|
||||
+ ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP);
|
||||
ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
|
||||
CONFIG_ROCKCHIP_LVDS);
|
||||
ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
|
||||
@ -0,0 +1,149 @@
|
||||
From 604be85547ce4d61b89292d2f9a78c721b778c16 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Yan <andy.yan@rock-chips.com>
|
||||
Date: Fri, 22 Apr 2022 09:28:39 +0200
|
||||
Subject: [PATCH] drm/rockchip: Add VOP2 driver
|
||||
|
||||
The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
|
||||
It replaces the VOP unit found in the older Rockchip SoCs.
|
||||
|
||||
This driver has been derived from the downstream Rockchip Kernel and
|
||||
heavily modified:
|
||||
|
||||
- All nonstandard DRM properties have been removed
|
||||
- dropped struct vop2_plane_state and pass around less data between
|
||||
functions
|
||||
- Dropped all DRM_FORMAT_* not known on upstream
|
||||
- rework register access to get rid of excessively used macros
|
||||
- Drop all waiting for framesyncs
|
||||
|
||||
The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
|
||||
board. Overlay support is tested with the modetest utility. AFBC support
|
||||
on the cluster windows is tested with weston-simple-dmabuf-egl on
|
||||
weston using the (yet to be upstreamed) panfrost driver support.
|
||||
|
||||
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
||||
Co-Developed-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
[dt-binding-header:]
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
[moved dt-binding header from dt-nodes patch to here
|
||||
and made checkpatch --strict happier]
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-23-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/Kconfig | 6 +
|
||||
drivers/gpu/drm/rockchip/Makefile | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 6 +-
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 14 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2706 ++++++++++++++++++
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 477 +++
|
||||
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 281 ++
|
||||
include/dt-bindings/soc/rockchip,vop2.h | 14 +
|
||||
10 files changed, 3507 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
|
||||
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/Kconfig
|
||||
+++ b/drivers/gpu/drm/rockchip/Kconfig
|
||||
@@ -29,6 +29,12 @@ config ROCKCHIP_VOP
|
||||
This selects support for the VOP driver. You should enable it
|
||||
on older SoCs.
|
||||
|
||||
+config ROCKCHIP_VOP2
|
||||
+ bool "Rockchip VOP2 driver"
|
||||
+ help
|
||||
+ This selects support for the VOP2 driver. The VOP2 hardware is
|
||||
+ first found on the RK3568.
|
||||
+
|
||||
config ROCKCHIP_ANALOGIX_DP
|
||||
bool "Rockchip specific extensions for Analogix DP driver"
|
||||
depends on ROCKCHIP_VOP
|
||||
--- a/drivers/gpu/drm/rockchip/Makefile
|
||||
+++ b/drivers/gpu/drm/rockchip/Makefile
|
||||
@@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rock
|
||||
rockchip_drm_gem.o
|
||||
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
|
||||
|
||||
+rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o
|
||||
rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
|
||||
rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
|
||||
rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
@@ -495,6 +495,7 @@ static int __init rockchip_drm_init(void
|
||||
|
||||
num_rockchip_sub_drivers = 0;
|
||||
ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP);
|
||||
+ ADD_ROCKCHIP_SUB_DRIVER(vop2_platform_driver, CONFIG_ROCKCHIP_VOP2);
|
||||
ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
|
||||
CONFIG_ROCKCHIP_LVDS);
|
||||
ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
|
||||
@@ -18,7 +18,7 @@
|
||||
|
||||
#define ROCKCHIP_MAX_FB_BUFFER 3
|
||||
#define ROCKCHIP_MAX_CONNECTOR 2
|
||||
-#define ROCKCHIP_MAX_CRTC 2
|
||||
+#define ROCKCHIP_MAX_CRTC 4
|
||||
|
||||
struct drm_device;
|
||||
struct drm_connector;
|
||||
@@ -31,6 +31,9 @@ struct rockchip_crtc_state {
|
||||
int output_bpc;
|
||||
int output_flags;
|
||||
bool enable_afbc;
|
||||
+ u32 bus_format;
|
||||
+ u32 bus_flags;
|
||||
+ int color_space;
|
||||
};
|
||||
#define to_rockchip_crtc_state(s) \
|
||||
container_of(s, struct rockchip_crtc_state, base)
|
||||
@@ -76,6 +79,7 @@ extern struct platform_driver rockchip_d
|
||||
extern struct platform_driver rockchip_lvds_driver;
|
||||
extern struct platform_driver vop_platform_driver;
|
||||
extern struct platform_driver rk3066_hdmi_driver;
|
||||
+extern struct platform_driver vop2_platform_driver;
|
||||
|
||||
static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder)
|
||||
{
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
|
||||
@@ -134,4 +134,6 @@ void rockchip_drm_mode_config_init(struc
|
||||
|
||||
dev->mode_config.funcs = &rockchip_drm_mode_config_funcs;
|
||||
dev->mode_config.helper_private = &rockchip_mode_config_helpers;
|
||||
+
|
||||
+ dev->mode_config.normalize_zpos = true;
|
||||
}
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
@@ -54,9 +54,23 @@ struct vop_afbc {
|
||||
struct vop_reg enable;
|
||||
struct vop_reg win_sel;
|
||||
struct vop_reg format;
|
||||
+ struct vop_reg rb_swap;
|
||||
+ struct vop_reg uv_swap;
|
||||
+ struct vop_reg auto_gating_en;
|
||||
+ struct vop_reg block_split_en;
|
||||
+ struct vop_reg pic_vir_width;
|
||||
+ struct vop_reg tile_num;
|
||||
struct vop_reg hreg_block_split;
|
||||
+ struct vop_reg pic_offset;
|
||||
struct vop_reg pic_size;
|
||||
+ struct vop_reg dsp_offset;
|
||||
+ struct vop_reg transform_offset;
|
||||
struct vop_reg hdr_ptr;
|
||||
+ struct vop_reg half_block_en;
|
||||
+ struct vop_reg xmirror;
|
||||
+ struct vop_reg ymirror;
|
||||
+ struct vop_reg rotate_270;
|
||||
+ struct vop_reg rotate_90;
|
||||
struct vop_reg rstn;
|
||||
};
|
||||
|
||||
@ -0,0 +1,36 @@
|
||||
From 5ee8c8f930ba7d20717c4fc2d9f1ce0e757d1155 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Wed, 11 May 2022 10:21:08 +0200
|
||||
Subject: [PATCH] drm/rockchip: Change register space names in vop2
|
||||
|
||||
"regs" seems to generic when there are multiple register spaces, so
|
||||
rename that one to "vop". Also change "gamma_lut" to better looking
|
||||
"gamma-lut".
|
||||
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220511082109.1110043-3-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
@@ -2620,7 +2620,7 @@ static int vop2_bind(struct device *dev,
|
||||
|
||||
dev_set_drvdata(dev, vop2);
|
||||
|
||||
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
|
||||
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop");
|
||||
if (!res) {
|
||||
drm_err(vop2->drm, "failed to get vop2 register byname\n");
|
||||
return -EINVAL;
|
||||
@@ -2637,7 +2637,7 @@ static int vop2_bind(struct device *dev,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
|
||||
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut");
|
||||
if (res) {
|
||||
vop2->lut_regs = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(vop2->lut_regs))
|
||||
@ -0,0 +1,72 @@
|
||||
From 431e7d2eece5b906578926d15ee22a70504c364d Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 08:38:28 -0400
|
||||
Subject: [PATCH] PCI: rockchip-dwc: Reset core at driver probe
|
||||
|
||||
The PCIe controller is in an unknown state at driver probe. This can
|
||||
lead to undesireable effects when the driver attempts to configure the
|
||||
controller.
|
||||
|
||||
Prevent issues in the future by resetting the core during probe.
|
||||
|
||||
Link: https://lore.kernel.org/r/20220429123832.2376381-3-pgwipeout@gmail.com
|
||||
Tested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
---
|
||||
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 ++++++++-----------
|
||||
1 file changed, 10 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
@@ -152,6 +152,11 @@ static int rockchip_pcie_resource_get(st
|
||||
if (IS_ERR(rockchip->rst_gpio))
|
||||
return PTR_ERR(rockchip->rst_gpio);
|
||||
|
||||
+ rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
|
||||
+ if (IS_ERR(rockchip->rst))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
|
||||
+ "failed to get reset lines\n");
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -182,18 +187,6 @@ static void rockchip_pcie_phy_deinit(str
|
||||
phy_power_off(rockchip->phy);
|
||||
}
|
||||
|
||||
-static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip)
|
||||
-{
|
||||
- struct device *dev = rockchip->pci.dev;
|
||||
-
|
||||
- rockchip->rst = devm_reset_control_array_get_exclusive(dev);
|
||||
- if (IS_ERR(rockchip->rst))
|
||||
- return dev_err_probe(dev, PTR_ERR(rockchip->rst),
|
||||
- "failed to get reset lines\n");
|
||||
-
|
||||
- return reset_control_deassert(rockchip->rst);
|
||||
-}
|
||||
-
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.link_up = rockchip_pcie_link_up,
|
||||
.start_link = rockchip_pcie_start_link,
|
||||
@@ -222,6 +215,10 @@ static int rockchip_pcie_probe(struct pl
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ ret = reset_control_assert(rockchip->rst);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
/* DON'T MOVE ME: must be enable before PHY init */
|
||||
rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
|
||||
if (IS_ERR(rockchip->vpcie3v3)) {
|
||||
@@ -241,7 +238,7 @@ static int rockchip_pcie_probe(struct pl
|
||||
if (ret)
|
||||
goto disable_regulator;
|
||||
|
||||
- ret = rockchip_pcie_reset_control_release(rockchip);
|
||||
+ ret = reset_control_deassert(rockchip->rst);
|
||||
if (ret)
|
||||
goto deinit_phy;
|
||||
|
||||
@ -0,0 +1,163 @@
|
||||
From e8aae154df6121167e5b4f156cfc2402e651d2b1 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 08:38:29 -0400
|
||||
Subject: [PATCH] PCI: rockchip-dwc: Add legacy interrupt support
|
||||
|
||||
The legacy interrupts on the rk356x PCIe controller are handled by a
|
||||
single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip
|
||||
driver to support the virtual domain.
|
||||
|
||||
Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
Reviewed-by: Marc Zyngier <maz@kernel.org>
|
||||
---
|
||||
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 96 ++++++++++++++++++-
|
||||
1 file changed, 94 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
@@ -10,9 +10,12 @@
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
+#include <linux/irqchip/chained_irq.h>
|
||||
+#include <linux/irqdomain.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
+#include <linux/of_irq.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
@@ -26,6 +29,7 @@
|
||||
*/
|
||||
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
|
||||
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
|
||||
+#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
|
||||
|
||||
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
|
||||
|
||||
@@ -36,10 +40,12 @@
|
||||
#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
|
||||
#define PCIE_L0S_ENTRY 0x11
|
||||
#define PCIE_CLIENT_GENERAL_CONTROL 0x0
|
||||
+#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
|
||||
+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
|
||||
#define PCIE_CLIENT_GENERAL_DEBUG 0x104
|
||||
-#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
|
||||
+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
|
||||
#define PCIE_CLIENT_LTSSM_STATUS 0x300
|
||||
-#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
|
||||
+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
|
||||
#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
|
||||
|
||||
struct rockchip_pcie {
|
||||
@@ -51,6 +57,7 @@ struct rockchip_pcie {
|
||||
struct reset_control *rst;
|
||||
struct gpio_desc *rst_gpio;
|
||||
struct regulator *vpcie3v3;
|
||||
+ struct irq_domain *irq_domain;
|
||||
};
|
||||
|
||||
static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
|
||||
@@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(str
|
||||
writel_relaxed(val, rockchip->apb_base + reg);
|
||||
}
|
||||
|
||||
+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
|
||||
+{
|
||||
+ struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
|
||||
+ unsigned long reg, hwirq;
|
||||
+
|
||||
+ chained_irq_enter(chip, desc);
|
||||
+
|
||||
+ reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
|
||||
+
|
||||
+ for_each_set_bit(hwirq, ®, 4)
|
||||
+ generic_handle_domain_irq(rockchip->irq_domain, hwirq);
|
||||
+
|
||||
+ chained_irq_exit(chip, desc);
|
||||
+}
|
||||
+
|
||||
+static void rockchip_intx_mask(struct irq_data *data)
|
||||
+{
|
||||
+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
|
||||
+ HIWORD_UPDATE_BIT(BIT(data->hwirq)),
|
||||
+ PCIE_CLIENT_INTR_MASK_LEGACY);
|
||||
+};
|
||||
+
|
||||
+static void rockchip_intx_unmask(struct irq_data *data)
|
||||
+{
|
||||
+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
|
||||
+ HIWORD_DISABLE_BIT(BIT(data->hwirq)),
|
||||
+ PCIE_CLIENT_INTR_MASK_LEGACY);
|
||||
+};
|
||||
+
|
||||
+static struct irq_chip rockchip_intx_irq_chip = {
|
||||
+ .name = "INTx",
|
||||
+ .irq_mask = rockchip_intx_mask,
|
||||
+ .irq_unmask = rockchip_intx_unmask,
|
||||
+ .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
||||
+ irq_hw_number_t hwirq)
|
||||
+{
|
||||
+ irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
|
||||
+ irq_set_chip_data(irq, domain->host_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct irq_domain_ops intx_domain_ops = {
|
||||
+ .map = rockchip_pcie_intx_map,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
|
||||
+{
|
||||
+ struct device *dev = rockchip->pci.dev;
|
||||
+ struct device_node *intc;
|
||||
+
|
||||
+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
|
||||
+ if (!intc) {
|
||||
+ dev_err(dev, "missing child interrupt-controller node\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
|
||||
+ &intx_domain_ops, rockchip);
|
||||
+ of_node_put(intc);
|
||||
+ if (!rockchip->irq_domain) {
|
||||
+ dev_err(dev, "failed to get a INTx IRQ domain\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
|
||||
{
|
||||
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
|
||||
@@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struc
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
|
||||
+ struct device *dev = rockchip->pci.dev;
|
||||
u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
|
||||
+ int irq, ret;
|
||||
+
|
||||
+ irq = of_irq_get_byname(dev->of_node, "legacy");
|
||||
+ if (irq < 0)
|
||||
+ return irq;
|
||||
+
|
||||
+ ret = rockchip_pcie_init_irq_domain(rockchip);
|
||||
+ if (ret < 0)
|
||||
+ dev_err(dev, "failed to init irq domain\n");
|
||||
+
|
||||
+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,
|
||||
+ rockchip);
|
||||
|
||||
/* LTSSM enable control mode */
|
||||
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
|
||||
@ -0,0 +1,27 @@
|
||||
From 98526c5bbe3267d447ddd076b685439e3e1396c6 Mon Sep 17 00:00:00 2001
|
||||
From: Dan Carpenter <dan.carpenter@oracle.com>
|
||||
Date: Mon, 9 May 2022 12:05:05 +0300
|
||||
Subject: [PATCH] drm/rockchip: vop2: unlock on error path in
|
||||
vop2_crtc_atomic_enable()
|
||||
|
||||
This error path needs an unlock before returning.
|
||||
|
||||
Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
|
||||
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
|
||||
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/YnjZQRV9lpub2ET8@kili
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
@@ -1524,6 +1524,7 @@ static void vop2_crtc_atomic_enable(stru
|
||||
if (ret < 0) {
|
||||
drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
|
||||
vp->id, ret);
|
||||
+ vop2_unlock(vop2);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -0,0 +1,96 @@
|
||||
From 6f1ae821a6c4aa9d5b8f437b27ec86fb569219fd Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Date: Sun, 12 Jun 2022 16:53:45 +0100
|
||||
Subject: [PATCH] media: hantro: Add support for RK356x encoder
|
||||
|
||||
The RK3566 and RK3568 SoCs come with a small Hantro instance which is
|
||||
solely dedicated to encoding. This patch adds the necessary structs to
|
||||
the Hantro driver to allow the JPEG encoder of it to function.
|
||||
|
||||
Through some sleuthing through the vendor's MPP source code and after
|
||||
closer inspection of the TRM, it was determined that the hardware likely
|
||||
supports VP8 and H.264 as well.
|
||||
|
||||
Tested with the following GStreamer command:
|
||||
|
||||
gst-launch-1.0 videotestsrc ! v4l2jpegenc ! matroskamux ! \
|
||||
filesink location=foo.mkv
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
|
||||
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
|
||||
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
---
|
||||
drivers/staging/media/hantro/hantro_drv.c | 1 +
|
||||
drivers/staging/media/hantro/hantro_hw.h | 1 +
|
||||
.../staging/media/hantro/rockchip_vpu_hw.c | 25 +++++++++++++++++++
|
||||
3 files changed, 27 insertions(+)
|
||||
|
||||
--- a/drivers/staging/media/hantro/hantro_drv.c
|
||||
+++ b/drivers/staging/media/hantro/hantro_drv.c
|
||||
@@ -588,6 +588,7 @@ static const struct of_device_id of_hant
|
||||
{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
|
||||
{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
|
||||
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
|
||||
+ { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
|
||||
{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
|
||||
#endif
|
||||
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
|
||||
--- a/drivers/staging/media/hantro/hantro_hw.h
|
||||
+++ b/drivers/staging/media/hantro/hantro_hw.h
|
||||
@@ -215,6 +215,7 @@ extern const struct hantro_variant rk306
|
||||
extern const struct hantro_variant rk3288_vpu_variant;
|
||||
extern const struct hantro_variant rk3328_vpu_variant;
|
||||
extern const struct hantro_variant rk3399_vpu_variant;
|
||||
+extern const struct hantro_variant rk3568_vepu_variant;
|
||||
extern const struct hantro_variant rk3568_vpu_variant;
|
||||
extern const struct hantro_variant sama5d4_vdec_variant;
|
||||
|
||||
--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
@@ -423,6 +423,14 @@ static const struct hantro_codec_ops rk3
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
|
||||
+ [HANTRO_MODE_JPEG_ENC] = {
|
||||
+ .run = rockchip_vpu2_jpeg_enc_run,
|
||||
+ .reset = rockchip_vpu2_enc_reset,
|
||||
+ .done = rockchip_vpu2_jpeg_enc_done,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
/*
|
||||
* VPU variant.
|
||||
*/
|
||||
@@ -445,6 +453,10 @@ static const struct hantro_irq rockchip_
|
||||
{ "vdpu", rockchip_vpu2_vdpu_irq },
|
||||
};
|
||||
|
||||
+static const struct hantro_irq rk3568_vepu_irqs[] = {
|
||||
+ { "vepu", rockchip_vpu2_vepu_irq },
|
||||
+};
|
||||
+
|
||||
static const char * const rk3066_vpu_clk_names[] = {
|
||||
"aclk_vdpu", "hclk_vdpu",
|
||||
"aclk_vepu", "hclk_vepu"
|
||||
@@ -549,6 +561,19 @@ const struct hantro_variant rk3399_vpu_v
|
||||
.init = rockchip_vpu_hw_init,
|
||||
.clk_names = rockchip_vpu_clk_names,
|
||||
.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
|
||||
+};
|
||||
+
|
||||
+const struct hantro_variant rk3568_vepu_variant = {
|
||||
+ .enc_offset = 0x0,
|
||||
+ .enc_fmts = rockchip_vpu_enc_fmts,
|
||||
+ .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
|
||||
+ .codec = HANTRO_JPEG_ENCODER,
|
||||
+ .codec_ops = rk3568_vepu_codec_ops,
|
||||
+ .irqs = rk3568_vepu_irqs,
|
||||
+ .num_irqs = ARRAY_SIZE(rk3568_vepu_irqs),
|
||||
+ .init = rockchip_vpu_hw_init,
|
||||
+ .clk_names = rockchip_vpu_clk_names,
|
||||
+ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
|
||||
};
|
||||
|
||||
const struct hantro_variant rk3568_vpu_variant = {
|
||||
@ -0,0 +1,36 @@
|
||||
From fd7d47484125c7d04578de9294faa7fec6e5df0a Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Holland <samuel@sholland.org>
|
||||
Date: Fri, 8 Jul 2022 01:14:34 -0500
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Ignore OTG IRQs in host mode
|
||||
|
||||
When the OTG port is fixed to host mode, the driver does not request its
|
||||
IRQs, nor does it enable those IRQs in hardware. Similarly, the driver
|
||||
should ignore the OTG port IRQs when handling the shared interrupt.
|
||||
|
||||
Otherwise, it would update the extcon based on an ID pin which may be in
|
||||
an undefined state, or try to queue a uninitialized work item.
|
||||
|
||||
Fixes: 6a98df08ccd5 ("phy: rockchip-inno-usb2: Fix muxed interrupt support")
|
||||
Reported-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||||
Tested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220708061434.38115-1-samuel@sholland.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -988,7 +988,9 @@ static irqreturn_t rockchip_usb2phy_irq(
|
||||
|
||||
switch (rport->port_id) {
|
||||
case USB2PHY_PORT_OTG:
|
||||
- ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
|
||||
+ if (rport->mode != USB_DR_MODE_HOST &&
|
||||
+ rport->mode != USB_DR_MODE_UNKNOWN)
|
||||
+ ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
|
||||
break;
|
||||
case USB2PHY_PORT_HOST:
|
||||
ret |= rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
@ -0,0 +1,126 @@
|
||||
From 177d841fa19542eb35aa5ec9579c4abb989c9255 Mon Sep 17 00:00:00 2001
|
||||
From: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
|
||||
Date: Wed, 29 Jun 2022 20:56:23 +0100
|
||||
Subject: [PATCH] media: hantro: Fix RK3399 H.264 format advertising
|
||||
|
||||
Commit 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
|
||||
enabled H.264 on some SoCs with VDPU2 cores. This had the side-effect
|
||||
of exposing H.264 coded format as supported on RK3399.
|
||||
|
||||
Fix this and clarify how the codec is explicitly disabled on RK3399 on
|
||||
this driver.
|
||||
|
||||
Fixes: 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
|
||||
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
|
||||
Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
|
||||
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
|
||||
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
|
||||
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
---
|
||||
.../staging/media/hantro/rockchip_vpu_hw.c | 60 ++++++++++++++++---
|
||||
1 file changed, 53 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
@@ -158,7 +158,7 @@ static const struct hantro_fmt rk3288_vp
|
||||
},
|
||||
};
|
||||
|
||||
-static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
|
||||
+static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
|
||||
{
|
||||
.fourcc = V4L2_PIX_FMT_NV12,
|
||||
.codec_mode = HANTRO_MODE_NONE,
|
||||
@@ -204,6 +204,47 @@ static const struct hantro_fmt rk3399_vp
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
|
||||
+ {
|
||||
+ .fourcc = V4L2_PIX_FMT_NV12,
|
||||
+ .codec_mode = HANTRO_MODE_NONE,
|
||||
+ .frmsize = {
|
||||
+ .min_width = FMT_MIN_WIDTH,
|
||||
+ .max_width = FMT_FHD_WIDTH,
|
||||
+ .step_width = MB_DIM,
|
||||
+ .min_height = FMT_MIN_HEIGHT,
|
||||
+ .max_height = FMT_FHD_HEIGHT,
|
||||
+ .step_height = MB_DIM,
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
|
||||
+ .codec_mode = HANTRO_MODE_MPEG2_DEC,
|
||||
+ .max_depth = 2,
|
||||
+ .frmsize = {
|
||||
+ .min_width = FMT_MIN_WIDTH,
|
||||
+ .max_width = FMT_FHD_WIDTH,
|
||||
+ .step_width = MB_DIM,
|
||||
+ .min_height = FMT_MIN_HEIGHT,
|
||||
+ .max_height = FMT_FHD_HEIGHT,
|
||||
+ .step_height = MB_DIM,
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .fourcc = V4L2_PIX_FMT_VP8_FRAME,
|
||||
+ .codec_mode = HANTRO_MODE_VP8_DEC,
|
||||
+ .max_depth = 2,
|
||||
+ .frmsize = {
|
||||
+ .min_width = FMT_MIN_WIDTH,
|
||||
+ .max_width = FMT_UHD_WIDTH,
|
||||
+ .step_width = MB_DIM,
|
||||
+ .min_height = FMT_MIN_HEIGHT,
|
||||
+ .max_height = FMT_UHD_HEIGHT,
|
||||
+ .step_height = MB_DIM,
|
||||
+ },
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct hantro_dev *vpu = dev_id;
|
||||
@@ -534,8 +575,8 @@ const struct hantro_variant rk3288_vpu_v
|
||||
|
||||
const struct hantro_variant rk3328_vpu_variant = {
|
||||
.dec_offset = 0x400,
|
||||
- .dec_fmts = rk3399_vpu_dec_fmts,
|
||||
- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
|
||||
+ .dec_fmts = rockchip_vdpu2_dec_fmts,
|
||||
+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
|
||||
.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
|
||||
HANTRO_H264_DECODER,
|
||||
.codec_ops = rk3399_vpu_codec_ops,
|
||||
@@ -546,6 +587,11 @@ const struct hantro_variant rk3328_vpu_v
|
||||
.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
|
||||
};
|
||||
|
||||
+/*
|
||||
+ * H.264 decoding explicitly disabled in RK3399.
|
||||
+ * This ensures userspace applications use the Rockchip VDEC core,
|
||||
+ * which has better performance.
|
||||
+ */
|
||||
const struct hantro_variant rk3399_vpu_variant = {
|
||||
.enc_offset = 0x0,
|
||||
.enc_fmts = rockchip_vpu_enc_fmts,
|
||||
@@ -578,8 +624,8 @@ const struct hantro_variant rk3568_vepu_
|
||||
|
||||
const struct hantro_variant rk3568_vpu_variant = {
|
||||
.dec_offset = 0x400,
|
||||
- .dec_fmts = rk3399_vpu_dec_fmts,
|
||||
- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
|
||||
+ .dec_fmts = rockchip_vdpu2_dec_fmts,
|
||||
+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
|
||||
.codec = HANTRO_MPEG2_DECODER |
|
||||
HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
|
||||
.codec_ops = rk3399_vpu_codec_ops,
|
||||
@@ -595,8 +641,8 @@ const struct hantro_variant px30_vpu_var
|
||||
.enc_fmts = rockchip_vpu_enc_fmts,
|
||||
.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
|
||||
.dec_offset = 0x400,
|
||||
- .dec_fmts = rk3399_vpu_dec_fmts,
|
||||
- .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
|
||||
+ .dec_fmts = rockchip_vdpu2_dec_fmts,
|
||||
+ .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
|
||||
.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
|
||||
HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
|
||||
.codec_ops = rk3399_vpu_codec_ops,
|
||||
@ -0,0 +1,27 @@
|
||||
From b113e55913e7f7f031d6cbf9d7b585c6b112f55a Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 25 Jun 2022 17:27:11 -0400
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Prevent incorrect error on probe
|
||||
|
||||
If a phy supply is designated but isn't available at probe time, an
|
||||
EPROBE_DEFER is returned. Use dev_err_probe to prevent this from
|
||||
incorrectly printing during boot.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220625212711.558495-1-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1295,7 +1295,7 @@ static int rockchip_usb2phy_probe(struct
|
||||
|
||||
phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
- dev_err(dev, "failed to create phy\n");
|
||||
+ dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
|
||||
ret = PTR_ERR(phy);
|
||||
goto put_child;
|
||||
}
|
||||
@ -0,0 +1,33 @@
|
||||
From 8dc60f8da22fdbaa1fafcfb5ff6d24bc9eff56aa Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Tue, 21 Jun 2022 20:31:40 -0400
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Sync initial otg state
|
||||
|
||||
The initial otg state for the phy defaults to device mode. The actual
|
||||
state isn't detected until an ID IRQ fires. Fix this by syncing the ID
|
||||
state during initialization.
|
||||
|
||||
Fixes: 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ")
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Reviewed-by: Samuel Holland <samuel@sholland.org>
|
||||
Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1174,6 +1174,12 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
EXTCON_USB_HOST, &rport->event_nb);
|
||||
if (ret)
|
||||
dev_err(rphy->dev, "register USB HOST notifier failed\n");
|
||||
+
|
||||
+ if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
|
||||
+ /* do initial sync of usb state */
|
||||
+ ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
|
||||
+ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret);
|
||||
+ }
|
||||
}
|
||||
|
||||
out:
|
||||
@ -0,0 +1,57 @@
|
||||
From 2e9bffc4f713db465177238f6033f7d367d6f151 Mon Sep 17 00:00:00 2001
|
||||
From: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Date: Thu, 25 Aug 2022 21:38:34 +0200
|
||||
Subject: [PATCH] phy: rockchip: Support PCIe v3
|
||||
|
||||
RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
|
||||
It use a dedicated PCIe-phy. Add support for this.
|
||||
|
||||
Initial support by Shawn Lin, modifications by Peter Geis and Frank
|
||||
Wunderlich.
|
||||
|
||||
Add data-lanes property for splitting pcie-lanes across controllers.
|
||||
|
||||
The data-lanes is an array where x=0 means lane is disabled and x > 0
|
||||
means controller x is assigned to phy lane.
|
||||
|
||||
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Suggested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.de
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 9 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 319 ++++++++++++++++++
|
||||
include/linux/phy/pcie.h | 12 +
|
||||
4 files changed, 341 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
create mode 100644 include/linux/phy/pcie.h
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE
|
||||
help
|
||||
Enable this to support the Rockchip PCIe PHY.
|
||||
|
||||
+config PHY_ROCKCHIP_SNPS_PCIE3
|
||||
+ tristate "Rockchip Snps PCIe3 PHY Driver"
|
||||
+ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
+ depends on HAS_IOMEM
|
||||
+ select GENERIC_PHY
|
||||
+ select MFD_SYSCON
|
||||
+ help
|
||||
+ Enable this to support the Rockchip snps PCIe3 PHY.
|
||||
+
|
||||
config PHY_ROCKCHIP_TYPEC
|
||||
tristate "Rockchip TYPEC PHY Driver"
|
||||
depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST)
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) +=
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
@ -0,0 +1,54 @@
|
||||
From f340ed8664a55a467850ec1689996e63d9ee971a Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 2 Sep 2022 14:45:42 -0400
|
||||
Subject: [PATCH] phy: rockchip-inno-usb2: Return zero after otg sync
|
||||
|
||||
The otg sync state patch reuses the ret variable, but fails to set it to
|
||||
zero after use. This leads to a situation when the otg port is in
|
||||
peripheral mode where the otg phy aborts halfway through setup. It also
|
||||
fails to account for a failure to register the extcon notifier. Fix this
|
||||
by using our own variable and skipping otg sync in case of failure.
|
||||
|
||||
Fixes: 8dc60f8da22f ("phy: rockchip-inno-usb2: Sync initial otg state")
|
||||
Reported-by: Markus Reichl <m.reichl@fivetechno.de>
|
||||
Reported-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
|
||||
Reviewed-by: Samuel Holland <samuel@sholland.org>
|
||||
Link: https://lore.kernel.org/r/20220902184543.1234835-1-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 10 ++++++----
|
||||
1 file changed, 6 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1134,7 +1134,7 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
{
|
||||
- int ret;
|
||||
+ int ret, id;
|
||||
|
||||
rport->port_id = USB2PHY_PORT_OTG;
|
||||
rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
|
||||
@@ -1172,13 +1172,15 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
|
||||
ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
|
||||
EXTCON_USB_HOST, &rport->event_nb);
|
||||
- if (ret)
|
||||
+ if (ret) {
|
||||
dev_err(rphy->dev, "register USB HOST notifier failed\n");
|
||||
+ goto out;
|
||||
+ }
|
||||
|
||||
if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
|
||||
/* do initial sync of usb state */
|
||||
- ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
|
||||
- extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret);
|
||||
+ id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
|
||||
+ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
|
||||
}
|
||||
}
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
From 37d40a21473fdf1d0194089eb259b8ceeec2a4b9 Mon Sep 17 00:00:00 2001
|
||||
From: Aurelien Jarno <aurelien@aurel32.net>
|
||||
Date: Tue, 27 Sep 2022 07:17:52 +0200
|
||||
Subject: [PATCH] phy: rockchip-snps-pcie3: only look for rockchip,pipe-grf on
|
||||
rk3588
|
||||
|
||||
The rockchip,pipe-grf property is only used on rk3588, but not on
|
||||
rk3568. Therefore this property is not present on rk3568 devices,
|
||||
leading to the following message:
|
||||
|
||||
rockchip-snps-pcie3-phy fe8c0000.phy: failed to find rockchip,pipe_grf regmap
|
||||
|
||||
Fix that by only looking for this property on rk3588.
|
||||
|
||||
Fixes: 2e9bffc4f713d ("phy: rockchip: Support PCIe v3")
|
||||
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
|
||||
Link: https://lore.kernel.org/r/20220927051752.53089-1-aurelien@aurel32.net
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 13 +++++++++----
|
||||
1 file changed, 9 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -257,10 +257,15 @@ static int rockchip_p3phy_probe(struct p
|
||||
return PTR_ERR(priv->phy_grf);
|
||||
}
|
||||
|
||||
- priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
- "rockchip,pipe-grf");
|
||||
- if (IS_ERR(priv->pipe_grf))
|
||||
- dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
|
||||
+ if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) {
|
||||
+ priv->pipe_grf =
|
||||
+ syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
+ "rockchip,pipe-grf");
|
||||
+ if (IS_ERR(priv->pipe_grf))
|
||||
+ dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
|
||||
+ } else {
|
||||
+ priv->pipe_grf = NULL;
|
||||
+ }
|
||||
|
||||
priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",
|
||||
priv->lanes, 2,
|
||||
@ -0,0 +1,47 @@
|
||||
From afa965a45e01e541cdbe5c8018226eff117610f0 Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Thu, 13 Apr 2023 16:43:47 +0200
|
||||
Subject: [PATCH] drm/rockchip: vop2: fix suspend/resume
|
||||
|
||||
During a suspend/resume cycle the VO power domain will be disabled and
|
||||
the VOP2 registers will reset to their default values. After that the
|
||||
cached register values will be out of sync and the read/modify/write
|
||||
operations we do on the window registers will result in bogus values
|
||||
written. Fix this by re-initializing the register cache each time we
|
||||
enable the VOP2. With this the VOP2 will show a picture after a
|
||||
suspend/resume cycle whereas without this the screen stays dark.
|
||||
|
||||
Fixes: 604be85547ce4 ("drm/rockchip: Add VOP2 driver")
|
||||
Cc: stable@vger.kernel.org
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Chris Morgan <macromorgan@hotmail.com>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20230413144347.3506023-1-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
@@ -214,6 +214,8 @@ struct vop2 {
|
||||
struct vop2_win win[];
|
||||
};
|
||||
|
||||
+static const struct regmap_config vop2_regmap_config;
|
||||
+
|
||||
static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
|
||||
{
|
||||
return container_of(crtc, struct vop2_video_port, crtc);
|
||||
@@ -838,6 +840,12 @@ static void vop2_enable(struct vop2 *vop
|
||||
return;
|
||||
}
|
||||
|
||||
+ ret = regmap_reinit_cache(vop2->map, &vop2_regmap_config);
|
||||
+ if (ret) {
|
||||
+ drm_err(vop2->drm, "failed to reinit cache: %d\n", ret);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
if (vop2->data->soc_id == 3566)
|
||||
vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
|
||||
|
||||
@ -0,0 +1,53 @@
|
||||
From b63a553e8f5aa6574eeb535a551817a93c426d8c Mon Sep 17 00:00:00 2001
|
||||
From: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Date: Mon, 17 Apr 2023 14:37:47 +0200
|
||||
Subject: [PATCH] drm/rockchip: vop2: Use regcache_sync() to fix suspend/resume
|
||||
|
||||
afa965a45e01 ("drm/rockchip: vop2: fix suspend/resume") uses
|
||||
regmap_reinit_cache() to fix the suspend/resume issue with the VOP2
|
||||
driver. During discussion it came up that we should rather use
|
||||
regcache_sync() instead. As the original patch is already applied
|
||||
fix this up in this follow-up patch.
|
||||
|
||||
Fixes: afa965a45e01 ("drm/rockchip: vop2: fix suspend/resume")
|
||||
Cc: stable@vger.kernel.org
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20230417123747.2179695-1-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 10 +++-------
|
||||
1 file changed, 3 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
@@ -214,8 +214,6 @@ struct vop2 {
|
||||
struct vop2_win win[];
|
||||
};
|
||||
|
||||
-static const struct regmap_config vop2_regmap_config;
|
||||
-
|
||||
static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
|
||||
{
|
||||
return container_of(crtc, struct vop2_video_port, crtc);
|
||||
@@ -840,11 +838,7 @@ static void vop2_enable(struct vop2 *vop
|
||||
return;
|
||||
}
|
||||
|
||||
- ret = regmap_reinit_cache(vop2->map, &vop2_regmap_config);
|
||||
- if (ret) {
|
||||
- drm_err(vop2->drm, "failed to reinit cache: %d\n", ret);
|
||||
- return;
|
||||
- }
|
||||
+ regcache_sync(vop2->map);
|
||||
|
||||
if (vop2->data->soc_id == 3566)
|
||||
vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
|
||||
@@ -874,6 +868,8 @@ static void vop2_disable(struct vop2 *vo
|
||||
|
||||
pm_runtime_put_sync(vop2->dev);
|
||||
|
||||
+ regcache_mark_dirty(vop2->map);
|
||||
+
|
||||
clk_disable_unprepare(vop2->aclk);
|
||||
clk_disable_unprepare(vop2->hclk);
|
||||
}
|
||||
@ -0,0 +1,123 @@
|
||||
From d0637c505f8a1d8c4088642f1f3e9e3b22da14f6 Mon Sep 17 00:00:00 2001
|
||||
From: Barry Song <v-songbaohua@oppo.com>
|
||||
Date: Wed, 20 Jul 2022 21:37:37 +1200
|
||||
Subject: [PATCH] arm64: enable THP_SWAP for arm64
|
||||
|
||||
THP_SWAP has been proven to improve the swap throughput significantly
|
||||
on x86_64 according to commit bd4c82c22c367e ("mm, THP, swap: delay
|
||||
splitting THP after swapped out").
|
||||
As long as arm64 uses 4K page size, it is quite similar with x86_64
|
||||
by having 2MB PMD THP. THP_SWAP is architecture-independent, thus,
|
||||
enabling it on arm64 will benefit arm64 as well.
|
||||
A corner case is that MTE has an assumption that only base pages
|
||||
can be swapped. We won't enable THP_SWAP for ARM64 hardware with
|
||||
MTE support until MTE is reworked to coexist with THP_SWAP.
|
||||
|
||||
A micro-benchmark is written to measure thp swapout throughput as
|
||||
below,
|
||||
|
||||
unsigned long long tv_to_ms(struct timeval tv)
|
||||
{
|
||||
return tv.tv_sec * 1000 + tv.tv_usec / 1000;
|
||||
}
|
||||
|
||||
main()
|
||||
{
|
||||
struct timeval tv_b, tv_e;;
|
||||
#define SIZE 400*1024*1024
|
||||
volatile void *p = mmap(NULL, SIZE, PROT_READ | PROT_WRITE,
|
||||
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
|
||||
if (!p) {
|
||||
perror("fail to get memory");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
madvise(p, SIZE, MADV_HUGEPAGE);
|
||||
memset(p, 0x11, SIZE); /* write to get mem */
|
||||
|
||||
gettimeofday(&tv_b, NULL);
|
||||
madvise(p, SIZE, MADV_PAGEOUT);
|
||||
gettimeofday(&tv_e, NULL);
|
||||
|
||||
printf("swp out bandwidth: %ld bytes/ms\n",
|
||||
SIZE/(tv_to_ms(tv_e) - tv_to_ms(tv_b)));
|
||||
}
|
||||
|
||||
Testing is done on rk3568 64bit Quad Core Cortex-A55 platform -
|
||||
ROCK 3A.
|
||||
thp swp throughput w/o patch: 2734bytes/ms (mean of 10 tests)
|
||||
thp swp throughput w/ patch: 3331bytes/ms (mean of 10 tests)
|
||||
|
||||
Cc: "Huang, Ying" <ying.huang@intel.com>
|
||||
Cc: Minchan Kim <minchan@kernel.org>
|
||||
Cc: Johannes Weiner <hannes@cmpxchg.org>
|
||||
Cc: Hugh Dickins <hughd@google.com>
|
||||
Cc: Andrea Arcangeli <aarcange@redhat.com>
|
||||
Cc: Steven Price <steven.price@arm.com>
|
||||
Cc: Yang Shi <shy828301@gmail.com>
|
||||
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
|
||||
Signed-off-by: Barry Song <v-songbaohua@oppo.com>
|
||||
Link: https://lore.kernel.org/r/20220720093737.133375-1-21cnbao@gmail.com
|
||||
Signed-off-by: Will Deacon <will@kernel.org>
|
||||
---
|
||||
arch/arm64/Kconfig | 1 +
|
||||
arch/arm64/include/asm/pgtable.h | 6 ++++++
|
||||
include/linux/huge_mm.h | 12 ++++++++++++
|
||||
mm/swap_slots.c | 2 +-
|
||||
4 files changed, 20 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/Kconfig
|
||||
+++ b/arch/arm64/Kconfig
|
||||
@@ -95,6 +95,7 @@ config ARM64
|
||||
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
|
||||
select ARCH_WANT_LD_ORPHAN_WARN
|
||||
select ARCH_WANTS_NO_INSTR
|
||||
+ select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
|
||||
select ARCH_HAS_UBSAN_SANITIZE_ALL
|
||||
select ARM_AMBA
|
||||
select ARM_ARCH_TIMER
|
||||
--- a/arch/arm64/include/asm/pgtable.h
|
||||
+++ b/arch/arm64/include/asm/pgtable.h
|
||||
@@ -44,6 +44,12 @@
|
||||
__flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
|
||||
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
||||
|
||||
+static inline bool arch_thp_swp_supported(void)
|
||||
+{
|
||||
+ return !system_supports_mte();
|
||||
+}
|
||||
+#define arch_thp_swp_supported arch_thp_swp_supported
|
||||
+
|
||||
/*
|
||||
* Outside of a few very special situations (e.g. hibernation), we always
|
||||
* use broadcast TLB invalidation instructions, therefore a spurious page
|
||||
--- a/include/linux/huge_mm.h
|
||||
+++ b/include/linux/huge_mm.h
|
||||
@@ -495,4 +495,16 @@ static inline unsigned long thp_size(str
|
||||
return PAGE_SIZE << thp_order(page);
|
||||
}
|
||||
|
||||
+/*
|
||||
+ * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to
|
||||
+ * limitations in the implementation like arm64 MTE can override this to
|
||||
+ * false
|
||||
+ */
|
||||
+#ifndef arch_thp_swp_supported
|
||||
+static inline bool arch_thp_swp_supported(void)
|
||||
+{
|
||||
+ return true;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
#endif /* _LINUX_HUGE_MM_H */
|
||||
--- a/mm/swap_slots.c
|
||||
+++ b/mm/swap_slots.c
|
||||
@@ -308,7 +308,7 @@ swp_entry_t get_swap_page(struct page *p
|
||||
entry.val = 0;
|
||||
|
||||
if (PageTransHuge(page)) {
|
||||
- if (IS_ENABLED(CONFIG_THP_SWAP))
|
||||
+ if (IS_ENABLED(CONFIG_THP_SWAP) && arch_thp_swp_supported())
|
||||
get_swap_pages(1, &entry, HPAGE_PMD_NR);
|
||||
goto out;
|
||||
}
|
||||
@ -0,0 +1,54 @@
|
||||
From 3b6c472822f8bdeaa3cea8290f5b4a210dca5585 Mon Sep 17 00:00:00 2001
|
||||
From: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
Date: Thu, 3 Mar 2022 17:45:22 +0100
|
||||
Subject: [PATCH] mmc: core: Improve fallback to speed modes if eMMC HS200
|
||||
fails
|
||||
|
||||
In the error path of mmc_select_hs200() we are trying our best to restore
|
||||
the card/host into a valid state. This makes sense, especially if we
|
||||
encounter a simple switch error (-EBADMSG). However, rather than then
|
||||
continue with using the legacy speed mode, let's try the other better speed
|
||||
modes first. Additionally, let's update the card->mmc_avail_type to avoid
|
||||
us from trying a broken HS200 mode again.
|
||||
|
||||
In an Amlogic S905W based TV box where the switch to HS200 mode fails for
|
||||
the eMMC, this allows us to use the eMMC in DDR mode in favor of the legacy
|
||||
mode, which greatly improves the performance.
|
||||
|
||||
Suggested-by: Heiner Kallweit <hkallweit1@gmail.com>
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
Tested-by: Heiner Kallweit <hkallweit1@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220303164522.129583-1-ulf.hansson@linaro.org
|
||||
---
|
||||
drivers/mmc/core/mmc.c | 16 +++++++++++++---
|
||||
1 file changed, 13 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/mmc/core/mmc.c
|
||||
+++ b/drivers/mmc/core/mmc.c
|
||||
@@ -1530,13 +1530,23 @@ static int mmc_select_timing(struct mmc_
|
||||
if (!mmc_can_ext_csd(card))
|
||||
goto bus_speed;
|
||||
|
||||
- if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES)
|
||||
+ if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES) {
|
||||
err = mmc_select_hs400es(card);
|
||||
- else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200)
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
+ if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) {
|
||||
err = mmc_select_hs200(card);
|
||||
- else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS)
|
||||
+ if (err == -EBADMSG)
|
||||
+ card->mmc_avail_type &= ~EXT_CSD_CARD_TYPE_HS200;
|
||||
+ else
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
+ if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS)
|
||||
err = mmc_select_hs(card);
|
||||
|
||||
+out:
|
||||
if (err && err != -EBADMSG)
|
||||
return err;
|
||||
|
||||
@ -0,0 +1,407 @@
|
||||
From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Sat, 3 Dec 2022 15:41:49 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
|
||||
|
||||
Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
|
||||
|
||||
This device is similar to the NanoPi R2S, and has a 16MB
|
||||
SPI NOR (mx25l12805d). The reset button is changed to
|
||||
directly reset the power supply, another detail is that
|
||||
both network ports have independent MAC addresses.
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
|
||||
2 files changed, 374 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -0,0 +1,373 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Based on rk3328-nanopi-r2s.dts, which is:
|
||||
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include "rk3328.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus";
|
||||
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet1 = &rtl8153;
|
||||
+ mmc0 = &sdmmc;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gmac_clk: gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ led-0 {
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-1 {
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+
|
||||
+ led-2 {
|
||||
+ function = LED_FUNCTION_WAN;
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd: sdmmc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&sdmmc0m1_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_sd";
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_io>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v_lan: vdd-5v-lan-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-0 = <&lan_vdd_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vdd_5v_lan";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&display_subsystem {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
|
||||
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rtl8211e>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-supply = <&vcc_io>;
|
||||
+ pinctrl-0 = <&rgmiim1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ snps,aal;
|
||||
+ rx_delay = <0x18>;
|
||||
+ tx_delay = <0x24>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rtl8211e: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk805: pmic@18 {
|
||||
+ compatible = "rockchip,rk805";
|
||||
+ reg = <0x18>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk805-clkout2";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc_sys>;
|
||||
+ vcc2-supply = <&vcc_sys>;
|
||||
+ vcc3-supply = <&vcc_sys>;
|
||||
+ vcc4-supply = <&vcc_sys>;
|
||||
+ vcc5-supply = <&vcc_io>;
|
||||
+ vcc6-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_log: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_io";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_18: LDO_REG1 {
|
||||
+ regulator-name = "vcc_18";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc18_emmc: LDO_REG2 {
|
||||
+ regulator-name = "vcc18_emmc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_10: LDO_REG3 {
|
||||
+ regulator-name = "vdd_10";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ pmuio-supply = <&vcc_io>;
|
||||
+ vccio1-supply = <&vcc_io>;
|
||||
+ vccio2-supply = <&vcc18_emmc>;
|
||||
+ vccio3-supply = <&vcc_io>;
|
||||
+ vccio4-supply = <&vcc_io>;
|
||||
+ vccio5-supply = <&vcc_io>;
|
||||
+ vccio6-supply = <&vcc_io>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac2io {
|
||||
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ lan {
|
||||
+ lan_vdd_pin: lan-vdd-pin {
|
||||
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&spi0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ /* Second port is for USB 3.0 */
|
||||
+ rtl8153: device@2 {
|
||||
+ compatible = "usbbda,8153";
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,753 @@
|
||||
From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001
|
||||
From: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
Date: Tue, 7 Mar 2023 22:32:40 -0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S
|
||||
|
||||
FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
|
||||
|
||||
Board Specifications
|
||||
- Rockchip RK3568
|
||||
- 2 or 4GB LPDDR4X
|
||||
- 8GB or 16GB eMMC, SD card slot
|
||||
- GbE LAN (Native)
|
||||
- 2x 2.5G LAN (PCIe)
|
||||
- M.2 Connector
|
||||
- HDMI 2.0, MIPI DSI/CSI
|
||||
- 2xUSB 3.0 Host
|
||||
- USB Type C PD, 5V/9V/12V
|
||||
- GPIO: 12-pin 0.5mm FPC connector
|
||||
|
||||
Based on Tianling Shen's <cnsztl@gmail.com> work.
|
||||
|
||||
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++
|
||||
2 files changed, 714 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -54,3 +54,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
@@ -0,0 +1,713 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyelec.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R5S";
|
||||
+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac0;
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ hdmi-con {
|
||||
+ compatible = "hdmi-connector";
|
||||
+ type = "a";
|
||||
+
|
||||
+ port {
|
||||
+ hdmi_con_in: endpoint {
|
||||
+ remote-endpoint = <&hdmi_out_con>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
|
||||
+
|
||||
+ led-lan1 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ function-enumerator = <1>;
|
||||
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-lan2 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ function-enumerator = <2>;
|
||||
+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ power_led: led-power {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = LED_FUNCTION_POWER;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-wan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WAN;
|
||||
+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_usbc: vdd-usbc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_usbc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vdd_usbc>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vdd_usbc>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ startup-delay-us = <200000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb: vcc5v0-usb-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vdd_usbc>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
+ regulator-name = "vcc5v0_usb_host";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gmac0 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy0>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac0_miim
|
||||
+ &gmac0_tx_bus2
|
||||
+ &gmac0_rx_bus2
|
||||
+ &gmac0_rgmii_clk
|
||||
+ &gmac0_rgmii_bus>;
|
||||
+ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 15ms, 50ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 15000 50000>;
|
||||
+ tx_delay = <0x3c>;
|
||||
+ rx_delay = <0x2f>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ avdd-0v9-supply = <&vdda0v9_image>;
|
||||
+ avdd-1v8-supply = <&vcca1v8_image>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint {
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_out {
|
||||
+ hdmi_out_con: endpoint {
|
||||
+ remote-endpoint = <&hdmi_con_in>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c5 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ hym8563: rtc@51 {
|
||||
+ compatible = "haoyu,hym8563";
|
||||
+ reg = <0x51>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-output-names = "rtcic_32kout";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hym8563_int>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s1_8ch {
|
||||
+ rockchip,trcm-sync-tx-only;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ rgmii_phy0: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy0_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ data-lanes = <1 2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ num-ib-windows = <8>;
|
||||
+ num-ob-windows = <8>;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac0 {
|
||||
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
|
||||
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ lan1_led_pin: lan1-led-pin {
|
||||
+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ lan2_led_pin: lan2-led-pin {
|
||||
+ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ power_led_pin: power-led-pin {
|
||||
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hym8563 {
|
||||
+ hym8563_int: hym8563-int {
|
||||
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic-int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ max-frequency = <150000000>;
|
||||
+ no-sdio;
|
||||
+ no-mmc;
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ extcon = <&usb2phy0>;
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_usb_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,151 @@
|
||||
From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 18 Mar 2023 16:37:43 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C
|
||||
|
||||
FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
|
||||
|
||||
Specification:
|
||||
- Rockchip RK3568
|
||||
- 1/4GB LPDDR4X RAM
|
||||
- 8/32GB eMMC
|
||||
- SD card slot
|
||||
- M.2 Connector
|
||||
- 2x USB 3.0 Port
|
||||
- 2x 2500 Base-T (PCIe, r8125)
|
||||
- HDMI 2.0
|
||||
- MIPI DSI/CSI
|
||||
- USB Type C 5V
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++
|
||||
2 files changed, 113 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -54,4 +54,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
@@ -0,0 +1,112 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyelec.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3568-nanopi-r5s.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R5C";
|
||||
+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ button-reset {
|
||||
+ debounce-interval = <50>;
|
||||
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
|
||||
+
|
||||
+ led-lan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ power_led: led-power {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = LED_FUNCTION_POWER;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-wan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WAN;
|
||||
+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-wlan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WLAN;
|
||||
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie20_reset_pin>;
|
||||
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ power_led_pin: power-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wlan_led_pin: wlan-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie20_reset_pin: pcie20-reset-pin {
|
||||
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -0,0 +1,49 @@
|
||||
From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 18 Mar 2023 16:37:44 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S
|
||||
|
||||
- Changed phy-mode to rgmii.
|
||||
|
||||
- Fixed pull type in pinctrl for gmac0.
|
||||
|
||||
- Removed duplicate properties in mdio node.
|
||||
These properties are defined in the gmac0 node already.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
|
||||
1 file changed, 2 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
@@ -57,7 +57,7 @@
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
- phy-mode = "rgmii-id";
|
||||
+ phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
@@ -79,9 +79,6 @@
|
||||
reg = <1>;
|
||||
pinctrl-0 = <ð_phy0_reset_pin>;
|
||||
pinctrl-names = "default";
|
||||
- reset-assert-us = <10000>;
|
||||
- reset-deassert-us = <50000>;
|
||||
- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -115,7 +112,7 @@
|
||||
&pinctrl {
|
||||
gmac0 {
|
||||
eth_phy0_reset_pin: eth-phy0-reset-pin {
|
||||
- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -0,0 +1,39 @@
|
||||
From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 18 Mar 2023 16:37:45 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5
|
||||
series
|
||||
|
||||
This is for the audio output which does not exist on the boards.
|
||||
Also disable regulator-always-on for vccio_acodec since it's only
|
||||
used by the audio output.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------
|
||||
1 file changed, 6 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
@@ -330,7 +330,6 @@
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
- regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
@@ -441,11 +440,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
-&i2s1_8ch {
|
||||
- rockchip,trcm-sync-tx-only;
|
||||
- status = "okay";
|
||||
-};
|
||||
-
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
@ -0,0 +1,70 @@
|
||||
From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 25 Mar 2023 15:40:20 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
|
||||
|
||||
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
|
||||
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++
|
||||
2 files changed, 41 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
@@ -0,0 +1,40 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C";
|
||||
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8521s>;
|
||||
+ tx_delay = <0x22>;
|
||||
+ rx_delay = <0x12>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8521s: ethernet-phy@3 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <3>;
|
||||
+
|
||||
+ motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
+ motorcomm,keep-pll-enabled;
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
+
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -0,0 +1,71 @@
|
||||
From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 25 Mar 2023 15:40:22 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
|
||||
|
||||
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
|
||||
the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
|
||||
identical to OrangePi R1 Plus.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++
|
||||
2 files changed, 41 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -0,0 +1,40 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
|
||||
+ * (http://www.orangepi.org)
|
||||
+ *
|
||||
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-orangepi-r1-plus.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus LTS";
|
||||
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8531c>;
|
||||
+ tx_delay = <0x19>;
|
||||
+ rx_delay = <0x05>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8531c: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
+ motorcomm,keep-pll-enabled;
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
+
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <15000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -0,0 +1,552 @@
|
||||
From ddb6cde1cf59eb57820a6c277b8b5cff45e68d68 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 6 May 2023 14:11:07 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Lunzn Fastrhino R66S
|
||||
|
||||
Lunzn Fastrhino R66S is a high-performance mini router.
|
||||
|
||||
Specification:
|
||||
- Rockchip RK3568
|
||||
- 1/2GB LPDDR4 RAM
|
||||
- SD card slot
|
||||
- 2x USB 3.0 Port
|
||||
- 2x 2500 Base-T (PCIe, r8125b)
|
||||
- 12v DC Jack
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230506061108.17658-2-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-fastrhino-r66s.dts | 27 ++
|
||||
.../boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi | 484 +++++++++++++++++++++
|
||||
3 files changed, 512 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -56,5 +56,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
|
||||
@@ -0,0 +1,27 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+#include "rk3568-fastrhino-r66s.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Lunzn FastRhino R66S";
|
||||
+ compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ max-frequency = <150000000>;
|
||||
+ no-sdio;
|
||||
+ no-mmc;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
@@ -0,0 +1,484 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ button-reset {
|
||||
+ debounce-interval = <50>;
|
||||
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&status_led_pin>;
|
||||
+
|
||||
+ status_led: led-status {
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ dc_12v: dc-12v-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "dc_12v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb_host";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-init-microvolt = <950000>;
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ data-lanes = <1 2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic-int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ dr_mode = "host";
|
||||
+ extcon = <&usb2phy0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ phy-supply = <&vcc5v0_usb_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,145 @@
|
||||
From 5a9447fd17668c34449052e4f77eebc7a98eccf3 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 6 May 2023 14:11:08 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Lunzn Fastrhino R68S
|
||||
|
||||
It's similar to Fastrhino R66S with the following changes:
|
||||
+ 2/4GB LPDDR4 RAM
|
||||
+ 2x 1000 Base-T (native, RTL8211f)
|
||||
+ ADC button
|
||||
+ 16GB eMMC on-board
|
||||
- No SD card slot
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230506061108.17658-3-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-fastrhino-r68s.dts | 112 +++++++++++++++++++++
|
||||
2 files changed, 113 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -57,5 +57,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
|
||||
@@ -0,0 +1,112 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+#include "rk3568-fastrhino-r66s.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Lunzn FastRhino R68S";
|
||||
+ compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
+ mmc0 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ adc-keys {
|
||||
+ compatible = "adc-keys";
|
||||
+ io-channels = <&saradc 0>;
|
||||
+ io-channel-names = "buttons";
|
||||
+ keyup-threshold-microvolt = <1800000>;
|
||||
+
|
||||
+ button-recovery {
|
||||
+ label = "Recovery";
|
||||
+ linux,code = <KEY_VENDOR>;
|
||||
+ press-threshold-microvolt = <1750>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gmac0 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy0>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac0_miim
|
||||
+ &gmac0_tx_bus2
|
||||
+ &gmac0_rx_bus2
|
||||
+ &gmac0_rgmii_clk
|
||||
+ &gmac0_rgmii_bus>;
|
||||
+ snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 15ms, 50ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 15000 50000>;
|
||||
+ tx_delay = <0x3c>;
|
||||
+ rx_delay = <0x2f>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus>;
|
||||
+ snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 15ms, 50ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 15000 50000>;
|
||||
+ tx_delay = <0x4f>;
|
||||
+ rx_delay = <0x26>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ rgmii_phy0: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-0 = <ð_phy0_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-0 = <ð_phy1_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac0 {
|
||||
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gmac1 {
|
||||
+ eth_phy1_reset_pin: eth-phy1-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,37 @@
|
||||
From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Thu, 11 May 2023 00:18:50 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c
|
||||
|
||||
The reset pin was wrongly assigned due to a copy/paste error,
|
||||
fix it to match actual gpio pin.
|
||||
|
||||
While at it, remove a blank line from nanopi r5s dts.
|
||||
|
||||
Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C")
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +-
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 -
|
||||
2 files changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
@@ -106,7 +106,7 @@
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
@@ -134,4 +134,3 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
-
|
||||
@ -0,0 +1,63 @@
|
||||
From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 13 May 2023 21:53:07 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus
|
||||
|
||||
The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
|
||||
eMMC flash (8G) included.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 33 ++++++++++++++++++++++
|
||||
2 files changed, 34 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
|
||||
@@ -0,0 +1,33 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-nanopi-r2c.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C Plus";
|
||||
+ compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc1 = &emmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ bus-width = <8>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ max-frequency = <150000000>;
|
||||
+ mmc-ddr-1_8v;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
+ vmmc-supply = <&vcc_io_33>;
|
||||
+ vqmmc-supply = <&vcc18_emmc>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,232 @@
|
||||
From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:38:20 +0200
|
||||
Subject: [PATCH] rockchip: use system LED for OpenWrt
|
||||
|
||||
Use the SYS LED on the casing for showing system status.
|
||||
|
||||
This patch is kept separate from the NanoPi R2S support patch, as i plan
|
||||
on submitting the device support upstream.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -16,6 +16,11 @@
|
||||
aliases {
|
||||
ethernet1 = &rtl8153;
|
||||
mmc0 = &sdmmc;
|
||||
+
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -49,18 +54,18 @@
|
||||
|
||||
lan_led: led-0 {
|
||||
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:green:lan";
|
||||
+ label = "green:lan";
|
||||
};
|
||||
|
||||
sys_led: led-1 {
|
||||
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:red:sys";
|
||||
+ label = "red:sys";
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
wan_led: led-2 {
|
||||
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:green:wan";
|
||||
+ label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -17,6 +17,11 @@
|
||||
aliases {
|
||||
ethernet1 = &rtl8153;
|
||||
mmc0 = &sdmmc;
|
||||
+
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -36,22 +41,18 @@
|
||||
pinctrl-names = "default";
|
||||
|
||||
led-0 {
|
||||
- function = LED_FUNCTION_LAN;
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:lan";
|
||||
};
|
||||
|
||||
- led-1 {
|
||||
- function = LED_FUNCTION_STATUS;
|
||||
- color = <LED_COLOR_ID_RED>;
|
||||
+ sys_led: led-1 {
|
||||
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
- linux,default-trigger = "heartbeat";
|
||||
+ label = "red:sys";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
- function = LED_FUNCTION_WAN;
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -13,6 +13,11 @@
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
mmc1 = &emmc;
|
||||
+
|
||||
+ led-boot = &power_led;
|
||||
+ led-failsafe = &power_led;
|
||||
+ led-running = &power_led;
|
||||
+ led-upgrade = &power_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -93,9 +98,7 @@
|
||||
|
||||
power_led: led-0 {
|
||||
label = "firefly:blue:power";
|
||||
- linux,default-trigger = "heartbeat";
|
||||
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
|
||||
- default-state = "on";
|
||||
};
|
||||
|
||||
user_led: led-1 {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -19,6 +19,13 @@
|
||||
model = "FriendlyElec NanoPi R4S";
|
||||
compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
|
||||
|
||||
+ aliases {
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
+ };
|
||||
+
|
||||
/delete-node/ display-subsystem;
|
||||
|
||||
gpio-leds {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
@@ -9,6 +9,13 @@
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
+ aliases {
|
||||
+ led-boot = &status_led;
|
||||
+ led-failsafe = &status_led;
|
||||
+ led-running = &status_led;
|
||||
+ led-upgrade = &status_led;
|
||||
+ };
|
||||
+
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
@@ -32,27 +32,22 @@
|
||||
pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
|
||||
|
||||
led-lan {
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
- function = LED_FUNCTION_LAN;
|
||||
+ label = "green:lan";
|
||||
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_led: led-power {
|
||||
- color = <LED_COLOR_ID_RED>;
|
||||
- function = LED_FUNCTION_POWER;
|
||||
- linux,default-trigger = "heartbeat";
|
||||
+ label = "red:power";
|
||||
gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-wan {
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
- function = LED_FUNCTION_WAN;
|
||||
+ label = "green:wan";
|
||||
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-wlan {
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
- function = LED_FUNCTION_WLAN;
|
||||
+ label = "green:wlan";
|
||||
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
@@ -23,29 +23,22 @@
|
||||
pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
|
||||
|
||||
led-lan1 {
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
- function = LED_FUNCTION_LAN;
|
||||
- function-enumerator = <1>;
|
||||
+ label = "green:lan1";
|
||||
gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-lan2 {
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
- function = LED_FUNCTION_LAN;
|
||||
- function-enumerator = <2>;
|
||||
+ label = "green:lan2";
|
||||
gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_led: led-power {
|
||||
- color = <LED_COLOR_ID_RED>;
|
||||
- function = LED_FUNCTION_POWER;
|
||||
- linux,default-trigger = "heartbeat";
|
||||
+ label = "red:power";
|
||||
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-wan {
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
- function = LED_FUNCTION_WAN;
|
||||
+ label = "green:wan";
|
||||
gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
@@ -18,6 +18,11 @@
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
+
|
||||
+ led-boot = &power_led;
|
||||
+ led-failsafe = &power_led;
|
||||
+ led-running = &power_led;
|
||||
+ led-upgrade = &power_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
@ -0,0 +1,88 @@
|
||||
From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 26 Jul 2020 13:32:59 +0200
|
||||
Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
|
||||
|
||||
This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
|
||||
NanoPi R2S. Add the correct value for the RTL8153 LED configuration
|
||||
register to match the blink behavior of the other port on the device.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
@@ -38,3 +38,7 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&rtl8153 {
|
||||
+ realtek,led-data = <0x78>;
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -401,9 +401,11 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Second port is for USB 3.0 */
|
||||
- rtl8153: device@2 {
|
||||
- compatible = "usbbda,8153";
|
||||
+ rtl8153: usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -359,9 +359,11 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Second port is for USB 3.0 */
|
||||
- rtl8153: device@2 {
|
||||
- compatible = "usbbda,8153";
|
||||
+ rtl8153: usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -38,3 +38,7 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&rtl8153 {
|
||||
+ realtek,led-data = <0x78>;
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -83,6 +83,19 @@
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ pcie@0 {
|
||||
+ reg = <0x00000000 0 0 0 0>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ pcie-eth@0,0 {
|
||||
+ compatible = "pci10ec,8168";
|
||||
+ reg = <0x000000 0 0 0 0>;
|
||||
+
|
||||
+ realtek,led-data = <0x870>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
@ -0,0 +1,36 @@
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
|
||||
|
||||
The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
|
||||
while U-Boot requires the card to be in 3.3V mode.
|
||||
|
||||
Remove UHS support from the SD controller so the card remains in 3.3V
|
||||
mode. This reduces transfer speeds but ensures a reboot whether from
|
||||
userspace or following a kernel panic is always working.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -333,7 +333,6 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
- sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -132,6 +132,11 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+&sdmmc {
|
||||
+ /delete-property/ sd-uhs-sdr104;
|
||||
+ cap-sd-highspeed;
|
||||
+};
|
||||
+
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vdd_5v>;
|
||||
};
|
||||
@ -0,0 +1,35 @@
|
||||
From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Wed, 20 Feb 2019 07:38:34 +0000
|
||||
Subject: [PATCH] mmc: core: set initial signal voltage on power off
|
||||
|
||||
Some boards have SD card connectors where the power rail cannot be switched
|
||||
off by the driver. If the card has not been power cycled, it may still be
|
||||
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
|
||||
will fail to boot from a UHS card that continue to use 1.8V signaling.
|
||||
|
||||
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
|
||||
|
||||
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
|
||||
same issue have been seen on some Rockchip RK3399 boards.
|
||||
|
||||
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
|
||||
this change fix a re-boot issue on my boards and does not break emmc/sdio.
|
||||
Is this an acceptable workaround? Any advice is appreciated.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/mmc/core/core.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/mmc/core/core.c
|
||||
+++ b/drivers/mmc/core/core.c
|
||||
@@ -1364,6 +1364,8 @@ void mmc_power_off(struct mmc_host *host
|
||||
|
||||
mmc_pwrseq_power_off(host);
|
||||
|
||||
+ mmc_set_initial_signal_voltage(host);
|
||||
+
|
||||
host->ios.clock = 0;
|
||||
host->ios.vdd = 0;
|
||||
|
||||
@ -0,0 +1,22 @@
|
||||
From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001
|
||||
From: QiuSimons <45143996+QiuSimons@users.noreply.github.com>
|
||||
Date: Tue, 4 Aug 2020 20:17:53 +0800
|
||||
Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++
|
||||
1 files changed, 4 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -173,6 +173,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
@ -0,0 +1,59 @@
|
||||
--- a/drivers/net/ethernet/realtek/r8169_main.c
|
||||
+++ b/drivers/net/ethernet/realtek/r8169_main.c
|
||||
@@ -21,6 +21,7 @@
|
||||
#include <linux/in.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/ip.h>
|
||||
+#include <linux/of.h>
|
||||
#include <linux/tcp.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
@@ -183,6 +184,7 @@ enum rtl_registers {
|
||||
MAR0 = 8, /* Multicast filter. */
|
||||
CounterAddrLow = 0x10,
|
||||
CounterAddrHigh = 0x14,
|
||||
+ CustomLED = 0x18,
|
||||
TxDescStartAddrLow = 0x20,
|
||||
TxDescStartAddrHigh = 0x24,
|
||||
TxHDescStartAddrLow = 0x28,
|
||||
@@ -2140,6 +2142,22 @@ void r8169_apply_firmware(struct rtl8169
|
||||
}
|
||||
}
|
||||
|
||||
+static int rtl8169_led_configuration(struct rtl8169_private *tp)
|
||||
+{
|
||||
+ u32 led_data;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = of_property_read_u32(tp->pci_dev->dev.of_node,
|
||||
+ "realtek,led-data", &led_data);
|
||||
+
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ RTL_W16(tp, CustomLED, led_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
|
||||
{
|
||||
/* Adjust EEE LED frequency */
|
||||
@@ -3243,6 +3261,8 @@ static void rtl_hw_start_8168h_1(struct
|
||||
r8168_mac_ocp_write(tp, 0xc094, 0x0000);
|
||||
r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
|
||||
|
||||
+ rtl8169_led_configuration(tp);
|
||||
+
|
||||
rtl_hw_aspm_clkreq_enable(tp, true);
|
||||
}
|
||||
|
||||
@@ -3695,6 +3715,8 @@ static void rtl_hw_start_8125b(struct rt
|
||||
rtl_ephy_init(tp, e_info_8125b);
|
||||
rtl_hw_start_8125_common(tp);
|
||||
|
||||
+ rtl8169_led_configuration(tp);
|
||||
+
|
||||
rtl_hw_aspm_clkreq_enable(tp, true);
|
||||
}
|
||||
|
||||
@ -0,0 +1,16 @@
|
||||
--- a/drivers/net/phy/motorcomm.c
|
||||
+++ b/drivers/net/phy/motorcomm.c
|
||||
@@ -1487,6 +1487,13 @@ static int yt8521_config_init(struct phy
|
||||
if (ret < 0)
|
||||
goto err_restore_page;
|
||||
}
|
||||
+
|
||||
+ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
|
||||
+ ytphy_write_ext(phydev, 0xa00b, 0xe004);
|
||||
+ ytphy_write_ext(phydev, 0xa00c, 0);
|
||||
+ ytphy_write_ext(phydev, 0xa00d, 0x2600);
|
||||
+ ytphy_write_ext(phydev, 0xa00e, 0x0070);
|
||||
+ ytphy_write_ext(phydev, 0xa00f, 0x000a);
|
||||
err_restore_page:
|
||||
return phy_restore_page(phydev, old_page, ret);
|
||||
}
|
||||
@ -0,0 +1,33 @@
|
||||
--- a/drivers/net/ethernet/realtek/r8169_main.c
|
||||
+++ b/drivers/net/ethernet/realtek/r8169_main.c
|
||||
@@ -2142,6 +2142,22 @@ void r8169_apply_firmware(struct rtl8169
|
||||
}
|
||||
}
|
||||
|
||||
+static int rtl8169_devname_configuration(struct rtl8169_private *tp)
|
||||
+{
|
||||
+ const char *devname;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = of_property_read_string(tp->pci_dev->dev.of_node,
|
||||
+ "label", &devname);
|
||||
+
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ strlcpy(tp->dev->name, devname, IFNAMSIZ);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rtl8169_led_configuration(struct rtl8169_private *tp)
|
||||
{
|
||||
u32 led_data;
|
||||
@@ -3715,6 +3731,7 @@ static void rtl_hw_start_8125b(struct rt
|
||||
rtl_ephy_init(tp, e_info_8125b);
|
||||
rtl_hw_start_8125_common(tp);
|
||||
|
||||
+ rtl8169_devname_configuration(tp);
|
||||
rtl8169_led_configuration(tp);
|
||||
|
||||
rtl_hw_aspm_clkreq_enable(tp, true);
|
||||
@ -0,0 +1,92 @@
|
||||
From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001
|
||||
From: Kever Yang <kever.yang@rock-chips.com>
|
||||
Date: Mon, 11 Jul 2022 20:35:52 +0800
|
||||
Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init
|
||||
|
||||
This fw fix some RX issue:
|
||||
1. connect detect error;
|
||||
2. transfer error in ssd huge data write(more than 10GB).
|
||||
|
||||
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
||||
Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
|
||||
---
|
||||
drivers/phy/phy-rockchip-snps-pcie3.c | 36 +-
|
||||
drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++
|
||||
2 files changed, 8225 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -20,6 +20,7 @@
|
||||
|
||||
/* Register for RK3568 */
|
||||
#define GRF_PCIE30PHY_CON1 0x4
|
||||
+#define GRF_PCIE30PHY_CON4 0x10
|
||||
#define GRF_PCIE30PHY_CON6 0x18
|
||||
#define GRF_PCIE30PHY_CON9 0x24
|
||||
#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
|
||||
@@ -63,6 +64,10 @@ struct rockchip_p3phy_ops {
|
||||
int (*phy_init)(struct rockchip_p3phy_priv *priv);
|
||||
};
|
||||
|
||||
+static u16 phy_fw[] = {
|
||||
+ #include "p3phy.fw"
|
||||
+};
|
||||
+
|
||||
static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
@@ -87,13 +92,14 @@ static int rockchip_p3phy_rk3568_init(st
|
||||
{
|
||||
struct phy *phy = priv->phy;
|
||||
bool bifurcation = false;
|
||||
+ int i;
|
||||
int ret;
|
||||
u32 reg;
|
||||
|
||||
/* Deassert PCIe PMA output clamp mode */
|
||||
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
|
||||
|
||||
- for (int i = 0; i < priv->num_lanes; i++) {
|
||||
+ for (i = 0; i < priv->num_lanes; i++) {
|
||||
dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
|
||||
if (priv->lanes[i] > 1)
|
||||
bifurcation = true;
|
||||
@@ -112,16 +118,35 @@ static int rockchip_p3phy_rk3568_init(st
|
||||
GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
|
||||
}
|
||||
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
|
||||
+ (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
|
||||
+ (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
|
||||
+
|
||||
reset_control_deassert(priv->p30phy);
|
||||
|
||||
ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
GRF_PCIE30PHY_STATUS0,
|
||||
reg, SRAM_INIT_DONE(reg),
|
||||
0, 500);
|
||||
- if (ret)
|
||||
+ if (ret) {
|
||||
dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
|
||||
__func__, reg);
|
||||
- return ret;
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
|
||||
+ (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
|
||||
+ for (i = 0; i < 8192; i++)
|
||||
+ writel(phy_fw[i], priv->mmio + (i<<2));
|
||||
+
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
|
||||
+ (0x0 << 8) | (0x3 << (8 + 16)));
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
|
||||
+ (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
|
||||
+
|
||||
+ dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static const struct rockchip_p3phy_ops rk3568_ops = {
|
||||
@ -0,0 +1,105 @@
|
||||
From a9d1129997cf016b24a33a822659abd13b686323 Mon Sep 17 00:00:00 2001
|
||||
From: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
Date: Wed, 2 Dec 2020 17:30:47 +0800
|
||||
Subject: [PATCH] irqchip/gic-v3-its: add GFP_DMA32 flag for memory allocated
|
||||
for ITS in rk356x
|
||||
|
||||
Change-Id: Ic1d866733b348b86bbfdf2df4c0416a68eb422b7
|
||||
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
---
|
||||
drivers/irqchip/irq-gic-v3-its.c | 28 ++++++++++++++++++++++++----
|
||||
1 file changed, 24 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -2172,6 +2172,8 @@ static struct page *its_allocate_prop_ta
|
||||
{
|
||||
struct page *prop_page;
|
||||
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ gfp_flags |= GFP_DMA32;
|
||||
prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
|
||||
if (!prop_page)
|
||||
return NULL;
|
||||
@@ -2295,6 +2297,7 @@ static int its_setup_baser(struct its_no
|
||||
u32 alloc_pages, psz;
|
||||
struct page *page;
|
||||
void *base;
|
||||
+ gfp_t gfp_flags;
|
||||
|
||||
psz = baser->psz;
|
||||
alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
|
||||
@@ -2306,7 +2309,10 @@ static int its_setup_baser(struct its_no
|
||||
order = get_order(GITS_BASER_PAGES_MAX * psz);
|
||||
}
|
||||
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
|
||||
+ gfp_flags = GFP_KERNEL | __GFP_ZERO;
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ gfp_flags |= GFP_DMA32;
|
||||
+ page = alloc_pages_node(its->numa_node, gfp_flags, order);
|
||||
if (!page)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -2935,6 +2941,8 @@ static struct page *its_allocate_pending
|
||||
{
|
||||
struct page *pend_page;
|
||||
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ gfp_flags |= GFP_DMA32;
|
||||
pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
|
||||
get_order(LPI_PENDBASE_SZ));
|
||||
if (!pend_page)
|
||||
@@ -3278,7 +3286,11 @@ static bool its_alloc_table_entry(struct
|
||||
|
||||
/* Allocate memory for 2nd level table */
|
||||
if (!table[idx]) {
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
|
||||
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
|
||||
+
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ gfp_flags |= GFP_DMA32;
|
||||
+ page = alloc_pages_node(its->numa_node, gfp_flags,
|
||||
get_order(baser->psz));
|
||||
if (!page)
|
||||
return false;
|
||||
@@ -3367,6 +3379,7 @@ static struct its_device *its_create_dev
|
||||
int nr_lpis;
|
||||
int nr_ites;
|
||||
int sz;
|
||||
+ gfp_t gfp_flags;
|
||||
|
||||
if (!its_alloc_device_table(its, dev_id))
|
||||
return NULL;
|
||||
@@ -3382,7 +3395,10 @@ static struct its_device *its_create_dev
|
||||
nr_ites = max(2, nvecs);
|
||||
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
|
||||
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
|
||||
- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
|
||||
+ gfp_flags = GFP_KERNEL;
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ gfp_flags |= GFP_DMA32;
|
||||
+ itt = kzalloc_node(sz, gfp_flags, its->numa_node);
|
||||
if (alloc_lpis) {
|
||||
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
|
||||
if (lpi_map)
|
||||
@@ -4974,6 +4990,7 @@ static int __init its_probe_one(struct r
|
||||
u64 baser, tmp, typer;
|
||||
struct page *page;
|
||||
int err;
|
||||
+ gfp_t gfp_flags;
|
||||
|
||||
its_base = ioremap(res->start, SZ_64K);
|
||||
if (!its_base) {
|
||||
@@ -5042,7 +5059,10 @@ static int __init its_probe_one(struct r
|
||||
|
||||
its->numa_node = numa_node;
|
||||
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
|
||||
+ gfp_flags = GFP_KERNEL | __GFP_ZERO;
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ gfp_flags |= GFP_DMA32;
|
||||
+ page = alloc_pages_node(its->numa_node, gfp_flags,
|
||||
get_order(ITS_CMD_QUEUE_SZ));
|
||||
if (!page) {
|
||||
err = -ENOMEM;
|
||||
@ -0,0 +1,58 @@
|
||||
From 44cbfbc637028698b73628a2a635b5466eb341d5 Mon Sep 17 00:00:00 2001
|
||||
From: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
Date: Wed, 2 Dec 2020 18:03:43 +0800
|
||||
Subject: [PATCH] irqchip/gic-v3-its: force to config its tables as
|
||||
no-inner-cache in rk356x
|
||||
|
||||
Change-Id: Idebfe94622cbb8169f4d464a3152c7828683c72c
|
||||
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
---
|
||||
drivers/irqchip/irq-gic-v3-its.c | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -2359,6 +2359,10 @@ retry_baser:
|
||||
its_write_baser(its, baser, val);
|
||||
tmp = baser->val;
|
||||
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
|
||||
+
|
||||
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
|
||||
/*
|
||||
* Shareability didn't stick. Just use
|
||||
@@ -3100,6 +3104,10 @@ static void its_cpu_init_lpis(void)
|
||||
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
|
||||
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
|
||||
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
|
||||
+
|
||||
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
|
||||
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
|
||||
/*
|
||||
@@ -3124,6 +3132,10 @@ static void its_cpu_init_lpis(void)
|
||||
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
|
||||
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
|
||||
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
|
||||
+
|
||||
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
|
||||
/*
|
||||
* The HW reports non-shareable, we must remove the
|
||||
@@ -5093,6 +5105,10 @@ static int __init its_probe_one(struct r
|
||||
gits_write_cbaser(baser, its->base + GITS_CBASER);
|
||||
tmp = gits_read_cbaser(its->base + GITS_CBASER);
|
||||
|
||||
+ if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
|
||||
+
|
||||
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
|
||||
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
|
||||
/*
|
||||
@ -0,0 +1,28 @@
|
||||
From bc0263dea7e284d67e4bbe97db3f226d353f4d39 Mon Sep 17 00:00:00 2001
|
||||
From: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
Date: Mon, 11 Jan 2021 19:51:18 +0800
|
||||
Subject: [PATCH] irqchip/gic-v3-its: flush base table if rk356x
|
||||
|
||||
Change-Id: Ia2b0dd3d47742c43939eb99d3f8adac8e1107603
|
||||
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
|
||||
---
|
||||
drivers/irqchip/irq-gic-v3-its.c | 8 ++++++--
|
||||
1 file changed, 6 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -2360,8 +2360,12 @@ retry_baser:
|
||||
tmp = baser->val;
|
||||
|
||||
if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
- of_machine_is_compatible("rockchip,rk3566"))
|
||||
- tmp &= ~GITS_BASER_SHAREABILITY_MASK;
|
||||
+ of_machine_is_compatible("rockchip,rk3566")) {
|
||||
+ if (tmp & GITS_BASER_SHAREABILITY_MASK)
|
||||
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
|
||||
+ else
|
||||
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
|
||||
+ }
|
||||
|
||||
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
|
||||
/*
|
||||
@ -0,0 +1,54 @@
|
||||
From 0b985f29304dcb9d644174edacb67298e8049d4f Mon Sep 17 00:00:00 2001
|
||||
From: Kever Yang <kever.yang@rock-chips.com>
|
||||
Date: Thu, 18 Mar 2021 20:15:23 +0800
|
||||
Subject: [PATCH] irqchip/gic-v3-its: force to config its tables as
|
||||
no-inner-cache in rk3588
|
||||
|
||||
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
||||
Change-Id: I7275cbf011061f11968505a7570230d2d789e9fc
|
||||
---
|
||||
drivers/irqchip/irq-gic-v3-its.c | 24 ++++++++++++++++--------
|
||||
1 file changed, 16 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -2360,7 +2360,8 @@ retry_baser:
|
||||
tmp = baser->val;
|
||||
|
||||
if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
- of_machine_is_compatible("rockchip,rk3566")) {
|
||||
+ of_machine_is_compatible("rockchip,rk3566") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3588")) {
|
||||
if (tmp & GITS_BASER_SHAREABILITY_MASK)
|
||||
tmp &= ~GITS_BASER_SHAREABILITY_MASK;
|
||||
else
|
||||
@@ -3109,7 +3110,8 @@ static void its_cpu_init_lpis(void)
|
||||
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
|
||||
|
||||
if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
- of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ of_machine_is_compatible("rockchip,rk3566") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3588"))
|
||||
tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
|
||||
|
||||
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
|
||||
@@ -3137,7 +3139,8 @@ static void its_cpu_init_lpis(void)
|
||||
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
|
||||
|
||||
if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
- of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ of_machine_is_compatible("rockchip,rk3566") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3588"))
|
||||
tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
|
||||
|
||||
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
|
||||
@@ -5110,7 +5113,8 @@ static int __init its_probe_one(struct r
|
||||
tmp = gits_read_cbaser(its->base + GITS_CBASER);
|
||||
|
||||
if (of_machine_is_compatible("rockchip,rk3568") ||
|
||||
- of_machine_is_compatible("rockchip,rk3566"))
|
||||
+ of_machine_is_compatible("rockchip,rk3566") ||
|
||||
+ of_machine_is_compatible("rockchip,rk3588"))
|
||||
tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
|
||||
|
||||
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
|
||||
@ -0,0 +1,56 @@
|
||||
From: Andrew Powers-Holmes <aholmes@omnom.net>
|
||||
To: linux-rockchip@lists.infradead.org
|
||||
Cc: "Ondřej Jirman" <megi@xff.cz>, "Rob Herring" <robh+dt@kernel.org>,
|
||||
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
|
||||
"Heiko Stuebner" <heiko@sntech.de>,
|
||||
"Peter Geis" <pgwipeout@gmail.com>,
|
||||
"Frank Wunderlich" <frank-w@public-files.de>,
|
||||
"Michael Riesch" <michael.riesch@wolfvision.net>,
|
||||
"Yifeng Zhao" <yifeng.zhao@rock-chips.com>,
|
||||
"Sascha Hauer" <s.hauer@pengutronix.de>,
|
||||
"Nicolas Frattaroli" <frattaroli.nicolas@gmail.com>,
|
||||
"Chris Morgan" <macromorgan@hotmail.com>,
|
||||
"Ezequiel Garcia" <ezequiel@vanguardiasur.com.ar>,
|
||||
"Robin Murphy" <robin.murphy@arm.com>,
|
||||
"Mark Kettenis" <mark.kettenis@xs4all.nl>,
|
||||
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
|
||||
linux-kernel@vger.kernel.org
|
||||
Subject: [PATCH 1/1] arm64: dts: rockchip: rk356x: Fix PCIe register and range mappings
|
||||
Date: Sat, 12 Nov 2022 22:41:26 +1100 [thread overview]
|
||||
Message-ID: <20221112114125.1637543-2-aholmes@omnom.net> (raw)
|
||||
In-Reply-To: <20221112114125.1637543-1-aholmes@omnom.net>
|
||||
|
||||
The register and range mappings for the PCIe controller in Rockchip's
|
||||
RK356x SoCs are incorrect. Replace them with corrected values from the
|
||||
vendor BSP sources, updated to match current DT schema.
|
||||
|
||||
Tested-by: Ondrej Jirman <megi@xff.cz>
|
||||
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
|
||||
2 files changed, 12 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -855,7 +855,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
reg = <0x3 0xc0000000 0x0 0x00400000>,
|
||||
<0x0 0xfe260000 0x0 0x00010000>,
|
||||
- <0x3 0x3f000000 0x0 0x01000000>;
|
||||
+ <0x0 0xf4000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@@ -884,8 +884,9 @@
|
||||
phys = <&combphy2 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
|
||||
- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
|
||||
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
|
||||
+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
|
||||
resets = <&cru SRST_PCIE20_POWERUP>;
|
||||
reset-names = "pipe";
|
||||
#address-cells = <3>;
|
||||
@ -0,0 +1,77 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -64,7 +64,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- bus-range = <0x0 0xf>;
|
||||
+ bus-range = <0x10 0x1f>;
|
||||
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||
<&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||
@@ -87,7 +87,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
- msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
+ msi-map = <0x1000 &its 0x1000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
@@ -116,7 +116,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- bus-range = <0x0 0xf>;
|
||||
+ bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
<&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
@@ -139,7 +139,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
- msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
+ msi-map = <0x2000 &its 0x2000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -315,14 +315,21 @@
|
||||
|
||||
gic: interrupt-controller@fd400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+ interrupt-controller;
|
||||
+
|
||||
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
||||
- <0x0 0xfd460000 0 0x80000>; /* GICR */
|
||||
+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-controller;
|
||||
- #interrupt-cells = <3>;
|
||||
- mbi-alias = <0x0 0xfd410000>;
|
||||
- mbi-ranges = <296 24>;
|
||||
- msi-controller;
|
||||
+ its: interrupt-controller@fd440000 {
|
||||
+ compatible = "arm,gic-v3-its";
|
||||
+ msi-controller;
|
||||
+ #msi-cells = <1>;
|
||||
+ reg = <0x0 0xfd440000 0x0 0x20000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fd800000 {
|
||||
@@ -879,7 +886,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <2>;
|
||||
- msi-map = <0x0 &gic 0x0 0x1000>;
|
||||
+ msi-map = <0x0 &its 0x0 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy2 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
@ -0,0 +1,46 @@
|
||||
From 1f1992c51a3f44352253204a11fc34738b739d20 Mon Sep 17 00:00:00 2001
|
||||
From: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
Date: Fri, 24 Aug 2018 09:15:03 +0800
|
||||
Subject: [PATCH] hwrng: rockchip - add support for Rockchip HW RNG
|
||||
|
||||
Change-Id: Ia14bd624716eb6531ef8674843ccfbada3197d8e
|
||||
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
---
|
||||
drivers/char/hw_random/Kconfig | 12 ++
|
||||
drivers/char/hw_random/Makefile | 1 +
|
||||
drivers/char/hw_random/rockchip-rng.c | 214 ++++++++++++++++++++++++++
|
||||
3 files changed, 227 insertions(+)
|
||||
create mode 100644 drivers/char/hw_random/rockchip-rng.c
|
||||
|
||||
--- a/drivers/char/hw_random/Kconfig
|
||||
+++ b/drivers/char/hw_random/Kconfig
|
||||
@@ -385,6 +385,19 @@ config HW_RANDOM_STM32
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
+config HW_RANDOM_ROCKCHIP
|
||||
+ tristate "Rockchip Random Number Generator support"
|
||||
+ depends on ARCH_ROCKCHIP
|
||||
+ default HW_RANDOM
|
||||
+ help
|
||||
+ This driver provides kernel-side support for the Random Number
|
||||
+ Generator hardware found on Rockchip cpus.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the
|
||||
+ module will be called rockchip-rng.
|
||||
+
|
||||
+ If unsure, say Y.
|
||||
+
|
||||
config HW_RANDOM_PIC32
|
||||
tristate "Microchip PIC32 Random Number Generator support"
|
||||
depends on HW_RANDOM && MACH_PIC32
|
||||
--- a/drivers/char/hw_random/Makefile
|
||||
+++ b/drivers/char/hw_random/Makefile
|
||||
@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
|
||||
obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
|
||||
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
|
||||
@ -0,0 +1,31 @@
|
||||
From 2677d71222197dfab25876b013718a14a19c86c1 Mon Sep 17 00:00:00 2001
|
||||
From: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
Date: Tue, 15 Oct 2019 10:12:29 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3328: add rng node
|
||||
|
||||
Change-Id: Ic443f0e08ac427654008a2225eb9a8565b20fda5
|
||||
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 11 +++++++++++
|
||||
1 file changed, 11 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -279,6 +279,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ rng: rng@ff060000 {
|
||||
+ compatible = "rockchip,cryptov1-rng";
|
||||
+ reg = <0x0 0xff060000 0x0 0x4000>;
|
||||
+
|
||||
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
grf: syscon@ff100000 {
|
||||
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff100000 0x0 0x1000>;
|
||||
@ -0,0 +1,32 @@
|
||||
From 2b80fe5ba53f83c568072a7cdd7478d0b2b7c0fc Mon Sep 17 00:00:00 2001
|
||||
From: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
Date: Sat, 12 Oct 2019 14:57:42 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rng node for rk3399
|
||||
|
||||
use rng of crypto1
|
||||
|
||||
Change-Id: Ic8cd339d43012a356d981284726ac4d8158a2316
|
||||
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1937,6 +1937,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ rng: rng@ff8b8000 {
|
||||
+ compatible = "rockchip,cryptov1-rng";
|
||||
+ reg = <0x0 0xff8b8000 0x0 0x1000>;
|
||||
+ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||
+ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
gpu: gpu@ff9a0000 {
|
||||
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
|
||||
reg = <0x0 0xff9a0000 0x0 0x10000>;
|
||||
@ -0,0 +1,30 @@
|
||||
From 7d56fae4afef7a73e4973c491e324c7fde60203c Mon Sep 17 00:00:00 2001
|
||||
From: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
Date: Mon, 30 Nov 2020 19:26:29 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3568: add rng node
|
||||
|
||||
Change-Id: I2654c935554ef278c5805bbc4b5c712a65834925
|
||||
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -211,6 +211,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ rng: rng@fe388000 {
|
||||
+ compatible = "rockchip,cryptov2-rng";
|
||||
+ reg = <0x0 0xfe388000 0x0 0x2000>;
|
||||
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
||||
+ clock-names = "clk_trng", "hclk_trng";
|
||||
+ resets = <&cru SRST_TRNG_NS>;
|
||||
+ reset-names = "reset";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
combphy0: phy@fe820000 {
|
||||
compatible = "rockchip,rk3568-naneng-combphy";
|
||||
reg = <0x0 0xfe820000 0x0 0x100>;
|
||||
@ -0,0 +1,39 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
|
||||
@@ -608,6 +608,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&rng {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&saradc {
|
||||
vref-supply = <&vcca1v8_s3>;
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
@@ -425,6 +425,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&rng {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
@@ -486,6 +486,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&rng {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
@ -0,0 +1,211 @@
|
||||
From 764e893ee82321938fc6f4349e9e7caf06a04410 Mon Sep 17 00:00:00 2001
|
||||
From: Tang Yun ping <typ@rock-chips.com>
|
||||
Date: Thu, 4 May 2017 20:49:58 +0800
|
||||
Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2
|
||||
APIs
|
||||
|
||||
1. Add support setting ddr clock via SIP Version 2 APIs
|
||||
2. RK3288 using SIP Vision 2.
|
||||
|
||||
Change-Id: I935e43b1885a96650dc86e3eb6d79de6795062a9
|
||||
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/clk/rockchip/clk-ddr.c | 159 ++++++++++++++++++++++++++++++
|
||||
drivers/clk/rockchip/clk-rk3288.c | 2 +-
|
||||
drivers/clk/rockchip/clk.h | 1 +
|
||||
3 files changed, 161 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-ddr.c
|
||||
+++ b/drivers/clk/rockchip/clk-ddr.c
|
||||
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr
|
||||
.get_parent = rockchip_ddrclk_get_parent,
|
||||
};
|
||||
|
||||
+/* See v4.4/include/dt-bindings/display/rk_fb.h */
|
||||
+#define SCREEN_NULL 0
|
||||
+#define SCREEN_HDMI 6
|
||||
+
|
||||
+static inline int rk_drm_get_lcdc_type(void)
|
||||
+{
|
||||
+ return SCREEN_NULL;
|
||||
+}
|
||||
+
|
||||
+struct share_params {
|
||||
+ u32 hz;
|
||||
+ u32 lcdc_type;
|
||||
+ u32 vop;
|
||||
+ u32 vop_dclk_mode;
|
||||
+ u32 sr_idle_en;
|
||||
+ u32 addr_mcu_el3;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag1;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag0;
|
||||
+ u32 complt_hwirq;
|
||||
+ /* if need, add parameter after */
|
||||
+};
|
||||
+
|
||||
+struct rockchip_ddrclk_data {
|
||||
+ u32 inited_flag;
|
||||
+ void __iomem *share_memory;
|
||||
+};
|
||||
+
|
||||
+static struct rockchip_ddrclk_data ddr_data;
|
||||
+
|
||||
+static void rockchip_ddrclk_data_init(void)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
+ 1, SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if (!res.a0) {
|
||||
+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
|
||||
+ ddr_data.inited_flag = 1;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long drate,
|
||||
+ unsigned long prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = drate;
|
||||
+ p->lcdc_type = rk_drm_get_lcdc_type();
|
||||
+ p->wait_flag1 = 1;
|
||||
+ p->wait_flag0 = 1;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if ((int)res.a1 == -6) {
|
||||
+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
|
||||
+ /* TODO: rockchip_dmcfreq_wait_complete(); */
|
||||
+ }
|
||||
+
|
||||
+ return res.a0;
|
||||
+}
|
||||
+
|
||||
+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
|
||||
+ (struct clk_hw *hw, unsigned long parent_rate)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long rate,
|
||||
+ unsigned long *prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = rate;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
|
||||
+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
|
||||
+ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
|
||||
+ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
|
||||
+ .get_parent = rockchip_ddrclk_get_parent,
|
||||
+};
|
||||
+
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
u8 num_parents, int mux_offset,
|
||||
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk
|
||||
case ROCKCHIP_DDRCLK_SIP:
|
||||
init.ops = &rockchip_ddrclk_sip_ops;
|
||||
break;
|
||||
+ case ROCKCHIP_DDRCLK_SIP_V2:
|
||||
+ init.ops = &rockchip_ddrclk_sip_ops_v2;
|
||||
+ break;
|
||||
default:
|
||||
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
|
||||
kfree(ddrclk);
|
||||
--- a/drivers/clk/rockchip/clk-rk3328.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3328.c
|
||||
@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328
|
||||
RK3328_CLKGATE_CON(14), 1, GFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
- RK3328_CLKGATE_CON(0), 4, GFLAGS),
|
||||
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
|
||||
+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
|
||||
+ ROCKCHIP_DDRCLK_SIP_V2),
|
||||
+
|
||||
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 6, GFLAGS),
|
||||
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -399,7 +399,8 @@ struct clk *rockchip_clk_register_mmc(co
|
||||
* DDRCLK flags, including method of setting the rate
|
||||
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
|
||||
*/
|
||||
-#define ROCKCHIP_DDRCLK_SIP BIT(0)
|
||||
+#define ROCKCHIP_DDRCLK_SIP 0x01
|
||||
+#define ROCKCHIP_DDRCLK_SIP_V2 0x03
|
||||
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
--- a/include/soc/rockchip/rockchip_sip.h
|
||||
+++ b/include/soc/rockchip/rockchip_sip.h
|
||||
@@ -16,5 +16,16 @@
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
|
||||
+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
|
||||
+
|
||||
+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009
|
||||
+
|
||||
+/* Share mem page types */
|
||||
+typedef enum {
|
||||
+ SHARE_PAGE_TYPE_INVALID = 0,
|
||||
+ SHARE_PAGE_TYPE_UARTDBG,
|
||||
+ SHARE_PAGE_TYPE_DDR,
|
||||
+ SHARE_PAGE_TYPE_MAX,
|
||||
+} share_page_type_t;
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,44 @@
|
||||
From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 13:53:25 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/devfreq/Kconfig | 18 +-
|
||||
drivers/devfreq/Makefile | 1 +
|
||||
drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 862 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/devfreq/rk3328_dmc.c
|
||||
|
||||
--- a/drivers/devfreq/Kconfig
|
||||
+++ b/drivers/devfreq/Kconfig
|
||||
@@ -120,6 +120,18 @@ config ARM_TEGRA_DEVFREQ
|
||||
It reads ACTMON counters of memory controllers and adjusts the
|
||||
operating frequencies and voltages with OPP support.
|
||||
|
||||
+config ARM_RK3328_DMC_DEVFREQ
|
||||
+ tristate "ARM RK3328 DMC DEVFREQ Driver"
|
||||
+ depends on ARCH_ROCKCHIP
|
||||
+ select DEVFREQ_EVENT_ROCKCHIP_DFI
|
||||
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
|
||||
+ select PM_DEVFREQ_EVENT
|
||||
+ select PM_OPP
|
||||
+ help
|
||||
+ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).
|
||||
+ It sets the frequency for the memory controller and reads the usage counts
|
||||
+ from hardware.
|
||||
+
|
||||
config ARM_RK3399_DMC_DEVFREQ
|
||||
tristate "ARM RK3399 DMC DEVFREQ Driver"
|
||||
depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
|
||||
--- a/drivers/devfreq/Makefile
|
||||
+++ b/drivers/devfreq/Makefile
|
||||
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) +=
|
||||
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
|
||||
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
|
||||
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
|
||||
+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o
|
||||
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
|
||||
|
||||
# DEVFREQ Event Drivers
|
||||
@ -0,0 +1,26 @@
|
||||
From d85e70122d0357ce714aace7ad23d9ae40dce587 Mon Sep 17 00:00:00 2001
|
||||
From: Jianqun Xu <jay.xu@rock-chips.com>
|
||||
Date: Fri, 19 Aug 2016 15:44:14 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: disable irqs during accessing ddr
|
||||
monitor
|
||||
|
||||
Change-Id: Ie4817a77fcb1283f37f41ab097f02ed7dc9cd18c
|
||||
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -151,8 +151,11 @@ static int rockchip_dfi_get_event(struct
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int busier_ch;
|
||||
+ unsigned long flags;
|
||||
|
||||
+ local_irq_save(flags);
|
||||
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
|
||||
edata->load_count = info->ch_usage[busier_ch].access;
|
||||
edata->total_count = info->ch_usage[busier_ch].total;
|
||||
@ -0,0 +1,242 @@
|
||||
From b495cbf3597ca0799c35c8bb4a12b8e70b911820 Mon Sep 17 00:00:00 2001
|
||||
From: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Date: Mon, 27 Mar 2017 11:09:51 +0800
|
||||
Subject: [PATCH] PM / devfreq: event: add support for rk3368 dfi
|
||||
|
||||
This adds the necessary data for handling dfi on the rk3368.
|
||||
Access the dfi via registers provided by GRF (general register
|
||||
files) module.
|
||||
|
||||
Change-Id: I96c2b4dcd34d90731b749ebdbe6922f01559d8e6
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
---
|
||||
.../bindings/devfreq/event/rockchip-dfi.txt | 11 +-
|
||||
drivers/devfreq/event/rockchip-dfi.c | 157 ++++++++++++++++--
|
||||
2 files changed, 148 insertions(+), 20 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
@@ -1,8 +1,15 @@
|
||||
|
||||
-* Rockchip rk3399 DFI device
|
||||
+* Rockchip DFI device
|
||||
|
||||
Required properties:
|
||||
-- compatible: Must be "rockchip,rk3399-dfi".
|
||||
+- compatible: Should be one of the following.
|
||||
+ - "rockchip,rk3368-dfi" - for RK3368 SoCs.
|
||||
+ - "rockchip,rk3399-dfi" - for RK3399 SoCs.
|
||||
+
|
||||
+Required properties for RK3368:
|
||||
+- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
+
|
||||
+Required properties for RK3399:
|
||||
- reg: physical base address of each DFI and length of memory mapped region
|
||||
- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
|
||||
- clocks: phandles for clock specified in "clock-names" property
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -20,6 +20,15 @@
|
||||
|
||||
#include <soc/rockchip/rk3399_grf.h>
|
||||
|
||||
+#define RK3368_GRF_DDRC0_CON0 0x600
|
||||
+#define RK3368_GRF_SOC_STATUS5 0x494
|
||||
+#define RK3368_GRF_SOC_STATUS6 0x498
|
||||
+#define RK3368_GRF_SOC_STATUS8 0x4a0
|
||||
+#define RK3368_GRF_SOC_STATUS9 0x4a4
|
||||
+#define RK3368_GRF_SOC_STATUS10 0x4a8
|
||||
+#define RK3368_DFI_EN (0x30003 << 5)
|
||||
+#define RK3368_DFI_DIS (0x30000 << 5)
|
||||
+
|
||||
#define RK3399_DMC_NUM_CH 2
|
||||
|
||||
/* DDRMON_CTRL */
|
||||
@@ -54,9 +63,77 @@ struct rockchip_dfi {
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct regmap *regmap_pmu;
|
||||
+ struct regmap *regmap_grf;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3368_dfi_ops = {
|
||||
+ .disable = rk3368_dfi_disable,
|
||||
+ .enable = rk3368_dfi_enable,
|
||||
+ .get_event = rk3368_dfi_get_event,
|
||||
+ .set_event = rk3368_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
@@ -170,23 +247,31 @@ static const struct devfreq_event_ops ro
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
-static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
- { .compatible = "rockchip,rk3399-dfi" },
|
||||
- { },
|
||||
-};
|
||||
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||
+static __init int rk3368_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
|
||||
-static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+ if (!dev->parent || !dev->parent->of_node)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+
|
||||
+ desc->ops = &rk3368_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rockchip_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
- struct rockchip_dfi *data;
|
||||
- struct devfreq_event_desc *desc;
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
|
||||
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
- if (!data)
|
||||
- return -ENOMEM;
|
||||
-
|
||||
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(data->regs))
|
||||
return PTR_ERR(data->regs);
|
||||
@@ -205,23 +290,59 @@ static int rockchip_dfi_probe(struct pla
|
||||
if (IS_ERR(data->regmap_pmu))
|
||||
return PTR_ERR(data->regmap_pmu);
|
||||
}
|
||||
- data->dev = dev;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
+ { },
|
||||
+};
|
||||
+
|
||||
+static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_dfi *data;
|
||||
+ struct devfreq_event_desc *desc;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ const struct of_device_id *match;
|
||||
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc);
|
||||
+
|
||||
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
+ if (!data)
|
||||
+ return -ENOMEM;
|
||||
|
||||
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
- desc->ops = &rockchip_dfi_ops;
|
||||
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
|
||||
+ if (match) {
|
||||
+ init = match->data;
|
||||
+ if (init) {
|
||||
+ if (init(pdev, data, desc))
|
||||
+ return -EINVAL;
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
desc->driver_data = data;
|
||||
desc->name = np->name;
|
||||
- data->desc = desc;
|
||||
|
||||
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
|
||||
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
|
||||
if (IS_ERR(data->edev)) {
|
||||
- dev_err(&pdev->dev,
|
||||
- "failed to add devfreq-event device\n");
|
||||
+ dev_err(dev, "failed to add devfreq-event device\n");
|
||||
return PTR_ERR(data->edev);
|
||||
}
|
||||
+ data->desc = desc;
|
||||
+ data->dev = &pdev->dev;
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
@ -0,0 +1,229 @@
|
||||
From 0519cdf40c8cd04663e2eba614d57f11f002b88f Mon Sep 17 00:00:00 2001
|
||||
From: Tang Yun ping <typ@rock-chips.com>
|
||||
Date: Wed, 12 Apr 2017 16:24:16 +0800
|
||||
Subject: [PATCH] PM / devfreq: event: add support for rk3288 dfi
|
||||
|
||||
This adds the necessary data for handling dfi on the rk3288.
|
||||
Access the dfi via registers provided by GRF (general register
|
||||
files) module.
|
||||
|
||||
Change-Id: Ic7241af3c20a269ab362055dea04d260e01c50de
|
||||
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
|
||||
---
|
||||
.../bindings/devfreq/event/rockchip-dfi.txt | 1 +
|
||||
drivers/devfreq/event/rockchip-dfi.c | 158 +++++++++++++++++-
|
||||
2 files changed, 150 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
@@ -3,6 +3,7 @@
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following.
|
||||
+ - "rockchip,rk3288-dfi" - for RK3288 SoCs.
|
||||
- "rockchip,rk3368-dfi" - for RK3368 SoCs.
|
||||
- "rockchip,rk3399-dfi" - for RK3399 SoCs.
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -20,6 +20,15 @@
|
||||
|
||||
#include <soc/rockchip/rk3399_grf.h>
|
||||
|
||||
+#define RK3288_PMU_SYS_REG2 0x9c
|
||||
+#define RK3288_GRF_SOC_CON4 0x254
|
||||
+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
|
||||
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
+#define RK3288_DFI_EN (0x30003 << 14)
|
||||
+#define RK3288_DFI_DIS (0x30000 << 14)
|
||||
+#define RK3288_LPDDR_SEL (0x10001 << 13)
|
||||
+#define RK3288_DDR3_SEL (0x10000 << 13)
|
||||
+
|
||||
#define RK3368_GRF_DDRC0_CON0 0x600
|
||||
#define RK3368_GRF_SOC_STATUS5 0x494
|
||||
#define RK3368_GRF_SOC_STATUS6 0x498
|
||||
@@ -29,23 +38,30 @@
|
||||
#define RK3368_DFI_EN (0x30003 << 5)
|
||||
#define RK3368_DFI_DIS (0x30000 << 5)
|
||||
|
||||
-#define RK3399_DMC_NUM_CH 2
|
||||
+#define RK3399_DMC_NUM_CH 2
|
||||
|
||||
/* DDRMON_CTRL */
|
||||
-#define DDRMON_CTRL 0x04
|
||||
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||
-#define LPDDR4_EN (0x10001 << 4)
|
||||
-#define HARDWARE_EN (0x10001 << 3)
|
||||
-#define LPDDR3_EN (0x10001 << 2)
|
||||
-#define SOFTWARE_EN (0x10001 << 1)
|
||||
-#define SOFTWARE_DIS (0x10000 << 1)
|
||||
-#define TIME_CNT_EN (0x10001 << 0)
|
||||
+#define DDRMON_CTRL 0x04
|
||||
+#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||
+#define LPDDR4_EN (0x10001 << 4)
|
||||
+#define HARDWARE_EN (0x10001 << 3)
|
||||
+#define LPDDR3_EN (0x10001 << 2)
|
||||
+#define SOFTWARE_EN (0x10001 << 1)
|
||||
+#define SOFTWARE_DIS (0x10000 << 1)
|
||||
+#define TIME_CNT_EN (0x10001 << 0)
|
||||
|
||||
#define DDRMON_CH0_COUNT_NUM 0x28
|
||||
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
|
||||
#define DDRMON_CH1_COUNT_NUM 0x3c
|
||||
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
|
||||
|
||||
+enum {
|
||||
+ DDR3 = 3,
|
||||
+ LPDDR3 = 6,
|
||||
+ LPDDR4 = 7,
|
||||
+ UNUSED = 0xFF
|
||||
+};
|
||||
+
|
||||
struct dmc_usage {
|
||||
u32 access;
|
||||
u32 total;
|
||||
@@ -67,6 +83,93 @@ struct rockchip_dfi {
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ u32 tmp, max = 0;
|
||||
+ u32 i, busier_ch = 0;
|
||||
+ u32 rd_count, wr_count, total_count;
|
||||
+
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ /* Find out which channel is busier */
|
||||
+ for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
|
||||
+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
|
||||
+ info->ch_usage[i].total = total_count;
|
||||
+ tmp = info->ch_usage[i].access;
|
||||
+ if (tmp > max) {
|
||||
+ busier_ch = i;
|
||||
+ max = tmp;
|
||||
+ }
|
||||
+ }
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return busier_ch;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ int busier_ch;
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+ busier_ch = rk3288_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ edata->load_count = info->ch_usage[busier_ch].access;
|
||||
+ edata->total_count = info->ch_usage[busier_ch].total;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3288_dfi_ops = {
|
||||
+ .disable = rk3288_dfi_disable,
|
||||
+ .enable = rk3288_dfi_enable,
|
||||
+ .get_event = rk3288_dfi_get_event,
|
||||
+ .set_event = rk3288_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
@@ -247,6 +350,42 @@ static const struct devfreq_event_ops ro
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
+static __init int rk3288_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 dram_type;
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmu = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmu))
|
||||
+ return PTR_ERR(data->regmap_pmu);
|
||||
+ }
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &dram_type);
|
||||
+ dram_type = READ_DRAMTYPE_INFO(dram_type);
|
||||
+
|
||||
+ if (dram_type == DDR3)
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_DDR3_SEL);
|
||||
+ else
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_LPDDR_SEL);
|
||||
+
|
||||
+ desc->ops = &rk3288_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static __init int rk3368_dfi_init(struct platform_device *pdev,
|
||||
struct rockchip_dfi *data,
|
||||
struct devfreq_event_desc *desc)
|
||||
@@ -297,6 +436,7 @@ static __init int rockchip_dfi_init(stru
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
{ },
|
||||
@ -0,0 +1,152 @@
|
||||
From 7d494650c32b81e22b0268b1209118ea11253a97 Mon Sep 17 00:00:00 2001
|
||||
From: Liang Chen <cl@rock-chips.com>
|
||||
Date: Tue, 5 Sep 2017 15:32:02 +0800
|
||||
Subject: [PATCH] PM / devfreq: event: add support for rk3128 dfi
|
||||
|
||||
This adds the necessary data for handling dfi on the rk3128.
|
||||
Access the dfi via registers provided by GRF (general register
|
||||
files) module.
|
||||
|
||||
Change-Id: Ife9e9987224088434e878102b7d1c3b132e761ad
|
||||
Signed-off-by: Liang Chen <cl@rock-chips.com>
|
||||
---
|
||||
.../bindings/devfreq/event/rockchip-dfi.txt | 1 +
|
||||
drivers/devfreq/event/rockchip-dfi.c | 96 +++++++++++++++++++
|
||||
2 files changed, 97 insertions(+)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
@@ -3,6 +3,7 @@
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following.
|
||||
+ - "rockchip,rk3128-dfi" - for RK3128 SoCs.
|
||||
- "rockchip,rk3288-dfi" - for RK3288 SoCs.
|
||||
- "rockchip,rk3368-dfi" - for RK3368 SoCs.
|
||||
- "rockchip,rk3399-dfi" - for RK3399 SoCs.
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -20,6 +20,14 @@
|
||||
|
||||
#include <soc/rockchip/rk3399_grf.h>
|
||||
|
||||
+#define RK3128_GRF_SOC_CON0 0x140
|
||||
+#define RK3128_GRF_OS_REG1 0x1cc
|
||||
+#define RK3128_GRF_DFI_WRNUM 0x220
|
||||
+#define RK3128_GRF_DFI_RDNUM 0x224
|
||||
+#define RK3128_GRF_DFI_TIMERVAL 0x22c
|
||||
+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
|
||||
+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
|
||||
+
|
||||
#define RK3288_PMU_SYS_REG2 0x9c
|
||||
#define RK3288_GRF_SOC_CON4 0x254
|
||||
#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
|
||||
@@ -83,6 +91,75 @@ struct rockchip_dfi {
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_DISB);
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi_wr, dfi_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi_wr + dfi_rd) * 4;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3128_dfi_ops = {
|
||||
+ .disable = rk3128_dfi_disable,
|
||||
+ .enable = rk3128_dfi_enable,
|
||||
+ .get_event = rk3128_dfi_get_event,
|
||||
+ .set_event = rk3128_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
@@ -350,6 +427,24 @@ static const struct devfreq_event_ops ro
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
+static __init int rk3128_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ desc->ops = &rk3128_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static __init int rk3288_dfi_init(struct platform_device *pdev,
|
||||
struct rockchip_dfi *data,
|
||||
struct devfreq_event_desc *desc)
|
||||
@@ -436,6 +531,7 @@ static __init int rockchip_dfi_init(stru
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||
{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
@ -0,0 +1,184 @@
|
||||
From 0873229b2495f356d84a0182e50c5ea27ae46816 Mon Sep 17 00:00:00 2001
|
||||
From: CanYang He <hcy@rock-chips.com>
|
||||
Date: Sat, 23 Dec 2017 14:51:38 +0800
|
||||
Subject: [PATCH] PM / devfreq: event: make dfi more extension
|
||||
|
||||
after modify, rockchip_dfi_ops can apply to other platform use such
|
||||
version ddr monitor. regardless of channel count, only one channel
|
||||
of rk3288,rk3399,rk3328 can work. and regardless of monitor clk,
|
||||
some platform like rk3328 monitor clk is always on.
|
||||
|
||||
Change-Id: Ia1c02a89116546ded385c5a6a3e36d020d66b7f3
|
||||
Signed-off-by: CanYang He <hcy@rock-chips.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 63 ++++++++++++++++++----------
|
||||
1 file changed, 40 insertions(+), 23 deletions(-)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -31,7 +31,6 @@
|
||||
#define RK3288_PMU_SYS_REG2 0x9c
|
||||
#define RK3288_GRF_SOC_CON4 0x254
|
||||
#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
|
||||
-#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
#define RK3288_DFI_EN (0x30003 << 14)
|
||||
#define RK3288_DFI_DIS (0x30000 << 14)
|
||||
#define RK3288_LPDDR_SEL (0x10001 << 13)
|
||||
@@ -46,7 +45,9 @@
|
||||
#define RK3368_DFI_EN (0x30003 << 5)
|
||||
#define RK3368_DFI_DIS (0x30000 << 5)
|
||||
|
||||
-#define RK3399_DMC_NUM_CH 2
|
||||
+#define MAX_DMC_NUM_CH 2
|
||||
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||
|
||||
/* DDRMON_CTRL */
|
||||
#define DDRMON_CTRL 0x04
|
||||
@@ -63,6 +64,9 @@
|
||||
#define DDRMON_CH1_COUNT_NUM 0x3c
|
||||
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
|
||||
|
||||
+/* pmu grf */
|
||||
+#define PMUGRF_OS_REG2 0x308
|
||||
+
|
||||
enum {
|
||||
DDR3 = 3,
|
||||
LPDDR3 = 6,
|
||||
@@ -83,12 +87,18 @@ struct dmc_usage {
|
||||
struct rockchip_dfi {
|
||||
struct devfreq_event_dev *edev;
|
||||
struct devfreq_event_desc *desc;
|
||||
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
|
||||
+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct regmap *regmap_pmu;
|
||||
struct regmap *regmap_grf;
|
||||
struct clk *clk;
|
||||
+ u32 dram_type;
|
||||
+ /*
|
||||
+ * available mask, 1: available, 0: not available
|
||||
+ * each bit represent a channel
|
||||
+ */
|
||||
+ u32 ch_msk;
|
||||
};
|
||||
|
||||
static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
@@ -203,7 +213,9 @@ static int rk3288_dfi_get_busier_ch(stru
|
||||
rk3288_dfi_stop_hardware_counter(edev);
|
||||
|
||||
/* Find out which channel is busier */
|
||||
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
regmap_read(info->regmap_grf,
|
||||
RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
|
||||
regmap_read(info->regmap_grf,
|
||||
@@ -318,21 +330,14 @@ static void rockchip_dfi_start_hardware_
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
- u32 val;
|
||||
- u32 ddr_type;
|
||||
-
|
||||
- /* get ddr type */
|
||||
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
|
||||
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
|
||||
- RK3399_PMUGRF_DDRTYPE_MASK;
|
||||
|
||||
/* clear DDRMON_CTRL setting */
|
||||
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* set ddr type to dfi */
|
||||
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
|
||||
+ if (info->dram_type == LPDDR3)
|
||||
writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
|
||||
+ else if (info->dram_type == LPDDR4)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* enable count, use software mode */
|
||||
@@ -357,7 +362,9 @@ static int rockchip_dfi_get_busier_ch(st
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
|
||||
/* Find out which channel is busier */
|
||||
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
info->ch_usage[i].access = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
@@ -378,7 +385,8 @@ static int rockchip_dfi_disable(struct d
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
- clk_disable_unprepare(info->clk);
|
||||
+ if (info->clk)
|
||||
+ clk_disable_unprepare(info->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -388,10 +396,13 @@ static int rockchip_dfi_enable(struct de
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int ret;
|
||||
|
||||
- ret = clk_prepare_enable(info->clk);
|
||||
- if (ret) {
|
||||
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
|
||||
- return ret;
|
||||
+ if (info->clk) {
|
||||
+ ret = clk_prepare_enable(info->clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
|
||||
+ ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
|
||||
rockchip_dfi_start_hardware_counter(edev);
|
||||
@@ -450,7 +461,7 @@ static __init int rk3288_dfi_init(struct
|
||||
struct devfreq_event_desc *desc)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
- u32 dram_type;
|
||||
+ u32 val;
|
||||
|
||||
node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||
if (node) {
|
||||
@@ -466,10 +477,11 @@ static __init int rk3288_dfi_init(struct
|
||||
return PTR_ERR(data->regmap_grf);
|
||||
}
|
||||
|
||||
- regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &dram_type);
|
||||
- dram_type = READ_DRAMTYPE_INFO(dram_type);
|
||||
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
|
||||
- if (dram_type == DDR3)
|
||||
+ if (data->dram_type == DDR3)
|
||||
regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
RK3288_DDR3_SEL);
|
||||
else
|
||||
@@ -505,6 +517,7 @@ static __init int rockchip_dfi_init(stru
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 val;
|
||||
|
||||
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(data->regs))
|
||||
@@ -525,6 +538,10 @@ static __init int rockchip_dfi_init(stru
|
||||
return PTR_ERR(data->regmap_pmu);
|
||||
}
|
||||
|
||||
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
+
|
||||
desc->ops = &rockchip_dfi_ops;
|
||||
|
||||
return 0;
|
||||
@ -0,0 +1,106 @@
|
||||
From 8d4209ee0613dfea700bcfc2ecb6052dc9dc9956 Mon Sep 17 00:00:00 2001
|
||||
From: CanYang He <hcy@rock-chips.com>
|
||||
Date: Tue, 26 Dec 2017 10:19:46 +0800
|
||||
Subject: [PATCH] PM / devfreq: event: add support for rk3328 dfi
|
||||
|
||||
This adds the necessary data for handling dfi on the rk3328.
|
||||
|
||||
Change-Id: Id870f78dad3ddd6cb5771674a4e8905322f9e8ef
|
||||
Signed-off-by: CanYang He <hcy@rock-chips.com>
|
||||
---
|
||||
.../bindings/devfreq/event/rockchip-dfi.txt | 1 +
|
||||
drivers/devfreq/event/rockchip-dfi.c | 40 ++++++++++++++++++-
|
||||
2 files changed, 39 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
@@ -5,6 +5,7 @@ Required properties:
|
||||
- compatible: Should be one of the following.
|
||||
- "rockchip,rk3128-dfi" - for RK3128 SoCs.
|
||||
- "rockchip,rk3288-dfi" - for RK3288 SoCs.
|
||||
+ - "rockchip,rk3328-dfi" - for RK3328 SoCs.
|
||||
- "rockchip,rk3368-dfi" - for RK3368 SoCs.
|
||||
- "rockchip,rk3399-dfi" - for RK3399 SoCs.
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -36,6 +36,8 @@
|
||||
#define RK3288_LPDDR_SEL (0x10001 << 13)
|
||||
#define RK3288_DDR3_SEL (0x10000 << 13)
|
||||
|
||||
+#define RK3328_GRF_OS_REG2 0x5d0
|
||||
+
|
||||
#define RK3368_GRF_DDRC0_CON0 0x600
|
||||
#define RK3368_GRF_SOC_STATUS5 0x494
|
||||
#define RK3368_GRF_SOC_STATUS6 0x498
|
||||
@@ -48,10 +50,10 @@
|
||||
#define MAX_DMC_NUM_CH 2
|
||||
#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||
-
|
||||
/* DDRMON_CTRL */
|
||||
#define DDRMON_CTRL 0x04
|
||||
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||
+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
|
||||
+#define DDR4_EN (0x10001 << 5)
|
||||
#define LPDDR4_EN (0x10001 << 4)
|
||||
#define HARDWARE_EN (0x10001 << 3)
|
||||
#define LPDDR3_EN (0x10001 << 2)
|
||||
@@ -68,6 +70,7 @@
|
||||
#define PMUGRF_OS_REG2 0x308
|
||||
|
||||
enum {
|
||||
+ DDR4 = 0,
|
||||
DDR3 = 3,
|
||||
LPDDR3 = 6,
|
||||
LPDDR4 = 7,
|
||||
@@ -339,6 +342,8 @@ static void rockchip_dfi_start_hardware_
|
||||
writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||
else if (info->dram_type == LPDDR4)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == DDR4)
|
||||
+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* enable count, use software mode */
|
||||
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
|
||||
@@ -547,9 +552,40 @@ static __init int rockchip_dfi_init(stru
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static __init int rk3328_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||
{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
{ },
|
||||
@ -0,0 +1,114 @@
|
||||
From eefc791ec8040d6cacf3e940d778b7fc82c5e99e Mon Sep 17 00:00:00 2001
|
||||
From: YouMin Chen <cym@rock-chips.com>
|
||||
Date: Mon, 5 Feb 2018 10:57:23 +0800
|
||||
Subject: [PATCH] PM / devfreq: event: add support for px30 dfi
|
||||
|
||||
Change-Id: Ib6808d961b65d993fea05ab15d648d814d14a4a2
|
||||
Signed-off-by: YouMin Chen <cym@rock-chips.com>
|
||||
---
|
||||
.../bindings/devfreq/event/rockchip-dfi.txt | 1 +
|
||||
drivers/devfreq/event/rockchip-dfi.c | 41 +++++++++++++++++--
|
||||
2 files changed, 39 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
|
||||
@@ -3,6 +3,7 @@
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following.
|
||||
+ - "rockchip,px30-dfi" - for PX30 SoCs.
|
||||
- "rockchip,rk3128-dfi" - for RK3128 SoCs.
|
||||
- "rockchip,rk3288-dfi" - for RK3288 SoCs.
|
||||
- "rockchip,rk3328-dfi" - for RK3328 SoCs.
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -20,6 +20,8 @@
|
||||
|
||||
#include <soc/rockchip/rk3399_grf.h>
|
||||
|
||||
+#define PX30_PMUGRF_OS_REG2 0x208
|
||||
+
|
||||
#define RK3128_GRF_SOC_CON0 0x140
|
||||
#define RK3128_GRF_OS_REG1 0x1cc
|
||||
#define RK3128_GRF_DFI_WRNUM 0x220
|
||||
@@ -56,7 +58,7 @@
|
||||
#define DDR4_EN (0x10001 << 5)
|
||||
#define LPDDR4_EN (0x10001 << 4)
|
||||
#define HARDWARE_EN (0x10001 << 3)
|
||||
-#define LPDDR3_EN (0x10001 << 2)
|
||||
+#define LPDDR2_3_EN (0x10001 << 2)
|
||||
#define SOFTWARE_EN (0x10001 << 1)
|
||||
#define SOFTWARE_DIS (0x10000 << 1)
|
||||
#define TIME_CNT_EN (0x10001 << 0)
|
||||
@@ -72,6 +74,7 @@
|
||||
enum {
|
||||
DDR4 = 0,
|
||||
DDR3 = 3,
|
||||
+ LPDDR2 = 5,
|
||||
LPDDR3 = 6,
|
||||
LPDDR4 = 7,
|
||||
UNUSED = 0xFF
|
||||
@@ -95,6 +98,7 @@ struct rockchip_dfi {
|
||||
void __iomem *regs;
|
||||
struct regmap *regmap_pmu;
|
||||
struct regmap *regmap_grf;
|
||||
+ struct regmap *regmap_pmugrf;
|
||||
struct clk *clk;
|
||||
u32 dram_type;
|
||||
/*
|
||||
@@ -338,8 +342,8 @@ static void rockchip_dfi_start_hardware_
|
||||
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* set ddr type to dfi */
|
||||
- if (info->dram_type == LPDDR3)
|
||||
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
|
||||
else if (info->dram_type == LPDDR4)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
else if (info->dram_type == DDR4)
|
||||
@@ -443,6 +447,36 @@ static const struct devfreq_event_ops ro
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
+static __init int px30_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmugrf))
|
||||
+ return PTR_ERR(data->regmap_pmugrf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static __init int rk3128_dfi_init(struct platform_device *pdev,
|
||||
struct rockchip_dfi *data,
|
||||
struct devfreq_event_desc *desc)
|
||||
@@ -583,6 +617,7 @@ static __init int rk3328_dfi_init(struct
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
||||
{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||
{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
@ -0,0 +1,21 @@
|
||||
From b949c38cbd8573cf1a3f9acc935324d2d5ecff94 Mon Sep 17 00:00:00 2001
|
||||
From: YouMin Chen <cym@rock-chips.com>
|
||||
Date: Tue, 21 Aug 2018 15:31:58 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: add support for rk1808 dfi
|
||||
|
||||
Change-Id: Id95eca244c666b103ce4f9676e2abbeb304196ac
|
||||
Signed-off-by: YouMin Chen <cym@rock-chips.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -618,6 +618,7 @@ static __init int rk3328_dfi_init(struct
|
||||
|
||||
static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
{ .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
|
||||
{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||
{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
@ -0,0 +1,39 @@
|
||||
From 354584ddce4f32563c41c5623f4b92f26713e3ae Mon Sep 17 00:00:00 2001
|
||||
From: YouMin Chen <cym@rock-chips.com>
|
||||
Date: Tue, 5 Mar 2019 19:38:11 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: fix lpddr4 calculation error
|
||||
|
||||
Fix lpddr4 calculation error about access.
|
||||
LPDDR4 BL(burst length) = 16,other DDR type BL(burst length) = 8.
|
||||
|
||||
Change-Id: Icc1b4f6764fa0b23ec1f7722bda8ffeff1da4ab7
|
||||
Signed-off-by: YouMin Chen <cym@rock-chips.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 14 +++++++++++---
|
||||
1 file changed, 11 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -374,11 +374,19 @@ static int rockchip_dfi_get_busier_ch(st
|
||||
for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
if (!(info->ch_msk & BIT(i)))
|
||||
continue;
|
||||
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
|
||||
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
|
||||
+
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_COUNT_NUM + i * 20);
|
||||
- tmp = info->ch_usage[i].access;
|
||||
+
|
||||
+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
|
||||
+ tmp = readl_relaxed(dfi_regs +
|
||||
+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
|
||||
+ if (info->dram_type == LPDDR4)
|
||||
+ tmp *= 8;
|
||||
+ else
|
||||
+ tmp *= 4;
|
||||
+ info->ch_usage[i].access = tmp;
|
||||
+
|
||||
if (tmp > max) {
|
||||
busier_ch = i;
|
||||
max = tmp;
|
||||
@ -0,0 +1,21 @@
|
||||
From 0369dd4ab2a13544c6f179d85bc7b7be844e6d5e Mon Sep 17 00:00:00 2001
|
||||
From: YouMin Chen <cym@rock-chips.com>
|
||||
Date: Thu, 19 Dec 2019 10:46:22 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: add support for rv1126 dfi
|
||||
|
||||
Change-Id: I65a403424b68804022025309f9af82b55c044192
|
||||
Signed-off-by: YouMin Chen <cym@rock-chips.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -632,6 +632,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
+ { .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init },
|
||||
{ },
|
||||
};
|
||||
|
||||
@ -0,0 +1,21 @@
|
||||
From e0603b1c9931b2e90f06596e3f8a9a123a66202d Mon Sep 17 00:00:00 2001
|
||||
From: YouMin Chen <cym@rock-chips.com>
|
||||
Date: Tue, 13 Oct 2020 17:32:01 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: add support for rk3568 dfi
|
||||
|
||||
Change-Id: I62d21e31cd56e82c04de675be502b261ba3740da
|
||||
Signed-off-by: YouMin Chen <cym@rock-chips.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -632,6 +632,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init },
|
||||
{ .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init },
|
||||
{ },
|
||||
};
|
||||
@ -0,0 +1,84 @@
|
||||
From a97e2d456d17e753c4540632fbc63fab825bbb6b Mon Sep 17 00:00:00 2001
|
||||
From: YouMin Chen <cym@rock-chips.com>
|
||||
Date: Tue, 29 Jun 2021 17:49:53 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: add support lpddr4x
|
||||
|
||||
Change-Id: Icd86a458dc9843e80d9206d620a1da6a71adf799
|
||||
Signed-off-by: YouMin Chen <cym@rock-chips.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 20 ++++++++++++++------
|
||||
1 file changed, 14 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -21,6 +21,7 @@
|
||||
#include <soc/rockchip/rk3399_grf.h>
|
||||
|
||||
#define PX30_PMUGRF_OS_REG2 0x208
|
||||
+#define PX30_PMUGRF_OS_REG3 0x20c
|
||||
|
||||
#define RK3128_GRF_SOC_CON0 0x140
|
||||
#define RK3128_GRF_OS_REG1 0x1cc
|
||||
@@ -52,6 +53,8 @@
|
||||
#define MAX_DMC_NUM_CH 2
|
||||
#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||
+#define READ_DRAMTYPE_INFO_V3(n, m) ((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3))
|
||||
+#define READ_SYSREG_VERSION(m) (((m) >> 28) & 0xf)
|
||||
/* DDRMON_CTRL */
|
||||
#define DDRMON_CTRL 0x04
|
||||
#define CLR_DDRMON_CTRL (0x3f0000 << 0)
|
||||
@@ -77,6 +80,7 @@ enum {
|
||||
LPDDR2 = 5,
|
||||
LPDDR3 = 6,
|
||||
LPDDR4 = 7,
|
||||
+ LPDDR4X = 8,
|
||||
UNUSED = 0xFF
|
||||
};
|
||||
|
||||
@@ -344,7 +348,7 @@ static void rockchip_dfi_start_hardware_
|
||||
/* set ddr type to dfi */
|
||||
if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||
writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
|
||||
- else if (info->dram_type == LPDDR4)
|
||||
+ else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
else if (info->dram_type == DDR4)
|
||||
writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
@@ -378,10 +382,10 @@ static int rockchip_dfi_get_busier_ch(st
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_COUNT_NUM + i * 20);
|
||||
|
||||
- /* LPDDR4 BL = 16,other DDR type BL = 8 */
|
||||
+ /* LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */
|
||||
tmp = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
|
||||
- if (info->dram_type == LPDDR4)
|
||||
+ if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
|
||||
tmp *= 8;
|
||||
else
|
||||
tmp *= 4;
|
||||
@@ -461,7 +465,7 @@ static __init int px30_dfi_init(struct p
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
struct resource *res;
|
||||
- u32 val;
|
||||
+ u32 val_2, val_3;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
@@ -475,8 +479,12 @@ static __init int px30_dfi_init(struct p
|
||||
return PTR_ERR(data->regmap_pmugrf);
|
||||
}
|
||||
|
||||
- regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
|
||||
- data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val_2);
|
||||
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG3, &val_3);
|
||||
+ if (READ_SYSREG_VERSION(val_3) >= 0x3)
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO_V3(val_2, val_3);
|
||||
+ else
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val_2);
|
||||
data->ch_msk = 1;
|
||||
data->clk = NULL;
|
||||
|
||||
@ -0,0 +1,229 @@
|
||||
From d9326406232efc48aa6ce446e5be754b2b75fcf0 Mon Sep 17 00:00:00 2001
|
||||
From: Zhihuan He <huan.he@rock-chips.com>
|
||||
Date: Wed, 1 Dec 2021 11:06:17 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: add rk3588 dfi support
|
||||
|
||||
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
|
||||
Change-Id: I0bebfd16aa4897f770f70aca70b0e9a88808446f
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 127 +++++++++++++++++++++++----
|
||||
1 file changed, 108 insertions(+), 19 deletions(-)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -23,6 +23,8 @@
|
||||
#define PX30_PMUGRF_OS_REG2 0x208
|
||||
#define PX30_PMUGRF_OS_REG3 0x20c
|
||||
|
||||
+#define RK3588_PMUGRF_OS_REG(n) (0x200 + (n) * 4)
|
||||
+
|
||||
#define RK3128_GRF_SOC_CON0 0x140
|
||||
#define RK3128_GRF_OS_REG1 0x1cc
|
||||
#define RK3128_GRF_DFI_WRNUM 0x220
|
||||
@@ -50,14 +52,18 @@
|
||||
#define RK3368_DFI_EN (0x30003 << 5)
|
||||
#define RK3368_DFI_DIS (0x30000 << 5)
|
||||
|
||||
-#define MAX_DMC_NUM_CH 2
|
||||
+#define MAX_DMC_NUM_CH 4
|
||||
#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||
#define READ_DRAMTYPE_INFO_V3(n, m) ((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3))
|
||||
#define READ_SYSREG_VERSION(m) (((m) >> 28) & 0xf)
|
||||
+#define READ_LP5_BANK_MODE(m) (((m) >> 1) & 0x3)
|
||||
+#define READ_LP5_CKR(m) (((m) >> 0) & 0x1)
|
||||
/* DDRMON_CTRL */
|
||||
#define DDRMON_CTRL 0x04
|
||||
-#define CLR_DDRMON_CTRL (0x3f0000 << 0)
|
||||
+#define CLR_DDRMON_CTRL (0xffff0000 << 0)
|
||||
+#define LPDDR5_BANK_MODE(m) ((0x30000 | ((m) & 0x3)) << 7)
|
||||
+#define LPDDR5_EN (0x10001 << 6)
|
||||
#define DDR4_EN (0x10001 << 5)
|
||||
#define LPDDR4_EN (0x10001 << 4)
|
||||
#define HARDWARE_EN (0x10001 << 3)
|
||||
@@ -81,12 +87,14 @@ enum {
|
||||
LPDDR3 = 6,
|
||||
LPDDR4 = 7,
|
||||
LPDDR4X = 8,
|
||||
+ LPDDR5 = 9,
|
||||
+ DDR5 = 10,
|
||||
UNUSED = 0xFF
|
||||
};
|
||||
|
||||
struct dmc_usage {
|
||||
- u32 access;
|
||||
- u32 total;
|
||||
+ u64 access;
|
||||
+ u64 total;
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -105,6 +113,13 @@ struct rockchip_dfi {
|
||||
struct regmap *regmap_pmugrf;
|
||||
struct clk *clk;
|
||||
u32 dram_type;
|
||||
+ u32 mon_idx;
|
||||
+ u32 count_rate;
|
||||
+ u32 dram_dynamic_info_reg;
|
||||
+ /* 0: BG mode, 1: 16 Bank mode, 2: 8 bank mode */
|
||||
+ u32 lp5_bank_mode;
|
||||
+ /* 0: clk:dqs = 1:2, 1: 1:4 */
|
||||
+ u32 lp5_ckr;
|
||||
/*
|
||||
* available mask, 1: available, 0: not available
|
||||
* each bit represent a channel
|
||||
@@ -341,28 +356,56 @@ static void rockchip_dfi_start_hardware_
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
+ u32 mon_idx = 0, val_6 = 0;
|
||||
+ u32 i;
|
||||
+
|
||||
+ if (info->mon_idx)
|
||||
+ mon_idx = info->mon_idx;
|
||||
+
|
||||
+ if (info->dram_dynamic_info_reg)
|
||||
+ regmap_read(info->regmap_pmugrf, info->dram_dynamic_info_reg, &val_6);
|
||||
+
|
||||
+ if (info->dram_type == LPDDR5) {
|
||||
+ info->lp5_bank_mode = READ_LP5_BANK_MODE(val_6);
|
||||
+ info->lp5_ckr = READ_LP5_CKR(val_6);
|
||||
+ }
|
||||
|
||||
- /* clear DDRMON_CTRL setting */
|
||||
- writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+ /* clear DDRMON_CTRL setting */
|
||||
+ writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + i * mon_idx + DDRMON_CTRL);
|
||||
|
||||
- /* set ddr type to dfi */
|
||||
- if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||
- writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
|
||||
- else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
|
||||
- writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
- else if (info->dram_type == DDR4)
|
||||
- writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ /* set ddr type to dfi */
|
||||
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
|
||||
+ writel_relaxed(LPDDR4_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == DDR4)
|
||||
+ writel_relaxed(DDR4_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == LPDDR5)
|
||||
+ writel_relaxed(LPDDR5_EN | LPDDR5_BANK_MODE(info->lp5_bank_mode),
|
||||
+ dfi_regs + i * mon_idx + DDRMON_CTRL);
|
||||
|
||||
- /* enable count, use software mode */
|
||||
- writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ /* enable count, use software mode */
|
||||
+ writel_relaxed(SOFTWARE_EN, dfi_regs + i * mon_idx + DDRMON_CTRL);
|
||||
+ }
|
||||
}
|
||||
|
||||
static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
+ u32 mon_idx = 0, i;
|
||||
+
|
||||
+ if (info->mon_idx)
|
||||
+ mon_idx = info->mon_idx;
|
||||
|
||||
- writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+ writel_relaxed(SOFTWARE_DIS, dfi_regs + i * mon_idx + DDRMON_CTRL);
|
||||
+ }
|
||||
}
|
||||
|
||||
static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
@@ -371,22 +414,31 @@ static int rockchip_dfi_get_busier_ch(st
|
||||
u32 tmp, max = 0;
|
||||
u32 i, busier_ch = 0;
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
+ u32 mon_idx = 0x20, count_rate = 1;
|
||||
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
|
||||
+ if (info->mon_idx)
|
||||
+ mon_idx = info->mon_idx;
|
||||
+ if (info->count_rate)
|
||||
+ count_rate = info->count_rate;
|
||||
+
|
||||
/* Find out which channel is busier */
|
||||
for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
if (!(info->ch_msk & BIT(i)))
|
||||
continue;
|
||||
|
||||
+ /* rk3588 counter is dfi clk rate */
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
- DDRMON_CH0_COUNT_NUM + i * 20);
|
||||
+ DDRMON_CH0_COUNT_NUM + i * mon_idx) * count_rate;
|
||||
|
||||
- /* LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */
|
||||
+ /* LPDDR5 LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */
|
||||
tmp = readl_relaxed(dfi_regs +
|
||||
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
|
||||
+ DDRMON_CH0_DFI_ACCESS_NUM + i * mon_idx);
|
||||
if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
|
||||
tmp *= 8;
|
||||
+ else if (info->dram_type == LPDDR5)
|
||||
+ tmp *= 16 / (4 << info->lp5_ckr);
|
||||
else
|
||||
tmp *= 4;
|
||||
info->ch_usage[i].access = tmp;
|
||||
@@ -459,6 +511,42 @@ static const struct devfreq_event_ops ro
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
+static __init int rk3588_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ struct resource *res;
|
||||
+ u32 val_2, val_3, val_4;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ data->regmap_pmugrf = syscon_regmap_lookup_by_phandle(np, "rockchip,pmu_grf");
|
||||
+ if (IS_ERR(data->regmap_pmugrf))
|
||||
+ return PTR_ERR(data->regmap_pmugrf);
|
||||
+
|
||||
+ regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(2), &val_2);
|
||||
+ regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(3), &val_3);
|
||||
+ regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(4), &val_4);
|
||||
+ if (READ_SYSREG_VERSION(val_3) >= 0x3)
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO_V3(val_2, val_3);
|
||||
+ else
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val_2);
|
||||
+
|
||||
+ data->mon_idx = 0x4000;
|
||||
+ data->count_rate = 2;
|
||||
+ data->dram_dynamic_info_reg = RK3588_PMUGRF_OS_REG(6);
|
||||
+ data->ch_msk = READ_CH_INFO(val_2) | READ_CH_INFO(val_4) << 2;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static __init int px30_dfi_init(struct platform_device *pdev,
|
||||
struct rockchip_dfi *data,
|
||||
struct devfreq_event_desc *desc)
|
||||
@@ -641,6 +729,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
{ .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
|
||||
{ .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init },
|
||||
{ },
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user