mediatek: bump to v4.19

2020-02-06 12:32:03 +08:00 · 2020-02-06 12:32:03 +08:00 · 021f2e001e
commit 021f2e001e
parent 0fa8e4728d
33 changed files with 759 additions and 603 deletions
--- a/target/linux/mediatek/Makefile
+++ b/target/linux/mediatek/Makefile
@ -9,7 +9,7 @@ SUBTARGETS:=mt7622 mt7623 mt7629
 FEATURES:=squashfs nand ramdisk fpu
 MAINTAINER:=John Crispin <john@phrozen.org>

-KERNEL_PATCHVER:=4.14
+KERNEL_PATCHVER:=4.19

 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \
--- a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@ -664,6 +664,17 @@
 		status = "disabled";
 	};

+	wmac: wmac@18000000 {
+		compatible = "mediatek,mt7622-wmac";
+		reg = <0 0x18000000 0 0x100000>;
+		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
+
+		mediatek,infracfg = <&infracfg>;
+		status = "disabled";
+
+		power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
+	};
+
 	ssusbsys: ssusbsys@1a000000 {
 		compatible = "mediatek,mt7622-ssusbsys",
 			     "syscon";
--- a/target/linux/mediatek/image/gen_mt7623_emmc_img.sh
+++ b/target/linux/mediatek/image/gen_mt7623_emmc_img.sh
@ -1,4 +1,4 @@
-#!/usr/bin/env bash
+#!/bin/sh

 OUTPUT_FILE=$1
 KERNEL_FILE=$2
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@ -1,4 +1,4 @@
-define Device/MTK-RFB1
+define Device/mediatek_mt7622-rfb1
  DEVICE_VENDOR := MediaTek
  DEVICE_MODEL := MTK7622 rfb1 AP
  DEVICE_DTS := mt7622-rfb1
@ -6,24 +6,26 @@ define Device/MTK-RFB1
  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb3 \
 			kmod-ata-core kmod-ata-ahci-mtk
 endef
-TARGET_DEVICES += MTK-RFB1
+TARGET_DEVICES += mediatek_mt7622-rfb1

-define Device/MTK-LYNX-RFB1
+define Device/mediatek_mt7622-lynx-rfb1
  DEVICE_VENDOR := MediaTek
  DEVICE_MODEL := MTK7622 Lynx rfb1 AP
  DEVICE_DTS := mt7622-lynx-rfb1
  DEVICE_DTS_DIR := $(DTS_DIR)/mediatek
+  SUPPORTED_DEVICES := mediatek,mt7622-rfb1
  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb3 \
 			kmod-ata-core kmod-ata-ahci-mtk
 endef
-TARGET_DEVICES += MTK-LYNX-RFB1
+TARGET_DEVICES += mediatek_mt7622-lynx-rfb1

-define Device/BPI-R64
+define Device/lemaker_bananapi-bpi-r64
  DEVICE_VENDOR := LeMaker
  DEVICE_MODEL := Banana Pi R64
  DEVICE_DTS := mt7622-bananapi-bpi-r64
  DEVICE_DTS_DIR := $(DTS_DIR)/mediatek
+  SUPPORTED_DEVICES := bananapi,bpi-r64
  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb3 \
 			kmod-ata-core kmod-ata-ahci-mtk
 endef
-TARGET_DEVICES += BPI-R64
+TARGET_DEVICES += lemaker_bananapi-bpi-r64
--- a/target/linux/mediatek/image/mt7623.mk
+++ b/target/linux/mediatek/image/mt7623.mk
@ -1,20 +1,18 @@
-define Device/7623a-unielec-u7623-02-emmc-512m
+define Device/unielec_u7623-02-emmc-512m
  DEVICE_VENDOR := UniElec
  DEVICE_MODEL := U7623-02
  DEVICE_VARIANT := eMMC/512MB RAM
-  DEVICE_DTS := mt7623a-unielec-u7623-02-emmc-512M
+  DEVICE_DTS := mt7623a-unielec-u7623-02-emmc-512m
  DEVICE_PACKAGES := mkf2fs e2fsprogs kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 kmod-mmc
-  SUPPORTED_DEVICES := unielec,u7623-02-emmc-512m
  IMAGES := sysupgrade-emmc.bin.gz
  IMAGE/sysupgrade-emmc.bin.gz := sysupgrade-emmc | gzip | append-metadata
 endef
+TARGET_DEVICES += unielec_u7623-02-emmc-512m

-TARGET_DEVICES += 7623a-unielec-u7623-02-emmc-512m
-
-define Device/7623n-bananapi-bpi-r2
+define Device/lemaker_bananapi-bpi-r2
  DEVICE_VENDOR := LeMaker
  DEVICE_MODEL := Banana Pi R2
  DEVICE_DTS := mt7623n-bananapi-bpi-r2
+  SUPPORTED_DEVICES := bananapi,bpi-r2
 endef
-
-TARGET_DEVICES += 7623n-bananapi-bpi-r2
+TARGET_DEVICES += lemaker_bananapi-bpi-r2
--- a/target/linux/mediatek/image/mt7629.mk
+++ b/target/linux/mediatek/image/mt7629.mk
@ -5,4 +5,3 @@ define Device/mediatek_mt7629-lynx-rfb
  DEVICE_PACKAGES := swconfig
 endef
 TARGET_DEVICES += mediatek_mt7629-lynx-rfb
-
--- a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network
@ -0,0 +1,29 @@
+#!/bin/sh
+
+. /lib/functions.sh
+. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
+
+mediatek_setup_interfaces()
+{
+	local board="$1"
+
+	case $board in
+	esac
+}
+
+mediatek_setup_macs()
+{
+	local board="$1"
+
+	case $board in
+	esac
+}
+
+board_config_update
+board=$(board_name)
+mediatek_setup_interfaces $board
+mediatek_setup_macs $board
+board_config_flush
+
+exit 0
--- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh
@ -0,0 +1,26 @@
+platform_do_upgrade() {
+	local board=$(board_name)
+
+	case "$board" in
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}
+
+PART_NAME=firmware
+
+platform_check_image() {
+	local board=$(board_name)
+
+	[ "$#" -gt 1 ] && return 1
+
+	case "$board" in
+	*)
+		echo "Sysupgrade is not supported on your board yet."
+		return 1
+		;;
+	esac
+
+	return 0
+}
--- a/target/linux/mediatek/mt7623/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/mt7623/base-files/etc/board.d/02_network
@ -9,12 +9,8 @@ mediatek_setup_interfaces()
 	local board="$1"

 	case $board in
-	'mediatek,mt7623a-rfb-emmc')
-		ucidef_set_interface_lan "lan0 lan1 lan2 lan3"
-		ucidef_set_interface_wan eth1
-		;;
-	'bananapi,bpi-r2'|\
-	"unielec,u7623"*)
+	bananapi,bpi-r2|\
+	unielec,u7623-02-emmc-512m)
 		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "wan"
 		;;
 	esac
@ -25,9 +21,8 @@ mediatek_setup_macs()
 	local board="$1"

 	case $board in
-	"unielec,u7623"*)
-		mac=$(cat /sys/class/net/wan/address)
-		ucidef_set_interface_macaddr "wan" $mac
+	unielec,u7623-02-emmc-512m)
+		ucidef_set_interface_macaddr "wan" "$(cat /sys/class/net/wan/address)"
 		;;
 	esac
 }
--- a/target/linux/mediatek/mt7623/base-files/lib/preinit/07_set_iface_mac
+++ b/target/linux/mediatek/mt7623/base-files/lib/preinit/07_set_iface_mac
@ -10,7 +10,7 @@ preinit_set_mac_address() {
 	. /lib/functions/system.sh

 	case $(board_name) in
-	"unielec,u7623"*)
+	unielec,u7623-02-emmc-512m)
 		if [ -b $RECOVERY_PART ]; then
 			insmod nls_cp437
 			insmod nls_iso8859-1
--- a/target/linux/mediatek/mt7623/base-files/lib/preinit/79_move_config
+++ b/target/linux/mediatek/mt7623/base-files/lib/preinit/79_move_config
--- a/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh
@ -1,7 +1,8 @@
-platform_do_upgrade() {                 
+platform_do_upgrade() {
 	local board=$(board_name)
+
 	case "$board" in
-	"unielec,u7623"*)
+	unielec,u7623-02-emmc-512m)
 		#Keep the persisten random mac address (if it exists)
 		mkdir -p /tmp/recovery
 		mount -o rw,noatime /dev/mmcblk0p1 /tmp/recovery
@ -26,29 +27,28 @@ platform_do_upgrade() {

 PART_NAME=firmware

-platform_check_image() {                                                         
-	local board=$(board_name)                                                
-	local magic="$(get_magic_long "$1")"                                     
+platform_check_image() {
+	local board=$(board_name)
+	local magic="$(get_magic_long "$1")"

-	[ "$#" -gt 1 ] && return 1                                               
+	[ "$#" -gt 1 ] && return 1

-	case "$board" in                                                       
+	case "$board" in
 	bananapi,bpi-r2|\
-	"unielec,u7623"*)
-		[ "$magic" != "27051956" ] && {   
+	unielec,u7623-02-emmc-512m)
+		[ "$magic" != "27051956" ] && {
 			echo "Invalid image type."
-			return 1                                     
-		}                                                    
-		return 0                                             
-		;;                                                   
-
-	*)                                                           
+			return 1
+		}
+		return 0
+		;;
+	*)
 		echo "Sysupgrade is not supported on your board yet."
-		return 1                                             
-		;;                                
-	esac                                      
+		return 1
+		;;
+	esac

-	return 0                                                                                         
+	return 0
 }

 platform_copy_config_emmc() {
@ -61,7 +61,7 @@ platform_copy_config_emmc() {

 platform_copy_config() {
 	case "$(board_name)" in
-	"unielec,u7623"*)
+	unielec,u7623-02-emmc-512m)
 		platform_copy_config_emmc
 		;;
 	esac
--- a/target/linux/mediatek/mt7623/config-4.19
+++ b/target/linux/mediatek/mt7623/config-4.19
@ -0,0 +1,515 @@
+# CONFIG_AIO is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_ARCH_HAS_PHYS_TO_DMA=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_MEDIATEK_CPUFREQ=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CLEANCACHE=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MT2701=y
+# CONFIG_COMMON_CLK_MT2701_AUDSYS is not set
+CONFIG_COMMON_CLK_MT2701_BDPSYS=y
+CONFIG_COMMON_CLK_MT2701_ETHSYS=y
+# CONFIG_COMMON_CLK_MT2701_G3DSYS is not set
+CONFIG_COMMON_CLK_MT2701_HIFSYS=y
+CONFIG_COMMON_CLK_MT2701_IMGSYS=y
+CONFIG_COMMON_CLK_MT2701_MMSYS=y
+CONFIG_COMMON_CLK_MT2701_VDECSYS=y
+# CONFIG_COMMON_CLK_MT7622 is not set
+# CONFIG_COMMON_CLK_MT7629 is not set
+# CONFIG_COMMON_CLK_MT7629_ETHSYS is not set
+# CONFIG_COMMON_CLK_MT7629_HIFSYS is not set
+# CONFIG_COMMON_CLK_MT8135 is not set
+# CONFIG_COMMON_CLK_MT8173 is not set
+CONFIG_COREDUMP=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+# CONFIG_CPU_THERMAL is not set
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_MEDIATEK=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_MT6589_UART0=y
+# CONFIG_DEBUG_MT8127_UART0 is not set
+# CONFIG_DEBUG_MT8135_UART3 is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_UART_8250=y
+# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
+CONFIG_DEBUG_UART_8250_SHIFT=2
+# CONFIG_DEBUG_UART_8250_WORD is not set
+CONFIG_DEBUG_UART_PHYS=0x11004000
+CONFIG_DEBUG_UART_VIRT=0xf1004000
+CONFIG_DEBUG_UNCOMPRESS=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EINT_MTK=y
+CONFIG_ELF_CORE=y
+CONFIG_EXT4_FS=y
+# CONFIG_F2FS_CHECK_FS is not set
+CONFIG_F2FS_FS=y
+# CONFIG_F2FS_FS_SECURITY is not set
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_STAT_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IIO=y
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_INITRAMFS_COMPRESSION=""
+CONFIG_INITRAMFS_ROOT_GID=1000
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_LEDS_MT6323=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MACH_MT2701 is not set
+# CONFIG_MACH_MT6589 is not set
+# CONFIG_MACH_MT6592 is not set
+CONFIG_MACH_MT7623=y
+# CONFIG_MACH_MT7629 is not set
+# CONFIG_MACH_MT8127 is not set
+# CONFIG_MACH_MT8135 is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MEDIATEK_MT6577_AUXADC=y
+CONFIG_MEDIATEK_WATCHDOG=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MT6397=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MT753X_GSW is not set
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_MT81xx_NOR=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_MTK=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTK_EFUSE=y
+# CONFIG_MTK_HSDMA is not set
+CONFIG_MTK_INFRACFG=y
+# CONFIG_MTK_IOMMU is not set
+# CONFIG_MTK_IOMMU_V1 is not set
+CONFIG_MTK_PMIC_WRAP=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_THERMAL=y
+CONFIG_MTK_TIMER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NET_VENDOR_AURORA is not set
+CONFIG_NET_VENDOR_MEDIATEK=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+# CONFIG_PCI_V3_SEMI is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_MTK_TPHY=y
+# CONFIG_PHY_MTK_XSPHY is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT2701=y
+CONFIG_PINCTRL_MT6397=y
+CONFIG_PINCTRL_MT7623=y
+# CONFIG_PINCTRL_MT7629 is not set
+CONFIG_PINCTRL_MTK=y
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REFCOUNT_FULL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MT6323=y
+# CONFIG_REGULATOR_MT6380 is not set
+# CONFIG_REGULATOR_MT6397 is not set
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_MT6397 is not set
+# CONFIG_RTC_DRV_MT7622 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SERIAL_8250_DMA is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SFP is not set
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT65XX=y
+# CONFIG_SPI_MTK_SNFI is not set
+CONFIG_SPMI=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TASKS_RCU=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
--- a/target/linux/mediatek/mt7629/target.mk
+++ b/target/linux/mediatek/mt7629/target.mk
@ -9,7 +9,6 @@ CPU_TYPE:=cortex-a7
 FEATURES:=squashfs nand ramdisk

 KERNELNAME:=Image dtbs
-KERNEL_PATCHVER:=4.19

 define Target/Description
 	Build firmware images for MediaTek mt7629 ARM based boards.
--- a/target/linux/mediatek/patches-4.14/0052-net-phy-add-FC.patch
+++ b/target/linux/mediatek/patches-4.14/0052-net-phy-add-FC.patch
@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>

 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1943,7 +1943,7 @@ static struct phy_driver genphy_driver =
+@@ -1944,7 +1944,7 @@ static struct phy_driver genphy_driver =
 	.config_init	= genphy_config_init,
 	.features	= PHY_GBIT_FEATURES | SUPPORTED_MII |
 			  SUPPORTED_AUI | SUPPORTED_FIBRE |
--- a/target/linux/mediatek/patches-4.14/0064-dts.patch
+++ b/target/linux/mediatek/patches-4.14/0064-dts.patch
@ -115,468 +115,6 @@
 
 &i2c0 {
 	pinctrl-names = "default";
--- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
- 	mt6580-evbp1.dtb \
- 	mt6589-aquaris5.dtb \
- 	mt6592-evb.dtb \
-+	mt7623a-rfb-emmc.dtb \
- 	mt7623n-rfb-nand.dtb \
- 	mt7623n-bananapi-bpi-r2.dtb \
- 	mt8127-moose.dtb \
--- /dev/null
-+++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
-@@ -0,0 +1,449 @@
-+/*
-+ * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/input/input.h>
-+#include "mt7623.dtsi"
-+#include "mt6323.dtsi"
-+
-+/ {
-+	model = "MediaTek MT7623N NAND reference board";
-+	compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
-+
-+	aliases {
-+		serial2 = &uart2;
-+	};
-+
-+	chosen {
-+		bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2";
-+
-+		stdout-path = "serial2:115200n8";
-+	};
-+
-+	memory {
-+		reg = <0 0x80000000 0 0x20000000>;
-+	};
-+
-+	cpus {
-+		cpu@0 {
-+			proc-supply = <&mt6323_vproc_reg>;
-+		};
-+
-+		cpu@1 {
-+			proc-supply = <&mt6323_vproc_reg>;
-+		};
-+
-+		cpu@2 {
-+			proc-supply = <&mt6323_vproc_reg>;
-+		};
-+
-+		cpu@3 {
-+			proc-supply = <&mt6323_vproc_reg>;
-+		};
-+	};
-+
-+	memory@80000000 {
-+		reg = <0 0x80000000 0 0x40000000>;
-+	};
-+
-+	mt7530: switch@0 {
-+		compatible = "mediatek,mt7530";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+	};
-+};
-+
-+&crypto {
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+
-+	gmac0: mac@0 {
-+		compatible = "mediatek,eth-mac";
-+		reg = <0>;
-+		phy-mode = "trgmii";
-+
-+		fixed-link {
-+			speed = <1000>;
-+			full-duplex;
-+			pause;
-+		};
-+	};
-+
-+	gmac1: mac@1 {
-+		compatible = "mediatek,eth-mac";
-+		reg = <1>;
-+		phy-mode = "rgmiii-rxid";
-+		phy-handle = <&phy5>;
-+	};
-+
-+	mdio: mdio-bus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		phy5: ethernet-phy@5 {
-+			reg = <5>;
-+			phy-mode = "rgmii-rxid";
-+		};
-+	};
-+};
-+
-+&mt7530 {
-+	compatible = "mediatek,mt7530";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	reg = <0>;
-+	pinctrl-names = "default";
-+	mediatek,mcm;
-+	resets = <&ethsys 2>;
-+	reset-names = "mcm";
-+	core-supply = <&mt6323_vpa_reg>;
-+	io-supply = <&mt6323_vemc3v3_reg>;
-+
-+	dsa,mii-bus = <&mdio>;
-+
-+	ports {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0>;
-+
-+		port@0 {
-+			reg = <0>;
-+			label = "lan0";
-+			cpu = <&cpu_port0>;
-+		};
-+
-+		port@1 {
-+			reg = <1>;
-+			label = "lan1";
-+			cpu = <&cpu_port0>;
-+		};
-+
-+		port@2 {
-+			reg = <2>;
-+			label = "lan2";
-+			cpu = <&cpu_port0>;
-+		};
-+
-+		port@3 {
-+			reg = <3>;
-+			label = "lan3";
-+			cpu = <&cpu_port0>;
-+		};
-+
-+		cpu_port0: port@6 {
-+			reg = <6>;
-+			label = "cpu";
-+			ethernet = <&gmac0>;
-+			phy-mode = "trgmii";
-+
-+			fixed-link {
-+				speed = <1000>;
-+				full-duplex;
-+			};
-+		};
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins_a>;
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins_a>;
-+	status = "okay";
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default", "state_uhs";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	pinctrl-1 = <&mmc0_pins_uhs>;
-+	status = "okay";
-+	bus-width = <8>;
-+	max-frequency = <50000000>;
-+	cap-mmc-highspeed;
-+	vmmc-supply = <&mt6323_vemc3v3_reg>;
-+	vqmmc-supply = <&mt6323_vio18_reg>;
-+	non-removable;
-+};
-+
-+&mmc1 {
-+	pinctrl-names = "default", "state_uhs";
-+	pinctrl-0 = <&mmc1_pins_default>;
-+	pinctrl-1 = <&mmc1_pins_uhs>;
-+	status = "okay";
-+	bus-width = <4>;
-+	max-frequency = <50000000>;
-+	cap-sd-highspeed;
-+	cd-gpios = <&pio 261 0>;
-+	vmmc-supply = <&mt6323_vmch_reg>;
-+	vqmmc-supply = <&mt6323_vio18_reg>;
-+};
-+
-+&pio {
-+	cir_pins_a:cir@0 {
-+		pins_cir {
-+			pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
-+			bias-disable;
-+		};
-+	};
-+
-+	i2c0_pins_a: i2c@0 {
-+		pins_i2c0 {
-+			pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
-+				 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
-+			bias-disable;
-+		};
-+	};
-+
-+	i2c1_pins_a: i2c@1 {
-+		pin_i2c1 {
-+			pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
-+				 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
-+			bias-disable;
-+		};
-+	};
-+
-+	i2s0_pins_a: i2s@0 {
-+		pin_i2s0 {
-+			pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
-+				 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
-+				 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
-+				 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
-+				 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
-+			drive-strength = <MTK_DRIVE_12mA>;
-+			bias-pull-down;
-+		};
-+	};
-+
-+	i2s1_pins_a: i2s@1 {
-+		pin_i2s1 {
-+			pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
-+				 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
-+				 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
-+				 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
-+				 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
-+			drive-strength = <MTK_DRIVE_12mA>;
-+			bias-pull-down;
-+		};
-+	};
-+
-+	mmc0_pins_default: mmc0default {
-+		pins_cmd_dat {
-+			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-+				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-+				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-+				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-+				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-+				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-+				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-+				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-+				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-+			input-enable;
-+			bias-pull-up;
-+		};
-+
-+		pins_clk {
-+			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-+			bias-pull-down;
-+		};
-+
-+		pins_rst {
-+			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-+			bias-pull-up;
-+		};
-+	};
-+
-+	mmc0_pins_uhs: mmc0 {
-+		pins_cmd_dat {
-+			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-+				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-+				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-+				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-+				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-+				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-+				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-+				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-+				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-+			input-enable;
-+			drive-strength = <MTK_DRIVE_2mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
-+		};
-+
-+		pins_clk {
-+			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-+			drive-strength = <MTK_DRIVE_2mA>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
-+		};
-+
-+		pins_rst {
-+			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-+			bias-pull-up;
-+		};
-+	};
-+
-+	mmc1_pins_default: mmc1default {
-+		pins_cmd_dat {
-+			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-+				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-+				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-+				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-+				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-+			input-enable;
-+			drive-strength = <MTK_DRIVE_4mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-+		};
-+
-+		pins_clk {
-+			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-+			bias-pull-down;
-+			drive-strength = <MTK_DRIVE_4mA>;
-+		};
-+
-+		pins_wp {
-+			pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
-+			input-enable;
-+			bias-pull-up;
-+		};
-+
-+		pins_insert {
-+			pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
-+			bias-pull-up;
-+		};
-+	};
-+
-+	mmc1_pins_uhs: mmc1 {
-+		pins_cmd_dat {
-+			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-+				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-+				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-+				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-+				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-+			input-enable;
-+			drive-strength = <MTK_DRIVE_4mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-+		};
-+
-+		pins_clk {
-+			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-+			drive-strength = <MTK_DRIVE_4mA>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
-+		};
-+	};
-+
-+	pwm_pins_a: pwm@0 {
-+		pins_pwm {
-+			pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
-+				 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
-+				 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
-+				 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
-+				 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
-+		};
-+	};
-+
-+	spi0_pins_a: spi@0 {
-+		pins_spi {
-+			pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
-+				<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
-+				<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
-+				<MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
-+			bias-disable;
-+		};
-+	};
-+
-+	uart0_pins_a: uart@0 {
-+		pins_dat {
-+			pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
-+				 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
-+		};
-+	};
-+
-+	uart1_pins_a: uart@1 {
-+		pins_dat {
-+			pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
-+				 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
-+		};
-+	};
-+};
-+
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins_a>;
-+	status = "okay";
-+};
-+
-+&pwrap {
-+	mt6323 {
-+		mt6323led: led {
-+			compatible = "mediatek,mt6323-led";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			led@0 {
-+				reg = <0>;
-+				label = "bpi-r2:isink:green";
-+				default-state = "off";
-+			};
-+
-+			led@1 {
-+				reg = <1>;
-+				label = "bpi-r2:isink:red";
-+				default-state = "off";
-+			};
-+
-+			led@2 {
-+				reg = <2>;
-+				label = "bpi-r2:isink:blue";
-+				default-state = "off";
-+			};
-+		};
-+	};
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins_a>;
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_pins_a>;
-+	status = "disabled";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins_a>;
-+	status = "disabled";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb1 {
-+	vusb33-supply = <&mt6323_vusb_reg>;
-+	status = "okay";
-+};
-+
-+&usb2 {
-+	vusb33-supply = <&mt6323_vusb_reg>;
-+	status = "okay";
-+};
-+
-+&u3phy1 {
-+	status = "okay";
-+};
-+
-+&u3phy2 {
-+	status = "okay";
-+};
-+
 --- a/arch/arm/boot/dts/mt7623.dtsi
 +++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -326,6 +326,7 @@
--- a/target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch
+++ b/target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch
@ -26,7 +26,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 
 /* MSDC_IOCON mask */
 #define MSDC_IOCON_SDR104CKS    (0x1 << 0)	/* RW */
-@@ -295,6 +298,10 @@ struct msdc_save_para {
+@@ -297,6 +300,10 @@ struct msdc_save_para {
 	u32 emmc50_cfg0;
 };
 
@ -37,7 +37,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 struct msdc_tune_para {
 	u32 iocon;
 	u32 pad_tune;
-@@ -309,6 +316,7 @@ struct msdc_delay_phase {
+@@ -311,6 +318,7 @@ struct msdc_delay_phase {
 
 struct msdc_host {
 	struct device *dev;
@ -45,7 +45,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	struct mmc_host *mmc;	/* mmc structure */
 	int cmd_rsp;
 
-@@ -350,6 +358,31 @@ struct msdc_host {
+@@ -352,6 +360,31 @@ struct msdc_host {
 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
 };
 
@ -77,7 +77,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 static void sdr_set_bits(void __iomem *reg, u32 bs)
 {
 	u32 val = readl(reg);
-@@ -509,7 +542,12 @@ static void msdc_set_timeout(struct msdc
+@@ -511,7 +544,12 @@ static void msdc_set_timeout(struct msdc
 		timeout = (ns + clk_ns - 1) / clk_ns + clks;
 		/* in 1048576 sclk cycle unit */
 		timeout = (timeout + (0x1 << 20) - 1) >> 20;
@ -91,7 +91,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 		/*DDR mode will double the clk cycles for data timeout */
 		timeout = mode >= 2 ? timeout * 2 : timeout;
 		timeout = timeout > 1 ? timeout - 1 : 0;
-@@ -548,7 +586,11 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -550,7 +588,11 @@ static void msdc_set_mclk(struct msdc_ho
 
 	flags = readl(host->base + MSDC_INTEN);
 	sdr_clr_bits(host->base + MSDC_INTEN, flags);
@ -104,7 +104,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	if (timing == MMC_TIMING_UHS_DDR50 ||
 	    timing == MMC_TIMING_MMC_DDR52 ||
 	    timing == MMC_TIMING_MMC_HS400) {
-@@ -568,8 +610,12 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -570,8 +612,12 @@ static void msdc_set_mclk(struct msdc_ho
 
 		if (timing == MMC_TIMING_MMC_HS400 &&
 		    hz >= (host->src_clk_freq >> 1)) {
@ -119,7 +119,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			sclk = host->src_clk_freq >> 1;
 			div = 0; /* div is ignore when bit18 is set */
 		}
-@@ -587,8 +633,15 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -589,8 +635,15 @@ static void msdc_set_mclk(struct msdc_ho
 			sclk = (host->src_clk_freq >> 2) / div;
 		}
 	}
@ -137,7 +137,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
 		cpu_relax();
-@@ -1617,12 +1670,17 @@ static int msdc_drv_probe(struct platfor
+@@ -1620,12 +1673,17 @@ static int msdc_drv_probe(struct platfor
 	struct mmc_host *mmc;
 	struct msdc_host *host;
 	struct resource *res;
@ -155,7 +155,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	/* Allocate MMC host for this device */
 	mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
 	if (!mmc)
-@@ -1686,11 +1744,15 @@ static int msdc_drv_probe(struct platfor
+@@ -1689,11 +1747,15 @@ static int msdc_drv_probe(struct platfor
 	msdc_of_property_parse(pdev, host);
 
 	host->dev = &pdev->dev;
@ -172,7 +172,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 
 	mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
 	/* MMC core transfer sizes tunable parameters */
-@@ -1839,12 +1901,6 @@ static const struct dev_pm_ops msdc_dev_
+@@ -1842,12 +1904,6 @@ static const struct dev_pm_ops msdc_dev_
 	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
 };
 
--- a/target/linux/mediatek/patches-4.14/0152-mmc-mediatek-make-hs400_tune_response-only-for-mt817.patch
+++ b/target/linux/mediatek/patches-4.14/0152-mmc-mediatek-make-hs400_tune_response-only-for-mt817.patch
@ -17,7 +17,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

 --- a/drivers/mmc/host/mtk-sd.c
 +++ b/drivers/mmc/host/mtk-sd.c
-@@ -300,6 +300,7 @@ struct msdc_save_para {
+@@ -302,6 +302,7 @@ struct msdc_save_para {
 
 struct mtk_mmc_compatible {
 	u8 clk_div_bits;
@ -25,7 +25,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 struct msdc_tune_para {
-@@ -360,18 +361,22 @@ struct msdc_host {
+@@ -362,18 +363,22 @@ struct msdc_host {
 
 static const struct mtk_mmc_compatible mt8135_compat = {
 	.clk_div_bits = 8,
@ -48,7 +48,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct of_device_id msdc_of_ids[] = {
-@@ -666,7 +671,8 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -668,7 +673,8 @@ static void msdc_set_mclk(struct msdc_ho
 		       host->base + PAD_CMD_TUNE);
 	}
 
@ -58,7 +58,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 		sdr_set_field(host->base + PAD_CMD_TUNE,
 			      MSDC_PAD_TUNE_CMDRRDLY,
 			      host->hs400_cmd_int_delay);
-@@ -1594,7 +1600,8 @@ static int msdc_execute_tuning(struct mm
+@@ -1597,7 +1603,8 @@ static int msdc_execute_tuning(struct mm
 	struct msdc_host *host = mmc_priv(mmc);
 	int ret;
 
--- a/target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch
+++ b/target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch
@ -23,7 +23,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 #define PAD_DS_TUNE      0x188
 #define PAD_CMD_TUNE     0x18c
 #define EMMC50_CFG0      0x208
-@@ -301,6 +302,7 @@ struct msdc_save_para {
+@@ -303,6 +304,7 @@ struct msdc_save_para {
 struct mtk_mmc_compatible {
 	u8 clk_div_bits;
 	bool hs400_tune; /* only used for MT8173 */
@ -31,7 +31,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 struct msdc_tune_para {
-@@ -362,21 +364,25 @@ struct msdc_host {
+@@ -364,21 +366,25 @@ struct msdc_host {
 static const struct mtk_mmc_compatible mt8135_compat = {
 	.clk_div_bits = 8,
 	.hs400_tune = false,
@ -57,7 +57,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct of_device_id msdc_of_ids[] = {
-@@ -581,6 +587,7 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -583,6 +589,7 @@ static void msdc_set_mclk(struct msdc_ho
 	u32 flags;
 	u32 div;
 	u32 sclk;
@ -65,7 +65,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 
 	if (!hz) {
 		dev_dbg(host->dev, "set mclk to 0\n");
-@@ -663,10 +670,10 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -665,10 +672,10 @@ static void msdc_set_mclk(struct msdc_ho
 	 */
 	if (host->sclk <= 52000000) {
 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
@ -78,7 +78,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 		writel(host->saved_tune_para.pad_cmd_tune,
 		       host->base + PAD_CMD_TUNE);
 	}
-@@ -1224,6 +1231,7 @@ static irqreturn_t msdc_irq(int irq, voi
+@@ -1226,6 +1233,7 @@ static irqreturn_t msdc_irq(int irq, voi
 static void msdc_init_hw(struct msdc_host *host)
 {
 	u32 val;
@ -86,7 +86,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 
 	/* Configure to MMC/SD mode, clock free running */
 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
-@@ -1239,7 +1247,7 @@ static void msdc_init_hw(struct msdc_hos
+@@ -1241,7 +1249,7 @@ static void msdc_init_hw(struct msdc_hos
 	val = readl(host->base + MSDC_INT);
 	writel(val, host->base + MSDC_INT);
 
@ -95,7 +95,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	writel(0, host->base + MSDC_IOCON);
 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
-@@ -1259,7 +1267,7 @@ static void msdc_init_hw(struct msdc_hos
+@@ -1261,7 +1269,7 @@ static void msdc_init_hw(struct msdc_hos
 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
 
 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
@ -104,7 +104,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	dev_dbg(host->dev, "init hardware done!");
 }
 
-@@ -1402,18 +1410,19 @@ static int msdc_tune_response(struct mmc
+@@ -1404,18 +1412,19 @@ static int msdc_tune_response(struct mmc
 	struct msdc_delay_phase internal_delay_phase;
 	u8 final_delay, final_maxlen;
 	u32 internal_delay = 0;
@ -126,7 +126,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			      MSDC_PAD_TUNE_CMDRDLY, i);
 		/*
 		 * Using the same parameters, it may sometimes pass the test,
-@@ -1437,7 +1446,7 @@ static int msdc_tune_response(struct mmc
+@@ -1439,7 +1448,7 @@ static int msdc_tune_response(struct mmc
 
 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
 	for (i = 0; i < PAD_DELAY_MAX; i++) {
@ -135,7 +135,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			      MSDC_PAD_TUNE_CMDRDLY, i);
 		/*
 		 * Using the same parameters, it may sometimes pass the test,
-@@ -1462,12 +1471,12 @@ skip_fall:
+@@ -1464,12 +1473,12 @@ skip_fall:
 		final_maxlen = final_fall_delay.maxlen;
 	if (final_maxlen == final_rise_delay.maxlen) {
 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
@ -150,7 +150,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			      final_fall_delay.final_phase);
 		final_delay = final_fall_delay.final_phase;
 	}
-@@ -1475,7 +1484,7 @@ skip_fall:
+@@ -1477,7 +1486,7 @@ skip_fall:
 		goto skip_internal;
 
 	for (i = 0; i < PAD_DELAY_MAX; i++) {
@ -159,7 +159,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			      MSDC_PAD_TUNE_CMDRRDLY, i);
 		mmc_send_tuning(mmc, opcode, &cmd_err);
 		if (!cmd_err)
-@@ -1483,7 +1492,7 @@ skip_fall:
+@@ -1485,7 +1494,7 @@ skip_fall:
 	}
 	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
 	internal_delay_phase = get_best_delay(host, internal_delay);
@ -168,7 +168,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 		      internal_delay_phase.final_phase);
 skip_internal:
 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
-@@ -1545,12 +1554,13 @@ static int msdc_tune_data(struct mmc_hos
+@@ -1548,12 +1557,13 @@ static int msdc_tune_data(struct mmc_hos
 	u32 rise_delay = 0, fall_delay = 0;
 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
 	u8 final_delay, final_maxlen;
@ -183,7 +183,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			      MSDC_PAD_TUNE_DATRRDLY, i);
 		ret = mmc_send_tuning(mmc, opcode, NULL);
 		if (!ret)
-@@ -1565,7 +1575,7 @@ static int msdc_tune_data(struct mmc_hos
+@@ -1568,7 +1578,7 @@ static int msdc_tune_data(struct mmc_hos
 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
 	for (i = 0; i < PAD_DELAY_MAX; i++) {
@ -192,7 +192,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			      MSDC_PAD_TUNE_DATRRDLY, i);
 		ret = mmc_send_tuning(mmc, opcode, NULL);
 		if (!ret)
-@@ -1578,14 +1588,14 @@ skip_fall:
+@@ -1581,14 +1591,14 @@ skip_fall:
 	if (final_maxlen == final_rise_delay.maxlen) {
 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
@ -209,7 +209,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 			      MSDC_PAD_TUNE_DATRRDLY,
 			      final_fall_delay.final_phase);
 		final_delay = final_fall_delay.final_phase;
-@@ -1599,6 +1609,7 @@ static int msdc_execute_tuning(struct mm
+@@ -1602,6 +1612,7 @@ static int msdc_execute_tuning(struct mm
 {
 	struct msdc_host *host = mmc_priv(mmc);
 	int ret;
@ -217,7 +217,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 
 	if (host->hs400_mode &&
 	    host->dev_comp->hs400_tune)
-@@ -1616,7 +1627,7 @@ static int msdc_execute_tuning(struct mm
+@@ -1619,7 +1630,7 @@ static int msdc_execute_tuning(struct mm
 	}
 
 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
@ -226,7 +226,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
 	return ret;
 }
-@@ -1857,10 +1868,12 @@ static int msdc_drv_remove(struct platfo
+@@ -1860,10 +1871,12 @@ static int msdc_drv_remove(struct platfo
 #ifdef CONFIG_PM
 static void msdc_save_reg(struct msdc_host *host)
 {
@ -240,7 +240,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
-@@ -1870,10 +1883,12 @@ static void msdc_save_reg(struct msdc_ho
+@@ -1873,10 +1886,12 @@ static void msdc_save_reg(struct msdc_ho
 
 static void msdc_restore_reg(struct msdc_host *host)
 {
--- a/target/linux/mediatek/patches-4.14/0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch
+++ b/target/linux/mediatek/patches-4.14/0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch
@ -23,9 +23,9 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 #define MSDC_PAD_TUNE    0xec
 #define MSDC_PAD_TUNE0   0xf0
 #define PAD_DS_TUNE      0x188
-@@ -216,11 +217,20 @@
- #define MSDC_PATCH_BIT_SPCPUSH    (0x1 << 29)	/* RW */
- #define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)	/* RW */
+@@ -218,11 +219,20 @@
+ 
+ #define MSDC_PATCH_BIT1_CMDTA     (0x7 << 3)    /* RW */
 
 +#define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
 +#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
@ -44,7 +44,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 
 #define PAD_DS_TUNE_DLY1	  (0x1f << 2)   /* RW */
 #define PAD_DS_TUNE_DLY2	  (0x1f << 7)   /* RW */
-@@ -294,6 +304,7 @@ struct msdc_save_para {
+@@ -296,6 +306,7 @@ struct msdc_save_para {
 	u32 pad_tune;
 	u32 patch_bit0;
 	u32 patch_bit1;
@ -52,7 +52,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	u32 pad_ds_tune;
 	u32 pad_cmd_tune;
 	u32 emmc50_cfg0;
-@@ -303,6 +314,8 @@ struct mtk_mmc_compatible {
+@@ -305,6 +316,8 @@ struct mtk_mmc_compatible {
 	u8 clk_div_bits;
 	bool hs400_tune; /* only used for MT8173 */
 	u32 pad_tune_reg;
@ -61,7 +61,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 struct msdc_tune_para {
-@@ -365,24 +378,32 @@ static const struct mtk_mmc_compatible m
+@@ -367,24 +380,32 @@ static const struct mtk_mmc_compatible m
 	.clk_div_bits = 8,
 	.hs400_tune = false,
 	.pad_tune_reg = MSDC_PAD_TUNE,
@ -94,7 +94,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct of_device_id msdc_of_ids[] = {
-@@ -1252,8 +1273,29 @@ static void msdc_init_hw(struct msdc_hos
+@@ -1254,8 +1275,29 @@ static void msdc_init_hw(struct msdc_hos
 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
@ -125,7 +125,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 
 	/* Configure to enable SDIO mode.
 	 * it's must otherwise sdio cmd5 failed
-@@ -1268,6 +1310,8 @@ static void msdc_init_hw(struct msdc_hos
+@@ -1270,6 +1312,8 @@ static void msdc_init_hw(struct msdc_hos
 
 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
 	host->def_tune_para.pad_tune = readl(host->base + tune_reg);
@ -134,7 +134,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	dev_dbg(host->dev, "init hardware done!");
 }
 
-@@ -1480,7 +1524,7 @@ skip_fall:
+@@ -1482,7 +1526,7 @@ skip_fall:
 			      final_fall_delay.final_phase);
 		final_delay = final_fall_delay.final_phase;
 	}
@ -143,7 +143,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 		goto skip_internal;
 
 	for (i = 0; i < PAD_DELAY_MAX; i++) {
-@@ -1638,6 +1682,8 @@ static int msdc_prepare_hs400_tuning(str
+@@ -1641,6 +1685,8 @@ static int msdc_prepare_hs400_tuning(str
 	host->hs400_mode = true;
 
 	writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
@ -152,7 +152,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	return 0;
 }
 
-@@ -1876,6 +1922,7 @@ static void msdc_save_reg(struct msdc_ho
+@@ -1879,6 +1925,7 @@ static void msdc_save_reg(struct msdc_ho
 	host->save_para.pad_tune = readl(host->base + tune_reg);
 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
@ -160,7 +160,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
-@@ -1891,6 +1938,7 @@ static void msdc_restore_reg(struct msdc
+@@ -1894,6 +1941,7 @@ static void msdc_restore_reg(struct msdc
 	writel(host->save_para.pad_tune, host->base + tune_reg);
 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
--- a/target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch
+++ b/target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch
@ -16,7 +16,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

 --- a/drivers/mmc/host/mtk-sd.c
 +++ b/drivers/mmc/host/mtk-sd.c
-@@ -316,6 +316,7 @@ struct mtk_mmc_compatible {
+@@ -318,6 +318,7 @@ struct mtk_mmc_compatible {
 	u32 pad_tune_reg;
 	bool async_fifo;
 	bool data_tune;
@ -24,7 +24,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 struct msdc_tune_para {
-@@ -380,6 +381,7 @@ static const struct mtk_mmc_compatible m
+@@ -382,6 +383,7 @@ static const struct mtk_mmc_compatible m
 	.pad_tune_reg = MSDC_PAD_TUNE,
 	.async_fifo = false,
 	.data_tune = false,
@ -32,7 +32,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct mtk_mmc_compatible mt8173_compat = {
-@@ -388,6 +390,7 @@ static const struct mtk_mmc_compatible m
+@@ -390,6 +392,7 @@ static const struct mtk_mmc_compatible m
 	.pad_tune_reg = MSDC_PAD_TUNE,
 	.async_fifo = false,
 	.data_tune = false,
@ -40,7 +40,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct mtk_mmc_compatible mt2701_compat = {
-@@ -396,6 +399,7 @@ static const struct mtk_mmc_compatible m
+@@ -398,6 +401,7 @@ static const struct mtk_mmc_compatible m
 	.pad_tune_reg = MSDC_PAD_TUNE0,
 	.async_fifo = true,
 	.data_tune = true,
@ -48,7 +48,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct mtk_mmc_compatible mt2712_compat = {
-@@ -404,6 +408,7 @@ static const struct mtk_mmc_compatible m
+@@ -406,6 +410,7 @@ static const struct mtk_mmc_compatible m
 	.pad_tune_reg = MSDC_PAD_TUNE0,
 	.async_fifo = true,
 	.data_tune = true,
@ -56,7 +56,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct of_device_id msdc_of_ids[] = {
-@@ -1275,6 +1280,8 @@ static void msdc_init_hw(struct msdc_hos
+@@ -1277,6 +1282,8 @@ static void msdc_init_hw(struct msdc_hos
 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
--- a/target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch
+++ b/target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch
@ -42,16 +42,16 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 /* MSDC_DMA_CTRL mask */
 #define MSDC_DMA_CTRL_START     (0x1 << 0)	/* W */
 #define MSDC_DMA_CTRL_STOP      (0x1 << 1)	/* W */
-@@ -217,6 +222,8 @@
- #define MSDC_PATCH_BIT_SPCPUSH    (0x1 << 29)	/* RW */
- #define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)	/* RW */
+@@ -219,6 +224,8 @@
+ 
+ #define MSDC_PATCH_BIT1_CMDTA     (0x7 << 3)    /* RW */
 
 +#define MSDC_PATCH_BIT1_STOP_DLY  (0xf << 8)    /* RW */
 +
 #define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
 #define MSDC_PB2_RESPWAIT         (0x3 << 2)    /* RW */
-@@ -242,6 +249,9 @@
+@@ -244,6 +251,9 @@
 #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
 #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
 
@ -61,7 +61,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 #define REQ_CMD_EIO  (0x1 << 0)
 #define REQ_CMD_TMO  (0x1 << 1)
 #define REQ_DAT_ERR  (0x1 << 2)
-@@ -308,6 +318,7 @@ struct msdc_save_para {
+@@ -310,6 +320,7 @@ struct msdc_save_para {
 	u32 pad_ds_tune;
 	u32 pad_cmd_tune;
 	u32 emmc50_cfg0;
@ -69,7 +69,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 struct mtk_mmc_compatible {
-@@ -317,6 +328,8 @@ struct mtk_mmc_compatible {
+@@ -319,6 +330,8 @@ struct mtk_mmc_compatible {
 	bool async_fifo;
 	bool data_tune;
 	bool busy_check;
@ -78,7 +78,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 struct msdc_tune_para {
-@@ -382,6 +395,8 @@ static const struct mtk_mmc_compatible m
+@@ -384,6 +397,8 @@ static const struct mtk_mmc_compatible m
 	.async_fifo = false,
 	.data_tune = false,
 	.busy_check = false,
@ -87,7 +87,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct mtk_mmc_compatible mt8173_compat = {
-@@ -391,6 +406,8 @@ static const struct mtk_mmc_compatible m
+@@ -393,6 +408,8 @@ static const struct mtk_mmc_compatible m
 	.async_fifo = false,
 	.data_tune = false,
 	.busy_check = false,
@ -96,7 +96,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct mtk_mmc_compatible mt2701_compat = {
-@@ -400,6 +417,8 @@ static const struct mtk_mmc_compatible m
+@@ -402,6 +419,8 @@ static const struct mtk_mmc_compatible m
 	.async_fifo = true,
 	.data_tune = true,
 	.busy_check = false,
@ -105,7 +105,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct mtk_mmc_compatible mt2712_compat = {
-@@ -409,6 +428,8 @@ static const struct mtk_mmc_compatible m
+@@ -411,6 +430,8 @@ static const struct mtk_mmc_compatible m
 	.async_fifo = true,
 	.data_tune = true,
 	.busy_check = true,
@ -114,7 +114,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 };
 
 static const struct of_device_id msdc_of_ids[] = {
-@@ -1280,15 +1301,31 @@ static void msdc_init_hw(struct msdc_hos
+@@ -1282,15 +1303,31 @@ static void msdc_init_hw(struct msdc_hos
 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
@ -150,7 +150,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 		/* use async fifo, then no need tune internal delay */
 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
 			     MSDC_PATCH_BIT2_CFGRESP);
-@@ -1933,6 +1970,7 @@ static void msdc_save_reg(struct msdc_ho
+@@ -1936,6 +1973,7 @@ static void msdc_save_reg(struct msdc_ho
 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
@ -158,7 +158,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 }
 
 static void msdc_restore_reg(struct msdc_host *host)
-@@ -1949,6 +1987,7 @@ static void msdc_restore_reg(struct msdc
+@@ -1952,6 +1990,7 @@ static void msdc_restore_reg(struct msdc
 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
--- a/target/linux/mediatek/patches-4.14/0157-mmc-mediatek-add-support-of-source_cg-clock.patch
+++ b/target/linux/mediatek/patches-4.14/0157-mmc-mediatek-add-support-of-source_cg-clock.patch
@ -15,7 +15,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

 --- a/drivers/mmc/host/mtk-sd.c
 +++ b/drivers/mmc/host/mtk-sd.c
-@@ -372,6 +372,7 @@ struct msdc_host {
+@@ -374,6 +374,7 @@ struct msdc_host {
 
 	struct clk *src_clk;	/* msdc source clock */
 	struct clk *h_clk;      /* msdc h_clk */
@ -23,7 +23,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	u32 mclk;		/* mmc subsystem clock frequency */
 	u32 src_clk_freq;	/* source clock frequency */
 	u32 sclk;		/* SD/MS bus clock frequency */
-@@ -616,6 +617,7 @@ static void msdc_set_timeout(struct msdc
+@@ -618,6 +619,7 @@ static void msdc_set_timeout(struct msdc
 
 static void msdc_gate_clock(struct msdc_host *host)
 {
@ -31,7 +31,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	clk_disable_unprepare(host->src_clk);
 	clk_disable_unprepare(host->h_clk);
 }
-@@ -624,6 +626,7 @@ static void msdc_ungate_clock(struct msd
+@@ -626,6 +628,7 @@ static void msdc_ungate_clock(struct msd
 {
 	clk_prepare_enable(host->h_clk);
 	clk_prepare_enable(host->src_clk);
@ -39,7 +39,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
 		cpu_relax();
 }
-@@ -692,6 +695,15 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -694,6 +697,15 @@ static void msdc_set_mclk(struct msdc_ho
 			sclk = (host->src_clk_freq >> 2) / div;
 		}
 	}
@ -55,7 +55,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	if (host->dev_comp->clk_div_bits == 8)
 		sdr_set_field(host->base + MSDC_CFG,
 			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
-@@ -700,10 +712,14 @@ static void msdc_set_mclk(struct msdc_ho
+@@ -702,10 +714,14 @@ static void msdc_set_mclk(struct msdc_ho
 		sdr_set_field(host->base + MSDC_CFG,
 			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
 			      (mode << 12) | div);
@ -71,7 +71,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	host->sclk = sclk;
 	host->mclk = hz;
 	host->timing = timing;
-@@ -1822,6 +1838,11 @@ static int msdc_drv_probe(struct platfor
+@@ -1825,6 +1841,11 @@ static int msdc_drv_probe(struct platfor
 		goto host_free;
 	}
 
--- a/target/linux/mediatek/patches-4.14/0158-mmc-mediatek-add-latch-ck-support.patch
+++ b/target/linux/mediatek/patches-4.14/0158-mmc-mediatek-add-latch-ck-support.patch
@ -16,7 +16,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

 --- a/drivers/mmc/host/mtk-sd.c
 +++ b/drivers/mmc/host/mtk-sd.c
-@@ -378,6 +378,7 @@ struct msdc_host {
+@@ -380,6 +380,7 @@ struct msdc_host {
 	u32 sclk;		/* SD/MS bus clock frequency */
 	unsigned char timing;
 	bool vqmmc_enabled;
@ -24,7 +24,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	u32 hs400_ds_delay;
 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
-@@ -1661,6 +1662,8 @@ static int msdc_tune_data(struct mmc_hos
+@@ -1664,6 +1665,8 @@ static int msdc_tune_data(struct mmc_hos
 	u32 tune_reg = host->dev_comp->pad_tune_reg;
 	int i, ret;
 
@ -33,7 +33,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
-@@ -1773,6 +1776,9 @@ static const struct mmc_host_ops mt_msdc
+@@ -1776,6 +1779,9 @@ static const struct mmc_host_ops mt_msdc
 static void msdc_of_property_parse(struct platform_device *pdev,
 				   struct msdc_host *host)
 {
--- a/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch
+++ b/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch
@ -23,7 +23,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 #define SDC_FIFO_CFG     0x228
 
 /*--------------------------------------------------------------------------*/
-@@ -249,6 +250,8 @@
+@@ -251,6 +252,8 @@
 #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
 #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
 
@ -32,7 +32,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 #define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
 #define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
 
-@@ -318,6 +321,7 @@ struct msdc_save_para {
+@@ -320,6 +323,7 @@ struct msdc_save_para {
 	u32 pad_ds_tune;
 	u32 pad_cmd_tune;
 	u32 emmc50_cfg0;
@ -40,7 +40,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	u32 sdc_fifo_cfg;
 };
 
-@@ -1747,6 +1751,9 @@ static int msdc_prepare_hs400_tuning(str
+@@ -1750,6 +1754,9 @@ static int msdc_prepare_hs400_tuning(str
 	writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
 	/* hs400 mode must set it to 0 */
 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
@ -50,7 +50,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	return 0;
 }
 
-@@ -1997,6 +2004,7 @@ static void msdc_save_reg(struct msdc_ho
+@@ -2000,6 +2007,7 @@ static void msdc_save_reg(struct msdc_ho
 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
@ -58,7 +58,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
 	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
 }
 
-@@ -2014,6 +2022,7 @@ static void msdc_restore_reg(struct msdc
+@@ -2017,6 +2025,7 @@ static void msdc_restore_reg(struct msdc
 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
--- a/target/linux/mediatek/patches-4.14/0160-mmc-mediatek-perfer-to-use-rise-edge-latching-for-cm.patch
+++ b/target/linux/mediatek/patches-4.14/0160-mmc-mediatek-perfer-to-use-rise-edge-latching-for-cm.patch
@ -16,7 +16,7 @@ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

 --- a/drivers/mmc/host/mtk-sd.c
 +++ b/drivers/mmc/host/mtk-sd.c
-@@ -1550,7 +1550,8 @@ static int msdc_tune_response(struct mmc
+@@ -1552,7 +1552,8 @@ static int msdc_tune_response(struct mmc
 	}
 	final_rise_delay = get_best_delay(host, rise_delay);
 	/* if rising edge has enough margin, then do not scan falling edge */
--- a/target/linux/mediatek/patches-4.14/0199-thermal-mtk-Cleanup-unused-defines.patch
+++ b/target/linux/mediatek/patches-4.14/0199-thermal-mtk-Cleanup-unused-defines.patch
@ -40,7 +40,7 @@ Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
 struct mtk_thermal;
 
 struct thermal_bank_cfg {
-@@ -765,7 +758,7 @@ static struct platform_driver mtk_therma
+@@ -767,7 +760,7 @@ static struct platform_driver mtk_therma
 	.probe = mtk_thermal_probe,
 	.remove = mtk_thermal_remove,
 	.driver = {
--- a/target/linux/mediatek/patches-4.14/0200-thermal-mediatek-add-support-for-MT7622-SoC.patch
+++ b/target/linux/mediatek/patches-4.14/0200-thermal-mediatek-add-support-for-MT7622-SoC.patch
@ -68,7 +68,7 @@ Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
 /**
  * raw_to_mcelsius - convert a raw ADC value to mcelsius
  * @mt:		The thermal controller
-@@ -631,6 +662,10 @@ static const struct of_device_id mtk_the
+@@ -633,6 +664,10 @@ static const struct of_device_id mtk_the
 	{
 		.compatible = "mediatek,mt2712-thermal",
 		.data = (void *)&mt2712_thermal_data,
--- a/target/linux/mediatek/patches-4.14/0203-mmc-mediatek-add-support-for-MT7622-SoC.patch
+++ b/target/linux/mediatek/patches-4.14/0203-mmc-mediatek-add-support-for-MT7622-SoC.patch
@ -16,7 +16,7 @@ Tested-by: Jumin Li <jumin.li@mediatek.com>

 --- a/drivers/mmc/host/mtk-sd.c
 +++ b/drivers/mmc/host/mtk-sd.c
-@@ -438,11 +438,23 @@ static const struct mtk_mmc_compatible m
+@@ -440,11 +440,23 @@ static const struct mtk_mmc_compatible m
 	.enhance_rx = true,
 };
 
--- a/target/linux/mediatek/patches-4.14/0227-arm-dts-Add-Unielec-U7623-DTS.patch
+++ b/target/linux/mediatek/patches-4.14/0227-arm-dts-Add-Unielec-U7623-DTS.patch
@ -5,24 +5,24 @@ Subject: [PATCH] arm: dts: Add Unielec U7623 DTS

 ---
 arch/arm/boot/dts/Makefile                         |   1 +
- .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts     |  18 +
+ .../dts/mt7623a-unielec-u7623-02-emmc-512m.dts     |  18 +
 .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi    | 366 +++++++++++++++++++++
 3 files changed, 385 insertions(+)
- create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
+ create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi

 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
-@@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ 	mt6580-evbp1.dtb \
 	mt6589-aquaris5.dtb \
 	mt6592-evb.dtb \
- 	mt7623a-rfb-emmc.dtb \
-+	mt7623a-unielec-u7623-02-emmc-512M.dtb \
+	mt7623a-unielec-u7623-02-emmc-512m.dtb \
 	mt7623n-rfb-nand.dtb \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt8127-moose.dtb \
 --- /dev/null
-+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
@@ -0,0 +1,18 @@
 +/*
 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
--- a/target/linux/mediatek/patches-4.19/0002-eth-fix-dsa-support.patch
+++ b/target/linux/mediatek/patches-4.19/0002-eth-fix-dsa-support.patch
@ -0,0 +1,34 @@
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -999,11 +999,6 @@ static int mtk_poll_rx(struct napi_struc
+ 		if (!(trxd.rxd2 & RX_DMA_DONE))
+ 			break;
+ 
+-		/* find out which mac the packet come from. values start at 1 */
+-#if defined(CONFIG_NET_DSA)
+-		mac = (trxd.rxd4 >> 22) & 0x1;
+-		mac = (mac + 1) % 2;
+-#else
+ 		mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
+ 			RX_DMA_FPORT_MASK;
+ 		/* From QDMA(5). This is a external interface case of HWNAT.
+@@ -1017,7 +1012,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			mac = 0;
+ 		else
+ 			mac--;
+-#endif
+		
+ 		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
+ 			     !eth->netdev[mac]))
+ 			goto release_desc;
+@@ -2030,10 +2025,6 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	/* Disable RX VLan Offloading */
+ 	mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
+ 
+-#if defined(CONFIG_NET_DSA)
+-	mtk_w32(eth, 0x81000001, MTK_CDMP_IG_CTRL);
+-#endif
+-
+ 	mtk_w32(eth, 0x8f0f8f0f, MTK_PDMA_DELAY_INT);
+ 	mtk_w32(eth, 0x8f0f8f0f, MTK_QDMA_DELAY_INT);
+ 
--- a/target/linux/mediatek/patches-4.19/0227-arm-dts-Add-Unielec-U7623-DTS.patch
+++ b/target/linux/mediatek/patches-4.19/0227-arm-dts-Add-Unielec-U7623-DTS.patch
@ -5,10 +5,10 @@ Subject: [PATCH] arm: dts: Add Unielec U7623 DTS

 ---
 arch/arm/boot/dts/Makefile                         |   1 +
- .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts     |  18 +
+ .../dts/mt7623a-unielec-u7623-02-emmc-512m.dts     |  18 +
 .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi    | 366 +++++++++++++++++++++
 3 files changed, 385 insertions(+)
- create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
+ create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi

 --- a/arch/arm/boot/dts/Makefile
@ -17,12 +17,12 @@ Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
 	mt7623a-rfb-nand.dtb \
 	mt7623n-rfb-emmc.dtb \
 	mt7623n-bananapi-bpi-r2.dtb \
-+	mt7623a-unielec-u7623-02-emmc-512M.dtb \
+	mt7623a-unielec-u7623-02-emmc-512m.dtb \
 	mt8127-moose.dtb \
 	mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
 --- /dev/null
-+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
@@ -0,0 +1,18 @@
 +/*
 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
--- a/target/linux/mediatek/patches-4.19/0228-arm-dts-bpir2-fix-console.patch
+++ b/target/linux/mediatek/patches-4.19/0228-arm-dts-bpir2-fix-console.patch
@ -0,0 +1,10 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -19,6 +19,7 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial2:115200n8";
+		bootargs = "console=ttyS2,115200n8";
+ 	};
+ 
+ 	cpus {